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authorRichard J. Knight <rjknight@us.ibm.com>2013-07-24 10:50:00 -0500
committerA. Patrick Williams III <iawillia@us.ibm.com>2013-09-13 10:00:51 -0500
commitb082024bbc723c6c9a3a15c03011302ffef4efdf (patch)
treef540671ba70bcb6e95567579aec4713861998d8a
parent7747d54277d67621aab5ae715c3c4db372aa8c2b (diff)
downloadtalos-hostboot-b082024bbc723c6c9a3a15c03011302ffef4efdf.tar.gz
talos-hostboot-b082024bbc723c6c9a3a15c03011302ffef4efdf.zip
INITPROC hwp updates (hostboot integration)
CQ:SW205470 Change-Id: I7adc6b2efefe09e559efedf791538903c61f4e50 Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6148 Tested-by: Jenkins Server Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile42
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile65
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile36
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C63
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H24
5 files changed, 187 insertions, 43 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile
index 9a42c8c36..2f4487273 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase1.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.pe.phase1.scom.initfile,v 1.3 2013/03/25 21:39:24 jmcgill Exp $
+#-- $Id: p8.pe.phase1.scom.initfile,v 1.4 2013/05/15 04:24:37 jmcgill Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2011
@@ -33,10 +33,28 @@ define lane32 = (ATTR_CHIP_EC_FEATURE_32_PCIE_LANES != 0);
#-- IOP 0
#--
+#-- IOP PLL FIR Action0 Register
+scom 0x09011406 {
+ bits, scom_data;
+ 0:63, 0x0000000000000000;
+}
+
+#-- IOP PLL FIR Action1 Register
+scom 0x09011407 {
+ bits, scom_data;
+ 0:63, 0xFF00000000000000;
+}
+
+#-- IOP PLL FIR Mask Register
+scom 0x09011403 {
+ bits, scom_data;
+ 0:63, 0xFF80000000000000;
+}
+
#-- G3 PLL Control Register 0
scom 0x800008010901143F {
- bits, scom_data;
- 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[0];
+ bits, scom_data;
+ 51:63, ATTR_PROC_PCIE_IOP_G3_PLL_CONTROL0[0];
}
#-- G2 PLL Control Register 0
@@ -758,6 +776,24 @@ scom 0x800008420901143F {
#-- IOP 1
#--
+#-- IOP PLL FIR Action0 Register
+scom 0x09011846 {
+ bits, scom_data;
+ 0:63, 0x0000000000000000;
+}
+
+#-- IOP PLL FIR Action1 Register
+scom 0x09011847 {
+ bits, scom_data;
+ 0:63, 0xFF00000000000000;
+}
+
+#-- IOP PLL FIR Mask Register
+scom 0x09011843 {
+ bits, scom_data;
+ 0:63, 0xFF80000000000000;
+}
+
#-- G3 PLL Control Register 0
scom 0x800008010901187F {
bits, scom_data;
diff --git a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile
index a62edd656..02021cf98 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.tpbridge.scom.initfile,v 1.1 2013/03/25 03:07:40 jmcgill Exp $
+#-- $Id: p8.tpbridge.scom.initfile,v 1.5 2013/07/17 16:48:42 jmcgill Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2011
@@ -41,6 +41,26 @@ scom 0x020109CB {
23:27, 0b00011; # data hang divider = 3
}
+# ICP FIR Register initializations
+
+# EN.TPC.INTP.SYNC_FIR_ACTION0_REG
+scom 0x020109C6 {
+ bits, scom_data;
+ 0:63, 0x0000000000000000;
+}
+
+# EN.TPC.INTP.SYNC_FIR_ACTION1_REG
+scom 0x020109C7 {
+ bits, scom_data;
+ 0:63, 0xF7E00DFFB0000000;
+}
+
+# EN.TPC.INTP.SYNC_FIR_MASK_REG
+scom 0x020109C3 {
+ bits, scom_data;
+ 0:63, 0x081FF2004C000000;
+}
+
#--------------------------------------------------------------------------------
#-- HCA SCOM initializations
@@ -48,6 +68,47 @@ scom 0x020109CB {
# HCA Mode Register
scom 0x0201094F {
+ bits, scom_data, expr;
+ 16:20, 0b00011, (ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL == 0); # oper/data hang divider = 3 (HW242836)
+ 16:20, 0b00001, (ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL != 0); # oper hang divider = 1 (HW242836)
+ 30:34, 0b00011, (ATTR_CHIP_EC_FEATURE_HCA_SPLIT_HANG_CONTROL != 0); # data hang divider = 3 (HW242836)
+}
+
+# HCA FIR Register initializations
+
+# EH.FIR ACTION0
+scom 0x02010986 {
bits, scom_data;
- 16:20, 0b00011; # oper/data hang divider = 3 (HW242836)
+ 0:63, 0x0000000000000000;
}
+
+# EH FIR ACTION1
+scom 0x02010987 {
+ bits, scom_data;
+ 0:63, 0xFFFFFFFFF0000000;
+}
+
+# EH FIR MASK
+scom 0x02010983 {
+ bits, scom_data;
+ 0:63, 0x0000000000000000;
+}
+
+# EN FIR ACTION0
+scom 0x02010946 {
+ bits, scom_data;
+ 0:63, 0x0000000000000000;
+}
+
+# EN FIR ACTION1
+scom 0x02010947 {
+ bits, scom_data;
+ 0:63, 0xFFC0000000000000;
+}
+
+# EN FIR MASK
+scom 0x02010943 {
+ bits, scom_data;
+ 0:63, 0x0000000000000000;
+}
+
diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
index 18c8cc48d..54a9efcc4 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.xbus.custom.scom.initfile,v 1.3 2013/03/15 21:18:37 thomsen Exp $
+#-- $Id: p8.xbus.custom.scom.initfile,v 1.4 2013/05/15 04:23:52 jmcgill Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date: | Comment:
@@ -76,40 +76,6 @@ define def_all_lanes=11111;
# tx_lane_pdwn, 0b0;
#}
-#--**************************************************************************************************************
-#----------------------------------------------------------------------------------------------------------------
-# ________________ ____ ________ ____ _ __ __ ___ __
-# / ____/ ____/ __ \ / __ )__ __/ __/ __/__ _____ / __ \____ ______(_) /___ __ / |/ /___ ______/ /__
-# / / __/ / / /_/ / / __ / / / / /_/ /_/ _ \/ ___/ / /_/ / __ `/ ___/ / __/ / / / / /|_/ / __ `/ ___/ //_/
-# / /_/ / /___/ _, _/ / /_/ / /_/ / __/ __/ __/ / / ____/ /_/ / / / / /_/ /_/ / / / / / /_/ (__ ) ,<
-# \____/\____/_/ |_| /_____/\__,_/_/ /_/ \___/_/ /_/ \__,_/_/ /_/\__/\__, / /_/ /_/\__,_/____/_/|_|
-# /____/
-#----------------------------------------------------------------------------------------------------------------
-#--**************************************************************************************************************
-# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
-# 0x800???0002011E3F
-# This is applied to all configured clkgrp's via chiplet targetting
-scom 0x800.0b(rx_fir1_mask_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
-bits, scom_data;
-rx_pg_fir_err_mask_gcr_buff, 0b1;
-}
-scom 0x800.0b(tx_fir_mask_pg)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(xbus0_gcr_addr) {
-bits, scom_data;
-tx_pg_fir_err_mask_gcr_buff, 0b1;
-}
-scom 0x800.0b(rx_fir_mask_pb)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
-bits, scom_data;
-rx_pb_fir_err_mask_gcr_buff0, 0b1;
-rx_pb_fir_err_mask_gcr_buff1, 0b1;
-rx_pb_fir_err_mask_gcr_buff2, 0b1;
-}
-
-# Mask off all rx and tx parity errors in the fir register
-scom 0x04011003 {
-scom_data;
-0xC000000000000000;
-}
-
############################################################################################
# END OF FILE
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
index 085e110a6..8a9df2e70 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_pcie_scominit.C,v 1.6 2013/04/08 14:57:39 jmcgill Exp $
+// $Id: proc_pcie_scominit.C,v 1.7 2013/05/15 04:18:56 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.C,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2012
@@ -379,7 +379,7 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete(
data);
if (!rc.ok())
{
- FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE%d_ETU_RESET_0x%016llX)",
+ FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE%d_ETU_RESET_0x%08X)",
i, PROC_PCIE_SCOMINIT_ETU_RESET[i]);
break;
}
@@ -389,6 +389,65 @@ fapi::ReturnCode proc_pcie_scominit_iop_complete(
break;
}
+ // configure IOP FIR
+ for (size_t i = 0; i < PROC_PCIE_SCOMINIT_NUM_IOP; i++)
+ {
+ rc_ecmd |= data.flushTo0();
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_pcie_scominit_iop_complete: Error 0x%x setting up PLL FIR register clear data buffer",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ // clear FIR
+ rc = fapiPutScom(i_target,
+ PROC_PCIE_SCOMINIT_PLL_FIR[i],
+ data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE_IOP%d_PLL_FIR_0x%08X)",
+ i, PROC_PCIE_SCOMINIT_PLL_FIR[i]);
+ break;
+ }
+
+ // clear FIR WOF
+ rc = fapiPutScom(i_target,
+ PROC_PCIE_SCOMINIT_PLL_FIR_WOF[i],
+ data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE_IOP%d_PLL_FIR_WOF_0x%08X)",
+ i, PROC_PCIE_SCOMINIT_PLL_FIR_WOF[i]);
+ break;
+ }
+
+ rc_ecmd |= data.setDoubleWord(0, PCIE_PLL_FIR_MASK_VAL);
+ if (rc_ecmd)
+ {
+ FAPI_ERR("proc_pcie_scominit_iop_complete: Error 0x%x setting up PLL FIR mask register data buffer",
+ rc_ecmd);
+ rc.setEcmdError(rc_ecmd);
+ break;
+ }
+
+ // unmask
+ rc = fapiPutScom(i_target,
+ PROC_PCIE_SCOMINIT_PLL_FIR_MASK[i],
+ data);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_pcie_scominit_iop_complete: Error from fapiPutScom (PCIE_IOP%d_PLL_FIR_MASK_0x%08X)",
+ i, PROC_PCIE_SCOMINIT_PLL_FIR_MASK[i]);
+ break;
+ }
+ }
+ if (!rc.ok())
+ {
+ break;
+ }
+
} while(0);
// mark function exit
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
index a57646d40..1a0b5920d 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_scominit/proc_pcie_scominit.H
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_pcie_scominit.H,v 1.3 2013/04/08 14:57:41 jmcgill Exp $
+// $Id: proc_pcie_scominit.H,v 1.4 2013/05/15 04:18:58 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_scominit.H,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2012
@@ -120,6 +120,28 @@ const uint64_t PROC_PCIE_SCOMINIT_PLL_GLOBAL_CONTROL2[PROC_PCIE_SCOMINIT_NUM_IOP
};
const uint32_t PLL_GLOBAL_CONTROL2_PROG_COMPLETE_BIT = 50;
+// PCIe PLL FIR register field/bit definitions
+const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+ PCIE_IOP0_PLL_FIR_0x09011400,
+ PCIE_IOP1_PLL_FIR_0x09011840
+};
+
+const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_WOF[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+ PCIE_IOP0_PLL_FIR_WOF_0x09011408,
+ PCIE_IOP1_PLL_FIR_WOF_0x09011848
+};
+
+const uint32_t PROC_PCIE_SCOMINIT_PLL_FIR_MASK[PROC_PCIE_SCOMINIT_NUM_IOP] =
+{
+ PCIE_IOP0_PLL_FIR_MASK_0x09011403,
+ PCIE_IOP1_PLL_FIR_MASK_0x09011843
+};
+
+const uint64_t PCIE_PLL_FIR_MASK_VAL = 0x0080000000000000ULL;
+
+
//------------------------------------------------------------------------------
// Structure definitions
//------------------------------------------------------------------------------
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