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author | Thi Tran <thi@us.ibm.com> | 2013-08-29 21:42:28 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-09-11 14:53:55 -0500 |
commit | acf1842a1be57bcc8b88175d15f0082e0f97dbd8 (patch) | |
tree | 025345324a24aa8469212bc2db339df2ede5e050 /src/usr/hwpf/hwp/nest_chiplets | |
parent | 86d20c2609a8f0fc8c082c68e0d76d6b05ffba1b (diff) | |
download | talos-hostboot-acf1842a1be57bcc8b88175d15f0082e0f97dbd8.tar.gz talos-hostboot-acf1842a1be57bcc8b88175d15f0082e0f97dbd8.zip |
Hostboot - Updated HWPs from defect SW220729 (week 8/20)
Change-Id: Ic1c5956385b7fe0eae4ce0f5a79d17f6ce93592e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5988
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/nest_chiplets')
-rw-r--r-- | src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C index 3f5cbbdb3..a5944b2cd 100644 --- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C +++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.2 2013/05/06 20:58:08 jmcgill Exp $ +// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.3 2013/08/20 02:05:06 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $ //------------------------------------------------------------------------------ // *| @@ -50,7 +50,10 @@ using namespace fapi; // Constant definitions //------------------------------------------------------------------------------ +// lock polling constants const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS = 50; +const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW = 2000000; +const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM = 1; // OPCG/Clock Region Register values const uint64_t OPCG_REG0_FOR_SETPULSE = 0x818C000000000000ull; @@ -432,6 +435,13 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll( FAPI_ERR("Error reading PLL lock register"); break; } + rc = fapiDelay(PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW, + PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM); + if (rc) + { + FAPI_ERR("Error from fapiDelay"); + break; + } } while (!timeout && !data.isBitSet(PLL_LOCK_REG_LOCK_START_BIT, (PLL_LOCK_REG_LOCK_END_BIT- |