Hostboot - Updated HWPs from defect SW220729 (week 8/20)

Change-Id: Ic1c5956385b7fe0eae4ce0f5a79d17f6ce93592e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5988
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

10 files changed, 175 insertions, 70 deletions

diff --git a/src/usr/hwpf/hwp/centaur_ec_attributes.xml b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
index fb99b1eb2..fbf29eb8c 100644
--- a/src/usr/hwpf/hwp/centaur_ec_attributes.xml
+++ b/src/usr/hwpf/hwp/centaur_ec_attributes.xml
@@ -22,7 +22,24 @@
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
 <!-- ********************************************************************* -->
-  <!-- $Id: centaur_ec_attributes.xml,v 1.5 2013/06/18 22:04:09 mjjones Exp $ -->
+  <!-- $Id: centaur_ec_attributes.xml,v 1.7 2013/08/08 14:30:33 yctschan Exp $ -->
+  <attribute>
+    <id>ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>
+        Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  For HW259719. If true, Trace LCL_CLK_GATE_CTRL will be enabled.
+    </description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+  </attribute>
+
   <attribute>
     <id>ATTR_CENTAUR_EC_WRITE_FIR_MASK_FEATURE</id>
     <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
@@ -96,4 +113,18 @@ Controls the ddr_phy_reset procedure.  When set to TRUE, the procedure will cont
     </chipEcFeature>
   </attribute>
 
+<attribute>
+    <id>ATTR_MSS_DISABLE1_REG_FIXED</id>
+    <targetType>TARGET_TYPE_MEMBUF_CHIP</targetType>
+    <description>Set by the platform depending on DD2.x or newer (TRUE), otherwise FALSE.  If false, then draminit_training will also set the wrclk registers to disable appropriate dqs based on the bad bit map attribute and the swizzle(board dependent).  If true, draminit_training will just do the default disable0 and disable1 registers.</description>
+    <chipEcFeature>
+      <chip>
+        <name>ENUM_ATTR_NAME_CENTAUR</name>
+        <ec>
+          <value>0x20</value>
+          <test>GREATER_THAN_OR_EQUAL</test>
+        </ec>
+      </chip>
+    </chipEcFeature>
+</attribute>
 </attributes>
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 9985b7014..8b8d12166 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,10 @@
 
-#-- $Id: mba_def.initfile,v 1.46 2013/07/17 18:23:53 yctschan Exp $
+#-- $Id: mba_def.initfile,v 1.47 2013/08/15 19:20:23 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.47|tschang | 8/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates
 #--     1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations
 #--     1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings
 #--                            setting RD ODT according to Menlo's equation
@@ -268,7 +269,7 @@ define def_has_spare    =   (SYS.ATTR_IS_SIMULATION==0) ;
 #define  def_ATTR_EFF_DRAM_2N_MODE = (0);
 #define def_ATTR_EFF_IBM_TYPE           = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
 #define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.ATTR_IS_SIMULATION==0) ;   # will evaluate to false
-define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+#define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 
 define CENTAUR = TGT1;
 
@@ -1703,6 +1704,19 @@ scom 0x03010416     {
 
 # ATTR_EFF_DIMM_TYPE
 # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
+
+###################################
+# TRACE_TRCTRL_CONFIG MBA01 Trace Control Configuration Register
+#
+# HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on
+# DD2 fixed ONLY
+###################################
+
+scom 0x03010882      {
+    bits    ,   scom_data    ,       ATTR_FUNCTIONAL,   expr;
+   12:13    ,   0b11         ,          1            ,    (CENTAUR.ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl
+}
+
 ###################################
 # Turn on DDR PHY clks
 ###################################
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
index 240245a94..d08dcb611 100644
--- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
@@ -1,8 +1,9 @@
-#-- $Id: mbs_def.initfile,v 1.36 2013/07/08 14:37:16 yctschan Exp $
+#-- $Id: mbs_def.initfile,v 1.37 2013/08/15 19:20:26 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--   1.37  |tschang |08/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates
 #--   1.36  |tschang |07/03/13| L4.ATTR_FUNCTIONAL for cache enable for some bits I missed
 #--   1.35  |tschang |07/02/13| L4.ATTR_FUNCTIONAL for cache enable
 #--   1.34  |tschang |06/11/13| removed mask out bit 8 - internal parity error - HW244827 and HW251643
@@ -84,6 +85,7 @@ define def_equal_test     =  (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT
 define MBA0 = TGT1;
 define MBA1 = TGT2;
 define L4 = TGT3;
+#define CENTAUR = TGT4;	# parent Centaur
 
 # MBA0.ATTR_CHIP_UNIT_POS - that should equal 0
 # MBA1.ATTR_CHIP_UNIT_POS should equal
@@ -96,7 +98,7 @@ define def_has_spare    =   (SYS.ATTR_IS_SIMULATION==0) ;
 #define  def_ATTR_EFF_DRAM_2N_MODE = 0;
 #define def_ATTR_EFF_IBM_TYPE           = (SYS.CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 #define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
-define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
+#define def_ATTR_EFF_DRAM_2N_MODE       = (CENTAUR.ATTR_MSS_FREQ == 1400) ;   # will evaluate to false
 
 define def_mba01_nomem        =  ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0b00000000) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0b00000000));
 define def_mba23_nomem        =  ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0b00000000) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0b00000000));
@@ -415,6 +417,29 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated    = (def_mb
 # }
 
 
+#--******************************************************************************
+# TRACE_TRCTRL_CONFIG MBA01 Trace Control Configuration Register
+#
+# HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on
+# DD2 fixed ONLY
+#--******************************************************************************
+
+# MBI trace
+scom 0x02010C42      {
+    bits    ,   scom_data    ,       ATTR_FUNCTIONAL,   expr;
+   12:13    ,   0b11         ,          1            ,     (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl
+}
+# MBS1 trace
+scom 0x02011882      {
+    bits    ,   scom_data    ,       ATTR_FUNCTIONAL,   expr;
+   12:13    ,   0b11         ,          1            ,     (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl
+}
+# MBS2 trace
+scom 0x020118C2      {
+    bits    ,   scom_data    ,       ATTR_FUNCTIONAL,   expr;
+   12:13    ,   0b11         ,          1            ,     (ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl
+}
+
 # YCT added for Irving
 #--******************************************************************************
 #-- MBI Configuration Register
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
index 3daec80bd..508ce4109 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_cke_map.C,v 1.3 2012/11/16 14:39:15 asaetow Exp $
+// $Id: mss_eff_config_cke_map.C,v 1.4 2013/08/16 13:45:30 kcook Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -42,7 +42,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.4   |          |         |
+//   1.4   | kcook    |16-AUG-12| Added LRDIMM support.
 //   1.3   | asaetow  |14-NOV-12| Added ATTR_EFF_SPCKE_MAP. 
 //   1.2   | asaetow  |13-NOV-12| Added FAPI_ERR for else "Undefined IBM_TYPE". 
 //         |          |         | Removed outter NUM_DROPS_PER_PORT check.
@@ -98,7 +98,7 @@ const uint8_t l_cke_map_u8array[IBM_TYPE_SIZE][DIMM_SIZE][RANK_SIZE] = {
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5A <-- UNDEFINED
    {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_5B
    {{0x80, 0x40, 0x80, 0x40}, {0x08, 0x04, 0x08, 0x04}},  // TYPE_5C
-   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5D <-- NOT YET SUPPORTED for LRDIMM DDR3
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_5D 
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6A <-- UNDEFINED
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6B <-- UNDEFINED
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6C <-- UNDEFINED
@@ -240,8 +240,9 @@ fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba) {
                FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
                FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
             }
-            FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            FAPI_INF("WIP 8Rank LRDIMM IBM_TYPE on %s!", i_target_mba.toEcmdString());
+//            FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
+//            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
          } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6A ) {
             l_ibm_type_index = 18;
             FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
index 4316c4d7c..2e7772ab5 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_rank_group.C,v 1.10 2013/04/17 11:26:02 asaetow Exp $
+// $Id: mss_eff_config_rank_group.C,v 1.11 2013/08/16 13:45:45 kcook Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -46,7 +46,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.11  |          |         |
+//   1.11  | kcook    |16-AUG-13| Added LRDIMM support.
 //   1.10  | asaetow  |17-APR-13| Removed 32G CDIMM 1R dualdrop workaround.
 //         |          |         | NOTE: Needs mss_draminit_training.C v1.57 or newer.
 //   1.9   | asaetow  |01-APR-13| Added 32G CDIMM 1R dualdrop workaround.
@@ -160,23 +160,77 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) {
          //quanternary_rank_group3_u8array[cur_port] = INVALID;
       //} else if (dimm_type_u8 == LRDIMM) {
       if (dimm_type_u8 == LRDIMM) {
-         // HERE: NOT correct, need to account for ATTR_EFF_DIMM_RANKS_CONFIGED for LRDIMMs /w multi master ranks
-         primary_rank_group0_u8array[cur_port] = 0;
-         primary_rank_group1_u8array[cur_port] = 4;
-         primary_rank_group2_u8array[cur_port] = 8;
-         primary_rank_group3_u8array[cur_port] = 12;
-         secondary_rank_group0_u8array[cur_port] = 1;
-         secondary_rank_group1_u8array[cur_port] = 5;
-         secondary_rank_group2_u8array[cur_port] = 9;
-         secondary_rank_group3_u8array[cur_port] = 13;
-         tertiary_rank_group0_u8array[cur_port] = 2;
-         tertiary_rank_group1_u8array[cur_port] = 6;
-         tertiary_rank_group2_u8array[cur_port] = 10;
-         tertiary_rank_group3_u8array[cur_port] = 14;
-         quanternary_rank_group0_u8array[cur_port] = 3;
-         quanternary_rank_group1_u8array[cur_port] = 7;
-         quanternary_rank_group2_u8array[cur_port] = 11;
-         quanternary_rank_group3_u8array[cur_port] = 15;
+         primary_rank_group2_u8array[cur_port] = INVALID;
+         secondary_rank_group2_u8array[cur_port] = INVALID;
+         tertiary_rank_group2_u8array[cur_port] = INVALID;
+         quanternary_rank_group2_u8array[cur_port] = INVALID;
+
+         primary_rank_group3_u8array[cur_port] = INVALID;
+         secondary_rank_group3_u8array[cur_port] = INVALID;
+         tertiary_rank_group3_u8array[cur_port] = INVALID;
+         quanternary_rank_group3_u8array[cur_port] = INVALID;
+
+         // dimm 0 (far socket)
+         switch (num_ranks_per_dimm_u8array[cur_port][0]) {
+           case 4:               // 4 rank lrdimm
+                 primary_rank_group0_u8array[cur_port] = 0;
+                 secondary_rank_group0_u8array[cur_port] = 1;
+                 tertiary_rank_group0_u8array[cur_port] = 2;
+                 quanternary_rank_group0_u8array[cur_port] = 3;
+                 break;
+           case 8:               // 8 rank lrdimm falls through to 2 rank case
+         // Rank Multiplication mode needed, CS2 & CS3 used as address lines into LRBuffer
+         // RM=4 -> only 2 CS valid, each CS controls 4 ranks with CS2 & CS3 as address
+         // CS0 = rank 0, 2, 4, 6;  CS1 = rank 1, 3, 5, 7
+           case 2:               // 2 rank lrdimm
+                 primary_rank_group0_u8array[cur_port] = 0;
+                 secondary_rank_group0_u8array[cur_port] = 1;
+                 tertiary_rank_group0_u8array[cur_port] = INVALID;
+                 quanternary_rank_group0_u8array[cur_port] = INVALID;
+                 break;
+           case 1:               // 1 rank lrdimm
+                 primary_rank_group0_u8array[cur_port] = 0;
+                 secondary_rank_group0_u8array[cur_port] = INVALID;
+                 tertiary_rank_group0_u8array[cur_port] = INVALID;
+                 quanternary_rank_group0_u8array[cur_port] = INVALID;
+                 break;
+           default:              // not 1, 2, 4, or 8 ranks
+                 primary_rank_group0_u8array[cur_port] = INVALID;
+                 secondary_rank_group0_u8array[cur_port] = INVALID;
+                 tertiary_rank_group0_u8array[cur_port] = INVALID;
+                 quanternary_rank_group0_u8array[cur_port] = INVALID;
+         }
+         // dimm 1 (near socket)
+         switch (num_ranks_per_dimm_u8array[cur_port][1]) {
+           case 4:               // 4 rank lrdimm
+                 primary_rank_group1_u8array[cur_port] = 4;
+                 secondary_rank_group1_u8array[cur_port] = 5;
+                 tertiary_rank_group1_u8array[cur_port] = 6;
+                 quanternary_rank_group1_u8array[cur_port] = 7;
+                 break;
+           case 8:               // 8 rank lrdimm falls through to case 2
+         // Rank Multiplication mode needed, CS6 & CS7 used as address lines into LRBuffer
+         // RM=4 -> only 2 CS valid, each CS controls 4 ranks with CS6 & CS7 as address
+         // CS4 = rank 0, 2, 4, 6;  CS5 = rank 1, 3, 5, 7
+           case 2:               // 2 rank lrdimm, RM=0
+                 primary_rank_group1_u8array[cur_port] = 4;
+                 secondary_rank_group1_u8array[cur_port] = 5;
+                 tertiary_rank_group1_u8array[cur_port] = INVALID;
+                 quanternary_rank_group1_u8array[cur_port] = INVALID;
+                 break;
+           case 1:               // 1 rank lrdimm
+                 primary_rank_group1_u8array[cur_port] = 4;
+                 secondary_rank_group1_u8array[cur_port] = INVALID;
+                 tertiary_rank_group1_u8array[cur_port] = INVALID;
+                 quanternary_rank_group1_u8array[cur_port] = INVALID;
+                 break;
+           default:              // not 1, 2, 4, or 8 ranks
+                 primary_rank_group1_u8array[cur_port] = INVALID;
+                 secondary_rank_group1_u8array[cur_port] = INVALID;
+                 tertiary_rank_group1_u8array[cur_port] = INVALID;
+                 quanternary_rank_group1_u8array[cur_port] = INVALID;
+         }
+
       } else { // RDIMM or CDIMM
          if ((num_ranks_per_dimm_u8array[cur_port][0] > 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) {
             primary_rank_group0_u8array[cur_port] = 0;
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
index 3f5cbbdb3..a5944b2cd 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.2 2013/05/06 20:58:08 jmcgill Exp $
+// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.3 2013/08/20 02:05:06 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -50,7 +50,10 @@ using namespace fapi;
 // Constant definitions
 //------------------------------------------------------------------------------
 
+// lock polling constants
 const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS = 50;
+const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW = 2000000;
+const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM = 1;
 
 // OPCG/Clock Region Register values
 const uint64_t OPCG_REG0_FOR_SETPULSE  = 0x818C000000000000ull;
@@ -432,6 +435,13 @@ fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll(
                     FAPI_ERR("Error reading PLL lock register");
                     break;
                 }
+                rc = fapiDelay(PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW,
+                               PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM);
+                if (rc)
+                {
+                    FAPI_ERR("Error from fapiDelay");
+                    break;
+                }
             } while (!timeout &&
                      !data.isBitSet(PLL_LOCK_REG_LOCK_START_BIT,
                                     (PLL_LOCK_REG_LOCK_END_BIT-
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C
index a74e51013..e21c0100e 100755
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_control.C
@@ -20,24 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-/* begin_generated_IBM_copyright_prolog                            */
-/*                                                                 */
-/* This is an automatically generated copyright prolog.            */
-/* After initializing,  DO NOT MODIFY OR MOVE                      */ 
-/* --------------------------------------------------------------- */
-/* IBM Confidential                                                */
-/*                                                                 */
-/* Licensed Internal Code Source Materials                         */
-/*                                                                 */
-/* (C)Copyright IBM Corp.  2014, 2014                              */
-/*                                                                 */
-/* The Source code for this program is not published  or otherwise */
-/* divested of its trade secrets,  irrespective of what has been   */
-/* deposited with the U.S. Copyright Office.                       */
-/*  -------------------------------------------------------------- */
-/*                                                                 */
-/* end_generated_IBM_copyright_prolog                              */
-// $Id: p8_occ_control.C,v 1.1 2012/08/21 16:17:31 jimyac Exp $
+// $Id: p8_occ_control.C,v 1.2 2013/08/13 18:16:59 jimyac Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_control.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -120,6 +103,7 @@ p8_occ_control(const Target& i_target, const uint8_t i_ppc405_reset_ctrl, const
   // check ppc405_reset_ctrl
   if (!(i_ppc405_reset_ctrl <= PPC405_RESET_ON) ) {
     FAPI_ERR("Bad PPC405 Reset Setting Passed to Procedure => %d", i_ppc405_reset_ctrl);
+    const uint8_t& RESET_PARM = i_ppc405_reset_ctrl;
     FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCC_CONTROL_BAD_405RESET_PARM);
     return rc;
   }
@@ -127,6 +111,7 @@ p8_occ_control(const Target& i_target, const uint8_t i_ppc405_reset_ctrl, const
   // check sram_bv_ctrl
   if (!(i_ppc405_boot_ctrl <= PPC405_BOOT_OLD) ) {
     FAPI_ERR("Bad Boot Vector Setting Passed to Procedure => %d", i_ppc405_boot_ctrl);
+    const uint8_t& BOOT_PARM = i_ppc405_boot_ctrl;
     FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCC_CONTROL_BAD_405BOOT_PARM);
     return rc;
   }
diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C
index e31d02d77..1eaae9a14 100755
--- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C
+++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_occ_sram_init.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_occ_sram_init.C,v 1.3 2013/04/01 04:11:52 stillgs Exp $
+// $Id: p8_occ_sram_init.C,v 1.4 2013/08/13 18:17:02 jimyac Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_occ_sram_init.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -122,6 +122,7 @@ p8_occ_sram_init(const Target& i_target, uint32_t mode)
   {
   
     FAPI_ERR("Unknown mode passed to p8_occ_sram_init. Mode %x ....", mode);
+    const uint32_t& MODE = mode;
     FAPI_SET_HWP_ERROR(rc, RC_PROCPM_OCCSRAM_CODE_BAD_MODE);
     
   }
diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_occ_control_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_occ_control_errors.xml
index f218be909..dc33d36e4 100644
--- a/src/usr/hwpf/hwp/runtime_errors/p8_occ_control_errors.xml
+++ b/src/usr/hwpf/hwp/runtime_errors/p8_occ_control_errors.xml
@@ -20,32 +20,20 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: p8_occ_control_errors.xml,v 1.2 2013/05/23 18:44:08 stillgs Exp $ -->
+<!-- $Id: p8_occ_control_errors.xml,v 1.3 2013/08/13 18:15:45 jimyac Exp $ -->
 <!-- Error definitions for p8_occ_control procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
-    <rc>RC_PROCPM_OCC_CONTROL_BAD_MODE</rc>
-    <description>Unknown mode passed to p8_occ_control.</description>
-  </hwpError>
-  <!-- *********************************************************************** -->
-  <hwpError>
     <rc>RC_PROCPM_OCC_CONTROL_BAD_405RESET_PARM</rc>
     <description>Bad Parm value for i_ppc405_reset_ctrl passed to p8_occ_control.</description>
+    <ffdc>RESET_PARM</ffdc>
   </hwpError>  
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROCPM_OCC_CONTROL_BAD_405BOOT_PARM</rc>
     <description>Bad Parm value for i_ppc405_boot_ctrl passed to p8_occ_control.</description>
+    <ffdc>BOOT_PARM</ffdc>
   </hwpError>    
   <!-- *********************************************************************** -->
-  <hwpError>
-    <rc>RC_PROCPM_OCC_CONTROL_TEST</rc>
-    <description>Generic Error return code for p8_occ_control.</description>
-  </hwpError>
-  <!-- *********************************************************************** -->
-  <hwpError>
-    <rc>RC_PROCPM_OCC_CONTROL_PUTSCOM</rc>
-    <description>Put SCOM failed in p8_occ_control.</description>
-  </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/runtime_errors/p8_occ_sram_init_errors.xml b/src/usr/hwpf/hwp/runtime_errors/p8_occ_sram_init_errors.xml
index c2914f557..1bb26dc0c 100644
--- a/src/usr/hwpf/hwp/runtime_errors/p8_occ_sram_init_errors.xml
+++ b/src/usr/hwpf/hwp/runtime_errors/p8_occ_sram_init_errors.xml
@@ -20,17 +20,13 @@
 <!-- Origin: 30                                                             -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: p8_occ_sram_init_errors.xml,v 1.2 2013/05/23 18:44:12 stillgs Exp $ -->
+<!-- $Id: p8_occ_sram_init_errors.xml,v 1.3 2013/08/13 18:15:47 jimyac Exp $ -->
 <!-- Error definitions for p8_occ_sram_init procedure -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
     <rc>RC_PROCPM_OCCSRAM_CODE_BAD_MODE</rc>
     <description>Unknown mode passed to p8_occ_sram_init. </description>
-  </hwpError>
-  <!-- *********************************************************************** -->
-  <hwpError>
-    <rc>RC_PROCPM_OCCSRAM_TEST</rc>
-    <description>A placeholder as errors occur if there is only one error defined!.</description>
+    <ffdc>MODE</ffdc>
   </hwpError>
 </hwpErrors>