INITPROC: Hostboot - Low Priority HW Init Procedures for week of 5/7

SW202434

Change-Id: I6bf082deb2cbe927c0ba92d670906b232482578f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4627
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 260 insertions, 16 deletions

diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile
index f0a7fc5eb..bd373169e 100644
--- a/src/usr/hwpf/hwp/mc_config/makefile
+++ b/src/usr/hwpf/hwp/mc_config/makefile
@@ -40,19 +40,20 @@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_volt
 EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_freq
 
-OBJS =  mc_config.o			\
-        mss_volt.o 			\
-        mss_freq.o 			\
-        mss_eff_config.o                \
-        mss_eff_grouping.o              \
-        opt_memmap.o                    \
-        mss_eff_config_thermal.o        \
-        mss_eff_config_termination.o    \
-        mss_eff_config_rank_group.o     \
-        mss_eff_config_cke_map.o        \
-        mss_bulk_pwr_throttles.o        \
-        mss_throttle_to_power.o		\
-	mss_eff_config_shmoo.o
+OBJS =  mc_config.o                \
+        mss_volt.o                 \
+        mss_freq.o                 \
+        mss_eff_config.o           \
+        mss_eff_grouping.o         \
+        opt_memmap.o               \
+        mss_eff_config_thermal.o   \
+        mss_eff_config_termination.o \
+        mss_eff_config_rank_group.o  \
+        mss_eff_config_cke_map.o     \
+        mss_bulk_pwr_throttles.o     \
+        mss_throttle_to_power.o      \
+        mss_eff_config_shmoo.o       \
+        mss_error_support.o
 
 ##  NOTE: add a new directory onto the vpaths when you add a new HWP
 ##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
index 2bfadd4be..0017cac92 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
@@ -260,7 +260,7 @@ extern "C" {
            {
               FAPI_ERR("UNABLE TO GROUP");
               FAPI_ERR("FABRIC IS IN NON-CHECKER BOARD MODE.  SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' , TO SUPPORT 2MCS , 4MCS AND 8MCS GROUPING. OR ENABLE CHECKER BOARD. ");
-//@thi - hack              const fapi::Target & PROC_CHIP = i_target;
+              const fapi::Target & PROC_CHIP = i_target;
               FAPI_SET_HWP_ERROR(rc, RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE);
               return rc;
            }
@@ -289,7 +289,7 @@ extern "C" {
             {
                FAPI_ERR("UNABLE TO GROUP");
                FAPI_ERR("FABRIC IS IN CHECKER BOARD MODE . SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' ");
-//@thi - hack               const fapi::Target & PROC_CHIP = i_target;
+               const fapi::Target & PROC_CHIP = i_target;
                FAPI_SET_HWP_ERROR(rc, RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE);
                return rc;
 
@@ -668,7 +668,7 @@ extern "C" {
        else
        {
           FAPI_ERR("Mirror Base address overlaps with memory base address. ");
-//@thi - hack          const fapi::Target & PROC_CHIP = i_target;
+          const fapi::Target & PROC_CHIP = i_target;
           FAPI_SET_HWP_ERROR(rc, RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS);
           return rc;
        }
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C
new file mode 100644
index 000000000..4e11554e7
--- /dev/null
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C
@@ -0,0 +1,243 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C $ */
+/*                                                                        */
+/* IBM CONFIDENTIAL                                                       */
+/*                                                                        */
+/* COPYRIGHT International Business Machines Corp. 2013                   */
+/*                                                                        */
+/* p1                                                                     */
+/*                                                                        */
+/* Object Code Only (OCO) source materials                                */
+/* Licensed Internal Code Source Materials                                */
+/* IBM HostBoot Licensed Internal Code                                    */
+/*                                                                        */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
+/*                                                                        */
+/* Origin: 30                                                             */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+// $Id: mss_error_support.C,v 1.1 2013/03/21 19:04:19 bellows Exp $
+
+//------------------------------------------------------------------------------
+// *! (C) Copyright International Business Machines Corp. 2013
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+//------------------------------------------------------------------------------
+// *! TITLE : mss_error_support.C
+// *! DESCRIPTION : common and hwp error collecting programs
+// *! OWNER NAME : bellows@us.ibm.com
+// *! BACKUP NAME :
+// #! ADDITIONAL COMMENTS :
+//
+
+//------------------------------------------------------------------------------
+// Don't forget to create CVS comments when you check in your changes!
+//------------------------------------------------------------------------------
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|  Author: |  Date:  | Comment:
+//---------|----------|---------|-----------------------------------------------
+//  1.1    | 03/08/13 | bellows | Initial Version
+
+//----------------------------------------------------------------------
+//  Includes
+//----------------------------------------------------------------------
+
+#include <fapi.H>
+#include <mss_error_support.H>
+#include <cen_scom_addresses.H>
+using namespace fapi;
+
+// This is the FFDC HWP specially written to collect the data specified by RC_ERROR_MEM_GROUPING
+fapi::ReturnCode hwpCollectMemGrouping(const fapi::Target & i_target,fapi::ReturnCode & o_rc)
+{
+  fapi::ReturnCode l_rc;
+
+  uint32_t _ATTR_PROC_POS;
+  uint32_t _ATTR_CEN_POS;
+  uint8_t _ATTR_CHIP_UNIT_POS_MBA0;
+  uint8_t _ATTR_CHIP_UNIT_POS_MBA1;
+  uint8_t _ATTR_EFF_DIMM_SIZE0[2][2];
+  uint8_t _ATTR_EFF_DIMM_SIZE1[2][2];
+  uint8_t _ATTR_MSS_INTERLEAVE_ENABLE;
+  uint8_t _ATTR_ALL_MCS_IN_INTERLEAVING_GROUP;
+  uint64_t _ATTR_PROC_MEM_BASE;
+  uint64_t _ATTR_PROC_MIRROR_BASE;
+  uint8_t _ATTR_MSS_MEM_MC_IN_GROUP[8];
+  uint64_t _ATTR_PROC_MEM_BASES[8];
+  uint64_t _ATTR_PROC_MEM_SIZES[8];
+  uint32_t _ATTR_MSS_MCS_GROUP_32[16][16];
+  uint64_t _ATTR_PROC_MIRROR_BASES[4];
+  uint64_t _ATTR_PROC_MIRROR_SIZES[4];
+
+  std::vector<fapi::Target> l_mba_chiplets;
+  std::vector<fapi::Target> l_memb;
+
+  unsigned i;
+
+  l_rc = FAPI_ATTR_GET(ATTR_POS, &i_target, _ATTR_PROC_POS);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_POS (Proc), ignoring");
+  }
+
+  l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MEMBUF_CHIP, l_memb);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error fapiGetChildChiplets, ignoring");
+  }
+
+  for(i=0;i<l_memb.size();i++) {
+    l_rc = FAPI_ATTR_GET(ATTR_POS, &l_memb[i], _ATTR_CEN_POS);
+
+    if (l_rc)
+    {
+      FAPI_ERR("Error reading ATTR_POS (cen), ignoring");
+    }
+
+    l_rc = fapiGetChildChiplets(l_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets);
+
+    if (l_rc)
+    {
+      FAPI_ERR("Error fapiGetChildChiplets, ignoring");
+    }
+
+
+    l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[0], _ATTR_CHIP_UNIT_POS_MBA0);
+
+    if (l_rc)
+    {
+      FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS (0), ignoring");
+    }
+
+    l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[1], _ATTR_CHIP_UNIT_POS_MBA1);
+
+    if (l_rc)
+    {
+      FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS (1), ignoring");
+    }
+
+    l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[0], _ATTR_EFF_DIMM_SIZE0);
+
+    if (l_rc)
+    {
+      FAPI_ERR("Error reading ATTR_EFF_DIMM_SIZE (0), ignoring");
+    }
+
+    l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[1], _ATTR_EFF_DIMM_SIZE1);
+
+    if (l_rc)
+    {
+      FAPI_ERR("Error reading ATTR_EFF_DIMM_SIZE (1), ignoring");
+    }
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_MSS_INTERLEAVE_ENABLE,&i_target, _ATTR_MSS_INTERLEAVE_ENABLE);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_MSS_INTERLEAVE_ENABLE, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,_ATTR_ALL_MCS_IN_INTERLEAVING_GROUP); // system level attribute
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,_ATTR_PROC_MEM_BASE);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_PROC_MEM_BASE, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,_ATTR_PROC_MIRROR_BASE);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_MSS_MEM_MC_IN_GROUP, &i_target, _ATTR_MSS_MEM_MC_IN_GROUP);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_MSS_MEM_MC_IN_GROUP, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, &i_target, _ATTR_PROC_MEM_BASES);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_PROC_MEM_BASES, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &i_target, _ATTR_PROC_MEM_SIZES);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_PROC_MEM_SIZES, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32,&i_target, _ATTR_MSS_MCS_GROUP_32);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_MSS_MCS_GROUP_32, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, &i_target, _ATTR_PROC_MIRROR_BASES);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASES, ignoring");
+  }
+
+  l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, &i_target, _ATTR_PROC_MIRROR_SIZES);
+
+  if (l_rc)
+  {
+    FAPI_ERR("Error reading ATTR_PROC_MIRROR_SIZES, ignoring");
+  }
+
+
+  FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MSS_GROUPING_ATTRS);
+
+  return fapi::FAPI_RC_SUCCESS;
+}
+
+fapi::ReturnCode hwpCollectMemFIRs(const fapi::Target & i_target,fapi::ReturnCode & o_rc)
+{
+  fapi::ReturnCode l_rc;
+
+  const fapi::Target & CENCHIP = i_target;
+
+  FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MSS_FIRS);
+
+
+  std::vector<fapi::Target> l_mba_chiplets;
+  unsigned i;
+  l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets);
+  if (l_rc)
+  {
+    FAPI_ERR("Error fapiGetChildChiplets, ignoring");
+  }
+
+  for(i=0;i<l_mba_chiplets.size(); i++) {
+    const fapi::Target & CENCHIP_MBA = l_mba_chiplets[i];
+    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MBA_FIRS);
+
+  }
+
+
+
+  return fapi::FAPI_RC_SUCCESS;
+}