Hostboot - Updated HWPs from defect SW220729 (week 8/20)

Change-Id: Ic1c5956385b7fe0eae4ce0f5a79d17f6ce93592e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5988
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 79 insertions, 24 deletions

diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
index 3daec80bd..508ce4109 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_cke_map.C,v 1.3 2012/11/16 14:39:15 asaetow Exp $
+// $Id: mss_eff_config_cke_map.C,v 1.4 2013/08/16 13:45:30 kcook Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -42,7 +42,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.4   |          |         |
+//   1.4   | kcook    |16-AUG-12| Added LRDIMM support.
 //   1.3   | asaetow  |14-NOV-12| Added ATTR_EFF_SPCKE_MAP. 
 //   1.2   | asaetow  |13-NOV-12| Added FAPI_ERR for else "Undefined IBM_TYPE". 
 //         |          |         | Removed outter NUM_DROPS_PER_PORT check.
@@ -98,7 +98,7 @@ const uint8_t l_cke_map_u8array[IBM_TYPE_SIZE][DIMM_SIZE][RANK_SIZE] = {
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5A <-- UNDEFINED
    {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_5B
    {{0x80, 0x40, 0x80, 0x40}, {0x08, 0x04, 0x08, 0x04}},  // TYPE_5C
-   {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_5D <-- NOT YET SUPPORTED for LRDIMM DDR3
+   {{0x80, 0x40, 0x00, 0x00}, {0x08, 0x04, 0x00, 0x00}},  // TYPE_5D 
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6A <-- UNDEFINED
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6B <-- UNDEFINED
    {{0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}},  // TYPE_6C <-- UNDEFINED
@@ -240,8 +240,9 @@ fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba) {
                FAPI_ERR("Invalid IBM_TYPE for CDIMM on %s!", i_target_mba.toEcmdString());
                FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
             }
-            FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
+            FAPI_INF("WIP 8Rank LRDIMM IBM_TYPE on %s!", i_target_mba.toEcmdString());
+//            FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
+//            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
          } else if ( l_ibm_type_u8array[l_cur_port][l_cur_dimm] == fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_6A ) {
             l_ibm_type_index = 18;
             FAPI_ERR("Undefined IBM_TYPE on %s!", i_target_mba.toEcmdString());
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
index 4316c4d7c..2e7772ab5 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_rank_group.C,v 1.10 2013/04/17 11:26:02 asaetow Exp $
+// $Id: mss_eff_config_rank_group.C,v 1.11 2013/08/16 13:45:45 kcook Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -46,7 +46,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//   1.11  |          |         |
+//   1.11  | kcook    |16-AUG-13| Added LRDIMM support.
 //   1.10  | asaetow  |17-APR-13| Removed 32G CDIMM 1R dualdrop workaround.
 //         |          |         | NOTE: Needs mss_draminit_training.C v1.57 or newer.
 //   1.9   | asaetow  |01-APR-13| Added 32G CDIMM 1R dualdrop workaround.
@@ -160,23 +160,77 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) {
          //quanternary_rank_group3_u8array[cur_port] = INVALID;
       //} else if (dimm_type_u8 == LRDIMM) {
       if (dimm_type_u8 == LRDIMM) {
-         // HERE: NOT correct, need to account for ATTR_EFF_DIMM_RANKS_CONFIGED for LRDIMMs /w multi master ranks
-         primary_rank_group0_u8array[cur_port] = 0;
-         primary_rank_group1_u8array[cur_port] = 4;
-         primary_rank_group2_u8array[cur_port] = 8;
-         primary_rank_group3_u8array[cur_port] = 12;
-         secondary_rank_group0_u8array[cur_port] = 1;
-         secondary_rank_group1_u8array[cur_port] = 5;
-         secondary_rank_group2_u8array[cur_port] = 9;
-         secondary_rank_group3_u8array[cur_port] = 13;
-         tertiary_rank_group0_u8array[cur_port] = 2;
-         tertiary_rank_group1_u8array[cur_port] = 6;
-         tertiary_rank_group2_u8array[cur_port] = 10;
-         tertiary_rank_group3_u8array[cur_port] = 14;
-         quanternary_rank_group0_u8array[cur_port] = 3;
-         quanternary_rank_group1_u8array[cur_port] = 7;
-         quanternary_rank_group2_u8array[cur_port] = 11;
-         quanternary_rank_group3_u8array[cur_port] = 15;
+         primary_rank_group2_u8array[cur_port] = INVALID;
+         secondary_rank_group2_u8array[cur_port] = INVALID;
+         tertiary_rank_group2_u8array[cur_port] = INVALID;
+         quanternary_rank_group2_u8array[cur_port] = INVALID;
+
+         primary_rank_group3_u8array[cur_port] = INVALID;
+         secondary_rank_group3_u8array[cur_port] = INVALID;
+         tertiary_rank_group3_u8array[cur_port] = INVALID;
+         quanternary_rank_group3_u8array[cur_port] = INVALID;
+
+         // dimm 0 (far socket)
+         switch (num_ranks_per_dimm_u8array[cur_port][0]) {
+           case 4:               // 4 rank lrdimm
+                 primary_rank_group0_u8array[cur_port] = 0;
+                 secondary_rank_group0_u8array[cur_port] = 1;
+                 tertiary_rank_group0_u8array[cur_port] = 2;
+                 quanternary_rank_group0_u8array[cur_port] = 3;
+                 break;
+           case 8:               // 8 rank lrdimm falls through to 2 rank case
+         // Rank Multiplication mode needed, CS2 & CS3 used as address lines into LRBuffer
+         // RM=4 -> only 2 CS valid, each CS controls 4 ranks with CS2 & CS3 as address
+         // CS0 = rank 0, 2, 4, 6;  CS1 = rank 1, 3, 5, 7
+           case 2:               // 2 rank lrdimm
+                 primary_rank_group0_u8array[cur_port] = 0;
+                 secondary_rank_group0_u8array[cur_port] = 1;
+                 tertiary_rank_group0_u8array[cur_port] = INVALID;
+                 quanternary_rank_group0_u8array[cur_port] = INVALID;
+                 break;
+           case 1:               // 1 rank lrdimm
+                 primary_rank_group0_u8array[cur_port] = 0;
+                 secondary_rank_group0_u8array[cur_port] = INVALID;
+                 tertiary_rank_group0_u8array[cur_port] = INVALID;
+                 quanternary_rank_group0_u8array[cur_port] = INVALID;
+                 break;
+           default:              // not 1, 2, 4, or 8 ranks
+                 primary_rank_group0_u8array[cur_port] = INVALID;
+                 secondary_rank_group0_u8array[cur_port] = INVALID;
+                 tertiary_rank_group0_u8array[cur_port] = INVALID;
+                 quanternary_rank_group0_u8array[cur_port] = INVALID;
+         }
+         // dimm 1 (near socket)
+         switch (num_ranks_per_dimm_u8array[cur_port][1]) {
+           case 4:               // 4 rank lrdimm
+                 primary_rank_group1_u8array[cur_port] = 4;
+                 secondary_rank_group1_u8array[cur_port] = 5;
+                 tertiary_rank_group1_u8array[cur_port] = 6;
+                 quanternary_rank_group1_u8array[cur_port] = 7;
+                 break;
+           case 8:               // 8 rank lrdimm falls through to case 2
+         // Rank Multiplication mode needed, CS6 & CS7 used as address lines into LRBuffer
+         // RM=4 -> only 2 CS valid, each CS controls 4 ranks with CS6 & CS7 as address
+         // CS4 = rank 0, 2, 4, 6;  CS5 = rank 1, 3, 5, 7
+           case 2:               // 2 rank lrdimm, RM=0
+                 primary_rank_group1_u8array[cur_port] = 4;
+                 secondary_rank_group1_u8array[cur_port] = 5;
+                 tertiary_rank_group1_u8array[cur_port] = INVALID;
+                 quanternary_rank_group1_u8array[cur_port] = INVALID;
+                 break;
+           case 1:               // 1 rank lrdimm
+                 primary_rank_group1_u8array[cur_port] = 4;
+                 secondary_rank_group1_u8array[cur_port] = INVALID;
+                 tertiary_rank_group1_u8array[cur_port] = INVALID;
+                 quanternary_rank_group1_u8array[cur_port] = INVALID;
+                 break;
+           default:              // not 1, 2, 4, or 8 ranks
+                 primary_rank_group1_u8array[cur_port] = INVALID;
+                 secondary_rank_group1_u8array[cur_port] = INVALID;
+                 tertiary_rank_group1_u8array[cur_port] = INVALID;
+                 quanternary_rank_group1_u8array[cur_port] = INVALID;
+         }
+
       } else { // RDIMM or CDIMM
          if ((num_ranks_per_dimm_u8array[cur_port][0] > 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) {
             primary_rank_group0_u8array[cur_port] = 0;