diff options
| author | Thi Tran <thi@us.ibm.com> | 2015-04-14 08:52:58 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2015-05-06 22:19:45 -0500 |
| commit | 70fc635abb02e22af3206092f4be94d082d66e54 (patch) | |
| tree | d71b797275bb8476d98d9a8166fd4a667c882e5b /src/usr/hwpf/hwp/initfiles | |
| parent | 1bb0f18f747e2e1a4ede9df16eac2ca340c72552 (diff) | |
| download | talos-hostboot-70fc635abb02e22af3206092f4be94d082d66e54.tar.gz talos-hostboot-70fc635abb02e22af3206092f4be94d082d66e54.zip | |
SW302513: Brazos FW840 : remove MRW parser change used with SW29500 fixes on pre
CQ:SW302513
Change-Id: I4ac6e89f50d08bc601edde0d5015318022966e47
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17091
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17093
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile | 14 | ||||
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile | 15 |
2 files changed, 20 insertions, 9 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile index 988e7e911..02d4b5162 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile @@ -1,8 +1,10 @@ -#-- $Id: p8.abus.custom.scom.initfile,v 1.16 2015/02/25 21:00:12 jgrell Exp $ +#-- $Id: p8.abus.custom.scom.initfile,v 1.18 2015/04/13 16:17:02 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.18|jgrell |04/25/15| Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500) +#-- 1.17|jmcgill |03/24/15| remove l2u delay settings,given filter bypass soln (SW299659) #-- 1.15|jgrell |02/25/15| Added rx_fifo_final_l2u_dly for Venice only (SW296793) #-- 1.14|garyp |02/19/14| Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding #-- 1.13|jgrell |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284) @@ -488,11 +490,19 @@ scom 0x8004340B08010C3F { tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; } + +#--*********************************************************************************** +#------------------------------------------------------------------------------------- +#-- Brazos only +#------------------------------------------------------------------------------------- +#--*********************************************************************************** + scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) { bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; + rx_fifo_final_l2u_dly, 0b0011, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } + #--*********************************************************************************** #------------------------------------------------------------------------------------- #-- DD2+ Murano & Venice diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile index 6323938a3..2c47e5754 100644 --- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile +++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile @@ -1,8 +1,10 @@ -#-- $Id: p8.xbus.custom.scom.initfile,v 1.9 2015/02/25 21:00:13 jgrell Exp $ +#-- $Id: p8.xbus.custom.scom.initfile,v 1.11 2015/04/13 16:17:02 jgrell Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.11|jgrell |04/25/15|Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500) +#-- 1.10|jmcgill |03/24/15|remove l2u delay settings,given filter bypass soln (SW299659) #-- 1.9 |jgrell |02/25/15|Added rx_fifo_final_l2u_dly for Venice only (SW296793) #-- 1.8 |garyp |02/19/14|Added rx_min_eye_width for manufacturing and lab thresholding #-- 1.7 |jgrell |12/03/13|Set rx_sls_extend_sel to 001 for DD2 @@ -104,25 +106,24 @@ scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { #--************************************************************************************************************** #---------------------------------------------------------------------------------------------------------------- -# Venice Specific Inits +# Brazos Specific Inits #---------------------------------------------------------------------------------------------------------------- #--************************************************************************************************************** - scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; + rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } scom 0x800.0b(rx_fifo_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; + rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } scom 0x800.0b(rx_fifo_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; + rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } scom 0x800.0b(rx_fifo_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) { bits, scom_data, expr; - rx_fifo_final_l2u_dly, 0b0100, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1; + rx_fifo_final_l2u_dly, 0b0100, SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1; } |
