SW302513: Brazos FW840 : remove MRW parser change used with SW29500 fixes on pre

CQ:SW302513
Change-Id: I4ac6e89f50d08bc601edde0d5015318022966e47
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17091
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17093
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 68 insertions, 26 deletions

diff --git a/src/usr/hwpf/hwp/ei_bus_attributes.xml b/src/usr/hwpf/hwp/ei_bus_attributes.xml
index 9c15f1fd4..b0505ac8d 100755
--- a/src/usr/hwpf/hwp/ei_bus_attributes.xml
+++ b/src/usr/hwpf/hwp/ei_bus_attributes.xml
@@ -5,7 +5,9 @@
 <!--                                                                        -->
 <!-- OpenPOWER HostBoot Project                                             -->
 <!--                                                                        -->
-<!-- COPYRIGHT International Business Machines Corp. 2012,2014              -->
+<!-- Contributors Listed Below - COPYRIGHT 2012,2015                        -->
+<!-- [+] International Business Machines Corp.                              -->
+<!--                                                                        -->
 <!--                                                                        -->
 <!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
 <!-- you may not use this file except in compliance with the License.       -->
@@ -20,7 +22,7 @@
 <!-- permissions and limitations under the License.                         -->
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
-<!-- $Id: ei_bus_attributes.xml,v 1.12 2013/09/06 20:04:08 dcrowell Exp $ -->
+<!-- $Id: ei_bus_attributes.xml,v 1.13 2015/04/13 16:13:24 jgrell Exp $ -->
 <!--
     XML file specifying HWPF attributes.
     These are platInit attributes associated with chips.
@@ -39,7 +41,7 @@
 		called MSB Swap where lane 0 of the TX chip wires to lane n-1 on the RX chip where 'n' is the width of the bus. A basic description
 		of this capability is that the board designer can save layers on the board wiring by crossing the wiring between the two chips in
 		a prescribed manner. In a non-MSB Swapped bus Lane 0 on the TX chip wires to lane 0 on the RX chip, lane 1 to lane 1 and so on.
-		If a bus is MSB Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1 to lane 'n-2', etc. Random or
+		If a bus is MSB Swapped then lane 0 of the TX chip wires to lane 'n-1' of the RX chip, lane 1 to lane 'n-2', etc. Random or 
 		arbitrary wiring of TX to RX lanes on different chips is NOT ALLOWED.
 
         The Master Chip of two connected chips is defined as the chip with the smaller value of (100*Node + Pos).
@@ -49,12 +51,12 @@
 
 		The Downstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Downstream bus is wired msb to lsb etc. and
 		0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0).
-
+		
 		The Upstream TX_MSBSWAP from the MRW is a uint8 value. 0x01 means the Upstream bus is wired msb to lsb etc. and
 		0x00 means the bus is wired normally, msb to msb, lsb to lsb (lane0 to lane0).
-
+		
 		It is up to the platform code to set up each ATTR_EI_BUS_TX_MSBSWAP value for the correct target endpoints.
-
+		 
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -69,23 +71,23 @@
 		Usage:  TX_LANE_INVERT initfile setting for DMI and A buses
 		This attribute represents the polarity of a differential wire pair on the DMI and A buses. Normally differential pair
 		wires are connected between the two positive phases of the pair and the two negative phases between two chips. In the DMI
-		and Abus designs it's allowable for the board designer to wire the positive phase of a lane from one chip to the negative phase of the
+		and Abus designs it's allowable for the board designer to wire the positive phase of a lane from one chip to the negative phase of the 
 		of the other chip on that same lane and vice versa in order to simplify wiring on the board and reduce the number of board layers.
-		This attribute is set up as a 32 bit uint value interpreted as a 32 bit binary vector where the left-most bit position (msb/bit0)
-		corresponds to the polarity of lane 0 and the right-most bit position (lsb/bit31) corresponds to lane 31.
+		This attribute is set up as a 32 bit uint value interpreted as a 32 bit binary vector where the left-most bit position (msb/bit0) 
+		corresponds to the polarity of lane 0 and the right-most bit position (lsb/bit31) corresponds to lane 31. 		
 		A binary 1 in any position in the attribute means that the board designer has done a polarity swap within the differential
 		pair and the initfile must set the tx_lane_invert bit in the driving chip for that wire pair (called a lane).
-		The Downstream N/P Lane Swap Mask from the MRW represents the polarity of the bus wiring as it goes from the master chip to
-		the slave chip (master chip is defined as the chip with a lower value of (node*100 + chip position) and
+		The Downstream N/P Lane Swap Mask from the MRW represents the polarity of the bus wiring as it goes from the master chip to 
+		the slave chip (master chip is defined as the chip with a lower value of (node*100 + chip position) and 
 		Upstream N/P Lane Swap Mask represents the polarity of the bus wiring as it goes from the slave chip back to the master chip.
-		Examples:
+		Examples: 
 		- Port A2 on Chip Target n0p0 connects to Port A2 on chip target n0p2. This connection has a Downstream N/P Lane Swap Mask and
-		  an Upstream N/P Lane Swap Mask. Setting the Downstream N/P Lane Swap Mask to a value of 0x80000000 means lane 0 is polarity
+		  an Upstream N/P Lane Swap Mask. Setting the Downstream N/P Lane Swap Mask to a value of 0x80000000 means lane 0 is polarity 
 		  swapped and the initfile should set lane 0's tx_lane_invert bit on the n0p0 targeted chip (the so-called master chip).
-          If the Upstream N/P Lane Swap Mask is 0x20000000 this means lane 2 is polarity swapped and the initfile should set lane 2's
+          If the Upstream N/P Lane Swap Mask is 0x20000000 this means lane 2 is polarity swapped and the initfile should set lane 2's 
 		  tx_lane_invert bit on the n0p2 targeted chip (the so-called slave chip).
-		It is up to the platform code to set up each ATTR_EI_BUS_TX_LANE_INVERT value for the correct target endpoints,
-		ie. 0x80000000 for n0p0 and 0x20000000 for n0p2.
+		It is up to the platform code to set up each ATTR_EI_BUS_TX_LANE_INVERT value for the correct target endpoints, 
+		ie. 0x80000000 for n0p0 and 0x20000000 for n0p2. 
     </description>
     <valueType>uint32</valueType>
     <platInit/>
@@ -95,7 +97,7 @@
     <id>ATTR_DMI_REFCLOCK_SWIZZLE</id>
     <targetType>TARGET_TYPE_MCS_CHIPLET</targetType>
     <description>
-      Defines Murano/Venice/Naples FSI GP8 refclock enable field bit offset (0:7) associated with this MCS chip unit.
+      Defines Murano/Venice FSI GP8 refclock enable field bit offset (0:7) associated with this MCS chip unit.
     </description>
     <valueType>uint8</valueType>
     <platInit/>
@@ -111,4 +113,14 @@
     <platInit/>
   </attribute>
 
+  <attribute>
+    <id>ATTR_BRAZOS_RX_FIFO_OVERRIDE</id>
+    <targetType>TARGET_TYPE_SYSTEM</targetType>
+    <description>
+      Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500.
+    </description>
+    <valueType>uint8</valueType>
+    <platInit/>
+  </attribute>
+
 </attributes>
diff --git a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
index 988e7e911..02d4b5162 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.abus.custom.scom.initfile
@@ -1,8 +1,10 @@
-#-- $Id: p8.abus.custom.scom.initfile,v 1.16 2015/02/25 21:00:12 jgrell Exp $
+#-- $Id: p8.abus.custom.scom.initfile,v 1.18 2015/04/13 16:17:02 jgrell Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.18|jgrell  |04/25/15| Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500)
+#--     1.17|jmcgill |03/24/15| remove l2u delay settings,given filter bypass soln (SW299659)
 #--     1.15|jgrell  |02/25/15| Added rx_fifo_final_l2u_dly for Venice only (SW296793)
 #--     1.14|garyp   |02/19/14| Added rx_min_eye_width and rx_min_eye_height for manufacturing and lab thresholding
 #--     1.13|jgrell  |02/12/14| Added rx_wt_lane_disabled=1 on lane 17 (SW244284)
@@ -488,11 +490,19 @@ scom 0x8004340B08010C3F {
 	tx_prbs_tap_id, 0b011, ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
 }
 
+
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#-- Brazos only
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+
 scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(abus_gcr_addr) {
     bits,                   	  scom_data,		expr;
-    rx_fifo_final_l2u_dly,        0b0011,		ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
+    rx_fifo_final_l2u_dly,        0b0011,		SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1;
 }
 
+
 #--***********************************************************************************
 #-------------------------------------------------------------------------------------
 #-- DD2+ Murano & Venice
diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
index 6323938a3..2c47e5754 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
@@ -1,8 +1,10 @@
-#-- $Id: p8.xbus.custom.scom.initfile,v 1.9 2015/02/25 21:00:13 jgrell Exp $
+#-- $Id: p8.xbus.custom.scom.initfile,v 1.11 2015/04/13 16:17:02 jgrell Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.11|jgrell  |04/25/15|Updated attribute to system type at Thi's request so it can be applied to Brazos only. (SW299500)
+#--     1.10|jmcgill |03/24/15|remove l2u delay settings,given filter bypass soln (SW299659)
 #--     1.9 |jgrell  |02/25/15|Added rx_fifo_final_l2u_dly for Venice only (SW296793)
 #--     1.8 |garyp   |02/19/14|Added rx_min_eye_width for manufacturing and lab thresholding
 #--     1.7 |jgrell  |12/03/13|Set rx_sls_extend_sel to 001 for DD2
@@ -104,25 +106,24 @@ scom 0x800.0b(rx_result_chk_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
 
 #--**************************************************************************************************************
 #----------------------------------------------------------------------------------------------------------------
-# Venice Specific Inits
+# Brazos Specific Inits
 #----------------------------------------------------------------------------------------------------------------
 #--**************************************************************************************************************
-
 scom 0x800.0b(rx_fifo_mode_pg)(rx_grp0)(lane_na).0x(xbus0_gcr_addr) {
     bits,                   	  scom_data,		expr;
-    rx_fifo_final_l2u_dly,        0b0100,		ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
+    rx_fifo_final_l2u_dly,        0b0100,		SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1;
 }
 scom 0x800.0b(rx_fifo_mode_pg)(rx_grp1)(lane_na).0x(xbus0_gcr_addr) {
     bits,                   	  scom_data,		expr;
-    rx_fifo_final_l2u_dly,        0b0100,		ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
+    rx_fifo_final_l2u_dly,        0b0100,		SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1;
 }
 scom 0x800.0b(rx_fifo_mode_pg)(rx_grp2)(lane_na).0x(xbus0_gcr_addr) {
     bits,                   	  scom_data,		expr;
-    rx_fifo_final_l2u_dly,        0b0100,		ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
+    rx_fifo_final_l2u_dly,        0b0100,		SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1;
 }
 scom 0x800.0b(rx_fifo_mode_pg)(rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
     bits,                   	  scom_data,		expr;
-    rx_fifo_final_l2u_dly,        0b0100,		ATTR_CHIP_EC_FEATURE_SET_ABUS_PRBS_TAP_ID==1;
+    rx_fifo_final_l2u_dly,        0b0100,		SYS.ATTR_BRAZOS_RX_FIFO_OVERRIDE==1;
 }
 
 
diff --git a/src/usr/targeting/common/genHwsvMrwXml.pl b/src/usr/targeting/common/genHwsvMrwXml.pl
index 9ca0a8fba..9373de6d4 100755
--- a/src/usr/targeting/common/genHwsvMrwXml.pl
+++ b/src/usr/targeting/common/genHwsvMrwXml.pl
@@ -258,6 +258,7 @@ push @systemAttr,
                                    $reqPol->{'mnfg_th_cen_mba_rt_rce_per_rank'},
     "MNFG_TH_CEN_L4_CACHE_CES", $reqPol->{'mnfg_th_cen_l4_cache_ces'},
     "OPT_MEMMAP_GROUP_POLICY", $reqPol->{'memmap_group_policy'},
+    "BRAZOS_RX_FIFO_OVERRIDE", $reqPol->{'rx_fifo_final_l2u_dly_override'},
 ];
 
 my %procLoadline = ();
diff --git a/src/usr/targeting/common/xmltohb/attribute_types.xml b/src/usr/targeting/common/xmltohb/attribute_types.xml
index 17729cdb2..717b1fda9 100644
--- a/src/usr/targeting/common/xmltohb/attribute_types.xml
+++ b/src/usr/targeting/common/xmltohb/attribute_types.xml
@@ -15444,6 +15444,23 @@ firmware notes: Platforms should initialize this attribute to AUTO (0)</descript
         <readable/>
 </attribute>
 
+<attribute>
+    <id>BRAZOS_RX_FIFO_OVERRIDE</id>
+    <description>
+      Defines where to apply Brazos rx_fifo_final_l2u_dly override settings for SW299500.
+    </description>
+    <simpleType>
+      <uint8_t>
+        <default>0</default>
+      </uint8_t>
+    </simpleType>
+    <persistency>non-volatile</persistency>
+    <readable/>
+    <hwpfToHbAttrMap>
+        <id>ATTR_BRAZOS_RX_FIFO_OVERRIDE</id>
+        <macro>DIRECT</macro>
+    </hwpfToHbAttrMap>
+</attribute>
 
 <!-- === Manufacturing threshold Attributes of PRD === -->
 
diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
index 82ec014be..aabb107f3 100644
--- a/src/usr/targeting/common/xmltohb/target_types.xml
+++ b/src/usr/targeting/common/xmltohb/target_types.xml
@@ -301,6 +301,7 @@
     <attribute><id>OPT_MEMMAP_GROUP_POLICY</id></attribute>
     <attribute><id>FRU_ID</id></attribute>
     <attribute><id>BMC_FRU_ID</id></attribute>
+    <attribute><id>BRAZOS_RX_FIFO_OVERRIDE</id></attribute>
 </targetType>
 
 <targetType>