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| author | Thi Tran <thi@us.ibm.com> | 2013-08-29 21:42:28 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-09-11 14:53:55 -0500 |
| commit | acf1842a1be57bcc8b88175d15f0082e0f97dbd8 (patch) | |
| tree | 025345324a24aa8469212bc2db339df2ede5e050 /src/usr/hwpf/hwp/initfiles/mba_def.initfile | |
| parent | 86d20c2609a8f0fc8c082c68e0d76d6b05ffba1b (diff) | |
| download | talos-hostboot-acf1842a1be57bcc8b88175d15f0082e0f97dbd8.tar.gz talos-hostboot-acf1842a1be57bcc8b88175d15f0082e0f97dbd8.zip | |
Hostboot - Updated HWPs from defect SW220729 (week 8/20)
Change-Id: Ic1c5956385b7fe0eae4ce0f5a79d17f6ce93592e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5988
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/initfiles/mba_def.initfile')
| -rw-r--r-- | src/usr/hwpf/hwp/initfiles/mba_def.initfile | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile index 9985b7014..8b8d12166 100644 --- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile +++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile @@ -1,9 +1,10 @@ -#-- $Id: mba_def.initfile,v 1.46 2013/07/17 18:23:53 yctschan Exp $ +#-- $Id: mba_def.initfile,v 1.47 2013/08/15 19:20:23 yctschan Exp $ #-- CHANGE HISTORY: #-------------------------------------------------------------------------------- #-- Version:|Author: | Date: | Comment: #-- --------|--------|--------|-------------------------------------------------- +#-- 1.47|tschang | 8/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates #-- 1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations #-- 1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings #-- setting RD ODT according to Menlo's equation @@ -268,7 +269,7 @@ define def_has_spare = (SYS.ATTR_IS_SIMULATION==0) ; #define def_ATTR_EFF_DRAM_2N_MODE = (0); #define def_ATTR_EFF_IBM_TYPE = (SYS.ATTR_IS_SIMULATION==0) ; # will evaluate to false #define def_ATTR_EFF_NUM_DROPS_PER_PORT = (SYS.ATTR_IS_SIMULATION==0) ; # will evaluate to false -define def_ATTR_EFF_DRAM_2N_MODE = (CENTAUR.ATTR_MSS_FREQ == 1400) ; # will evaluate to false +#define def_ATTR_EFF_DRAM_2N_MODE = (CENTAUR.ATTR_MSS_FREQ == 1400) ; # will evaluate to false define CENTAUR = TGT1; @@ -1703,6 +1704,19 @@ scom 0x03010416 { # ATTR_EFF_DIMM_TYPE # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3 + +################################### +# TRACE_TRCTRL_CONFIG MBA01 Trace Control Configuration Register +# +# HW259719 - lcl_clk_gate_ctrl needs to be turned on and left on +# DD2 fixed ONLY +################################### + +scom 0x03010882 { + bits , scom_data , ATTR_FUNCTIONAL, expr; + 12:13 , 0b11 , 1 , (CENTAUR.ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL == 1); # turn on lcl_clk_gate_ctrl +} + ################################### # Turn on DDR PHY clks ################################### |
