TULETA PON - HW procedures (P8) - 03/25/2013

Change-Id: Iebbcd909dfefa1347facb592c947f360fb3e6b92
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3767
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 145 insertions, 73 deletions

diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 44734b1c8..4a7790ca4 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.49 2013/01/24 00:56:27 jdsloat Exp $
+// $Id: cen_scom_addresses.H,v 1.54 2013/03/08 23:25:10 jdsloat Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,10 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.53   | jdsloat  |08-Mar-13| Added MBA01_MBARPC0Q_0x03010434
+//  1.52   | jdsloat  |27-Feb-13| Fixed additional typos in READ TIMING REF
+//  1.51   | sglancy  |27-Feb-13| Fixed typos in READ TIMING REF
+//  1.50   | jdsloat  |27-Feb-13| Added READ TIMING REFERENCE REGS
 //  1.49   | jdsloat  |23-Jan-13| Added PC_RANK_GROUP and PC_RANK_GROUP_EXT
 //  1.48   | jdsloat  |09-Jan-13| Fixed typos.  Excuse me.
 //  1.47   | jdsloat  |09-Jan-13| Added DQS READ Phase select regs for RP 1-3
@@ -68,7 +72,7 @@
 //  1.41   | gollub   |26-Oct-12| Added MBECCFIR AND/OR MASK registers
 //         |          |         | Added MBSPA AND/OR MASK registers
 //  1.38   | pardeik  |31-Oct-12| Added N/M Throttling Control Register
-//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers 
+//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers
 //  1.36   | menlowuu |25-Oct-12| Added PHY port 1 disable bit registers
 //  1.35   | menlowuu |25-Oct-12| Added PHY disable bit registers
 //  1.34   | aditya   |12-Oct-12| Added MCBIST and DPHY registers
@@ -670,6 +674,11 @@ CONST_UINT64_T( MBA01_MBA_ERR_REPORTQ_0x0301041A     , ULL(0x0301041A) );
 CONST_UINT64_T( MBA01_MBA_WRD_MODE_0x03010449           , ULL(0x03010449) );
 
 
+//------------------------------------------------------------------------------
+//      MBA Power Control Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MBARPC0Q_0x03010434		,ULL(0x03010434) );
+
 
 
 
@@ -1079,7 +1088,7 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,	           ULL(0x8001087A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,	           ULL(0x80010C7A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,	           ULL(0x8001107A0301143F) );
-                                                                                       
+
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,	           ULL(0x8000007B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,	           ULL(0x8000047B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,	           ULL(0x8000087B0301143F) );
@@ -1320,6 +1329,34 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F0
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F , ULL(0x800113090301143F) );
 
 //------------------------------------------------------------------------------
+//     READ TIMING REFERENCE REGS
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F , ULL(0x800000700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F , ULL(0x800004700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F , ULL(0x800008700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F , ULL(0x80000C700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F , ULL(0x800010700301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F , ULL(0x800000710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F , ULL(0x800004710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F , ULL(0x800008710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F , ULL(0x80000C710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F , ULL(0x800010710301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F , ULL(0x800100700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F , ULL(0x800104700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F , ULL(0x800108700301143F	) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F , ULL(0x80010C700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F , ULL(0x800110700301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F , ULL(0x800100710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F , ULL(0x800104710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F , ULL(0x800108710301143F	) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F , ULL(0x80010C710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F , ULL(0x800110710301143F) );
+
+
+//------------------------------------------------------------------------------
 //     DQS Gate Delay Rank Pair 0
 //------------------------------------------------------------------------------
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F , ULL(0x800000130301143F) );
@@ -1361,7 +1398,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD1Q_0x02011782  , ULL(0x02011782) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD2Q_0x02011783  , ULL(0x02011783) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD3Q_0x02011784  , ULL(0x02011784) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD4Q_0x02011785  , ULL(0x02011785) );
-CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) ); 
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD6Q_0x02011787  , ULL(0x02011787) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD7Q_0x02011788  , ULL(0x02011788) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDQ_0x02011789   , ULL(0x02011789) );
@@ -1371,7 +1408,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A , ULL(0x0201178A) );
 //------------------------------------------------------------------------------
 
 CONST_UINT64_T( MBA01_CCS_MODEQ_0x030106a7       		, ULL(0x030106a7) );
-CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) );
 //------------------------------------------------------------------------------
 //     MBA MCBIST Configuration Register
 //------------------------------------------------------------------------------
@@ -1381,39 +1418,39 @@ CONST_UINT64_T( MBA01_MCBIST_MCBCFGQ_0x030106e0  		, ULL(0x030106e0) );
 //     MBS Error Map Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) );
 //------------------------------------------------------------------------------
 //     MBA MCBIST Memory Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) ); 
-CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) );
+CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) );
 //------------------------------------------------------------------------------
 //     MBA Fixed Data Seed Registers
 
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MCBIST_MCBFD0Q_0x030106be  		, ULL(0x030106be) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) );
 //------------------------------------------------------------------------------
 //     MBA Data Rotate Configuration Register
 
@@ -1425,7 +1462,7 @@ CONST_UINT64_T( MBA01_MCBIST_MCBDRCRQ_0x030106bd 		, ULL(0x030106bd) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_MCBIST01_MCBCMA1Q_0x02011672 		, ULL(0x02011672) );
 
-CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );      
+CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );
 CONST_UINT64_T( MBS_MCBIST01_MCBCMABQ_0x02011674 		, ULL(0x02011674) );
 //------------------------------------------------------------------------------
 //    MBA MCBIST Control Register
@@ -1436,60 +1473,60 @@ CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLQ_0x030106db		, ULL(0x030106db) );
 //    MBA MCBIST Memory Parameter Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) );
 //------------------------------------------------------------------------------
 //    MBA Address Map Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );    
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );       
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) ); 
-      
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );  
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) ); 
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );   
-
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) ); 
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) );
 CONST_UINT64_T( MBA01_MCBIST_MCBAGRAQ_0x030106d6  , ULL(0x030106d6) );
 //------------------------------------------------------------------------------
 //    MBA Performance monitor  Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );  
+CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );
 //------------------------------------------------------------------------------
 //    MBA Maintenance Buffer Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );
 //------------------------------------------------------------------------------
 //    DPHY01 PC Rank Pair Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) ); 
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) ); 
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) );
 //------------------------------------------------------------------------------
 //    MCBIST Random Data Seed Registers
 
@@ -1520,6 +1557,12 @@ CONST_UINT64_T( MBA01_MBA_FARB3Q_0x03010416, ULL(0x03010416) );
 //*********  ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/
 //******************************************************************************/
 // moved to common_scom_addresses.H       1/24/2010   mfred
+CONST_UINT64_T( CEN_SCAN_CLK_PLL,                   ULL(0x08100E0000000000) );
+CONST_UINT64_T( CEN_SCAN_PLL_GPTR,                  ULL(0x0810020000000000) );
+CONST_UINT64_T( CEN_SCAN_PLL_BNDY_FUNC,             ULL(0x0810080800000000) );
+
+CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
+CONST_UINT64_T( SCAN_GPTR_TIME_REP_NO_PLL,          ULL(0x0FE0023000000000) );
 
 #endif
 
@@ -1530,6 +1573,22 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.54  2013/03/08 23:25:10  jdsloat
+added MBA01_MBARPC0Q_0x03010434
+
+Revision 1.53  2013/03/07 17:01:39  gweber
+added centaur-only SCAN_ constants
+
+Revision 1.52  2013/02/27 20:36:18  jdsloat
+
+Fixed additional typos in READ TIMING REF
+
+Revision 1.51  2013/02/27 19:03:22  lapietra
+Fixed typos
+
+Revision 1.50  2013/02/27 16:43:31  jdsloat
+Added READ TIMING REFERENCE REGS
+
 Revision 1.49  2013/01/24 00:56:27  jdsloat
 Added PC_RANK_GROUP and PC_RANK_GROUP_EXT
 
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index 5566ba5f4..709301edc 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: common_scom_addresses.H,v 1.40 2013/01/08 18:24:16 koenig Exp $
+// $Id: common_scom_addresses.H,v 1.44 2013/03/18 19:43:27 jeshua Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -133,6 +133,7 @@ CONST_UINT64_T( GENERIC_CLK_SYNC_CONFIG_0x00030000    , ULL(0x00030000) );
 CONST_UINT64_T( GENERIC_CLK_REGION_0x00030006         , ULL(0x00030006) );
 CONST_UINT64_T( GENERIC_CLK_SCANSEL_0x00030007        , ULL(0x00030007) );
 CONST_UINT64_T( GENERIC_CLK_STATUS_0x00030008         , ULL(0x00030008) );
+CONST_UINT64_T( GENERIC_CLK_ERROR_0x00030009          , ULL(0x00030009) );
 CONST_UINT64_T( GENERIC_CLK_SCANDATA0_0x00038000      , ULL(0x00038000) );
 CONST_UINT64_T( GENERIC_CLK_SCAN_UPDATEDR_0x0003A000  , ULL(0x0003A000) );
 CONST_UINT64_T( GENERIC_CLK_SCAN_CAPTUREDR_0x0003C000 , ULL(0x0003C000) );
@@ -225,8 +226,6 @@ CONST_UINT32_T( CFAM_FSI_SBE_VITAL_0x0000281C         , ULL(0x0000281C) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( OTPROM_0x00010000                     , ULL(0x00010000) );
 
-CONST_UINT64_T( OTPROM_SECURE_SWITCHES_0x00010005     , ULL(0x00010005) );
-
 //------------------------------------------------------------------------------
 //      PIBMEM
 //------------------------------------------------------------------------------
@@ -596,7 +595,6 @@ CONST_UINT64_T( SCAN_ALLSCANEXVITAL,                ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALLSCANEXPRV,                  ULL(0x0FF00DCE00000000) );  // Looking to be deprecated
 CONST_UINT64_T( SCAN_ALL_BUT_GPTRTIMEREP,           ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALL_BUT_VITALDPLLGPTRTIME,     ULL(0x0FE00DCE00000000) );
-CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
 CONST_UINT64_T( SCAN_GPTR_TIME_REP,                 ULL(0x0FF0023000000000) );
 CONST_UINT64_T( SCAN_PLL_GPTR,                      ULL(0x0010020000000000) );
 CONST_UINT64_T( SCAN_PLL_BNDY_FUNC,                 ULL(0x0010080800000000) );
@@ -636,6 +634,18 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.44  2013/03/18 19:43:27  jeshua
+Removed OTPROM_SECURE_SWITCHES_0x00010005 because it's not common between P8 and Centaur. P8 code should use OTPC_M_SECURITY_SWITCH_0x00010005
+
+Revision 1.43  2013/03/07 17:02:58  gweber
+moved centaur-only SCAN_ constants to cen_scom_addresses.H
+
+Revision 1.42  2013/03/06 12:43:59  gweber
+Set CLOCK_REGION_PERV for scan0 perv
+
+Revision 1.41  2013/02/20 17:44:46  cmolsen
+Added CC error reg 30009.
+
 Revision 1.40  2013/01/08 18:24:16  koenig
 Updates - AK
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 6c6012d62..ca8d10265 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.139 2013/03/17 22:07:53 jmcgill Exp $
+// $Id: p8_scom_addresses.H,v 1.140 2013/03/21 13:50:57 pchatnah Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -862,7 +862,7 @@ CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C75         , ULL(0x02010C75) );
 //------------------------------------------------------------------------------
 // PLL lock information
 CONST_UINT64_T( PB_PLLLOCKREG_0x020F0019              , ULL(0x020F0019) );
-
+CONST_UINT64_T( PCBMS_INTERRUPT_TYPE_REG_0x000F001A ,   ULL(0x000F001A));
 //------------------------------------------------------------------------------
 //      CAPP
 //------------------------------------------------------------------------------
@@ -1824,6 +1824,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.140  2013/03/21 13:50:57  pchatnah
+ading checkstop register
+
 Revision 1.139  2013/03/17 22:07:53  jmcgill
 add L3 BAR registers