TULETA PON - HW procedures (P8) - 03/25/2013

Change-Id: Iebbcd909dfefa1347facb592c947f360fb3e6b92
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/3767
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

31 files changed, 2480 insertions, 3117 deletions

diff --git a/src/makefile b/src/makefile
index 5ed063483..e1c137c15 100644
--- a/src/makefile
+++ b/src/makefile
@@ -88,7 +88,7 @@ hbicore_DATA_MODULES =  sample.if p8.dmi.scom.if cen.dmi.scom.if \
                         p8.abus.scom.if p8.xbus.scom.if p8.mcs.scom.if \
                         p8.as.scom.if p8.nx.scom.if p8.dmi.custom.scom.if \
                         cen.dmi.custom.scom.if p8.abus.custom.scom.if \
-                        p8.xbus.custom.scom.if p8.psi.scom.if
+                        p8.xbus.custom.scom.if p8.psi.scom.if p8.tpbridge.scom.if
 
 hbicore_test_OBJECTS = ${hbicore_OBJECTS}
 hbicore_test_MODULES = ${hbicore_MODULES}
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
index 545e378bb..444ad0777 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp.C,v 1.7 2013/01/28 14:45:45 jmcgill Exp $
+// $Id: proc_build_smp.C,v 1.8 2013/02/25 18:11:44 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -89,6 +89,9 @@ fapi::ReturnCode proc_build_smp_process_system(
 
     do
     {
+        // TODO: link to attribute if PB AVP mode support is needed
+        io_smp.avp_mode = false;
+
         // get PB frequency attribute
         FAPI_DBG("proc_build_smp_process_system: Querying PB frequency attribute");
         rc = FAPI_ATTR_GET(ATTR_FREQ_PB,
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
index 8f2bc2489..9329711f1 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp.H,v 1.8 2013/01/21 03:11:30 jmcgill Exp $
+// $Id: proc_build_smp.H,v 1.9 2013/02/14 00:51:31 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -63,7 +63,6 @@
 // *!        (current: placeholder settings from Murano sim)
 // *! TODO:: phase 2 execution for Venice (FSP drawer integration)
 // *! TODO:: support for manufacturing AVP mode configurations
-// *! TODO:: attributes for PBIEX EX inits in winkle image (scan)
 //------------------------------------------------------------------------------
 
 #ifndef _PROC_BUILD_SMP_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
index 591496f77..a2e2f0a47 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_adu.C,v 1.3 2012/09/24 05:02:10 jmcgill Exp $
+// $Id: proc_build_smp_adu.C,v 1.4 2013/02/25 14:50:52 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -223,6 +223,7 @@ fapi::ReturnCode proc_build_smp_adu_check_status(
     fapi::ReturnCode rc;
     proc_adu_utils_adu_status status_exp, status_act;
     bool match = false;
+    uint8_t num_polls = 0;
 
     FAPI_DBG("proc_build_smp_adu_check_status: Start");
     do
@@ -242,13 +243,28 @@ fapi::ReturnCode proc_build_smp_adu_check_status(
         status_exp.pbinit_missing   = ADU_STATUS_BIT_DONT_CARE;
 
         // retreive actual status value
-        FAPI_DBG("proc_build_smp_adu_check_status: Calling library to read ADU status");
-        rc = proc_adu_utils_get_adu_status(i_target,
-                                           status_act);
-        if (!rc.ok())
+        while (num_polls < PROC_BUILD_SMP_MAX_STATUS_POLLS)
         {
-            FAPI_ERR("proc_build_smp_adu_check_status: Error from proc_adu_utils_get_adu_status");
-            break;
+            FAPI_DBG("proc_build_smp_adu_check_status: Calling library to read ADU status (poll %d)",
+                     num_polls+1);
+            rc = proc_adu_utils_get_adu_status(i_target,
+                                               status_act);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_build_smp_adu_check_status: Error from proc_adu_utils_get_adu_status");
+                break;
+            }
+
+            // status reported as busy, poll again
+            if (status_act.busy)
+            {
+                num_polls++;
+            }
+            // not busy, check for expected status
+            else
+            {
+                break;
+            }
         }
 
         // check status bits versus expected pattern
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
index 64ba94e0d..be4d538b3 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_adu.H,v 1.2 2012/09/05 03:11:26 jmcgill Exp $
+// $Id: proc_build_smp_adu.H,v 1.3 2013/02/25 14:50:53 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -49,6 +49,8 @@
 // Constants
 //------------------------------------------------------------------------------
 
+const uint32_t PROC_BUILD_SMP_MAX_STATUS_POLLS = 5;
+
 const uint32_t PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS = 1;
 const bool PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK = false;
 const uint32_t PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY = 128;
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
index 0c05f5861..669d6ef41 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_epsilon.C,v 1.4 2012/09/24 05:02:40 jmcgill Exp $
+// $Id: proc_build_smp_epsilon.C,v 1.6 2013/02/22 17:55:10 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -181,7 +181,11 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2(
     bool r_t1_fits = false;
     bool r_t2_fits = false;
     bool w_t2_fits = false;
-    uint32_t attr_value;
+    uint8_t l2_force_t2_attr_value;
+    uint32_t l2_r_t0_attr_value;
+    uint32_t l2_r_t1_attr_value;
+    uint32_t l2_r_t2_attr_value;
+    uint32_t l2_w_attr_value;
 
     // mark function entry
     FAPI_DBG("proc_build_smp_set_epsilons_l2: Start");
@@ -245,12 +249,12 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2(
 
         // set attributes based on unit implementation
         FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T2_EPS");
-        attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2)?
-                      (0):(i_eps_cfg.r_t2+1));
+        l2_r_t2_attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2)?
+                              (0):(i_eps_cfg.r_t2+1));
         rc = FAPI_ATTR_SET(
             ATTR_L2_R_T2_EPS,
             NULL,
-            attr_value);
+            l2_r_t2_attr_value);
 
         if (!rc.ok())
         {
@@ -259,12 +263,12 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2(
         }
 
         FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_W_EPS");
-        attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2)?
-                      (0):(i_eps_cfg.w_t2+1));
+        l2_w_attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2)?
+                           (0):(i_eps_cfg.w_t2+1));
         rc = FAPI_ATTR_SET(
             ATTR_L2_W_EPS,
             NULL,
-            attr_value);
+            l2_w_attr_value);
 
         if (!rc.ok())
         {
@@ -275,49 +279,54 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l2(
         // force tier2 if necessary
         if (!r_t0_fits || !r_t1_fits)
         {
-            FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_FORCE_R_T2_EPS");
-            uint8_t attr_value = PROC_BUILD_SMP_EPSILON_L2_FORCE_T2;
-            rc = FAPI_ATTR_SET(
-                ATTR_L2_FORCE_R_T2_EPS,
-                NULL,
-                attr_value);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_FORCE_R_T2_EPS)");
-                break;
-            }
+            l2_force_t2_attr_value = fapi::ENUM_ATTR_L2_FORCE_R_T2_EPS_ON;
+            l2_r_t0_attr_value = 0;
+            l2_r_t1_attr_value = 0;
         }
         // otherwise, write explicit read tier0, read tier1 attribute values
         else
         {
-            FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T0_EPS");
-            attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0)?
-                          (0):(i_eps_cfg.r_t0+1));
-            rc = FAPI_ATTR_SET(
-                ATTR_L2_R_T0_EPS,
-                NULL,
-                attr_value);
+            l2_force_t2_attr_value = fapi::ENUM_ATTR_L2_FORCE_R_T2_EPS_OFF;
+            l2_r_t0_attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0)?
+                                  (0):(i_eps_cfg.r_t0+1));
+            l2_r_t1_attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1)?
+                                  (0):(i_eps_cfg.r_t1+1));
+        }
 
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T0_EPS)");
-                break;
-            }
+        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_FORCE_R_T2_EPS");
+        rc = FAPI_ATTR_SET(
+            ATTR_L2_FORCE_R_T2_EPS,
+            NULL,
+            l2_force_t2_attr_value);
 
-            FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T1_EPS");
-            attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1)?
-                          (0):(i_eps_cfg.r_t1+1));
-            rc = FAPI_ATTR_SET(
-                ATTR_L2_R_T1_EPS,
-                NULL,
-                attr_value);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_FORCE_R_T2_EPS)");
+            break;
+        }
 
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T1_EPS)");
-                break;
-            }
+        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T0_EPS");
+        rc = FAPI_ATTR_SET(
+            ATTR_L2_R_T0_EPS,
+            NULL,
+            l2_r_t0_attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T0_EPS)");
+            break;
+        }
+
+        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T1_EPS");
+        rc = FAPI_ATTR_SET(
+            ATTR_L2_R_T1_EPS,
+            NULL,
+            l2_r_t1_attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T1_EPS)");
+            break;
         }
     } while(0);
 
@@ -343,7 +352,12 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3(
     bool r_t1_fits = false;
     bool r_t2_fits = false;
     bool w_t2_fits = false;
-    uint32_t attr_value;
+
+    uint8_t l3_force_t2_attr_value;
+    uint32_t l3_r_t0_attr_value;
+    uint32_t l3_r_t1_attr_value;
+    uint32_t l3_r_t2_attr_value;
+    uint32_t l3_w_attr_value;
 
     // mark function entry
     FAPI_DBG("proc_build_smp_set_epsilons_l3: Start");
@@ -409,12 +423,12 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3(
 
         // set attributes based on unit implementation
         FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T2_EPS");
-        attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2)?
-                      (0):(i_eps_cfg.r_t2+1));
+        l3_r_t2_attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2)?
+                              (0):(i_eps_cfg.r_t2+1));
         rc = FAPI_ATTR_SET(
             ATTR_L3_R_T2_EPS,
             NULL,
-            attr_value);
+            l3_r_t2_attr_value);
 
         if (!rc.ok())
         {
@@ -423,12 +437,12 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3(
         }
 
         FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_W_EPS");
-        attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2)?
-                      (0):(i_eps_cfg.w_t2+1));
+        l3_w_attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2)?
+                           (0):(i_eps_cfg.w_t2+1));
         rc = FAPI_ATTR_SET(
             ATTR_L3_W_EPS,
             NULL,
-            attr_value);
+            l3_w_attr_value);
 
         if (!rc.ok())
         {
@@ -439,49 +453,54 @@ fapi::ReturnCode proc_build_smp_set_epsilons_l3(
         // force tier2 if necessary
         if (!r_t0_fits || !r_t1_fits)
         {
-            FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_FORCE_R_T2_EPS");
-            uint8_t attr_value = PROC_BUILD_SMP_EPSILON_L3_FORCE_T2;
-            rc = FAPI_ATTR_SET(
-                ATTR_L3_FORCE_R_T2_EPS,
-                NULL,
-                attr_value);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_FORCE_R_T2_EPS)");
-                break;
-            }
+            l3_force_t2_attr_value = fapi::ENUM_ATTR_L3_FORCE_R_T2_EPS_ON;
+            l3_r_t0_attr_value = 0;
+            l3_r_t1_attr_value = 0;
         }
         // otherwise, write explicit read tier0, read tier1 attribute values
         else
         {
-            FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T0_EPS");
-            attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0)?
-                          (0):(i_eps_cfg.r_t0+1));
-            rc = FAPI_ATTR_SET(
-                ATTR_L3_R_T0_EPS,
-                NULL,
-                attr_value);
+            l3_force_t2_attr_value = fapi::ENUM_ATTR_L2_FORCE_R_T2_EPS_OFF;
+            l3_r_t0_attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0)?
+                                  (0):(i_eps_cfg.r_t0+1));
+            l3_r_t1_attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1)?
+                                  (0):(i_eps_cfg.r_t1+1));
+        }
 
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T0_EPS)");
-                break;
-            }
+        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_FORCE_R_T2_EPS");
+        rc = FAPI_ATTR_SET(
+            ATTR_L3_FORCE_R_T2_EPS,
+            NULL,
+            l3_force_t2_attr_value);
 
-            FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T1_EPS");
-            attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1)?
-                          (0):(i_eps_cfg.r_t1+1));
-            rc = FAPI_ATTR_SET(
-                ATTR_L3_R_T1_EPS,
-                NULL,
-                attr_value);
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_FORCE_R_T2_EPS)");
+            break;
+        }
 
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T1_EPS)");
-                break;
-            }
+        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T0_EPS");
+        rc = FAPI_ATTR_SET(
+            ATTR_L3_R_T0_EPS,
+            NULL,
+            l3_r_t0_attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T0_EPS)");
+            break;
+        }
+
+        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T1_EPS");
+        rc = FAPI_ATTR_SET(
+            ATTR_L3_R_T1_EPS,
+            NULL,
+            l3_r_t1_attr_value);
+
+        if (!rc.ok())
+        {
+            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T1_EPS)");
+            break;
         }
     } while(0);
 
@@ -1292,14 +1311,6 @@ fapi::ReturnCode proc_build_smp_set_epsilons(
                     break;
                 }
 
-                // NX
-                rc = proc_build_smp_set_epsilons_nx(target, i_smp.eps_cfg);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_nx");
-                    break;
-                }
-
                 // HCA
                 rc = proc_build_smp_set_epsilons_hca(target, i_smp.eps_cfg);
                 if (!rc.ok())
@@ -1308,12 +1319,24 @@ fapi::ReturnCode proc_build_smp_set_epsilons(
                     break;
                 }
 
-                // CAPP
-                rc = proc_build_smp_set_epsilons_capp(target, i_smp.eps_cfg);
-                if (!rc.ok())
+                // set epsilons for NX regions only if partial good attribute is set
+                if (p_iter->second.nx_enabled)
                 {
-                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_capp");
-                    break;
+                    // NX
+                    rc = proc_build_smp_set_epsilons_nx(target, i_smp.eps_cfg);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_nx");
+                        break;
+                    }
+
+                    // CAPP
+                    rc = proc_build_smp_set_epsilons_capp(target, i_smp.eps_cfg);
+                    if (!rc.ok())
+                    {
+                        FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_capp");
+                        break;
+                    }
                 }
 
                 // MCD
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
index 50b244482..2d1394838 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_epsilon.H,v 1.2 2012/09/05 03:11:55 jmcgill Exp $
+// $Id: proc_build_smp_epsilon.H,v 1.4 2013/03/17 21:43:43 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -55,13 +55,14 @@
 const uint32_t PROC_BUILD_SMP_EPSILON_MIN_VALUE = 0x1;
 const uint32_t PROC_BUILD_SMP_EPSILON_MAX_VALUE = 0xFFFFFFFF;
 
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_HE[] = {    6,    6,    7,    8,    9,   17 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_HE[] = {   42,   44,   46,   49,   53,   75 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = {   85,   87,   89,   92,   96,  118 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[]  = {   57,   59,   61,   64,   68,   90 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[]    = {   30,   31,   31,   32,   34,   41 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[]  = {   13,   13,   14,   15,   16,   23 };
-const uint32_t PROC_BUILD_SMP_EPSILON_P_HE[]    = {  925, 1605, 1605, 1605, 1605, 1605 };
+// MR epsilon (Murano)
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_HE[] = {    5,    5,    6,    7,    8,   15 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_HE[] = {   35,   37,   39,   41,   45,   63 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = {   71,   73,   75,   77,   80,   99 };
+const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[]  = {   55,   56,   58,   60,   65,   82 };
+const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[]    = {   26,   27,   28,   29,   30,   35 };
+const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[]  = {   26,   27,   28,   29,   30,   35 };
+const uint32_t PROC_BUILD_SMP_EPSILON_P_HE[]    = {  771, 1338, 1338, 1338, 1338, 1338 };
 
 const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_LE[] = {    6,    6,    7,    8,    9,   17 };
 const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_LE[] = {    6,    6,    7,    8,    9,   17 };
@@ -82,16 +83,12 @@ const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1 = 512;
 const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2 = 2048;
 const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2 = 128;
 
-const uint8_t  PROC_BUILD_SMP_EPSILON_L2_FORCE_T2 = 0x1;
-
 // L3
 const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0 = 512;
 const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1 = 512;
 const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2 = 2048;
 const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2 = 128;
 
-const uint8_t  PROC_BUILD_SMP_EPSILON_L3_FORCE_T2 = 0x1;
-
 // MCS
 const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0 = 1016;
 const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1 = 1016;
diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
index 43694298c..a34f347bc 100644
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
@@ -20,222 +20,176 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_clear_firs.C,v 1.5 2013/02/20 09:40:22 jaswamin Exp $

-// *!***************************************************************************

-// *! (C) Copyright International Business Machines Corp. 2012, 2013

-// *!           All Rights Reserved -- Property of IBM

-// *!                   *** IBM Confidential ***

-// *!***************************************************************************

-// *! FILENAME             : io_clear_firs.C

-// *! TITLE                : 

-// *! DESCRIPTION          : To clear summary fir registers

-// *! CONTEXT              : 

-// *!

-// *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com

-// *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com

-// *!

-// *!***************************************************************************

-// CHANGE HISTORY:

-//------------------------------------------------------------------------------

-// Version:|Author: | Date:  | Comment:

-// --------|--------|--------|--------------------------------------------------

-//   1.3   |varkeykv|02/18/13|  Missing function check in

-//   1.2   |jaswamin|02/14/13|  function for reading the fir scom register contents, enums and arrays for doing fir isolation

-//   1.1   |jaswamin|02/14/13|  Additions for reading the fir register.

-//   1.0   |jaswamin|01/30/13|  Initial check in .

-//------------------------------------------------------------------------------

-

-#include <fapi.H>

-#include "io_clear_firs.H"

-//#include "gcr_funcs.H"

-//#include "ei4_regs.h"

-

-extern "C" {

-

-

+// $Id: io_clear_firs.C,v 1.9 2013/03/26 14:45:18 jaswamin Exp $
+// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 2012, 2013
+// *!           All Rights Reserved -- Property of IBM
+// *!                   *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME             : io_clear_firs.C
+// *! TITLE                : 
+// *! DESCRIPTION          : To clear summary fir registers
+// *! CONTEXT              : 
+// *!
+// *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com
+// *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date:  | Comment:
+// --------|--------|--------|--------------------------------------------------
+//   1.9   |jaswmain|03/26/13|  Removed DOS line endings
+//   1.8   |jaswamin|03/25/13|  Removed 64 bit fir clearing function.
+//   1.7   |varkeykv|03/20/13|  Additional moved FIR functions from clear firs to training files
+//   1.6   |jaswamin|03/05/13|  Modifications as per review comments
+//   1.5   |jaswamin|02/20/13|  Changes as per review comment
+//   1.4   |varkeykv|02/18/13|  Missing function check in
+//   1.3   |jaswamin|02/14/13|  function for reading the fir scom register contents, enums and arrays for doing fir isolation
+//   1.2   |jaswamin|02/14/13|  Additions for reading the fir register.
+//   1.1   |jaswamin|01/30/13|  Initial check in .
+//------------------------------------------------------------------------------
+
+#include <fapi.H>
+#include "io_clear_firs.H"
+//#include "gcr_funcs.H"
+//#include "ei4_regs.h"
+
+extern "C" {
+
+
 using namespace fapi;
 
-// For clearing the FIR mask , used by io run training 
-ReturnCode clear_fir_mask_reg(const Target &i_target,fir_io_interface_t i_chip_interface){
+
+// for toggling the rx and tx fir reset.
+ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_interface,uint32_t i_group){
+    
+    ReturnCode rc;
+    uint32_t rc_ecmd=0;
+    uint16_t bits = 0;
+    ecmdDataBufferBase data_buffer;
+ 
+    ecmdDataBufferBase set_bits(16);
+    ecmdDataBufferBase clear_bits(16);
+    
+    //set the rx_fir_reset bit
+    bits=rx_fir_reset;
+    rc_ecmd|=set_bits.insert(bits,0,16);
+    bits=rx_fir_reset_clear;
+    rc_ecmd|=clear_bits.insert(bits,0,16);
+    if(rc_ecmd)
+    {
+        rc.setEcmdError(rc_ecmd);
+        return(rc);
+    }
+    rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+    
+    //clear the rx_fir_reset bit
+    bits=0x0000;
+    rc_ecmd|=set_bits.insert(bits,0,16);
+    bits=rx_fir_reset_clear;
+    rc_ecmd|=clear_bits.insert(bits,0,16);
+    if(rc_ecmd)
+    {
+        rc.setEcmdError(rc_ecmd);
+        return(rc);
+    }
+    rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+    
+    //set the tx_fir_reset bit
+    bits=tx_fir_reset;
+    rc_ecmd|=set_bits.insert(bits,0,16);
+    bits=tx_fir_reset_clear;
+    rc_ecmd|=clear_bits.insert(bits,0,16);
+    if(rc_ecmd)
+    {
+        rc.setEcmdError(rc_ecmd);
+        return(rc);
+    }
+    rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+    
+    //clear the tx_fir_reset
+    bits=0x0000;
+    rc_ecmd|=set_bits.insert(bits,0,16);
+    bits=tx_fir_reset_clear;
+    rc_ecmd|=clear_bits.insert(bits,0,16);
+    if(rc_ecmd)
+    {
+        rc.setEcmdError(rc_ecmd);
+        return(rc);
+    }
+    rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
+    
+    return(rc);
+
+    
+}
+
+
+ReturnCode read_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface,ecmdDataBufferBase &o_databuf_64bit){
     
     ReturnCode rc;
-//@thi - Fixed compiler error. Varkey will fix this in next version
-//    uint32_t rc_ecmd=0;
-    uint64_t  scom_address64=0;
-    ecmdDataBufferBase putscom_data64(64),temp(64);
-    //rc_ecmd |=getscom_data64.flushTo0();
-    //rc_ecmd |=putscom_data64.flushTo0();
-    FAPI_INF("io_run_training:In the Clear FIR MASK register function ");
-    //get the 64 bit data
-    temp.setDoubleWord(0,fir_clear_mask_reg_addr[i_chip_interface]);
+    uint32_t rc_ecmd=0;
+    uint64_t scom_address64=0;
+    ecmdDataBufferBase temp(64);
+    rc_ecmd |=o_databuf_64bit.flushTo0();
+    
+    //get the 64 bit scom address.
+    temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]);
     scom_address64=temp.getDoubleWord(0);
     
-    //do the putscom
-    rc=fapiPutScom( i_target, scom_address64, putscom_data64);
+    //read the 64 bit fir register
+    rc=fapiGetScom(i_target,scom_address64,o_databuf_64bit);
     
     return(rc);
+}
+
+ReturnCode io_clear_firs(const fapi::Target &i_target){
+    
+    ReturnCode rc;
+    fir_io_interface_t interface;
+    io_interface_t gcr_interface; // requires different base address for gcr scoms
+    uint32_t group;
     
-}

-

-// for toggling the rx and tx fir reset.

-ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_interface,uint32_t i_group){

-    

-    ReturnCode rc;

-    uint32_t rc_ecmd=0;

-    uint16_t bits = 0;

-    ecmdDataBufferBase data_buffer;

- 

-    ecmdDataBufferBase set_bits(16);

-    ecmdDataBufferBase clear_bits(16);

-    

-    FAPI_DBG("In the Clear fir procedure");

-    //const Target *target_ptr=&target;

-    

-    //set the rx_fir_reset bit

-    bits=rx_fir_reset;

-    rc_ecmd|=set_bits.insert(bits,0,16);

-    bits=rx_fir_reset_clear;

-    rc_ecmd|=clear_bits.insert(bits,0,16);

-    if(rc_ecmd)

-    {

-        rc.setEcmdError(rc_ecmd);

-        return(rc);

-    }

-    rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}

-    

-    //clear the rx_fir_reset bit

-    bits=0x0000;

-    rc_ecmd|=set_bits.insert(bits,0,16);

-    bits=rx_fir_reset_clear;

-    rc_ecmd|=clear_bits.insert(bits,0,16);

-    if(rc_ecmd)

-    {

-        rc.setEcmdError(rc_ecmd);

-        return(rc);

-    }

-    rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}

-    

-    //set the tx_fir_reset bit

-    bits=tx_fir_reset;

-    rc_ecmd|=set_bits.insert(bits,0,16);

-    bits=tx_fir_reset_clear;

-    rc_ecmd|=clear_bits.insert(bits,0,16);

-    if(rc_ecmd)

-    {

-        rc.setEcmdError(rc_ecmd);

-        return(rc);

-    }

-    rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}

-    

-    //clear the tx_fir_reset

-    bits=0x0000;

-    rc_ecmd|=set_bits.insert(bits,0,16);

-    bits=tx_fir_reset_clear;

-    rc_ecmd|=clear_bits.insert(bits,0,16);

-    if(rc_ecmd)

-    {

-        rc.setEcmdError(rc_ecmd);

-        return(rc);

-    }

-    rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}

-    

-    return(rc);

-

-    

-}

-

-ReturnCode clear_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface){

-    

-    ReturnCode rc;

-//@thi - Fixed compiler error. Varkey will fix this in next version
-//    uint32_t rc_ecmd=0;

-    uint64_t  scom_address64=0;

-    ecmdDataBufferBase putscom_data64(64),temp(64);

-    //rc_ecmd |=getscom_data64.flushTo0();

-    //rc_ecmd |=putscom_data64.flushTo0();

-    

-    //get the 64 bit data

-    temp.setDoubleWord(0,fir_clear_reg_addr[i_chip_interface]);

-    scom_address64=temp.getDoubleWord(0);

-    

-    //do the putscom

-    rc=fapiPutScom( i_target, scom_address64, putscom_data64);

-    

-    return(rc);

-    

-}

-

-ReturnCode read_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface,ecmdDataBufferBase &o_databuf_64bit){

-    

-    ReturnCode rc;

-    uint32_t rc_ecmd=0;

-    uint64_t scom_address64=0;

-    ecmdDataBufferBase temp(64);

-    rc_ecmd |=o_databuf_64bit.flushTo0();

-    

-    //rc_ecmd |=putscom_data64.flushTo0();

-    

-    //get the 64 bit scom address.

-    temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]);

-    scom_address64=temp.getDoubleWord(0);

-    

-    //read the 64 bit fir register

-    rc=fapiGetScom(i_target,scom_address64,o_databuf_64bit);

-    

-    return(rc);

-    

-    

-}

-

-ReturnCode io_clear_firs(const fapi::Target &i_target){

-    

-    ReturnCode rc;

-    fir_io_interface_t interface;

-    io_interface_t gcr_interface; // requires different base address for gcr scoms

-    uint32_t group;

-    

-    //on dmi

-    if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){

-          FAPI_DBG("This is a Processor DMI bus using base DMI scom address");

-          interface=FIR_CP_IOMC0_P0; // base scom for MC bus

-          gcr_interface=CP_IOMC0_P0;

-          group=3; // design requires us to swap

-          

-     }

-     else if((i_target.getType() ==  fapi::TARGET_TYPE_MEMBUF_CHIP)){

-            FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");

-            interface=FIR_CEN_DMI;

-            gcr_interface=CEN_DMI;

-            group=0;

-           

-     }

-     else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){

-            FAPI_DBG("This is a X Bus invocation");

-            interface=FIR_CP_FABRIC_X0;

-            gcr_interface=CP_FABRIC_X0;

-            group=0;

-            

-     }

-     

-     else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){

-            FAPI_DBG("This is an A Bus invocation");

-            interface=FIR_CP_FABRIC_A0;

-            gcr_interface=CP_FABRIC_A0;

-            group=0;

-            

-     }

-     else{

-        FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances");

-        FAPI_SET_HWP_ERROR(rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC);

-        return(rc);

-     }

-     

-    rc=clear_fir_err_regs(i_target,gcr_interface,group);

-    if(rc){

-               return rc;

-    }

-    rc=clear_fir_reg(i_target,interface);

-    return(rc);

-}

-

-} //end extern C

+    //on dmi
+    if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
+          FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
+          interface=FIR_CP_IOMC0_P0; // base scom for MC bus
+          gcr_interface=CP_IOMC0_P0;
+          group=3; // design requires us to swap
+          
+     }
+     else if((i_target.getType() ==  fapi::TARGET_TYPE_MEMBUF_CHIP)){
+            FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
+            interface=FIR_CEN_DMI;
+            gcr_interface=CEN_DMI;
+            group=0;
+           
+     }
+     else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){
+            FAPI_DBG("This is a X Bus invocation");
+            interface=FIR_CP_FABRIC_X0;
+            gcr_interface=CP_FABRIC_X0;
+            group=0;
+            
+     }
+     
+     else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
+            FAPI_DBG("This is an A Bus invocation");
+            interface=FIR_CP_FABRIC_A0;
+            gcr_interface=CP_FABRIC_A0;
+            group=0;
+            
+     }
+     else{
+        FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances");
+        FAPI_SET_HWP_ERROR(rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC);
+        return(rc);
+     }
+     
+    rc=clear_fir_err_regs(i_target,gcr_interface,group);
+    
+    return(rc);
+}
+
+} //end extern C
diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
index d5bacf3a1..4821e2a31 100644
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
@@ -20,60 +20,86 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_clear_firs.H,v 1.4 2013/02/20 09:40:22 jaswamin Exp $

-#ifndef IO_CLEAR_FIRS_H

-#define IO_CLEAR_FIRS_H

-

-#include <fapi.H>

-#include "gcr_funcs.H"

-

-using namespace fapi;

-

-/**

- * io_clear_firs HWP func pointer typedef

- *

- */

-typedef fapi::ReturnCode (*io_clear_firs_FP_t)(const fapi::Target &target);

-

-// P8 chip interfaces

-const uint32_t FIR_INTERFACES=8;

-const uint32_t FIR_ISOLATION_REGS=42;

-

-enum fir_io_interface_t {FIR_CP_FABRIC_X0,

-                FIR_CP_FABRIC_X1,

-                FIR_CP_FABRIC_X2,

-                FIR_CP_FABRIC_X3,

-                FIR_CP_FABRIC_A0,

-                FIR_CP_IOMC0_P0,  

-                FIR_CP_IOMC1_P0,  

-                FIR_CEN_DMI };

-           

-const char * const fir_interface_name[FIR_INTERFACES] = {"CP_FABRIC_X0",

-                                            "CP_FABRIC_X1",

-                                            "CP_FABRIC_X2",

-                                            "CP_FABRIC_X3",

-                                            "CP_FABRIC_A0",

-                                            "CP_IOMC0_P0",  

-                                            "CP_IOMC1_P0",  

-                                            "CEN_DMI" };

-                                            

-// FIR register addresses for interfaces

-const uint32_t fir_clear_reg_addr[FIR_INTERFACES] = {   0x04011001,

-                                                  0x04011401,

-                                                  0x04011c01,

-                                                  0x04011801,

-                                                  0x08010c01, 

-                                                  0x02011a01, 

-                                                  0x02011e01, 

-                                                  0x02010401  };

-                                                  

-const uint32_t fir_rw_reg_addr[FIR_INTERFACES]={0x04011000,

-                                                  0x04011400,

-                                                  0x04011c00,

-                                                  0x04011800,

-                                                  0x08010c00, 

-                                                  0x02011a00, 

-                                                  0x02011e00, 

+// $Id: io_clear_firs.H,v 1.7 2013/03/26 14:45:18 jaswamin Exp $
+// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 2012, 2013
+// *!           All Rights Reserved -- Property of IBM
+// *!                   *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME             : io_clear_firs.H
+// *! TITLE                : 
+// *! DESCRIPTION          : To clear summary fir registers
+// *! CONTEXT              : 
+// *!
+// *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com
+// *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date:  | Comment:
+// --------|--------|--------|--------------------------------------------------
+//   1.7   |jaswmain|03/26/13|  Removed DOS line endings
+//   1.6   |jaswamin|03/25/13|  Removed 64 bit fir clearing function.
+//   1.5   |varkeykv|03/20/13|  Additional moved FIR functions from clear firs to training files
+//   1.4   |jaswamin|02/20/13|  Changes as per review comment
+//   1.3   |varkeykv|02/18/13|  Added func decl for clear mask fir function
+//   1.2   |jaswamin|02/14/13|  function for reading the fir scom register contents,enums and arrays for doing fir isolation
+//   1.1   |jaswamin|01/30/13|  Initial check in .
+//------------------------------------------------------------------------------
+#ifndef IO_CLEAR_FIRS_H
+#define IO_CLEAR_FIRS_H
+
+#include <fapi.H>
+#include "gcr_funcs.H"
+
+using namespace fapi;
+
+/**
+ * io_clear_firs HWP func pointer typedef
+ *
+ */
+typedef fapi::ReturnCode (*io_clear_firs_FP_t)(const fapi::Target &target);
+
+// P8 chip interfaces
+const uint32_t FIR_INTERFACES=8;
+const uint32_t FIR_ISOLATION_REGS=42;
+
+enum fir_io_interface_t {FIR_CP_FABRIC_X0,
+                FIR_CP_FABRIC_X1,
+                FIR_CP_FABRIC_X2,
+                FIR_CP_FABRIC_X3,
+                FIR_CP_FABRIC_A0,
+                FIR_CP_IOMC0_P0,  
+                FIR_CP_IOMC1_P0,  
+                FIR_CEN_DMI };
+           
+const char * const fir_interface_name[FIR_INTERFACES] = {"CP_FABRIC_X0",
+                                            "CP_FABRIC_X1",
+                                            "CP_FABRIC_X2",
+                                            "CP_FABRIC_X3",
+                                            "CP_FABRIC_A0",
+                                            "CP_IOMC0_P0",  
+                                            "CP_IOMC1_P0",  
+                                            "CEN_DMI" };
+                                            
+// FIR register addresses for interfaces
+const uint32_t fir_clear_reg_addr[FIR_INTERFACES] = {   0x04011001,
+                                                  0x04011401,
+                                                  0x04011c01,
+                                                  0x04011801,
+                                                  0x08010c01, 
+                                                  0x02011a01, 
+                                                  0x02011e01, 
+                                                  0x02010401  };
+                                                  
+const uint32_t fir_rw_reg_addr[FIR_INTERFACES]={0x04011000,
+                                                  0x04011400,
+                                                  0x04011c00,
+                                                  0x04011800,
+                                                  0x08010c00, 
+                                                  0x02011a00, 
+                                                  0x02011e00, 
                                                   0x02010400  };
                                                   
 const uint32_t fir_clear_mask_reg_addr[FIR_INTERFACES]={0x04011004,
@@ -83,94 +109,92 @@ const uint32_t fir_clear_mask_reg_addr[FIR_INTERFACES]={0x04011004,
                                                   0x08010c04, 
                                                   0x02011a04, 
                                                   0x02011e04, 
-                                                  0x02010404  };

-enum fir_error_type{

-    RX_PARITY,

-    TX_PARITY,

-    GCR_HANG_ERROR,

-    BUS0_SPARE_DEPLOYED=9,

-    BUS0_MAX_SPARES_EXCEEDED=10,

-    BUS0_RECALIBRATION_ERROR=11,

-    BUS0_TOO_MANY_BUS_ERRORS=12,

-    BUS1_SPARE_DEPLOYED=17,

-    BUS1_MAX_SPARES_EXCEEDED=18,

-    BUS1_RECALIBRATION_ERROR=19,

-    BUS1_TOO_MANY_BUS_ERRORS=20,

-    BUS2_SPARE_DEPLOYED=25,

-    BUS2_MAX_SPARES_EXCEEDED=26,

-    BUS2_RECALIBRATION_ERROR=27,

-    BUS2_TOO_MANY_BUS_ERRORS=28,

-    BUS3_SPARE_DEPLOYED=33,

-    BUS3_MAX_SPARES_EXCEEDED=34,

-    BUS3_RECALIBRATION_ERROR=35,

-    BUS3_TOO_MANY_BUS_ERRORS=36,

-    BUS4_SPARE_DEPLOYED=41,

-    BUS4_MAX_SPARES_EXCEEDED=42,

-    BUS4_RECALIBRATION_ERROR=43,

-    BUS4_TOO_MANY_BUS_ERRORS=44,                                              

-};

-const char * const fir1_reg[16] = {"RX_PG_FIR_ERR_PG_REGS",

-                                            "RX_PG_FIR_ERR_GCR_BUFF",

-                                            "RESERVED_FIR",

-                                            "RX_PG_FIR_ERR_GCRS_LD_SM",

-                                            "RX_PG_FIR_ERR_GCRS_UNLD_SM",

-                                            "RX_PG_FIR_ERR_GLB_INIT_SND_MSG_SM",  

-                                            "RX_PG_FIR_ERR_MAIN_INIT_SM",  

-                                            "RX_PG_FIR_ERR_WTM_SM",

-                                            "RX_PG_FIR_ERR_WTR_SM",

-                                            "RX_PG_FIR_ERR_WTL_SM",

-                                            "RX_PG_FIR_ERR_RPR_SM",

-                                            "RX_PG_FIR_ERR_EYEOPT_SM",

-                                            "RX_PG_FIR_ERR_DSM_SM",

-                                            "RX_PG_FIR_ERR_RXDSM_SM",

-                                            "RX_PG_CHAN_FAIL_RSVD",

-                                            "RX_PL_FIR_ERR"};

-                                            

-

-const char * const fir2_reg[16] = {"RX_PG_FIR_ERR_DYN_RPR_SM",

-                                            "RX_PG_FIR_ERR_SLS_HNDSHK_SM",

-                                            "RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM",

-                                            "RX_PG_FIR_ERR_RECAL_SM",

-                                            "RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM",

-                                            "RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM",

-                                            "RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR",

-                                            "RESERVED_FIR"};

-

-extern "C"

-{

-

-/**

- * io_clear_firs HWP 

- *

- * target is any IO target P8 MCS,XBUS,Abus or centaur

- * 

- * 

- *

- * 

- */

-

-fapi::ReturnCode io_clear_firs(const fapi::Target &target);

-

-fapi::ReturnCode clear_fir_err_regs(const Target &target,io_interface_t chip_interface,uint32_t group);

-

-fapi::ReturnCode clear_fir_reg(const Target &target,fir_io_interface_t chip_interface);
-
-fapi::ReturnCode clear_fir_mask_reg(const Target &target,fir_io_interface_t chip_interface);

-

+                                                  0x02010404  };
+                                                  
+
+enum fir_error_type{
+    RX_PARITY,
+    TX_PARITY,
+    GCR_HANG_ERROR,
+    BUS0_SPARE_DEPLOYED=9,
+    BUS0_MAX_SPARES_EXCEEDED=10,
+    BUS0_RECALIBRATION_ERROR=11,
+    BUS0_TOO_MANY_BUS_ERRORS=12,
+    BUS1_SPARE_DEPLOYED=17,
+    BUS1_MAX_SPARES_EXCEEDED=18,
+    BUS1_RECALIBRATION_ERROR=19,
+    BUS1_TOO_MANY_BUS_ERRORS=20,
+    BUS2_SPARE_DEPLOYED=25,
+    BUS2_MAX_SPARES_EXCEEDED=26,
+    BUS2_RECALIBRATION_ERROR=27,
+    BUS2_TOO_MANY_BUS_ERRORS=28,
+    BUS3_SPARE_DEPLOYED=33,
+    BUS3_MAX_SPARES_EXCEEDED=34,
+    BUS3_RECALIBRATION_ERROR=35,
+    BUS3_TOO_MANY_BUS_ERRORS=36,
+    BUS4_SPARE_DEPLOYED=41,
+    BUS4_MAX_SPARES_EXCEEDED=42,
+    BUS4_RECALIBRATION_ERROR=43,
+    BUS4_TOO_MANY_BUS_ERRORS=44,                                              
+};
+const char * const fir1_reg[16] = {"RX_PG_FIR_ERR_PG_REGS",
+                                            "RX_PG_FIR_ERR_GCR_BUFF",
+                                            "RESERVED_FIR",
+                                            "RX_PG_FIR_ERR_GCRS_LD_SM",
+                                            "RX_PG_FIR_ERR_GCRS_UNLD_SM",
+                                            "RX_PG_FIR_ERR_GLB_INIT_SND_MSG_SM",  
+                                            "RX_PG_FIR_ERR_MAIN_INIT_SM",  
+                                            "RX_PG_FIR_ERR_WTM_SM",
+                                            "RX_PG_FIR_ERR_WTR_SM",
+                                            "RX_PG_FIR_ERR_WTL_SM",
+                                            "RX_PG_FIR_ERR_RPR_SM",
+                                            "RX_PG_FIR_ERR_EYEOPT_SM",
+                                            "RX_PG_FIR_ERR_DSM_SM",
+                                            "RX_PG_FIR_ERR_RXDSM_SM",
+                                            "RX_PG_CHAN_FAIL_RSVD",
+                                            "RX_PL_FIR_ERR"};
+                                            
+
+const char * const fir2_reg[16] = {"RX_PG_FIR_ERR_DYN_RPR_SM",
+                                            "RX_PG_FIR_ERR_SLS_HNDSHK_SM",
+                                            "RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM",
+                                            "RX_PG_FIR_ERR_RECAL_SM",
+                                            "RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM",
+                                            "RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM",
+                                            "RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR",
+                                            "RESERVED_FIR"};
+
+extern "C"
+{
+
+/**
+ * io_clear_firs HWP 
+ *
+ * target is any IO target P8 MCS,XBUS,Abus or centaur
+ * 
+ * 
+ *
+ * 
+ */
+
+fapi::ReturnCode io_clear_firs(const fapi::Target &target);
+
+fapi::ReturnCode clear_fir_err_regs(const Target &target,io_interface_t chip_interface,uint32_t group);
+
 fapi::ReturnCode read_fir_reg(const Target &target,fir_io_interface_t chip_interface,ecmdDataBufferBase &databuf_64bit);
 
-

-

-

-    

-} // extern "C"

-#endif // CLEAR_IO_FIRS_H_

-

+
+
+
+    
+} // extern "C"
+#endif // CLEAR_IO_FIRS_H_
+
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
index 99a123b2c..7a50b4d70 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.C,v 1.16 2013/02/07 10:07:28 varkeykv Exp $
+// $Id: io_funcs.C,v 1.17 2013/03/20 10:47:08 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -45,21 +45,23 @@
 //------------------------------------------------------------------------------
 #include "io_funcs.H"
 
+
 extern "C"
 {
     using namespace fapi;
+    
 
 /****************************************************************************************/
 /* edi_training.C   - functions of edi_training class                                */
 /****************************************************************************************/
 
-
 //! Wrapper to Run W,D,E,R , F based on bus_status (selected on);
 ReturnCode  edi_training::run_training(const Target& master_target,  io_interface_t master_interface,uint32_t master_group, const Target&  slave_target,  io_interface_t  slave_interface,uint32_t slave_group) {
     ReturnCode rc;
     // bool master_chip_found=false; -- maybe for fabric ...need to test later
 	
 	FAPI_DBG("io_run_training: Starting training on SLAVE side");
+
 	// Set the slave rx_start_wderf
         rc=run_training_functions(slave_target,slave_interface,slave_group);
 	if (!rc.ok())  {
@@ -90,7 +92,6 @@ ReturnCode  edi_training::run_training(const Target& master_target,  io_interfac
 			}
 		    }
 		 }
-
         }
     return(rc);
 }
@@ -243,7 +244,6 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                        FAPI_ERR("io_run_training: the wiretest training state reported a fail  \n");
 				       FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
-				       //fapiLogError(rc);
                                        wire_test_status =  FAILED ;
                                        rx_wderf_failed[WIRE_TEST]=true;
                                       // Run First FAILED Data Capture for Wire Test for FAILED bus
@@ -272,7 +272,6 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                             rx_wderf_failed[DESKEW]=true;
                                             FAPI_ERR("io_run_training : deskew training state reported a fail  \n");
                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
-					    //fapiLogError(rc);
                                             desckew_status =  FAILED ;
 					    break;
                                     }
@@ -296,7 +295,6 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                              FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n");
                                              FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
-					     //fapiLogError(rc);
                                              rx_wderf_failed[EYE_OPT]=true;
                                              eye_opt_status =  FAILED ;
 					     break;
@@ -321,8 +319,6 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                     {
                                              FAPI_DBG("io_run_training: static repair encountered an error    \n");
                                              rx_wderf_failed[REPAIR]=true;
-                                             FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_REPAIR_RC);
-					     //fapiLogError(rc);
                                              repair_status =  FAILED ;
 					     break;
                                     }
@@ -349,7 +345,6 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                              FAPI_DBG("io_run_training:   rx_func_mode_failed    \n");
                                              rx_wderf_failed[FUNCTIONAL]=true;
                                              FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
-					     //fapiLogError(rc);
                                              functional_status =   FAILED ;
 					     break;
                                     }
@@ -370,7 +365,8 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                         curr_cyc++;
                         FAPI_DBG("\n\t io_run_training: Cycles into polling = %lld\n", curr_cyc);
                         FAPI_DBG("\n\t io_run_training: Cycles remaining in polling = %lld\n", end_cycle - curr_cyc );
-			// Updated Loop count and per delay call count to acheive max of 100ms theoretical delay as per Mike Spear 
+			// Updated Loop count and per delay call count to acheive max of 100ms theoretical delay as per Mike Spear
+			// This is 1ms poll call..Loop counter =100 .. a total of ~100ms
                         rc=fapiDelay(1000000,increment_poll_cycles);
                         if(!rc.ok())
                         {
@@ -384,9 +380,6 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                      break;
                     }
                     
-                    //@thi - Display loop count
-                    FAPI_INF("io_run_training: curr_cyc = %lld\n", curr_cyc);
-                    
                     if ( curr_cyc >= end_cycle )
                     {
                             dump_ffdc_wiretest(master_chip_target, master_chip_interface ,master_group,  slave_chip_target ,  slave_chip_interface,slave_group);
@@ -395,31 +388,26 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
 			    {
 			    FAPI_ERR("io_run_training: wiretest timeout");
 			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_WIRETEST_TIMEOUT_RC);
-			    //fapiLogError(rc);
 			    }
 			    else if (desckew_selected && desckew_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: deskew timeout");
 			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_DESKEW_TIMEOUT_RC);
-			   // fapiLogError(rc);
 			    }
 			    else if (repair_selected && repair_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: repair timeout");
 			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_REPAIR_TIMEOUT_RC);
-			   // fapiLogError(rc);
 			    }
 			    else if (eye_opt_selected && eye_opt_status == RUNNING)
 			    {
 			    FAPI_ERR("io_run_training: eyeopt timeout");
 			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_EYE_OPT_TIMEOUT_RC);
-			    //fapiLogError(rc);
 			    }
 			    else
 			    {
 			    FAPI_ERR("io_run_training: func timeout");
 			    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FUNC_MODE_TIMEOUT_RC);
-			    //fapiLogError(rc);
 			    }
 			    break;
                     }
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H
index 0034d6485..5977d84b7 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.H,v 1.14 2013/02/12 06:25:32 varkeykv Exp $
+// $Id: io_funcs.H,v 1.15 2013/03/20 10:47:08 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -49,6 +49,7 @@
 #define IO_funcs
 #include <fapi.H>
 #include "gcr_funcs.H"
+#include "io_clear_firs.H"
 
 using namespace fapi;
 	// Bus Status State
@@ -75,10 +76,7 @@ public:
 	bus_status    eye_opt_status;
 	bus_status    repair_status;
 	bus_status    functional_status;
-       //@thi - Pete & Varkey will release a new version that has max_poll_cycles = 300.
-       //       Because we need this in a build quickly, I go ahead and temporarily
-       //       change it here in this version.
-        //Updating max cycles to suit 300ms theoretical max timeout as per Mike Spear
+        //Updating max cycles to suit 280ms theoretical max timeout as per Mike Spear
 	static const uint32_t      max_poll_cycles=300;
 	static const uint32_t      increment_poll_cycles=1;
 	uint32_t endpoints_set; // How many end points have we accessed so far
@@ -147,6 +145,7 @@ public:
     ReturnCode isChipMaster(const Target& target, io_interface_t interface,uint32_t current_group,
                             bool& master_chip_found
                             );
+        
 };
 
 
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
index e6b92d869..f290a5e9a 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
@@ -20,8 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-/// $Id: proc_cen_framelock.C,v 1.11 2013/01/28 03:31:02 baysah Exp $
-
+/// $Id: proc_cen_framelock.C,v 1.12 2013/03/14 04:10:28 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
 //------------------------------------------------------------------------------
 // *|
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
index a236f9207..da63f3081 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_dmi_scominit.C,v 1.3 2013/01/24 20:20:34 thomsen Exp $
+// $Id: proc_dmi_scominit.C,v 1.5 2013/02/11 03:58:59 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -39,10 +39,12 @@
 //------------------------------------------------------------------------------
 //  Version		Date		Owner		Description
 //------------------------------------------------------------------------------
+//    1.5	   	02/06/13	jmcgill		Change passed targets in order to match scominit file updates.
+//    1.4	   	02/04/13	thomsen		Fixed informational print to not say Error
 //    1.3	   	01/23/13	thomsen		Added separate calls to base & customized scominit files. Removed separate calls to SIM vs. HW scominit files
 //    1.2	   	01/10/13	thomsen		Added separate calls to SIM vs. HW scominit files
 //   									Added commented-out call to OVERRIDE initfile for system/bus/lane specific inits
-//                                      Changed passed targets in order to match scominit file updates. 
+//                                      Changed passed targets in order to match scominit file updates.
 //                                      CO-REQs required: p8.dmi.vbu.scom.initfile v1.1 and p8.dmi.hw.scom.initfile v1.1
 //    1.1       8/11/12     jmcgill		Initial release
 //------------------------------------------------------------------------------
@@ -63,7 +65,6 @@ extern "C" {
 fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
 {
     fapi::ReturnCode rc;
-    //fapi::TargetType target_type;
     fapi::Target i_this_pu_target;
     std::vector<fapi::Target> targets;
 
@@ -72,22 +73,20 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
 
     do
     {
-  
+
 	    // Get parent chip target
         rc = fapiGetParentChip(i_target, i_this_pu_target); if(rc) return rc;
 
-		// populate targets vector (i_this_pu_target=proc target, i_target=chiplet target)
-        targets.push_back(i_this_pu_target); 
+		// populate targets vector (i_target=chiplet target)
         targets.push_back(i_target);
 
-        // processor target, processor MCS chiplet target
-        // test target types to confirm correct before calling initfile(s) to execute
-        if ((i_this_pu_target.getType() == fapi::TARGET_TYPE_PROC_CHIP)   &&
-            (i_target.getType()         == fapi::TARGET_TYPE_MCS_CHIPLET))
+        // processor MCS chiplet target
+        // test target type to confirm correct before calling initfile(s) to execute
+        if (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
         {
 		    // Call BASE DMI SCOMINIT
-            FAPI_INF("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s & %s",
-                  MCS_DMI_BASE_IF, i_this_pu_target.toEcmdString(), i_target.toEcmdString());
+            FAPI_INF("proc_dmi_scominit: fapiHwpExecInitfile executing %s on %s",
+                     MCS_DMI_BASE_IF, i_target.toEcmdString());
             FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_BASE_IF);
             if (!rc.ok())
             {
@@ -96,8 +95,8 @@ fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
                 break;
             }
 		    // Call CUSTOMIZED DMI SCOMINIT (system specific)
-            FAPI_INF("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s & %s",
-                  MCS_DMI_CUSTOM_IF, i_this_pu_target.toEcmdString(), i_target.toEcmdString());
+            FAPI_INF("proc_dmi_scominit: fapiHwpExecInitfile executing %s on %s",
+                     MCS_DMI_CUSTOM_IF, i_target.toEcmdString());
             FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_CUSTOM_IF);
             if (!rc.ok())
             {
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
index 11961b81c..0139bdf55 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.C,v 1.8 2012/12/11 23:59:28 jmcgill Exp $
+// $Id: proc_setup_bars.C,v 1.9 2013/03/17 22:56:03 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -2421,7 +2421,6 @@ proc_setup_bars_write_local_chip_region_bars(
         }
 
         // MCD (non-mirrored)
-        // TODO: potential optimization if DSMP links are known to be disabled?
         if (i_smp_chip.non_mirrored_range.enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 0 (Non-Mirrored) register");
@@ -2438,7 +2437,6 @@ proc_setup_bars_write_local_chip_region_bars(
         }
 
         // MCD (mirrored)
-        // TODO: potential optimization if DSMP links are known to be disabled?
         if (i_smp_chip.mirrored_range.enabled)
         {
             FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 1 (Mirrored) register");
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
index 494210403..fc1b68da7 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.H,v 1.4 2012/12/11 23:59:31 jmcgill Exp $
+// $Id: proc_setup_bars.H,v 1.5 2013/03/17 22:56:07 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -905,7 +905,6 @@ const proc_setup_bars_bar_reg_def mcd_f1_bar_reg_def =
 };
 
 // PCIe BAR constants
-// TODO: investigate development of PCIe chip unit support
 const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
 {
     PCIE0_NODAL_BAR0_0x02012010,
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 44734b1c8..4a7790ca4 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_scom_addresses.H,v 1.49 2013/01/24 00:56:27 jdsloat Exp $
+// $Id: cen_scom_addresses.H,v 1.54 2013/03/08 23:25:10 jdsloat Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,10 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.53   | jdsloat  |08-Mar-13| Added MBA01_MBARPC0Q_0x03010434
+//  1.52   | jdsloat  |27-Feb-13| Fixed additional typos in READ TIMING REF
+//  1.51   | sglancy  |27-Feb-13| Fixed typos in READ TIMING REF
+//  1.50   | jdsloat  |27-Feb-13| Added READ TIMING REFERENCE REGS
 //  1.49   | jdsloat  |23-Jan-13| Added PC_RANK_GROUP and PC_RANK_GROUP_EXT
 //  1.48   | jdsloat  |09-Jan-13| Fixed typos.  Excuse me.
 //  1.47   | jdsloat  |09-Jan-13| Added DQS READ Phase select regs for RP 1-3
@@ -68,7 +72,7 @@
 //  1.41   | gollub   |26-Oct-12| Added MBECCFIR AND/OR MASK registers
 //         |          |         | Added MBSPA AND/OR MASK registers
 //  1.38   | pardeik  |31-Oct-12| Added N/M Throttling Control Register
-//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers 
+//  1.37   | aditya   |26-Oct-12| Added MCBIST Random Data Seed Registers
 //  1.36   | menlowuu |25-Oct-12| Added PHY port 1 disable bit registers
 //  1.35   | menlowuu |25-Oct-12| Added PHY disable bit registers
 //  1.34   | aditya   |12-Oct-12| Added MCBIST and DPHY registers
@@ -670,6 +674,11 @@ CONST_UINT64_T( MBA01_MBA_ERR_REPORTQ_0x0301041A     , ULL(0x0301041A) );
 CONST_UINT64_T( MBA01_MBA_WRD_MODE_0x03010449           , ULL(0x03010449) );
 
 
+//------------------------------------------------------------------------------
+//      MBA Power Control Register
+//------------------------------------------------------------------------------
+CONST_UINT64_T( MBA01_MBARPC0Q_0x03010434		,ULL(0x03010434) );
+
 
 
 
@@ -1079,7 +1088,7 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,	           ULL(0x8001087A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,	           ULL(0x80010C7A0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,	           ULL(0x8001107A0301143F) );
-                                                                                       
+
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,	           ULL(0x8000007B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,	           ULL(0x8000047B0301143F) );
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,	           ULL(0x8000087B0301143F) );
@@ -1320,6 +1329,34 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F0
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F , ULL(0x800113090301143F) );
 
 //------------------------------------------------------------------------------
+//     READ TIMING REFERENCE REGS
+//------------------------------------------------------------------------------
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F , ULL(0x800000700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F , ULL(0x800004700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F , ULL(0x800008700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F , ULL(0x80000C700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F , ULL(0x800010700301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F , ULL(0x800000710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F , ULL(0x800004710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F , ULL(0x800008710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F , ULL(0x80000C710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F , ULL(0x800010710301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F , ULL(0x800100700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F , ULL(0x800104700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F , ULL(0x800108700301143F	) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F , ULL(0x80010C700301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F , ULL(0x800110700301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F , ULL(0x800100710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F , ULL(0x800104710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F , ULL(0x800108710301143F	) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F , ULL(0x80010C710301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F , ULL(0x800110710301143F) );
+
+
+//------------------------------------------------------------------------------
 //     DQS Gate Delay Rank Pair 0
 //------------------------------------------------------------------------------
 CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F , ULL(0x800000130301143F) );
@@ -1361,7 +1398,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD1Q_0x02011782  , ULL(0x02011782) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD2Q_0x02011783  , ULL(0x02011783) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD3Q_0x02011784  , ULL(0x02011784) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD4Q_0x02011785  , ULL(0x02011785) );
-CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) ); 
+CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD5Q_0x02011786  , ULL(0x02011786) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD6Q_0x02011787  , ULL(0x02011787) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFD7Q_0x02011788  , ULL(0x02011788) );
 CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDQ_0x02011789   , ULL(0x02011789) );
@@ -1371,7 +1408,7 @@ CONST_UINT64_T( MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A , ULL(0x0201178A) );
 //------------------------------------------------------------------------------
 
 CONST_UINT64_T( MBA01_CCS_MODEQ_0x030106a7       		, ULL(0x030106a7) );
-CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc	, ULL(0x030106dc) );
 //------------------------------------------------------------------------------
 //     MBA MCBIST Configuration Register
 //------------------------------------------------------------------------------
@@ -1381,39 +1418,39 @@ CONST_UINT64_T( MBA01_MCBIST_MCBCFGQ_0x030106e0  		, ULL(0x030106e0) );
 //     MBS Error Map Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) ); 
-CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) ); 
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA1Q_0x0201166a 		, ULL(0x0201166a) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA2Q_0x0201166b 		, ULL(0x0201166b) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMA3Q_0x0201166c 		, ULL(0x0201166c) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB1Q_0x0201166d 		, ULL(0x0201166d) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB2Q_0x0201166e 		, ULL(0x0201166e) );
+CONST_UINT64_T( MBS_MCBIST01_MCBEMB3Q_0x0201166f 		, ULL(0x0201166f) );
 //------------------------------------------------------------------------------
 //     MBA MCBIST Memory Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) ); 
-CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBMR0Q_0x030106a8  		, ULL(0x030106a8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR1Q_0x030106a9  		, ULL(0x030106a9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR2Q_0x030106aa  		, ULL(0x030106aa) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR3Q_0x030106ab  		, ULL(0x030106ab) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR4Q_0x030106ac  		, ULL(0x030106ac) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR5Q_0x030106ad  		, ULL(0x030106ad) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR6Q_0x030106ae  		, ULL(0x030106ae) );
+CONST_UINT64_T( MBA01_MCBIST_MCBMR7Q_0x030106df  		, ULL(0x030106df) );
+CONST_UINT64_T( MBA01_MCBIST_RUNTIMECTRQ_0x030106b0		, ULL(0x030106b0) );
 //------------------------------------------------------------------------------
 //     MBA Fixed Data Seed Registers
 
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBA01_MCBIST_MCBFD0Q_0x030106be  		, ULL(0x030106be) );
-CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );         
-CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBFD1Q_0x030106bf  		, ULL(0x030106bf) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD2Q_0x030106c0  		, ULL(0x030106c0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD3Q_0x030106c1  		, ULL(0x030106c1) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD4Q_0x030106c2  		, ULL(0x030106c2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD5Q_0x030106c3  		, ULL(0x030106c3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD6Q_0x030106c4  		, ULL(0x030106c4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFD7Q_0x030106c5  		, ULL(0x030106c5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFDQ_0x030106c6   		, ULL(0x030106c6) );
+CONST_UINT64_T( MBA01_MCBIST_MCBFDSPQ_0x030106c7 		, ULL(0x030106c7) );
 //------------------------------------------------------------------------------
 //     MBA Data Rotate Configuration Register
 
@@ -1425,7 +1462,7 @@ CONST_UINT64_T( MBA01_MCBIST_MCBDRCRQ_0x030106bd 		, ULL(0x030106bd) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( MBS_MCBIST01_MCBCMA1Q_0x02011672 		, ULL(0x02011672) );
 
-CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );      
+CONST_UINT64_T( MBS_MCBIST01_MCBCMB1Q_0x02011673 		, ULL(0x02011673) );
 CONST_UINT64_T( MBS_MCBIST01_MCBCMABQ_0x02011674 		, ULL(0x02011674) );
 //------------------------------------------------------------------------------
 //    MBA MCBIST Control Register
@@ -1436,60 +1473,60 @@ CONST_UINT64_T( MBA01_MCBIST_MCB_CNTLQ_0x030106db		, ULL(0x030106db) );
 //    MBA MCBIST Memory Parameter Register
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBPARMQ_0x030106af 		, ULL(0x030106af) );
 //------------------------------------------------------------------------------
 //    MBA Address Map Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );      
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );    
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );       
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) ); 
-      
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );  
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) ); 
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );  
-CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );   
-
-CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) ); 
-  
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );   
-CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) ); 
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A0Q_0x030106c8, ULL(0x030106c8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A0Q_0x030106c9, ULL(0x030106c9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A0Q_0x030106ca, ULL(0x030106ca) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A0Q_0x030106cb, ULL(0x030106cb) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR0A1Q_0x030106d7, ULL(0x030106d7) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR1A1Q_0x030106d8, ULL(0x030106d8) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR2A1Q_0x030106d9, ULL(0x030106d9) );
+CONST_UINT64_T( MBA01_MCBIST_MCBAMR3A1Q_0x030106da, ULL(0x030106da) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA0Q_0x030106d4, ULL(0x030106d4) );
+CONST_UINT64_T( MBA01_MCBIST_MCBLFSRA1Q_0x030106d5, ULL(0x030106d5) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA0Q_0x030106d2, ULL(0x030106d2) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSEARA1Q_0x030106d3, ULL(0x030106d3) );
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA0Q_0x030106cc, ULL(0x030106cc) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBRSARA1Q_0x030106cd, ULL(0x030106cd) );
+
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA0Q_0x030106ce, ULL(0x030106ce) );
+CONST_UINT64_T( MBA01_MCBIST_MCBREARA1Q_0x030106cf, ULL(0x030106cf) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA0Q_0x030106d0, ULL(0x030106d0) );
+CONST_UINT64_T( MBA01_MCBIST_MCBSSARA1Q_0x030106d1, ULL(0x030106d1) );
 CONST_UINT64_T( MBA01_MCBIST_MCBAGRAQ_0x030106d6  , ULL(0x030106d6) );
 //------------------------------------------------------------------------------
 //    MBA Performance monitor  Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );  
+CONST_UINT64_T( MBA01_MBA_PMU0Q_0x03010437        , ULL(0x03010437) );
 //------------------------------------------------------------------------------
 //    MBA Maintenance Buffer Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );   
-CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );   
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA1Q_0x02011664, ULL(0x02011664) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTA2Q_0x02011665, ULL(0x02011665) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB1Q_0x02011667, ULL(0x02011667) );
+CONST_UINT64_T( MBS_MCBIST01_MCB_ERRCNTB2Q_0x02011668, ULL(0x02011668) );
 //------------------------------------------------------------------------------
 //    DPHY01 PC Rank Pair Registers
 
 //------------------------------------------------------------------------------
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );   
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) ); 
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) ); 
-CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) ); 
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P0, ULL(0x8000c0020301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR0_P1, ULL(0x8001c0020301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P0, ULL(0x8000c0030301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR1_P1, ULL(0x8001c0030301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P0, ULL(0x8000c0300301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR2_P1, ULL(0x8001c0300301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P0, ULL(0x8000c0310301143f) );
+CONST_UINT64_T( DPHY01_DDRPHY_PC_RANK_PAIR3_P1, ULL(0x8001c0310301143f) );
 //------------------------------------------------------------------------------
 //    MCBIST Random Data Seed Registers
 
@@ -1520,6 +1557,12 @@ CONST_UINT64_T( MBA01_MBA_FARB3Q_0x03010416, ULL(0x03010416) );
 //*********  ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/
 //******************************************************************************/
 // moved to common_scom_addresses.H       1/24/2010   mfred
+CONST_UINT64_T( CEN_SCAN_CLK_PLL,                   ULL(0x08100E0000000000) );
+CONST_UINT64_T( CEN_SCAN_PLL_GPTR,                  ULL(0x0810020000000000) );
+CONST_UINT64_T( CEN_SCAN_PLL_BNDY_FUNC,             ULL(0x0810080800000000) );
+
+CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
+CONST_UINT64_T( SCAN_GPTR_TIME_REP_NO_PLL,          ULL(0x0FE0023000000000) );
 
 #endif
 
@@ -1530,6 +1573,22 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: cen_scom_addresses.H,v $
+Revision 1.54  2013/03/08 23:25:10  jdsloat
+added MBA01_MBARPC0Q_0x03010434
+
+Revision 1.53  2013/03/07 17:01:39  gweber
+added centaur-only SCAN_ constants
+
+Revision 1.52  2013/02/27 20:36:18  jdsloat
+
+Fixed additional typos in READ TIMING REF
+
+Revision 1.51  2013/02/27 19:03:22  lapietra
+Fixed typos
+
+Revision 1.50  2013/02/27 16:43:31  jdsloat
+Added READ TIMING REFERENCE REGS
+
 Revision 1.49  2013/01/24 00:56:27  jdsloat
 Added PC_RANK_GROUP and PC_RANK_GROUP_EXT
 
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index 5566ba5f4..709301edc 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: common_scom_addresses.H,v 1.40 2013/01/08 18:24:16 koenig Exp $
+// $Id: common_scom_addresses.H,v 1.44 2013/03/18 19:43:27 jeshua Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -133,6 +133,7 @@ CONST_UINT64_T( GENERIC_CLK_SYNC_CONFIG_0x00030000    , ULL(0x00030000) );
 CONST_UINT64_T( GENERIC_CLK_REGION_0x00030006         , ULL(0x00030006) );
 CONST_UINT64_T( GENERIC_CLK_SCANSEL_0x00030007        , ULL(0x00030007) );
 CONST_UINT64_T( GENERIC_CLK_STATUS_0x00030008         , ULL(0x00030008) );
+CONST_UINT64_T( GENERIC_CLK_ERROR_0x00030009          , ULL(0x00030009) );
 CONST_UINT64_T( GENERIC_CLK_SCANDATA0_0x00038000      , ULL(0x00038000) );
 CONST_UINT64_T( GENERIC_CLK_SCAN_UPDATEDR_0x0003A000  , ULL(0x0003A000) );
 CONST_UINT64_T( GENERIC_CLK_SCAN_CAPTUREDR_0x0003C000 , ULL(0x0003C000) );
@@ -225,8 +226,6 @@ CONST_UINT32_T( CFAM_FSI_SBE_VITAL_0x0000281C         , ULL(0x0000281C) );
 //------------------------------------------------------------------------------
 CONST_UINT64_T( OTPROM_0x00010000                     , ULL(0x00010000) );
 
-CONST_UINT64_T( OTPROM_SECURE_SWITCHES_0x00010005     , ULL(0x00010005) );
-
 //------------------------------------------------------------------------------
 //      PIBMEM
 //------------------------------------------------------------------------------
@@ -596,7 +595,6 @@ CONST_UINT64_T( SCAN_ALLSCANEXVITAL,                ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALLSCANEXPRV,                  ULL(0x0FF00DCE00000000) );  // Looking to be deprecated
 CONST_UINT64_T( SCAN_ALL_BUT_GPTRTIMEREP,           ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALL_BUT_VITALDPLLGPTRTIME,     ULL(0x0FE00DCE00000000) );
-CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
 CONST_UINT64_T( SCAN_GPTR_TIME_REP,                 ULL(0x0FF0023000000000) );
 CONST_UINT64_T( SCAN_PLL_GPTR,                      ULL(0x0010020000000000) );
 CONST_UINT64_T( SCAN_PLL_BNDY_FUNC,                 ULL(0x0010080800000000) );
@@ -636,6 +634,18 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.44  2013/03/18 19:43:27  jeshua
+Removed OTPROM_SECURE_SWITCHES_0x00010005 because it's not common between P8 and Centaur. P8 code should use OTPC_M_SECURITY_SWITCH_0x00010005
+
+Revision 1.43  2013/03/07 17:02:58  gweber
+moved centaur-only SCAN_ constants to cen_scom_addresses.H
+
+Revision 1.42  2013/03/06 12:43:59  gweber
+Set CLOCK_REGION_PERV for scan0 perv
+
+Revision 1.41  2013/02/20 17:44:46  cmolsen
+Added CC error reg 30009.
+
 Revision 1.40  2013/01/08 18:24:16  koenig
 Updates - AK
 
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index 6c6012d62..ca8d10265 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.139 2013/03/17 22:07:53 jmcgill Exp $
+// $Id: p8_scom_addresses.H,v 1.140 2013/03/21 13:50:57 pchatnah Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -862,7 +862,7 @@ CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C75         , ULL(0x02010C75) );
 //------------------------------------------------------------------------------
 // PLL lock information
 CONST_UINT64_T( PB_PLLLOCKREG_0x020F0019              , ULL(0x020F0019) );
-
+CONST_UINT64_T( PCBMS_INTERRUPT_TYPE_REG_0x000F001A ,   ULL(0x000F001A));
 //------------------------------------------------------------------------------
 //      CAPP
 //------------------------------------------------------------------------------
@@ -1824,6 +1824,9 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.140  2013/03/21 13:50:57  pchatnah
+ading checkstop register
+
 Revision 1.139  2013/03/17 22:07:53  jmcgill
 add L3 BAR registers
 
diff --git a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile
index 6ad2fb3f6..d816f15d8 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.as.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.as.scom.initfile,v 1.3 2013/01/16 20:26:34 irish Exp $
+#-- $Id: p8.as.scom.initfile,v 1.5 2013/03/19 14:16:52 mikos Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2013
@@ -67,7 +67,7 @@ scom 0x020130FE {
 #-- AS EG Config Register (0x020130F2)
 scom 0x020130F2 {
     bits  ,  scom_data      ;
-    0     ,  0b1            ;  #-- EG enable (ON)
+    0     ,  0b0            ;  #-- EG disable (OFF)
     1     ,  0b0            ;  #-- page migration mode  (OFF)
     2:3   ,  0b00           ;  #-- credwt pref level (0)
     4     ,  0b0            ;  #-- relaxed DMA ordering (OFF)
@@ -126,5 +126,5 @@ scom 0x020130C7                                  {
 #--- Mask
 scom 0x020130C3                                  {
     scom_data        ;
-    0x60BD600DEF7FFFFF             ;
+    0x60BD600DEF600000             ;
     }
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
index c574d6a69..4a4932786 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.custom.scom.initfile
@@ -1,19 +1,26 @@
-#-- $Id: p8.dmi.custom.scom.initfile,v 1.2 2013/01/24 23:46:35 thomsen Exp $
+#-- $Id: p8.dmi.custom.scom.initfile,v 1.7 2013/03/15 21:19:29 thomsen Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
-#--     1.2 |thomsen |01/24/13|Fixed tx_msbswap for groups 1,2,3
+#--     1.7 |jgrell  |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab.
+#--     1.6 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
+#--     1.5 |thomsen |02/12/13|Added Lane Power Ups and Clock Invert
+#--     1.4 |jmcgill |02/09/13|Use chiplet level targeting, reference attributes
+#--     1.3 |thomsen |02/01/13|Fixed tx_msbswap for groups 1,2,3
+#--     1.2 |berger  |02/01/13|Removed a handful of settings already in the base file, added sim attr for MSB swap and lane invert
 #--     1.1 |thomsen |01/23/13|Created initial version
 #-- --------|--------|--------|--------------------------------------------------
 #--------------------------------------------------------------------------------
 # End of revision history
 #--------------------------------------------------------------------------------
+#-- TARGETS:
+#-- SYS. Chiplet target
+#-- TGT1. Proc target
+#-- TGT2. Connected Chiplet target
+#-- TGT3. Connected Proc target
 
-#--Master list of variables that can be used in this file is at:
-#--<Attribute Definition Location>
-
-#-- TGT1.ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in
+#--  ATTR_CHIP_UNIT_POS is the MCS unit number (0-7 on Venice, 4-7 on Murano) and corresponds to the scom address translation done in
 #--  the p8.chipunit.scominfo file. It is used to be able to select a specific clock group number.
 #--  Chip     UNIT_POS  DMI_UNIT  CLOCKGRP
 #--  ----     --------  --------  --------
@@ -24,527 +31,262 @@
 
 SyntaxVersion = 1
 
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
 #--
 #-- Includes
 #-- Note:  Must include the path to the .define file.
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
+#--
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+
 include edi.io.define
 
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
 #--
 #-- Defines
 #--
-#-- -----------------------------------------------------------------------------
-#--******************************************************************************
-#-- -----------------------------------------------------------------------------
-
-# ./iotk put rx_fence=1
-# 0x
-scom 0x800.0b(rx_fence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_fence,                 0b1;
-}
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
 
-# ./iotk put rx_c4_sel=00
-# ./iotk put rx_prot_speed_slct=1
-# 0x8009C00002011E3F 
-scom 0x800.0b(rx_misc_analog_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_c4_sel,                0b00;
-rx_prot_speed_slct,       0b1;
-}
-# ./iotk put rx_servo_timeout_sel_D=1001
-# 0x800B600002011E3F 
-scom 0x800.0b(rx_servo_to1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_servo_timeout_sel_d,   0b1001;
-}
-# ./iotk put rx_servo_timeout_sel_H=1110
-# 0x800B680002011E3F 
-scom 0x800.0b(rx_servo_to2_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_servo_timeout_sel_h,   0b1110;
-}
-# ./iotk put rx_servo_timeout_sel_I=1011
-# ./iotk put rx_servo_timeout_sel_J=1100
-# 0x800B700002011E3F 
-scom 0x800.0b(rx_servo_to3_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_servo_timeout_sel_i,   0b1011;
-rx_servo_timeout_sel_j,   0b1100;
-rx_servo_timeout_sel_k,   0b1101;
-}
-# ./iotk put rx_wt_timeout_sel=111
-# ./iotk put rx_ds_bl_timeout_sel=101
-# ./iotk put rx_ds_timeout_sel=110
-#./iotk put rx_sls_timeout_sel=111
-# 0x8008980002011E3F 
-scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_wt_timeout_sel,        0b111;
-rx_ds_bl_timeout_sel,     0b101;
-rx_ds_timeout_sel,        0b110;
-rx_sls_timeout_sel,       0b001;
-}
+define def_IS_HW  = (SYS.ATTR_IS_SIMULATION == 0);
+define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1);
 
-# ./iotk put rx_bit_lock_timeout_sel=110
-# 0x800B080002011E3F 
-scom 0x800.0b(rx_mode1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_bit_lock_timeout_sel,  0b110;
-}
-# ./iotk put rx_eo_offset_timeout_sel=111
-# ./iotk put rx_eo_amp_timeout_sel=111
-# ./iotk put rx_eo_ctle_timeout_sel=111
-# ./iotk put rx_eo_h1ap_timeout_sel=111
-# ./iotk put rx_eo_ddc_timeout_sel=111
-# 0x8009100002011E3F 
-scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-rx_eo_offset_timeout_sel, 0b111;
-rx_eo_amp_timeout_sel,    0b111;
-rx_eo_ctle_timeout_sel,   0b111;
-rx_eo_h1ap_timeout_sel,   0b111;
-rx_eo_ddc_timeout_sel,    0b111;
-}
+define def_all_lanes=11111;
 
-#./iotk put tx_zcal_sm_min_val=0010101
-#./iotk put tx_zcal_sm_max_val=1000110
-# 0x800F2C0002011E3F 
-scom 0x800.0b(tx_impcal_swo2_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-tx_zcal_sm_min_val,       0b0010101;
-tx_zcal_sm_max_val,       0b1000110;
-}
-#./iotk put tx_zcal_p_4x=00100
-# 0x800F1C0002011E3F 
-scom 0x800.0b(tx_impcal_p_4x_pb)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data;
-tx_zcal_p_4x,             0b00100;
-}
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#-- Overrides
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
 
-# 800A380002011E3F
-scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                               scom_data;
-rx_eo_enable_latch_offset_cal,      0b1;
-rx_eo_enable_ctle_cal,              0b1;
-rx_eo_enable_vga_cal,               0b1;
-rx_eo_enable_dfe_h1_cal,            0b1;
-rx_eo_enable_h1ap_tweak,            0b1;
-rx_eo_enable_ddc,                   0b1;
-rx_eo_enable_final_l2u_adj,         0b1;
-rx_eo_enable_ber_test,              0b1;
-rx_eo_enable_result_check,          0b1;
-}
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#     __                        ____                             __  __
+#    / /   ____ _____  ___     / __ \____ _      _____  _____   / / / /___
+#   / /   / __ `/ __ \/ _ \   / /_/ / __ \ | /| / / _ \/ ___/  / / / / __ \
+#  / /___/ /_/ / / / /  __/  / ____/ /_/ / |/ |/ /  __/ /     / /_/ / /_/ /
+# /_____/\__,_/_/ /_/\___/  /_/    \____/|__/|__/\___/_/      \____/ .___/
+#                                                                 /_/
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
 
-scom 0x800.0b(rx_eo_convergence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                               scom_data;
-rx_eo_converged_end_count,          0b111;
-}
+# rx_lane_pdwn
+#scom 0x800.0b(rx_mode_pl)(tx_grp3)(def_all_lanes).0x(dmi0_gcr_addr){
+#    bits,            scom_data;
+#    rx_lane_pdwn,    0b0;
+#}
 
-# 0x800AB80002011E3F
-scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                               scom_data;
-rx_rc_enable_latch_offset_cal,      0b1;
-rx_rc_enable_ctle_cal,              0b1;
-rx_rc_enable_vga_cal,               0b1;
-rx_rc_enable_h1ap_tweak,            0b1;
-rx_rc_enable_ddc,                   0b1;
-rx_rc_enable_ber_test,              0b1;
-rx_rc_enable_result_check,          0b1;
-#rx_rc_enable_dfe_h1_cal,           0b0; # Leave DFE off during recal for now
-}
+# tx_lane_pdwn
+#scom 0x800.0b(tx_mode_pl)(tx_grp3)(def_all_lanes).0x(dmi0_gcr_addr){
+#    bits,            scom_data;
+#    tx_lane_pdwn,    0b0;
+#}
 
 
-#--******************************************************************************
+#--***********************************************************************************
 #-------------------------------------------------------------------------------------
 #   _______  __    __    ___    _   ________   _____   ___    ____________  ______
 #  /_  __/ |/ /   / /   /   |  / | / / ____/  /  _/ | / / |  / / ____/ __ \/_  __/
-#   / /  |   /   / /   / /| | /  |/ / __/     / //  |/ /| | / / __/ / /_/ / / /   
-#  / /  /   |   / /___/ ___ |/ /|  / /___   _/ // /|  / | |/ / /___/ _, _/ / /    
-# /_/  /_/|_|  /_____/_/  |_/_/ |_/_____/  /___/_/ |_/  |___/_____/_/ |_| /_/     
-#                                        figlet -fslant
+#   / /  |   /   / /   / /| | /  |/ / __/     / //  |/ /| | / / __/ / /_/ / / /
+#  / /  /   |   / /___/ ___ |/ /|  / /___   _/ // /|  / | |/ / /___/ _, _/ / /
+# /_/  /_/|_|  /_____/_/  |_/_/ |_/_____/  /___/_/ |_/  |___/_____/_/ |_| /_/
+#
 #-------------------------------------------------------------------------------------
-#--******************************************************************************
+#--***********************************************************************************
 
-# These need to come as attributes from the MRW rather than be hardcoded here
-define  def_EI_TX_LANE_INVERT_VEC_MCS4 = 0x00F80000;  # MSBSWAP=0 ON TULETA  # TX3
-define  def_EI_TX_LANE_INVERT_VEC_MCS5 = 0xF7FF8000;  # MSBSWAP=1 ON TULETA  # TX2
-#define  def_EI_TX_LANE_INVERT_VEC_MCS5 = 0x7FF40000;  # MSBSWAP=1 ON TULETA
-define  def_EI_TX_LANE_INVERT_VEC_MCS6 = 0xFEFF8000;  # MSBSWAP=1 ON TULETA  # TX1
-define  def_EI_TX_LANE_INVERT_VEC_MCS7 = 0x96CF8000;  # MSBSWAP=1 ON TULETA  # TX0
+# These only do a scom if the invert attribute is set (saves scom's).
+# The default scanflush value of tx_lane_invert for each lane is '0'.
 
-# These only do a scom if the invert attribute is set (saves scom's). The default scanflush value of tx_lane_invert for each lane is '0'.
 # Lane 0
 # 0x8004040002011E3F
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_0).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_0).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_0).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_0).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x80000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x80000000) > 0; 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_0).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x80000000) > 0);
 }
+
 # Lane 1
 # 0x8004040102011E3F
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_1).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_1).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_1).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_1).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x40000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x40000000) > 0; 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_1).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x40000000) > 0);
 }
+
 # Lane 2
-# 0x8004040202011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_2).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_2).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_2).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_2).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x20000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x20000000) > 0; 
+# 0x8004040202011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_2).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x20000000) > 0);
 }
+
 # Lane 3
-# 0x8004040302011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_3).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_3).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_3).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_3).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x10000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x10000000) > 0; 
+# 0x8004040302011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_3).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x10000000) > 0);
 }
+
 # Lane 4
-# 0x8004040402011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_4).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_4).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_4).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_4).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x08000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x08000000) > 0; 
+# 0x8004040402011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_4).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x08000000) > 0);
 }
+
 # Lane 5
-# 0x8004040502011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_5).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_5).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_5).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_5).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x04000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x04000000) > 0; 
+# 0x8004040502011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_5).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x04000000) > 0);
 }
+
 # Lane 6
-# 0x8004040602011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_6).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_6).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_6).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_6).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x02000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x02000000) > 0; 
+# 0x8004040602011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_6).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x02000000) > 0);
 }
+
 # Lane 7
-# 0x8004040702011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_7).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_7).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_7).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_7).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x01000000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x01000000) > 0; 
+# 0x8004040702011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_7).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x01000000) > 0);
 }
+
 # Lane 8
-# 0x8004040802011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_8).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_8).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_8).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_8).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00800000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00800000) > 0; 
+# 0x8004040802011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_8).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00800000) > 0);
 }
+
 # Lane 9
 # 0x8004040902011E3F {
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_9).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_9).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_9).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_9).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00400000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00400000) > 0; 
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_9).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00400000) > 0);
 }
+
 # Lane 10
-# 0x8004040A02011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_10).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_10).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_10).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_10).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00200000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00200000) > 0; 
+# 0x8004040A02011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_10).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00200000) > 0);
 }
+
 # Lane 11
-# 0x8004040B02011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_11).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_11).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_11).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_11).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00100000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00100000) > 0; 
+# 0x8004040B02011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_11).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00100000) > 0);
 }
+
 # Lane 12
-# 0x8004040C02011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_12).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_12).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_12).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_12).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00080000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00080000) > 0; 
+# 0x8004040C02011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_12).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00080000) > 0);
 }
+
 # Lane 13
-# 0x8004040D02011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_13).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_13).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_13).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_13).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00040000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00040000) > 0; 
+# 0x8004040D02011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_13).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00040000) > 0);
 }
+
 # Lane 14
-# 0x8004040E02011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_14).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_14).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_14).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_14).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00020000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00020000) > 0; 
+# 0x8004040E02011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_14).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00020000) > 0);
 }
+
 # Lane 15
-# 0x8004040F02011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_15).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_15).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_15).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_15).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00010000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00010000) > 0; 
+# 0x8004040F02011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_15).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00010000) > 0);
 }
+
 # Lane 16
-# 0x8004041002011E3F 
-scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_16).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS4 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==0; 
+# 0x8004041002011E3F
+scom 0x800.0b(tx_mode_pl)(tx_grp3)(lane_16).0x(dmi0_gcr_addr) {
+    bits,            scom_data, expr;
+    tx_lane_invert,  0b1,       ((ATTR_EI_BUS_TX_LANE_INVERT & 0x00008000) > 0);
 }
-scom 0x800.0b(tx_mode_pl)(tx_grp2)(lane_16).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS5 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==1; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp1)(lane_16).0x(dmi1_gcr_addr) {
-bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS6 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==2; 
-}
-scom 0x800.0b(tx_mode_pl)(tx_grp0)(lane_16).0x(dmi1_gcr_addr) {
+
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#   _______  __    ________    __ __    ____                     __ 
+#  /_  __/ |/ /   / ____/ /   / //_/   /  _/___ _   _____  _____/ /_
+#   / /  |   /   / /   / /   / ,<      / // __ \ | / / _ \/ ___/ __/
+#  / /  /   |   / /___/ /___/ /| |   _/ // / / / |/ /  __/ /  / /_  
+# /_/  /_/|_|   \____/_____/_/ |_|  /___/_/ /_/|___/\___/_/   \__/  
+
+#                                        figlet -fslant
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+# CLK Lane (assigned to bit 31 of TX Lane Invert Attribute)
+# 0x800???7008010C3F 
+scom 0x800.0b(tx_clk_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) {
 bits,            scom_data, expr;
-tx_lane_invert,  0b1,       ((def_EI_TX_LANE_INVERT_VEC_MCS7 & 0x00008000) > 0) && TGT1.ATTR_CHIP_UNIT_POS%4==3; 
-#tx_lane_invert,  0b1,       (TGT1.ATTR_EI_TX_LANE_INVERT && 0x00008000) > 0; 
+tx_lane_invert,  0b1,       (ATTR_EI_BUS_TX_LANE_INVERT & 0x00000001) > 0;
 }
 
 #--***********************************************************************************
 #-------------------------------------------------------------------------------------
-#     __  ________ ____     _____                   
-#    /  |/  / ___// __ )   / ___/      ______ _____ 
+#     __  ________ ____     _____
+#    /  |/  / ___// __ )   / ___/      ______ _____
 #   / /|_/ /\__ \/ __  |   \__ \ | /| / / __ `/ __ \
 #  / /  / /___/ / /_/ /   ___/ / |/ |/ / /_/ / /_/ /
-# /_/  /_//____/_____/   /____/|__/|__/\__,_/ .___/ 
-#                                         /_/      
-#                                        figlet -fslant
+# /_/  /_//____/_____/   /____/|__/|__/\__,_/ .___/
+#                                         /_/
+#
 #-------------------------------------------------------------------------------------
 #--***********************************************************************************
 
-# TX_MSBSWAP setting via manaual SCOM overrides
-# ./iotk put tx_msbswap=1 (only when p# mod 4 = 3 for centaur or mcs mod 4 = 0, ie. grp0)
-# 0x800C1C0002011E3F 
-scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data, expr;
-tx_msbswap,               0b0,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 0); # MCS4
-#tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 1); # MCS5
-#tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 2); # MCS6
-#tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 3); # MCS7
-#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
-}
-scom 0x800.0b(tx_mode_pg)(tx_grp2)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data, expr;
-tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 1); # MCS5
-#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
-}
-scom 0x800.0b(tx_mode_pg)(tx_grp1)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data, expr;
-tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 2); # MCS6
-#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+# 0x800C1C0002011E3F
+scom 0x800.0b(tx_mode_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) {
+    bits,            scom_data;
+    tx_msbswap,      (ATTR_EI_BUS_TX_MSBSWAP & 0x01);
 }
-scom 0x800.0b(tx_mode_pg)(tx_grp0)(lane_na).0x(dmi1_gcr_addr) {
-bits,                     scom_data, expr;
-tx_msbswap,               0b1,       (TGT1.ATTR_CHIP_UNIT_POS % 4 == 3); # MCS7
-#tx_msbswap,               0b1,       (ATTR_EI_BUS_TX_MSBSWAP == 0x01);
+
+#--**************************************************************************************************************
+#----------------------------------------------------------------------------------------------------------------
+#    ________________     ____        ________             ____             _ __           __  ___           __  
+#   / ____/ ____/ __ \   / __ )__  __/ __/ __/__  _____   / __ \____ ______(_) /___  __   /  |/  /___ ______/ /__
+#  / / __/ /   / /_/ /  / __  / / / / /_/ /_/ _ \/ ___/  / /_/ / __ `/ ___/ / __/ / / /  / /|_/ / __ `/ ___/ //_/
+# / /_/ / /___/ _, _/  / /_/ / /_/ / __/ __/  __/ /     / ____/ /_/ / /  / / /_/ /_/ /  / /  / / /_/ (__  ) ,<   
+# \____/\____/_/ |_|  /_____/\__,_/_/ /_/  \___/_/     /_/    \__,_/_/  /_/\__/\__, /  /_/  /_/\__,_/____/_/|_|  
+#                                                                             /____/                             
+#----------------------------------------------------------------------------------------------------------------
+#--**************************************************************************************************************
+# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
+# 0x800???0002011E3F
+# This is applied to all configured clkgrp's via chiplet targetting
+scom 0x800.0b(rx_fir1_mask_pg)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) {
+bits,                             scom_data;
+rx_pg_fir_err_mask_gcr_buff,      0b1;
+}
+scom 0x800.0b(tx_fir_mask_pg)(tx_grp3)(lane_na).0x(dmi0_gcr_addr) {
+bits,                             scom_data;
+tx_pg_fir_err_mask_gcr_buff,      0b1;
+}
+scom 0x800.0b(rx_fir_mask_pb)(rx_grp3)(lane_na).0x(dmi0_gcr_addr) {
+bits,                             scom_data;
+rx_pb_fir_err_mask_gcr_buff0,    0b1;
+rx_pb_fir_err_mask_gcr_buff1,    0b1;
+rx_pb_fir_err_mask_gcr_buff2,    0b1;
 }
 
+# Mask off all rx and tx parity errors in the fir register
+scom 0x02011A03 {
+scom_data;
+0xC000000000000000;
+}
 
 ############################################################################################
 # END OF FILE
diff --git a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
index d12b0e139..eee853719 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.dmi.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.dmi.scom.initfile,v 1.12 2013/01/26 18:16:08 thomsen Exp $ 
+#-- $Id: p8.dmi.scom.initfile,v 1.16 2013/03/22 20:55:00 jgrell Exp $ 
 
 
 ####################################################################
@@ -7,13 +7,14 @@
 ##      Based on SETUP_ID_MODE DMI_BUS_TR_HW
 ##      from ../../logic/mesa_sim/fusion/run/IODPV_MC_WRAP.IODPV_MC_WRAP.figdb
 ##
-##   Created on Thu Jan 24 14:48:02 EST 2013, by derrin
+##   Created on Fri Mar 22 14:31:13 CDT 2013, by jgrell
 ####################################################################
 
 ## -- CHANGE HISTORY:
  ## --------------------------------------------------------------------------------
  ## -- VersionID: |Author:  | Date:  | Comment:
  ## -- -----------|---------|--------|-------------------------------------------------
+ ## -- jgr13031300| jgr     |03-13-13| Added missing entries from rel 0128
  ## -- mbs13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
  ## -- mbs12121100| mbs     |12-11-12| Added rx_prot_speed_slct and rx_c4_sel
  ## -- smr12112700| SMR     |11-27-12| Added rx_dyn_recal_overall_timeout_sel init to 0b001
@@ -57,2022 +58,1329 @@ SyntaxVersion = 1
 ####################################################################
 include edi.io.define
 
-                    define HW_EXPRESS = SYS.ATTR_IS_SIMULATION == 0;
-                    define VBU_EXPRESS = SYS.ATTR_IS_SIMULATION == 1;
+                    define def_IS_HW  = SYS.ATTR_IS_SIMULATION == 0;
+                    define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1;
                 
 
 
-define def_bus_id3 = ((TGT1.ATTR_CHIP_UNIT_POS == 0) || (TGT1.ATTR_CHIP_UNIT_POS == 4));
-define def_bus_id2 = ((TGT1.ATTR_CHIP_UNIT_POS == 1) || (TGT1.ATTR_CHIP_UNIT_POS == 5));
-define def_bus_id1 = ((TGT1.ATTR_CHIP_UNIT_POS == 2) || (TGT1.ATTR_CHIP_UNIT_POS == 6));
-define def_bus_id0 = ((TGT1.ATTR_CHIP_UNIT_POS == 3) || (TGT1.ATTR_CHIP_UNIT_POS == 7));
+define def_bus_id3 = ((ATTR_CHIP_UNIT_POS == 0) || (ATTR_CHIP_UNIT_POS == 4));
+define def_bus_id2 = ((ATTR_CHIP_UNIT_POS == 1) || (ATTR_CHIP_UNIT_POS == 5));
+define def_bus_id1 = ((ATTR_CHIP_UNIT_POS == 2) || (ATTR_CHIP_UNIT_POS == 7));
+define def_bus_id0 = ((ATTR_CHIP_UNIT_POS == 3) || (ATTR_CHIP_UNIT_POS == 6));
 
 
 
-#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_P_4X_PB
-scom 0x800F1C0002011E3F { 
-	bits, scom_data, expr;
-	tx_zcal_p_4x, 0b00100, any;
-}
-
-#BUSCTL.BUS_CTL_REGS.TX_IMPCAL_SWO2_PB
-scom 0x800F2C0002011E3F { 
-	bits, scom_data, expr;
-	tx_zcal_sm_max_val, 0b1000110, any;
-     tx_zcal_sm_min_val,  0b0010101   , HW_EXPRESS;
-     tx_zcal_sm_min_val,  0b0010110  , VBU_EXPRESS;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
-scom 0x800B780002011E3F { 
-	bits, scom_data, expr;
-     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id0;
-     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id0;
-     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id0;
-     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id0;
-     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id0;
-     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id0;
-     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id0;
-     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
-scom 0x800B800002011E3F { 
-	bits, scom_data, expr;
-     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id0;
-     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
-scom 0x800A180002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
-scom 0x8009D80002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0;
-	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0;
-	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
-scom 0x800AE00002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id0;
-	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
-scom 0x800A380002011E3F { 
-	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0;
-     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG
-scom 0x8009A80002011E3F { 
-	bits, scom_data, expr;
-	rx_fence, 0b1, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_ID1_PG
-scom 0x8008500002011E3F { 
-	bits, scom_data, expr;
-	rx_bus_id, 0b000000, def_bus_id0;
-	rx_group_id, 0b000000, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_ID2_PG
-scom 0x8008580002011E3F { 
-	bits, scom_data, expr;
-	rx_last_group_id, 0b000000, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_ID3_PG
-scom 0x8008600002011E3F { 
-	bits, scom_data, expr;
-	rx_end_lane_id, 0b0010111, def_bus_id0;
-	rx_start_lane_id, 0b0000000, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
-scom 0x8009280002011E3F { 
-	bits, scom_data, expr;
-	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
-scom 0x8009300002011E3F { 
-	bits, scom_data, expr;
-	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
-scom 0x8009C00002011E3F { 
-	bits, scom_data, expr;
-     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id0;
-     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id0;
-     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG
-scom 0x8008180002011E3F { 
-	bits, scom_data, expr;
-	rx_master_mode, 0b1, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
-scom 0x800AB80002011E3F { 
-	bits, scom_data, expr;
-     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id0;
-     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id0;
-     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
-scom 0x800B980002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id0;
-     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id0;
-     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id0;
-     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
-scom 0x800BA00002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id0;
-     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id0;
-     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id0;
-     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
-scom 0x800B600002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
-scom 0x800B680002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
-scom 0x800B700002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id0;
-     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
-scom 0x8008980002011E3F { 
-	bits, scom_data, expr;
-	rx_sls_timeout_sel, 0b001, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
-scom 0x8009980002011E3F { 
-	bits, scom_data, expr;
-	rx_rx_bus_width, 0b0011000, def_bus_id0;
-	rx_tx_bus_width, 0b0010001, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
-scom 0x8009580002011E3F { 
-	bits, scom_data, expr;
-	rx_wtr_max_bad_lanes, 0b00010, def_bus_id0;
-}
-
-#RX0.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
-scom 0x800A300002011E3F { 
-	bits, scom_data, expr;
-     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id0;
-     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id0;
-     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id0;
-     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id0;
-}
-
-#RX0.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00002011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#RX0.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00102011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id0;
-}
-
-#RX0.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00202011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id0;
-}
-
-#RX0.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00302011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id0;
-}
-
-#RX0.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00402011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b100, def_bus_id0;
-}
-
-#RX0.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00502011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b101, def_bus_id0;
-}
-
-#RX0.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00602011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b110, def_bus_id0;
-}
-
-#RX0.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00702011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b111, def_bus_id0;
-}
-
-#RX0.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01402011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id0;
-}
-
-#RX0.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01502011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id0;
-}
-
-#RX0.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01602011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id0;
-}
-
-#RX0.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01702011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#RX0.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01002011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b111, def_bus_id0;
-}
-
-#RX0.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01102011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b110, def_bus_id0;
-}
-
-#RX0.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01202011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b101, def_bus_id0;
-}
-
-#RX0.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B01302011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b100, def_bus_id0;
-}
-
-#RX0.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00E02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id0;
-}
-
-#RX0.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00F02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#RX0.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00C02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id0;
-}
-
-#RX0.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00D02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id0;
-}
-
-#RX0.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00A02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id0;
-}
-
-#RX0.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00B02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id0;
-}
-
-#RX0.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00802011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#RX0.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B00902011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id0;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
-scom 0x800B782002011E3F { 
-	bits, scom_data, expr;
-     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id1;
-     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id1;
-     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id1;
-     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id1;
-     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id1;
-     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id1;
-     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id1;
-     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
-scom 0x800B802002011E3F { 
-	bits, scom_data, expr;
-     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id1;
-     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
-scom 0x800A182002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
-scom 0x8009D82002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1;
-	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1;
-	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
-scom 0x800AE02002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id1;
-	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
-scom 0x800A382002011E3F { 
-	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1;
-     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG
-scom 0x8009A82002011E3F { 
-	bits, scom_data, expr;
-	rx_fence, 0b1, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_ID1_PG
-scom 0x8008502002011E3F { 
-	bits, scom_data, expr;
-	rx_bus_id, 0b000001, def_bus_id1;
-	rx_group_id, 0b000000, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_ID2_PG
-scom 0x8008582002011E3F { 
-	bits, scom_data, expr;
-	rx_last_group_id, 0b000000, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_ID3_PG
-scom 0x8008602002011E3F { 
-	bits, scom_data, expr;
-	rx_end_lane_id, 0b0010111, def_bus_id1;
-	rx_start_lane_id, 0b0000000, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
-scom 0x8009282002011E3F { 
-	bits, scom_data, expr;
-	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
-scom 0x8009302002011E3F { 
-	bits, scom_data, expr;
-	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
-scom 0x8009C02002011E3F { 
-	bits, scom_data, expr;
-     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id1;
-     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id1;
-     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG
-scom 0x8008182002011E3F { 
-	bits, scom_data, expr;
-	rx_master_mode, 0b1, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
-scom 0x800AB82002011E3F { 
-	bits, scom_data, expr;
-     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id1;
-     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id1;
-     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
-scom 0x800B982002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id1;
-     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id1;
-     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id1;
-     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
-scom 0x800BA02002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id1;
-     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id1;
-     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id1;
-     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
-scom 0x800B602002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
-scom 0x800B682002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
-scom 0x800B702002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id1;
-     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
-scom 0x8008982002011E3F { 
-	bits, scom_data, expr;
-	rx_sls_timeout_sel, 0b001, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
-scom 0x8009982002011E3F { 
-	bits, scom_data, expr;
-	rx_rx_bus_width, 0b0011000, def_bus_id1;
-	rx_tx_bus_width, 0b0010001, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
-scom 0x8009582002011E3F { 
-	bits, scom_data, expr;
-	rx_wtr_max_bad_lanes, 0b00010, def_bus_id1;
-}
-
-#RX1.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
-scom 0x800A302002011E3F { 
-	bits, scom_data, expr;
-     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id1;
-     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id1;
-     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id1;
-     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id1;
-}
-
-#RX1.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02002011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#RX1.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02102011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id1;
-}
-
-#RX1.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02202011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id1;
-}
-
-#RX1.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02302011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id1;
-}
-
-#RX1.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02402011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b100, def_bus_id1;
-}
-
-#RX1.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02502011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b101, def_bus_id1;
-}
-
-#RX1.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02602011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b110, def_bus_id1;
-}
-
-#RX1.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02702011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b111, def_bus_id1;
-}
-
-#RX1.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03402011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id1;
-}
-
-#RX1.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03502011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id1;
-}
-
-#RX1.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03602011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id1;
-}
-
-#RX1.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03702011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#RX1.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03002011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b111, def_bus_id1;
-}
-
-#RX1.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03102011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b110, def_bus_id1;
-}
-
-#RX1.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03202011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b101, def_bus_id1;
-}
-
-#RX1.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B03302011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b100, def_bus_id1;
-}
-
-#RX1.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02E02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id1;
-}
-
-#RX1.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02F02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#RX1.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02C02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id1;
-}
-
-#RX1.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02D02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id1;
-}
-
-#RX1.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02A02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id1;
-}
-
-#RX1.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02B02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id1;
-}
-
-#RX1.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02802011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#RX1.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B02902011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id1;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
-scom 0x800B784002011E3F { 
-	bits, scom_data, expr;
-     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id2;
-     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id2;
-     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id2;
-     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id2;
-     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id2;
-     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id2;
-     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id2;
-     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
-scom 0x800B804002011E3F { 
-	bits, scom_data, expr;
-     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id2;
-     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
-scom 0x800A184002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
-scom 0x8009D84002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2;
-	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2;
-	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
-scom 0x800AE04002011E3F { 
-	bits, scom_data, expr;
-	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id2;
-	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
-scom 0x800A384002011E3F { 
-	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2;
-     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_FENCE_PG
-scom 0x8009A84002011E3F { 
-	bits, scom_data, expr;
-	rx_fence, 0b1, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_ID1_PG
-scom 0x8008504002011E3F { 
-	bits, scom_data, expr;
-	rx_bus_id, 0b000010, def_bus_id2;
-	rx_group_id, 0b000000, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_ID2_PG
-scom 0x8008584002011E3F { 
-	bits, scom_data, expr;
-	rx_last_group_id, 0b000000, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_ID3_PG
-scom 0x8008604002011E3F { 
-	bits, scom_data, expr;
-	rx_end_lane_id, 0b0010111, def_bus_id2;
-	rx_start_lane_id, 0b0000000, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
-scom 0x8009284002011E3F { 
-	bits, scom_data, expr;
-	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
-scom 0x8009304002011E3F { 
-	bits, scom_data, expr;
-	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
-scom 0x8009C04002011E3F { 
-	bits, scom_data, expr;
-     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id2;
-     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id2;
-     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_MODE_PG
-scom 0x8008184002011E3F { 
-	bits, scom_data, expr;
-	rx_master_mode, 0b1, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
-scom 0x800AB84002011E3F { 
-	bits, scom_data, expr;
-     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id2;
-     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id2;
-     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
-scom 0x800B984002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id2;
-     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id2;
-     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id2;
-     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
-scom 0x800BA04002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id2;
-     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id2;
-     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id2;
-     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
-scom 0x800B604002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
-scom 0x800B684002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
-scom 0x800B704002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id2;
-     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
-scom 0x8008984002011E3F { 
-	bits, scom_data, expr;
-	rx_sls_timeout_sel, 0b001, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
-scom 0x8009984002011E3F { 
-	bits, scom_data, expr;
-	rx_rx_bus_width, 0b0011000, def_bus_id2;
-	rx_tx_bus_width, 0b0010001, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
-scom 0x8009584002011E3F { 
-	bits, scom_data, expr;
-	rx_wtr_max_bad_lanes, 0b00010, def_bus_id2;
-}
-
-#RX2.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
-scom 0x800A304002011E3F { 
-	bits, scom_data, expr;
-     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id2;
-     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id2;
-     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id2;
-     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id2;
-}
-
-#RX2.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04002011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#RX2.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04102011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id2;
-}
-
-#RX2.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04202011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id2;
-}
-
-#RX2.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04302011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id2;
-}
-
-#RX2.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04402011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b100, def_bus_id2;
-}
-
-#RX2.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04502011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b101, def_bus_id2;
-}
-
-#RX2.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04602011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b110, def_bus_id2;
-}
-
-#RX2.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04702011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b111, def_bus_id2;
-}
-
-#RX2.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05402011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id2;
-}
-
-#RX2.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05502011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id2;
-}
-
-#RX2.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05602011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id2;
-}
-
-#RX2.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05702011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#RX2.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05002011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b111, def_bus_id2;
-}
-
-#RX2.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05102011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b110, def_bus_id2;
-}
-
-#RX2.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05202011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b101, def_bus_id2;
-}
-
-#RX2.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B05302011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b100, def_bus_id2;
-}
-
-#RX2.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04E02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id2;
-}
-
-#RX2.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04F02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#RX2.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04C02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id2;
-}
-
-#RX2.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04D02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id2;
-}
-
-#RX2.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04A02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b010, def_bus_id2;
-}
-
-#RX2.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04B02011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b011, def_bus_id2;
-}
-
-#RX2.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04802011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#RX2.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B04902011E3F { 
-	bits, scom_data, expr;
-	rx_prbs_tap_id, 0b001, def_bus_id2;
-}
-
 #RX3.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
-scom 0x800B786002011E3F { 
-	bits, scom_data, expr;
-     rx_amin_cfg,  0b010,   HW_EXPRESS && def_bus_id3;
-     rx_amin_cfg,  0b000,  VBU_EXPRESS && def_bus_id3;
-     rx_anap_cfg,  0b10,   HW_EXPRESS && def_bus_id3;
-     rx_anap_cfg,  0b00,  VBU_EXPRESS && def_bus_id3;
-     rx_h1ap_cfg,  0b011,   HW_EXPRESS && def_bus_id3;
-     rx_h1ap_cfg,  0b000,  VBU_EXPRESS && def_bus_id3;
-     rx_peak_cfg,  0b10,   HW_EXPRESS && def_bus_id3;
-     rx_peak_cfg,  0b00,  VBU_EXPRESS && def_bus_id3;
+scom 0x800B786002011A3F { 
+	bits, scom_data, expr;
+     rx_amin_cfg,  0b010,   def_IS_HW && def_bus_id3;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_amin_cfg,  0b000,  def_IS_VBU && def_bus_id3;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id0;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id0;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id1;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_amin_cfg, 0b010, def_IS_HW && def_bus_id2;
+	rx_amin_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_anap_cfg,  0b10,   def_IS_HW && def_bus_id3;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_anap_cfg,  0b00,  def_IS_VBU && def_bus_id3;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id0;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id0;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_anap_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_anap_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_h1ap_cfg,  0b011,   def_IS_HW && def_bus_id3;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_h1ap_cfg,  0b000,  def_IS_VBU && def_bus_id3;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id0;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id0;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id1;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_h1ap_cfg, 0b011, def_IS_HW && def_bus_id2;
+	rx_h1ap_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_peak_cfg,  0b10,   def_IS_HW && def_bus_id3;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_peak_cfg,  0b00,  def_IS_VBU && def_bus_id3;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id0;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id0;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_peak_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_peak_cfg, 0b00, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_DFE_TIMERS_PP
-scom 0x800B806002011E3F { 
-	bits, scom_data, expr;
-     rx_init_tmr_cfg,  0b100,   HW_EXPRESS && def_bus_id3;
-     rx_init_tmr_cfg,  0b000,  VBU_EXPRESS && def_bus_id3;
+scom 0x800B806002011A3F { 
+	bits, scom_data, expr;
+     rx_init_tmr_cfg,  0b100,   def_IS_HW && def_bus_id3;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_init_tmr_cfg,  0b000,  def_IS_VBU && def_bus_id3;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id0;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id0;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id1;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id1;
+	rx_init_tmr_cfg, 0b100, def_IS_HW && def_bus_id2;
+	rx_init_tmr_cfg, 0b000, def_IS_VBU && def_bus_id2;
+     rx_prot_cfg,  0b10,   def_IS_HW && def_bus_id3;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2;
+     rx_prot_cfg,  0b00,  def_IS_VBU && def_bus_id3;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id0;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id0;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id1;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id1;
+	rx_prot_cfg, 0b10, def_IS_HW && def_bus_id2;
+	rx_prot_cfg, 0b00, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RECAL_CONFIG_PG
-scom 0x800A186002011E3F { 
+scom 0x800A186002011A3F { 
 	bits, scom_data, expr;
 	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id3;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id0;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id1;
+	rx_dyn_recal_overall_timeout_sel, 0b001, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
-scom 0x8009D86002011E3F { 
+scom 0x8009D86002011A3F { 
 	bits, scom_data, expr;
 	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id3;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id0;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id1;
+	rx_dyn_rpr_bad_lane_max, 0b0001111, def_bus_id2;
 	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id3;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id0;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id1;
+	rx_dyn_rpr_enc_bad_data_lane_width, 0b101, def_bus_id2;
 	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id3;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id0;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id1;
+	rx_dyn_rpr_err_cntr1_duration, 0b0111, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING2_PG
-scom 0x800AE06002011E3F { 
+scom 0x800AE06002011A3F { 
 	bits, scom_data, expr;
 	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id3;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id0;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id1;
+	rx_dyn_rpr_bad_bus_max, 0b0111111, def_bus_id2;
 	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id3;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id0;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id1;
+	rx_dyn_rpr_err_cntr2_duration, 0b0111, def_bus_id2;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_EO_CONVERGENCE_PG
+scom 0x800A806002011A3F { 
+	bits, scom_data, expr;
+     rx_eo_converged_end_count,  0b0111,   def_IS_HW && def_bus_id3;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2;
+     rx_eo_converged_end_count,  0b0011,  def_IS_VBU && def_bus_id3;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id0;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id0;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id1;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id1;
+	rx_eo_converged_end_count, 0b0111, def_IS_HW && def_bus_id2;
+	rx_eo_converged_end_count, 0b0011, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
-scom 0x800A386002011E3F { 
-	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_eo_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_eo_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_eo_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+scom 0x800A386002011A3F { 
+	bits, scom_data, expr;
+     rx_eo_enable_ber_test,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ber_test,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ctle_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ctle_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ddc,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_ddc,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_dfe_h1_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_dfe_h1_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2;
 	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id3;
-     rx_eo_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_eo_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_eo_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_eo_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_eo_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id0;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id1;
+	rx_eo_enable_final_l2u_adj, 0b1, def_bus_id2;
+     rx_eo_enable_h1ap_tweak,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_h1ap_tweak,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_latch_offset_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_latch_offset_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_result_check,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_result_check,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_vga_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_eo_enable_vga_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_eo_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_eo_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_FENCE_PG
-scom 0x8009A86002011E3F { 
+scom 0x8009A86002011A3F { 
 	bits, scom_data, expr;
 	rx_fence, 0b1, def_bus_id3;
+	rx_fence, 0b1, def_bus_id0;
+	rx_fence, 0b1, def_bus_id1;
+	rx_fence, 0b1, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_ID1_PG
-scom 0x8008506002011E3F { 
+scom 0x8008506002011A3F { 
 	bits, scom_data, expr;
 	rx_bus_id, 0b000011, def_bus_id3;
+	rx_bus_id, 0b000000, def_bus_id0;
+	rx_bus_id, 0b000001, def_bus_id1;
+	rx_bus_id, 0b000010, def_bus_id2;
 	rx_group_id, 0b000000, def_bus_id3;
+	rx_group_id, 0b000000, def_bus_id0;
+	rx_group_id, 0b000000, def_bus_id1;
+	rx_group_id, 0b000000, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_ID2_PG
-scom 0x8008586002011E3F { 
+scom 0x8008586002011A3F { 
 	bits, scom_data, expr;
 	rx_last_group_id, 0b000000, def_bus_id3;
+	rx_last_group_id, 0b000000, def_bus_id0;
+	rx_last_group_id, 0b000000, def_bus_id1;
+	rx_last_group_id, 0b000000, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_ID3_PG
-scom 0x8008606002011E3F { 
+scom 0x8008606002011A3F { 
 	bits, scom_data, expr;
 	rx_end_lane_id, 0b0010111, def_bus_id3;
+	rx_end_lane_id, 0b0010111, def_bus_id0;
+	rx_end_lane_id, 0b0010111, def_bus_id1;
+	rx_end_lane_id, 0b0010111, def_bus_id2;
 	rx_start_lane_id, 0b0000000, def_bus_id3;
+	rx_start_lane_id, 0b0000000, def_bus_id0;
+	rx_start_lane_id, 0b0000000, def_bus_id1;
+	rx_start_lane_id, 0b0000000, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_0_15_PG
-scom 0x8009286002011E3F { 
+scom 0x8009286002011A3F { 
 	bits, scom_data, expr;
 	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
+	rx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_LANE_DISABLED_VEC_16_31_PG
-scom 0x8009306002011E3F { 
+scom 0x8009306002011A3F { 
 	bits, scom_data, expr;
 	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id3;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id0;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id1;
+	rx_lane_disabled_vec_16_31, 0b0000000011111111, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_MISC_ANALOG_PG
-scom 0x8009C06002011E3F { 
-	bits, scom_data, expr;
-     rx_c4_sel,  0b00,   HW_EXPRESS && def_bus_id3;
-     rx_c4_sel,  0b11,  VBU_EXPRESS && def_bus_id3;
-     rx_prot_speed_slct,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_prot_speed_slct,  0b0,  VBU_EXPRESS && def_bus_id3;
+scom 0x8009C06002011A3F { 
+	bits, scom_data, expr;
+     rx_c4_sel,  0b00,   def_IS_HW && def_bus_id3;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id0;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id1;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id2;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2;
+     rx_c4_sel,  0b11,  def_IS_VBU && def_bus_id3;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id0;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id0;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id1;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id1;
+	rx_c4_sel, 0b00, def_IS_HW && def_bus_id2;
+	rx_c4_sel, 0b11, def_IS_VBU && def_bus_id2;
+     rx_prot_speed_slct,  0b1,   def_IS_HW && def_bus_id3;
+	rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id0;
+	rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id0;
+	rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id1;
+	rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id1;
+	rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id2;
+	rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2;
+     rx_prot_speed_slct,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id0;
+	rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id0;
+	rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id1;
+	rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id1;
+	rx_prot_speed_slct, 0b1, def_IS_HW && def_bus_id2;
+	rx_prot_speed_slct, 0b0, def_IS_VBU && def_bus_id2;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_MODE1_PP
+scom 0x800B086002011A3F { 
+	bits, scom_data, expr;
+     rx_bit_lock_timeout_sel,  0b110,   def_IS_HW && def_bus_id3;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2;
+     rx_bit_lock_timeout_sel,  0b101,  def_IS_VBU && def_bus_id3;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id0;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id0;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id1;
+	rx_bit_lock_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_bit_lock_timeout_sel, 0b101, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_MODE_PG
-scom 0x8008186002011E3F { 
+scom 0x8008186002011A3F { 
 	bits, scom_data, expr;
 	rx_master_mode, 0b1, def_bus_id3;
+	rx_master_mode, 0b1, def_bus_id0;
+	rx_master_mode, 0b1, def_bus_id1;
+	rx_master_mode, 0b1, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
-scom 0x800AB86002011E3F { 
-	bits, scom_data, expr;
-     rx_rc_enable_ber_test,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_ber_test,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_ctle_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_ctle_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_ddc,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_ddc,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_dfe_h1_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_dfe_h1_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_h1ap_tweak,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_h1ap_tweak,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_latch_offset_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_latch_offset_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_result_check,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_result_check,  0b0,  VBU_EXPRESS && def_bus_id3;
-     rx_rc_enable_vga_cal,  0b1,   HW_EXPRESS && def_bus_id3;
-     rx_rc_enable_vga_cal,  0b0,  VBU_EXPRESS && def_bus_id3;
+scom 0x800AB86002011A3F { 
+	bits, scom_data, expr;
+     rx_rc_enable_ber_test,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ber_test,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ber_test, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ber_test, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ctle_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ctle_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ctle_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ctle_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ddc,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_ddc,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_ddc, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_ddc, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_dfe_h1_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_dfe_h1_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_dfe_h1_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_dfe_h1_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_h1ap_tweak,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_h1ap_tweak,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_h1ap_tweak, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_h1ap_tweak, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_latch_offset_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_latch_offset_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_latch_offset_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_latch_offset_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_result_check,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_result_check,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_result_check, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_result_check, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_vga_cal,  0b1,   def_IS_HW && def_bus_id3;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
+     rx_rc_enable_vga_cal,  0b0,  def_IS_VBU && def_bus_id3;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id0;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id0;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id1;
+	rx_rc_enable_vga_cal, 0b1, def_IS_HW && def_bus_id2;
+	rx_rc_enable_vga_cal, 0b0, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO2_PP
-scom 0x800B986002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id3;
-     rx_recal_timeout_sel_g,  0b0110,  VBU_EXPRESS && def_bus_id3;
-     rx_recal_timeout_sel_h,  0b0110,   HW_EXPRESS && def_bus_id3;
-     rx_recal_timeout_sel_h,  0b1000,  VBU_EXPRESS && def_bus_id3;
+scom 0x800B986002011A3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_g,  0b0111,   def_IS_HW && def_bus_id3;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_g,  0b0110,  def_IS_VBU && def_bus_id3;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_g, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_h,  0b0110,   def_IS_HW && def_bus_id3;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_h,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_h, 0b0110, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_RECAL_TO3_PP
-scom 0x800BA06002011E3F { 
-	bits, scom_data, expr;
-     rx_recal_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id3;
-     rx_recal_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id3;
-     rx_recal_timeout_sel_l,  0b0100,   HW_EXPRESS && def_bus_id3;
-     rx_recal_timeout_sel_l,  0b0110,  VBU_EXPRESS && def_bus_id3;
+scom 0x800BA06002011A3F { 
+	bits, scom_data, expr;
+     rx_recal_timeout_sel_i,  0b0111,   def_IS_HW && def_bus_id3;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_i,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_i, 0b0111, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_l,  0b0100,   def_IS_HW && def_bus_id3;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_recal_timeout_sel_l,  0b0110,  def_IS_VBU && def_bus_id3;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id0;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id0;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_recal_timeout_sel_l, 0b0100, def_IS_HW && def_bus_id2;
+	rx_recal_timeout_sel_l, 0b0110, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
-scom 0x800B606002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_d,  0b1010,   HW_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_d,  0b1000,  VBU_EXPRESS && def_bus_id3;
+scom 0x800B606002011A3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_d,  0b1001,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_d,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_d, 0b1001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_d, 0b1000, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
-scom 0x800B686002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b0001,   HW_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_f,  0b0110,  VBU_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_g,  0b0111,   HW_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_g,  0b0100,  VBU_EXPRESS && def_bus_id3;
+scom 0x800B686002011A3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_f,  0b0001,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_f,  0b0110,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_f, 0b0001, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_f, 0b0110, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_g,  0b0111,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_g,  0b0100,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_g, 0b0111, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_g, 0b0100, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_h,  0b1110,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_h,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_h, 0b1110, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_h, 0b1000, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_SERVO_TO3_PP
-scom 0x800B706002011E3F { 
-	bits, scom_data, expr;
-     rx_servo_timeout_sel_i,  0b0111,   HW_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_i,  0b1000,  VBU_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_k,  0b0111,   HW_EXPRESS && def_bus_id3;
-     rx_servo_timeout_sel_k,  0b1000,  VBU_EXPRESS && def_bus_id3;
+scom 0x800B706002011A3F { 
+	bits, scom_data, expr;
+     rx_servo_timeout_sel_i,  0b1011,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_i,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_i, 0b1011, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_i, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_j,  0b1100,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_j,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_j, 0b1100, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_j, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_k,  0b1101,   def_IS_HW && def_bus_id3;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2;
+     rx_servo_timeout_sel_k,  0b1000,  def_IS_VBU && def_bus_id3;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id0;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id0;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id1;
+	rx_servo_timeout_sel_k, 0b1101, def_IS_HW && def_bus_id2;
+	rx_servo_timeout_sel_k, 0b1000, def_IS_VBU && def_bus_id2;
+}
+
+#RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG
+scom 0x8009106002011A3F { 
+	bits, scom_data, expr;
+     rx_eo_amp_timeout_sel,  0b111,   def_IS_HW && def_bus_id3;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_amp_timeout_sel,  0b110,  def_IS_VBU && def_bus_id3;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_amp_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_amp_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ctle_timeout_sel,  0b111,   def_IS_HW && def_bus_id3;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ctle_timeout_sel,  0b110,  def_IS_VBU && def_bus_id3;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ctle_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ctle_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ddc_timeout_sel,  0b111,   def_IS_HW && def_bus_id3;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_ddc_timeout_sel,  0b110,  def_IS_VBU && def_bus_id3;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_ddc_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_ddc_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_h1ap_timeout_sel,  0b111,   def_IS_HW && def_bus_id3;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_h1ap_timeout_sel,  0b110,  def_IS_VBU && def_bus_id3;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_h1ap_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_h1ap_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_offset_timeout_sel,  0b111,   def_IS_HW && def_bus_id3;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
+     rx_eo_offset_timeout_sel,  0b110,  def_IS_VBU && def_bus_id3;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id0;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id1;
+	rx_eo_offset_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_eo_offset_timeout_sel, 0b110, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
-scom 0x8008986002011E3F { 
-	bits, scom_data, expr;
+scom 0x8008986002011A3F { 
+	bits, scom_data, expr;
+     rx_ds_bl_timeout_sel,  0b101,   def_IS_HW && def_bus_id3;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2;
+     rx_ds_bl_timeout_sel,  0b001,  def_IS_VBU && def_bus_id3;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id0;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id0;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id1;
+	rx_ds_bl_timeout_sel, 0b101, def_IS_HW && def_bus_id2;
+	rx_ds_bl_timeout_sel, 0b001, def_IS_VBU && def_bus_id2;
+     rx_ds_timeout_sel,  0b110,   def_IS_HW && def_bus_id3;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id0;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id0;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2;
+     rx_ds_timeout_sel,  0b010,  def_IS_VBU && def_bus_id3;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id0;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id0;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id1;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id1;
+	rx_ds_timeout_sel, 0b110, def_IS_HW && def_bus_id2;
+	rx_ds_timeout_sel, 0b010, def_IS_VBU && def_bus_id2;
 	rx_sls_timeout_sel, 0b001, def_bus_id3;
+	rx_sls_timeout_sel, 0b001, def_bus_id0;
+	rx_sls_timeout_sel, 0b001, def_bus_id1;
+	rx_sls_timeout_sel, 0b001, def_bus_id2;
+     rx_wt_timeout_sel,  0b111,   def_IS_HW && def_bus_id3;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2;
+     rx_wt_timeout_sel,  0b011,  def_IS_VBU && def_bus_id3;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id0;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id0;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id1;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id1;
+	rx_wt_timeout_sel, 0b111, def_IS_HW && def_bus_id2;
+	rx_wt_timeout_sel, 0b011, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
-scom 0x8009986002011E3F { 
+scom 0x8009986002011A3F { 
 	bits, scom_data, expr;
 	rx_rx_bus_width, 0b0011000, def_bus_id3;
+	rx_rx_bus_width, 0b0011000, def_bus_id0;
+	rx_rx_bus_width, 0b0011000, def_bus_id1;
+	rx_rx_bus_width, 0b0011000, def_bus_id2;
 	rx_tx_bus_width, 0b0010001, def_bus_id3;
+	rx_tx_bus_width, 0b0010001, def_bus_id0;
+	rx_tx_bus_width, 0b0010001, def_bus_id1;
+	rx_tx_bus_width, 0b0010001, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_LANEINFO_PG
-scom 0x8009586002011E3F { 
+scom 0x8009586002011A3F { 
 	bits, scom_data, expr;
 	rx_wtr_max_bad_lanes, 0b00010, def_bus_id3;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id0;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id1;
+	rx_wtr_max_bad_lanes, 0b00010, def_bus_id2;
 }
 
 #RX3.RXCTL.RX_CTL_REGS.RX_WIRETEST_PLL_CNTL_PG
-scom 0x800A306002011E3F { 
-	bits, scom_data, expr;
-     rx_wt_cu_pll_pgooddly,  0b001,   HW_EXPRESS && def_bus_id3;
-     rx_wt_cu_pll_pgooddly,  0b000,  VBU_EXPRESS && def_bus_id3;
-     rx_wt_cu_pll_reset,  0b0,   HW_EXPRESS && def_bus_id3;
-     rx_wt_cu_pll_reset,  0b1,  VBU_EXPRESS && def_bus_id3;
+scom 0x800A306002011A3F { 
+	bits, scom_data, expr;
+     rx_wt_cu_pll_pgooddly,  0b001,   def_IS_HW && def_bus_id3;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2;
+     rx_wt_cu_pll_pgooddly,  0b000,  def_IS_VBU && def_bus_id3;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id0;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id0;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_pgooddly, 0b001, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_pgooddly, 0b000, def_IS_VBU && def_bus_id2;
+     rx_wt_cu_pll_reset,  0b0,   def_IS_HW && def_bus_id3;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2;
+     rx_wt_cu_pll_reset,  0b1,  def_IS_VBU && def_bus_id3;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id0;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id0;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id1;
+	rx_wt_cu_pll_reset, 0b0, def_IS_HW && def_bus_id2;
+	rx_wt_cu_pll_reset, 0b1, def_IS_VBU && def_bus_id2;
 }
 
 #RX3.RXPACKS#0.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06002011E3F { 
+scom 0x8000B06002011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b000, def_bus_id3;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX3.RXPACKS#0.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06102011E3F { 
+scom 0x8000B06102011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b001, def_bus_id3;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #RX3.RXPACKS#0.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06202011E3F { 
+scom 0x8000B06202011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b010, def_bus_id3;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX3.RXPACKS#0.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06302011E3F { 
+scom 0x8000B06302011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b011, def_bus_id3;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX3.RXPACKS#1.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06402011E3F { 
+scom 0x8000B06402011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b100, def_bus_id3;
+	rx_prbs_tap_id, 0b100, def_bus_id0;
+	rx_prbs_tap_id, 0b100, def_bus_id1;
+	rx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #RX3.RXPACKS#1.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06502011E3F { 
+scom 0x8000B06502011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b101, def_bus_id3;
+	rx_prbs_tap_id, 0b101, def_bus_id0;
+	rx_prbs_tap_id, 0b101, def_bus_id1;
+	rx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #RX3.RXPACKS#1.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06602011E3F { 
+scom 0x8000B06602011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b110, def_bus_id3;
+	rx_prbs_tap_id, 0b110, def_bus_id0;
+	rx_prbs_tap_id, 0b110, def_bus_id1;
+	rx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #RX3.RXPACKS#1.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06702011E3F { 
+scom 0x8000B06702011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b111, def_bus_id3;
+	rx_prbs_tap_id, 0b111, def_bus_id0;
+	rx_prbs_tap_id, 0b111, def_bus_id1;
+	rx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #RX3.RXPACKS#2.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07402011E3F { 
+scom 0x8000B07402011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b011, def_bus_id3;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX3.RXPACKS#2.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07502011E3F { 
+scom 0x8000B07502011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b010, def_bus_id3;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX3.RXPACKS#2.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07602011E3F { 
+scom 0x8000B07602011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b001, def_bus_id3;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #RX3.RXPACKS#2.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07702011E3F { 
+scom 0x8000B07702011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b000, def_bus_id3;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX3.RXPACKS#3.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07002011E3F { 
+scom 0x8000B07002011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b111, def_bus_id3;
+	rx_prbs_tap_id, 0b111, def_bus_id0;
+	rx_prbs_tap_id, 0b111, def_bus_id1;
+	rx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #RX3.RXPACKS#3.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07102011E3F { 
+scom 0x8000B07102011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b110, def_bus_id3;
+	rx_prbs_tap_id, 0b110, def_bus_id0;
+	rx_prbs_tap_id, 0b110, def_bus_id1;
+	rx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #RX3.RXPACKS#3.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07202011E3F { 
+scom 0x8000B07202011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b101, def_bus_id3;
+	rx_prbs_tap_id, 0b101, def_bus_id0;
+	rx_prbs_tap_id, 0b101, def_bus_id1;
+	rx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #RX3.RXPACKS#3.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B07302011E3F { 
+scom 0x8000B07302011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b100, def_bus_id3;
+	rx_prbs_tap_id, 0b100, def_bus_id0;
+	rx_prbs_tap_id, 0b100, def_bus_id1;
+	rx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #RX3.RXPACKS#4.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06E02011E3F { 
+scom 0x8000B06E02011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b001, def_bus_id3;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #RX3.RXPACKS#4.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06F02011E3F { 
+scom 0x8000B06F02011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b000, def_bus_id3;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX3.RXPACKS#4.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06C02011E3F { 
+scom 0x8000B06C02011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b011, def_bus_id3;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX3.RXPACKS#4.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06D02011E3F { 
+scom 0x8000B06D02011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b010, def_bus_id3;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX3.RXPACKS#5.RXPACK.RD.SLICE#0.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06A02011E3F { 
+scom 0x8000B06A02011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b010, def_bus_id3;
+	rx_prbs_tap_id, 0b010, def_bus_id0;
+	rx_prbs_tap_id, 0b010, def_bus_id1;
+	rx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #RX3.RXPACKS#5.RXPACK.RD.SLICE#1.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06B02011E3F { 
+scom 0x8000B06B02011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b011, def_bus_id3;
+	rx_prbs_tap_id, 0b011, def_bus_id0;
+	rx_prbs_tap_id, 0b011, def_bus_id1;
+	rx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #RX3.RXPACKS#5.RXPACK.RD.SLICE#2.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06802011E3F { 
+scom 0x8000B06802011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b000, def_bus_id3;
+	rx_prbs_tap_id, 0b000, def_bus_id0;
+	rx_prbs_tap_id, 0b000, def_bus_id1;
+	rx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #RX3.RXPACKS#5.RXPACK.RD.SLICE#3.RD.RX_BIT_REGS.RX_PRBS_MODE_PL
-scom 0x8000B06902011E3F { 
+scom 0x8000B06902011A3F { 
 	bits, scom_data, expr;
 	rx_prbs_tap_id, 0b001, def_bus_id3;
+	rx_prbs_tap_id, 0b001, def_bus_id0;
+	rx_prbs_tap_id, 0b001, def_bus_id1;
+	rx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
-scom 0x800CC40002011E3F { 
+#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
+scom 0x800CC46002011A3F { 
 	bits, scom_data, expr;
+	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id3;
 	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID1_PG
-scom 0x800C940002011E3F { 
-	bits, scom_data, expr;
-	tx_bus_id, 0b000000, def_bus_id0;
-	tx_group_id, 0b100000, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID2_PG
-scom 0x800C9C0002011E3F { 
-	bits, scom_data, expr;
-	tx_last_group_id, 0b100000, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_ID3_PG
-scom 0x800CA40002011E3F { 
-	bits, scom_data, expr;
-	tx_end_lane_id, 0b0010000, def_bus_id0;
-	tx_start_lane_id, 0b0000000, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
-scom 0x800D1C0002011E3F { 
-	bits, scom_data, expr;
-	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
-scom 0x800D240002011E3F { 
-	bits, scom_data, expr;
-	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXCTL.TX_CTL_REGS.TX_MODE_PG
-scom 0x800C1C0002011E3F { 
-	bits, scom_data, expr;
-	tx_max_bad_lanes, 0b00010, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340002011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340102011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b001, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340202011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b010, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340302011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b011, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340402011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b100, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340502011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b101, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340602011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b110, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340702011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b111, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004341002011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340F02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b001, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340E02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b010, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340D02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b011, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340C02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b100, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340B02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b101, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340A02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b110, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340902011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b111, def_bus_id0;
-}
-
-#TX_WRAP.TX0.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004340802011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id0;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
-scom 0x800CC42002011E3F { 
-	bits, scom_data, expr;
 	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID1_PG
-scom 0x800C942002011E3F { 
-	bits, scom_data, expr;
-	tx_bus_id, 0b000001, def_bus_id1;
-	tx_group_id, 0b100000, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID2_PG
-scom 0x800C9C2002011E3F { 
-	bits, scom_data, expr;
-	tx_last_group_id, 0b100000, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_ID3_PG
-scom 0x800CA42002011E3F { 
-	bits, scom_data, expr;
-	tx_end_lane_id, 0b0010000, def_bus_id1;
-	tx_start_lane_id, 0b0000000, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
-scom 0x800D1C2002011E3F { 
-	bits, scom_data, expr;
-	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
-scom 0x800D242002011E3F { 
-	bits, scom_data, expr;
-	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXCTL.TX_CTL_REGS.TX_MODE_PG
-scom 0x800C1C2002011E3F { 
-	bits, scom_data, expr;
-	tx_max_bad_lanes, 0b00010, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342002011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342102011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b001, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342202011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b010, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342302011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b011, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342402011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b100, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342502011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b101, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342602011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b110, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342702011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b111, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004343002011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342F02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b001, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342E02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b010, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342D02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b011, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342C02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b100, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342B02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b101, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342A02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b110, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342902011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b111, def_bus_id1;
-}
-
-#TX_WRAP.TX1.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004342802011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id1;
-}
-
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
-scom 0x800CC44002011E3F { 
-	bits, scom_data, expr;
 	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id2;
 }
 
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID1_PG
-scom 0x800C944002011E3F { 
-	bits, scom_data, expr;
-	tx_bus_id, 0b000010, def_bus_id2;
-	tx_group_id, 0b100000, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID2_PG
-scom 0x800C9C4002011E3F { 
-	bits, scom_data, expr;
-	tx_last_group_id, 0b100000, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_ID3_PG
-scom 0x800CA44002011E3F { 
-	bits, scom_data, expr;
-	tx_end_lane_id, 0b0010000, def_bus_id2;
-	tx_start_lane_id, 0b0000000, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
-scom 0x800D1C4002011E3F { 
-	bits, scom_data, expr;
-	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
-scom 0x800D244002011E3F { 
-	bits, scom_data, expr;
-	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXCTL.TX_CTL_REGS.TX_MODE_PG
-scom 0x800C1C4002011E3F { 
-	bits, scom_data, expr;
-	tx_max_bad_lanes, 0b00010, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344002011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344102011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b001, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344202011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b010, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344302011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b011, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344402011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b100, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344502011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b101, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344602011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b110, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344702011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b111, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004345002011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344F02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b001, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344E02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b010, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344D02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b011, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344C02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b100, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344B02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b101, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344A02011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b110, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344902011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b111, def_bus_id2;
-}
-
-#TX_WRAP.TX2.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004344802011E3F { 
-	bits, scom_data, expr;
-	tx_prbs_tap_id, 0b000, def_bus_id2;
-}
-
-#TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_CLK_CNTL_GCRMSG_PG
-scom 0x800CC46002011E3F { 
-	bits, scom_data, expr;
-	tx_drv_clk_pattern_gcrmsg, 0b00, def_bus_id3;
-}
-
 #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID1_PG
-scom 0x800C946002011E3F { 
+scom 0x800C946002011A3F { 
 	bits, scom_data, expr;
 	tx_bus_id, 0b000011, def_bus_id3;
+	tx_bus_id, 0b000000, def_bus_id0;
+	tx_bus_id, 0b000001, def_bus_id1;
+	tx_bus_id, 0b000010, def_bus_id2;
 	tx_group_id, 0b100000, def_bus_id3;
+	tx_group_id, 0b100000, def_bus_id0;
+	tx_group_id, 0b100000, def_bus_id1;
+	tx_group_id, 0b100000, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID2_PG
-scom 0x800C9C6002011E3F { 
+scom 0x800C9C6002011A3F { 
 	bits, scom_data, expr;
 	tx_last_group_id, 0b100000, def_bus_id3;
+	tx_last_group_id, 0b100000, def_bus_id0;
+	tx_last_group_id, 0b100000, def_bus_id1;
+	tx_last_group_id, 0b100000, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_ID3_PG
-scom 0x800CA46002011E3F { 
+scom 0x800CA46002011A3F { 
 	bits, scom_data, expr;
 	tx_end_lane_id, 0b0010000, def_bus_id3;
+	tx_end_lane_id, 0b0010000, def_bus_id0;
+	tx_end_lane_id, 0b0010000, def_bus_id1;
+	tx_end_lane_id, 0b0010000, def_bus_id2;
 	tx_start_lane_id, 0b0000000, def_bus_id3;
+	tx_start_lane_id, 0b0000000, def_bus_id0;
+	tx_start_lane_id, 0b0000000, def_bus_id1;
+	tx_start_lane_id, 0b0000000, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_0_15_PG
-scom 0x800D1C6002011E3F { 
+scom 0x800D1C6002011A3F { 
 	bits, scom_data, expr;
 	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id3;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id0;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id1;
+	tx_lane_disabled_vec_0_15, 0b0000000000000000, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_LANE_DISABLED_VEC_16_31_PG
-scom 0x800D246002011E3F { 
+scom 0x800D246002011A3F { 
 	bits, scom_data, expr;
 	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id3;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id0;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id1;
+	tx_lane_disabled_vec_16_31, 0b0111111111111111, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXCTL.TX_CTL_REGS.TX_MODE_PG
-scom 0x800C1C6002011E3F { 
+scom 0x800C1C6002011A3F { 
 	bits, scom_data, expr;
 	tx_max_bad_lanes, 0b00010, def_bus_id3;
+	tx_max_bad_lanes, 0b00010, def_bus_id0;
+	tx_max_bad_lanes, 0b00010, def_bus_id1;
+	tx_max_bad_lanes, 0b00010, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346002011E3F { 
+scom 0x8004346002011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b000, def_bus_id3;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346102011E3F { 
+scom 0x8004346102011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b001, def_bus_id3;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346202011E3F { 
+scom 0x8004346202011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b010, def_bus_id3;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#0.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346302011E3F { 
+scom 0x8004346302011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b011, def_bus_id3;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346402011E3F { 
+scom 0x8004346402011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b100, def_bus_id3;
+	tx_prbs_tap_id, 0b100, def_bus_id0;
+	tx_prbs_tap_id, 0b100, def_bus_id1;
+	tx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346502011E3F { 
+scom 0x8004346502011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b101, def_bus_id3;
+	tx_prbs_tap_id, 0b101, def_bus_id0;
+	tx_prbs_tap_id, 0b101, def_bus_id1;
+	tx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346602011E3F { 
+scom 0x8004346602011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b110, def_bus_id3;
+	tx_prbs_tap_id, 0b110, def_bus_id0;
+	tx_prbs_tap_id, 0b110, def_bus_id1;
+	tx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#1.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346702011E3F { 
+scom 0x8004346702011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b111, def_bus_id3;
+	tx_prbs_tap_id, 0b111, def_bus_id0;
+	tx_prbs_tap_id, 0b111, def_bus_id1;
+	tx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004347002011E3F { 
+scom 0x8004347002011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b000, def_bus_id3;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346F02011E3F { 
+scom 0x8004346F02011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b001, def_bus_id3;
+	tx_prbs_tap_id, 0b001, def_bus_id0;
+	tx_prbs_tap_id, 0b001, def_bus_id1;
+	tx_prbs_tap_id, 0b001, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346E02011E3F { 
+scom 0x8004346E02011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b010, def_bus_id3;
+	tx_prbs_tap_id, 0b010, def_bus_id0;
+	tx_prbs_tap_id, 0b010, def_bus_id1;
+	tx_prbs_tap_id, 0b010, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#2.TXPACK_DEFAULT.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346D02011E3F { 
+scom 0x8004346D02011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b011, def_bus_id3;
+	tx_prbs_tap_id, 0b011, def_bus_id0;
+	tx_prbs_tap_id, 0b011, def_bus_id1;
+	tx_prbs_tap_id, 0b011, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#0.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346C02011E3F { 
+scom 0x8004346C02011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b100, def_bus_id3;
+	tx_prbs_tap_id, 0b100, def_bus_id0;
+	tx_prbs_tap_id, 0b100, def_bus_id1;
+	tx_prbs_tap_id, 0b100, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#1.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346B02011E3F { 
+scom 0x8004346B02011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b101, def_bus_id3;
+	tx_prbs_tap_id, 0b101, def_bus_id0;
+	tx_prbs_tap_id, 0b101, def_bus_id1;
+	tx_prbs_tap_id, 0b101, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#2.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346A02011E3F { 
+scom 0x8004346A02011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b110, def_bus_id3;
+	tx_prbs_tap_id, 0b110, def_bus_id0;
+	tx_prbs_tap_id, 0b110, def_bus_id1;
+	tx_prbs_tap_id, 0b110, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#3.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346902011E3F { 
+scom 0x8004346902011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b111, def_bus_id3;
+	tx_prbs_tap_id, 0b111, def_bus_id0;
+	tx_prbs_tap_id, 0b111, def_bus_id1;
+	tx_prbs_tap_id, 0b111, def_bus_id2;
 }
 
 #TX_WRAP.TX3.TXPACKS#3.TXPACK_3.TXPACK.DD.SLICE#4.TD.TX_BIT_REGS.TX_PRBS_MODE_PL
-scom 0x8004346802011E3F { 
+scom 0x8004346802011A3F { 
 	bits, scom_data, expr;
 	tx_prbs_tap_id, 0b000, def_bus_id3;
+	tx_prbs_tap_id, 0b000, def_bus_id0;
+	tx_prbs_tap_id, 0b000, def_bus_id1;
+	tx_prbs_tap_id, 0b000, def_bus_id2;
 }
 
 
diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
index ef2c6b7b7..1914e579c 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.mcs.scom.initfile,v 1.1 2012/10/08 03:24:14 jmcgill Exp $
+#-- $Id: p8.mcs.scom.initfile,v 1.2 2013/03/25 03:08:07 jmcgill Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
@@ -16,7 +16,7 @@ SyntaxVersion = 1
 
 
 #--******************************************************************************
-#-- MC Mode0 Register Ship Mode
+#-- MCS Mode0 Register
 #--******************************************************************************
  scom 0x0000000002011807              {
      bits ,                    scom_data        ;
@@ -52,7 +52,7 @@ SyntaxVersion = 1
 
 
 #--******************************************************************************
-#-- MC Mode2 Register Ship Mode
+#-- MCS Mode2 Register
 #--******************************************************************************
  scom 0x0000000002011809              {
      bits ,                    scom_data        ;
@@ -72,14 +72,14 @@ SyntaxVersion = 1
      36:38,                    0b010            ;              # MCMODE2Q_CHANNEL_ARB_WRITE_HP_THRESHOLD
      39   ,                    0b0              ;              # MCMODE2Q_DISABLE_BAD_CRESP_TO_CENTAUR
      40   ,                    0b1              ;              # MCMODE2Q_ENABLE_CRC_BYPASS_ALWAYS
-     41:43,                    0b111            ;              # MCMODE2Q_CHANNEL_HANG_VALUE
+     41:43,                    0b011            ;              # MCMODE2Q_CHANNEL_HANG_VALUE
      44   ,                    0b1              ;              # MCMODE2Q_ENABLE_RD_HANG
      45   ,                    0b1              ;              # MCMODE2Q_ENABLE_WR_HANG
      46   ,                    0b1              ;              # MCMODE2Q_ENABLE_MIRROR_RD_HANG
      47   ,                    0b1              ;              # MCMODE2Q_ENABLE_MIRROR_WR_HANG
      48   ,                    0b1              ;              # MCMODE2Q_ENABLE_AO_HANG
      49   ,                    0b1              ;              # MCMODE2Q_ENABLE_INBAND_HANG
-     50:52,                    0b111            ;              # MCMODE2Q_NONMIRROR_HANG_VALUE
+     50:52,                    0b110            ;              # MCMODE2Q_NONMIRROR_HANG_VALUE
      53:55,                    0b111            ;              # MCMODE2Q_MIRROR_HANG_VALUE
      56   ,                    0b1              ;              # MCMODE2Q_ENABLE_EMER_THROTTLE
      57   ,                    0b0              ;              # MCMODE2Q_DRIVE_SHARED_PRESP_WITH_LOST_CLAIM
@@ -94,7 +94,26 @@ SyntaxVersion = 1
 
 
 #--******************************************************************************
-#-- MC Busy Control Register Ship Mode
+#-- MCS Mode3 Register
+#--******************************************************************************
+ scom 0x000000000201180A              {
+     bits ,                    scom_data        ;
+     24   ,                    0b1              ;              # MCMODE3Q_ENABLE_LOCAL_TIMEOUT_TIMEBASE
+     25:30,                    0b000001         ;              # MCMODE3Q_LOCAL_TIMEOUT_TIMEBASE_THRESHOLD
+}
+
+
+#--******************************************************************************
+#-- MCS Mode4 Register
+#--******************************************************************************
+ scom 0x000000000201181A              {
+     bits ,                    scom_data        ;
+     17:18,                    0b01             ;              # MCMODE4Q_SELECT_RPTHANG_DECODE
+     19   ,                    0b1              ;              # MCMODE4Q_LOCAL_TIMEBASE_SELECT
+}
+
+#--******************************************************************************
+#-- MC Busy Control Register
 #--******************************************************************************
  scom 0x0000000002011818              {
      bits ,                    scom_data        ;
diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
index fb1836b0a..c1df2f029 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.nx.scom.initfile,v 1.3 2013/01/25 16:23:46 johnre Exp $
+#-- $Id: p8.nx.scom.initfile,v 1.5 2013/03/25 21:38:50 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -138,7 +138,6 @@ scom 0x0201308F {
 #-- PowerBus Epsilon Config Register (0x0201309D)
 scom 0x0201309D {
     bits  ,  scom_data      ;
-     0:5  ,  0b000101       ;  #-- epsilon count value.  number * 7 clock cycles.
      6    ,  0b0            ;  #-- disable epsilon counter
 }
 
@@ -334,4 +333,20 @@ scom 0x02013107 {
 
 
 
+#-- APC Master Config Register
+scom 0x02013019 {
+    bits  , scom_data       ;
+    4:7   , 0b0000          ;   #-- HANG_POLL_SCALE
+}
+
+#-- CAPP Snoop Control Register
+scom 0x0201301B {
+    bits  ,  scom_data      ;
+    48:51 ,  0b0010         ;   #-- CXA_SNP_DATA_HANG_POLL_SCALE
+}
 
+#-- CAPP Transport Control Register
+scom 0x0201301C {
+    bits  ,  scom_data      ;
+    15:18 ,  0b1000         ;   #-- TLBI_DATA_POLL_PULSE_DIV
+}
diff --git a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile
index 9fd4dcecb..8d4ebdf5b 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.pe.phase2.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.pe.phase2.scom.initfile,v 1.1 2012/11/05 21:39:35 jmcgill Exp $
+#-- $Id: p8.pe.phase2.scom.initfile,v 1.2 2013/03/25 03:08:11 jmcgill Exp $
 #-------------------------------------------------------------------------------
 #--
 #-- (C) Copyright International Business Machines Corp. 2011
@@ -40,6 +40,9 @@ scom 0x02012(0,4,8)0B {
 #-- PCI Hardware Configuration 0 Register
 scom 0x02012(0,4,8)18 {
     bits,    scom_data;
+    0:3,     0b0001;                                                #-- hang poll scale = 1
+    4:7,     0b0010;                                                #-- data poll scale = 2
+    8:11,    0b0001;                                                #-- data poll scale (PE) = 1
     17,      0b1;                                                   #-- disable out-of-order store behavior
 }
 
diff --git a/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile
new file mode 100644
index 000000000..a62edd656
--- /dev/null
+++ b/src/usr/hwpf/hwp/initfiles/p8.tpbridge.scom.initfile
@@ -0,0 +1,53 @@
+#-- $Id: p8.tpbridge.scom.initfile,v 1.1 2013/03/25 03:07:40 jmcgill Exp $
+#-------------------------------------------------------------------------------
+#--
+#-- (C) Copyright International Business Machines Corp. 2011
+#-- All Rights Reserved -- Property of IBM
+#-- *** IBM Confidential ***
+#--
+#-- TITLE       : p8.tpbridge.scom.initfile
+#-- DESCRIPTION : Perform SCOM configuration for TP bridge units
+#--
+#-- OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
+#--
+#--------------------------------------------------------------------------------
+
+SyntaxVersion = 1
+
+#--------------------------------------------------------------------------------
+#-- Includes
+#--------------------------------------------------------------------------------
+
+
+#--------------------------------------------------------------------------------
+#-- HTM SCOM initializations
+#--------------------------------------------------------------------------------
+
+# HTM Configuration Register
+scom 0x02010888 {
+    bits,    scom_data;
+    0:4,     0b00001; # oper hang divider = 1
+}
+
+
+#--------------------------------------------------------------------------------
+#-- ICP SCOM initializations
+#--------------------------------------------------------------------------------
+
+# ICP Mode Register 0
+scom 0x020109CB {
+    bits,    scom_data;
+    15:19,   0b00001; # oper hang divider = 1
+    23:27,   0b00011; # data hang divider = 3
+}
+
+
+#--------------------------------------------------------------------------------
+#-- HCA SCOM initializations
+#--------------------------------------------------------------------------------
+
+# HCA Mode Register
+scom 0x0201094F {
+    bits,    scom_data;
+    16:20,   0b00011; # oper/data hang divider = 3 (HW242836)
+}
diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
index 63759d6da..18c8cc48d 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.custom.scom.initfile
@@ -1,13 +1,21 @@
-#-- $Id: p8.xbus.custom.scom.initfile,v 1.1 2013/02/04 19:52:00 thomsen Exp $
+#-- $Id: p8.xbus.custom.scom.initfile,v 1.3 2013/03/15 21:18:37 thomsen Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.3 |jgrell  |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab.
+#--     1.2 |thomsen |02/13/13|Cleaned up and Added Commented-out Lane Power Ups
+#--         |        |        |Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
 #--     1.1 |thomsen |01/29/13|Created initial version
 #-- --------|--------|--------|--------------------------------------------------
 #--------------------------------------------------------------------------------
 # End of revision history
 #--------------------------------------------------------------------------------
+#-- TARGETS:
+#-- SYS. Chiplet target
+#-- TGT1. Proc target
+#-- TGT2. Connected Chiplet target
+#-- TGT3. Connected Proc target
 
 #--Master list of variables that can be used in this file is at:
 #--<Attribute Definition Location>
@@ -34,110 +42,74 @@ include ei4.io.define
 #-- -----------------------------------------------------------------------------
 #--******************************************************************************
 #-- -----------------------------------------------------------------------------
+define def_IS_HW  = (SYS.ATTR_IS_SIMULATION == 0);
+define def_IS_VBU = (SYS.ATTR_IS_SIMULATION == 1);
 
-## ./iotk put rx_fence=1
-## 0x
-#scom 0x800.0b(rx_fence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_fence,                 0b1;
-#}
-#
-## ./iotk put rx_c4_sel=00
-## ./iotk put rx_prot_speed_slct=1
-## 0x8009C00002011E3F 
-#scom 0x800.0b(rx_misc_analog_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_c4_sel,                0b00;
-#rx_prot_speed_slct,       0b1;
-#}
-## ./iotk put rx_servo_timeout_sel_D=1001
-## 0x800B600002011E3F 
-#scom 0x800.0b(rx_servo_to1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_servo_timeout_sel_d,   0b1001;
-#}
-## ./iotk put rx_servo_timeout_sel_H=1110
-## 0x800B680002011E3F 
-#scom 0x800.0b(rx_servo_to2_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_servo_timeout_sel_h,   0b1110;
-#}
-## ./iotk put rx_servo_timeout_sel_I=1011
-## ./iotk put rx_servo_timeout_sel_J=1100
-## 0x800B700002011E3F 
-#scom 0x800.0b(rx_servo_to3_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_servo_timeout_sel_i,   0b1011;
-#rx_servo_timeout_sel_j,   0b1100;
-#rx_servo_timeout_sel_k,   0b1101;
-#}
-## ./iotk put rx_wt_timeout_sel=111
-## ./iotk put rx_ds_bl_timeout_sel=101
-## ./iotk put rx_ds_timeout_sel=110
-##./iotk put rx_sls_timeout_sel=111
-## 0x8008980002011E3F 
-#scom 0x800.0b(rx_timeout_sel_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_wt_timeout_sel,        0b111;
-#rx_ds_bl_timeout_sel,     0b101;
-#rx_ds_timeout_sel,        0b110;
-#rx_sls_timeout_sel,       0b001;
-#}
-#
-## ./iotk put rx_bit_lock_timeout_sel=110
-## 0x800B080002011E3F 
-#scom 0x800.0b(rx_mode1_pp)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_bit_lock_timeout_sel,  0b110;
-#}
-## ./iotk put rx_eo_offset_timeout_sel=111
-## ./iotk put rx_eo_amp_timeout_sel=111
-## ./iotk put rx_eo_ctle_timeout_sel=111
-## ./iotk put rx_eo_h1ap_timeout_sel=111
-## ./iotk put rx_eo_ddc_timeout_sel=111
-## 0x8009100002011E3F 
-#scom 0x800.0b(rx_timeout_sel1_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                     scom_data;
-#rx_eo_offset_timeout_sel, 0b111;
-#rx_eo_amp_timeout_sel,    0b111;
-#rx_eo_ctle_timeout_sel,   0b111;
-#rx_eo_h1ap_timeout_sel,   0b111;
-#rx_eo_ddc_timeout_sel,    0b111;
-#}
-#
-#
-## 800A380002011E3F
-#scom 0x800.0b(rx_eo_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                               scom_data;
-#rx_eo_enable_latch_offset_cal,      0b1;
-#rx_eo_enable_ctle_cal,              0b1;
-#rx_eo_enable_vga_cal,               0b1;
-#rx_eo_enable_dfe_h1_cal,            0b1;
-#rx_eo_enable_h1ap_tweak,            0b1;
-#rx_eo_enable_ddc,                   0b1;
-#rx_eo_enable_final_l2u_adj,         0b1;
-#rx_eo_enable_ber_test,              0b1;
-#rx_eo_enable_result_check,          0b1;
-#}
-#
-#scom 0x800.0b(rx_eo_convergence_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                               scom_data;
-#rx_eo_converged_end_count,          0b111;
+define def_all_lanes=11111;
+
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#-- Overrides
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+
+#--***********************************************************************************
+#-------------------------------------------------------------------------------------
+#     __                        ____                             __  __
+#    / /   ____ _____  ___     / __ \____ _      _____  _____   / / / /___
+#   / /   / __ `/ __ \/ _ \   / /_/ / __ \ | /| / / _ \/ ___/  / / / / __ \
+#  / /___/ /_/ / / / /  __/  / ____/ /_/ / |/ |/ /  __/ /     / /_/ / /_/ /
+# /_____/\__,_/_/ /_/\___/  /_/    \____/|__/|__/\___/_/      \____/ .___/
+#                                                                 /_/
+#-------------------------------------------------------------------------------------
+#--***********************************************************************************
+
+## rx_lane_pdwn
+#scom 0x800.0b(rx_mode_pl)(rx_grp0)(def_all_lanes).0x(xbus0_gcr_addr){
+#    bits,            scom_data;
+#    rx_lane_pdwn,    0b0;
 #}
 #
-## 0x800AB80002011E3F
-#scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr,xbus1_gcr_addr,xbus2_gcr_addr,xbus3_gcr_addr) {
-#bits,                               scom_data;
-#rx_rc_enable_latch_offset_cal,      0b1;
-#rx_rc_enable_ctle_cal,              0b1;
-#rx_rc_enable_vga_cal,               0b1;
-#rx_rc_enable_h1ap_tweak,            0b1;
-#rx_rc_enable_ddc,                   0b1;
-#rx_rc_enable_ber_test,              0b1;
-#rx_rc_enable_result_check,          0b1;
-##rx_rc_enable_dfe_h1_cal,           0b0; # Leave DFE off during recal for now
+## tx_lane_pdwn
+#scom 0x800.0b(tx_mode_pl)(tx_grp0)(def_all_lanes).0x(xbus0_gcr_addr){
+#    bits,            scom_data;
+#    tx_lane_pdwn,    0b0;
 #}
 
+#--**************************************************************************************************************
+#----------------------------------------------------------------------------------------------------------------
+#    ________________     ____        ________             ____             _ __           __  ___           __  
+#   / ____/ ____/ __ \   / __ )__  __/ __/ __/__  _____   / __ \____ ______(_) /___  __   /  |/  /___ ______/ /__
+#  / / __/ /   / /_/ /  / __  / / / / /_/ /_/ _ \/ ___/  / /_/ / __ `/ ___/ / __/ / / /  / /|_/ / __ `/ ___/ //_/
+# / /_/ / /___/ _, _/  / /_/ / /_/ / __/ __/  __/ /     / ____/ /_/ / /  / / /_/ /_/ /  / /  / / /_/ (__  ) ,<   
+# \____/\____/_/ |_|  /_____/\__,_/_/ /_/  \___/_/     /_/    \__,_/_/  /_/\__/\__, /  /_/  /_/\__,_/____/_/|_|  
+#                                                                             /____/                             
+#----------------------------------------------------------------------------------------------------------------
+#--**************************************************************************************************************
+# HW242564: Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
+# 0x800???0002011E3F
+# This is applied to all configured clkgrp's via chiplet targetting
+scom 0x800.0b(rx_fir1_mask_pg)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
+bits,                             scom_data;
+rx_pg_fir_err_mask_gcr_buff,      0b1;
+}
+scom 0x800.0b(tx_fir_mask_pg)(tx_grp0,tx_grp1,tx_grp2,tx_grp3)(lane_na).0x(xbus0_gcr_addr) {
+bits,                             scom_data;
+tx_pg_fir_err_mask_gcr_buff,      0b1;
+}
+scom 0x800.0b(rx_fir_mask_pb)(rx_grp0,rx_grp1,rx_grp2,rx_grp3)(lane_na).0x(xbus0_gcr_addr) {
+bits,                             scom_data;
+rx_pb_fir_err_mask_gcr_buff0,    0b1;
+rx_pb_fir_err_mask_gcr_buff1,    0b1;
+rx_pb_fir_err_mask_gcr_buff2,    0b1;
+}
+
+# Mask off all rx and tx parity errors in the fir register
+scom 0x04011003 {
+scom_data;
+0xC000000000000000;
+}
+
 
 ############################################################################################
 # END OF FILE
diff --git a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile
index 9b5a593d9..58c7f4439 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.xbus.scom.initfile
@@ -1,19 +1,21 @@
-#-- $Id: p8.xbus.scom.initfile,v 1.6 2013/02/06 22:20:58 thomsen Exp $ 
+#-- $Id: p8.xbus.scom.initfile,v 1.8 2013/03/22 20:34:43 jgrell Exp $ 
 
 
 ####################################################################
 ##  
 ##  Auto-genrated by fig2scominit.pl
-##      Based on SETUP_ID_MODE X_BUS_8B_TR_HW RX_MASTER_MODE MASTER
+##      Based on SETUP_ID_MODE X_BUS_8B_TR_HW
 ##      from ../../logic/mesa_sim/fusion/run/IOEPC_XBUS_WRAP.IOEPC_XBUS_WRAP.figdb
 ##
-##   Created on Wed Feb  6 11:20:13 EST 2013, by derrin
+##   Created on Fri Mar 22 14:31:30 CDT 2013, by jgrell
 ####################################################################
 
 ## -- CHANGE HISTORY:
  ## --------------------------------------------------------------------------------
  ## -- Version:|Author:  | Date:  | Comment:
  ## -- --------|---------|--------|-------------------------------------------------
+ ## -- jgr13031300| jgr     |03-13-13| Added missing entries from rel 0128
+ ## -- 13030500| thomsen |03-05-13| Added DLL settings for HW241376
  ## -- 13011802| mbs     |01-18-13| Added rx_fence to run_mode dial (HW236326)
  ## -- 12112700| SMR     |11-27-12| HW20806: Added rx_sls_extend_sel default of 0b101 (slave side only!)
  ## -- 12111300| berger  |11-13-12| Updated with HW eyeopt and recal settings
@@ -56,8 +58,8 @@ SyntaxVersion = 1
 ####################################################################
 include ei4.io.define
 
-                    define HW_EXPRESS = SYS.ATTR_IS_SIMULATION == 0;
-                    define VBU_EXPRESS = SYS.ATTR_IS_SIMULATION == 1;
+                    define def_IS_HW  = SYS.ATTR_IS_SIMULATION == 0;
+                    define def_IS_VBU = SYS.ATTR_IS_SIMULATION == 1;
                 
 
 define def_bus_id0 = (ATTR_CHIP_UNIT_POS == 0);
@@ -65,12 +67,26 @@ define def_bus_id1 = (ATTR_CHIP_UNIT_POS == 1);
 define def_bus_id2 = (ATTR_CHIP_UNIT_POS == 2);
 define def_bus_id3 = (ATTR_CHIP_UNIT_POS == 3);
 
-define def_is_master = (TGT1.ATTR_FABRIC_CHIP_ID < TGT3.ATTR_FABRIC_CHIP_ID);
-define def_is_slave  = (TGT1.ATTR_FABRIC_CHIP_ID > TGT3.ATTR_FABRIC_CHIP_ID);
+define prim_id = (TGT1.ATTR_FABRIC_NODE_ID*100) + TGT1.ATTR_POS;
+define conn_id = (TGT3.ATTR_FABRIC_NODE_ID*100) + TGT3.ATTR_POS;
+
+define def_is_master = (prim_id < conn_id);
+define def_is_slave  = (prim_id > conn_id);
 
 define xbus_base_addr = xbus0_gcr_addr;
 
 
+#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG
+scom 0x800E7800(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_dll1_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll1_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll2_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll2_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll_vreg_compcon,  0b101   , def_IS_HW;
+     rx_dll_vreg_compcon,  0b000  , def_IS_VBU;
+}
+
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
 scom 0x8009D800(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -89,80 +105,80 @@ scom 0x800AE000(xbus_base_addr) {
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP
 scom 0x800B1800(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_ddc_use_cyc_block_lock,  0b0   , HW_EXPRESS;
-     rx_ddc_use_cyc_block_lock,  0b1  , VBU_EXPRESS;
+     rx_ddc_use_cyc_block_lock,  0b0   , def_IS_HW;
+     rx_ddc_use_cyc_block_lock,  0b1  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP
 scom 0x800B3000(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_dec_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_dec_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_dec_val_a,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_dec_val_b,  0b0001   , def_IS_HW;
+     rx_cal_dec_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_c,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_d,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP
 scom 0x800B3800(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_dec_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_dec_val_e,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_dec_val_f,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_g,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_h,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP
 scom 0x800B2000(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_inc_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_inc_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_inc_val_a,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_inc_val_b,  0b0001   , def_IS_HW;
+     rx_cal_inc_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_c,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_d,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP
 scom 0x800B2800(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_inc_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_inc_val_e,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_inc_val_f,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_g,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_h,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
 scom 0x800A3800(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ber_test,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_ber_test,  0b1   , def_IS_HW;
+     rx_eo_enable_ber_test,  0b0  , def_IS_VBU;
+     rx_eo_enable_ctle_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_ctle_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_dcd_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_dcd_cal,  0b0  , def_IS_VBU;
 	rx_eo_enable_final_l2u_adj, 0b1, any;
-     rx_eo_enable_latch_offset_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_latch_offset_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_eo_enable_result_check,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_vref_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_vref_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_latch_offset_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_latch_offset_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_eo_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_eo_enable_result_check,  0b1   , def_IS_HW;
+     rx_eo_enable_result_check,  0b0  , def_IS_VBU;
+     rx_eo_enable_vref_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_vref_cal,  0b0  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG
@@ -203,6 +219,13 @@ scom 0x80093000(xbus_base_addr) {
 	rx_lane_disabled_vec_16_31, 0b0000111111111111, any;
 }
 
+#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP
+scom 0x800B0800(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_bit_lock_timeout_sel,  0b110   , def_IS_HW;
+     rx_bit_lock_timeout_sel,  0b101  , def_IS_VBU;
+}
+
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG
 scom 0x80081800(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -212,34 +235,36 @@ scom 0x80081800(xbus_base_addr) {
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
 scom 0x800AB800(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_rc_enable_dll_update,  0b1   , HW_EXPRESS;
-     rx_rc_enable_dll_update,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_edge_track,  0b1   , HW_EXPRESS;
-     rx_rc_enable_edge_track,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_rc_enable_result_check,  0b0  , VBU_EXPRESS;
+     rx_rc_enable_dll_update,  0b1   , def_IS_HW;
+     rx_rc_enable_dll_update,  0b0  , def_IS_VBU;
+     rx_rc_enable_edge_track,  0b1   , def_IS_HW;
+     rx_rc_enable_edge_track,  0b0  , def_IS_VBU;
+     rx_rc_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_rc_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_rc_enable_result_check,  0b1   , def_IS_HW;
+     rx_rc_enable_result_check,  0b0  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
 scom 0x800B6000(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_a,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_a,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1010   , HW_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_c,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_c,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_a,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_a,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_b,  0b1010   , def_IS_HW;
+     rx_servo_timeout_sel_b,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_c,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_c,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_d,  0b1001   , def_IS_HW;
+     rx_servo_timeout_sel_d,  0b0101  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
 scom 0x800B6800(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b1000   , HW_EXPRESS;
-     rx_servo_timeout_sel_f,  0b0110  , VBU_EXPRESS;
-     rx_servo_timeout_sel_h,  0b0110   , HW_EXPRESS;
-     rx_servo_timeout_sel_h,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_f,  0b1000   , def_IS_HW;
+     rx_servo_timeout_sel_f,  0b0110  , def_IS_VBU;
+     rx_servo_timeout_sel_h,  0b1110   , def_IS_HW;
+     rx_servo_timeout_sel_h,  0b1000  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG
@@ -248,10 +273,27 @@ scom 0x80080800(xbus_base_addr) {
 	rx_sls_extend_sel, 0b101, def_is_slave;
 }
 
+#RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG
+scom 0x80091000(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_eo_ctle_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_ctle_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_offset_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_offset_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_vref_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_vref_timeout_sel,  0b110  , def_IS_VBU;
+}
+
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
 scom 0x80089800(xbus_base_addr) { 
 	bits, scom_data, expr;
+     rx_ds_bl_timeout_sel,  0b101   , def_IS_HW;
+     rx_ds_bl_timeout_sel,  0b001  , def_IS_VBU;
+     rx_ds_timeout_sel,  0b110   , def_IS_HW;
+     rx_ds_timeout_sel,  0b010  , def_IS_VBU;
 	rx_sls_timeout_sel, 0b001, any;
+     rx_wt_timeout_sel,  0b111   , def_IS_HW;
+     rx_wt_timeout_sel,  0b011  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
@@ -387,6 +429,17 @@ scom 0x8000B013(xbus_base_addr) {
 	rx_prbs_tap_id, 0b000, any;
 }
 
+#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG
+scom 0x800E7820(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_dll1_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll1_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll2_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll2_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll_vreg_compcon,  0b101   , def_IS_HW;
+     rx_dll_vreg_compcon,  0b000  , def_IS_VBU;
+}
+
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
 scom 0x8009D820(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -405,80 +458,80 @@ scom 0x800AE020(xbus_base_addr) {
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP
 scom 0x800B1820(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_ddc_use_cyc_block_lock,  0b0   , HW_EXPRESS;
-     rx_ddc_use_cyc_block_lock,  0b1  , VBU_EXPRESS;
+     rx_ddc_use_cyc_block_lock,  0b0   , def_IS_HW;
+     rx_ddc_use_cyc_block_lock,  0b1  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP
 scom 0x800B3020(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_dec_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_dec_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_dec_val_a,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_dec_val_b,  0b0001   , def_IS_HW;
+     rx_cal_dec_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_c,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_d,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP
 scom 0x800B3820(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_dec_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_dec_val_e,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_dec_val_f,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_g,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_h,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP
 scom 0x800B2020(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_inc_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_inc_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_inc_val_a,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_inc_val_b,  0b0001   , def_IS_HW;
+     rx_cal_inc_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_c,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_d,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP
 scom 0x800B2820(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_inc_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_inc_val_e,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_inc_val_f,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_g,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_h,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
 scom 0x800A3820(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ber_test,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_ber_test,  0b1   , def_IS_HW;
+     rx_eo_enable_ber_test,  0b0  , def_IS_VBU;
+     rx_eo_enable_ctle_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_ctle_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_dcd_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_dcd_cal,  0b0  , def_IS_VBU;
 	rx_eo_enable_final_l2u_adj, 0b1, any;
-     rx_eo_enable_latch_offset_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_latch_offset_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_eo_enable_result_check,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_vref_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_vref_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_latch_offset_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_latch_offset_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_eo_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_eo_enable_result_check,  0b1   , def_IS_HW;
+     rx_eo_enable_result_check,  0b0  , def_IS_VBU;
+     rx_eo_enable_vref_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_vref_cal,  0b0  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG
@@ -519,6 +572,13 @@ scom 0x80093020(xbus_base_addr) {
 	rx_lane_disabled_vec_16_31, 0b0000111111111111, any;
 }
 
+#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE1_PP
+scom 0x800B0820(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_bit_lock_timeout_sel,  0b110   , def_IS_HW;
+     rx_bit_lock_timeout_sel,  0b101  , def_IS_VBU;
+}
+
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG
 scom 0x80081820(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -528,34 +588,36 @@ scom 0x80081820(xbus_base_addr) {
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
 scom 0x800AB820(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_rc_enable_dll_update,  0b1   , HW_EXPRESS;
-     rx_rc_enable_dll_update,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_edge_track,  0b1   , HW_EXPRESS;
-     rx_rc_enable_edge_track,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_rc_enable_result_check,  0b0  , VBU_EXPRESS;
+     rx_rc_enable_dll_update,  0b1   , def_IS_HW;
+     rx_rc_enable_dll_update,  0b0  , def_IS_VBU;
+     rx_rc_enable_edge_track,  0b1   , def_IS_HW;
+     rx_rc_enable_edge_track,  0b0  , def_IS_VBU;
+     rx_rc_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_rc_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_rc_enable_result_check,  0b1   , def_IS_HW;
+     rx_rc_enable_result_check,  0b0  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
 scom 0x800B6020(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_a,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_a,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1010   , HW_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_c,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_c,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_a,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_a,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_b,  0b1010   , def_IS_HW;
+     rx_servo_timeout_sel_b,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_c,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_c,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_d,  0b1001   , def_IS_HW;
+     rx_servo_timeout_sel_d,  0b0101  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
 scom 0x800B6820(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b1000   , HW_EXPRESS;
-     rx_servo_timeout_sel_f,  0b0110  , VBU_EXPRESS;
-     rx_servo_timeout_sel_h,  0b0110   , HW_EXPRESS;
-     rx_servo_timeout_sel_h,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_f,  0b1000   , def_IS_HW;
+     rx_servo_timeout_sel_f,  0b0110  , def_IS_VBU;
+     rx_servo_timeout_sel_h,  0b1110   , def_IS_HW;
+     rx_servo_timeout_sel_h,  0b1000  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG
@@ -564,10 +626,27 @@ scom 0x80080820(xbus_base_addr) {
 	rx_sls_extend_sel, 0b101, def_is_slave;
 }
 
+#RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG
+scom 0x80091020(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_eo_ctle_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_ctle_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_offset_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_offset_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_vref_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_vref_timeout_sel,  0b110  , def_IS_VBU;
+}
+
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
 scom 0x80089820(xbus_base_addr) { 
 	bits, scom_data, expr;
+     rx_ds_bl_timeout_sel,  0b101   , def_IS_HW;
+     rx_ds_bl_timeout_sel,  0b001  , def_IS_VBU;
+     rx_ds_timeout_sel,  0b110   , def_IS_HW;
+     rx_ds_timeout_sel,  0b010  , def_IS_VBU;
 	rx_sls_timeout_sel, 0b001, any;
+     rx_wt_timeout_sel,  0b111   , def_IS_HW;
+     rx_wt_timeout_sel,  0b011  , def_IS_VBU;
 }
 
 #RX01_GEN.RX01.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
@@ -703,6 +782,17 @@ scom 0x8000B033(xbus_base_addr) {
 	rx_prbs_tap_id, 0b000, any;
 }
 
+#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG
+scom 0x800E7840(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_dll1_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll1_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll2_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll2_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll_vreg_compcon,  0b101   , def_IS_HW;
+     rx_dll_vreg_compcon,  0b000  , def_IS_VBU;
+}
+
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
 scom 0x8009D840(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -721,80 +811,80 @@ scom 0x800AE040(xbus_base_addr) {
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP
 scom 0x800B1840(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_ddc_use_cyc_block_lock,  0b0   , HW_EXPRESS;
-     rx_ddc_use_cyc_block_lock,  0b1  , VBU_EXPRESS;
+     rx_ddc_use_cyc_block_lock,  0b0   , def_IS_HW;
+     rx_ddc_use_cyc_block_lock,  0b1  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP
 scom 0x800B3040(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_dec_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_dec_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_dec_val_a,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_dec_val_b,  0b0001   , def_IS_HW;
+     rx_cal_dec_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_c,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_d,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP
 scom 0x800B3840(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_dec_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_dec_val_e,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_dec_val_f,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_g,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_h,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP
 scom 0x800B2040(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_inc_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_inc_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_inc_val_a,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_inc_val_b,  0b0001   , def_IS_HW;
+     rx_cal_inc_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_c,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_d,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP
 scom 0x800B2840(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_inc_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_inc_val_e,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_inc_val_f,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_g,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_h,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
 scom 0x800A3840(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ber_test,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_ber_test,  0b1   , def_IS_HW;
+     rx_eo_enable_ber_test,  0b0  , def_IS_VBU;
+     rx_eo_enable_ctle_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_ctle_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_dcd_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_dcd_cal,  0b0  , def_IS_VBU;
 	rx_eo_enable_final_l2u_adj, 0b1, any;
-     rx_eo_enable_latch_offset_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_latch_offset_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_eo_enable_result_check,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_vref_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_vref_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_latch_offset_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_latch_offset_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_eo_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_eo_enable_result_check,  0b1   , def_IS_HW;
+     rx_eo_enable_result_check,  0b0  , def_IS_VBU;
+     rx_eo_enable_vref_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_vref_cal,  0b0  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_FENCE_PG
@@ -835,6 +925,13 @@ scom 0x80093040(xbus_base_addr) {
 	rx_lane_disabled_vec_16_31, 0b0000111111111111, any;
 }
 
+#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE1_PP
+scom 0x800B0840(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_bit_lock_timeout_sel,  0b110   , def_IS_HW;
+     rx_bit_lock_timeout_sel,  0b101  , def_IS_VBU;
+}
+
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_MODE_PG
 scom 0x80081840(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -844,34 +941,36 @@ scom 0x80081840(xbus_base_addr) {
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
 scom 0x800AB840(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_rc_enable_dll_update,  0b1   , HW_EXPRESS;
-     rx_rc_enable_dll_update,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_edge_track,  0b1   , HW_EXPRESS;
-     rx_rc_enable_edge_track,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_rc_enable_result_check,  0b0  , VBU_EXPRESS;
+     rx_rc_enable_dll_update,  0b1   , def_IS_HW;
+     rx_rc_enable_dll_update,  0b0  , def_IS_VBU;
+     rx_rc_enable_edge_track,  0b1   , def_IS_HW;
+     rx_rc_enable_edge_track,  0b0  , def_IS_VBU;
+     rx_rc_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_rc_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_rc_enable_result_check,  0b1   , def_IS_HW;
+     rx_rc_enable_result_check,  0b0  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
 scom 0x800B6040(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_a,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_a,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1010   , HW_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_c,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_c,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_a,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_a,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_b,  0b1010   , def_IS_HW;
+     rx_servo_timeout_sel_b,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_c,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_c,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_d,  0b1001   , def_IS_HW;
+     rx_servo_timeout_sel_d,  0b0101  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
 scom 0x800B6840(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b1000   , HW_EXPRESS;
-     rx_servo_timeout_sel_f,  0b0110  , VBU_EXPRESS;
-     rx_servo_timeout_sel_h,  0b0110   , HW_EXPRESS;
-     rx_servo_timeout_sel_h,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_f,  0b1000   , def_IS_HW;
+     rx_servo_timeout_sel_f,  0b0110  , def_IS_VBU;
+     rx_servo_timeout_sel_h,  0b1110   , def_IS_HW;
+     rx_servo_timeout_sel_h,  0b1000  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG
@@ -880,10 +979,27 @@ scom 0x80080840(xbus_base_addr) {
 	rx_sls_extend_sel, 0b101, def_is_slave;
 }
 
+#RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG
+scom 0x80091040(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_eo_ctle_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_ctle_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_offset_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_offset_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_vref_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_vref_timeout_sel,  0b110  , def_IS_VBU;
+}
+
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
 scom 0x80089840(xbus_base_addr) { 
 	bits, scom_data, expr;
+     rx_ds_bl_timeout_sel,  0b101   , def_IS_HW;
+     rx_ds_bl_timeout_sel,  0b001  , def_IS_VBU;
+     rx_ds_timeout_sel,  0b110   , def_IS_HW;
+     rx_ds_timeout_sel,  0b010  , def_IS_VBU;
 	rx_sls_timeout_sel, 0b001, any;
+     rx_wt_timeout_sel,  0b111   , def_IS_HW;
+     rx_wt_timeout_sel,  0b011  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX0.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
@@ -1019,6 +1135,17 @@ scom 0x8000B053(xbus_base_addr) {
 	rx_prbs_tap_id, 0b000, any;
 }
 
+#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DLL_ANALOG_TWEAKS_PG
+scom 0x800E7860(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_dll1_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll1_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll2_vreg_drvcon,  0b001   , def_IS_HW;
+     rx_dll2_vreg_drvcon,  0b000  , def_IS_VBU;
+     rx_dll_vreg_compcon,  0b101   , def_IS_HW;
+     rx_dll_vreg_compcon,  0b000  , def_IS_VBU;
+}
+
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_DYN_RPR_ERR_TALLYING1_PG
 scom 0x8009D860(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -1037,80 +1164,80 @@ scom 0x800AE060(xbus_base_addr) {
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_CNTL_PP
 scom 0x800B1860(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_ddc_use_cyc_block_lock,  0b0   , HW_EXPRESS;
-     rx_ddc_use_cyc_block_lock,  0b1  , VBU_EXPRESS;
+     rx_ddc_use_cyc_block_lock,  0b0   , def_IS_HW;
+     rx_ddc_use_cyc_block_lock,  0b1  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_A_D_PP
 scom 0x800B3060(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_dec_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_dec_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_dec_val_a,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_dec_val_b,  0b0001   , def_IS_HW;
+     rx_cal_dec_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_c,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_d,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_DEC_E_H_PP
 scom 0x800B3860(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_dec_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_dec_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_dec_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_dec_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_dec_val_e,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_dec_val_f,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_g,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_dec_val_h,  0b0111   , def_IS_HW;
+     rx_cal_dec_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_A_D_PP
 scom 0x800B2060(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_a,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_a,  0b1000  , VBU_EXPRESS;
-     rx_cal_inc_val_b,  0b0001   , HW_EXPRESS;
-     rx_cal_inc_val_b,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_c,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_c,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_d,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_d,  0b1110  , VBU_EXPRESS;
+     rx_cal_inc_val_a,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_a,  0b1000  , def_IS_VBU;
+     rx_cal_inc_val_b,  0b0001   , def_IS_HW;
+     rx_cal_inc_val_b,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_c,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_c,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_d,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_d,  0b0110  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EI4_CAL_INC_E_H_PP
 scom 0x800B2860(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_cal_inc_val_e,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_e,  0b1110  , VBU_EXPRESS;
-     rx_cal_inc_val_f,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_f,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_g,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_g,  0b0000  , VBU_EXPRESS;
-     rx_cal_inc_val_h,  0b1111   , HW_EXPRESS;
-     rx_cal_inc_val_h,  0b0000  , VBU_EXPRESS;
+     rx_cal_inc_val_e,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_e,  0b0110  , def_IS_VBU;
+     rx_cal_inc_val_f,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_f,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_g,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_g,  0b0000  , def_IS_VBU;
+     rx_cal_inc_val_h,  0b0111   , def_IS_HW;
+     rx_cal_inc_val_h,  0b0000  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_EO_STEP_CNTL_PG
 scom 0x800A3860(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_eo_enable_ber_test,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ber_test,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_ctle_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_dcd_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_ber_test,  0b1   , def_IS_HW;
+     rx_eo_enable_ber_test,  0b0  , def_IS_VBU;
+     rx_eo_enable_ctle_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_ctle_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_dcd_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_dcd_cal,  0b0  , def_IS_VBU;
 	rx_eo_enable_final_l2u_adj, 0b1, any;
-     rx_eo_enable_latch_offset_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_latch_offset_cal,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_eo_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_eo_enable_result_check,  0b0  , VBU_EXPRESS;
-     rx_eo_enable_vref_cal,  0b1   , HW_EXPRESS;
-     rx_eo_enable_vref_cal,  0b0  , VBU_EXPRESS;
+     rx_eo_enable_latch_offset_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_latch_offset_cal,  0b0  , def_IS_VBU;
+     rx_eo_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_eo_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_eo_enable_result_check,  0b1   , def_IS_HW;
+     rx_eo_enable_result_check,  0b0  , def_IS_VBU;
+     rx_eo_enable_vref_cal,  0b1   , def_IS_HW;
+     rx_eo_enable_vref_cal,  0b0  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_FENCE_PG
@@ -1151,6 +1278,13 @@ scom 0x80093060(xbus_base_addr) {
 	rx_lane_disabled_vec_16_31, 0b0000111111111111, any;
 }
 
+#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE1_PP
+scom 0x800B0860(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_bit_lock_timeout_sel,  0b110   , def_IS_HW;
+     rx_bit_lock_timeout_sel,  0b101  , def_IS_VBU;
+}
+
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_MODE_PG
 scom 0x80081860(xbus_base_addr) { 
 	bits, scom_data, expr;
@@ -1160,34 +1294,36 @@ scom 0x80081860(xbus_base_addr) {
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_RC_STEP_CNTL_PG
 scom 0x800AB860(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_rc_enable_dll_update,  0b1   , HW_EXPRESS;
-     rx_rc_enable_dll_update,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_edge_track,  0b1   , HW_EXPRESS;
-     rx_rc_enable_edge_track,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b1   , HW_EXPRESS;
-     rx_rc_enable_measure_eye_width,  0b0  , VBU_EXPRESS;
-     rx_rc_enable_result_check,  0b1   , HW_EXPRESS;
-     rx_rc_enable_result_check,  0b0  , VBU_EXPRESS;
+     rx_rc_enable_dll_update,  0b1   , def_IS_HW;
+     rx_rc_enable_dll_update,  0b0  , def_IS_VBU;
+     rx_rc_enable_edge_track,  0b1   , def_IS_HW;
+     rx_rc_enable_edge_track,  0b0  , def_IS_VBU;
+     rx_rc_enable_measure_eye_width,  0b1   , def_IS_HW;
+     rx_rc_enable_measure_eye_width,  0b0  , def_IS_VBU;
+     rx_rc_enable_result_check,  0b1   , def_IS_HW;
+     rx_rc_enable_result_check,  0b0  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO1_PP
 scom 0x800B6060(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_a,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_a,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1010   , HW_EXPRESS;
-     rx_servo_timeout_sel_b,  0b1000  , VBU_EXPRESS;
-     rx_servo_timeout_sel_c,  0b0101   , HW_EXPRESS;
-     rx_servo_timeout_sel_c,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_a,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_a,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_b,  0b1010   , def_IS_HW;
+     rx_servo_timeout_sel_b,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_c,  0b0101   , def_IS_HW;
+     rx_servo_timeout_sel_c,  0b1000  , def_IS_VBU;
+     rx_servo_timeout_sel_d,  0b1001   , def_IS_HW;
+     rx_servo_timeout_sel_d,  0b0101  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SERVO_TO2_PP
 scom 0x800B6860(xbus_base_addr) { 
 	bits, scom_data, expr;
-     rx_servo_timeout_sel_f,  0b1000   , HW_EXPRESS;
-     rx_servo_timeout_sel_f,  0b0110  , VBU_EXPRESS;
-     rx_servo_timeout_sel_h,  0b0110   , HW_EXPRESS;
-     rx_servo_timeout_sel_h,  0b1000  , VBU_EXPRESS;
+     rx_servo_timeout_sel_f,  0b1000   , def_IS_HW;
+     rx_servo_timeout_sel_f,  0b0110  , def_IS_VBU;
+     rx_servo_timeout_sel_h,  0b1110   , def_IS_HW;
+     rx_servo_timeout_sel_h,  0b1000  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_SPARE_MODE_PG
@@ -1196,10 +1332,27 @@ scom 0x80080860(xbus_base_addr) {
 	rx_sls_extend_sel, 0b101, def_is_slave;
 }
 
+#RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL1_PG
+scom 0x80091060(xbus_base_addr) { 
+	bits, scom_data, expr;
+     rx_eo_ctle_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_ctle_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_offset_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_offset_timeout_sel,  0b110  , def_IS_VBU;
+     rx_eo_vref_timeout_sel,  0b111   , def_IS_HW;
+     rx_eo_vref_timeout_sel,  0b110  , def_IS_VBU;
+}
+
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TIMEOUT_SEL_PG
 scom 0x80089860(xbus_base_addr) { 
 	bits, scom_data, expr;
+     rx_ds_bl_timeout_sel,  0b101   , def_IS_HW;
+     rx_ds_bl_timeout_sel,  0b001  , def_IS_VBU;
+     rx_ds_timeout_sel,  0b110   , def_IS_HW;
+     rx_ds_timeout_sel,  0b010  , def_IS_VBU;
 	rx_sls_timeout_sel, 0b001, any;
+     rx_wt_timeout_sel,  0b111   , def_IS_HW;
+     rx_wt_timeout_sel,  0b011  , def_IS_VBU;
 }
 
 #RX23_GEN.RX23.RX1.RXCTL.RX_CTL_REGS.RX_TX_BUS_INFO_PG
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
index 7fc4fd22b..5892dbd05 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
@@ -20,8 +20,8 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_chiplet_scominit.C,v 1.10 2013/03/04 17:32:59 jmcgill Exp $
-// $Source: /afs/awd.austin.ibm.com/proj/p9/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $
+// $Id: proc_chiplet_scominit.C,v 1.11 2013/03/25 02:39:41 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -101,6 +101,22 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
                 break;
             }
 
+            // execute TP bridge SCOM initfile
+            FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
+                     PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF, i_target.toEcmdString());
+            FAPI_EXEC_HWP(
+                rc,
+                fapiHwpExecInitFile,
+                initfile_targets,
+                PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF);
+            if (!rc.ok())
+            {
+                FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
+                         PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF,
+                         i_target.toEcmdString());
+                break;
+            }
+
             // query NX partial good attribute
             rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE,
                                &i_target,
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H
index 75904635a..0019ee938 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H
@@ -20,8 +20,8 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_chiplet_scominit.H,v 1.9 2013/03/04 17:33:04 jmcgill Exp $
-// $Source: /afs/awd.austin.ibm.com/proj/p9/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.H,v $
+// $Id: proc_chiplet_scominit.H,v 1.10 2013/03/25 02:39:43 jmcgill Exp $
+// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -49,11 +49,12 @@
 // Constant definitions
 //------------------------------------------------------------------------------
 
-const char * const PROC_CHIPLET_SCOMINIT_FBC_IF = "p8.fbc.scom.if";
-const char * const PROC_CHIPLET_SCOMINIT_PSI_IF = "p8.psi.scom.if";
-const char * const PROC_CHIPLET_SCOMINIT_NX_IF  = "p8.nx.scom.if";
-const char * const PROC_CHIPLET_SCOMINIT_AS_IF  = "p8.as.scom.if";
-const char * const PROC_CHIPLET_SCOMINIT_MCS_IF = "p8.mcs.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_FBC_IF       = "p8.fbc.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_PSI_IF       = "p8.psi.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF  = "p8.tpbridge.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_NX_IF        = "p8.nx.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_AS_IF        = "p8.as.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_MCS_IF       = "p8.mcs.scom.if";
 
 //------------------------------------------------------------------------------
 // Structure definitions
@@ -79,6 +80,7 @@ extern "C" {
  *                     If TARGET_TYPE_PROC_CHIP, calls:
  *                     - p8.fbc.scom.initfile
  *                     - p8.psi.scom.initfile
+ *                     - p8.tpbridge.scom.initfile
  *                     - p8.nx.scom.initfile
  *                     - p8.as.scom.initfile
  *                     - p8.mcs.scom.initfile for each functional MCS chiplet
diff --git a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C
index c760dd1ef..b6f086e32 100644
--- a/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C
+++ b/src/usr/hwpf/hwp/thread_activate/proc_thread_control/proc_thread_control.C
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012                   */
+/* COPYRIGHT International Business Machines Corp. 2012,2013              */
 /*                                                                        */
 /* p1                                                                     */
 /*                                                                        */
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_thread_control.C,v 1.18 2012/09/26 15:14:36 karm Exp $
+// $Id: proc_thread_control.C,v 1.20 2013/03/15 15:03:58 jklazyns Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
 // *! All Rights Reserved -- Property of IBM
@@ -346,7 +346,7 @@ extern "C"
 
         do
         {
-            FAPI_DBG("proc_thread_control_stop : Initiating stop command to core PC logic for thread %d", i_thread);
+            FAPI_INF("proc_thread_control_stop : Initiating stop command to core PC logic for thread %d", i_thread);
 
             rc_ecmd |= scomData.flushTo0();
             rc_ecmd |= scomData.setBit(PTC_DIR_CTL_SP_STOP);
@@ -662,7 +662,10 @@ extern "C"
 
         do
         {
+            FAPI_INF("proc_thread_control_query: Start");
+
             o_state = 0;
+
             rc = fapiGetScom(i_target, rasStatAddr, scomData);
             if (!rc.ok())
             {
@@ -691,7 +694,10 @@ extern "C"
             {
                 o_state |= THREAD_STATE_ENABLED;
             }
-            if (o_ras_status.isBitSet(PTC_RAS_STAT_RUN_BIT))
+            // Threads that are not in maintenance and not checkstopped are also considered 'running'
+            if (o_ras_status.isBitSet(PTC_RAS_STAT_RUN_BIT)  ||
+               ((!o_ras_status.isBitSet(PTC_RAS_STAT_MAINT)) &&
+                (!o_ras_status.isBitSet(PTC_RAS_STAT_CHKSTOP))))
             {
                 o_state |= THREAD_STATE_RUNNING;
             }
@@ -721,6 +727,7 @@ extern "C"
                 o_state |= THREAD_STATE_RAM_ACTIVE;
             }
 
+            FAPI_INF("proc_thread_control_query: thread state=%016llX (ras_status=%016llX)", o_state, o_ras_status.getDoubleWord(0));
         }
         while (0);
         return rc;
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index ca2bd5902..dfa61f7f3 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -136,7 +136,8 @@ HWP_INITFILES = hwp/initfiles/sample.initfile \
                 hwp/initfiles/cen.dmi.custom.scom.initfile \
                 hwp/initfiles/p8.abus.custom.scom.initfile \
                 hwp/initfiles/p8.xbus.custom.scom.initfile \
-                hwp/initfiles/p8.psi.scom.initfile
+                hwp/initfiles/p8.psi.scom.initfile \
+                hwp/initfiles/p8.tpbridge.scom.initfile
 
 HWP_IF_DEFINE_DIR = hwp/initfiles