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author | Thi Tran <thi@us.ibm.com> | 2013-04-24 07:54:12 -0500 |
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committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-05-02 15:20:12 -0500 |
commit | 34b67dcc6f93420790ced1241ab6a5b715d4f00e (patch) | |
tree | ec7c2049bccf8db11f7f229bc1e444dc209e028a /src/usr/hwpf/hwp/include | |
parent | 7e236aac934843e875280b3f9456f026466bc68b (diff) | |
download | talos-hostboot-34b67dcc6f93420790ced1241ab6a5b715d4f00e.tar.gz talos-hostboot-34b67dcc6f93420790ced1241ab6a5b715d4f00e.zip |
TULETA Bring Up - Update Mem & Proc procedures 04/24
SW198433
Change-Id: I40a65adc63648e2252e5351b4ae7b817f43d032d
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4190
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/include')
-rwxr-xr-x | src/usr/hwpf/hwp/include/cen_scom_addresses.H | 41 |
1 files changed, 39 insertions, 2 deletions
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H index 3865eeb7c..a06f96e50 100755 --- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H +++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: cen_scom_addresses.H,v 1.56 2013/04/04 20:32:53 jdsloat Exp $ +// $Id: cen_scom_addresses.H,v 1.57 2013/04/11 23:41:36 jdsloat Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -44,6 +44,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.56 | jdsloat |11-Apr-13| Added DQS Gate Delay Values // 1.55 | jdsloat |04-Apr-13| Added DPHY01_DDRPHY_WC_CONFIG3 regs // 1.54 | jdsloat |03-Apr-13| Fixed MR Sec shadow regs // 1.53 | jdsloat |08-Mar-13| Added MBA01_MBARPC0Q_0x03010434 @@ -1362,7 +1363,7 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143 //------------------------------------------------------------------------------ -// DQS Gate Delay Rank Pair 0 +// DQS Gate Delay //------------------------------------------------------------------------------ CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F , ULL(0x800000130301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F , ULL(0x800004130301143F) ); @@ -1375,6 +1376,39 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F , ULL( CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F , ULL(0x80010C130301143F) ); CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F , ULL(0x800110130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F , ULL(0x800001130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F , ULL(0x800005130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F , ULL(0x800009130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F , ULL(0x80000D130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F , ULL(0x800011130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F , ULL(0x800101130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F , ULL(0x800105130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F , ULL(0x800109130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F , ULL(0x80010D130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F , ULL(0x800111130301143F) ); + +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F , ULL(0x800002130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F , ULL(0x800006130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F , ULL(0x80000A130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F , ULL(0x80000E130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F , ULL(0x800012130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F , ULL(0x800102130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F , ULL(0x800106130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F , ULL(0x80010A130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F , ULL(0x80010E130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F , ULL(0x800112130301143F) ); + +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F , ULL(0x800003130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F , ULL(0x800007130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F , ULL(0x80000B130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F , ULL(0x80000F130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F , ULL(0x800013130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F , ULL(0x800103130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F , ULL(0x800107130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F , ULL(0x80010B130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F , ULL(0x80010F130301143F) ); +CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F , ULL(0x800113130301143F) ); + //------------------------------------------------------------------------------ // RC config registers 0 and 3 @@ -1578,6 +1612,9 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_scom_addresses.H,v $ +Revision 1.57 2013/04/11 23:41:36 jdsloat +Added DQS Gate Delay Values + Revision 1.56 2013/04/04 20:32:53 jdsloat Added DPHY01_DDRPHY_WC_CONFIG3 regs |