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-rw-r--r--src/makefile3
-rw-r--r--src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C7
-rw-r--r--src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml1
-rw-r--r--src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C5
-rw-r--r--src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C132
-rw-r--r--src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C23
-rw-r--r--src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C773
-rwxr-xr-xsrc/usr/hwpf/hwp/include/cen_scom_addresses.H41
-rw-r--r--src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile17
-rw-r--r--src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile12
-rw-r--r--src/usr/hwpf/hwp/initfiles/mba_def.initfile6
-rw-r--r--src/usr/hwpf/hwp/initfiles/mbs_def.initfile314
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile46
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile45
-rw-r--r--src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile22
-rw-r--r--src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C37
-rw-r--r--src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C45
-rw-r--r--src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C71
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C18
-rw-r--r--src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H4
-rw-r--r--src/usr/hwpf/makefile3
21 files changed, 1254 insertions, 371 deletions
diff --git a/src/makefile b/src/makefile
index 750555c3b..27c3660c6 100644
--- a/src/makefile
+++ b/src/makefile
@@ -87,7 +87,8 @@ hbicore_DATA_MODULES = sample.if p8.dmi.scom.if cen.dmi.scom.if \
p8.abus.scom.if p8.xbus.scom.if p8.mcs.scom.if \
p8.as.scom.if p8.nx.scom.if p8.dmi.custom.scom.if \
cen.dmi.custom.scom.if p8.abus.custom.scom.if \
- p8.xbus.custom.scom.if p8.psi.scom.if p8.tpbridge.scom.if
+ p8.xbus.custom.scom.if p8.psi.scom.if p8.tpbridge.scom.if \
+ p8.cxa.scom.if
hbicore_test_OBJECTS = ${hbicore_OBJECTS}
hbicore_test_MODULES = ${hbicore_MODULES}
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
index a2e2f0a47..da64c9232 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_build_smp_adu.C,v 1.4 2013/02/25 14:50:52 jmcgill Exp $
+// $Id: proc_build_smp_adu.C,v 1.6 2013/03/28 16:28:32 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $
//------------------------------------------------------------------------------
// *|
@@ -266,6 +266,10 @@ fapi::ReturnCode proc_build_smp_adu_check_status(
break;
}
}
+ if (!rc.ok())
+ {
+ break;
+ }
// check status bits versus expected pattern
match =
@@ -324,6 +328,7 @@ fapi::ReturnCode proc_build_smp_adu_check_status(
FAPI_ERR("proc_adu_utils_check_adu_status: FBC_ALTD_PBINIT_MISSING_ERROR = %d",
(status_act.pbinit_missing == ADU_STATUS_BIT_SET)?(1):(0));
const proc_adu_utils_adu_status & STATUS_DATA = status_act;
+ const uint8_t & NUM_POLLS = num_polls;
FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH);
break;
}
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml
index f3d839bad..d6aca2133 100644
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml
+++ b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_errors.xml
@@ -107,6 +107,7 @@
<hwpError>
<rc>RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH</rc>
<description>Status mismatch detected on ADU operation executed for SMP configuration.</description>
+ <ffdc>NUM_POLLS</ffdc>
<ffdc>STATUS_DATA</ffdc>
</hwpError>
<hwpError>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index cbb43ee54..97abcdaf5 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_draminit_mc.C,v 1.35 2013/04/01 20:24:02 lapietra Exp $
+// $Id: mss_draminit_mc.C,v 1.36 2013/04/15 13:07:51 lapietra Exp $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
// *! All Rights Reserved -- Property of IBM
@@ -44,6 +44,7 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|-----------------------------------------------
+// 1.36 | dcadiga |03-APR-13| Fixed compile warning
// 1.35 | dcadiga |01-APR-13| Temp Fix For Parity Error on 32GB
// 1.34 | dcadiga |12-MAR-13| Added spare cke disable as step 0
// 1.33 | dcadiga |04-FEB-13| For some reason the main procedure call was commented out in the last commit... commenting it back in
@@ -192,7 +193,7 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target)
rc = fapiPutScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64);
if(rc)
{
- FAPI_ERR("---Error During Clear Parity Bit", uint32_t(rc), rc.getCreator());
+ FAPI_ERR("---Error During Clear Parity Bit rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
return rc;
}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
index 04efb9d00..7993f87df 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_draminit_training_advanced.C,v 1.27 2013/04/09 11:08:44 lapietra Exp $
+// $Id: mss_draminit_training_advanced.C,v 1.29 2013/04/23 14:26:07 sasethur Exp $
/* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
//------------------------------------------------------------------------------
@@ -67,6 +67,8 @@
// 1.25 | abhijsau |31-Jan-13| Removed mss_mcbist_common.C include file , needs to be included while compiling
// 1.26 | abhijsau |06-Mar-13| Fixed fw comment
// 1.27 | sasethur |09-Apr-13| Updated for port in parallel and pass shmoo param
+// 1.28 | sasethur |22-Apr-13| Fixed fw comment
+// 1.29 | sasethur |23-Apr-13| Fixed fw comment
// This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure
// DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation
@@ -92,7 +94,8 @@
#include <mss_unmask_errors.H>
//#include <mss_mcbist_common.C>
-
+const uint8_t PATTERN = 14;
+const uint8_t TESTTYPE = 13;
const uint32_t MASK = 1;
const uint32_t MAX_DIMM =2;
@@ -160,8 +163,8 @@ fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mb
uint8_t i_test_type)
{
// const fapi::Target is centaur.mba
- i_pattern=13;
- i_test_type=14;
+ i_pattern= PATTERN; // MPR - Hard coded will be removed after attribute is assigned in firmware
+ i_test_type= TESTTYPE; // SIMPLE RAND - Hard coded will be removed after attribute is assigned in firmware
fapi::ReturnCode rc;
FAPI_INF(" pattern bit is %d and test_type_bit is %d",i_pattern,i_test_type);
@@ -210,7 +213,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta
uint32_t l_attr_mss_volt_u32 = 0;
uint8_t l_num_drops_per_port_u8 = 2;
uint8_t l_num_ranks_per_dimm_u8array[MAX_PORT][MAX_DIMM] = {{0}};
- uint8_t __attribute__((unused)) l_actual_dimm_size_u8 = 0; // SW198827
+ //nuint8_t l_actual_dimm_size_u8 = 0;
uint8_t l_port = 0;
uint8_t l_dimm_type_u8 = 0; //default is set to CDIMM
uint32_t l_left_margin=0;
@@ -246,14 +249,14 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta
FAPI_INF("num_ranks_per_dimm = [%02d][%02d][%02d][%02d] on %s.", l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[0][1], l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[1][1], i_target_mba.toEcmdString());
FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
- if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL )
- {
- l_actual_dimm_size_u8 = 2;
- }
- else
- {
- l_actual_dimm_size_u8 = 1;
- }
+ // if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL )
+ // {
+ // l_actual_dimm_size_u8 = 2;
+ // }
+ // else
+ // {
+ // l_actual_dimm_size_u8 = 1;
+ // }
rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t);
if(rc) return rc;
@@ -451,14 +454,14 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba,
if (l_drv_imp_dq_dqs_new[i_port] != l_drv_imp_dq_dqs_nom[i_port])
{
- FAPI_INF("Better Margin found on %d Ohms on %s", l_drv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString());
- rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_new);
- if (rc) return rc;
- FAPI_INF("Configuring New Driver Impedance Value to Registers:");
- rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs_new[i_port]);
- if (rc) return rc;
- rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_new[i_port], l_slew_rate_dq_dqs[i_port]);
- if (rc) return rc;
+ //FAPI_INF("Better Margin found on %d Ohms on %s", l_drv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString());
+ //rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_new);
+ //if (rc) return rc;
+ //FAPI_INF("Configuring New Driver Impedance Value to Registers:");
+ //rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs_new[i_port]);
+ //if (rc) return rc;
+ //rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_new[i_port], l_slew_rate_dq_dqs[i_port]);
+ //if (rc) return rc;
}
else
{
@@ -583,11 +586,11 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba,
if (l_slew_rate_dq_dqs_new[i_port] != l_slew_rate_dq_dqs_nom[i_port])
{
- FAPI_INF("Better Margin found on Slew Rate: %d V/ns on %s", l_slew_rate_dq_dqs_new[i_port], i_target_mba.toEcmdString());
- rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_new);
+ //FAPI_INF("Better Margin found on Slew Rate: %d V/ns on %s", l_slew_rate_dq_dqs_new[i_port], i_target_mba.toEcmdString());
+ //rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_new);
if (rc) return rc;
- FAPI_INF("Configuring New Slew Rate Value to Registers:");
- rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs_new[i_port]);
+ //FAPI_INF("Configuring New Slew Rate Value to Registers:");
+ //rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs_new[i_port]);
if (rc) return rc;
}
else
@@ -640,7 +643,7 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba,
if (rc) return rc;
rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, l_wr_dram_vref_schmoo);
if (rc) return rc;
- FAPI_INF("+++++++++++++++++DRAM VREF Shmoo Attributes Values+++++++++++++++");
+ FAPI_INF("+++++++++++++++++WRITE DRAM VREF Shmoo Attributes Values+++++++++++++++");
FAPI_INF("DRAM_WR_VREF[0] = %d , DRAM_WR_VREF[1] = %d on %s", l_wr_dram_vref_nom[0], l_wr_dram_vref_nom[1],i_target_mba.toEcmdString());
FAPI_INF("DRAM_WR_VREF_SCHMOO[0] = [%x],DRAM_WR_VREF_SCHMOO[1] = [%x] on %s", l_wr_dram_vref_schmoo[0], l_wr_dram_vref_schmoo[1],i_target_mba.toEcmdString());
FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
@@ -656,12 +659,12 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba,
{
if (l_wr_dram_vref_schmoo[i_port] & MASK)
{
- FAPI_INF("Current Vref value is %dmV", wr_vref_array[index]);
+ FAPI_INF("Current Vref multiplier value is %d", wr_vref_array[index]);
l_wr_dram_vref[i_port] = wr_vref_array[index];
rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref[i_port]);
if (rc) return rc;
l_wr_dram_vref_in = l_wr_dram_vref[i_port];
- FAPI_INF(" Calling Shmoo for finding Timing Margin:");
+ //FAPI_INF(" Calling Shmoo for finding Timing Margin:");
rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
&l_left_margin, &l_right_margin, i_pattern, i_test_type, l_wr_dram_vref_in);
if (rc) return rc;
@@ -681,7 +684,7 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba,
l_right_margin_wr_vref_array, MAX_WR_VREF, l_wr_dram_vref_nom_fc, count);
if (count >= MAX_WR_VREF)
{
- FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)",
+ FAPI_ERR("Write dram vref input(%d) out of bounds, (>= %d)",
count, MAX_WR_VREF);
FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
return rc;
@@ -702,12 +705,12 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba,
if(l_wr_dram_vref_new[i_port] != l_wr_dram_vref_nom[i_port])
{
- FAPI_INF("Best Margin Found on Vref : %d , %d mV on %s", count, wr_vref_array_fitness[count], i_target_mba.toEcmdString());
- rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_new);
- if (rc) return rc;
- FAPI_INF("Configuring New Vref Value to registers:");
- rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_new[i_port]);
- if (rc) return rc;
+ //FAPI_INF("Best Margin Found on Vref Multiplier : %d on %s", wr_vref_array_fitness[count], i_target_mba.toEcmdString());
+ //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_new);
+ //if (rc) return rc;
+ //FAPI_INF("Configuring New Vref Value to registers:");
+ //rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_new[i_port]);
+ //if (rc) return rc;
}
else
{
@@ -716,7 +719,7 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba,
if (rc) return rc;
}
}
- FAPI_INF("++++ Write Vref Shmoo function executed successfully ++++");
+ FAPI_INF("++++ Write DRAM Vref Shmoo function executed successfully ++++");
}
return rc;
}
@@ -778,11 +781,11 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba,
if ((l_rd_cen_vref_schmoo[i_port] & MASK) == 1)
{
l_rd_cen_vref[i_port] = rd_cen_vref_array[index];
- FAPI_INF("Current Vref value is %dmV", rd_cen_vref_array[index]);
+ FAPI_INF("Current Read Vref Multiplier value is %d", rd_cen_vref_array[index]);
FAPI_INF("Configuring Read Vref Registers:");
rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref[i_port]); if (rc) return rc;
l_rd_cen_vref_in = l_rd_cen_vref[i_port];
- FAPI_INF(" Calling Shmoo function to find out Timing Margin:");
+ //FAPI_INF(" Calling Shmoo function to find out Timing Margin:");
rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type, l_rd_cen_vref_in);
if (rc) return rc;
l_left_margin_rd_vref_array[index]= l_left_margin;
@@ -800,7 +803,7 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba,
l_right_margin_rd_vref_array, MAX_RD_VREF, l_rd_cen_vref_nom_fc, count);
if (count >= MAX_RD_VREF)
{
- FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)",
+ FAPI_ERR("Read vref new input(%d) out of bounds, (>= %d)",
count, MAX_RD_VREF);
FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
return rc;
@@ -821,12 +824,12 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba,
if(l_rd_cen_vref_new[i_port] != l_rd_cen_vref_nom[i_port])
{
- FAPI_INF("Best Margin Found on Vref : %dmv , %dmV on %s", l_rd_cen_vref_new[i_port], rd_cen_vref_array_fitness[count], i_target_mba.toEcmdString());
- rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_new);
- if (rc) return rc;
- FAPI_INF("Configuring New Read Vref Value to Registers:");
- rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_new[i_port]);
- if (rc) return rc;
+ //FAPI_INF("Best Margin Found on Vref : %dmv , %dmV on %s", l_rd_cen_vref_new[i_port], rd_cen_vref_array_fitness[count], i_target_mba.toEcmdString());
+ //rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_new);
+ //if (rc) return rc;
+ //FAPI_INF("Configuring New Read Vref Value to Registers:");
+ //rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_new[i_port]);
+ //if (rc) return rc;
}
else
{
@@ -835,7 +838,7 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba,
if (rc) return rc;
}
}
- FAPI_INF("++++ Read Vref Shmoo function executed successfully ++++");
+ FAPI_INF("++++ Centaur Read Vref Shmoo function executed successfully ++++");
}
return rc;
}
@@ -916,7 +919,7 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba,
l_right_margin_rcv_imp_array, MAX_RCV_IMP, l_rcv_imp_dq_dqs_nom_fc, count);
if (count >= MAX_RCV_IMP)
{
- FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)",
+ FAPI_ERR("Receiver Imp new input(%d) out of bounds, (>= %d)",
count, MAX_RCV_IMP);
FAPI_SET_HWP_ERROR(rc, RC_MSS_INVALID_FN_INPUT_ERROR);
return rc;
@@ -937,11 +940,11 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba,
if (l_rcv_imp_dq_dqs_new[i_port] != l_rcv_imp_dq_dqs_nom[i_port])
{
- FAPI_INF("Better Margin found on %d on %s", l_rcv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString());
- rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_new);
- if (rc) return rc;
- rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs_new[i_port]);
- if (rc) return rc;
+ //FAPI_INF("Better Margin found on %d on %s", l_rcv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString());
+ //rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_new);
+ //if (rc) return rc;
+ //rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs_new[i_port]);
+ //if (rc) return rc;
}
else
{
@@ -978,7 +981,7 @@ fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
FAPI_INF(" Inside the delay shmoo " );
//Constructor CALL: generic_shmoo::generic_shmoo(uint8_t i_port, uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm)
//generic_shmoo mss_shmoo=generic_shmoo(i_port,2,SEQ_LIN);
- generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN);
+ generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN);
rc = mss_shmoo.run(i_target_mba, o_left_margin, o_right_margin,i_pattern,i_test_type,i_shmoo_param);
if(rc)
{
@@ -1010,9 +1013,9 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
uint32_t right_margin = 0;
uint32_t left_margin_nom = 0;
uint32_t right_margin_nom = 0;
- uint32_t diff_margin_nom = 0;
- uint32_t __attribute__((unused)) total_margin = 0; //SW198827
- uint32_t diff_margin = 0;
+ uint32_t __attribute__((unused)) diff_margin_nom = 0; // SW198827
+ //uint32_t total_margin = 0;
+ uint32_t __attribute__((unused)) diff_margin = 0; // SW198827
uint8_t index = 0;
uint8_t index2 = 0;
@@ -1026,7 +1029,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
left_margin_nom = i_left[index];
right_margin_nom = i_right[index];
diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]);
- FAPI_INF("Driver impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
+ //FAPI_INF("Driver impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
break;
}
}
@@ -1037,7 +1040,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
left_margin_nom = i_left[index];
right_margin_nom = i_right[index];
diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]);
- FAPI_INF("Slew rate value (NOM): %d V/ns Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
+ //FAPI_INF("Slew rate value (NOM): %d V/ns Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
break;
}
}
@@ -1048,7 +1051,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
left_margin_nom = i_left[index];
right_margin_nom = i_right[index];
diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]);
- FAPI_INF("Write DRAM Vref value (NOM): %d mV Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
+ //FAPI_INF("Write DRAM Vref Multiplier value (NOM): %d Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
break;
}
}
@@ -1059,7 +1062,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
left_margin_nom = i_left[index];
right_margin_nom = i_right[index];
diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]);
- FAPI_INF("Centaur Read Vref value (NOM): %d mV Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
+ //FAPI_INF("Centaur Read Vref Multiplier value (NOM): %d Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
break;
}
}
@@ -1070,7 +1073,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
left_margin_nom = i_left[index];
right_margin_nom = i_right[index];
diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]);
- FAPI_INF("Receiver Impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
+ // FAPI_INF("Receiver Impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
break;
}
}
@@ -1080,15 +1083,16 @@ void find_best_margin(shmoo_param i_shmoo_param_valid,
{
left_margin = i_left[index2];
right_margin = i_right[index2];
- total_margin = i_left[index2] + i_right[index2];
+ //total_margin = i_left[index2] + i_right[index2];
diff_margin = (i_left[index2] >= i_right[index2]) ? (i_left[index2] - i_right[index2]) : (i_right[index2] - i_left[index2]);
if ((left_margin > 0 && right_margin > 0))
{
- if((left_margin >= left_margin_nom) && (right_margin >= right_margin_nom) && (diff_margin <= diff_margin_nom))
+ // if((left_margin >= left_margin_nom) && (right_margin >= right_margin_nom) && (diff_margin <= diff_margin_nom))
+ if((left_margin >= left_margin_nom) && (right_margin >= right_margin_nom))
{
o_index = index2;
//wont break this loop, since the purpose is to find the best parameter value & best timing margin The enum is constructed to do that
- FAPI_INF("Best Value found on index %d, Setup Margin: %d, Hold Margin: %d", o_index, i_left[index2], i_right[index2]);
+ // FAPI_INF("Best Value found on index %d, Setup Margin: %d, Hold Margin: %d", o_index, i_left[index2], i_right[index2]);
}
}
}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
index b29864630..7ade47d33 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
@@ -21,7 +21,7 @@
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_generic_shmoo.C,v 1.43 2013/04/11 15:06:18 bellows Exp $
+// $Id: mss_generic_shmoo.C,v 1.44 2013/04/22 17:03:34 sasethur Exp $
// *!***************************************************************************
// *! (C) Copyright International Business Machines Corp. 1997, 1998
// *! All Rights Reserved -- Property of IBM
@@ -40,6 +40,7 @@
//------------------------------------------------------------------------------
// Version:|Author: | Date: | Comment:
// --------|--------|---------|--------------------------------------------------
+// 1.44 |bellows |04/22/13 | fixed fw comments
// 1.43 |bellows |04/11/13 | quick fix for firmware delivery. Uninitialized varialbles: i_mcbtest, i_mcbpatt
// 1.42 |abhijit |04/09/13 | added shmoo param
// 1.40 |abhijit |03/22/13 | Fixed boundary checks
@@ -626,7 +627,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
uint8_t l_p=0;
uint16_t l_delay=0;
- uint32_t __attribute__((unused)) l_max=0; //SW198827
+ //uint32_t l_max=0;
uint16_t l_max_limit=500;
uint8_t rank=0;
uint8_t l_rank=0;
@@ -744,7 +745,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_
rc = mss_getrankpair(i_target,l_p,rank,&l_rp,valid_rank);if(rc) return rc;
for (l_n=0; l_n<l_SCHMOO_NIBBLES;l_n++){
- l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
+ //l_max=SHMOO[scenario].MBA.P[l_p].S[rank].K.lb_regval[l_dq][l_rp];
if(schmoo_error_map[l_p][rank][l_n]==0){
@@ -1150,12 +1151,12 @@ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uin
{
- uint8_t __attribute__((unused)) l_socket=0; //SW198827
-
+ uint8_t __attribute__((unused)) l_socket=0; //SW198827
+
//uint32_t rc_num =0;
uint8_t l_pattern=0;
uint8_t l_testtype=0;
- uint8_t l_rank=0;
+ //uint8_t l_rank=0;
fapi::ReturnCode rc;
uint64_t l_start =0x0000000000000000ull;
@@ -1165,14 +1166,8 @@ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uin
mcbist_test_mem i_mcbtest = CENSHMOO; // bellows: initialize to this type
mcbist_data_gen i_mcbpatt = ABLE_FIVE; // bellows: initialize to this data type
- if(l_rank<4)
- {
- l_socket=0;
- }
- else
- {
- l_socket=1;
- }
+
+
//send shmoo mode to vary the address range
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index 08512d949..c4b59e331 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_draminit_training.C,v 1.56 2013/03/09 00:05:43 jdsloat Exp $
+// $Id: mss_draminit_training.C,v 1.57 2013/04/16 21:22:50 jdsloat Exp $
//------------------------------------------------------------------------------
// Don't forget to create CVS comments when you check in your changes!
//------------------------------------------------------------------------------
@@ -28,6 +28,7 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|------------------------------------------------
+// 1.57 | jdsloat |27-FEB-13| Added second workaround adjustment to waterfall problem in order to use 2 rank pairs.
// 1.56 | jdsloat |27-FEB-13| Fixed rtt_nom and rtt_wr swap bug during condition of rtt_nom = diabled and rtt_wr = non-disabled
// | | | Added workaround on a per quad resolution
// | | | Added workaround as a seperate sub
@@ -160,10 +161,11 @@ using namespace fapi;
ReturnCode mss_draminit_training(Target& i_target);
ReturnCode mss_draminit_training_cloned(Target& i_target);
-ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status);
-ReturnCode mss_check_error_status(Target& i_target, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status);
-ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original);
+ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, mss_draminit_training_result& io_status);
+ReturnCode mss_check_error_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group, uint8_t cur_cal_step, mss_draminit_training_result& io_status);
+ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint8_t i_mbaPosition, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original);
ReturnCode mss_read_center_workaround(Target& i_target, uint8_t i_mbaPosition, uint32_t i_port, uint32_t i_rank_group);
+ReturnCode mss_read_center_second_workaround(Target& i_target);
ReturnCode getC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg);
ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg);
@@ -348,7 +350,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
(cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
(cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ))
{
- FAPI_INF( "Performing External ZQ Calibration on MBA %d.", mbaPosition);
+ FAPI_INF( "Performing External ZQ Calibration on %s.", i_target.toEcmdString());
//Execute ZQ_CAL
for(port = 0; port < MAX_NUM_PORT; port++)
@@ -376,7 +378,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
rc_num = rc_num | rasn_buffer_1.flushTo1();
rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal
- FAPI_INF( "+++ Setting up Init Cal on MBA: %d Port: %d rank group: %d cal_steps: 0x%02X +++", mbaPosition, port, group, cal_steps);
+ FAPI_INF( "+++ Setting up Init Cal on %s Port: %d rank group: %d cal_steps: 0x%02X +++", i_target.toEcmdString(), port, group, cal_steps);
for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps
{
@@ -498,7 +500,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
(cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
(cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )
{
- FAPI_INF( "+++ Executing ALL Cal Steps at the same time on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Executing ALL Cal Steps at the same time on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(48);
rc_num = rc_num | data_buffer_64.setBit(50);
rc_num = rc_num | data_buffer_64.setBit(51);
@@ -509,42 +511,42 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
}
else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) )
{
- FAPI_INF( "+++ Write Leveling (WR_LVL) on MBA: %d Port %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Write Leveling (WR_LVL) on %s Port %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(48);
}
else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) )
{
- FAPI_INF( "+++ DQS Align (DQS_ALIGN) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ DQS Align (DQS_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(50);
}
else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) )
{
- FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(51);
}
else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) )
{
- FAPI_INF( "+++ Read Centering (READ_CTR) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Read Centering (READ_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(52);
}
else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) )
{
- FAPI_INF( "+++ Write Centering (WRITE_CTR) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Write Centering (WRITE_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(53);
}
else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) )
{
- FAPI_INF( "+++ Initial Course Write (COURSE_WR) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Initial Course Write (COURSE_WR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(54);
}
else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) )
{
- FAPI_INF( "+++ Course Read (COURSE_RD) on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Course Read (COURSE_RD) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(55);
}
else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) )
{
- FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on MBA: %d Port: %d rank group: %d +++", mbaPosition, port, group);
+ FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
rc_num = rc_num | data_buffer_64.setBit(54);
rc_num = rc_num | data_buffer_64.setBit(55);
}
@@ -563,6 +565,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
{
dram_rtt_nom_original = 0xFF;
rc = mss_rtt_nom_rtt_wr_swap(i_target,
+ mbaPosition,
port,
primary_ranks_array[group][port],
group,
@@ -622,7 +625,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
//Check to see if the training completes
- rc = mss_check_cal_status(i_target, port, group, cur_complete_status);
+ rc = mss_check_cal_status(i_target, mbaPosition, port, group, cur_complete_status);
if(rc) return rc;
if (cur_complete_status == MSS_INIT_CAL_STALL)
@@ -631,7 +634,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
}
//Check to see if the training errored out
- rc = mss_check_error_status(i_target, port, group, cur_error_status);
+ rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status);
if(rc) return rc;
if (cur_error_status == MSS_INIT_CAL_FAIL)
@@ -643,6 +646,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
if (cur_cal_step == 1)
{
rc = mss_rtt_nom_rtt_wr_swap(i_target,
+ mbaPosition,
port,
primary_ranks_array[group][port],
group,
@@ -668,7 +672,10 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
}//end of group loop
}//end of port loop
+ // Make sure the DQS_CLK values of each byte have matching nibble values, using the lowest
+ rc = mss_read_center_second_workaround(i_target);
if(rc) return rc;
+
//rc = mss_get_bbm_regs(i_target);
//if(rc)
//{
@@ -695,6 +702,7 @@ ReturnCode mss_draminit_training_cloned(Target& i_target)
}
ReturnCode mss_check_cal_status( Target& i_target,
+ uint8_t i_mbaPosition,
uint8_t i_port,
uint8_t i_group,
mss_draminit_training_result& io_status
@@ -723,7 +731,7 @@ ReturnCode mss_check_cal_status( Target& i_target,
while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) &&
(poll_count <= 20))
{
- FAPI_INF( "+++ Calibration on port: %d rank group: %d in progress. Poll count: %d +++", i_port, i_group, poll_count);
+ FAPI_INF( "+++ Calibration on %s port: %d rank group: %d in progress. Poll count: %d +++", i_target.toEcmdString(), i_port, i_group, poll_count);
poll_count++;
if(i_port == 0)
@@ -741,21 +749,23 @@ ReturnCode mss_check_cal_status( Target& i_target,
if(cal_status_buffer_64.isBitSet(cal_status_reg_offset))
{
- FAPI_INF( "+++ Calibration on port: %d rank group: %d finished. +++", i_port, i_group);
+ FAPI_INF( "+++ Calibration on %s port: %d rank group: %d finished. +++", i_target.toEcmdString(), i_port, i_group);
io_status = MSS_INIT_CAL_COMPLETE;
}
else
{
- FAPI_ERR( "+++ Calibration on port: %d rank group: %d has stalled! +++", i_port, i_group);
+ FAPI_ERR( "+++ Calibration on %s port: %d rank group: %d has stalled! +++", i_target.toEcmdString(), i_port, i_group);
io_status = MSS_INIT_CAL_STALL;
}
return rc;
}
-ReturnCode mss_check_error_status( Target& i_target,
+ReturnCode mss_check_error_status( Target& i_target,
+ uint8_t i_mbaPosition,
uint8_t i_port,
uint8_t i_group,
+ uint8_t cur_cal_step,
mss_draminit_training_result& io_status
)
{
@@ -780,44 +790,68 @@ ReturnCode mss_check_error_status( Target& i_target,
if(cal_error_buffer_64.isBitSet(48))
{
- FAPI_ERR( "+++ Write leveling error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Write leveling error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(50))
{
- FAPI_ERR( "+++ DQS Alignment error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ DQS Alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(51))
{
- FAPI_ERR( "+++ RDCLK to SysClk alignment error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ RDCLK to SysClk alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(52))
{
- FAPI_ERR( "+++ Read centering error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(53))
{
- FAPI_ERR( "+++ Write centering error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(55))
{
- FAPI_ERR( "+++ Coarse read centering error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Coarse read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(56))
{
- FAPI_ERR( "+++ Custom pattern read centering error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Custom pattern read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(57))
{
- FAPI_ERR( "+++ Custom pattern write centering error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Custom pattern write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
if(cal_error_buffer_64.isBitSet(58))
{
- FAPI_ERR( "+++ Digital eye error occured on port: %d rank group: %d! +++", i_port, i_group);
+ FAPI_ERR( "+++ Digital eye error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
}
}
else
{
- FAPI_INF( "+++ Calibration on port: %d rank group: %d was successful. +++", i_port, i_group);
+ if (cur_cal_step == 1)
+ {
+ FAPI_INF( "+++ Write_leveling on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
+ }
+ else if (cur_cal_step == 2)
+ {
+ FAPI_INF( "+++ DQS Alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
+ }
+ else if (cur_cal_step == 3)
+ {
+ FAPI_INF( "+++ RDCLK to SysClk alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
+ }
+ else if (cur_cal_step == 4)
+ {
+ FAPI_INF( "+++ Read Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
+ }
+ else if (cur_cal_step == 5)
+ {
+ FAPI_INF( "+++ Write Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
+ }
+ else if (cur_cal_step == 6)
+ {
+ FAPI_INF( "+++ Course Read and/or Course Write on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
+ }
+
io_status = MSS_INIT_CAL_PASS;
}
@@ -877,7 +911,7 @@ ReturnCode mss_read_center_workaround(
uint8_t l_timing_ref_quad2 = 0;
uint8_t l_timing_ref_quad3 = 0;
- FAPI_INF( "+++ Read Centering Workaround on MBA: %d Port: %d rank group: %d +++", i_mbaPosition, i_port, i_rank_group);
+ FAPI_INF( "+++ Read Centering Workaround on %s Port: %d rank group: %d +++", i_target.toEcmdString(), i_port, i_rank_group);
FAPI_INF( "+++ Choosing New RD PHASE SELECT values based on timing values. +++");
FAPI_INF( "+++ Incrementing DQS CLK PHASE SELECT regs based on timing values. +++");
@@ -1010,7 +1044,7 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
read_phase_value_quad0 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 0 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
+ FAPI_INF( "+++ ALL Blocks ALL Quads using workaround number %d with dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
if ( quad1_workaround_type == 0 )
{
@@ -1027,7 +1061,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
read_phase_value_quad1 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 0 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1);
if ( quad2_workaround_type == 0 )
{
@@ -1044,7 +1077,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
read_phase_value_quad2 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 0 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2);
if ( quad3_workaround_type == 0 )
{
@@ -1061,7 +1093,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
read_phase_value_quad3 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 0 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3);
rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
if (rc) return rc;
@@ -1119,7 +1150,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
read_phase_value_quad0 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 1 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
if ( quad1_workaround_type == 0 )
{
@@ -1136,7 +1166,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
read_phase_value_quad1 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 1 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1);
if ( quad2_workaround_type == 0 )
{
@@ -1153,7 +1182,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
read_phase_value_quad2 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 1 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2);
if ( quad3_workaround_type == 0 )
{
@@ -1170,7 +1198,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
read_phase_value_quad3 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 1 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3);
rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
@@ -1229,7 +1256,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
read_phase_value_quad0 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 2 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
if ( quad1_workaround_type == 0 )
{
@@ -1246,7 +1272,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
read_phase_value_quad1 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 2 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1);
if ( quad2_workaround_type == 0 )
{
@@ -1263,7 +1288,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
read_phase_value_quad2 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 2 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2);
if ( quad3_workaround_type == 0 )
{
@@ -1280,7 +1304,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
read_phase_value_quad3 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 2 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3);
rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
@@ -1338,7 +1361,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
read_phase_value_quad0 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 3 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
if ( quad1_workaround_type == 0 )
{
@@ -1355,7 +1377,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
read_phase_value_quad1 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 3 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1);
if ( quad2_workaround_type == 0 )
{
@@ -1372,7 +1393,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
read_phase_value_quad2 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 3 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2);
if ( quad3_workaround_type == 0 )
{
@@ -1389,7 +1409,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
read_phase_value_quad3 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 3 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3);
rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
@@ -1448,7 +1467,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
read_phase_value_quad0 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 4 Quad 0 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
if ( quad1_workaround_type == 0 )
{
@@ -1465,7 +1483,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
read_phase_value_quad1 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 4 Quad 1 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad1, read_phase_value_quad1);
if ( quad2_workaround_type == 0 )
{
@@ -1482,7 +1499,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
read_phase_value_quad2 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 4 Quad 2 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad2, read_phase_value_quad2);
if ( quad3_workaround_type == 0 )
{
@@ -1499,7 +1515,6 @@ ReturnCode mss_read_center_workaround(
dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
read_phase_value_quad3 = read_phase_value_wa2;
}
- FAPI_INF( "+++ Block 4 Quad 3 using workaround %d dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad3, read_phase_value_quad3);
rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
@@ -1541,8 +1556,660 @@ ReturnCode mss_read_center_workaround(
return rc;
}
+ReturnCode mss_read_center_second_workaround(
+ Target& i_target
+ )
+{
+ //MBA target level
+ //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte
+ //Across all byte lanes
+
+ uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
+ ecmdDataBufferBase data_buffer_64(64);
+ uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0;
+ uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0;
+ uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0;
+ uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0;
+ uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0;
+ uint64_t GATE_DELAY_ADDR_0 = 0;
+ uint64_t GATE_DELAY_ADDR_1 = 0;
+ uint64_t GATE_DELAY_ADDR_2 = 0;
+ uint64_t GATE_DELAY_ADDR_3 = 0;
+ uint64_t GATE_DELAY_ADDR_4 = 0;
+ uint8_t port = 0;
+ uint8_t rank_group = 0;
+ uint8_t l_value_n0_u8 = 0;
+ uint8_t l_value_n1_u8 = 0;
+ //uint8_t l_lowest_value_u8 = 0;
+ ReturnCode rc;
+ uint32_t rc_num = 0;
+
+ uint32_t block;
+ uint32_t maxblocks = 5;
+ uint32_t byte;
+ uint32_t maxbytes = 2;
+ uint32_t nibble;
+ uint32_t maxnibbles = 2;
+
+ uint8_t l_lowest_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
+ uint8_t l_gate_delay_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
+
+
+ //populate primary_ranks_arrays_array
+ rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
+ if(rc) return rc;
+ rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
+ if(rc) return rc;
+ rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
+ if(rc) return rc;
+ rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
+ if(rc) return rc;
+
+
+ for(port = 0; port < MAX_PORTS; port++)
+ {
+
+
+ //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
+
+ //Gather all the byte information
+ for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
+ {
+
+ //Initialize values
+ for(block = 0; block < maxblocks; block++)
+ {
+ for (byte = 0; byte < maxbytes; byte++)
+ {
+ for (nibble = 0; nibble < maxnibbles; nibble++)
+ {
+ l_lowest_value_u8[rank_group][block][byte][nibble] = 255;
+ l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255;
+ }
+ }
+ }
+
+ //Check if rank group exists
+ if(primary_ranks_array[rank_group][port] != 255)
+ {
+ FAPI_INF( "DQS_CLK Byte matching Workaround being applied on %s PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
+ if ( port == 0 )
+ {
+
+ if ( rank_group == 0 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
+
+ }
+ else if ( rank_group == 1 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
+
+ }
+ else if ( rank_group == 2 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
+
+ }
+ else if ( rank_group == 3 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
+
+ }
+ }
+ else if (port == 1 )
+ {
+
+ if ( rank_group == 0 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
+
+ }
+ else if ( rank_group == 1 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
+
+ }
+ else if ( rank_group == 2 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
+
+ }
+ else if ( rank_group == 3 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
+
+ }
+ }
+
+
+ // PHY BLOCK 0
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
+ l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
+ l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
+ l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
+ l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8;
+
+ // PHY BLOCK 1
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
+ l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
+ l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
+ l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
+ l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8;
+
+ // PHY BLOCK 2
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
+ l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
+ l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
+ l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
+ l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8;
+
+ // PHY BLOCK 3
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
+ l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
+ l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
+ l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
+ l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8;
+
+ // PHY BLOCK 4
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
+ l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
+ l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8;
+ l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
+ if (rc) return rc;
+ // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
+ l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8;
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
+ rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
+ l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8;
+ l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8;
+
+ }
+ }
+
+ //Finding the lowest Value
+ for(block = 0; block < maxblocks; block++)
+ {
+ for (byte = 0; byte < maxbytes; byte++)
+ {
+
+ for (nibble = 0; nibble < maxnibbles; nibble++)
+ {
+
+ if ( (l_lowest_value_u8[0][block][byte][nibble] == 0) ||
+ (l_lowest_value_u8[1][block][byte][nibble] == 0) ||
+ (l_lowest_value_u8[2][block][byte][nibble] == 0) ||
+ (l_lowest_value_u8[3][block][byte][nibble] == 0) )
+ {
+ if ( (l_lowest_value_u8[0][block][byte][nibble] == 3) ||
+ (l_lowest_value_u8[1][block][byte][nibble] == 3) ||
+ (l_lowest_value_u8[2][block][byte][nibble] == 3) ||
+ (l_lowest_value_u8[3][block][byte][nibble] == 3) )
+ {
+
+ //In this case alone we make all gate values equal the gate of the lowest DQSCLK
+ if (l_lowest_value_u8[0][block][byte][nibble] == 3)
+ {
+ l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble];
+ l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble];
+ l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble];
+ }
+ else if (l_lowest_value_u8[1][block][byte][nibble] == 3)
+ {
+ l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble];
+ l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble];
+ l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble];
+ }
+ else if (l_lowest_value_u8[2][block][byte][nibble] == 3)
+ {
+ l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble];
+ l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble];
+ l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble];
+ }
+ else if (l_lowest_value_u8[3][block][byte][nibble] == 3)
+ {
+ l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble];
+ l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble];
+ l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble];
+ }
+
+ l_lowest_value_u8[0][block][byte][nibble] = 3;
+ l_lowest_value_u8[1][block][byte][nibble] = 3;
+ l_lowest_value_u8[2][block][byte][nibble] = 3;
+ l_lowest_value_u8[3][block][byte][nibble] = 3;
+ }
+ else
+ {
+ l_lowest_value_u8[0][block][byte][nibble] = 0;
+ l_lowest_value_u8[1][block][byte][nibble] = 0;
+ l_lowest_value_u8[2][block][byte][nibble] = 0;
+ l_lowest_value_u8[3][block][byte][nibble] = 0;
+
+ }
+ }
+ else if ( (l_lowest_value_u8[0][block][byte][nibble] == 2) ||
+ (l_lowest_value_u8[1][block][byte][nibble] == 2) ||
+ (l_lowest_value_u8[2][block][byte][nibble] == 2) ||
+ (l_lowest_value_u8[3][block][byte][nibble] == 2) )
+ {
+ if ( (l_lowest_value_u8[0][block][byte][nibble] == 1) ||
+ (l_lowest_value_u8[1][block][byte][nibble] == 1) ||
+ (l_lowest_value_u8[2][block][byte][nibble] == 1) ||
+ (l_lowest_value_u8[3][block][byte][nibble] == 1) )
+ {
+ l_lowest_value_u8[0][block][byte][nibble] = 1;
+ l_lowest_value_u8[1][block][byte][nibble] = 1;
+ l_lowest_value_u8[2][block][byte][nibble] = 1;
+ l_lowest_value_u8[3][block][byte][nibble] = 1;
+
+ }
+ else
+ {
+ l_lowest_value_u8[0][block][byte][nibble] = 2;
+ l_lowest_value_u8[1][block][byte][nibble] = 2;
+ l_lowest_value_u8[2][block][byte][nibble] = 2;
+ l_lowest_value_u8[3][block][byte][nibble] = 2;
+
+ }
+ }
+
+ }
+ }
+
+ }
+
+
+ //Scoming in the New Values
+ for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
+ {
+
+ //Check if rank group exists
+ if(primary_ranks_array[rank_group][port] != 255)
+ {
+
+ if ( port == 0 )
+ {
+
+ if ( rank_group == 0 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
+
+ }
+ else if ( rank_group == 1 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
+
+ }
+ else if ( rank_group == 2 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
+
+ }
+ else if ( rank_group == 3 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
+
+ }
+ }
+ else if (port == 1 )
+ {
+
+ if ( rank_group == 0 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
+
+ }
+ else if ( rank_group == 1 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
+
+ }
+ else if ( rank_group == 2 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
+
+ }
+ else if ( rank_group == 3 )
+ {
+ DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
+ DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
+ DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
+ DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
+ DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
+ GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
+ GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
+ GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
+ GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
+ GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
+
+ }
+ }
+
+ //BLOCK 0
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 48, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 52, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 56, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 60, 2);
+ rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
+ if (rc) return rc;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3);
+ rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
+ if (rc) return rc;
+
+ //BLOCK 1
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 48, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 52, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 56, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 60, 2);
+ rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
+ if (rc) return rc;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3);
+ rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
+ if (rc) return rc;
+
+ //BLOCK 2
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 48, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 52, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 56, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 60, 2);
+ rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
+ if (rc) return rc;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3);
+ rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
+ if (rc) return rc;
+
+ //BLOCK 3
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 48, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 52, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 56, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 60, 2);
+ rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
+ if (rc) return rc;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3);
+ rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
+ if (rc) return rc;
+
+ //Block 4
+ rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 48, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 52, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 56, 2);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 60, 2);
+ rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
+ if (rc) return rc;
+
+ rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
+ if (rc) return rc;
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3);
+ rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3);
+ rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
+ if (rc) return rc;
+
+ }
+ }
+ }
+
+ return rc;
+}
+
+
ReturnCode mss_rtt_nom_rtt_wr_swap(
Target& i_target,
+ uint8_t i_mbaPosition,
uint32_t i_port_number,
uint8_t i_rank,
uint32_t i_rank_pair_group,
@@ -1675,7 +2342,7 @@ ReturnCode mss_rtt_nom_rtt_wr_swap(
// MRS CMD to CMD spacing = 12 cycles
rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
- FAPI_INF( "Editing RTT_NOM during wr_lvl for PORT%d RP%d", i_port_number, i_rank_pair_group);
+ FAPI_INF( "Editing RTT_NOM during wr_lvl for %s PORT: %d RP: %d", i_target.toEcmdString(), i_port_number, i_rank_pair_group);
//MRS1
// Get contents of MRS 1 Shadow Reg
diff --git a/src/usr/hwpf/hwp/include/cen_scom_addresses.H b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
index 3865eeb7c..a06f96e50 100755
--- a/src/usr/hwpf/hwp/include/cen_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/cen_scom_addresses.H
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: cen_scom_addresses.H,v 1.56 2013/04/04 20:32:53 jdsloat Exp $
+// $Id: cen_scom_addresses.H,v 1.57 2013/04/11 23:41:36 jdsloat Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/cen_scom_addresses.H,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
@@ -44,6 +44,7 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|-----------------------------------------------
+// 1.56 | jdsloat |11-Apr-13| Added DQS Gate Delay Values
// 1.55 | jdsloat |04-Apr-13| Added DPHY01_DDRPHY_WC_CONFIG3 regs
// 1.54 | jdsloat |03-Apr-13| Fixed MR Sec shadow regs
// 1.53 | jdsloat |08-Mar-13| Added MBA01_MBARPC0Q_0x03010434
@@ -1362,7 +1363,7 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143
//------------------------------------------------------------------------------
-// DQS Gate Delay Rank Pair 0
+// DQS Gate Delay
//------------------------------------------------------------------------------
CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F , ULL(0x800000130301143F) );
CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F , ULL(0x800004130301143F) );
@@ -1375,6 +1376,39 @@ CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F , ULL(
CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F , ULL(0x80010C130301143F) );
CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F , ULL(0x800110130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F , ULL(0x800001130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F , ULL(0x800005130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F , ULL(0x800009130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F , ULL(0x80000D130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F , ULL(0x800011130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F , ULL(0x800101130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F , ULL(0x800105130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F , ULL(0x800109130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F , ULL(0x80010D130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F , ULL(0x800111130301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F , ULL(0x800002130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F , ULL(0x800006130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F , ULL(0x80000A130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F , ULL(0x80000E130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F , ULL(0x800012130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F , ULL(0x800102130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F , ULL(0x800106130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F , ULL(0x80010A130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F , ULL(0x80010E130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F , ULL(0x800112130301143F) );
+
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F , ULL(0x800003130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F , ULL(0x800007130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F , ULL(0x80000B130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F , ULL(0x80000F130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F , ULL(0x800013130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F , ULL(0x800103130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F , ULL(0x800107130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F , ULL(0x80010B130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F , ULL(0x80010F130301143F) );
+CONST_UINT64_T( DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F , ULL(0x800113130301143F) );
+
//------------------------------------------------------------------------------
// RC config registers 0 and 3
@@ -1578,6 +1612,9 @@ This section is automatically updated by CVS when you check in this file.
Be sure to create CVS comments when you commit so that they can be included here.
$Log: cen_scom_addresses.H,v $
+Revision 1.57 2013/04/11 23:41:36 jdsloat
+Added DQS Gate Delay Values
+
Revision 1.56 2013/04/04 20:32:53 jdsloat
Added DPHY01_DDRPHY_WC_CONFIG3 regs
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
index a9192ad09..6d086b1a8 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.custom.scom.initfile
@@ -1,8 +1,9 @@
-#-- $Id: cen.dmi.custom.scom.initfile,v 1.6 2013/03/15 21:21:27 thomsen Exp $
+#-- $Id: cen.dmi.custom.scom.initfile,v 1.7 2013/04/18 19:20:50 jgrell Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date: | Comment:
#-- --------|--------|--------|--------------------------------------------------
+#-- 1.7 |jgrell |04/18/13|Added EC level control of the Recal DFE, DDC, and CTLE enable bits. ('0' when EC < 20)
#-- 1.6 |jgrell |03/14/13|Added temporary masking of the GCR Buffer Parity Checkers in the GCR Master until the source of the error can be found. This ungates the lab.
#-- 1.5 |thomsen |03/07/13|Temporarily mask the GCR Buffer Parity Checker until the source of the error can be found. This ungates the lab.
#-- | | |Fixed address typo on tx_clk_invert entry
@@ -374,6 +375,20 @@ scom_data;
0xC000000000000000;
}
+#--**************************************************************************************************************
+#----------------------------------------------------------------------------------------------------------------
+# Recal
+#----------------------------------------------------------------------------------------------------------------
+#--**************************************************************************************************************
+# HW235842
+
+scom 0x800.0b(rx_rc_step_cntl_pg)(rx_grp0)(lane_na).0x(cn_gcr_addr) {
+bits, scom_data, expr;
+rx_rc_enable_dfe_h1_cal, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_DFE_ENABLE==0;
+rx_rc_enable_ddc, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_DDC_ENABLE==0;
+rx_rc_enable_ctle_cal, 0b0, ATTR_CHIP_EC_FEATURE_RECAL_CTLE_ENABLE==0;
+}
+
############################################################################################
# END OF FILE
############################################################################################
diff --git a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
index 3e2abbaa6..96b7ce8c2 100644
--- a/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/cen.dmi.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: cen.dmi.scom.initfile,v 1.11 2013/03/20 18:11:01 jgrell Exp $
+#-- $Id: cen.dmi.scom.initfile,v 1.12 2013/04/18 19:20:14 jgrell Exp $
####################################################################
@@ -7,13 +7,14 @@
## Based on SETUP_ID_MODE DMI_BUS_TR_HW
## from ../../logic/mesa_sim/fusion/run/IODNC_MB_TOP.IODNC_MB_TOP.figdb
##
-## Created on Wed Mar 20 11:03:01 CDT 2013, by jgrell
+## Created on Mon Apr 15 15:04:16 CDT 2013, by jgrell
####################################################################
## -- CHANGE HISTORY:
## --------------------------------------------------------------------------------
## -- VersionID: |Author: | Date: | Comment:
## -- -----------|---------|--------|-------------------------------------------------
+ ## -- jgr13041800| jgr |04-18-13| Added rx_max_ber_check_count setting to 0x03
## -- jgr13031300| jgr |03-13-13| Added missing entries from rel 0128
## -- mbs13011802| mbs |01-18-13| Added rx_fence to run_mode dial (HW236326)
## -- mbs13011000| mbs |01-10-13| Added rx_prot_speed_slct and rx_c4_sel
@@ -65,6 +66,13 @@ include edi.io.define
+#RX.RXCTL.RX_CTL_REGS.RX_BER_CHK_PG
+scom 0x800AF0000201043F {
+ bits, scom_data, expr;
+ rx_max_ber_check_count, 0b00000011 , def_IS_HW;
+ rx_max_ber_check_count, 0b00000000 , def_IS_VBU;
+}
+
#RX.RXCTL.RX_CTL_REGS.RX_DFE_CONFIG_PP
scom 0x800B78000201043F {
bits, scom_data, expr;
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 7637934af..195df9e3c 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,11 @@
-#-- $Id: mba_def.initfile,v 1.37 2013/04/04 21:24:21 yctschan Exp $
+#-- $Id: mba_def.initfile,v 1.39 2013/04/17 16:55:32 yctschan Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date: | Comment:
#-- --------|--------|--------|--------------------------------------------------
+#-- 1.39|tschang | 4/17/13|commented out maxall_min0 power controls until decision has been made for default value
+#-- 1.38|tschang | 4/08/13|set cfg_min_domain_reduction_enable to 1 and maxall_min0 power controls
#-- 1.37|tschang | 4/04/13|ACT signal in CCS idle pattern set to 1 for DDR4 and 0 for non DDR4
#-- 1.36|tschang | 4/04/13|MBA_FARB2Q fixed rank master typo for IS1A_IS1B_IS1D_C1A_C1B_C1C_C1D_C5C cfg
#-- 1.35|tschang | 3/27/13|set trfc and refresh interval according to refresh equation
@@ -2168,6 +2170,7 @@ scom 0x03010432 {
#
scom 0x03010434 {
bits , scom_data , ATTR_FUNCTIONAL, expr;
+# 3:5 , 0b010 , 1 , any; # cfg_min_max_domains 36
6:10 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1); # MBARPC0Q_cfg_pup_avail 36
6:10 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1); # MBARPC0Q_cfg_pup_avail 36
6:10 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1); # MBARPC0Q_cfg_pup_avail 36
@@ -2187,6 +2190,7 @@ scom 0x03010434 {
16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38
16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38
16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38
+ 22 , 0b1 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls
}
# MBAPC1Q power control settings reg 1
diff --git a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
index e30b0999c..73e583ae7 100644
--- a/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mbs_def.initfile
@@ -1,8 +1,10 @@
-#-- $Id: mbs_def.initfile,v 1.29 2013/04/08 15:52:55 yctschan Exp $
+#-- $Id: mbs_def.initfile,v 1.31 2013/04/17 14:41:41 yctschan Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date: | Comment:
#-- --------|--------|--------|--------------------------------------------------
+#-- 1.30 |tschang |04/17/13| hash mode updated for type 1a/1b/5b
+#-- 1.30 |tschang |04/16/13| updated file for new IBM_TYPE defnitions
#-- 1.29 |tschang |04/08/13| added MBI cfg register initialization for Irving
#-- 1.26 |tschang |03/13/13| changed cache interleave mode to have ATTR_MSS_CACHE_ENABLE as a condition
#-- 1.25 |tschang |01/17/13| cache enabled when (ATTR_MSS_CACHE_ENABLE != 0) - enabled cache when 1/2 cache mode is choosen
@@ -111,82 +113,82 @@ define def_mba01_1c_cdimm = ((((MBA0.ATTR_CHIP_UNIT_POS == 1 ) && (MBA0
## Current they is no 1D IBM type in the attribute
#define def_mba01_1d_1socket = 0;
#define def_mba01_1d_2socket = 0;
-define def_mba01_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
-define def_mba01_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
-#define def_mba01_1d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-#define def_mba01_1d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+#define def_mba01_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
+#define def_mba01_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
+define def_mba01_1d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba01_1d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs
-define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm));
-define def_mba01_2a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_2c_cdimm) || (def_mba01_3a_cdimm));
-define def_mba01_2a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg
-define def_mba01_2a_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm));
-define def_mba01_2a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3a_ddr4_cdimm));
-define def_mba01_2a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 4 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg
-
-define def_mba01_2b_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_cdimm));
-define def_mba01_2b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_mba01_2b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg
-define def_mba01_2b_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_ddr4_cdimm));
-define def_mba01_2b_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3b_ddr4_cdimm));
-define def_mba01_2b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg
+define def_mba01_2a_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm));
+define def_mba01_2a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_2c_cdimm) || (def_mba01_3a_cdimm));
+define def_mba01_2a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg
+define def_mba01_2a_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm));
+define def_mba01_2a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3a_ddr4_cdimm));
+define def_mba01_2a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 5 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg
+
+define def_mba01_2b_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_cdimm));
+define def_mba01_2b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_mba01_2b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg
+define def_mba01_2b_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2b_ddr4_cdimm));
+define def_mba01_2b_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3b_ddr4_cdimm));
+define def_mba01_2b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg
# centuar spec only has DDR4 for 2C cfg
-define def_mba01_2c_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm));
-define def_mba01_2c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_mba01_2c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket cfg
-define def_mba01_2c_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm));
-define def_mba01_2c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3c_ddr4_cdimm));
-define def_mba01_2c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 6 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket DDR4 cfg
-
-define def_mba01_3a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba01_3a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_cdimm));
-#define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 2 socket cfg
-define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0) && (MBA0.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg
-define def_mba01_3a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba01_3a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_ddr4_cdimm));
-define def_mba01_3a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0) && (MBA0.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg
-
-define def_mba01_3b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba01_3b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_mba01_3b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg
-define def_mba01_3b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg ??
-
-define def_mba01_3c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba01_3c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4c_ddr4_cdimm));
-define def_mba01_3c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
-define def_mba01_3c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
-
-define def_mba01_4a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket cfg
-define def_mba01_4a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket DDR4 cfg
-
-define def_mba01_4b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3B 2 socket DDR4 cfg
-
-define def_mba01_4c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 12))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3C 2 socket DDR4 cfg
-
-define def_mba01_5b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 14))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_5b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 14))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-
-define def_mba01_5c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_5c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-
-define def_mba01_5d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_5d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-
-define def_mba01_7a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 20))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 20))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 20))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7a_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 20))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-
-define def_mba01_7b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7b_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7b_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-
-define def_mba01_7c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba01_7c_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_2c_1socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_cdimm));
+define def_mba01_2c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_mba01_2c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket cfg
+define def_mba01_2c_1socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba01_2a_ddr4_cdimm));
+define def_mba01_2c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_3c_ddr4_cdimm));
+define def_mba01_2c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 7 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket DDR4 cfg
+
+define def_mba01_3a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba01_3a_2socket = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_cdimm));
+#define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 2 socket cfg
+define def_mba01_3a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0) && (MBA0.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg
+define def_mba01_3a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba01_3a_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4a_ddr4_cdimm));
+define def_mba01_3a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 8 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 0) && (MBA0.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg
+
+define def_mba01_3b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba01_3b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_mba01_3b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg
+define def_mba01_3b_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 9 ))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg ??
+
+define def_mba01_3c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba01_3c_2socket_ddr4 = (((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba01_4c_ddr4_cdimm));
+define def_mba01_3c_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
+define def_mba01_3c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 10))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
+
+define def_mba01_4a_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket cfg
+define def_mba01_4a_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 11))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket DDR4 cfg
+
+define def_mba01_4b_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 12))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3B 2 socket DDR4 cfg
+
+define def_mba01_4c_ddr4_cdimm = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 13))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 0)); # same as type3C 2 socket DDR4 cfg
+
+define def_mba01_5b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_5b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+
+define def_mba01_5c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_5c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 16))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+
+define def_mba01_5d_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 17))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_5d_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 17))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+
+define def_mba01_7a_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7a_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7a_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7a_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 21))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+
+define def_mba01_7b_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7b_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7b_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7b_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 22))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+
+define def_mba01_7c_1socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7c_2socket = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7c_1socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba01_7c_2socket_ddr4 = ((((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 23))) && (MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA0.ATTR_EFF_DIMM_TYPE == 3));
# MBA1 (mba23)
define def_mba23_1a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)); # DDR3/4 are same
@@ -207,82 +209,82 @@ define def_mba23_1c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 3 ))) &
## Current they is no 1D IBM type in the attribute
#define def_mba23_1d_1socket = 0;
#define def_mba23_1d_2socket = 0;
-define def_mba23_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
-define def_mba23_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
-#define def_mba23_1d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-#define def_mba23_1d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+#define def_mba23_1d_1socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
+#define def_mba23_1d_2socket = (ATTR_MSS_FREQ == 1400) ; # will evaluate to false
+#efine def_mba23_1d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+#efine def_mba23_1d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
## note the CDIMMs 2A-2C CDIMMs are wired just like the single slot ISDIMMs
-define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm));
-define def_mba23_2a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_2c_cdimm) || (def_mba23_3a_cdimm));
-define def_mba23_2a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg
-define def_mba23_2a_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm));
-define def_mba23_2a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3a_ddr4_cdimm));
-define def_mba23_2a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 4 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg
-
-define def_mba23_2b_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_cdimm));
-define def_mba23_2b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_mba23_2b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg
-define def_mba23_2b_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_ddr4_cdimm));
-define def_mba23_2b_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3b_ddr4_cdimm));
-define def_mba23_2b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg
+define def_mba23_2a_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm));
+define def_mba23_2a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_2c_cdimm) || (def_mba23_3a_cdimm));
+define def_mba23_2a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket cfg
+define def_mba23_2a_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm));
+define def_mba23_2a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3a_ddr4_cdimm));
+define def_mba23_2a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 5 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 1 socket DDR4 cfg
+
+define def_mba23_2b_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_cdimm));
+define def_mba23_2b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_mba23_2b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket cfg
+define def_mba23_2b_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2b_ddr4_cdimm));
+define def_mba23_2b_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3b_ddr4_cdimm));
+define def_mba23_2b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 1 socket DDR4 cfg
# centuar spec only has DDR4 for 2C cfg
-define def_mba23_2c_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm));
-define def_mba23_2c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_mba23_2c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket cfg
-define def_mba23_2c_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm));
-define def_mba23_2c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3c_ddr4_cdimm));
-define def_mba23_2c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 6 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket DDR4 cfg
+define def_mba23_2c_1socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_cdimm));
+define def_mba23_2c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_mba23_2c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket cfg
+define def_mba23_2c_1socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1)) || (def_mba23_2a_ddr4_cdimm));
+define def_mba23_2c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_3c_ddr4_cdimm));
+define def_mba23_2c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 1 socket DDR4 cfg
-define def_mba23_3a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba23_3a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_cdimm));
-#define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 2 socket cfg
-define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0) && (MBA1.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg
-define def_mba23_3a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba23_3a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_ddr4_cdimm));
-define def_mba23_3a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 7 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0) && (MBA1.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg
+define def_mba23_3a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba23_3a_2socket = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_cdimm));
+#define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2A 2 socket cfg
+define def_mba23_3a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0) && (MBA1.ATTR_EFF_DRAM_GEN == 1)); # same as type2A 2 socket DDR4 cfg
+define def_mba23_3a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba23_3a_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4a_ddr4_cdimm));
+define def_mba23_3a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 0) && (MBA1.ATTR_EFF_DRAM_GEN == 2)); # same as type2A 2 socket DDR4 cfg
-define def_mba23_3b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba23_3b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
-define def_mba23_3b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg
-define def_mba23_3b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 8 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg ??
+define def_mba23_3b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba23_3b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2));
+define def_mba23_3b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg
+define def_mba23_3b_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2B 2 socket DDR4 cfg ??
-define def_mba23_3c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
-define def_mba23_3c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4c_ddr4_cdimm));
-define def_mba23_3c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
-define def_mba23_3c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 9 ))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
+define def_mba23_3c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1));
+define def_mba23_3c_2socket_ddr4 = (((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2)) || (def_mba23_4c_ddr4_cdimm));
+define def_mba23_3c_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
+define def_mba23_3c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type2C 2 socket DDR4 cfg
-define def_mba23_4a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket cfg
-define def_mba23_4a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 10))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket DDR4 cfg
+define def_mba23_4a_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket cfg
+define def_mba23_4a_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3A 2 socket DDR4 cfg
-define def_mba23_4b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 11))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3B 2 socket DDR4 cfg
+define def_mba23_4b_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3B 2 socket DDR4 cfg
-define def_mba23_4c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 12))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3C 2 socket DDR4 cfg
+define def_mba23_4c_ddr4_cdimm = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 13))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 0)); # same as type3C 2 socket DDR4 cfg
-define def_mba23_5b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 14))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_5b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 14))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_5b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_5b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_5c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_5c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_5c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_5c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_5d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_5d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 16))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_5d_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 17))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_5d_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 17))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 20))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 20))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 20))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7a_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 20))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7a_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7a_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7a_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7a_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7b_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7b_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 21))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7b_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7b_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7b_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7b_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
-define def_mba23_7c_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 22))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7c_1socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7c_2socket = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7c_1socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 1) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
+define def_mba23_7c_2socket_ddr4 = ((((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 23))) && (MBA1.ATTR_EFF_NUM_DROPS_PER_PORT == 2) && (MBA1.ATTR_EFF_DIMM_TYPE == 3));
define def_mba01_mtype_1a = (def_mba01_1a_1socket ||def_mba01_1a_2socket);# ||def_mba01_1b_cdimm);
@@ -387,10 +389,6 @@ define def_mba23_Planar_DIMM_with_both_DIMM_slots_0_and_1_populated = (def_mb
#define def_ATTR_MSS_CACHE_ENABLE = 0; # cache disable
#define def_ATTR_MSS_PREFETCH_ENABLE = 0; # prefetch disable
#define def_ATTR_MSS_MBA_ADDR_INTERLEAVE_BIT = 0; # no MBA interleave
-#define def_01ATTR_MSS_HASH_MODE = 0; # -MW switched to match dials
-#define def_23ATTR_MSS_HASH_MODE = 1;
-#define def_01ATTR_MSS_HASH_MODE = 1;
-#define def_23ATTR_MSS_HASH_MODE = 0;
#define def_01ATTR_MSS_MBA_INTERLEAVE_MODE = 0;
#define def_23ATTR_MSS_MBA_INTERLEAVE_MODE = 0;
#define def_01ATTR_EFF_MBA_POS = 0; # -MW not needed?
@@ -549,6 +547,30 @@ scom 0x0201140A {
5 , 0b0 , any ; # Z mode only
}
+# Hash mode Selection
+# Select hash mode with most interleaving (higher hash number)
+# Section 5.6 in centuar workbook for hashing
+# MBA01 Type 1A - simplied table to hash mode 1 when both dimm configured
+define def_mba01_hash1_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.ATTR_EFF_IBM_TYPE[0][1] == 1)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0);
+define def_mba01_hash0_type1a = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 1) || (MBA0.ATTR_EFF_IBM_TYPE[0][1] == 1)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0));
+# Type 1B/5B - simplied table to hash mode 2 when both dimm configured and hash mode 1 when 1 dimm is configured
+define def_mba01_hash2_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] != 0) && (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] != 0);
+define def_mba01_hash1_type1b_5b = ((MBA0.ATTR_EFF_IBM_TYPE[0][0] == 2) || (MBA0.ATTR_EFF_IBM_TYPE[0][0] == 15)) && ((MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][0] == 0) || (MBA0.ATTR_EFF_DIMM_RANKS_CONFIGED[0][1] == 0));
+
+# MBA23 Type 1A - simplied table to hash mode 1 when both dimm configured
+define def_mba23_hash1_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0);
+define def_mba23_hash0_type1a = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 1) || (MBA1.ATTR_EFF_IBM_TYPE[1][1] == 1)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0));
+# Type 1B/5B - simplied table to hash mode 2 when both dimm configured and hash mode 1 when 1 dimm is configured
+define def_mba23_hash2_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] != 0) && (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] != 0);
+define def_mba23_hash1_type1b_5b = ((MBA1.ATTR_EFF_IBM_TYPE[1][0] == 2) || (MBA1.ATTR_EFF_IBM_TYPE[1][0] == 15)) && ((MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][0] == 0) || (MBA1.ATTR_EFF_DIMM_RANKS_CONFIGED[1][1] == 0));
+
+define def_mba01_hash0_sel = (def_mba01_hash0_type1a);
+define def_mba01_hash1_sel = (def_mba01_hash1_type1a) || (def_mba01_hash1_type1b_5b);
+define def_mba01_hash2_sel = (def_mba01_hash1_type1b_5b);
+
+define def_mba23_hash0_sel = (def_mba23_hash0_type1a);
+define def_mba23_hash1_sel = (def_mba23_hash1_type1a) || (def_mba23_hash1_type1b_5b);
+define def_mba23_hash2_sel = (def_mba23_hash1_type1b_5b);
####################################
# MBA01 address translation config #
####################################
@@ -582,12 +604,12 @@ scom 0x0201140B {
# 8 , 0b1 , 1 , ((((MBA0.ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1); # MBAXCR01Q_MBA01_Configuration D
9 , 0b1 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA01_DRAM_Width D
9 , 0b0 , 1 , (MBA0.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA01_DRAM_Width D
- 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode
- 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode
- 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode
-# 12 , 0b0 , 1 , any; # -MW match dials # MBAXCR01Q_MBA01_Interleave_Mode
-# 12 , 0b0 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0); # MBAXCR01Q_MBA01_Interleave_Mode
-# 12 , 0b1 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1); # MBAXCR01Q_MBA01_Interleave_Mode
+ 10:11 , 0b00 , 1 , def_mba01_hash0_sel; # MBAXCR01Q_MBA01_Hash_Mode
+ 10:11 , 0b01 , 1 , def_mba01_hash1_sel; # MBAXCR01Q_MBA01_Hash_Mode
+ 10:11 , 0b10 , 1 , def_mba01_hash2_sel; # MBAXCR01Q_MBA01_Hash_Mode
+# 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA01_Hash_Mode
+# 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA01_Hash_Mode
+# 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA01_Hash_Mode
12 , 0b0 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0) || (ATTR_MSS_CACHE_ENABLE != 1)); # MBAXCR01Q_MBA01_Interleave_Mode
12 , 0b1 , 1 , ((SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1) && (ATTR_MSS_CACHE_ENABLE == 1)); # MBAXCR01Q_MBA01_Interleave_Mod
}
@@ -625,9 +647,9 @@ scom 0x0201140C {
# 8 , 0b1 , 1 , ((((ATTR_EFF_NUM_DROPS_PER_PORT == 2) || (ATTR_EFF_DIMM_TYPE == 0)) && (MBA0.ATTR_CHIP_UNIT_POS == 0)) == 1); # MBAXCR01Q_MBA23_Configuration D
9 , 0b1 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 4); # MBAXCR01Q_MBA23_DRAM_Width D
9 , 0b0 , 1 , (MBA1.ATTR_EFF_DRAM_WIDTH == 8); # MBAXCR01Q_MBA23_DRAM_Width D
- 10:11 , 0b00 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 0); # MBAXCR01Q_MBA23_Hash_Mode
- 10:11 , 0b01 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 1); # MBAXCR01Q_MBA23_Hash_Mode
- 10:11 , 0b10 , 1 , (SYS.ATTR_MSS_MCA_HASH_MODE == 2); # MBAXCR01Q_MBA23_Hash_Mode
+ 10:11 , 0b00 , 1 , def_mba23_hash0_sel; # MBAXCR01Q_MBA23_Hash_Mode
+ 10:11 , 0b01 , 1 , def_mba23_hash1_sel; # MBAXCR01Q_MBA23_Hash_Mode
+ 10:11 , 0b10 , 1 , def_mba23_hash2_sel; # MBAXCR01Q_MBA23_Hash_Mode
# 12 , 0b0 , 1 , any; # -MW match dials # MBAXCR01Q_MBA23_Interleave_Mode
12 , 0b0 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 0); # MBAXCR01Q_MBA23_Interleave_Mode
12 , 0b1 , 1 , (SYS.ATTR_MSS_MBA_CACHELINE_INTERLEAVE_MODE == 1); # MBAXCR01Q_MBA23_Interleave_Mode
diff --git a/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile
new file mode 100644
index 000000000..c458b4a06
--- /dev/null
+++ b/src/usr/hwpf/hwp/initfiles/p8.cxa.scom.initfile
@@ -0,0 +1,46 @@
+#-- $Id: p8.cxa.scom.initfile,v 1.2 2013/04/08 13:50:19 jmcgill Exp $
+#-------------------------------------------------------------------------------
+#--
+#-- (C) Copyright International Business Machines Corp. 2011
+#-- All Rights Reserved -- Property of IBM
+#-- *** IBM Confidential ***
+#--
+#-- TITLE : p8.cxa.scom.initfile
+#-- DESCRIPTION : Perform CAPP configuration
+#--
+#-- OWNER NAME : Bill Daly Email: billdaly@us.ibm.com
+#--
+#--------------------------------------------------------------------------------
+
+SyntaxVersion = 1
+
+#--------------------------------------------------------------------------------
+#-- Includes
+#--------------------------------------------------------------------------------
+
+#--------------------------------------------------------------------------------
+#-- Defines
+#--------------------------------------------------------------------------------
+
+#--------------------------------------------------------------------------------
+#-- SCOM initializations
+#--------------------------------------------------------------------------------
+
+
+#-- APC Master Config Register
+scom 0x02013019 {
+ bits , scom_data, expr;
+ 4:7 , 0b0000, (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); #-- HANG_POLL_SCALE
+}
+
+#-- CAPP Snoop Control Register
+scom 0x0201301B {
+ bits , scom_data, expr;
+ 48:51 , 0b0010, (ATTR_CHIP_EC_FEATURE_CAPP_HANG_CONTROL_ON_SCOM != 0); #-- CXA_SNP_DATA_HANG_POLL_SCALE
+}
+
+#-- CAPP Transport Control Register
+scom 0x0201301C {
+ bits , scom_data;
+ 15:18 , 0b1000; #-- TLBI_DATA_POLL_PULSE_DIV
+}
diff --git a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
index 1914e579c..67dee1974 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.mcs.scom.initfile
@@ -1,8 +1,12 @@
-#-- $Id: p8.mcs.scom.initfile,v 1.2 2013/03/25 03:08:07 jmcgill Exp $
+#-- $Id: p8.mcs.scom.initfile,v 1.4 2013/04/08 20:22:28 jmcgill Exp $
#-- CHANGE HISTORY:
#--------------------------------------------------------------------------------
#-- Version:|Author: | Date: | Comment:
#-- --------|--------|--------|--------------------------------------------------
+#-- 1.30|baysah |04/04/13|- Set MCI Replay timeout value to 2ms.
+#-- | | |- Disable MCS arbiter blocking after checkstop.
+#-- | | |
+#-- --------|--------|--------|--------------------------------------------------
#-- 1.00|baysah |08/12/12|Created MCS init file
#-- --------|--------|--------|--------------------------------------------------
#--------------------------------------------------------------------------------
@@ -79,7 +83,7 @@ SyntaxVersion = 1
47 , 0b1 ; # MCMODE2Q_ENABLE_MIRROR_WR_HANG
48 , 0b1 ; # MCMODE2Q_ENABLE_AO_HANG
49 , 0b1 ; # MCMODE2Q_ENABLE_INBAND_HANG
- 50:52, 0b110 ; # MCMODE2Q_NONMIRROR_HANG_VALUE
+ 50:52, 0b101 ; # MCMODE2Q_NONMIRROR_HANG_VALUE
53:55, 0b111 ; # MCMODE2Q_MIRROR_HANG_VALUE
56 , 0b1 ; # MCMODE2Q_ENABLE_EMER_THROTTLE
57 , 0b0 ; # MCMODE2Q_DRIVE_SHARED_PRESP_WITH_LOST_CLAIM
@@ -108,6 +112,7 @@ SyntaxVersion = 1
#--******************************************************************************
scom 0x000000000201181A {
bits , scom_data ;
+ 1:3, 0b111 ; # DISABLE INTERFACE AND ARBITER BLOCKING DURING INTERNAL MCS CHECKSTOP
17:18, 0b01 ; # MCMODE4Q_SELECT_RPTHANG_DECODE
19 , 0b1 ; # MCMODE4Q_LOCAL_TIMEBASE_SELECT
}
@@ -123,4 +128,38 @@ SyntaxVersion = 1
14:23, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD1
24:33, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD2
34:43, 0b0000000000 ; # MCBUSYQ_BUSY_COUNTER_THRESHOLD3
-} \ No newline at end of file
+}
+
+
+#--******************************************************************************
+#-- MCI Configuration Register
+#--******************************************************************************
+ scom 0x000000000201184A {
+ bits , scom_data ;
+ 0 , 0b0 ; # MCICFGQ_FORCE_CHANNEL_FAIL
+ 1 , 0b0 ; # MCICFGQ_REPLAY_CRC_DISABLE
+ 2 , 0b0 ; # MCICFGQ_REPLAY_NOACK_DISABLE
+ 3 , 0b0 ; # MCICFGQ_REPLAY_OUTOFORDER_DISABLE
+ 4 , 0b0 ; # MCICFGQ_FORCE_LFSR_REPLAY
+ 5 , 0b0 ; # MCICFGQ_CRC_CHECK_DISABLE
+ 6 , 0b0 ; # MCICFGQ_ECC_CHECK_DISABLE
+ 7 , 0b0 ; # MCICFGQ_START_FRAME_LOCK
+ 8 , 0b0 ; # MCICFGQ_START_FRTL
+ 9 , 0b0 ; # MCICFGQ_AUTO_FRTL_DISABLE
+ 10:16, 0b0000000 ; # MCICFGQ_MANUAL_FRTL_VALUE
+ 17 , 0x0 ; # MCICFGQ_MANUAL_FRTL_DONE
+ 18 , 0b0 ; # MCICFGQ_ECC_CORRECT_DISABLE
+ 19 , 0b0 ; # MCICFGQ_SPARE1
+ 20 , 0b0 ; # MCICFGQ_LANE_VOTING_BYPASS
+ 21:25, 0b00000 ; # MCICFGQ_BAD_LANE_VALUE
+ 26 , 0b0 ; # MCICFGQ_BAD_LANE_VOTING_DISABLE
+ 27:32, 0b001001 ; # MCICFGQ_NO_FORWARD_PROGRESS_TIMEOUT_VALUE (0x09 = 9 => 1ms)
+ 33:34, 0b00 ; # MCICFGQ_PERFORMANCE_DEGRADATION_PERCENT_SELECT
+ 35:36, 0b00 ; # MCICFGQ_CHANNEL_INITIALIZATION_STATE_MACHINE_TIMEOUT_VALUE
+ 37 , 0b0 ; # MCICFGQ_RESET_KEEPER
+ 38:41, 0b0001 ; # MCICFGQ_REPLAY_DELAY_VALUE (set to 1 for pSeries, which is default value)
+ 42:43, 0b00 ; # MCICFGQ_RESERVED
+
+ }
+
+
diff --git a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
index c1df2f029..589150e03 100644
--- a/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
+++ b/src/usr/hwpf/hwp/initfiles/p8.nx.scom.initfile
@@ -1,4 +1,4 @@
-#-- $Id: p8.nx.scom.initfile,v 1.5 2013/03/25 21:38:50 jmcgill Exp $
+#-- $Id: p8.nx.scom.initfile,v 1.6 2013/04/08 13:48:09 jmcgill Exp $
#-------------------------------------------------------------------------------
#--
#-- (C) Copyright International Business Machines Corp. 2011
@@ -330,23 +330,3 @@ scom 0x02013107 {
48 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit" ;
49 , 0b0 ; #-- 0b00 mask FIR/SCOM satellite parity error FIR bit duplicate"
}
-
-
-
-#-- APC Master Config Register
-scom 0x02013019 {
- bits , scom_data ;
- 4:7 , 0b0000 ; #-- HANG_POLL_SCALE
-}
-
-#-- CAPP Snoop Control Register
-scom 0x0201301B {
- bits , scom_data ;
- 48:51 , 0b0010 ; #-- CXA_SNP_DATA_HANG_POLL_SCALE
-}
-
-#-- CAPP Transport Control Register
-scom 0x0201301C {
- bits , scom_data ;
- 15:18 , 0b1000 ; #-- TLBI_DATA_POLL_PULSE_DIV
-}
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
index 340bd6f7d..82dc4344d 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_eff_config.C,v 1.21 2013/03/22 21:57:25 asaetow Exp $
+// $Id: mss_eff_config.C,v 1.24 2013/04/22 14:17:45 asaetow Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
// centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $
//------------------------------------------------------------------------------
@@ -44,12 +44,15 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|-----------------------------------------------
-// 1.22 | | |
-// 1.21 | asaetow |22-Mar-13| Changed ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL back to enable.
+// 1.25 | | |
+// 1.24 | asaetow |19-APR-13| Fixed X4 CDIMM spare for RCB to use LOW_NIBBLE only.
+// 1.23 | asaetow |17-APR-13| Added 10% margin to TRFI per defect HW248225
+// 1.22 | asaetow |11-APR-13| Changed eff_dram_tdqs from 0 back to 1 for X8 ISDIMMs.
+// 1.21 | asaetow |22-MAR-13| Changed ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL back to enable.
// | | | NOTE: Need mba_def.initfile v1.27 or newer
-// 1.20 | asaetow |28-Feb-13| Changed temporary ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL to disable.
+// 1.20 | asaetow |28-FEB-13| Changed temporary ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL to disable.
// | | | NOTE: Temporary until we get timeout error fixed.
-// 1.19 | sauchadh |26-Feb-13| Added MCBIST related attributes
+// 1.19 | sauchadh |26-FEB-13| Added MCBIST related attributes
// 1.18 | asaetow |12-FEB-13| Changed eff_dram_tdqs from 1 to 0.
// 1.17 | asaetow |30-JAN-13| Changed "ATTR_SPD_MODULE_TYPE_CDIMM is obsolete..." message from error to warning.
// 1.16 | bellows |24-JAN-13| Added in CUSTOM bit of SPD and CUSTOM Attr
@@ -1188,13 +1191,19 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
== fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W4)
{
p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4;
+ p_o_atts->eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE;
}
else if (p_i_data->dram_width[0][0]
== fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W8)
{
p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8;
// NOTE: TDQS enable MR1(A11) is only avaliable for X8 in DDR3
- p_o_atts->eff_dram_tdqs = 0;
+ // TDQS disabled for X8 DDR3 CDIMM, enable for ISDIMM
+ if ( p_o_atts->eff_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO ) {
+ p_o_atts->eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE;
+ } else {
+ p_o_atts->eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE;
+ }
}
else if (p_i_data->dram_width[0][0]
== fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W16)
@@ -1541,6 +1550,8 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
// Calculate tRFI
p_o_atts->eff_dram_trfi = (3900 *
p_i_mss_eff_config_data->mss_freq) / 2000;
+ // Added 10% margin to TRFI per defect HW248225
+ p_o_atts->eff_dram_trfi = (p_o_atts->eff_dram_trfi * 9) / 10;
// Assigning dependent values to attributes
for (int l_cur_mba_port = 0; l_cur_mba_port <
@@ -1588,12 +1599,16 @@ fapi::ReturnCode mss_eff_config_setup_eff_atts(
if (( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)
&& ( l_cur_mba_rank < p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] ))
{
- p_o_atts->
- eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
- = fapi::ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE;
+ // Added for CDIMM RC_B which uses x4 parts
+ if ( p_o_atts->eff_dram_width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4 ) {
+ p_o_atts->eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
+ = fapi::ENUM_ATTR_EFF_DIMM_SPARE_LOW_NIBBLE;
+ } else {
+ p_o_atts->eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
+ = fapi::ENUM_ATTR_EFF_DIMM_SPARE_FULL_BYTE;
+ }
} else {
- p_o_atts->
- eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
+ p_o_atts->eff_dimm_spare[l_cur_mba_port][l_cur_mba_dimm][l_cur_mba_rank]
= fapi::ENUM_ATTR_EFF_DIMM_SPARE_NO_SPARE;
}
}
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
index 99086973d..4316c4d7c 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_eff_config_rank_group.C,v 1.9 2013/04/01 20:08:03 asaetow Exp $
+// $Id: mss_eff_config_rank_group.C,v 1.10 2013/04/17 11:26:02 asaetow Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
@@ -46,7 +46,9 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|-----------------------------------------------
-// 1.10 | | |
+// 1.11 | | |
+// 1.10 | asaetow |17-APR-13| Removed 32G CDIMM 1R dualdrop workaround.
+// | | | NOTE: Needs mss_draminit_training.C v1.57 or newer.
// 1.9 | asaetow |01-APR-13| Added 32G CDIMM 1R dualdrop workaround.
// | | | NOTE: Normally primary_rank_group0=0, primary_rank_group1=4.
// 1.8 | asaetow |29-AUG-12| Fixed variable init for rank_group to INVALID for PORT1.
@@ -136,25 +138,28 @@ fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) {
uint8_t quanternary_rank_group3_u8array[PORT_SIZE];
for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) {
- if ((dimm_type_u8 == CDIMM) && (num_ranks_per_dimm_u8array[cur_port][0] == 1) && (num_ranks_per_dimm_u8array[cur_port][1] == 1)) {
+ //Removed 32G CDIMM 1R dualdrop workaround.
+ //NOTE: Needs mss_draminit_training.C v1.57 or newer.
+ //if ((dimm_type_u8 == CDIMM) && (num_ranks_per_dimm_u8array[cur_port][0] == 1) && (num_ranks_per_dimm_u8array[cur_port][1] == 1)) {
// NOTE: 32G CDIMM 1R dualdrop workaround, normally primary_rank_group0=0, primary_rank_group1=4.
- primary_rank_group0_u8array[cur_port] = 0;
- primary_rank_group1_u8array[cur_port] = INVALID;
- primary_rank_group2_u8array[cur_port] = INVALID;
- primary_rank_group3_u8array[cur_port] = INVALID;
- secondary_rank_group0_u8array[cur_port] = 4;
- secondary_rank_group1_u8array[cur_port] = INVALID;
- secondary_rank_group2_u8array[cur_port] = INVALID;
- secondary_rank_group3_u8array[cur_port] = INVALID;
- tertiary_rank_group0_u8array[cur_port] = INVALID;
- tertiary_rank_group1_u8array[cur_port] = INVALID;
- tertiary_rank_group2_u8array[cur_port] = INVALID;
- tertiary_rank_group3_u8array[cur_port] = INVALID;
- quanternary_rank_group0_u8array[cur_port] = INVALID;
- quanternary_rank_group1_u8array[cur_port] = INVALID;
- quanternary_rank_group2_u8array[cur_port] = INVALID;
- quanternary_rank_group3_u8array[cur_port] = INVALID;
- } else if (dimm_type_u8 == LRDIMM) {
+ //primary_rank_group0_u8array[cur_port] = 0;
+ //primary_rank_group1_u8array[cur_port] = INVALID;
+ //primary_rank_group2_u8array[cur_port] = INVALID;
+ //primary_rank_group3_u8array[cur_port] = INVALID;
+ //secondary_rank_group0_u8array[cur_port] = 4;
+ //secondary_rank_group1_u8array[cur_port] = INVALID;
+ //secondary_rank_group2_u8array[cur_port] = INVALID;
+ //secondary_rank_group3_u8array[cur_port] = INVALID;
+ //tertiary_rank_group0_u8array[cur_port] = INVALID;
+ //tertiary_rank_group1_u8array[cur_port] = INVALID;
+ //tertiary_rank_group2_u8array[cur_port] = INVALID;
+ //tertiary_rank_group3_u8array[cur_port] = INVALID;
+ //quanternary_rank_group0_u8array[cur_port] = INVALID;
+ //quanternary_rank_group1_u8array[cur_port] = INVALID;
+ //quanternary_rank_group2_u8array[cur_port] = INVALID;
+ //quanternary_rank_group3_u8array[cur_port] = INVALID;
+ //} else if (dimm_type_u8 == LRDIMM) {
+ if (dimm_type_u8 == LRDIMM) {
// HERE: NOT correct, need to account for ATTR_EFF_DIMM_RANKS_CONFIGED for LRDIMMs /w multi master ranks
primary_rank_group0_u8array[cur_port] = 0;
primary_rank_group1_u8array[cur_port] = 4;
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
index 0d6e0d323..2bfadd4be 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: mss_eff_grouping.C,v 1.23 2013/03/27 15:36:37 bellows Exp $
+// $Id: mss_eff_grouping.C,v 1.24 2013/04/09 20:34:54 bellows Exp $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2011
// *! All Rights Reserved -- Property of IBM
@@ -38,14 +38,15 @@
//------------------------------------------------------------------------------
// Version:| Author: | Date: | Comment:
//---------|----------|---------|-----------------------------------------------
+// 1.24 | bellows | 04-09-13| Updates that really allow checkboard and all group sizes. Before, group size of 1 was all that was possible
// 1.23 | bellows | 03-26-13| Allow for checkboard mode with more than one mcs per group
// 1.22 | bellows | 03-21-13| Error Logging support
// 1.21 | bellows | 03-11-13| Fixed syntax error with respect to the fapi macro under cronus
// 1.20 | bellows | 03-08-13| Proper way to deconfigure mulitple/variable MCS
// 1.19 | bellows | 02-27-13| Added back in mirror overlap check. Added in error rc for grouping
// 1.18 | asaetow | 02-01-13| Removed FAPI_ERR("Mirror Base address overlaps with memory base address. "); temporarily.
-// | | | NOTE: Need Giri to check mirroring enable before checking for overlaps.
-// 1.17 | gpaulraj | 01-31-13| Error place holders added
+// | | | NOTE: Need Giri to check mirroring enable before checking for overlaps.
+// 1.17 | gpaulraj | 01-31-13| Error place holders added
// 1.16 | gpaulraj | 12-14-12| Modified "nnable to group dimm size" as Error message
// 1.15 | bellows | 12-11-12| Picked up latest updates from Girisankar
// 1.14 | bellows | 12-11-12| added ; to DBG line
@@ -67,7 +68,7 @@
#include <mss_eff_grouping.H>
#include <fapi.H>
#include "cen_scom_addresses.H"
-//#include <mss_error_support.H>
+#include <mss_error_support.H>
//#include <mss_funcs.H>
//#ifdef FAPIECMD
@@ -246,34 +247,51 @@ extern "C" {
FAPI_INF("FABRIC IS IN NON-CHECKER BOARD MODE.");
FAPI_INF("FABRIC SUPPORTS THE FOLLOWING ");
- if( (groups_allowed & 0x02)&& check_board){FAPI_INF("2MCS/GROUP");}
- if( (groups_allowed & 0x04)&& check_board){FAPI_INF("4MCS/GROUP");}
- if( (groups_allowed & 0x08)&& check_board){FAPI_INF("8MCS/GROUP");}
+ if(groups_allowed & 0x02){FAPI_INF("2MCS/GROUP");}
+ if(groups_allowed & 0x04){FAPI_INF("4MCS/GROUP");}
+ if(groups_allowed & 0x08){FAPI_INF("8MCS/GROUP");}
FAPI_INF("FABRIC DOES NOT SUPPORT THE FOLLOWING ");
- if(! ((groups_allowed & 0x01)&& !check_board)){FAPI_INF("1MCS/GROUP");}
- if(!((groups_allowed & 0x02)&& check_board)){FAPI_INF("2MCS/GROUP");}
- if(!((groups_allowed & 0x04)&& check_board)){FAPI_INF("4MCS/GROUP");}
- if(!((groups_allowed & 0x08)&& check_board)){FAPI_INF("8MCS/GROUP");}
+ FAPI_INF("1MCS/GROUP");
+ if(!(groups_allowed & 0x02)){FAPI_INF("2MCS/GROUP");}
+ if(!(groups_allowed & 0x04)){FAPI_INF("4MCS/GROUP");}
+ if(!(groups_allowed & 0x08)){FAPI_INF("8MCS/GROUP");}
}
else
{
FAPI_ERR("UNABLE TO GROUP");
- FAPI_ERR("FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. ");
+ FAPI_ERR("FABRIC IS IN NON-CHECKER BOARD MODE. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' , TO SUPPORT 2MCS , 4MCS AND 8MCS GROUPING. OR ENABLE CHECKER BOARD. ");
+//@thi - hack const fapi::Target & PROC_CHIP = i_target;
FAPI_SET_HWP_ERROR(rc, RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE);
return rc;
}
}
else // Fabric is in checkerboard mode, allow all sizes. Anything but 1 will have performance impacts
{
- if(groups_allowed & 0x01) {
- FAPI_INF("FABRIC IS IN CHECKER BOARD MODE AND IT SUPPORTS 1MCS/GROUP"); }
- else {
-// FAPI_ERR("UNABLE TO GROUP");
-// FAPI_ERR("FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP AND 8MCS/GROUP'.");
-// const fapi::Target & PROC_CHIP = i_target;
-// FAPI_SET_HWP_ERROR(rc, RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE);
-// return rc;
- FAPI_INF("FABRIC IS IN CHECKER BOARD MODE BUT YOU ARE ASKING FOR MORE THAN 1MCS/GROUP. YOU ARE NOT GOING TO HAVE PERFOMRANCE YOU COULD GET IF YOU WERE IN CHECKERBOARD MODE");
+ if((groups_allowed & 0x01) || (groups_allowed & 0x02) || (groups_allowed & 0x04)||(groups_allowed & 0x08))
+ {
+ FAPI_INF("FABRIC IS IN CHECKER BOARD MODE AND IT SUPPORTS THE FOLLOWING ");
+ if(groups_allowed & 0x01){FAPI_INF("1MCS/GROUP");}
+ if(groups_allowed & 0x02){FAPI_INF("2MCS/GROUP");}
+ if(groups_allowed & 0x04){FAPI_INF("4MCS/GROUP");}
+ if(groups_allowed & 0x08){FAPI_INF("8MCS/GROUP");}
+ FAPI_INF("FABRIC DOES NOT SUPPORT THE FOLLOWING ");
+ if(!(groups_allowed & 0x01)){FAPI_INF("FABRIC IS IN CHECKER BOARD MODE BUT YOU ARE ASKING FOR MORE THAN 1MCS/GROUP. YOU ARE NOT GOING TO HAVE PERFOMRANCE YOU COULD GET IF YOU WERE IN CHECKERBOARD MODE");}
+ if(!(groups_allowed & 0x02)){FAPI_INF("2MCS/GROUP");}
+ if(!(groups_allowed & 0x04)){FAPI_INF("4MCS/GROUP");}
+ if(!(groups_allowed & 0x08)){FAPI_INF("8MCS/GROUP");}
+ if((groups_allowed & 0x02) || (groups_allowed & 0x04)||(groups_allowed & 0x08)){FAPI_INF("FABRIC IS IN CHECKER BOARD MODE BUT YOU ARE ASKING FOR MORE THAN 1MCS/GROUP. YOU ARE NOT GOING TO HAVE PERFOMRANCE YOU COULD GET IF YOU WERE IN CHECKERBOARD MODE");}
+
+
+
+
+ }
+ else
+ {
+ FAPI_ERR("UNABLE TO GROUP");
+ FAPI_ERR("FABRIC IS IN CHECKER BOARD MODE . SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' ");
+//@thi - hack const fapi::Target & PROC_CHIP = i_target;
+ FAPI_SET_HWP_ERROR(rc, RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE);
+ return rc;
}
@@ -308,7 +326,7 @@ extern "C" {
done = 0 ;
- if(!done && (groups_allowed & 0x08) && check_board)
+ if(!done && (groups_allowed & 0x08))
{
count =0;
@@ -338,7 +356,7 @@ extern "C" {
}
}
- if(!done && (groups_allowed & 0x04) && check_board)
+ if(!done && (groups_allowed & 0x04))
{
count=0;
for(uint8_t i=0;i<6;i++)
@@ -433,7 +451,7 @@ extern "C" {
}
}
}
- if(!done && (groups_allowed & 0x02) && check_board)
+ if(!done && (groups_allowed & 0x02))
{
for(pos=0;pos< gp_pos;pos=pos+2)
{
@@ -453,7 +471,7 @@ extern "C" {
}
}
}
- if(!done && (groups_allowed & 0x01)&& !check_board)
+ if(!done && (groups_allowed & 0x01) && !check_board)
{
for(pos=0;pos< gp_pos;pos++)
{
@@ -484,7 +502,7 @@ extern "C" {
ungroup++;
if(ungroup == 1) { // First time, call out the Main error
FAPI_SET_HWP_ERROR(ungroup_rc, RC_MSS_UNABLE_TO_GROUP_SUMMARY);
- }
+ }
const fapi::Target & TARGET_MCS = l_proc_chiplets[i];
FAPI_ADD_INFO_TO_HWP_ERROR(rc, RC_MSS_UNABLE_TO_GROUP_MCS);
@@ -650,6 +668,7 @@ extern "C" {
else
{
FAPI_ERR("Mirror Base address overlaps with memory base address. ");
+//@thi - hack const fapi::Target & PROC_CHIP = i_target;
FAPI_SET_HWP_ERROR(rc, RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS);
return rc;
}
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
index 5892dbd05..51f913ac7 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.C
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_chiplet_scominit.C,v 1.11 2013/03/25 02:39:41 jmcgill Exp $
+// $Id: proc_chiplet_scominit.C,v 1.12 2013/04/08 13:49:08 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.C,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2012
@@ -146,6 +146,22 @@ fapi::ReturnCode proc_chiplet_scominit(const fapi::Target & i_target)
break;
}
+ // execute CXA SCOM initfile
+ FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
+ PROC_CHIPLET_SCOMINIT_CXA_IF, i_target.toEcmdString());
+ FAPI_EXEC_HWP(
+ rc,
+ fapiHwpExecInitFile,
+ initfile_targets,
+ PROC_CHIPLET_SCOMINIT_CXA_IF);
+ if (!rc.ok())
+ {
+ FAPI_ERR("proc_chiplet_scominit: Error from fapiHwpExecInitfile executing %s on %s",
+ PROC_CHIPLET_SCOMINIT_CXA_IF,
+ i_target.toEcmdString());
+ break;
+ }
+
// execute AS SCOM initfile
FAPI_INF("proc_chiplet_scominit: Executing %s on %s",
PROC_CHIPLET_SCOMINIT_AS_IF, i_target.toEcmdString());
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H
index 0019ee938..1c6a42a61 100644
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H
+++ b/src/usr/hwpf/hwp/nest_chiplets/proc_chiplet_scominit/proc_chiplet_scominit.H
@@ -20,7 +20,7 @@
/* Origin: 30 */
/* */
/* IBM_PROLOG_END_TAG */
-// $Id: proc_chiplet_scominit.H,v 1.10 2013/03/25 02:39:43 jmcgill Exp $
+// $Id: proc_chiplet_scominit.H,v 1.11 2013/04/08 13:49:12 jmcgill Exp $
// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_chiplet_scominit.H,v $
//------------------------------------------------------------------------------
// *! (C) Copyright International Business Machines Corp. 2012
@@ -54,6 +54,7 @@ const char * const PROC_CHIPLET_SCOMINIT_PSI_IF = "p8.psi.scom.if";
const char * const PROC_CHIPLET_SCOMINIT_TPBRIDGE_IF = "p8.tpbridge.scom.if";
const char * const PROC_CHIPLET_SCOMINIT_NX_IF = "p8.nx.scom.if";
const char * const PROC_CHIPLET_SCOMINIT_AS_IF = "p8.as.scom.if";
+const char * const PROC_CHIPLET_SCOMINIT_CXA_IF = "p8.cxa.scom.if";
const char * const PROC_CHIPLET_SCOMINIT_MCS_IF = "p8.mcs.scom.if";
//------------------------------------------------------------------------------
@@ -82,6 +83,7 @@ extern "C" {
* - p8.psi.scom.initfile
* - p8.tpbridge.scom.initfile
* - p8.nx.scom.initfile
+ * - p8.cxa.scom.initfile
* - p8.as.scom.initfile
* - p8.mcs.scom.initfile for each functional MCS chiplet
*
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index a8ae92228..244e8115b 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -138,7 +138,8 @@ HWP_INITFILES = hwp/initfiles/sample.initfile \
hwp/initfiles/p8.abus.custom.scom.initfile \
hwp/initfiles/p8.xbus.custom.scom.initfile \
hwp/initfiles/p8.psi.scom.initfile \
- hwp/initfiles/p8.tpbridge.scom.initfile
+ hwp/initfiles/p8.tpbridge.scom.initfile \
+ hwp/initfiles/p8.cxa.scom.initfile
HWP_IF_DEFINE_DIR = hwp/initfiles
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