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| author | Dan Crowell <dcrowell@us.ibm.com> | 2016-04-08 21:03:51 -0500 |
|---|---|---|
| committer | Stephen Cprek <smcprek@us.ibm.com> | 2016-04-21 13:51:32 -0500 |
| commit | 76f1c48130a060fbe83c851fce2474c17b2df9b2 (patch) | |
| tree | e258515dcbdab5817603c9d290befe2324df7d59 /src/usr/hwpf/hwp/include/p8_scom_addresses.H | |
| parent | 3967f43b9478d7e6b58180dd0b331e61412997cd (diff) | |
| download | talos-hostboot-76f1c48130a060fbe83c851fce2474c17b2df9b2.tar.gz talos-hostboot-76f1c48130a060fbe83c851fce2474c17b2df9b2.zip | |
Removing some more old fapi1 and hwp code
Deleted all of the old fapi1 code
Moved potentially reuseable occ code to a new dir
Deleted a variety of p8 hwp files
Change-Id: I8b6ab72fef3f1413d919bdd21bc88f2c4f59c5c3
RTC: 146345
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23075
Tested-by: Jenkins Server
Tested-by: FSP CI Jenkins
Reviewed-by: Matt Derksen <v2cibmd@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/include/p8_scom_addresses.H')
| -rwxr-xr-x | src/usr/hwpf/hwp/include/p8_scom_addresses.H | 2909 |
1 files changed, 0 insertions, 2909 deletions
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H deleted file mode 100755 index b0f9f52fe..000000000 --- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H +++ /dev/null @@ -1,2909 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/include/p8_scom_addresses.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: p8_scom_addresses.H,v 1.199 2015/09/16 19:33:47 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : p8_scom_addresses.H -// *! DESCRIPTION : Defines for P8 scom addresses -// *! OWNER NAME : Jeshua Smith Email: jeshua@us.ibm.com -// *! BACKUP NAME : Email: @us.ibm.com -// #! ADDITIONAL COMMENTS : -// -// The purpose of this header is to define scom addresses for use by procedures. -// This will help catch address typos at compile time, and will make it easy -// to track down which procedures use each address -// - -#ifndef P8_SCOM_ADDRESSES -#define P8_SCOM_ADDRESSES - -//---------------------------------------------------------------------- -// Scom address overview -//---------------------------------------------------------------------- -// P8 uses 64-bit scom addresses, which are classified into two formats: -// -// "Normal" (legacy) format -// -// 111111 11112222 22222233 33333333 44444444 44555555 55556666 -// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 -// -------- -------- -------- -------- -------- -------- -------- -------- -// 00000000 00000000 00000000 00000000 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL -// || | | -// || | `-> Local Address* -// || | -// || `-> Port -// || -// |`-> Chiplet ID** -// | -// `-> Multicast bit -// -// * Local address is composed of "00" + 4-bit ring + 10-bit ID -// The 10-bit ID is usually 4-bit sat_id and 6-bit reg_id -// -// ** Chiplet ID turns into multicast operation type and group number -// if the multicast bit is set -// -// "Indirect" format -// -// -// 111111 11112222 22222233 33333333 44444444 44555555 55556666 -// 01234567 89012345 67890123 45678901 23456789 01234567 89012345 67890123 -// -------- -------- -------- -------- -------- -------- -------- -------- -// 10000000 0000IIII IIIIIGGG GGGLLLLL 0MCCCCCC ????PPPP 00LLLLLL LLLLLLLL -// | | | || | | -// | | | || | `-> Local Address* -// | | | || | -// | | | || `-> Port -// | | | || -// | | | |`-> Chiplet ID** -// | | | | -// | | | `-> Multicast bit -// | | | -// | | `-> Lane ID -// | | -// | `-> RX or TX Group ID -// | -// `-> Indirect Register Address -// -// * Local address is composed of "00" + 4-bit ring + 4-bit sat_id + "111111" -// -// ** Chiplet ID turns into multicast operation type and group number -// if the multicast bit is set -// - -#include "common_scom_addresses.H" -#include "fapi_sbe_common.H" - -/******************************************************************************/ -/********************************** CHIPLET *********************************/ -/******************************************************************************/ -// use for lpcs P0, <chipletID> -CONST_UINT64_T( X_BUS_CHIPLET_0x04000000 , ULL(0x04000000) ); -CONST_UINT64_T( PCIE_CHIPLET_0x09000000 , ULL(0x09000000) ); -CONST_UINT64_T( A_BUS_CHIPLET_0x08000000 , ULL(0x08000000) ); -// EX00_CHIPLET - EX15_CHIPLET defined in the EX CHIPLET section -// "Multicast" chiplets -CONST_UINT64_T( ALL_CHIPLETS_OR_0x40000000 , ULL(0x40000000) ); -CONST_UINT64_T( ALL_CHIPLETS_AND_0x48000000 , ULL(0x48000000) ); -CONST_UINT64_T( ALL_CHIPLETS_BITX_0x50000000 , ULL(0x50000000) ); -CONST_UINT64_T( ALL_CHIPLETS_COMP_0x60000000 , ULL(0x60000000) ); -CONST_UINT64_T( ALL_CHIPLETS_WRITE_0x68000000 , ULL(0x68000000) ); - -// Group 1 : EX chiplets -CONST_UINT64_T( ALL_EXS_OR_0x41000000 , ULL(0x41000000) ); -CONST_UINT64_T( ALL_EXS_AND_0x49000000 , ULL(0x49000000) ); -CONST_UINT64_T( ALL_EXS_BITX_0x51000000 , ULL(0x51000000) ); -CONST_UINT64_T( ALL_EXS_COMP_0x61000000 , ULL(0x61000000) ); -CONST_UINT64_T( ALL_EXS_WRITE_0x69000000 , ULL(0x69000000) ); -CONST_UINT64_T( WRITE_ALL_EXS_GP0_AND_0x69000004 , ULL(0x69000004) ); -CONST_UINT64_T( WRITE_ALL_EXS_GP0_OR_0x69000005 , ULL(0x69000005) ); -CONST_UINT64_T( WRITE_ALL_EXS_CLK_REGION_0x69030006 , ULL(0x69030006) ); -CONST_UINT64_T( WRITE_ALL_EXS_CLK_SCANSEL_0x69030007 , ULL(0x69030007) ); -CONST_UINT64_T( READ_OR_ALL_EXS_CLK_STATUS_0x41030008 , ULL(0x41030008) ); -CONST_UINT64_T( WRITE_ALL_EXS_GP3_AND_0x690F0013 , ULL(0x690F0013) ); -CONST_UINT64_T( WRITE_ALL_EXS_GP3_OR_0x690F0014 , ULL(0x690F0014) ); -//CONST_UINT64_T( WRITE_EX_GP3_AND_0x690F0013 , ULL(0x690F0013) ); // and all EX GP3 -//CONST_UINT64_T( WRITE_EX_GP3_OR_0x690F0014 , ULL(0x690F0014) ); // or all EX GP3 -//CONST_UINT64_T( WRITE_EX_PMGP0_OR_0x690F0102 , ULL(0x690F0102) ); // or all EX PMGP0 - -CONST_UINT64_T( ALL_CORES_OR_0x42000000 , ULL(0x42000000) ); -CONST_UINT64_T( ALL_CORES_AND_0x4A000000 , ULL(0x4A000000) ); -CONST_UINT64_T( ALL_CORES_BITX_0x52000000 , ULL(0x52000000) ); -CONST_UINT64_T( ALL_CORES_COMP_0x62000000 , ULL(0x62000000) ); -CONST_UINT64_T( ALL_CORES_WRITE_0x6A000000 , ULL(0x6A000000) ); - - -CONST_UINT64_T( DEVICE_ID_REG_0x000F000F , ULL(0x000F000F) ); - - -/******************************************************************************/ -/******************************** TP CHIPLET ********************************/ -/******************************************************************************/ - - - //------------------------------------------------------------------------------ - // MULTICAST REGISTER DEFINITION - //------------------------------------------------------------------------------ - CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_RWx690F0103 , ULL(0x690F0103) ); - CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_WANDx690F0104 , ULL(0x690F0104) ); - CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 , ULL(0x690F0105) ); - CONST_UINT64_T( WRITE_ALL_PCBSPM_MODE_REG_0x690F0156 , ULL(0x690F0156) ); - CONST_UINT64_T( WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D , ULL(0x690F015D) ); - - -//------------------------------------------------------------------------------ -// FSI MBOX (CFAM) -//------------------------------------------------------------------------------ -CONST_UINT32_T( CFAM_FSI_INTR_MASK_0x0000081C , ULL(0x0000081C) ); -CONST_UINT32_T( CFAM_FSI_INTR_STATUS_0x0000100B , ULL(0x0000100B) ); -CONST_UINT32_T( CFAM_FSI_TRUE_MASK_0x0000100D , ULL(0x0000100D) ); -CONST_UINT32_T( CFAM_FSI_GP3_0x00002812 , ULL(0x00002812) ); -CONST_UINT32_T( CFAM_FSI_GP4_0x00002813 , ULL(0x00002813) ); -CONST_UINT32_T( CFAM_FSI_GP5_0x00002814 , ULL(0x00002814) ); -CONST_UINT32_T( CFAM_FSI_GP6_0x00002815 , ULL(0x00002815) ); -CONST_UINT32_T( CFAM_FSI_GP7_0x00002816 , ULL(0x00002816) ); -CONST_UINT32_T( CFAM_FSI_GP8_0x00002817 , ULL(0x00002817) ); -CONST_UINT32_T( CFAM_FSI_WRITE_PROTECT_0x00002818 , ULL(0x00002818) ); -CONST_UINT32_T( CFAM_OSCSW_SENSE1_0x00002819 , ULL(0x00002819) ); -CONST_UINT32_T( CFAM_OSCSW_SENSE2_0x0000281A , ULL(0x0000281A) ); -CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000281B , ULL(0x0000281B) ); -CONST_UINT32_T( CFAM_FSI_SBE_VITAL_0x0000281C , ULL(0x0000281C) ); - -CONST_UINT64_T( MBOX_SCRATCH_REG0_0x00002838 , ULL(0x00002838) ); -CONST_UINT64_T( MBOX_SCRATCH_REG1_0x00002839 , ULL(0x00002839) ); -CONST_UINT64_T( MBOX_SCRATCH_REG2_0x0000283A , ULL(0x0000283A) ); -CONST_UINT64_T( MBOX_SCRATCH_REG3_0x0000283B , ULL(0x0000283B) ); - -//------------------------------------------------------------------------------ -// OTPROM -//------------------------------------------------------------------------------ -CONST_UINT64_T( OTPC_M_COMMAND_REGISTER_0x00010000 , ULL(0x00010000) ); -CONST_UINT64_T( OTPC_M_STATUS_REGISTER_0x00010002 , ULL(0x00010002) ); -CONST_UINT64_T( OTPC_M_DATA_REGISTER_0x00010003 , ULL(0x00010003) ); -CONST_UINT64_T( OTPC_M_SECURITY_SWITCH_0x00010005 , ULL(0x00010005) ); -CONST_UINT64_T( OTPC_M_MODE_REGISTER_0x00010008 , ULL(0x00010008) ); -CONST_UINT64_T( OTPC_M_PRGM_REGISTER_0x00010009 , ULL(0x00010009) ); -CONST_UINT64_T( ECID_PART_0_0x00018000 , ULL(0x00018000) ); -CONST_UINT64_T( ECID_PART_1_0x00018001 , ULL(0x00018001) ); -CONST_UINT64_T( ECID_PART_12_0x0001800C , ULL(0x0001800C) ); -CONST_UINT64_T( ECID_PART_13_0x0001800D , ULL(0x0001800D) ); -CONST_UINT64_T( ECID_PART_14_0x0001800E , ULL(0x0001800E) ); -CONST_UINT64_T( ECID_PART_15_0x0001800F , ULL(0x0001800F) ); -CONST_UINT64_T( ECID_PART_16_0x00018010 , ULL(0x00018010) ); -CONST_UINT64_T( ECID_PART_17_0x00018011 , ULL(0x00018011) ); -CONST_UINT64_T( ECID_PART_18_0x00018012 , ULL(0x00018012) ); -CONST_UINT64_T( ECID_PART_19_0x00018013 , ULL(0x00018013) ); -CONST_UINT64_T( ECID_PART_20_0x00018014 , ULL(0x00018014) ); -CONST_UINT64_T( ECID_PART_21_0x00018015 , ULL(0x00018015) ); -CONST_UINT64_T( ECID_PART_22_0x00018016 , ULL(0x00018016) ); -CONST_UINT64_T( ECID_PART_23_0x00018017 , ULL(0x00018017) ); - - -//------------------------------------------------------------------------------ -// Time of Day (TOD) -//------------------------------------------------------------------------------ -CONST_UINT64_T( TOD_M_PATH_CTRL_REG_00040000 , ULL(0x00040000) ); -CONST_UINT64_T( TOD_PRI_PORT_0_CTRL_REG_00040001 , ULL(0x00040001) ); -CONST_UINT64_T( TOD_PRI_PORT_1_CTRL_REG_00040002 , ULL(0x00040002) ); -CONST_UINT64_T( TOD_SEC_PORT_0_CTRL_REG_00040003 , ULL(0x00040003) ); -CONST_UINT64_T( TOD_SEC_PORT_1_CTRL_REG_00040004 , ULL(0x00040004) ); -CONST_UINT64_T( TOD_S_PATH_CTRL_REG_00040005 , ULL(0x00040005) ); -CONST_UINT64_T( TOD_I_PATH_CTRL_REG_00040006 , ULL(0x00040006) ); -CONST_UINT64_T( TOD_PSS_MSS_CTRL_REG_00040007 , ULL(0x00040007) ); -CONST_UINT64_T( TOD_PSS_MSS_STATUS_REG_00040008 , ULL(0x00040008) ); -CONST_UINT64_T( TOD_M_PATH_STATUS_REG_00040009 , ULL(0x00040009) ); -CONST_UINT64_T( TOD_S_PATH_STATUS_REG_0004000A , ULL(0x0004000A) ); -CONST_UINT64_T( TOD_MISC_RESET_REG_0004000B , ULL(0x0004000B) ); -CONST_UINT64_T( TOD_PROBE_SELECT_REG_0004000C , ULL(0x0004000C) ); -CONST_UINT64_T( TOD_CHIP_CTRL_REG_00040010 , ULL(0x00040010) ); -CONST_UINT64_T( TOD_TX_TTYPE_0_REG_00040011 , ULL(0x00040011) ); -CONST_UINT64_T( TOD_TX_TTYPE_1_REG_00040012 , ULL(0x00040012) ); -CONST_UINT64_T( TOD_TX_TTYPE_2_REG_00040013 , ULL(0x00040013) ); -CONST_UINT64_T( TOD_TX_TTYPE_3_REG_00040014 , ULL(0x00040014) ); -CONST_UINT64_T( TOD_TX_TTYPE_4_REG_00040015 , ULL(0x00040015) ); -CONST_UINT64_T( TOD_TX_TTYPE_5_REG_00040016 , ULL(0x00040016) ); -CONST_UINT64_T( TOD_MOVE_TOD_TO_TB_REG_00040017 , ULL(0x00040017) ); -CONST_UINT64_T( TOD_LOAD_TOD_MOD_REG_00040018 , ULL(0x00040018) ); -CONST_UINT64_T( TOD_TRACE_DATA_1_REG_0004001D , ULL(0x0004001D) ); -CONST_UINT64_T( TOD_TRACE_DATA_2_REG_0004001E , ULL(0x0004001E) ); -CONST_UINT64_T( TOD_TRACE_DATA_3_REG_0004001F , ULL(0x0004001F) ); -CONST_UINT64_T( TOD_VALUE_REG_00040020 , ULL(0x00040020) ); -CONST_UINT64_T( TOD_LOAD_TOD_REG_00040021 , ULL(0x00040021) ); -CONST_UINT64_T( TOD_START_TOD_REG_00040022 , ULL(0x00040022) ); -CONST_UINT64_T( TOD_LOW_ORDER_STEP_REG_00040023 , ULL(0x00040023) ); -CONST_UINT64_T( TOD_FSM_REG_00040024 , ULL(0x00040024) ); -CONST_UINT64_T( TOD_TX_TTYPE_CTRL_REG_00040027 , ULL(0x00040027) ); -CONST_UINT64_T( TOD_RX_TTYPE_CTRL_REG_00040029 , ULL(0x00040029) ); -CONST_UINT64_T( TOD_ERROR_REG_00040030 , ULL(0x00040030) ); -CONST_UINT64_T( TOD_ERROR_INJECT_REG_00040031 , ULL(0x00040031) ); -CONST_UINT64_T( TOD_ERROR_MASK_STATUS_REG_00040032 , ULL(0x00040032) ); -CONST_UINT64_T( TOD_ERROR_ROUTING_REG_00040033 , ULL(0x00040033) ); - - -//------------------------------------------------------------------------------ -// SBE VITAL REG -//------------------------------------------------------------------------------ -CONST_UINT64_T( PORE_SBE_VITAL_0x0005001C , ULL(0x0005001C) ); - - - -//------------------------------------------------------------------------------ -// PORE-GPE0 -//------------------------------------------------------------------------------ -CONST_UINT64_T( PORE_GPE0_0x00060000 , ULL(0x00060000) ); -CONST_UINT64_T( PORE_GPE0_STATUS_0x00060000 , ULL(0x00060000) ); -CONST_UINT64_T( PORE_GPE0_CONTROL_0x00060001 , ULL(0x00060001) ); -CONST_UINT64_T( PORE_GPE0_RESET_0x00060002 , ULL(0x00060002) ); -CONST_UINT64_T( PORE_GPE0_ERROR_MASK_0x00060003 , ULL(0x00060003) ); -CONST_UINT64_T( PORE_GPE0_PRV_BASE_ADDRESS0_0x00060004 , ULL(0x00060004) ); -CONST_UINT64_T( PORE_GPE0_PRV_BASE_ADDRESS1_0x00060005 , ULL(0x00060005) ); -CONST_UINT64_T( PORE_GPE0_OCI_BASE_ADDRESS0_0x00060006 , ULL(0x00060006) ); -CONST_UINT64_T( PORE_GPE0_OCI_BASE_ADDRESS1_0x00060007 , ULL(0x00060007) ); -CONST_UINT64_T( PORE_GPE0_TABLE_BASE_ADDR_0x00060008 , ULL(0x00060008) ); -CONST_UINT64_T( PORE_GPE0_EXE_TRIGGER_0x00060009 , ULL(0x00060009) ); -CONST_UINT64_T( PORE_GPE0_SCRATCH0_0x0006000A , ULL(0x0006000A) ); -CONST_UINT64_T( PORE_GPE0_SCRATCH1_0x0006000B , ULL(0x0006000B) ); -CONST_UINT64_T( PORE_GPE0_SCRATCH2_0x0006000C , ULL(0x0006000C) ); -CONST_UINT64_T( PORE_GPE0_IBUF_01_0x0006000D , ULL(0x0006000D) ); -CONST_UINT64_T( PORE_GPE0_IBUF_2_0x0006000E , ULL(0x0006000E) ); -CONST_UINT64_T( PORE_GPE0_DBG0_0x0006000F , ULL(0x0006000F) ); -CONST_UINT64_T( PORE_GPE0_DBG1_0x00060010 , ULL(0x00060010) ); -CONST_UINT64_T( PORE_GPE0_PC_STACK0_0x00060011 , ULL(0x00060011) ); -CONST_UINT64_T( PORE_GPE0_PC_STACK1_0x00060012 , ULL(0x00060012) ); -CONST_UINT64_T( PORE_GPE0_PC_STACK2_0x00060013 , ULL(0x00060013) ); -CONST_UINT64_T( PORE_GPE0_ID_FLAGS_0x00060014 , ULL(0x00060014) ); -CONST_UINT64_T( PORE_GPE0_DATA0_0x00060015 , ULL(0x00060015) ); -CONST_UINT64_T( PORE_GPE0_MEMORY_RELOC_0x00060016 , ULL(0x00060016) ); -CONST_UINT64_T( PORE_GPE0_I2C_E0_PARAM_0x00060017 , ULL(0x00060017) ); -CONST_UINT64_T( PORE_GPE0_I2C_E1_PARAM_0x00060018 , ULL(0x00060018) ); -CONST_UINT64_T( PORE_GPE0_I2C_E2_PARAM_0x00060019 , ULL(0x00060019) ); - -//------------------------------------------------------------------------------ -// PORE-GPE1 -//------------------------------------------------------------------------------ -CONST_UINT64_T( PORE_GPE1_0x00060020 , ULL(0x00060020) ); -CONST_UINT64_T( PORE_GPE1_STATUS_0x00060020 , ULL(0x00060020) ); -CONST_UINT64_T( PORE_GPE1_CONTROL_0x00060021 , ULL(0x00060021) ); -CONST_UINT64_T( PORE_GPE1_RESET_0x00060022 , ULL(0x00060022) ); -CONST_UINT64_T( PORE_GPE1_ERROR_MASK_0x00060023 , ULL(0x00060023) ); -CONST_UINT64_T( PORE_GPE1_PRV_BASE_ADDRESS0_0x00060024 , ULL(0x00060024) ); -CONST_UINT64_T( PORE_GPE1_PRV_BASE_ADDRESS1_0x00060025 , ULL(0x00060025) ); -CONST_UINT64_T( PORE_GPE1_OCI_BASE_ADDRESS0_0x00060026 , ULL(0x00060026) ); -CONST_UINT64_T( PORE_GPE1_OCI_BASE_ADDRESS1_0x00060027 , ULL(0x00060027) ); -CONST_UINT64_T( PORE_GPE1_TABLE_BASE_ADDR_0x00060028 , ULL(0x00060028) ); -CONST_UINT64_T( PORE_GPE1_EXE_TRIGGER_0x00060029 , ULL(0x00060029) ); -CONST_UINT64_T( PORE_GPE1_SCRATCH0_0x0006002A , ULL(0x0006002A) ); -CONST_UINT64_T( PORE_GPE1_SCRATCH1_0x0006002B , ULL(0x0006002B) ); -CONST_UINT64_T( PORE_GPE1_SCRATCH2_0x0006002C , ULL(0x0006002C) ); -CONST_UINT64_T( PORE_GPE1_IBUF_01_0x0006002D , ULL(0x0006002D) ); -CONST_UINT64_T( PORE_GPE1_IBUF_2_0x0006002E , ULL(0x0006002E) ); -CONST_UINT64_T( PORE_GPE1_DBG0_0x0006002F , ULL(0x0006002F) ); -CONST_UINT64_T( PORE_GPE1_DBG1_0x00060030 , ULL(0x00060030) ); -CONST_UINT64_T( PORE_GPE1_PC_STACK0_0x00060031 , ULL(0x00060031) ); -CONST_UINT64_T( PORE_GPE1_PC_STACK1_0x00060032 , ULL(0x00060032) ); -CONST_UINT64_T( PORE_GPE1_PC_STACK2_0x00060033 , ULL(0x00060033) ); -CONST_UINT64_T( PORE_GPE1_ID_FLAGS_0x00060034 , ULL(0x00060034) ); -CONST_UINT64_T( PORE_GPE1_DATA0_0x00060035 , ULL(0x00060035) ); -CONST_UINT64_T( PORE_GPE1_MEMORY_RELOC_0x00060036 , ULL(0x00060036) ); -CONST_UINT64_T( PORE_GPE1_I2C_E0_PARAM_0x00060037 , ULL(0x00060037) ); -CONST_UINT64_T( PORE_GPE1_I2C_E1_PARAM_0x00060038 , ULL(0x00060038) ); -CONST_UINT64_T( PORE_GPE1_I2C_E2_PARAM_0x00060039 , ULL(0x00060039) ); - -//------------------------------------------------------------------------------ -// PORE-SLW -//------------------------------------------------------------------------------ -CONST_UINT64_T( PORE_SLW_0x00068000 , ULL(0x00068000) ); -CONST_UINT64_T( PORE_SLW_STATUS_0x00068000 , ULL(0x00068000) ); -CONST_UINT64_T( PORE_SLW_CONTROL_0x00068001 , ULL(0x00068001) ); -CONST_UINT64_T( PORE_SLW_RESET_0x00068002 , ULL(0x00068002) ); -CONST_UINT64_T( PORE_SLW_ERROR_MASK_0x00068003 , ULL(0x00068003) ); -CONST_UINT64_T( PORE_SLW_PRV_BASE_ADDRESS0_0x00068004 , ULL(0x00068004) ); -CONST_UINT64_T( PORE_SLW_PRV_BASE_ADDRESS1_0x00068005 , ULL(0x00068005) ); -CONST_UINT64_T( PORE_SLW_OCI_BASE_ADDRESS0_0x00068006 , ULL(0x00068006) ); -CONST_UINT64_T( PORE_SLW_OCI_BASE_ADDRESS1_0x00068007 , ULL(0x00068007) ); -CONST_UINT64_T( PORE_SLW_TABLE_BASE_ADDR_0x00068008 , ULL(0x00068008) ); -CONST_UINT64_T( PORE_SLW_EXE_TRIGGER_0x00068009 , ULL(0x00068009) ); -CONST_UINT64_T( PORE_SLW_SCRATCH0_0x0006800A , ULL(0x0006800A) ); -CONST_UINT64_T( PORE_SLW_SCRATCH1_0x0006800B , ULL(0x0006800B) ); -CONST_UINT64_T( PORE_SLW_SCRATCH2_0x0006800C , ULL(0x0006800C) ); -CONST_UINT64_T( PORE_SLW_IBUF_01_0x0006800D , ULL(0x0006800D) ); -CONST_UINT64_T( PORE_SLW_IBUF_2_0x0006800E , ULL(0x0006800E) ); -CONST_UINT64_T( PORE_SLW_DBG0_0x0006800F , ULL(0x0006800F) ); -CONST_UINT64_T( PORE_SLW_DBG1_0x00068010 , ULL(0x00068010) ); -CONST_UINT64_T( PORE_SLW_PC_STACK0_0x00068011 , ULL(0x00068011) ); -CONST_UINT64_T( PORE_SLW_PC_STACK1_0x00068012 , ULL(0x00068012) ); -CONST_UINT64_T( PORE_SLW_PC_STACK2_0x00068013 , ULL(0x00068013) ); -CONST_UINT64_T( PORE_SLW_ID_FLAGS_0x00068014 , ULL(0x00068014) ); -CONST_UINT64_T( PORE_SLW_DATA0_0x00068015 , ULL(0x00068015) ); -CONST_UINT64_T( PORE_SLW_MEMORY_RELOC_0x00068016 , ULL(0x00068016) ); -CONST_UINT64_T( PORE_SLW_I2C_E0_PARAM_0x00068017 , ULL(0x00068017) ); -CONST_UINT64_T( PORE_SLW_I2C_E1_PARAM_0x00068018 , ULL(0x00068018) ); -CONST_UINT64_T( PORE_SLW_I2C_E2_PARAM_0x00068019 , ULL(0x00068019) ); - -//------------------------------------------------------------------------------ -// OCC/OCB -//------------------------------------------------------------------------------ - -CONST_UINT64_T( OCC_CONTROL_0x0006B000 , ULL(0x0006B000) ); -CONST_UINT64_T( OCC_CONTROL_AND_0x0006B001 , ULL(0x0006B001) ); -CONST_UINT64_T( OCC_CONTROL_OR_0x0006B002 , ULL(0x0006B002) ); -CONST_UINT64_T( OCC_DEBUG_MODE_0x0006B003 , ULL(0x0006B003) ); -CONST_UINT64_T( OCC_JTG_PIB_OJCFG_0x0006B004 , ULL(0x0006B004) ); -CONST_UINT64_T( OCC_JTG_PIB_OJCFG_AND_0x0006B005 , ULL(0x0006B005) ); -CONST_UINT64_T( OCC_JTG_PIB_OJCFG_OR_0x0006B006 , ULL(0x0006B006) ); - -CONST_UINT64_T( OCB0_ADDRESS_0x0006B010 , ULL(0x0006B010) ); -CONST_UINT64_T( OCB0_STATUS_CONTROL_0x0006B011 , ULL(0x0006B011) ); -CONST_UINT64_T( OCB0_STATUS_CONTROL_AND_0x0006B012 , ULL(0x0006B012) ); -CONST_UINT64_T( OCB0_STATUS_CONTROL_OR_0x0006B013 , ULL(0x0006B013) ); -CONST_UINT64_T( OCB0_ERROR_STATUS_0x0006B014 , ULL(0x0006B014) ); -CONST_UINT64_T( OCB0_DATA_0x0006B015 , ULL(0x0006B015) ); -CONST_UINT64_T( OCB0_PULL_BASE_0x0006A200 , ULL(0x0006A200) ); -CONST_UINT64_T( OCB0_PULL_STATUS_CONTROL_0x0006A201 , ULL(0x0006A201) ); -CONST_UINT64_T( OCB0_PUSH_BASE_0x0006A203 , ULL(0x0006A203) ); -CONST_UINT64_T( OCB0_PUSH_STATUS_CONTROL_0x0006A204 , ULL(0x0006A204) ); -CONST_UINT64_T( OCB0_STREAM_ERR_STATUS_0x0006A206 , ULL(0x0006A206) ); -CONST_UINT64_T( OCB0_UNTRUSTED_CONTROL_0x0006A207 , ULL(0x0006A207) ); -CONST_UINT64_T( OCB0_LIN_WINDOW_CONTROL_0x0006A208 , ULL(0x0006A208) ); -CONST_UINT64_T( OCB0_LIN_WINDOW_BASE_0x0006A20C , ULL(0x0006A20C) ); - -CONST_UINT64_T( OCB1_ADDRESS_0x0006B030 , ULL(0x0006B030) ); -CONST_UINT64_T( OCB1_STATUS_CONTROL_0x0006B031 , ULL(0x0006B031) ); -CONST_UINT64_T( OCB1_STATUS_CONTROL_AND_0x0006B032 , ULL(0x0006B032) ); -CONST_UINT64_T( OCB1_STATUS_CONTROL_OR_0x0006B033 , ULL(0x0006B033) ); -CONST_UINT64_T( OCB1_ERROR_STATUS_0x0006B034 , ULL(0x0006B034) ); -CONST_UINT64_T( OCB1_DATA_0x0006B035 , ULL(0x0006B035) ); -CONST_UINT64_T( OCB1_PULL_BASE_0x0006A210 , ULL(0x0006A210) ); -CONST_UINT64_T( OCB1_PULL_STATUS_CONTROL_0x0006A211 , ULL(0x0006A211) ); -CONST_UINT64_T( OCB1_PUSH_BASE_0x0006A213 , ULL(0x0006A213) ); -CONST_UINT64_T( OCB1_PUSH_STATUS_CONTROL_0x0006A214 , ULL(0x0006A214) ); -CONST_UINT64_T( OCB1_STREAM_ERR_STATUS_0x0006A216 , ULL(0x0006A216) ); -CONST_UINT64_T( OCB1_UNTRUSTED_CONTROL_0x0006A217 , ULL(0x0006A217) ); -CONST_UINT64_T( OCB1_LIN_WINDOW_CONTROL_0x0006A218 , ULL(0x0006A218) ); -CONST_UINT64_T( OCB1_LIN_WINDOW_BASE_0x0006A21C , ULL(0x0006A21C) ); - -CONST_UINT64_T( OCB2_ADDRESS_0x0006B050 , ULL(0x0006B050) ); -CONST_UINT64_T( OCB2_STATUS_CONTROL_0x0006B051 , ULL(0x0006B051) ); -CONST_UINT64_T( OCB2_STATUS_CONTROL_AND_0x0006B052 , ULL(0x0006B052) ); -CONST_UINT64_T( OCB2_STATUS_CONTROL_OR_0x0006B053 , ULL(0x0006B053) ); -CONST_UINT64_T( OCB2_ERROR_STATUS_0x0006B054 , ULL(0x0006B054) ); -CONST_UINT64_T( OCB2_DATA_0x0006B055 , ULL(0x0006B055) ); -CONST_UINT64_T( OCB2_PULL_BASE_0x0006A220 , ULL(0x0006A220) ); -CONST_UINT64_T( OCB2_PULL_STATUS_CONTROL_0x0006A221 , ULL(0x0006A221) ); -CONST_UINT64_T( OCB2_PUSH_BASE_0x0006A223 , ULL(0x0006A223) ); -CONST_UINT64_T( OCB2_PUSH_STATUS_CONTROL_0x0006A224 , ULL(0x0006A224) ); -CONST_UINT64_T( OCB2_STREAM_ERR_STATUS_0x0006A226 , ULL(0x0006A226) ); -CONST_UINT64_T( OCB2_UNTRUSTED_CONTROL_0x0006A227 , ULL(0x0006A227) ); -CONST_UINT64_T( OCB2_LIN_WINDOW_CONTROL_0x0006A228 , ULL(0x0006A228) ); -CONST_UINT64_T( OCB2_LIN_WINDOW_BASE_0x0006A22C , ULL(0x0006A22C) ); - -CONST_UINT64_T( OCB3_ADDRESS_0x0006B070 , ULL(0x0006B070) ); -CONST_UINT64_T( OCB3_STATUS_CONTROL_0x0006B071 , ULL(0x0006B071) ); -CONST_UINT64_T( OCB3_STATUS_CONTROL_AND_0x0006B072 , ULL(0x0006B072) ); -CONST_UINT64_T( OCB3_STATUS_CONTROL_OR_0x0006B073 , ULL(0x0006B073) ); -CONST_UINT64_T( OCB3_ERROR_STATUS_0x0006B074 , ULL(0x0006B074) ); -CONST_UINT64_T( OCB3_DATA_0x0006B075 , ULL(0x0006B075) ); - -CONST_UINT64_T( OCC_LFIR_0x01010800 , ULL(0x01010800) ); -CONST_UINT64_T( OCC_LFIR_AND_0x01010801 , ULL(0x01010801) ); -CONST_UINT64_T( OCC_LFIR_OR_0x01010802 , ULL(0x01010802) ); -CONST_UINT64_T( OCC_LFIR_MASK_0x01010803 , ULL(0x01010803) ); -CONST_UINT64_T( OCC_LFIR_MASK_AND_0x01010804 , ULL(0x01010804) ); -CONST_UINT64_T( OCC_LFIR_MASK_OR_0x01010805 , ULL(0x01010805) ); -CONST_UINT64_T( OCC_LFIR_ACT0_0x01010806 , ULL(0x01010806) ); -CONST_UINT64_T( OCC_LFIR_ACT1_0x01010807 , ULL(0x01010807) ); - -CONST_UINT64_T( OCC_PMC_LFIR_0x01010C00 , ULL(0x01010C00) ); -CONST_UINT64_T( OCC_PMC_LFIR_AND_0x01010C01 , ULL(0x01010C01) ); -CONST_UINT64_T( OCC_PMC_LFIR_MASK_0x01010C03 , ULL(0x01010C03) ); - -// sram registers -CONST_UINT64_T( OCC_SRAM_BOOT_VEC0_0x00066004 , ULL(0x00066004) ); -CONST_UINT64_T( OCC_SRAM_BOOT_VEC1_0x00066005 , ULL(0x00066005) ); -CONST_UINT64_T( OCC_SRAM_BOOT_VEC2_0x00066006 , ULL(0x00066006) ); -CONST_UINT64_T( OCC_SRAM_BOOT_VEC3_0x00066007 , ULL(0x00066007) ); - -// interrupt controller registers -CONST_UINT64_T( OCC_ITP_SOURCE0_MASK_AND_0x0006A001 , ULL(0x0006A001) ); -CONST_UINT64_T( OCC_ITP_SOURCE1_MASK_AND_0x0006A011 , ULL(0x0006A011) ); -CONST_UINT64_T( OCC_ITP_MASK0_MASK_OR_0x0006A006 , ULL(0x0006A006) ); -CONST_UINT64_T( OCC_ITP_MASK1_MASK_OR_0x0006A016 , ULL(0x0006A016) ); -CONST_UINT64_T( OCC_ITP_TYPE0_0x0006A008 , ULL(0x0006A008) ); -CONST_UINT64_T( OCC_ITP_TYPE1_0x0006A018 , ULL(0x0006A018) ); -CONST_UINT64_T( OCC_ITP_EDGE_POLARITY0_0x0006A009 , ULL(0x0006A009) ); -CONST_UINT64_T( OCC_ITP_EDGE_POLARITY1_0x0006A019 , ULL(0x0006A019) ); -CONST_UINT64_T( OCC_ITP_CRITICAL_EN0_0x0006A00A , ULL(0x0006A00A) ); -CONST_UINT64_T( OCC_ITP_CRITICAL_EN1_0x0006A01A , ULL(0x0006A01A) ); -CONST_UINT64_T( OCC_ITP_DEBUG_HALT_EN0_0x0006A00E , ULL(0x0006A00E) ); -CONST_UINT64_T( OCC_ITP_DEBUG_HALT_EN1_0x0006A01E , ULL(0x0006A01E) ); -CONST_UINT64_T( OCC_ITP_UNCOND_DEBUG_EN0_0x0006A00C , ULL(0x0006A00C) ); -CONST_UINT64_T( OCC_ITP_UNCOND_DEBUG_EN1_0x0006A01C , ULL(0x0006A01C) ); -CONST_UINT64_T( OCC_ITP_MISC_0x0006A020 , ULL(0x0006A020) ); -CONST_UINT64_T( OCC_ITP_MISC_AND_0x0006A021 , ULL(0x0006A021) ); -CONST_UINT64_T( OCC_ITP_MISC_OR_0x0006A022 , ULL(0x0006A022) ); -CONST_UINT64_T( OCC_ITP_TIMER0_0x0006A100 , ULL(0x0006A100) ); -CONST_UINT64_T( OCC_ITP_TIMER1_0x0006A101 , ULL(0x0006A101) ); - -//------------------------------------------------------------------------------ -// PMC -//------------------------------------------------------------------------------ - -// PIB Space Addresses - -CONST_UINT64_T( PMC_MODE_REG_0x00062000 , ULL(0x00062000) ); -CONST_UINT64_T( PMC_PSTATE_MONITOR_AND_CTRL_REG_0x00062002, ULL(0x00062002)) ; -CONST_UINT64_T( PMC_RAIL_BOUNDS_0x00062003 , ULL(0x00062003) ); -CONST_UINT64_T( PMC_GLOBAL_PSTATE_BOUNDS_0x00062004 , ULL(0x00062004) ); -CONST_UINT64_T( PMC_PARAMETER_REG1_0x00062006 , ULL(0x00062006) ); -CONST_UINT64_T( PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG_0x00062007, ULL(0x00062007) ); -CONST_UINT64_T( PMC_STATUS_REG_0x00062009 , ULL(0x00062009) ); -CONST_UINT64_T( PMC_OCC_HEARTBEAT_REG_0x00062066 , ULL(0x00062066) ); -CONST_UINT64_T( PMC_CORE_DECONFIG_REG_0x0006200D , ULL(0x0006200D) ); -CONST_UINT64_T( PMC_FSMSTATE_STATUS_REG_0x00062020 , ULL(0x00062020) ); -CONST_UINT64_T( PMC_PIRR0_REG_0x00062080 , ULL(0x00062080) ); -CONST_UINT64_T( PMC_PIRR0_REG_0x00062081 , ULL(0x00062081) ); -CONST_UINT64_T( PMC_PIRR0_REG_0x00062082 , ULL(0x00062082) ); -CONST_UINT64_T( PMC_PIRR0_REG_0x00062083 , ULL(0x00062083) ); -CONST_UINT64_T( PMC_PORRR0_REG_0x0006208E , ULL(0x0006208E) ); -CONST_UINT64_T( PMC_PORRR1_REG_0x0006208F , ULL(0x0006208F) ); -CONST_UINT64_T( PMC_PORRS_REG_0x00062090 , ULL(0x00062090) ); -CONST_UINT64_T( PMC_DEEPEXIT_MASK_0x00062092 , ULL(0x00062092) ); -CONST_UINT64_T( PMC_DEEPEXIT_MASK_WAND_0x000620A0 , ULL(0x000620A0) ); -CONST_UINT64_T( PMC_DEEPEXIT_MASK_WOR_0x000620A1 , ULL(0x000620A1) ); -CONST_UINT64_T( PMC_INTCHP_PSTATE_REG_0x00062017 , ULL(0x00062017) ); -CONST_UINT64_T( PMC_INTCHP_COMMAND_REG_0x00062014 , ULL(0x00062014) ); -CONST_UINT64_T( PMC_INTCHP_STATUS_REG_0x00062013 , ULL(0x00062013) ); -CONST_UINT64_T( PMC_INTCHP_CTRL_REG1_0x00062010 , ULL(0x00062010) ); -CONST_UINT64_T( PMC_INTCHP_CTRL_REG4_0x00062012 , ULL(0x00062012) ); -CONST_UINT64_T( PMC_PORE_REQ_REG0_0x0006208E , ULL(0x0006208E) ); -CONST_UINT64_T( PMC_PARAMETER_REG0_0x00062005 , ULL(0x00062005) ); -CONST_UINT64_T( PMC_O2P_CTRL_STATUS_REG_0x00062061 , ULL (0x00062061)); - -CONST_UINT64_T( OCB_OCI_OIMR1_0x0006a014 , ULL(0x0006a014) ); -CONST_UINT64_T( OCB_OCI_OIMR0_0x0006a004 , ULL(0x0006a004) ); - -// SPIVID Controller -CONST_UINT64_T( PMC_SPIV_CTRL_REG0A_0x00062040 , ULL(0x00062040) ); -CONST_UINT64_T( PMC_SPIV_CTRL_REG0B_0x00062041 , ULL(0x00062041) ); -CONST_UINT64_T( PMC_SPIV_CTRL_REG1_0x00062042 , ULL(0x00062042) ); -CONST_UINT64_T( PMC_SPIV_CTRL_REG2_0x00062043 , ULL(0x00062043) ); -CONST_UINT64_T( PMC_SPIV_CTRL_REG3_0x00062044 , ULL(0x00062044) ); -CONST_UINT64_T( PMC_SPIV_CTRL_REG4_0x00062045 , ULL(0x00062045) ); -CONST_UINT64_T( PMC_SPIV_STATUS_REG_0x00062046 , ULL(0x00062046) ); -CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00062047 , ULL(0x00062047) ); -// OCI to SPI (O2S) -CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); -CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 , ULL(0x00062051) ); -CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 , ULL(0x00062052) ); -CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 , ULL(0x00062053) ); -CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 , ULL(0x00062055) ); -CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 , ULL(0x00062056) ); -CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 , ULL(0x00062057) ); -CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 , ULL(0x00062058) ); -CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 , ULL(0x00062059) ); -// PORE interface -CONST_UINT64_T( PMC_PORE_REQ_STAT_REG_0x00062090 , ULL(0x00062090) ); -// PMC LFIR -CONST_UINT64_T( PMC_LFIR_0x01010840 , ULL(0x01010840) ); -CONST_UINT64_T( PMC_LFIR_AND_0x01010841 , ULL(0x01010841) ); -CONST_UINT64_T( PMC_LFIR_OR_0x01010842 , ULL(0x01010842) ); -CONST_UINT64_T( PMC_LFIR_MASK_0x01010843 , ULL(0x01010843) ); -CONST_UINT64_T( PMC_LFIR_MASK_AND_0x01010844 , ULL(0x01010844) ); -CONST_UINT64_T( PMC_LFIR_MASK_OR_0x01010845 , ULL(0x01010845) ); -CONST_UINT64_T( PMC_LFIR_ACT0_0x01010846 , ULL(0x01010846) ); -CONST_UINT64_T( PMC_LFIR_ACT1_0x01010847 , ULL(0x01010847) ); -CONST_UINT64_T( PMC_ERROR_INT_MASK_HI_0x00062067 , ULL(0x00062067) ); -CONST_UINT64_T( PMC_ERROR_INT_MASK_LO_0x00062068 , ULL(0x00062068) ); - -// OCI Space Addresses - -CONST_UINT32_T( OCI_PMC_PORE_REQ_STAT_REG_0x40010480 , ULL(0x40010480) ); -CONST_UINT32_T( OCI_PMC_PORE_SCRATCH0_REG_0x400104E8 , ULL(0x400104E8) ); -CONST_UINT32_T( OCI_PMC_PORE_SCRATCH1_REG_0x400104F0 , ULL(0x400104F0) ); -CONST_UINT32_T( OCI_OCB_OTR0_REG_0x40050800 , ULL(0x40050800) ); - -//------------------------------------------------------------------------------ -// SPIADC -//------------------------------------------------------------------------------ -CONST_UINT64_T( SPIPSS_ADC_CTRL_REG0_0x00070000 , ULL(0x00070000) ); -CONST_UINT64_T( SPIPSS_ADC_CTRL_REG1_0x00070001 , ULL(0x00070001) ); -CONST_UINT64_T( SPIPSS_ADC_CTRL_REG2_0x00070002 , ULL(0x00070002) ); -CONST_UINT64_T( SPIPSS_ADC_STATUS_REG_0x00070003 , ULL(0x00070003) ); -CONST_UINT64_T( SPIPSS_ADC_CMD_REG_0x00070004 , ULL(0x00070004) ); -CONST_UINT64_T( SPIPSS_ADC_WDATA_REG_0x00070010 , ULL(0x00070010) ); -CONST_UINT64_T( SPIPSS_ADC_RDATA_REG0_0x00070020 , ULL(0x00070020) ); -CONST_UINT64_T( SPIPSS_ADC_RDATA_REG1_0x00070021 , ULL(0x00070021) ); -CONST_UINT64_T( SPIPSS_ADC_RDATA_REG2_0x00070022 , ULL(0x00070022) ); -CONST_UINT64_T( SPIPSS_ADC_RDATA_REG3_0x00070023 , ULL(0x00070023) ); -CONST_UINT64_T( SPIPSS_100NS_REG_0x00070028 , ULL(0x00070028) ); -CONST_UINT64_T( SPIPSS_P2S_CTRL_REG0_0x00070040 , ULL(0x00070040) ); -CONST_UINT64_T( SPIPSS_P2S_CTRL_REG1_0x00070041 , ULL(0x00070041) ); -CONST_UINT64_T( SPIPSS_P2S_CTRL_REG2_0x00070042 , ULL(0x00070042) ); -CONST_UINT64_T( SPIPSS_P2S_STATUS_REG_0x00070043 , ULL(0x00070043) ); -CONST_UINT64_T( SPIPSS_P2S_COMMAND_REG_0x00070044 , ULL(0x00070044) ); -CONST_UINT64_T( SPIPSS_P2S_WDATA_REG_0x00070050 , ULL(0x00070050) ); -CONST_UINT64_T( SPIPSS_P2S_RDATA_REG_0x00070060 , ULL(0x00070060) ); -CONST_UINT64_T( SPIPSS_ADC_RESET_REGISTER_0x00070005 , ULL(0x00070005) ); -CONST_UINT64_T( SPIPSS_P2S_RESET_REGISTER_0x00070045 , ULL(0x00070045) ); - -//------------------------------------------------------------------------------ -// PIB-ATTACHED MEMORY -//------------------------------------------------------------------------------ -CONST_UINT64_T( PIBMEM0_0x00080000 , ULL(0x00080000) ); -CONST_UINT64_T( PIBMEM_CONTROL_0x00088000 , ULL(0x00088000) ); -CONST_UINT64_T( PIBMEM_ADDRESS_0x00088001 , ULL(0x00088001) ); -CONST_UINT64_T( PIBMEM_DATA_0x00088002 , ULL(0x00088002) ); -CONST_UINT64_T( PIBMEM_DATA_INC_0x00088003 , ULL(0x00088003) ); -CONST_UINT64_T( PIBMEM_DATA_DEC_0x00088004 , ULL(0x00088004) ); -CONST_UINT64_T( PIBMEM_STATUS_0x00088005 , ULL(0x00088005) ); -CONST_UINT64_T( PIBMEM_RESET_0x00088006 , ULL(0x00088006) ); -CONST_UINT64_T( PIBMEM_REPAIR_0x00088007 , ULL(0x00088007) ); - -//------------------------------------------------------------------------------ -// I2C MASTER (MODE) -//------------------------------------------------------------------------------ -CONST_UINT64_T( I2CM_MODE_REGISTER_0_0x000A0006 , ULL(0x000A0006) ); -CONST_UINT64_T( I2CM_WATER_MARK_0_0x000A0007 , ULL(0x000A0007) ); -CONST_UINT64_T( I2CM_INTERRUPT_MASK_0_0x000A0008 , ULL(0x000A0008) ); -CONST_UINT64_T( I2CM_INTERRUPT_COND_0_0x000A0009 , ULL(0x000A0009) ); -CONST_UINT64_T( I2CM_INTERRUPTS_0_0x000A000A , ULL(0x000A000A) ); -CONST_UINT64_T( I2CM_STATUS_REGISTER_ENGINE_0_0x000A000B , ULL(0x000A000B) ); -CONST_UINT64_T( I2CM_EXTENDED_STATUS_0_0x000A000C , ULL(0x000A000C) ); -CONST_UINT64_T( I2CM_RESIDUAL_FE_BE_LENGTH_0_0x000A000D , ULL(0x000A000D) ); -CONST_UINT64_T( I2CM_BUSY_REGISTER_0_0x000A000E , ULL(0x000A000E) ); - -//------------------------------------------------------------------------------ -// I2C MASTER (MEMS1) -//------------------------------------------------------------------------------ -CONST_UINT64_T( I2CMS_MEMS1_CONTROL_0x000A0020 , ULL(0x000A0020) ); -CONST_UINT64_T( I2CMS_MEMS1_RESET_0x000A0021 , ULL(0x000A0021) ); -CONST_UINT64_T( I2CMS_MEMS1_STATUS_0x000A0022 , ULL(0x000A0022) ); -CONST_UINT64_T( I2CMS_MEMS1_DATA_0x000A0023 , ULL(0x000A0023) ); -CONST_UINT64_T( I2CMS_MEMS1_COMMAND_0x000A0025 , ULL(0x000A0025) ); - -//------------------------------------------------------------------------------ -// I2C MASTER (PCI) -//------------------------------------------------------------------------------ -CONST_UINT64_T( I2CMS_PCI_0x000A0040 , ULL(0x000A0040) ); -CONST_UINT64_T( I2CMS_PCI_CONTROL_0x000A0040 , ULL(0x000A0040) ); -CONST_UINT64_T( I2CMS_PCI_RESET_0x000A0041 , ULL(0x000A0041) ); -CONST_UINT64_T( I2CMS_PCI_STATUS_0x000A0042 , ULL(0x000A0042) ); -CONST_UINT64_T( I2CMS_PCI_DATA_0x000A0043 , ULL(0x000A0043) ); -CONST_UINT64_T( I2CMS_PCI_COMMAND_0x000A0045 , ULL(0x000A0045) ); - -//------------------------------------------------------------------------------ -// LPC -//------------------------------------------------------------------------------ -CONST_UINT64_T( LPC_CONTROL_0x000B0000 , ULL(0x000B0000) ); -CONST_UINT64_T( LPC_RESET_0x000B0001 , ULL(0x000B0001) ); -CONST_UINT64_T( LPC_STATUS_0x000B0002 , ULL(0x000B0002) ); -CONST_UINT64_T( LPC_DATA_0x000B0003 , ULL(0x000B0003) ); -CONST_UINT64_T( LPC_ECC_ADDRESS_0x000B0004 , ULL(0x000B0004) ); -CONST_UINT64_T( LPC_I2C_ADDRESS_0x000B0005 , ULL(0x000B0005) ); -CONST_UINT64_T( LPC_FW_CONTROL_0x000B0020 , ULL(0x000B0020) ); -CONST_UINT64_T( LPC_FW_RESET_0x000B0021 , ULL(0x000B0021) ); -CONST_UINT64_T( LPC_FW_STATUS_0x000B0022 , ULL(0x000B0022) ); -CONST_UINT64_T( LPC_FW_DATA_0x000B0023 , ULL(0x000B0023) ); - -//------------------------------------------------------------------------------ -// PORE_ECCB -//------------------------------------------------------------------------------ - -CONST_UINT64_T( PORE_ECCB_CONTROL_REGISTER_0x000C0000 , ULL(0x000C0000) ); -CONST_UINT64_T( PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, ULL(0x000C0002) ); -CONST_UINT64_T( PORE_ECCB_DATA_REGISTER_0x000C0003 , ULL(0x000C0003) ); -CONST_UINT64_T( PORE_ECCB_ECC_ADDRESS_REGISTER_0x000C0004 , ULL(0x000C0004) ); - -//------------------------------------------------------------------------------ -// I2CS -//------------------------------------------------------------------------------ -CONST_UINT64_T( I2C_SLAVE_CONFIG_REG_0x000D0000 , ULL(0x000D0000) ); - -//------------------------------------------------------------------------------ -// PORE-SBE -//------------------------------------------------------------------------------ -CONST_UINT64_T( PORE_SBE_0x000E0000 , ULL(0x000E0000) ); -CONST_UINT64_T( PORE_SBE_STATUS_0x000E0000 , ULL(0x000E0000) ); -CONST_UINT64_T( PORE_SBE_CONTROL_0x000E0001 , ULL(0x000E0001) ); -CONST_UINT64_T( PORE_SBE_RESET_0x000E0002 , ULL(0x000E0002) ); -CONST_UINT64_T( PORE_SBE_ERROR_MASK_0x000E0003 , ULL(0x000E0003) ); -CONST_UINT64_T( PORE_SBE_PRV_BASE_ADDRESS0_0x000E0004 , ULL(0x000E0004) ); -CONST_UINT64_T( PORE_SBE_PRV_BASE_ADDRESS1_0x000E0005 , ULL(0x000E0005) ); -CONST_UINT64_T( PORE_SBE_OCI_BASE_ADDRESS0_0x000E0006 , ULL(0x000E0006) ); -CONST_UINT64_T( PORE_SBE_OCI_BASE_ADDRESS1_0x000E0007 , ULL(0x000E0007) ); -CONST_UINT64_T( PORE_SBE_TABLE_BASE_ADDR_0x000E0008 , ULL(0x000E0008) ); -CONST_UINT64_T( PORE_SBE_EXE_TRIGGER_0x000E0009 , ULL(0x000E0009) ); -CONST_UINT64_T( PORE_SBE_SCRATCH0_0x000E000A , ULL(0x000E000A) ); -CONST_UINT64_T( PORE_SBE_SCRATCH1_0x000E000B , ULL(0x000E000B) ); -CONST_UINT64_T( PORE_SBE_SCRATCH2_0x000E000C , ULL(0x000E000C) ); -CONST_UINT64_T( PORE_SBE_IBUF_01_0x000E000D , ULL(0x000E000D) ); -CONST_UINT64_T( PORE_SBE_IBUF_2_0x000E000E , ULL(0x000E000E) ); -CONST_UINT64_T( PORE_SBE_DBG0_0x000E000F , ULL(0x000E000F) ); -CONST_UINT64_T( PORE_SBE_DBG1_0x000E0010 , ULL(0x000E0010) ); -CONST_UINT64_T( PORE_SBE_PC_STACK0_0x000E0011 , ULL(0x000E0011) ); -CONST_UINT64_T( PORE_SBE_PC_STACK1_0x000E0012 , ULL(0x000E0012) ); -CONST_UINT64_T( PORE_SBE_PC_STACK2_0x000E0013 , ULL(0x000E0013) ); -CONST_UINT64_T( PORE_SBE_ID_FLAGS_0x000E0014 , ULL(0x000E0014) ); -CONST_UINT64_T( PORE_SBE_DATA0_0x000E0015 , ULL(0x000E0015) ); -CONST_UINT64_T( PORE_SBE_MEMORY_RELOC_0x000E0016 , ULL(0x000E0016) ); -CONST_UINT64_T( PORE_SBE_I2C_E0_PARAM_0x000E0017 , ULL(0x000E0017) ); -CONST_UINT64_T( PORE_SBE_I2C_E1_PARAM_0x000E0018 , ULL(0x000E0018) ); -CONST_UINT64_T( PORE_SBE_I2C_E2_PARAM_0x000E0019 , ULL(0x000E0019) ); - -//------------------------------------------------------------------------------ -// LPC -//------------------------------------------------------------------------------ -CONST_UINT64_T( LPC_FIR_0x01010C00 , ULL(0x01010C00) ); -CONST_UINT64_T( LPC_FIR_AND_0x01010C01 , ULL(0x01010C01) ); -CONST_UINT64_T( LPC_FIR_OR_0x01010C02 , ULL(0x01010C02) ); -CONST_UINT64_T( LPC_FIR_MASK_0x01010C03 , ULL(0x01010C03) ); -CONST_UINT64_T( LPC_FIR_MASK_AND_0x01010C04 , ULL(0x01010C04) ); -CONST_UINT64_T( LPC_FIR_MASK_OR_0x01010C05 , ULL(0x01010C05) ); -CONST_UINT64_T( LPC_FIR_ACTION0_0x01010C06 , ULL(0x01010C06) ); -CONST_UINT64_T( LPC_FIR_ACTION1_0x01010C07 , ULL(0x01010C07) ); - -//------------------------------------------------------------------------------ -// PCB Master -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCBMS_RESET_REG_0x000F001D , ULL(0x000F001D) ); - -//------------------------------------------------------------------------------ -// TP Chiplet PCB slave -//------------------------------------------------------------------------------ -CONST_UINT64_T( HANG_PULSE_0_REG_0x010F0020 , ULL(0x010F0020) ); -CONST_UINT64_T( HANG_PULSE_1_REG_0x010F0021 , ULL(0x010F0021) ); -CONST_UINT64_T( HANG_PULSE_2_REG_0x010F0022 , ULL(0x010F0022) ); -CONST_UINT64_T( HANG_PULSE_3_REG_0x010F0023 , ULL(0x010F0023) ); -CONST_UINT64_T( HANG_PULSE_4_REG_0x010F0024 , ULL(0x010F0024) ); -CONST_UINT64_T( HANG_PULSE_5_REG_0x010F0025 , ULL(0x010F0025) ); -CONST_UINT64_T( HANG_PULSE_6_REG_0x010F0026 , ULL(0x010F0026) ); -CONST_UINT64_T( PRE_COUNTER_REG_0x010F0028 , ULL(0x010F0028) ); - -//------------------------------------------------------------------------------ -// TP SCOM -// ring 1 = Trace -// ring 2 = OCC -// ring 3 = PIB -// ring 15 = OCCSEC -//------------------------------------------------------------------------------ - - -/******************************************************************************/ -/******************************* NEST CHIPLET *******************************/ -/******************************************************************************/ - -//------------------------------------------------------------------------------ -// NEST SCOM -// ring 1 = Trace -// ring 2 = TCBR -// ring 3 = PB -// ring 6 = MCL -// MC0 MCS0 = 0x02011800 -// MC0 MCS1 = 0x02011880 -// MC1 MCS0 = 0x02011900 -// MC1 MCS0 = 0x02011980 -// IOMC0 = 0x02011A00 -// ring 7 = MCR -// MC2 MCS0 = 0x02011C00 -// MC2 MCS1 = 0x02011C80 -// MC3 MCS0 = 0x02011D00 -// MC3 MCS1 = 0x02011D80 -// IOMC1 = 0x02011E00 -// ring 8 = PCIS0 -// ring 9 = PCIS1 -// ring 10 = PCIS2 -// ring 11 = PCIS3 -// ring 12 = NX -// ring 13 = MCD -// ring 15 = TCBRSEC -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// NEST TRACE -//------------------------------------------------------------------------------ -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T1_0x02010440 , ULL(0x02010440) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T1_0x02010441 , ULL(0x02010441) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T2_0x02010480 , ULL(0x02010480) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T2_0x02010481 , ULL(0x02010481) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T3_0x020104C0 , ULL(0x020104C0) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T3_0x020104C1 , ULL(0x020104C1) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T4_0x02010500 , ULL(0x02010500) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T4_0x02010501 , ULL(0x02010501) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T5_0x02010540 , ULL(0x02010540) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T5_0x02010541 , ULL(0x02010541) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T6_0x02010580 , ULL(0x02010580) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T6_0x02010581 , ULL(0x02010581) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T7_0x020105C0 , ULL(0x020105C0) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T7_0x020105C1 , ULL(0x020105C1) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T8_0x02010600 , ULL(0x02010600) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T8_0x02010601 , ULL(0x02010601) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_PB_T9_0x02010640 , ULL(0x02010640) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_PB_T9_0x02010641 , ULL(0x02010641) ); -CONST_UINT64_T( NEST_TRACE_DATA_HI_NX_0x02010A00 , ULL(0x02010A00) ); -CONST_UINT64_T( NEST_TRACE_DATA_LO_NX_0x02010A01 , ULL(0x02010A01) ); - -//------------------------------------------------------------------------------ -// POWERBUS ACCESS BRIDGE (PBA) -//------------------------------------------------------------------------------ -CONST_UINT64_T( PBA_CC_SYNC_CONF_0x02030000 , ULL(0x02030000) ); - -CONST_UINT64_T( PBA_FIR_0x02010840 , ULL(0x02010840) ); -CONST_UINT64_T( PBA_FIR_AND_0x02010841 , ULL(0x02010841) ); -CONST_UINT64_T( PBA_FIR_OR_0x02010842 , ULL(0x02010842) ); -CONST_UINT64_T( PBA_FIR_MASK_0x02010843 , ULL(0x02010843) ); -CONST_UINT64_T( PBA_FIR_MASK_AND_0x02010844 , ULL(0x02010844) ); -CONST_UINT64_T( PBA_FIR_MASK_OR_0x02010845 , ULL(0x02010845) ); -CONST_UINT64_T( PBA_FIR_ACTION0_0x02010846 , ULL(0x02010846) ); -CONST_UINT64_T( PBA_FIR_ACTION1_0x02010847 , ULL(0x02010847) ); - -CONST_UINT64_T( PBA_OCC_ACTION_0x0201084A , ULL(0x0201084A) ); -CONST_UINT64_T( PBA_CONFIG_0x0201084B , ULL(0x0201084B) ); -CONST_UINT64_T( PBA_ERR_RPT0_0x0201084C , ULL(0x0201084C) ); -CONST_UINT64_T( PBA_ERR_RPT1_0x0201084D , ULL(0x0201084D) ); -CONST_UINT64_T( PBA_ERR_RPT2_0x0201084E , ULL(0x0201084E) ); -CONST_UINT64_T( PBA_RBUFVAL0_0x02010850 , ULL(0x02010850) ); -CONST_UINT64_T( PBA_RBUFVAL1_0x02010851 , ULL(0x02010851) ); -CONST_UINT64_T( PBA_RBUFVAL2_0x02010852 , ULL(0x02010852) ); -CONST_UINT64_T( PBA_RBUFVAL3_0x02010853 , ULL(0x02010853) ); -CONST_UINT64_T( PBA_RBUFVAL4_0x02010854 , ULL(0x02010854) ); -CONST_UINT64_T( PBA_RBUFVAL5_0x02010855 , ULL(0x02010855) ); -CONST_UINT64_T( PBA_WBUFVAL0_0x02010858 , ULL(0x02010858) ); -CONST_UINT64_T( PBA_WBUFVAL1_0x02010859 , ULL(0x02010859) ); - -CONST_UINT64_T( PBA_MODE_0x00064000 , ULL(0x00064000) ); -CONST_UINT64_T( PBA_SLVRST_0x00064001 , ULL(0x00064001) ); -CONST_UINT64_T( PBA_SLVCTL0_0x00064004 , ULL(0x00064004) ); -CONST_UINT64_T( PBA_SLVCTL1_0x00064005 , ULL(0x00064005) ); -CONST_UINT64_T( PBA_SLVCTL2_0x00064006 , ULL(0x00064006) ); -CONST_UINT64_T( PBA_SLVCTL3_0x00064007 , ULL(0x00064007) ); -CONST_UINT64_T( PBA_BCDE_CTL_0x00064010 , ULL(0x00064010) ); -CONST_UINT64_T( PBA_BCDE_SET_0x00064011 , ULL(0x00064011) ); -CONST_UINT64_T( PBA_BCDE_STAT_0x00064012 , ULL(0x00064012) ); -CONST_UINT64_T( PBA_BCDE_PBADR_0x00064013 , ULL(0x00064013) ); -CONST_UINT64_T( PBA_BCDE_OCIBAR_0x00064014 , ULL(0x00064014) ); -CONST_UINT64_T( PBA_BCUE_CTL_0x00064015 , ULL(0x00064015) ); -CONST_UINT64_T( PBA_BCUE_SET_0x00064016 , ULL(0x00064016) ); -CONST_UINT64_T( PBA_BCUE_STAT_0x00064017 , ULL(0x00064017) ); -CONST_UINT64_T( PBA_BCUE_PBADR_0x00064018 , ULL(0x00064018) ); -CONST_UINT64_T( PBA_BCUE_OCIBAR_0x00064019 , ULL(0x00064019) ); -CONST_UINT64_T( PBA_PBOCR0_0x00064020 , ULL(0x00064020) ); -CONST_UINT64_T( PBA_PBOCR1_0x00064021 , ULL(0x00064021) ); -CONST_UINT64_T( PBA_PBOCR2_0x00064022 , ULL(0x00064022) ); -CONST_UINT64_T( PBA_PBOCR3_0x00064023 , ULL(0x00064023) ); -CONST_UINT64_T( PBA_PBOCR4_0x00064024 , ULL(0x00064024) ); -CONST_UINT64_T( PBA_PBOCR5_0x00064025 , ULL(0x00064025) ); - -CONST_UINT64_T( PBA_BAR0_0x02013F00 , ULL(0x02013F00) ); -CONST_UINT64_T( PBA_BARMSK0_0x02013F04 , ULL(0x02013F04) ); -CONST_UINT64_T( PBA_BAR1_0x02013F01 , ULL(0x02013F01) ); -CONST_UINT64_T( PBA_BARMSK1_0x02013F05 , ULL(0x02013F05) ); -CONST_UINT64_T( PBA_BAR2_0x02013F02 , ULL(0x02013F02) ); -CONST_UINT64_T( PBA_BARMSK2_0x02013F06 , ULL(0x02013F06) ); -CONST_UINT64_T( PBA_BAR3_0x02013F03 , ULL(0x02013F03) ); -CONST_UINT64_T( PBA_BARMSK3_0x02013F07 , ULL(0x02013F07) ); -CONST_UINT64_T( PBA_TRUSTMODE_0x02013F08 , ULL(0x02013F08) ); - -//------------------------------------------------------------------------------ -// PBAX -//------------------------------------------------------------------------------ -CONST_UINT64_T( PBAXSNDTX_00064020 , ULL(0x00064020) ); -CONST_UINT64_T( PBAXCFG_00064021 , ULL(0x00064021) ); -CONST_UINT64_T( PBAXSHBR0_00064026 , ULL(0x00064026) ); -CONST_UINT64_T( PBAXSHCS0_00064027 , ULL(0x00064027) ); -CONST_UINT64_T( PBAXSHBR1_0006402A , ULL(0x0006402A) ); -CONST_UINT64_T( PBAXSHBR1_0006402B , ULL(0x0006402B) ); - -//------------------------------------------------------------------------------ -// PSI -//------------------------------------------------------------------------------ -CONST_UINT64_T( PSI_TXCSR_0x02010800 , ULL(0x02010800) ); -CONST_UINT64_T( PSI_TXERR_0x02010802 , ULL(0x02010802) ); -CONST_UINT64_T( PSI_TXDFSM_0x2010806 , ULL(0x02010806) ); -CONST_UINT64_T( PSI_RXCSR_0x02010808 , ULL(0x02010808) ); -CONST_UINT64_T( PSI_RXERR_0x0201080A , ULL(0x0201080A) ); -CONST_UINT64_T( PSI_RXDFSM_0x201080E , ULL(0x0201080E) ); -CONST_UINT64_T( PSI_TXCIAR_0x02010810 , ULL(0x02010810) ); -CONST_UINT64_T( PSI_TXCMISC_0x02010813 , ULL(0x02010813) ); -CONST_UINT64_T( PSI_RXCIAR_0x02010818 , ULL(0x02010818) ); -CONST_UINT64_T( PSI_RXCMISC_0x0201081B , ULL(0x0201081B) ); -CONST_UINT64_T( PSI_BRIDGE_BAR_0x0201090A , ULL(0x0201090A) ); -CONST_UINT64_T( PSI_FSP_BAR_0x0201090B , ULL(0x0201090B) ); -CONST_UINT64_T( PSI_FSP_MMR_0x0201090C , ULL(0x0201090C) ); -CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_0x0201090E , ULL(0x0201090E) ); -CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_OR_0x02010912 , ULL(0x02010912) ); -CONST_UINT64_T( PSI_BRIDGE_STATUS_CTL_AND_0x02010913 , ULL(0x02010913) ); - -CONST_UINT64_T( PSI_NOTRUST_BAR0_0x02013F40 , ULL(0x02013F40) ); -CONST_UINT64_T( PSI_NOTRUST_BAR1_0x02013F41 , ULL(0x02013F41) ); -CONST_UINT64_T( PSI_NOTRUST_BAR0_MASK_0x02013F42 , ULL(0x02013F42) ); -CONST_UINT64_T( PSI_NOTRUST_BAR1_MASK_0x02013F43 , ULL(0x02013F43) ); - -CONST_UINT64_T( PSI_HB_FIR_0x02010900 , ULL(0x02010900) ); -CONST_UINT64_T( PSI_HB_FIR_AND_0x02010901 , ULL(0x02010901) ); -CONST_UINT64_T( PSI_HB_FIR_OR_0x02010902 , ULL(0x02010902) ); -CONST_UINT64_T( PSI_HB_FIR_MASK_0x02010903 , ULL(0x02010903) ); - -//------------------------------------------------------------------------------ -// HCA -//------------------------------------------------------------------------------ -CONST_UINT64_T( HCA_EN_FIR_0x02010940 , ULL(0x02010940) ); -CONST_UINT64_T( HCA_EN_FIR_AND_0x02010941 , ULL(0x02010941) ); -CONST_UINT64_T( HCA_EN_FIR_MASK_0x02010943 , ULL(0x02010943) ); -CONST_UINT64_T( HCA_EN_BAR_0x0201094A , ULL(0x0201094A) ); -CONST_UINT64_T( HCA_EN_COUNT_BAR_0x0201094B , ULL(0x0201094B) ); -CONST_UINT64_T( HCA_EN_DECAY1_0x0201094C , ULL(0x0201094C) ); -CONST_UINT64_T( HCA_EN_DECAY2_0x0201094D , ULL(0x0201094D) ); -CONST_UINT64_T( HCA_EN_REF_BAR_0x0201094E , ULL(0x0201094E) ); -CONST_UINT64_T( HCA_MODE_0x0201094F , ULL(0x0201094F) ); -CONST_UINT64_T( HCA_EN_RESET_0x02010952 , ULL(0x02010952) ); -CONST_UINT64_T( HCA_EN_MIRROR_BAR_0x02010953 , ULL(0x02010953) ); - -CONST_UINT64_T( HCA_EN_EHHCA_FIR_0x02010980 , ULL(0x02010980) ); -CONST_UINT64_T( HCA_EN_EHHCA_FIR_AND_0x02010981 , ULL(0x02010981) ); -CONST_UINT64_T( HCA_EN_EHHCA_FIR_MASK_0x02010983 , ULL(0x02010983) ); -CONST_UINT64_T( HCA_EH_BAR_0x0201098A , ULL(0x0201098A) ); -CONST_UINT64_T( HCA_EH_COUNT_BAR_0x0201098B , ULL(0x0201098B) ); -CONST_UINT64_T( HCA_EH_REF_BAR_0x0201098E , ULL(0x0201098E) ); -CONST_UINT64_T( HCA_EH_MODE_REG_0x0201098F , ULL(0x0201098F) ); -CONST_UINT64_T( HCA_EH_FLUSH_0x02010990 , ULL(0x02010990) ); -CONST_UINT64_T( HCA_EH_RESET_0x02010992 , ULL(0x02010992) ); -CONST_UINT64_T( HCA_EH_MIRROR_BAR_0x02010993 , ULL(0x02010993) ); - -//------------------------------------------------------------------------------ -// INTERRUPT CONTROL PRESENTER (ICP) -//------------------------------------------------------------------------------ -CONST_UINT64_T( ICP_BAR_0x020109CA , ULL(0x020109CA) ); -CONST_UINT64_T( ICP_SYNC_MODE_REG0_0x020109CB , ULL(0x020109CB) ); -CONST_UINT64_T( ICP_INTR_INJECT_0x020109CC , ULL(0x020109CC) ); - -CONST_UINT64_T( EN_TPC_INTP_SYNC_FIR_0x020109C0 , ULL(0x020109C0) ); -CONST_UINT64_T( EN_TPC_INTP_SYNC_FIR_AND_0x020109C1 , ULL(0x020109C1) ); -CONST_UINT64_T( EN_TPC_INTP_SYNC_FIR_MASK_0x020109C3 , ULL(0x020109C3) ); - - -//------------------------------------------------------------------------------ -// NEST PB EH -//------------------------------------------------------------------------------ -// registers with multiple physical/shadow copies -// west -CONST_UINT64_T( PB_MODE_WEST_0x02010C0A , ULL(0x02010C0A) ); -CONST_UINT64_T( PB_HP_MODE_NEXT_WEST_0x02010C0B , ULL(0x02010C0B) ); -CONST_UINT64_T( PB_HP_MODE_CURR_WEST_0x02010C0C , ULL(0x02010C0C) ); -CONST_UINT64_T( PB_HPX_MODE_NEXT_WEST_0x02010C0D , ULL(0x02010C0D) ); -CONST_UINT64_T( PB_HPX_MODE_CURR_WEST_0x02010C0E , ULL(0x02010C0E) ); -CONST_UINT64_T( PB_FLMCFG0_WEST_0x02010C12 , ULL(0x02010C12) ); -CONST_UINT64_T( PB_FLMCFG1_WEST_0x02010C13 , ULL(0x02010C13) ); -CONST_UINT64_T( PB_FRMCFG0_WEST_0x02010C14 , ULL(0x02010C14) ); -CONST_UINT64_T( PB_FRMCFG1_WEST_0x02010C15 , ULL(0x02010C15) ); -CONST_UINT64_T( PB_SCONFIG_LOAD_WEST_0x02010C16 , ULL(0x02010C16) ); -// center -CONST_UINT64_T( PB_MODE_CENT_0x02010C4A , ULL(0x02010C4A) ); -CONST_UINT64_T( PB_HP_MODE_NEXT_CENT_0x02010C4B , ULL(0x02010C4B) ); -CONST_UINT64_T( PB_HP_MODE_CURR_CENT_0x02010C4C , ULL(0x02010C4C) ); -CONST_UINT64_T( PB_HPX_MODE_NEXT_CENT_0x02010C4D , ULL(0x02010C4D) ); -CONST_UINT64_T( PB_HPX_MODE_CURR_CENT_0x02010C4E , ULL(0x02010C4E) ); -CONST_UINT64_T( PB_FLMCFG0_CENT_0x02010C5E , ULL(0x02010C5E) ); -CONST_UINT64_T( PB_FLMCFG1_CENT_0x02010C5F , ULL(0x02010C5F) ); -CONST_UINT64_T( PB_FRMCFG0_CENT_0x02010C60 , ULL(0x02010C60) ); -CONST_UINT64_T( PB_FRMCFG1_CENT_0x02010C61 , ULL(0x02010C61) ); -CONST_UINT64_T( PB_SCONFIG_LOAD_CENT_0x02010C6D , ULL(0x02010C6D) ); -// east -CONST_UINT64_T( PB_MODE_EAST_0x02010C8A , ULL(0x02010C8A) ); -CONST_UINT64_T( PB_HP_MODE_NEXT_EAST_0x02010C8B , ULL(0x02010C8B) ); -CONST_UINT64_T( PB_HP_MODE_CURR_EAST_0x02010C8C , ULL(0x02010C8C) ); -CONST_UINT64_T( PB_HPX_MODE_NEXT_EAST_0x02010C8D , ULL(0x02010C8D) ); -CONST_UINT64_T( PB_HPX_MODE_CURR_EAST_0x02010C8E , ULL(0x02010C8E) ); -CONST_UINT64_T( PB_FLMCFG0_EAST_0x02010C92 , ULL(0x02010C92) ); -CONST_UINT64_T( PB_FLMCFG1_EAST_0x02010C93 , ULL(0x02010C93) ); -CONST_UINT64_T( PB_FRMCFG0_EAST_0x02010C94 , ULL(0x02010C94) ); -CONST_UINT64_T( PB_FRMCFG1_EAST_0x02010C95 , ULL(0x02010C95) ); -CONST_UINT64_T( PB_SCONFIG_LOAD_EAST_0x02010C96 , ULL(0x02010C96) ); - -// registers without shadow copies -// center -CONST_UINT64_T( PB_TRACE_0x02010C4F , ULL(0x02010C4F) ); -CONST_UINT64_T( PB_NMPM_COUNT_0x02010C50 , ULL(0x02010C50) ); -CONST_UINT64_T( PB_LMPM_COUNT_0x02010C51 , ULL(0x02010C51) ); -CONST_UINT64_T( PB_RCMD_INTDAT_COUNT_0x02010C52 , ULL(0x02010C52) ); -CONST_UINT64_T( PB_EXTDAT_COUNT_0x02010C53 , ULL(0x02010C53) ); -CONST_UINT64_T( PB_PMU_COUNT0_0x02010C54 , ULL(0x02010C54) ); -CONST_UINT64_T( PB_PMU_COUNT1_0x02010C55 , ULL(0x02010C55) ); -CONST_UINT64_T( PB_PMU_COUNT2_0x02010C56 , ULL(0x02010C56) ); -CONST_UINT64_T( PB_PMU_COUNT3_0x02010C57 , ULL(0x02010C57) ); -CONST_UINT64_T( PB_RGMCFG00_0x02010C58 , ULL(0x02010C58) ); -CONST_UINT64_T( PB_RGMCFG01_0x02010C59 , ULL(0x02010C59) ); -CONST_UINT64_T( PB_RGMCFG10_0x02010C5A , ULL(0x02010C5A) ); -CONST_UINT64_T( PB_RGMCFGM00_0x02010C5B , ULL(0x02010C5B) ); -CONST_UINT64_T( PB_RGMCFGM01_0x02010C5C , ULL(0x02010C5C) ); -CONST_UINT64_T( PB_RGMCFGM10_0x02010C5D , ULL(0x02010C5D) ); -CONST_UINT64_T( PB_GP_CMD_RATE_DP_LO_0x02010C62 , ULL(0x02010C62) ); -CONST_UINT64_T( PB_GP_CMD_RATE_DP_HI_0x02010C63 , ULL(0x02010C63) ); -CONST_UINT64_T( PB_RGP_CMD_RATE_DP_LO_0x02010C64 , ULL(0x02010C64) ); -CONST_UINT64_T( PB_RGP_CMD_RATE_DP_HI_0x02010C65 , ULL(0x02010C65) ); -CONST_UINT64_T( PB_SP_CMD_RATE_DP_LO_0x02010C66 , ULL(0x02010C66) ); -CONST_UINT64_T( PB_SP_CMD_RATE_DP_HI_0x02010C67 , ULL(0x02010C67) ); -CONST_UINT64_T( PB_PMU_0x02010C68 , ULL(0x02010C68) ); -CONST_UINT64_T( PB_EVENT_SEL_0x02010C69 , ULL(0x02010C69) ); -CONST_UINT64_T( PB_EVENT_COMPA_0x02010C6A , ULL(0x02010C6A) ); -CONST_UINT64_T( PB_EVENT_COMPB_0x02010C6B , ULL(0x02010C6B) ); -CONST_UINT64_T( PB_CR_ERROR_0x02010C6C , ULL(0x02010C6C) ); - -//------------------------------------------------------------------------------ -// NEST PB EH FIR -//------------------------------------------------------------------------------ -// west FIR -CONST_UINT64_T( PB_FIR_WEST_0x02010C00 , ULL(0x02010C00) ); -CONST_UINT64_T( PB_FIR_AND_WEST_0x02010C01 , ULL(0x02010C01) ); -CONST_UINT64_T( PB_FIR_OR_WEST_0x02010C02 , ULL(0x02010C02) ); -CONST_UINT64_T( PB_FIR_MASK_WEST_0x02010C03 , ULL(0x02010C03) ); -CONST_UINT64_T( PB_FIR_MASK_AND_WEST_0x02010C04 , ULL(0x02010C04) ); -CONST_UINT64_T( PB_FIR_MASK_OR_WEST_0x02010C05 , ULL(0x02010C05) ); -CONST_UINT64_T( PB_FIR_ACTION0_WEST_0x02010C06 , ULL(0x02010C06) ); -CONST_UINT64_T( PB_FIR_ACTION1_WEST_0x02010C07 , ULL(0x02010C07) ); -// center FIR -CONST_UINT64_T( PB_FIR_CENT_0x02010C40 , ULL(0x02010C40) ); -CONST_UINT64_T( PB_FIR_AND_CENT_0x02010C41 , ULL(0x02010C41) ); -CONST_UINT64_T( PB_FIR_OR_CENT_0x02010C42 , ULL(0x02010C42) ); -CONST_UINT64_T( PB_FIR_MASK_CENT_0x02010C43 , ULL(0x02010C43) ); -CONST_UINT64_T( PB_FIR_MASK_AND_CENT_0x02010C44 , ULL(0x02010C44) ); -CONST_UINT64_T( PB_FIR_MASK_OR_CENT_0x02010C45 , ULL(0x02010C45) ); -CONST_UINT64_T( PB_FIR_ACTION0_CENT_0x02010C46 , ULL(0x02010C46) ); -CONST_UINT64_T( PB_FIR_ACTION1_CENT_0x02010C47 , ULL(0x02010C47) ); -// east FIR -CONST_UINT64_T( PB_FIR_EAST_0x02010C80 , ULL(0x02010C80) ); -CONST_UINT64_T( PB_FIR_AND_EAST_0x02010C81 , ULL(0x02010C81) ); -CONST_UINT64_T( PB_FIR_OR_EAST_0x02010C82 , ULL(0x02010C82) ); -CONST_UINT64_T( PB_FIR_MASK_EAST_0x02010C83 , ULL(0x02010C83) ); -CONST_UINT64_T( PB_FIR_MASK_AND_EAST_0x02010C84 , ULL(0x02010C84) ); -CONST_UINT64_T( PB_FIR_MASK_OR_EAST_0x02010C85 , ULL(0x02010C85) ); -CONST_UINT64_T( PB_FIR_ACTION0_EAST_0x02010C86 , ULL(0x02010C86) ); -CONST_UINT64_T( PB_FIR_ACTION1_EAST_0x02010C87 , ULL(0x02010C87) ); -// RAS FIR -CONST_UINT64_T( PB_RAS_FIR_0x02010C6E , ULL(0x02010C6E) ); -CONST_UINT64_T( PB_RAS_FIR_AND_0x02010C6F , ULL(0x02010C6F) ); -CONST_UINT64_T( PB_RAS_FIR_OR_0x02010C70 , ULL(0x02010C70) ); -CONST_UINT64_T( PB_RAS_FIR_MASK_0x02010C71 , ULL(0x02010C71) ); -CONST_UINT64_T( PB_RAS_FIR_MASK_AND_0x02010C72 , ULL(0x02010C72) ); -CONST_UINT64_T( PB_RAS_FIR_MASK_OR_0x02010C73 , ULL(0x02010C73) ); -CONST_UINT64_T( PB_RAS_FIR_ACTION0_0x02010C74 , ULL(0x02010C74) ); -CONST_UINT64_T( PB_RAS_FIR_ACTION1_0x02010C75 , ULL(0x02010C75) ); -//------------------------------------------------------------------------------ -// PLL LOCK -//------------------------------------------------------------------------------ -// PLL lock information -CONST_UINT64_T( PB_PLLLOCKREG_0x020F0019 , ULL(0x020F0019) ); -CONST_UINT64_T( PCBMS_INTERRUPT_TYPE_REG_0x000F001A , ULL(0x000F001A)); -//------------------------------------------------------------------------------ -// CAPP -//------------------------------------------------------------------------------ -CONST_UINT64_T( CAPP_APC_MASTER_PB_CTL_0x02013018 , ULL(0x02013018) ); -CONST_UINT64_T( CAPP_APC_MASTER_CAPI_CTL_0x02013019 , ULL(0x02013019) ); -CONST_UINT64_T( CAPP_CXA_SNOOP_CFG_0x0201301A , ULL(0x0201301A) ); -CONST_UINT64_T( CAPP_CXA_SNOOP_CTL_0x0201301B , ULL(0x0201301B) ); -CONST_UINT64_T( CAPP_APC_MASTER_LCO_TARGET_0x02013021 , ULL(0x02013021) ); -CONST_UINT64_T( CAPP_CXA_SNP_ARRAY_ADDR_0x02013028 , ULL(0x02013028) ); -CONST_UINT64_T( CAPP_CXA_SNP_ARRAY_DATA_0x02013029 , ULL(0x02013029) ); - -CONST_UINT64_T( CAPP1_APC_MASTER_PB_CTL_0x02013198 , ULL(0x02013198) ); -CONST_UINT64_T( CAPP1_CXA_SNOOP_CFG_0x0201319A , ULL(0x0201319A) ); -CONST_UINT64_T( CAPP1_CXA_SNOOP_CTL_0x0201319B , ULL(0x0201319B) ); -CONST_UINT64_T( CAPP1_APC_MASTER_LCO_TARGET_0x020131A1, ULL(0x020131A1) ); -CONST_UINT64_T( CAPP1_CXA_SNP_ARRAY_ADDR_0x020131A8 , ULL(0x020131A8) ); -CONST_UINT64_T( CAPP1_CXA_SNP_ARRAY_DATA_0x020131A9 , ULL(0x020131A9) ); - -//------------------------------------------------------------------------------ -// MCS -//------------------------------------------------------------------------------ -CONST_UINT64_T( MCS_MCFGP_0x02011800 , ULL(0x02011800) ); -CONST_UINT64_T( MCS_MCFGPM_0x02011801 , ULL(0x02011801) ); -CONST_UINT64_T( MCS_MCFGPR_0x02011802 , ULL(0x02011802) ); -CONST_UINT64_T( MCS_MCSMODE0_0x02011807 , ULL(0x02011807) ); -CONST_UINT64_T( MCS_MCSMODE1_0x02011808 , ULL(0x02011808) ); -CONST_UINT64_T( MCS_MCSYNC_0x0201180B , ULL(0x0201180B) ); -CONST_UINT64_T( MCS_MODE3_REGISTER_0x0201180A , ULL(0x0201180A) ); -CONST_UINT64_T( MCS_MCSMODE4_0x0201181A , ULL(0x0201181A) ); -CONST_UINT64_T( MCS_MCFGPA_0x02011814 , ULL(0x02011814) ); -CONST_UINT64_T( MCS_MCFGPMA_0x02011815 , ULL(0x02011815) ); -CONST_UINT64_T( MCS_MCEPS_0x02011816 , ULL(0x02011816) ); - -CONST_UINT64_T( MCS_MCIFIR_0x02011840 , ULL(0x02011840) ); -CONST_UINT64_T( MCS_MCIFIR_AND_0x02011841 , ULL(0x02011841) ); -CONST_UINT64_T( MCS_MCIFIR_OR_0x02011842 , ULL(0x02011842) ); -CONST_UINT64_T( MCS_MCIFIRMASK_0x02011843 , ULL(0x02011843) ); -CONST_UINT64_T( MCS_MCIFIRMASK_AND_0x02011844 , ULL(0x02011844) ); -CONST_UINT64_T( MCS_MCIFIRMASK_OR_0x02011845 , ULL(0x02011845) ); -CONST_UINT64_T( MCS_MCIFIRACT0_0x02011846 , ULL(0x02011846) ); -CONST_UINT64_T( MCS_MCIFIRACT1_0x02011847 , ULL(0x02011847) ); - -CONST_UINT64_T( MCS_MCICFG_0x0201184A , ULL(0x0201184A) ); -CONST_UINT64_T( MCS_MCISTAT_0x0201184B , ULL(0x0201184B) ); -CONST_UINT64_T( MCS_MCICRCSYN_0x0201184C , ULL(0x0201184C) ); - -CONST_UINT64_T( IOMC_SCOM_MODE_PB_0x02011A20 , ULL(0x02011A20) ); - -CONST_UINT64_T( IOMC0_BUSCNTL_FIR_0x02011A00 , ULL(0x02011A00) ); -CONST_UINT64_T( IOMC0_BUSCNTL_FIR_AND_0x02011A01 , ULL(0x02011A01) ); -CONST_UINT64_T( IOMC0_BUSCNTL_FIR_MASK_0x02011A03 , ULL(0x02011A03) ); - -CONST_UINT64_T( MC1_BUSCNTL_FIR_0x02011E00 , ULL(0x02011E00) ); -CONST_UINT64_T( MC1_BUSCNTL_FIR_AND_0x02011E01 , ULL(0x02011E01) ); - -CONST_UINT64_T( MC2_MCS0_RIGHT_FIR_0x02011C40 , ULL(0x02011C40) ); -CONST_UINT64_T( MC2_MCS0_RIGHT_FIR_AND_0x02011C41 , ULL(0x02011C41) ); - -CONST_UINT64_T( MC2_MCS1_RIGHT_FIR_0x02011CC0 , ULL(0x02011CC0) ); -CONST_UINT64_T( MC2_MCS1_RIGHT_FIR_AND_0x02011CC1 , ULL(0x02011CC1) ); - -CONST_UINT64_T( MC3_MCS0_RIGHT_FIR_0x02011D40 , ULL(0x02011D40) ); -CONST_UINT64_T( MC3_MCS0_RIGHT_FIR_AND_0x02011D41 , ULL(0x02011D41) ); - -CONST_UINT64_T( MC3_MCS1_RIGHT_FIR_0x02011DC0 , ULL(0x02011DC0) ); -CONST_UINT64_T( MC3_MCS1_RIGHT_FIR_AND_0x02011DC1 , ULL(0x02011DC1) ); - -//------------------------------------------------------------------------------ -// NEST Alter-Diplay Unit (ADU) -//------------------------------------------------------------------------------ -CONST_UINT64_T( ADU_CONTROL_0x02020000 , ULL(0x02020000) ); -CONST_UINT64_T( ADU_COMMAND_0x02020001 , ULL(0x02020001) ); -CONST_UINT64_T( ADU_STATUS_0x02020002 , ULL(0x02020002) ); -CONST_UINT64_T( ADU_DATA_0x02020003 , ULL(0x02020003) ); -CONST_UINT64_T( ADU_XSCOM_BASE_0x02020005 , ULL(0x02020005) ); -CONST_UINT64_T( ADU_FORCE_ECC_0x02020010 , ULL(0x02020010) ); -CONST_UINT64_T( ADU_MALF_REG_0x02020011 , ULL(0x02020011) ); -CONST_UINT64_T( ADU_PMISC_MODE_0x0202000B , ULL(0x0202000B) ); -CONST_UINT64_T( ADU_UNTRUSTED_BAR_0x02020015 , ULL(0x02020015) ); -CONST_UINT64_T( ADU_UNTRUSTED_BAR_MASK_0x02020016 , ULL(0x02020016) ); -CONST_UINT64_T( ADU_TBROM_BAR_0x02020017 , ULL(0x02020017) ); -CONST_UINT64_T( ADU_HANG_DIV_0x02020018 , ULL(0x02020018) ); -CONST_UINT64_T( ADU_IOS_LINK_EN_0x02020019 , ULL(0x02020019) ); - -//------------------------------------------------------------------------------ -// PCIe -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE0_FIR_0x02012000 , ULL(0x02012000) ); -CONST_UINT64_T( PCIE0_FIR_AND_0x02012001 , ULL(0x02012001) ); -CONST_UINT64_T( PCIE0_FIR_MASK_0x02012003 , ULL(0x02012003) ); -CONST_UINT64_T( PCIE0_FIR_ACTION0_0x02012006 , ULL(0x02012006) ); -CONST_UINT64_T( PCIE0_FIR_ACTION1_0x02012007 , ULL(0x02012007) ); -CONST_UINT64_T( PCIE0_FIR_ACTION2_0x02012020 , ULL(0x02012020) ); -CONST_UINT64_T( PCIE0_FIR_WOF_0x02012008 , ULL(0x02012008) ); -CONST_UINT64_T( PCIE0_NODAL_BAR0_0x02012010 , ULL(0x02012010) ); -CONST_UINT64_T( PCIE0_NODAL_BAR1_0x02012011 , ULL(0x02012011) ); -CONST_UINT64_T( PCIE0_GROUP_BAR0_0x02012012 , ULL(0x02012012) ); -CONST_UINT64_T( PCIE0_GROUP_BAR1_0x02012013 , ULL(0x02012013) ); -CONST_UINT64_T( PCIE0_NEAR_BAR_F0_0x02012014 , ULL(0x02012014) ); -CONST_UINT64_T( PCIE0_FAR_BAR_F0_0x02012015 , ULL(0x02012015) ); -CONST_UINT64_T( PCIE0_NEAR_BAR_F1_0x02012016 , ULL(0x02012016) ); -CONST_UINT64_T( PCIE0_FAR_BAR_F1_0x02012017 , ULL(0x02012017) ); -CONST_UINT64_T( PCIE0_IO_BAR0_0x02012040 , ULL(0x02012040) ); -CONST_UINT64_T( PCIE0_IO_BAR1_0x02012041 , ULL(0x02012041) ); -CONST_UINT64_T( PCIE0_IO_BAR2_0x02012042 , ULL(0x02012042) ); -CONST_UINT64_T( PCIE0_IO_MASK0_0x02012043 , ULL(0x02012043) ); -CONST_UINT64_T( PCIE0_IO_MASK1_0x02012044 , ULL(0x02012044) ); -CONST_UINT64_T( PCIE0_IO_BAR_EN_0x02012045 , ULL(0x02012045) ); - -CONST_UINT64_T( PCIE1_FIR_0x02012400 , ULL(0x02012400) ); -CONST_UINT64_T( PCIE1_FIR_AND_0x02012401 , ULL(0x02012401) ); -CONST_UINT64_T( PCIE1_FIR_MASK_0x02012403 , ULL(0x02012403) ); -CONST_UINT64_T( PCIE1_FIR_ACTION0_0x02012406 , ULL(0x02012406) ); -CONST_UINT64_T( PCIE1_FIR_ACTION1_0x02012407 , ULL(0x02012407) ); -CONST_UINT64_T( PCIE1_FIR_ACTION2_0x02012420 , ULL(0x02012420) ); -CONST_UINT64_T( PCIE1_FIR_WOF_0x02012408 , ULL(0x02012408) ); -CONST_UINT64_T( PCIE1_NODAL_BAR0_0x02012410 , ULL(0x02012410) ); -CONST_UINT64_T( PCIE1_NODAL_BAR1_0x02012411 , ULL(0x02012411) ); -CONST_UINT64_T( PCIE1_GROUP_BAR0_0x02012412 , ULL(0x02012412) ); -CONST_UINT64_T( PCIE1_GROUP_BAR1_0x02012413 , ULL(0x02012413) ); -CONST_UINT64_T( PCIE1_NEAR_BAR_F0_0x02012414 , ULL(0x02012414) ); -CONST_UINT64_T( PCIE1_FAR_BAR_F0_0x02012415 , ULL(0x02012415) ); -CONST_UINT64_T( PCIE1_NEAR_BAR_F1_0x02012416 , ULL(0x02012416) ); -CONST_UINT64_T( PCIE1_FAR_BAR_F1_0x02012417 , ULL(0x02012417) ); -CONST_UINT64_T( PCIE1_IO_BAR0_0x02012440 , ULL(0x02012440) ); -CONST_UINT64_T( PCIE1_IO_BAR1_0x02012441 , ULL(0x02012441) ); -CONST_UINT64_T( PCIE1_IO_BAR2_0x02012442 , ULL(0x02012442) ); -CONST_UINT64_T( PCIE1_IO_MASK0_0x02012443 , ULL(0x02012443) ); -CONST_UINT64_T( PCIE1_IO_MASK1_0x02012444 , ULL(0x02012444) ); -CONST_UINT64_T( PCIE1_IO_BAR_EN_0x02012445 , ULL(0x02012445) ); - -CONST_UINT64_T( PCIE2_FIR_0x02012800 , ULL(0x02012800) ); -CONST_UINT64_T( PCIE2_FIR_AND_0x02012801 , ULL(0x02012801) ); -CONST_UINT64_T( PCIE2_FIR_MASK_0x02012803 , ULL(0x02012803) ); -CONST_UINT64_T( PCIE2_FIR_ACTION0_0x02012806 , ULL(0x02012806) ); -CONST_UINT64_T( PCIE2_FIR_ACTION1_0x02012807 , ULL(0x02012807) ); -CONST_UINT64_T( PCIE2_FIR_ACTION2_0x02012820 , ULL(0x02012820) ); -CONST_UINT64_T( PCIE2_FIR_WOF_0x02012808 , ULL(0x02012808) ); -CONST_UINT64_T( PCIE2_NODAL_BAR0_0x02012810 , ULL(0x02012810) ); -CONST_UINT64_T( PCIE2_NODAL_BAR1_0x02012811 , ULL(0x02012811) ); -CONST_UINT64_T( PCIE2_GROUP_BAR0_0x02012812 , ULL(0x02012812) ); -CONST_UINT64_T( PCIE2_GROUP_BAR1_0x02012813 , ULL(0x02012813) ); -CONST_UINT64_T( PCIE2_NEAR_BAR_F0_0x02012814 , ULL(0x02012814) ); -CONST_UINT64_T( PCIE2_FAR_BAR_F0_0x02012815 , ULL(0x02012815) ); -CONST_UINT64_T( PCIE2_NEAR_BAR_F1_0x02012816 , ULL(0x02012816) ); -CONST_UINT64_T( PCIE2_FAR_BAR_F1_0x02012817 , ULL(0x02012817) ); -CONST_UINT64_T( PCIE2_IO_BAR0_0x02012840 , ULL(0x02012840) ); -CONST_UINT64_T( PCIE2_IO_BAR1_0x02012841 , ULL(0x02012841) ); -CONST_UINT64_T( PCIE2_IO_BAR2_0x02012842 , ULL(0x02012842) ); -CONST_UINT64_T( PCIE2_IO_MASK0_0x02012843 , ULL(0x02012843) ); -CONST_UINT64_T( PCIE2_IO_MASK1_0x02012844 , ULL(0x02012844) ); -CONST_UINT64_T( PCIE2_IO_BAR_EN_0x02012845 , ULL(0x02012845) ); - -CONST_UINT64_T( PCIE3_FIR_0x02012C00 , ULL(0x02012C00) ); -CONST_UINT64_T( PCIE3_FIR_AND_0x02012C01 , ULL(0x02012C01) ); -CONST_UINT64_T( PCIE3_FIR_MASK_0x02012C03 , ULL(0x02012C03) ); -CONST_UINT64_T( PCIE3_FIR_ACTION0_0x02012C06 , ULL(0x02012C06) ); -CONST_UINT64_T( PCIE3_FIR_ACTION1_0x02012C07 , ULL(0x02012C07) ); -CONST_UINT64_T( PCIE3_FIR_ACTION2_0x02012C20 , ULL(0x02012C20) ); -CONST_UINT64_T( PCIE3_FIR_WOF_0x02012C08 , ULL(0x02012C08) ); -CONST_UINT64_T( PCIE3_NODAL_BAR0_0x02012C10 , ULL(0x02012C10) ); -CONST_UINT64_T( PCIE3_NODAL_BAR1_0x02012C11 , ULL(0x02012C11) ); -CONST_UINT64_T( PCIE3_GROUP_BAR0_0x02012C12 , ULL(0x02012C12) ); -CONST_UINT64_T( PCIE3_GROUP_BAR1_0x02012C13 , ULL(0x02012C13) ); -CONST_UINT64_T( PCIE3_NEAR_BAR_F0_0x02012C14 , ULL(0x02012C14) ); -CONST_UINT64_T( PCIE3_FAR_BAR_F0_0x02012C15 , ULL(0x02012C15) ); -CONST_UINT64_T( PCIE3_NEAR_BAR_F1_0x02012C16 , ULL(0x02012C16) ); -CONST_UINT64_T( PCIE3_FAR_BAR_F1_0x02012C17 , ULL(0x02012C17) ); -CONST_UINT64_T( PCIE3_IO_BAR0_0x02012C40 , ULL(0x02012C40) ); -CONST_UINT64_T( PCIE3_IO_BAR1_0x02012C41 , ULL(0x02012C41) ); -CONST_UINT64_T( PCIE3_IO_BAR2_0x02012C42 , ULL(0x02012C42) ); -CONST_UINT64_T( PCIE3_IO_MASK0_0x02012C43 , ULL(0x02012C43) ); -CONST_UINT64_T( PCIE3_IO_MASK1_0x02012C44 , ULL(0x02012C44) ); -CONST_UINT64_T( PCIE3_IO_BAR_EN_0x02012C45 , ULL(0x02012C45) ); - -//------------------------------------------------------------------------------ -// NX -//------------------------------------------------------------------------------ -CONST_UINT64_T( NX_APC_NODAL_BAR0_0x0201302D , ULL(0x0201302D) ); -CONST_UINT64_T( NX_APC_NODAL_BAR1_0x0201302E , ULL(0x0201302E) ); -CONST_UINT64_T( NX_APC_GROUP_BAR0_0x0201302F , ULL(0x0201302F) ); -CONST_UINT64_T( NX_APC_GROUP_BAR1_0x02013030 , ULL(0x02013030) ); -CONST_UINT64_T( NX_APC_NEAR_BAR_F0_0x02013031 , ULL(0x02013031) ); -CONST_UINT64_T( NX_APC_FAR_BAR_F0_0x02013032 , ULL(0x02013032) ); -CONST_UINT64_T( NX_APC_NEAR_BAR_F1_0x02013033 , ULL(0x02013033) ); -CONST_UINT64_T( NX_APC_FAR_BAR_F1_0x02013034 , ULL(0x02013034) ); -CONST_UINT64_T( NX_MMIO_BAR_0x0201308D , ULL(0x0201308D) ); -CONST_UINT64_T( NX_NODAL_BAR0_0x02013095 , ULL(0x02013095) ); -CONST_UINT64_T( NX_NODAL_BAR1_0x02013096 , ULL(0x02013096) ); -CONST_UINT64_T( NX_GROUP_BAR0_0x02013097 , ULL(0x02013097) ); -CONST_UINT64_T( NX_GROUP_BAR1_0x02013098 , ULL(0x02013098) ); -CONST_UINT64_T( NX_NEAR_BAR_F0_0x02013099 , ULL(0x02013099) ); -CONST_UINT64_T( NX_FAR_BAR_F0_0x0201309A , ULL(0x0201309A) ); -CONST_UINT64_T( NX_NEAR_BAR_F1_0x0201309B , ULL(0x0201309B) ); -CONST_UINT64_T( NX_FAR_BAR_F1_0x0201309C , ULL(0x0201309C) ); -CONST_UINT64_T( NX_CQ_EPS_0x0201309D , ULL(0x0201309D) ); -CONST_UINT64_T( NX_AS_MMIO_BAR_0x0201309E , ULL(0x0201309E) ); - -CONST_UINT64_T( NX_CXA1_APC_NODAL_BAR0_0x020131AD , ULL(0x020131AD) ); -CONST_UINT64_T( NX_CXA1_APC_NODAL_BAR1_0x020131AE , ULL(0x020131AE) ); -CONST_UINT64_T( NX_CXA1_APC_GROUP_BAR0_0x020131AF , ULL(0x020131AF) ); -CONST_UINT64_T( NX_CXA1_APC_GROUP_BAR1_0x020131B0 , ULL(0x020131B0) ); -CONST_UINT64_T( NX_CXA1_APC_NEAR_BAR_F0_0x020131B1 , ULL(0x020131B1) ); -CONST_UINT64_T( NX_CXA1_APC_FAR_BAR_F0_0x020131B2 , ULL(0x020131B2) ); -CONST_UINT64_T( NX_CXA1_APC_NEAR_BAR_F1_0x020131B3 , ULL(0x020131B3) ); -CONST_UINT64_T( NX_CXA1_APC_FAR_BAR_F1_0x020131B4 , ULL(0x020131B4) ); - -CONST_UINT64_T( NX_CAPP_FIR_0x02013000 , ULL(0x02013000) ); -CONST_UINT64_T( NX_CAPP_FIR_AND_0x02013001 , ULL(0x02013001) ); -CONST_UINT64_T( NX_CAPP_FIR_MASK_0x02013003 , ULL(0x02013003) ); -CONST_UINT64_T( NX_CAPP_FIR_ACTION0_0x02013006 , ULL(0x02013006) ); -CONST_UINT64_T( NX_CAPP_FIR_ACTION1_0x02013007 , ULL(0x02013007) ); -CONST_UINT64_T( NX_CAPP_SNOOP_ERR_REPORT_0x0201300A , ULL(0x0201300A) ); -CONST_UINT64_T( NX_CAPP_APC_MASTER_ERR_REPORT_0x0201300B, ULL(0x0201300B) ); -CONST_UINT64_T( NX_CAPP_TRANSPORT_ERR_HOLD_0x0201300C , ULL(0x0201300C) ); -CONST_UINT64_T( NX_CAPP_TLBI_ERR_HOLD_0x0201300D , ULL(0x0201300D) ); -CONST_UINT64_T( NX_CAPP_ERR_STAT_CTRL_0x0201300E , ULL(0x0201300E) ); -CONST_UINT64_T( NX_CAPP_FLUSH_SUE_STATE_MAP_0x0201300F, ULL(0x0201300F) ); -CONST_UINT64_T( NX_CAPP_ERR_INJECT_0x02013010 , ULL(0x02013010) ); -CONST_UINT64_T( NX_CAPP_DEBUG_CTRL_0x02013011 , ULL(0x02013011) ); -CONST_UINT64_T( NX_CAPP_EPOCH_RECOV_TIMERS_CTRL_0x0201302C, ULL(0x0201302C) ); -CONST_UINT64_T( NX_CAPP_FLUSH_SUE_UOP1_0x02013803 , ULL(0x02013803) ); -CONST_UINT64_T( NX_CAPP_FLUSH_SUE_UOP2_0x02013804 , ULL(0x02013804) ); - -CONST_UINT64_T( NX_CAPP1_FIR_0x02013180 , ULL(0x02013180) ); -CONST_UINT64_T( NX_CAPP1_FIR_AND_0x02013181 , ULL(0x02013181) ); -CONST_UINT64_T( NX_CAPP1_FIR_MASK_0x02013183 , ULL(0x02013183) ); -CONST_UINT64_T( NX_CAPP1_FIR_ACTION0_0x02013186 , ULL(0x02013186) ); -CONST_UINT64_T( NX_CAPP1_FIR_ACTION1_0x02013187 , ULL(0x02013187) ); -CONST_UINT64_T( NX_CAPP1_SNOOP_ERR_REPORT_0x0201318A , ULL(0x0201318A) ); -CONST_UINT64_T( NX_CAPP1_APC_MASTER_ERR_REPORT_0x0201318B, ULL(0x0201318B) ); -CONST_UINT64_T( NX_CAPP1_TRANSPORT_ERR_HOLD_0x0201318C, ULL(0x0201318C) ); -CONST_UINT64_T( NX_CAPP1_TLBI_ERR_HOLD_0x0201318D , ULL(0x0201318D) ); -CONST_UINT64_T( NX_CAPP1_ERR_STAT_CTRL_0x0201318E , ULL(0x0201318E) ); -CONST_UINT64_T( NX_CAPP1_FLUSH_SUE_STATE_MAP_0x0201318F, ULL(0x0201318F) ); -CONST_UINT64_T( NX_CAPP1_ERR_INJECT_0x02013190 , ULL(0x02013190) ); -CONST_UINT64_T( NX_CAPP1_DEBUG_CTRL_0x02013191 , ULL(0x02013191) ); -CONST_UINT64_T( NX_CAPP1_EPOCH_RECOV_TIMERS_CTRL_0x020131AC, ULL(0x020131AC) ); -CONST_UINT64_T( NX_CAPP1_FLUSH_SUE_UOP1_0x02013983 , ULL(0x02013983) ); -CONST_UINT64_T( NX_CAPP1_FLUSH_SUE_UOP2_0x02013984 , ULL(0x02013984) ); - -CONST_UINT64_T( NX_PB_DEBUG_0x02013090 , ULL(0x02013090) ); -CONST_UINT64_T( NX_DEBUG_SNAPSHOT0_0x020130A4 , ULL(0x020130A4) ); -CONST_UINT64_T( NX_DEBUG_SNAPSHOT1_0x020130A5 , ULL(0x020130A5) ); - -CONST_UINT64_T( NX_DMA_ENG_FIR_0x02013100 , ULL(0x02013100) ); -CONST_UINT64_T( NX_DMA_ENG_FIR_AND_0x02013101 , ULL(0x02013101) ); -CONST_UINT64_T( NX_DMA_ENG_FIR_MASK_0x02013103 , ULL(0x02013103) ); - -CONST_UINT64_T( NX_DEBUGMUX_CTRL_0x0201310A , ULL(0x0201310A) ); - -CONST_UINT64_T( NX_CQ_FIR_0x02013080 , ULL(0x02013080) ); -CONST_UINT64_T( NX_CQ_FIR_AND_0x02013081 , ULL(0x02013081) ); -CONST_UINT64_T( NX_CQ_FIR_MASK_0x02013083 , ULL(0x02013083) ); - -CONST_UINT64_T( NX_AS_FIR_0x020130C0 , ULL(0x020130C0) ); -CONST_UINT64_T( NX_AS_FIR_AND_0x020130C1 , ULL(0x020130C1) ); -CONST_UINT64_T( NX_AS_FIR_MASK_0x020130C3 , ULL(0x020130C3) ); - -//------------------------------------------------------------------------------ -// MCD -//------------------------------------------------------------------------------ -CONST_UINT64_T( MCD_FIR_0x02013400 , ULL(0x02013400) ); -CONST_UINT64_T( MCD_FIR_AND_0x02013401 , ULL(0x02013401) ); -CONST_UINT64_T( MCD_FIR_OR_0x02013402 , ULL(0x02013402) ); -CONST_UINT64_T( MCD_FIR_MASK_0x02013403 , ULL(0x02013403) ); -CONST_UINT64_T( MCD_FIR_MASK_AND_0x02013404 , ULL(0x02013404) ); -CONST_UINT64_T( MCD_FIR_MASK_OR_0x02013405 , ULL(0x02013405) ); -CONST_UINT64_T( MCD_FIR_ACTION0_0x02013406 , ULL(0x02013406) ); -CONST_UINT64_T( MCD_FIR_ACTION1_0x02013407 , ULL(0x02013407) ); - -CONST_UINT64_T( MCD_PRE_EPS_0x0201340B , ULL(0x0201340B) ); -CONST_UINT64_T( MCD_CN00_0x0201340C , ULL(0x0201340C) ); -CONST_UINT64_T( MCD_CN01_0x0201340D , ULL(0x0201340D) ); -CONST_UINT64_T( MCD_CN10_0x0201340E , ULL(0x0201340E) ); -CONST_UINT64_T( MCD_CN11_0x0201340F , ULL(0x0201340F) ); -CONST_UINT64_T( MCD_REC_EVEN_0x02013410 , ULL(0x02013410) ); -CONST_UINT64_T( MCD_REC_ODD_0x02013411 , ULL(0x02013411) ); - - -/******************************************************************************/ -/****************************** X-BUS CHIPLET *******************************/ -/******************************************************************************/ - -//------------------------------------------------------------------------------ -// X-BUS GPIO -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_GP0_0x04000000 , ULL(0x04000000) ); -CONST_UINT64_T( X_GP1_0x04000001 , ULL(0x04000001) ); -CONST_UINT64_T( X_GP2_0x04000002 , ULL(0x04000002) ); - -CONST_UINT64_T( X_CLK_ADJ_DAT_REG_0x040F0015 , ULL(0x040F0015) ); -CONST_UINT64_T( X_CLK_ADJ_SET_0x040F0016 , ULL(0x040F0016) ); - -//------------------------------------------------------------------------------ -// X-BUS SCOM -// ring 1 = Trace 0 -// ring 2 = Trace 1 -// ring 3 = PBEN -// ring 4 = IOX0 -// ring 5 = IOX1 -// ring 6 = IOX3 -// ring 7 = IOX2 -// ring 9 = IOPSI -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_SCOM_0x04010000 , ULL(0x04010000) ); - -//------------------------------------------------------------------------------ -// X-BUS TRACE -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_TRACE_STATUS_0x04010004 , ULL(0x04010004) ); -CONST_UINT64_T( X_TRACE_DATA_HI_T0_0x04010400 , ULL(0x04010400) ); -CONST_UINT64_T( X_TRACE_DATA_LO_T0_0x04010401 , ULL(0x04010401) ); -CONST_UINT64_T( X_TRACE_DATA_HI_T1_0x04010800 , ULL(0x04010800) ); -CONST_UINT64_T( X_TRACE_DATA_LO_T1_0x04010801 , ULL(0x04010801) ); - - - -//------------------------------------------------------------------------------ -// X-BUS PBEN -//------------------------------------------------------------------------------ -CONST_UINT64_T( PB_X_FIR_0x04010C00 , ULL(0x04010C00) ); -CONST_UINT64_T( PB_X_FIR_AND_0x04010C01 , ULL(0x04010C01) ); -CONST_UINT64_T( PB_X_FIR_OR_0x04010C02 , ULL(0x04010C02) ); -CONST_UINT64_T( PB_X_FIR_MASK_0x04010C03 , ULL(0x04010C03) ); -CONST_UINT64_T( PB_X_FIR_MASK_AND_0x04010C04 , ULL(0x04010C04) ); -CONST_UINT64_T( PB_X_FIR_MASK_OR_0x04010C05 , ULL(0x04010C05) ); -CONST_UINT64_T( PB_X_FIR_ACTION0_0x04010C06 , ULL(0x04010C06) ); -CONST_UINT64_T( PB_X_FIR_ACTION1_0x04010C07 , ULL(0x04010C07) ); - -CONST_UINT64_T( PB_X_MODE_0x04010C0A , ULL(0x04010C0A) ); - -//------------------------------------------------------------------------------ -// X-BUS IOPSI -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_PSI_FIR_0x04012400 , ULL(0x04012400) ); -CONST_UINT64_T( X_PSI_FIR_MASK_0x04012403 , ULL(0x04012403) ); -CONST_UINT64_T( X_PSI_RXCNTL_0x04012420 , ULL(0x04012420) ); -CONST_UINT64_T( X_PSI_RXSTATUS_0x04012422 , ULL(0x04012422) ); -CONST_UINT64_T( X_PSI_TXCNTL_0x04012430 , ULL(0x04012430) ); - -//------------------------------------------------------------------------------ -// X-BUS CLOCK CONTROL -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_OPCG_CNTL0_0x04030002 , ULL(0x04030002) ); -CONST_UINT64_T( X_OPCG_CNTL1_0x04030003 , ULL(0x04030003) ); -CONST_UINT64_T( X_OPCG_CNTL2_0x04030004 , ULL(0x04030004) ); -CONST_UINT64_T( X_OPCG_CNTL3_0x04030005 , ULL(0x04030005) ); -CONST_UINT64_T( X_CLK_REGION_0x04030006 , ULL(0x04030006) ); -CONST_UINT64_T( X_CLK_SCANSEL_0x04030007 , ULL(0x04030007) ); -CONST_UINT64_T( X_CLK_STATUS_0x04030008 , ULL(0x04030008) ); -CONST_UINT64_T( X_CC_ERROR_STATUS_0x04030009 , ULL(0x04030009) ); -CONST_UINT64_T( X_CC_PROTECT_MODE_0x040303FE , ULL(0x040303FE) ); - -//------------------------------------------------------------------------------ -// X-BUS FIR -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_XSTOP_0x04040000 , ULL(0x04040000) ); -CONST_UINT64_T( X_RECOV_0x04040001 , ULL(0x04040001) ); -CONST_UINT64_T( X_FIR_MASK_0x04040002 , ULL(0x04040002) ); -CONST_UINT64_T( X_SPATTN_0x04040004 , ULL(0x04040004) ); -CONST_UINT64_T( X_SPATTN_AND_0x04040005 , ULL(0x04040005) ); -CONST_UINT64_T( X_SPATTN_OR_0x04040006 , ULL(0x04040006) ); -CONST_UINT64_T( X_SPATTN_MASK_0x04040007 , ULL(0x04040007) ); -CONST_UINT64_T( X_FIR_MODE_0x04040008 , ULL(0x04040008) ); -CONST_UINT64_T( X_PERV_LFIR_0x0404000A , ULL(0x0404000A) ); -CONST_UINT64_T( X_PERV_LFIR_AND_0x0404000B , ULL(0x0404000B) ); -CONST_UINT64_T( X_PERV_LFIR_OR_0x0404000C , ULL(0x0404000C) ); -CONST_UINT64_T( X_PERV_LFIR_MASK_0x0404000D , ULL(0x0404000D) ); -CONST_UINT64_T( X_PERV_LFIR_MASK_AND_0x0404000E , ULL(0x0404000E) ); -CONST_UINT64_T( X_PERV_LFIR_MASK_OR_0x0404000F , ULL(0x0404000F) ); -CONST_UINT64_T( X_PERV_LFIR_ACT0_0x04040010 , ULL(0x04040010) ); -CONST_UINT64_T( X_PERV_LFIR_ACT1_0x04040011 , ULL(0x04040011) ); - -CONST_UINT64_T( X_XBUS0_BUSCNTL_FIR_0x04011000 , ULL(0x04011000) ); -CONST_UINT64_T( X_XBUS0_BUSCNTL_FIR_AND_0x04011001 , ULL(0x04011001) ); -CONST_UINT64_T( X_XBUS0_BUSCNTL_FIR_MASK_0x04011003 , ULL(0x04011003) ); - -CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_0x04011400 , ULL(0x04011400) ); -CONST_UINT64_T( X_XBUS1_BUSCNTL_FIR_AND_0x04011401 , ULL(0x04011401) ); - -CONST_UINT64_T( X_XBUS_SCOM_MODE_PB_0x04011020 , ULL(0x04011020) ); - -//------------------------------------------------------------------------------ -// X-BUS THERMAL -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_THERM_0x04050000 , ULL(0x04050000) ); - -//------------------------------------------------------------------------------ -// X-BUS PCB SLAVE -//------------------------------------------------------------------------------ -//Multicast Group Registers -CONST_UINT64_T( X_MCGR1_0x040F0001 , ULL(0x040F0001) ); -CONST_UINT64_T( X_MCGR2_0x040F0002 , ULL(0x040F0002) ); -CONST_UINT64_T( X_MCGR3_0x040F0003 , ULL(0x040F0003) ); -CONST_UINT64_T( X_MCGR4_0x040F0004 , ULL(0x040F0004) ); -//GP0 Register -CONST_UINT64_T( X_GP0_AND_0x04000004 , ULL(0x04000004) ); -CONST_UINT64_T( X_GP0_OR_0x04000005 , ULL(0x04000005) ); -//GP3 Register -CONST_UINT64_T( X_GP3_0x040F0012 , ULL(0x040F0012) ); -CONST_UINT64_T( X_GP3_AND_0x040F0013 , ULL(0x040F0013) ); -CONST_UINT64_T( X_GP3_OR_0x040F0014 , ULL(0x040F0014) ); -// PLL lock information -CONST_UINT64_T( X_PLLLOCKREG_0x040F0019 , ULL(0x040F0019) ); - -//------------------------------------------------------------------------------ -// X-BUS HANG DETECTION -//------------------------------------------------------------------------------ -CONST_UINT64_T( X_HANG_P0_XBUS_0x040F0020 , ULL(0x040F0020) ); // XBUS : setup hang pulse register0 -CONST_UINT64_T( X_HANG_P6_XBUS_0x040F0026 , ULL(0x040F0026) ); // XBUS : setup hang pulse register6 -CONST_UINT64_T( X_HANG_PRE_XBUS_0x040F0028 , ULL(0x040F0028) ); // XBUS : setup hang precounter (HEX:01) - - -/******************************************************************************/ -/****************************** A-BUS CHIPLET *******************************/ -/******************************************************************************/ -//------------------------------------------------------------------------------ -// A-BUS GPIO -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_GP0_0x08000000 , ULL(0x08000000) ); -CONST_UINT64_T( A_GP1_0x08000001 , ULL(0x08000001) ); -CONST_UINT64_T( A_GP2_0x08000002 , ULL(0x08000002) ); - -//------------------------------------------------------------------------------ -// A-BUS SCOM -// ring 1 = trace -// ring 2 = PBES -// ring 3 = IOA -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_SCOM_0x08010000 , ULL(0x08010000) ); - -//------------------------------------------------------------------------------ -// A-BUS TRACE[0,1] -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_TRACE_STATUS_0x08010004 , ULL(0x08010004) ); -CONST_UINT64_T( A_TRACE_DATA_HI_0x08010400 , ULL(0x08010400) ); -CONST_UINT64_T( A_TRACE_DATA_LO_0x08010401 , ULL(0x08010401) ); -CONST_UINT64_T( A_TRACE_DATA_HI_0x08010440 , ULL(0x08010440) ); -CONST_UINT64_T( A_TRACE_DATA_LO_0x08010441 , ULL(0x08010441) ); - -//------------------------------------------------------------------------------ -// A-BUS CLOCK CONTROL -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_OPCG_CNTL0_0x08030002 , ULL(0x08030002) ); -CONST_UINT64_T( A_OPCG_CNTL1_0x08030003 , ULL(0x08030003) ); -CONST_UINT64_T( A_OPCG_CNTL2_0x08030004 , ULL(0x08030004) ); -CONST_UINT64_T( A_OPCG_CNTL3_0x08030005 , ULL(0x08030005) ); -CONST_UINT64_T( A_CLK_REGION_0x08030006 , ULL(0x08030006) ); -CONST_UINT64_T( A_CLK_SCANSEL_0x08030007 , ULL(0x08030007) ); -CONST_UINT64_T( A_CLK_STATUS_0x08030008 , ULL(0x08030008) ); -CONST_UINT64_T( A_CC_ERROR_STATUS_0x08030009 , ULL(0x08030009) ); -CONST_UINT64_T( A_CC_PROTECT_MODE_0x080303FE , ULL(0x080303FE) ); - -//------------------------------------------------------------------------------ -// A-BUS FIR -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_XSTOP_0x08040000 , ULL(0x08040000) ); -CONST_UINT64_T( A_RECOV_0x08040001 , ULL(0x08040001) ); -CONST_UINT64_T( A_FIR_MASK_0x08040002 , ULL(0x08040002) ); -CONST_UINT64_T( A_SPATTN_0x08040004 , ULL(0x08040004) ); -CONST_UINT64_T( A_SPATTN_AND_0x08040005 , ULL(0x08040005) ); -CONST_UINT64_T( A_SPATTN_OR_0x08040006 , ULL(0x08040006) ); -CONST_UINT64_T( A_SPATTN_MASK_0x08040007 , ULL(0x08040007) ); -CONST_UINT64_T( A_FIR_MODE_0x08040008 , ULL(0x08040008) ); -CONST_UINT64_T( A_PERV_LFIR_0x0804000A , ULL(0x0804000A) ); -CONST_UINT64_T( A_PERV_LFIR_AND_0x0804000B , ULL(0x0804000B) ); -CONST_UINT64_T( A_PERV_LFIR_OR_0x0804000C , ULL(0x0804000C) ); -CONST_UINT64_T( A_PERV_LFIR_MASK_0x0804000D , ULL(0x0804000D) ); -CONST_UINT64_T( A_PERV_LFIR_MASK_AND_0x0804000E , ULL(0x0804000E) ); -CONST_UINT64_T( A_PERV_LFIR_MASK_OR_0x0804000F , ULL(0x0804000F) ); -CONST_UINT64_T( A_PERV_LFIR_ACT0_0x08040010 , ULL(0x08040010) ); -CONST_UINT64_T( A_PERV_LFIR_ACT1_0x08040011 , ULL(0x08040011) ); - -CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_0x08010C00 , ULL(0x08010C00) ); -CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_AND_0x08010C01 , ULL(0x08010C01) ); -CONST_UINT64_T( A_ABUS_BUSCNTL_FIR_MASK_0x08010C03 , ULL(0x08010C03) ); - -CONST_UINT64_T( A_ABUS_SCOM_MODE_PB_0x08010C20 , ULL(0x08010C20) ); - -//------------------------------------------------------------------------------ -// NV/NPU -//------------------------------------------------------------------------------ -CONST_UINT64_T( NV0_BUSCNTL_FIR_0x08010C00 , ULL(0x08010C00) ); -CONST_UINT64_T( NV1_BUSCNTL_FIR_0x08010C40 , ULL(0x08010C40) ); - -CONST_UINT64_T( NPU0_MMIO_BAR0_0x08013C02 , ULL(0x08013C02) ); -CONST_UINT64_T( NPU0_MMIO_BAR1_0x08013C03 , ULL(0x08013C03) ); -CONST_UINT64_T( NPU0_NODAL_BAR0_0x08013C04 , ULL(0x08013C04) ); -CONST_UINT64_T( NPU0_NODAL_BAR1_0x08013C05 , ULL(0x08013C05) ); -CONST_UINT64_T( NPU0_GROUP_BAR0_0x08013C06 , ULL(0x08013C06) ); -CONST_UINT64_T( NPU0_GROUP_BAR1_0x08013C07 , ULL(0x08013C07) ); -CONST_UINT64_T( NPU0_CQ_EPS_0x08013C08 , ULL(0x08013C08) ); - -CONST_UINT64_T( NPU1_MMIO_BAR0_0x08013C42 , ULL(0x08013C42) ); -CONST_UINT64_T( NPU1_MMIO_BAR1_0x08013C43 , ULL(0x08013C43) ); -CONST_UINT64_T( NPU1_NODAL_BAR0_0x08013C44 , ULL(0x08013C44) ); -CONST_UINT64_T( NPU1_NODAL_BAR1_0x08013C45 , ULL(0x08013C45) ); -CONST_UINT64_T( NPU1_GROUP_BAR0_0x08013C46 , ULL(0x08013C46) ); -CONST_UINT64_T( NPU1_GROUP_BAR1_0x08013C47 , ULL(0x08013C47) ); -CONST_UINT64_T( NPU1_CQ_EPS_0x08013C48 , ULL(0x08013C48) ); - -CONST_UINT64_T( NPU2_MMIO_BAR0_0x08013D02 , ULL(0x08013D02) ); -CONST_UINT64_T( NPU2_MMIO_BAR1_0x08013D03 , ULL(0x08013D03) ); -CONST_UINT64_T( NPU2_NODAL_BAR0_0x08013D04 , ULL(0x08013D04) ); -CONST_UINT64_T( NPU2_NODAL_BAR1_0x08013D05 , ULL(0x08013D05) ); -CONST_UINT64_T( NPU2_GROUP_BAR0_0x08013D06 , ULL(0x08013D06) ); -CONST_UINT64_T( NPU2_GROUP_BAR1_0x08013D07 , ULL(0x08013D07) ); -CONST_UINT64_T( NPU2_CQ_EPS_0x08013D08 , ULL(0x08013D08) ); - -CONST_UINT64_T( NPU3_MMIO_BAR0_0x08013D42 , ULL(0x08013D42) ); -CONST_UINT64_T( NPU3_MMIO_BAR1_0x08013D43 , ULL(0x08013D43) ); -CONST_UINT64_T( NPU3_NODAL_BAR0_0x08013D44 , ULL(0x08013D44) ); -CONST_UINT64_T( NPU3_NODAL_BAR1_0x08013D45 , ULL(0x08013D45) ); -CONST_UINT64_T( NPU3_GROUP_BAR0_0x08013D46 , ULL(0x08013D46) ); -CONST_UINT64_T( NPU3_GROUP_BAR1_0x08013D47 , ULL(0x08013D47) ); -CONST_UINT64_T( NPU3_CQ_EPS_0x08013D48 , ULL(0x08013D48) ); - -CONST_UINT64_T( NPU_FIR_0x08013D80 , ULL(0x08013D80) ); -CONST_UINT64_T( NPU_FIR_AND_0x08013D81 , ULL(0x08013D81) ); -CONST_UINT64_T( NPU_FIR_OR_0x08013D82 , ULL(0x08013D82) ); -CONST_UINT64_T( NPU_FIR_MASK_0x08013D83 , ULL(0x08013D83) ); -CONST_UINT64_T( NPU_FIR_MASK_AND_0x08013D84 , ULL(0x08013D84) ); -CONST_UINT64_T( NPU_FIR_MASK_OR_0x08013D85 , ULL(0x08013D85) ); - -//------------------------------------------------------------------------------ -// PLL LOCK -//------------------------------------------------------------------------------ -// PLL lock information -CONST_UINT64_T( A_PLLLOCKREG_0x080F0019 , ULL(0x080F0019) ); - -//------------------------------------------------------------------------------ -// A-BUS THERMAL -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_THERM_0x08050000 , ULL(0x08050000) ); - -//------------------------------------------------------------------------------ -// A-BUS PCB SLAVE -//------------------------------------------------------------------------------ -//Multicast Group Registers -CONST_UINT64_T( A_MCGR1_0x080F0001 , ULL(0x080F0001) ); -CONST_UINT64_T( A_MCGR2_0x080F0002 , ULL(0x080F0002) ); -CONST_UINT64_T( A_MCGR3_0x080F0003 , ULL(0x080F0003) ); -CONST_UINT64_T( A_MCGR4_0x080F0004 , ULL(0x080F0004) ); -//GP0 Register -CONST_UINT64_T( A_GP0_AND_0x08000004 , ULL(0x08000004) ); -CONST_UINT64_T( A_GP0_OR_0x08000005 , ULL(0x08000005) ); -//GP3 Register -CONST_UINT64_T( A_GP3_0x080F0012 , ULL(0x080F0012) ); -CONST_UINT64_T( A_GP3_AND_0x080F0013 , ULL(0x080F0013) ); -CONST_UINT64_T( A_GP3_OR_0x080F0014 , ULL(0x080F0014) ); - -//------------------------------------------------------------------------------ -// A-BUS HANG DETECTION -//------------------------------------------------------------------------------ -CONST_UINT64_T( A_HANG_P0_0x080F0020 , ULL(0x080F0020) ); // ABUS : setup hang pulse register0 -CONST_UINT64_T( A_HANG_P6_0x080F0026 , ULL(0x080F0026) ); // ABUS : setup hang pulse register6 -CONST_UINT64_T( A_HANG_PRE_0x080F0028 , ULL(0x080F0028) ); // ABUS : setup hang precounter (HEX:01) - -//------------------------------------------------------------------------------ -// A-BUS PBES -//------------------------------------------------------------------------------ -CONST_UINT64_T( PB_A_FIR_0x08010800 , ULL(0x08010800) ); -CONST_UINT64_T( PB_A_FIR_AND_0x08010801 , ULL(0x08010801) ); -CONST_UINT64_T( PB_A_FIR_OR_0x08010802 , ULL(0x08010802) ); -CONST_UINT64_T( PB_A_FIR_MASK_0x08010803 , ULL(0x08010803) ); -CONST_UINT64_T( PB_A_FIR_MASK_AND_0x08010804 , ULL(0x08010804) ); -CONST_UINT64_T( PB_A_FIR_MASK_OR_0x08010805 , ULL(0x08010805) ); -CONST_UINT64_T( PB_A_FIR_ACTION0_0x08010806 , ULL(0x08010806) ); -CONST_UINT64_T( PB_A_FIR_ACTION1_0x08010807 , ULL(0x08010807) ); - -CONST_UINT64_T( PB_A_MODE_0x0801080A , ULL(0x0801080A) ); -CONST_UINT64_T( PB_A_TRACE_0x08010812 , ULL(0x08010812) ); -CONST_UINT64_T( PB_A_FMR_CFG_0x08010813 , ULL(0x08010813) ); - -/******************************************************************************/ -/***************************** PCIE-BUS CHIPLET *****************************/ -/******************************************************************************/ -//------------------------------------------------------------------------------ -// PCIE-BUS GPIO -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_GP0_0x09000000 , ULL(0x09000000) ); -CONST_UINT64_T( PCIE_GP1_0x09000001 , ULL(0x09000001) ); -CONST_UINT64_T( PCIE_GP2_0x09000002 , ULL(0x09000002) ); -CONST_UINT64_T( PCIE_GP3_0x09000003 , ULL(0x09000003) ); - -CONST_UINT64_T( PCIE_GP0_AND_0x09000004 , ULL(0x09000004) ); -CONST_UINT64_T( PCIE_GP0_OR_0x09000005 , ULL(0x09000005) ); -CONST_UINT64_T( PCIE_GP4_AND_0x09000006 , ULL(0x09000006) ); -CONST_UINT64_T( PCIE_GP4_OR_0x09000007 , ULL(0x09000007) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS SCOM -// ring 1 = trace -// ring 2 = PBF -// ring 5 = IOPCI0 -// ring 6 = IOPCI1 -// ring 7 = IOPCI2 -// ring 8 = PCI0 -// ring 9 = PCI1 -// ring 10 = PCI2 -// ring 11 = PCI3 -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_SCOM_0x09010000 , ULL(0x09010000) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS PB -//------------------------------------------------------------------------------ -CONST_UINT64_T( PB_F_TRACE_0x09010812 , ULL(0x09010812) ); -CONST_UINT64_T( PB_F_FMR_CFG_0x09010813 , ULL(0x09010813) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS TRACE -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_TRACE_STATUS_0x09010004 , ULL(0x09010004) ); -CONST_UINT64_T( PCIE_TRACE_DATA_HI_0x09010400 , ULL(0x09010400) ); -CONST_UINT64_T( PCIE_TRACE_DATA_LO_0x09010401 , ULL(0x09010401) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS PHB -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE0_ETU_RESET_0x0901200A , ULL(0x0901200A) ); -CONST_UINT64_T( PCIE0_ASB_BAR_0x0901200B , ULL(0x0901200B) ); - -CONST_UINT64_T( PCIE1_ETU_RESET_0x0901240A , ULL(0x0901240A) ); -CONST_UINT64_T( PCIE1_ASB_BAR_0x0901240B , ULL(0x0901240B) ); - -CONST_UINT64_T( PCIE2_ETU_RESET_0x0901280A , ULL(0x0901280A) ); -CONST_UINT64_T( PCIE2_ASB_BAR_0x0901280B , ULL(0x0901280B) ); - -CONST_UINT64_T( PCIE3_ETU_RESET_0x09012C0A , ULL(0x09012C0A) ); -CONST_UINT64_T( PCIE3_ASB_BAR_0x09012C0B , ULL(0x09012C0B) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS PB -//------------------------------------------------------------------------------ -CONST_UINT64_T( PB_IOF_MODE_0x09011C0A , ULL(0x09011C0A) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS CLOCK CONTROL -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_OPCG_CNTL0_0x09030002 , ULL(0x09030002) ); -CONST_UINT64_T( PCIE_OPCG_CNTL1_0x09030003 , ULL(0x09030003) ); -CONST_UINT64_T( PCIE_OPCG_CNTL2_0x09030004 , ULL(0x09030004) ); -CONST_UINT64_T( PCIE_OPCG_CNTL3_0x09030005 , ULL(0x09030005) ); -CONST_UINT64_T( PCIE_CLK_REGION_0x09030006 , ULL(0x09030006) ); -CONST_UINT64_T( PCIE_CLK_SCANSEL_0x09030007 , ULL(0x09030007) ); -CONST_UINT64_T( PCIE_CLK_STATUS_0x09030008 , ULL(0x09030008) ); -CONST_UINT64_T( PCIE_CC_ERROR_STATUS_0x09030009 , ULL(0x09030009) ); -CONST_UINT64_T( PCIE_CC_PROTECT_MODE_0x090303FE , ULL(0x090303FE) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS FIR -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_XSTOP_0x09040000 , ULL(0x09040000) ); -CONST_UINT64_T( PCIE_RECOV_0x09040001 , ULL(0x09040001) ); -CONST_UINT64_T( PCIE_FIR_MASK_0x09040002 , ULL(0x09040002) ); -CONST_UINT64_T( PCIE_SPATTN_0x09040004 , ULL(0x09040004) ); -CONST_UINT64_T( PCIE_SPATTN_AND_0x09040005 , ULL(0x09040005) ); -CONST_UINT64_T( PCIE_SPATTN_OR_0x09040006 , ULL(0x09040006) ); -CONST_UINT64_T( PCIE_SPATTN_MASK_0x09040007 , ULL(0x09040007) ); -CONST_UINT64_T( PCIE_FIR_MODE_0x09040008 , ULL(0x09040008) ); -CONST_UINT64_T( PCIE_PERV_LFIR_0x0904000A , ULL(0x0904000A) ); -CONST_UINT64_T( PCIE_PERV_LFIR_AND_0x0904000B , ULL(0x0904000B) ); -CONST_UINT64_T( PCIE_PERV_LFIR_OR_0x0904000C , ULL(0x0904000C) ); -CONST_UINT64_T( PCIE_PERV_LFIR_MASK_0x0904000D , ULL(0x0904000D) ); -CONST_UINT64_T( PCIE_PERV_LFIR_MASK_AND_0x0904000E , ULL(0x0904000E) ); -CONST_UINT64_T( PCIE_PERV_LFIR_MASK_OR_0x0904000F , ULL(0x0904000F) ); -CONST_UINT64_T( PCIE_PERV_LFIR_ACT0_0x09040010 , ULL(0x09040010) ); -CONST_UINT64_T( PCIE_PERV_LFIR_ACT1_0x09040011 , ULL(0x09040011) ); - -CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_0x09010800 , ULL(0x09010800) ); -CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_AND_0x09010801 , ULL(0x09010801) ); -CONST_UINT64_T( ES_PBES_WRAP_TOP_FIR_MASK_0x09010803 , ULL(0x09010803) ); - -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_0x09011400 , ULL(0x09011400) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_AND_0x09011401 , ULL(0x09011401) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_OR_0x09011402 , ULL(0x09011402) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_MASK_0x09011403 , ULL(0x09011403) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_MASK_AND_0x09011404 , ULL(0x09011404) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_MASK_OR_0x09011405 , ULL(0x09011405) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_ACTION0_0x09011406 , ULL(0x09011406) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_ACTION1_0x09011407 , ULL(0x09011407) ); -CONST_UINT64_T( PCIE_IOP0_PLL_FIR_WOF_0x09011408 , ULL(0x09011408) ); - -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_0x09011840 , ULL(0x09011840) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_AND_0x09011841 , ULL(0x09011841) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_OR_0x09011842 , ULL(0x09011842) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_MASK_0x09011843 , ULL(0x09011843) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_MASK_AND_0x09011844 , ULL(0x09011844) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_MASK_OR_0x09011845 , ULL(0x09011845) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_ACTION0_0x09011846 , ULL(0x09011846) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_ACTION1_0x09011847 , ULL(0x09011847) ); -CONST_UINT64_T( PCIE_IOP1_PLL_FIR_WOF_0x09011848 , ULL(0x09011848) ); - -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_0x09011C40 , ULL(0x09011C40) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_AND_0x09011C41 , ULL(0x09011C41) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_OR_0x09011C42 , ULL(0x09011C42) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_MASK_0x09011C43 , ULL(0x09011C43) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_MASK_AND_0x09011C44 , ULL(0x09011C44) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_MASK_OR_0x09011C45 , ULL(0x09011C45) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_ACTION0_0x09011C46 , ULL(0x09011C46) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_ACTION1_0x09011C47 , ULL(0x09011C47) ); -CONST_UINT64_T( PCIE_IOP2_PLL_FIR_WOF_0x09011C48 , ULL(0x09011C48) ); - -//------------------------------------------------------------------------------ -// PLL LOCK -//------------------------------------------------------------------------------ -// PLL lock information -CONST_UINT64_T( PCIE_PLLLOCKREG_0x090F0019 , ULL(0x090F0019) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS THERMAL -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_THERM_0x09050000 , ULL(0x09050000) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS PCB SLAVE -//------------------------------------------------------------------------------ -//Multicast Group Registers -CONST_UINT64_T( PCIE_MCGR1_0x090F0001 , ULL(0x090F0001) ); -CONST_UINT64_T( PCIE_MCGR2_0x090F0002 , ULL(0x090F0002) ); -CONST_UINT64_T( PCIE_MCGR3_0x090F0003 , ULL(0x090F0003) ); -CONST_UINT64_T( PCIE_MCGR4_0x090F0004 , ULL(0x090F0004) ); -//GP3 Register -CONST_UINT64_T( PCIE_GP3_0x090F0012 , ULL(0x090F0012) ); -CONST_UINT64_T( PCIE_GP3_AND_0x090F0013 , ULL(0x090F0013) ); -CONST_UINT64_T( PCIE_GP3_OR_0x090F0014 , ULL(0x090F0014) ); - -//------------------------------------------------------------------------------ -// PCIE-BUS HANG DETECTION -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_HANG_P6_0x090F0026 , ULL(0x090F0026) ); // PCIE : setup hang counter 6 -CONST_UINT64_T( PCIE_HANG_PRE_0x090F0028 , ULL(0x090F0028) ); // PCIE : setup hang precounter (HEX:01) - -//------------------------------------------------------------------------------ -// PCIE-BUS INDIRECT SCOM ADDRESSES (IOP) -//------------------------------------------------------------------------------ -CONST_UINT64_T( PCIE_IOP0_PLL_GLOBAL_CONTROL2_0x8000080A0901143F, ULL(0x8000080A0901143F) ); -CONST_UINT64_T( PCIE_IOP1_PLL_GLOBAL_CONTROL2_0x8000080A0901187F, ULL(0x8000080A0901187F) ); -CONST_UINT64_T( PCIE_IOP2_PLL_GLOBAL_CONTROL2_0x8000080A09011C7F, ULL(0x8000080A09011C7F) ); - - -/******************************************************************************/ -/******************************** EX CHIPLET ********************************/ -/******************************************************************************/ -// Note: ECMD will require the use of these addresses, and it will update them -// under the covers to point to the actual EX chiplet in question. -// -// Example: getscom pu.ex 10000001 -c3 ---> scom address 0x13000001 - -//------------------------------------------------------------------------------ -// EX CHIPLET ID -// use for lpcs P0, <chipletID> -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX00_CHIPLET_0x10000000 , ULL(0x10000000) ); -CONST_UINT64_T( EX01_CHIPLET_0x11000000 , ULL(0x11000000) ); -CONST_UINT64_T( EX02_CHIPLET_0x12000000 , ULL(0x12000000) ); -CONST_UINT64_T( EX03_CHIPLET_0x13000000 , ULL(0x13000000) ); -CONST_UINT64_T( EX04_CHIPLET_0x14000000 , ULL(0x14000000) ); -CONST_UINT64_T( EX05_CHIPLET_0x15000000 , ULL(0x15000000) ); -CONST_UINT64_T( EX06_CHIPLET_0x16000000 , ULL(0x16000000) ); -CONST_UINT64_T( EX07_CHIPLET_0x17000000 , ULL(0x17000000) ); -CONST_UINT64_T( EX08_CHIPLET_0x18000000 , ULL(0x18000000) ); -CONST_UINT64_T( EX09_CHIPLET_0x19000000 , ULL(0x19000000) ); -CONST_UINT64_T( EX10_CHIPLET_0x1A000000 , ULL(0x1A000000) ); -CONST_UINT64_T( EX11_CHIPLET_0x1B000000 , ULL(0x1B000000) ); -CONST_UINT64_T( EX12_CHIPLET_0x1C000000 , ULL(0x1C000000) ); -CONST_UINT64_T( EX13_CHIPLET_0x1D000000 , ULL(0x1D000000) ); -CONST_UINT64_T( EX14_CHIPLET_0x1E000000 , ULL(0x1E000000) ); -CONST_UINT64_T( EX15_CHIPLET_0x1F000000 , ULL(0x1F000000) ); - -//------------------------------------------------------------------------------ -// EX GPIO -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_GP0_0x10000000 , ULL(0x10000000) ); -CONST_UINT64_T( EX_GP0_AND_0x10000004 , ULL(0x10000004) ); -CONST_UINT64_T( EX_GP0_OR_0x10000005 , ULL(0x10000005) ); -CONST_UINT64_T( EX_GP1_0x10000001 , ULL(0x10000001) ); -CONST_UINT64_T( EX_GP2_0x10000002 , ULL(0x10000002) ); - -//------------------------------------------------------------------------------ -// EX SCOM -// ring 1 = ECO trace -// ring 2 = L3 -// ring 3 = NC -// ring 4 = HTM -// ring 8 = L2 trace 0 -// ring 9 = L2 trace 1 -// ring 10 = L2 -// ring 11 = PC trace -// ring 12 = PC -// ring 15 = PC sec -//------------------------------------------------------------------------------ -//L3 -CONST_UINT64_T( EX_L3_FIR_REG_0x10010800 , ULL(0x10010800) ); -CONST_UINT64_T( EX_L3_FIR_AND_REG_0x10010801 , ULL(0x10010801) ); -CONST_UINT64_T( EX_L3_FIR_OR_REG_0x10010802 , ULL(0x10010802) ); -CONST_UINT64_T( EX_L3_FIR_MASK_REG_0x10010803 , ULL(0x10010803) ); -CONST_UINT64_T( EX_L3_FIR_ACTION0_REG_0x10010806 , ULL(0x10010806) ); -CONST_UINT64_T( EX_L3_FIR_ACTION1_REG_0x10010807 , ULL(0x10010807) ); -CONST_UINT64_T( EX_L3_MODE_REG1_0x1001080A , ULL(0x1001080A) ); -CONST_UINT64_T( EX_L3_BAR1_REG_0x1001080B , ULL(0x1001080B) ); -CONST_UINT64_T( EX_L3_PRD_PURGE_REG_0x1001080E , ULL(0x1001080E) ); -CONST_UINT64_T( EX_L3_CERRS_REG0_0x10010810 , ULL(0x10010810) ); -CONST_UINT64_T( EX_L3_BAR2_REG_0x10010813 , ULL(0x10010813) ); -CONST_UINT64_T( EX_L3_PHYP_PURGE_REG_0x10010814 , ULL(0x10010814) ); -CONST_UINT64_T( EX_L3_BAR_GROUP_MASK_REG_0x10010816 , ULL(0x10010816) ); -CONST_UINT64_T( EX_L3_CERRS_REG1_0x10010817 , ULL(0x10010817) ); -CONST_UINT64_T( EX_L3_CERRS_RD_EPS_REG_0x10010829 , ULL(0x10010829) );//p8_xip_customize -CONST_UINT64_T( EX_L3_CERRS_WR_EPS_REG_0x1001082A , ULL(0x1001082A) );//p8_xip_customize -CONST_UINT64_T( EX_L3_MODE_REG0_0x1001082B , ULL(0x1001082B) ); -CONST_UINT64_T( EX_L3_RD_EPSILON_CFG_REG_0x10010829 , ULL(0x10010829) );//?? -CONST_UINT64_T( EX_L3_WR_EPSILON_CFG_REG_0x1001082A , ULL(0x1001082A) );//?? -CONST_UINT64_T( EX_L3_HA_DIRTY_ADDR_WR_PTR_0x10010832 , ULL(0x10010832) ); - -//NCU -CONST_UINT64_T( EX_NCU_FIR_REG_0x10010C00 , ULL(0x10010C00) ); -CONST_UINT64_T( EX_NCU_FIR_AND_REG_0x10010C01 , ULL(0x10010C01) ); -CONST_UINT64_T( EX_NCU_FIR_OR_REG_0x10010C02 , ULL(0x10010C02) ); -CONST_UINT64_T( EX_NCU_FIR_MASK_REG_0x10010C03 , ULL(0x10010C03) ); -CONST_UINT64_T( EX_NCU_FIR_ACTION0_REG_0x10010C06 , ULL(0x10010C06) ); -CONST_UINT64_T( EX_NCU_FIR_ACTION1_REG_0x10010C07 , ULL(0x10010C07) ); -CONST_UINT64_T( EX_NCU_MODE_REG_0x10010C0A , ULL(0x10010C0A) ); - -//CHTM, IMA -CONST_UINT64_T( EX_CHTM_MODE_REG_0x10011000 , ULL(0x10011000) ); -CONST_UINT64_T( EX_CHTM_IMA_PDBAR_REG_0x1001100B , ULL(0x1001100B) ); -CONST_UINT64_T( EX_IMA_EVENT_MASK_0x100132CF , ULL(0x100132CF) ); - -//L2 -CONST_UINT64_T( EX_L2_FIR_REG_0x10012800 , ULL(0x10012800) ); -CONST_UINT64_T( EX_L2_FIR_AND_REG_0x10012801 , ULL(0x10012801) ); -CONST_UINT64_T( EX_L2_FIR_OR_REG_0x10012802 , ULL(0x10012802) ); -CONST_UINT64_T( EX_L2_FIR_MASK_REG_0x10012803 , ULL(0x10012803) ); -CONST_UINT64_T( EX_L2_FIR_ACTION0_REG_0x10012806 , ULL(0x10012806) ); -CONST_UINT64_T( EX_L2_FIR_ACTION1_REG_0x10012807 , ULL(0x10012807) ); -CONST_UINT64_T( EX_L2_CERRS_RD_EPS_REG_0x10012814 , ULL(0x10012814) ); -CONST_UINT64_T( EX_L2_CERRS_REG0_0x10012815 , ULL(0x10012815) ); -CONST_UINT64_T( EX_L2_CERRS_REG1_0x10012816 , ULL(0x10012816) ); -CONST_UINT64_T( EX_L2_MODE_REG0_0x1001280A , ULL(0x1001280A) ); -CONST_UINT64_T( EX_L2_PURGE_CMD_PRD_0x1001280E , ULL(0x1001280E) ); -CONST_UINT64_T( EX_L2_PURGE_CMD_PHYP_0x1001280F , ULL(0x1001280F) ); - - -//------------------------------------------------------------------------------ -// EX/CORE TRACE -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_TRACE_STATUS_0x10010004 , ULL(0x10010004) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_ECO_0x10010400 , ULL(0x10010400) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_ECO_0x10010401 , ULL(0x10010401) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T0_0x10012000 , ULL(0x10012000) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_L2_T0_0x10012001 , ULL(0x10012001) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_L2_T1_0x10012400 , ULL(0x10012400) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_L2_T1_0x10012401 , ULL(0x10012401) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T0_0x10012C00 , ULL(0x10012C00) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T0_0x10012C01 , ULL(0x10012C01) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T1_0x10012C40 , ULL(0x10012C40) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T1_0x10012C41 , ULL(0x10012C41) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T2_0x10012C80 , ULL(0x10012C80) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T2_0x10012C81 , ULL(0x10012C81) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T3_0x10012CC0 , ULL(0x10012CC0) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T3_0x10012CC1 , ULL(0x10012CC1) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T4_0x10012D00 , ULL(0x10012D00) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T4_0x10012D01 , ULL(0x10012D01) ); -CONST_UINT64_T( EX_TRACE_DATA_HI_CORE_T5_0x10012D40 , ULL(0x10012D40) ); -CONST_UINT64_T( EX_TRACE_DATA_LO_CORE_T5_0x10012D41 , ULL(0x10012D41) ); -CONST_UINT64_T( EX_CORE_DIRECT_DEBUG_CTL_0x100132AF , ULL(0x100132AF) ); - -//------------------------------------------------------------------------------ -// EX/CORE PERVASIVE THREAD CONTROLS -// (chiplet/core set by P0 register) -//------------------------------------------------------------------------------ -// TCTL Direct Controls (for each thread) -CONST_UINT64_T( EX_PERV_TCTL0_DIRECT_0x10013000 , ULL(0x10013000) ); -CONST_UINT64_T( EX_PERV_TCTL1_DIRECT_0x10013010 , ULL(0x10013010) ); -CONST_UINT64_T( EX_PERV_TCTL2_DIRECT_0x10013020 , ULL(0x10013020) ); -CONST_UINT64_T( EX_PERV_TCTL3_DIRECT_0x10013030 , ULL(0x10013030) ); -CONST_UINT64_T( EX_PERV_TCTL4_DIRECT_0x10013040 , ULL(0x10013040) ); -CONST_UINT64_T( EX_PERV_TCTL5_DIRECT_0x10013050 , ULL(0x10013050) ); -CONST_UINT64_T( EX_PERV_TCTL6_DIRECT_0x10013060 , ULL(0x10013060) ); -CONST_UINT64_T( EX_PERV_TCTL7_DIRECT_0x10013070 , ULL(0x10013070) ); - -// TCTL RAS Mode (for each thread) -CONST_UINT64_T( EX_PERV_TCTL0_R_MODE_0x10013001 , ULL(0x10013001) ); -CONST_UINT64_T( EX_PERV_TCTL1_R_MODE_0x10013011 , ULL(0x10013011) ); -CONST_UINT64_T( EX_PERV_TCTL2_R_MODE_0x10013021 , ULL(0x10013021) ); -CONST_UINT64_T( EX_PERV_TCTL3_R_MODE_0x10013031 , ULL(0x10013031) ); -CONST_UINT64_T( EX_PERV_TCTL4_R_MODE_0x10013041 , ULL(0x10013041) ); -CONST_UINT64_T( EX_PERV_TCTL5_R_MODE_0x10013051 , ULL(0x10013051) ); -CONST_UINT64_T( EX_PERV_TCTL6_R_MODE_0x10013061 , ULL(0x10013061) ); -CONST_UINT64_T( EX_PERV_TCTL7_R_MODE_0x10013071 , ULL(0x10013071) ); - -// TCTL RAS Status (for each thread) -CONST_UINT64_T( EX_PERV_TCTL0_R_STAT_0x10013002 , ULL(0x10013002) ); -CONST_UINT64_T( EX_PERV_TCTL1_R_STAT_0x10013012 , ULL(0x10013012) ); -CONST_UINT64_T( EX_PERV_TCTL2_R_STAT_0x10013022 , ULL(0x10013022) ); -CONST_UINT64_T( EX_PERV_TCTL3_R_STAT_0x10013032 , ULL(0x10013032) ); -CONST_UINT64_T( EX_PERV_TCTL4_R_STAT_0x10013042 , ULL(0x10013042) ); -CONST_UINT64_T( EX_PERV_TCTL5_R_STAT_0x10013052 , ULL(0x10013052) ); -CONST_UINT64_T( EX_PERV_TCTL6_R_STAT_0x10013062 , ULL(0x10013062) ); -CONST_UINT64_T( EX_PERV_TCTL7_R_STAT_0x10013072 , ULL(0x10013072) ); - -// TCTL POW Status (for each thread) -CONST_UINT64_T( EX_PERV_TCTL0_POW_STAT_0x10013004 , ULL(0x10013004) ); -CONST_UINT64_T( EX_PERV_TCTL1_POW_STAT_0x10013014 , ULL(0x10013014) ); -CONST_UINT64_T( EX_PERV_TCTL2_POW_STAT_0x10013024 , ULL(0x10013024) ); -CONST_UINT64_T( EX_PERV_TCTL3_POW_STAT_0x10013034 , ULL(0x10013034) ); -CONST_UINT64_T( EX_PERV_TCTL4_POW_STAT_0x10013044 , ULL(0x10013044) ); -CONST_UINT64_T( EX_PERV_TCTL5_POW_STAT_0x10013054 , ULL(0x10013054) ); -CONST_UINT64_T( EX_PERV_TCTL6_POW_STAT_0x10013064 , ULL(0x10013064) ); -CONST_UINT64_T( EX_PERV_TCTL7_POW_STAT_0x10013074 , ULL(0x10013074) ); - -// TCL Spattn Status (for each thread) -CONST_UINT64_T( EX_PERV_TCTL0_SPATTN_0x10013007 , ULL(0x10013007) ); -CONST_UINT64_T( EX_PERV_TCTL1_SPATTN_0x10013017 , ULL(0x10013017) ); -CONST_UINT64_T( EX_PERV_TCTL2_SPATTN_0x10013027 , ULL(0x10013027) ); -CONST_UINT64_T( EX_PERV_TCTL3_SPATTN_0x10013037 , ULL(0x10013037) ); -CONST_UINT64_T( EX_PERV_TCTL4_SPATTN_0x10013047 , ULL(0x10013047) ); -CONST_UINT64_T( EX_PERV_TCTL5_SPATTN_0x10013057 , ULL(0x10013057) ); -CONST_UINT64_T( EX_PERV_TCTL6_SPATTN_0x10013067 , ULL(0x10013067) ); -CONST_UINT64_T( EX_PERV_TCTL7_SPATTN_0x10013077 , ULL(0x10013077) ); - -CONST_UINT64_T( EX_PCNE_REG0_HOLD_OUT_0x1001300D , ULL(0x1001300D) ); -CONST_UINT64_T( EX_PCNE_REG1_HOLD_OUT_0x1001301D , ULL(0x1001301D) ); -CONST_UINT64_T( EX_PCNE_REG2_HOLD_OUT_0x1001302D , ULL(0x1001302D) ); -CONST_UINT64_T( EX_PCNE_REG3_HOLD_OUT_0x1001303D , ULL(0x1001303D) ); -CONST_UINT64_T( EX_PCNE_REG4_HOLD_OUT_0x1001304D , ULL(0x1001304D) ); -CONST_UINT64_T( EX_PCNE_REG5_HOLD_OUT_0x1001305D , ULL(0x1001305D) ); -CONST_UINT64_T( EX_PCNE_REG6_HOLD_OUT_0x1001306D , ULL(0x1001306D) ); -CONST_UINT64_T( EX_PCNE_REG7_HOLD_OUT_0x1001307D , ULL(0x1001307D) ); - -// Thread Active Status -CONST_UINT64_T( EX_PERV_THREAD_ACTIVE_0x1001310E , ULL(0x1001310E) ); - -// RAM Registers -CONST_UINT64_T( EX_PERV_RAM_MODE_0x10013C00 , ULL(0x10013C00) ); -CONST_UINT64_T( EX_PERV_RAM_CTRL_0x10013C01 , ULL(0x10013C01) ); -CONST_UINT64_T( EX_PERV_RAM_STAT_0x10013C02 , ULL(0x10013C02) ); - -// SPRC/SPRD/Scratch -CONST_UINT64_T( EX_PERV_L0_SCOM_SPRC_10013280 , ULL(0x10013280) ); -CONST_UINT64_T( EX_PERV_SPR_MODE_10013281 , ULL(0x10013281) ); -CONST_UINT64_T( EX_PERV_SCRATCH0_10013283 , ULL(0x10013283) ); -CONST_UINT64_T( EX_PERV_SCRATCH1_10013284 , ULL(0x10013284) ); -CONST_UINT64_T( EX_PERV_SCRATCH2_10013285 , ULL(0x10013285) ); -CONST_UINT64_T( EX_PERV_SCRATCH3_10013286 , ULL(0x10013286) ); -CONST_UINT64_T( EX_PERV_SCRATCH4_10013287 , ULL(0x10013287) ); -CONST_UINT64_T( EX_PERV_SCRATCH5_10013288 , ULL(0x10013288) ); -CONST_UINT64_T( EX_PERV_SCRATCH6_10013289 , ULL(0x10013289) ); -CONST_UINT64_T( EX_PERV_SCRATCH7_1001328A , ULL(0x1001328A) ); -CONST_UINT64_T( EX_PERV_SPRD_L0_100132A3 , ULL(0x100132A3) ); -CONST_UINT64_T( EX_PERV_SPRD_L1_100132A4 , ULL(0x100132A4) ); -CONST_UINT64_T( EX_PERV_SPRD_L2_100132A5 , ULL(0x100132A5) ); -CONST_UINT64_T( EX_PERV_SPRD_L3_100132A6 , ULL(0x100132A6) ); - -// SPURR regs -CONST_UINT64_T( EX_PERV_SPURR_FREQ_SCALE_0x1001329F , ULL(0x1001329F) ); -CONST_UINT64_T( EX_PERV_SPURR_FREQ_REF_0x100132A0 , ULL(0x100132A0) ); - -// Performance Throttle Mode -CONST_UINT64_T( EX_PERV_PFTH_THROT_0x100132AD , ULL(0x100132AD) ); - - -//------------------------------------------------------------------------------ -// EX OHA -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_SCOM_0x10020000 , ULL(0x10020000) ); -CONST_UINT64_T( EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , ULL(0x10020000) ); -CONST_UINT64_T( EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , ULL(0x10020003) ); -CONST_UINT64_T( EX_OHA_PROXY_REG_0x10020006 , ULL(0x10020006) ); -CONST_UINT64_T( EX_OHA_PROXY_LEGACY_REG_0x10020007 , ULL(0x10020007) ); -CONST_UINT64_T( EX_OHA_SKITTER_CTRL_MODE_REG_0x10020008 , ULL(0x10020008) ); -CONST_UINT64_T( EX_OHA_CPM_CTRL_REG_0x1002000A , ULL(0x1002000A) ); -CONST_UINT64_T( EX_OHA_RO_STATUS_REG_0x1002000B , ULL(0x1002000B) ); -CONST_UINT64_T( EX_OHA_MODE_REG_RWx1002000D , ULL(0x1002000D) ); -CONST_UINT64_T( EX_OHA_ERROR_ERROR_MASK_REG_RWx1002000E , ULL(0x1002000E) ); -CONST_UINT64_T( EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , ULL(0x10020011) ); -CONST_UINT64_T( EX_OHA_AISS_IO_REG_0x10020014 , ULL(0x10020014) ); - -//------------------------------------------------------------------------------ -// EX CLOCK CONTROL -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_SYNC_CONFIG_0x10030000 , ULL(0x10030000) ); -CONST_UINT64_T( EX_OPCG_CNTL0_0x10030002 , ULL(0x10030002) ); -CONST_UINT64_T( EX_OPCG_CNTL1_0x10030003 , ULL(0x10030003) ); -CONST_UINT64_T( EX_OPCG_CNTL2_0x10030004 , ULL(0x10030004) ); -CONST_UINT64_T( EX_OPCG_CNTL3_0x10030005 , ULL(0x10030005) ); -CONST_UINT64_T( EX_CLK_REGION_0x10030006 , ULL(0x10030006) ); -CONST_UINT64_T( EX_CLK_SCANSEL_0x10030007 , ULL(0x10030007) ); -CONST_UINT64_T( EX_CLK_STATUS_0x10030008 , ULL(0x10030008) ); -CONST_UINT64_T( EX_CC_ERROR_STATUS_0x10030009 , ULL(0x10030009) ); -CONST_UINT64_T( EX_CC_PROTECT_MODE_0x100303FE , ULL(0x100303FE) ); - -//------------------------------------------------------------------------------ -// EX FIR -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_CORE_FIR_0x10013100 , ULL(0x10013100) ); -CONST_UINT64_T( EX_CORE_FIR_AND_0x10013101 , ULL(0x10013101) ); -CONST_UINT64_T( EX_CORE_FIR_OR_0x10013102 , ULL(0x10013102) ); -CONST_UINT64_T( EX_CORE_FIR_MASK_0x10013103 , ULL(0x10013103) ); -CONST_UINT64_T( EX_CORE_FIR_MASK_AND_0x10013104 , ULL(0x10013104) ); -CONST_UINT64_T( EX_CORE_FIR_MASK_OR_0x10013105 , ULL(0x10013105) ); -CONST_UINT64_T( EX_CORE_FIR_ACTION0_0x10013106 , ULL(0x10013106) ); -CONST_UINT64_T( EX_CORE_FIR_ACTION1_0x10013107 , ULL(0x10013107) ); -CONST_UINT64_T( EX_CORE_FIR_WOF_0x10013108 , ULL(0x10013108) ); -CONST_UINT64_T( EX_XSTOP_0x10040000 , ULL(0x10040000) ); -CONST_UINT64_T( EX_RECOV_0x10040001 , ULL(0x10040001) ); -CONST_UINT64_T( EX_FIR_MASK_0x10040002 , ULL(0x10040002) ); -CONST_UINT64_T( EX_SPATTN_0x10040004 , ULL(0x10040004) ); -CONST_UINT64_T( EX_SPATTN_AND_0x10040005 , ULL(0x10040005) ); -CONST_UINT64_T( EX_SPATTN_OR_0x10040006 , ULL(0x10040006) ); -CONST_UINT64_T( EX_SPATTN_MASK_0x10040007 , ULL(0x10040007) ); -CONST_UINT64_T( EX_FIR_MODE_0x10040008 , ULL(0x10040008) ); -CONST_UINT64_T( EX_PERV_LFIR_0x1004000A , ULL(0x1004000A) ); -CONST_UINT64_T( EX_PERV_LFIR_AND_0x1004000B , ULL(0x1004000B) ); -CONST_UINT64_T( EX_PERV_LFIR_OR_0x1004000C , ULL(0x1004000C) ); -CONST_UINT64_T( EX_PERV_LFIR_MASK_0x1004000D , ULL(0x1004000D) ); -CONST_UINT64_T( EX_PERV_LFIR_MASK_AND_0x1004000E , ULL(0x1004000E) ); -CONST_UINT64_T( EX_PERV_LFIR_MASK_OR_0x1004000F , ULL(0x1004000F) ); -CONST_UINT64_T( EX_PERV_LFIR_ACT0_0x10040010 , ULL(0x10040010) ); -CONST_UINT64_T( EX_PERV_LFIR_ACT1_0x10040011 , ULL(0x10040011) ); - -//------------------------------------------------------------------------------ -// EX THERMAL -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_THERM_0x10050000 , ULL(0x10050000) ); -CONST_UINT64_T( EX_THERM_DTS_RESULT0_0x10050000 , ULL(0x10050000) ); -CONST_UINT64_T( EX_THERM_DTS_RESULT1_0x10050001 , ULL(0x10050001) ); -CONST_UINT64_T( EX_THERM_MODE_REG_0x1005000F , ULL(0x1005000F) ); -CONST_UINT64_T( EX_THERM_CONTROL_REG_0x10050012 , ULL(0x10050012) ); -CONST_UINT64_T( EX_THERM_ERR_STATUS_REG_0x10050013 , ULL(0x10050013) ); -CONST_UINT64_T( EX_CPM_CONFIG_WRITE_REG0_0x10050000 , ULL(0x10050000) ); -CONST_UINT64_T( EX_CPM_CONFIG_WRITE_REG1_0x10050001 , ULL(0x10050001) ); -CONST_UINT64_T( EX_CPM_RAW_RESULT0_10050005 , ULL(0x10050005) ); -CONST_UINT64_T( EX_CPM_RAW_RESULT1_10050006 , ULL(0x10050006) ); -CONST_UINT64_T( EX_CPM_ENCODED_RESULT0_10050008 , ULL(0x10050008) ); -CONST_UINT64_T( EX_CPM_ENCODED_RESULT1_10050009 , ULL(0x10050009) ); - -//------------------------------------------------------------------------------ -// EX Security -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_TRUSTED_BOOT_EN_0x10013C03 , ULL(0x10013C03) ); - -//------------------------------------------------------------------------------ -// EX PCB SLAVE -//------------------------------------------------------------------------------ -//Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used -// special wakeup registers -CONST_UINT64_T( PM_SPECIAL_WKUP_FSP_0x100F010B , ULL(0x100F010B) ); -CONST_UINT64_T( PM_SPECIAL_WKUP_OCC_0x100F010C , ULL(0x100F010C) ); -CONST_UINT64_T( PM_SPECIAL_WKUP_PHYP_0x100F010D , ULL(0x100F010D) ); - -//Multicast Group Registers -CONST_UINT64_T( EX_MCGR1_0x100F0001 , ULL(0x100F0001) ); -CONST_UINT64_T( EX_MCGR2_0x100F0002 , ULL(0x100F0002) ); -CONST_UINT64_T( EX_MCGR3_0x100F0003 , ULL(0x100F0003) ); -CONST_UINT64_T( EX_MCGR4_0x100F0004 , ULL(0x100F0004) ); - -//GP3 Register -CONST_UINT64_T( EX_GP3_0x100F0012 , ULL(0x100F0012) ); -CONST_UINT64_T( EX_GP3_AND_0x100F0013 , ULL(0x100F0013) ); -CONST_UINT64_T( EX_GP3_OR_0x100F0014 , ULL(0x100F0014) ); - -CONST_UINT64_T( EX_CLK_ADJ_SET_0x100F0016 , ULL(0x100F0016) ); - -//Slave Configuration Register -CONST_UINT64_T( EX_SLAVE_CONFIG_0x100F001E , ULL(0x100F001E) ); - -//Hang counter registers -CONST_UINT64_T( EX_HANG_P0_0x100F0020 , ULL(0x100F0020) ); -CONST_UINT64_T( EX_HANG_P1_0x100F0021 , ULL(0x100F0021) ); -CONST_UINT64_T( EX_HANG_P2_0x100F0022 , ULL(0x100F0022) ); -CONST_UINT64_T( EX_HANG_P3_0x100F0023 , ULL(0x100F0023) ); -CONST_UINT64_T( EX_HANG_P4_0x100F0024 , ULL(0x100F0024) ); -CONST_UINT64_T( EX_HANG_P5_0x100F0025 , ULL(0x100F0025) ); -CONST_UINT64_T( EX_HANG_P6_0x100F0026 , ULL(0x100F0026) ); -CONST_UINT64_T( EX_HANG_PRE_0x100F0028 , ULL(0x100F0028) ); - -//PCB Error Capture -CONST_UINT64_T( EX_PCBS_ATTN_REG_0x100F001A , ULL(0x100F001A) ); -CONST_UINT64_T( EX_PCBS_RECOV_REG_0x100F001B , ULL(0x100F001B) ); -CONST_UINT64_T( EX_PCBS_XSTOP_REG_0x100F001C , ULL(0x100F001C) ); -CONST_UINT64_T( EX_PCBS_SLAVE_CONFIG_REG_0x100F001E , ULL(0x100F001E) ); -CONST_UINT64_T( EX_PCBS_ERROR_REG_0x100F001F , ULL(0x100F001F) ); - -// Atomic Lock -CONST_UINT64_T( EX_ATOMIC_LOCK_0x100F03FF , ULL(0x100F03FF) ); - -//Chiplet specific names (probably won't ever be used) -CONST_UINT64_T( EX00_GP3_0x100F0012 , ULL(0x100F0012) ); -CONST_UINT64_T( EX00_GP3_AND_0x100F0013 , ULL(0x100F0013) ); -CONST_UINT64_T( EX00_GP3_OR_0x100F0014 , ULL(0x100F0014) ); - -CONST_UINT64_T( EX01_GP3_0x110F0012 , ULL(0x110F0012) ); -CONST_UINT64_T( EX01_GP3_AND_0x110F0013 , ULL(0x110F0013) ); -CONST_UINT64_T( EX01_GP3_OR_0x110F0014 , ULL(0x110F0014) ); - -CONST_UINT64_T( EX02_GP3_0x120F0012 , ULL(0x120F0012) ); -CONST_UINT64_T( EX02_GP3_AND_0x120F0013 , ULL(0x120F0013) ); -CONST_UINT64_T( EX02_GP3_OR_0x120F0014 , ULL(0x120F0014) ); - -CONST_UINT64_T( EX03_GP3_0x130F0012 , ULL(0x130F0012) ); -CONST_UINT64_T( EX03_GP3_AND_0x130F0013 , ULL(0x130F0013) ); -CONST_UINT64_T( EX03_GP3_OR_0x130F0014 , ULL(0x130F0014) ); - -CONST_UINT64_T( EX04_GP3_0x140F0012 , ULL(0x140F0012) ); -CONST_UINT64_T( EX04_GP3_AND_0x140F0013 , ULL(0x140F0013) ); -CONST_UINT64_T( EX04_GP3_OR_0x140F0014 , ULL(0x140F0014) ); - -CONST_UINT64_T( EX05_GP3_0x150F0012 , ULL(0x150F0012) ); -CONST_UINT64_T( EX05_GP3_AND_0x150F0013 , ULL(0x150F0013) ); -CONST_UINT64_T( EX05_GP3_OR_0x150F0014 , ULL(0x150F0014) ); - -CONST_UINT64_T( EX06_GP3_0x160F0012 , ULL(0x160F0012) ); -CONST_UINT64_T( EX06_GP3_AND_0x160F0013 , ULL(0x160F0013) ); -CONST_UINT64_T( EX06_GP3_OR_0x160F0014 , ULL(0x160F0014) ); - -CONST_UINT64_T( EX07_GP3_0x170F0012 , ULL(0x170F0012) ); -CONST_UINT64_T( EX07_GP3_AND_0x170F0013 , ULL(0x170F0013) ); -CONST_UINT64_T( EX07_GP3_OR_0x170F0014 , ULL(0x170F0014) ); - -CONST_UINT64_T( EX08_GP3_0x180F0012 , ULL(0x180F0012) ); -CONST_UINT64_T( EX08_GP3_AND_0x180F0013 , ULL(0x180F0013) ); -CONST_UINT64_T( EX08_GP3_OR_0x180F0014 , ULL(0x180F0014) ); - -CONST_UINT64_T( EX09_GP3_0x190F0012 , ULL(0x190F0012) ); -CONST_UINT64_T( EX09_GP3_AND_0x190F0013 , ULL(0x190F0013) ); -CONST_UINT64_T( EX09_GP3_OR_0x190F0014 , ULL(0x190F0014) ); - -CONST_UINT64_T( EX10_GP3_0x1A0F0012 , ULL(0x1A0F0012) ); -CONST_UINT64_T( EX10_GP3_AND_0x1A0F0013 , ULL(0x1A0F0013) ); -CONST_UINT64_T( EX10_GP3_OR_0x1A0F0014 , ULL(0x1A0F0014) ); - -CONST_UINT64_T( EX11_GP3_0x1B0F0012 , ULL(0x1B0F0012) ); -CONST_UINT64_T( EX11_GP3_AND_0x1B0F0013 , ULL(0x1B0F0013) ); -CONST_UINT64_T( EX11_GP3_OR_0x1B0F0014 , ULL(0x1B0F0014) ); - -CONST_UINT64_T( EX12_GP3_0x1C0F0012 , ULL(0x1C0F0012) ); -CONST_UINT64_T( EX12_GP3_AND_0x1C0F0013 , ULL(0x1C0F0013) ); -CONST_UINT64_T( EX12_GP3_OR_0x1C0F0014 , ULL(0x1C0F0014) ); - -CONST_UINT64_T( EX13_GP3_0x1D0F0012 , ULL(0x1D0F0012) ); -CONST_UINT64_T( EX13_GP3_AND_0x1D0F0013 , ULL(0x1D0F0013) ); -CONST_UINT64_T( EX13_GP3_OR_0x1D0F0014 , ULL(0x1D0F0014) ); - -CONST_UINT64_T( EX14_GP3_0x1E0F0012 , ULL(0x1E0F0012) ); -CONST_UINT64_T( EX14_GP3_AND_0x1E0F0013 , ULL(0x1E0F0013) ); -CONST_UINT64_T( EX14_GP3_OR_0x1E0F0014 , ULL(0x1E0F0014) ); - -CONST_UINT64_T( EX15_GP3_0x1F0F0012 , ULL(0x1F0F0012) ); -CONST_UINT64_T( EX15_GP3_AND_0x1F0F0013 , ULL(0x1F0F0013) ); -CONST_UINT64_T( EX15_GP3_OR_0x1F0F0014 , ULL(0x1F0F0014) ); - -//------------------------------------------------------------------------------ -// EX PCB SLAVE PM -//------------------------------------------------------------------------------ -//Generic names (need to add in (cuTarget.chipUnitNum * 0x01000000)) when being used - -//PMGP0 Register -CONST_UINT64_T( EX_PMGP0_0x100F0100 , ULL(0x100F0100) ); -CONST_UINT64_T( EX_PMGP0_AND_0x100F0101 , ULL(0x100F0101) ); -CONST_UINT64_T( EX_PMGP0_OR_0x100F0102 , ULL(0x100F0102) ); -//PMGP1 Register -CONST_UINT64_T( EX_PMGP1_0x100F0103 , ULL(0x100F0103) ); -CONST_UINT64_T( EX_PMGP1_AND_0x100F0104 , ULL(0x100F0104) ); -CONST_UINT64_T( EX_PMGP1_OR_0x100F0105 , ULL(0x100F0105) ); - -CONST_UINT64_T( EX_PFET_CTL_REG_0x100F0106 , ULL(0x100F0106) ); -CONST_UINT64_T( EX_PFET_STAT_REG_0x100F0107 , ULL(0x100F0107) ); -CONST_UINT64_T( EX_PFET_CTL_REG_0x100F010E , ULL(0x100F010E) ); - - -CONST_UINT64_T( EX_IDLEGOTO_0x100F0114 , ULL(0x100F0114) ); -CONST_UINT64_T( EX_FREQCNTL_0x100F0151 , ULL(0x100F0151) ); -CONST_UINT64_T( EX_PMGP1_REG_0_RWXx100F0103 , ULL(0x100F0103) ); -CONST_UINT64_T( EX_PMGP1_REG_0_WANDx100F0104 , ULL(0x100F0104) ); -CONST_UINT64_T( EX_PMGP1_REG_0_WORx100F0105 , ULL(0x100F0105) ); -CONST_UINT64_T( EX_PFVddCntlStat_REG_0x100F0106 , ULL(0x100F0106) ); -CONST_UINT64_T( EX_PFVcsCntlStat_REG_0x100F010E , ULL(0x100F010E) ); -CONST_UINT64_T( EX_PMErr_REG_0x100F0109 , ULL(0x100F0109) ); -CONST_UINT64_T( EX_PMErrMask_REG_0x100F010A , ULL(0x100F010A) ); -CONST_UINT64_T( EX_PMSpcWkupFSP_REG_0x100F010B , ULL(0x100F010B) ); -CONST_UINT64_T( EX_PMSpcWkupOCC_REG_0x100F010C , ULL(0x100F010C) ); -CONST_UINT64_T( EX_PMSpcWkupPHYP_REG_0x100F010D , ULL(0x100F010D) ); -CONST_UINT64_T( EX_PMSTATEHISTPHYP_REG_0x100F0110 , ULL(0x100F0110) ); -CONST_UINT64_T( EX_PMSTATEHISTFSP_REG_0x100F0111 , ULL(0x100F0111) ); -CONST_UINT64_T( EX_PMSTATEHISTOCC_REG_0x100F0112 , ULL(0x100F0112) ); -CONST_UINT64_T( EX_PMSTATEHISTPERF_REG_0x100F0113 , ULL(0x100F0113) ); -CONST_UINT64_T( EX_IdleFSMGotoCmd_REG_0x100F0114 , ULL(0x100F0114) ); -CONST_UINT64_T( EX_CorePFPUDly_REG_0x100F012C , ULL(0x100F012C) ); -CONST_UINT64_T( EX_CorePFPDDly_REG_0x100F012D , ULL(0x100F012D) ); -CONST_UINT64_T( EX_CorePFVRET_REG_0x100F0130 , ULL(0x100F0130) ); -CONST_UINT64_T( EX_ECOPFPUDly_REG_0x100F014C , ULL(0x100F014C) ); -CONST_UINT64_T( EX_ECOPFPDDly_REG_0x100F014D , ULL(0x100F014D) ); -CONST_UINT64_T( EX_ECOPFVRET_REG_0x100F0150 , ULL(0x100F0150) ); -CONST_UINT64_T( EX_DPLL_CPM_PARM_REG_0x100F0152 , ULL(0x100F0152) ); -CONST_UINT64_T( EX_PCBS_POWER_MANAGEMENT_STATUS_REG_0x100F0153 , ULL(0x100F0153) ); //ROX -CONST_UINT64_T( EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 , ULL(0x100F0154) ); -CONST_UINT64_T( EX_PCBS_iVRM_Value_Setting_Reg_0x100F0155 , ULL(0x100F0155) ); -CONST_UINT64_T( EX_PCBSPM_MODE_REG_0x100F0156 , ULL(0x100F0156) ); -CONST_UINT64_T( EX_PCBS_iVRM_PFETSTR_Sense_Reg_0x100F0157 , ULL(0x100F0157) ); -CONST_UINT64_T( EX_PCBS_Power_Management_Idle_Control_Reg_0x100F0158 , ULL(0x100F0158) ); -CONST_UINT64_T( EX_PCBS_Power_Management_Control_Reg_0x100F0159 , ULL(0x100F0159) ); -CONST_UINT64_T( EX_PCBS_PMC_VF_CTRL_REG_0x100F015A , ULL(0x100F015A) ); -CONST_UINT64_T( EX_PCBS_UNDERVOLTING_REG_0x100F015B , ULL(0x100F015B) ); -CONST_UINT64_T( EX_PCBS_Pstate_Index_Bound_Reg_0x100F015C , ULL(0x100F015C) ); -CONST_UINT64_T( EX_PCBS_Power_Management_Bounds_Reg_0x100F015D , ULL(0x100F015D) ); -CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E , ULL(0x100F015E) ); -CONST_UINT64_T( EX_PCBS_PSTATE_TABLE_REG_0x100F015F , ULL(0x100F015F) ); -CONST_UINT64_T( EX_PCBS_Pstate_Step_Target_Register_0x100F0160 , ULL(0x100F0160) ); -CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg0_0x100F0162 , ULL(0x100F0162) ); -CONST_UINT64_T( EX_PCBS_DPLL_STATUS_REG_100F0161 , ULL(0x100F0161) ); -CONST_UINT64_T( EX_PCBS_iVRM_VID_Control_Reg1_0x100F0163 , ULL(0x100F0163) ); -CONST_UINT64_T( EX_PCBS_OCC_Heartbeat_Reg_0x100F0164 , ULL(0x100F0164) ); -CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg0_0x100F0165 , ULL(0x100F0165) ); -CONST_UINT64_T( EX_PCBS_Resonant_Clock_Control_Reg1_0x100F0166 , ULL(0x100F0166) ); -CONST_UINT64_T( EX_PCBS_Resonant_Clock_Status_Reg_0x100F0167 , ULL(0x100F0167) ); -CONST_UINT64_T( EX_PCBS_Local_Pstate_Frequency_Target_Control_Register_0x100F0168 , ULL(0x100F0168) ); -CONST_UINT64_T( EX_PCBS_FSM_MONITOR1_REG_0x100F0170 , ULL(0x100F0170) ); -CONST_UINT64_T( EX_PCBS_FSM_MONITOR2_REG_0x100F0171 , ULL(0x100F0171) ); - -//------------------------------------------------------------------------------ -// MULTICAST REGISTER DEFINITION -//------------------------------------------------------------------------------ -CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_RWx690F0103 , ULL(0x690F0103) ); // PM GP1 Multicast Group1 -CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WANDx690F0104 , ULL(0x690F0104) ); // PM GP1 Multicast Group1 -CONST_UINT64_T( EX_WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105 , ULL(0x690F0105) ); // PM GP1 Multicast Group1 -CONST_UINT64_T( EX_WRITE_ALL_PCBSPM_MODE_REG_0x690F0156 , ULL(0x690F0156) ); // PCBSLV Mode Multicast Group1 -CONST_UINT64_T( EX_WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D , ULL(0x690F015D) ); // PCBSLV PM Bounds Multicast Group1 - -CONST_UINT64_T( EX_PARTIAL_GOOD_0x520F0012 , ULL(0x520F0012) ); // EX GP3 bit 0s - - -//******************************************************************************/ -//********* ADDRESS PREFIXES FOR SUBROUTINE SCAN0_MODULE CALLS ****************/ -//******************************************************************************/ -CONST_UINT8_T( SCAN_CHIPLET_XBUS, ULL(0x04) ); -CONST_UINT8_T( SCAN_CHIPLET_ABUS, ULL(0x08) ); -CONST_UINT8_T( SCAN_CHIPLET_PCIE, ULL(0x09) ); - -//******************************************************************************/ -//********* MULTICAST REGISTER DEFINITIONS FOR PERVASIVE INITs ****************/ -//******************************************************************************/ - -CONST_UINT64_T( WRITE_ALL_HPRE0_0x690F0020 , ULL(0x690F0020) ); // hang pulse register 0 -CONST_UINT64_T( WRITE_ALL_HPRE1_0x690F0021 , ULL(0x690F0021) ); // hang pulse register 1 -CONST_UINT64_T( WRITE_ALL_HPRE2_0x690F0022 , ULL(0x690F0022) ); // hang pulse register 2 -CONST_UINT64_T( WRITE_ALL_HPRE3_0x690F0023 , ULL(0x690F0023) ); // hang pulse register 3 -CONST_UINT64_T( WRITE_ALL_HPRE4_0x690F0024 , ULL(0x690F0024) ); // hang pulse register 4 -CONST_UINT64_T( WRITE_ALL_HPRE5_0x690F0025 , ULL(0x690F0025) ); // hang pulse register 5 -CONST_UINT64_T( WRITE_ALL_HPRE6_0x690F0026 , ULL(0x690F0026) ); // hang pulse register 6 -CONST_UINT64_T( WRITE_ALL_HPCRE_0x690F0028 , ULL(0x690F0028) ); // hang pulse count register - -CONST_UINT64_T( READ_GLOBAL_SPATT_FIR_0x570F001A , ULL(0x570F001A) ); // Bitwise read -CONST_UINT64_T( READ_GLOBAL_XSTOP_FIR_0x570F001B , ULL(0x570F001B) ); // Bitwise read -CONST_UINT64_T( READ_GLOBAL_RECOV_FIR_0x570F001C , ULL(0x570F001C) ); // Bitwise read - -CONST_UINT64_T( WRITE_EX_PMGP0_AND_0x690F0101 , ULL(0x690F0101) ); // PM G0 initialization - - - -// other multicast constants were moved to common_scom_addresses.H 1/24/2010 mfred - -#endif - - -/* -*************** Do not edit this area *************** -This section is automatically updated by CVS when you check in this file. -Be sure to create CVS comments when you commit so that they can be included here. - -$Log: p8_scom_addresses.H,v $ -Revision 1.199 2015/09/16 19:33:47 jmcgill -add I2CM registers for SBE FFDC collection - -Revision 1.198 2015/08/04 22:06:23 baiocchi -Updating Support for starting the SBEs without a FSP - -Revision 1.197 2015/06/29 01:43:56 jmcgill -add definition for PCIE NEST FIR Action2 Registers (Naples only) - -Revision 1.196 2015/05/19 19:19:40 jmcgill -add OCC core external interrupt register - -Revision 1.195 2015/05/01 17:40:55 belldi - -- Added constant: CONST_UINT64_T( CAPP_APC_MASTER_CAPI_CTL_0x02013019 , ULL(0x02013019) ); - -Revision 1.194 2015/03/17 18:55:38 jmcgill -add NPU FIR register constants - -Revision 1.193 2015/02/02 18:57:13 jmcgill -add 2nd CAPP unit memory BAR/NPU MMIO BAR address definitions - -Revision 1.192 2015/01/26 15:07:09 jmcgill -add NPU SCOM addresses - -Revision 1.191 2014/12/18 20:44:35 jmcgill -add NPU/NVlink SCOM address definitions - -Revision 1.190 2014/12/18 16:10:45 jmcgill -add entry for CAPP snoop config registers - -Revision 1.189 2014/11/20 17:56:55 jmcgill -add definition for I2C_SLAVE_CONFIG register - -Revision 1.188 2014/11/18 17:30:54 jmcgill -added definitions for PCIe PHB3/IOP2 & CAPP SCOM addresses referenced by Naples HWP updates - -Revision 1.187 2014/09/30 13:59:57 gweber -added A_TRA1 support for Naples - -Revision 1.186 2014/09/17 13:58:45 jmcgill -add EX clk adjust register definition (SW278630) - -Revision 1.185 2014/09/01 20:16:49 jmcgill -add support for CAPI directory dump - -Revision 1.184 2014/07/15 21:12:03 jmcgill -add PC_NE error report hold register definitions for FFDC collection (SW261816) - -Revision 1.183 2014/06/08 19:49:24 jmcgill -add XBUS skew adjust data register definition - -Revision 1.182 2014/04/24 23:14:55 cmolsen -Added four PIRR reg defs. - -Revision 1.181 2014/04/22 03:47:27 jmcgill -reset HCA logic for MPIPL (SW257953) - -Revision 1.180 2014/04/12 03:14:16 cmolsen -Added two SPURR regs. - -Revision 1.179 2014/03/27 03:43:43 jmcgill -updates for proc_mpipl_clear_xstop (SW252842) - -Revision 1.178 2014/03/12 18:55:47 jmcgill -add IO SCOM_MODE_PB register constant definitions (DMI/XBUS/ABUS) - -Revision 1.177 2014/03/05 00:13:59 belldi - -Added following CAPP Error Reporting and Handling regs. FFDC is collected from them in proc_suspend_io. -NX_CAPP_FIR_MASK_0x02013003 -NX_CAPP_FIR_ACTION0_0x02013006 -NX_CAPP_FIR_ACTION1_0x02013007 -NX_CAPP_SNOOP_ERR_REPORT_0x0201300A -NX_CAPP_APC_MASTER_ERR_REPORT_0x0201300B -NX_CAPP_TRANSPORT_ERR_HOLD_0x0201300C -NX_CAPP_TLBI_ERR_HOLD_0x0201300D -NX_CAPP_ERR_STAT_CTRL_0x0201300E -NX_CAPP_FLUSH_SUE_STATE_MAP_0x0201300F -NX_CAPP_ERR_INJECT_0x02013010 -NX_CAPP_EPOCH_RECOV_TIMERS_CTRL_0x0201302C -NX_CAPP_FLUSH_SUE_UOP1_0x02013803 -NX_CAPP_FLUSH_SUE_UOP2_0x02013804 - -Revision 1.176 2014/03/03 23:41:45 stillgs -Add PMC Error Mask to OCC per RAS review; Add JTAG Accelerator regs - -Revision 1.175 2014/03/03 15:52:06 cmolsen -Added IMA_EVENT_MASK_0x100132CF - -Revision 1.174 2014/03/03 00:04:13 cmolsen -Added CHTM_IMA_PDBAR_REG_0x1001100B - -Revision 1.173 2014/02/10 14:36:30 jmcgill -add NX addresses for debug bus/NXD trace collection - -Revision 1.172 2014/01/30 16:19:24 mfred -Add some clock control regs for FFDC. - -Revision 1.171 2014/01/20 22:17:37 jdavidso -Added additional pmc registers for SW239845. - -Revision 1.170 2013/11/13 21:21:53 bellows -updates for running centaur throttling sync support - -Revision 1.169 2013/11/05 20:29:39 bellows -Added MCS_MCIARCSYN register - -Revision 1.168 2013/10/31 15:36:58 jmcgill -add address for CAPP APC Master LCO Target register - -Revision 1.167 2013/10/21 12:39:19 stillgs - -- Add base FIR registers for reading during MPIPL clear xstop processing -- Add bitwise multicast read addresses for xstop, recoverable and special attention. - Xstop and Recoverable reads used for MPIPL clear xstop - -Revision 1.166 2013/10/17 13:41:10 jmcgill -correct PB PMU register definitions - -Revision 1.165 2013/10/15 16:10:39 jeshua -Added PCBMS_RESET_REG_0x000F001D - -Revision 1.164 2013/10/07 14:17:57 jeshua -Added some L3 registers and ECID (OTPROM) registers - -Revision 1.163 2013/10/04 15:50:56 jmcgill -add TCTL special attention status registers - -Revision 1.162 2013/10/03 14:56:38 stillgs - -Added EX PCB Slave error capture registers - -Revision 1.161 2013/08/21 15:11:23 gweber -added CFAM_OSCSW_SENSE1,2 - -Revision 1.160 2013/08/08 02:48:33 stillgs - -Add NCU and CHTM mode registers - -Revision 1.159 2013/06/28 16:50:17 stillgs - -Adde PBAX Push Control/Status 1 registers for pba_init -reset - -Revision 1.158 2013/06/21 18:23:33 jeshua -Added EX_PARTIAL_GOOD_0x520F0012 for FFDC - -Revision 1.157 2013/06/21 15:17:24 jmcgill -support HCA EN/EH BAR and Range registers - -Revision 1.156 2013/06/20 16:10:16 campisan -Added SCOM addresses for CPM calibration code not previously defined. - -Revision 1.155 2013/06/13 13:22:10 jmcgill -add HCA BAR and Range registers - -Revision 1.154 2013/06/05 21:06:58 stillgs - -Add PMC Rail Bounds, Global Pstate Bounds and PCBS FSM monitor1 registers - -Revision 1.153 2013/05/31 18:02:44 jmcgill -add LPC addresses - -Revision 1.152 2013/05/30 13:13:45 jmcgill -add MCSMODE0 register - -Revision 1.151 2013/05/23 19:49:59 jmcgill -add PSI addresses, fix PB X bus FIR constant names per FW review - -Revision 1.150 2013/05/15 04:22:35 jmcgill -add PB X/A, PCI IOP PLL FIR register addresses - -Revision 1.149 2013/05/09 04:05:36 jmcgill -add AS MMIO BAR - -Revision 1.148 2013/04/28 02:30:41 jmcgill -add MCD recovery config register definitions - -Revision 1.147 2013/04/23 16:30:27 jimyac -added additional OCC interrupt registers - -Revision 1.146 2013/04/17 16:16:32 jimyac -added OCC registers - OUDER0/1 & OTR0/1 - -Revision 1.145 2013/04/16 22:15:34 jeshua -Moved in cfam addresses from common file -Added in write protect cfam address -Renamed PIBMEM_REPAIR_LOAD_0x00088007 to PIBMEM_REPAIR_0x00088007 - -Revision 1.144 2013/04/15 19:28:23 jmcgill -add MCD FIR entries - -Revision 1.143 2013/04/08 14:56:05 jmcgill -add PCIE ETU reset registers - -Revision 1.142 2013/03/26 12:17:16 stillgs - -Added EX DTS/Therm registers - -Revision 1.141 2013/03/26 11:45:14 pchatnah -adding some more registers from prep_for_reset - -Revision 1.140 2013/03/21 13:50:57 pchatnah -ading checkstop register - -Revision 1.139 2013/03/17 22:07:53 jmcgill -add L3 BAR registers - -Revision 1.138 2013/03/07 17:21:18 jmcgill -add ADU hang divider register - -Revision 1.137 2013/03/07 06:29:23 pchatnah -adding intchip address - -Revision 1.136 2013/03/04 02:51:38 jmcgill -fix PB RAS/EXTFIR addresses, add ADU secure iovalid register - -Revision 1.135 2013/03/01 03:05:38 pchatnah -adding device_id register - -Revision 1.134 2013/02/20 19:04:32 cmolsen -Added L2/L3 Epsilon registers. - -Revision 1.133 2013/02/05 14:33:50 koenig -Added XBus skew adjust register - AK - -Revision 1.132 2013/01/23 15:46:10 pchatnah -fixing address mistakes - -Revision 1.130 2013/01/17 11:39:08 pchatnah -updating the pmc_init registers - -Revision 1.129 2013/01/10 01:17:27 stillgs -Fix ID line typo - -Revision 1.128 2013/01/09 22:04:52 stillgs -Fix PMC_FSMSTATE_STATU_REG name with correct value to match the address - -Revision 1.127 2013/01/09 16:21:54 stillgs -Fix PMC_DEEPEXIT_MASK_WOR name typo --- make name match the actual address - -Revision 1.126 2012/12/20 18:55:31 stillgs -Added PC POW STATUS regs - -Revision 1.125 2012/12/12 04:55:22 stillgs -Added EX PCBS Slave Configuration register - -Revision 1.124 2012/12/07 21:32:13 stillgs -Fix ECO PFET Delay register name problem - -Revision 1.123 2012/12/03 22:28:51 baysah -Added mcs mode4 register. - -Revision 1.122 2012/11/30 03:39:35 klhillp8 -Added the FIR_AND register addresses for mpipl_clear_xstop. - -Revision 1.121 2012/11/26 03:16:48 stillgs -Add PMC LFIR and other addresses needed for SLW recovery - -Revision 1.120 2012/11/17 19:52:43 jmcgill -add trace status registers, chiplet scan constants - -Revision 1.119 2012/11/16 11:14:43 koenig -Corrected ABUS and PCI chiplet offsets - AK - -Revision 1.118 2012/11/16 04:05:59 jmcgill -remove FSI2PIB addresses already in common address file - -Revision 1.117 2012/11/12 18:46:14 jmcgill -updates for FSI2IB cfam registers, MCS SCOM registers - -Revision 1.116 2012/11/06 20:22:39 klhillp8 -Kevin Hill - Updated FIR OR and AND addresses for L2_FIR, L3_FIR, and NCU_FIR - -Revision 1.115 2012/11/05 01:39:53 jmcgill -add entries needed for proc_pcie_scominit and proc_pcie_config procedures - -Revision 1.114 2012/10/25 21:52:47 bgass -Added EX trusted boot scom. - -Revision 1.113 2012/10/25 11:55:05 koenig -Added some hangcounter register - AK - -Revision 1.112 2012/10/15 16:37:47 jklazyns - - Added TP chiplet PCB slave hang pulse registers - -Revision 1.111 2012/10/15 04:18:10 stillgs -Added L3 HA Dirty Address Write Pointer reg for SLW save/restore - -Revision 1.110 2012/10/15 01:17:12 jklazyns - - Added TOD registers - - Added SPRD registers for each LPAR (pg 105 of PC Workbook) - -Revision 1.109 2012/10/12 03:27:42 baysah -Added MCI FIR mask register. - -Revision 1.108 2012/10/11 13:44:27 jimyac -removed channel3 OCI register addresses - they were removed in the logic a while ago - -Revision 1.107 2012/10/10 01:39:17 jmcgill -add EX chiplet FIR register SCOM addresses - -Revision 1.106 2012/10/04 22:44:00 szhong -commented out WRITE_EX_GP3_AND_0x690F0013 WRITE_EX_GP3_OR_0x690F0014 WRITE_EX_PMGP0_OR_0x690F0102 due to duplicated definition - -added OTP rom related scom addresses - -Revision 1.105 2012/09/26 17:53:25 jklazyns - -Added EX_L3_PRD_PURGE_REG to support L3 purge procedure - -Revision 1.104 2012/09/26 15:11:07 jklazyns - -Added addresses for Core FIR, Mask, Action, and WOF - -Revision 1.103 2012/09/24 03:06:59 jmcgill -add security switch register, PSI notrust BARs - -Revision 1.102 2012/09/21 10:54:18 stillgs -Clean up old PMC entries - -Revision 1.101 2012/09/20 10:43:03 rmaier -Added TOD_FSM_REG_00040024 - -Revision 1.100 2012/09/15 21:26:14 jmcgill -add cfam addresses for mailbox scratch registers - -Revision 1.99 2012/09/13 20:27:35 mfred -Added some multicast group 1 addresses to the file. - -Revision 1.98 2012/09/13 19:54:41 mfred -Move group 1 (ex chiplet) multicast group definitions to this file. - -Revision 1.97 2012/09/12 17:19:36 jmcgill -add LPC SCOM registers - -Revision 1.96 2012/09/11 14:20:23 szhong -added: SBE VITAL REG - I2C MASTER (MODE) - PORE_ECCB CONTROL REG - PORE_ECCB STATUS REG - PORE_ECCB DATA REG - -Revision 1.95 2012/09/04 15:40:09 jimyac -added OCC LFIR registers - -Revision 1.94 2012/08/28 07:56:27 pchatnah -updating - -Revision 1.93 2012/08/26 01:54:37 jmcgill -add EX hang pulse register definitions - -Revision 1.92 2012/08/21 03:30:37 jmcgill -add A/F link framer config registers - -Revision 1.91 2012/08/20 19:25:19 jmcgill -add entry from ADU TBROM BAR - -Revision 1.90 2012/08/15 15:03:12 jmcgill -add PB A/F link trace register addresses - -Revision 1.89 2012/08/11 22:21:04 jmcgill -add addresses for proc_build_smp procedure - -Revision 1.88 2012/08/08 14:25:13 kgungl -pbax updates - -Revision 1.87 2012/08/08 13:18:30 stillgs -Added PMC monitoring registers - -Revision 1.86 2012/08/08 11:32:16 pchatnah -updating register address for vsafe mode - -Revision 1.85 2012/08/06 18:35:34 karm -added EX_SYNC_CONFIG - -Revision 1.84 2012/07/30 15:34:53 bellows -Updates for set up bars - -Revision 1.83 2012/07/23 14:42:39 jmcgill -add addresses needed proc_psi_init - -Revision 1.82 2012/06/27 07:43:32 rkoester -add remaining PLLLOCK register - -Revision 1.80 2012/06/20 14:49:32 rkoester -add plllock register - -Revision 1.79 2012/06/17 20:26:00 jmcgill -update trace SCOM addresses - -Revision 1.78 2012/06/17 19:00:37 jmcgill -add core direct debug control register - -Revision 1.77 2012/06/09 19:24:39 jmcgill -add ADU BAR registers - -Revision 1.76 2012/06/05 06:03:04 jmcgill -add ADU XSCOM BAR register - -Revision 1.75 2012/06/01 02:45:26 jmcgill -updates for MCS registers - -Revision 1.74 2012/05/30 12:28:52 kgungl -issues resolved: scom addresses for pba - -Revision 1.73 2012/05/23 16:31:18 karm -added EX core RAS_MODE - -Revision 1.72 2012/05/23 11:04:28 pchatnah -updating pss spivid spwkup registers - -Revision 1.71 2012/05/18 17:59:24 jmcgill -add addresses for proc_setup_bars - -Revision 1.70 2012/05/11 21:15:05 jeshua -Added EX_PCBS_FSM_MONITOR2_REG - -Revision 1.69 2012/05/08 13:31:46 karm -changes to RAM registers in EX PC unit - -Revision 1.68 2012/05/08 11:55:20 stillgs -Added some additional PCBS-PM addresses - -Revision 1.67 2012/05/03 21:36:59 karm -added core thread_active - -Revision 1.66 2012/05/02 21:37:42 jeshua -Added ECID_PART_0 and ECID_PART_1 - -Revision 1.65 2012/05/01 14:30:39 stillgs -Add additional OHA registers - -Revision 1.64 2012/04/27 14:48:20 rmaier -Added RESCLK_status_reg - -Revision 1.63 2012/04/26 22:47:18 karm -added EX_PERV registers for ram and thread ctrl - -Revision 1.62 2012/04/16 23:55:37 bcbrock -Corrected problems related to C/C++ and 32-bit/64-bit portability and Host -Boot after initial review by FW team. - -o Renamed fapi_sbe_common.h to fapi_sbe_common.H -o Renamed p8_scan_compression.[ch] to .[CH] since these are for use by C++ - procedures only (no requirement to execute on OCC). -o Modified sbe_xip_image.c to use the C99 standard way to print uint64_t - variables. -o Added __cplusplus guards to sbe_xip_image.h - -Revision 1.61 2012/04/09 22:35:14 jeshua -Added L2 FIR and CERR registers - -Revision 1.60 2012/03/21 08:15:53 rmaier -Added OHA_ARCH_IDLE_STATE_REG - -Revision 1.59 2012/03/14 11:50:03 stillgs -Added PMC O2S and SPIVID control regs for use by proc_pmc_init.C and proc_sbe_set_pvid.S - -Revision 1.58 2012/03/02 21:41:45 jimyac -added additional OCB Indirect Channel 0-3 Registers - -Revision 1.57 2012/03/01 16:09:20 rmaier -Added PCBS/OHA constants - -Revision 1.56 2012/02/29 22:57:24 bcbrock -Added PIBMEM control registers to p8_scom_addresses.H - -Revision 1.55 2012/02/10 23:09:52 jmcgill -add trace array addresses - -Revision 1.54 2012/01/30 16:08:40 jimyac -added OCC SRAM Boot Vector0-3 registers - -Revision 1.53 2012/01/30 15:59:43 jimyac -added ocb channel0-3 push & pull register and fixed typo in ocb addressed where address in variable name did not match actual address value - -Revision 1.52 2012/01/24 21:59:42 mfred -Moved common multicast address constants to common_scom_accresses.H - -Revision 1.51 2012/01/18 12:55:03 koenig -Added PBA clock sync reg - -Revision 1.50 2012/01/06 22:20:53 jmcgill -move shared/common addresses to common_scom_addresses.H, general cleanup - -Revision 1.49 2012/01/05 22:07:47 jeshua -Updated ring numbers for most chiplets - -Revision 1.48 2012/01/05 21:38:17 jmcgill -adjust EX SCOM ring comments, pervasive thread control/status register addresses - -Revision 1.47 2012/01/05 20:18:16 jmcgill -adjust L2 SCOM addresses - -Revision 1.46 2011/12/15 17:49:30 bcbrock -Added the PIBMEM base address to p8_scom_addresses.H - -Revision 1.45 2011/11/07 23:52:21 bcbrock -Added GENERIC_CLK_SCANDATA0_0x00038000 - -Revision 1.44 2011/11/07 05:49:06 jmcgill -update PBA trusted SCOM ring and PB X mode register addresses, add GP0 and/or addresses for A bus chiplet - -Revision 1.43 2011/09/28 12:49:47 stillgs -Added some PCBS-PM addresses for early PM FAPI work - -Revision 1.42 2011/09/16 16:01:34 jeshua -Added MBOX_SBEVITAL - -Revision 1.41 2011/09/16 16:00:26 jeshua -Undo Ralph's X-bus change. The X-bus is now chiplet 4, not chiplet 3. - -Revision 1.40 2011/09/16 10:28:56 rkoester -wrong X-BUS addresses corrected, changed from 0b04 to 0b03 - -Revision 1.39 2011/09/09 21:00:33 jeshua -X_BUS is now chiplet 4 (as of 051 chip) - -Revision 1.37 2011/09/02 18:45:46 dan -Added scan_time_rep - -Revision 1.36 2011/09/01 20:37:17 jmcgill -add PBA config register, shift L2 scom addresses for HW170113, fix L3 Mode Reg0 address - -Revision 1.35 2011/08/30 22:07:37 jeshua -Added NEST_GP0_AND - -Revision 1.34 2011/08/29 21:11:31 jmcgill -add generic PM GP0 OR constant - -Revision 1.33 2011/08/26 15:51:38 jeshua -Added chiplet defines for multicast operations - -Revision 1.32 2011/08/26 12:53:27 gweber -added constant SCAN_ALLSCANEXPRV_IMM - -Revision 1.31 2011/08/11 20:56:24 dan -removed redundant GENERIC_PMGP0_AND_0x000F0101. -added WRITE_ALL_GP0_AND_0x6B000004, WRITE_ALL_GP0_OR_0x6B000005 - -Revision 1.30 2011/07/28 16:36:30 jmcgill -add comment regarding L2 SCOM addresses which need to be adjusted when model fixes arrive (HW170113) - -Revision 1.29 2011/07/27 12:28:55 dan -Added scan0 defines. - -Revision 1.28 2011/07/25 22:31:03 venton -Added back in global addresses still used in SBe procs from version 1.24 - -Revision 1.27 2011/07/25 20:52:58 jmcgill -temporary workaround for L2 Purge Register SCOM access - -Revision 1.26 2011/07/25 17:30:35 dan -Added some generic registers. - -Revision 1.25 2011/07/25 13:05:09 gweber -moved centaur constants to cen_scom_addresses.H - -Revision 1.23 2011/07/20 15:32:10 gweber -added some centaur constants - -Revision 1.22 2011/07/15 20:50:13 jeshua -Added chiplet and some generic addresses - -Revision 1.21 2011/07/15 20:24:14 jeshua -TP_GP3_0x01000003 should be TP_GP4_0x01000003 - -Revision 1.20 2011/07/08 19:49:01 jeshua -Moved some addresses to their appropriate sections -Fixes some addresses that didn't match their name -Added EX08-15 generics -Removed some non-generic EX01 addresses - -Revision 1.19 2011/07/07 21:36:11 rkoester -more addresses added - -Revision 1.18 2011/07/07 16:27:49 karm -added chiplet_core_pervasive registers for start and status, added chiplet id - -Revision 1.17 2011/07/07 12:24:49 rkoester -addresses added - -Revision 1.16 2011/07/06 20:03:46 jmcgill -updates to handle TP design modifications which changed SCOM access method for subset of PBA facilities - -Revision 1.15 2011/07/06 15:01:36 bcbrock -Fix header file name - -Revision 1.14 2011/07/06 04:06:49 bcbrock -Added a common header for FAPI/SBE #defines, fapi_sbe_common.h - -Revision 1.13 2011/07/01 15:13:16 rkoester -addresses added for mailbox register - -Revision 1.12 2011/06/30 09:50:28 rkoester -private version of .H file released back to LIB, MBOX addresses added - -Revision 1.11 2011/06/15 22:46:26 jeshua -Added Mailbox registers - -Revision 1.10 2011/06/14 15:55:46 rkoester -move SCOM addresses from porinit.C to p8_scom_addresses.H - -Revision 1.9 2011/06/14 04:57:04 bcbrock -Latest version of PGAS and PORE inline tools; Added PORE SCOM addresses - -Revision 1.8 2011/06/07 21:26:49 jeshua -Updated OCB names to have the correct addresses - -Revision 1.7 2011/06/02 14:28:26 jmcgill -add PB EH scom addresses, L3 mode register1 address - -Revision 1.6 2011/05/31 22:09:47 jeshua -Updated the ULL macro, because the previous one didn't work with the assembler - -Revision 1.5 2011/05/27 21:49:13 jeshua -Switch to constants instead of #defines -Added in a macro to allow PORE assembler to use this header as well - -Revision 1.4 2011/05/24 19:01:58 jmcgill -add addresses from OCC/OCB/PBA - -Revision 1.3 2011/04/21 19:48:23 jeshua -Added L2 and L3 Mode Reg 0 - -Revision 1.2 2011/04/06 18:27:01 jmcgill -fixup ADU Control Register name, add ADU PMISC Mode Register address - -Revision 1.1 2011/02/23 17:09:44 jeshua -Initial version - - - -*/ |
