INITPROC: Hostboot - Low Priority HW Init Procedures for week of 5/7

SW202434

Change-Id: I6bf082deb2cbe927c0ba92d670906b232482578f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4627
Tested-by: Jenkins Server
Reviewed-by: Mark W. Wenning <wenning@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 232 insertions, 31 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/memory_errors.xml b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
index b12665f62..cf0704487 100644
--- a/src/usr/hwpf/hwp/dram_training/memory_errors.xml
+++ b/src/usr/hwpf/hwp/dram_training/memory_errors.xml
@@ -21,6 +21,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <hwpErrors>
+<!-- $Id: memory_errors.xml,v 1.39 2013/05/20 16:51:14 gollub Exp $ -->
 <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID -->
 <!-- *********************************************************************** -->
 
@@ -211,6 +212,24 @@
 </hwpError>
 
   <hwpError>
+    <rc>RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR</rc>
+    <description>MCS is listed as a member in multiple groups.</description>
+    <ffdc>MCS_POS</ffdc>
+    <ffdc>GROUP_INDEX_A</ffdc>
+    <ffdc>GROUP_INDEX_B</ffdc>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR</rc>
+    <description>Invalid non-mirrored alternate BAR configuration.</description>
+  </hwpError>
+
+  <hwpError>
+    <rc>RC_MSS_SETUP_BARS_M_ALT_BAR_ERR</rc>
+    <description>Invalid mirrored alternate BAR configuration.</description>
+  </hwpError>
+
+  <hwpError>
     <rc>RC_MSS_MAINT_START_NOT_RESET</rc>
     <description>MBMCCQ[0]: maint_cmd_start not reset by hw.</description>
     <!-- FFDC: Capture register we are checking -->    
@@ -223,7 +242,7 @@
     <callout><target>MBA</target><priority>HIGH</priority></callout>
     <!-- Deconfigure MBA -->
     <deconfigure><target>MBA</target></deconfigure>
-    <!-- Create GARD record for MASTER_CHIP -->    
+    <!-- Create GARD record for MBA -->    
     <gard><target>MBA</target></gard>    
 </hwpError>
 
@@ -240,7 +259,7 @@
     <callout><target>MBA</target><priority>HIGH</priority></callout>
     <!-- Deconfigure MBA -->
     <deconfigure><target>MBA</target></deconfigure>
-    <!-- Create GARD record for MASTER_CHIP -->    
+    <!-- Create GARD record for MBA -->    
     <gard><target>MBA</target></gard>    
 </hwpError>
 
@@ -258,7 +277,7 @@
     <callout><target>MBA</target><priority>LOW</priority></callout>
     <!-- Deconfigure MBA -->
     <deconfigure><target>MBA</target></deconfigure>
-    <!-- Create GARD record for MASTER_CHIP -->    
+    <!-- Create GARD record for MBA -->    
     <gard><target>MBA</target></gard>        
 </hwpError>
 
@@ -357,7 +376,7 @@
     <callout><target>MBA</target><priority>LOW</priority></callout>
     <!-- Deconfigure MBA -->
     <deconfigure><target>MBA</target></deconfigure>
-    <!-- Create GARD record for MASTER_CHIP -->    
+    <!-- Create GARD record for MBA -->    
     <gard><target>MBA</target></gard>        
 </hwpError>
 
@@ -419,8 +438,6 @@
     <description>ATTR_MSS_FREQ set to zero so can't calculate scrub rate.</description>
     <!-- FFDC: MBA target -->    
     <ffdc>MBA</ffdc>
-    <!-- FFDC: DDR_FREQ -->    
-    <ffdc>DDR_FREQ</ffdc>
     <!-- FFDC: Capture command type we are trying to run -->        
     <ffdc>CMD_TYPE</ffdc>        
     <!-- TODO: Callout FW HIGH -->
@@ -433,6 +450,8 @@
     <ffdc>MBA</ffdc>
     <!-- FFDC: Capture register we are checking -->    
     <ffdc>MBAXCR</ffdc>
+    <!-- FFDC: DRAM width -->    
+    <ffdc>DRAM_WIDTH</ffdc>
     <!-- TODO: Callout FW HIGH -->
 </hwpError>
 
@@ -607,7 +626,7 @@
     <callout><target>MBA</target><priority>HIGH</priority></callout>
     <!-- Deconfigure MBA -->
     <deconfigure><target>MBA</target></deconfigure>
-    <!-- Create GARD record for MASTER_CHIP -->    
+    <!-- Create GARD record for MBA -->    
     <gard><target>MBA</target></gard>    
 </hwpError>
 
@@ -655,7 +674,7 @@
 
   <hwpError>
     <rc>RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT</rc>
-    <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range</description>
+    <description>i_rank or i_muxType or i_steerType or i_symbol input to mss_put_steer_mux out of range</description>
     <!-- FFDC: MBA target -->    
     <ffdc>MBA</ffdc>
     <!-- FFDC: RANK we are writing steer mux for -->    
@@ -696,7 +715,7 @@
     <callout><target>MBA</target><priority>HIGH</priority></callout>
     <!-- Deconfigure MBA -->
     <deconfigure><target>MBA</target></deconfigure>
-    <!-- Create GARD record for MASTER_CHIP -->    
+    <!-- Create GARD record for MBA -->    
     <gard><target>MBA</target></gard>    
 </hwpError>
 
@@ -872,11 +891,13 @@
 <hwpError>
     <rc>RC_MSS_NON_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc>
     <description>FABRIC IS IN NON-CHECKER BOARD MODE.  SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '2MCS/GROUP, 4MCS/GROUP  AND 8MCS/GROUP'. OR ENABLE CHECKER BOARD, TO SUPPORT '1MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description>
+    <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc>
 </hwpError>
 
 <hwpError>
     <rc>RC_MSS_CHECKER_BOARD_MODE_GROUPING_NOT_POSSIBLE</rc>
     <description>FABRIC IS IN CHECKER BOARD MODE BUT IT DOES NOT SUPPORT 1MCS/GROUP. SET ATTRIBUTE 'ATTR_MSS_INTERLEAVE_ENABLE' TO SUPPORT '1MCS/GROUP'. OR DISABLE CHECKER BOARD, TO SUPPORT '2MCS/GROUP, 4MCS/GROUP  AND 8MCS/GROUP'. MRW NEEDS TO BE UPDATED. </description>
+    <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc>
 </hwpError>
 
 <hwpError>
@@ -887,6 +908,27 @@
 </hwpError>
 
 <hwpError>
+    <rc>RC_ERROR_MSS_GROUPING_ATTRS</rc>
+    <description>MEM grouping Attributes collection and printing function</description>
+    <ffdc>_ATTR_PROC_POS</ffdc>
+    <ffdc>_ATTR_CEN_POS</ffdc>
+    <ffdc>_ATTR_CHIP_UNIT_POS_MBA0</ffdc>
+    <ffdc>_ATTR_CHIP_UNIT_POS_MBA1</ffdc>
+    <ffdc>_ATTR_EFF_DIMM_SIZE0</ffdc>
+    <ffdc>_ATTR_EFF_DIMM_SIZE1</ffdc>
+    <ffdc>_ATTR_MSS_INTERLEAVE_ENABLE</ffdc>
+    <ffdc>_ATTR_ALL_MCS_IN_INTERLEAVING_GROUP</ffdc>
+    <ffdc>_ATTR_PROC_MEM_BASE</ffdc>
+    <ffdc>_ATTR_PROC_MIRROR_BASE</ffdc>
+    <ffdc>_ATTR_MSS_MEM_MC_IN_GROUP</ffdc>
+    <ffdc>_ATTR_PROC_MEM_BASES</ffdc>
+    <ffdc>_ATTR_PROC_MEM_SIZES</ffdc>
+    <ffdc>_ATTR_MSS_MCS_GROUP_32</ffdc>
+    <ffdc>_ATTR_PROC_MIRROR_BASES</ffdc>
+    <ffdc>_ATTR_PROC_MIRROR_SIZES</ffdc>
+</hwpError>
+
+<hwpError>
     <rc>RC_MSS_UNABLE_TO_GROUP_SUMMARY</rc>
     <description>MCS COULD NOT BE GROUPED.  SEE PREVIOUS ERROR MESSAGES FOR WHICH MCS HAS BEEN RC_MSS_UNABLE_TO_GROUP_MCS</description>
 </hwpError>
@@ -894,7 +936,153 @@
 <hwpError>
     <rc>RC_MSS_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS</rc>
     <description>MIRROR BASE ADDRESS OVERLAPS WITH MEMORY BASE ADDRESS.</description>
+    <collectFfdc>hwpCollectMemGrouping, PROC_CHIP</collectFfdc>
 </hwpError>
 
+<hwpError>
+    <rc>RC_ERROR_MSS_FIRS</rc>
+    <description>MEM FIR REGISTERS</description>
+ 
+<!-- DMI_FIR -->
+    <collectRegisterFfdc>
+	<id>REG_FFDC_DMI_FIR_REGS</id>
+	<target>CENCHIP</target>
+    </collectRegisterFfdc>
+<!-- MBIFIRQ -->
+    <collectRegisterFfdc>
+       <id>REG_FFDC_MBI_FIR_REGS</id>
+       <target>CENCHIP</target>
+    </collectRegisterFfdc>
+ 
+<!-- MBSFIRQ -->
+    <collectRegisterFfdc>
+       <id>REG_FFDC_MBS_FIR_REGS</id>
+       <target>CENCHIP</target>
+    </collectRegisterFfdc>
+ 
+<!-- SCAC_LFIR -->
+    <collectRegisterFfdc>
+       <id>REG_FFDC_SCAC_FIR_REGS</id>
+       <target>CENCHIP</target>
+    </collectRegisterFfdc>
+ 
+</hwpError>
+
+<hwpError>
+    <rc>RC_ERROR_MBA_FIRS</rc>
+    <description>MEM MBA FIR REGISTERS</description>
+ 
+<!-- MBA01_MBACALFIR -->
+<!-- MBA01_MBAFIRQ -->
+<!-- MBA01_MBSPAQ -->
+    <collectRegisterFfdc>
+       <id>REG_FFDC_MBA_FIR_REGS</id>
+       <target>CENCHIP_MBA</target>
+    </collectRegisterFfdc>
+
+<!-- PHY01_DDRPHY_FIR_REG -->
+    <collectRegisterFfdc>
+       <id>REG_FFDC_DDR_PHY_FIR_REGS</id>
+       <target>CENCHIP_MBA</target>
+    </collectRegisterFfdc>
+
+
+ 
+</hwpError>
+
+
+<registerFfdc>
+  <id>REG_FFDC_MBA_FIR_REGS</id>
+
+  <!-- MBA Special Attention Registers -->    
+  <scomRegister>MBA01_MBSPAQ_0x03010611</scomRegister>
+  <scomRegister>MBA01_MBSPAMSKQ_0x03010614</scomRegister>
+
+  <!-- MBA Fault Isolation Registers -->  
+  <scomRegister>MBA01_MBAFIRQ_0x03010600</scomRegister>  
+  <scomRegister>MBA01_MBAFIRMASK_0x03010603</scomRegister>  
+  <scomRegister>MBA01_MBAFIRACT0_0x03010606</scomRegister>  
+  <scomRegister>MBA01_MBAFIRACT1_0x03010607</scomRegister>  
+  <!-- MBA Error Report Register -->  
+  <scomRegister>MBA01_MBA_MCBERRPTQ_0x030106e7</scomRegister>  
+
+  <!-- MBA CAL FIR Registers -->  
+  <scomRegister>MBA01_MBACALFIR_0x03010400</scomRegister>  
+  <scomRegister>MBA01_MBACALFIR_MASK_0x03010403</scomRegister>  
+  <scomRegister>MBA01_MBACALFIR_ACTION0_0x03010406</scomRegister>  
+  <scomRegister>MBA01_MBACALFIR_ACTION1_0x03010407</scomRegister>  
+  <!-- MBA Error report register -->  
+  <scomRegister>MBA01_MBA_ERR_REPORTQ_0x0301041A</scomRegister>  
+</registerFfdc>
+
+<registerFfdc>
+  <id>REG_FFDC_MBI_FIR_REGS</id>
+  <scomRegister>CEN_MBIFIRQ_0x02010800</scomRegister>
+  <scomRegister>CEN_MBIFIRMASK_0x02010803</scomRegister>
+  <scomRegister>CEN_MBIFIRACT0_0x02010806</scomRegister>
+  <scomRegister>CEN_MBIFIRACT1_0x02010807</scomRegister>
+</registerFfdc>
+
+<registerFfdc>
+  <id>REG_FFDC_MBS_FIR_REGS</id>
+  <scomRegister>MBS_FIR_REG_0x02011400</scomRegister>
+  <scomRegister>MBS_FIR_MASK_REG_0x02011403</scomRegister>
+  <scomRegister>MBS_FIR_ACTION0_REG_0x02011406</scomRegister>
+  <scomRegister>MBS_FIR_ACTION1_REG_0x02011407</scomRegister>
+  <scomRegister>MBS_FIR_WOF_REG_0x02011408</scomRegister>
+
+  <scomRegister>MBS_ECC0_MBECCFIR_0x02011440</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_MASK_0x02011443</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_ACTION0_0x02011446</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_ACTION1_0x02011447</scomRegister>
+  <scomRegister>MBS_ECC0_MBECCFIR_WOF_0x02011448</scomRegister>
+
+  <scomRegister>MBS_ECC1_MBECCFIR_0x02011480</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_MASK_0x02011483</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_ACTION0_0x02011486</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_ACTION1_0x02011487</scomRegister>
+  <scomRegister>MBS_ECC1_MBECCFIR_WOF_0x02011488</scomRegister>
+
+  <scomRegister>CEN_MBS01_MBSFIRQ_0x02011600</scomRegister>
+  <scomRegister>CEN_MBS01_MBSFIRMASK_0x02011603</scomRegister>
+  <scomRegister>CEN_MBS01_MBSFIRACT0_0x02011606</scomRegister>
+  <scomRegister>CEN_MBS01_MBSFIRACT1_0x02011607</scomRegister>
+  <scomRegister>CEN_MBS01_MBSFIRWOF_0x02011608</scomRegister>
+
+  <scomRegister>CEN_MBS23_MBSFIRQ_0x02011700</scomRegister>
+  <scomRegister>CEN_MBS23_MBSFIRMASK_0x02011703</scomRegister>
+  <scomRegister>CEN_MBS23_MBSFIRACT0_0x02011706</scomRegister>
+  <scomRegister>CEN_MBS23_MBSFIRACT1_0x02011707</scomRegister>
+  <scomRegister>CEN_MBS23_MBSFIRWOF_0x02011708</scomRegister>
+</registerFfdc>
+
+<registerFfdc>
+  <id>REG_FFDC_SCAC_FIR_REGS</id>
+  <scomRegister>CEN_SCAC_LFIR_0x020115c0</scomRegister>
+  <scomRegister>CEN_SCAC_FIRMASK_0x020115c3</scomRegister>
+  <scomRegister>CEN_SCAC_FIRACTION0_0x020115c6</scomRegister>
+  <scomRegister>CEN_SCAC_FIRACTION1_0x020115c7</scomRegister>
+  <scomRegister>CEN_SCAC_FIRWOF_0x020115c8</scomRegister>
+</registerFfdc>
+
+<registerFfdc>
+  <id>REG_FFDC_DDR_PHY_FIR_REGS</id>
+  <scomRegister>PHY01_DDRPHY_FIR_REG_0x800200900301143fULL</scomRegister>
+  <scomRegister>PHY01_DDRPHY_FIR_MASK_REG_0x800200930301143fULL</scomRegister>
+  <scomRegister>PHY01_DDRPHY_FIR_ACTION0_REG_0x800200960301143fULL</scomRegister>
+  <scomRegister>PHY01_DDRPHY_FIR_ACTION1_REG_0x800200970301143fULL</scomRegister>
+  <scomRegister>PHY01_DDRPHY_FIR_WOF_REG_0x800200980301143fULL</scomRegister>
+</registerFfdc>
+
+
+<registerFfdc>
+  <id>REG_FFDC_DMI_FIR_REGS</id>
+  <scomRegister>CEN_DMIFIR_0x02010400</scomRegister>
+  <scomRegister>CEN_DMIFIR_MASK_0x02010403</scomRegister>
+  <scomRegister>CEN_DMIFIR_ACT0_0x02010406</scomRegister>
+  <scomRegister>CEN_DMIFIR_ACT0_0x02010407</scomRegister>
+  <scomRegister>CEN_DMIFIR_ACT0_0x02010408</scomRegister>
+</registerFfdc>
+
 <!-- EDIT THIS FILE DIRECTLY. THE ODS FILE METHOD IS NO LONGER VALID -->
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
index 2d59480c4..f36b459b8 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_address.C,v 1.9 2013/04/04 20:56:10 bellows Exp $
+// $Id: mss_mcbist_address.C,v 1.11 2013/05/16 22:00:24 sasethur Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013
 // *!           All Rights Reserved -- Property of IBM
@@ -38,9 +38,12 @@
 //-------------------------------------------------------------------------------
 // Version:|Author: | Date:   | Comment:
 // --------|--------|---------|--------------------------------------------------
+// 1.11	   |preeragh|17-May-13| Fixed FW Review Comments
+// 1.10	   |preeragh|30-Apr-13| Fixed FW Review Comment
 // 1.9     |bellows |04-Apr-13| Changed program to be Hostboot compliant
 // 1.2     |bellows |03-Apr-13| Added Id and cleaned up a warning msg.
 // 1.1     |        |xx-Apr-13| Copied from original which is now known as mss_mcbist_address_default/_lab.C
+// 1.2 	   Preetham | xx - Apr -13| Fixed rc_num call
 //------------------------------------------------------------------------------
 
 #include "mss_mcbist_address.H"
@@ -48,15 +51,17 @@ extern "C"
 {
 using namespace fapi;
 
-#define MAX_STRING_LEN 80
+#define MAX_ADDR_BITS 37
+#define MAX_VALUE_TWO 2
+
 #define DELIMITERS ","
 
 fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,uint8_t i_port,mcbist_addr_mode i_addr_type,interleave_type i_add_inter_type,uint8_t i_rank,uint64_t &io_start_address, uint64_t &io_end_address)
 
 {
 fapi::ReturnCode  rc;
-uint8_t l_num_ranks_per_dimm[2][2];
-uint8_t l_num_master_ranks[2][2];
+uint8_t l_num_ranks_per_dimm[MAX_VALUE_TWO][MAX_VALUE_TWO];
+uint8_t l_num_master_ranks[MAX_VALUE_TWO][MAX_VALUE_TWO];
 uint8_t l_dram_gen=0;
 uint8_t l_dram_banks=0;
 uint8_t l_dram_rows=0;
@@ -66,7 +71,7 @@ uint8_t l_dram_width=0;
 uint8_t l_addr_inter=0;
 uint8_t l_num_ranks_p0_dim0,l_num_ranks_p0_dim1,l_num_ranks_p1_dim0,l_num_ranks_p1_dim1;
 uint8_t mr3_valid,mr2_valid,mr1_valid;
-uint32_t __attribute__((unused)) rc_num; // SW198827 
+uint32_t rc_num;
 char S0[] = "b";
 //char l_my_addr[MAX_STRING_LEN];
 
@@ -76,8 +81,10 @@ char S0[] = "b";
 ecmdDataBufferBase l_default_add_buffer(64);
 ecmdDataBufferBase l_new_add_buffer(64);
 
- rc_num = l_default_add_buffer.flushTo0();
- rc_num = l_new_add_buffer.flushTo0();
+rc_num = l_default_add_buffer.flushTo0();
+if (rc_num){FAPI_ERR( "Error in function  addr_gen:");rc.setEcmdError(rc_num);return rc;}
+rc_num = l_new_add_buffer.flushTo0();
+if (rc_num){FAPI_ERR( "Error in function  addr_gen:");rc.setEcmdError(rc_num);return rc;}
 
 
 rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm); if(rc) return rc;
@@ -101,7 +108,7 @@ FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]);
 FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]);
 FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]);
 FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]);
-FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM is l_num_master_p1_dim1 %d ",l_num_master_ranks[1][1]);
+FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim1 is %d ",l_num_master_ranks[1][1]);
 
 //-------------------------------------------------------------------------------
 
@@ -181,14 +188,14 @@ return rc;
 fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba, char addr_string[],uint8_t mr3_valid,uint8_t mr2_valid,uint8_t mr1_valid,uint8_t l_dram_rows,uint8_t l_dram_cols,uint8_t l_addr_inter) 
 {
 fapi::ReturnCode  rc; 
-uint8_t i=37;
+uint8_t i=MAX_ADDR_BITS;
 
 uint8_t l_slave_rank = 0;
 uint8_t l_value;
 uint32_t l_value32 = 0;
 uint32_t l_sbit,rc_num;
 uint32_t l_start=0;
-uint32_t l_len = 6;
+uint32_t l_len = 0;
 uint64_t l_readscom_value = 0;
 uint64_t l_end = 0;
 uint64_t l_start_addr = 0;
@@ -196,7 +203,7 @@ uint8_t l_value_zero = 0;
 uint8_t l_user_end_addr = 0;
 ecmdDataBufferBase l_data_buffer_64(64);
 ecmdDataBufferBase l_data_buffer_rd64(64); 
-uint8_t l_attr_addr_mode = 3;
+uint8_t l_attr_addr_mode = 3; //default Value - FULL Address Mode
 uint8_t l_num_cols = 0;
 uint8_t l_num_rows = 0;
 
@@ -222,17 +229,18 @@ if(l_num_rows == 0 )
 
 rc_num = l_data_buffer_64.flushTo0();
 	
-	l_sbit = 0;l_value =i;
-	rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc;
-	rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);return rc;}
-	rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64);  if(rc) return rc;
-	i--;
+		l_sbit = 0;l_value =i;
+		rc = fapiGetScom(i_target_mba,0x030106c9,l_data_buffer_64); if(rc) return rc;
+		rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);if (rc_num){FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);return rc;}
+		rc = fapiPutScom(i_target_mba,0x030106c9,l_data_buffer_64);  if(rc) return rc;
+		i--;
 		
 		l_sbit = 54;l_value =i;
 		rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64);
 		rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
 		rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);  if(rc) return rc;
 		i--;
+		
 		//FAPI_INF("Inside strcmp ba2");
 		l_sbit = 48;l_value =i;
 		rc = fapiGetScom(i_target_mba,0x030106c8,l_data_buffer_64); if(rc) return rc;
@@ -939,7 +947,7 @@ rc = fapiPutScom(i_target_mba,0x030106d3,l_data_buffer_rd64); if(rc) return rc;
 else
 {
 
-l_attr_addr_mode = 3;
+l_attr_addr_mode = 3; //Default it for FW with Full Address Range
 
 if(l_attr_addr_mode == 0)
 {
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
index 54db45502..f7de7db2a 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_common.C,v 1.36 2013/04/09 09:02:14 ppcaelab Exp $
+// $Id: mss_mcbist_common.C,v 1.38 2013/04/30 08:53:46 ppcaelab Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -38,6 +38,8 @@
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
+//   1.38  |aditya  |05/30/13|Minor fix for firmware 
+//   1.37  |aditya  |04/22/13|Minor Fix
 //   1.36  |aditya  |04/09/13|Updated cfg_byte_mask and setup_mcbist functions
 //   1.35  |aditya  |03/18/13|Updated cfg_byte_mask and error map functions
 //   1.34  |aditya  |03/15/13|Added ISDIMM error map
@@ -146,6 +148,7 @@ fapi::ReturnCode  setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port
 	uint8_t l_index = 0;
 	uint8_t l_index1 = 0;
 	uint8_t l_flag = 0;
+	uint8_t l_new_addr = 1;
 	uint64_t scom_array[24] = {0x03010440,0x03010441,0x03010442,0x03010443,0x03010444,0x03010445,0x03010446,0x03010447,0x0201145E,0x0201145F,0x02011460,0x02011461,0x02011462,0x02011463,0x02011464,0x02011465,0x0201149E,0x0201149F,0x020114A0,0x020114A1,0x020114A2,0x020114A3,0x020114A4,0x020114A5};	
 	
 	
@@ -266,11 +269,13 @@ fapi::ReturnCode  setup_mcbist(const fapi::Target & i_target_mba, uint8_t i_port
     //preet
 	//FAPI_INF("DEBUG-----Print----Address Gen ");
 	
-	//if (new_address_map == 1)
-	//{
+	rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, l_new_addr); if(rc) return rc;
+
+	if (l_new_addr != 0)
+	{
 		rc = address_generation(i_target_mba,i_port,SF,BANK_RANK,i_rank,io_start_address,io_end_address);
 		if(rc) {FAPI_INF("BAD - RC ADDR Generation\n");return rc;}
-	//}
+	}
 
 	
 	
@@ -1094,7 +1099,7 @@ fapi::ReturnCode  cfg_byte_mask(const fapi::Target & i_target_mba,uint8_t i_rank
 	
 	l_max_1 = num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1];
     
-//SW198827    uint32_t __attribute__((unused)) rc_num = 0;
+   // uint32_t rc_num = 0;
      
     rc_num =  l_data_buffer3_64.flushTo0();if (rc_num){FAPI_ERR( "Error in function  cfg_byte_mask:");rc.setEcmdError(rc_num);return rc;}