diff options
| author | Matt Ploetz <maploetz@us.ibm.com> | 2013-10-03 14:31:43 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-10-10 21:55:28 -0500 |
| commit | b5ab69e7d4026ff821b1321d599f22d75397756a (patch) | |
| tree | 162c12e529da81a45586b503fd4d359895e2cd30 /src/usr/hwpf/hwp/dram_training | |
| parent | 5ee48041d8328da9ab3a53aa8a057ff2b62d0f6f (diff) | |
| download | talos-hostboot-b5ab69e7d4026ff821b1321d599f22d75397756a.tar.gz talos-hostboot-b5ab69e7d4026ff821b1321d599f22d75397756a.zip | |
INITPROC: Hostboot - from defect SW226794 mss_termination_control
Change-Id: I2869014c25246d2f150232b80aa8ea8cd86572cf
CQ: SW226794
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6476
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/dram_training')
| -rw-r--r-- | src/usr/hwpf/hwp/dram_training/mss_termination_control.C | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C index 148210bdb..b2f6ce6cf 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C +++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C @@ -20,7 +20,7 @@ /* Origin: 30 */ /* */ /* IBM_PROLOG_END_TAG */ -// $Id: mss_termination_control.C,v 1.21 2013/04/22 16:36:34 sasethur Exp $ +// $Id: mss_termination_control.C,v 1.22 2013/09/24 22:14:02 mwuu Exp $ /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */ //------------------------------------------------------------------------------ @@ -43,6 +43,8 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.22 | mwuu |20-Sep-13| Updated ADR DDR3 slew calibration table for 1 setting, +// 1066 20ohms, 4V/ns, changed from 11 to 10. // 1.21 | sasethur |16-Apr-13| Added DDR4 settings for rd_vref // 1.20 | sasethur |09-Apr-13| Changed wr_vref register settings as per ddr3spec // 1.19 | sasethur |05-Apr-13| Updated for port in parallel @@ -1022,9 +1024,10 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba) // adr(1), /* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______ Slew 3 4 5 6 3 4 5 6 3 4 5 6 3 4 5 6 (V/ns) */ -/*1066*/{{ 17, 13, 10, 8}, { 13, 11, 7, 6}, { 12, 8, 5, 131}, { 7, 4, 131, 131}}, -/*1333*/{{ 21, 16, 12, 10}, { 17, 12, 9, 7}, { 15, 10, 6, 132}, { 9, 5, 132, 132}}, -/*1600*/{{ 25, 19, 15, 12}, { 20, 14, 13, 8}, { 19, 12, 7, 133}, { 11, 6, 133, 133}}, +// 1066 {{ 17, 13, 10, 8}, { 13, 11, 7, 6}, { 12, 8, 5, 131}, { 7, 4, 131, 131}}, // old before May 2013 +/*1066*/{{ 17, 13, 10, 8}, { 13, 10, 7, 6}, { 12, 8, 5, 131}, { 7, 4, 131, 131}}, +/*1333*/{{ 21, 16, 12, 10}, { 17, 12, 9, 7}, { 15, 10, 6, 132}, { 6, 5, 132, 132}}, +/*1600*/{{ 25, 19, 15, 12}, { 20, 14, 13, 8}, { 19, 12, 7, 133}, { 7, 6, 133, 133}}, /*1866*/{{157, 150, 145, 142}, {151, 145, 141, 138}, {150, 142, 136, 134}, {141, 134, 134, 134}} } }, /* DDR4(1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */ |
