INITPROC: Hostboot - from defect SW226794 mss_termination_control

Change-Id: I2869014c25246d2f150232b80aa8ea8cd86572cf
CQ: SW226794
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/6476
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

3 files changed, 32 insertions, 7 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
index 148210bdb..b2f6ce6cf 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_termination_control.C,v 1.21 2013/04/22 16:36:34 sasethur Exp $
+// $Id: mss_termination_control.C,v 1.22 2013/09/24 22:14:02 mwuu Exp $
 /* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
 
 //------------------------------------------------------------------------------
@@ -43,6 +43,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.22   | mwuu     |20-Sep-13| Updated ADR DDR3 slew calibration table for 1 setting,
+//  							  1066 20ohms, 4V/ns, changed from 11 to 10.
 //  1.21   | sasethur |16-Apr-13| Added DDR4 settings for rd_vref
 //  1.20   | sasethur |09-Apr-13| Changed wr_vref register settings as per ddr3spec
 //  1.19   | sasethur |05-Apr-13| Updated for port in parallel 
@@ -1022,9 +1024,10 @@ fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba)
 	// adr(1),
 /* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______
    Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
-/*1066*/{{ 17,  13,  10,   8}, { 13,  11,   7,   6}, { 12,   8,   5, 131}, {  7,   4, 131, 131}},
-/*1333*/{{ 21,  16,  12,  10}, { 17,  12,   9,   7}, { 15,  10,   6, 132}, {  9,   5, 132, 132}},
-/*1600*/{{ 25,  19,  15,  12}, { 20,  14,  13,   8}, { 19,  12,   7, 133}, { 11,   6, 133, 133}},
+// 1066 {{ 17,  13,  10,   8}, { 13,  11,   7,   6}, { 12,   8,   5, 131}, {  7,   4, 131, 131}}, // old before May 2013
+/*1066*/{{ 17,  13,  10,   8}, { 13,  10,   7,   6}, { 12,   8,   5, 131}, {  7,   4, 131, 131}},
+/*1333*/{{ 21,  16,  12,  10}, { 17,  12,   9,   7}, { 15,  10,   6, 132}, {  6,   5, 132, 132}},
+/*1600*/{{ 25,  19,  15,  12}, { 20,  14,  13,   8}, { 19,  12,   7, 133}, {  7,   6, 133, 133}},
 /*1866*/{{157, 150, 145, 142}, {151, 145, 141, 138}, {150, 142, 136, 134}, {141, 134, 134, 134}}
 	} },
 /* DDR4(1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
index 8b8d12166..d07c06c79 100644
--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
@@ -1,9 +1,10 @@
 
-#-- $Id: mba_def.initfile,v 1.47 2013/08/15 19:20:23 yctschan Exp $
+#-- $Id: mba_def.initfile,v 1.48 2013/09/30 21:29:38 yctschan Exp $
 #-- CHANGE HISTORY:
 #--------------------------------------------------------------------------------
 #-- Version:|Author: | Date:  | Comment:
 #-- --------|--------|--------|--------------------------------------------------
+#--     1.48|tschang | 9/30/13|add 10% margin to refresh check interval calculations
 #--     1.47|tschang | 8/15/13| HW259719 - dd2 only fix - ATTR_CENTAUR_EC_ENABLE_TRACE_LCL_CLK_GATE_CTRL to turn on clock gates
 #--     1.46|tschang | 7/17/13|updated refresh interval and refresh check interval calculations
 #--     1.45|tschang | 6/04/13|using ATTR_EFF_DRAM_RRD, etc timing parms for settings
@@ -2129,7 +2130,8 @@ define def_mba01_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[0][0] + ATTR_EFF_NUM_R
 define def_mba23_num_ranks = (ATTR_EFF_NUM_RANKS_PER_DIMM[1][0] + ATTR_EFF_NUM_RANKS_PER_DIMM[1][1]);
 define def_mba01_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba01_num_ranks));
 define def_mba23_refresh_interval = ((ATTR_EFF_DRAM_TRFI)/(8*def_mba23_num_ranks));
-define def_refresh_check_interval = (ATTR_EFF_DRAM_TRFI/8);  # same for both mba01 and mba23
+# mulitply by 1.1 to give it 10% margin
+define def_refresh_check_interval = ((ATTR_EFF_DRAM_TRFI/8) + ((ATTR_EFF_DRAM_TRFI/8)/10));  # same for both mba01 and mba23
 
 # MBAREF0Q   mba01 refresh settings
 #
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
index 7fe7da0ff..674c66982 100644
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
+++ b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.C,v 1.18 2013/09/19 19:02:12 bellows Exp $
+// $Id: mss_eff_config_thermal.C,v 1.19 2013/09/23 22:05:04 pardeik Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
 //          centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $
 //------------------------------------------------------------------------------
@@ -53,6 +53,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//   1.19  | pardeik  |23-SEP-13| initial support for the ras/cas increments
 //   1.18  | bellows  |19-SEP-13| fixed possible buffer overrun found by stradale
 //   1.17  | pardeik  |19-JUL-13| Use runtime throttles for IPL for scominit
 //         |          |         | Removed MRW safemode throttle stuff
@@ -332,6 +333,8 @@ extern "C" {
 	uint32_t cdimm_master_power_intercept;
 	uint32_t cdimm_supplier_power_slope;
 	uint32_t cdimm_supplier_power_intercept;
+	uint8_t ras_increment;
+	uint8_t cas_increment;
 
 	power_table_size = (sizeof(power_table))/(sizeof(power_data_t));
 
@@ -1083,6 +1086,11 @@ extern "C" {
 		return rc;
 	    }
 
+// Setup the RAS and CAS increments used in the throttling register
+// TODO:  base these values off of number of ranks and dram width
+	    ras_increment=0;
+	    cas_increment=1;
+
 // update output attributes
 	    rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
 			       &i_target_mba, runtime_throttle_n_per_mba);
@@ -1102,6 +1110,18 @@ extern "C" {
 		FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
 		return rc;
 	    }
+	    rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT,
+			       &i_target_mba, ras_increment);
+	    if (rc) {
+		FAPI_ERR("Error writing attribute ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT");
+		return rc;
+	    }
+	    rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT,
+			       &i_target_mba, cas_increment);
+	    if (rc) {
+		FAPI_ERR("Error writing attribute ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT");
+		return rc;
+	    }
 
 
 // Initialize the generic throttle attributes to be used for scominit