Need to update some HWPs to the latest version for 7/15 milestone

Change-Id: Iac5a5ccbd6ba569fbca44e2a925aec67d20a1baa
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1389
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

5 files changed, 426 insertions, 584 deletions

diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C
index 49c93e59b..d68bebeba 100644
--- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C
+++ b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: cen_mem_startclocks.C,v 1.7 2012/05/31 18:29:20 mfred Exp $
+// $Id: cen_mem_startclocks.C,v 1.9 2012/06/07 13:52:27 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2012
@@ -117,22 +117,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
     fapi::ReturnCode rc;
     uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data;
+    ecmdDataBufferBase scom_data(64);
+    ecmdDataBufferBase cfam_data(32);
 
 
 
     FAPI_INF("********* cen_mem_startclocks start *********");
     do
     {
-        rc_ecmd |= data.setBitLength(64);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer bit length.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-
         //
         // The following details are from the Common POR spreadsheet sections 20.1 and 21.1 and from the Centaur Chip Spec.
         //
@@ -142,15 +134,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x030F0013  bit(18)=0b0    , drop fence in GP3
         FAPI_DBG("Writing GP3 AND mask to clear chiplet fence (bit 18) ...");
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP3_FENCE_EN_BIT);
+        rc_ecmd |= scom_data.flushTo1();
+        rc_ecmd |= scom_data.clearBit(GP3_FENCE_EN_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear chiplet fence.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, data);
+        rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing GP3 AND mask 0x030F0013 (bit 18) to clear chiplet fence.");
@@ -160,15 +152,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x030F0014  bit(28)=0b1    , enable EDRAM, just chiplets with EDRAM logic
         FAPI_DBG("Writing GP3 OR mask to enable EDRAM (bit 28) ...");
-        rc_ecmd |= data.flushTo0();
-        rc_ecmd |= data.setBit(GP3_EDRAM_ENABLE_BIT);
+        rc_ecmd |= scom_data.flushTo0();
+        rc_ecmd |= scom_data.setBit(GP3_EDRAM_ENABLE_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to enable EDRAM.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, data);
+        rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing GP3 OR mask 0x030F0014 (bit 28) to enable EDRAM.");
@@ -183,17 +175,17 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
         //   Write SCOM      address 0x03000004  bit(0)=0b0, bit(1)=0b0    , clear mux selects in GP0
         FAPI_DBG("Writing GP0 AND mask to drop pervasive fence (bit 63) ...");
         FAPI_DBG("Writing GP0 AND mask to clear mux selects (bits 0-1) ...");
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP0_ABSTCLK_MUXSEL_BIT);
-        rc_ecmd |= data.clearBit(GP0_SYNCCLK_MUXSEL_BIT);
-        rc_ecmd |= data.clearBit(GP0_PERV_FENCE_BIT);
+        rc_ecmd |= scom_data.flushTo1();
+        rc_ecmd |= scom_data.clearBit(GP0_ABSTCLK_MUXSEL_BIT);
+        rc_ecmd |= scom_data.clearBit(GP0_SYNCCLK_MUXSEL_BIT);
+        rc_ecmd |= scom_data.clearBit(GP0_PERV_FENCE_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to drop pervasive fence and clear mux selects.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, data);
+        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bits 0,1,63) to drop pervasive fence and clear mux selects.");
@@ -203,15 +195,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x03000005  bit(11)=0b1        abist_mode_dc for core chiplets (core recovery)
         FAPI_DBG("Writing GP0 OR mask to set abist_mode_dc (bit 11) ...");
-        rc_ecmd |= data.flushTo0();
-        rc_ecmd |= data.setBit(GP0_ABIST_MODE_BIT);
+        rc_ecmd |= scom_data.flushTo0();
+        rc_ecmd |= scom_data.setBit(GP0_ABIST_MODE_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to set abist_mode_dc.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, data);
+        rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing GP0 OR mask 0x03000005 (bit 11) to set abist_mode_dc.");
@@ -221,14 +213,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x03030007  0x0000000000000000     Write CC Scan Region Reg, set all bits='0' prior clk start
         FAPI_DBG("Writing CC Scan Region Register to all zeros prior to clock start ...");
-        rc_ecmd |= data.flushTo0();
+        rc_ecmd |= scom_data.flushTo0();
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to flush Scan Region Register.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, data);
+        rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing CC Scan Region Register 0x03030007 to all zeros prior to clock start.");
@@ -242,14 +234,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x03030006  data=0x4FE0 0600 0000 0000    unicast, write CC clock region reg in MEM chiplet. start clocks
         FAPI_DBG("Writing CC Clock Region Register to 0x4FE0060000000000 to start array and nsl clocks ...");
-        rc_ecmd |= data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_NSL_ARY);
+        rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_NSL_ARY);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to start array and nsl clocks.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, data);
+        rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE0060000000000 to start array and nsl clocks.");
@@ -259,14 +251,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x03030006  data=0x4FE0 0E00 0000 0000    unicast, write CC clock region reg in MEM chiplet. start clocks
         FAPI_DBG("Writing CC Clock Region Register to 0x4FE00E0000000000 to start sl clocks ...");
-        rc_ecmd |= data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_ALL);
+        rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_ALL);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to start sl clocks.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, data);
+        rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE00E0000000000 to start sl clocks.");
@@ -276,15 +268,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Read SCOM       address 0x03030008  expect=0x0000 001F FFFF FFFF  unicast, read clock status reg in MEM chiplet
         FAPI_DBG("Reading CC Clock Status Register to see if clocks are running ...");
-        rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, data);
+        rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, scom_data);
         if ( rc )
         {
             FAPI_ERR("Error reading CC Clock Status Register 0x03030008.");
             break;
         }
-        if ( data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA )
+        if ( scom_data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA )
         {
-            FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA);
+            FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",scom_data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA);
             FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_CLOCK_STATUS);
             break;
         }
@@ -298,20 +290,20 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write CFAM      address 0x13        bit(02)=0b1       Set MemReset Stability Control
         FAPI_DBG("Writing FSI GP4 register (bit2) to set MemReset Stability control ...");
-        rc = fapiGetScom( i_target, CFAM_FSI_GP4_0x00001013, data);
+        rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
         if (rc)
         {
             FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013.");
             break;
         }
-        rc_ecmd |= data.setBit(FSI_GP4_MEMRESET_STABILITY_BIT);
+        rc_ecmd |= cfam_data.setBit(FSI_GP4_MEMRESET_STABILITY_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to set MemReset Stability control.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, CFAM_FSI_GP4_0x00001013, data);
+        rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
         if (rc)
         {
             FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 2) to set MemReset Stability control.");
@@ -321,20 +313,20 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write CFAM      address 0x13        bit(04)=0b1     Release D3PHY PLL Reset Control
         FAPI_DBG("Writing FSI GP4 register (bit4) to release D3PHY PLL Reset Control ...");
-        rc = fapiGetScom( i_target, CFAM_FSI_GP4_0x00001013, data);
+        rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
         if (rc)
         {
             FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013.");
             break;
         }
-        rc_ecmd |= data.setBit(FSI_GP4_DPHY_PLLRESET_BIT);
+        rc_ecmd |= cfam_data.setBit(FSI_GP4_DPHY_PLLRESET_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to release D3PHY PLL Reset Control.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, CFAM_FSI_GP4_0x00001013, data);
+        rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
         if (rc)
         {
             FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 4) to release D3PHY PLL Reset Control.");
@@ -348,15 +340,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x03000004  bit(3)=0b0    clear force_align in all Chiplets in GP0
         FAPI_DBG("Writing GP0 AND mask to clear force_align (bit 3) ...");
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP0_FORCE_ALIGN_BIT);
+        rc_ecmd |= scom_data.flushTo1();
+        rc_ecmd |= scom_data.clearBit(GP0_FORCE_ALIGN_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear force_align.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, data);
+        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 3) to clear force_align.");
@@ -366,15 +358,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 
         //   Write SCOM      address 0x03000004  bit(2)=0b0    clear flushmode_inhibit in Chiplet in GP0
         FAPI_DBG("Writing GP0 AND mask to clear flushmode_inhibit (bit 2) ...");
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT);
+        rc_ecmd |= scom_data.flushTo1();
+        rc_ecmd |= scom_data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT);
         if (rc_ecmd)
         {
             FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear flushmode_inhibit.",  rc_ecmd);
             rc.setEcmdError(rc_ecmd);
             break;
         }
-        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, data);
+        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
         if (rc)
         {
             FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 2) to clear flushmode_inhibit.");
@@ -401,6 +393,12 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
 This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 $Log: cen_mem_startclocks.C,v $
+Revision 1.9  2012/06/07 13:52:27  jmcgill
+use independent data buffers for cfam/scom accesses
+
+Revision 1.8  2012/06/06 20:04:59  jmcgill
+change FSI GP3/GP4/status register accesses from SCOM->CFAM
+
 Revision 1.7  2012/05/31 18:29:20  mfred
 Updates for RC checking and error messages, etc.
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
index 57d7a439c..2322a5a1b 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: mss_ddr_phy_reset.C,v 1.7 2012/05/31 18:27:54 mfred Exp $
+// $Id: mss_ddr_phy_reset.C,v 1.9 2012/07/18 16:27:39 mfred Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -72,6 +72,7 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
     uint32_t rc_ecmd = 0;
     uint32_t poll_count = 0;
     uint32_t done_polling = 0;
+    uint8_t is_simulation = 0;
     ecmdDataBufferBase i_data, j_data, k_data, l_data;
 
 
@@ -581,6 +582,205 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
         }
 
 
+
+        // Work-around required to get alignment in simulation
+        // Read the ATTR_IS_SIMULATION attribute
+        rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation);
+        if (rc)
+        {
+            FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION.");
+            break;
+        }
+        if (is_simulation)
+        {
+            FAPI_DBG("Step 11.1 (SIM ONLY): Write '8000'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
+            rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008000ull);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.",  rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
+                break;
+            }
+    
+    
+            FAPI_DBG("Step 11.2 (SIM ONLY): Write '8080'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
+            rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008080ull);
+            if (rc_ecmd)
+            {
+                FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.",  rc_ecmd);
+                rc.setEcmdError(rc_ecmd);
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
+                break;
+            }
+            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
+            if (rc)
+            {
+                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
+                break;
+            }
+        }
+
   
         //
         // 12.Wait at least 32 memory clock cycles.
@@ -621,7 +821,6 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
 
 
 
-
     } while(0);
 
     FAPI_INF("********* mss_ddr_phy_reset complete *********");
@@ -640,6 +839,12 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: mss_ddr_phy_reset.C,v $
+Revision 1.9  2012/07/18 16:27:39  mfred
+Check for ATTR_IS_SIMULATION attribute instead of use compiler switch.
+
+Revision 1.8  2012/06/07 22:30:25  jmcgill
+add sim only inits for phase rotator alignment (wrapped in SIM_ONLY ifdef for now)
+
 Revision 1.7  2012/05/31 18:27:54  mfred
 Removing some config settings that are now done in config file.  See Gary Van Huben note May 3, 2012
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index 85cbaa184..f3400b38b 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -1,25 +1,26 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -27,6 +28,11 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.33   | jdsloat  | 6/26/12 | Added rtt_nom rank by rank value.
+//  1.32   | jdsloat  | 6/11/12 | Fixed Attributes: RTT_NOM, CL, DRAM_WR within the MRS load.
+//  1.31   | bellows  | 5/24/12 | Removed GP Bit 
+//  1.30   | bellows  | 5/03/12 | MODEQ reg writes (HW191966). Has GP Bit for backwards compatibility
+//  1.29   | bellows  | 5/03/12 | Workaround removed for (HW199042). Use new hardware or workaround.initfile after phyreset
 //  1.28   | bellows  | 4/11/12 | fixed missing fapi:: for targets and return codes
 //  1.27   | bellows  | 4/11/12 | Workaround for fixing up phy config reset (HW199042)
 //  1.26   | jdsloat  | 3/20/12 | MRS bank fixe to remove reverse in ccs_inst_arry0
@@ -72,7 +78,7 @@
 //  Centaur function Includes
 //----------------------------------------------------------------------
 #include <mss_funcs.H>
-
+#include "cen_scom_addresses.H"
 
 //----------------------------------------------------------------------
 //  Constants
@@ -83,236 +89,10 @@ const uint8_t MRS0_BA = 0;
 const uint8_t MRS1_BA = 1;
 const uint8_t MRS2_BA = 2;
 const uint8_t MRS3_BA = 3;
-const uint16_t GP4_REG_0x1013 = 0x1013;
 
 
 extern "C" {
 
-// WORKAROUND START
-// THIS NEEDS TO BE REMOVED = WORKAROUNDS FOR HARDWARE RESET PROBLEM
-  fapi::ReturnCode mss_putscom(fapi::Target target,uint64_t scom_address_64, uint64_t data_64) {
-    // Target is centaur.mba
-    // This procedure does a putscom to an address with constant data
-    ecmdDataBufferBase data_buffer_64(64);
-    data_buffer_64.flushTo0();
-    uint32_t rc_ecmd=0;
-    fapi::ReturnCode rc;
-
-    rc_ecmd=data_buffer_64.setDoubleWord(0,data_64);
-    if(rc_ecmd)
-    {
-      rc=rc_ecmd;
-      FAPI_ERR("ecmddatabuffer operation failed");
-
-    }
-    rc=fapiPutScom(target,scom_address_64,data_buffer_64);
-    if(!rc.ok()){
-      FAPI_ERR("putscom error occurred");
-      return(rc);
-    } 
-    return rc;
-  }
-
-  fapi::ReturnCode mss_workaround_phy_reset(fapi::Target target) {
-    // Target is centaur.mba
-    // This procedure does the series of putscoms to fix HW199042 where the phy resets the state of the config
-    // This only supports one config and only the known bad registers and allows calibration to pass
-    fapi::ReturnCode rc;
-    uint8_t core;
-
-    rc=mss_putscom( target, 0x8000C0160301143FULL,    0x000000000000BF28ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800000370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800000370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800004370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800004370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800008370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800008370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x80000C370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x80000C370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800010370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800010370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800100370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800100370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800104370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800104370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800108370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800108370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x80010C370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x80010C370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800110370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-    rc=mss_putscom( target, 0x800110370301143FULL,    0x0000000000001000ULL  ); if(rc) return(rc);
-
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &target, core);
-    if(rc) return rc;
-
-    if(core == 0) {
-      rc=mss_putscom( target, 0x800000040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800000050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800001040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800001050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800002040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800002050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800003040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800003050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800004040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800004050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800005040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800005050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800006040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800006050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800007040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800007050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800008040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800008050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800009040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800009050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000A040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000A050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000B040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000B050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000C040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000C050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000D040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000D050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000E040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000E050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000F040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000F050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800010040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800010050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800011040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800011050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800012040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800012050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800013040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800013050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800100040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800100050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800101040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800101050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800102040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800102050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800103040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800103050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800104040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800104050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800105040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800105050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800106040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800106050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800107040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800107050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800108040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800108050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800109040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800109050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010A040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010A050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010B040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010B050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010C040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010C050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010D040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010D050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010E040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010E050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010F040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010F050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800110040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800110050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800111040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800111050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800112040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800112050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800113040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800113050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-    } 
-    else { 
-      rc=mss_putscom( target, 0x800000040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800000050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800001040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800001050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800002040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800002050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800003040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800003050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800004040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800004050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800005040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800005050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800006040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800006050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800007040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800007050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800008040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800008050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800009040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800009050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000A040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000A050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000B040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000B050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000C040301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000C050301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000D040301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000D050301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000E040301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000E050301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000F040301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80000F050301143FULL, 0x000000000000C0C0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800010040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800010050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800011040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800011050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800012040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800012050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800013040301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800013050301143FULL, 0x0000000000000C00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800100040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800100050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800101040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800101050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800102040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800102050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800103040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800103050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800104040301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800104050301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800105040301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800105050301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800106040301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800106050301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800107040301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800107050301143FULL, 0x000000000000C000ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800108040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800108050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800109040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800109050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010A040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010A050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010B040301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010B050301143FULL, 0x0000000000000F00ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010C040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010C050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010D040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010D050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010E040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010E050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010F040301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x80010F050301143FULL, 0x000000000000C300ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800110040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800110050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800111040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800111050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800112040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800112050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800113040301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-      rc=mss_putscom( target, 0x800113050301143FULL, 0x0000000000000CC0ULL   ); if(rc) return(rc);
-    }
-    return rc;
-  }
-// WORKAROUND END: END OF REMOVAL
-
 using namespace fapi;
 
 ReturnCode mss_rcd_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt);
@@ -325,9 +105,6 @@ ReturnCode mss_draminit(Target& i_target)
 {
     // Target is centaur.mba
     //
-  FAPI_INF("WARNING: Calling workaround_phy_reset");
-  mss_workaround_phy_reset(i_target);
-  FAPI_INF("WARNING: Done workaround_phy_reset");
 
     ReturnCode rc;
     uint32_t port_number;
@@ -453,19 +230,14 @@ ReturnCode mss_deassert_force_mclk_low (Target& i_target)
 
     FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++");
 
-    // Read GP4 
-    rc = fapiGetCfamRegister(i_target, GP4_REG_0x1013, data_buffer);
-    if(rc)return rc;
-    // set bit 3 high
-    rc_num = data_buffer.setBit(4);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    //  Stick it back into GP4
-    rc = fapiPutCfamRegister(i_target, GP4_REG_0x1013, data_buffer);
-    if(rc)return rc;
+
+    rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
+    if(rc) return rc;
+    rc_num = data_buffer.setBit(63);
+    rc.setEcmdError( rc_num);
+    if(rc) return rc;
+    rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
+    if(rc) return rc;
 
     return rc;
 }
@@ -492,6 +264,7 @@ ReturnCode mss_assert_resetn_drive_mem_clks(
     rc_num = rc_num | resetn_1.setBit(0);
     ecmdDataBufferBase reset_recover_1(1);
     ecmdDataBufferBase copy_spare_cke_1(1);
+    rc_num = rc_num | copy_spare_cke_1.setBit(0); // mdb : clk enable on for spare
 
     FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN, DRIVING MEM CLKS +++++++++++++++++++++");
 
@@ -790,6 +563,40 @@ ReturnCode mss_mrs_load(
         dram_bl = 0x40;
     }
 
+    if (dram_wr == 16)
+    {
+	dram_wr = 0x00;
+    }
+    else if (dram_wr == 5)
+    {
+        dram_wr = 0x80;
+    }
+    else if (dram_wr == 6)
+    {
+        dram_wr = 0x40;
+    }
+    else if (dram_wr == 7)
+    {
+        dram_wr = 0xC0;
+    }
+    else if (dram_wr == 8)
+    {
+        dram_wr = 0x20;
+    }
+    else if (dram_wr == 10)
+    {
+        dram_wr = 0xA0;
+    }
+    else if (dram_wr == 12)
+    {
+        dram_wr = 0x60;
+    }
+    else if (dram_wr == 14)
+    {
+        dram_wr = 0xE0;
+    }
+
+
     if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL)
     {
         read_bt = 0x00;
@@ -803,7 +610,7 @@ ReturnCode mss_mrs_load(
     {
         dram_cl = (dram_cl - 4) << 1; 
     }
-    else if ((dram_cl > 11)&&(dram_cl > 16))
+    else if ((dram_cl > 11)&&(dram_cl < 17))
     {
         dram_cl = ((dram_cl - 12) << 1) + 1;   
     }
@@ -827,8 +634,6 @@ ReturnCode mss_mrs_load(
         dll_reset = 0x00;
     }
 
-    dram_wr = mss_reverse_8bits(dram_wr);
-
     if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
     {
         dll_precharge = 0x00;
@@ -1096,13 +901,13 @@ ReturnCode mss_mrs_load(
 
                     rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0);
                     rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 2, 1, 0);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 2, 1, 0);
                     rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0);
                     rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 6, 1, 2);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 6, 1, 1);
                     rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0);
                     rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 9, 1, 3);
+                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 9, 1, 2);
                     rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1);
                     rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0);
                     rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0);
@@ -1129,7 +934,7 @@ ReturnCode mss_mrs_load(
                     rc_num = rc_num | mrs2.insert((uint8_t) auto_sr, 6, 1);
                     rc_num = rc_num | mrs2.insert((uint8_t) sr_temp, 7, 1);
                     rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][0], 9, 2);
+                    rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2);
                     rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 10, 6);
 
         	    rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index 2b8841aeb..49f7a8772 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -1,25 +1,26 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -43,6 +44,10 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.20   | jdsloat  |21-MAY-12| Typo fix, addresses moved to cen_scom_addresses.H, moved per cal settings to initfile
+//  1.19   | jdsloat  |08-MAY-12| All Refresh controls moved to initfile, changed to just enable refresh
+//  1.18   | jdsloat  |07-MAY-12| Fixed refresh interval, trfc, ref check interval bit ordering
+//  1.16   | bellows  |04-MAY-12| Temporary remove of attr read of freq until method defined
 //  1.15   | jdsloat  |16-APR-12| TRFC fixed to insert the right aligned 8 bits
 //  1.15   | jdsloat  |12-Mar-12| Attribute upgrade for cronusflex 12.4 ... trfc to uint32
 //  1.14   | jdsloat  |07-Mar-12| Fixed iml_complete to match target
@@ -81,6 +86,10 @@
 //----------------------------------------------------------------------
 #include <mss_funcs.H>
 
+//----------------------------------------------------------------------
+//  Address Includes
+//----------------------------------------------------------------------
+#include <cen_scom_addresses.H>
 
 
 extern "C" {
@@ -98,22 +107,8 @@ ReturnCode mss_enable_power_management(Target& i_target);
 ReturnCode mss_enable_control_bit_ecc(Target& i_target);
 ReturnCode mss_ccs_mode_reset(Target& i_target);
 
-//----------------------------------------------------------------------
-//  Constants - Addresses - TODO: to be moved to cen_scom_addresses.H later
-//----------------------------------------------------------------------
-const uint32_t MBA01_REF0Q_0x03010432 = 0x03010432;
-//Master Registers
-const uint64_t DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL = 0x8000C00B0301143FULL;
-const uint64_t DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL = 0x8001C00B0301143FULL;
-//ZQCal Control Registers - currently not being used, need to write in settings for these regs
-const uint64_t DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301143FULL = 0x8000C00F0301143FULL;
-const uint64_t DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143FULL = 0x8001C00F0301143FULL;
-const uint32_t MBSSQ_0x02011417 = 0x02011417;
-// Power Management addresses
-const uint32_t MBA01_PM0Q_0x03010434 = 0x03010434;
-// ECC enable addresses
-const uint32_t MBS_ECC0_MBSECCQ_0x0201144A = 0x0201144A;
-const uint32_t MBS_ECC1_MBSECCQ_0x0201148A = 0x0201148A;
+
+
 
 ReturnCode mss_draminit_mc (Target& i_target)
 {
@@ -121,6 +116,7 @@ ReturnCode mss_draminit_mc (Target& i_target)
 //
     ReturnCode rc;
     std::vector<fapi::Target> l_mbaChiplets;
+    uint32_t rc_num  = 0;
 
     // Get associated MBA's on this centaur
     rc=fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets);
@@ -148,23 +144,35 @@ ReturnCode mss_draminit_mc (Target& i_target)
            return rc;
         }
 
-        // Step Three: Setup Refresh Controls
-        FAPI_INF( "+++ Setting Up Refresh Controls +++");
-        rc = mss_start_refresh(l_mbaChiplets[i],i_target);
+        // Step Three: Enable Refresh
+        FAPI_INF( "+++ Enabling Refresh +++");
+	ecmdDataBufferBase mba01_ref0q_data_buffer_64(64);
+	rc = fapiGetScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
+	if(rc) return rc;
+	//Bit 0 is enable		   
+	rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0);
+	rc = fapiPutScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
         if(rc)
         {
-           FAPI_ERR("---Error During Refresh Control Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+           FAPI_ERR("---Error During Refresh Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
            return rc;
         }
+	if (rc_num)
+	{
+	    FAPI_ERR( "Refresh Enable: Error setting up buffers");
+	    rc.setEcmdError(rc_num);
+	    return rc;
+	}
 
         // Step Four: Setup Periodic Cals
-        FAPI_INF( "+++ Setting Up Periodic Cals +++");
-        rc = mss_enable_periodic_cal(l_mbaChiplets[i]);
-        if(rc)
-        {
-           FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
+        FAPI_INF( "+++ Skipping Periodic Cals +++");
+        // FAPI_INF( "+++ Setting Up Periodic Cals +++");
+        // rc = mss_enable_periodic_cal(l_mbaChiplets[i]);
+        // if(rc)
+        // {
+        //    FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+        //    return rc;
+        // }
 
         // Step Five: Setup Power Management
         FAPI_INF( "+++ Setting Up Power Management +++");
@@ -189,100 +197,6 @@ ReturnCode mss_draminit_mc (Target& i_target)
     return rc;
 }
 
-ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget)
-{
-    //Target MBA, centaur
-
-    //Variables
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-
-    uint32_t refresh_interval = 0;
-    uint32_t refresh_interval_reset = 0;
-    uint32_t num_ranks = 0;
-
-    //Bit 0 is enable
-    //bit 4..7 cfg_refresh_priority_threshold
-    //bit 8..18 cfg_refresh_interval
-    //bit 19..29 cfg_refresh_reset_interval
-    //bit 30..39 cfg_trfc
-    //bit 40..49 cfg_refr_tsv_stack
-    //bit 50..60 cfg_refr_check_interval
-    ecmdDataBufferBase mba01_ref0q_data_buffer_64(64);
-
-
-    uint32_t dimm_freq;
-    rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &i_centarget, dimm_freq);
-    if(rc) return rc; 
-
-    //Configure Refresh based on system attributes MBA01
-    rc = fapiGetScom(i_mbatarget, MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
-    if(rc) return rc;
-
-    //Configure Refresh Priority  Hard coded to 8 refreshes 
-    rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(4);
-    
-    //Configure Refresh Interval
-    //MBA01 - Get number of ranks, then calculate refresh rate.  
-
-    // FAPI ATTR GET NUM RANKS
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_mbatarget, num_ranks_array);
-    if(rc) return rc;
-
-    // Adding them up
-    num_ranks = num_ranks_array[0][0] + num_ranks_array[0][1]+ num_ranks_array[1][0] + num_ranks_array[1][1];
-
-    if (num_ranks == 0)
-    {
-        FAPI_INF("+++ No Configured Ranks for current target +++");
-    }
-    else
-    {
-        //Now program in the refresh rate for MBA01
-
-        // TODO: Waiting for tREFI to appear as attribute in XML file 
-        // Until then tREFI will be hardcoded 
-        uint16_t trefi = 6240; // given in Nclks = 3.9us (DDR3 Jedec) at 1600
-        //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TREFI, &i_target, num_ranks_array);
-        //if(rc) return rc;
-
-        refresh_interval = (trefi/num_ranks)/8;
-        refresh_interval_reset = refresh_interval - 1;
-        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval, 8,10);
-        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval, 50,10);
-        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval_reset,19,10);
-        //tRFC
-        uint32_t trfc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TRFC, &i_mbatarget, trfc);
-        if(rc) return rc;
-
-	FAPI_INF("TRFC: 0x%08X ", trfc);
-
-        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(trfc, 30, 8, 24);
-        rc_num = rc_num | mba01_ref0q_data_buffer_64.insert((uint8_t) 0, 38, 2);
-
-        //Enable Refresh
-        //MBA01
-        rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0);
-        rc = fapiPutScom(i_mbatarget, MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
-        if(rc) return rc;
-
-        if (rc_num)
-        {
-            FAPI_ERR( "mss_start_refresh: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-
-        FAPI_INF("+++ Refresh Enabled +++");
-
-    }
-
-    return rc;
-}
-
 ReturnCode mss_enable_periodic_cal (Target& i_target)
 {
     //Target MBA
@@ -293,47 +207,6 @@ ReturnCode mss_enable_periodic_cal (Target& i_target)
     ReturnCode rc_buff;
     uint32_t rc_num  = 0;
 
-    //PER CAL Types  
-    //MBA01
-
-    // TODO: Waiting for these attributes in XML
-    // Used to pull enable bits.
-    //uint8_t memcal_interval;
-    //rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_interval);
-    //if(rc) return rc;
-    //uint8_t zqcal_interval;
-    //rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zqcal_interval);
-    //if(rc) return rc;
-
-    uint32_t p0_per_zqcal_mba01_ena = 1;
-    uint32_t p0_per_sysclk_mba01_ena = 1;
-    uint32_t p0_per_rd_ck_mba01_ena = 1;
-    uint32_t p0_per_rd_dqs_mba01_ena = 1;
-    uint32_t p0_per_rd_center_mba01_ena = 1;
-    uint32_t p1_per_zqcal_mba01_ena = 1;
-    uint32_t p1_per_sysclk_mba01_ena = 1;
-    uint32_t p1_per_rd_ck_mba01_ena = 1;
-    uint32_t p1_per_rd_dqs_mba01_ena = 1;
-    uint32_t p1_per_rd_center_mba01_ena = 1;
-
-    // TODO: waiting for ZQ Cal and Mem Cal intevals in XML
-    // Example one hot code.  Not the real order/decode. 
-    //p0_per_zqcal_mba01_ena = 0x1 & zqcal_interval;
-    //p1_per_zqcal_mba01_ena = 0x2 & zqcal_interval >> 1;
-    //p0_per_sysclk_mba01_ena = 0x1 & memcal_interval;
-    //p0_per_rd_ck_mba01_ena = (0x2 & memcal_interval) >> 1;
-    //p0_per_rd_dqs_mba01_ena = (0x4 & memcal_interval) >> 2;
-    //p0_per_rd_center_mba01_ena = (0x8 & memcal_interval) >> 3;
-    //p1_per_sysclk_mba01_ena = 0x1 & memcal_interval;
-    //p1_per_rd_ck_mba01_ena = (0x2 & memcal_interval) >> 1;
-    //p1_per_rd_dqs_mba01_ena = (0x4 & memcal_interval) >> 2;
-    //p1_per_rd_center_mba01_ena = (0x8 & memcal_interval) >> 3;
-
-    //DDR Calibration Register Addresses - currently not in use, need to write in settings for these regs
-    //uint32_t mba01_cal0q = 0x0301040F;
-    //uint32_t mba01_cal1q = 0x03010410;
-    //uint32_t mba01_cal2q = 0x03010411;
-
  
     ecmdDataBufferBase mba01_data_buffer_64_p0(64);
     ecmdDataBufferBase mba01_data_buffer_64_p1(64);
@@ -342,11 +215,11 @@ ReturnCode mss_enable_periodic_cal (Target& i_target)
     //ALL CALS CURRENTLY SET AS ON, ONLY CHECK RANK PAIRS PRESENT
     //***mba01 Setup
     rc_num = rc_num | mba01_data_buffer_64_p0.flushTo0();
-    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL, mba01_data_buffer_64_p0);
+    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0);
     if(rc) return rc;
 
     rc_num = rc_num | mba01_data_buffer_64_p1.flushTo0();
-    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL, mba01_data_buffer_64_p1);
+    rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, mba01_data_buffer_64_p1);
     if(rc) return rc;
 
     uint8_t primary_rank_group0_array[2]; //[rank]
@@ -406,57 +279,14 @@ ReturnCode mss_enable_periodic_cal (Target& i_target)
        rc_num = rc_num | mba01_data_buffer_64_p1.setBit(51);
     }
 
-   
-    
-    //p0
-    if(p0_per_zqcal_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(52);
-    }
-    if(p0_per_sysclk_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(53);
-    }
-    if(p0_per_rd_ck_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(54);
-    }
-    if(p0_per_rd_dqs_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(55);
-    }
-    if(p0_per_rd_center_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p0.setBit(56);
-    }
+    //Start the periodic Cal
+     rc_num = rc_num | mba01_data_buffer_64_p1.setBit(61);
 
-    //p1
-    if(p1_per_zqcal_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(52);
-    }
-    if(p1_per_sysclk_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(53);
-    }
-    if(p1_per_rd_ck_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(54);
-    }
-    if(p1_per_rd_dqs_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(55);
-    }
-    if(p1_per_rd_center_mba01_ena == 1)
-    {
-       rc_num = rc_num | mba01_data_buffer_64_p1.setBit(56);
-    }
-    
     //Write the mba_p01_PER_CAL_CFG_REG
-    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL, mba01_data_buffer_64_p0);
+    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0);
     if(rc) return rc;
     FAPI_INF("+++ Periodic Calibration Enabled p0+++");
-    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL, mba01_data_buffer_64_p1);
+    rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, mba01_data_buffer_64_p1);
     if(rc) return rc;
     FAPI_INF("+++ Periodic Calibration Enabled p1+++");
 
@@ -515,7 +345,7 @@ ReturnCode mss_enable_control_bit_ecc (Target& i_target)
     rc = fapiGetScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64);
     if(rc) return rc;
 
-    rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc0_data_buffer_64);
+    rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64);
     if(rc) return rc;
 
     // Enable Memory ECC Check/Correct for MBA01
@@ -540,7 +370,7 @@ ReturnCode mss_enable_control_bit_ecc (Target& i_target)
     rc = fapiPutScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64);
     if(rc) return rc;
 
-    rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc0_data_buffer_64);
+    rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64);
     if(rc) return rc;
 
     FAPI_INF("+++ mss_enable_control_bit_ecc complete +++");
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index dd10ac4c7..c07e9edc1 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -1,25 +1,26 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -27,6 +28,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.28   | bellows  |02-May-12| cal ranks are 4 bits, this needed to be adjusted
 //  1.26   | asaetow  |12-Apr-12| Added "if(rc) return rc;" at line 180.
 //  1.25   | asaetow  |06-Apr-12| Added "if(rc) return rc;" at line 165.
 //  1.24   | asaetow  |03-Apr-12| Changed FAPI_INF to FAPI_ERR where applicable from lines 275 to 324, per Mike Jones.
@@ -146,8 +148,8 @@ ReturnCode mss_draminit_training(Target& i_target)
     rc_num = rc_num | data_buffer_20.flushTo0();
     ecmdDataBufferBase read_compare_buffer_1(1);
     rc_num = rc_num | read_compare_buffer_1.flushTo0();
-    ecmdDataBufferBase rank_cal_buffer_3(3); 
-    rc_num = rc_num | rank_cal_buffer_3.flushTo0();
+    ecmdDataBufferBase rank_cal_buffer_4(4); 
+    rc_num = rc_num | rank_cal_buffer_4.flushTo0();
     ecmdDataBufferBase ddr_cal_enable_buffer_1(1);
     ecmdDataBufferBase ccs_end_buffer_1(1);
     rc_num = rc_num | ccs_end_buffer_1.flushTo1();
@@ -160,7 +162,7 @@ ReturnCode mss_draminit_training(Target& i_target)
     ecmdDataBufferBase resetn_buffer_1(1);
     rc_num = rc_num | resetn_buffer_1.setBit(0);
     ecmdDataBufferBase cal_timeout_cnt_mult_buffer_2(2);
-    rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo0();
+    rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo1();
 
     ecmdDataBufferBase data_buffer_64(64);
     if(rc_num)
@@ -226,15 +228,17 @@ ReturnCode mss_draminit_training(Target& i_target)
             FAPI_INF( "+++++++++++++++ Sending init cal on rank group: %d +++++++++++++++", group);
             rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, 0);
             if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
+            FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0],
+                      group, primary_ranks_array[group][1]);
             if(primary_ranks_array[group][0] == INVALID)
             {
-                rc_num = rc_num | rank_cal_buffer_3.insert(primary_ranks_array[group][1], 0, 3, 0);
+                rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][1], 0, 4, 4); // 8 bit storage, need last 4 bits
             }
             else
             {
-                rc_num = rc_num | rank_cal_buffer_3.insert(primary_ranks_array[group][0], 0, 3, 0);
+                rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][0], 0, 4, 4); // 8 bit storage, need last 4 bits
             }
-            rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
+            rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_4, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
             if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
             FAPI_INF( "+++++++++++++++ Execute CCS array +++++++++++++++");
             rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
@@ -278,7 +282,7 @@ ReturnCode mss_check_cal_status(
         rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64);
         if(rc) return rc;
     }
-    while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) && (!cal_error_buffer_64.isBitSet(cal_error_reg_offset)) && (poll_count <= 5))
+    while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) && (!cal_error_buffer_64.isBitSet(cal_error_reg_offset)) && (poll_count <= 20))
     {
         FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d in progress. Poll count: %d +++++++++++++++", i_port, i_group, poll_count);
         poll_count++;