diff options
| author | Van Lee <vanlee@us.ibm.com> | 2012-07-18 13:34:08 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-07-18 19:34:56 -0500 |
| commit | 0101e2e19dc660a13fa7546ed4836395f2c719e3 (patch) | |
| tree | ae092fb045a093b028730b87199a8ab726987bc7 | |
| parent | 49c2bbaf5fb75d534a2f08ef0a4e9fafcf847ebe (diff) | |
| download | talos-hostboot-0101e2e19dc660a13fa7546ed4836395f2c719e3.tar.gz talos-hostboot-0101e2e19dc660a13fa7546ed4836395f2c719e3.zip | |
Need to update some HWPs to the latest version for 7/15 milestone
Change-Id: Iac5a5ccbd6ba569fbca44e2a925aec67d20a1baa
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1389
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
12 files changed, 2106 insertions, 1455 deletions
diff --git a/src/usr/hwpf/hwp/bus_training/edi_regs.h b/src/usr/hwpf/hwp/bus_training/edi_regs.h index b6d28b971..313b14b83 100644 --- a/src/usr/hwpf/hwp/bus_training/edi_regs.h +++ b/src/usr/hwpf/hwp/bus_training/edi_regs.h @@ -42,7 +42,7 @@ //----------------------------------------------------- // Constant file for edi_reg_attribute.txt_fixed // File generated at 16:23 on 8/31/2011 using system_pervasive/common/tools/CreateConstantsH.pl -// $Id: edi_regs.h,v 1.7 2012/05/17 08:32:23 varkeykv Exp $ +// $Id: edi_regs.h,v 1.8 2012/05/21 12:22:01 varkeykv Exp $ // $URL: $ // // *!************************************************************************** @@ -61,7 +61,7 @@ //FROM EDI_REGS typedef enum { - tx_mode_pl, +tx_mode_pl, tx_cntl_stat_pl, tx_spare_mode_pl, tx_bist_stat_pl, @@ -72,6 +72,8 @@ typedef enum { tx_fir_mask_pl, tx_fir_error_inject_pl, tx_mode_fast_pl, + tx_tdr_stat_pl, + tx_cntl_gcrmsg_pl, tx_clk_mode_pg, tx_spare_mode_pg, tx_cntl_stat_pg, @@ -87,7 +89,6 @@ typedef enum { tx_id1_pg, tx_id2_pg, tx_id3_pg, - tx_minikerf_pg, tx_clk_cntl_gcrmsg_pg, tx_ffe_mode_pg, tx_ffe_main_pg, @@ -95,6 +96,7 @@ typedef enum { tx_ffe_margin_pg, tx_bad_lane_enc_gcrmsg_pg, tx_sls_lane_enc_gcrmsg_pg, + tx_wt_seg_enable_pg, tx_lane_disabled_vec_0_15_pg, tx_lane_disabled_vec_16_31_pg, tx_sls_lane_mux_gcrmsg_pg, @@ -110,19 +112,24 @@ typedef enum { tx_ber_cntl_sls_pp, tx_cntl_pp, tx_reset_cfg_pp, + tx_tdr_cntl1_pp, + tx_tdr_cntl2_pp, + tx_tdr_cntl3_pp, tx_impcal_pb, tx_impcal_nval_pb, tx_impcal_pval_pb, tx_impcal_p_4x_pb, tx_impcal_swo1_pb, tx_impcal_swo2_pb, + tx_analog_iref_pb, + tx_minikerf_pb, + tx_init_version_pb, + tx_scratch_reg_pb, rx_mode_pl, rx_cntl_pl, rx_spare_mode_pl, rx_prot_edge_status_pl, rx_bist_stat_pl, - rx_eyeopt_mode_pl, - rx_eyeopt_stat_pl, rx_offset_even_pl, rx_offset_odd_pl, rx_amp_val_pl, @@ -156,27 +163,29 @@ typedef enum { rx_eye_width_status_pl, rx_eye_width_cntl_pl, rx_dfe_clkadj_pl, + rx_trace_pl, + rx_servo_ber_count_pl, + rx_eye_opt_stat_pl, rx_clk_mode_pg, rx_spare_mode_pg, + rx_stop_cntl_stat_pg, rx_mode_pg, rx_bus_repair_pg, rx_grp_repair_vec_0_15_pg, rx_grp_repair_vec_16_31_pg, - rx_recal_mode_pg, + rx_stop_addr_lsb_pg, + rx_stop_mask_lsb_pg, rx_reset_act_pg, rx_id1_pg, rx_id2_pg, rx_id3_pg, rx_minikerf_pg, - rx_bist_cntl_pg, rx_sls_mode_pg, rx_training_start_pg, rx_training_status_pg, rx_recal_status_pg, rx_timeout_sel_pg, rx_fifo_mode_pg, - rx_state_debug_pg, - rx_state_val_pg, rx_sls_status_pg, rx_fir1_pg, rx_fir2_pg, @@ -210,7 +219,7 @@ typedef enum { rx_misc_analog_pg, rx_dyn_rpr_pg, rx_dyn_rpr_gcrmsg_pg, - rx_dyn_rpr_err_tallying_pg, + rx_dyn_rpr_err_tallying1_pg, rx_eo_final_l2u_gcrmsgs_pg, rx_gcr_msg_debug_dest_ids_pg, rx_gcr_msg_debug_src_ids_pg, @@ -219,7 +228,6 @@ typedef enum { rx_dyn_recal_pg, rx_wt_clk_status_pg, rx_dyn_recal_config_pg, - rx_servo_recal_gcrmsg_pg, rx_dyn_recal_gcrmsg_pg, rx_wiretest_pll_cntl_pg, rx_eo_step_cntl_pg, @@ -237,11 +245,20 @@ typedef enum { rx_tx_lane_info_gcrmsg_pg, rx_err_tallying_gcrmsg_pg, rx_trace_pg, + rx_rc_step_cntl_pg, + rx_eo_recal_pg, + rx_servo_ber_count_pg, + rx_func_state_pg, + rx_dyn_rpr_debug_pg, + rx_dyn_rpr_err_tallying2_pg, + rx_result_chk_pg, + rx_ber_chk_pg, + rx_sls_rcvy_fin_gcrmsg_pg, rx_wiretest_pp, - rx_mode_pp, + rx_mode1_pp, rx_cntl_pp, rx_dyn_recal_timeouts_pp, - rx_servo_recal_gcrmsg_pp, + rx_mode2_pp, rx_ber_cntl_pp, rx_ber_mode_pp, rx_servo_to1_pp, @@ -250,7 +267,19 @@ typedef enum { rx_dfe_config_pp, rx_dfe_timers_pp, rx_reset_cfg_pp, + rx_recal_to1_pp, + rx_recal_to2_pp, + rx_recal_to3_pp, + rx_recal_cntl_pp, + rx_trace_pp, + rx_bist_gcrmsg_pp, + rx_scope_cntl_pp, + rx_fir_reset_pb, + rx_fir_pb, + rx_fir_mask_pb, + rx_fir_error_inject_pb, rx_fir_msg_pb, + ei4_tx_mode_pl, ei4_tx_cntl_stat_pl, ei4_tx_spare_mode_pl, @@ -277,10 +306,10 @@ typedef enum { ei4_tx_id1_pg, ei4_tx_id2_pg, ei4_tx_id3_pg, - ei4_tx_minikerf_pg, ei4_tx_clk_cntl_gcrmsg_pg, ei4_tx_bad_lane_enc_gcrmsg_pg, ei4_tx_sls_lane_enc_gcrmsg_pg, + ei4_tx_wt_seg_enable_pg, ei4_tx_pc_ffe_pg, ei4_tx_misc_analog_pg, ei4_tx_lane_disabled_vec_0_15_pg, @@ -288,6 +317,16 @@ typedef enum { ei4_tx_sls_lane_mux_gcrmsg_pg, ei4_tx_dyn_rpr_pg, ei4_tx_slv_mv_sls_ln_req_gcrmsg_pg, + ei4_tx_rdt_cntl_pg, + ei4_rx_dll_cal_cntl_pg, + ei4_rx_dll1_setpoint1_pg, + ei4_rx_dll1_setpoint2_pg, + ei4_rx_dll1_setpoint3_pg, + ei4_rx_dll2_setpoint1_pg, + ei4_rx_dll2_setpoint2_pg, + ei4_rx_dll2_setpoint3_pg, + ei4_rx_dll_filter_mode_pg, + ei4_rx_dll_analog_tweaks_pg, ei4_tx_wiretest_pp, ei4_tx_mode_pp, ei4_tx_sls_gcrmsg_pp, @@ -297,13 +336,12 @@ typedef enum { ei4_tx_ber_cntl_sls_pp, ei4_tx_cntl_pp, ei4_tx_reset_cfg_pp, + ei4_tx_tdr_cntl2_pp, + ei4_tx_tdr_cntl3_pp, ei4_rx_mode_pl, ei4_rx_cntl_pl, ei4_rx_spare_mode_pl, - ei4_rx_prot_edge_status_pl, ei4_rx_bist_stat_pl, - ei4_rx_eyeopt_mode_pl, - ei4_rx_eyeopt_stat_pl, ei4_rx_offset_even_pl, ei4_rx_offset_odd_pl, ei4_rx_amp_val_pl, @@ -331,29 +369,29 @@ typedef enum { ei4_rx_fifo_diag_32_47_pl, ei4_rx_eye_width_status_pl, ei4_rx_eye_width_cntl_pl, + ei4_rx_trace_pl, + ei4_rx_servo_ber_count_pl, + ei4_rx_eye_opt_stat_pl, ei4_rx_clk_mode_pg, ei4_rx_spare_mode_pg, + ei4_rx_stop_cntl_stat_pg, ei4_rx_mode_pg, ei4_rx_bus_repair_pg, ei4_rx_grp_repair_vec_0_15_pg, ei4_rx_grp_repair_vec_16_31_pg, - ei4_rx_recal_mode_pg, + ei4_rx_stop_addr_lsb_pg, + ei4_rx_stop_mask_lsb_pg, ei4_rx_reset_act_pg, ei4_rx_id1_pg, ei4_rx_id2_pg, ei4_rx_id3_pg, - ei4_rx_minikerf_pg, - ei4_rx_bist_cntl_pg, ei4_rx_sls_mode_pg, ei4_rx_training_start_pg, ei4_rx_training_status_pg, ei4_rx_recal_status_pg, ei4_rx_timeout_sel_pg, ei4_rx_fifo_mode_pg, - ei4_rx_state_debug_pg, - ei4_rx_state_val_pg, ei4_rx_sls_status_pg, - ei4_rx_prot_mode_pg, ei4_rx_fir1_pg, ei4_rx_fir2_pg, ei4_rx_fir1_mask_pg, @@ -386,7 +424,7 @@ typedef enum { ei4_rx_timeout_sel2_pg, ei4_rx_dyn_rpr_pg, ei4_rx_dyn_rpr_gcrmsg_pg, - ei4_rx_dyn_rpr_err_tallying_pg, + ei4_rx_dyn_rpr_err_tallying1_pg, ei4_rx_eo_final_l2u_gcrmsgs_pg, ei4_rx_gcr_msg_debug_dest_ids_pg, ei4_rx_gcr_msg_debug_src_ids_pg, @@ -403,28 +441,47 @@ typedef enum { ei4_rx_ei4_tx_lane_info_gcrmsg_pg, ei4_rx_err_tallying_gcrmsg_pg, ei4_rx_trace_pg, + ei4_rx_rdt_cntl_pg, + ei4_rx_rc_step_cntl_pg, + ei4_rx_eo_recal_pg, + ei4_rx_servo_ber_count_pg, + ei4_rx_func_state_pg, + ei4_rx_dyn_rpr_debug_pg, + ei4_rx_dyn_rpr_err_tallying2_pg, + ei4_rx_result_chk_pg, + ei4_rx_sls_rcvy_fin_gcrmsg_pg, ei4_rx_wiretest_pp, - ei4_rx_mode_pp, + ei4_rx_mode1_pp, ei4_rx_cntl_pp, ei4_rx_ei4_cal_cntl_pp, ei4_rx_ei4_cal_inc_a_d_pp, ei4_rx_ei4_cal_inc_e_h_pp, ei4_rx_ei4_cal_dec_a_d_pp, ei4_rx_ei4_cal_dec_e_h_pp, + ei4_rx_mode2_pp, ei4_rx_ber_cntl_pp, ei4_rx_ber_mode_pp, ei4_rx_servo_to1_pp, ei4_rx_servo_to2_pp, ei4_rx_reset_cfg_pp, + ei4_rx_recal_to1_pp, + ei4_rx_recal_to2_pp, + ei4_rx_recal_cntl_pp, + ei4_rx_trace_pp, + ei4_rx_bist_gcrmsg_pp, + ei4_rx_fir_reset_pb, + ei4_rx_fir_pb, + ei4_rx_fir_mask_pb, + ei4_rx_fir_error_inject_pb, ei4_rx_fir_msg_pb, NUM_REGS } GCR_sub_registers; // merged ei4 and edi ext addresses -const uint32_t GCR_sub_reg_ext_addr[] = { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x195, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x000, 0x001, 0x002, 0x003, 0x005, 0x006, 0x007, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x100, 0x101, 0x103, 0x104, 0x105, 0x106, 0x107, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10E, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x115, 0x116, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x144, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x1FE, 0x108 , -0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x195, 0x198, 0x19D, 0x19F, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x006, 0x007, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x100, 0x101, 0x103, 0x104, 0x105, 0x106, 0x107, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10E, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x115, 0x116, 0x117, 0x118, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x16A, 0x16B, 0x16C, 0x16D, 0x108 }; - +const uint32_t GCR_sub_reg_ext_addr[] = { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3, +0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3 +}; //merged ei4 and edi const char* const GCR_sub_reg_names[] = { "TX Lane Mode Reg", @@ -438,6 +495,8 @@ const char* const GCR_sub_reg_names[] = { "TX Per-Lane FIR Error Mask Reg", "TX Per-Lane FIR Error Injection Reg", "TX Per-Lane Fast-Clocked Mode Reg", + "TX TDR Capture status", + "TX Cntl Reg via GCR Messages", "TX Per-Group Clk Mode Reg", "TX Per-Group Spare Mode Reg", "TX Cntl and Status Reg", @@ -453,7 +512,6 @@ const char* const GCR_sub_reg_names[] = { "TX Clock Group Identification 1 Reg", "TX Clock Group Identification 2 Reg", "TX Clock Group Identification 3 Reg", - "TX Minikerf Cntl Reg", "TX Clock Control Reg", "TX FFE Test Mode Reg", "TX FFE Main Reg", @@ -461,6 +519,7 @@ const char* const GCR_sub_reg_names[] = { "TX FFE Margin Reg", "TX Bad Lanes Encoded", "TX SLS Lane Encoded", + "TX Wiretest Driver Segment Enable", "TX Lane Disable(d) 0 to 15 Reg", "TX Lane Disable(d) 16 to 31 Reg", "TX SLS Lane TX Mux Setting", @@ -476,19 +535,24 @@ const char* const GCR_sub_reg_names[] = { "TX Bit Error Injection Control SLS Shadow Reg", "TX Cntl Per-Pack Reg", "TX Configurable Reset Control Register (CRCR)", + "TX TDR Control Register", + "TX TDR Control Register", + "TX TDR Control Register", "TX Impedance Cal Cntl and Status Reg", "TX Impedance Cal N Value Reg", "TX Impedance Cal P Value Reg", "TX Impedance Cal P 4x Value Reg", "TX Impedance Cal SW Workaround 1 Reg", "TX Impedance Cal SW Workaround 2 Reg", + "TX Iref bias code input", + "TX Minikerf Cntl Reg", + "TX Initfile Version Reg", + "TX Scratch Reg", "RX Lane Mode Reg", "RX Cntl and Status Reg", "RX Per-lane Spare Mode Reg", "RX Phase Rotator Edge Status Reg", "RX BIST Status Reg", - "RX Eye Optimization Mode Reg", - "RX Eye Optimization Status Reg", "RX Even Sample Latch Offset Cntl Reg", "RX Odd Sample Latch Offset Cntl Reg", "RX Preamp value Reg", @@ -522,27 +586,29 @@ const char* const GCR_sub_reg_names[] = { "RX Current and historic minimum eye width", "RX historic minimum eye width reset control", "RX dfe clock adjust register", + "RX Trace Per Lane Settings", + "RX servo-based BER count PL", + "RX Eye optimization error register", "RX Per-Group Clk Mode Reg", "RX Per-Group Spare Mode Reg", + "RX Trace/State stop control/status/ MSB Reg", "RX Mode Reg", "RX Bus Repair Reg", "RX Clkgrp Repair Lanes 0-15 Reg", "RX Clkgrp Repair Lanes 16-31 Reg", - "RX Bus Repair Reg", + "RX Trace/State stop address 4-19 Reg", + "RX Trace/State stop mask 4-19 Reg", "RX Reset Control Action Register (RCAR)", "RX Clock Group Identification 1 Reg", "RX Clock Group Identification 2 Reg", "RX Clock Group Identification 3 Reg", "RX Minikerf Cntl Reg", - "RX BIST Cntl Reg", "RX Spare Lane Signaling Mode Reg", "RX Training State Start Reg", "RX Training State Status Reg", "RX Recal Status Reg", "RX Timeout Select Reg", "RX FIFO Mode Reg", - "RX State Machine Debug Cntl/Status Reg", - "RX State Machine Debug Value Reg", "RX Spare Lane Signalling Status Reg", "RX Per-Group FIR Error Source-Isolation Reg", "RX Per-Group FIR Error Source-Isolation Reg", @@ -576,7 +642,7 @@ const char* const GCR_sub_reg_names[] = { "RX Misc Analog Reg", "RX Dynamic Repair & Recalibration Status", "CRC/ECC Dynamic Repair GCR Message Reg", - "CRC/ECC Dynamic Repair Error Frequency Settings", + "CRC/ECC Dynamic Repair Lane Error Frequency Settings", "RX Final Load to Unload GCR Messages", "RX SW Initiated GCR Message Destination IDs", "RX SW Initiated GCR Message Source IDs", @@ -585,9 +651,8 @@ const char* const GCR_sub_reg_names[] = { "RX Dynamic Recalibration Status", "RX Clock Wiretest Status", "RX Dynamic Recalibration Configuration", - "RX Servo Dynamic Recalibration GCR Messages", "RX Dynamic Recalibration GCR Messages", - "RX Cleanup PLL Enable ", + "RX PLL or DLL reset and calibration controls", "RX Eye optimization step control", "RX Eye optimization step status", "RX Eye optimization step fail flags", @@ -603,11 +668,20 @@ const char* const GCR_sub_reg_names[] = { "RX: TX Lane Info", "CRC/ECC Syndrome Tallying GCR Message Reg", "RX Trace Mode Reg", + "RX Recalibraton step control", + "RX Eye Opt and Recal Status", + "RX Recal Bit Error Rate Count Working Register", + "RX Func Mode Status", + "Dynamic Repair Testfloor/Debug Register", + "CRC/ECC Dynamic Repair Bus Error Frequency Settings", + "Eye widhth/height results check limits", + "Bit error rate check max rate k limits", + "RX SLS Handshake Recovery Finish GCR Messages", "RX Wiretest Per-Pack Shadow Reg", "RX Mode Per-Pack Shadow Reg", "RX Cntl Per-Pack Shadow Reg", "RX Dynamic Recalibration Timeout Selects", - "RX Servo Dynamic Recalibration GCR Messages", + "RX Mode Per-Pack Shadow Reg", "RX BER Control Reg", "RX BER Mode Reg", "RX Servo Timeout Select Regs 1", @@ -616,7 +690,17 @@ const char* const GCR_sub_reg_names[] = { "RX DFE Configuration Register", "RX DFE timers Configuration Register", "RX Configurable Reset Control Register (CRCR)", - + "RX Recal Servo Timeout Select Regs 1", + "RX Recal Servo Timeout Select Regs 2", + "RX Recal Servo Timeout Select Regs 3", + "RX Recal in progress control", + "RX Trace Per Pack Settings", + "RX BIST Cntl Reg", + "RX Scope Cntl Reg", + "Per-Bus BUSCTL FIR Error Reset Reg", + "Per-Bus FIR Error Source-Isolation Reg", + "Per-Bus FIR Error Source-Isolation Mask Reg", + "Per-Bus FIR Error Injection Reg" "TX Lane Mode Reg", "TX Cntl and Status Reg", "TX Per-Lane Spare Mode Reg", @@ -643,10 +727,10 @@ const char* const GCR_sub_reg_names[] = { "TX Clock Group Identification 1 Reg", "TX Clock Group Identification 2 Reg", "TX Clock Group Identification 3 Reg", - "TX Minikerf Cntl Reg", "TX Clock Control Reg", "TX Bad Lanes Encoded", "TX SLS Lane Encoded", + "TX Wiretest Driver Segment Enable", "TX Precomp and Impedance Reg", "TX Misc Analog Reg", "TX Lane Disable(d) 0 to 15 Reg", @@ -654,6 +738,16 @@ const char* const GCR_sub_reg_names[] = { "TX SLS Lane TX Mux Setting", "TX Dynamic Repair & Recalibration Status", "TX Dynamic Repair & Recalibration Messages", + "TX control for RDT (EI3-Mode only)", + "RX DLL Calibration Sequence Status", + "RX DLL 1 Manual Delay/Vreg DAC Coarse Override", + "RX DLL 1 Manual Vreg DAC Fine Override", + "RX DLL 1 Manual Vreg DAC Fine Override", + "RX DLL 2 Manual Delay/Vreg DAC Coarse Override", + "RX DLL 2 Manual Vreg DAC Fine Override", + "RX DLL 2 Manual Vreg DAC Fine Override", + "RX DLL Clock Phase Detector Filtering", + "RX DLL Analog Fine Tuning", "TX Wiretest Per-Group & Pack Shadow Reg", "TX Mode Per-Pack Shadow Reg", "TX SLS Command", @@ -663,13 +757,12 @@ const char* const GCR_sub_reg_names[] = { "TX Bit Error Injection Control SLS Shadow Reg", "TX Cntl Per-Pack Reg", "TX Configurable Reset Control Register (CRCR)", + "TX TDR Control Register", + "TX TDR Control Register", "RX Lane Mode Reg", "RX Cntl and Status Reg", "RX Per-lane Spare Mode Reg", - "RX Phase Rotator Edge Status Reg", "RX BIST Status Reg", - "RX Eye Optimization Mode Reg", - "RX Eye Optimization Status Reg", "RX Even Sample Latch Offset Cntl Reg", "RX Odd Sample Latch Offset Cntl Reg", "RX Preamp value Reg", @@ -697,29 +790,29 @@ const char* const GCR_sub_reg_names[] = { "RX FIFO output 32 to 47 for diag", "RX Current and historic minimum eye width", "RX historic minimum eye width reset control", + "RX Trace Per Lane Settings", + "RX servo-based BER count PL", + "RX Eye optimization error register", "RX Per-Group Clk Mode Reg", "RX Per-Group Spare Mode Reg", + "RX Trace/State stop control/status/ MSB Reg", "RX Mode Reg", "RX Bus Repair Reg", "RX Clkgrp Repair Lanes 0-15 Reg", "RX Clkgrp Repair Lanes 16-31 Reg", - "RX Bus Repair Reg", + "RX Trace/State stop address 4-19 Reg", + "RX Trace/State stop mask 4-19 Reg", "RX Reset Control Action Register (RCAR)", "RX Clock Group Identification 1 Reg", "RX Clock Group Identification 2 Reg", "RX Clock Group Identification 3 Reg", - "RX Minikerf Cntl Reg", - "RX BIST Cntl Reg", "RX Spare Lane Signaling Mode Reg", "RX Training State Start Reg", "RX Training State Status Reg", "RX Recal Status Reg", "RX Timeout Select Reg", "RX FIFO Mode Reg", - "RX State Machine Debug Cntl/Status Reg", - "RX State Machine Debug Value Reg", "RX Spare Lane Signalling Status Reg", - "RX Phase Rotator/Detector Mode Reg", "RX Per-Group FIR Error Source-Isolation Reg", "RX Per-Group FIR Error Source-Isolation Reg", "RX Per-Group FIR Error Source-Isolation Mask Reg", @@ -752,14 +845,14 @@ const char* const GCR_sub_reg_names[] = { "RX Timeout Select Reg 2", "RX Dynamic Repair & Recalibration Status", "CRC/ECC Dynamic Repair GCR Message Reg", - "CRC/ECC Dynamic Repair Error Frequency Settings", + "CRC/ECC Dynamic Repair Lane Error Frequency Settings", "RX Final Load to Unload GCR Messages", "RX SW Initiated GCR Message Destination IDs", "RX SW Initiated GCR Message Source IDs", "RX SW Initiated GCR Message Destination Addr", "RX SW Initiated GCR Message Write Data", "RX Clock Wiretest Status", - "RX Cleanup PLL Enable ", + "RX PLL or DLL reset and calibration controls", "RX Eye optimization step control", "RX Eye optimization step status", "RX Eye optimization step fail flags", @@ -769,6 +862,15 @@ const char* const GCR_sub_reg_names[] = { "RX: TX Lane Info", "CRC/ECC Syndrome Tallying GCR Message Reg", "RX Trace Mode Reg", + "RX control for RDT (EI3-Mode only)", + "RX Recalibraton step control", + "RX Eye Opt and Recal Status", + "RX Recal Bit Error Rate Count Working Register", + "RX Func Mode Status", + "Dynamic Repair Testfloor/Debug Register", + "CRC/ECC Dynamic Repair Bus Error Frequency Settings", + "Eye widhth/height results check limits", + "RX SLS Handshake Recovery Finish GCR Messages", "RX Wiretest Per-Pack Shadow Reg", "RX Mode Per-Pack Shadow Reg", "RX Cntl Per-Pack Shadow Reg", @@ -777,21 +879,25 @@ const char* const GCR_sub_reg_names[] = { "RX Cal Accum inc value Reg", "RX Cal Accum dec value Reg", "RX Cal Accum dec value Reg", + "RX Mode Per-Pack Shadow Reg", "RX BER Control Reg", "RX BER Mode Reg", "RX Servo Timeout Select Regs 1", "RX Servo Timeout Select Regs 2", - "RX Configurable Reset Control Register (CRCR)" -}; - -const char* const ei4_GCR_sub_reg_names[] = { - + "RX Configurable Reset Control Register (CRCR)", + "RX Recal Servo Timeout Select Regs 1", + "RX Recal Servo Timeout Select Regs 2", + "RX Recal in progress control", + "RX Trace Per Pack Settings", + "RX BIST Cntl Reg", + "Per-Bus BUSCTL FIR Error Reset Reg", + "Per-Bus FIR Error Source-Isolation Reg", + "Per-Bus FIR Error Source-Isolation Mask Reg", + "Per-Bus FIR Error Injection Reg" }; - - // tx_mode_pl Register field name data value Description -#define tx_lane_pdwn 0x8000 //Used to drive inhibit (tristate) and fully power down a lane. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers tx_lane_disabled_vec_0_15 and tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines. +#define tx_lane_pdwn 0x8000 //Used to drive inhibit (tristate) and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (tx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers tx_lane_disabled_vec_0_15 and tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. #define tx_lane_pdwn_clear 0x7FFF // Clear mask #define tx_lane_invert 0x4000 //Used to invert the polarity of a lane. #define tx_lane_invert_clear 0xBFFF // Clear mask @@ -805,22 +911,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_lane_quiesce_n_clear 0xF3FF // Clear mask #define tx_lane_scramble_disable 0x0200 //Used to disable the TX scrambler on a specific lane or all lanes by using a per-lane/per-group global write. #define tx_lane_scramble_disable_clear 0xFDFF // Clear mask -#define tx_lane_error_inject_mode_single_err_inj 0x0001 //Used to set the error injection rate to a particular value. Single Error Injection -#define tx_lane_error_inject_mode_0 0x0002 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_1 0x0003 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_2 0x0010 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_3 0x0011 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_4 0x0012 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_5 0x0013 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_6 0x0020 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_7 0x0021 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_8 0x0022 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_9 0x0023 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_10 0x0030 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_11 0x0031 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_12 0x0032 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_13 0x0033 //Used to set the error injection rate to a particular value. TBD -#define tx_lane_error_inject_mode_clear 0xF300 // Clear mask // tx_cntl_stat_pl Register field name data value Description #define tx_fifo_err 0x8000 //Indicates an error condition in the TX FIFO. @@ -855,7 +945,7 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_prbs_tap_id_pattern_c 0x4000 //TX Per-Lane PRBS Tap Selector PRBS tap point C #define tx_prbs_tap_id_pattern_d 0x6000 //TX Per-Lane PRBS Tap Selector PRBS tap point D #define tx_prbs_tap_id_pattern_e 0x8000 //TX Per-Lane PRBS Tap Selector PRBS tap point E -#define tx_prbs_tap_id_pattern_F 0xA000 //TX Per-Lane PRBS Tap Selector PRBS tap point F +#define tx_prbs_tap_id_pattern_f 0xA000 //TX Per-Lane PRBS Tap Selector PRBS tap point F #define tx_prbs_tap_id_pattern_g 0xC000 //TX Per-Lane PRBS Tap Selector PRBS tap point G #define tx_prbs_tap_id_pattern_h 0xE000 //TX Per-Lane PRBS Tap Selector PRBS tap point H #define tx_prbs_tap_id_clear 0x1FFF // Clear mask @@ -870,12 +960,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_drv_data_pattern_gcrmsg_drv_9th_prbs23 0x7000 //GCR Message: TX Per Data Lane Drive Patterns PRBS-23 9th pattern #define tx_drv_data_pattern_gcrmsg_drv_ei3_iap 0x8000 //GCR Message: TX Per Data Lane Drive Patterns EI-3 Busy IAP Pattern (EI4 only #define tx_drv_data_pattern_gcrmsg_drv_ei3_prbs12 0x9000 //GCR Message: TX Per Data Lane Drive Patterns Drive EI-3 PRBS-12 Shifted RDT Pattern (EI4 only -#define tx_drv_data_pattern_gcrmsg_unused_A 0xA000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define tx_drv_data_pattern_gcrmsg_unused_B 0xB000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define tx_drv_data_pattern_gcrmsg_unused_C 0xC000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define tx_drv_data_pattern_gcrmsg_unused_D 0xD000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define tx_drv_data_pattern_gcrmsg_unused_E 0xE000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define tx_drv_data_pattern_gcrmsg_unused_F 0xF000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_TDR_square_wave 0xA000 //GCR Message: TX Per Data Lane Drive Patterns Drives TDR Pulse-Square waves +#define tx_drv_data_pattern_gcrmsg_k28_5 0xB000 //GCR Message: TX Per Data Lane Drive Patterns Drives 20-bit K28.5 pattern - padded to 32 bits +#define tx_drv_data_pattern_gcrmsg_unused_A 0xC000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_B 0xD000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_C 0xE000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define tx_drv_data_pattern_gcrmsg_unused_D 0xF000 //GCR Message: TX Per Data Lane Drive Patterns Unused #define tx_drv_data_pattern_gcrmsg_clear 0x0FFF // Clear mask #define tx_drv_func_data_gcrmsg 0x0800 //GCR Message: Functional Data #define tx_drv_func_data_gcrmsg_clear 0xF7FF // Clear mask @@ -883,8 +973,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_sls_lane_sel_gcrmsg_clear 0xFBFF // Clear mask // tx_sync_pattern_gcrmsg_pl Register field name data value Description -#define tx_sync_pattern_gcrmsg_pl_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED -#define tx_sync_pattern_gcrmsg_pl_spare_clear 0x7FFF // Clear mask #define tx_drv_sync_patt_gcrmsg 0x4000 //Sync Pattern #define tx_drv_sync_patt_gcrmsg_clear 0xBFFF // Clear mask @@ -901,16 +989,21 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_pl_fir_err_inj_clear 0x7FFF // Clear mask // tx_mode_fast_pl Register field name data value Description -#define tx_err_inject_lane0 0x8000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 0. -#define tx_err_inject_lane1 0x4000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 1. -#define tx_err_inject_lane2 0x2000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) inject error on lane 2. -#define tx_err_inject_lane3 0x1000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 3. +#define tx_err_inject 0x0000 //Software-only controlled register to inject one or more errors for one deserialized clock pulse on one or more specified beats on this lane. Set bit position X to inject on beat X of a cycle. Bits 0:3 are used in EDI and 0:1 are used in EI4. #define tx_err_inject_clear 0x0FFF // Clear mask -#define tx_err_inj_A_enable 0x0800 //Control to enable the random bit error injection A.(default) +#define tx_err_inj_A_enable 0x0800 //Control to enable the random bit error injection pattern A for this lane.(default) #define tx_err_inj_A_enable_clear 0xF7FF // Clear mask -#define tx_err_inj_B_enable 0x0400 //Control to enable the random bit error injection B.(default) +#define tx_err_inj_B_enable 0x0400 //Control to enable the random bit error injection pattern B for this lane.(default) #define tx_err_inj_B_enable_clear 0xFBFF // Clear mask +// tx_tdr_stat_pl Register field name data value Description +#define tx_tdr_capt_val 0x8000 //value captured by TDR function, 1-bit shared over a pack, so this value should be the same for each bit (dmb) +#define tx_tdr_capt_val_clear 0x7FFF // Clear mask + +// tx_cntl_gcrmsg_pl Register field name data value Description +#define tx_pdwn_lite_gcrmsg 0x8000 //GCR Message: When set, gates TX data path (post FIFO) to 0s on unused spare lanes when not being recalibrated +#define tx_pdwn_lite_gcrmsg_clear 0x7FFF // Clear mask + // tx_clk_mode_pg Register field name data value Description #define tx_clk_pdwn 0x8000 //Used to disable the TX clock and put it into a low power state. #define tx_clk_pdwn_clear 0x7FFF // Clear mask @@ -946,16 +1039,16 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_pg_spare_mode_7_clear 0xFEFF // Clear mask // tx_cntl_stat_pg Register field name data value Description -#define tx_cntl_stat_pg_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED -#define tx_cntl_stat_pg_spare_clear 0x7FFF // Clear mask #define tx_fifo_init 0x4000 //Used to initialize the TX FIFO and put it into a known reset state. This will cause the load to unload delay of the FIFO to be set to the value in the TX_FIFO_L2U_DLY field of the TX_FIFO_Mode register. #define tx_fifo_init_clear 0xBFFF // Clear mask // tx_mode_pg Register field name data value Description -#define tx_max_bad_lanes 0x0000 //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus +#define tx_max_bad_lanes 0x0000 //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus (NOTE: should match RX side) #define tx_max_bad_lanes_clear 0x07FF // Clear mask #define tx_msbswap 0x0400 //Used to enable end-for-end or msb swap of TX lanes. For example, lanes 0 and N-1 swap, lanes 1 and N-2 swap, etc. #define tx_msbswap_clear 0xFBFF // Clear mask +#define tx_pdwn_lite_disable 0x0200 //Disables the power down lite feature of unused spare lanes (generally should match rx_pdwn_lite_disable) +#define tx_pdwn_lite_disable_clear 0xFDFF // Clear mask // tx_bus_repair_pg Register field name data value Description #define tx_bus_repair_count 0x0000 //This field is used to TBD. @@ -982,10 +1075,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_fir_reset_clear 0xFFFE // Clear mask // tx_bist_stat_pg Register field name data value Description -#define tx_clk_bist_err 0x8000 //Indicates a TXBIST error occurred. -#define tx_clk_bist_err_clear 0x7FFF // Clear mask -#define tx_clk_bist_done 0x4000 //Indicates TXBIST has completed. -#define tx_clk_bist_done_clear 0xBFFF // Clear mask +#define tx_clk_bist_err 0x4000 //Indicates a TXBIST error occurred. +#define tx_clk_bist_err_clear 0xBFFF // Clear mask +#define tx_clk_bist_done 0x1000 //Indicates TXBIST has completed. +#define tx_clk_bist_done_clear 0xEFFF // Clear mask // tx_fir_pg Register field name data value Description #define tx_pg_fir_errs_clear 0x00FF // Clear mask @@ -1017,10 +1110,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_end_lane_id 0x0000 //This field is used to programmably set the last lane position in the group but relative to the bus. #define tx_end_lane_id_clear 0x7F80 // Clear mask -// tx_minikerf_pg Register field name data value Description -#define tx_minikerf 0x0000 //Used to configure the TX Minikerf for analog characterization. -#define tx_minikerf_clear 0x0000 // Clear mask - // tx_clk_cntl_gcrmsg_pg Register field name data value Description #define tx_drv_clk_pattern_gcrmsg_drv_wt 0x4000 //TX Clock Drive Patterns Drive Wiretest Pattern #define tx_drv_clk_pattern_gcrmsg_drv_c4 0x8000 //TX Clock Drive Patterns Drive Clock Pattern @@ -1039,21 +1128,21 @@ const char* const ei4_GCR_sub_reg_names[] = { // tx_ffe_main_pg Register field name data value Description #define tx_ffe_main_p_enc 0x0000 //TBD -#define tx_ffe_main_p_enc_clear 0xC0FF // Clear mask +#define tx_ffe_main_p_enc_clear 0x80FF // Clear mask #define tx_ffe_main_n_enc 0x0000 //TBD -#define tx_ffe_main_n_enc_clear 0x3FC0 // Clear mask +#define tx_ffe_main_n_enc_clear 0x7F80 // Clear mask // tx_ffe_post_pg Register field name data value Description -#define tx_ffe_post_p_enc 0x0000 //TBD +#define tx_ffe_post_p_enc 0x0000 //TBD This field is updated during TX BIST by logic temporarily #define tx_ffe_post_p_enc_clear 0x00FF // Clear mask #define tx_ffe_post_n_enc 0x0000 //TBD -#define tx_ffe_post_n_enc_clear 0x0FF0 // Clear mask +#define tx_ffe_post_n_enc_clear 0x1FE0 // Clear mask // tx_ffe_margin_pg Register field name data value Description #define tx_ffe_margin_p_enc 0x0000 //TBD #define tx_ffe_margin_p_enc_clear 0x00FF // Clear mask #define tx_ffe_margin_n_enc 0x0000 //TBD -#define tx_ffe_margin_n_enc_clear 0x0FF0 // Clear mask +#define tx_ffe_margin_n_enc_clear 0x1FE0 // Clear mask // tx_bad_lane_enc_gcrmsg_pg Register field name data value Description #define tx_bad_lane1_gcrmsg 0x0000 //GCR Message: Encoded bad lane one in relation to the entire TX bus @@ -1071,6 +1160,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_sls_lane_val_gcrmsg 0x0100 //GCR Message: TX SLS Lane Valid #define tx_sls_lane_val_gcrmsg_clear 0xFEFF // Clear mask +// tx_wt_seg_enable_pg Register field name data value Description +#define tx_wt_en_all_clk_segs_gcrmsg 0x8000 //TX Clock Wiretest driver segnments enable +#define tx_wt_en_all_clk_segs_gcrmsg_clear 0x7FFF // Clear mask +#define tx_wt_en_all_data_segs_gcrmsg 0x4000 //TX Data Wiretest driver segnments enable +#define tx_wt_en_all_data_segs_gcrmsg_clear 0xBFFF // Clear mask + // tx_lane_disabled_vec_0_15_pg Register field name data value Description #define tx_lane_disabled_vec_0_15 0x0000 //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control). #define tx_lane_disabled_vec_0_15_clear 0x0000 // Clear mask @@ -1095,10 +1190,16 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_slv_mv_sls_unshdw_req_gcrmsg_clear 0xDFFF // Clear mask #define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg 0x1000 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register #define tx_slv_mv_sls_unshdw_rpr_req_gcrmsg_clear 0xEFFF // Clear mask -#define tx_bus_width 0x0000 //TX Bus Width +#define tx_bus_width 0x0000 //GCR Message: TX Bus Width #define tx_bus_width_clear 0xF01F // Clear mask #define tx_slv_mv_sls_rpr_req_gcrmsg 0x0010 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register #define tx_slv_mv_sls_rpr_req_gcrmsg_clear 0xFFEF // Clear mask +#define tx_sls_lane_sel_lg_gcrmsg 0x0008 //GCR Message: Sets the tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios +#define tx_sls_lane_sel_lg_gcrmsg_clear 0xFFF7 // Clear mask +#define tx_sls_lane_unsel_lg_gcrmsg 0x0004 //GCR Message: Clears the tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios +#define tx_sls_lane_unsel_lg_gcrmsg_clear 0xFFFB // Clear mask +#define tx_spr_lns_pdwn_lite_gcrmsg 0x0002 //GCR Message: Signals the TX side to Power Down Lite (data gate) unused spare lanes at the end of static repair +#define tx_spr_lns_pdwn_lite_gcrmsg_clear 0xFFFD // Clear mask // tx_wiretest_pp Register field name data value Description #define tx_wt_pattern_length_256 0x4000 //TX Wiretest Pattern Length 256 @@ -1127,49 +1228,69 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_dyn_recal_tsr_ignore_gcrmsg_clear 0xBFFF // Clear mask #define tx_sls_cmd_gcrmsg 0x0000 //GCR Message: TX SLS Command #define tx_sls_cmd_gcrmsg_clear 0xC0FF // Clear mask +#define tx_snd_sls_cmd_prev_gcrmsg 0x0080 //GCR Message: Revert to sending previous SLS Command or Recalibration Data after recovery repair made +#define tx_snd_sls_cmd_prev_gcrmsg_clear 0xFF7F // Clear mask +#define tx_snd_sls_using_reg_scramble 0x0040 //GCR Message: Send SLS command using normal scramble pattern instead of 9th pattern +#define tx_snd_sls_using_reg_scramble_clear 0xFFBF // Clear mask // tx_ber_cntl_a_pp Register field name data value Description -#define tx_err_inj_a_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data. +#define tx_err_inj_a_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data for pattern A. #define tx_err_inj_a_rand_beat_dis_clear 0x7FFF // Clear mask -#define tx_err_inj_a_fine_sel_0_15 0x1000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-15 -#define tx_err_inj_a_fine_sel_0_7 0x2000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-7 -#define tx_err_inj_a_fine_sel_0_3 0x3000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-3 -#define tx_err_inj_a_fine_sel_0_1 0x4000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-1 -#define tx_err_inj_a_fine_sel_fixed1 0x5000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 1 -#define tx_err_inj_a_fine_sel_fixed3 0x6000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 3 -#define tx_err_inj_a_fine_sel_fixed7 0x7000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 7. +#define tx_err_inj_a_fine_sel_1_16 0x1000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-16 cycles +#define tx_err_inj_a_fine_sel_1_8 0x2000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-8 cycles +#define tx_err_inj_a_fine_sel_1_4 0x3000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-4 cycles +#define tx_err_inj_a_fine_sel_1_2 0x4000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-2 cycles +#define tx_err_inj_a_fine_sel_fixed1 0x5000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 1 cycle +#define tx_err_inj_a_fine_sel_fixed3 0x6000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 3 cycles +#define tx_err_inj_a_fine_sel_fixed7 0x7000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 7 cycles. #define tx_err_inj_a_fine_sel_clear 0x8FFF // Clear mask -#define tx_err_inj_a_coarse_sel_8_23 0x0100 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 8-32, mean of 16 -#define tx_err_inj_a_coarse_sel_12_19 0x0200 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 12-19, mean of 16 -#define tx_err_inj_a_coarse_sel_14_17 0x0300 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 14-17, mean of 16 -#define tx_err_inj_a_coarse_sel_min 0x0400 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Min range of 15-16, mean of 16 -#define tx_err_inj_a_coarse_sel_fixed16 0x0500 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 16 -#define tx_err_inj_a_coarse_sel_fixed24 0x0600 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 24 -#define tx_err_inj_a_coarse_sel_fixed20 0x0700 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 20. -#define tx_err_inj_a_coarse_sel_clear 0xF8FF // Clear mask -#define tx_err_inj_a_ber_sel 0x0000 //Used to set the random bit error injection rate to a particular value. See workbook for details. +#define tx_err_inj_a_coarse_sel_9_24 0x0100 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 9-24, mean of 16.5 +#define tx_err_inj_a_coarse_sel_13_20 0x0200 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 13-20, mean of 16.5 +#define tx_err_inj_a_coarse_sel_16_19 0x0300 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-19, mean of 16.5 +#define tx_err_inj_a_coarse_sel_17_18 0x0400 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-17, mean of 16.5 +#define tx_err_inj_a_coarse_sel_1_8 0x0500 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 1-8, mean of 4.5 +#define tx_err_inj_a_coarse_sel_3_6 0x0600 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 3-6, mean of 4.5 +#define tx_err_inj_a_coarse_sel_4_5 0x0700 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 4-5, mean of 4.5 +#define tx_err_inj_a_coarse_sel_fixed1 0x0800 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 1 +#define tx_err_inj_a_coarse_sel_fixed3 0x0900 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 3 +#define tx_err_inj_a_coarse_sel_fixed5 0x0A00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 5 +#define tx_err_inj_a_coarse_sel_fixed6 0x0B00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 6 +#define tx_err_inj_a_coarse_sel_fixed7 0x0C00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 7 +#define tx_err_inj_a_coarse_sel_fixed17 0x0D00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 17 +#define tx_err_inj_a_coarse_sel_fixed21 0x0E00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 21 +#define tx_err_inj_a_coarse_sel_fixed25 0x0F00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 25 +#define tx_err_inj_a_coarse_sel_clear 0xF0FF // Clear mask +#define tx_err_inj_a_ber_sel 0x0000 //Used to set the random bit error injection rate for pattern A. When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). #define tx_err_inj_a_ber_sel_clear 0x3FC0 // Clear mask // tx_ber_cntl_b_pp Register field name data value Description -#define tx_err_inj_b_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data.(default) +#define tx_err_inj_b_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data for pattern B. #define tx_err_inj_b_rand_beat_dis_clear 0x7FFF // Clear mask -#define tx_err_inj_b_fine_sel_0_15 0x1000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-15 -#define tx_err_inj_b_fine_sel_0_7 0x2000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-7 -#define tx_err_inj_b_fine_sel_0_3 0x3000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-3 -#define tx_err_inj_b_fine_sel_0_1 0x4000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-1 -#define tx_err_inj_b_fine_sel_fixed1 0x5000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 1 -#define tx_err_inj_b_fine_sel_fixed3 0x6000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 3 -#define tx_err_inj_b_fine_sel_fixed7 0x7000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 7. +#define tx_err_inj_b_fine_sel_1_16 0x1000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-16 cycles +#define tx_err_inj_b_fine_sel_1_8 0x2000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-8 cycles +#define tx_err_inj_b_fine_sel_1_4 0x3000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-4 cycles +#define tx_err_inj_b_fine_sel_1_2 0x4000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-2 cycles +#define tx_err_inj_b_fine_sel_fixed1 0x5000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 1 cycle +#define tx_err_inj_b_fine_sel_fixed3 0x6000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 3 cycles +#define tx_err_inj_b_fine_sel_fixed7 0x7000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 7 cycles. #define tx_err_inj_b_fine_sel_clear 0x8FFF // Clear mask -#define tx_err_inj_b_coarse_sel_8_23 0x0100 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 8-32, mean of 16 -#define tx_err_inj_b_coarse_sel_12_19 0x0200 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 12-19, mean of 16 -#define tx_err_inj_b_coarse_sel_14_17 0x0300 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 14-17, mean of 16 -#define tx_err_inj_b_coarse_sel_min 0x0400 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Min range of 15-16, mean of 16 -#define tx_err_inj_b_coarse_sel_fixed16 0x0500 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 16 -#define tx_err_inj_b_coarse_sel_fixed24 0x0600 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 24 -#define tx_err_inj_b_coarse_sel_fixed20 0x0700 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 20. -#define tx_err_inj_b_coarse_sel_clear 0xF8FF // Clear mask -#define tx_err_inj_b_ber_sel 0x0000 //Used to set the random bit error injection rate to a particular value. See workbook for details. +#define tx_err_inj_b_coarse_sel_9_24 0x0100 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 9-24, mean of 16.5 +#define tx_err_inj_b_coarse_sel_13_20 0x0200 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 13-20, mean of 16.5 +#define tx_err_inj_b_coarse_sel_16_19 0x0300 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-19, mean of 16.5 +#define tx_err_inj_b_coarse_sel_17_18 0x0400 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-17, mean of 16.5 +#define tx_err_inj_b_coarse_sel_1_8 0x0500 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 1-8, mean of 4.5 +#define tx_err_inj_b_coarse_sel_3_6 0x0600 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 3-6, mean of 4.5 +#define tx_err_inj_b_coarse_sel_4_5 0x0700 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 4-5, mean of 4.5 +#define tx_err_inj_b_coarse_sel_fixed1 0x0800 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 1 +#define tx_err_inj_b_coarse_sel_fixed3 0x0900 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 3 +#define tx_err_inj_b_coarse_sel_fixed5 0x0A00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 5 +#define tx_err_inj_b_coarse_sel_fixed6 0x0B00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 6 +#define tx_err_inj_b_coarse_sel_fixed7 0x0C00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 7 +#define tx_err_inj_b_coarse_sel_fixed17 0x0D00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 17 +#define tx_err_inj_b_coarse_sel_fixed21 0x0E00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 21 +#define tx_err_inj_b_coarse_sel_fixed25 0x0F00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 25 +#define tx_err_inj_b_coarse_sel_clear 0xF0FF // Clear mask +#define tx_err_inj_b_ber_sel 0x0000 //Used to set the random bit error injection rate for pattern B. When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). #define tx_err_inj_b_ber_sel_clear 0x3FC0 // Clear mask // tx_dyn_recal_timeouts_pp Register field name data value Description @@ -1187,19 +1308,21 @@ const char* const ei4_GCR_sub_reg_names[] = { #define tx_dyn_recal_status_rpt_timeout_sel_clear 0xF3FF // Clear mask // tx_bist_cntl_pp Register field name data value Description -#define tx_bist_en 0x8000 //TBD +#define tx_bist_en 0x8000 //TBD. jgr #define tx_bist_en_clear 0x7FFF // Clear mask -#define tx_bist_clr 0x4000 //TBD +#define tx_bist_clr 0x4000 //TBD. jgr #define tx_bist_clr_clear 0xBFFF // Clear mask -#define tx_bist_prbs7_en 0x2000 //TBD +#define tx_bist_prbs7_en 0x2000 //TBD. This field is updated by the TX BIST logic when BIST is running. jgr #define tx_bist_prbs7_en_clear 0xDFFF // Clear mask // tx_ber_cntl_sls_pp Register field name data value Description -#define tx_err_inj_sls_mode 0x8000 //Used to set the random bit error injection during SLS. See workbook for details. +#define tx_err_inj_sls_mode 0x8000 //Used to set the random bit error injection for pattern A to work during SLS transmission only. #define tx_err_inj_sls_mode_clear 0x7FFF // Clear mask -#define tx_err_inj_sls_all_cmd 0x4000 //Used to qualify the SLS mode error injection, to inject on all command values. See workbook for details. +#define tx_err_inj_sls_all_cmd 0x4000 //Used to qualify the SLS mode error injection for pattern A, to inject on all SLS command transmissions. #define tx_err_inj_sls_all_cmd_clear 0xBFFF // Clear mask -#define tx_err_inj_sls_cmd 0x0000 //Used to qualify the SLS mode error injection, to only inject on this set command value. See workbook for details. +#define tx_err_inj_sls_recal 0x2000 //Used to qualify the SLS mode error injection for pattern A, to inject on the calibration lane only when not sending an SLS command. See workbook for details. +#define tx_err_inj_sls_recal_clear 0xDFFF // Clear mask +#define tx_err_inj_sls_cmd 0x0000 //Used to qualify the SLS mode error injection for pattern A, to inject on only this SLS command transmission. See workbook for SLS command codes. #define tx_err_inj_sls_cmd_clear 0xFFC0 // Clear mask // tx_cntl_pp Register field name data value Description @@ -1209,61 +1332,91 @@ const char* const ei4_GCR_sub_reg_names[] = { // tx_reset_cfg_pp Register field name data value Description #define tx_reset_cfg_hld_clear 0x0000 // Clear mask +// tx_tdr_cntl1_pp Register field name data value Description +#define tx_tdr_dac_cntl 0x0000 //Controls Variable Threshold Receiver for TDR function +#define tx_tdr_dac_cntl_clear 0x00FF // Clear mask +#define tx_tdr_phase_sel 0x0040 //Controls Phase Select for TDR function, 0 is for _n loeg, 1 is for _p leg. +#define tx_tdr_phase_sel_clear 0xFFBF // Clear mask + +// tx_tdr_cntl2_pp Register field name data value Description +#define tx_tdr_pulse_offset 0x0000 //Offset value for TDR pulse. +#define tx_tdr_pulse_offset_clear 0x000F // Clear mask + +// tx_tdr_cntl3_pp Register field name data value Description +#define tx_tdr_pulse_width 0x0000 //With of TDR pulse. +#define tx_tdr_pulse_width_clear 0x000F // Clear mask + // tx_impcal_pb Register field name data value Description -#define tx_zcal_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED. -#define tx_zcal_spare_clear 0x7FFF // Clear mask -#define tx_zcal_req 0x4000 //\bImpedance Calibration Sequence Enable\b +#define tx_zcal_req 0x4000 //Impedance Calibration Sequence Enable #define tx_zcal_req_clear 0xBFFF // Clear mask -#define tx_zcal_done 0x2000 //\bImpedance Calibration Sequence Complete\b +#define tx_zcal_done 0x2000 //Impedance Calibration Sequence Complete #define tx_zcal_done_clear 0xDFFF // Clear mask -#define tx_zcal_error 0x1000 //\bImpedance Calibration Sequence Error\b +#define tx_zcal_error 0x1000 //Impedance Calibration Sequence Error #define tx_zcal_error_clear 0xEFFF // Clear mask -#define tx_zcal_busy 0x0800 //\bImpedance Calibration Sequence Busy\b +#define tx_zcal_busy 0x0800 //Impedance Calibration Sequence Busy #define tx_zcal_busy_clear 0xF7FF // Clear mask -#define tx_zcal_force_sample 0x0400 //\bImpedance Comparison Sample Force\b +#define tx_zcal_force_sample 0x0400 //Impedance Comparison Sample Force #define tx_zcal_force_sample_clear 0xFBFF // Clear mask -#define tx_zcal_cmp_out 0x0200 //\bCalibration Circuit Unqualified Sample\b +#define tx_zcal_cmp_out 0x0200 //Calibration Circuit Unqualified Sample #define tx_zcal_cmp_out_clear 0xFDFF // Clear mask #define tx_zcal_sample_cnt_clear 0xFE00 // Clear mask // tx_impcal_nval_pb Register field name data value Description -#define tx_zcal_n 0x0000 //\bCalibration Circuit NSeg Enable Value\b May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices). +#define tx_zcal_n 0x0000 //Calibration Circuit NSeg Enable Value This holds the current value of the enabled segments and is 4x multiple of the actual segment count. May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices). #define tx_zcal_n_clear 0x007F // Clear mask // tx_impcal_pval_pb Register field name data value Description -#define tx_zcal_p 0x0000 //\bCalibration Circuit PSeg Enable Value\b May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices). +#define tx_zcal_p 0x0000 //Calibration Circuit PSeg Enable Value This holds the current value of the enabled segments and is 4x multiple of the actual segment count. May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices). #define tx_zcal_p_clear 0x007F // Clear mask // tx_impcal_p_4x_pb Register field name data value Description -#define tx_zcal_p_4x 0x0000 //\bCalibration Circuit PSeg-4X Enable Value\b May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0x15 is maximum slices). +#define tx_zcal_p_4x 0x0000 //Calibration Circuit PSeg-4X Enable Value This holds the current value of the enabled segments and is 2x multiple of the actual segment count. May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0x15 is maximum slices). #define tx_zcal_p_4x_clear 0x07FF // Clear mask // tx_impcal_swo1_pb Register field name data value Description -#define tx_zcal_swo_en 0x8000 //\bImpedance Calibration Software Override\b +#define tx_zcal_swo_en 0x8000 //Impedance Calibration Software Override #define tx_zcal_swo_en_clear 0x7FFF // Clear mask -#define tx_zcal_swo_cal_segs 0x4000 //\bImpedance Calibration Software Bank Select\b +#define tx_zcal_swo_cal_segs 0x4000 //Impedance Calibration Software Bank Select #define tx_zcal_swo_cal_segs_clear 0xBFFF // Clear mask -#define tx_zcal_swo_cmp_inv 0x2000 //\bImpedance Calibration Software Compare Invert\b +#define tx_zcal_swo_cmp_inv 0x2000 //Impedance Calibration Software Compare Invert #define tx_zcal_swo_cmp_inv_clear 0xDFFF // Clear mask -#define tx_zcal_swo_cmp_offset 0x1000 //\bImpedance Calibration Software Offset Flush\b +#define tx_zcal_swo_cmp_offset 0x1000 //Impedance Calibration Software Offset Flush #define tx_zcal_swo_cmp_offset_clear 0xEFFF // Clear mask -#define tx_zcal_swo_cmp_reset 0x0800 //\bImpedance Calibration Software Comparator reset\b +#define tx_zcal_swo_cmp_reset 0x0800 //Impedance Calibration Software Comparator reset #define tx_zcal_swo_cmp_reset_clear 0xF7FF // Clear mask -#define tx_zcal_swo_powerdown 0x0400 //\bImpedance Calibration Software Circuit Powerdown\b +#define tx_zcal_swo_powerdown 0x0400 //Impedance Calibration Software Circuit Powerdown #define tx_zcal_swo_powerdown_clear 0xFBFF // Clear mask -#define tx_zcal_cya_data_inv 0x0200 //\bImpedance Calibration CYA Sample Inversion\b +#define tx_zcal_cya_data_inv 0x0200 //Impedance Calibration CYA Sample Inversion #define tx_zcal_cya_data_inv_clear 0xFDFF // Clear mask -#define tx_zcal_test_ovr_2r 0x0100 //\bImpedance Calibration Test-Only 2R segment override\b +#define tx_zcal_test_ovr_2r 0x0100 //Impedance Calibration Test-Only 2R segment override #define tx_zcal_test_ovr_2r_clear 0xFEFF // Clear mask +#define tx_zcal_debug_mode_Filters 0x0001 //Calibration Circuit Debug Mode Select probeA=rcin_p, probeB=rcin_n Observe filter input nodes, rcin_n is off-chip. +#define tx_zcal_debug_mode_Comparators 0x0002 //Calibration Circuit Debug Mode Select probeA=comp_in_p, probeB=comp_in_n Observe comparator inputs. +#define tx_zcal_debug_mode_disabled11 0x0003 //Calibration Circuit Debug Mode Select Debug mode disabled +#define tx_zcal_debug_mode_clear 0xFFF0 // Clear mask // tx_impcal_swo2_pb Register field name data value Description -#define tx_zcal_sm_min_val 0x0000 //\bImpedance Calibration Minimum Search Threshold\b Low-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices). +#define tx_zcal_sm_min_val 0x0000 //Impedance Calibration Minimum Search Threshold Low-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices). #define tx_zcal_sm_min_val_clear 0x01FF // Clear mask -#define tx_zcal_sm_max_val 0x0000 //\bImpedance Calibration Maximum Search Threshold\b High-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices). +#define tx_zcal_sm_max_val 0x0000 //Impedance Calibration Maximum Search Threshold High-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices). #define tx_zcal_sm_max_val_clear 0xFE03 // Clear mask +// tx_analog_iref_pb Register field name data value Description +#define tx_iref_bc 0x0000 //Bias Code for the Iref macros on the TX side. All eight 3 bit codes enable current out. The cml voltage swings of the output current will vary with this code. +#define tx_iref_bc_clear 0x1FFF // Clear mask + +// tx_minikerf_pb Register field name data value Description +#define tx_minikerf 0x0000 //Used to configure the TX Minikerf for analog characterization. +#define tx_minikerf_clear 0x0000 // Clear mask + +// tx_init_version_pb Register field name data value Description +#define tx_init_version_clear 0x0000 // Clear mask + +// tx_scratch_reg_pb Register field name data value Description +#define tx_scratch_reg_clear 0x0000 // Clear mask + // rx_mode_pl Register field name data value Description -#define rx_lane_pdwn 0x8000 //Used to receive inhibit and fully power down a lane. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers rx_lane_disabled_vec_0_15 and rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines. +#define rx_lane_pdwn 0x8000 //Used to receive inhibit and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (rx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers rx_lane_disabled_vec_0_15 and rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. #define rx_lane_pdwn_clear 0x7FFF // Clear mask #define rx_lane_scramble_disable 0x0200 //Used to disable the RX descrambler on a specific lane or all lanes by using a per-lane/per-group global write. #define rx_lane_scramble_disable_clear 0xFDFF // Clear mask @@ -1271,10 +1424,10 @@ const char* const ei4_GCR_sub_reg_names[] = { // rx_cntl_pl Register field name data value Description #define rx_block_lock_lane 0x8000 //Enables rotation and checking for block lock. #define rx_block_lock_lane_clear 0x7FFF // Clear mask -#define rx_check_skew_lane 0x4000 //Per-Lane Initialization controls checks skew requst +#define rx_check_skew_lane 0x4000 //Per-Lane Initialization controls. Checks skew request #define rx_check_skew_lane_clear 0xBFFF // Clear mask -#define rx_cntl_pl_tbd 0x0000 //TBD -#define rx_cntl_pl_tbd_clear 0xC07F // Clear mask +#define rx_pdwn_lite 0x2000 //GCR Message: When set, partially powers down unused spare lanes when not being recalibrated +#define rx_pdwn_lite_clear 0xDFFF // Clear mask // rx_spare_mode_pl Register field name data value Description #define rx_pl_spare_mode_0 0x8000 //Per-lane spare mode latch @@ -1306,25 +1459,17 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_bist_done 0x4000 //Indicates a RXBIST has completed. #define rx_bist_done_clear 0xBFFF // Clear mask -// rx_eyeopt_mode_pl Register field name data value Description -#define rx_ddc_disable 0x8000 //When set to a 1 this causes the phase detector to stop running which results in the phase rotator value to stop updating. This mode is used for diagnostics and characterization. -#define rx_ddc_disable_clear 0x7FFF // Clear mask - -// rx_eyeopt_stat_pl Register field name data value Description -#define rx_eyeopt_stat_tbd 0x8000 //Eye optimization status. TBD -#define rx_eyeopt_stat_tbd_clear 0x7FFF // Clear mask - // rx_offset_even_pl Register field name data value Description #define rx_offset_even_samp1 0x0000 //This is the vertical offset of the even sampling latch. -#define rx_offset_even_samp1_clear 0xC0FF // Clear mask +#define rx_offset_even_samp1_clear 0x80FF // Clear mask #define rx_offset_even_samp0 0x0000 //This is the vertical offset of the even sampling latch. -#define rx_offset_even_samp0_clear 0x3FC0 // Clear mask +#define rx_offset_even_samp0_clear 0x7F80 // Clear mask // rx_offset_odd_pl Register field name data value Description #define rx_offset_odd_samp1 0x0000 //This is the vertical offset of the odd sampling latch. #define rx_offset_odd_samp1_clear 0x00FF // Clear mask #define rx_offset_odd_samp0 0x0000 //This is the vertical offset of the odd sampling latch. -#define rx_offset_odd_samp0_clear 0x3FC0 // Clear mask +#define rx_offset_odd_samp0_clear 0x7F80 // Clear mask // rx_amp_val_pl Register field name data value Description #define rx_amp_peak 0x0000 //This is the vertical offset of the pre-amp. @@ -1367,7 +1512,7 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_ext_sl_clear 0xFBFF // Clear mask // rx_fifo_stat_pl Register field name data value Description -#define rx_fifo_l2u_dly 0x0000 //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine. For setting X, the latency is 4*X to 4*X+4 UI. Default is 16-20 UI. +#define rx_fifo_l2u_dly 0x0000 //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine. For setting X, the latency is 4*X to 4*X+4 UI. Default is 20-24 UI. #define rx_fifo_l2u_dly_clear 0x0FFF // Clear mask #define rx_fifo_init 0x0800 //Initializes the fifo unload counter with the load counter and initializes the fifo load to unload delay #define rx_fifo_init_clear 0xF7FF // Clear mask @@ -1440,11 +1585,11 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_pl_fir_errs_clear 0x3FFF // Clear mask // rx_fir_mask_pl Register field name data value Description -#define rx_pl_fir_errs_mask 0x0000 //A 1 in this field indicates that a register or state machine parity error has occurred in per-group logic. +#define rx_pl_fir_errs_mask_err_pl_mask_ddc_sm 0x4000 //FIR mask for register or state machine parity checkers in per-lane logic. A value of 1 masks the error from generating a FIR error. Per-Lane DDC SM Parity Error. #define rx_pl_fir_errs_mask_clear 0x3FFF // Clear mask // rx_fir_error_inject_pl Register field name data value Description -#define rx_pl_fir_err_inj_inj_par_err 0x4000 //RX Per-Lane Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pl_fir_err_inj_inj_par_err 0x4000 //RX Per-Lane Parity Error Injection While this value is a 1, the parity bit is inverted in the specific parity checker. #define rx_pl_fir_err_inj_clear 0x3FFF // Clear mask // rx_sls_pl Register field name data value Description @@ -1474,12 +1619,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_fifo_dec_l2u_dly_clear 0xBFFF // Clear mask #define rx_clr_skew_valid 0x2000 //Clear skew valid registers #define rx_clr_skew_valid_clear 0xDFFF // Clear mask -#define rx_fifo_cntl_spare 0x1000 //Spare to make cr happy. -#define rx_fifo_cntl_spare_clear 0xEFFF // Clear mask // rx_ber_status_pl Register field name data value Description #define rx_ber_count 0x0000 //Per-Lane (PL) Diagnostic Bit Error Rate (BER) error counter. Increments when in diagnostic BER mode AND the output of the descrambler is non-zero. This counter counts errors on every UI so it is a true BER counter. -#define rx_ber_count_clear 0x80FF // Clear mask +#define rx_ber_count_clear 0x00FF // Clear mask #define rx_ber_count_saturated 0x0080 //PL Diag BER Error Counter saturation indicator. When '1' indicates that the error counter has saturated to the selected max value. A global per-lane read of this field will indicate if any lane error counters in the group are saturated. #define rx_ber_count_saturated_clear 0xFF7F // Clear mask #define rx_ber_count_frozen_by_lane 0x0040 //PL Diag BER Error Counter and or PP Timer has been frozen by another lane's error counter being saturated. @@ -1508,6 +1651,8 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_servo_op_all_done_b_clear 0xBFFF // Clear mask #define rx_servo_op 0x0000 //Servo Operation code #define rx_servo_op_clear 0xC1FF // Clear mask +#define rx_scope_en 0x0100 //Set this bit to enable per lane scope mode +#define rx_scope_en_clear 0xFEFF // Clear mask // rx_fifo_diag_0_15_pl Register field name data value Description #define rx_fifo_out_0_15 0x0000 //Diag Capture: fifo entries 0 to 15 @@ -1532,13 +1677,29 @@ const char* const ei4_GCR_sub_reg_names[] = { // rx_eye_width_cntl_pl Register field name data value Description #define rx_reset_hist_eye_width_min 0x8000 //RX Historic Eye Minimum Reset--reset historic min to maximum value and clears valid bits. #define rx_reset_hist_eye_width_min_clear 0x7FFF // Clear mask -#define rx_eye_width_cntl_pl_spare 0x4000 //RX Eye width control spare -#define rx_eye_width_cntl_pl_spare_clear 0xBFFF // Clear mask // rx_dfe_clkadj_pl Register field name data value Description #define rx_dfe_clkadj 0x0000 //TBD #define rx_dfe_clkadj_clear 0x0FFF // Clear mask +// rx_trace_pl Register field name data value Description +#define rx_ln_trc_en 0x8000 //Enable tracing of this lane +#define rx_ln_trc_en_clear 0x7FFF // Clear mask + +// rx_servo_ber_count_pl Register field name data value Description +#define rx_servo_ber_count 0x0000 //Servo-based bit error count. +#define rx_servo_ber_count_clear 0x000F // Clear mask + +// rx_eye_opt_stat_pl Register field name data value Description +#define rx_bad_eye_opt_ber 0x8000 //Eye opt Step failed BER test--lane marked bad +#define rx_bad_eye_opt_ber_clear 0x7FFF // Clear mask +#define rx_bad_eye_opt_width 0x4000 //Eye opt Step failed width test--lane marked bad +#define rx_bad_eye_opt_width_clear 0xBFFF // Clear mask +#define rx_bad_eye_opt_height 0x2000 //Eye opt Step failed height test--lane marked bad +#define rx_bad_eye_opt_height_clear 0xDFFF // Clear mask +#define rx_bad_eye_opt_ddc 0x1000 //Eye opt Step failed dynamic data centering--lane marked bad +#define rx_bad_eye_opt_ddc_clear 0xEFFF // Clear mask + // rx_clk_mode_pg Register field name data value Description #define rx_clk_pdwn 0x8000 //Used to disable the rx clock and put it into a low power state. #define rx_clk_pdwn_clear 0x7FFF // Clear mask @@ -1563,11 +1724,27 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_pg_spare_mode_7 0x0100 //Per-group spare mode latch #define rx_pg_spare_mode_7_clear 0xFEFF // Clear mask +// rx_stop_cntl_stat_pg Register field name data value Description +#define rx_stop_state_enable 0x8000 //Enable State machine stop of address +#define rx_stop_state_enable_clear 0x7FFF // Clear mask +#define rx_state_stopped 0x4000 //State Machines stopped +#define rx_state_stopped_clear 0xBFFF // Clear mask +#define rx_resume_from_stop 0x2000 //Resume stopped state machines and /or counters +#define rx_resume_from_stop_clear 0xDFFF // Clear mask +#define rx_stop_addr_msb 0x0000 //Stop address Most-significant four bits 0 to 3 +#define rx_stop_addr_msb_clear 0xFF0F // Clear mask +#define rx_stop_mask_msb 0x0000 //Stop mask Most-significant four bits 0 to 3 +#define rx_stop_mask_msb_clear 0xF0F0 // Clear mask + // rx_mode_pg Register field name data value Description #define rx_master_mode 0x8000 //Master Mode #define rx_master_mode_clear 0x7FFF // Clear mask #define rx_disable_fence_reset 0x4000 //Set to disable clearing of the RX and TX fence controls at the end of training. #define rx_disable_fence_reset_clear 0xBFFF // Clear mask +#define rx_pdwn_lite_disable 0x2000 //Disables the power down lite feature of unused spare lanes (generally should match tx_pdwn_lite_disable) +#define rx_pdwn_lite_disable_clear 0xDFFF // Clear mask +#define rx_use_sls_as_spr 0x1000 //Determines whether the RX SLS lane can be used as a spare lane on the bus to repair bad lanes (NOTE: if yes, recal is disabled once the SLS lane has been used as a spare lane.) +#define rx_use_sls_as_spr_clear 0xEFFF // Clear mask // rx_bus_repair_pg Register field name data value Description #define rx_bus_repair_count 0x0000 //TBD @@ -1585,9 +1762,13 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_grp_repair_vec_16_31 0x0000 //TBD #define rx_grp_repair_vec_16_31_clear 0x0000 // Clear mask -// rx_recal_mode_pg Register field name data value Description -#define rx_recal_disable 0x8000 //TBD -#define rx_recal_disable_clear 0x7FFF // Clear mask +// rx_stop_addr_lsb_pg Register field name data value Description +#define rx_stop_addr_lsb 0x0000 //Stop address least-significant 16 bits 4 to 19 +#define rx_stop_addr_lsb_clear 0x0000 // Clear mask + +// rx_stop_mask_lsb_pg Register field name data value Description +#define rx_stop_mask_lsb 0x0000 //Stop mask least-significant 16 bits 4 to 19 +#define rx_stop_mask_lsb_clear 0x0000 // Clear mask // rx_reset_act_pg Register field name data value Description #define rx_reset_cfg_ena 0x8000 //Enable Configurable Group Reset @@ -1617,14 +1798,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_minikerf 0x0000 //Used to configure the rx Minikerf for analog characterization. #define rx_minikerf_clear 0x0000 // Clear mask -// rx_bist_cntl_pg Register field name data value Description -#define rx_bist_en 0x8000 //TBD -#define rx_bist_en_clear 0x7FFF // Clear mask -#define rx_bist_jitter_pulse_ctl 0x0000 //TBD -#define rx_bist_jitter_pulse_ctl_clear 0x9FFF // Clear mask -#define rx_bist_min_eye_width 0x0000 //TBD -#define rx_bist_min_eye_width_clear 0xF03F // Clear mask - // rx_sls_mode_pg Register field name data value Description #define rx_sls_disable 0x8000 //Disables receiving & decoding of SLS commands #define rx_sls_disable_clear 0x7FFF // Clear mask @@ -1652,11 +1825,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_start_repair_clear 0xEFFF // Clear mask #define rx_start_func_mode 0x0800 //When this register is written to a 1 the training state machine will run the transition to functional data portion of the training states. #define rx_start_func_mode_clear 0xF7FF // Clear mask -#define rx_start_bist_helper_1 0x0200 //Starts BIST helper state machine. (wtbyp -#define rx_start_bist_helper_2 0x0400 //Starts BIST helper state machine. (ocal -#define rx_start_bist_helper_3 0x0600 //Starts BIST helper state machine. (bist -#define rx_start_bist_helper_clear 0xF9FF // Clear mask - +#define rx_start_bist 0x0400 //Run initializations for BIST before enabling the BIST state machine. +#define rx_start_bist_clear 0xFBFF // Clear mask +#define rx_start_offset_cal 0x0200 //Run offset cal. +#define rx_start_offset_cal_clear 0xFDFF // Clear mask +#define rx_start_wt_bypass 0x0100 //Run wiretest bypass. +#define rx_start_wt_bypass_clear 0xFEFF // Clear mask // rx_training_status_pg Register field name data value Description #define rx_wiretest_done 0x8000 //When this bit is read as a 1, the wiretest training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. @@ -1669,8 +1843,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_repair_done_clear 0xEFFF // Clear mask #define rx_func_mode_done 0x0800 //When this bit is read as a 1, the transition to functional data training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state. #define rx_func_mode_done_clear 0xF7FF // Clear mask -#define rx_bist_helper_done 0x0400 //When this bit is read as a 1, the BIST helper state machine has completed. -#define rx_bist_helper_done_clear 0xFBFF // Clear mask +#define rx_bist_started 0x0400 //When this bit is read as a 1, the RX BIST initialization has finished and RX BIST has started running. +#define rx_bist_started_clear 0xFBFF // Clear mask +#define rx_offset_cal_done 0x0200 //When this bit is read as a 1, offset cal has completed. +#define rx_offset_cal_done_clear 0xFDFF // Clear mask +#define rx_wt_bypass_done 0x0100 //When this bit is read as a 1, wiretest bypass has completed. +#define rx_wt_bypass_done_clear 0xFEFF // Clear mask #define rx_wiretest_failed 0x0080 //When this bit is read as a 1, the wiretest training state encountered an error. #define rx_wiretest_failed_clear 0xFF7F // Clear mask #define rx_deskew_failed 0x0040 //When this bit is read as a 1, the deskew training state encountered an error. @@ -1679,22 +1857,26 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_eye_opt_failed_clear 0xFFDF // Clear mask #define rx_repair_failed 0x0010 //When this bit is read as a 1, the static lane repair training state encountered an error. #define rx_repair_failed_clear 0xFFEF // Clear mask -#define rx_func_mode_failed 0x0008 //When this bit is read as a 1, the transition to functional data training state encountered and error. +#define rx_func_mode_failed 0x0008 //When this bit is read as a 1, the transition to functional data training state encountered an error. #define rx_func_mode_failed_clear 0xFFF7 // Clear mask - - +#define rx_start_bist_failed 0x0004 //When this bit is read as a 1, the RX BIST initialization has encountered and error. +#define rx_start_bist_failed_clear 0xFFFB // Clear mask +#define rx_offset_cal_failed 0x0002 //When this bit is read as a 1, offset cal has encountered an error. +#define rx_offset_cal_failed_clear 0xFFFD // Clear mask +#define rx_wt_bypass_failed 0x0001 //When this bit is read as a 1, wiretest bypass has encountered an error. +#define rx_wt_bypass_failed_clear 0xFFFE // Clear mask // rx_recal_status_pg Register field name data value Description -#define rx_recal_status 0x0000 //\bRX Recalibration Status\b +#define rx_recal_status 0x0000 //RX Recalibration Status #define rx_recal_status_clear 0x0000 // Clear mask // rx_timeout_sel_pg Register field name data value Description -#define rx_sls_timeout_sel_tap1 0x2000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 64k UI -#define rx_sls_timeout_sel_tap2 0x4000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 128k UI -#define rx_sls_timeout_sel_tap3 0x6000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 256k UI -#define rx_sls_timeout_sel_tap4 0x8000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 512k UI -#define rx_sls_timeout_sel_tap5 0xA000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 1024k UI -#define rx_sls_timeout_sel_tap6 0xC000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 32768k UI +#define rx_sls_timeout_sel_tap1 0x2000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 54.6us +#define rx_sls_timeout_sel_tap2 0x4000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 109.2us +#define rx_sls_timeout_sel_tap3 0x6000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 218.4us +#define rx_sls_timeout_sel_tap4 0x8000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 436.7us +#define rx_sls_timeout_sel_tap5 0xA000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 873.5us +#define rx_sls_timeout_sel_tap6 0xC000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 28.0ms #define rx_sls_timeout_sel_tap7 0xE000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) infinite #define rx_sls_timeout_sel_clear 0x1FFF // Clear mask #define rx_ds_bl_timeout_sel_tap1 0x0400 //Selects Deskew Block Lock Timeout value. 128k UI or 13.6us @@ -1742,22 +1924,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_fifo_final_l2u_min_err_thresh_tap3 0x000C //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel. 255 errors #define rx_fifo_final_l2u_min_err_thresh_clear 0xFF33 // Clear mask -// rx_state_debug_pg Register field name data value Description -#define rx_start_at_state_en 0x8000 //Enable Statemachine to Start -#define rx_start_at_state_en_clear 0x7FFF // Clear mask -#define rx_stop_at_state_en 0x4000 //Enable Statemachine to Stop -#define rx_stop_at_state_en_clear 0xBFFF // Clear mask -#define rx_state_stopped 0x2000 //Statemachine Has Stopped at RX_STOP_STATE -#define rx_state_stopped_clear 0xDFFF // Clear mask -#define rx_cur_state 0x0000 //Current Value of Statemachine Vector -#define rx_cur_state_clear 0xE01F // Clear mask - -// rx_state_val_pg Register field name data value Description -#define rx_start_state 0x0000 //Start Value for Statemachine -#define rx_start_state_clear 0x00FF // Clear mask -#define rx_stop_state 0x0000 //Stop Value for Statemachine -#define rx_stop_state_clear 0xFF00 // Clear mask - // rx_sls_status_pg Register field name data value Description #define rx_sls_cmd_val 0x8000 //Current SLS Command Valid #define rx_sls_cmd_val_clear 0x7FFF // Clear mask @@ -1796,48 +1962,61 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_sls_err_chk_cnt_clear 0xFF00 // Clear mask // rx_fir1_pg Register field name data value Description +#define rx_pg_fir1_errs_par_err_rx_rpr_state 0x0800 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. +#define rx_pg_fir1_errs_par_err_rx_eyeopt_state 0x0C00 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. +#define rx_pg_fir1_errs_par_err_dsm_state 0x0400 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. +#define rx_pg_fir1_errs_par_err_rxdsm_state 0x0400 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. #define rx_pg_fir1_errs_clear 0x0003 // Clear mask #define rx_pl_fir_err 0x0001 //Summary bit indicating an RX per-lane register or state machine parity error has occurred in one or more lanes. The rx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane. #define rx_pl_fir_err_clear 0xFFFE // Clear mask // rx_fir2_pg Register field name data value Description -#define rx_pg_fir2_errs_clear 0x1FFF // Clear mask +#define rx_pg_fir2_errs_err_sls_hndshk_sm 0x0200 //A Per-Group Register or State Machine Parity Error has occurred. RXCTL SLS Handshake SM Parity Error. +#define rx_pg_fir2_errs_clear 0x01FF // Clear mask // rx_fir1_mask_pg Register field name data value Description #define rx_pg_fir1_errs_mask_clear 0x0003 // Clear mask -#define rx_pg_chan_fail_mask 0x0002 //FIR mask for generation of channel fail error when Max Spares Exceeded is active. Default is disabled with a value of 1. -#define rx_pg_chan_fail_mask_clear 0xFFFD // Clear mask #define rx_pl_fir_err_mask 0x0001 //FIR mask for the summary bit that indicates an RX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane parity errors from causing a FIR error. #define rx_pl_fir_err_mask_clear 0xFFFE // Clear mask // rx_fir2_mask_pg Register field name data value Description -#define rx_pg_fir2_errs_mask_clear 0x1FFF // Clear mask +#define rx_pg_fir2_errs_mask_mask_sls_hndshk_sm 0x0200 //FIR mask for register or state machine parity checkers in per-group RX logic. A value of 1 masks the error from generating a FIR error. RXCTL SLS Handshake SM Parity Error Mask. +#define rx_pg_fir2_errs_mask_clear 0x01FF // Clear mask // rx_fir1_error_inject_pg Register field name data value Description -#define rx_pg_fir1_err_inj_inj_par_err 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pg_fir1_err_inj_1 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pg_fir1_err_inj_inj_rpr_sm 0x0800 //RX Per-Group Parity Error Injection RXCTL Repair SM Parity Error Inject. +#define rx_pg_fir1_err_inj_inj_eyeopt_sm 0x0C00 //RX Per-Group Parity Error Injection RXCTL Eyeopt SM Parity Error Inject. +#define rx_pg_fir1_err_inj_inj_dsm_sm 0x0400 //RX Per-Group Parity Error Injection RXCTL Deskew SM Parity Error Inject. +#define rx_pg_fir1_err_inj_inj_rxdsm_sm 0x0400 //RX Per-Group Parity Error Injection RXCTL RX Deskew SM Parity Error Inject. #define rx_pg_fir1_err_inj_clear 0x0003 // Clear mask // rx_fir2_error_inject_pg Register field name data value Description -#define rx_pg_fir2_err_inj_inj_par_err 0x2000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. -#define rx_pg_fir2_err_inj_clear 0x1FFF // Clear mask +#define rx_pg_fir2_err_inj_1 0x2000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pg_fir2_err_inj_inj_sls_hndshk_sm 0x0200 //RX Per-Group Parity Error Injection RXCTL SLS Handshake SM Parity Error Inject. +#define rx_pg_fir2_err_inj_clear 0x01FF // Clear mask // rx_fir_training_pg Register field name data value Description -#define rx_pg_fir_training_error 0x8000 //A Training Error has occurred. The Training Error FFDC registers should be read to help isolate to a particular piece of logic. +#define rx_pg_fir_training_error 0x8000 //This field is now defunct and is permanently masked in the rx_fir_training_mask_pg FIR isolation register. #define rx_pg_fir_training_error_clear 0x7FFF // Clear mask -#define rx_pg_fir_static_spare_deployed 0x4000 //A spare lane has been deployed during training to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed +#define rx_pg_fir_static_spare_deployed 0x4000 //A spare lane has been deployed during training to heal a lane that was detected as bad. rx_Static_Spare_Deployed (SSD) will be set after the repair training step if during training either wiretest, deskew, eyeopt or repair has detected one or more bad lanes have been detected. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed and the rx_bad_lane. #define rx_pg_fir_static_spare_deployed_clear 0xBFFF // Clear mask -#define rx_pg_fir_static_max_spares_exceeded 0x2000 //A lane has been detected as bad during training but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_static_max_spares_exceeded 0x2000 //A lane has been detected as bad during training but there are no spare lanes available to heal it. THIS FIR WILL NOT BE SET UNTIL THE REPAIR TRAINING STEP HAS BEEN RUN. THIS IS A CATASTROPHIC FAILURE FOR THE BUS WHEN IN MISSION MODE BUT ALL TRAINING STEPS WILL STILL BE RUN ON WHATEVER GOOD LANES THERE ARE. rx_static_max_spares_exceeded will be set if wiretest, deskew, eyeopt or repair find the excessive number of bad lanes. #define rx_pg_fir_static_max_spares_exceeded_clear 0xDFFF // Clear mask -#define rx_pg_fir_dynamic_spare_deployed 0x1000 //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. -#define rx_pg_fir_dynamic_spare_deployed_clear 0xEFFF // Clear mask -#define rx_pg_fir_dynamic_max_spares_exceeded 0x0800 //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. -#define rx_pg_fir_dynamic_max_spares_exceeded_clear 0xF7FF // Clear mask -#define rx_pg_fir_recal_error 0x0400 //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. -#define rx_pg_fir_recal_error_clear 0xFBFF // Clear mask -#define rx_pg_fir_recal_spare_deployed 0x0200 //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. -#define rx_pg_fir_recal_spare_deployed_clear 0xFDFF // Clear mask -#define rx_pg_fir_recal_max_spares_exceeded 0x0100 //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. -#define rx_pg_fir_recal_max_spares_exceeded_clear 0xFEFF // Clear mask +#define rx_pg_fir_dynamic_repair_error 0x1000 //A Dynamic Repair error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. +#define rx_pg_fir_dynamic_repair_error_clear 0xEFFF // Clear mask +#define rx_pg_fir_dynamic_spare_deployed 0x0800 //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. +#define rx_pg_fir_dynamic_spare_deployed_clear 0xF7FF // Clear mask +#define rx_pg_fir_dynamic_max_spares_exceeded 0x0400 //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_dynamic_max_spares_exceeded_clear 0xFBFF // Clear mask +#define rx_pg_fir_recal_error 0x0200 //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. +#define rx_pg_fir_recal_error_clear 0xFDFF // Clear mask +#define rx_pg_fir_recal_spare_deployed 0x0100 //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. +#define rx_pg_fir_recal_spare_deployed_clear 0xFEFF // Clear mask +#define rx_pg_fir_recal_max_spares_exceeded 0x0080 //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_recal_max_spares_exceeded_clear 0xFF7F // Clear mask +#define rx_pg_fir_too_many_bus_errors 0x0040 //More than one lane has been detected as having too many errors during functional operation. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define rx_pg_fir_too_many_bus_errors_clear 0xFFBF // Clear mask // rx_fir_training_mask_pg Register field name data value Description #define rx_pg_fir_training_error_mask 0x8000 //FIR mask for rx_pg_fir_training_error. @@ -1846,16 +2025,20 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_pg_fir_static_spare_deployed_mask_clear 0xBFFF // Clear mask #define rx_pg_fir_static_max_spares_exceeded_mask 0x2000 //FIR mask for rx_pg_fir_static_max_spares_exceeded #define rx_pg_fir_static_max_spares_exceeded_mask_clear 0xDFFF // Clear mask -#define rx_pg_fir_dynamic_spare_deployed_mask 0x1000 //FIR mask for rx_pg_fir_dynamic_spare_deployed. -#define rx_pg_fir_dynamic_spare_deployed_mask_clear 0xEFFF // Clear mask -#define rx_pg_fir_dynamic_max_spares_exceeded_mask 0x0800 //FIR mask for rx_pg_fir_dynamic_max_spares_exceeded. -#define rx_pg_fir_dynamic_max_spares_exceeded_mask_clear 0xF7FF // Clear mask -#define rx_pg_fir_recal_error_mask 0x0400 //FIR mask for rx_pg_fir_recal_error. -#define rx_pg_fir_recal_error_mask_clear 0xFBFF // Clear mask -#define rx_pg_fir_recal_spare_deployed_mask 0x0200 //FIR mask for rx_pg_fir_recal_spare_deployed. -#define rx_pg_fir_recal_spare_deployed_mask_clear 0xFDFF // Clear mask -#define rx_pg_fir_recal_max_spares_exceeded_mask 0x0100 //FIR mask for rx_pg_fir_recal_max_spares_exceeded. -#define rx_pg_fir_recal_max_spares_exceeded_mask_clear 0xFEFF // Clear mask +#define rx_pg_fir_dynamic_repair_error_mask 0x1000 //FIR mask for rx_pg_fir_dynamic_repair_error +#define rx_pg_fir_dynamic_repair_error_mask_clear 0xEFFF // Clear mask +#define rx_pg_fir_dynamic_spare_deployed_mask 0x0800 //FIR mask for rx_pg_fir_dynamic_spare_deployed. +#define rx_pg_fir_dynamic_spare_deployed_mask_clear 0xF7FF // Clear mask +#define rx_pg_fir_dynamic_max_spares_exceeded_mask 0x0400 //FIR mask for rx_pg_fir_dynamic_max_spares_exceeded. +#define rx_pg_fir_dynamic_max_spares_exceeded_mask_clear 0xFBFF // Clear mask +#define rx_pg_fir_recal_error_mask 0x0200 //FIR mask for rx_pg_fir_recal_error. +#define rx_pg_fir_recal_error_mask_clear 0xFDFF // Clear mask +#define rx_pg_fir_recal_spare_deployed_mask 0x0100 //FIR mask for rx_pg_fir_recal_spare_deployed. +#define rx_pg_fir_recal_spare_deployed_mask_clear 0xFEFF // Clear mask +#define rx_pg_fir_recal_max_spares_exceeded_mask 0x0080 //FIR mask for rx_pg_fir_recal_max_spares_exceeded. +#define rx_pg_fir_recal_max_spares_exceeded_mask_clear 0xFF7F // Clear mask +#define rx_pg_fir_too_many_bus_errors_mask 0x0040 //FIR mask for rx_pg_fir_too_many_bus_errors. +#define rx_pg_fir_too_many_bus_errors_mask_clear 0xFFBF // Clear mask // rx_timeout_sel1_pg Register field name data value Description #define rx_eo_offset_timeout_sel_tap1 0x2000 //Selects Latch offset timeout. 128k UI or 13.6us @@ -1902,7 +2085,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_eo_final_l2u_timeout_sel_clear 0xFFFE // Clear mask // rx_lane_bad_vec_0_15_pg Register field name data value Description -#define rx_lane_bad_vec_0_15 0x0000 //Lanes found bad by HW (status) or method to force lane bad from software (control). #define rx_lane_bad_vec_0_15_clear 0x0000 // Clear mask // rx_lane_bad_vec_16_31_pg Register field name data value Description @@ -2022,6 +2204,18 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_func_mode_timeout_sel_tap6 0xC000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. 64M UI or 7ms #define rx_func_mode_timeout_sel_tap7 0xE000 //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel. infinite #define rx_func_mode_timeout_sel_clear 0x1FFF // Clear mask +#define rx_rc_slowdown_timeout_sel_tap1 0x0400 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. 128k UI or 13.7us +#define rx_rc_slowdown_timeout_sel_tap2 0x0800 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. 256k UI or 27.3us +#define rx_rc_slowdown_timeout_sel_tap3 0x0C00 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. 512k UI or 54.6us +#define rx_rc_slowdown_timeout_sel_tap4 0x1000 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. 1M UI or 109.2us +#define rx_rc_slowdown_timeout_sel_tap5 0x1400 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. 2M UI or 218.5us +#define rx_rc_slowdown_timeout_sel_tap6 0x1800 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. 64M UI or 7ms +#define rx_rc_slowdown_timeout_sel_tap7 0x1C00 //Selects Recal Slowdown timeout. Note that his should be longer than rx_sls_timeout_sel. infinite +#define rx_rc_slowdown_timeout_sel_clear 0xE3FF // Clear mask +#define rx_pup_lite_wait_sel_tap1 0x0100 //How long to wait for analog logic to power up an unused spare lane for recal/repair 107ns (default value +#define rx_pup_lite_wait_sel_tap2 0x0200 //How long to wait for analog logic to power up an unused spare lane for recal/repair 213ns +#define rx_pup_lite_wait_sel_tap3 0x0300 //How long to wait for analog logic to power up an unused spare lane for recal/repair 427ns +#define rx_pup_lite_wait_sel_clear 0xFCFF // Clear mask // rx_misc_analog_pg Register field name data value Description #define rx_c4_sel 0x0000 //Select 1 of 4 possible phases for the C4 clock to send along with the data for integration flexibility and tuning for slack into the Rx FIFO. @@ -2047,19 +2241,31 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_dyn_rpr_complete_gcrmsg 0x0040 //GCR Message: CRC/ECC Bad Lane Repaired #define rx_dyn_rpr_complete_gcrmsg_clear 0xFFBF // Clear mask -// rx_dyn_rpr_err_tallying_pg Register field name data value Description +// rx_dyn_rpr_err_tallying1_pg Register field name data value Description #define rx_dyn_rpr_bad_lane_max 0x0000 //CRC/ECC Dynamic Repair: Max number of times a lane can be found bad before repaired -#define rx_dyn_rpr_bad_lane_max_clear 0x07FF // Clear mask -#define rx_dyn_rpr_err_cntr_duration_tap1 0x0100 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 106.6ns -#define rx_dyn_rpr_err_cntr_duration_tap2 0x0200 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 1.7uS -#define rx_dyn_rpr_err_cntr_duration_tap3 0x0300 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 27.3uS -#define rx_dyn_rpr_err_cntr_duration_tap4 0x0400 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 436.7uS -#define rx_dyn_rpr_err_cntr_duration_tap5 0x0500 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 7.0mS -#define rx_dyn_rpr_err_cntr_duration_tap6 0x0600 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 111.8mS -#define rx_dyn_rpr_err_cntr_duration_tap7 0x0700 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 1.8S -#define rx_dyn_rpr_err_cntr_duration_clear 0xF8FF // Clear mask -#define rx_dyn_rpr_clr_err_cntr 0x0080 //CRC/ECC Dynamic Repair: Firmware-based clear of error counter register -#define rx_dyn_rpr_clr_err_cntr_clear 0xFF7F // Clear mask +#define rx_dyn_rpr_bad_lane_max_clear 0x01FF // Clear mask +#define rx_dyn_rpr_err_cntr1_duration_tap1 0x0020 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 853.0ns & 1.3uS +#define rx_dyn_rpr_err_cntr1_duration_tap2 0x0040 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 27.3uS & 41.0uS +#define rx_dyn_rpr_err_cntr1_duration_tap3 0x0060 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 873.5uS & 1.3mS +#define rx_dyn_rpr_err_cntr1_duration_tap4 0x0080 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 1.7mS & 2.6mS +#define rx_dyn_rpr_err_cntr1_duration_tap5 0x00A0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 3.5mS & 5.1mS +#define rx_dyn_rpr_err_cntr1_duration_tap6 0x00C0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 7.0mS & 10.5mS +#define rx_dyn_rpr_err_cntr1_duration_tap7 0x00E0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 14.0mS & 21.0mS +#define rx_dyn_rpr_err_cntr1_duration_tap8 0x0100 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 28.0mS & 41.9mS +#define rx_dyn_rpr_err_cntr1_duration_tap9 0x0120 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 55.9mS & 83.9mS +#define rx_dyn_rpr_err_cntr1_duration_tap10 0x0140 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 111.8mS & 167.8mS +#define rx_dyn_rpr_err_cntr1_duration_tap11 0x0160 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 223.6mS & 335.5mS +#define rx_dyn_rpr_err_cntr1_duration_tap12 0x0180 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 447.2mS & 671.1mS +#define rx_dyn_rpr_err_cntr1_duration_tap13 0x01A0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 894.4mS & 1.3 S +#define rx_dyn_rpr_err_cntr1_duration_tap14 0x01C0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 1.8 S & 2.7 S +#define rx_dyn_rpr_err_cntr1_duration_tap15 0x01E0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) infinite +#define rx_dyn_rpr_err_cntr1_duration_clear 0x3E1F // Clear mask +#define rx_dyn_rpr_clr_err_cntr1 0x0010 //CRC/ECC Dynamic Repair: Firmware-based clear of lane error counter1 register +#define rx_dyn_rpr_clr_err_cntr1_clear 0xFFEF // Clear mask +#define rx_dyn_rpr_disable 0x0008 //CRC/ECC Dynamic Repair: When set, disables dynamic repair error tallying (both per lane and per bus error counters...cntr1 & cntr2) +#define rx_dyn_rpr_disable_clear 0xFFF7 // Clear mask +#define rx_dyn_rpr_enc_bad_data_lane_width 0x0000 //CRC/ECC Dynamic Repair: Width of the enc_bad_data_lane vector used to determine number of 1s in clear code +#define rx_dyn_rpr_enc_bad_data_lane_width_clear 0xFFB8 // Clear mask // rx_eo_final_l2u_gcrmsgs_pg Register field name data value Description #define rx_eo_final_l2u_dly_seq_gcrmsg_fl2uallchg 0x4000 //GCR Message: RX Final Load to Unload Delay GCR messages Indicate all groups have calculated max load to unload change. @@ -2088,7 +2294,9 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_gcr_msg_debug_write_data_clear 0x0000 // Clear mask // rx_dyn_recal_pg Register field name data value Description -#define rx_dyn_recal_main_state_clear 0x00FF // Clear mask +#define rx_servo_recal_ip 0x8000 //RX Servo Lane Calibration In Progress +#define rx_servo_recal_ip_clear 0x7FFF // Clear mask +#define rx_dyn_recal_main_state_clear 0xC0FF // Clear mask #define rx_dyn_recal_hndshk_state_clear 0x7F80 // Clear mask // rx_wt_clk_status_pg Register field name data value Description @@ -2114,26 +2322,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_dyn_recal_overall_timeout_sel_clear 0x1FFF // Clear mask #define rx_dyn_recal_suspend 0x1000 //Suspend Dynamic Recalibration; otherwise starts automatically after link training #define rx_dyn_recal_suspend_clear 0xEFFF // Clear mask -#define rx_dyn_recal_latch_offset 0x0200 //RX Dynamic Recalibration latch offset adjustment enable (EDI only) -#define rx_dyn_recal_latch_offset_clear 0xFDFF // Clear mask -#define rx_dyn_recal_ctle 0x0100 //RX Dynamic Recalibration CTLE/Peakin enable (EDI only) -#define rx_dyn_recal_ctle_clear 0xFEFF // Clear mask -#define rx_dyn_recal_vga 0x0080 //RX Dynamic Recalibration VGA gain and offset adjust enable (EDI only) -#define rx_dyn_recal_vga_clear 0xFF7F // Clear mask -#define rx_dyn_recal_dfe_h1 0x0040 //RX Dynamic Recalibration DFE H1 adjust enable (EDI only) -#define rx_dyn_recal_dfe_h1_clear 0xFFBF // Clear mask -#define rx_dyn_recal_h1ap_tweak 0x0020 //RX Dynamic Recalibration H1/AN PR adjust enable (EDI only) -#define rx_dyn_recal_h1ap_tweak_clear 0xFFDF // Clear mask -#define rx_dyn_recal_ddc 0x0010 //RX Dynamic Recalibration Dynamic data centering enable (EDI only) -#define rx_dyn_recal_ddc_clear 0xFFEF // Clear mask -#define rx_dyn_recal_ber_test 0x0008 //RX Dynamic Recalibration Dynamic data centering enable (EDI only) -#define rx_dyn_recal_ber_test_clear 0xFFF7 // Clear mask -#define rx_dyn_recal_ber_test_timeout 0x0000 //RX Dynamic Recalibration Bit Error Rate test timeout (EDI only) -#define rx_dyn_recal_ber_test_timeout_clear 0xFFB8 // Clear mask - -// rx_servo_recal_gcrmsg_pg Register field name data value Description -#define rx_servo_recal_done_gcrmsg 0x8000 //GCR Message: RX Servo Done Calibrating Lane for Dynamic Recal -#define rx_servo_recal_done_gcrmsg_clear 0x7FFF // Clear mask // rx_dyn_recal_gcrmsg_pg Register field name data value Description #define rx_dyn_recal_ip_gcrmsg 0x8000 //GCR Message: RX Dynamic Recalibration In Progress @@ -2146,20 +2334,24 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_dyn_recal_timeout_gcrmsg_clear 0xEFFF // Clear mask // rx_wiretest_pll_cntl_pg Register field name data value Description -#define rx_wt_cu_pll_pgood 0x8000 //RX cleanup PLL Enable +#define rx_wt_cu_pll_pgood 0x8000 //RX PLL/DLL Enable #define rx_wt_cu_pll_pgood_clear 0x7FFF // Clear mask -#define rx_wt_cu_pll_reset 0x4000 //RX cleanup PLL Enable Request +#define rx_wt_cu_pll_reset 0x4000 //RX PLL/DLL Enable Request #define rx_wt_cu_pll_reset_clear 0xBFFF // Clear mask -#define rx_wt_cu_pll_pgooddly_50ns 0x0800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Nominal 50ns Reset per PLL Spec -#define rx_wt_cu_pll_pgooddly_100ns 0x1000 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Double Nominal 50ns Reset per PLL Spec -#define rx_wt_cu_pll_pgooddly_960ui 0x1800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Typical simulation delay exceeding TX PLL 40-refclk locking period -#define rx_wt_cu_pll_pgooddly_unused_100 0x2000 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Reserved -#define rx_wt_cu_pll_pgooddly_unused_101 0x2800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Reserved -#define rx_wt_cu_pll_pgooddly_MAX 0x3000 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. 1024 UI -#define rx_wt_cu_pll_pgooddly_disable 0x3800 //RX cleanup PLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Disable rx_wt_cu_pll_reset +#define rx_wt_cu_pll_pgooddly_50ns 0x0800 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Nominal 50ns Reset per PLL Spec +#define rx_wt_cu_pll_pgooddly_100ns 0x1000 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Double Nominal 50ns Reset per PLL Spec +#define rx_wt_cu_pll_pgooddly_960ui 0x1800 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Typical simulation delay exceeding TX PLL 40-refclk locking period +#define rx_wt_cu_pll_pgooddly_unused_100 0x2000 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Reserved +#define rx_wt_cu_pll_pgooddly_unused_101 0x2800 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Reserved +#define rx_wt_cu_pll_pgooddly_MAX 0x3000 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. 1024 UI +#define rx_wt_cu_pll_pgooddly_disable 0x3800 //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set. Disable rx_wt_cu_pll_reset #define rx_wt_cu_pll_pgooddly_clear 0xC7FF // Clear mask -#define rx_wt_cu_pll_lock 0x0400 //RX cleanup PLL Locked +#define rx_wt_cu_pll_lock 0x0400 //RX PLL/DLL Locked #define rx_wt_cu_pll_lock_clear 0xFBFF // Clear mask +#define rx_wt_pll_refclksel 0x0200 //Select between IO clock and BIST/Refclock +#define rx_wt_pll_refclksel_clear 0xFDFF // Clear mask +#define rx_pll_refclksel_scom_en 0x0100 //Selects between PLL controls and GCR register to select refclk +#define rx_pll_refclksel_scom_en_clear 0xFEFF // Clear mask // rx_eo_step_cntl_pg Register field name data value Description #define rx_eo_enable_latch_offset_cal 0x8000 //RX eye optimization latch offset adjustment enable @@ -2176,6 +2368,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_eo_enable_ddc_clear 0xFDFF // Clear mask #define rx_eo_enable_final_l2u_adj 0x0080 //RX eye optimization Final RX FIFO load-to-unload delay adjustment enable #define rx_eo_enable_final_l2u_adj_clear 0xFF7F // Clear mask +#define rx_eo_enable_ber_test 0x0040 //RX eye optimization Bit error rate test enable +#define rx_eo_enable_ber_test_clear 0xFFBF // Clear mask +#define rx_eo_enable_result_check 0x0020 //RX eye optimization Final results check enable +#define rx_eo_enable_result_check_clear 0xFFDF // Clear mask +#define rx_eo_enable_ctle_edge_track_only 0x0010 //RX eye optimization CTLE/Peakin enable with edge tracking only +#define rx_eo_enable_ctle_edge_track_only_clear 0xFFEF // Clear mask // rx_eo_step_stat_pg Register field name data value Description #define rx_eo_latch_offset_done 0x8000 //RX eye optimization latch offset adjustment done @@ -2194,6 +2392,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_eo_final_l2u_adj_done_clear 0xFF7F // Clear mask #define rx_eo_dfe_flag 0x0040 //RX eye optimization DFE mode flag #define rx_eo_dfe_flag_clear 0xFFBF // Clear mask +#define rx_eo_ber_test_done 0x0020 //RX eye optimization Bit Error rate test done +#define rx_eo_ber_test_done_clear 0xFFDF // Clear mask +#define rx_eo_result_check_done 0x0010 //RX eye optimization Eye width/heightER check done +#define rx_eo_result_check_done_clear 0xFFEF // Clear mask // rx_eo_step_fail_pg Register field name data value Description #define rx_eo_latch_offset_failed 0x8000 //RX eye optimization latch offset adjustment failed @@ -2210,6 +2412,8 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_eo_ddc_failed_clear 0xFDFF // Clear mask #define rx_eo_final_l2u_adj_failed 0x0080 //RX eye optimization Final RX FIFO load-to-unload adjust failed #define rx_eo_final_l2u_adj_failed_clear 0xFF7F // Clear mask +#define rx_eo_result_check_failed 0x0040 //RX eye optimization Final Result checking failed +#define rx_eo_result_check_failed_clear 0xFFBF // Clear mask // rx_ap_pg Register field name data value Description #define rx_ap_even_work 0x0000 //RX Ap even working register @@ -2256,33 +2460,17 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_eo_converged_end_count_clear 0xF0FF // Clear mask // rx_sls_rcvy_pg Register field name data value Description +#define rx_sls_rcvy_disable 0x8000 //Disable SLS Recovery +#define rx_sls_rcvy_disable_clear 0x7FFF // Clear mask #define rx_sls_rcvy_state_clear 0xE0FF // Clear mask // rx_sls_rcvy_gcrmsg_pg Register field name data value Description -#define rx_slv_shdw_done_fin_gcrmsg 0x8000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done -#define rx_slv_shdw_done_fin_gcrmsg_clear 0x7FFF // Clear mask -#define rx_slv_shdw_nop_fin_gcrmsg 0x4000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define rx_slv_shdw_nop_fin_gcrmsg_clear 0xBFFF // Clear mask -#define rx_slv_shdw_rpr_done_fin_gcrmsg 0x2000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done -#define rx_slv_shdw_rpr_done_fin_gcrmsg_clear 0xDFFF // Clear mask -#define rx_slv_shdw_rpr_nop_fin_gcrmsg 0x1000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define rx_slv_shdw_rpr_nop_fin_gcrmsg_clear 0xEFFF // Clear mask -#define rx_slv_unshdw_done_fin_gcrmsg 0x0800 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done -#define rx_slv_unshdw_done_fin_gcrmsg_clear 0xF7FF // Clear mask -#define rx_slv_unshdw_nop_fin_gcrmsg 0x0400 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define rx_slv_unshdw_nop_fin_gcrmsg_clear 0xFBFF // Clear mask -#define rx_slv_unshdw_rpr_done_fin_gcrmsg 0x0200 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done -#define rx_slv_unshdw_rpr_done_fin_gcrmsg_clear 0xFDFF // Clear mask -#define rx_slv_unshdw_rpr_nop_fin_gcrmsg 0x0100 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear 0xFEFF // Clear mask -#define rx_slv_recal_done_nop_fin_gcrmsg 0x0080 //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop -#define rx_slv_recal_done_nop_fin_gcrmsg_clear 0xFF7F // Clear mask -#define rx_slv_recal_fail_nop_fin_gcrmsg 0x0040 //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop -#define rx_slv_recal_fail_nop_fin_gcrmsg_clear 0xFFBF // Clear mask -#define rx_sls_rcvy_rx_ip_gcrmsg 0x0020 //GCR Message: SLS Rcvy; RX Lane Repair IP -#define rx_sls_rcvy_rx_ip_gcrmsg_clear 0xFFDF // Clear mask -#define rx_sls_rcvy_rx_rpred_gcrmsg 0x0010 //GCR Message: SLS Rcvy; RX Lane Repair Done -#define rx_sls_rcvy_rx_rpred_gcrmsg_clear 0xFFEF // Clear mask +#define rx_sls_rcvy_req_gcrmsg 0x8000 //GCR Message: SLS Rcvy; RX Lane Repair Req +#define rx_sls_rcvy_req_gcrmsg_clear 0x7FFF // Clear mask +#define rx_sls_rcvy_ip_gcrmsg 0x4000 //GCR Message: SLS Rcvy; RX Lane Repair IP +#define rx_sls_rcvy_ip_gcrmsg_clear 0xBFFF // Clear mask +#define rx_sls_rcvy_done_gcrmsg 0x2000 //GCR Message: SLS Rcvy; RX Lane Repair Done +#define rx_sls_rcvy_done_gcrmsg_clear 0xDFFF // Clear mask // rx_tx_lane_info_gcrmsg_pg Register field name data value Description #define rx_tx_bad_lane_cntr_gcrmsg 0x0000 //GCR Message: RX Side TX Bad Lane Counter @@ -2297,12 +2485,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_trc_mode_tap2 0x2000 //RX Trace Mode SLS Handshake State Machines with Recovery #define rx_trc_mode_tap3 0x3000 //RX Trace Mode Dynamic Recal State Machines #define rx_trc_mode_tap4 0x4000 //RX Trace Mode Recal Handshake State Machine with Recovery -#define rx_trc_mode_tap5 0x5000 //RX Trace Mode CRC/ECC Tallying Logic +#define rx_trc_mode_tap5 0x5000 //RX Trace Mode CRC or ECC Tallying Logic #define rx_trc_mode_tap6 0x6000 //RX Trace Mode RX SLS Commands #define rx_trc_mode_tap7 0x7000 //RX Trace Mode RX Bad Lanes #define rx_trc_mode_tap8 0x8000 //RX Trace Mode RX SLS Lanes -#define rx_trc_mode_tap9 0x9000 //RX Trace Mode TBD -#define rx_trc_mode_tap10 0xA000 //RX Trace Mode TBD +#define rx_trc_mode_tap9 0x9000 //RX Trace Mode GCR +#define rx_trc_mode_tap10 0xA000 //RX Trace Mode Per Lane / Per Pack Trace (see rx_pp_trc_mode for details #define rx_trc_mode_tap11 0xB000 //RX Trace Mode TBD #define rx_trc_mode_tap12 0xC000 //RX Trace Mode TBD #define rx_trc_mode_tap13 0xD000 //RX Trace Mode TBD @@ -2311,13 +2499,117 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_trc_mode_clear 0x0FFF // Clear mask #define rx_trc_grp_clear 0xFC0F // Clear mask +// rx_rc_step_cntl_pg Register field name data value Description +#define rx_rc_enable_latch_offset_cal 0x8000 //RX recalibration latch offset adjustment enable +#define rx_rc_enable_latch_offset_cal_clear 0x7FFF // Clear mask +#define rx_rc_enable_ctle_cal 0x4000 //RX recalibration CTLE/Peaking enable +#define rx_rc_enable_ctle_cal_clear 0xBFFF // Clear mask +#define rx_rc_enable_vga_cal 0x2000 //RX recalibration VGA gainand offset adjust enable +#define rx_rc_enable_vga_cal_clear 0xDFFF // Clear mask +#define rx_rc_enable_dfe_h1_cal 0x0800 //RX recalibration DFE H1 adjust enable +#define rx_rc_enable_dfe_h1_cal_clear 0xF7FF // Clear mask +#define rx_rc_enable_h1ap_tweak 0x0400 //RX recalibration H1/AN PR adjust enable +#define rx_rc_enable_h1ap_tweak_clear 0xFBFF // Clear mask +#define rx_rc_enable_ddc 0x0200 //RX recalibration Dynamic data centering enable +#define rx_rc_enable_ddc_clear 0xFDFF // Clear mask +#define rx_rc_enable_ber_test 0x0080 //RX recalibration Bit error rate test enable +#define rx_rc_enable_ber_test_clear 0xFF7F // Clear mask +#define rx_rc_enable_result_check 0x0040 //RX recalibration Final results check enable +#define rx_rc_enable_result_check_clear 0xFFBF // Clear mask +#define rx_rc_enable_ctle_edge_track_only 0x0010 //RX recalibration CTLE/Peaking enable with edge tracking only +#define rx_rc_enable_ctle_edge_track_only_clear 0xFFEF // Clear mask + +// rx_eo_recal_pg Register field name data value Description +#define rx_eye_opt_state 0x0000 //Common EDI/EI4 Eye optimizaton State Machine +#define rx_eye_opt_state_clear 0x00FF // Clear mask +#define rx_recal_state 0x0000 //Common EDI/EI4 recalibration State Machine +#define rx_recal_state_clear 0xFF00 // Clear mask + +// rx_servo_ber_count_pg Register field name data value Description +#define rx_servo_ber_count_work 0x0000 //Rx servo-based bit error rate count working register +#define rx_servo_ber_count_work_clear 0x000F // Clear mask + +// rx_func_state_pg Register field name data value Description +#define rx_func_mode_state 0x0000 //Functional Mode State Machine(RJR): +#define rx_func_mode_state_clear 0x0FFF // Clear mask + +// rx_dyn_rpr_debug_pg Register field name data value Description +#define rx_dyn_rpr_enc_bad_data_lane_debug 0x0000 //For testfloor/debug purposes, specify the encoded bad data lane to report to the dynamic repair tally logic +#define rx_dyn_rpr_enc_bad_data_lane_debug_clear 0x01FF // Clear mask +#define rx_dyn_rpr_bad_lane_valid_debug 0x0080 //For testfloor/debug purposes, the specified encoded bad data lane will be tallied as having one cycle of a valid CRC/ECC error (this is a write-only pulse register) +#define rx_dyn_rpr_bad_lane_valid_debug_clear 0xFF7F // Clear mask + +// rx_dyn_rpr_err_tallying2_pg Register field name data value Description +#define rx_dyn_rpr_bad_bus_max 0x0000 //CRC/ECC Dynamic Repair: Max number of times CRC or ECC errors can be found on the bus (not included in the bad lane cntr1 tally) before setting a FIR error +#define rx_dyn_rpr_bad_bus_max_clear 0x01FF // Clear mask +#define rx_dyn_rpr_err_cntr2_duration_tap1 0x0020 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 853.0ns & 1.3uS +#define rx_dyn_rpr_err_cntr2_duration_tap2 0x0040 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 27.3uS & 41.0uS +#define rx_dyn_rpr_err_cntr2_duration_tap3 0x0060 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 873.5uS & 1.3mS +#define rx_dyn_rpr_err_cntr2_duration_tap4 0x0080 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 1.7mS & 2.6mS +#define rx_dyn_rpr_err_cntr2_duration_tap5 0x00A0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 3.5mS & 5.1mS +#define rx_dyn_rpr_err_cntr2_duration_tap6 0x00C0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 7.0mS & 10.5mS +#define rx_dyn_rpr_err_cntr2_duration_tap7 0x00E0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 14.0mS & 21.0mS +#define rx_dyn_rpr_err_cntr2_duration_tap8 0x0100 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 28.0mS & 41.9mS +#define rx_dyn_rpr_err_cntr2_duration_tap9 0x0120 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 55.9mS & 83.9mS +#define rx_dyn_rpr_err_cntr2_duration_tap10 0x0140 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 111.8mS & 167.8mS +#define rx_dyn_rpr_err_cntr2_duration_tap11 0x0160 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 223.6mS & 335.5mS +#define rx_dyn_rpr_err_cntr2_duration_tap12 0x0180 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 447.2mS & 671.1mS +#define rx_dyn_rpr_err_cntr2_duration_tap13 0x01A0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 894.4mS & 1.3 S +#define rx_dyn_rpr_err_cntr2_duration_tap14 0x01C0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 1.8 S & 2.7 S +#define rx_dyn_rpr_err_cntr2_duration_tap15 0x01E0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) infinite +#define rx_dyn_rpr_err_cntr2_duration_clear 0x3E1F // Clear mask +#define rx_dyn_rpr_clr_err_cntr2 0x0010 //CRC/ECC Dynamic Repair: Firmware-based clear of bus error counter2 register +#define rx_dyn_rpr_clr_err_cntr2_clear 0xFFEF // Clear mask + +// rx_result_chk_pg Register field name data value Description +#define rx_min_eye_width 0x0000 //Minimum acceptable eye width used during init or recal results checking--EDI or EI4 +#define rx_min_eye_width_clear 0xC0FF // Clear mask +#define rx_min_eye_height 0x0000 //Minimum acceptable eye height used during init or recal results checking--EDI only +#define rx_min_eye_height_clear 0xFF00 // Clear mask + +// rx_ber_chk_pg Register field name data value Description +#define rx_max_ber_check_count 0x0000 //Maximum acceptable number of bit errors allowable after recal--EDI only +#define rx_max_ber_check_count_clear 0x0000 // Clear mask + +// rx_sls_rcvy_fin_gcrmsg_pg Register field name data value Description +#define rx_slv_shdw_done_fin_gcrmsg 0x8000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done +#define rx_slv_shdw_done_fin_gcrmsg_clear 0x7FFF // Clear mask +#define rx_slv_shdw_nop_fin_gcrmsg 0x4000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_shdw_nop_fin_gcrmsg_clear 0xBFFF // Clear mask +#define rx_slv_shdw_rpr_done_fin_gcrmsg 0x2000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done +#define rx_slv_shdw_rpr_done_fin_gcrmsg_clear 0xDFFF // Clear mask +#define rx_slv_shdw_rpr_nop_fin_gcrmsg 0x1000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_shdw_rpr_nop_fin_gcrmsg_clear 0xEFFF // Clear mask +#define rx_slv_unshdw_done_fin_gcrmsg 0x0800 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done +#define rx_slv_unshdw_done_fin_gcrmsg_clear 0xF7FF // Clear mask +#define rx_slv_unshdw_nop_fin_gcrmsg 0x0400 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_unshdw_nop_fin_gcrmsg_clear 0xFBFF // Clear mask +#define rx_slv_unshdw_rpr_done_fin_gcrmsg 0x0200 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done +#define rx_slv_unshdw_rpr_done_fin_gcrmsg_clear 0xFDFF // Clear mask +#define rx_slv_unshdw_rpr_nop_fin_gcrmsg 0x0100 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear 0xFEFF // Clear mask +#define rx_slv_recal_done_nop_fin_gcrmsg 0x0080 //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_done_nop_fin_gcrmsg_clear 0xFF7F // Clear mask +#define rx_slv_recal_fail_nop_fin_gcrmsg 0x0040 //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_fail_nop_fin_gcrmsg_clear 0xFFBF // Clear mask +#define rx_slv_recal_presults_fin_gcrmsg 0x0020 //GCR Message: Slave Recal Pass Results; Need to finish slave recal handshake starting with waiting for results +#define rx_slv_recal_presults_fin_gcrmsg_clear 0xFFDF // Clear mask +#define rx_slv_recal_fresults_fin_gcrmsg 0x0010 //GCR Message: Slave Recal Fail Results; Need to finish slave recal handshake starting with waiting for results +#define rx_slv_recal_fresults_fin_gcrmsg_clear 0xFFEF // Clear mask +#define rx_slv_recal_abort_ack_fin_gcrmsg 0x0008 //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_abort_ack_fin_gcrmsg_clear 0xFFF7 // Clear mask +#define rx_slv_recal_abort_mnop_fin_gcrmsg 0x0004 //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_abort_mnop_fin_gcrmsg_clear 0xFFFB // Clear mask +#define rx_slv_recal_abort_snop_fin_gcrmsg 0x0002 //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop +#define rx_slv_recal_abort_snop_fin_gcrmsg_clear 0xFFFD // Clear mask + // rx_wiretest_pp Register field name data value Description #define rx_wt_pattern_length_256 0x4000 //RX Wiretest Pattern Length 256 #define rx_wt_pattern_length_512 0x8000 //RX Wiretest Pattern Length 512 #define rx_wt_pattern_length_1024 0xC000 //RX Wiretest Pattern Length 1024 #define rx_wt_pattern_length_clear 0x3FFF // Clear mask -// rx_mode_pp Register field name data value Description +// rx_mode1_pp Register field name data value Description #define rx_reduced_scramble_mode_disable_1 0x4000 //Sets reduced density of scramble pattern. Disable reduced density #define rx_reduced_scramble_mode_enable_div2 0x8000 //Sets reduced density of scramble pattern. Enable Div2 Reduced Density #define rx_reduced_scramble_mode_enable_div4 0xC000 //Sets reduced density of scramble pattern. Enable Div4 Reduced Density @@ -2371,9 +2663,13 @@ const char* const ei4_GCR_sub_reg_names[] = { #define rx_dyn_recal_status_rpt_timeout_sel_tap3 0x0C00 //RX Dynamic Recalibration Status Reporting Timeout Selects 4096UI or 426.0ns #define rx_dyn_recal_status_rpt_timeout_sel_clear 0xF3FF // Clear mask -// rx_servo_recal_gcrmsg_pp Register field name data value Description -#define rx_servo_recal_ip_gcrmsg 0x8000 //GCR Message: RX Servo Lane Calibration In Progress -#define rx_servo_recal_ip_gcrmsg_clear 0x7FFF // Clear mask +// rx_mode2_pp Register field name data value Description +#define rx_bist_jitter_pulse_ctl_0 0x4000 //Jitter Select (steps8 +#define rx_bist_jitter_pulse_ctl_1 0x8000 //Jitter Select (steps2 +#define rx_bist_jitter_pulse_ctl_2 0xC000 //Jitter Select (steps0 +#define rx_bist_jitter_pulse_ctl_clear 0x3FFF // Clear mask +#define rx_bist_min_eye_width 0x0000 //Sets the minimum eye width value considered acceptable by PHYBIST. +#define rx_bist_min_eye_width_clear 0xE07F // Clear mask // rx_ber_cntl_pp Register field name data value Description #define rx_ber_en 0x8000 //Per-Pack (PP) Diagnostic Bit Error Rate (BER) error checking enable control. When 1 enables error checking. When 0 the error checking is disabled. This control enables the BER timer as well as enables the error checker and BER counters. The assumption is that the driver(s) are currently driving PRBS23 and the link has been trained before enabling BER checking. @@ -2640,8 +2936,187 @@ const char* const ei4_GCR_sub_reg_names[] = { // rx_reset_cfg_pp Register field name data value Description #define rx_reset_cfg_hld_clear 0x0000 // Clear mask -// tx_mode_pl Register field name data value Description -#define ei4_tx_lane_pdwn 0x8000 //Used to drive inhibit (tristate) and fully power down a lane. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers ei4_tx_lane_disabled_vec_0_15 and ei4_tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines. +// rx_recal_to1_pp Register field name data value Description +#define rx_recal_timeout_sel_A_512ui 0x1000 //RX recal servo operation timeout A. 512 UI +#define rx_recal_timeout_sel_A_1Kui 0x2000 //RX recal servo operation timeout A. 1K UI +#define rx_recal_timeout_sel_A_2Kui 0x3000 //RX recal servo operation timeout A. 2K UI +#define rx_recal_timeout_sel_A_4Kui 0x4000 //RX recal servo operation timeout A. 4096 UI +#define rx_recal_timeout_sel_A_8Kui 0x5000 //RX recal servo operation timeout A. 8K UI +#define rx_recal_timeout_sel_A_16Kui 0x6000 //RX recal servo operation timeout A. 16K UI +#define rx_recal_timeout_sel_A_32Kui 0x7000 //RX recal servo operation timeout A. 32K UI +#define rx_recal_timeout_sel_A_64Kui 0x8000 //RX recal servo operation timeout A. 64K UI +#define rx_recal_timeout_sel_A_128Kui 0x9000 //RX recal servo operation timeout A. 128K UI +#define rx_recal_timeout_sel_A_256Kui 0xA000 //RX recal servo operation timeout A. 256K UI +#define rx_recal_timeout_sel_A_512Kui 0xB000 //RX recal servo operation timeout A. 512K UI +#define rx_recal_timeout_sel_A_1Mui 0xC000 //RX recal servo operation timeout A. 1M UI +#define rx_recal_timeout_sel_A_2Mui 0xD000 //RX recal servo operation timeout A. 2M UI +#define rx_recal_timeout_sel_A_4Mui 0xE000 //RX recal servo operation timeout A. 4M UI +#define rx_recal_timeout_sel_A_Infinite 0xF000 //RX recal servo operation timeout A. Infinite +#define rx_recal_timeout_sel_A_clear 0x0FFF // Clear mask +#define rx_recal_timeout_sel_B_512ui 0x0100 //RX recal servo operation timeout B. 512 UI +#define rx_recal_timeout_sel_B_1Kui 0x0200 //RX recal servo operation timeout B. 1K UI +#define rx_recal_timeout_sel_B_2Kui 0x0300 //RX recal servo operation timeout B. 2K UI +#define rx_recal_timeout_sel_B_4Kui 0x0400 //RX recal servo operation timeout B. 4096 UI +#define rx_recal_timeout_sel_B_8Kui 0x0500 //RX recal servo operation timeout B. 8K UI +#define rx_recal_timeout_sel_B_16Kui 0x0600 //RX recal servo operation timeout B. 16K UI +#define rx_recal_timeout_sel_B_32Kui 0x0700 //RX recal servo operation timeout B. 32K UI +#define rx_recal_timeout_sel_B_64Kui 0x0800 //RX recal servo operation timeout B. 64K UI +#define rx_recal_timeout_sel_B_128Kui 0x0900 //RX recal servo operation timeout B. 128K UI +#define rx_recal_timeout_sel_B_256Kui 0x0A00 //RX recal servo operation timeout B. 256K UI +#define rx_recal_timeout_sel_B_512Kui 0x0B00 //RX recal servo operation timeout B. 512K UI +#define rx_recal_timeout_sel_B_1Mui 0x0C00 //RX recal servo operation timeout B. 1M UI +#define rx_recal_timeout_sel_B_2Mui 0x0D00 //RX recal servo operation timeout B. 2M UI +#define rx_recal_timeout_sel_B_4Mui 0x0E00 //RX recal servo operation timeout B. 4M UI +#define rx_recal_timeout_sel_B_Infinite 0x0F00 //RX recal servo operation timeout B. Infinite +#define rx_recal_timeout_sel_B_clear 0xF0FF // Clear mask + +// rx_recal_to2_pp Register field name data value Description +#define rx_recal_timeout_sel_G_512ui 0x0010 //RX recal servo operation timeout G. 512 UI +#define rx_recal_timeout_sel_G_1Kui 0x0020 //RX recal servo operation timeout G. 1K UI +#define rx_recal_timeout_sel_G_2Kui 0x0030 //RX recal servo operation timeout G. 2K UI +#define rx_recal_timeout_sel_G_4Kui 0x0040 //RX recal servo operation timeout G. 4096 UI +#define rx_recal_timeout_sel_G_8Kui 0x0050 //RX recal servo operation timeout G. 8K UI +#define rx_recal_timeout_sel_G_16Kui 0x0060 //RX recal servo operation timeout G. 16K UI +#define rx_recal_timeout_sel_G_32Kui 0x0070 //RX recal servo operation timeout G. 32K UI +#define rx_recal_timeout_sel_G_64Kui 0x0080 //RX recal servo operation timeout G. 64K UI +#define rx_recal_timeout_sel_G_128Kui 0x0090 //RX recal servo operation timeout G. 128K UI +#define rx_recal_timeout_sel_G_256Kui 0x00A0 //RX recal servo operation timeout G. 256K UI +#define rx_recal_timeout_sel_G_512Kui 0x00B0 //RX recal servo operation timeout G. 512K UI +#define rx_recal_timeout_sel_G_1Mui 0x00C0 //RX recal servo operation timeout G. 1M UI +#define rx_recal_timeout_sel_G_2Mui 0x00D0 //RX recal servo operation timeout G. 2M UI +#define rx_recal_timeout_sel_G_4Mui 0x00E0 //RX recal servo operation timeout G. 4M UI +#define rx_recal_timeout_sel_G_Infinite 0x00F0 //RX recal servo operation timeout G. Infinite +#define rx_recal_timeout_sel_G_clear 0x0F0F // Clear mask +#define rx_recal_timeout_sel_H_512ui 0x0001 //RX recal servo operation timeout H. 512 UI +#define rx_recal_timeout_sel_H_1Kui 0x0002 //RX recal servo operation timeout H. 1K UI +#define rx_recal_timeout_sel_H_2Kui 0x0003 //RX recal servo operation timeout H. 2K UI +#define rx_recal_timeout_sel_H_4Kui 0x0004 //RX recal servo operation timeout H. 4096 UI +#define rx_recal_timeout_sel_H_8Kui 0x0005 //RX recal servo operation timeout H. 8K UI +#define rx_recal_timeout_sel_H_16Kui 0x0006 //RX recal servo operation timeout H. 16K UI +#define rx_recal_timeout_sel_H_32Kui 0x0007 //RX recal servo operation timeout H. 32K UI +#define rx_recal_timeout_sel_H_64Kui 0x0008 //RX recal servo operation timeout H. 64K UI +#define rx_recal_timeout_sel_H_128Kui 0x0009 //RX recal servo operation timeout H. 128K UI +#define rx_recal_timeout_sel_H_256Kui 0x000A //RX recal servo operation timeout H. 256K UI +#define rx_recal_timeout_sel_H_512Kui 0x000B //RX recal servo operation timeout H. 512K UI +#define rx_recal_timeout_sel_H_1Mui 0x000C //RX recal servo operation timeout H. 1M UI +#define rx_recal_timeout_sel_H_2Mui 0x000D //RX recal servo operation timeout H. 2M UI +#define rx_recal_timeout_sel_H_4Mui 0x000E //RX recal servo operation timeout H. 4M UI +#define rx_recal_timeout_sel_H_Infinite 0x000F //RX recal servo operation timeout H. Infinite +#define rx_recal_timeout_sel_H_clear 0xFF00 // Clear mask + +// rx_recal_to3_pp Register field name data value Description +#define rx_recal_timeout_sel_I_512ui 0x1000 //RX recal servo operation timeout I. 512 UI +#define rx_recal_timeout_sel_I_1Kui 0x2000 //RX recal servo operation timeout I. 1K UI +#define rx_recal_timeout_sel_I_2Kui 0x3000 //RX recal servo operation timeout I. 2K UI +#define rx_recal_timeout_sel_I_4Kui 0x4000 //RX recal servo operation timeout I. 4096 UI +#define rx_recal_timeout_sel_I_8Kui 0x5000 //RX recal servo operation timeout I. 8K UI +#define rx_recal_timeout_sel_I_16Kui 0x6000 //RX recal servo operation timeout I. 16K UI +#define rx_recal_timeout_sel_I_32Kui 0x7000 //RX recal servo operation timeout I. 32K UI +#define rx_recal_timeout_sel_I_64Kui 0x8000 //RX recal servo operation timeout I. 64K UI +#define rx_recal_timeout_sel_I_128Kui 0x9000 //RX recal servo operation timeout I. 128K UI +#define rx_recal_timeout_sel_I_256Kui 0xA000 //RX recal servo operation timeout I. 256K UI +#define rx_recal_timeout_sel_I_512Kui 0xB000 //RX recal servo operation timeout I. 512K UI +#define rx_recal_timeout_sel_I_1Mui 0xC000 //RX recal servo operation timeout I. 1M UI +#define rx_recal_timeout_sel_I_2Mui 0xD000 //RX recal servo operation timeout I. 2M UI +#define rx_recal_timeout_sel_I_4Mui 0xE000 //RX recal servo operation timeout I. 4M UI +#define rx_recal_timeout_sel_I_Infinite 0xF000 //RX recal servo operation timeout I. Infinite +#define rx_recal_timeout_sel_I_clear 0x0FFF // Clear mask +#define rx_recal_timeout_sel_J_512ui 0x0100 //RX recal servo operation timeout J. 512 UI +#define rx_recal_timeout_sel_J_1Kui 0x0200 //RX recal servo operation timeout J. 1K UI +#define rx_recal_timeout_sel_J_2Kui 0x0300 //RX recal servo operation timeout J. 2K UI +#define rx_recal_timeout_sel_J_4Kui 0x0400 //RX recal servo operation timeout J. 4096 UI +#define rx_recal_timeout_sel_J_8Kui 0x0500 //RX recal servo operation timeout J. 8K UI +#define rx_recal_timeout_sel_J_16Kui 0x0600 //RX recal servo operation timeout J. 16K UI +#define rx_recal_timeout_sel_J_32Kui 0x0700 //RX recal servo operation timeout J. 32K UI +#define rx_recal_timeout_sel_J_64Kui 0x0800 //RX recal servo operation timeout J. 64K UI +#define rx_recal_timeout_sel_J_128Kui 0x0900 //RX recal servo operation timeout J. 128K UI +#define rx_recal_timeout_sel_J_256Kui 0x0A00 //RX recal servo operation timeout J. 256K UI +#define rx_recal_timeout_sel_J_512Kui 0x0B00 //RX recal servo operation timeout J. 512K UI +#define rx_recal_timeout_sel_J_1Mui 0x0C00 //RX recal servo operation timeout J. 1M UI +#define rx_recal_timeout_sel_J_2Mui 0x0D00 //RX recal servo operation timeout J. 2M UI +#define rx_recal_timeout_sel_J_4Mui 0x0E00 //RX recal servo operation timeout J. 4M UI +#define rx_recal_timeout_sel_J_Infinite 0x0F00 //RX recal servo operation timeout J. Infinite +#define rx_recal_timeout_sel_J_clear 0xF0FF // Clear mask +#define rx_recal_timeout_sel_K_512ui 0x0010 //RX recal servo operation timeout K. 512 UI +#define rx_recal_timeout_sel_K_1Kui 0x0020 //RX recal servo operation timeout K. 1K UI +#define rx_recal_timeout_sel_K_2Kui 0x0030 //RX recal servo operation timeout K. 2K UI +#define rx_recal_timeout_sel_K_4Kui 0x0040 //RX recal servo operation timeout K. 4096 UI +#define rx_recal_timeout_sel_K_8Kui 0x0050 //RX recal servo operation timeout K. 8K UI +#define rx_recal_timeout_sel_K_16Kui 0x0060 //RX recal servo operation timeout K. 16K UI +#define rx_recal_timeout_sel_K_32Kui 0x0070 //RX recal servo operation timeout K. 32K UI +#define rx_recal_timeout_sel_K_64Kui 0x0080 //RX recal servo operation timeout K. 64K UI +#define rx_recal_timeout_sel_K_128Kui 0x0090 //RX recal servo operation timeout K. 128K UI +#define rx_recal_timeout_sel_K_256Kui 0x00A0 //RX recal servo operation timeout K. 256K UI +#define rx_recal_timeout_sel_K_512Kui 0x00B0 //RX recal servo operation timeout K. 512K UI +#define rx_recal_timeout_sel_K_1Mui 0x00C0 //RX recal servo operation timeout K. 1M UI +#define rx_recal_timeout_sel_K_2Mui 0x00D0 //RX recal servo operation timeout K. 2M UI +#define rx_recal_timeout_sel_K_4Mui 0x00E0 //RX recal servo operation timeout K. 4M UI +#define rx_recal_timeout_sel_K_Infinite 0x00F0 //RX recal servo operation timeout K. Infinite +#define rx_recal_timeout_sel_K_clear 0x0F0F // Clear mask +#define rx_recal_timeout_sel_L_512ui 0x0001 //RX recal servo operation timeout L. 512 UI +#define rx_recal_timeout_sel_L_1Kui 0x0002 //RX recal servo operation timeout L. 1K UI +#define rx_recal_timeout_sel_L_2Kui 0x0003 //RX recal servo operation timeout L. 2K UI +#define rx_recal_timeout_sel_L_4Kui 0x0004 //RX recal servo operation timeout L. 4096 UI +#define rx_recal_timeout_sel_L_8Kui 0x0005 //RX recal servo operation timeout L. 8K UI +#define rx_recal_timeout_sel_L_16Kui 0x0006 //RX recal servo operation timeout L. 16K UI +#define rx_recal_timeout_sel_L_32Kui 0x0007 //RX recal servo operation timeout L. 32K UI +#define rx_recal_timeout_sel_L_64Kui 0x0008 //RX recal servo operation timeout L. 64K UI +#define rx_recal_timeout_sel_L_128Kui 0x0009 //RX recal servo operation timeout L. 128K UI +#define rx_recal_timeout_sel_L_256Kui 0x000A //RX recal servo operation timeout L. 256K UI +#define rx_recal_timeout_sel_L_512Kui 0x000B //RX recal servo operation timeout L. 512K UI +#define rx_recal_timeout_sel_L_1Mui 0x000C //RX recal servo operation timeout L. 1M UI +#define rx_recal_timeout_sel_L_2Mui 0x000D //RX recal servo operation timeout L. 2M UI +#define rx_recal_timeout_sel_L_4Mui 0x000E //RX recal servo operation timeout L. 4M UI +#define rx_recal_timeout_sel_L_Infinite 0x000F //RX recal servo operation timeout L. Infinite +#define rx_recal_timeout_sel_L_clear 0xFF00 // Clear mask + +// rx_recal_cntl_pp Register field name data value Description +#define rx_recal_in_progress 0x8000 //Selects which servo timeouts are used. +#define rx_recal_in_progress_clear 0x7FFF // Clear mask + +// rx_trace_pp Register field name data value Description +#define rx_pp_trc_mode_tap1 0x2000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_tap2 0x4000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_tap3 0x6000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_tap4 0x8000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_tap5 0xA000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_tap6 0xC000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_tap7 0xE000 //Per Pack RX Trace Mode TBD +#define rx_pp_trc_mode_clear 0x1FFF // Clear mask + +// rx_bist_gcrmsg_pp Register field name data value Description +#define rx_bist_en 0x8000 //TBD +#define rx_bist_en_clear 0x7FFF // Clear mask + +// rx_scope_cntl_pp Register field name data value Description +#define rx_scope_control 0x0000 //Bit 0 odd/even (1 is odd) Bit 1 speculation latch 0=0 1=1. +#define rx_scope_control_clear 0x3FFF // Clear mask +#define rx_bump_scope 0x2000 //This is a write only pulse which must stay on for 1 slow cycle. When pulsed it will bump the scope sync counter one notch. +#define rx_bump_scope_clear 0xDFFF // Clear mask + +// rx_fir_reset_pb Register field name data value Description +#define rx_pb_clr_par_errs 0x0002 //Clear All RX Parity Error Latches +#define rx_pb_clr_par_errs_clear 0xFFFD // Clear mask +#define rx_pb_fir_reset 0x0001 //FIR Reset +#define rx_pb_fir_reset_clear 0xFFFE // Clear mask + +// rx_fir_pb Register field name data value Description +#define rx_pb_fir_errs_err_busctl_gcrs_ld_sm 0x0400 //A Per-Bus BUSCTL Register or State Machine Parity Error has occurred. BUSCTL GCR Load SM Parity Error. +#define rx_pb_fir_errs_clear 0x003F // Clear mask + +// rx_fir_mask_pb Register field name data value Description +#define rx_pb_fir_errs_mask_err_busctl_gcrs_ld_sm 0x0400 //FIR mask for register or state machine parity checkers in per-bus BUSCTL logic. A value of 1 masks the error from generating a FIR error. BUSCTL GCR Load SM Parity Error. +#define rx_pb_fir_errs_mask_clear 0x003F // Clear mask + +// rx_fir_error_inject_pb Register field name data value Description +#define rx_pb_fir_errs_inj_1 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define rx_pb_fir_errs_inj_err_inj_busctl_gcrs_ld_sm 0x0400 //RX Per-Group Parity Error Injection BUSCTL GCR Load SM Parity Error Inject. +#define rx_pb_fir_errs_inj_clear 0x003F // Clear mask + + + +// ei4_tx_mode_pl Register field name data value Description +#define ei4_tx_lane_pdwn 0x8000 //Used to drive inhibit (tristate) and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (ei4_tx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers ei4_tx_lane_disabled_vec_0_15 and ei4_tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. #define ei4_tx_lane_pdwn_clear 0x7FFF // Clear mask #define ei4_tx_lane_invert 0x4000 //Used to invert the polarity of a lane. #define ei4_tx_lane_invert_clear 0xBFFF // Clear mask @@ -2651,22 +3126,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_lane_quiesce_clear 0xCFFF // Clear mask #define ei4_tx_lane_scramble_disable 0x0200 //Used to disable the TX scrambler on a specific lane or all lanes by using a per-lane/per-group global write. #define ei4_tx_lane_scramble_disable_clear 0xFDFF // Clear mask -#define ei4_tx_lane_error_inject_mode_single_err_inj 0x0001 //Used to set the error injection rate to a particular value. Single Error Injection -#define ei4_tx_lane_error_inject_mode_0 0x0002 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_1 0x0003 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_2 0x0010 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_3 0x0011 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_4 0x0012 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_5 0x0013 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_6 0x0020 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_7 0x0021 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_8 0x0022 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_9 0x0023 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_10 0x0030 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_11 0x0031 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_12 0x0032 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_13 0x0033 //Used to set the error injection rate to a particular value. TBD -#define ei4_tx_lane_error_inject_mode_clear 0xF300 // Clear mask // ei4_tx_cntl_stat_pl Register field name data value Description #define ei4_tx_fifo_err 0x8000 //Indicates an error condition in the TX FIFO. @@ -2701,7 +3160,7 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_prbs_tap_id_pattern_c 0x4000 //TX Per-Lane PRBS Tap Selector PRBS tap point C #define ei4_tx_prbs_tap_id_pattern_d 0x6000 //TX Per-Lane PRBS Tap Selector PRBS tap point D #define ei4_tx_prbs_tap_id_pattern_e 0x8000 //TX Per-Lane PRBS Tap Selector PRBS tap point E -#define ei4_tx_prbs_tap_id_pattern_F 0xA000 //TX Per-Lane PRBS Tap Selector PRBS tap point F +#define ei4_tx_prbs_tap_id_pattern_f 0xA000 //TX Per-Lane PRBS Tap Selector PRBS tap point F #define ei4_tx_prbs_tap_id_pattern_g 0xC000 //TX Per-Lane PRBS Tap Selector PRBS tap point G #define ei4_tx_prbs_tap_id_pattern_h 0xE000 //TX Per-Lane PRBS Tap Selector PRBS tap point H #define ei4_tx_prbs_tap_id_clear 0x1FFF // Clear mask @@ -2716,12 +3175,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_drv_data_pattern_gcrmsg_drv_9th_prbs23 0x7000 //GCR Message: TX Per Data Lane Drive Patterns PRBS-23 9th pattern #define ei4_tx_drv_data_pattern_gcrmsg_drv_ei3_iap 0x8000 //GCR Message: TX Per Data Lane Drive Patterns EI-3 Busy IAP Pattern (EI4 only #define ei4_tx_drv_data_pattern_gcrmsg_drv_ei3_prbs12 0x9000 //GCR Message: TX Per Data Lane Drive Patterns Drive EI-3 PRBS-12 Shifted RDT Pattern (EI4 only -#define ei4_tx_drv_data_pattern_gcrmsg_unused_A 0xA000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define ei4_tx_drv_data_pattern_gcrmsg_unused_B 0xB000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define ei4_tx_drv_data_pattern_gcrmsg_unused_C 0xC000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define ei4_tx_drv_data_pattern_gcrmsg_unused_D 0xD000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define ei4_tx_drv_data_pattern_gcrmsg_unused_E 0xE000 //GCR Message: TX Per Data Lane Drive Patterns Unused -#define ei4_tx_drv_data_pattern_gcrmsg_unused_F 0xF000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define ei4_tx_drv_data_pattern_gcrmsg_TDR_square_wave 0xA000 //GCR Message: TX Per Data Lane Drive Patterns Drives TDR Pulse-Square waves +#define ei4_tx_drv_data_pattern_gcrmsg_k28_5 0xB000 //GCR Message: TX Per Data Lane Drive Patterns Drives 20-bit K28.5 pattern - padded to 32 bits +#define ei4_tx_drv_data_pattern_gcrmsg_unused_A 0xC000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define ei4_tx_drv_data_pattern_gcrmsg_unused_B 0xD000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define ei4_tx_drv_data_pattern_gcrmsg_unused_C 0xE000 //GCR Message: TX Per Data Lane Drive Patterns Unused +#define ei4_tx_drv_data_pattern_gcrmsg_unused_D 0xF000 //GCR Message: TX Per Data Lane Drive Patterns Unused #define ei4_tx_drv_data_pattern_gcrmsg_clear 0x0FFF // Clear mask #define ei4_tx_drv_func_data_gcrmsg 0x0800 //GCR Message: Functional Data #define ei4_tx_drv_func_data_gcrmsg_clear 0xF7FF // Clear mask @@ -2729,8 +3188,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_sls_lane_sel_gcrmsg_clear 0xFBFF // Clear mask // ei4_tx_sync_pattern_gcrmsg_pl Register field name data value Description -#define ei4_tx_sync_pattern_gcrmsg_pl_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED -#define ei4_tx_sync_pattern_gcrmsg_pl_spare_clear 0x7FFF // Clear mask #define ei4_tx_drv_sync_patt_gcrmsg 0x4000 //Sync Pattern #define ei4_tx_drv_sync_patt_gcrmsg_clear 0xBFFF // Clear mask @@ -2747,14 +3204,11 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_pl_fir_err_inj_clear 0x7FFF // Clear mask // ei4_tx_mode_fast_pl Register field name data value Description -#define ei4_tx_err_inject_lane0 0x8000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 0. -#define ei4_tx_err_inject_lane1 0x4000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 1. -#define ei4_tx_err_inject_lane2 0x2000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) inject error on lane 2. -#define ei4_tx_err_inject_lane3 0x1000 //One Hot - Software Only controled register to inject a error for one pulse on a specified lane.(default) Inject error on lane 3. +#define ei4_tx_err_inject 0x0000 //Software-only controlled register to inject one or more errors for one deserialized clock pulse on one or more specified beats on this lane. Set bit position X to inject on beat X of a cycle. Bits 0:3 are used in EDI and 0:1 are used in EI4. #define ei4_tx_err_inject_clear 0x0FFF // Clear mask -#define ei4_tx_err_inj_A_enable 0x0800 //Control to enable the random bit error injection A.(default) +#define ei4_tx_err_inj_A_enable 0x0800 //Control to enable the random bit error injection pattern A for this lane.(default) #define ei4_tx_err_inj_A_enable_clear 0xF7FF // Clear mask -#define ei4_tx_err_inj_B_enable 0x0400 //Control to enable the random bit error injection B.(default) +#define ei4_tx_err_inj_B_enable 0x0400 //Control to enable the random bit error injection pattern B for this lane.(default) #define ei4_tx_err_inj_B_enable_clear 0xFBFF // Clear mask // ei4_tx_clk_mode_pg Register field name data value Description @@ -2790,13 +3244,11 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_pg_spare_mode_7_clear 0xFEFF // Clear mask // ei4_tx_cntl_stat_pg Register field name data value Description -#define ei4_tx_cntl_stat_pg_spare 0x8000 //REMOVE ME ONCE CREATEREGS WO/RO ADDRESS DECLARATION BUG IS FIXED -#define ei4_tx_cntl_stat_pg_spare_clear 0x7FFF // Clear mask #define ei4_tx_fifo_init 0x4000 //Used to initialize the TX FIFO and put it into a known reset state. This will cause the load to unload delay of the FIFO to be set to the value in the ei4_tx_FIFO_L2U_DLY field of the ei4_tx_FIFO_Mode register. #define ei4_tx_fifo_init_clear 0xBFFF // Clear mask // ei4_tx_mode_pg Register field name data value Description -#define ei4_tx_max_bad_lanes 0x0000 //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus +#define ei4_tx_max_bad_lanes 0x0000 //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus (NOTE: should match RX side) #define ei4_tx_max_bad_lanes_clear 0x07FF // Clear mask #define ei4_tx_msbswap 0x0400 //Used to enable end-for-end or msb swap of TX lanes. For example, lanes 0 and N-1 swap, lanes 1 and N-2 swap, etc. #define ei4_tx_msbswap_clear 0xFBFF // Clear mask @@ -2826,10 +3278,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_fir_reset_clear 0xFFFE // Clear mask // ei4_tx_bist_stat_pg Register field name data value Description -#define ei4_tx_clk_bist_err 0x8000 //Indicates a TXBIST error occurred. -#define ei4_tx_clk_bist_err_clear 0x7FFF // Clear mask -#define ei4_tx_clk_bist_done 0x4000 //Indicates TXBIST has completed. -#define ei4_tx_clk_bist_done_clear 0xBFFF // Clear mask +#define ei4_tx_clk_bist_err 0x0000 //TBD +#define ei4_tx_clk_bist_err_clear 0x3FFF // Clear mask +#define ei4_tx_clk_bist_done 0x0000 //TBD +#define ei4_tx_clk_bist_done_clear 0xCFFF // Clear mask // ei4_tx_fir_pg Register field name data value Description #define ei4_tx_pg_fir_errs_clear 0x00FF // Clear mask @@ -2861,10 +3313,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_end_lane_id 0x0000 //This field is used to programmably set the last lane position in the group but relative to the bus. #define ei4_tx_end_lane_id_clear 0x7F80 // Clear mask -// ei4_tx_minikerf_pg Register field name data value Description -#define ei4_tx_minikerf 0x0000 //Used to configure the TX Minikerf for analog characterization. -#define ei4_tx_minikerf_clear 0x0000 // Clear mask - // ei4_tx_clk_cntl_gcrmsg_pg Register field name data value Description #define ei4_tx_drv_clk_pattern_gcrmsg_drv_wt 0x4000 //TX Clock Drive Patterns Drive Wiretest Pattern #define ei4_tx_drv_clk_pattern_gcrmsg_drv_c4 0x8000 //TX Clock Drive Patterns Drive Clock Pattern @@ -2887,6 +3335,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_sls_lane_val_gcrmsg 0x0100 //GCR Message: TX SLS Lane Valid #define ei4_tx_sls_lane_val_gcrmsg_clear 0xFEFF // Clear mask +// ei4_tx_wt_seg_enable_pg Register field name data value Description +#define ei4_tx_wt_en_all_clk_segs_gcrmsg 0x8000 //TX Clock Wiretest driver segnments enable +#define ei4_tx_wt_en_all_clk_segs_gcrmsg_clear 0x7FFF // Clear mask +#define ei4_tx_wt_en_all_data_segs_gcrmsg 0x4000 //TX Data Wiretest driver segnments enable +#define ei4_tx_wt_en_all_data_segs_gcrmsg_clear 0xBFFF // Clear mask + // ei4_tx_pc_ffe_pg Register field name data value Description #define ei4_tx_pc_test_mode 0x8000 //Driver Segment Test mode #define ei4_tx_pc_test_mode_clear 0x7FFF // Clear mask @@ -2896,12 +3350,18 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_pc_slice_en_enc_clear 0x0FF0 // Clear mask // ei4_tx_misc_analog_pg Register field name data value Description -#define ei4_tx_slewctl 0x0000 //TBD +#define ei4_tx_slewctl_slew110ps 0x4000 //Driver Slew Control (bits 2:3 are reserved) 110ps nominal rate +#define ei4_tx_slewctl_slew140ps 0x8000 //Driver Slew Control (bits 2:3 are reserved) 140ps nominal rate +#define ei4_tx_slewctl_slew170ps 0xC000 //Driver Slew Control (bits 2:3 are reserved) 170ps nominal rate #define ei4_tx_slewctl_clear 0x0FFF // Clear mask -#define ei4_tx_pvtnl_enc 0x0000 //TBD -#define ei4_tx_pvtnl_enc_clear 0xFF0F // Clear mask -#define ei4_tx_pvtpl_enc 0x0000 //TBD -#define ei4_tx_pvtpl_enc_clear 0xF0F0 // Clear mask +#define ei4_tx_pvtnl_enc_2400ohms 0x0010 //PVT pfet enables for all driver slices min pvt pfet enabled in parallel +#define ei4_tx_pvtnl_enc_1200ohms 0x0020 //PVT pfet enables for all driver slices max pvt pfet enabled in parallel +#define ei4_tx_pvtnl_enc_800ohms 0x0030 //PVT pfet enables for all driver slices both pvt pfets enabled in parallel +#define ei4_tx_pvtnl_enc_clear 0xF3CF // Clear mask +#define ei4_tx_pvtpl_enc_2400ohms 0x0001 //PVT nfet enables for all driver slices Min pvt nfet enabled in parallel +#define ei4_tx_pvtpl_enc_1200ohms 0x0002 //PVT nfet enables for all driver slices Max pvt nfet enabled in parallel +#define ei4_tx_pvtpl_enc_800ohms 0x0003 //PVT nfet enables for all driver slices Both pvt nfets enabled in parallel +#define ei4_tx_pvtpl_enc_clear 0xFFF0 // Clear mask // ei4_tx_lane_disabled_vec_0_15_pg Register field name data value Description #define ei4_tx_lane_disabled_vec_0_15 0x0000 //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control). @@ -2927,10 +3387,97 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_slv_mv_sls_unshdw_req_gcrmsg_clear 0xDFFF // Clear mask #define ei4_tx_slv_mv_sls_unshdw_rpr_req_gcrmsg 0x1000 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register #define ei4_tx_slv_mv_sls_unshdw_rpr_req_gcrmsg_clear 0xEFFF // Clear mask -#define ei4_tx_bus_width 0x0000 //TX Bus Width +#define ei4_tx_bus_width 0x0000 //GCR Message: TX Bus Width #define ei4_tx_bus_width_clear 0xF01F // Clear mask #define ei4_tx_slv_mv_sls_rpr_req_gcrmsg 0x0010 //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register #define ei4_tx_slv_mv_sls_rpr_req_gcrmsg_clear 0xFFEF // Clear mask +#define ei4_tx_sls_lane_sel_lg_gcrmsg 0x0008 //GCR Message: Sets the ei4_tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios +#define ei4_tx_sls_lane_sel_lg_gcrmsg_clear 0xFFF7 // Clear mask +#define ei4_tx_sls_lane_unsel_lg_gcrmsg 0x0004 //GCR Message: Clears the ei4_tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios +#define ei4_tx_sls_lane_unsel_lg_gcrmsg_clear 0xFFFB // Clear mask + +// ei4_tx_rdt_cntl_pg Register field name data value Description +#define ei4_tx_rdt_mode 0x8000 //Sets RDT mode +#define ei4_tx_rdt_mode_clear 0x7FFF // Clear mask +#define ei4_tx_run_rdt 0x4000 //Drives RDT pattern +#define ei4_tx_run_rdt_clear 0xBFFF // Clear mask + +// ei4_rx_dll_cal_cntl_pg Register field name data value Description +#define ei4_rx_dll1_cal_good 0x8000 //RX DLL 1 Calibration has completed successfully and clock is properly aligned. This remains static (not dynamically updated) unless the initialization process requests either a new calibration or a fine update. +#define ei4_rx_dll1_cal_good_clear 0x7FFF // Clear mask +#define ei4_rx_dll1_cal_error 0x4000 //RX DLL 1 Calibration has failed to pass coarse delay or coarse vreg calibration and clock is not aligned. +#define ei4_rx_dll1_cal_error_clear 0xBFFF // Clear mask +#define ei4_rx_dll1_cal_error_fine 0x2000 //RX DLL 1 Calibration has failed to pass fine vreg calibration on either reset or on update and clock is not aligned. +#define ei4_rx_dll1_cal_error_fine_clear 0xDFFF // Clear mask +#define ei4_rx_dll1_cal_skip_skip_delay 0x0800 //RX DLL 1 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped. Skip coarse delay cal only +#define ei4_rx_dll1_cal_skip_skip_vreg 0x1000 //RX DLL 1 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped. Skip coarse vreg cal only +#define ei4_rx_dll1_cal_skip_skip_both 0x1800 //RX DLL 1 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped. Skip both coarse vreg and coarse delay cal +#define ei4_rx_dll1_cal_skip_clear 0xE7FF // Clear mask +#define ei4_rx_dll1_coarse_adj_by2 0x0400 //RX DLL 1 Calibration Coarse Delay Backoff TweakWhen coarse delay is calibrated normally 1 delay step is removed to assist finding the edge for fine delay. This allows for 2 steps adjustment. +#define ei4_rx_dll1_coarse_adj_by2_clear 0xFBFF // Clear mask +#define ei4_rx_dll2_cal_good 0x0080 //RX DLL 2 Calibration has completed successfully and clock is properly aligned. This remains static (not dynamically updated) unless the initialization process requests either a new calibration or a fine update. +#define ei4_rx_dll2_cal_good_clear 0xFF7F // Clear mask +#define ei4_rx_dll2_cal_error 0x0040 //RX DLL 2 Calibration has failed to pass coarse delay or coarse vreg calibration and clock is not aligned. +#define ei4_rx_dll2_cal_error_clear 0xFFBF // Clear mask +#define ei4_rx_dll2_cal_error_fine 0x0020 //RX DLL 2 Calibration has failed to pass fine vreg calibration on either reset or on update and clock is not aligned. +#define ei4_rx_dll2_cal_error_fine_clear 0xFFDF // Clear mask +#define ei4_rx_dll2_cal_skip_skip_delay 0x0008 //RX DLL 2 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped. Skip coarse delay cal only +#define ei4_rx_dll2_cal_skip_skip_vreg 0x0010 //RX DLL 2 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped. Skip coarse vreg cal only +#define ei4_rx_dll2_cal_skip_skip_both 0x0018 //RX DLL 2 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped. Skip both coarse vreg and coarse delay cal +#define ei4_rx_dll2_cal_skip_clear 0xFCE7 // Clear mask +#define ei4_rx_dll2_coarse_adj_by2 0x0004 //RX DLL 2 Calibration Coarse Delay Backoff TweakWhen coarse delay is calibrated normally 1 delay step is removed to assist finding the edge for fine delay. This allows for 2 steps adjustment. +#define ei4_rx_dll2_coarse_adj_by2_clear 0xFFFB // Clear mask + +// ei4_rx_dll1_setpoint1_pg Register field name data value Description +#define ei4_rx_dll1_coarse_en 0x0000 //RX DLL 1 Calibration Result/Setting for Coarse Delay Adjust +#define ei4_rx_dll1_coarse_en_clear 0x03FF // Clear mask +#define ei4_rx_dll1_vreg_dac_coarse 0x0000 //RX DLL 1 Calibration Result/Setting for Coarse VREG DAC +#define ei4_rx_dll1_vreg_dac_coarse_clear 0xFE03 // Clear mask + +// ei4_rx_dll1_setpoint2_pg Register field name data value Description +#define ei4_rx_dll1_vreg_dac_lower 0x0000 //RX DLL 1 Calibration Result/Setting for Fine VREG DAC Lower +#define ei4_rx_dll1_vreg_dac_lower_clear 0x0001 // Clear mask + +// ei4_rx_dll1_setpoint3_pg Register field name data value Description +#define ei4_rx_dll1_vreg_dac_upper 0x0000 //RX DLL 1 Calibration Result/Setting for Fine VREG DAC Upper +#define ei4_rx_dll1_vreg_dac_upper_clear 0x0001 // Clear mask + +// ei4_rx_dll2_setpoint1_pg Register field name data value Description +#define ei4_rx_dll2_coarse_en 0x0000 //RX DLL 2 Calibration Result/Setting for Coarse Delay Adjust +#define ei4_rx_dll2_coarse_en_clear 0x03FF // Clear mask +#define ei4_rx_dll2_vreg_dac_coarse 0x0000 //RX DLL 2 Calibration Result/Setting for Coarse VREG DAC +#define ei4_rx_dll2_vreg_dac_coarse_clear 0xFE03 // Clear mask + +// ei4_rx_dll2_setpoint2_pg Register field name data value Description +#define ei4_rx_dll2_vreg_dac_lower 0x0000 //RX DLL 2 Calibration Result/Setting for Fine VREG DAC Lower +#define ei4_rx_dll2_vreg_dac_lower_clear 0x0001 // Clear mask + +// ei4_rx_dll2_setpoint3_pg Register field name data value Description +#define ei4_rx_dll2_vreg_dac_upper 0x0000 //RX DLL 2 Calibration Result/Setting for Fine VREG DAC Upper +#define ei4_rx_dll2_vreg_dac_upper_clear 0x0001 // Clear mask + +// ei4_rx_dll_filter_mode_pg Register field name data value Description +#define ei4_rx_dll_dll_filter_length_two 0x2000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 2 samples +#define ei4_rx_dll_dll_filter_length_four 0x4000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 4 samples +#define ei4_rx_dll_dll_filter_length_eight 0x6000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 8 samples +#define ei4_rx_dll_dll_filter_length_sixteen 0x8000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 16 samples +#define ei4_rx_dll_dll_filter_length_thirtytwo 0xA000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 32 samples +#define ei4_rx_dll_dll_filter_length_sixtyfour 0xC000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 64 samples +#define ei4_rx_dll_dll_filter_length_one28 0xE000 //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time. 128 samples +#define ei4_rx_dll_dll_filter_length_clear 0x1FFF // Clear mask +#define ei4_rx_dll_dll_lead_lag_separation 0x0000 //\bRX DLL Phase Detector Hysteresis Select\b. The DLL phase detector filters the clock Lead/Lag indicator. This specifies hysteresis separation between a valid lead and valid lag filter sample count in total number of samples. Do not set this higher than the ei4_rx_dll_dll_filter_length +#define ei4_rx_dll_dll_lead_lag_separation_clear 0xF1FF // Clear mask + +// ei4_rx_dll_analog_tweaks_pg Register field name data value Description +#define ei4_rx_dll_vreg_con 0x8000 //RX DLL Vreg KPrime Voltage Level Adjust. +#define ei4_rx_dll_vreg_con_clear 0x7FFF // Clear mask +#define ei4_rx_dll_vreg_compcon_clear 0x8FFF // Clear mask +#define ei4_rx_dll_vreg_ref_sel 0x0000 //RX DLL Vreg Active Voltage Range Adjust. This is primarily for experimentation.000 is default. Others TBD. +#define ei4_rx_dll_vreg_ref_sel_clear 0xF1FF // Clear mask +#define ei4_rx_dll1_vreg_drvcon_clear 0xFE3F // Clear mask +#define ei4_rx_dll2_vreg_drvcon_clear 0x8FC7 // Clear mask +#define ei4_rx_dll_vreg_dac_pullup 0x0004 //RX DLL Vreg DAC Pullup Chickenswitchadjust dac range for bad hardware. +#define ei4_rx_dll_vreg_dac_pullup_clear 0xFFFB // Clear mask // ei4_tx_wiretest_pp Register field name data value Description #define ei4_tx_wt_pattern_length_256 0x4000 //TX Wiretest Pattern Length 256 @@ -2953,65 +3500,87 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_tx_dyn_recal_tsr_ignore_gcrmsg_clear 0xBFFF // Clear mask #define ei4_tx_sls_cmd_gcrmsg 0x0000 //GCR Message: TX SLS Command #define ei4_tx_sls_cmd_gcrmsg_clear 0xC0FF // Clear mask +#define ei4_tx_snd_sls_cmd_prev_gcrmsg 0x0080 //GCR Message: Revert to sending previous SLS Command or Recalibration Data after recovery repair made +#define ei4_tx_snd_sls_cmd_prev_gcrmsg_clear 0xFF7F // Clear mask +#define ei4_tx_snd_sls_using_reg_scramble 0x0040 //GCR Message: Send SLS command using normal scramble pattern instead of 9th pattern +#define ei4_tx_snd_sls_using_reg_scramble_clear 0xFFBF // Clear mask // ei4_tx_ber_cntl_a_pp Register field name data value Description -#define ei4_tx_err_inj_a_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data. +#define ei4_tx_err_inj_a_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data for pattern A. #define ei4_tx_err_inj_a_rand_beat_dis_clear 0x7FFF // Clear mask -#define ei4_tx_err_inj_a_fine_sel_0_15 0x1000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-15 -#define ei4_tx_err_inj_a_fine_sel_0_7 0x2000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-7 -#define ei4_tx_err_inj_a_fine_sel_0_3 0x3000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-3 -#define ei4_tx_err_inj_a_fine_sel_0_1 0x4000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-1 -#define ei4_tx_err_inj_a_fine_sel_fixed1 0x5000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 1 -#define ei4_tx_err_inj_a_fine_sel_fixed3 0x6000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 3 -#define ei4_tx_err_inj_a_fine_sel_fixed7 0x7000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 7. +#define ei4_tx_err_inj_a_fine_sel_1_16 0x1000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-16 cycles +#define ei4_tx_err_inj_a_fine_sel_1_8 0x2000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-8 cycles +#define ei4_tx_err_inj_a_fine_sel_1_4 0x3000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-4 cycles +#define ei4_tx_err_inj_a_fine_sel_1_2 0x4000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-2 cycles +#define ei4_tx_err_inj_a_fine_sel_fixed1 0x5000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 1 cycle +#define ei4_tx_err_inj_a_fine_sel_fixed3 0x6000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 3 cycles +#define ei4_tx_err_inj_a_fine_sel_fixed7 0x7000 //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 7 cycles. #define ei4_tx_err_inj_a_fine_sel_clear 0x8FFF // Clear mask -#define ei4_tx_err_inj_a_coarse_sel_8_23 0x0100 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 8-32, mean of 16 -#define ei4_tx_err_inj_a_coarse_sel_12_19 0x0200 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 12-19, mean of 16 -#define ei4_tx_err_inj_a_coarse_sel_14_17 0x0300 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 14-17, mean of 16 -#define ei4_tx_err_inj_a_coarse_sel_min 0x0400 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Min range of 15-16, mean of 16 -#define ei4_tx_err_inj_a_coarse_sel_fixed16 0x0500 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 16 -#define ei4_tx_err_inj_a_coarse_sel_fixed24 0x0600 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 24 -#define ei4_tx_err_inj_a_coarse_sel_fixed20 0x0700 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 20. -#define ei4_tx_err_inj_a_coarse_sel_clear 0xF8FF // Clear mask -#define ei4_tx_err_inj_a_ber_sel 0x0000 //Used to set the random bit error injection rate to a particular value. See workbook for details. +#define ei4_tx_err_inj_a_coarse_sel_9_24 0x0100 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 9-24, mean of 16.5 +#define ei4_tx_err_inj_a_coarse_sel_13_20 0x0200 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 13-20, mean of 16.5 +#define ei4_tx_err_inj_a_coarse_sel_16_19 0x0300 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-19, mean of 16.5 +#define ei4_tx_err_inj_a_coarse_sel_17_18 0x0400 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-17, mean of 16.5 +#define ei4_tx_err_inj_a_coarse_sel_1_8 0x0500 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 1-8, mean of 4.5 +#define ei4_tx_err_inj_a_coarse_sel_3_6 0x0600 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 3-6, mean of 4.5 +#define ei4_tx_err_inj_a_coarse_sel_4_5 0x0700 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 4-5, mean of 4.5 +#define ei4_tx_err_inj_a_coarse_sel_fixed1 0x0800 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 1 +#define ei4_tx_err_inj_a_coarse_sel_fixed3 0x0900 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 3 +#define ei4_tx_err_inj_a_coarse_sel_fixed5 0x0A00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 5 +#define ei4_tx_err_inj_a_coarse_sel_fixed6 0x0B00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 6 +#define ei4_tx_err_inj_a_coarse_sel_fixed7 0x0C00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 7 +#define ei4_tx_err_inj_a_coarse_sel_fixed17 0x0D00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 17 +#define ei4_tx_err_inj_a_coarse_sel_fixed21 0x0E00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 21 +#define ei4_tx_err_inj_a_coarse_sel_fixed25 0x0F00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 25 +#define ei4_tx_err_inj_a_coarse_sel_clear 0xF0FF // Clear mask +#define ei4_tx_err_inj_a_ber_sel 0x0000 //Used to set the random bit error injection rate for pattern A. When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). #define ei4_tx_err_inj_a_ber_sel_clear 0x3FC0 // Clear mask // ei4_tx_ber_cntl_b_pp Register field name data value Description -#define ei4_tx_err_inj_b_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data.(default) +#define ei4_tx_err_inj_b_rand_beat_dis 0x8000 //Used to disable randomization of error inject on different beats of data for pattern B. #define ei4_tx_err_inj_b_rand_beat_dis_clear 0x7FFF // Clear mask -#define ei4_tx_err_inj_b_fine_sel_0_15 0x1000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-15 -#define ei4_tx_err_inj_b_fine_sel_0_7 0x2000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-7 -#define ei4_tx_err_inj_b_fine_sel_0_3 0x3000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-3 -#define ei4_tx_err_inj_b_fine_sel_0_1 0x4000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Range of 0-1 -#define ei4_tx_err_inj_b_fine_sel_fixed1 0x5000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 1 -#define ei4_tx_err_inj_b_fine_sel_fixed3 0x6000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 3 -#define ei4_tx_err_inj_b_fine_sel_fixed7 0x7000 //Acts as an adder to the error rate and so does not have any over all effect on the average of the bit error rate. Fixed 7. +#define ei4_tx_err_inj_b_fine_sel_1_16 0x1000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-16 cycles +#define ei4_tx_err_inj_b_fine_sel_1_8 0x2000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-8 cycles +#define ei4_tx_err_inj_b_fine_sel_1_4 0x3000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-4 cycles +#define ei4_tx_err_inj_b_fine_sel_1_2 0x4000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Random offset in range of 1-2 cycles +#define ei4_tx_err_inj_b_fine_sel_fixed1 0x5000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 1 cycle +#define ei4_tx_err_inj_b_fine_sel_fixed3 0x6000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 3 cycles +#define ei4_tx_err_inj_b_fine_sel_fixed7 0x7000 //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI). Fixed offset of 7 cycles. #define ei4_tx_err_inj_b_fine_sel_clear 0x8FFF // Clear mask -#define ei4_tx_err_inj_b_coarse_sel_8_23 0x0100 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 8-32, mean of 16 -#define ei4_tx_err_inj_b_coarse_sel_12_19 0x0200 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 12-19, mean of 16 -#define ei4_tx_err_inj_b_coarse_sel_14_17 0x0300 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Range of 14-17, mean of 16 -#define ei4_tx_err_inj_b_coarse_sel_min 0x0400 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Min range of 15-16, mean of 16 -#define ei4_tx_err_inj_b_coarse_sel_fixed16 0x0500 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 16 -#define ei4_tx_err_inj_b_coarse_sel_fixed24 0x0600 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 24 -#define ei4_tx_err_inj_b_coarse_sel_fixed20 0x0700 //Multipler for the error rate, narrows or widens the range of the variance in the bit error rate. Fixed 20. -#define ei4_tx_err_inj_b_coarse_sel_clear 0xF8FF // Clear mask -#define ei4_tx_err_inj_b_ber_sel 0x0000 //Used to set the random bit error injection rate to a particular value. See workbook for details. +#define ei4_tx_err_inj_b_coarse_sel_9_24 0x0100 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 9-24, mean of 16.5 +#define ei4_tx_err_inj_b_coarse_sel_13_20 0x0200 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 13-20, mean of 16.5 +#define ei4_tx_err_inj_b_coarse_sel_16_19 0x0300 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-19, mean of 16.5 +#define ei4_tx_err_inj_b_coarse_sel_17_18 0x0400 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 16-17, mean of 16.5 +#define ei4_tx_err_inj_b_coarse_sel_1_8 0x0500 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 1-8, mean of 4.5 +#define ei4_tx_err_inj_b_coarse_sel_3_6 0x0600 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 3-6, mean of 4.5 +#define ei4_tx_err_inj_b_coarse_sel_4_5 0x0700 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Range of 4-5, mean of 4.5 +#define ei4_tx_err_inj_b_coarse_sel_fixed1 0x0800 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 1 +#define ei4_tx_err_inj_b_coarse_sel_fixed3 0x0900 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 3 +#define ei4_tx_err_inj_b_coarse_sel_fixed5 0x0A00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 5 +#define ei4_tx_err_inj_b_coarse_sel_fixed6 0x0B00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 6 +#define ei4_tx_err_inj_b_coarse_sel_fixed7 0x0C00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 7 +#define ei4_tx_err_inj_b_coarse_sel_fixed17 0x0D00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 17 +#define ei4_tx_err_inj_b_coarse_sel_fixed21 0x0E00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 21 +#define ei4_tx_err_inj_b_coarse_sel_fixed25 0x0F00 //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B. There are also a number of nonrandom settings which are specifically chosen to avoid powers of two. Fixed 25 +#define ei4_tx_err_inj_b_coarse_sel_clear 0xF0FF // Clear mask +#define ei4_tx_err_inj_b_ber_sel 0x0000 //Used to set the random bit error injection rate for pattern B. When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). #define ei4_tx_err_inj_b_ber_sel_clear 0x3FC0 // Clear mask // ei4_tx_bist_cntl_pp Register field name data value Description -#define ei4_tx_bist_en 0x8000 //TBD +#define ei4_tx_bist_en 0x8000 //TBD. jgr #define ei4_tx_bist_en_clear 0x7FFF // Clear mask -#define ei4_tx_bist_clr 0x4000 //TBD +#define ei4_tx_bist_clr 0x4000 //TBD. jgr #define ei4_tx_bist_clr_clear 0xBFFF // Clear mask -#define ei4_tx_bist_prbs7_en 0x2000 //TBD +#define ei4_tx_bist_prbs7_en 0x2000 //TBD. This field is updated by the TX BIST logic when BIST is running. jgr #define ei4_tx_bist_prbs7_en_clear 0xDFFF // Clear mask // ei4_tx_ber_cntl_sls_pp Register field name data value Description -#define ei4_tx_err_inj_sls_mode 0x8000 //Used to set the random bit error injection during SLS. See workbook for details. +#define ei4_tx_err_inj_sls_mode 0x8000 //Used to set the random bit error injection for pattern A to work during SLS transmission only. #define ei4_tx_err_inj_sls_mode_clear 0x7FFF // Clear mask -#define ei4_tx_err_inj_sls_all_cmd 0x4000 //Used to qualify the SLS mode error injection, to inject on all command values. See workbook for details. +#define ei4_tx_err_inj_sls_all_cmd 0x4000 //Used to qualify the SLS mode error injection for pattern A, to inject on all SLS command transmissions. #define ei4_tx_err_inj_sls_all_cmd_clear 0xBFFF // Clear mask -#define ei4_tx_err_inj_sls_cmd 0x0000 //Used to qualify the SLS mode error injection, to only inject on this set command value. See workbook for details. +#define ei4_tx_err_inj_sls_recal 0x2000 //Used to qualify the SLS mode error injection for pattern A, to inject on the calibration lane only when not sending an SLS command. See workbook for details. +#define ei4_tx_err_inj_sls_recal_clear 0xDFFF // Clear mask +#define ei4_tx_err_inj_sls_cmd 0x0000 //Used to qualify the SLS mode error injection for pattern A, to inject on only this SLS command transmission. See workbook for SLS command codes. #define ei4_tx_err_inj_sls_cmd_clear 0xFFC0 // Clear mask // ei4_tx_cntl_pp Register field name data value Description @@ -3021,8 +3590,16 @@ const char* const ei4_GCR_sub_reg_names[] = { // ei4_tx_reset_cfg_pp Register field name data value Description #define ei4_tx_reset_cfg_hld_clear 0x0000 // Clear mask +// ei4_tx_tdr_cntl2_pp Register field name data value Description +#define ei4_tx_tdr_pulse_offset 0x0000 //Offset value for TDR pulse. +#define ei4_tx_tdr_pulse_offset_clear 0x000F // Clear mask + +// ei4_tx_tdr_cntl3_pp Register field name data value Description +#define ei4_tx_tdr_pulse_width 0x0000 //With of TDR pulse. +#define ei4_tx_tdr_pulse_width_clear 0x000F // Clear mask + // ei4_rx_mode_pl Register field name data value Description -#define ei4_rx_lane_pdwn 0x8000 //Used to receive inhibit and fully power down a lane. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers ei4_rx_lane_disabled_vec_0_15 and ei4_rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines. +#define ei4_rx_lane_pdwn 0x8000 //Used to receive inhibit and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (ei4_rx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance. Also note that per-group registers ei4_rx_lane_disabled_vec_0_15 and ei4_rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. #define ei4_rx_lane_pdwn_clear 0x7FFF // Clear mask #define ei4_rx_lane_scramble_disable 0x0200 //Used to disable the RX descrambler on a specific lane or all lanes by using a per-lane/per-group global write. #define ei4_rx_lane_scramble_disable_clear 0xFDFF // Clear mask @@ -3030,10 +3607,8 @@ const char* const ei4_GCR_sub_reg_names[] = { // ei4_rx_cntl_pl Register field name data value Description #define ei4_rx_block_lock_lane 0x8000 //Enables rotation and checking for block lock. #define ei4_rx_block_lock_lane_clear 0x7FFF // Clear mask -#define ei4_rx_check_skew_lane 0x4000 //Per-Lane Initialization controls checks skew requst +#define ei4_rx_check_skew_lane 0x4000 //Per-Lane Initialization controls. Checks skew request #define ei4_rx_check_skew_lane_clear 0xBFFF // Clear mask -#define ei4_rx_cntl_pl_tbd 0x0000 //TBD -#define ei4_rx_cntl_pl_tbd_clear 0xC07F // Clear mask // ei4_rx_spare_mode_pl Register field name data value Description #define ei4_rx_pl_spare_mode_0 0x8000 //Per-lane spare mode latch @@ -3053,35 +3628,23 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_pl_spare_mode_7 0x0100 //Per-lane spare mode latch #define ei4_rx_pl_spare_mode_7_clear 0xFEFF // Clear mask -// ei4_rx_prot_edge_status_pl Register field name data value Description -#define ei4_rx_phaserot_left_edge 0x0000 //RX Phase Rotator left edge. -#define ei4_rx_phaserot_left_edge_clear 0x80FF // Clear mask - // ei4_rx_bist_stat_pl Register field name data value Description #define ei4_rx_bist_err 0x8000 //Indicates a RXBIST error occurred. #define ei4_rx_bist_err_clear 0x7FFF // Clear mask #define ei4_rx_bist_done 0x4000 //Indicates a RXBIST has completed. #define ei4_rx_bist_done_clear 0xBFFF // Clear mask -// ei4_rx_eyeopt_mode_pl Register field name data value Description -#define ei4_rx_ddc_disable 0x8000 //When set to a 1 this causes the phase detector to stop running which results in the phase rotator value to stop updating. This mode is used for diagnostics and characterization. -#define ei4_rx_ddc_disable_clear 0x7FFF // Clear mask - -// ei4_rx_eyeopt_stat_pl Register field name data value Description -#define ei4_rx_eyeopt_stat_tbd 0x8000 //Eye optimization status. TBD -#define ei4_rx_eyeopt_stat_tbd_clear 0x7FFF // Clear mask - // ei4_rx_offset_even_pl Register field name data value Description #define ei4_rx_offset_even_samp1 0x0000 //This is the vertical offset of the even sampling latch. -#define ei4_rx_offset_even_samp1_clear 0xC0FF // Clear mask +#define ei4_rx_offset_even_samp1_clear 0x80FF // Clear mask #define ei4_rx_offset_even_samp0 0x0000 //This is the vertical offset of the even sampling latch. -#define ei4_rx_offset_even_samp0_clear 0x3FC0 // Clear mask +#define ei4_rx_offset_even_samp0_clear 0x7F80 // Clear mask // ei4_rx_offset_odd_pl Register field name data value Description #define ei4_rx_offset_odd_samp1 0x0000 //This is the vertical offset of the odd sampling latch. #define ei4_rx_offset_odd_samp1_clear 0x00FF // Clear mask #define ei4_rx_offset_odd_samp0 0x0000 //This is the vertical offset of the odd sampling latch. -#define ei4_rx_offset_odd_samp0_clear 0x3FC0 // Clear mask +#define ei4_rx_offset_odd_samp0_clear 0x7F80 // Clear mask // ei4_rx_amp_val_pl Register field name data value Description #define ei4_rx_amp_peak 0x0000 //This is the vertical offset of the pre-amp. @@ -3104,7 +3667,7 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_ext_sl_clear 0xFBFF // Clear mask // ei4_rx_fifo_stat_pl Register field name data value Description -#define ei4_rx_fifo_l2u_dly 0x0000 //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine. For setting X, the latency is 4*X to 4*X+4 UI. Default is 16-20 UI. +#define ei4_rx_fifo_l2u_dly 0x0000 //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine. For setting X, the latency is 2*X to 2*X+2 UI. Default is 8-10 UI. #define ei4_rx_fifo_l2u_dly_clear 0x0FFF // Clear mask #define ei4_rx_fifo_init 0x0800 //Initializes the fifo unload counter with the load counter and initializes the fifo load to unload delay #define ei4_rx_fifo_init_clear 0xF7FF // Clear mask @@ -3152,7 +3715,7 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_pl_fir_errs_clear 0x7FFF // Clear mask // ei4_rx_fir_mask_pl Register field name data value Description -#define ei4_rx_pl_fir_errs_mask 0x8000 //A 1 in this field indicates that a register or state machine parity error has occurred in per-group logic. +#define ei4_rx_pl_fir_errs_mask 0x8000 //FIR mask for register or state machine parity checkers in per-lane logic. A value of 1 masks the error from generating a FIR error. #define ei4_rx_pl_fir_errs_mask_clear 0x7FFF // Clear mask // ei4_rx_fir_error_inject_pl Register field name data value Description @@ -3186,12 +3749,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_fifo_dec_l2u_dly_clear 0xBFFF // Clear mask #define ei4_rx_clr_skew_valid 0x2000 //Clear skew valid registers #define ei4_rx_clr_skew_valid_clear 0xDFFF // Clear mask -#define ei4_rx_fifo_cntl_spare 0x1000 //Spare to make cr happy. -#define ei4_rx_fifo_cntl_spare_clear 0xEFFF // Clear mask // ei4_rx_ber_status_pl Register field name data value Description #define ei4_rx_ber_count 0x0000 //Per-Lane (PL) Diagnostic Bit Error Rate (BER) error counter. Increments when in diagnostic BER mode AND the output of the descrambler is non-zero. This counter counts errors on every UI so it is a true BER counter. -#define ei4_rx_ber_count_clear 0x80FF // Clear mask +#define ei4_rx_ber_count_clear 0x00FF // Clear mask #define ei4_rx_ber_count_saturated 0x0080 //PL Diag BER Error Counter saturation indicator. When '1' indicates that the error counter has saturated to the selected max value. A global per-lane read of this field will indicate if any lane error counters in the group are saturated. #define ei4_rx_ber_count_saturated_clear 0xFF7F // Clear mask #define ei4_rx_ber_count_frozen_by_lane 0x0040 //PL Diag BER Error Counter and or PP Timer has been frozen by another lane's error counter being saturated. @@ -3244,8 +3805,20 @@ const char* const ei4_GCR_sub_reg_names[] = { // ei4_rx_eye_width_cntl_pl Register field name data value Description #define ei4_rx_reset_hist_eye_width_min 0x8000 //RX Historic Eye Minimum Reset--reset historic min to maximum value and clears valid bits. #define ei4_rx_reset_hist_eye_width_min_clear 0x7FFF // Clear mask -#define ei4_rx_eye_width_cntl_pl_spare 0x4000 //RX Eye width control spare -#define ei4_rx_eye_width_cntl_pl_spare_clear 0xBFFF // Clear mask + +// ei4_rx_trace_pl Register field name data value Description +#define ei4_rx_ln_trc_en 0x8000 //Enable tracing of this lane +#define ei4_rx_ln_trc_en_clear 0x7FFF // Clear mask + +// ei4_rx_servo_ber_count_pl Register field name data value Description +#define ei4_rx_servo_ber_count 0x0000 //Servo-based bit error count. +#define ei4_rx_servo_ber_count_clear 0x000F // Clear mask + +// ei4_rx_eye_opt_stat_pl Register field name data value Description +#define ei4_rx_bad_eye_opt_ber 0x8000 //Eye opt Step failed BER test--lane marked bad +#define ei4_rx_bad_eye_opt_ber_clear 0x7FFF // Clear mask +#define ei4_rx_bad_eye_opt_width 0x4000 //Eye opt Step failed width test--lane marked bad +#define ei4_rx_bad_eye_opt_width_clear 0xBFFF // Clear mask // ei4_rx_clk_mode_pg Register field name data value Description #define ei4_rx_clk_pdwn 0x8000 //Used to disable the rx clock and put it into a low power state. @@ -3271,6 +3844,18 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_pg_spare_mode_7 0x0100 //Per-group spare mode latch #define ei4_rx_pg_spare_mode_7_clear 0xFEFF // Clear mask +// ei4_rx_stop_cntl_stat_pg Register field name data value Description +#define ei4_rx_stop_state_enable 0x8000 //Enable State machine stop of address +#define ei4_rx_stop_state_enable_clear 0x7FFF // Clear mask +#define ei4_rx_state_stopped 0x4000 //State Machines stopped +#define ei4_rx_state_stopped_clear 0xBFFF // Clear mask +#define ei4_rx_resume_from_stop 0x2000 //Resume stopped state machines and /or counters +#define ei4_rx_resume_from_stop_clear 0xDFFF // Clear mask +#define ei4_rx_stop_addr_msb 0x0000 //Stop address Most-significant four bits 0 to 3 +#define ei4_rx_stop_addr_msb_clear 0xFF0F // Clear mask +#define ei4_rx_stop_mask_msb 0x0000 //Stop mask Most-significant four bits 0 to 3 +#define ei4_rx_stop_mask_msb_clear 0xF0F0 // Clear mask + // ei4_rx_mode_pg Register field name data value Description #define ei4_rx_master_mode 0x8000 //Master Mode #define ei4_rx_master_mode_clear 0x7FFF // Clear mask @@ -3293,9 +3878,13 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_grp_repair_vec_16_31 0x0000 //TBD #define ei4_rx_grp_repair_vec_16_31_clear 0x0000 // Clear mask -// ei4_rx_recal_mode_pg Register field name data value Description -#define ei4_rx_recal_disable 0x8000 //TBD -#define ei4_rx_recal_disable_clear 0x7FFF // Clear mask +// ei4_rx_stop_addr_lsb_pg Register field name data value Description +#define ei4_rx_stop_addr_lsb 0x0000 //Stop address least-significant 16 bits 4 to 19 +#define ei4_rx_stop_addr_lsb_clear 0x0000 // Clear mask + +// ei4_rx_stop_mask_lsb_pg Register field name data value Description +#define ei4_rx_stop_mask_lsb 0x0000 //Stop mask least-significant 16 bits 4 to 19 +#define ei4_rx_stop_mask_lsb_clear 0x0000 // Clear mask // ei4_rx_reset_act_pg Register field name data value Description #define ei4_rx_reset_cfg_ena 0x8000 //Enable Configurable Group Reset @@ -3321,18 +3910,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_end_lane_id 0x0000 //This field is used to programmably set the last lane position in the group but relative to the bus. #define ei4_rx_end_lane_id_clear 0x7F80 // Clear mask -// ei4_rx_minikerf_pg Register field name data value Description -#define ei4_rx_minikerf 0x0000 //Used to configure the rx Minikerf for analog characterization. -#define ei4_rx_minikerf_clear 0x0000 // Clear mask - -// ei4_rx_bist_cntl_pg Register field name data value Description -#define ei4_rx_bist_en 0x8000 //TBD -#define ei4_rx_bist_en_clear 0x7FFF // Clear mask -#define ei4_rx_bist_jitter_pulse_ctl 0x0000 //TBD -#define ei4_rx_bist_jitter_pulse_ctl_clear 0x9FFF // Clear mask -#define ei4_rx_bist_min_eye_width 0x0000 //TBD -#define ei4_rx_bist_min_eye_width_clear 0xE03F // Clear mask - // ei4_rx_sls_mode_pg Register field name data value Description #define ei4_rx_sls_disable 0x8000 //Disables receiving & decoding of SLS commands #define ei4_rx_sls_disable_clear 0x7FFF // Clear mask @@ -3360,10 +3937,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_start_repair_clear 0xEFFF // Clear mask #define ei4_rx_start_func_mode 0x0800 //When this register is written to a 1 the training state machine will run the transition to functional data portion of the training states. #define ei4_rx_start_func_mode_clear 0xF7FF // Clear mask -#define ei4_rx_start_bist_helper_1 0x0200 //Starts BIST helper state machine. (wtbyp -#define ei4_rx_start_bist_helper_2 0x0400 //Starts BIST helper state machine. (ocal -#define ei4_rx_start_bist_helper_3 0x0600 //Starts BIST helper state machine. (bist -#define ei4_rx_start_bist_helper_clear 0xF9FF // Clear mask +#define ei4_rx_start_bist 0x0400 //Run initializations for BIST before enabling the BIST state machine. +#define ei4_rx_start_bist_clear 0xFBFF // Clear mask +#define ei4_rx_start_offset_cal 0x0200 //Run offset cal. +#define ei4_rx_start_offset_cal_clear 0xFDFF // Clear mask +#define ei4_rx_start_wt_bypass 0x0100 //Run wiretest bypass. +#define ei4_rx_start_wt_bypass_clear 0xFEFF // Clear mask // ei4_rx_training_status_pg Register field name data value Description #define ei4_rx_wiretest_done 0x8000 //When this bit is read as a 1, the wiretest training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state. @@ -3376,8 +3955,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_repair_done_clear 0xEFFF // Clear mask #define ei4_rx_func_mode_done 0x0800 //When this bit is read as a 1, the transition to functional data training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state. #define ei4_rx_func_mode_done_clear 0xF7FF // Clear mask -#define ei4_rx_bist_helper_done 0x0400 //When this bit is read as a 1, the BIST helper state machine has completed. -#define ei4_rx_bist_helper_done_clear 0xFBFF // Clear mask +#define ei4_rx_bist_started 0x0400 //When this bit is read as a 1, the RX BIST initialization has finished and RX BIST has started running. +#define ei4_rx_bist_started_clear 0xFBFF // Clear mask +#define ei4_rx_offset_cal_done 0x0200 //When this bit is read as a 1, offset cal has completed. +#define ei4_rx_offset_cal_done_clear 0xFDFF // Clear mask +#define ei4_rx_wt_bypass_done 0x0100 //When this bit is read as a 1, wiretest bypass has completed. +#define ei4_rx_wt_bypass_done_clear 0xFEFF // Clear mask #define ei4_rx_wiretest_failed 0x0080 //When this bit is read as a 1, the wiretest training state encountered an error. #define ei4_rx_wiretest_failed_clear 0xFF7F // Clear mask #define ei4_rx_deskew_failed 0x0040 //When this bit is read as a 1, the deskew training state encountered an error. @@ -3386,20 +3969,26 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_eye_opt_failed_clear 0xFFDF // Clear mask #define ei4_rx_repair_failed 0x0010 //When this bit is read as a 1, the static lane repair training state encountered an error. #define ei4_rx_repair_failed_clear 0xFFEF // Clear mask -#define ei4_rx_func_mode_failed 0x0008 //When this bit is read as a 1, the transition to functional data training state encountered and error. +#define ei4_rx_func_mode_failed 0x0008 //When this bit is read as a 1, the transition to functional data training state encountered an error. #define ei4_rx_func_mode_failed_clear 0xFFF7 // Clear mask +#define ei4_rx_start_bist_failed 0x0004 //When this bit is read as a 1, the RX BIST initialization has encountered and error. +#define ei4_rx_start_bist_failed_clear 0xFFFB // Clear mask +#define ei4_rx_offset_cal_failed 0x0002 //When this bit is read as a 1, offset cal has encountered an error. +#define ei4_rx_offset_cal_failed_clear 0xFFFD // Clear mask +#define ei4_rx_wt_bypass_failed 0x0001 //When this bit is read as a 1, wiretest bypass has encountered an error. +#define ei4_rx_wt_bypass_failed_clear 0xFFFE // Clear mask // ei4_rx_recal_status_pg Register field name data value Description -#define ei4_rx_recal_status 0x0000 //\bRX Recalibration Status\b +#define ei4_rx_recal_status 0x0000 //RX Recalibration Status #define ei4_rx_recal_status_clear 0x0000 // Clear mask // ei4_rx_timeout_sel_pg Register field name data value Description -#define ei4_rx_sls_timeout_sel_tap1 0x2000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 64k UI -#define ei4_rx_sls_timeout_sel_tap2 0x4000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 128k UI -#define ei4_rx_sls_timeout_sel_tap3 0x6000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 256k UI -#define ei4_rx_sls_timeout_sel_tap4 0x8000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 512k UI -#define ei4_rx_sls_timeout_sel_tap5 0xA000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 1024k UI -#define ei4_rx_sls_timeout_sel_tap6 0xC000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 32768k UI +#define ei4_rx_sls_timeout_sel_tap1 0x2000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 54.6us +#define ei4_rx_sls_timeout_sel_tap2 0x4000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 109.2us +#define ei4_rx_sls_timeout_sel_tap3 0x6000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 218.4us +#define ei4_rx_sls_timeout_sel_tap4 0x8000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 436.7us +#define ei4_rx_sls_timeout_sel_tap5 0xA000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 873.5us +#define ei4_rx_sls_timeout_sel_tap6 0xC000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) 28.0ms #define ei4_rx_sls_timeout_sel_tap7 0xE000 //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command) infinite #define ei4_rx_sls_timeout_sel_clear 0x1FFF // Clear mask #define ei4_rx_ds_bl_timeout_sel_tap1 0x0400 //Selects Deskew Block Lock Timeout value. 128k UI or 13.6us @@ -3447,22 +4036,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_fifo_final_l2u_min_err_thresh_tap3 0x000C //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by ei4_rx_eo_final_l2u_timeout_sel. 255 errors #define ei4_rx_fifo_final_l2u_min_err_thresh_clear 0xFF33 // Clear mask -// ei4_rx_state_debug_pg Register field name data value Description -#define ei4_rx_start_at_state_en 0x8000 //Enable Statemachine to Start -#define ei4_rx_start_at_state_en_clear 0x7FFF // Clear mask -#define ei4_rx_stop_at_state_en 0x4000 //Enable Statemachine to Stop -#define ei4_rx_stop_at_state_en_clear 0xBFFF // Clear mask -#define ei4_rx_state_stopped 0x2000 //Statemachine Has Stopped at ei4_rx_STOP_STATE -#define ei4_rx_state_stopped_clear 0xDFFF // Clear mask -#define ei4_rx_cur_state 0x0000 //Current Value of Statemachine Vector -#define ei4_rx_cur_state_clear 0xE01F // Clear mask - -// ei4_rx_state_val_pg Register field name data value Description -#define ei4_rx_start_state 0x0000 //Start Value for Statemachine -#define ei4_rx_start_state_clear 0x00FF // Clear mask -#define ei4_rx_stop_state 0x0000 //Stop Value for Statemachine -#define ei4_rx_stop_state_clear 0xFF00 // Clear mask - // ei4_rx_sls_status_pg Register field name data value Description #define ei4_rx_sls_cmd_val 0x8000 //Current SLS Command Valid #define ei4_rx_sls_cmd_val_clear 0x7FFF // Clear mask @@ -3500,53 +4073,62 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_sls_err_chk_cnt 0x0000 //Error count result for SLS error checking mode #define ei4_rx_sls_err_chk_cnt_clear 0xFF00 // Clear mask -// ei4_rx_prot_mode_pg Register field name data value Description -#define ei4_rx_reverse_shift 0x8000 //RX Phase Rotator Direction -#define ei4_rx_reverse_shift_clear 0x7FFF // Clear mask - // ei4_rx_fir1_pg Register field name data value Description +#define ei4_rx_pg_fir1_errs_par_err_ei4_rx_rpr_state 0x0800 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. +#define ei4_rx_pg_fir1_errs_par_err_ei4_rx_eyeopt_state 0x0C00 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. +#define ei4_rx_pg_fir1_errs_par_err_dsm_state 0x0400 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. +#define ei4_rx_pg_fir1_errs_par_err_rxdsm_state 0x0400 //A Per-Group RXCTL Register or State Machine Parity Error has occurred. #define ei4_rx_pg_fir1_errs_clear 0x0003 // Clear mask #define ei4_rx_pl_fir_err 0x0001 //Summary bit indicating an RX per-lane register or state machine parity error has occurred in one or more lanes. The ei4_rx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane. #define ei4_rx_pl_fir_err_clear 0xFFFE // Clear mask // ei4_rx_fir2_pg Register field name data value Description -#define ei4_rx_pg_fir2_errs_clear 0x1FFF // Clear mask +#define ei4_rx_pg_fir2_errs_err_sls_hndshk_sm 0x0200 //A Per-Group Register or State Machine Parity Error has occurred. RXCTL SLS Handshake SM Parity Error. +#define ei4_rx_pg_fir2_errs_clear 0x01FF // Clear mask // ei4_rx_fir1_mask_pg Register field name data value Description #define ei4_rx_pg_fir1_errs_mask_clear 0x0003 // Clear mask -#define ei4_rx_pg_chan_fail_mask 0x0002 //FIR mask for generation of channel fail error when Max Spares Exceeded is active. Default is disabled with a value of 1. -#define ei4_rx_pg_chan_fail_mask_clear 0xFFFD // Clear mask #define ei4_rx_pl_fir_err_mask 0x0001 //FIR mask for the summary bit that indicates an RX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane parity errors from causing a FIR error. #define ei4_rx_pl_fir_err_mask_clear 0xFFFE // Clear mask // ei4_rx_fir2_mask_pg Register field name data value Description -#define ei4_rx_pg_fir2_errs_mask_clear 0x1FFF // Clear mask +#define ei4_rx_pg_fir2_errs_mask_mask_sls_hndshk_sm 0x0200 //FIR mask for register or state machine parity checkers in per-group RX logic. A value of 1 masks the error from generating a FIR error. RXCTL SLS Handshake SM Parity Error Mask. +#define ei4_rx_pg_fir2_errs_mask_clear 0x01FF // Clear mask // ei4_rx_fir1_error_inject_pg Register field name data value Description -#define ei4_rx_pg_fir1_err_inj_inj_par_err 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define ei4_rx_pg_fir1_err_inj_1 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define ei4_rx_pg_fir1_err_inj_inj_rpr_sm 0x0800 //RX Per-Group Parity Error Injection RXCTL Repair SM Parity Error Inject. +#define ei4_rx_pg_fir1_err_inj_inj_eyeopt_sm 0x0C00 //RX Per-Group Parity Error Injection RXCTL Eyeopt SM Parity Error Inject. +#define ei4_rx_pg_fir1_err_inj_inj_dsm_sm 0x0400 //RX Per-Group Parity Error Injection RXCTL Deskew SM Parity Error Inject. +#define ei4_rx_pg_fir1_err_inj_inj_rxdsm_sm 0x0400 //RX Per-Group Parity Error Injection RXCTL RX Deskew SM Parity Error Inject. #define ei4_rx_pg_fir1_err_inj_clear 0x0003 // Clear mask // ei4_rx_fir2_error_inject_pg Register field name data value Description -#define ei4_rx_pg_fir2_err_inj_inj_par_err 0x2000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. -#define ei4_rx_pg_fir2_err_inj_clear 0x1FFF // Clear mask +#define ei4_rx_pg_fir2_err_inj_1 0x2000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define ei4_rx_pg_fir2_err_inj_inj_sls_hndshk_sm 0x0200 //RX Per-Group Parity Error Injection RXCTL SLS Handshake SM Parity Error Inject. +#define ei4_rx_pg_fir2_err_inj_clear 0x01FF // Clear mask // ei4_rx_fir_training_pg Register field name data value Description -#define ei4_rx_pg_fir_training_error 0x8000 //A Training Error has occurred. The Training Error FFDC registers should be read to help isolate to a particular piece of logic. +#define ei4_rx_pg_fir_training_error 0x8000 //This field is now defunct and is permanently masked in the ei4_rx_fir_training_mask_pg FIR isolation register. #define ei4_rx_pg_fir_training_error_clear 0x7FFF // Clear mask -#define ei4_rx_pg_fir_static_spare_deployed 0x4000 //A spare lane has been deployed during training to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed +#define ei4_rx_pg_fir_static_spare_deployed 0x4000 //A spare lane has been deployed during training to heal a lane that was detected as bad. ei4_rx_Static_Spare_Deployed (SSD) will be set after the repair training step if during training either wiretest, deskew, eyeopt or repair has detected one or more bad lanes have been detected. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed and the ei4_rx_bad_lane. #define ei4_rx_pg_fir_static_spare_deployed_clear 0xBFFF // Clear mask -#define ei4_rx_pg_fir_static_max_spares_exceeded 0x2000 //A lane has been detected as bad during training but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define ei4_rx_pg_fir_static_max_spares_exceeded 0x2000 //A lane has been detected as bad during training but there are no spare lanes available to heal it. THIS FIR WILL NOT BE SET UNTIL THE REPAIR TRAINING STEP HAS BEEN RUN. THIS IS A CATASTROPHIC FAILURE FOR THE BUS WHEN IN MISSION MODE BUT ALL TRAINING STEPS WILL STILL BE RUN ON WHATEVER GOOD LANES THERE ARE. ei4_rx_static_max_spares_exceeded will be set if wiretest, deskew, eyeopt or repair find the excessive number of bad lanes. #define ei4_rx_pg_fir_static_max_spares_exceeded_clear 0xDFFF // Clear mask -#define ei4_rx_pg_fir_dynamic_spare_deployed 0x1000 //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. -#define ei4_rx_pg_fir_dynamic_spare_deployed_clear 0xEFFF // Clear mask -#define ei4_rx_pg_fir_dynamic_max_spares_exceeded 0x0800 //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. -#define ei4_rx_pg_fir_dynamic_max_spares_exceeded_clear 0xF7FF // Clear mask -#define ei4_rx_pg_fir_recal_error 0x0400 //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. -#define ei4_rx_pg_fir_recal_error_clear 0xFBFF // Clear mask -#define ei4_rx_pg_fir_recal_spare_deployed 0x0200 //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. -#define ei4_rx_pg_fir_recal_spare_deployed_clear 0xFDFF // Clear mask -#define ei4_rx_pg_fir_recal_max_spares_exceeded 0x0100 //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. -#define ei4_rx_pg_fir_recal_max_spares_exceeded_clear 0xFEFF // Clear mask +#define ei4_rx_pg_fir_dynamic_repair_error 0x1000 //A Dynamic Repair error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. +#define ei4_rx_pg_fir_dynamic_repair_error_clear 0xEFFF // Clear mask +#define ei4_rx_pg_fir_dynamic_spare_deployed 0x0800 //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. +#define ei4_rx_pg_fir_dynamic_spare_deployed_clear 0xF7FF // Clear mask +#define ei4_rx_pg_fir_dynamic_max_spares_exceeded 0x0400 //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define ei4_rx_pg_fir_dynamic_max_spares_exceeded_clear 0xFBFF // Clear mask +#define ei4_rx_pg_fir_recal_error 0x0200 //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic. +#define ei4_rx_pg_fir_recal_error_clear 0xFDFF // Clear mask +#define ei4_rx_pg_fir_recal_spare_deployed 0x0100 //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed. +#define ei4_rx_pg_fir_recal_spare_deployed_clear 0xFEFF // Clear mask +#define ei4_rx_pg_fir_recal_max_spares_exceeded 0x0080 //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define ei4_rx_pg_fir_recal_max_spares_exceeded_clear 0xFF7F // Clear mask +#define ei4_rx_pg_fir_too_many_bus_errors 0x0040 //More than one lane has been detected as having too many errors during functional operation. THIS IS A CATASTROPHIC FAILURE FOR THE BUS. +#define ei4_rx_pg_fir_too_many_bus_errors_clear 0xFFBF // Clear mask // ei4_rx_fir_training_mask_pg Register field name data value Description #define ei4_rx_pg_fir_training_error_mask 0x8000 //FIR mask for ei4_rx_pg_fir_training_error. @@ -3555,16 +4137,20 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_pg_fir_static_spare_deployed_mask_clear 0xBFFF // Clear mask #define ei4_rx_pg_fir_static_max_spares_exceeded_mask 0x2000 //FIR mask for ei4_rx_pg_fir_static_max_spares_exceeded #define ei4_rx_pg_fir_static_max_spares_exceeded_mask_clear 0xDFFF // Clear mask -#define ei4_rx_pg_fir_dynamic_spare_deployed_mask 0x1000 //FIR mask for ei4_rx_pg_fir_dynamic_spare_deployed. -#define ei4_rx_pg_fir_dynamic_spare_deployed_mask_clear 0xEFFF // Clear mask -#define ei4_rx_pg_fir_dynamic_max_spares_exceeded_mask 0x0800 //FIR mask for ei4_rx_pg_fir_dynamic_max_spares_exceeded. -#define ei4_rx_pg_fir_dynamic_max_spares_exceeded_mask_clear 0xF7FF // Clear mask -#define ei4_rx_pg_fir_recal_error_mask 0x0400 //FIR mask for ei4_rx_pg_fir_recal_error. -#define ei4_rx_pg_fir_recal_error_mask_clear 0xFBFF // Clear mask -#define ei4_rx_pg_fir_recal_spare_deployed_mask 0x0200 //FIR mask for ei4_rx_pg_fir_recal_spare_deployed. -#define ei4_rx_pg_fir_recal_spare_deployed_mask_clear 0xFDFF // Clear mask -#define ei4_rx_pg_fir_recal_max_spares_exceeded_mask 0x0100 //FIR mask for ei4_rx_pg_fir_recal_max_spares_exceeded. -#define ei4_rx_pg_fir_recal_max_spares_exceeded_mask_clear 0xFEFF // Clear mask +#define ei4_rx_pg_fir_dynamic_repair_error_mask 0x1000 //FIR mask for ei4_rx_pg_fir_dynamic_repair_error +#define ei4_rx_pg_fir_dynamic_repair_error_mask_clear 0xEFFF // Clear mask +#define ei4_rx_pg_fir_dynamic_spare_deployed_mask 0x0800 //FIR mask for ei4_rx_pg_fir_dynamic_spare_deployed. +#define ei4_rx_pg_fir_dynamic_spare_deployed_mask_clear 0xF7FF // Clear mask +#define ei4_rx_pg_fir_dynamic_max_spares_exceeded_mask 0x0400 //FIR mask for ei4_rx_pg_fir_dynamic_max_spares_exceeded. +#define ei4_rx_pg_fir_dynamic_max_spares_exceeded_mask_clear 0xFBFF // Clear mask +#define ei4_rx_pg_fir_recal_error_mask 0x0200 //FIR mask for ei4_rx_pg_fir_recal_error. +#define ei4_rx_pg_fir_recal_error_mask_clear 0xFDFF // Clear mask +#define ei4_rx_pg_fir_recal_spare_deployed_mask 0x0100 //FIR mask for ei4_rx_pg_fir_recal_spare_deployed. +#define ei4_rx_pg_fir_recal_spare_deployed_mask_clear 0xFEFF // Clear mask +#define ei4_rx_pg_fir_recal_max_spares_exceeded_mask 0x0080 //FIR mask for ei4_rx_pg_fir_recal_max_spares_exceeded. +#define ei4_rx_pg_fir_recal_max_spares_exceeded_mask_clear 0xFF7F // Clear mask +#define ei4_rx_pg_fir_too_many_bus_errors_mask 0x0040 //FIR mask for ei4_rx_pg_fir_too_many_bus_errors. +#define ei4_rx_pg_fir_too_many_bus_errors_mask_clear 0xFFBF // Clear mask // ei4_rx_timeout_sel1_pg Register field name data value Description #define ei4_rx_eo_offset_timeout_sel_tap1 0x2000 //Selects Latch offset timeout. 128k UI or 13.6us @@ -3603,7 +4189,6 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_eo_final_l2u_timeout_sel_clear 0xFFFE // Clear mask // ei4_rx_lane_bad_vec_0_15_pg Register field name data value Description -#define ei4_rx_lane_bad_vec_0_15 0x0000 //Lanes found bad by HW (status) or method to force lane bad from software (control). #define ei4_rx_lane_bad_vec_0_15_clear 0x0000 // Clear mask // ei4_rx_lane_bad_vec_16_31_pg Register field name data value Description @@ -3715,10 +4300,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_fence_clear 0x7FFF // Clear mask // ei4_rx_term_pg Register field name data value Description -#define ei4_rx_term_p_mode_enc 0x0000 //Slice enable for 240ohm pfet for termination mode (binary code - 0000 is zero slices and 1000 is maximum slices) -#define ei4_rx_term_p_mode_enc_clear 0xF0FF // Clear mask -#define ei4_rx_term_test_mode 0x0080 //Termination Segment Test mode -#define ei4_rx_term_test_mode_clear 0xFF7F // Clear mask +#define ei4_rx_term_test_mode 0x8000 //Termination Segment Test mode +#define ei4_rx_term_test_mode_clear 0x7FFF // Clear mask +#define ei4_rx_term_mode_enc 0x0000 //Slice enable for pfet/nfet pairs for termination mode. Bits 0:3 determine how many 240ohm pairs to enable, out of 14. Bit 4 enables a half-strength 480ohm pfet/nfet pair, and also controls whether that pair is enabled in test mode. +#define ei4_rx_term_mode_enc_clear 0xE0FF // Clear mask // ei4_rx_timeout_sel2_pg Register field name data value Description #define ei4_rx_func_mode_timeout_sel_tap1 0x2000 //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 128k UI or 13.7us @@ -3729,6 +4314,18 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_func_mode_timeout_sel_tap6 0xC000 //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 64M UI or 7ms #define ei4_rx_func_mode_timeout_sel_tap7 0xE000 //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. infinite #define ei4_rx_func_mode_timeout_sel_clear 0x1FFF // Clear mask +#define ei4_rx_rc_slowdown_timeout_sel_tap1 0x0400 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 128k UI or 13.7us +#define ei4_rx_rc_slowdown_timeout_sel_tap2 0x0800 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 256k UI or 27.3us +#define ei4_rx_rc_slowdown_timeout_sel_tap3 0x0C00 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 512k UI or 54.6us +#define ei4_rx_rc_slowdown_timeout_sel_tap4 0x1000 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 1M UI or 109.2us +#define ei4_rx_rc_slowdown_timeout_sel_tap5 0x1400 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 2M UI or 218.5us +#define ei4_rx_rc_slowdown_timeout_sel_tap6 0x1800 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. 64M UI or 7ms +#define ei4_rx_rc_slowdown_timeout_sel_tap7 0x1C00 //Selects Recal Slowdown timeout. Note that his should be longer than ei4_rx_sls_timeout_sel. infinite +#define ei4_rx_rc_slowdown_timeout_sel_clear 0xE3FF // Clear mask +#define ei4_rx_pup_lite_wait_sel_tap1 0x0100 //How long to wait for analog logic to power up an unused spare lane for recal/repair 107ns (default value +#define ei4_rx_pup_lite_wait_sel_tap2 0x0200 //How long to wait for analog logic to power up an unused spare lane for recal/repair 213ns +#define ei4_rx_pup_lite_wait_sel_tap3 0x0300 //How long to wait for analog logic to power up an unused spare lane for recal/repair 427ns +#define ei4_rx_pup_lite_wait_sel_clear 0xFCFF // Clear mask // ei4_rx_dyn_rpr_pg Register field name data value Description #define ei4_rx_dyn_rpr_state_clear 0xC0FF // Clear mask @@ -3744,19 +4341,31 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_dyn_rpr_complete_gcrmsg 0x0040 //GCR Message: CRC/ECC Bad Lane Repaired #define ei4_rx_dyn_rpr_complete_gcrmsg_clear 0xFFBF // Clear mask -// ei4_rx_dyn_rpr_err_tallying_pg Register field name data value Description +// ei4_rx_dyn_rpr_err_tallying1_pg Register field name data value Description #define ei4_rx_dyn_rpr_bad_lane_max 0x0000 //CRC/ECC Dynamic Repair: Max number of times a lane can be found bad before repaired -#define ei4_rx_dyn_rpr_bad_lane_max_clear 0x07FF // Clear mask -#define ei4_rx_dyn_rpr_err_cntr_duration_tap1 0x0100 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 106.6ns -#define ei4_rx_dyn_rpr_err_cntr_duration_tap2 0x0200 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 1.7uS -#define ei4_rx_dyn_rpr_err_cntr_duration_tap3 0x0300 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 27.3uS -#define ei4_rx_dyn_rpr_err_cntr_duration_tap4 0x0400 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 436.7uS -#define ei4_rx_dyn_rpr_err_cntr_duration_tap5 0x0500 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 7.0mS -#define ei4_rx_dyn_rpr_err_cntr_duration_tap6 0x0600 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 111.8mS -#define ei4_rx_dyn_rpr_err_cntr_duration_tap7 0x0700 //CRC/ECC Dynamic Repair: Duration the error counter can run before being cleared (determines the allowed error frequency) 1.8S -#define ei4_rx_dyn_rpr_err_cntr_duration_clear 0xF8FF // Clear mask -#define ei4_rx_dyn_rpr_clr_err_cntr 0x0080 //CRC/ECC Dynamic Repair: Firmware-based clear of error counter register -#define ei4_rx_dyn_rpr_clr_err_cntr_clear 0xFF7F // Clear mask +#define ei4_rx_dyn_rpr_bad_lane_max_clear 0x01FF // Clear mask +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap1 0x0020 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 853.0ns & 1.3uS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap2 0x0040 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 27.3uS & 41.0uS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap3 0x0060 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 873.5uS & 1.3mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap4 0x0080 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 1.7mS & 2.6mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap5 0x00A0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 3.5mS & 5.1mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap6 0x00C0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 7.0mS & 10.5mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap7 0x00E0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 14.0mS & 21.0mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap8 0x0100 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 28.0mS & 41.9mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap9 0x0120 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 55.9mS & 83.9mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap10 0x0140 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 111.8mS & 167.8mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap11 0x0160 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 223.6mS & 335.5mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap12 0x0180 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 447.2mS & 671.1mS +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap13 0x01A0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 894.4mS & 1.3 S +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap14 0x01C0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) 1.8 S & 2.7 S +#define ei4_rx_dyn_rpr_err_cntr1_duration_tap15 0x01E0 //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency) infinite +#define ei4_rx_dyn_rpr_err_cntr1_duration_clear 0x3E1F // Clear mask +#define ei4_rx_dyn_rpr_clr_err_cntr1 0x0010 //CRC/ECC Dynamic Repair: Firmware-based clear of lane error counter1 register +#define ei4_rx_dyn_rpr_clr_err_cntr1_clear 0xFFEF // Clear mask +#define ei4_rx_dyn_rpr_disable 0x0008 //CRC/ECC Dynamic Repair: When set, disables dynamic repair error tallying (both per lane and per bus error counters...cntr1 & cntr2) +#define ei4_rx_dyn_rpr_disable_clear 0xFFF7 // Clear mask +#define ei4_rx_dyn_rpr_enc_bad_data_lane_width 0x0000 //CRC/ECC Dynamic Repair: Width of the enc_bad_data_lane vector used to determine number of 1s in clear code +#define ei4_rx_dyn_rpr_enc_bad_data_lane_width_clear 0xFFB8 // Clear mask // ei4_rx_eo_final_l2u_gcrmsgs_pg Register field name data value Description #define ei4_rx_eo_final_l2u_dly_seq_gcrmsg_fl2uallchg 0x4000 //GCR Message: RX Final Load to Unload Delay GCR messages Indicate all groups have calculated max load to unload change. @@ -3797,20 +4406,22 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_wt_clk_lane_bad_code_clear 0xC7FF // Clear mask // ei4_rx_wiretest_pll_cntl_pg Register field name data value Description -#define ei4_rx_wt_cu_pll_pgood 0x8000 //RX cleanup PLL Enable +#define ei4_rx_wt_cu_pll_pgood 0x8000 //RX PLL/DLL Enable #define ei4_rx_wt_cu_pll_pgood_clear 0x7FFF // Clear mask -#define ei4_rx_wt_cu_pll_reset 0x4000 //RX cleanup PLL Enable Request +#define ei4_rx_wt_cu_pll_reset 0x4000 //RX PLL/DLL Enable Request #define ei4_rx_wt_cu_pll_reset_clear 0xBFFF // Clear mask -#define ei4_rx_wt_cu_pll_pgooddly_50ns 0x0800 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Nominal 50ns Reset per PLL Spec -#define ei4_rx_wt_cu_pll_pgooddly_100ns 0x1000 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Double Nominal 50ns Reset per PLL Spec -#define ei4_rx_wt_cu_pll_pgooddly_960ui 0x1800 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Typical simulation delay exceeding TX PLL 40-refclk locking period -#define ei4_rx_wt_cu_pll_pgooddly_unused_100 0x2000 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Reserved -#define ei4_rx_wt_cu_pll_pgooddly_unused_101 0x2800 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Reserved -#define ei4_rx_wt_cu_pll_pgooddly_MAX 0x3000 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. 1024 UI -#define ei4_rx_wt_cu_pll_pgooddly_disable 0x3800 //RX cleanup PLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Disable ei4_rx_wt_cu_pll_reset +#define ei4_rx_wt_cu_pll_pgooddly_50ns 0x0800 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Nominal 50ns Reset per PLL Spec +#define ei4_rx_wt_cu_pll_pgooddly_100ns 0x1000 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Double Nominal 50ns Reset per PLL Spec +#define ei4_rx_wt_cu_pll_pgooddly_960ui 0x1800 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Typical simulation delay exceeding TX PLL 40-refclk locking period +#define ei4_rx_wt_cu_pll_pgooddly_unused_100 0x2000 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Reserved +#define ei4_rx_wt_cu_pll_pgooddly_unused_101 0x2800 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Reserved +#define ei4_rx_wt_cu_pll_pgooddly_MAX 0x3000 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. 1024 UI +#define ei4_rx_wt_cu_pll_pgooddly_disable 0x3800 //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set. Disable ei4_rx_wt_cu_pll_reset #define ei4_rx_wt_cu_pll_pgooddly_clear 0xC7FF // Clear mask -#define ei4_rx_wt_cu_pll_lock 0x0400 //RX cleanup PLL Locked +#define ei4_rx_wt_cu_pll_lock 0x0400 //RX PLL/DLL Locked #define ei4_rx_wt_cu_pll_lock_clear 0xFBFF // Clear mask +#define ei4_rx_wt_pll_refclksel 0x0200 //Select between IO clock and BIST/Refclock +#define ei4_rx_wt_pll_refclksel_clear 0xFDFF // Clear mask // ei4_rx_eo_step_cntl_pg Register field name data value Description #define ei4_rx_eo_enable_latch_offset_cal 0x8000 //RX eye optimization latch offset adjustment enable @@ -3823,6 +4434,10 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_eo_enable_measure_eye_width_clear 0xFEFF // Clear mask #define ei4_rx_eo_enable_final_l2u_adj 0x0080 //RX eye optimization Final RX FIFO load-to-unload delay adjustment enable #define ei4_rx_eo_enable_final_l2u_adj_clear 0xFF7F // Clear mask +#define ei4_rx_eo_enable_ber_test 0x0040 //RX eye optimization Bit error rate test enable +#define ei4_rx_eo_enable_ber_test_clear 0xFFBF // Clear mask +#define ei4_rx_eo_enable_result_check 0x0020 //RX eye optimization Final results check enable +#define ei4_rx_eo_enable_result_check_clear 0xFFDF // Clear mask // ei4_rx_eo_step_stat_pg Register field name data value Description #define ei4_rx_eo_latch_offset_done 0x8000 //RX eye optimization latch offset adjustment done @@ -3835,6 +4450,8 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_eo_measure_eye_width_done_clear 0xFEFF // Clear mask #define ei4_rx_eo_final_l2u_adj_done 0x0080 //RX eye optimization Final RX FIFO load-to-unload adjust done #define ei4_rx_eo_final_l2u_adj_done_clear 0xFF7F // Clear mask +#define ei4_rx_eo_result_check_done 0x0010 //RX eye optimization Eye width/heightER check done +#define ei4_rx_eo_result_check_done_clear 0xFFEF // Clear mask // ei4_rx_eo_step_fail_pg Register field name data value Description #define ei4_rx_eo_latch_offset_failed 0x8000 //RX eye optimization latch offset adjustment failed @@ -3843,43 +4460,29 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_eo_ctle_failed_clear 0xBFFF // Clear mask #define ei4_rx_eo_vref_failed 0x1000 //RX eye optimization VRef adjust failed #define ei4_rx_eo_vref_failed_clear 0xEFFF // Clear mask -#define ei4_rx_eo_measure_eye_width_failed 0x0100 //RX eye optimization Measure eye width filed +#define ei4_rx_eo_measure_eye_width_failed 0x0100 //RX eye optimization Measure eye width failed #define ei4_rx_eo_measure_eye_width_failed_clear 0xFEFF // Clear mask #define ei4_rx_eo_final_l2u_adj_failed 0x0080 //RX eye optimization Final RX FIFO load-to-unload adjust failed #define ei4_rx_eo_final_l2u_adj_failed_clear 0xFF7F // Clear mask +#define ei4_rx_eo_result_check_failed 0x0040 //RX eye optimization Final Result checking failed +#define ei4_rx_eo_result_check_failed_clear 0xFFBF // Clear mask // ei4_rx_amp_val_pg Register field name data value Description #define ei4_rx_amp_peak_work 0x0000 //Rx amp peak working register #define ei4_rx_amp_peak_work_clear 0x0FFF // Clear mask // ei4_rx_sls_rcvy_pg Register field name data value Description +#define ei4_rx_sls_rcvy_disable 0x8000 //Disable SLS Recovery +#define ei4_rx_sls_rcvy_disable_clear 0x7FFF // Clear mask #define ei4_rx_sls_rcvy_state_clear 0xE0FF // Clear mask // ei4_rx_sls_rcvy_gcrmsg_pg Register field name data value Description -#define ei4_rx_slv_shdw_done_fin_gcrmsg 0x8000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done -#define ei4_rx_slv_shdw_done_fin_gcrmsg_clear 0x7FFF // Clear mask -#define ei4_rx_slv_shdw_nop_fin_gcrmsg 0x4000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define ei4_rx_slv_shdw_nop_fin_gcrmsg_clear 0xBFFF // Clear mask -#define ei4_rx_slv_shdw_rpr_done_fin_gcrmsg 0x2000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done -#define ei4_rx_slv_shdw_rpr_done_fin_gcrmsg_clear 0xDFFF // Clear mask -#define ei4_rx_slv_shdw_rpr_nop_fin_gcrmsg 0x1000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define ei4_rx_slv_shdw_rpr_nop_fin_gcrmsg_clear 0xEFFF // Clear mask -#define ei4_rx_slv_unshdw_done_fin_gcrmsg 0x0800 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done -#define ei4_rx_slv_unshdw_done_fin_gcrmsg_clear 0xF7FF // Clear mask -#define ei4_rx_slv_unshdw_nop_fin_gcrmsg 0x0400 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define ei4_rx_slv_unshdw_nop_fin_gcrmsg_clear 0xFBFF // Clear mask -#define ei4_rx_slv_unshdw_rpr_done_fin_gcrmsg 0x0200 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done -#define ei4_rx_slv_unshdw_rpr_done_fin_gcrmsg_clear 0xFDFF // Clear mask -#define ei4_rx_slv_unshdw_rpr_nop_fin_gcrmsg 0x0100 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop -#define ei4_rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear 0xFEFF // Clear mask -#define ei4_rx_slv_recal_done_nop_fin_gcrmsg 0x0080 //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop -#define ei4_rx_slv_recal_done_nop_fin_gcrmsg_clear 0xFF7F // Clear mask -#define ei4_rx_slv_recal_fail_nop_fin_gcrmsg 0x0040 //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop -#define ei4_rx_slv_recal_fail_nop_fin_gcrmsg_clear 0xFFBF // Clear mask -#define ei4_rx_sls_rcvy_ei4_rx_ip_gcrmsg 0x0020 //GCR Message: SLS Rcvy; RX Lane Repair IP -#define ei4_rx_sls_rcvy_ei4_rx_ip_gcrmsg_clear 0xFFDF // Clear mask -#define ei4_rx_sls_rcvy_ei4_rx_rpred_gcrmsg 0x0010 //GCR Message: SLS Rcvy; RX Lane Repair Done -#define ei4_rx_sls_rcvy_ei4_rx_rpred_gcrmsg_clear 0xFFEF // Clear mask +#define ei4_rx_sls_rcvy_req_gcrmsg 0x8000 //GCR Message: SLS Rcvy; RX Lane Repair Req +#define ei4_rx_sls_rcvy_req_gcrmsg_clear 0x7FFF // Clear mask +#define ei4_rx_sls_rcvy_ip_gcrmsg 0x4000 //GCR Message: SLS Rcvy; RX Lane Repair IP +#define ei4_rx_sls_rcvy_ip_gcrmsg_clear 0xBFFF // Clear mask +#define ei4_rx_sls_rcvy_done_gcrmsg 0x2000 //GCR Message: SLS Rcvy; RX Lane Repair Done +#define ei4_rx_sls_rcvy_done_gcrmsg_clear 0xDFFF // Clear mask // ei4_rx_ei4_tx_lane_info_gcrmsg_pg Register field name data value Description #define ei4_rx_ei4_tx_bad_lane_cntr_gcrmsg 0x0000 //GCR Message: RX Side TX Bad Lane Counter @@ -3894,12 +4497,12 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_trc_mode_tap2 0x2000 //RX Trace Mode SLS Handshake State Machines with Recovery #define ei4_rx_trc_mode_tap3 0x3000 //RX Trace Mode Dynamic Recal State Machines #define ei4_rx_trc_mode_tap4 0x4000 //RX Trace Mode Recal Handshake State Machine with Recovery -#define ei4_rx_trc_mode_tap5 0x5000 //RX Trace Mode CRC/ECC Tallying Logic +#define ei4_rx_trc_mode_tap5 0x5000 //RX Trace Mode CRC or ECC Tallying Logic #define ei4_rx_trc_mode_tap6 0x6000 //RX Trace Mode RX SLS Commands #define ei4_rx_trc_mode_tap7 0x7000 //RX Trace Mode RX Bad Lanes #define ei4_rx_trc_mode_tap8 0x8000 //RX Trace Mode RX SLS Lanes -#define ei4_rx_trc_mode_tap9 0x9000 //RX Trace Mode TBD -#define ei4_rx_trc_mode_tap10 0xA000 //RX Trace Mode TBD +#define ei4_rx_trc_mode_tap9 0x9000 //RX Trace Mode GCR +#define ei4_rx_trc_mode_tap10 0xA000 //RX Trace Mode Per Lane / Per Pack Trace (see ei4_rx_pp_trc_mode for details #define ei4_rx_trc_mode_tap11 0xB000 //RX Trace Mode TBD #define ei4_rx_trc_mode_tap12 0xC000 //RX Trace Mode TBD #define ei4_rx_trc_mode_tap13 0xD000 //RX Trace Mode TBD @@ -3908,13 +4511,109 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_trc_mode_clear 0x0FFF // Clear mask #define ei4_rx_trc_grp_clear 0xFC0F // Clear mask +// ei4_rx_rdt_cntl_pg Register field name data value Description +#define ei4_rx_run_rdt 0x8000 //RCV RDT pattern 0:(0) RDT off +#define ei4_rx_run_rdt_clear 0x7FFF // Clear mask +#define ei4_rx_rdt_check_mask 0x0000 //RCV RDT bit mask: 11111 checks all bits, otherwise only check the bit specified +#define ei4_rx_rdt_check_mask_clear 0xC1FF // Clear mask +#define ei4_rx_rdt_failed 0x0100 //RCV RDT FAILED +#define ei4_rx_rdt_failed_clear 0xFEFF // Clear mask + +// ei4_rx_rc_step_cntl_pg Register field name data value Description +#define ei4_rx_rc_enable_edge_track 0x1000 //RX recalibration Eye tracking +#define ei4_rx_rc_enable_edge_track_clear 0xEFFF // Clear mask +#define ei4_rx_rc_enable_measure_eye_width 0x0100 //RX recalibration Eye width check enable +#define ei4_rx_rc_enable_measure_eye_width_clear 0xFEFF // Clear mask +#define ei4_rx_rc_enable_result_check 0x0040 //RX recalibration Final results check enable +#define ei4_rx_rc_enable_result_check_clear 0xFFBF // Clear mask +#define ei4_rx_rc_enable_dll_update 0x0020 //RX recalibration DLL update enable +#define ei4_rx_rc_enable_dll_update_clear 0xFFDF // Clear mask + +// ei4_rx_eo_recal_pg Register field name data value Description +#define ei4_rx_eye_opt_state 0x0000 //Common EDI/EI4 Eye optimizaton State Machine +#define ei4_rx_eye_opt_state_clear 0x00FF // Clear mask +#define ei4_rx_recal_state 0x0000 //Common EDI/EI4 recalibration State Machine +#define ei4_rx_recal_state_clear 0xFF00 // Clear mask + +// ei4_rx_servo_ber_count_pg Register field name data value Description +#define ei4_rx_servo_ber_count_work 0x0000 //Rx servo-based bit error rate count working register +#define ei4_rx_servo_ber_count_work_clear 0x000F // Clear mask + +// ei4_rx_func_state_pg Register field name data value Description +#define ei4_rx_func_mode_state 0x0000 //Functional Mode State Machine(RJR): +#define ei4_rx_func_mode_state_clear 0x0FFF // Clear mask + +// ei4_rx_dyn_rpr_debug_pg Register field name data value Description +#define ei4_rx_dyn_rpr_enc_bad_data_lane_debug 0x0000 //For testfloor/debug purposes, specify the encoded bad data lane to report to the dynamic repair tally logic +#define ei4_rx_dyn_rpr_enc_bad_data_lane_debug_clear 0x01FF // Clear mask +#define ei4_rx_dyn_rpr_bad_lane_valid_debug 0x0080 //For testfloor/debug purposes, the specified encoded bad data lane will be tallied as having one cycle of a valid CRC/ECC error (this is a write-only pulse register) +#define ei4_rx_dyn_rpr_bad_lane_valid_debug_clear 0xFF7F // Clear mask + +// ei4_rx_dyn_rpr_err_tallying2_pg Register field name data value Description +#define ei4_rx_dyn_rpr_bad_bus_max 0x0000 //CRC/ECC Dynamic Repair: Max number of times CRC or ECC errors can be found on the bus (not included in the bad lane cntr1 tally) before setting a FIR error +#define ei4_rx_dyn_rpr_bad_bus_max_clear 0x01FF // Clear mask +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap1 0x0020 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 853.0ns & 1.3uS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap2 0x0040 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 27.3uS & 41.0uS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap3 0x0060 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 873.5uS & 1.3mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap4 0x0080 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 1.7mS & 2.6mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap5 0x00A0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 3.5mS & 5.1mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap6 0x00C0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 7.0mS & 10.5mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap7 0x00E0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 14.0mS & 21.0mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap8 0x0100 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 28.0mS & 41.9mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap9 0x0120 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 55.9mS & 83.9mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap10 0x0140 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 111.8mS & 167.8mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap11 0x0160 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 223.6mS & 335.5mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap12 0x0180 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 447.2mS & 671.1mS +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap13 0x01A0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 894.4mS & 1.3 S +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap14 0x01C0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) 1.8 S & 2.7 S +#define ei4_rx_dyn_rpr_err_cntr2_duration_tap15 0x01E0 //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency) infinite +#define ei4_rx_dyn_rpr_err_cntr2_duration_clear 0x3E1F // Clear mask +#define ei4_rx_dyn_rpr_clr_err_cntr2 0x0010 //CRC/ECC Dynamic Repair: Firmware-based clear of bus error counter2 register +#define ei4_rx_dyn_rpr_clr_err_cntr2_clear 0xFFEF // Clear mask + +// ei4_rx_result_chk_pg Register field name data value Description +#define ei4_rx_min_eye_width 0x0000 //Minimum acceptable eye width used during init or recal results checking--EDI or EI4 +#define ei4_rx_min_eye_width_clear 0xC0FF // Clear mask + +// ei4_rx_sls_rcvy_fin_gcrmsg_pg Register field name data value Description +#define ei4_rx_slv_shdw_done_fin_gcrmsg 0x8000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done +#define ei4_rx_slv_shdw_done_fin_gcrmsg_clear 0x7FFF // Clear mask +#define ei4_rx_slv_shdw_nop_fin_gcrmsg 0x4000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define ei4_rx_slv_shdw_nop_fin_gcrmsg_clear 0xBFFF // Clear mask +#define ei4_rx_slv_shdw_rpr_done_fin_gcrmsg 0x2000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done +#define ei4_rx_slv_shdw_rpr_done_fin_gcrmsg_clear 0xDFFF // Clear mask +#define ei4_rx_slv_shdw_rpr_nop_fin_gcrmsg 0x1000 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define ei4_rx_slv_shdw_rpr_nop_fin_gcrmsg_clear 0xEFFF // Clear mask +#define ei4_rx_slv_unshdw_done_fin_gcrmsg 0x0800 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done +#define ei4_rx_slv_unshdw_done_fin_gcrmsg_clear 0xF7FF // Clear mask +#define ei4_rx_slv_unshdw_nop_fin_gcrmsg 0x0400 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define ei4_rx_slv_unshdw_nop_fin_gcrmsg_clear 0xFBFF // Clear mask +#define ei4_rx_slv_unshdw_rpr_done_fin_gcrmsg 0x0200 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done +#define ei4_rx_slv_unshdw_rpr_done_fin_gcrmsg_clear 0xFDFF // Clear mask +#define ei4_rx_slv_unshdw_rpr_nop_fin_gcrmsg 0x0100 //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop +#define ei4_rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear 0xFEFF // Clear mask +#define ei4_rx_slv_recal_done_nop_fin_gcrmsg 0x0080 //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop +#define ei4_rx_slv_recal_done_nop_fin_gcrmsg_clear 0xFF7F // Clear mask +#define ei4_rx_slv_recal_fail_nop_fin_gcrmsg 0x0040 //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop +#define ei4_rx_slv_recal_fail_nop_fin_gcrmsg_clear 0xFFBF // Clear mask +#define ei4_rx_slv_recal_presults_fin_gcrmsg 0x0020 //GCR Message: Slave Recal Pass Results; Need to finish slave recal handshake starting with waiting for results +#define ei4_rx_slv_recal_presults_fin_gcrmsg_clear 0xFFDF // Clear mask +#define ei4_rx_slv_recal_fresults_fin_gcrmsg 0x0010 //GCR Message: Slave Recal Fail Results; Need to finish slave recal handshake starting with waiting for results +#define ei4_rx_slv_recal_fresults_fin_gcrmsg_clear 0xFFEF // Clear mask +#define ei4_rx_slv_recal_abort_ack_fin_gcrmsg 0x0008 //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop +#define ei4_rx_slv_recal_abort_ack_fin_gcrmsg_clear 0xFFF7 // Clear mask +#define ei4_rx_slv_recal_abort_mnop_fin_gcrmsg 0x0004 //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop +#define ei4_rx_slv_recal_abort_mnop_fin_gcrmsg_clear 0xFFFB // Clear mask +#define ei4_rx_slv_recal_abort_snop_fin_gcrmsg 0x0002 //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop +#define ei4_rx_slv_recal_abort_snop_fin_gcrmsg_clear 0xFFFD // Clear mask + // ei4_rx_wiretest_pp Register field name data value Description #define ei4_rx_wt_pattern_length_256 0x4000 //RX Wiretest Pattern Length 256 #define ei4_rx_wt_pattern_length_512 0x8000 //RX Wiretest Pattern Length 512 #define ei4_rx_wt_pattern_length_1024 0xC000 //RX Wiretest Pattern Length 1024 #define ei4_rx_wt_pattern_length_clear 0x3FFF // Clear mask -// ei4_rx_mode_pp Register field name data value Description +// ei4_rx_mode1_pp Register field name data value Description #define ei4_rx_reduced_scramble_mode_disable_1 0x4000 //Sets reduced density of scramble pattern. Disable reduced density #define ei4_rx_reduced_scramble_mode_enable_div2 0x8000 //Sets reduced density of scramble pattern. Enable Div2 Reduced Density #define ei4_rx_reduced_scramble_mode_enable_div4 0xC000 //Sets reduced density of scramble pattern. Enable Div4 Reduced Density @@ -3943,6 +4642,8 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_bit_lock_timeout_sel_16384ui 0x00C0 //Sets bit lock/edge detect timeout value. 16384 UI #define ei4_rx_bit_lock_timeout_sel_infinite 0x00E0 //Sets bit lock/edge detect timeout value. Infinite #define ei4_rx_bit_lock_timeout_sel_clear 0x1F1F // Clear mask +#define ei4_rx_reverse_shift 0x0002 //RX Phase Rotator Direction +#define ei4_rx_reverse_shift_clear 0xFFFD // Clear mask #define ei4_rx_ei3_mode 0x0001 //EI3 mode - See also ei4_tx_ei3_mode #define ei4_rx_ei3_mode_clear 0xFFFE // Clear mask @@ -4000,6 +4701,14 @@ const char* const ei4_GCR_sub_reg_names[] = { #define ei4_rx_cal_dec_val_H 0x0000 //RX Servo Accum Dec Value H #define ei4_rx_cal_dec_val_H_clear 0xF0F0 // Clear mask +// ei4_rx_mode2_pp Register field name data value Description +#define ei4_rx_bist_jitter_pulse_ctl_0 0x4000 //Jitter Select (steps8 +#define ei4_rx_bist_jitter_pulse_ctl_1 0x8000 //Jitter Select (steps2 +#define ei4_rx_bist_jitter_pulse_ctl_2 0xC000 //Jitter Select (steps0 +#define ei4_rx_bist_jitter_pulse_ctl_clear 0x3FFF // Clear mask +#define ei4_rx_bist_min_eye_width 0x0000 //Sets the minimum eye width value considered acceptable by PHYBIST. +#define ei4_rx_bist_min_eye_width_clear 0xC07F // Clear mask + // ei4_rx_ber_cntl_pp Register field name data value Description #define ei4_rx_ber_en 0x8000 //Per-Pack (PP) Diagnostic Bit Error Rate (BER) error checking enable control. When 1 enables error checking. When 0 the error checking is disabled. This control enables the BER timer as well as enables the error checker and BER counters. The assumption is that the driver(s) are currently driving PRBS23 and the link has been trained before enabling BER checking. #define ei4_rx_ber_en_clear 0x7FFF // Clear mask @@ -4169,5 +4878,98 @@ const char* const ei4_GCR_sub_reg_names[] = { // ei4_rx_reset_cfg_pp Register field name data value Description #define ei4_rx_reset_cfg_hld_clear 0x0000 // Clear mask +// ei4_rx_recal_to1_pp Register field name data value Description +#define ei4_rx_recal_timeout_sel_A_512ui 0x1000 //RX recal servo operation timeout A. 512 UI +#define ei4_rx_recal_timeout_sel_A_1Kui 0x2000 //RX recal servo operation timeout A. 1K UI +#define ei4_rx_recal_timeout_sel_A_2Kui 0x3000 //RX recal servo operation timeout A. 2K UI +#define ei4_rx_recal_timeout_sel_A_4Kui 0x4000 //RX recal servo operation timeout A. 4096 UI +#define ei4_rx_recal_timeout_sel_A_8Kui 0x5000 //RX recal servo operation timeout A. 8K UI +#define ei4_rx_recal_timeout_sel_A_16Kui 0x6000 //RX recal servo operation timeout A. 16K UI +#define ei4_rx_recal_timeout_sel_A_32Kui 0x7000 //RX recal servo operation timeout A. 32K UI +#define ei4_rx_recal_timeout_sel_A_64Kui 0x8000 //RX recal servo operation timeout A. 64K UI +#define ei4_rx_recal_timeout_sel_A_128Kui 0x9000 //RX recal servo operation timeout A. 128K UI +#define ei4_rx_recal_timeout_sel_A_256Kui 0xA000 //RX recal servo operation timeout A. 256K UI +#define ei4_rx_recal_timeout_sel_A_512Kui 0xB000 //RX recal servo operation timeout A. 512K UI +#define ei4_rx_recal_timeout_sel_A_1Mui 0xC000 //RX recal servo operation timeout A. 1M UI +#define ei4_rx_recal_timeout_sel_A_2Mui 0xD000 //RX recal servo operation timeout A. 2M UI +#define ei4_rx_recal_timeout_sel_A_4Mui 0xE000 //RX recal servo operation timeout A. 4M UI +#define ei4_rx_recal_timeout_sel_A_Infinite 0xF000 //RX recal servo operation timeout A. Infinite +#define ei4_rx_recal_timeout_sel_A_clear 0x0FFF // Clear mask + +// ei4_rx_recal_to2_pp Register field name data value Description +#define ei4_rx_recal_timeout_sel_E_512ui 0x1000 //RX recal servo operation timeout E. 512 UI +#define ei4_rx_recal_timeout_sel_E_1Kui 0x2000 //RX recal servo operation timeout E. 1K UI +#define ei4_rx_recal_timeout_sel_E_2Kui 0x3000 //RX recal servo operation timeout E. 2K UI +#define ei4_rx_recal_timeout_sel_E_4Kui 0x4000 //RX recal servo operation timeout E. 4096 UI +#define ei4_rx_recal_timeout_sel_E_8Kui 0x5000 //RX recal servo operation timeout E. 8K UI +#define ei4_rx_recal_timeout_sel_E_16Kui 0x6000 //RX recal servo operation timeout E. 16K UI +#define ei4_rx_recal_timeout_sel_E_32Kui 0x7000 //RX recal servo operation timeout E. 32K UI +#define ei4_rx_recal_timeout_sel_E_64Kui 0x8000 //RX recal servo operation timeout E. 64K UI +#define ei4_rx_recal_timeout_sel_E_128Kui 0x9000 //RX recal servo operation timeout E. 128K UI +#define ei4_rx_recal_timeout_sel_E_256Kui 0xA000 //RX recal servo operation timeout E. 256K UI +#define ei4_rx_recal_timeout_sel_E_512Kui 0xB000 //RX recal servo operation timeout E. 512K UI +#define ei4_rx_recal_timeout_sel_E_1Mui 0xC000 //RX recal servo operation timeout E. 1M UI +#define ei4_rx_recal_timeout_sel_E_2Mui 0xD000 //RX recal servo operation timeout E. 2M UI +#define ei4_rx_recal_timeout_sel_E_4Mui 0xE000 //RX recal servo operation timeout E. 4M UI +#define ei4_rx_recal_timeout_sel_E_Infinite 0xF000 //RX recal servo operation timeout E. Infinite +#define ei4_rx_recal_timeout_sel_E_clear 0x0FFF // Clear mask +#define ei4_rx_recal_timeout_sel_F_512ui 0x0100 //RX recal servo operation timeout F. 512 UI +#define ei4_rx_recal_timeout_sel_F_1Kui 0x0200 //RX recal servo operation timeout F. 1K UI +#define ei4_rx_recal_timeout_sel_F_2Kui 0x0300 //RX recal servo operation timeout F. 2K UI +#define ei4_rx_recal_timeout_sel_F_4Kui 0x0400 //RX recal servo operation timeout F. 4096 UI +#define ei4_rx_recal_timeout_sel_F_8Kui 0x0500 //RX recal servo operation timeout F. 8K UI +#define ei4_rx_recal_timeout_sel_F_16Kui 0x0600 //RX recal servo operation timeout F. 16K UI +#define ei4_rx_recal_timeout_sel_F_32Kui 0x0700 //RX recal servo operation timeout F. 32K UI +#define ei4_rx_recal_timeout_sel_F_64Kui 0x0800 //RX recal servo operation timeout F. 64K UI +#define ei4_rx_recal_timeout_sel_F_128Kui 0x0900 //RX recal servo operation timeout F. 128K UI +#define ei4_rx_recal_timeout_sel_F_256Kui 0x0A00 //RX recal servo operation timeout F. 256K UI +#define ei4_rx_recal_timeout_sel_F_512Kui 0x0B00 //RX recal servo operation timeout F. 512K UI +#define ei4_rx_recal_timeout_sel_F_1Mui 0x0C00 //RX recal servo operation timeout F. 1M UI +#define ei4_rx_recal_timeout_sel_F_2Mui 0x0D00 //RX recal servo operation timeout F. 2M UI +#define ei4_rx_recal_timeout_sel_F_4Mui 0x0E00 //RX recal servo operation timeout F. 4M UI +#define ei4_rx_recal_timeout_sel_F_Infinite 0x0F00 //RX recal servo operation timeout F. Infinite +#define ei4_rx_recal_timeout_sel_F_clear 0xF0FF // Clear mask + +// ei4_rx_recal_cntl_pp Register field name data value Description +#define ei4_rx_recal_in_progress 0x8000 //Selects which servo timeouts are used. +#define ei4_rx_recal_in_progress_clear 0x7FFF // Clear mask + +// ei4_rx_trace_pp Register field name data value Description +#define ei4_rx_pp_trc_mode_tap1 0x2000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_tap2 0x4000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_tap3 0x6000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_tap4 0x8000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_tap5 0xA000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_tap6 0xC000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_tap7 0xE000 //Per Pack RX Trace Mode TBD +#define ei4_rx_pp_trc_mode_clear 0x1FFF // Clear mask + +// ei4_rx_bist_gcrmsg_pp Register field name data value Description +#define ei4_rx_bist_en 0x8000 //TBD +#define ei4_rx_bist_en_clear 0x7FFF // Clear mask + +// ei4_rx_fir_reset_pb Register field name data value Description +#define ei4_rx_pb_clr_par_errs 0x0002 //Clear All RX Parity Error Latches +#define ei4_rx_pb_clr_par_errs_clear 0xFFFD // Clear mask +#define ei4_rx_pb_fir_reset 0x0001 //FIR Reset +#define ei4_rx_pb_fir_reset_clear 0xFFFE // Clear mask + +// ei4_rx_fir_pb Register field name data value Description +#define ei4_rx_pb_fir_errs_err_busctl_gcrs_ld_sm 0x0400 //A Per-Bus BUSCTL Register or State Machine Parity Error has occurred. BUSCTL GCR Load SM Parity Error. +#define ei4_rx_pb_fir_errs_clear 0x003F // Clear mask + +// ei4_rx_fir_mask_pb Register field name data value Description +#define ei4_rx_pb_fir_errs_mask_err_busctl_gcrs_ld_sm 0x0400 //FIR mask for register or state machine parity checkers in per-bus BUSCTL logic. A value of 1 masks the error from generating a FIR error. BUSCTL GCR Load SM Parity Error. +#define ei4_rx_pb_fir_errs_mask_clear 0x003F // Clear mask + +// ei4_rx_fir_error_inject_pb Register field name data value Description +#define ei4_rx_pb_fir_errs_inj_1 0x4000 //RX Per-Group Parity Error Injection Causes a parity flip in the specific parity checker. +#define ei4_rx_pb_fir_errs_inj_err_inj_busctl_gcrs_ld_sm 0x0400 //RX Per-Group Parity Error Injection BUSCTL GCR Load SM Parity Error Inject. +#define ei4_rx_pb_fir_errs_inj_clear 0x003F // Clear mask + + + + #endif + diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C index d67d4dea1..3b5c01e27 100644 --- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C +++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C @@ -21,229 +21,237 @@ * * IBM_PROLOG_END_TAG */ -// *!*************************************************************************** -// *! (C) Copyright International Business Machines Corp. 1997, 1998 -// *! All Rights Reserved -- Property of IBM -// *! *** IBM Confidential *** -// *!*************************************************************************** -// *! FILENAME : gcr_funcs.C -// *! TITLE : -// *! DESCRIPTION : -// *! CONTEXT : -// *! -// *! OWNER NAME : Varghese, Varkey Email: varkeykv@in.ibm.com -// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com -// *! -// *!*************************************************************************** -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:|Author: | Date: | Comment: -// --------|--------|--------|-------------------------------------------------- -// 1.0 |varkeykv|01/19/12| Initial check in to solve hostboot linker -//------------------------------------------------------------------------------ -#include "gcr_funcs.H" -using namespace fapi; -ReturnCode GCR_read(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase &databuf_16bit) -{ - ReturnCode rc; - uint32_t rc_ecmd=0; - ecmdDataBufferBase set_bits(16), clear_bits(16); - rc_ecmd|=set_bits.flushTo0(); - rc_ecmd|=clear_bits.flushTo1(); - - if(rc_ecmd){ - FAPI_ERR("Unexpected error in buffer manipulation\n"); - rc.setEcmdError(rc_ecmd); - } - else{ - rc=doGCRop(chip_target, interface, gcr_op_read, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit); - if(!rc.ok()) - { - FAPI_ERR("Unexpected error while performing GCR OP \n"); - } - } - - return rc; -} -//------------------------------------------------------------------------------------------------------------------------------------ -// GCR SCOM WRITE - main api for write - do not use doGCRop directly -//------------------------------------------------------------------------------------------------------------------------------------ -ReturnCode GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, int skipCheck) -{ - ReturnCode rc; - uint32_t rc_ecmd=0; - ecmdDataBufferBase databuf_16bit(16); - rc_ecmd|=databuf_16bit.flushTo0(); - if(rc_ecmd){ - FAPI_ERR("Unexpected error in buffer manipulation\n"); - rc.setEcmdError(rc_ecmd); - } - else{ - rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck); - if(!rc.ok()) - { - FAPI_ERR("Unexpected error while performing GCR OP \n"); - } - } - return rc; -} - -// UPPER LAYER FUNCTIONS - -//------------------------------------------------------------------------------------------------------------------------------------ -// generate the 64 bit scom address for the GCR -//------------------------------------------------------------------------------------------------------------------------------------ -uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) { - uint32_t rc_ecmd=0; - ecmdDataBufferBase reg_scom_address(64), temp(64); - temp.flushTo0(); - temp.setDoubleWord(0,gcr_data); - - // 64 bit address - rc_ecmd|= reg_scom_address.setWord(0,temp.getWord(0)); - rc_ecmd |= reg_scom_address.setWord(1,gcr_addr); - rc_ecmd |= reg_scom_address.setBit(0); - - if(rc_ecmd) - { - FAPI_ERR("io_run_training: Unexpected failure in scom_address_64bit helper func"); - } - return(reg_scom_address.getDoubleWord(0)); -} - - -// use GCR_read and GCR_write for reg access - not this function!!!! -/*************************************************************************************************************************/ -/* gcr2 is pgp mailbox format */ -/* gcr2 0 0 64 # total length */ -/* gcr2 wr 0 1 # gcr register read/write bit (read=1, write=0, opposite of gcr0) */ -/* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */ -/* gcr2 rxtx 21 1 # =1 for a tx group */ -/* gcr2 group 22 5 # does NOT include tx/rx as leading bit */ -/* gcr2 lane 27 5 # lane address */ -/* gcr2 data 48 16 # data */ -/* gcr2 readvalid 39 1 # read data valid bit */ -/*************************************************************************************************************************/ - -ReturnCode doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck) { - ReturnCode rc; - uint32_t rc_ecmd=0; - uint64_t scom_address64=0; - ecmdDataBufferBase getscom_data64(64), putscom_data64(64), local_data16(16); - rc_ecmd |=getscom_data64.flushTo0(); - rc_ecmd |=putscom_data64.flushTo0(); - rc_ecmd |=local_data16.flushTo0(); - - // Generate the gcr2_register_data putscom data - /* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */ - // align the extended address to bit (12:20) - rc_ecmd |= getscom_data64.insert( GCR_sub_reg_ext_addr[target_io_reg], 12, 9, 23 ); - - /* gcr2 group 22 5 # does NOT include tx/rx as leading bit */ - // align the group address to bit (22:26) - rc_ecmd |= getscom_data64.insert( group_address, 22, 5, 27); // does not include leading TX bit now since we are using only RX - - /* gcr2 lane 27 5 # lane address */ - // align the lane address to bit (27:31) - rc_ecmd |= getscom_data64.insert( lane_address, 27, 5, 27 ); - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); - rc.setEcmdError(rc_ecmd); - } - else - { - FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]); - scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0)); - rc = fapiGetScom( chip_target, scom_address64, getscom_data64 ); - if(!rc.ok()) - { - FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n"); - FAPI_ERR( "IO GCR FUNCS \tRead GCR %s, @ = %llX, Data = %08X%08X Failed group_address=%d\n", - GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1),group_address); - } - else - { - FAPI_DBG( "\tRead GCR2 %s: GETSCOM 0x%llX %08X%08X \n", - GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1) ); - rc_ecmd|=getscom_data64.extract( local_data16, 48, 16 ); // return data on read ops -- for 54/52 onwards - - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); - rc.setEcmdError(rc_ecmd); - } - else - { - // register write operation - if (read_or_write == gcr_op_read) { - databuf_16bit = local_data16; - } - else - { // write - // write operation - putscom_data64 = getscom_data64; - - // clear the desired bits first - databuf_16bit = databuf_16bit & clear_bits; - - // now set desired bits - databuf_16bit = databuf_16bit | set_bits; - - // data is now 64 bits and only last 16 bits are used 48:63 = 16bits # data - rc_ecmd|=putscom_data64.insert( databuf_16bit, 48, 16); //-- for model 54/52 onwards - - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred"); - rc.setEcmdError(rc_ecmd); - } - else - { - FAPI_DBG( "\tWrite GCR2 %s: PUTSCOM 0x%llX 0x%08X%08X", - GCR_sub_reg_names[target_io_reg], scom_address64, putscom_data64.getWord(0), putscom_data64.getWord(1) ); - rc = fapiPutScom( chip_target, scom_address64, putscom_data64); - if(!rc.ok()) - { - FAPI_ERR("IO gcr_funcs: PUTSCOM error occurred\n"); - } - else - { - // check the write - rc = fapiGetScom( chip_target, scom_address64, getscom_data64 ); - if(!rc.ok()){ - FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n"); - return(rc); - } - rc_ecmd=local_data16.insert(getscom_data64,0,16,48); //-- for 54/52 onwards - if(rc_ecmd) - { - FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n"); - rc.setEcmdError(rc_ecmd); - } - else{ - if ( !skipCheck ) - { //add skipCheck for tx_err_inj since self resetting -- djd 2/11/11 - if ( local_data16 != databuf_16bit ) - { - FAPI_ERR( "\t %s VALIDATE write failed: read=0x%04X write=%04X\n", - GCR_sub_reg_names[target_io_reg], local_data16.getHalfWord(0), databuf_16bit.getHalfWord(0) ); - ecmdDataBufferBase &READ_BUF=local_data16; - ecmdDataBufferBase &WRITE_BUF=databuf_16bit; - FAPI_SET_HWP_ERROR(rc, IO_GCR_WRITE_MISMATCH_RC); - } - } - - } - } - - } - } - } - - } - } - - return(rc); -} - +// *!***************************************************************************
+// *! (C) Copyright International Business Machines Corp. 1997, 1998
+// *! All Rights Reserved -- Property of IBM
+// *! *** IBM Confidential ***
+// *!***************************************************************************
+// *! FILENAME : gcr_funcs.C
+// *! TITLE :
+// *! DESCRIPTION :
+// *! CONTEXT :
+// *!
+// *! OWNER NAME : Varghese, Varkey Email: varkeykv@in.ibm.com
+// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com
+// *!
+// *!***************************************************************************
+// CHANGE HISTORY:
+//------------------------------------------------------------------------------
+// Version:|Author: | Date: | Comment:
+// --------|--------|--------|--------------------------------------------------
+// 1.0 |varkeykv|01/19/12| Initial check in to solve hostboot linker
+//------------------------------------------------------------------------------
+#include "gcr_funcs.H"
+using namespace fapi;
+ReturnCode GCR_read(const Target& chip_target, io_interface_t interface,GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase &databuf_16bit)
+{
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase set_bits(16), clear_bits(16);
+ rc_ecmd|=set_bits.flushTo0();
+ rc_ecmd|=clear_bits.flushTo1();
+
+ if(rc_ecmd){
+ FAPI_ERR("Unexpected error in buffer manipulation\n");
+ rc.setEcmdError(rc_ecmd);
+ }
+ else{
+ rc=doGCRop(chip_target, interface, gcr_op_read, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit);
+ if(!rc.ok())
+ {
+ FAPI_ERR("Unexpected error while performing GCR OP \n");
+ }
+ }
+
+ return rc;
+}
+//------------------------------------------------------------------------------------------------------------------------------------
+// GCR SCOM WRITE - main api for write - do not use doGCRop directly
+//------------------------------------------------------------------------------------------------------------------------------------
+ReturnCode GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, int skipCheck)
+{
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase databuf_16bit(16);
+ rc_ecmd|=databuf_16bit.flushTo0();
+ if(rc_ecmd){
+ FAPI_ERR("Unexpected error in buffer manipulation\n");
+ rc.setEcmdError(rc_ecmd);
+ }
+ else{
+ rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck);
+ if(!rc.ok())
+ {
+ FAPI_ERR("Unexpected error while performing GCR OP \n");
+ }
+ }
+ return rc;
+}
+
+// UPPER LAYER FUNCTIONS
+
+//------------------------------------------------------------------------------------------------------------------------------------
+// generate the 64 bit scom address for the GCR
+//------------------------------------------------------------------------------------------------------------------------------------
+uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) {
+ uint32_t rc_ecmd=0;
+ ecmdDataBufferBase reg_scom_address(64), temp(64);
+ temp.flushTo0();
+ temp.setDoubleWord(0,gcr_data);
+
+ // 64 bit address
+ rc_ecmd|= reg_scom_address.setWord(0,temp.getWord(0));
+ rc_ecmd |= reg_scom_address.setWord(1,gcr_addr);
+ rc_ecmd |= reg_scom_address.setBit(0);
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("io_run_training: Unexpected failure in scom_address_64bit helper func");
+ }
+ return(reg_scom_address.getDoubleWord(0));
+}
+
+
+// use GCR_read and GCR_write for reg access - not this function!!!!
+/*************************************************************************************************************************/
+/* gcr2 is pgp mailbox format */
+/* gcr2 0 0 64 # total length */
+/* gcr2 wr 0 1 # gcr register read/write bit (read=1, write=0, opposite of gcr0) */
+/* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */
+/* gcr2 rxtx 21 1 # =1 for a tx group */
+/* gcr2 group 22 5 # does NOT include tx/rx as leading bit */
+/* gcr2 lane 27 5 # lane address */
+/* gcr2 data 48 16 # data */
+/* gcr2 readvalid 39 1 # read data valid bit */
+/*************************************************************************************************************************/
+
+ReturnCode doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address, uint32_t lane_address, ecmdDataBufferBase set_bits, ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck) {
+ ReturnCode rc;
+ uint32_t rc_ecmd=0;
+ uint64_t scom_address64=0;
+ ecmdDataBufferBase getscom_data64(64), putscom_data64(64), local_data16(16);
+ rc_ecmd |=getscom_data64.flushTo0();
+ rc_ecmd |=putscom_data64.flushTo0();
+ rc_ecmd |=local_data16.flushTo0();
+
+ // Generate the gcr2_register_data putscom data
+ /* gcr2 reg_addr 12 9 # gcr ring (register) address (ext_addr) */
+ // align the extended address to bit (12:20)
+ rc_ecmd |= getscom_data64.insert( GCR_sub_reg_ext_addr[target_io_reg], 12, 9, 23 );
+ FAPI_DBG("Register Extended address = %x\n",GCR_sub_reg_ext_addr[target_io_reg]);
+
+ const char *temp;
+ temp=GCR_sub_reg_names[target_io_reg];
+ if(temp[0] == 'T' )
+ {
+ // This is a TX register/field need to set the TX bit
+ rc_ecmd |= getscom_data64.setBit( 21 ); // does not include leading TX bit now since we are using only RX
+ }
+ /* gcr2 group 22 5 # does NOT include tx/rx as leading bit */
+ // align the group address to bit (22:26)
+ rc_ecmd |= getscom_data64.insert( group_address, 22, 5, 27); // does not include leading TX bit now since we are using only RX
+
+ /* gcr2 lane 27 5 # lane address */
+ // align the lane address to bit (27:31)
+ rc_ecmd |= getscom_data64.insert( lane_address, 27, 5, 27 );
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
+ rc.setEcmdError(rc_ecmd);
+ }
+ else
+ {
+ FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]);
+ scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0));
+ rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );
+ if(!rc.ok())
+ {
+ FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n");
+ FAPI_ERR( "IO GCR FUNCS \tRead GCR %s, @ = %llX, Data = %08X%08X Failed group_address=%d\n",
+ GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1),group_address);
+
+ }
+ else
+ {
+ FAPI_DBG( "\tRead GCR2 %s: GETSCOM 0x%llX %08X%08X \n",
+ GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1) );
+ rc_ecmd|=getscom_data64.extract( local_data16, 48, 16 ); // return data on read ops -- for 54/52 onwards
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
+ rc.setEcmdError(rc_ecmd);
+ }
+ else
+ {
+ // register write operation
+ if (read_or_write == gcr_op_read) {
+ databuf_16bit = local_data16;
+ }
+ else
+ { // write
+ // write operation
+ putscom_data64 = getscom_data64;
+
+ // clear the desired bits first
+ databuf_16bit = databuf_16bit & clear_bits;
+
+ // now set desired bits
+ databuf_16bit = databuf_16bit | set_bits;
+
+ // data is now 64 bits and only last 16 bits are used 48:63 = 16bits # data
+ rc_ecmd|=putscom_data64.insert( databuf_16bit, 48, 16); //-- for model 54/52 onwards
+
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred");
+ rc.setEcmdError(rc_ecmd);
+ }
+ else
+ {
+ FAPI_DBG( "\tWrite GCR2 %s: PUTSCOM 0x%llX 0x%08X%08X",
+ GCR_sub_reg_names[target_io_reg], scom_address64, putscom_data64.getWord(0), putscom_data64.getWord(1) );
+ rc = fapiPutScom( chip_target, scom_address64, putscom_data64);
+ if(!rc.ok())
+ {
+ FAPI_ERR("IO gcr_funcs: PUTSCOM error occurred\n");
+ }
+ else
+ {
+ // check the write
+ rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );
+ if(!rc.ok()){
+ FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n");
+ return(rc);
+ }
+ rc_ecmd=local_data16.insert(getscom_data64,0,16,48); //-- for 54/52 onwards
+ if(rc_ecmd)
+ {
+ FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
+ rc.setEcmdError(rc_ecmd);
+ }
+ else{
+ if ( !skipCheck )
+ { //add skipCheck for tx_err_inj since self resetting -- djd 2/11/11
+ if ( local_data16 != databuf_16bit )
+ {
+ FAPI_ERR( "\t %s VALIDATE write failed: read=0x%04X write=%04X\n",
+ GCR_sub_reg_names[target_io_reg], local_data16.getHalfWord(0), databuf_16bit.getHalfWord(0) );
+ ecmdDataBufferBase &READ_BUF=local_data16;
+ ecmdDataBufferBase &WRITE_BUF=databuf_16bit;
+ FAPI_SET_HWP_ERROR(rc, IO_GCR_WRITE_MISMATCH_RC);
+ }
+ }
+
+ }
+ }
+
+ }
+ }
+ }
+ }
+ }
+
+ return(rc);
+}
+
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C index c7bc5db4e..55d79fe9c 100644 --- a/src/usr/hwpf/hwp/bus_training/io_run_training.C +++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C @@ -44,7 +44,7 @@ //------------------------------------------------------------------------------ #include <fapi.H> #include "io_run_training.H" - +#include "io_funcs.H" extern "C" { using namespace fapi; @@ -79,7 +79,7 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe if(!is_master){ //Swap master and slave targets !! FAPI_DBG("X Bus ..target swap performed"); - for(int i=0;i<4;++i){ + for(int i=0;i<5;++i){ master_group=slave_group=i; FAPI_DBG("X Bus training for group %d",i); rc=init.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group); @@ -90,7 +90,7 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe } } else{ - for(int i=0;i<4;++i){ + for(int i=0;i<5;++i){ master_group=slave_group=i; FAPI_DBG("X Bus training for group %d",i); rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group); diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C index 0d0e8be53..08c817a92 100644 --- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C +++ b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C @@ -62,15 +62,13 @@ extern "C" { using namespace fapi; -ReturnCode mss_extent_setup() -{ +ReturnCode mss_extent_setup(){ ReturnCode rc; - - if(rc) - { - FAPI_ERR("Error occured in mss_extent_setup() "); - } + if(rc){ + FAPI_ERR(" Calling Extent function Error "); + return rc; + } return rc; } diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C index 49c93e59b..d68bebeba 100644 --- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C +++ b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C @@ -21,7 +21,7 @@ * * IBM_PROLOG_END_TAG */ -// $Id: cen_mem_startclocks.C,v 1.7 2012/05/31 18:29:20 mfred Exp $ +// $Id: cen_mem_startclocks.C,v 1.9 2012/06/07 13:52:27 jmcgill Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2012 @@ -117,22 +117,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) fapi::ReturnCode rc; uint32_t rc_ecmd = 0; - ecmdDataBufferBase data; + ecmdDataBufferBase scom_data(64); + ecmdDataBufferBase cfam_data(32); FAPI_INF("********* cen_mem_startclocks start *********"); do { - rc_ecmd |= data.setBitLength(64); - if (rc_ecmd) - { - FAPI_ERR("Error 0x%x setting up ecmd data buffer bit length.", rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // // The following details are from the Common POR spreadsheet sections 20.1 and 21.1 and from the Centaur Chip Spec. // @@ -142,15 +134,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x030F0013 bit(18)=0b0 , drop fence in GP3 FAPI_DBG("Writing GP3 AND mask to clear chiplet fence (bit 18) ..."); - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP3_FENCE_EN_BIT); + rc_ecmd |= scom_data.flushTo1(); + rc_ecmd |= scom_data.clearBit(GP3_FENCE_EN_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear chiplet fence.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, data); + rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, scom_data); if (rc) { FAPI_ERR("Error writing GP3 AND mask 0x030F0013 (bit 18) to clear chiplet fence."); @@ -160,15 +152,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x030F0014 bit(28)=0b1 , enable EDRAM, just chiplets with EDRAM logic FAPI_DBG("Writing GP3 OR mask to enable EDRAM (bit 28) ..."); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(GP3_EDRAM_ENABLE_BIT); + rc_ecmd |= scom_data.flushTo0(); + rc_ecmd |= scom_data.setBit(GP3_EDRAM_ENABLE_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to enable EDRAM.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, data); + rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, scom_data); if (rc) { FAPI_ERR("Error writing GP3 OR mask 0x030F0014 (bit 28) to enable EDRAM."); @@ -183,17 +175,17 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03000004 bit(0)=0b0, bit(1)=0b0 , clear mux selects in GP0 FAPI_DBG("Writing GP0 AND mask to drop pervasive fence (bit 63) ..."); FAPI_DBG("Writing GP0 AND mask to clear mux selects (bits 0-1) ..."); - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP0_ABSTCLK_MUXSEL_BIT); - rc_ecmd |= data.clearBit(GP0_SYNCCLK_MUXSEL_BIT); - rc_ecmd |= data.clearBit(GP0_PERV_FENCE_BIT); + rc_ecmd |= scom_data.flushTo1(); + rc_ecmd |= scom_data.clearBit(GP0_ABSTCLK_MUXSEL_BIT); + rc_ecmd |= scom_data.clearBit(GP0_SYNCCLK_MUXSEL_BIT); + rc_ecmd |= scom_data.clearBit(GP0_PERV_FENCE_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to drop pervasive fence and clear mux selects.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, data); + rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); if (rc) { FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bits 0,1,63) to drop pervasive fence and clear mux selects."); @@ -203,15 +195,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03000005 bit(11)=0b1 abist_mode_dc for core chiplets (core recovery) FAPI_DBG("Writing GP0 OR mask to set abist_mode_dc (bit 11) ..."); - rc_ecmd |= data.flushTo0(); - rc_ecmd |= data.setBit(GP0_ABIST_MODE_BIT); + rc_ecmd |= scom_data.flushTo0(); + rc_ecmd |= scom_data.setBit(GP0_ABIST_MODE_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to set abist_mode_dc.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, data); + rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data); if (rc) { FAPI_ERR("Error writing GP0 OR mask 0x03000005 (bit 11) to set abist_mode_dc."); @@ -221,14 +213,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03030007 0x0000000000000000 Write CC Scan Region Reg, set all bits='0' prior clk start FAPI_DBG("Writing CC Scan Region Register to all zeros prior to clock start ..."); - rc_ecmd |= data.flushTo0(); + rc_ecmd |= scom_data.flushTo0(); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to flush Scan Region Register.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, data); + rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, scom_data); if (rc) { FAPI_ERR("Error writing CC Scan Region Register 0x03030007 to all zeros prior to clock start."); @@ -242,14 +234,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03030006 data=0x4FE0 0600 0000 0000 unicast, write CC clock region reg in MEM chiplet. start clocks FAPI_DBG("Writing CC Clock Region Register to 0x4FE0060000000000 to start array and nsl clocks ..."); - rc_ecmd |= data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_NSL_ARY); + rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_NSL_ARY); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to start array and nsl clocks.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, data); + rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data); if (rc) { FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE0060000000000 to start array and nsl clocks."); @@ -259,14 +251,14 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03030006 data=0x4FE0 0E00 0000 0000 unicast, write CC clock region reg in MEM chiplet. start clocks FAPI_DBG("Writing CC Clock Region Register to 0x4FE00E0000000000 to start sl clocks ..."); - rc_ecmd |= data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_ALL); + rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_ALL); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to start sl clocks.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, data); + rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data); if (rc) { FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE00E0000000000 to start sl clocks."); @@ -276,15 +268,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Read SCOM address 0x03030008 expect=0x0000 001F FFFF FFFF unicast, read clock status reg in MEM chiplet FAPI_DBG("Reading CC Clock Status Register to see if clocks are running ..."); - rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, data); + rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, scom_data); if ( rc ) { FAPI_ERR("Error reading CC Clock Status Register 0x03030008."); break; } - if ( data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA ) + if ( scom_data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA ) { - FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA); + FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",scom_data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA); FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_CLOCK_STATUS); break; } @@ -298,20 +290,20 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write CFAM address 0x13 bit(02)=0b1 Set MemReset Stability Control FAPI_DBG("Writing FSI GP4 register (bit2) to set MemReset Stability control ..."); - rc = fapiGetScom( i_target, CFAM_FSI_GP4_0x00001013, data); + rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); if (rc) { FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013."); break; } - rc_ecmd |= data.setBit(FSI_GP4_MEMRESET_STABILITY_BIT); + rc_ecmd |= cfam_data.setBit(FSI_GP4_MEMRESET_STABILITY_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to set MemReset Stability control.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, CFAM_FSI_GP4_0x00001013, data); + rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); if (rc) { FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 2) to set MemReset Stability control."); @@ -321,20 +313,20 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write CFAM address 0x13 bit(04)=0b1 Release D3PHY PLL Reset Control FAPI_DBG("Writing FSI GP4 register (bit4) to release D3PHY PLL Reset Control ..."); - rc = fapiGetScom( i_target, CFAM_FSI_GP4_0x00001013, data); + rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); if (rc) { FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013."); break; } - rc_ecmd |= data.setBit(FSI_GP4_DPHY_PLLRESET_BIT); + rc_ecmd |= cfam_data.setBit(FSI_GP4_DPHY_PLLRESET_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to release D3PHY PLL Reset Control.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, CFAM_FSI_GP4_0x00001013, data); + rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data); if (rc) { FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 4) to release D3PHY PLL Reset Control."); @@ -348,15 +340,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03000004 bit(3)=0b0 clear force_align in all Chiplets in GP0 FAPI_DBG("Writing GP0 AND mask to clear force_align (bit 3) ..."); - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP0_FORCE_ALIGN_BIT); + rc_ecmd |= scom_data.flushTo1(); + rc_ecmd |= scom_data.clearBit(GP0_FORCE_ALIGN_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear force_align.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, data); + rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); if (rc) { FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 3) to clear force_align."); @@ -366,15 +358,15 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) // Write SCOM address 0x03000004 bit(2)=0b0 clear flushmode_inhibit in Chiplet in GP0 FAPI_DBG("Writing GP0 AND mask to clear flushmode_inhibit (bit 2) ..."); - rc_ecmd |= data.flushTo1(); - rc_ecmd |= data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT); + rc_ecmd |= scom_data.flushTo1(); + rc_ecmd |= scom_data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT); if (rc_ecmd) { FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear flushmode_inhibit.", rc_ecmd); rc.setEcmdError(rc_ecmd); break; } - rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, data); + rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data); if (rc) { FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 2) to clear flushmode_inhibit."); @@ -401,6 +393,12 @@ fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target) This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: cen_mem_startclocks.C,v $ +Revision 1.9 2012/06/07 13:52:27 jmcgill +use independent data buffers for cfam/scom accesses + +Revision 1.8 2012/06/06 20:04:59 jmcgill +change FSI GP3/GP4/status register accesses from SCOM->CFAM + Revision 1.7 2012/05/31 18:29:20 mfred Updates for RC checking and error messages, etc. diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C index 57d7a439c..2322a5a1b 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C +++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C @@ -21,7 +21,7 @@ * * IBM_PROLOG_END_TAG */ -// $Id: mss_ddr_phy_reset.C,v 1.7 2012/05/31 18:27:54 mfred Exp $ +// $Id: mss_ddr_phy_reset.C,v 1.9 2012/07/18 16:27:39 mfred Exp $ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 @@ -72,6 +72,7 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target) uint32_t rc_ecmd = 0; uint32_t poll_count = 0; uint32_t done_polling = 0; + uint8_t is_simulation = 0; ecmdDataBufferBase i_data, j_data, k_data, l_data; @@ -581,6 +582,205 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target) } + + // Work-around required to get alignment in simulation + // Read the ATTR_IS_SIMULATION attribute + rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation); + if (rc) + { + FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION."); + break; + } + if (is_simulation) + { + FAPI_DBG("Step 11.1 (SIM ONLY): Write '8000'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n"); + rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008000ull); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register."); + break; + } + + + FAPI_DBG("Step 11.2 (SIM ONLY): Write '8080'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n"); + rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008080ull); + if (rc_ecmd) + { + FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.", rc_ecmd); + rc.setEcmdError(rc_ecmd); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register."); + break; + } + rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data); + if (rc) + { + FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register."); + break; + } + } + // // 12.Wait at least 32 memory clock cycles. @@ -621,7 +821,6 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target) - } while(0); FAPI_INF("********* mss_ddr_phy_reset complete *********"); @@ -640,6 +839,12 @@ This section is automatically updated by CVS when you check in this file. Be sure to create CVS comments when you commit so that they can be included here. $Log: mss_ddr_phy_reset.C,v $ +Revision 1.9 2012/07/18 16:27:39 mfred +Check for ATTR_IS_SIMULATION attribute instead of use compiler switch. + +Revision 1.8 2012/06/07 22:30:25 jmcgill +add sim only inits for phase rotator alignment (wrapped in SIM_ONLY ifdef for now) + Revision 1.7 2012/05/31 18:27:54 mfred Removing some config settings that are now done in config file. See Gary Van Huben note May 3, 2012 diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C index 85cbaa184..f3400b38b 100755 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C @@ -1,25 +1,26 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -27,6 +28,11 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.33 | jdsloat | 6/26/12 | Added rtt_nom rank by rank value. +// 1.32 | jdsloat | 6/11/12 | Fixed Attributes: RTT_NOM, CL, DRAM_WR within the MRS load. +// 1.31 | bellows | 5/24/12 | Removed GP Bit +// 1.30 | bellows | 5/03/12 | MODEQ reg writes (HW191966). Has GP Bit for backwards compatibility +// 1.29 | bellows | 5/03/12 | Workaround removed for (HW199042). Use new hardware or workaround.initfile after phyreset // 1.28 | bellows | 4/11/12 | fixed missing fapi:: for targets and return codes // 1.27 | bellows | 4/11/12 | Workaround for fixing up phy config reset (HW199042) // 1.26 | jdsloat | 3/20/12 | MRS bank fixe to remove reverse in ccs_inst_arry0 @@ -72,7 +78,7 @@ // Centaur function Includes //---------------------------------------------------------------------- #include <mss_funcs.H> - +#include "cen_scom_addresses.H" //---------------------------------------------------------------------- // Constants @@ -83,236 +89,10 @@ const uint8_t MRS0_BA = 0; const uint8_t MRS1_BA = 1; const uint8_t MRS2_BA = 2; const uint8_t MRS3_BA = 3; -const uint16_t GP4_REG_0x1013 = 0x1013; extern "C" { -// WORKAROUND START -// THIS NEEDS TO BE REMOVED = WORKAROUNDS FOR HARDWARE RESET PROBLEM - fapi::ReturnCode mss_putscom(fapi::Target target,uint64_t scom_address_64, uint64_t data_64) { - // Target is centaur.mba - // This procedure does a putscom to an address with constant data - ecmdDataBufferBase data_buffer_64(64); - data_buffer_64.flushTo0(); - uint32_t rc_ecmd=0; - fapi::ReturnCode rc; - - rc_ecmd=data_buffer_64.setDoubleWord(0,data_64); - if(rc_ecmd) - { - rc=rc_ecmd; - FAPI_ERR("ecmddatabuffer operation failed"); - - } - rc=fapiPutScom(target,scom_address_64,data_buffer_64); - if(!rc.ok()){ - FAPI_ERR("putscom error occurred"); - return(rc); - } - return rc; - } - - fapi::ReturnCode mss_workaround_phy_reset(fapi::Target target) { - // Target is centaur.mba - // This procedure does the series of putscoms to fix HW199042 where the phy resets the state of the config - // This only supports one config and only the known bad registers and allows calibration to pass - fapi::ReturnCode rc; - uint8_t core; - - rc=mss_putscom( target, 0x8000C0160301143FULL, 0x000000000000BF28ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800000370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800000370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800004370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800004370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800008370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800008370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000C370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000C370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800010370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800010370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800100370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800100370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800104370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800104370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800108370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800108370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010C370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010C370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800110370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800110370301143FULL, 0x0000000000001000ULL ); if(rc) return(rc); - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &target, core); - if(rc) return rc; - - if(core == 0) { - rc=mss_putscom( target, 0x800000040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800000050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800001040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800001050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800002040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800002050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800003040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800003050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800004040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800004050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800005040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800005050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800006040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800006050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800007040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800007050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800008040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800008050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800009040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800009050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000A040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000A050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000B040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000B050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000C040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000C050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000D040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000D050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000E040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000E050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000F040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000F050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800010040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800010050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800011040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800011050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800012040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800012050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800013040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800013050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800100040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800100050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800101040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800101050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800102040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800102050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800103040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800103050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800104040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800104050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800105040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800105050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800106040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800106050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800107040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800107050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800108040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800108050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800109040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800109050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010A040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010A050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010B040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010B050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010C040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010C050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010D040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010D050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010E040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010E050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010F040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010F050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800110040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800110050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800111040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800111050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800112040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800112050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800113040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800113050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - } - else { - rc=mss_putscom( target, 0x800000040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800000050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800001040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800001050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800002040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800002050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800003040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800003050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800004040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800004050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800005040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800005050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800006040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800006050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800007040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800007050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800008040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800008050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800009040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800009050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000A040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000A050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000B040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000B050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000C040301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000C050301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000D040301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000D050301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000E040301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000E050301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000F040301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80000F050301143FULL, 0x000000000000C0C0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800010040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800010050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800011040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800011050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800012040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800012050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800013040301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800013050301143FULL, 0x0000000000000C00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800100040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800100050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800101040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800101050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800102040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800102050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800103040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800103050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800104040301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800104050301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800105040301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800105050301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800106040301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800106050301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800107040301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800107050301143FULL, 0x000000000000C000ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800108040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800108050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800109040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800109050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010A040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010A050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010B040301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010B050301143FULL, 0x0000000000000F00ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010C040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010C050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010D040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010D050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010E040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010E050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010F040301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x80010F050301143FULL, 0x000000000000C300ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800110040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800110050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800111040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800111050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800112040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800112050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800113040301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - rc=mss_putscom( target, 0x800113050301143FULL, 0x0000000000000CC0ULL ); if(rc) return(rc); - } - return rc; - } -// WORKAROUND END: END OF REMOVAL - using namespace fapi; ReturnCode mss_rcd_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt); @@ -325,9 +105,6 @@ ReturnCode mss_draminit(Target& i_target) { // Target is centaur.mba // - FAPI_INF("WARNING: Calling workaround_phy_reset"); - mss_workaround_phy_reset(i_target); - FAPI_INF("WARNING: Done workaround_phy_reset"); ReturnCode rc; uint32_t port_number; @@ -453,19 +230,14 @@ ReturnCode mss_deassert_force_mclk_low (Target& i_target) FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++"); - // Read GP4 - rc = fapiGetCfamRegister(i_target, GP4_REG_0x1013, data_buffer); - if(rc)return rc; - // set bit 3 high - rc_num = data_buffer.setBit(4); - if(rc_num) - { - rc.setEcmdError(rc_num); - return rc; - } - // Stick it back into GP4 - rc = fapiPutCfamRegister(i_target, GP4_REG_0x1013, data_buffer); - if(rc)return rc; + + rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer); + if(rc) return rc; + rc_num = data_buffer.setBit(63); + rc.setEcmdError( rc_num); + if(rc) return rc; + rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer); + if(rc) return rc; return rc; } @@ -492,6 +264,7 @@ ReturnCode mss_assert_resetn_drive_mem_clks( rc_num = rc_num | resetn_1.setBit(0); ecmdDataBufferBase reset_recover_1(1); ecmdDataBufferBase copy_spare_cke_1(1); + rc_num = rc_num | copy_spare_cke_1.setBit(0); // mdb : clk enable on for spare FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN, DRIVING MEM CLKS +++++++++++++++++++++"); @@ -790,6 +563,40 @@ ReturnCode mss_mrs_load( dram_bl = 0x40; } + if (dram_wr == 16) + { + dram_wr = 0x00; + } + else if (dram_wr == 5) + { + dram_wr = 0x80; + } + else if (dram_wr == 6) + { + dram_wr = 0x40; + } + else if (dram_wr == 7) + { + dram_wr = 0xC0; + } + else if (dram_wr == 8) + { + dram_wr = 0x20; + } + else if (dram_wr == 10) + { + dram_wr = 0xA0; + } + else if (dram_wr == 12) + { + dram_wr = 0x60; + } + else if (dram_wr == 14) + { + dram_wr = 0xE0; + } + + if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL) { read_bt = 0x00; @@ -803,7 +610,7 @@ ReturnCode mss_mrs_load( { dram_cl = (dram_cl - 4) << 1; } - else if ((dram_cl > 11)&&(dram_cl > 16)) + else if ((dram_cl > 11)&&(dram_cl < 17)) { dram_cl = ((dram_cl - 12) << 1) + 1; } @@ -827,8 +634,6 @@ ReturnCode mss_mrs_load( dll_reset = 0x00; } - dram_wr = mss_reverse_8bits(dram_wr); - if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT) { dll_precharge = 0x00; @@ -1096,13 +901,13 @@ ReturnCode mss_mrs_load( rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0); rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 2, 1, 0); + rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 2, 1, 0); rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0); rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 6, 1, 2); + rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 6, 1, 1); rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0); rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][0], 9, 1, 3); + rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 9, 1, 2); rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1); rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0); rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0); @@ -1129,7 +934,7 @@ ReturnCode mss_mrs_load( rc_num = rc_num | mrs2.insert((uint8_t) auto_sr, 6, 1); rc_num = rc_num | mrs2.insert((uint8_t) sr_temp, 7, 1); rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1); - rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][0], 9, 2); + rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2); rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 10, 6); rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0); diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C index 2b8841aeb..49f7a8772 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C @@ -1,25 +1,26 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ //------------------------------------------------------------------------------ // *! (C) Copyright International Business Machines Corp. 2011 // *! All Rights Reserved -- Property of IBM @@ -43,6 +44,10 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- +// 1.20 | jdsloat |21-MAY-12| Typo fix, addresses moved to cen_scom_addresses.H, moved per cal settings to initfile +// 1.19 | jdsloat |08-MAY-12| All Refresh controls moved to initfile, changed to just enable refresh +// 1.18 | jdsloat |07-MAY-12| Fixed refresh interval, trfc, ref check interval bit ordering +// 1.16 | bellows |04-MAY-12| Temporary remove of attr read of freq until method defined // 1.15 | jdsloat |16-APR-12| TRFC fixed to insert the right aligned 8 bits // 1.15 | jdsloat |12-Mar-12| Attribute upgrade for cronusflex 12.4 ... trfc to uint32 // 1.14 | jdsloat |07-Mar-12| Fixed iml_complete to match target @@ -81,6 +86,10 @@ //---------------------------------------------------------------------- #include <mss_funcs.H> +//---------------------------------------------------------------------- +// Address Includes +//---------------------------------------------------------------------- +#include <cen_scom_addresses.H> extern "C" { @@ -98,22 +107,8 @@ ReturnCode mss_enable_power_management(Target& i_target); ReturnCode mss_enable_control_bit_ecc(Target& i_target); ReturnCode mss_ccs_mode_reset(Target& i_target); -//---------------------------------------------------------------------- -// Constants - Addresses - TODO: to be moved to cen_scom_addresses.H later -//---------------------------------------------------------------------- -const uint32_t MBA01_REF0Q_0x03010432 = 0x03010432; -//Master Registers -const uint64_t DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL = 0x8000C00B0301143FULL; -const uint64_t DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL = 0x8001C00B0301143FULL; -//ZQCal Control Registers - currently not being used, need to write in settings for these regs -const uint64_t DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P0_0x8000C00F0301143FULL = 0x8000C00F0301143FULL; -const uint64_t DPHY01_DDRPHY_PC_PER_ZCAL_CONFIG_P1_0x8001C00F0301143FULL = 0x8001C00F0301143FULL; -const uint32_t MBSSQ_0x02011417 = 0x02011417; -// Power Management addresses -const uint32_t MBA01_PM0Q_0x03010434 = 0x03010434; -// ECC enable addresses -const uint32_t MBS_ECC0_MBSECCQ_0x0201144A = 0x0201144A; -const uint32_t MBS_ECC1_MBSECCQ_0x0201148A = 0x0201148A; + + ReturnCode mss_draminit_mc (Target& i_target) { @@ -121,6 +116,7 @@ ReturnCode mss_draminit_mc (Target& i_target) // ReturnCode rc; std::vector<fapi::Target> l_mbaChiplets; + uint32_t rc_num = 0; // Get associated MBA's on this centaur rc=fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets); @@ -148,23 +144,35 @@ ReturnCode mss_draminit_mc (Target& i_target) return rc; } - // Step Three: Setup Refresh Controls - FAPI_INF( "+++ Setting Up Refresh Controls +++"); - rc = mss_start_refresh(l_mbaChiplets[i],i_target); + // Step Three: Enable Refresh + FAPI_INF( "+++ Enabling Refresh +++"); + ecmdDataBufferBase mba01_ref0q_data_buffer_64(64); + rc = fapiGetScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64); + if(rc) return rc; + //Bit 0 is enable + rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0); + rc = fapiPutScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64); if(rc) { - FAPI_ERR("---Error During Refresh Control Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); + FAPI_ERR("---Error During Refresh Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); return rc; } + if (rc_num) + { + FAPI_ERR( "Refresh Enable: Error setting up buffers"); + rc.setEcmdError(rc_num); + return rc; + } // Step Four: Setup Periodic Cals - FAPI_INF( "+++ Setting Up Periodic Cals +++"); - rc = mss_enable_periodic_cal(l_mbaChiplets[i]); - if(rc) - { - FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); - return rc; - } + FAPI_INF( "+++ Skipping Periodic Cals +++"); + // FAPI_INF( "+++ Setting Up Periodic Cals +++"); + // rc = mss_enable_periodic_cal(l_mbaChiplets[i]); + // if(rc) + // { + // FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator()); + // return rc; + // } // Step Five: Setup Power Management FAPI_INF( "+++ Setting Up Power Management +++"); @@ -189,100 +197,6 @@ ReturnCode mss_draminit_mc (Target& i_target) return rc; } -ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget) -{ - //Target MBA, centaur - - //Variables - ReturnCode rc; - ReturnCode rc_buff; - uint32_t rc_num = 0; - - uint32_t refresh_interval = 0; - uint32_t refresh_interval_reset = 0; - uint32_t num_ranks = 0; - - //Bit 0 is enable - //bit 4..7 cfg_refresh_priority_threshold - //bit 8..18 cfg_refresh_interval - //bit 19..29 cfg_refresh_reset_interval - //bit 30..39 cfg_trfc - //bit 40..49 cfg_refr_tsv_stack - //bit 50..60 cfg_refr_check_interval - ecmdDataBufferBase mba01_ref0q_data_buffer_64(64); - - - uint32_t dimm_freq; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &i_centarget, dimm_freq); - if(rc) return rc; - - //Configure Refresh based on system attributes MBA01 - rc = fapiGetScom(i_mbatarget, MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64); - if(rc) return rc; - - //Configure Refresh Priority Hard coded to 8 refreshes - rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(4); - - //Configure Refresh Interval - //MBA01 - Get number of ranks, then calculate refresh rate. - - // FAPI ATTR GET NUM RANKS - uint8_t num_ranks_array[2][2]; //[port][dimm] - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_mbatarget, num_ranks_array); - if(rc) return rc; - - // Adding them up - num_ranks = num_ranks_array[0][0] + num_ranks_array[0][1]+ num_ranks_array[1][0] + num_ranks_array[1][1]; - - if (num_ranks == 0) - { - FAPI_INF("+++ No Configured Ranks for current target +++"); - } - else - { - //Now program in the refresh rate for MBA01 - - // TODO: Waiting for tREFI to appear as attribute in XML file - // Until then tREFI will be hardcoded - uint16_t trefi = 6240; // given in Nclks = 3.9us (DDR3 Jedec) at 1600 - //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TREFI, &i_target, num_ranks_array); - //if(rc) return rc; - - refresh_interval = (trefi/num_ranks)/8; - refresh_interval_reset = refresh_interval - 1; - rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval, 8,10); - rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval, 50,10); - rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(refresh_interval_reset,19,10); - //tRFC - uint32_t trfc; - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TRFC, &i_mbatarget, trfc); - if(rc) return rc; - - FAPI_INF("TRFC: 0x%08X ", trfc); - - rc_num = rc_num | mba01_ref0q_data_buffer_64.insert(trfc, 30, 8, 24); - rc_num = rc_num | mba01_ref0q_data_buffer_64.insert((uint8_t) 0, 38, 2); - - //Enable Refresh - //MBA01 - rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0); - rc = fapiPutScom(i_mbatarget, MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64); - if(rc) return rc; - - if (rc_num) - { - FAPI_ERR( "mss_start_refresh: Error setting up buffers"); - rc_buff.setEcmdError(rc_num); - return rc_buff; - } - - FAPI_INF("+++ Refresh Enabled +++"); - - } - - return rc; -} - ReturnCode mss_enable_periodic_cal (Target& i_target) { //Target MBA @@ -293,47 +207,6 @@ ReturnCode mss_enable_periodic_cal (Target& i_target) ReturnCode rc_buff; uint32_t rc_num = 0; - //PER CAL Types - //MBA01 - - // TODO: Waiting for these attributes in XML - // Used to pull enable bits. - //uint8_t memcal_interval; - //rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_interval); - //if(rc) return rc; - //uint8_t zqcal_interval; - //rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zqcal_interval); - //if(rc) return rc; - - uint32_t p0_per_zqcal_mba01_ena = 1; - uint32_t p0_per_sysclk_mba01_ena = 1; - uint32_t p0_per_rd_ck_mba01_ena = 1; - uint32_t p0_per_rd_dqs_mba01_ena = 1; - uint32_t p0_per_rd_center_mba01_ena = 1; - uint32_t p1_per_zqcal_mba01_ena = 1; - uint32_t p1_per_sysclk_mba01_ena = 1; - uint32_t p1_per_rd_ck_mba01_ena = 1; - uint32_t p1_per_rd_dqs_mba01_ena = 1; - uint32_t p1_per_rd_center_mba01_ena = 1; - - // TODO: waiting for ZQ Cal and Mem Cal intevals in XML - // Example one hot code. Not the real order/decode. - //p0_per_zqcal_mba01_ena = 0x1 & zqcal_interval; - //p1_per_zqcal_mba01_ena = 0x2 & zqcal_interval >> 1; - //p0_per_sysclk_mba01_ena = 0x1 & memcal_interval; - //p0_per_rd_ck_mba01_ena = (0x2 & memcal_interval) >> 1; - //p0_per_rd_dqs_mba01_ena = (0x4 & memcal_interval) >> 2; - //p0_per_rd_center_mba01_ena = (0x8 & memcal_interval) >> 3; - //p1_per_sysclk_mba01_ena = 0x1 & memcal_interval; - //p1_per_rd_ck_mba01_ena = (0x2 & memcal_interval) >> 1; - //p1_per_rd_dqs_mba01_ena = (0x4 & memcal_interval) >> 2; - //p1_per_rd_center_mba01_ena = (0x8 & memcal_interval) >> 3; - - //DDR Calibration Register Addresses - currently not in use, need to write in settings for these regs - //uint32_t mba01_cal0q = 0x0301040F; - //uint32_t mba01_cal1q = 0x03010410; - //uint32_t mba01_cal2q = 0x03010411; - ecmdDataBufferBase mba01_data_buffer_64_p0(64); ecmdDataBufferBase mba01_data_buffer_64_p1(64); @@ -342,11 +215,11 @@ ReturnCode mss_enable_periodic_cal (Target& i_target) //ALL CALS CURRENTLY SET AS ON, ONLY CHECK RANK PAIRS PRESENT //***mba01 Setup rc_num = rc_num | mba01_data_buffer_64_p0.flushTo0(); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL, mba01_data_buffer_64_p0); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0); if(rc) return rc; rc_num = rc_num | mba01_data_buffer_64_p1.flushTo0(); - rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL, mba01_data_buffer_64_p1); + rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, mba01_data_buffer_64_p1); if(rc) return rc; uint8_t primary_rank_group0_array[2]; //[rank] @@ -406,57 +279,14 @@ ReturnCode mss_enable_periodic_cal (Target& i_target) rc_num = rc_num | mba01_data_buffer_64_p1.setBit(51); } - - - //p0 - if(p0_per_zqcal_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p0.setBit(52); - } - if(p0_per_sysclk_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p0.setBit(53); - } - if(p0_per_rd_ck_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p0.setBit(54); - } - if(p0_per_rd_dqs_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p0.setBit(55); - } - if(p0_per_rd_center_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p0.setBit(56); - } + //Start the periodic Cal + rc_num = rc_num | mba01_data_buffer_64_p1.setBit(61); - //p1 - if(p1_per_zqcal_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p1.setBit(52); - } - if(p1_per_sysclk_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p1.setBit(53); - } - if(p1_per_rd_ck_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p1.setBit(54); - } - if(p1_per_rd_dqs_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p1.setBit(55); - } - if(p1_per_rd_center_mba01_ena == 1) - { - rc_num = rc_num | mba01_data_buffer_64_p1.setBit(56); - } - //Write the mba_p01_PER_CAL_CFG_REG - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143FULL, mba01_data_buffer_64_p0); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0); if(rc) return rc; FAPI_INF("+++ Periodic Calibration Enabled p0+++"); - rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143FULL, mba01_data_buffer_64_p1); + rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F, mba01_data_buffer_64_p1); if(rc) return rc; FAPI_INF("+++ Periodic Calibration Enabled p1+++"); @@ -515,7 +345,7 @@ ReturnCode mss_enable_control_bit_ecc (Target& i_target) rc = fapiGetScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64); if(rc) return rc; - rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc0_data_buffer_64); + rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64); if(rc) return rc; // Enable Memory ECC Check/Correct for MBA01 @@ -540,7 +370,7 @@ ReturnCode mss_enable_control_bit_ecc (Target& i_target) rc = fapiPutScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64); if(rc) return rc; - rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc0_data_buffer_64); + rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64); if(rc) return rc; FAPI_INF("+++ mss_enable_control_bit_ecc complete +++"); diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C index dd10ac4c7..c07e9edc1 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C @@ -1,25 +1,26 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ //------------------------------------------------------------------------------ // Don't forget to create CVS comments when you check in your changes! //------------------------------------------------------------------------------ @@ -27,6 +28,7 @@ //------------------------------------------------------------------------------ // Version:| Author: | Date: | Comment: //---------|----------|---------|------------------------------------------------ +// 1.28 | bellows |02-May-12| cal ranks are 4 bits, this needed to be adjusted // 1.26 | asaetow |12-Apr-12| Added "if(rc) return rc;" at line 180. // 1.25 | asaetow |06-Apr-12| Added "if(rc) return rc;" at line 165. // 1.24 | asaetow |03-Apr-12| Changed FAPI_INF to FAPI_ERR where applicable from lines 275 to 324, per Mike Jones. @@ -146,8 +148,8 @@ ReturnCode mss_draminit_training(Target& i_target) rc_num = rc_num | data_buffer_20.flushTo0(); ecmdDataBufferBase read_compare_buffer_1(1); rc_num = rc_num | read_compare_buffer_1.flushTo0(); - ecmdDataBufferBase rank_cal_buffer_3(3); - rc_num = rc_num | rank_cal_buffer_3.flushTo0(); + ecmdDataBufferBase rank_cal_buffer_4(4); + rc_num = rc_num | rank_cal_buffer_4.flushTo0(); ecmdDataBufferBase ddr_cal_enable_buffer_1(1); ecmdDataBufferBase ccs_end_buffer_1(1); rc_num = rc_num | ccs_end_buffer_1.flushTo1(); @@ -160,7 +162,7 @@ ReturnCode mss_draminit_training(Target& i_target) ecmdDataBufferBase resetn_buffer_1(1); rc_num = rc_num | resetn_buffer_1.setBit(0); ecmdDataBufferBase cal_timeout_cnt_mult_buffer_2(2); - rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo0(); + rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo1(); ecmdDataBufferBase data_buffer_64(64); if(rc_num) @@ -226,15 +228,17 @@ ReturnCode mss_draminit_training(Target& i_target) FAPI_INF( "+++++++++++++++ Sending init cal on rank group: %d +++++++++++++++", group); rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, 0); if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs + FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0], + group, primary_ranks_array[group][1]); if(primary_ranks_array[group][0] == INVALID) { - rc_num = rc_num | rank_cal_buffer_3.insert(primary_ranks_array[group][1], 0, 3, 0); + rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][1], 0, 4, 4); // 8 bit storage, need last 4 bits } else { - rc_num = rc_num | rank_cal_buffer_3.insert(primary_ranks_array[group][0], 0, 3, 0); + rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][0], 0, 4, 4); // 8 bit storage, need last 4 bits } - rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1); + rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_4, ddr_cal_enable_buffer_1, ccs_end_buffer_1); if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs FAPI_INF( "+++++++++++++++ Execute CCS array +++++++++++++++"); rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60); @@ -278,7 +282,7 @@ ReturnCode mss_check_cal_status( rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64); if(rc) return rc; } - while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) && (!cal_error_buffer_64.isBitSet(cal_error_reg_offset)) && (poll_count <= 5)) + while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) && (!cal_error_buffer_64.isBitSet(cal_error_reg_offset)) && (poll_count <= 20)) { FAPI_INF( "+++++++++++++++ Calibration on port: %d rank group: %d in progress. Poll count: %d +++++++++++++++", i_port, i_group, poll_count); poll_count++; diff --git a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C index 4c48419d1..ff09263c3 100644 --- a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C +++ b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C @@ -1,25 +1,26 @@ -// IBM_PROLOG_BEGIN_TAG -// This is an automatically generated prolog. -// -// $Source: src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C $ -// -// IBM CONFIDENTIAL -// -// COPYRIGHT International Business Machines Corp. 2012 -// -// p1 -// -// Object Code Only (OCO) source materials -// Licensed Internal Code Source Materials -// IBM HostBoot Licensed Internal Code -// -// The source code for this program is not published or other- -// wise divested of its trade secrets, irrespective of what has -// been deposited with the U.S. Copyright Office. -// -// Origin: 30 -// -// IBM_PROLOG_END +/* IBM_PROLOG_BEGIN_TAG + * This is an automatically generated prolog. + * + * $Source: src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C $ + * + * IBM CONFIDENTIAL + * + * COPYRIGHT International Business Machines Corp. 2012 + * + * p1 + * + * Object Code Only (OCO) source materials + * Licensed Internal Code Source Materials + * IBM HostBoot Licensed Internal Code + * + * The source code for this program is not published or other- + * wise divested of its trade secrets, irrespective of what has + * been deposited with the U.S. Copyright Office. + * + * Origin: 30 + * + * IBM_PROLOG_END_TAG + */ /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */ //------------------------------------------------------------------------------ @@ -47,7 +48,9 @@ // 1.3 | bellows | 12/21/11 | fapiGetAssociatedDimms funciton does not work, added quick exit // 1.4 | jsabrow | 02/13/12 | Updates for code review // 1.5 | jsabrow | 03/26/12 | Updates for code review -// 1.5 | jdsloat | 04/26/12 | fixed 1.5V issue +// 1.8 | jdsloat | 04/26/12 | fixed 1.5V issue +// 1.9 | jdsloat | 05/08/12 | Removed debug message +// 1.10 | jdsloat | 05/09/12 | Fixed typo // This procedure takes a vector of Centaurs behind a voltage domain, // reads in supported DIMM voltages from SPD and determines optimal @@ -120,8 +123,6 @@ fapi::ReturnCode mss_volt(std::vector<fapi::Target> & i_targets_memb) // now we figure out if we have a supported ddr type and voltage // note: only support DDR3=1.35V and DDR4=1.2xV - FAPI_INF( "dram type, ddr3 enum, ddr4 enum: 0x%02X 0x%02X 0x%02X", l_spd_dramtype, fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3, fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4); - if (l_dram_ddr3_found_flag && l_dram_ddr4_found_flag) { FAPI_ERR("mss_volt: DDR3 and DDR4 mixing not allowed"); diff --git a/src/usr/pore/makefile b/src/usr/pore/makefile index a98318689..6d395cd3b 100644 --- a/src/usr/pore/makefile +++ b/src/usr/pore/makefile @@ -23,6 +23,6 @@ ROOTPATH = ../../.. SUBDIRS = fapiporeve.d poreve.d test.d -BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:f09e776669b675baa9cd4fa5ad91e0e7d7671f0b +BINARY_FILES = $(IMGDIR)/centaur.sbe_pnor.bin:36036d093c958af39ca4e0719e9e79bfe2269c43 include ${ROOTPATH}/config.mk diff --git a/src/usr/targeting/common/xmltohb/vbu.system.xml b/src/usr/targeting/common/xmltohb/vbu.system.xml index 1e152b22a..aad12f5bc 100644 --- a/src/usr/targeting/common/xmltohb/vbu.system.xml +++ b/src/usr/targeting/common/xmltohb/vbu.system.xml @@ -297,7 +297,7 @@ </attribute> <attribute> <id>CHIP_UNIT</id> - <default>5</default> + <default>4</default> </attribute> </targetInstance> @@ -813,7 +813,7 @@ <targetInstance> <id>sys0node0dimm32</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030020</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -836,7 +836,7 @@ <targetInstance> <id>sys0node0dimm33</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030021</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -859,7 +859,7 @@ <targetInstance> <id>sys0node0dimm34</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030022</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -882,7 +882,7 @@ <targetInstance> <id>sys0node0dimm35</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030023</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -905,7 +905,7 @@ <targetInstance> <id>sys0node0dimm36</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030024</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -928,7 +928,7 @@ <targetInstance> <id>sys0node0dimm37</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030025</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -951,7 +951,7 @@ <targetInstance> <id>sys0node0dimm38</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030026</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -974,7 +974,7 @@ <targetInstance> <id>sys0node0dimm39</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030027</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -997,7 +997,7 @@ <targetInstance> <id>sys0node0dimm40</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030028</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1020,7 +1020,7 @@ <targetInstance> <id>sys0node0dimm41</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x00030029</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1043,7 +1043,7 @@ <targetInstance> <id>sys0node0dimm42</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x0003002A</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1066,7 +1066,7 @@ <targetInstance> <id>sys0node0dimm43</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x0003002B</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1089,7 +1089,7 @@ <targetInstance> <id>sys0node0dimm44</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x0003002C</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1112,7 +1112,7 @@ <targetInstance> <id>sys0node0dimm45</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x0003002D</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1135,7 +1135,7 @@ <targetInstance> <id>sys0node0dimm46</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x0003002E</default></attribute> <attribute> <id>PHYS_PATH</id> @@ -1158,7 +1158,7 @@ <targetInstance> <id>sys0node0dimm47</id> - <type>lcard-dimm-jedec</type> + <type>lcard-dimm-cdimm</type> <attribute><id>HUID</id><default>0x0003002F</default></attribute> <attribute> <id>PHYS_PATH</id> |
