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| author | Dan Crowell <dcrowell@us.ibm.com> | 2016-08-26 10:03:53 -0500 |
|---|---|---|
| committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2016-08-30 17:22:01 -0400 |
| commit | ab651844afcc9b0ac6a1c74779da555b62342bf1 (patch) | |
| tree | a2237315dc22c11545d00f4f97aea7645028f5ef /src/usr/hwpf/hwp/dram_initialization | |
| parent | 85cb1f757c9de446ab4e1f460e206091242b2c49 (diff) | |
| download | talos-hostboot-ab651844afcc9b0ac6a1c74779da555b62342bf1.tar.gz talos-hostboot-ab651844afcc9b0ac6a1c74779da555b62342bf1.zip | |
Remove last of old hwpf directory
Remove all of the old fapi1 HWPs from P8
Update makefiles/code to not include old hwpf headers
Change-Id: Idc840554721f68b0af3b6ee6c7ad84f5df258e60
RTC: 146345
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28844
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/hwpf/hwp/dram_initialization')
26 files changed, 0 insertions, 10546 deletions
diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C deleted file mode 100644 index d7fbcd0af..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C +++ /dev/null @@ -1,140 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/dram_initialization.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -/** - * @file dram_initialization.C - * - * Support file for IStep: dram_initialization - * Dram Initialization - * - * HWP_IGNORE_VERSION_CHECK - * - */ - -/******************************************************************************/ -// Includes -/******************************************************************************/ -#include <stdint.h> -#include <trace/interface.H> -#include <initservice/taskargs.H> -#include <errl/errlentry.H> -#include <errl/errludtarget.H> -#include <diag/mdia/mdia.H> -#include <diag/attn/attn.H> -#include <initservice/isteps_trace.H> -#include <isteps/hwpisteperror.H> -#include <errl/errludtarget.H> -#include <intr/interrupt.H> // for PIR_t structure - -// targeting support -#include <targeting/common/commontargeting.H> -#include <targeting/common/util.H> -#include <targeting/common/utilFilter.H> - -// fapi support -#include <fapi.H> -#include <fapiPlatHwpInvoker.H> -#include <isteps/hwpf_reasoncodes.H> - -#include "dram_initialization.H" -#include <pbusLinkSvc.H> - -// Uncomment these files as they become available: -// #include "host_startPRD_dram/host_startPRD_dram.H" -#include "host_mpipl_service/proc_mpipl_ex_cleanup.H" -#include "host_mpipl_service/proc_mpipl_chip_cleanup.H" -#include "mss_extent_setup/mss_extent_setup.H" -// #include "mss_memdiag/mss_memdiag.H" -// #include "mss_scrub/mss_scrub.H" -#include "mss_thermal_init/mss_thermal_init.H" -#include "proc_setup_bars/mss_setup_bars.H" -#include "proc_setup_bars/proc_setup_bars.H" -#include "proc_pcie_config/proc_pcie_config.H" -#include "proc_exit_cache_contained/proc_exit_cache_contained.H" -#include "mss_power_cleanup/mss_power_cleanup.H" -#include "proc_throttle_sync/proc_throttle_sync.H" -//remove these once memory setup workaround is removed -#include <devicefw/driverif.H> -#include <vpd/spdenums.H> -#include <sys/time.h> -#include <sys/mm.h> -#include <dump/dumpif.H> -#include <vfs/vfs.H> - -#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS - #include <occ/occ_common.H> -#endif - -namespace DRAM_INITIALIZATION -{ - -using namespace ISTEP; -using namespace ISTEP_ERROR; -using namespace ERRORLOG; -using namespace TARGETING; -using namespace EDI_EI_INITIALIZATION; -using namespace fapi; -using namespace ERRORLOG; - -// -// Wrapper function to call mss_extent_setup -// -void* call_mss_extent_setup( void *io_pArgs ) -{ - errlHndl_t l_errl = NULL; - - IStepError l_stepError; - - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_mss_extent_setup entry" ); - - // call the HWP - FAPI_INVOKE_HWP( l_errl, mss_extent_setup ); - - if ( l_errl ) - { - TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace, - "ERROR : failed executing mss_extent_setup returning error" ); - - // Create IStep error log and cross reference to error that occurred - l_stepError.addErrorDetails( l_errl ); - - // Commit Error - errlCommit( l_errl, HWPF_COMP_ID ); - } - else - { - TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "SUCCESS : mss_extent_setup completed ok" ); - } - - - TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, - "call_mss_extent_setup exit" ); - - // end task, returning any errorlogs to IStepDisp - return l_stepError.getErrorHandle(); -} - -}; // end namespace diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H deleted file mode 100644 index c6f5ae633..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H +++ /dev/null @@ -1,230 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/dram_initialization.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -#ifndef __DRAM_INITIALIZATION_DRAM_INITIALIZATION_H -#define __DRAM_INITIALIZATION_DRAM_INITIALIZATION_H - -#include <errl/errlentry.H> - -/** - * @file dram_initialization.H - * - * Dram Initialization - * - * All of the following routines are "named isteps" - they are invoked as - * tasks by the @ref IStepDispatcher. - * - * ***************************************************************** - * THIS FILE WAS GENERATED ON 2012-04-11:1608 - * ***************************************************************** - * - * HWP_IGNORE_VERSION_CHECK - * - */ - - /* @tag isteplist - * @docversion v1.28 (12/03/12) - * @istepname dram_initialization - * @istepnum 14 - * @istepdesc Dram Initialization - * - * @{ - * @substepnum 1 - * @substepname host_startprd_dram - * @substepdesc : Load PRD for DRAM domain - * @target_sched serial - * @} - * @{ - * @substepnum 2 - * @substepname mss_extent_setup - * @substepdesc MSS Extent Setup - * @target_sched serial - * @} - * @{ - * @substepnum 3 - * @substepname mss_memdiag - * @substepdesc Mainstore Pattern Testing - * @target_sched serial - * @} - * @{ - * @substepnum 4 - * @substepname mss_thermal_init - * @substepdesc : Initialize the thermal sensor - * @target_sched serial - * @} - * @{ - * @substepnum 5 - * @substepname proc_pcie_config - * @substepdesc : Configure the PHBs - * @target_sched serial - * @} - * @{ - * @substepnum 6 - * @substepname mss_power_cleanup - * @substepdesc : Clean up any MCS/Centuars - * @target_sched serial - * @} - * @{ - * @substepnum 7 - * @substepname proc_setup_bars - * @substepdesc : Setup Memory BARs - * @target_sched serial - * @} - * @{ - * @substepnum 8 - * @substepname proc_exit_cache_contained - * @substepdesc : Allow execution from memory - * @target_sched serial - * @} - * @{ - * @substepnum 9 - * @substepname host_mpipl_service - * @substepdesc : host_mpipl_service - * @target_sched serial - * @} - - */ - -namespace DRAM_INITIALIZATION -{ - - -/** - * @brief host_startprd_dram - * - * Load PRD for DRAM domain - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_host_startprd_dram( void *io_pArgs ); - - -/** - * @brief mss_extent_setup - * - * MSS Extent Setup - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_mss_extent_setup( void *io_pArgs ); - -/** - * @brief mss_memdiag - * - * Mainstore Pattern Testing - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_mss_memdiag( void *io_pArgs ); - - -/** - * @brief mss_thermal_init - * - * Initialize the thermal sensor - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_mss_thermal_init( void *io_pArgs ); - -/** - * @brief proc_pcie_config - * - * Configure the PHBs - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_proc_pcie_config( void *io_pArgs ); - -/** - * @brief mss_power_cleanup - * - * Clean up any MCS/Centaurs - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_mss_power_cleanup( void *io_pArgs ); - - -/** - * @brief proc_setup_bars - * - * Setup Memory BARs - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_proc_setup_bars( void *io_pArgs ); - - -/** - * @brief proc_exit_cache_contained - * - * Allow execution from memory - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - */ -void* call_proc_exit_cache_contained( void *io_pArgs ); - - -/** - * @brief host_mpipl_service - * - * Perform MPIPL tasks - * - * param[in,out] - pointer to any arguments, usually NULL - * - * return pointer to any errlogs - * - * NOTE: this step will only run as part of an mpipl, - * the istep dispatcher will not call this step for - * the normal ipl flow - * - */ -void* call_host_mpipl_service( void *io_pArgs); - -}; // end namespace - -#endif diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C deleted file mode 100644 index 2d4c9b01a..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C +++ /dev/null @@ -1,346 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_mpipl_chip_cleanup.C,v 1.11 2015/05/01 18:04:36 belldi Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_chip_cleanup.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_mpipl_chip_cleanup.C -// *! DESCRIPTION : To enable MCD recovery -// *! -// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com -// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com -// *! -// *! -// *! -// *! -// *! -// *! Additional Note(s): -// *! -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_mpipl_chip_cleanup.H" -#include "p8_scom_addresses.H" - -extern "C" -{ - //------------------------------------------------------------------------------ - // Function definitions - //------------------------------------------------------------------------------ - - //------------------------------------------------------------------------------ - // name: proc_mpipl_chip_cleanup - //------------------------------------------------------------------------------ - // purpose: - // To enable MCD recovery - // To remove PCIe Express Controllers (PECs) from CAPP mode - // - // Note: PHBs are left in ETU reset state after executing proc_mpipl_nest_cleanup, which runs before this procedure. PHYP releases PHBs from ETU reset post HostBoot IPL. - // - // SCOM regs - // - // 1) MCD even recovery control register - // 0000000002013410 (SCOM) - // bit 0 (MCD_REC_EVEN_ENABLE): 0 to 1 transition needed to start, reset to 0 at end of request. - // bit 5 (MCD_REC_EVEN_REQ_PEND) - // - // - // 2) MCD odd recovery control register - // 0000000002013411 (SCOM) - // bit 0 (MCD_REC_ODD_ENABLE): 0 to 1 transition needed to start, reset to 0 at end of request. - // bit 5 (MCD_REC_ODD_REQ_PEND) - // - // 3) Clear PCI Nest FIR registers - // 02012X00 (SCOM) - // - // 4) PB AIB CAPP Enable registers - // 09013CX3 (SCOM) - // bit 0 (PE_CAPP_EN): Enable CAPP mode of operation - // - // - // parameters: - // 'i_target' is reference to chip target - // - // returns: - // FAPI_RC_SUCCESS (success, MCD recovery enabled for odd and even slices) - // - // RC_MCD_RECOVERY_NOT_DISABLED_RC (MCD recovery for even or odd slice is not disabled; therefore can't re-enable MCD recovery) - // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_mpipl_chip_cleanup_errors.xml) - // - // getscom/putscom fapi errors - // fapi error assigned from eCMD function failure - // - //------------------------------------------------------------------------------ - fapi::ReturnCode proc_mpipl_chip_cleanup(const fapi::Target &i_target){ - const char *procedureName = "proc_mpipl_chip_cleanup"; //Name of this procedure - fapi::ReturnCode rc; //fapi return code value - uint32_t rc_ecmd = 0; //ecmd return code value - const uint32_t data_size = 64; //Size of data buffer - const int MAX_MCD_DIRS = 2; //Max of 2 MCD Directories (even and odd) - ecmdDataBufferBase fsi_data[MAX_MCD_DIRS]; - const uint64_t ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[MAX_MCD_DIRS] = { - 0x0000000002013410, //MCD even recovery control register address - 0x0000000002013411 //MCD odd recovery control register address - }; - const uint32_t MCD_RECOVERY_CTRL_REG_BIT_POS0 = 0; //Bit 0 of MCD even and odd recovery control regs - const char *ARY_MCD_DIR_STRS[MAX_MCD_DIRS] = { - "Even", //Ptr to char string "Even" for even MCD - "Odd" //Ptr to char string "Odd" for odd MCD - }; - uint8_t num_phb; - const int MAX_PHBS = 4; - const uint64_t PCI_NEST_FIR_REG_ADDRS[MAX_PHBS] = { - 0x02012000, - 0x02012400, - 0x02012800, - 0x02012C00 - }; - - const uint64_t PE_SECURE_CAPP_ENABLE_REG_ADDRS[MAX_PHBS] = { - 0x09013C03, - 0x09013C43, - 0x09013C83, - 0x09013CC3 - }; - - - do { - //Set bit length for 64-bit buffers - rc_ecmd = fsi_data[0].setBitLength(data_size); - rc_ecmd |= fsi_data[1].setBitLength(data_size); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - break; - } - - //Verify MCD recovery was previously disabled for even and odd slices - //If not, this is an error condition - for (int counter = 0; counter < MAX_MCD_DIRS; counter++) { - FAPI_DBG("Verifying MCD %s Recovery is disabled, target=%s", ARY_MCD_DIR_STRS[counter], i_target.toEcmdString()); - - //Get data from MCD Even or Odd Recovery Ctrl reg - rc = fapiGetScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data[counter]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], i_target.toEcmdString()); - break; - } - - - //Check whether bit 0 is 0, meaning MCD recovery is disabled as expected - if( fsi_data[counter].getBit(MCD_RECOVERY_CTRL_REG_BIT_POS0) ) { - FAPI_ERR("%s: MCD %s Recovery not disabled as expected, target=%s", procedureName, ARY_MCD_DIR_STRS[counter], i_target.toEcmdString()); - const fapi::Target & CHIP_TARGET = i_target; - const uint64_t & MCD_RECOV_CTRL_REG_ADDR = ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter]; - ecmdDataBufferBase & MCD_RECOV_CTRL_REG_DATA = fsi_data[counter]; - FAPI_SET_HWP_ERROR(rc, RC_MPIPL_MCD_RECOVERY_NOT_DISABLED_RC); - break; - } - } - if(!rc.ok()) { - break; - } - - //Assert bit 0 of MCD Recovery Ctrl regs to enable MCD recovery - for (int counter = 0; counter < MAX_MCD_DIRS; counter++) { - FAPI_DBG("Enabling MCD %s Recovery, target=%s", ARY_MCD_DIR_STRS[counter], i_target.toEcmdString()); - - //Assert bit 0 of MCD Even or Odd Recovery Control reg to enable recovery - rc_ecmd = fsi_data[counter].setBit(MCD_RECOVERY_CTRL_REG_BIT_POS0 ); - if(rc_ecmd) { - FAPI_ERR("%s: Error (%u) asserting bit pos %u in ecmdDataBufferBase that stores value of MCD %s Recovery Control reg (addr: 0x%08llX), target=%s", procedureName, rc_ecmd, MCD_RECOVERY_CTRL_REG_BIT_POS0, ARY_MCD_DIR_STRS[counter], ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - - //Write data to MCD Even or Odd Recovery Control reg - rc = fapiPutScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data[counter]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], i_target.toEcmdString()); - break; - } - } - if(!rc.ok()) { - break; - } - - // SW227429: clear PCI Nest FIR registers - // hostboot is blindly sending EOIs in order to ensure no interrupts are pending when PHYP starts up again - // with ETU held in reset, these get trapped in PCI and force a freeze to occur (PCI Nest FIR(14)) - // clearing the FIR should remove the freeze condition - rc_ecmd = fsi_data[0].flushTo0(); - if (rc_ecmd) { - FAPI_ERR("%s: Error (%u) forming PCI Nest FIR clear data buffer, target=%s", procedureName, rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, &i_target, num_phb); - if (!rc.ok()) - { - FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)"); - break; - } - - for (int counter = 0; counter < num_phb; counter++) { - FAPI_DBG("Clearing PCI%d Nest FIR, target=%s", counter, i_target.toEcmdString()); - rc = fapiPutScom(i_target, PCI_NEST_FIR_REG_ADDRS[counter], fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, PCI_NEST_FIR_REG_ADDRS[counter], i_target.toEcmdString()); - break; - } - } - if(!rc.ok()) { - break; - } - - //SW295661: Clear bit 0 of the Snoop CAPI Configuration register to disable snoop pipelines so Ttype aren't decoded for CAPI - FAPI_DBG("Reading Snoop CAPI Configuration register, addr=0x%08llX, target=%s", CAPP_CXA_SNOOP_CFG_0x0201301A, i_target.toEcmdString()); - rc = fapiGetScom(i_target, CAPP_CXA_SNOOP_CFG_0x0201301A, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_CXA_SNOOP_CFG_0x0201301A, i_target.toEcmdString()); - break; - } - rc_ecmd = fsi_data[0].clearBit(0); - if (rc_ecmd) { - FAPI_ERR("%s: Error (%u) Couldn't clear bit 0 in data buffer for Snoop CAPI Configuration register, target=%s", procedureName, rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - FAPI_DBG("Snoop CAPI configuration register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", CAPP_CXA_SNOOP_CFG_0x0201301A, fsi_data[0].getDoubleWord(0), i_target.toEcmdString()); - - FAPI_DBG("Writing Snoop CAPI Configuration register, target=%s", i_target.toEcmdString()); - rc = fapiPutScom(i_target, CAPP_CXA_SNOOP_CFG_0x0201301A, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_CXA_SNOOP_CFG_0x0201301A, i_target.toEcmdString()); - break; - } - - //SW295661: Clear bit 3 of the APC Master PowerBus Control register to turn off examing cresps when PHBs taken out of CAPP mode - FAPI_DBG("Reading APC Master PowerBus Control register, addr=0x%08llX, target=%s", CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString()); - rc = fapiGetScom(i_target, CAPP_APC_MASTER_PB_CTL_0x02013018, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString()); - break; - } - rc_ecmd = fsi_data[0].clearBit(3); - if (rc_ecmd) { - FAPI_ERR("%s: Error (%u) Couldn't clear bit 3 in data buffer for APC Master PowerBus Control register (addr: 0x%08llX), target=%s", procedureName, rc_ecmd, CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - FAPI_DBG("APC Master PowerBus Control register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", CAPP_APC_MASTER_PB_CTL_0x02013018, fsi_data[0].getDoubleWord(0), i_target.toEcmdString()); - - FAPI_DBG("Writing APC Master PowerBus Control register (addr: 0x%08llX), target=%s", CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString()); - rc = fapiPutScom(i_target, CAPP_APC_MASTER_PB_CTL_0x02013018, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString()); - break; - } - - //SW295661: Clear bits 1-3 of the APC Master CAPI Control register to disable PHBs in ES chiplet attached to CAPP PHB port 0 and port 1 interfaces (will get reset to correct vals when code walks PCI buses and configures CAPI) - FAPI_DBG("Reading APC Master CAPI Control register, addr=0x%08llX, target=%s", CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString()); - rc = fapiGetScom(i_target, CAPP_APC_MASTER_CAPI_CTL_0x02013019, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString()); - break; - } - rc_ecmd = fsi_data[0].clearBit(1,3); - if (rc_ecmd) { - FAPI_ERR("%s: Error (%u) Couldn't clear bits 1-3 in data buffer for APC Master CAPI Control register (addr: 0x%08llX) , target=%s", procedureName, rc_ecmd, CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - FAPI_DBG("APC Master CAPI Control register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", CAPP_APC_MASTER_CAPI_CTL_0x02013019, fsi_data[0].getDoubleWord(0), i_target.toEcmdString()); - - FAPI_DBG("Writing APC Master CAPI Control register (addr: 0x%08llX), target=%s", CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString()); - rc = fapiPutScom(i_target, CAPP_APC_MASTER_CAPI_CTL_0x02013019, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString()); - break; - } - - //SW295661: Clear bits 0 and 1 of CAPP Error Status and Control reg (scom addr: 0x0201300E). - FAPI_DBG("Reading CAPP Error Status and Control register, addr=0x%08llX, target=%s", NX_CAPP_ERR_STAT_CTRL_0x0201300E, i_target.toEcmdString()); - rc = fapiGetScom(i_target, NX_CAPP_ERR_STAT_CTRL_0x0201300E, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, NX_CAPP_ERR_STAT_CTRL_0x0201300E, i_target.toEcmdString()); - break; - } - rc_ecmd |= fsi_data[0].clearBit(0); //Clear bit 0 (Error Recovery Initiated) - rc_ecmd |= fsi_data[0].clearBit(1); //Clear bit 1 (Error Recovery Complete) - if (rc_ecmd) { - FAPI_ERR("%s: Error (%u) Couldn't clear bit(s) in data buffer for CAPP Error Status and Control register, target=%s", procedureName, rc_ecmd, i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - FAPI_DBG("CAPP Error Status and Control register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", NX_CAPP_ERR_STAT_CTRL_0x0201300E, fsi_data[0].getDoubleWord(0), i_target.toEcmdString()); - - FAPI_DBG("Writing CAPP Error Status and Control register, target=%s", i_target.toEcmdString()); - rc = fapiPutScom(i_target, NX_CAPP_ERR_STAT_CTRL_0x0201300E, fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, NX_CAPP_ERR_STAT_CTRL_0x0201300E, i_target.toEcmdString()); - break; - } - - //SW295661: Disable CAPP mode of operation by clearing bit 0 of PE Secure CAPP Enable register - for (int counter = 0; counter < num_phb; counter++) { - FAPI_DBG("Reading PE%d Secure CAPP Enable register (addr: 0x%08llX), target=%s", counter, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString()); - rc = fapiGetScom(i_target, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString()); - break; - } - - rc_ecmd = fsi_data[0].clearBit(0); - if (rc_ecmd) { - FAPI_ERR("%s: Error (%u) Couldn't clear bit 0 in data buffer for PE%d Secure CAPP Enable register (addr: 0x%08llX), target=%s", procedureName, rc_ecmd, counter, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString()); - rc.setEcmdError(rc_ecmd); - break; - } - - FAPI_DBG("Writing PE%d Secure CAPP Enable register (addr: 0x%08llX), target=%s", counter, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString()); - rc = fapiPutScom(i_target, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], fsi_data[0]); - if (!rc.ok()) { - FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString()); - break; - } - } - } while(0); - - FAPI_IMP("Exiting %s", procedureName); - - return rc; - } - - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H deleted file mode 100644 index 0d12def30..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H +++ /dev/null @@ -1,73 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_mpipl_chip_cleanup.H,v 1.3 2014/03/02 23:16:17 belldi Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_chip_cleanup.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_mpipl_chip_cleanup.H -// *! DESCRIPTION : To enable MCD recovery -// *! -// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com -// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_MPIPL_CHIP_CLEANUP_H_ -#define _PROC_MPIPL_CHIP_CLEANUP_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - -//------------------------------------------------------------------------------ -// Structure Definition(s) -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_mpipl_chip_cleanup_FP_t) (const fapi::Target &); - -extern "C" -{ - /** - * @brief To enable MCD recovery - * - * @param[in] (1) 'i_target' Reference to processor chip target - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode proc_mpipl_chip_cleanup(const fapi::Target & i_target); - - - -} //extern "C" - -#endif diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C deleted file mode 100644 index d90305dc3..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C +++ /dev/null @@ -1,277 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_mpipl_ex_cleanup.C,v 1.6 2013/08/20 17:31:41 stillgs Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_mpipl_ex_cleanup.C -// *! DESCRIPTION : Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode -// *! -// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com -// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com -// *! -// *! -// *! -// *! -// *! Additional Note(s): -// *! -// *! -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_mpipl_ex_cleanup.H" -#include "p8_scom_addresses.H" - -extern "C" -{ - - //------------------------------------------------------------------------------ - // name: proc_mpipl_ex_cleanup - //------------------------------------------------------------------------------ - // purpose: - // Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode - // SCOM regs: - // 1) GP3 Register (NA in PERV CPLT) - // - // bit 27 (TP_LVLTRANS_FENCE): Electrical winkel fence. Mainly used by power management. - // - // 2) PowerManagement GP0 reg - // - // bit 22 (TP_TC_PERVASIVE_ECO_FENCE): Pervasive ECO fence - // - // bit 39 (PM_SLV_WINKLE_FENCE): Fence off the powered off chiplet in winkle. - Logical fence/hold for pcb_slave and pcb_slave_pm. For electrical fence see bit 23. - // - // 3) PowerManagement GP1 - // - // Bit 5: WINKLE_POWER_OFF_SEL: Winkle Power Off Select: - // Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode). Depending on the setting of pmicr_latency_en, this bit is controlled with a PCB-write (0) or by the PMICR in the core (1). - // - // Bit 15: PMICR_LATENCY_EN: Selects how the sleep/winkle latency (which is deep/fast) is controlled. If asserted the PMICR controls the winkle/sleep_power_off_sel in PMGP1, otherwise those bits are controlled via SCOM by OCC. - - // parameters: - // 'i_target' is chip target - // - // returns: - // FAPI_RC_SUCCESS (success, EX chiplets entered fast winkle) - // - // getscom/putscom/getattribute fapi errors - // fapi error assigned from eCMD function failure - // - //------------------------------------------------------------------------------ - fapi::ReturnCode proc_mpipl_ex_cleanup(const fapi::Target & i_target) { - const char *procedureName = "proc_mpipl_ex_cleanup"; - fapi::ReturnCode rc; //fapi return code - uint32_t rc_ecmd = 0; //ecmd return code value - ecmdDataBufferBase fsi_data(64); //64-bit data buffer - uint8_t attr_chip_unit_pos; //EX chiplet's unit offset within chip with respect to similar EX units - const uint64_t EX_OFFSET_MULT = 0x01000000; //Multiplier used to calculate offset for respective EX chiplet - - uint64_t address; // Varible for computed addresses - uint64_t offset; - char reg_name[32]; // Character array for register names - - - // Relevant PMGP0 bits -// const uint32_t PM_DISABLE = 0; - const uint32_t BLOCK_REG_WKUP_SOURCE = 53; - - - // Relevant PMGP1 bits - const uint32_t WINKLE_POWER_OFF_SEL = 5; - - std::vector<fapi::Target> v_ex_chiplets; //Vector of EX chiplets - - - do - { - //Entering fapi function - FAPI_INF("Entering %s", procedureName); - - //Get vector of EX chiplets - rc = fapiGetChildChiplets( i_target, - fapi::TARGET_TYPE_EX_CHIPLET, - v_ex_chiplets, - fapi::TARGET_STATE_FUNCTIONAL); - if (rc) - { - FAPI_ERR("%s: fapiGetChildChiplets error", procedureName); - break; - } - - FAPI_INF("Processing target %s", i_target.toEcmdString()); - - //Parse thru EX chiplets and prepare fast-winkled cores for deep operations - //Loop thru EX chiplets in vector - for (uint32_t counter = 0; counter < v_ex_chiplets.size(); counter++) - { - - // Get EX chiplet number - rc = FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS, - &(v_ex_chiplets[counter]), - attr_chip_unit_pos); - if (rc) - { - FAPI_ERR("%s: fapiGetAttribute error (ATTR_CHIP_UNIT_POS)", procedureName); - break; - } - FAPI_INF("EX chiplet pos = 0x%02X", attr_chip_unit_pos); - - - // Calculate the address offset based on chiplet number - offset = EX_OFFSET_MULT * attr_chip_unit_pos; - - // ----------------------------------------------------------------- - FAPI_DBG("\tOriginal register contents"); - address = EX_GP3_0x100F0012 + offset; - strcpy(reg_name, "GP3"); - rc = fapiGetScom( i_target, address, fsi_data ); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - break; - } - FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0)); - - address = EX_PMGP0_0x100F0100 + offset; - strcpy(reg_name, "PMGP0"); - rc = fapiGetScom( i_target, address, fsi_data ); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - break; - } - FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0)); - - address = EX_PMGP1_0x100F0103 + offset; - strcpy(reg_name, "PMGP1"); - rc = fapiGetScom( i_target, address, fsi_data ); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - break; - } - FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0)); - // ----------------------------------------------------------------- - - // Clean up configuration remnants of the fast-winkle configuration - // that was used to flush the chiplets after checkstop. EX chiplets - // will have been through SBE EX Init with certain step skippled due - // to MPIPL. - - FAPI_INF("Re-establish Deep Winkle mode default"); - address = EX_PMGP1_OR_0x100F0105 + offset; - strcpy(reg_name, "PMGP1 OR"); - - rc_ecmd |= fsi_data.flushTo0(); - rc_ecmd |= fsi_data.setBit(WINKLE_POWER_OFF_SEL); - if(rc_ecmd) - { - FAPI_ERR("ecmdDatatBuffer error preparing %s reg (addr: 0x%08llX) with rc %x", reg_name, address, rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, address, fsi_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX)", address); - break; - } - - FAPI_INF("Clear block wakeup sources to PM logic. PM is NOT re-enabled"); - // (eg clear Block Interrrupt Sources) - address = EX_PMGP0_AND_0x100F0101 + offset; - strcpy(reg_name, "PMGP0 AND"); - - rc_ecmd |= fsi_data.flushTo1(); -// rc_ecmd |= fsi_data.clearBit(PM_DISABLE); - rc_ecmd |= fsi_data.clearBit(BLOCK_REG_WKUP_SOURCE); - if(rc_ecmd) - { - FAPI_ERR("ecmdDatatBuffer error preparing %s reg (addr: 0x%08llX)", reg_name, address); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, address, fsi_data); - if (rc) - { - FAPI_ERR("fapiPutScom error (addr: 0x%08llX)", address); - break; - } - - // ----------------------------------------------------------------- - FAPI_DBG("\tUpdated register contents"); - address = EX_GP3_0x100F0012 + offset; - strcpy(reg_name, "GP3"); - rc = fapiGetScom( i_target, address, fsi_data ); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - break; - } - FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0)); - - address = EX_PMGP0_0x100F0100 + offset; - strcpy(reg_name, "PMGP0"); - rc = fapiGetScom( i_target, address, fsi_data ); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - break; - } - FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0)); - - address = EX_PMGP1_0x100F0103 + offset; - strcpy(reg_name, "PMGP1"); - rc = fapiGetScom( i_target, address, fsi_data ); - if (rc) - { - FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address); - break; - } - FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0)); - // ----------------------------------------------------------------- - } // chiplet loop - - // Error exit from above loop - // Not really needed as outer while(0) is next but here for consistent structure - if (!rc.ok()) - { - break; - } - } while (0); - - //Exiting fapi function - FAPI_INF("Exiting %s", procedureName); - - return rc; - } - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H deleted file mode 100644 index 9b2f6e694..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H +++ /dev/null @@ -1,71 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_mpipl_ex_cleanup.H,v 1.4 2014/03/03 00:42:49 belldi Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_mpipl_ex_cleanup.H -// *! DESCRIPTION : Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode -// *! -// *! OWNER NAME : Dion Bell Email: belldi@us.ibm.com -// *! BACKUP NAME : Dion Bell Email: belldi@us.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_MPIPL_EX_CLEANUP_H_ -#define _PROC_MPIPL_EX_CLEANUP_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> -#include <vector> - -//------------------------------------------------------------------------------ -// Structure Definition(s) -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*proc_mpipl_ex_cleanup_FP_t) (const fapi::Target &); - -extern "C" -{ - /** - * @brief Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode - * - * @param[in] (1) 'i_target' Reference to processor chip target - * - * @return ReturnCode - * - * - */ - fapi::ReturnCode proc_mpipl_ex_cleanup(const fapi::Target &i_target); -} - -#endif diff --git a/src/usr/hwpf/hwp/dram_initialization/makefile b/src/usr/hwpf/hwp/dram_initialization/makefile deleted file mode 100644 index b5bf93cf2..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/makefile +++ /dev/null @@ -1,90 +0,0 @@ -# IBM_PROLOG_BEGIN_TAG -# This is an automatically generated prolog. -# -# $Source: src/usr/hwpf/hwp/dram_initialization/makefile $ -# -# OpenPOWER HostBoot Project -# -# Contributors Listed Below - COPYRIGHT 2012,2014 -# [+] International Business Machines Corp. -# -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -# implied. See the License for the specific language governing -# permissions and limitations under the License. -# -# IBM_PROLOG_END_TAG -ROOTPATH = ../../../../.. - -MODULE = dram_initialization - -## support for Targeting and fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp - -## pointer to common HWP files -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training - -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/cen_stopclocks - -## NOTE: add the base istep dir here. -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization - -## Include sub dirs -## NOTE: add a new EXTRAINCDIR when you add a new HWP -## EXAMPLE: -## EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/<HWP_dir> -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init -EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/dram_initialization/mss_memdiag -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config/ -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync -EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup - -## NOTE: add new object files when you add a new HWP -OBJS += dram_initialization.o -OBJS += proc_exit_cache_contained.o -OBJS += mss_extent_setup.o -OBJS += mss_setup_bars.o -OBJS += proc_fab_smp.o -OBJS += proc_setup_bars.o -OBJS += proc_pcie_config.o -OBJS += proc_mpipl_ex_cleanup.o -OBJS += proc_mpipl_chip_cleanup.o -OBJS += mss_thermal_init.o -OBJS += mss_power_cleanup.o -OBJS += proc_throttle_sync.o - - -## NOTE: add a new directory onto the vpaths when you add a new HWP -## EXAMPLE: -# VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/<HWP_dir> -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup -VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync - -include ${ROOTPATH}/config.mk - diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C deleted file mode 100644 index 465862227..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C +++ /dev/null @@ -1,78 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* COPYRIGHT International Business Machines Corp. 2012,2014 */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_extent_setup.C,v 1.8 2012/07/17 13:24:10 bellows Exp $ -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -//Owner :- Girisankar paulraj -//Back-up owner :- Mark bellows -// -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.8 | bellows |16-Jul-12| added in Id tag -// 1.7 | bellows |15-Jun-12| Updated for Firmware -// 1.3 | gpaulraj |11-Nov-11| modified according HWPF format -// 1.2 | gpaulraj |02-oct-11| supported for MCS loop - SIM model. compiled in the ecmd & FAPI calls included. -// 1.1 | gpaulraj |31-jul-11| First drop for centaur -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -//#include <prcdUtils.H> -//#include <verifUtils.H> -//#include <cen_maintcmds.H> -#include <mss_extent_setup.H> -//---------------------------------------------------------------------- -// eCMD Includes -//---------------------------------------------------------------------- -//#include <ecmdClientCapi.H> -//#include <ecmdDataBuffer.H> -//#include <ecmdUtils.H> -//#include <ecmdSharedUtils.H> -//#include <fapiClientCapi.H> -//#include <croClientCapi.H> -//#include <fapi.H> -//#include <fapiSystemConfig.H> -//#include <fapiSharedUtils.H> -// attributes listing -// FAPI procedure calling -// -extern "C" { - -using namespace fapi; - - -ReturnCode mss_extent_setup(){ - - ReturnCode rc; - if(rc){ - FAPI_ERR(" Calling Extent function Error "); - return rc; - } - return rc; -} - - -} //end extern C - diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H deleted file mode 100755 index 9fa840606..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H +++ /dev/null @@ -1,72 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_extent_setup.H,v 1.8 2012/07/17 13:22:51 bellows Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_extent_setup.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : girisankar paulraj Email: gpaulraj@in.ibm.com -// *! BACKUP NAME : Mark Bellows Email: bellows@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for mss_extent_setup. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.8 | bellows |16-Jul-12| added in Id tag -// 1.7 | bellows |15-Jun-12| Updated for Firmware -// 1.2 | | | -// 1.1 | gpaulraj |11-NOV-11| First Draft. - -#ifndef MSS_EXTENT_SETUP_H_ -#define MSS_EXTENT_SETUP_H_ - -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_extent_setup_FP_t)(); - -extern "C" -{ - -/** - * @brief extent setup procedure -- currently an open shell until extent functions are found t obe needed - * - * - * @return ReturnCode - */ - -fapi::ReturnCode mss_extent_setup(); - -} // extern "C" - -#endif // MSS_EXTENT_SETUP_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C deleted file mode 100644 index 9165bcf7e..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C +++ /dev/null @@ -1,541 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_power_cleanup.C,v 1.7 2014/02/19 13:41:33 bellows Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_power_cleanup.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_power_cleanup -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com -// *! BACKUP NAME : Anuwat Saetow Email: asaetow@us.ibm.com - -// *! ADDITIONAL COMMENTS : -// -// power clean up -// needs to deconfig centaurs and mba - (needs three targets) -// Two reasons: centaur is bad and no DIMMs -// Needed to set up fences and turn off power / clock drivers -// -// There is a sub function that cleans up an mba that needs to be called if we deconfigure an mba -// this procedure does not write attributes just shuts down hardware -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.7 | bellows |19-FEB-14| RAS Review Updates Pass 2 -// 1.6 |bellows |17-FEB-14| RAS review updates -// 1.5 |bellows |05-FEB-14| Making this procedure work on really non-functional centaurs -// 1.4 |bellows |21-Nov-13| Gerrit Review Updates - unused variable removed -// 1.3 |bellows |11-Nov-13| Gerrit Review Updates -// 1.2 |bellows |11-Nov-13| Update due to new istep location -// 1.1 |bellows |07-Nov-13| copied from mss_cnfg_cleanup version 1.3 -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// My Includes -//------------------------------------------------------------------------------ -#include <cen_stopclocks.H> -#include <mss_power_cleanup.H> -#include <cen_scom_addresses.H> -#include <mss_eff_config.H> -#include <common_scom_addresses.H> - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - -//------------------------------------------------------------------------------ -// Constants -//------------------------------------------------------------------------------ - -const uint8_t PORT_SIZE = 2; -const uint8_t DIMM_SIZE = 2; - - -//------------------------------------------------------------------------------ -// extern encapsulation -//------------------------------------------------------------------------------ -extern "C" -{ - -//------------------------------------------------------------------------------ -// @brief mss_power_cleanup(): This function will disable a centaur - fencing it and powering it down -// -// @param const fapi::Target i_target_centaur: the fapi target of the centaur -// @param const fapi::Target i_target_mba0: the mba0 target -// @param const fapi::Target i_target_mba1: the mba1 target -// -// @return fapi::ReturnCode -//------------------------------------------------------------------------------ - fapi::ReturnCode mss_power_cleanup(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1) - { - fapi::ReturnCode rc,rc0,rc1,rcf,rcc; - uint8_t centaur_functional=1, mba0_functional=1, mba1_functional=1; - - FAPI_INF("Running mss_power_cleanupon %s\n", i_target_centaur.toEcmdString()); - - do - { - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_centaur, centaur_functional); - if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; } - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba0, mba0_functional); - if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; } - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba1, mba1_functional); - if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; } - - rc0 = mss_power_cleanup_mba_part1(i_target_centaur, i_target_mba0); - rc1 = mss_power_cleanup_mba_part1(i_target_centaur, i_target_mba1); - - rcf = mss_power_cleanup_mba_fence(i_target_centaur, i_target_mba0, i_target_mba1); - - rcc = mss_power_cleanup_centaur(i_target_centaur); - - - - if(rc0) { - if(mba0_functional) { - FAPI_ERR("mba0 was functional yet it got a bad return code"); - const fapi::Target & MBA_CHIPLET = i_target_mba0; - FAPI_SET_HWP_ERROR(rc0, RC_MSS_POWER_CLEANUP_MBA0_UNEXPECTED_BAD_RC); - rc=rc0; - break; - } - else { - FAPI_INF("mba0 was not functional and it got a bad return code"); - } - } - - if(rc1) { - if(mba1_functional) { - FAPI_ERR("mba1 was functional yet it got a bad return code"); - const fapi::Target & MBA_CHIPLET = i_target_mba1; - FAPI_SET_HWP_ERROR(rc1, RC_MSS_POWER_CLEANUP_MBA1_UNEXPECTED_BAD_RC); - rc=rc1; - break; - } - else { - FAPI_INF("mba1 was not functional and it got a bad return code"); - } - } - - if(rcf) { - if(centaur_functional) { - FAPI_ERR("centaur was functional yet it got a bad return code during fencing"); - const fapi::Target & CENTAUR = i_target_centaur; - FAPI_SET_HWP_ERROR(rcf, RC_MSS_POWER_CLEANUP_FENCING_UNEXPECTED_BAD_RC); - rc=rcf; - break; - } - else { - FAPI_INF("centaur was not functional and it got a bad return code"); - } - } - - if(rcc) { - if(centaur_functional) { - FAPI_ERR("centaur was functional yet it got a bad return code during cleanup"); - const fapi::Target & CENTAUR = i_target_centaur; - FAPI_SET_HWP_ERROR(rcc, RC_MSS_POWER_CLEANUP_CENTAUR_UNEXPECTED_BAD_RC); - rc=rcc; - break; - } - else { - FAPI_INF("centaur was not functional and it got a bad return code"); - } - } - - } while(0); - - return rc; - } // end mss_power_cleanup() - - fapi::ReturnCode set_powerdown_bits(int mba_functional, ecmdDataBufferBase &data_buffer_64) - { - fapi::ReturnCode rc; - uint32_t rc_num = 0; - - if(mba_functional == 0) - { - FAPI_INF("set_powerdown_bits MBA not Functional"); - rc_num |= data_buffer_64.setBit(0 +48); // MASTER_PD_CNTL (48) - rc_num |= data_buffer_64.setBit(1 +48); // ANALOG_INPUT_STAB2 (49) - rc_num |= data_buffer_64.setBit(7 +48); // ANALOG_INPUT_STAB1 (55) - rc_num |= data_buffer_64.setBit(8 +48,2); // SYSCLK_CLK_GATE (56:57) - rc_num |= data_buffer_64.setBit(10 +48); // DP18_RX_PD(0) (58) - rc_num |= data_buffer_64.setBit(11 +48); // DP18_RX_PD(1) (59) - rc_num |= data_buffer_64.setBit(14 +48); // TX_TRISTATE_CNTL (62) - rc_num |= data_buffer_64.setBit(15 +48); // VCC_REG_PD (63) - } - else - { - rc_num |= data_buffer_64.clearBit(0 +48); // MASTER_PD_CNTL (48) - rc_num |= data_buffer_64.clearBit(1 +48); // ANALOG_INPUT_STAB2 (49) - rc_num |= data_buffer_64.clearBit(7 +48); // ANALOG_INPUT_STAB1 (55) - rc_num |= data_buffer_64.clearBit(8 +48,2); // SYSCLK_CLK_GATE (56:57) - rc_num |= data_buffer_64.clearBit(10 +48); // DP18_RX_PD(0) (58) - rc_num |= data_buffer_64.clearBit(11 +48); // DP18_RX_PD(1) (59) - rc_num |= data_buffer_64.clearBit(14 +48); // TX_TRISTATE_CNTL (62) - rc_num |= data_buffer_64.clearBit(15 +48); // VCC_REG_PD (63) - } - - if (rc_num) - { - FAPI_ERR( "Error setting up buffers"); - rc.setEcmdError(rc_num); - } - - return rc; - } - - fapi::ReturnCode mss_power_cleanup_mba_part1(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba) - { - // turn off functional vector - fapi::ReturnCode rc; - uint8_t centaur_functional; - uint8_t mba_functional; - ecmdDataBufferBase data_buffer_64(64); - uint32_t rc_num = 0; - uint8_t unit_pos = 0; - ecmdDataBufferBase cfam_data(32); - int memon=0; - - do - { - FAPI_INF("Starting mss_power_cleanup_mba_part1"); - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_centaur, centaur_functional); - if(rc) - { - FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); - break; - } - FAPI_INF("working on a centaur whose functional is %d", centaur_functional); - - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba, mba_functional); - if(rc) { - FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); - break; - } - FAPI_INF("working on an mba whose functional is %d", mba_functional); - -// But to clarify so there's no misconception, you can only turn off the clocks to the MEMS grid (Ports 2/3). If you want to deconfigure Ports 0/1, there is no way to turn those clocks off. The best you can do there is shut down the PHY inside DDR (I think they have an ultra low power mode where you can turn off virtually everything including their PLLs, phase rotators, analogs , FIFOs, etc) plus of course you can disable their I/O. I think those steps should be done no matter which port you're deconfiguring, but in terms of the chip clock grid, you only get that additional power savings in the bad Port 2/3 case. - if(centaur_functional == 1 && mba_functional == 0) - { - FAPI_INF("cleanup_part1 MBA not functional"); - // check that clocks are up to the DDR partition before turning it off - // this case will only happen if we get memory up and later come back and want to - // deconfigure it. The first time, it may not even be up yet. - rc = fapiGetScom(i_target_centaur, TP_CLK_STATUS_0x01030008, data_buffer_64); - if(rc) { - FAPI_ERR("ERROR: Cannot getScom 0x1030008"); - break; - } - if(data_buffer_64.getDoubleWord(0) == 0x000007FFFFFFFFFFull) - { // pervasive clocks are on - rc = fapiGetScom(i_target_centaur, MEM_CLK_STATUS_0x03030008, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot getScom 0x3030008"); - break; - } - if(data_buffer_64.getDoubleWord(0) == 0x0000001FFFFFFFFFull) - { - memon=1; - } - } - - - if(memon) - { - FAPI_INF("Mem Clocks On"); - - if(mba_functional == 0) - { - - FAPI_INF("This mba is not functional, doing more transactions"); - - // Do Port 0 - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot getScom DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F"); - break; - } - - rc = set_powerdown_bits(mba_functional, data_buffer_64); - if(rc) break; - - rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot putScom DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F"); - break; - } - - // Do Port 1 - rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot getScom DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F"); - break; - } - - rc = set_powerdown_bits(mba_functional, data_buffer_64); - if(rc) break; - - rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot putScom DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F"); - break; - } -// From Section 10.4 - } // mba functional - } -//12. Grid Clock off , South Port Pair. This is done by asserting the GP bit controlling -//TP_CHIP_DPHY23_GRID_DISABLE (Table 57 ). This must be decided during CFAMINIT . it may not be -//dynamically updated - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, unit_pos); // 0 = MBA01 and 1 = MBA23 - if(rc) - { - FAPI_ERR("ERROR: Cannot get ATTR_CHIP_UNIT_POS"); - break; - } - - if(unit_pos == 1) - { - rc = fapiGetCfamRegister( i_target_centaur, CFAM_FSI_GP4_0x00001013, cfam_data); - if(rc) - { - FAPI_ERR("ERROR: Cannot getCfamRegister CFAM_FSI_GP4_0x00001013"); - break; - } - - if(mba_functional == 0) - { - rc_num |= cfam_data.setBit(1); - } - else - { - rc_num |= cfam_data.clearBit(1); - } - - if (rc_num) - { - FAPI_ERR( "Error setting up buffers"); - rc.setEcmdError(rc_num); - break; - } - - rc = fapiPutCfamRegister( i_target_centaur, CFAM_FSI_GP4_0x00001013, cfam_data); - if(rc) - { - FAPI_ERR("ERROR: Cannot putCfamRegister CFAM_FSI_GP4_0x00001013"); - break; - } - } // mba 1 only code - - } - } - while(0); - - if(rc) { - FAPI_ERR("ERROR: Bad RC in mss_power_cleanup_mba_part1"); - } - return rc; - } // end of mss_power_cleanup_mba_part1 - - fapi::ReturnCode mss_power_cleanup_mba_fence(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1) { - // turn off functional vector - fapi::ReturnCode rc; - uint8_t mba_functional0, mba_functional1; - ecmdDataBufferBase data_buffer_64(64); - uint32_t rc_num = 0; - ecmdDataBufferBase cfam_data(32); - int memon=0; - - do - { - FAPI_INF("Starting mss_power_cleanup_mba_fence"); - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba0, mba_functional0); - if(rc) break; - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba1, mba_functional1); - if(rc) break; - FAPI_INF("mba0 functional is %d", mba_functional0); - FAPI_INF("mba1 functional is %d", mba_functional1); - - -//enable_partial_good_dc memn_fence_dc mems_fence_dc Fencing Behavior -//0 0 0 Normal operation, no fencing enabled -//0 1 1 Chiplet boundary (inter chiplet nets) fencing enabled. Both -// bits set for full fencing. Both MBAs fenced from MBS but -// not from each other -//0 0 1 Not a valid setting. Fencing enabled for MEMS chiplet boundary only. -//0 1 0 Not a valid setting. Fencing enabled for MEMS chiplet boundary only. -//1 0 0 No Fencing enabled . -//1 0 1 MEMS (Ports 2/3) bad, fencing enabled to MEMN and at chiplet boundary of MEMS -//1 1 0 MEMN (Ports 0/1) bad, fencing enabled to MEMS and at chiplet boundary of MEMN -//1 1 1 Fencing enabled between MEMN and MEMS and at chiplet boundary. - rc = fapiGetScom(i_target_centaur, TP_CLK_STATUS_0x01030008, data_buffer_64); - if(rc) break; - if(data_buffer_64.getDoubleWord(0) == 0x000007FFFFFFFFFFull) - { // pervasive clocks are on - rc = fapiGetScom(i_target_centaur, MEM_CLK_STATUS_0x03030008, data_buffer_64); - if(rc) break; - if(data_buffer_64.getDoubleWord(0) == 0x0000001FFFFFFFFFull) - { - memon=1; - } - } - - if(memon) { - FAPI_INF("Mem Clocks On"); - rc = fapiGetScom( i_target_centaur, MEM_GP3_0x030F0012, data_buffer_64); - if (rc) break; - - if(mba_functional0 == 0 || mba_functional1 == 0) - { // one of the two are non-functional - rc_num |= data_buffer_64.setBit(31); // enable_partial_good_dc - } - else - { - rc_num |= data_buffer_64.clearBit(31); - } - - if(mba_functional0 == 0) - { - rc_num |= data_buffer_64.setBit(18); // memn_fence_dc - } - else - { - rc_num |= data_buffer_64.clearBit(18); // memn_fence_dc - } - if(mba_functional1 == 0) - { - rc_num |= data_buffer_64.setBit(17); // mems_fence_dc - } - else { - rc_num |= data_buffer_64.clearBit(17); // mems_fence_dc - } - - if (rc_num) - { - FAPI_ERR( "Error setting up buffers"); - rc.setEcmdError(rc_num); - break; - } - - rc = fapiPutScom( i_target_centaur, MEM_GP3_0x030F0012, data_buffer_64); - if (rc) break; - } - - - } while(0); - - if(rc) - { - FAPI_ERR("ERROR: during mss_power_cleanup_mba_fence"); - } - return rc; - } // end of mss_power_cleanup_mba_fense - - fapi::ReturnCode mss_power_cleanup_centaur(const fapi::Target & i_target_centaur) { - // turn off functional vector - fapi::ReturnCode rc; - uint8_t centaur_functional; - - do - { - FAPI_INF("Starting mss_power_cleanup_centaur"); - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_centaur, centaur_functional); - if(rc) { - FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); - break; - } - - int memon=0; - int pervon=0; - ecmdDataBufferBase data_buffer_64(64); - - if(centaur_functional == 0) { - // check that clocks are up to the DDR partition before turning it off - // this case will only happen if we get memory up and later come back and want to - // deconfigure it. The first time, it may not even be up yet. - rc = fapiGetScom(i_target_centaur, TP_CLK_STATUS_0x01030008, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot getScom 0x1030008"); - break; - } - if(data_buffer_64.getDoubleWord(0) == 0x000007FFFFFFFFFFull) - { // pervasive clocks are on - pervon=1; - rc = fapiGetScom(i_target_centaur, MEM_CLK_STATUS_0x03030008, data_buffer_64); - if(rc) - { - FAPI_ERR("ERROR: Cannot getScom 0x3030008"); - break; - } - if(data_buffer_64.getDoubleWord(0) == 0x0000001FFFFFFFFFull) - { - memon=1; - } - } - - - if(pervon || memon) - { - bool l_stop_mem_clks=true; - bool l_stop_nest_clks=true; - bool l_stop_dram_rfrsh_clks=true; - bool l_stop_tp_clks=false; - bool l_stop_vitl_clks=false; - FAPI_INF("Calling cen_stopclocks"); - rc = cen_stopclocks(i_target_centaur, l_stop_mem_clks, l_stop_nest_clks, l_stop_dram_rfrsh_clks, l_stop_tp_clks, l_stop_vitl_clks ); - - } // clocks are on, so kill them - } // non functional centaurs - FAPI_INF("Ending mss_power_cleanup_centaur"); - } - while(0); - - if(rc) { FAPI_ERR("ERROR: Bad RC in mss_power_cleanup_centaur"); } - return rc; - } // end of mss_power_cleanup_centaur - - -} // extern "C" - diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H deleted file mode 100644 index d93584ec2..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H +++ /dev/null @@ -1,100 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_power_cleanup.H,v 1.3 2014/02/19 13:41:35 bellows Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_power_cleanup.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_power_cleanup.H -// *! DESCRIPTION : Header file for mss_eff_config. -// *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com -// *! BACKUP NAME : Anuwat Saetow Email: asaetow@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.3 | bellows |19-FEB-14| RAS Review Updates -// 1.2 |bellows |11-Nov-13| Gerrit Review Comments -// 1.1 |bellows |07-Nov-13| copied from mss_cnfg_cleanup.H version 1.2 -//------------------------------------------------------------------------------ - - -#ifndef mss_power_cleanup_H_ -#define mss_power_cleanup_H_ - -//------------------------------------------------------------------------------ -// My Includes -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - -typedef fapi::ReturnCode (*mss_power_cleanup_FP_t)(const fapi::Target & i_target_centaur, - const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1); -typedef fapi::ReturnCode (*mss_power_cleanup_mba_FP_t)( const fapi::Target & i_target_mba); - -extern "C" { - -//------------------------------------------------------------------------------ -// @brief mss_power_cleanup(): Clean up a centaur and also MBAs, also calls the mba cleanup under the covers -// -// @param const fapi::Target i_target_centaur: the centaur -// @param const fapi::Target i_target_mba0: the mba0 -// @param const fapi::Target i_target_mba1: the mba1 -// -// @return fapi::ReturnCode -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_power_cleanup(const fapi::Target & i_target_centaur, - const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1); -//------------------------------------------------------------------------------ -// @brief mss_power_cleanup_mba(): Clean up a centaur and also MBAs -// -// @param const fapi::Target i_target_mba0: the mba0 -// -// @return fapi::ReturnCode -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_power_cleanup_mba(const fapi::Target & i_target_mba); // clean up an mba - -fapi::ReturnCode mss_power_cleanup_centaur(const fapi::Target & i_target_centaur); -fapi::ReturnCode mss_power_cleanup_mba_part1(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba); -fapi::ReturnCode mss_power_cleanup_mba_fence(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1 ); - - - -} // extern "C" - -#endif // mss_power_cleanup_H - diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C deleted file mode 100644 index a98b58ddf..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C +++ /dev/null @@ -1,662 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_thermal_init.C,v 1.20 2015/03/02 20:43:37 pardeik Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_thermal_init -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Michael Pardeik Email: pardeik@us.ibm.com -// *! BACKUP NAME : Jacob Sloat Email: jdsloat@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// applicable CQ component memory_screen -// -// DESCRIPTION: -// The purpose of this procedure is to configure and start the OCC cache and Centaur thermal cache -// -// TODO: -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.20 | pardeik |02-MAR-15| initialize l_dimm_ranks_array to zero -// | use const variables in for loops instead of numbers -// 1.18 | pardeik |12-FEB-15| change ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP to -// | a centaur target (was system) -// 1.17 | pardeik |19-NOV-14| Use MRW attribute for SC address map for ISDIMMs -// 1.16 | pardeik |06-FEB-14| removed string in trace statement -// 1.15 | pardeik |24-FEB-14| added support for ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE -// 1.14 | pardeik |12-FEB-14| changed CONFIG_INTERVAL_TIMER from 5 to 15 to -// 1.13 | pardeik |30-JAN-14| workaround for SW243504 (enable sensors on master -// | i2c bus if ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE=ON) -// 1.12 | pardeik |06-JAN-14| enable writing of safemode IPL throttles -// 1.11 | pardeik |20-DEC-13| Only get sensor map attributes if a custom dimm -// 1.10 | pardeik |21-NOV-13| added support for dimm temperature sensor attributes -// 1.9 | pardeik |11-OCT-13| gerrit review updates to remove uneeded items -// 1.8 | pardeik |04-OCT-13| changes done from gerrit review -// 1.7 | pardeik |01-AUG-13| Functional corrections to procedure -// | Updates for defect HW257484 -// | Use custom DIMM instead of dimm type attribute -// | Added commented out throttle section at end to enable later -// 1.6 | joabhend |28-NOV-12| Corrected procedure_name from char* to const char* -// 1.5 | joabhend |16-NOV-12| Updated code to reflect review output -// 1.4 | joabhend |02-NOV-12| Corrected scom call from SCAC_FIRMASK to SCAC_ADDRMAP -// 1.3 | joabhend |10-OCT-12| Added section for emergency throttle disable, removed FIR bit 33 handling -// 1.2 | gollub |05-SEP-12| Calling mss_unmask_fetch_errors after mss_thermal_init_cloned -// 1.1 | joabhend |30-APR-12| First Draft - - - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <mss_thermal_init.H> -#include <fapi.H> -#include <mss_unmask_errors.H> -#include <cen_scom_addresses.H> - -extern "C" { - - using namespace fapi; - - - // Procedures in this file - fapi::ReturnCode mss_thermal_init_cloned(const fapi::Target & i_target); - - -//****************************************************************************** -// -//****************************************************************************** - -fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target) -{ - // Target is centaur - - fapi::ReturnCode l_rc; - - l_rc = mss_thermal_init_cloned(i_target); - - // If mss_unmask_fetch_errors gets it's own bad rc, - // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_fetch_errors runs clean, - // it will just return the passed in rc. - l_rc = mss_unmask_fetch_errors(i_target, l_rc); - - return l_rc; -} - - -//****************************************************************************** -// -//****************************************************************************** - - fapi::ReturnCode mss_thermal_init_cloned(const fapi::Target & i_target) - { - - fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; - - FAPI_INF("*** Running mss_thermal_init ***"); - - // Constant declaration - const uint8_t l_NUM_MBAS = 2; // Number of MBAs per Centaur - const uint8_t l_NUM_PORTS = 2; // Number of ports per MBA - const uint8_t l_NUM_DIMMS = 2; // Number of dimms per MBA port - - const uint64_t HANG_PULSE_0_REG = 0x00000000020f0020ULL; - const uint64_t THERM_MODE_REG = 0x000000000205000fULL; - const uint64_t CONTROL_REG = 0x0000000002050012ULL; - - const uint64_t SCAC_FIRMASK = 0x00000000020115c3ULL; - const uint64_t SCAC_ACTMASK = 0x00000000020115d3ULL; - const uint64_t SCAC_ADDRMAP = 0x00000000020115cdULL; - const uint64_t SCAC_CONFIG = 0x00000000020115ceULL; - const uint64_t SCAC_ENABLE = 0x00000000020115ccULL; - const uint64_t SCAC_I2CMCTRL = 0x00000000020115d1ULL; - const uint64_t SCAC_PIBTARGET = 0x00000000020115d2ULL; - const uint64_t I2CM_RESET = 0x00000000000A0001ULL; - - const uint64_t MBS_EMER_THROT = 0x000000000201142dULL; - const uint64_t MBS_FIR_REG = 0x0000000002011400ULL; - - const uint32_t PRIMARY_I2C_BASE_ADDR = 0x000A0000; - const uint32_t SPARE_I2C_BASE_ADDR = 0x000A0000; - const uint32_t I2C_SETUP_UPPER_HALF = 0xD2314049; - const uint32_t I2C_SETUP_LOWER_HALF = 0x05000000; - const uint32_t ACT_MASK_UPPER_HALF = 0x00018000; - const uint32_t ACT_MASK_LOWER_HALF = 0x00000000; -// OCC polls cacheline every 2 ms (could vary from this, as seen on scope) -// For I2C bus at 50kHz (9.6 ms max to read 8 sensors), use interval of 15 for margin and to prevent stall errors when 8 sensors are enabled to be read - const uint32_t CONFIG_INTERVAL_TIMER = 15; - const uint32_t CONFIG_STALL_TIMER = 128; - const uint8_t I2C_BUS_ENCODE_PRIMARY = 0; - const uint8_t I2C_BUS_ENCODE_SECONDARY = 8; - const uint8_t MAX_NUM_DIMM_SENSORS = 8; - const uint8_t MAX_I2C_BUSSES = 2; - - // Variable declaration - uint8_t l_dimm_ranks_array[l_NUM_MBAS][l_NUM_PORTS][l_NUM_DIMMS]; // Number of ranks for each configured DIMM in each MBA - uint8_t l_custom_dimm[l_NUM_MBAS]; // Custom DIMM - uint8_t l_mba_pos = 0; // Current MBA for populating rank array - ecmdDataBufferBase l_data(64); - ecmdDataBufferBase l_data_scac_enable(64); - ecmdDataBufferBase l_data_scac_addrmap(64); - uint8_t l_cdimm_sensor_map; - uint8_t l_cdimm_sensor_map_primary; - uint8_t l_cdimm_sensor_map_secondary; - uint8_t l_cdimm_number_dimm_temp_sensors; - uint8_t l_i2c_address_map; - uint8_t l_data_scac_addrmap_offset; - uint8_t l_i2c_bus_encode; - uint8_t l_sensor_map_mask; - uint8_t l_master_i2c_temp_sensor_enable; - uint8_t l_spare_i2c_temp_sensor_enable; - uint32_t l_dimm_sensor_cache_addr_map = 0; - -//******************************************** -// Centaur internal temperature polling setup -//******************************************** -// setup hang pulse - l_rc = fapiGetScom(i_target, HANG_PULSE_0_REG, l_data); - if (l_rc) return l_rc; - l_ecmd_rc |= l_data.setBit(1); - l_ecmd_rc |= l_data.setBit(2); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, HANG_PULSE_0_REG, l_data); - if (l_rc) return l_rc; -// setup DTS enables - l_rc = fapiGetScom(i_target, THERM_MODE_REG, l_data); - if (l_rc) return l_rc; - l_ecmd_rc |= l_data.setBit(20); - l_ecmd_rc |= l_data.setBit(21); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, THERM_MODE_REG, l_data); - if (l_rc) return l_rc; -// setup pulse count and enable DTS sampling - l_rc = fapiGetScom(i_target, THERM_MODE_REG, l_data); - if (l_rc) return l_rc; - l_ecmd_rc |= l_data.setBit(5); - l_ecmd_rc |= l_data.setBit(6); - l_ecmd_rc |= l_data.setBit(7); - l_ecmd_rc |= l_data.setBit(8); - l_ecmd_rc |= l_data.setBit(9); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, THERM_MODE_REG, l_data); - if (l_rc) return l_rc; -// issue a reset - l_ecmd_rc |= l_data.flushTo0(); - l_ecmd_rc |= l_data.setBit(0); - l_ecmd_rc |= l_data.setBit(1); - l_ecmd_rc |= l_data.setBit(2); - l_ecmd_rc |= l_data.setBit(3); - l_ecmd_rc |= l_data.setBit(4); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, CONTROL_REG, l_data); - if (l_rc) return l_rc; -// Centaur internal temperature polling setup complete - - - // Get input attributes from MBAs - std::vector<fapi::Target> l_target_mba_array; - l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_target_mba_array); - if (l_rc) return l_rc; - - // need to clear out the array since it could be sparsely filled - // in the ISDIMM case - for( size_t i = 0; - i < (sizeof(l_custom_dimm)/sizeof(l_custom_dimm[0])); - i++ ) - { - l_custom_dimm[i] = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO; - } - - // zero out the l_dimm_ranks_array so it is initialized for later use if there is a deconfigured MBA - for (uint8_t i = 0; i < l_NUM_MBAS; i++) - { - for (uint8_t j = 0; j < l_NUM_PORTS; j++) - { - for (uint8_t k = 0; k < l_NUM_DIMMS; k++) - { - l_dimm_ranks_array[i][j][k]=0; - } - } - - } - - for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){ - l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_target_mba_array[mba_index], l_mba_pos); - if (l_rc) return l_rc; - FAPI_INF("MBA_POS: %d", l_mba_pos); - - l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &l_target_mba_array[mba_index], l_dimm_ranks_array[l_mba_pos]); - if (l_rc) return l_rc; - FAPI_INF("EFF_NUM_RANKS: %d:%d:%d:%d", l_dimm_ranks_array[l_mba_pos][0][0], l_dimm_ranks_array[l_mba_pos][0][1], l_dimm_ranks_array[l_mba_pos][1][0], l_dimm_ranks_array[l_mba_pos][1][1]); - - l_rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &l_target_mba_array[mba_index], l_custom_dimm[l_mba_pos]); - if (l_rc) return l_rc; - FAPI_INF("ATTR_EFF_CUSTOM_DIMM: %d", l_custom_dimm[l_mba_pos]); - } - - // Get attributes for dimm temperature sensor mapping for only a custom dimm so we don't get an error - // Get attritute for custom dimms for enablement on the master i2c bus - if ((l_custom_dimm[0] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_custom_dimm[1] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)) - { - l_rc = FAPI_ATTR_GET(ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY, &i_target, l_cdimm_sensor_map_primary); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_VPD_CDIMM_SENSOR_MAP_SECONDARY, &i_target, l_cdimm_sensor_map_secondary); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE, NULL, l_master_i2c_temp_sensor_enable); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE, NULL, l_spare_i2c_temp_sensor_enable); - if (l_rc) return l_rc; - } - else - { - // sensor cache address map for non custom dimm temperature sensors (which i2c bus and i2c address they are) - l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, &i_target, l_dimm_sensor_cache_addr_map); - if (l_rc) return l_rc; - } - - // Configure Centaur Thermal Cache - - // --------------------------------- - // Clear the master enable bit - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_CONFIG, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.clearBit(0); //Master enable is bit 0 - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, SCAC_CONFIG, l_data); - if (l_rc) return l_rc; - - // --------------------------------- - // Mask FIR bit 33 - // Sets if any sensor cache addresses are written while the master enable is set - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_FIRMASK, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.setBit(33); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, SCAC_FIRMASK, l_data); - if (l_rc) return l_rc; - - // --------------------------------- - // Program PibTarget Register - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_PIBTARGET, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.insert(PRIMARY_I2C_BASE_ADDR, 0, 32, 0); - l_ecmd_rc |= l_data.insert(SPARE_I2C_BASE_ADDR, 32, 32, 0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, SCAC_PIBTARGET, l_data); - if (l_rc) return l_rc; - - // --------------------------------- - // Program I2CMCtrl Register - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_I2CMCTRL, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.insert(I2C_SETUP_UPPER_HALF, 0, 32, 0); - l_ecmd_rc |= l_data.insert(I2C_SETUP_LOWER_HALF, 32, 32, 0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, SCAC_I2CMCTRL, l_data); - if (l_rc) return l_rc; - - - // --------------------------------- - // Program Action Mask Register - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_ACTMASK, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.insert(ACT_MASK_UPPER_HALF, 0, 32, 0); - l_ecmd_rc |= l_data.insert(ACT_MASK_LOWER_HALF, 32, 32, 0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, SCAC_ACTMASK, l_data); - if (l_rc) return l_rc; - - - // --------------------------------- - // Program SensorCacheConfiguration Register - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_CONFIG, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.setBit(1); //Sync to OCC_Read signal - l_ecmd_rc |= l_data.insert(CONFIG_INTERVAL_TIMER, 11, 5, 32-5); - l_ecmd_rc |= l_data.insert(CONFIG_STALL_TIMER, 16, 8, 32-8); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(i_target, SCAC_CONFIG, l_data); - if (l_rc) return l_rc; - - // -------------------------------------------------------- - // Program SensorCacheEnable and SensorAddressMap Registers - // -------------------------------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_ENABLE, l_data_scac_enable); - if (l_rc) return l_rc; - - l_rc = fapiGetScom(i_target, SCAC_ADDRMAP, l_data_scac_addrmap); - if (l_rc) return l_rc; - - if ((l_custom_dimm[0] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_custom_dimm[1] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){ - - l_cdimm_number_dimm_temp_sensors = 0; - // cycle through both primary and secondary i2c busses, determine i2c address and enable bits - for (uint8_t k = 0; k < MAX_I2C_BUSSES; k++) - { - for (uint8_t i = 0; i < MAX_NUM_DIMM_SENSORS; i++) - { - if (k == 0) - { - l_i2c_bus_encode = I2C_BUS_ENCODE_PRIMARY; - l_cdimm_sensor_map = l_cdimm_sensor_map_primary; - } - else - { - l_i2c_bus_encode = I2C_BUS_ENCODE_SECONDARY; - l_cdimm_sensor_map = l_cdimm_sensor_map_secondary; - } - switch (i) - { - case 0: - l_sensor_map_mask = 0x01; - break; - case 1: - l_sensor_map_mask = 0x02; - break; - case 2: - l_sensor_map_mask = 0x04; - break; - case 3: - l_sensor_map_mask = 0x08; - break; - case 4: - l_sensor_map_mask = 0x10; - break; - case 5: - l_sensor_map_mask = 0x20; - break; - case 6: - l_sensor_map_mask = 0x40; - break; - case 7: - l_sensor_map_mask = 0x80; - break; - default: - l_sensor_map_mask = 0x00; - } - if ((l_cdimm_sensor_map & l_sensor_map_mask) != 0) - { - // Only enable the sensor for custom dimms based on the attributes - if ( - ( - (k==0) - && - (l_master_i2c_temp_sensor_enable == - ENUM_ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE_OFF) - ) - || - ( - (k==1) - && - (l_spare_i2c_temp_sensor_enable == - ENUM_ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE_OFF) - ) - ) - { - // do nothing here - do not enable the sensor - } - else - { - l_ecmd_rc |= l_data_scac_enable.setBit(l_cdimm_number_dimm_temp_sensors); - } - l_i2c_address_map = i + l_i2c_bus_encode; - l_data_scac_addrmap_offset = l_cdimm_number_dimm_temp_sensors * 4; - l_ecmd_rc |= l_data_scac_addrmap.insert(l_i2c_address_map, l_data_scac_addrmap_offset , 4, 4); - l_cdimm_number_dimm_temp_sensors++; - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - if (l_cdimm_number_dimm_temp_sensors > MAX_NUM_DIMM_SENSORS) - { - FAPI_ERR("Invalid number of dimm temperature sensors specified in the CDIMM VPD MW keyword"); - const fapi::Target & MEM_CHIP = i_target; - uint8_t FFDC_DATA_1 = l_cdimm_sensor_map_primary; - uint8_t FFDC_DATA_2 = l_cdimm_sensor_map_secondary; - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_CDIMM_INVALID_NUMBER_SENSORS); - return l_rc; - } - } - } - } - } - else{ - // Iterate through the num_ranks array to determine what DIMMs are plugged - // Enable sensor monitoring for each plugged DIMM - uint32_t l_iterator = 0; - for (uint32_t i = 0; i < l_NUM_MBAS; i++){ - if (l_dimm_ranks_array[i][0][0] != 0){ - l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator); - } - l_iterator++; - if (l_dimm_ranks_array[i][0][1] != 0){ - l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator); - } - l_iterator++; - if (l_dimm_ranks_array[i][1][0] != 0){ - l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator); - } - l_iterator++; - if (l_dimm_ranks_array[i][1][1] != 0){ - l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator); - } - l_iterator++; - } - l_ecmd_rc |= l_data_scac_addrmap.insert(l_dimm_sensor_cache_addr_map, 0, 32, 0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - } - - - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, SCAC_ENABLE, l_data_scac_enable); - if (l_rc) return l_rc; - - l_rc = fapiPutScom(i_target, SCAC_ADDRMAP, l_data_scac_addrmap); - if (l_rc) return l_rc; - - //--------------------------------- - // Reset the I2CM - //--------------------------------- - - ecmdDataBufferBase l_reset(64); - l_ecmd_rc |= l_reset.setBit(0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, I2CM_RESET, l_reset); - if (l_rc) return l_rc; - - // --------------------------------- - // Set the master enable bit - // --------------------------------- - - l_rc = fapiGetScom(i_target, SCAC_CONFIG, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.setBit(0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, SCAC_CONFIG, l_data); - if (l_rc) return l_rc; - - // Configure Centaur Thermal Cache COMPLETED - - - - // Disable Emergency Throttles - - // --------------------------------- - // Clear the emergency throttle FIR bit (MBS FIR 21) - // --------------------------------- - - l_rc = fapiGetScom(i_target, MBS_FIR_REG, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.clearBit(21); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, MBS_FIR_REG, l_data); - if (l_rc) return l_rc; - - - // --------------------------------- - // Reset emergency throttle in progress bit (EMER THROT 0) - // --------------------------------- - - l_rc = fapiGetScom(i_target, MBS_EMER_THROT, l_data); - if (l_rc) return l_rc; - - l_ecmd_rc |= l_data.clearBit(0); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - - l_rc = fapiPutScom(i_target, MBS_EMER_THROT, l_data); - if (l_rc) return l_rc; - - // Disable Emergency Throttles COMPLETED - - -// Write the IPL Safe Mode Throttles -// For centaur DD2 and above since OCC only writes runtime throttles for this - - uint8_t l_enable_safemode_throttle = 0; - l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_SAFEMODE_THROTTLE, &i_target, l_enable_safemode_throttle); - if (l_rc) return l_rc; - - if (l_enable_safemode_throttle) - { - uint32_t l_safemode_throttle_n_per_mba; - uint32_t l_safemode_throttle_n_per_chip; - uint32_t l_throttle_d; - - l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, NULL, l_safemode_throttle_n_per_mba); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, NULL, l_safemode_throttle_n_per_chip); - if (l_rc) return l_rc; - l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_THROTTLE_DENOMINATOR, NULL, l_throttle_d); - if (l_rc) return l_rc; -// write the N/M throttle control register - for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){ - l_rc = fapiGetScom(l_target_mba_array[mba_index], MBA01_MBA_FARB3Q_0x03010416, l_data); - if (l_rc) return l_rc; - l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_n_per_mba, 0, 15); - l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_n_per_chip, 15, 16); - l_ecmd_rc |= l_data.insertFromRight(l_throttle_d, 31, 14); - if(l_ecmd_rc) { - l_rc.setEcmdError(l_ecmd_rc); - return l_rc; - } - l_rc = fapiPutScom(l_target_mba_array[mba_index], MBA01_MBA_FARB3Q_0x03010416, l_data); - if (l_rc) return l_rc; - } - } - - FAPI_INF("*** mss_thermal_init COMPLETE ***"); - return l_rc; - - } //end mss_thermal_init - -} //end extern C - diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H deleted file mode 100644 index 191fe47af..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H +++ /dev/null @@ -1,88 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_thermal_init.H,v 1.1 2012/09/05 18:11:58 joabhend Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : mss_throttle_to_power.H -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Joab Henderson Email: joabhend@us.ibm.com -// *! BACKUP NAME : Michael Pardeik Email: pardeik@us.ibm.com -// *! ADDITIONAL COMMENTS : -// -// Header file for mss_thermal_init. -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.1 | joabhend |30-APR-12| First Draft. - - - -#ifndef MSS_THERMAL_INIT_H_ -#define MSS_THERMAL_INIT_H_ - -//---------------------------------------------------------------------- -// Includes -//---------------------------------------------------------------------- -#include <fapi.H> - -//---------------------------------------------------------------------- -// Defines -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// ENUMs -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// Data Types -//---------------------------------------------------------------------- - -typedef fapi::ReturnCode (*mss_thermal_init_FP_t)(const fapi::Target & i_target); - -extern "C" -{ - -/** - * @brief mss_thermal_init procedure. Configure and start the OCC cache and Centaur thermal cache - * - * @param[in] i_target Reference to centaur target - * - * @return ReturnCode - */ - - fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target); - -} // extern "C" - -#endif // MSS_THERMAL_INIT_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C b/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C deleted file mode 100644 index 786d21a76..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C +++ /dev/null @@ -1,71 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_exit_cache_contained.C,v 1.3 2014/02/10 04:49:54 stillgs Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_exit_cache_contained.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_exit_cache_contained.C -// *! DESCRIPTION : -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <proc_exit_cache_contained.H> - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// HWP entry point -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_exit_cache_contained() -{ - // return code - fapi::ReturnCode rc; - - // mark HWP entry - FAPI_IMP("proc_exit_cache_contained : Entering ..."); - - - // log function exit - FAPI_IMP("proc_exit_cache_contained : Exiting ..."); - return rc; -} - -} diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H b/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H deleted file mode 100644 index 614c8a7b3..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H +++ /dev/null @@ -1,70 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_exit_cache_contained.H,v 1.2 2014/02/10 04:49:53 stillgs Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_exit_cache_contained.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_exit_cache_contained.H -// *! DESCRIPTION : -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -// *! ADDITIONAL COMMENTS: -// *! -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_EXIT_CACHE_CONTAINED_H_ -#define _PROC_EXIT_CACHE_CONTAINED_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_exit_cache_contained_FP_t)(); - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -extern "C" -{ -fapi::ReturnCode proc_exit_cache_contained(); - -} // extern "C" - -#endif // _PROC_EXIT_CACHE_CONTAINED_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C deleted file mode 100644 index f189f668e..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C +++ /dev/null @@ -1,329 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_config.C,v 1.11 2015/06/29 01:47:49 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : proc_pcie_config.C -// *! DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapiHwpExecInitFile.H> -#include <proc_pcie_config.H> -#include <proc_a_x_pci_dmi_pll_setup.H> - -extern "C" { - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// function: apply PBCQ/AIB customization via SCOM initfile -// parameters: i_target => processor chip target -// returns: FAPI_RC_SUCCESS if initfile evaluation is successful, -// else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_pcie_config_pbcq( - const fapi::Target & i_target) -{ - fapi::ReturnCode rc; - std::vector<fapi::Target> targets; - - // mark function entry - FAPI_INF("proc_pcie_config_pbcq: Start"); - - do - { - // execute Phase2 SCOM initfile - targets.push_back(i_target); - FAPI_INF("proc_pcie_config_pbcq: Executing %s on %s", - PROC_PCIE_CONFIG_PHASE2_IF, i_target.toEcmdString()); - FAPI_EXEC_HWP( - rc, - fapiHwpExecInitFile, - targets, - PROC_PCIE_CONFIG_PHASE2_IF); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq: Error from fapiHwpExecInitfile executing %s on %s", - PROC_PCIE_CONFIG_PHASE2_IF, - i_target.toEcmdString()); - break; - } - } while(0); - - // mark function exit - FAPI_INF("proc_pcie_config_pbcq: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: initialize PBCQ FIRs -// clear FIR/WOF -// initialize FIR action settings -// reset FIR masks -// parameters: i_target => processor chip target -// i_num_phb => number of PHB units -// returns: FAPI_RC_SUCCESS if all actions are successful, -// else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_pcie_config_pbcq_fir( - const fapi::Target & i_target, - uint8_t i_num_phb) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - ecmdDataBufferBase data(64); - - // mark function entry - FAPI_INF("proc_pcie_config_pbcq_fir: Start"); - - // loop over all PHBs - for (size_t i = 0; i < i_num_phb; i++) - { - // clear FIR - rc_ecmd |= data.flushTo0(); - if (rc_ecmd) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR clear data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_target, - PROC_PCIE_CONFIG_PCIE_NEST_FIR[i], - data); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_0x%08X)", - i, PROC_PCIE_CONFIG_PCIE_NEST_FIR[i]); - break; - } - - // clear FIR WOF - rc = fapiPutScom(i_target, - PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i], - data); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_WOF_0x%08X)", - i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i]); - break; - } - - // set action0 - rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL); - if (rc_ecmd) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action0 register data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(i_target, - PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i], - data); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION0_0x%08X)", - i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i]); - break; - } - - // set action1 - rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL); - if (rc_ecmd) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action1 register data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(i_target, - PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i], - data); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION1_0x%08X)", - i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i]); - break; - } - - // set action2 - fapi::ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT_Type action2_present = 0; - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT, &i_target, action2_present); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: fapiGetAttribute of ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT failed"); - break; - } - if (action2_present) - { - rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2_VAL); - if (rc_ecmd) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action2 register data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(i_target, - PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[i], - data); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION2_0x%08X)", - i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[i]); - break; - } - } - - // set mask - rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL); - if (rc_ecmd) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Mask register data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(i_target, - PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i], - data); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_MASK_0x%08X)", - i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i]); - break; - } - } - - // mark function exit - FAPI_INF("proc_pcie_config_pbcq_fir: End"); - return rc; -} - - -// HWP entry point, comments in header -fapi::ReturnCode proc_pcie_config( - const fapi::Target & i_target) -{ - fapi::ReturnCode rc; - uint8_t pcie_enabled; - uint8_t num_phb; - - // mark HWP entry - FAPI_INF("proc_pcie_config: Start"); - - do - { - // check for supported target type - if (i_target.getType() != fapi::TARGET_TYPE_PROC_CHIP) - { - FAPI_ERR("proc_pcie_config: Unsupported target type"); - const fapi::Target & TARGET = i_target; - FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_CONFIG_INVALID_TARGET); - break; - } - - // query PCIE partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, - &i_target, - pcie_enabled); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config: Error querying ATTR_PROC_PCIE_ENABLE"); - break; - } - - // initialize PBCQ/AIB, configure PBCQ FIRs (only if partial good - // atttribute is set) - if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) - { - // determine PHB configuration - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, - &i_target, - num_phb); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)"); - break; - } - - rc = proc_pcie_config_pbcq(i_target); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq"); - break; - } - - rc = proc_pcie_config_pbcq_fir(i_target, num_phb); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq_fir"); - break; - } - - rc = proc_a_x_pci_dmi_pll_setup_unmask_lock( - i_target, - PCIE_CHIPLET_0x09000000); - if (!rc.ok()) - { - FAPI_ERR("proc_pcie_config: Error from proc_a_x_pci_dmi_pll_setup_unmask_lock"); - break; - } - } - else - { - FAPI_DBG("proc_pcie_config: Skipping initialization (partial good)"); - } - - } while(0); - - // mark HWP exit - FAPI_INF("proc_pcie_config: End"); - return rc; -} - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H deleted file mode 100644 index 63339f41d..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H +++ /dev/null @@ -1,142 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_pcie_config.H,v 1.7 2015/07/01 21:15:04 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! TITLE : proc_pcie_config.H -// *! DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -// *! ADDITIONAL COMMENTS : -// *! Configure PBCQ/AIB registers -// *! Clear PBCQ FIRs, setup for runtime -// *! -//------------------------------------------------------------------------------ - -#ifndef PROC_PCIE_CONFIG_H_ -#define PROC_PCIE_CONFIG_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> -#include <p8_scom_addresses.H> - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// SCOM initfile to execute -const char * const PROC_PCIE_CONFIG_PHASE2_IF = "p8.pe.phase2.scom.if"; - -// PCIe physical constants -const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 4; - -const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR[PROC_PCIE_CONFIG_NUM_PHB] = -{ - PCIE0_FIR_0x02012000, - PCIE1_FIR_0x02012400, - PCIE2_FIR_0x02012800, - PCIE3_FIR_0x02012C00 -}; - -const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[PROC_PCIE_CONFIG_NUM_PHB] = -{ - PCIE0_FIR_WOF_0x02012008, - PCIE1_FIR_WOF_0x02012408, - PCIE2_FIR_WOF_0x02012808, - PCIE3_FIR_WOF_0x02012C08 -}; - -const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[PROC_PCIE_CONFIG_NUM_PHB] = -{ - PCIE0_FIR_ACTION0_0x02012006, - PCIE1_FIR_ACTION0_0x02012406, - PCIE2_FIR_ACTION0_0x02012806, - PCIE3_FIR_ACTION0_0x02012C06 -}; - -const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[PROC_PCIE_CONFIG_NUM_PHB] = -{ - PCIE0_FIR_ACTION1_0x02012007, - PCIE1_FIR_ACTION1_0x02012407, - PCIE2_FIR_ACTION1_0x02012807, - PCIE3_FIR_ACTION1_0x02012C07 -}; - -const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[PROC_PCIE_CONFIG_NUM_PHB] = -{ - PCIE0_FIR_ACTION2_0x02012020, - PCIE1_FIR_ACTION2_0x02012420, - PCIE2_FIR_ACTION2_0x02012820, - PCIE3_FIR_ACTION2_0x02012C20 -}; - -const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] = -{ - PCIE0_FIR_MASK_0x02012003, - PCIE1_FIR_MASK_0x02012403, - PCIE2_FIR_MASK_0x02012803, - PCIE3_FIR_MASK_0x02012C03 -}; - -const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL = 0x5B0F819000000000ULL; -const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL = 0x7F0F819000000000ULL; -const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2_VAL = 0xEFF07E0800000000ULL; -const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL = 0x0030006E00000000ULL; - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_pcie_config_FP_t)(const fapi::Target & i_target); - -extern "C" { - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) -// parameters: i_target => processor chip target -// returns: FAPI_RC_SUCCESS if all programming is successful, -// RC_PROC_PCIE_CONFIG_INVALID_TARGET if invalid target is supplied, -// else error -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_pcie_config(const fapi::Target & i_target); - - -} // extern "C" - -#endif // PROC_PCIE_CONFIG_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C deleted file mode 100644 index ecf7279fe..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C +++ /dev/null @@ -1,788 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_setup_bars.C,v 1.45 2015/04/24 06:25:04 gpaulraj Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2012 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! -// *! TITLE : mss_setup_bars.C -// *! DESCRIPTION : Program MCS base address registers (BARs) (FAPI) -// *! -// *! OWNER NAME : Girisankar Paulraj Email: gpaulraj@in.ibm.com -// *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com -// *! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.45 | gpaulraj | 04/24/15| fix for SW304630 -// 1.43 | gpaulraj | 03/19/15| fix SW296125 - modified k as k = 0 -// 1.42 | gpaulraj | 05/21/14| fixed on 1 MCS mirror BAR EN issue -SW261358 -// 1.40 | gpaulraj | 05/06/14| fixed on mirror configuration issue -// 1.39 | gpaulraj | 04/08/14| 5/5 FW review feedback - gerrit process - SW251227 -// 1.33 | | 03/09/14| RAS review -// 1.32 | gpaulraj | 08/16/13| fixed code -// 1.31 | gpaulraj | 08/13/13| fix HW259884 Mirror BAR Scom Parity Error -// 1.30 | gpaulraj | 08/13/13| added fix HW259884 Mirror BAR Scom Parity Error -// 1.29 | gpaulraj | 08/12/13| fixed mirror BAR issues -// 1.27 | jmcgill | 05/21/13| address FW review issues -// 1.26 | jmcgill | 04/22/13| rewrite to line up with attribute changes -// 1.23 | bellows | 12/04/12| more updates -// 1.22 | gpaulraj | 10/03/12| review updates -// 1.21 | gpaulraj | 10/02/12| review updates -// 1.19 | bellows | 09/25/12| review updates -// 1.18 | bellows | 09/06/12| updates suggested by Van -// 1.17 | bellows | 08/31/12| use the final 32bit attribute -// 1.16 | bellows | 08/29/12| remove compile error, use 32bit group info -// | | | as a temporary fix -// 1.10 | bellows | 07/16/12| added in Id tag -// 1.4 | bellows | 06-05-12| Updates to Match First Configuration, work for -// | | | P8 and Murano -// 1.3 | gpaulraj | 05-22-12| 2MCS/group supported for 128GB CDIMM -// 1.2 | gpaulraj | 05-07-12| 256 group configuration in -// 1.1 | gpaulraj | 03-19-12| First drop for centaur -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <mss_setup_bars.H> - - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - -extern "C" { - - -const int SETUP_BARS_MBA_SIZE_MCS=8; -const int SETUP_BARS_MBA_SIZE_PORT=2; -struct MssSetupBarsSizeInfo{ - uint8_t MBA_size[SETUP_BARS_MBA_SIZE_MCS][SETUP_BARS_MBA_SIZE_PORT]; // mcs, mba pairs, port, dimm - uint32_t MCS_size[SETUP_BARS_MBA_SIZE_MCS]; -}; - -//------------------------------------------------------------------------------ -// function: write non-mirrored BAR registers (MCFGP/MCFGPA) for a single MCS -// parameters: i_mcs_target => MCS chiplet target -// i_pri_valid => true if MCS primary non-mirrored BAR -// should be marked valid -// i_group_member_id => group member ID (only valid if -// i_pri_valid=true) -// i_group_data => MSS_MCS_GROUP_32 attribute data -// for member group (only valid if -// i_pri_valid=true) -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_setup_bars_init_nm_bars( - const fapi::Target& i_mcs_target, - bool i_pri_valid, - uint32_t i_group_member_id, - uint32_t i_group_data[]) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - ecmdDataBufferBase MCFGP(64); - ecmdDataBufferBase MCFGPA(64); - - // Defect HW259884 (AddNote by retter) P8 Lab Brazos: Mirror BAR Scom Parity Error - workaround - ecmdDataBufferBase MCIFIR(64); - ecmdDataBufferBase MCIFIRMASK(64); - ecmdDataBufferBase MCSMODE4(64); - - do - { - rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - // Mask MCIFIR bit 25 - rc_ecmd |= MCIFIRMASK.setBit(25); - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCIFIRMASK data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - - // establish base content for MCFGP register - rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_RCMD0_BIT); - rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_RCMD1_BIT); - rc_ecmd |= MCFGP.setBit(MCFGP_RSVD_1_BIT); - rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_FASTPATH_BIT); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGP base data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - if (i_pri_valid) - { - // MCFGPQ_VALID - rc_ecmd |= MCFGP.setBit(MCFGP_VALID_BIT); - // MCFGPQ_MCS_UNITS_PER_GROUP - rc_ecmd |= MCFGP.insertFromRight( - i_group_data[MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX] / 2, - MCFGP_MCS_UNITS_PER_GROUP_START_BIT, - (MCFGP_MCS_UNITS_PER_GROUP_END_BIT- - MCFGP_MCS_UNITS_PER_GROUP_START_BIT)+1); - // MCFGPQ_GROUP_MEMBER_IDENTIFICATION - rc_ecmd |= MCFGP.insertFromRight( - i_group_member_id, - MCFGP_GROUP_MEMBER_ID_START_BIT, - (MCFGP_GROUP_MEMBER_ID_END_BIT- - MCFGP_GROUP_MEMBER_ID_START_BIT)+1); - // MCFGPQ_GROUP_SIZE - rc_ecmd |= MCFGP.insertFromRight( - (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/4)-1, - MCFGP_GROUP_SIZE_START_BIT, - (MCFGP_GROUP_SIZE_END_BIT- - MCFGP_GROUP_SIZE_START_BIT)+1); - - // MCFGPQ_BASE_ADDRESS_OF_GROUP - rc_ecmd |= MCFGP.insertFromRight( - i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] >> 2, - MCFGP_BASE_ADDRESS_START_BIT, - (MCFGP_BASE_ADDRESS_END_BIT- - MCFGP_BASE_ADDRESS_START_BIT)+1); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGP data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - bool alt_valid = i_group_data[MSS_MCS_GROUP_32_ALT_VALID_INDEX]; - if (alt_valid) - { - if (i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] != - (i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] + - (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/2))) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Invalid non-mirrored alternate BAR configuration"); - const uint32_t & ALT_BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX]; - const uint32_t & BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_BASE_INDEX]; - const uint32_t & SIZE_INDEX= i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]; - FAPI_SET_HWP_ERROR(rc, - RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR); - break; - } - - // MCFGPAQ_VALID - rc_ecmd |= MCFGPA.setBit(MCFGPA_VALID_BIT); - - // MCFGPAQ_GROUP_SIZE - rc_ecmd |= MCFGPA.insertFromRight( - (i_group_data[MSS_MCS_GROUP_32_ALT_SIZE_INDEX]/4)-1, - MCFGPA_GROUP_SIZE_START_BIT, - (MCFGPA_GROUP_SIZE_END_BIT- - MCFGPA_GROUP_SIZE_START_BIT)+1); - - // MCFGPAQ_BASE_ADDRESS_OF_GROUP - rc_ecmd |= MCFGPA.insertFromRight( - i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] >> 2, - MCFGPA_BASE_ADDRESS_START_BIT, - (MCFGPA_BASE_ADDRESS_END_BIT- - MCFGPA_BASE_ADDRESS_START_BIT)+1); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGPA data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - } - - // write registers - rc = fapiPutScom(i_mcs_target, MCS_MCFGP_0x02011800, MCFGP); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCFGP_0x02011800)"); - break; - } - - rc = fapiPutScom(i_mcs_target, MCS_MCFGPA_0x02011814, MCFGPA); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCFGPA_0x02011814)"); - break; - } - - rc = fapiGetScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCSMODE4_0x0201181A"); - break; - } - // set MCSMODE4 bit 0 - rc_ecmd |= MCSMODE4.setBit(0); - rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A"); - break; - } - // Clear MCSMODE4 bit 0 - rc_ecmd |= MCSMODE4.clearBit(0); - rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A"); - break; - } - - rc = fapiGetScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCIFIR_0x02011840"); - break; - } - // Reset MCIFIR bit 25 - rc_ecmd |= MCIFIR.clearBit(25); - rc = fapiPutScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCIFIR_0x02011840"); - break; - } - - rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - // Unmask MCIFIR bit 25 - rc_ecmd |= MCIFIRMASK.clearBit(25); - rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - } while(0); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: write mirrored BAR registers (MCFGPM/MCFGPMA) for a single MCS -// parameters: i_mcs_target => MCS chiplet target -// i_pri_valid => true if MCS primary mirrored BAR -// should be marked valid -// i_group_data => MSS_MCS_GROUP_32 attribute data -// for member group (only valid if -// i_pri_valid=true) -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_setup_bars_init_m_bars( - const fapi::Target& i_mcs_target, - bool i_pri_valid, - uint32_t i_group_data[]) -{ - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - ecmdDataBufferBase MCFGPM(64); - ecmdDataBufferBase MCFGPMA(64); - - // Defect HW259884 (AddNote by retter) P8 Lab Brazos: Mirror BAR Scom Parity Error - workaround - ecmdDataBufferBase MCIFIR(64); - ecmdDataBufferBase MCIFIRMASK(64); - ecmdDataBufferBase MCSMODE4(64); - do - { - - rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - // Mask MCIFIR bit 25 - rc_ecmd |= MCIFIRMASK.setBit(25); - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCIFIRMASK data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - if (i_pri_valid) - { - - // MCFGPMQ_VALID - rc_ecmd |= MCFGPM.setBit(MCFGPM_VALID_BIT); - // MCFGPMQ_GROUP_SIZE - rc_ecmd |= MCFGPM.insertFromRight( - (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/4)-1, - MCFGPM_GROUP_SIZE_START_BIT, - (MCFGPM_GROUP_SIZE_END_BIT- - MCFGPM_GROUP_SIZE_START_BIT)+1); - - // MCFGPMQ_BASE_ADDRESS_OF_GROUP - rc_ecmd |= MCFGPM.insertFromRight( - i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] >> 2, - MCFGPM_BASE_ADDRESS_START_BIT, - (MCFGPM_BASE_ADDRESS_END_BIT- - MCFGPM_BASE_ADDRESS_START_BIT)+1); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCFGPM data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - bool alt_valid = i_group_data[MSS_MCS_GROUP_32_ALT_VALID_INDEX]; - if (alt_valid) - { - // MCFGPMAQ_VALID - rc_ecmd |= MCFGPMA.setBit(MCFGPMA_VALID_BIT); - - // MCFGPMAQ_GROUP_SIZE - rc_ecmd |= MCFGPMA.insertFromRight( - (i_group_data[MSS_MCS_GROUP_32_ALT_SIZE_INDEX]/4)-1, - MCFGPMA_GROUP_SIZE_START_BIT, - (MCFGPMA_GROUP_SIZE_END_BIT- - MCFGPMA_GROUP_SIZE_START_BIT)+1); - - // MCFGPMAQ_BASE_ADDRESS_OF_GROUP - rc_ecmd |= MCFGPMA.insertFromRight( - i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] >> 2, - MCFGPMA_BASE_ADDRESS_START_BIT, - (MCFGPMA_BASE_ADDRESS_END_BIT- - MCFGPMA_BASE_ADDRESS_START_BIT)+1); - - if (i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] != - (i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] + - (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/2))) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Invalid mirrored alternate BAR configuration"); - const uint32_t & ALT_BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX]; - const uint32_t & BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_BASE_INDEX]; - const uint32_t & SIZE_INDEX= i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]; - FAPI_SET_HWP_ERROR(rc, - RC_MSS_SETUP_BARS_M_ALT_BAR_ERR); - break; - } - } - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCFGPMA data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - - // write registers - rc = fapiPutScom(i_mcs_target, MCS_MCFGPM_0x02011801, MCFGPM); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCFGPM_0x02011801)"); - break; - } - rc = fapiPutScom(i_mcs_target, MCS_MCFGPMA_0x02011815, MCFGPMA); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCFGPMA_0x02011815"); - break; - } - - rc = fapiGetScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCSMODE4_0x0201181A"); - break; - } - // set MCSMODE4 bit 0 - rc_ecmd |= MCSMODE4.setBit(0); - rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A"); - break; - } - // Clear MCSMODE4 bit 0 - rc_ecmd |= MCSMODE4.clearBit(0); - rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A"); - break; - } - - rc = fapiGetScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIR_0x02011840"); - break; - } - // Reset MCIFIR bit 25 - rc_ecmd |= MCIFIR.clearBit(25); - rc = fapiPutScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIR_0x02011840"); - break; - } - - rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - // Unmask MCIFIR bit 25 - rc_ecmd |= MCIFIRMASK.clearBit(25); - rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843"); - break; - } - } while(0); - - return rc; -} - - -//------------------------------------------------------------------------------ -// function: mss_setup_bars_mcs_size -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_setup_bars_mcs_size( const fapi::Target & i_target,std::vector<fapi::Target> & i_associated_centaurs, MssSetupBarsSizeInfo & io_sizeInfo) -{ - fapi::ReturnCode rc; - uint8_t centaur; - uint8_t mba_i; - uint8_t mba=0; - uint8_t dimm=0; - uint32_t cenpos; - uint32_t procpos; - uint8_t port; - uint32_t l_unit_pos =0; - uint8_t min_group = 1; - uint8_t mba_pos[2][2] = { {0, 0},{0,0}}; - std::vector<fapi::Target> l_mba_chiplets; - uint8_t cen_count=0; - rc = FAPI_ATTR_GET(ATTR_POS,&i_target, procpos); - if(rc) return rc; - for(centaur= 0; centaur < i_associated_centaurs.size(); centaur++) { - mba=0;port=0;dimm=0; - fapi::Target & centaur_t = i_associated_centaurs[centaur]; - rc = FAPI_ATTR_GET(ATTR_POS,¢aur_t, cenpos); - if(rc) return rc; - if(cenpos>=procpos*8 && cenpos<(procpos*8+8)){ - FAPI_INF("... working on centaur %d", cenpos); - io_sizeInfo.MCS_size[cenpos - procpos * 8]=0; - rc = fapiGetChildChiplets(i_associated_centaurs[centaur], fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets); - if(rc) return rc; - for(mba_i=0; mba_i<l_mba_chiplets.size(); mba_i++) { - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[mba_i], mba); - if(rc) return rc; - FAPI_INF("... working on mba %d", mba); - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[mba_i],mba_pos); - if(rc) return rc; - for(port = 0; port<2; port++) - { - for(dimm=0; dimm<2; dimm++) { - io_sizeInfo.MCS_size[cenpos - procpos * 8]+=mba_pos[port][dimm]; - io_sizeInfo.MBA_size[cenpos - procpos * 8][mba] += mba_pos[port][dimm]; - } - } - - FAPI_INF(" Cen Pos %d mba %d DIMM SIZE %d \n",cenpos,mba, io_sizeInfo.MBA_size[cenpos - procpos * 8][mba]); - FAPI_INF(" Cen Pos %d MBA SIZE %d %d %d %d \n",cenpos, mba_pos[0][0],mba_pos[0][1],mba_pos[1][0],mba_pos[1][1]); - FAPI_INF(" MCS SIZE %d\n",io_sizeInfo.MCS_size[cenpos - procpos * 8]); - } - cen_count++;l_unit_pos++; - } - } - FAPI_INF("attr_mss_setting %d and no of MBAs %d \n",min_group,l_unit_pos); - return rc; -} - -//------------------------------------------------------------------------------ -// function: mss_setup_bars HWP entry point -// NOTE: see comments above function prototype in header -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target, std::vector<fapi::Target> & i_associated_centaurs) -{ - fapi::ReturnCode rc; - std::vector<fapi::Target> l_mcs_chiplets; - uint32_t group_data[16][16]; - uint8_t M_valid; - MssSetupBarsSizeInfo sizeInfo; - do - { - - rc= mss_setup_bars_mcs_size(i_pu_target,i_associated_centaurs, sizeInfo); - // obtain group configuration attribute for this chip - rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, &i_pu_target, group_data); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error reading ATTR_MSS_MCS_GROUP_32"); - break; - } - rc = FAPI_ATTR_GET(ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING, NULL, M_valid); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error reading ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING"); - break; - } - - - //check if all the grouped mcs are valid - for (size_t i = MSS_MCS_GROUP_32_NM_START_INDEX; - (i <= MSS_MCS_GROUP_32_NM_END_INDEX); - i++) - { - // only process valid groups - if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0) - { - continue; - } - - uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX]; - - uint32_t mcs_sz = group_data[i][0]; - for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX; - (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group); - j++) - { - if(mcs_sz != sizeInfo.MCS_size[group_data[i][j]]) - { - FAPI_INF(" Group %zd will not be configured as MCS %d is not valid grouped size is %d , present MCS size is %d \n",i,group_data[i][j],mcs_sz, sizeInfo.MCS_size[group_data[i][j]]); - for(uint8_t k = 0; k<16;k++) { group_data[i][k]=0; } - } - } - } - // get child MCS chiplets - rc = fapiGetChildChiplets(i_pu_target, - fapi::TARGET_TYPE_MCS_CHIPLET, - l_mcs_chiplets, - fapi::TARGET_STATE_FUNCTIONAL); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error from fapiGetChildChiplets"); - break; - } - - // loop through & set configuration of each MCS chiplet - for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin(); - iter != l_mcs_chiplets.end(); - iter++) - { - // obtain MCS chip unit number - uint8_t mcs_pos = 0x0; - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error reading ATTR_CHIP_UNIT_POS"); - break; - } - - // determine non-mirrored member group - bool nm_bar_valid = false; - uint8_t nm_bar_group_index = 0x0; - uint8_t nm_bar_group_member_id = 0x0; - for (size_t i = MSS_MCS_GROUP_32_NM_START_INDEX; - (i <= MSS_MCS_GROUP_32_NM_END_INDEX); - i++) - { - // only process valid groups - if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0) - { - continue; - } - - uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX]; - - - for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX; - (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group); - j++) - { - if (mcs_pos == group_data[i][j]) - { - if (nm_bar_valid) - { - const uint8_t& MCS_POS = mcs_pos; - const uint8_t& GROUP_INDEX_A = nm_bar_group_index; - const uint8_t& GROUP_INDEX_B = i; - FAPI_ERR("mss_setup_bars: MCS %d is listed as a member in multiple non-mirrored groups", - mcs_pos); - FAPI_SET_HWP_ERROR( - rc, - RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR); - break; - } - nm_bar_valid = true; - nm_bar_group_index = i; - nm_bar_group_member_id = - j-MSS_MCS_GROUP_32_MEMBERS_START_INDEX; - } - } - if (!rc.ok()) - { - break; - } - } - if (!rc.ok()) - { - break; - } - - // write non-mirrored BARs based on group configuration - rc = mss_setup_bars_init_nm_bars( - *iter, - nm_bar_valid, - nm_bar_group_member_id, - group_data[nm_bar_group_index]); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error from mss_setup_bars_init_nm_bars"); - break; - } - - // determine mirrored member group - if(!M_valid) - { - bool m_bar_valid = false; - uint8_t m_bar_group_index = 0x0; - for (size_t i = MSS_MCS_GROUP_32_M_START_INDEX; - (i <= MSS_MCS_GROUP_32_M_END_INDEX); - i++) - { - // only process valid groups - if (group_data[i-8][MSS_MCS_GROUP_32_SIZE_INDEX] == 0) - { - continue; - } - - uint32_t mcs_in_group = group_data[i-8][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX]; - if( mcs_in_group > 1) - { - for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX; - (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group); - j++) - { - if (mcs_pos == group_data[i-8][j]) - { - if (m_bar_valid) - { - const uint8_t& MCS_POS = mcs_pos; - const uint8_t& GROUP_INDEX_A = m_bar_group_index; - const uint8_t& GROUP_INDEX_B = i; - FAPI_ERR("mss_setup_bars: MCS %d is listed as a member in multiple mirrored groups", - mcs_pos); - FAPI_SET_HWP_ERROR( - rc, - RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR); - break; - } - m_bar_valid = true; - m_bar_group_index = i; - } - } - if (!rc.ok()) - { - break; - } - } - } - if (!rc.ok()) - { - break; - } - // write mirrored BARs based on group configuration - rc = mss_setup_bars_init_m_bars( - *iter, - m_bar_valid, - group_data[m_bar_group_index]); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error from mss_setup_bars_init_m_bars"); - break; - } - } - // write attribute signifying BARs are valid & MSS inits are finished - uint8_t final = 1; - rc = FAPI_ATTR_SET(ATTR_MSS_MEM_IPL_COMPLETE, &i_pu_target, final); - if (!rc.ok()) - { - FAPI_ERR("mss_setup_bars: Error from FAPI_ATTR_SET (ATTR_MSS_MEM_IPL_COMPLETE)"); - break; - } - - } - } while(0); - - return rc; -} - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H deleted file mode 100644 index ed59991f5..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H +++ /dev/null @@ -1,149 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: mss_setup_bars.H,v 1.9 2014/04/08 16:04:12 gpaulraj Exp $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -//------------------------------------------------------------------------------ -// *! -// *! TITLE : mss_setup_bars.C -// *! DESCRIPTION : Program MCS base address registers (BARs) (FAPI) -// *! -// *! OWNER NAME : Girisankar Paulraj Email: gpaulraj@in.ibm.com -// *! OWNER NAME : Mark Bellows Email: bellows@us.ibm.com -// *! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.9 | gpaulraj | 04/08/14| 5/5 FW review feedback - gerrit process - SW251227 -// 1.4 | jdsloat | 03/13/14| changed const names to stop interfering with eff_grouping -// 1.3 | bellows | 07/16/12| added in ID tag -// 1.1 | gpaulraj | 03/19/12| Updated -//------------------------------------------------------------------------------ - -#ifndef MSS_SETUP_BARS_H_ -#define MSS_SETUP_BARS_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ - -#include <fapi.H> -#include "p8_scom_addresses.H" - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// MCFGP bit/field definitions -const uint32_t MCFGP_VALID_BIT = 0; -const uint32_t MCFGP_MCS_UNITS_PER_GROUP_START_BIT = 1; -const uint32_t MCFGP_MCS_UNITS_PER_GROUP_END_BIT = 3; -const uint32_t MCFGP_GROUP_MEMBER_ID_START_BIT = 4; -const uint32_t MCFGP_GROUP_MEMBER_ID_END_BIT = 8; -const uint32_t MCFGP_ENABLE_RCMD0_BIT = 9; -const uint32_t MCFGP_ENABLE_RCMD1_BIT = 10; -const uint32_t MCFGP_GROUP_SIZE_START_BIT = 11; -const uint32_t MCFGP_GROUP_SIZE_END_BIT = 23; -const uint32_t MCFGP_RSVD_1_BIT = 24; -const uint32_t MCFGP_ENABLE_FASTPATH_BIT = 25; -const uint32_t MCFGP_BASE_ADDRESS_START_BIT = 26; -const uint32_t MCFGP_BASE_ADDRESS_END_BIT = 43; - -// MCFGPA bit/field defintions -const uint32_t MCFGPA_VALID_BIT = 0; -const uint32_t MCFGPA_GROUP_SIZE_START_BIT = 11; -const uint32_t MCFGPA_GROUP_SIZE_END_BIT = 23; -const uint32_t MCFGPA_BASE_ADDRESS_START_BIT = 26; -const uint32_t MCFGPA_BASE_ADDRESS_END_BIT = 43; - -// MCFGPM bit/field definitions -const uint32_t MCFGPM_VALID_BIT = 0; -const uint32_t MCFGPM_GROUP_SIZE_START_BIT = 11; -const uint32_t MCFGPM_GROUP_SIZE_END_BIT = 23; -const uint32_t MCFGPM_BASE_ADDRESS_START_BIT = 26; -const uint32_t MCFGPM_BASE_ADDRESS_END_BIT = 43; - -// MCFGPMA bit/field definitions -const uint32_t MCFGPMA_VALID_BIT = 0; -const uint32_t MCFGPMA_GROUP_SIZE_START_BIT = 11; -const uint32_t MCFGPMA_GROUP_SIZE_END_BIT = 23; -const uint32_t MCFGPMA_BASE_ADDRESS_START_BIT = 26; -const uint32_t MCFGPMA_BASE_ADDRESS_END_BIT = 43; - -// attribute index constants -// first array dimension (group ID) -const uint8_t MSS_MCS_GROUP_32_NM_START_INDEX = 0; -const uint8_t MSS_MCS_GROUP_32_NM_END_INDEX = 7; -const uint8_t MSS_MCS_GROUP_32_M_START_INDEX = 8; -const uint8_t MSS_MCS_GROUP_32_M_END_INDEX = 15; - -// second array dimension (group definition) -const uint8_t MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX = 1; -const uint8_t MSS_MCS_GROUP_32_SIZE_INDEX = 2; -const uint8_t MSS_MCS_GROUP_32_BASE_INDEX = 3; -const uint8_t MSS_MCS_GROUP_32_MEMBERS_START_INDEX = 4; -const uint8_t MSS_MCS_GROUP_32_ALT_VALID_INDEX = 12; -const uint8_t MSS_MCS_GROUP_32_ALT_SIZE_INDEX = 13; -const uint8_t MSS_MCS_GROUP_32_ALT_BASE_INDEX = 14; - - - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode (*mss_setup_bars_FP_t)(const fapi::Target& i_pu_target, std::vector<fapi::Target> & i_associated_centaurs); - - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -extern "C" -{ - -//------------------------------------------------------------------------------ -// function: program MCS base address registers (BARs) -// writes non-mirrored (MCFGP/MCFGPA) & -// mirrored BAR registers (MCFGPM/MCFGPMA) -// parameters: i_pu_target => chip level target -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR if a child MCS is listed -// as a member in multiple groups -// else failing return code -//------------------------------------------------------------------------------ -fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target, std::vector<fapi::Target> & i_associated_centaurs); - - -} // extern "C" - -#endif // MSS_SETUP_BARS_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C deleted file mode 100644 index 487def4a2..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C +++ /dev/null @@ -1,329 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_fab_smp.C,v 1.9 2014/01/27 05:22:07 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_fab_smp.C -// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <proc_fab_smp.H> - -extern "C" { - - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// function: utility function to read & return fabric node ID attribute -// parameters: i_target => pointer to chip/chiplet target -// o_node_id => node ID value -// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, -// RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is -// invalid, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_smp_get_node_id_attr( - const fapi::Target* i_target, - proc_fab_smp_node_id& o_node_id) -{ - // return code - fapi::ReturnCode rc; - // chiplet->chip target conversion - bool use_parent = false; - fapi::Target parent_target; - // temporary attribute storage used to build procedure data structures - uint8_t node_id_attr; - - // mark function entry - FAPI_DBG("proc_fab_smp_get_node_id_attr: Start"); - - do - { - if (i_target->getType() != fapi::TARGET_TYPE_PROC_CHIP) - { - use_parent = true; - // retrieve parent target if input target is a chiplet - rc = fapiGetParentChip(*i_target, - parent_target); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_smp_get_node_id_attr: Error from fapiGetParentChip"); - break; - } - } - - // retrieve node ID attribute - rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID, - ((use_parent)? - (&parent_target): - (i_target)), - node_id_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_smp_get_node_id_attr: Error querying ATTR_FABRIC_NODE_ID"); - break; - } - - // print attribute value - FAPI_DBG("proc_fab_smp_get_node_id_attr: ATTR_FABRIC_NODE_ID = 0x%X", - node_id_attr); - - // translate to output value - switch (node_id_attr) - { - case 0: - o_node_id = FBC_NODE_ID_0; - break; - case 1: - o_node_id = FBC_NODE_ID_1; - break; - case 2: - o_node_id = FBC_NODE_ID_2; - break; - case 3: - o_node_id = FBC_NODE_ID_3; - break; - case 4: - o_node_id = FBC_NODE_ID_4; - break; - case 5: - o_node_id = FBC_NODE_ID_5; - break; - case 6: - o_node_id = FBC_NODE_ID_6; - break; - case 7: - o_node_id = FBC_NODE_ID_7; - break; - default: - FAPI_ERR("proc_fab_smp_get_node_id_attr: Invalid fabric node ID attribute value 0x%02X", - node_id_attr); - const fapi::Target & TARGET = *i_target; - const uint8_t& ATTR_DATA = node_id_attr; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR); - break; - } - } while(0); - - // mark function exit - FAPI_DBG("proc_fab_smp_get_node_id_attr: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility function to read & return fabric chip ID attribute -// parameters: i_target => pointer to chip/chiplet target -// o_chip_id => chip ID value -// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, -// RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is -// invalid, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_smp_get_chip_id_attr( - const fapi::Target* i_target, - proc_fab_smp_chip_id& o_chip_id) -{ - // return code - fapi::ReturnCode rc; - // chiplet->chip target conversion - bool use_parent = false; - fapi::Target parent_target; - // temporary attribute storage used to build procedure data structures - uint8_t chip_id_attr; - - // mark function entry - FAPI_DBG("proc_fab_smp_get_chip_id_attr: Start"); - - do - { - if (i_target->getType() != fapi::TARGET_TYPE_PROC_CHIP) - { - use_parent = true; - // retrieve parent target if input target is a chiplet - rc = fapiGetParentChip(*i_target, - parent_target); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_smp_get_chip_id_attr: Error from fapiGetParentChip"); - break; - } - } - - // retrieve chip ID attribute - rc = FAPI_ATTR_GET(ATTR_FABRIC_CHIP_ID, - ((use_parent)? - (&parent_target): - (i_target)), - chip_id_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_smp_get_chip_id_attr: Error querying ATTR_FABRIC_CHIP_ID"); - break; - } - - // print attribute value - FAPI_DBG("proc_fab_smp_get_chip_id_attr: ATTR_FABRIC_CHIP_ID = 0x%X", - chip_id_attr); - - // translate to output value - switch (chip_id_attr) - { - case 0: - o_chip_id = FBC_CHIP_ID_0; - break; - case 1: - o_chip_id = FBC_CHIP_ID_1; - break; - case 2: - o_chip_id = FBC_CHIP_ID_2; - break; - case 3: - o_chip_id = FBC_CHIP_ID_3; - break; - case 4: - o_chip_id = FBC_CHIP_ID_4; - break; - case 5: - o_chip_id = FBC_CHIP_ID_5; - break; - case 6: - o_chip_id = FBC_CHIP_ID_6; - break; - case 7: - o_chip_id = FBC_CHIP_ID_7; - break; - default: - FAPI_ERR("proc_fab_smp_get_chip_id_attr: Invalid fabric chip ID attribute value 0x%02X", - chip_id_attr); - const fapi::Target & TARGET = *i_target; - const uint8_t& ATTR_DATA = chip_id_attr; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR); - break; - } - } while(0); - - // mark function exit - FAPI_DBG("proc_fab_smp_get_chip_id_attr: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility function to read & return PCIe/DSMP mux attribute values -// parameters: i_target => pointer to chip target -// o_pcie_not_f_link => vector of boolean values representing state -// of PCIe/DSMP mux settings (one value per -// foreign link, true=PCIe function, false= -// DSMP function) -// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, -// RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is -// invalid, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs( - const fapi::Target* i_target, - bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]) -{ - // return code - fapi::ReturnCode rc; - // temporary attribute storage used to build procedure data structures - uint8_t pcie_not_f_link_attr[PROC_FAB_SMP_NUM_F_LINKS]; - - // mark function entry - FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: Start"); - - do - { - // retrieve PCIe/DSMP mux attributes - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NOT_F_LINK, - i_target, - pcie_not_f_link_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Error querying ATTR_PROC_PCIE_NOT_F_LINK"); - break; - } - - // loop over all links - for (uint8_t l = 0; - l < PROC_FAB_SMP_NUM_F_LINKS; - l++) - { - // print attribute value - FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: ATTR_PROC_PCIE_NOT_F_LINK[%d] = 0x%X", - l, pcie_not_f_link_attr[l]); - - // validate attribute value - switch (pcie_not_f_link_attr[l]) - { - case 0: - o_pcie_not_f_link[l] = false; - break; - case 1: - o_pcie_not_f_link[l] = true; - break; - default: - FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Invalid PCIe/DSMP mux attribute value 0x%02X", - pcie_not_f_link_attr[l]); - const fapi::Target & TARGET = *i_target; - const uint8_t& ATTR_DATA = pcie_not_f_link_attr[l]; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR); - break; - } - if (!rc.ok()) - { - break; - } - } - } while(0); - - // mark function exit - FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: End"); - return rc; -} - - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H deleted file mode 100644 index 7f26f083c..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H +++ /dev/null @@ -1,163 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_fab_smp.H,v 1.9 2014/01/27 05:22:15 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_fab_smp.H -// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_FAB_SMP_H_ -#define _PROC_FAB_SMP_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <fapi.H> - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// define set of supported fabric node ID values -enum proc_fab_smp_node_id -{ - FBC_NODE_ID_0 = 0, - FBC_NODE_ID_1 = 1, - FBC_NODE_ID_2 = 2, - FBC_NODE_ID_3 = 3, - FBC_NODE_ID_4 = 4, - FBC_NODE_ID_5 = 5, - FBC_NODE_ID_6 = 6, - FBC_NODE_ID_7 = 7 -}; - -// define set of supported fabric chip ID values -enum proc_fab_smp_chip_id -{ - FBC_CHIP_ID_0 = 0, - FBC_CHIP_ID_1 = 1, - FBC_CHIP_ID_2 = 2, - FBC_CHIP_ID_3 = 3, - FBC_CHIP_ID_4 = 4, - FBC_CHIP_ID_5 = 5, - FBC_CHIP_ID_6 = 6, - FBC_CHIP_ID_7 = 7 -}; - -// define set of supported epsilon table types -enum proc_fab_smp_eps_table_type -{ - PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE = 1, - PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE = 2, - PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S = 3 -}; - -// define set of supported broadcast/pump modes -enum proc_fab_smp_pump_mode -{ - PROC_FAB_SMP_PUMP_MODE1 = 1, - PROC_FAB_SMP_PUMP_MODE2 = 2 -}; - - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// largest representable fabric real address given HW implementation -const uint64_t PROC_FAB_SMP_MAX_ADDRESS = ((1ULL << 50)-1ULL); - -// number of links supported per chip -const uint8_t PROC_FAB_SMP_NUM_A_LINKS = 3; -const uint8_t PROC_FAB_SMP_NUM_X_LINKS = 4; -const uint8_t PROC_FAB_SMP_NUM_F_LINKS = 2; - -// range of fabric node/chip ID fields -const uint8_t PROC_FAB_SMP_NUM_CHIP_IDS = 8; -const uint8_t PROC_FAB_SMP_NUM_NODE_IDS = 8; - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: utility function to read & return fabric node ID attribute -// parameters: i_target => pointer to chip/chiplet target -// o_node_id => node ID value -// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, -// RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is -// invalid, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_smp_get_node_id_attr( - const fapi::Target* i_target, - proc_fab_smp_node_id& o_node_id); - -//------------------------------------------------------------------------------ -// function: utility function to read & return fabric chip ID attribute -// parameters: i_target => pointer to chip/chiplet target -// o_chip_id => chip ID value -// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, -// RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is -// invalid, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_smp_get_chip_id_attr( - const fapi::Target* i_target, - proc_fab_smp_chip_id& o_chip_id); - -//------------------------------------------------------------------------------ -// function: utility function to read & return PCIe/DSMP mux attribute values -// parameters: i_target => pointer to chip target -// o_pcie_not_f_link => vector of boolean values representing state -// of PCIe/DSMP mux settings (one value per -// foreign link, true=PCIe function, false= -// DSMP function) -// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid, -// RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is -// invalid, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs( - const fapi::Target* i_target, - bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]); - - -} // extern "C" - -#endif // _PROC_FAB_SMP_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C deleted file mode 100644 index 2315b73cd..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C +++ /dev/null @@ -1,3887 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars.C,v 1.29 2015/11/10 19:39:58 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_setup_bars.C -// *! DESCRIPTION : Program nest base address registers (BARs) (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <proc_setup_bars.H> -#include <proc_setup_bars_defs.H> - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// logical size->physical encoding translation maps -const std::map<uint64_t, uint64_t> proc_setup_bars_nf_bar_size::xlate_map = - proc_setup_bars_nf_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_f_bar_size::xlate_map = - proc_setup_bars_f_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_bar_size::xlate_map = - proc_setup_bars_fsp_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_mmio_mask_size::xlate_map = - proc_setup_bars_fsp_mmio_mask_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_nx_mmio_bar_size::xlate_map = - proc_setup_bars_nx_mmio_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_npu_mmio_bar_size::xlate_map = - proc_setup_bars_npu_mmio_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_hca_nm_bar_size::xlate_map = - proc_setup_bars_hca_nm_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_as_mmio_bar_size::xlate_map = - proc_setup_bars_as_mmio_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_mcd_bar_size::xlate_map = - proc_setup_bars_mcd_bar_size::create_map(); - -const std::map<uint64_t, uint64_t> proc_setup_bars_pcie_bar_size::xlate_map = - proc_setup_bars_pcie_bar_size::create_map(); - - -extern "C" { - -//------------------------------------------------------------------------------ -// Function definitions -//------------------------------------------------------------------------------ - - -//------------------------------------------------------------------------------ -// function: utility function to display address range/BAR information and -// check properties -// parameters: i_bar_def => structure encapsulating address range/BAR -// properties -// i_bar_addr_range => structure encapsulating address range -// returns: true if any properties specified by i_bar_def are violated, -// false otherwise -//------------------------------------------------------------------------------ -bool proc_setup_bars_common_check_bar( - const proc_setup_bars_bar_def& i_bar_def, - const proc_setup_bars_addr_range& i_bar_addr_range) -{ - // return code - fapi::ReturnCode rc; - // set if error should be logged at end of function - bool error = false; - - do - { - // print range information - i_bar_addr_range.print(); - - // only check if BAR enable attribute is set - if (i_bar_addr_range.enabled) - { - // ensure that address range lies in fabric real address space - if (!i_bar_addr_range.is_in_fbc_range()) - { - FAPI_ERR("proc_setup_bars_common_check_bar: BAR range is not wholly contained in FBC real address space"); - error = true; - break; - } - // ensure that base address value lies in implemented address space - if (i_bar_addr_range.base_addr & - i_bar_def.base_addr_mask) - { - FAPI_ERR("proc_setup_bars_common_check_bar: BAR base address attribute value is out-of-range"); - error = true; - break; - } - // ensure that address range size is in range - if ((i_bar_addr_range.size < i_bar_def.size_min) || - (i_bar_addr_range.size > i_bar_def.size_max)) - { - FAPI_ERR("proc_setup_bars_common_check_bar: BAR size attribute value is out-of-range"); - error = true; - break; - } - // check that base address range and mask are aligned - if (i_bar_def.check_aligned && - !i_bar_addr_range.is_aligned()) - { - FAPI_ERR("proc_setup_bars_common_check_bar: BAR base address/size range values are not aligned"); - error = true; - break; - } - } - } while(0); - - return error; -} - - -//------------------------------------------------------------------------------ -// function: retrieve attribute (with optional indices) using FAPI AttributeId -// parameters: i_attr => attribute ID to query -// i_attr_id => enum identifying attribute function -// i_target => pointer to chip target -// i_attr_idx1 => attribute array index1 -// i_attr_idx2 => attribute array index1 -// o_val => output value -// returns: FAPI_RC_SUCCESS if attribute read is successful & output value -// is valid, -// RC_PROC_SETUP_BARS_ATTR_QUERY_ERR if FAPI attribute ID is -// unsupported, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_query_attr( - const fapi::AttributeId i_attr, - const proc_setup_bars_attr_id i_attr_id, - const fapi::Target* i_target, - const uint32_t i_attr_idx1, - const uint32_t i_attr_idx2, - uint64_t& o_val) -{ - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_query_attr: Start"); - - // ATTR_PROC_MEM_BASES_ACK - if (i_attr == fapi::ATTR_PROC_MEM_BASES_ACK) - { - fapi::ATTR_PROC_MEM_BASES_ACK_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES_ACK, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_MEM_SIZES_ACK - else if (i_attr == fapi::ATTR_PROC_MEM_SIZES_ACK) - { - fapi::ATTR_PROC_MEM_SIZES_ACK_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES_ACK, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_MIRROR_BASES_ACK - else if (i_attr == fapi::ATTR_PROC_MIRROR_BASES_ACK) - { - fapi::ATTR_PROC_MIRROR_BASES_ACK_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES_ACK, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_MIRROR_SIZES_ACK - else if (i_attr == fapi::ATTR_PROC_MIRROR_SIZES_ACK) - { - fapi::ATTR_PROC_MIRROR_SIZES_ACK_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES_ACK, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_FOREIGN_NEAR_BASE - else if (i_attr == fapi::ATTR_PROC_FOREIGN_NEAR_BASE) - { - fapi::ATTR_PROC_FOREIGN_NEAR_BASE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_NEAR_BASE, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_FOREIGN_NEAR_SIZE - else if (i_attr == fapi::ATTR_PROC_FOREIGN_NEAR_SIZE) - { - fapi::ATTR_PROC_FOREIGN_NEAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_NEAR_SIZE, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_FOREIGN_FAR_BASE - else if (i_attr == fapi::ATTR_PROC_FOREIGN_FAR_BASE) - { - fapi::ATTR_PROC_FOREIGN_FAR_BASE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_FAR_BASE, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_FOREIGN_FAR_SIZE - else if (i_attr == fapi::ATTR_PROC_FOREIGN_FAR_SIZE) - { - fapi::ATTR_PROC_FOREIGN_FAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_FAR_SIZE, i_target, attr_data); - o_val = attr_data[i_attr_idx1]; - } - // ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_PSI_BRIDGE_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_PSI_BRIDGE_BAR_ENABLE) - { - fapi::ATTR_PROC_PSI_BRIDGE_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_PSI_BRIDGE_BAR_ENABLE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_FSP_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_FSP_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_FSP_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_FSP_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_FSP_BAR_ENABLE) - { - fapi::ATTR_PROC_FSP_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_ENABLE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_FSP_BAR_SIZE - else if (i_attr == fapi::ATTR_PROC_FSP_BAR_SIZE) - { - fapi::ATTR_PROC_FSP_BAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_SIZE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_FSP_MMIO_MASK_SIZE - else if (i_attr == fapi::ATTR_PROC_FSP_MMIO_MASK_SIZE) - { - fapi::ATTR_PROC_FSP_MMIO_MASK_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_FSP_MMIO_MASK_SIZE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_INTP_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_INTP_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_INTP_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_INTP_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_INTP_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_INTP_BAR_ENABLE) - { - fapi::ATTR_PROC_INTP_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_INTP_BAR_ENABLE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_NX_MMIO_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_NX_MMIO_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_NX_MMIO_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_NX_MMIO_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_NX_MMIO_BAR_ENABLE) - { - fapi::ATTR_PROC_NX_MMIO_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_ENABLE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_NX_MMIO_BAR_SIZE - else if (i_attr == fapi::ATTR_PROC_NX_MMIO_BAR_SIZE) - { - fapi::ATTR_PROC_NX_MMIO_BAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_SIZE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_AS_MMIO_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_AS_MMIO_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_AS_MMIO_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_AS_MMIO_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_AS_MMIO_BAR_ENABLE) - { - fapi::ATTR_PROC_AS_MMIO_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_ENABLE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_AS_MMIO_BAR_SIZE - else if (i_attr == fapi::ATTR_PROC_AS_MMIO_BAR_SIZE) - { - fapi::ATTR_PROC_AS_MMIO_BAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_SIZE, i_target, attr_data); - o_val = attr_data; - } - // ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data[i_attr_idx1][i_attr_idx2]; - } - // ATTR_PROC_NPU_MMIO_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_NPU_MMIO_BAR_ENABLE) - { - fapi::ATTR_PROC_NPU_MMIO_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_NPU_MMIO_BAR_ENABLE, i_target, attr_data); - o_val = attr_data[i_attr_idx1][i_attr_idx2]; - } - // ATTR_PROC_NPU_MMIO_BAR_SIZE - else if (i_attr == fapi::ATTR_PROC_NPU_MMIO_BAR_SIZE) - { - fapi::ATTR_PROC_NPU_MMIO_BAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_NPU_MMIO_BAR_SIZE, i_target, attr_data); - o_val = attr_data[i_attr_idx1][i_attr_idx2]; - } - // ATTR_PROC_PCIE_BAR_BASE_ADDR - else if (i_attr == fapi::ATTR_PROC_PCIE_BAR_BASE_ADDR) - { - fapi::ATTR_PROC_PCIE_BAR_BASE_ADDR_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_BASE_ADDR, i_target, attr_data); - o_val = attr_data[i_attr_idx1][i_attr_idx2]; - } - // ATTR_PROC_PCIE_BAR_ENABLE - else if (i_attr == fapi::ATTR_PROC_PCIE_BAR_ENABLE) - { - fapi::ATTR_PROC_PCIE_BAR_ENABLE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_ENABLE, i_target, attr_data); - o_val = attr_data[i_attr_idx1][i_attr_idx2]; - } - // ATTR_PROC_PCIE_BAR_SIZE - else if (i_attr == fapi::ATTR_PROC_PCIE_BAR_SIZE) - { - fapi::ATTR_PROC_PCIE_BAR_SIZE_Type attr_data; - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_SIZE, i_target, attr_data); - o_val = attr_data[i_attr_idx1][i_attr_idx2]; - } - else - { - FAPI_ERR("proc_setup_bars_query_attr: Unsupported FAPI Attribute ID"); - const fapi::Target & TARGET = *i_target; - const fapi::AttributeId & FAPI_ATTR_ID = i_attr; - const proc_setup_bars_attr_id & ATTR_ID = i_attr_id; - const uint32_t & ATTR_IDX1 = i_attr_idx1; - const uint32_t & ATTR_IDX2 = i_attr_idx2; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_ATTR_QUERY_ERR); - } - - FAPI_DBG("proc_setup_bars_query_attr: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: retrieve attributes defining unit BAR/range programming -// parameters: i_target => pointer to chip target -// i_attr_id => enum identifying BAR/range function -// i_base_addr_attr => pointer to attribute ID associated with -// BAR/range base address -// i_enable_attr => pointer to attribute ID associated with -// BAR/range enable -// i_size_attr => pointer to attribute ID associated with -// BAR/range size -// i_attr_idx1 => attribute array index1 -// i_attr_idx2 => attribute array index2 -// i_bar_def => structure encapsulating BAR/range -// properties -// io_addr_range => address range structure encapsulating -// attribute values -// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values -// are valid, -// RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR if no rule is -// provided to set BAR/range address/enable/size, -// RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR if BAR/range -// attribute content violates expected behavior, -// else FAPI_ATTR_GET return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_get_range_attrs( - const fapi::Target* i_target, - const proc_setup_bars_attr_id i_attr_id, - const fapi::AttributeId* i_base_addr_attr, - const fapi::AttributeId* i_enable_attr, - const fapi::AttributeId* i_size_attr, - const uint32_t i_attr_idx1, - const uint32_t i_attr_idx2, - const proc_setup_bars_bar_def& i_bar_def, - proc_setup_bars_addr_range& io_addr_range) -{ - // return code - fapi::ReturnCode rc; - uint64_t bar_enabled; - - FAPI_DBG("proc_setup_bars_get_range_attrs: Start"); - do - { - // BAR base address - if ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FSP_MMIO) && !i_attr_idx1 && !i_attr_idx2) - { - io_addr_range.base_addr = 0x0; - } - else if (i_base_addr_attr) - { - rc = proc_setup_bars_query_attr( - *i_base_addr_attr, - i_attr_id, - i_target, - i_attr_idx1, i_attr_idx2, - io_addr_range.base_addr); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_range_attrs: Error querying BAR base address attribute (Unit/Range ID = 0x%X, FAPI Attribute ID = %08X)", - i_attr_id, *i_base_addr_attr); - break; - } - } - else - { - FAPI_ERR("proc_setup_bars_get_range_attrs: No rule to set range base address"); - const fapi::Target & TARGET = *i_target; - const proc_setup_bars_attr_id & ATTR_ID = i_attr_id; - const uint32_t & ATTR_IDX1 = i_attr_idx1; - const uint32_t & ATTR_IDX2 = i_attr_idx2; - const proc_setup_bars_attr_lookup_err_type & ERR_TYPE = PROC_SETUP_BARS_BASE_ADDR_ATTR_LOOKUP_ERR; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR); - break; - } - - // BAR size - if (((i_attr_id == PROC_SETUP_BARS_ATTR_ID_PSI) || - (i_attr_id == PROC_SETUP_BARS_ATTR_ID_INTP)) && - !i_attr_idx1 && !i_attr_idx2) - { - io_addr_range.size = PROC_SETUP_BARS_SIZE_1_MB; - } - else if (i_size_attr) - { - rc = proc_setup_bars_query_attr( - *i_size_attr, - i_attr_id, - i_target, - i_attr_idx1, i_attr_idx2, - io_addr_range.size); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_range_attrs: Error querying BAR size attribute (Unit/Range ID = 0x%X, FAPI Attribute ID = 0x%08X)", - i_attr_id, *i_size_attr); - break; - } - } - else - { - FAPI_ERR("proc_setup_bars_get_range_attrs: No rule to set range size"); - const fapi::Target & TARGET = *i_target; - const proc_setup_bars_attr_id & ATTR_ID = i_attr_id; - const uint32_t & ATTR_IDX1 = i_attr_idx1; - const uint32_t & ATTR_IDX2 = i_attr_idx2; - const proc_setup_bars_attr_lookup_err_type & ERR_TYPE = PROC_SETUP_BARS_SIZE_ATTR_LOOKUP_ERR; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR); - break; - } - - // BAR enable - if ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FSP_MMIO) && !i_attr_idx1 && !i_attr_idx2) - { - io_addr_range.enabled = true; - } - - else if (((i_attr_id == PROC_SETUP_BARS_ATTR_ID_NM) && (i_attr_idx1 < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES) && !i_attr_idx2) || - ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_M) && (i_attr_idx1 < PROC_SETUP_BARS_NUM_MIRRORED_RANGES) && !i_attr_idx2) || - ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FN) && (i_attr_idx1 < PROC_FAB_SMP_NUM_F_LINKS) && !i_attr_idx2) || - ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FF) && (i_attr_idx1 < PROC_FAB_SMP_NUM_F_LINKS) && !i_attr_idx2)) - { - io_addr_range.enabled = (io_addr_range.size != 0); - } - else if (i_enable_attr) - { - rc = proc_setup_bars_query_attr( - *i_enable_attr, - i_attr_id, - i_target, - i_attr_idx1, i_attr_idx2, - bar_enabled); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_range_attrs: Error querying BAR enable attribute (Unit/Range ID = 0x%X, FAPI Attribute ID = 0x%08X)", - i_attr_id, *i_enable_attr); - break; - } - io_addr_range.enabled = (bar_enabled == 0x1ULL); - } - else - { - FAPI_ERR("proc_setup_bars_get_range_attrs: No rule to set range enable"); - const fapi::Target & TARGET = *i_target; - const proc_setup_bars_attr_id & ATTR_ID = i_attr_id; - const uint32_t & ATTR_IDX1 = i_attr_idx1; - const uint32_t & ATTR_IDX2 = i_attr_idx2; - const proc_setup_bars_attr_lookup_err_type & ERR_TYPE = PROC_SETUP_BARS_ENABLE_ATTR_LOOKUP_ERR; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR); - break; - } - - // check BAR attribute content - if (proc_setup_bars_common_check_bar( - i_bar_def, - io_addr_range) != false) - { - FAPI_ERR("proc_setup_bars_get_range_attrs: Error from proc_setup_bars_common_check_bar"); - const fapi::Target & TARGET = *i_target; - const proc_setup_bars_attr_id & ATTR_ID = i_attr_id; - const uint32_t & ATTR_IDX1 = i_attr_idx1; - const uint32_t & ATTR_IDX2 = i_attr_idx2; - const uint64_t & BASE_ADDR = io_addr_range.base_addr; - const bool & ENABLED = io_addr_range.enabled; - const uint64_t & SIZE = io_addr_range.size; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR); - break; - } - } while(0); - - FAPI_DBG("proc_setup_bars_get_range_attrs: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: retrieve attributes defining non-mirrored/mirrored memory ranges -// parameters: i_target => pointer to chip target -// i_range_id => enum identifying range function -// i_base_addr_attr => pointer to attribute ID associated with -// ange base addresses -// i_size_attr => pointer to attribute ID associated with -// range sizes -// i_num_ranges => number of ranges (attribute dimension) -// i_range_def => structure encapsulating range -// properties -// io_addr_range => address range structure encapsulating -// attribute -// values (size will be rounded up to nearest -// power of two) -// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values -// are valid, -// RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ATTR_OVERLAP_ERR if chip -// memory range attributes specify overlapping address ranges, -// RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ERR if merged chip -// memory address range is invalid, -// RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR if BAR/range -// attribute content violates expected behavior, -// else proc_setup_bars_get_range_attrs failing return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_get_memory_range_attrs( - const fapi::Target* i_target, - const proc_setup_bars_attr_id i_range_id, - const fapi::AttributeId i_base_addr_attr, - const fapi::AttributeId i_size_attr, - const uint8_t i_num_ranges, - const proc_setup_bars_bar_def& i_range_def, - proc_setup_bars_addr_range& io_addr_range) -{ - // return code - fapi::ReturnCode rc; - // set of ranges, to be checked/merged into single range - std::vector<proc_setup_bars_addr_range> ranges(i_num_ranges); - - // mark function entry - FAPI_DBG("proc_setup_bars_get_memory_range_attrs: Start"); - - do - { - // build individual ranges - for (uint8_t r = 0; r < i_num_ranges; r++) - { - rc = proc_setup_bars_get_range_attrs( - i_target, - i_range_id, - &i_base_addr_attr, - NULL, - &i_size_attr, - r, 0, - i_range_def, - ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_memory_range_attrs: Error from proc_setup_bars_get_range_attrs (Range ID = 0x%X, Range index = %d)", - i_range_id, r); - break; - } - } - if (!rc.ok()) - { - break; - } - - // check that ranges are non-overlapping - if (i_num_ranges > 1) - { - for (uint8_t r = 0; (r < i_num_ranges-1) && rc.ok(); r++) - { - for (uint8_t x = r+1; x < i_num_ranges; x++) - { - if (ranges[r].overlaps(ranges[x])) - { - FAPI_ERR("proc_setup_bars_get_memory_range_attrs: Memory range attributes specify overlapping address regions (Range ID = 0x%X, Range index1 = %d, Range index2 = %d)", - i_range_id, r, x); - const fapi::Target & TARGET = *i_target; - const proc_setup_bars_attr_id & RANGE_ID = i_range_id; - const uint32_t & ATTR_IDX1 = r; - const uint64_t & BASE_ADDR1 = ranges[r].base_addr; - const uint64_t & END_ADDR1 = ranges[r].end_addr(); - const bool & ENABLED1 = ranges[r].enabled; - const uint32_t & ATTR_IDX2 = x; - const uint64_t & BASE_ADDR2 = ranges[x].base_addr; - const uint64_t & END_ADDR2 = ranges[x].end_addr(); - const bool & ENABLED2 = ranges[x].enabled; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ATTR_OVERLAP_ERR); - break; - } - } - } - if (!rc.ok()) - { - break; - } - } - - // ranges are non-overlapping, merge to single range - for (uint8_t r = 0; r < i_num_ranges; r++) - { - // merge to build single range - io_addr_range.merge(ranges[r]); - } - - // ensure range is power of 2 aligned - if (io_addr_range.enabled && !io_addr_range.is_power_of_2()) - { - io_addr_range.round_next_power_of_2(); - } - - // check final range content - if (proc_setup_bars_common_check_bar( - i_range_def, - io_addr_range) != false) - { - FAPI_ERR("proc_setup_bars_get_memory_range_attrs: Error from proc_setup_bars_common_check_bar"); - const fapi::Target & TARGET = *i_target; - const proc_setup_bars_attr_id & RANGE_ID = i_range_id; - const uint64_t & BASE_ADDR = io_addr_range.base_addr; - const uint64_t & END_ADDR = io_addr_range.end_addr(); - const bool & ENABLED = io_addr_range.enabled; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ERR); - break; - } - } while(0); - - // mark function exit - FAPI_DBG("proc_setup_bars_get_memory_range_attrs: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to call all BAR attribute query functions -// parameters: io_smp_chip => structure encapsulating single chip in SMP -// topology (containing target for attribute -// query and storage for all address ranges) -// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values -// are valid, -// else failing return code from attribute query function -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_get_bar_attrs( - proc_setup_bars_smp_chip& io_smp_chip) -{ - // return code - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("proc_setup_bars_get_bar_attrs: Start"); - - do - { - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for non-mirrored memory range"); - rc = proc_setup_bars_get_memory_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_NM, - fapi::ATTR_PROC_MEM_BASES_ACK, - fapi::ATTR_PROC_MEM_SIZES_ACK, - PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES, - non_mirrored_range_def, - io_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_memory_range_attrs (non-mirrored)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for mirrored memory range"); - rc = proc_setup_bars_get_memory_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_M, - fapi::ATTR_PROC_MIRROR_BASES_ACK, - fapi::ATTR_PROC_MIRROR_SIZES_ACK, - PROC_SETUP_BARS_NUM_MIRRORED_RANGES, - mirrored_range_def, - io_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_memory_range_attrs (mirrored)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for foreign near memory ranges"); - for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++) - { - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_FN, - &f_near_range_base_addr_attr, - NULL, - &f_near_range_size_attr, - l, 0, - common_f_scope_bar_def, - io_smp_chip.foreign_near_ranges[l]); - - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (foreign near, link = %d)", - l); - break; - } - } - if (!rc.ok()) - { - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for foreign far memory ranges"); - for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++) - { - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_FF, - &f_far_range_base_addr_attr, - NULL, - &f_far_range_size_attr, - l, 0, - common_f_scope_bar_def, - io_smp_chip.foreign_far_ranges[l]); - - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (foreign far, link = %d)", - l); - break; - } - } - if (!rc.ok()) - { - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PSI address range"); - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_PSI, - &psi_bridge_bar_base_addr_attr, - &psi_bridge_bar_en_attr, - NULL, - 0, 0, - psi_bridge_bar_def, - io_smp_chip.psi_range); - - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (PSI)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for FSP address range"); - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_FSP, - &fsp_bar_base_addr_attr, - &fsp_bar_en_attr, - &fsp_bar_size_attr, - 0, 0, - fsp_bar_def, - io_smp_chip.fsp_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (FSP)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for FSP MMIO mask"); - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_FSP_MMIO, - NULL, - NULL, - &fsp_mmio_mask_size_attr, - 0, 0, - fsp_mmio_mask_def, - io_smp_chip.fsp_mmio_mask_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_addrs (FSP MMIO)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for INTP address range"); - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_INTP, - &intp_bar_base_addr_attr, - &intp_bar_en_attr, - NULL, - 0, 0, - intp_bar_def, - io_smp_chip.intp_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (INTP)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for NX MMIO address range"); - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_NX, - &nx_mmio_bar_base_addr_attr, - &nx_mmio_bar_en_attr, - &nx_mmio_bar_size_attr, - 0, 0, - nx_mmio_bar_def, - io_smp_chip.nx_mmio_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (NX)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for AS MMIO address range"); - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_AS, - &as_mmio_bar_base_addr_attr, - &as_mmio_bar_en_attr, - &as_mmio_bar_size_attr, - 0, 0, - as_mmio_bar_def, - io_smp_chip.as_mmio_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (AS)"); - break; - } - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for NPU MMIO address ranges"); - for (uint8_t u = 0; - (u < PROC_SETUP_BARS_NPU_NUM_UNITS) && (rc.ok()); - u++) - { - for (uint8_t r = 0; - r < PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT; - r++) - { - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_NPU, - &npu_mmio_bar_base_addr_attr, - &npu_mmio_bar_en_attr, - &npu_mmio_bar_size_attr, - u, r, - npu_mmio_bar_def, - io_smp_chip.npu_mmio_ranges[u][r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (NPU MMIO, unit = %d, range=%d)", - u, r); - break; - } - } - } - if (!rc.ok()) - { - break; - } - - - FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PCIe address ranges"); - for (uint8_t u = 0; - (u < PROC_SETUP_BARS_PCIE_NUM_UNITS) && (rc.ok()); - u++) - { - for (uint8_t r = 0; - r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT; - r++) - { - rc = proc_setup_bars_get_range_attrs( - &(io_smp_chip.chip->this_chip), - PROC_SETUP_BARS_ATTR_ID_PCIE, - &pcie_mmio_bar_base_addr_attr, - &pcie_mmio_bar_en_attr, - &pcie_mmio_bar_size_attr, - u, r, - ((PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[r])? - (pcie_mmio_bar_def): - (pcie_phb_bar_def)), - io_smp_chip.pcie_ranges[u][r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (PCIE, unit = %d, range=%d)", - u, r); - break; - } - } - } - if (!rc.ok()) - { - break; - } - - } while(0); - - // mark function exit - FAPI_DBG("proc_setup_bars_get_bar_attrs: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to call all chip attribute query functions -// (fabric configuration/node/position/BARs) -// parameters: i_proc_chip => pointer to HWP input structure for this chip -// io_smp_chip => fully specified structure encapsulating -// single chip in SMP topology -// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values -// are valid, -// else failing return code from attribute query function -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_process_chip( - proc_setup_bars_proc_chip* i_proc_chip, - proc_setup_bars_smp_chip& io_smp_chip) -{ - // return code - fapi::ReturnCode rc; - uint8_t pcie_enabled; - uint8_t nx_enabled; - uint8_t nv_present; - uint8_t init_group_as_chip; - uint8_t dual_capp_present; - - // mark function entry - FAPI_DBG("proc_setup_bars_process_chip: Start"); - - do - { - // set HWP input pointer - io_smp_chip.chip = i_proc_chip; - - // display target information for this chip - FAPI_DBG("proc_setup_bars_process_chip: Target: %s", - io_smp_chip.chip->this_chip.toEcmdString()); - - // determine number of PHBs - FAPI_DBG("proc_setup_bars_process_chip: Querying PHB configuration"); - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, - &(io_smp_chip.chip->this_chip), - io_smp_chip.num_phb); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_NUM_PHB"); - break; - } - - // get PCIe/DSMP mux attributes - FAPI_DBG("proc_setup_bars_process_chip: Querying PCIe/DSMP mux attribute"); - rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip), - io_smp_chip.pcie_not_f_link); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_pcie_dsmp_mux_attrs"); - break; - } - - // get node ID attribute - FAPI_DBG("proc_setup_bars_process_chip: Querying node ID attribute"); - rc = proc_fab_smp_get_node_id_attr(&(io_smp_chip.chip->this_chip), - io_smp_chip.node_id); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_node_id_attr"); - break; - } - - // get chip ID attribute - FAPI_DBG("proc_setup_bars_process_chip: Querying chip ID attribute"); - rc = proc_fab_smp_get_chip_id_attr(&(io_smp_chip.chip->this_chip), - io_smp_chip.chip_id); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_chip_id_attr"); - break; - } - - // query NX partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE, - &(io_smp_chip.chip->this_chip), - nx_enabled); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_NX_ENABLE"); - break; - } - - // query PCIE partial good attribute - rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE, - &(io_smp_chip.chip->this_chip), - pcie_enabled); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_ENABLE"); - break; - } - - io_smp_chip.nx_enabled = - (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE); - - io_smp_chip.pcie_enabled = - (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE); - - // configure group BARs to cover chip ranges? - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS, - &(io_smp_chip.chip->this_chip), - init_group_as_chip); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS"); - break; - } - io_smp_chip.init_group_as_chip = (init_group_as_chip != 0); - - // get NV link presence attribute - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NV_PRESENT, - &(io_smp_chip.chip->this_chip), - nv_present); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_NV_PRESENT"); - break; - } - io_smp_chip.nv_present = (nv_present != 0); - - // get dual CAPP presence attribute - rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT, - &(io_smp_chip.chip->this_chip), - dual_capp_present); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT"); - break; - } - io_smp_chip.dual_capp_present = (dual_capp_present != 0); - - // get BAR attributes - rc = proc_setup_bars_get_bar_attrs(io_smp_chip); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chip: Error from proc_setup_bars_get_bar_attrs"); - break; - } - } while(0); - - // mark function exit - FAPI_DBG("proc_setup_bars_process_chip: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: insert chip structure into proper position within SMP model based -// on its fabric node/chip ID -// chip non-mirrored/mirrored range information will be merged -// with those of its enclosing node -// parameters: i_smp_chip => structure encapsulating single chip in SMP topology -// io_smp => structure encapsulating full SMP -// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges -// are valid, -// RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails, -// RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR if chips with duplicate -// fabric node/chip IDs are detected -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_insert_chip( - proc_setup_bars_smp_chip& i_smp_chip, - proc_setup_bars_smp_system& io_smp) -{ - // return code - fapi::ReturnCode rc; - // node/chip ID - proc_fab_smp_node_id node_id = i_smp_chip.node_id; - proc_fab_smp_chip_id chip_id = i_smp_chip.chip_id; - - // mark function entry - FAPI_DBG("proc_setup_bars_insert_chip: Start"); - - do - { - FAPI_DBG("proc_setup_bars_insert_chip: Inserting n%d p%d", - node_id, chip_id); - - // search to see if node structure already exists for the node ID - // associated with this chip - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator - n_iter; - n_iter = io_smp.nodes.find(node_id); - // no matching node found, create one - if (n_iter == io_smp.nodes.end()) - { - FAPI_DBG("proc_setup_bars_insert_chip: No matching node found, inserting new node structure"); - proc_setup_bars_smp_node n; - std::pair< - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator, - bool> ret; - ret = io_smp.nodes.insert( - std::pair<proc_fab_smp_node_id, proc_setup_bars_smp_node> - (node_id, n)); - n_iter = ret.first; - if (!ret.second) - { - FAPI_ERR("proc_setup_bars_insert_chip: Error encountered adding node to SMP map"); - const fapi::Target & TARGET = i_smp_chip.chip->this_chip; - const proc_fab_smp_node_id & NODE_ID = node_id; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR); - break; - } - } - - // search to see if match exists in this node for the chip ID associated - // with this chip - std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator - p_iter; - p_iter = io_smp.nodes[node_id].chips.find(chip_id); - // matching chip ID & node ID already found, flag an error - if (p_iter != io_smp.nodes[node_id].chips.end()) - { - FAPI_ERR("proc_setup_bars_insert_chip: Duplicate fabric node ID / chip ID found"); - const fapi::Target & TARGET1 = i_smp_chip.chip->this_chip; - const fapi::Target & TARGET2 = p_iter->second.chip->this_chip; - const proc_fab_smp_node_id & NODE_ID = node_id; - const proc_fab_smp_chip_id & CHIP_ID = chip_id; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR); - break; - } - // insert chip into SMP - io_smp.nodes[node_id].chips[chip_id] = i_smp_chip; - - // update node address regions - i_smp_chip.non_mirrored_range.print(); - io_smp.nodes[node_id].non_mirrored_range.print(); - io_smp.nodes[node_id].non_mirrored_range.merge(io_smp.nodes[node_id].chips[chip_id].non_mirrored_range); - io_smp.nodes[node_id].non_mirrored_range.print(); - - i_smp_chip.mirrored_range.print(); - io_smp.nodes[node_id].mirrored_range.print(); - io_smp.nodes[node_id].mirrored_range.merge(io_smp.nodes[node_id].chips[chip_id].mirrored_range); - io_smp.nodes[node_id].mirrored_range.print(); - } while(0); - - // mark function exit - FAPI_DBG("proc_setup_bars_insert_chip: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to process all HWP input structures and build -// SMP data structure -// parameters: i_proc_chips => vector of HWP input structures (one entry per -// chip in SMP) -// io_smp => fully specified structure encapsulating full SMP -// returns: FAPI_RC_SUCCESS if all processing is successful, -// else failing return code from chip processing/insertion wrapper -// functions -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_process_chips( - std::vector<proc_setup_bars_proc_chip>& i_proc_chips, - proc_setup_bars_smp_system& io_smp) -{ - // return code - fapi::ReturnCode rc; - - // mark function entry - FAPI_DBG("proc_setup_bars_process_chips: Start"); - - do - { - // loop over all chips passed from platform to HWP - std::vector<proc_setup_bars_proc_chip>::iterator c_iter; - for (c_iter = i_proc_chips.begin(); - c_iter != i_proc_chips.end(); - c_iter++) - { - // process platform provided data in chip argument, - // query chip specific attributes - proc_setup_bars_smp_chip smp_chip; - rc = proc_setup_bars_process_chip(&(*c_iter), - smp_chip); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chips: Error from proc_setup_bars_process_chip"); - break; - } - - // insert chip into SMP data structure given node & chip ID - rc = proc_setup_bars_insert_chip(smp_chip, - io_smp); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_process_chips: Error from proc_setup_bars_insert_chip"); - break; - } - } - if (!rc.ok()) - { - break; - } - - // perform final adjustment on node specific resources once - // all chips have been processed - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter; - for (n_iter = io_smp.nodes.begin(); - n_iter != io_smp.nodes.end(); - n_iter++) - { - FAPI_DBG("Performing final adjustment on n%d", n_iter->first); - - // update node address ranges (non-mirrored & mirrored) - FAPI_DBG("proc_setup_bars_process_chips: Ranges after merging:"); - n_iter->second.non_mirrored_range.print(); - n_iter->second.mirrored_range.print(); - - // update node address ranges (non-mirrored & mirrored) to - // ensure ranges are power of 2 aligned - FAPI_DBG("proc_setup_bars_process_chips: Node %d ranges after power of two alignment:", - n_iter->first); - if (n_iter->second.non_mirrored_range.enabled && - !n_iter->second.non_mirrored_range.is_power_of_2()) - { - n_iter->second.non_mirrored_range.round_next_power_of_2(); - } - n_iter->second.non_mirrored_range.print(); - - if (n_iter->second.mirrored_range.enabled && - !n_iter->second.mirrored_range.is_power_of_2()) - { - n_iter->second.mirrored_range.round_next_power_of_2(); - } - n_iter->second.mirrored_range.print(); - } - if (!rc.ok()) - { - break; - } - } while(0); - - // mark function exit - FAPI_DBG("proc_setup_bars_process_chips: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility function to write HW BAR register given address range -// structure and register definition structure -// parameters: i_target => chip target -// i_scom_addr => BAR SCOM address -// i_bar_reg_def => structure defining rules to format address -// range content into register layout -// i_addr_range => structure defining BAR address range -// (enable/base/size) -// returns: FAPI_RC_SUCCESS if register write is successful, -// RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF if BAR register definition -// structure is invalid, -// RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size -// translation is unsuccessful, -// else failing return code from SCOM/data buffer manipulation -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_common_write_bar_reg( - const fapi::Target& i_target, - const uint32_t& i_scom_addr, - const proc_setup_bars_bar_reg_def& i_bar_reg_def, - const proc_setup_bars_addr_range& i_addr_range) -{ - // return code - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - // BAR register data buffer - ecmdDataBufferBase bar_data(64); - ecmdDataBufferBase bar_data_mask(64); - ecmdDataBufferBase size_data(64); - ecmdDataBufferBase static_data(64); - ecmdDataBufferBase static_data_mask(64); - - FAPI_DBG("proc_setup_bars_common_write_bar_reg: Start"); - do - { - // write base address - if (i_bar_reg_def.has_base) - { - // previous checking ensures zeroes for all non-implemented bits - rc_ecmd |= bar_data.setDoubleWord(0, i_addr_range.base_addr); - // shift position to proper location in register - if (i_bar_reg_def.base_shift == PROC_SETUP_BARS_SHIFT_LEFT) - { - rc_ecmd |= bar_data.shiftLeft(i_bar_reg_def.base_shift_amount); - } - else if (i_bar_reg_def.base_shift == PROC_SETUP_BARS_SHIFT_RIGHT) - { - rc_ecmd |= bar_data.shiftRight(i_bar_reg_def.base_shift_amount); - } - else if (i_bar_reg_def.base_shift != PROC_SETUP_BARS_SHIFT_NONE) - { - FAPI_ERR("proc_setup_bars_common_write_bar_reg: Invalid base shift value in register definition"); - const fapi::Target & TARGET = i_target; - const uint32_t & SCOM_ADDR = i_scom_addr; - const uint64_t & BASE_ADDR = i_addr_range.base_addr; - const bool & ENABLED = i_addr_range.enabled; - const uint64_t & SIZE = i_addr_range.size; - FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF); - break; - } - // set mask - rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.base_start_bit, - (i_bar_reg_def.base_end_bit - - i_bar_reg_def.base_start_bit + 1)); - } - - // write enable bit - if (i_bar_reg_def.has_enable) - { - rc_ecmd |= bar_data.writeBit(i_bar_reg_def.enable_bit, - i_addr_range.enabled ? 1 : 0); - rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.enable_bit); - } - - // write size field - if (i_bar_reg_def.has_size) - { - // encoded size value for register programming - std::map<uint64_t, uint64_t>::const_iterator s; - uint64_t size_xlate; - // translate size into register encoding - s = i_bar_reg_def.xlate_map->find(i_addr_range.size); - if (s == i_bar_reg_def.xlate_map->end()) - { - FAPI_ERR("proc_setup_bars_common_write_bar_reg: Unsupported BAR size 0x%016llX", - i_addr_range.size); - const fapi::Target & TARGET = i_target; - const uint32_t & SCOM_ADDR = i_scom_addr; - const uint64_t & BASE_ADDR = i_addr_range.base_addr; - const bool & ENABLED = i_addr_range.enabled; - const uint64_t & SIZE = i_addr_range.size; - FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_SIZE_XLATE_ERR); - break; - } - size_xlate = s->second; - - rc_ecmd |= size_data.setDoubleWord(0, size_xlate); - rc_ecmd |= size_data.shiftLeft(63 - i_bar_reg_def.size_end_bit); - rc_ecmd |= bar_data.merge(size_data); - rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.size_start_bit, - (i_bar_reg_def.size_end_bit - - i_bar_reg_def.size_start_bit + 1)); - } - - // merge static data & mask - rc_ecmd |= static_data.setDoubleWord( - 0, - i_bar_reg_def.static_data); - rc_ecmd |= static_data_mask.setDoubleWord( - 0, - i_bar_reg_def.static_data_mask); - - rc_ecmd |= bar_data.merge(static_data); - rc_ecmd |= bar_data_mask.merge(static_data_mask); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("proc_setup_bars_common_write_bar_reg: Error 0x%X setting up BAR data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // write BAR register with updated content - rc = fapiPutScomUnderMask(i_target, - i_scom_addr, - bar_data, - bar_data_mask); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_common_write_bar_reg: fapiPutScomUnderMask error (%08X)", - i_scom_addr); - break; - } - } while(0); - - FAPI_DBG("proc_setup_bars_common_write_bar_reg: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: write L3 BAR attributes (consumed by winkle image creation -// procedures) specific to enabled local chip -// non-mirrored/mirrored memory ranges -// parameters: i_target => chip target -// i_is_non_mirrored_range => boolean idenitfying range type -// (true=non-mirrored, false=mirrored) -// i_addr_range => structure representing chip -// non-mirrored/mirrored range -// returns: FAPI_RC_SUCCESS if attribute writes are successful, -// RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size -// translation is unsuccessful, -// else failing return code from attribute/data buffer manipulation -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr( - const fapi::Target* i_target, - const bool i_is_non_mirrored_range, - const proc_setup_bars_addr_range& i_addr_range) -{ - // return code - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - // BAR1 register data buffer - ecmdDataBufferBase bar_data(64); - ecmdDataBufferBase bar_size_data(64); - uint64_t bar_attr_data; - - FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Start"); - do - { - // previous checking ensures zeroes for all non-implemented bits - rc_ecmd |= bar_data.setDoubleWord(0, i_addr_range.base_addr); - rc_ecmd |= bar_data.shiftLeft(L3_BAR12_BASE_ADDR_LEFT_SHIFT_AMOUNT); - - // encoded size value for register programming - std::map<uint64_t, uint64_t>::const_iterator s; - uint64_t size_xlate; - // translate size into register encoding - s = proc_setup_bars_nf_bar_size::xlate_map.find(i_addr_range.size); - if (s == proc_setup_bars_nf_bar_size::xlate_map.end()) - { - FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Unsupported BAR size 0x%016llX", - i_addr_range.size); - const fapi::Target & TARGET = *i_target; - const uint32_t & SCOM_ADDR = EX_L3_BAR1_REG_0x1001080B; - const uint64_t & BASE_ADDR = i_addr_range.base_addr; - const bool & ENABLED = i_addr_range.enabled; - const uint64_t & SIZE = i_addr_range.size; - FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_SIZE_XLATE_ERR); - break; - } - size_xlate = s->second; - rc_ecmd |= bar_size_data.setDoubleWord(0, size_xlate); - rc_ecmd |= bar_size_data.shiftLeft(63 - L3_BAR12_SIZE_END_BIT); - rc_ecmd |= bar_data.merge(bar_size_data); - - // enable bit only in BAR2 - if (!i_is_non_mirrored_range) - { - rc_ecmd |= bar_data.writeBit(L3_BAR2_ENABLE_BIT, - i_addr_range.enabled ? 1 : 0); - } - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error 0x%X setting up BAR data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // set data for attribute push - bar_attr_data = bar_data.getDoubleWord(0); - - if (i_is_non_mirrored_range) - { - // L3 BAR1 (non-mirrored) - FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Setting ATTR_PROC_L3_BAR1_REG = %016llX", - bar_attr_data); - rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR1_REG, - i_target, - bar_attr_data); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error setting ATTR_PROC_L3_BAR1_REG"); - break; - } - } - else - { - // L3 BAR2 (mirrored) - FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Setting ATTR_PROC_L3_BAR2_REG = %016llX", - bar_attr_data); - rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR2_REG, - i_target, - bar_attr_data); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error setting ATTR_PROC_L3_BAR2_REG"); - break; - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write PCIe BARs specific to enabled local -// chip non-mirrored/mirrored memory ranges -// parameters: i_target => chip target -// i_num_phb => number of PHBs -// i_non_mirrored_range => structure representing chip non-mirrored -// address range -// i_mirrored_range => structure representing chip mirrored -// address range -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars( - const fapi::Target& i_target, - const uint8_t i_num_phb, - const proc_setup_bars_addr_range& i_non_mirrored_range, - const proc_setup_bars_addr_range& i_mirrored_range) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Start"); - // loop over all units - for (uint8_t u = 0; - u < i_num_phb; - u++) - { - if (i_non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Writing PCIe %d Nodal Non-Mirrored BAR register", - u); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - i_non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_local_chip_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (i_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Writing PCIe %d Nodal Mirrored BAR register", - u); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - i_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_local_chip_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - - FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: write L3 BAR attributes (consumed by winkle image creation -// procedures) specific to enabled local node -// non-mirrored/mirrored memory ranges -// parameters: i_target => chip target -// i_is_non_mirrored_range => boolean idenitfying range type -// (true=non-mirrored, false=mirrored) -// i_node_addr_range => structure representing node -// non-mirrored/mirrored range -// i_chip_addr_range => structure representing chip -// non-mirrored/mirrored range -// returns: FAPI_RC_SUCCESS if attribute writes are successful, -// else failing return code from attribute/data buffer manipulation -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr( - const fapi::Target* i_target, - const bool i_is_non_mirrored_range, - const proc_setup_bars_addr_range& i_node_addr_range, - const proc_setup_bars_addr_range& i_chip_addr_range) -{ - // return code - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - ecmdDataBufferBase base(64); - ecmdDataBufferBase diff(64); - ecmdDataBufferBase mask(64); - uint64_t mask_attr = 0x0; - - FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Start"); - - do - { - // retrieve mask register attribute - rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG, - i_target, - mask_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error querying ATTR_PROC_L3_BAR_GROUP_MASK_REG"); - break; - } - FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Read ATTR_PROC_L3_BAR_GROUP_MASK_REG = %016llX", - mask_attr); - // push current value into data buffer - rc_ecmd |= mask.setDoubleWord(0, mask_attr); - - // set group mask based on first difference between - // node start/end addresses - uint32_t first_diff_bit = 0; - // load base address - rc_ecmd |= base.setDoubleWord(0, i_node_addr_range.base_addr); - // load end address - rc_ecmd |= diff.setDoubleWord(0, i_node_addr_range.end_addr()); - // XOR base/end address - rc_ecmd |= diff.setXor(base, 0, 64); - - // walk range of XOR result over group mask, stop at first 1 found - bool match_found = false; - for (first_diff_bit = L3_BAR_GROUP_MASK_RA_DIFF_START_BIT; - first_diff_bit <= L3_BAR_GROUP_MASK_RA_DIFF_END_BIT; - first_diff_bit++) - { - if (diff.getBit(first_diff_bit)) - { - match_found = true; - break; - } - } - - if (match_found) - { - // set all group mask bits to a 1, starting from first bit which - // was found to be different, to the end of the mask range - uint32_t mask_set_start_bit = (i_is_non_mirrored_range)? - L3_BAR_GROUP_MASK_NON_MIRROR_MASK_START_BIT: - L3_BAR_GROUP_MASK_MIRROR_MASK_START_BIT; - - mask_set_start_bit += (first_diff_bit- - L3_BAR_GROUP_MASK_RA_DIFF_START_BIT); - - uint32_t mask_set_num_bits = (i_is_non_mirrored_range)? - L3_BAR_GROUP_MASK_NON_MIRROR_MASK_END_BIT: - L3_BAR_GROUP_MASK_MIRROR_MASK_END_BIT; - - mask_set_num_bits -= (mask_set_start_bit-1); - - rc_ecmd |= mask.setBit(mask_set_start_bit, - mask_set_num_bits); - } - - // enable bit only for mirorred region - if (!i_is_non_mirrored_range) - { - rc_ecmd |= mask.writeBit(L3_BAR_GROUP_MASK_MIRROR_ENABLE_BIT, - i_node_addr_range.enabled ? 1 : 0); - } - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error 0x%X setting up BAR mask data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - // push current data buffer state back into attribute - mask_attr = mask.getDoubleWord(0); - FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Setting ATTR_PROC_L3_BAR_GROUP_MASK_REG = %016llX", - mask_attr); - rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR_GROUP_MASK_REG, - i_target, - mask_attr); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error setting ATTR_PROC_L3_BAR_GROUP_MASK_REG"); - break; - } - - // if no memory is installed on the local chip, fill the shared - // BAR address with the node base - if (!i_chip_addr_range.enabled) - { - // clear size mask - proc_setup_bars_addr_range base_addr_range = i_node_addr_range; - base_addr_range.size = PROC_SETUP_BARS_SIZE_4_GB; - - rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr( - i_target, - i_is_non_mirrored_range, - base_addr_range); - - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr"); - break; - } - } - } while(0); - - - FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write PCIe BARs specific to enabled local -// node non-mirrored/mirrored memory ranges -// parameters: i_target => chip target -// i_num_phb => number of PHBs -// i_non_mirrored_range => structure representing node non-mirrored -// address range -// i_mirrored_range => structure representing node mirrored -// address range -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars( - const fapi::Target& i_target, - const uint8_t i_num_phb, - const proc_setup_bars_addr_range& i_non_mirrored_range, - const proc_setup_bars_addr_range& i_mirrored_range) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Start"); - // loop over all units - for (uint8_t u = 0; - u < i_num_phb; - u++) - { - if (i_non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Writing PCIe %d Group Non-Mirrored BAR register", - u); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - i_non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_local_node_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (i_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Writing PCIe %d Group Mirrored BAR register", - u); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - i_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_local_node_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - - FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write PCIe BARs specific to enabled local -// chip near/far foreign memory ranges -// NOTE: only links which are marked for processing will be acted on -// parameters: i_target => chip target -// i_num_phb => number of PHBs -// i_process_links => array of boolean values dictating which -// links should be acted on (one per link) -// i_foreign_near_ranges => array of structures representing -// near foreign address range (one per link) -// i_foreign_far_ranges => array of structures representing -// far foreign address range (one per link) -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars( - const fapi::Target& i_target, - const uint8_t i_num_phb, - const bool i_process_links[PROC_FAB_SMP_NUM_F_LINKS], - const proc_setup_bars_addr_range i_foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS], - const proc_setup_bars_addr_range i_foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS]) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Start"); - - // loop over all units - for (uint8_t u = 0; - (u < i_num_phb) && (rc.ok()); - u++) - { - // process ranges - for (uint8_t r = 0; - (r < PROC_FAB_SMP_NUM_F_LINKS) && (rc.ok()); - r++) - { - if (i_foreign_near_ranges[r].enabled && i_process_links[r]) - { - FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Writing PCIe %d Foreign F%d Near BAR register", - u, r); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[u][r], - common_f_scope_bar_reg_def, - i_foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_foreign_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (i_foreign_far_ranges[r].enabled && i_process_links[r]) - { - FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Writing PCIe %d Foreign F%d Far BAR register", - u, r); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[u][r], - common_f_scope_bar_reg_def, - i_foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_foreign_memory_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - } - - FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write enabled PCIe IO BARs -// parameters: i_target => chip target -// i_num_phb => number of PHBs -// io_addr_ranges => 2D array of address range structures -// encapsulating attribute values -// (first dimension = unit, second dimension = -// links per unit) -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function or -// data buffer manipulation -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs( - const fapi::Target& i_target, - const uint8_t i_num_phb, - const proc_setup_bars_addr_range addr_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]) -{ - // return code - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Start"); - // loop over all units - for (uint8_t u = 0; - u < i_num_phb; - u++) - { - // enable bit/mask bit per range - ecmdDataBufferBase enable_data(64); - ecmdDataBufferBase enable_mask(64); - - // loop over all ranges - for (uint8_t r = 0; - r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT; - r++) - { - if (addr_ranges[u][r].enabled) - { - // MMIO range (BAR + mask) - if (PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[r]) - { - // write BAR register - FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d MMIO BAR%d register", - u, r); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[u][r], - pcie_mmio_bar_reg_def, - addr_ranges[u][r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // write BAR mask register - FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d MMIO BAR%d Mask register", - u, r); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[u][r], - pcie_mmio_bar_mask_reg_def, - addr_ranges[u][r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - // PHB range (only BAR, mask is implied) - else - { - for (uint8_t i = 0; - i < PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE; - i++) - { - FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d PHB BAR (%s) register", - u, (i == 0)?("Nest"):("PCIe")); - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[u][i], - pcie_phb_bar_reg_def, - addr_ranges[u][r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (!rc.ok()) - { - break; - } - } - // set enable bit data/mask - rc_ecmd |= enable_data.setBit( - PROC_SETUP_BARS_PCIE_BAR_EN_BIT[r]); - rc_ecmd |= enable_mask.setBit( - PROC_SETUP_BARS_PCIE_BAR_EN_BIT[r]); - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error 0x%X setting up BAR Enable data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - } - } - if (!rc.ok()) - { - break; - } - - if (enable_data.getDoubleWord(0) != 0x0ULL) - { - // set static data field with BAR enable bits - proc_setup_bars_bar_reg_def pcie_bar_en_reg_def = - { - false, // base: other reg - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 0, - 0, - false, // enable: static data - 0, - false, // size: other reg - 0, - 0, - NULL, - enable_data.getDoubleWord(0), - enable_mask.getDoubleWord(0) - }; - proc_setup_bars_addr_range pcie_bar_en_dummy_range; - - // write BAR enable register (do last, when all unit BAR content is set) - rc = proc_setup_bars_common_write_bar_reg( - i_target, - PROC_SETUP_BARS_PCIE_BAR_EN_REGS[u], - pcie_bar_en_reg_def, - pcie_bar_en_dummy_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // if enabling BARs, pull ETU out of reset - ecmdDataBufferBase etu_reset(64); - rc = fapiPutScom(i_target, - PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[u], - etu_reset); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from fapiPutScom (PCIE%d_ETU_RESET_0x%08X)", - u, PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[u]); - break; - } - } - } - - FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write all BARs tied to local chip region -// (non-mirrored/mirrored/MMIO regions) -// parameters: i_smp_chip => structure encapsulating single chip in SMP topology -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -// -// Local chip region BARs: -// -// PSI/FSP -// PSI Bridge BAR (PSI_BRIDGE_BAR_0x0201090A) -// FSP BAR (PSI_FSP_BAR_0x0201090B) -// FSP Memory Mask (PSI_FSP_MMR_0x0201090C) -// FSP MMIO Mask (PSI_BRIDGE_STATUS_CTL_0x0201090E) -// -// INTP -// INTP BAR (ICP_BAR_0x020109CA) -// -// L3 (transmitted via attributes) -// L3 BAR1 (Non-Mirrored) (EX_L3_BAR1_0x1001080B) -// L3 BAR2 (Mirrored) (EX_L3_BAR2_0x10010813) -// -// NX -// NX MMIO BAR (NX_MMIO_BAR_0x0201308D) -// NX CXA0 Nodal Non-Mirrored BAR (NX_APC_NODAL_BAR0_0x0201302D) -// NX CXA1 Nodal Non-Mirrored BAR (NX_CXA1_APC_NODAL_BAR0_0x020131AD) -// NX Nodal Non-Mirrored BAR (NX_NODAL_BAR0_0x02013095) -// NX CXA0 Nodal Mirrored BAR (NX_APC_NODAL_BAR1_0x0201302E) -// NX CXA1 Nodal Mirrored BAR (NX_CXA1_APC_NODAL_BAR1_0x020131AE) -// NX Nodal Mirrored BAR (NX_NODAL_BAR1_0x02013096) -// -// NPU -// NPU0 Nodal Non-Mirrored BAR (NPU0_NODAL_BAR0_0x08013C04) -// NPU0 Nodal Mirrored BAR (NPU0_NODAL_BAR1_0x08013C05) -// NPU1 Nodal Non-Mirrored BAR (NPU1_NODAL_BAR0_0x08013C44) -// NPU1 Nodal Mirrored BAR (NPU1_NODAL_BAR1_0x08013C45) -// NPU2 Nodal Non-Mirrored BAR (NPU2_NODAL_BAR0_0x08013D04) -// NPU2 Nodal Mirrored BAR (NPU2_NODAL_BAR1_0x08013D05) -// NPU3 Nodal Non-Mirrored BAR (NPU3_NODAL_BAR0_0x08013D44) -// NPU3 Nodal Mirrored BAR (NPU3_NODAL_BAR1_0x08013D45) -// -// NPU0 MMIO BAR0 (NPU0_MMIO_BAR0_0x08013C02) -// NPU0 MMIO BAR1 (NPU0_MMIO_BAR1_0x08013C03) -// NPU1 MMIO BAR0 (NPU1_MMIO_BAR0_0x08013C42) -// NPU1 MMIO BAR1 (NPU1_MMIO_BAR1_0x08013C43) -// NPU2 MMIO BAR0 (NPU2_MMIO_BAR0_0x08013D02) -// NPU2 MMIO BAR1 (NPU2_MMIO_BAR1_0x08013D03) -// NPU3 MMIO BAR0 (NPU3_MMIO_BAR0_0x08013D42) -// NPU3 MMIO BAR1 (NPU3_MMIO_BAR1_0x08013D43) -// -// HCA -// HCA EN BAR and Range Register (HCA_EN_BAR_0x0201094A) -// HCA EN Mirror BAR and Range Register (HCA_EN_MIRROR_BAR_0x02010953) -// HCA EH BAR and Range Register (HCA_EH_BAR_0x0201098A) -// HCA EH Mirror BAR and Range Register (HCA_EH_MIRROR_BAR_0x02010993) -// -// MCD -// MCD Configuration 0 (Non-Mirrored) (MCD_CN00_0x0201340C) -// MCD Configuration 1 (Mirrored) (MCD_CN01_0x0201340D) -// -// PCIe -// PCIE0 Nodal Non-Mirrored BAR (PCIE0_NODAL_BAR0_0x02012010) -// PCIE0 Nodal Mirrored BAR (PCIE0_NODAL_BAR1_0x02012011) -// PCIE0 IO BAR0 (PCIE0_IO_BAR0_0x02012040) -// PCIE0 IO BAR0 Mask (PCIE0_IO_MASK0_0x02012043) -// PCIE0 IO BAR1 (PCIE0_IO_BAR1_0x02012041) -// PCIE0 IO BAR1 Mask (PCIE0_IO_MASK1_0x02012044) -// PCIE0 IO BAR2 (PCIE0_IO_BAR2_0x02012042) -// PCIE0 IO BAR Enable (PCIE0_IO_BAR_EN_0x02012045) -// -// PCIE1 Nodal Non-Mirrored BAR (PCIE1_NODAL_BAR0_0x02012410) -// PCIE1 Nodal Mirrored BAR (PCIE1_NODAL_BAR1_0x02012411) -// PCIE1_IO BAR0 (PCIE1_IO_BAR0_0x02012440) -// PCIE1_IO BAR0 Mask (PCIE1_IO_MASK0_0x02012443) -// PCIE1_IO BAR1 (PCIE1_IO_BAR1_0x02012441) -// PCIE1_IO BAR1 Mask (PCIE1_IO_MASK1_0x02012444) -// PCIE1_IO BAR2 (PCIE1_IO_BAR2_0x02012442) -// PCIE1_IO BAR Enable (PCIE1_IO_BAR_EN_0x02012445) -// -// PCIE2 Nodal Non-Mirrored BAR (PCIE2_NODAL_BAR0_0x02012810) -// PCIE2 Nodal Mirrored BAR (PCIE2_NODAL_BAR1_0x02012811) -// PCIE2 IO BAR0 (PCIE2_IO_BAR0_0x02012840) -// PCIE2 IO BAR0 Mask (PCIE2_IO_MASK0_0x02012843) -// PCIE2 IO BAR1 (PCIE2_IO_BAR1_0x02012841) -// PCIE2 IO BAR1 Mask (PCIE2_IO_MASK1_0x02012844) -// PCIE2 IO BAR2 (PCIE2_IO_BAR2_0x02012842) -// PCIE2 IO BAR Enable (PCIE2_IO_BAR_EN_0x02012845) -// -// PCIE3 Nodal Non-Mirrored BAR (PCIE3_NODAL_BAR0_0x02012C10) -// PCIE3 Nodal Mirrored BAR (PCIE3_NODAL_BAR1_0x02012C11) -// PCIE3 IO BAR0 (PCIE3_IO_BAR0_0x02012C40) -// PCIE3 IO BAR0 Mask (PCIE3_IO_MASK0_0x02012C43) -// PCIE3 IO BAR1 (PCIE3_IO_BAR1_0x02012C41) -// PCIE3 IO BAR1 Mask (PCIE3_IO_MASK1_0x02012C44) -// PCIE3 IO BAR2 (PCIE3_IO_BAR2_0x02012C42) -// PCIE3 IO BAR Enable (PCIE3_IO_BAR_EN_0x02012C45) -// -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_write_local_chip_region_bars( - proc_setup_bars_smp_chip& i_smp_chip) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Start"); - - do - { - // PSI - if (i_smp_chip.psi_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PSI_BRIDGE_BAR_0x0201090A, - psi_bridge_bar_reg_def, - i_smp_chip.psi_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // FSP - if (i_smp_chip.fsp_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing FSP BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PSI_FSP_BAR_0x0201090B, - fsp_bar_reg_def, - i_smp_chip.fsp_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing FSP Memory Mask register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PSI_FSP_MMR_0x0201090C, - fsp_bar_mask_reg_def, - i_smp_chip.fsp_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge Status Control register (FSP BAR enable)"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PSI_BRIDGE_STATUS_CTL_0x0201090E, - fsp_bar_en_reg_def, - i_smp_chip.fsp_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.fsp_mmio_mask_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge Status Control register (FSP MMIO mask)"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PSI_BRIDGE_STATUS_CTL_0x0201090E, - fsp_mmio_mask_reg_def, - i_smp_chip.fsp_mmio_mask_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - - // INTP - if (i_smp_chip.intp_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing INTP BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - ICP_BAR_0x020109CA, - intp_bar_reg_def, - i_smp_chip.intp_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // NX (MMIO) - if (i_smp_chip.nx_mmio_range.enabled && i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX MMIO BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_MMIO_BAR_0x0201308D, - nx_mmio_bar_reg_def, - i_smp_chip.nx_mmio_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing AS MMIO BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_AS_MMIO_BAR_0x0201309E, - as_mmio_bar_reg_def, - i_smp_chip.as_mmio_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // NX (non-mirrored) - if (i_smp_chip.non_mirrored_range.enabled && i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA0 APC Nodal Non-Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_APC_NODAL_BAR0_0x0201302D, - common_nf_scope_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.dual_capp_present) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA1 APC Nodal Non-Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_CXA1_APC_NODAL_BAR0_0x020131AD, - common_nf_scope_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX Nodal Non-Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_NODAL_BAR0_0x02013095, - common_nf_scope_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // NX (mirrored) - if (i_smp_chip.mirrored_range.enabled && i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA0 APC Nodal Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_APC_NODAL_BAR1_0x0201302E, - common_nf_scope_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.dual_capp_present) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA1 APC Nodal Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_CXA1_APC_NODAL_BAR1_0x020131AE, - common_nf_scope_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX Nodal Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_NODAL_BAR1_0x02013096, - common_nf_scope_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // NPU (non-mirrored) - if (i_smp_chip.non_mirrored_range.enabled && i_smp_chip.nv_present) - { - for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NPU%d Nodal Non-Mirrored BAR register", u); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PROC_SETUP_BARS_NPU_CHIP_NON_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (!rc.ok()) - { - break; - } - } - - // NPU (mirrored) - if (i_smp_chip.mirrored_range.enabled && i_smp_chip.nv_present) - { - for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NPU%d Nodal Mirrored BAR register", u); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PROC_SETUP_BARS_NPU_CHIP_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (!rc.ok()) - { - break; - } - } - - // NPU (MMIO) - if (i_smp_chip.nv_present) - { - for (uint8_t u = 0; (u < PROC_SETUP_BARS_NPU_NUM_UNITS); u++) - { - for (uint8_t r = 0; (r < PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT); r++) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NPU%d MMIO BAR%d register", u, r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PROC_SETUP_BARS_NPU_MMIO_BAR[u][r], - npu_mmio_bar_reg_def, - i_smp_chip.npu_mmio_ranges[u][r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (!rc.ok()) - { - break; - } - } - if (!rc.ok()) - { - break; - } - } - - // HCA (non-mirrored) - if (i_smp_chip.non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EN BAR and Range (Non-Mirrored) register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - HCA_EN_BAR_0x0201094A, - hca_nm_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EH BAR and Range (Non-Mirrored) register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - HCA_EH_BAR_0x0201098A, - hca_nm_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // HCA (mirrored) - if (i_smp_chip.mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EN Mirror BAR and Range (Mirrored) register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - HCA_EN_MIRROR_BAR_0x02010953, - hca_m_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EH Mirror BAR and Range (Mirrored) register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - HCA_EH_MIRROR_BAR_0x02010993, - hca_m_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // MCD (non-mirrored) - if (i_smp_chip.non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 0 (Non-Mirrored) register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - MCD_CN00_0x0201340C, - mcd_nf_bar_reg_def, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // MCD (mirrored) - if (i_smp_chip.mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 1 (Mirrored) register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - MCD_CN01_0x0201340D, - mcd_nf_bar_reg_def, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // L3 (non-mirrored) - if (i_smp_chip.non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing L3 BAR1 (Non-Mirrored) attribute"); - rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr( - &(i_smp_chip.chip->this_chip), - true, - i_smp_chip.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr"); - break; - } - } - - // L3 (mirrored) - if (i_smp_chip.mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing L3 BAR2 (Mirrored) attribute"); - rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr( - &(i_smp_chip.chip->this_chip), - false, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr"); - break; - } - } - - // PCIe (non-mirrored/mirrored) - if (i_smp_chip.pcie_enabled) - { - rc = proc_setup_bars_pcie_write_local_chip_memory_bars( - i_smp_chip.chip->this_chip, - i_smp_chip.num_phb, - i_smp_chip.non_mirrored_range, - i_smp_chip.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_local_chip_memory_bars"); - break; - } - } - - // PCIe (IO) - if (i_smp_chip.pcie_enabled) - { - rc = proc_setup_bars_pcie_write_io_bar_regs( - i_smp_chip.chip->this_chip, - i_smp_chip.num_phb, - i_smp_chip.pcie_ranges); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_io_bar_regs"); - break; - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write all BARs tied to local node region -// (non-mirrored/mirrored regions) -// parameters: i_smp_chip => structure encapsulating single chip in SMP topology -// i_smp_node => structure encapsulating node which this chip -// resides in -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -// -// Local node region BARs: -// -// L3 (transmitted via attributes) -// L3 BAR Group Mask (EX_L3_BAR_GROUP_MASK_0x10010816) -// -// NX -// NX CXA0 Group Non-Mirorred BAR (NX_APC_GROUP_BAR0_0x0201302F) -// NX CXA1 Group Non-Mirorred BAR (NX_CXA1_APC_GROUP_BAR0_0x020131AF) -// NX Group Non-Mirorred BAR (NX_GROUP_BAR0_0x02013097) -// NX CXA0 Group Mirrored BAR (NX_APC_GROUP_BAR1_0x02013030) -// NX CXA1 Group Mirrored BAR (NX_CXA1_APC_GROUP_BAR1_0x020131B0) -// NX Group Mirrored BAR (NX_GROUP_BAR1_0x02013098) -// -// NPU -// NPU0 Group Non-Mirrored BAR (NPU0_GROUP_BAR0_0x08013C06) -// NPU0 Group Mirrored BAR (NPU0_GROUP_BAR1_0x08013C07) -// NPU1 Group Non-Mirrored BAR (NPU1_GROUP_BAR0_0x08013C46) -// NPU1 Group Mirrored BAR (NPU1_GROUP_BAR1_0x08013C47) -// NPU2 Group Non-Mirrored BAR (NPU2_GROUP_BAR0_0x08013D06) -// NPU2 Group Mirrored BAR (NPU2_GROUP_BAR1_0x08013D07) -// NPU3 Group Non-Mirrored BAR (NPU3_GROUP_BAR0_0x08013D46) -// NPU3 Group Mirrored BAR (NPU3_GROUP_BAR1_0x08013D47) -// -// PCIe -// PCIE0 Group Non-Mirrored BAR (PCIE0_GROUP_BAR0_0x02012012) -// PCIE0 Group Mirrored BAR (PCIE0_GROUP_BAR1_0x02012013) -// -// PCIE1 Group Non-Mirrored BAR (PCIE1_GROUP_BAR0_0x02012412) -// PCIE1 Group Mirrored BAR (PCIE1_GROUP_BAR1_0x02012413) -// -// PCIE2 Group Non-Mirrored BAR (PCIE2_GROUP_BAR0_0x02012812) -// PCIE2 Group Mirrored BAR (PCIE2_GROUP_BAR1_0x02012813) -// -// PCIE3 Group Non-Mirrored BAR (PCIE3_GROUP_BAR0_0x02012C12) -// PCIE3 Group Mirrored BAR (PCIE3_GROUP_BAR1_0x02012C13) -// -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_write_local_node_region_bars( - proc_setup_bars_smp_chip& i_smp_chip, - proc_setup_bars_smp_node& i_smp_node) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Start"); - - // set non-mirrored/mirrored ranges based on group=chip EC feature attribute - proc_setup_bars_addr_range non_mirrored_range = - ((i_smp_chip.init_group_as_chip)?(i_smp_chip.non_mirrored_range):(i_smp_node.non_mirrored_range)); - proc_setup_bars_addr_range mirrored_range = - ((i_smp_chip.init_group_as_chip)?(i_smp_chip.mirrored_range):(i_smp_node.mirrored_range)); - - do - { - // NX (non-mirrored) - if (non_mirrored_range.enabled && i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA0 APC Group Non-Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_APC_GROUP_BAR0_0x0201302F, - common_nf_scope_bar_reg_def, - non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.dual_capp_present) - { - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA1 APC Group Non-Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_CXA1_APC_GROUP_BAR0_0x020131AF, - common_nf_scope_bar_reg_def, - non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX Group Non-Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_GROUP_BAR0_0x02013097, - common_nf_scope_bar_reg_def, - non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // NX (mirrored) - if (mirrored_range.enabled && i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA0 APC Group Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_APC_GROUP_BAR1_0x02013030, - common_nf_scope_bar_reg_def, - mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.dual_capp_present) - { - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA1 APC Group Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_CXA1_APC_GROUP_BAR1_0x020131B0, - common_nf_scope_bar_reg_def, - mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX Group Mirrored BAR register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - NX_GROUP_BAR1_0x02013098, - common_nf_scope_bar_reg_def, - mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - // NPU (non-mirrored) - if (non_mirrored_range.enabled && i_smp_chip.nv_present) - { - for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) - { - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NPU%d Group Non-Mirrored BAR register", u); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PROC_SETUP_BARS_NPU_NODE_NON_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (!rc.ok()) - { - break; - } - - } - - // NPU (mirrored) - if (mirrored_range.enabled && i_smp_chip.nv_present) - { - for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) - { - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NPU%d Group Mirrored BAR register", u); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PROC_SETUP_BARS_NPU_NODE_MIRRORED_BAR[u], - common_nf_scope_bar_reg_def, - mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - if (!rc.ok()) - { - break; - } - } - - // L3 (non-mirrored) - if (non_mirrored_range.enabled) - { - rc = proc_setup_bars_l3_write_local_node_memory_bar_attr( - &(i_smp_chip.chip->this_chip), - true, - non_mirrored_range, - i_smp_chip.non_mirrored_range); - - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_l3_write_local_node_memory_bar_attr"); - break; - } - } - - // L3 (mirrored) - if (mirrored_range.enabled) - { - rc = proc_setup_bars_l3_write_local_node_memory_bar_attr( - &(i_smp_chip.chip->this_chip), - false, - mirrored_range, - i_smp_chip.mirrored_range); - - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_l3_write_local_node_memory_bar_attr"); - break; - } - } - - // PCIe (non-mirrored/mirrored) - if (i_smp_chip.pcie_enabled) - { - rc = proc_setup_bars_pcie_write_local_node_memory_bars( - i_smp_chip.chip->this_chip, - i_smp_chip.num_phb, - non_mirrored_range, - mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_pcie_write_local_node_memory_bars"); - break; - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_write_local_node_region_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write all BARs tied to remote node regions -// (non-mirrored/mirrored regions) -// parameters: i_smp_chip => structure encapsulating single chip in SMP -// topology -// i_smp_node_a0 => structure encapsulating node reachable from -// A0 link on this chip -// i_smp_node_a1 => structure encapsulating node reachable from -// A1 link on this chip -// i_smp_node_a2 => structure encapsulating node reachable from -// A2 link on this chip -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -// -// Remote node region BARs: -// -// PB -// PB Remote Group (A0) Non-Mirrored BAR (PB_RGMCFG00_0x02010C58) -// PB Remote Group (A0) Mirrored BAR (PB_RGMCFGM00_0x02010C5B) -// PB Remote Group (A1) Non-Mirrored BAR (PB_RGMCFG01_0x02010C59) -// PB Remote Group (A1) Mirrored BAR (PB_RGMCFGM01_0x02010C5C) -// PB Remote Group (A2) Non-Mirrored BAR (PB_RGMCFG10_0x02010C5A) -// PB Remote Group (A2) Mirrored BAR (PB_RGMCFGM10_0x02010C5D) -// -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_write_remote_node_region_bars( - proc_setup_bars_smp_chip& i_smp_chip, - proc_setup_bars_smp_node& i_smp_node_a0, - proc_setup_bars_smp_node& i_smp_node_a1, - proc_setup_bars_smp_node& i_smp_node_a2) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Start"); - - do - { - // A0 (non-mirrored) - if (i_smp_node_a0.non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A0) Non-Mirrored Configuration register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PB_RGMCFG00_0x02010C58, - common_nf_scope_bar_reg_def, - i_smp_node_a0.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // A0 (mirrored) - if (i_smp_node_a0.mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A0) Mirrored Configuration register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PB_RGMCFGM00_0x02010C5B, - common_nf_scope_bar_reg_def, - i_smp_node_a0.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // A1 (non-mirrored) - if (i_smp_node_a1.non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A1) Non-Mirrored Configuration register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PB_RGMCFG01_0x02010C59, - common_nf_scope_bar_reg_def, - i_smp_node_a1.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // A1 (mirrored) - if (i_smp_node_a1.mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A1) Mirrored Configuration register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PB_RGMCFGM01_0x02010C5C, - common_nf_scope_bar_reg_def, - i_smp_node_a1.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // A2 (non-mirrored) - if (i_smp_node_a2.non_mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A2) Non-Mirrored Configuration register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PB_RGMCFG10_0x02010C5A, - common_nf_scope_bar_reg_def, - i_smp_node_a2.non_mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // A2 (mirrored) - if (i_smp_node_a2.mirrored_range.enabled) - { - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A2) Mirrored Configuration register"); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - PB_RGMCFGM10_0x02010C5D, - common_nf_scope_bar_reg_def, - i_smp_node_a2.mirrored_range); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write all BARs tied to local chip foreign -// regions (near/far) -// parameters: i_smp_chip => structure encapsulating single chip in SMP -// topology -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from common BAR write function -//------------------------------------------------------------------------------ -// -// Foreign region BARs: -// -// PB -// PB F0 Near BAR (West) (PB_FLMCFG0_WEST_0x02010C12) -// PB F0 Near BAR (Center) (PB_FLMCFG0_CENT_0x02010C5E) -// PB F0 Near BAR (East) (PB_FLMCFG0_EAST_0x02010C92) -// PB F0 Far BAR (West) (PB_FRMCFG0_WEST_0x02010C14) -// PB F0 Far BAR (Center) (PB_FRMCFG0_CENT_0x02010C60) -// PB F0 Far BAR (East) (PB_FRMCFG0_EAST_0x02010C94) -// PB F1 Near BAR (West) (PB_FLMCFG1_WEST_0x02010C13) -// PB F1 Near BAR (Center) (PB_FLMCFG1_CENT_0x02010C5F) -// PB F1 Near BAR (East) (PB_FLMCFG1_EAST_0x02010C93) -// PB F1 Far BAR (West) (PB_FRMCFG1_WEST_0x02010C15) -// PB F1 Far BAR (Center) (PB_FRMCFG1_CENT_0x02010C61) -// PB F1 Far BAR (East) (PB_FRMCFG1_EAST_0x02010C95) -// -// NX -// NX CXA0 APC F0 Near BAR (NX_APC_NEAR_BAR_F0_0x02013031) -// NX CXA1 APC F0 Near BAR (NX_CXA1_APC_NEAR_BAR_F0_0x020131B1) -// NX CXA0 APC F0 Far BAR (NX_APC_FAR_BAR_F0_0x02013032) -// NX CXA1 APC F0 Far BAR (NX_CXA1_APC_FAR_BAR_F0_0x020131B2) -// NX CXA0 APC F1 Near BAR (NX_APC_NEAR_BAR_F1_0x02013033) -// NX CXA1 APC F1 Near BAR (NX_CXA1_APC_NEAR_BAR_F1_0x020131B3) -// NX CXA0 APC F1 Far BAR (NX_APC_FAR_BAR_F1_0x02013034) -// NX CXA1 APC F1 Far BAR (NX_CXA1_APC_FAR_BAR_F1_0x020131B4) -// NX F0 Near BAR (NX_NEAR_BAR_F0_0x02013099) -// NX F0 Far BAR (NX_FAR_BAR_F0_0x0201309A) -// NX F1 Near BAR (NX_NEAR_BAR_F1_0x0201309B) -// NX F1 Far BAR (NX_FAR_BAR_F1_0x0201309C) -// -// MCD -// MCD Configuration 2 (F0) (MCD_CN10_0x0201340E) -// MCD Configuration 3 (F1) (MCD_CN11_0x0201340F) -// -// PCIe -// PCIE0 F0 Near BAR (PCIE0_NEAR_BAR_F0_0x02012014) -// PCIE0 F0 Far BAR (PCIE0_FAR_BAR_F0_0x02012015) -// PCIE0 F1 Near BAR (PCIE0_NEAR_BAR_F1_0x02012016) -// PCIE0 F1 Far BAR (PCIE0_FAR_BAR_F1_0x02012017) -// -// PCIE1 F0 Near BAR (PCIE1_NEAR_BAR_F0_0x02012414) -// PCIE1 F0 Far BAR (PCIE1_FAR_BAR_F0_0x02012415) -// PCIE1 F1 Near BAR (PCIE1_NEAR_BAR_F1_0x02012416) -// PCIE1 F1 Far BAR (PCIE1_FAR_BAR_F1_0x02012417) -// -// PCIE2 F0 Near BAR (PCIE2_NEAR_BAR_F0_0x02012814) -// PCIE2 F0 Far BAR (PCIE2_FAR_BAR_F0_0x02012815) -// PCIE2 F1 Near BAR (PCIE2_NEAR_BAR_F1_0x02012816) -// PCIE2 F1 Far BAR (PCIE2_FAR_BAR_F1_0x02012817) -// -// PCIE3 F0 Near BAR (PCIE3_NEAR_BAR_F0_0x02012C14) -// PCIE3 F0 Far BAR (PCIE3_FAR_BAR_F0_0x02012C15) -// PCIE3 F1 Near BAR (PCIE3_NEAR_BAR_F1_0x02012C16) -// PCIE3 F1 Far BAR (PCIE3_FAR_BAR_F1_0x02012C17) -// -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_write_foreign_region_bars( - proc_setup_bars_smp_chip& i_smp_chip) -{ - // return code - fapi::ReturnCode rc; - - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Start"); - - do - { - bool process_links[PROC_FAB_SMP_NUM_F_LINKS] = - { - i_smp_chip.chip->process_f0, - i_smp_chip.chip->process_f1 - }; - - // PCIe (near/far) - if (i_smp_chip.pcie_enabled) - { - rc = proc_setup_bars_pcie_write_foreign_memory_bars( - i_smp_chip.chip->this_chip, - i_smp_chip.num_phb, - process_links, - i_smp_chip.foreign_near_ranges, - i_smp_chip.foreign_far_ranges); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_pcie_write_foreign_memory_bars"); - break; - } - } - - // process ranges - for (uint8_t r = 0; - (r < PROC_FAB_SMP_NUM_F_LINKS) && (rc.ok()); - r++) - { - // near - if (process_links[r] && - i_smp_chip.foreign_near_ranges[r].enabled) - { - // PB (near, west) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (West) register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - PB_FLMCFG0_WEST_0x02010C12: - PB_FLMCFG1_WEST_0x02010C13, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // PB (near, cent) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (Center) register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - PB_FLMCFG0_CENT_0x02010C5E: - PB_FLMCFG1_CENT_0x02010C5F, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // PB (near, east) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (East) register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - PB_FLMCFG0_EAST_0x02010C92: - PB_FLMCFG1_EAST_0x02010C93, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // NX APC (near) - if (i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA0 APC F%d Near BAR register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - NX_APC_NEAR_BAR_F0_0x02013031: - NX_APC_NEAR_BAR_F1_0x02013033, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.dual_capp_present) - { - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA1 APC F%d Near BAR register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - NX_CXA1_APC_NEAR_BAR_F0_0x020131B1: - NX_CXA1_APC_NEAR_BAR_F1_0x020131B3, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - - // NX (near) - if (i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Near BAR register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - NX_NEAR_BAR_F0_0x02013099: - NX_NEAR_BAR_F1_0x0201309B, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // MCD (near only) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing MCD Configuration %d (F%d) register", - r+1, r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - MCD_CN10_0x0201340E: - MCD_CN11_0x0201340F, - (r == 0)? - mcd_f0_bar_reg_def: - mcd_f1_bar_reg_def, - i_smp_chip.foreign_near_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - - // far - if (process_links[r] && - i_smp_chip.foreign_near_ranges[r].enabled) - { - // PB (far, west) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (West) register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - PB_FRMCFG0_WEST_0x02010C14: - PB_FRMCFG1_WEST_0x02010C15, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // PB (far, center) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (Center) register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - PB_FRMCFG0_CENT_0x02010C60: - PB_FRMCFG1_CENT_0x02010C61, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // PB (far, east) - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (East) register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - PB_FRMCFG0_EAST_0x02010C94: - PB_FRMCFG1_EAST_0x02010C95, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - // NX APC (far) - if (i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA0 APC F%d Far BAR register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - NX_APC_FAR_BAR_F0_0x02013032: - NX_APC_FAR_BAR_F1_0x02013034, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - - if (i_smp_chip.dual_capp_present) - { - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA1 APC F%d Far BAR register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - NX_CXA1_APC_FAR_BAR_F0_0x020131B2: - NX_CXA1_APC_FAR_BAR_F1_0x020131B4, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - - // NX (far) - if (i_smp_chip.nx_enabled) - { - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Far BAR register", - r); - rc = proc_setup_bars_common_write_bar_reg( - i_smp_chip.chip->this_chip, - (r == 0)? - NX_FAR_BAR_F0_0x0201309A: - NX_FAR_BAR_F1_0x0201309C, - common_f_scope_bar_reg_def, - i_smp_chip.foreign_far_ranges[r]); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg"); - break; - } - } - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_write_foreign_region_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: utility function to find node structure associated with a given -// target -// parameters: i_target => chip target -// i_smp => structure encapsulating SMP topology -// o_node => node structure associated with chip target input -// returns: FAPI_RC_SUCCESS if matching node is found -// RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR if node map lookup is -// unsuccessful, -// else failing return code from node ID attribute query function -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_find_node( - const fapi::Target& i_target, - proc_setup_bars_smp_system& i_smp, - proc_setup_bars_smp_node& o_node) -{ - // return code - fapi::ReturnCode rc; - proc_fab_smp_node_id node_id; - - FAPI_DBG("proc_setup_bars_find_node: Start"); - - do - { - // get node ID attribute - FAPI_DBG("proc_setup_find_node: Querying node ID attribute"); - rc = proc_fab_smp_get_node_id_attr(&(i_target), - node_id); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_find_node: Error from proc_fab_smp_get_node_id_attr"); - break; - } - - // search to see if node structure already exists for the node ID - // associated with this chip - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator - n_iter; - n_iter = i_smp.nodes.find(node_id); - // no match node found, exit - if (n_iter == i_smp.nodes.end()) - { - FAPI_ERR("proc_setup_bars_find_node: insert_chip: Error encountered finding node in SMP map"); - const fapi::Target & TARGET = i_target; - const proc_fab_smp_node_id & NODE_ID = node_id; - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR); - break; - } - o_node = n_iter->second; - } while(0); - - FAPI_DBG("proc_setup_bars_find_node: End"); - return rc; -} - -//------------------------------------------------------------------------------ -// function: check that all address ranges are non-overlapping -// parameters: i_smp => structure encapsulating fully -// specified SMP topology -// returns: FAPI_RC_SUCCESS if all ranges are non-overlapping -// else RC_PROC_SETUP_BARS_SYSTEM_RANGE_OVERLAP_ERR -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_check_bars( - proc_setup_bars_smp_system& i_smp) -{ - // return code - fapi::ReturnCode rc; - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter; - std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator p_iter; - - std::vector<proc_setup_bars_addr_range*> sys_ranges; - std::vector<fapi::Target*> targets; - - // fsp_mmio_mask_range specifically excluded, as this range by itself - // does not represent an active portion of real address space - const uint32_t ranges_per_chip = 7 + - (2* PROC_FAB_SMP_NUM_F_LINKS) + - (PROC_SETUP_BARS_NPU_NUM_UNITS * PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT) + - (PROC_SETUP_BARS_PCIE_NUM_UNITS * PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT); - - FAPI_DBG("proc_setup_bars_check_bars: Start"); - - do - { - for (n_iter = i_smp.nodes.begin(); - n_iter != i_smp.nodes.end(); - n_iter++) - { - for (p_iter = n_iter->second.chips.begin(); - p_iter != n_iter->second.chips.end(); - p_iter++) - { - targets.push_back(&(p_iter->second.chip->this_chip)); - - sys_ranges.push_back(&(p_iter->second.non_mirrored_range)); - sys_ranges.push_back(&(p_iter->second.mirrored_range)); - for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++) - { - sys_ranges.push_back(&(p_iter->second.foreign_near_ranges[l])); - } - for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++) - { - sys_ranges.push_back(&(p_iter->second.foreign_far_ranges[l])); - } - sys_ranges.push_back(&(p_iter->second.psi_range)); - sys_ranges.push_back(&(p_iter->second.fsp_range)); - sys_ranges.push_back(&(p_iter->second.intp_range)); - sys_ranges.push_back(&(p_iter->second.nx_mmio_range)); - sys_ranges.push_back(&(p_iter->second.as_mmio_range)); - for (uint8_t u = 0; u < PROC_SETUP_BARS_PCIE_NUM_UNITS; u++) - { - for (uint8_t r = 0; r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT; r++) - { - sys_ranges.push_back(&(p_iter->second.pcie_ranges[u][r])); - } - } - for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++) - { - for (uint8_t r = 0; r < PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT; r++) - { - sys_ranges.push_back(&(p_iter->second.npu_mmio_ranges[u][r])); - } - } - } - } - - // check that ranges are non-overlapping - if (sys_ranges.size() > 1) - { - for (uint32_t r = 0; (r < sys_ranges.size()-1) && rc.ok(); r++) - { - for (uint32_t x = r+1; x < sys_ranges.size(); x++) - { - if (sys_ranges[r]->overlaps(*(sys_ranges[x]))) - { - uint32_t target_r = r / ranges_per_chip; - uint32_t range_r = r % ranges_per_chip; - uint32_t target_x = x / ranges_per_chip; - uint32_t range_x = x % ranges_per_chip; - - FAPI_ERR("proc_setup_bars_check_bars: Overlapping address regions detected"); - FAPI_ERR(" target: %s, Range index = %d", - targets[target_r]->toEcmdString(), range_r); - sys_ranges[r]->print(); - FAPI_ERR(" target: %s, Range index = %d", - targets[target_x]->toEcmdString(), range_x); - sys_ranges[x]->print(); - - const fapi::Target & TARGET1 = *(targets[target_r]); - const uint32_t RANGE_ID1 = range_r; - const uint64_t & BASE_ADDR1 = sys_ranges[r]->base_addr; - const uint64_t & END_ADDR1 = sys_ranges[r]->end_addr(); - const bool & ENABLED1 = sys_ranges[r]->enabled; - - const fapi::Target & TARGET2 = *(targets[target_x]); - const uint32_t RANGE_ID2 = range_x; - const uint64_t & BASE_ADDR2 = sys_ranges[x]->base_addr; - const uint64_t & END_ADDR2 = sys_ranges[x]->end_addr(); - const bool & ENABLED2 = sys_ranges[x]->enabled; - - FAPI_SET_HWP_ERROR(rc, - RC_PROC_SETUP_BARS_SYSTEM_RANGE_OVERLAP_ERR); - break; - } - } - } - if (!rc.ok()) - { - break; - } - } - - } while(0); - - FAPI_DBG("proc_setup_bars_check_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: wrapper function to write all chip BARs -// parameters: i_smp => structure encapsulating fully -// specified SMP topology -// i_init_local_chip_local_node => boolean qualifying application -// of local chip/local node range -// specific BAR resources -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from lower level BAR write/node search -// functions -//------------------------------------------------------------------------------ -fapi::ReturnCode -proc_setup_bars_write_bars( - proc_setup_bars_smp_system& i_smp, - const bool i_init_local_chip_local_node) -{ - // return code - fapi::ReturnCode rc; - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter; - std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator p_iter; - - FAPI_DBG("proc_setup_bars_write_bars: Start"); - - do - { - for (n_iter = i_smp.nodes.begin(); - (n_iter != i_smp.nodes.end()) && (rc.ok()); - n_iter++) - { - for (p_iter = n_iter->second.chips.begin(); - (p_iter != n_iter->second.chips.end()) && (rc.ok()); - p_iter++) - { - // init local chip/local node resources? - if (i_init_local_chip_local_node) - { - rc = proc_setup_bars_write_local_chip_region_bars( - p_iter->second); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_local_chip_region_bars"); - break; - } - - rc = proc_setup_bars_write_local_node_region_bars( - p_iter->second, - n_iter->second); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_local_node_region_bars"); - break; - } - } - - // determine which remote node ranges should be initialized - proc_setup_bars_smp_node smp_node_a0; - proc_setup_bars_smp_node smp_node_a1; - proc_setup_bars_smp_node smp_node_a2; - if (p_iter->second.chip->a0_chip.getType() != fapi::TARGET_TYPE_NONE) - { - rc = proc_setup_bars_find_node( - p_iter->second.chip->a0_chip, - i_smp, - smp_node_a0); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node"); - break; - } - } - if (p_iter->second.chip->a1_chip.getType() != fapi::TARGET_TYPE_NONE) - { - rc = proc_setup_bars_find_node( - p_iter->second.chip->a1_chip, - i_smp, - smp_node_a1); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node"); - break; - } - } - if (p_iter->second.chip->a2_chip.getType() != fapi::TARGET_TYPE_NONE) - { - rc = proc_setup_bars_find_node( - p_iter->second.chip->a2_chip, - i_smp, - smp_node_a2); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node"); - break; - } - } - - // initialize remote node related ranges - rc = proc_setup_bars_write_remote_node_region_bars( - p_iter->second, - smp_node_a0, - smp_node_a1, - smp_node_a2); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_remote_node_region_bars"); - break; - } - - // initialize foreign link related regions - rc = proc_setup_bars_write_foreign_region_bars( - p_iter->second); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_foreign_region_bars"); - break; - } - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_write_bars: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: enable MCD probes/unmask FIRs -// parameters: i_smp => structure encapsulating fully -// specified SMP topology -// i_init_local_chip_local_node => boolean qualifying application -// of local chip/local node range -// specific BAR resources -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// else failing return code from failing SCOM access -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars_config_mcd( - proc_setup_bars_smp_system& i_smp, - const bool i_init_local_chip_local_node) -{ - // return code - fapi::ReturnCode rc; - uint32_t rc_ecmd = 0; - - ecmdDataBufferBase mcd_fir_mask_data(64); - ecmdDataBufferBase mcd_recov_data(64); - ecmdDataBufferBase mcd_recov_mask(64); - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::const_iterator n_iter; - std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::const_iterator p_iter; - - FAPI_DBG("proc_setup_bars_config_mcd: Start"); - - do - { - for (n_iter = i_smp.nodes.begin(); - (n_iter != i_smp.nodes.end()) && (rc.ok()); - n_iter++) - { - for (p_iter = n_iter->second.chips.begin(); - (p_iter != n_iter->second.chips.end()) && (rc.ok()); - p_iter++) - { - bool config_mcd = false; - bool cfg_enable[PROC_SETUP_BARS_NUM_MCD_CFG] = - { false, false, false, false }; - - // ensure MCD probes are enabled and FIR is unmasked if: - // initializing local chip resources and there is a - // non-mirrored/mirrored range enabled OR - // initializing foreign resources and there is a - // near range enabled - - if (i_init_local_chip_local_node && - (p_iter->second.non_mirrored_range.enabled || - p_iter->second.mirrored_range.enabled)) - { - config_mcd = true; - cfg_enable[0] = p_iter->second.non_mirrored_range.enabled; - cfg_enable[1] = p_iter->second.mirrored_range.enabled; - } - - bool process_f_links[PROC_FAB_SMP_NUM_F_LINKS] = - { - p_iter->second.chip->process_f0, - p_iter->second.chip->process_f1 - }; - - // process ranges - for (uint8_t r = 0; - (r < PROC_FAB_SMP_NUM_F_LINKS); - r++) - { - if (process_f_links[r] && - p_iter->second.foreign_near_ranges[r].enabled) - { - config_mcd = true; - cfg_enable[2+r] = true; - } - } - - if (config_mcd) - { - uint64_t mcd_fir_mask = MCD_FIR_MASK_RUNTIME_VAL; - - // unmask MCD FIR - rc_ecmd |= mcd_fir_mask_data.setDoubleWord( - 0, - mcd_fir_mask); - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("proc_setup_bars_config_mcd: Error 0x%X setting up FIR mask data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScom(p_iter->second.chip->this_chip, - MCD_FIR_MASK_0x02013403, - mcd_fir_mask_data); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_FIR_MASK_0x02013403)"); - break; - } - - // enable MCD probes for selected config registers - rc_ecmd |= mcd_recov_data.setBit(MCD_RECOVERY_ENABLE_BIT); - rc_ecmd |= mcd_recov_mask.setBit(MCD_RECOVERY_ENABLE_BIT); - for (uint8_t i = 0; - i < PROC_SETUP_BARS_NUM_MCD_CFG; - i++) - { - rc_ecmd |= mcd_recov_data.writeBit( - MCD_RECOVERY_CFG_EN_BIT[i], - cfg_enable[i]); - rc_ecmd |= mcd_recov_mask.writeBit( - MCD_RECOVERY_CFG_EN_BIT[i], - cfg_enable[i]); - } - - // check buffer manipulation return codes - if (rc_ecmd) - { - FAPI_ERR("proc_setup_bars_config_mcd: Error 0x%X setting up recovery data buffer", - rc_ecmd); - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScomUnderMask(p_iter->second.chip->this_chip, - MCD_REC_EVEN_0x02013410, - mcd_recov_data, - mcd_recov_mask); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_REC_EVEN_0x02013410)"); - break; - } - - rc = fapiPutScomUnderMask(p_iter->second.chip->this_chip, - MCD_REC_ODD_0x02013411, - mcd_recov_data, - mcd_recov_mask); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_REC_ODD_0x02013411)"); - break; - } - } - } - } - } while(0); - - FAPI_DBG("proc_setup_bars_config_mcd: End"); - return rc; -} - - -//------------------------------------------------------------------------------ -// function: proc_setup_bars HWP entry point -// NOTE: see comments above function prototype in header -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars( - std::vector<proc_setup_bars_proc_chip>& i_proc_chips, - const bool i_init_local_chip_local_node) -{ - // return code - fapi::ReturnCode rc; - // SMP model - proc_setup_bars_smp_system smp; - - // mark HWP entry - FAPI_IMP("proc_setup_bars: Entering ..."); - - do - { - // process all chips passed from platform to HWP, query chip - // specific attributes and insert into system SMP data structure - // given logical node & chip ID - rc = proc_setup_bars_process_chips(i_proc_chips, - smp); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_process_chips"); - break; - } - - // check that all ranges are non-overlapping - rc = proc_setup_bars_check_bars(smp); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_check_bars"); - break; - } - - // write BAR registers - rc = proc_setup_bars_write_bars(smp, - i_init_local_chip_local_node); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_write_bars"); - break; - } - - // configure MCD resources - rc = proc_setup_bars_config_mcd(smp, - i_init_local_chip_local_node); - if (!rc.ok()) - { - FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_config_mcd"); - break; - } - - } while(0); - - // log function exit - FAPI_IMP("proc_setup_bars: Exiting ..."); - return rc; -} - - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H deleted file mode 100644 index 5d64c74ed..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H +++ /dev/null @@ -1,183 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2012,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars.H,v 1.17 2014/08/05 20:43:46 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_setup_bars.H -// *! DESCRIPTION : Program nest base address registers (BARs) (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -// *! ADDITIONAL COMMENTS: -// *! -// *! Program nest unit BAR registers, driven by attributes representing system -// *! memory map (including MMIO). -// *! -// *! High level execution flow: -// *! proc_setup_bars() -// *! proc_setup_bars_process_chips() -// *! proc_setup_bars_process_chip() -// *! proc_fab_smp_get_pcie_dsmp_mux_attrs() -// *! proc_fab_smp_get_node_id_attr() -// *! proc_fab_smp_get_chip_id_attr() -// *! proc_setup_bars_get_bar_attrs() -// *! proc_setup_bars_get_memory_range_attrs (non-mirrored) -// *! proc_setup_bars_get_memory_range_attrs (mirrored) -// *! proc_setup_bars_get_range_attrs (foreign, near) -// *! proc_setup_bars_get_range_attrs (foreign, far) -// *! proc_setup_bars_get_range_attrs (psi) -// *! proc_setup_bars_get_range_attrs (fsp) -// *! proc_setup_bars_get_range_attrs (fsp mmio mask) -// *! proc_setup_bars_get_range_attrs (intp) -// *! proc_setup_bars_get_range_attrs (nx) -// *! proc_setup_bars_get_range_attrs (as) -// *! proc_setup_bars_get_range_attrs (pcie) -// *! proc_setup_bars_insert_chip() -// *! proc_setup_bars_write_bars() -// *! proc_setup_bars_write_local_chip_region_bars() -// *! proc_setup_bars_write_local_node_region_bars() -// *! proc_setup_bars_find_remote_node() -// *! proc_setup_bars_write_remote_node_region_bars() -// *! proc_setup_bars_write_foreign_region_bars() -// *! -// *! Platform Notes: -// *! This HWP has multiple IPL use cases. In all cases the HWP input -// *! is expected to contain an entry for each chip in the SMP at the -// *! time/scope of the invocation: -// *! -// *! 1. HBI (drawer scope): -// *! All local chip/local node resources should be initialized -// *! at this time (HWP boolean flag controlling this function -// *! set to true). -// *! -// *! All A links active in the scope of the drawer should be -// *! reflected in the per-chip HWP input structures. -// *! -// *! 2. FSP (drawer integration): -// *! All local chip/local node resources should already have -// *! been initialized in each drawer, so the HWP boolean flag -// *! controlling this function should be set to false. -// *! -// *! Only 'new' A links which cross previously initialized -// *! drawers should be reflected in the per-chip HWP input -// *! structures. -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_SETUP_BARS_H_ -#define _PROC_SETUP_BARS_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include <vector> -#include <map> -#include <fapi.H> -#include "proc_fab_smp.H" -#include "p8_scom_addresses.H" - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// HWP argument structure defining properties of this chip -// and links which should be considered in this invocation (A/F) -struct proc_setup_bars_proc_chip -{ - // target for this chip - fapi::Target this_chip; - - // targets defining A link connected chips - // qualify which remote node based BAR resources should be initalized on - // this chip - fapi::Target a0_chip; - fapi::Target a1_chip; - fapi::Target a2_chip; - - // init F link related BARs for this chip? - bool process_f0; - bool process_f1; -}; - -// function pointer typedef definition for HWP call support -typedef fapi::ReturnCode -(*proc_setup_bars_FP_t)(std::vector<proc_setup_bars_proc_chip>&, - const bool); - - -extern "C" -{ - -//------------------------------------------------------------------------------ -// Function prototypes -//------------------------------------------------------------------------------ - -//------------------------------------------------------------------------------ -// function: program nest unit BAR registers, driven by attributes representing -// system memory map (including MMIO) -// parameters: i_proc_chips => vector of structures defining properties of each -// chip and links which should be considered in -// this invocation to drive initialization of BARs -// tied to remote node regions (A links) and -// foreign regions (F links) -// i_init_local_chip_local_node => boolean qualifying initilization -// of BARs tied to local chip/local -// node regions -// returns: FAPI_RC_SUCCESS if all register writes are successful, -// RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR if no rule is found to set -// BAR/range address, enable, or size, -// RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR if BAR/range attribute content -// violates expected behavior, -// RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ATTR_OVERLAP_ERR if chip -// memory range attributes specify overlapping address ranges, -// RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ERR if merged -// chip memory address range is invalid, -// RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails, -// RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR if node map lookup is -// unsuccessful, -// RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR if chips with duplicate -// fabric node/chip IDs are detected, -// RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF if BAR register definition -// structure is invalid, -// RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if BAR logical->physical size -// translation is unsuccessful, -// RC_PROC_SETUP_BARS_SYSTEM_RANGE_OVERLAP_ERR if any overapping -// ranges are detected, considering all ranges in system, -// else failing return code -//------------------------------------------------------------------------------ -fapi::ReturnCode proc_setup_bars( - std::vector<proc_setup_bars_proc_chip>& i_proc_chips, - const bool i_init_local_chip_local_node); - -} // extern "C" - - -#endif // _PROC_SETUP_BARS_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H deleted file mode 100644 index 7e70a1e4d..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H +++ /dev/null @@ -1,1332 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2014,2015 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_setup_bars_defs.H,v 1.6 2015/11/10 19:39:58 jmcgill Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars_defs.H,v $ -//------------------------------------------------------------------------------ -// *| -// *! (C) Copyright International Business Machines Corp. 2011 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *| -// *! TITLE : proc_setup_bars_defs.H -// *! DESCRIPTION : Structure/constant definitions for proc_setup_bars HWP (FAPI) -// *! -// *! OWNER NAME : Joe McGill Email: jmcgill@us.ibm.com -// *! -// *! ADDITIONAL COMMENTS: -// *! -//------------------------------------------------------------------------------ - -#ifndef _PROC_SETUP_BARS_DEFS_H_ -#define _PROC_SETUP_BARS_DEFS_H_ - -//------------------------------------------------------------------------------ -// Includes -//------------------------------------------------------------------------------ -#include "proc_setup_bars.H" - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// address range size definition constants -const uint64_t PROC_SETUP_BARS_SIZE_1_PB = 0x0004000000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_512_TB = 0x0002000000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_256_TB = 0x0001000000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_128_TB = 0x0000800000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_64_TB = 0x0000400000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_32_TB = 0x0000200000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_16_TB = 0x0000100000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_8_TB = 0x0000080000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_4_TB = 0x0000040000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_2_TB = 0x0000020000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_1_TB = 0x0000010000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_512_GB = 0x0000008000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_256_GB = 0x0000004000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_128_GB = 0x0000002000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_64_GB = 0x0000001000000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_32_GB = 0x0000000800000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_16_GB = 0x0000000400000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_8_GB = 0x0000000200000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_4_GB = 0x0000000100000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_2_GB = 0x0000000080000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_1_GB = 0x0000000040000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_512_MB = 0x0000000020000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_256_MB = 0x0000000010000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_128_MB = 0x0000000008000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_64_MB = 0x0000000004000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_32_MB = 0x0000000002000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_16_MB = 0x0000000001000000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_8_MB = 0x0000000000800000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_4_MB = 0x0000000000400000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_2_MB = 0x0000000000200000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_1_MB = 0x0000000000100000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_512_KB = 0x0000000000080000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_256_KB = 0x0000000000040000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_128_KB = 0x0000000000020000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_64_KB = 0x0000000000010000ULL; -const uint64_t PROC_SETUP_BARS_SIZE_4_KB = 0x0000000000001000ULL; - -// memory (non-mirrored/mirrored) constants -const uint8_t PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES = 8; -const uint8_t PROC_SETUP_BARS_NUM_MIRRORED_RANGES = 4; - -// PCIe unit contstants -const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 4; -const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT = 3; - -// NPU unit constants -const uint8_t PROC_SETUP_BARS_NPU_NUM_UNITS = 4; -const uint8_t PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT = 2; - - -//------------------------------------------------------------------------------ -// Structure definitions -//------------------------------------------------------------------------------ - -// structure to represent range of FBC real address space -struct proc_setup_bars_addr_range -{ - // default constructor (mark range disabled) - proc_setup_bars_addr_range() : - enabled(false), - base_addr(0), - size(0) - { - } - - // constructor - proc_setup_bars_addr_range( - const uint64_t& range_base_addr, - const uint64_t& range_size) : - enabled(range_size != 0), - base_addr(range_base_addr), - size(range_size) - { - } - - // determine if region size is power of 2 aligned - bool is_power_of_2() const - { - return ((size != 0) && !(size & (size - 1))); - } - - // round region size to next largest power of 2 - void round_next_power_of_2() - { - size = size - 1; - size = size | (size >> 1); - size = size | (size >> 2); - size = size | (size >> 4); - size = size | (size >> 8); - size = size | (size >> 16); - size = size | (size >> 32); - size = size + 1; - } - - // return ending address of range - uint64_t end_addr() const - { - return(base_addr + size - 1); - } - - // check for overlapping ranges - bool overlaps(const proc_setup_bars_addr_range& range_compare) const - { - // if either range is disabled, consider them non-overlapping - return(enabled && - range_compare.enabled && - (base_addr <= range_compare.end_addr()) && - (end_addr() >= range_compare.base_addr)); - } - - // merge two ranges (span breadth of both ranges) - void merge(const proc_setup_bars_addr_range& range_new) - { - // if range is disabled, set values to track those of new - // range (which may also be disabled) - if (!enabled) - { - enabled = range_new.enabled; - base_addr = range_new.base_addr; - size = range_new.size; - } - // if new range is disabled, leave as-is - // otherwise merge two valid ranges - else if (range_new.enabled) - { - uint64_t new_start_addr; - uint64_t new_end_addr; - - // calculate new base address (smaller of the two start addresses) - if (base_addr < range_new.base_addr) - { - new_start_addr = base_addr; - } - else - { - new_start_addr = range_new.base_addr; - } - // calculate new end address (larger of the two end addresses) - if (end_addr() > range_new.end_addr()) - { - new_end_addr = end_addr(); - } - else - { - new_end_addr = range_new.end_addr(); - } - // set new range values - base_addr = new_start_addr; - size = (new_end_addr - new_start_addr + 1); - } - } - - // check that if region size aligns exactly to base address range - // (i.e., no overlap between BAR and size) - bool is_aligned() const - { - return ((base_addr & (size - 1)) == 0x0ULL); - } - - // does range lie completely within FBC address range? - bool is_in_fbc_range() const - { - return ((base_addr < PROC_FAB_SMP_MAX_ADDRESS) && - (end_addr() < PROC_FAB_SMP_MAX_ADDRESS)); - } - - // utility function to display address range information - void print() const - { - FAPI_DBG("proc_setup_bars_print_addr_range: %s :: [ %016llX-%016llX ]", - (enabled)?("E"):("D"), - base_addr, - end_addr()); - } - - bool enabled; - uint64_t base_addr; - uint64_t size; -}; - -// structure to represent fabric connectivty & properites for a single chip -// in the SMP topology -struct proc_setup_bars_smp_chip -{ - // associated HWP input structure - proc_setup_bars_proc_chip* chip; - - // chip properties/attributes: - // fabric chip/node ID - proc_fab_smp_chip_id chip_id; - proc_fab_smp_node_id node_id; - // partial good attributes - bool nx_enabled; - bool pcie_enabled; - bool nv_present; - bool init_group_as_chip; - bool dual_capp_present; - // number of valid PCIe PHBs - uint8_t num_phb; - // select for PCIe/DSMP mux (one per link) - bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]; - // real address ranges covered by resources on this chip - proc_setup_bars_addr_range non_mirrored_range; - proc_setup_bars_addr_range mirrored_range; - proc_setup_bars_addr_range foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS]; - proc_setup_bars_addr_range foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS]; - proc_setup_bars_addr_range psi_range; - proc_setup_bars_addr_range fsp_range; - proc_setup_bars_addr_range fsp_mmio_mask_range; - proc_setup_bars_addr_range intp_range; - proc_setup_bars_addr_range nx_mmio_range; - proc_setup_bars_addr_range as_mmio_range; - proc_setup_bars_addr_range npu_mmio_ranges[PROC_SETUP_BARS_NPU_NUM_UNITS][PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT]; - proc_setup_bars_addr_range pcie_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT]; -}; - -// structure to represent properties for a single node in the SMP topology -struct proc_setup_bars_smp_node -{ - // chips which reside in this node - std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip> chips; - - // node properties/attributes: - // fabric node ID - proc_fab_smp_node_id node_id; - // real address ranges covered for mirrored & non-mirrored regions - // (considering all chips in node) - proc_setup_bars_addr_range non_mirrored_range; - proc_setup_bars_addr_range mirrored_range; -}; - -// structure to represent collection of nodes in SMP topology -struct proc_setup_bars_smp_system -{ - // nodes which reside in this SMP - std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node> nodes; -}; - -// define set of shared design non-foreign BAR sizes -struct proc_setup_bars_nf_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_64_TB] = 0x3FFFULL; - m[PROC_SETUP_BARS_SIZE_32_TB] = 0x1FFFULL; - m[PROC_SETUP_BARS_SIZE_16_TB] = 0x0FFFULL; - m[PROC_SETUP_BARS_SIZE_8_TB] = 0x07FFULL; - m[PROC_SETUP_BARS_SIZE_4_TB] = 0x03FFULL; - m[PROC_SETUP_BARS_SIZE_2_TB] = 0x01FFULL; - m[PROC_SETUP_BARS_SIZE_1_TB] = 0x00FFULL; - m[PROC_SETUP_BARS_SIZE_512_GB] = 0x007FULL; - m[PROC_SETUP_BARS_SIZE_256_GB] = 0x003FULL; - m[PROC_SETUP_BARS_SIZE_128_GB] = 0x001FULL; - m[PROC_SETUP_BARS_SIZE_64_GB] = 0x000FULL; - m[PROC_SETUP_BARS_SIZE_32_GB] = 0x0007ULL; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x0003ULL; - m[PROC_SETUP_BARS_SIZE_8_GB] = 0x0001ULL; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x0000ULL; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of shared design foreign BAR sizes -struct proc_setup_bars_f_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_8_TB] = 0x7FFFFULL; - m[PROC_SETUP_BARS_SIZE_4_TB] = 0x3FFFFULL; - m[PROC_SETUP_BARS_SIZE_2_TB] = 0x1FFFFULL; - m[PROC_SETUP_BARS_SIZE_1_TB] = 0x0FFFFULL; - m[PROC_SETUP_BARS_SIZE_512_GB] = 0x07FFFULL; - m[PROC_SETUP_BARS_SIZE_256_GB] = 0x03FFFULL; - m[PROC_SETUP_BARS_SIZE_128_GB] = 0x01FFFULL; - m[PROC_SETUP_BARS_SIZE_64_GB] = 0x00FFFULL; - m[PROC_SETUP_BARS_SIZE_32_GB] = 0x007FFULL; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x003FFULL; - m[PROC_SETUP_BARS_SIZE_8_GB] = 0x001FFULL; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x000FFULL; - m[PROC_SETUP_BARS_SIZE_2_GB] = 0x0007FULL; - m[PROC_SETUP_BARS_SIZE_1_GB] = 0x0003FULL; - m[PROC_SETUP_BARS_SIZE_512_MB] = 0x0001FULL; - m[PROC_SETUP_BARS_SIZE_256_MB] = 0x0000FULL; - m[PROC_SETUP_BARS_SIZE_128_MB] = 0x00007ULL; - m[PROC_SETUP_BARS_SIZE_64_MB] = 0x00003ULL; - m[PROC_SETUP_BARS_SIZE_32_MB] = 0x00001ULL; - m[PROC_SETUP_BARS_SIZE_16_MB] = 0x00000ULL; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of FSP BAR sizes -struct proc_setup_bars_fsp_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x000ULL; - m[PROC_SETUP_BARS_SIZE_2_GB] = 0x800ULL; - m[PROC_SETUP_BARS_SIZE_1_GB] = 0xC00ULL; - m[PROC_SETUP_BARS_SIZE_512_MB] = 0xE00ULL; - m[PROC_SETUP_BARS_SIZE_256_MB] = 0xF00ULL; - m[PROC_SETUP_BARS_SIZE_128_MB] = 0xF80ULL; - m[PROC_SETUP_BARS_SIZE_64_MB] = 0xFC0ULL; - m[PROC_SETUP_BARS_SIZE_32_MB] = 0xFE0ULL; - m[PROC_SETUP_BARS_SIZE_16_MB] = 0xFF0ULL; - m[PROC_SETUP_BARS_SIZE_8_MB] = 0xFF8ULL; - m[PROC_SETUP_BARS_SIZE_4_MB] = 0xFFCULL; - m[PROC_SETUP_BARS_SIZE_2_MB] = 0xFFEULL; - m[PROC_SETUP_BARS_SIZE_1_MB] = 0xFFFULL; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of FSP MMIO mask sizes -struct proc_setup_bars_fsp_mmio_mask_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0xF; - m[PROC_SETUP_BARS_SIZE_2_GB] = 0x7; - m[PROC_SETUP_BARS_SIZE_1_GB] = 0x3; - m[PROC_SETUP_BARS_SIZE_512_MB] = 0x1; - m[PROC_SETUP_BARS_SIZE_256_MB] = 0x0; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of NX MMIO mask sizes -struct proc_setup_bars_nx_mmio_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x2; - m[PROC_SETUP_BARS_SIZE_16_MB] = 0x4; - m[PROC_SETUP_BARS_SIZE_1_MB] = 0x3; - m[PROC_SETUP_BARS_SIZE_64_KB] = 0x1; - m[PROC_SETUP_BARS_SIZE_4_KB] = 0x0; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of NPU MMIO mask sizes -struct proc_setup_bars_npu_mmio_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_2_MB] = 0x5; - m[PROC_SETUP_BARS_SIZE_1_MB] = 0x4; - m[PROC_SETUP_BARS_SIZE_512_KB] = 0x3; - m[PROC_SETUP_BARS_SIZE_256_KB] = 0x2; - m[PROC_SETUP_BARS_SIZE_128_KB] = 0x1; - m[PROC_SETUP_BARS_SIZE_64_KB] = 0x0; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of AS MMIO mask sizes -struct proc_setup_bars_as_mmio_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_2_MB] = 0x3; - m[PROC_SETUP_BARS_SIZE_1_MB] = 0x2; - m[PROC_SETUP_BARS_SIZE_512_KB] = 0x1; - m[PROC_SETUP_BARS_SIZE_256_KB] = 0x0; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of HCA BAR sizes -struct proc_setup_bars_hca_nm_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_2_TB] = 0x1FFULL; - m[PROC_SETUP_BARS_SIZE_1_TB] = 0x0FFULL; - m[PROC_SETUP_BARS_SIZE_512_GB] = 0x07FULL; - m[PROC_SETUP_BARS_SIZE_256_GB] = 0x03FULL; - m[PROC_SETUP_BARS_SIZE_128_GB] = 0x01FULL; - m[PROC_SETUP_BARS_SIZE_64_GB] = 0x00FULL; - m[PROC_SETUP_BARS_SIZE_32_GB] = 0x007ULL; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x003ULL; - m[PROC_SETUP_BARS_SIZE_8_GB] = 0x001ULL; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x000ULL; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of MCD BAR sizes -struct proc_setup_bars_mcd_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_32_TB] = 0x1FFFFFULL; - m[PROC_SETUP_BARS_SIZE_16_TB] = 0x0FFFFFULL; - m[PROC_SETUP_BARS_SIZE_8_TB] = 0x07FFFFULL; - m[PROC_SETUP_BARS_SIZE_4_TB] = 0x03FFFFULL; - m[PROC_SETUP_BARS_SIZE_2_TB] = 0x01FFFFULL; - m[PROC_SETUP_BARS_SIZE_1_TB] = 0x00FFFFULL; - m[PROC_SETUP_BARS_SIZE_512_GB] = 0x007FFFULL; - m[PROC_SETUP_BARS_SIZE_256_GB] = 0x003FFFULL; - m[PROC_SETUP_BARS_SIZE_128_GB] = 0x001FFFULL; - m[PROC_SETUP_BARS_SIZE_64_GB] = 0x000FFFULL; - m[PROC_SETUP_BARS_SIZE_32_GB] = 0x0007FFULL; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x0003FFULL; - m[PROC_SETUP_BARS_SIZE_8_GB] = 0x0001FFULL; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x0000FFULL; - m[PROC_SETUP_BARS_SIZE_2_GB] = 0x00007FULL; - m[PROC_SETUP_BARS_SIZE_1_GB] = 0x00003FULL; - m[PROC_SETUP_BARS_SIZE_512_MB] = 0x00001FULL; - m[PROC_SETUP_BARS_SIZE_256_MB] = 0x00000FULL; - m[PROC_SETUP_BARS_SIZE_128_MB] = 0x000007ULL; - m[PROC_SETUP_BARS_SIZE_64_MB] = 0x000003ULL; - m[PROC_SETUP_BARS_SIZE_32_MB] = 0x000001ULL; - m[PROC_SETUP_BARS_SIZE_16_MB] = 0x000000ULL; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// define set of PCIe MMIO BAR (BAR0/1 only) sizes -struct proc_setup_bars_pcie_bar_size -{ - static std::map<uint64_t, uint64_t> create_map() - { - std::map<uint64_t, uint64_t> m; - m[PROC_SETUP_BARS_SIZE_1_PB] = 0x000000000ULL; - m[PROC_SETUP_BARS_SIZE_512_TB] = 0x200000000ULL; - m[PROC_SETUP_BARS_SIZE_256_TB] = 0x300000000ULL; - m[PROC_SETUP_BARS_SIZE_128_TB] = 0x380000000ULL; - m[PROC_SETUP_BARS_SIZE_64_TB] = 0x3C0000000ULL; - m[PROC_SETUP_BARS_SIZE_32_TB] = 0x3E0000000ULL; - m[PROC_SETUP_BARS_SIZE_16_TB] = 0x3F0000000ULL; - m[PROC_SETUP_BARS_SIZE_8_TB] = 0x3F8000000ULL; - m[PROC_SETUP_BARS_SIZE_4_TB] = 0x3FC000000ULL; - m[PROC_SETUP_BARS_SIZE_2_TB] = 0x3FE000000ULL; - m[PROC_SETUP_BARS_SIZE_1_TB] = 0x3FF000000ULL; - m[PROC_SETUP_BARS_SIZE_512_GB] = 0x3FF800000ULL; - m[PROC_SETUP_BARS_SIZE_256_GB] = 0x3FFC00000ULL; - m[PROC_SETUP_BARS_SIZE_128_GB] = 0x3FFE00000ULL; - m[PROC_SETUP_BARS_SIZE_64_GB] = 0x3FFF00000ULL; - m[PROC_SETUP_BARS_SIZE_32_GB] = 0x3FFF80000ULL; - m[PROC_SETUP_BARS_SIZE_16_GB] = 0x3FFFC0000ULL; - m[PROC_SETUP_BARS_SIZE_8_GB] = 0x3FFFE0000ULL; - m[PROC_SETUP_BARS_SIZE_4_GB] = 0x3FFFF0000ULL; - m[PROC_SETUP_BARS_SIZE_2_GB] = 0x3FFFF8000ULL; - m[PROC_SETUP_BARS_SIZE_1_GB] = 0x3FFFFC000ULL; - m[PROC_SETUP_BARS_SIZE_512_MB] = 0x3FFFFE000ULL; - m[PROC_SETUP_BARS_SIZE_256_MB] = 0x3FFFFF000ULL; - m[PROC_SETUP_BARS_SIZE_128_MB] = 0x3FFFFF800ULL; - m[PROC_SETUP_BARS_SIZE_64_MB] = 0x3FFFFFC00ULL; - m[PROC_SETUP_BARS_SIZE_32_MB] = 0x3FFFFFE00ULL; - m[PROC_SETUP_BARS_SIZE_16_MB] = 0x3FFFFFF00ULL; - m[PROC_SETUP_BARS_SIZE_8_MB] = 0x3FFFFFF80ULL; - m[PROC_SETUP_BARS_SIZE_4_MB] = 0x3FFFFFFC0ULL; - m[PROC_SETUP_BARS_SIZE_2_MB] = 0x3FFFFFFE0ULL; - m[PROC_SETUP_BARS_SIZE_1_MB] = 0x3FFFFFFF0ULL; - m[PROC_SETUP_BARS_SIZE_512_KB] = 0x3FFFFFFF8ULL; - m[PROC_SETUP_BARS_SIZE_256_KB] = 0x3FFFFFFFCULL; - m[PROC_SETUP_BARS_SIZE_128_KB] = 0x3FFFFFFFEULL; - m[PROC_SETUP_BARS_SIZE_64_KB] = 0x3FFFFFFFFULL; - return m; - } - static const std::map<uint64_t, uint64_t> xlate_map; -}; - -// structure to represent logical HW BAR properties -struct proc_setup_bars_bar_def -{ - // mask for implemented base address bits (1 for all non implemented bits) - uint64_t base_addr_mask; - // minimum/maximum supported size values - uint64_t size_min; - uint64_t size_max; - // check that base address/size are aligned? - bool check_aligned; -}; - -// define set of supported shift operations for aligning logical -// BAR base address to physical position in HW register -enum proc_setup_bars_shift_base -{ - PROC_SETUP_BARS_SHIFT_LEFT, - PROC_SETUP_BARS_SHIFT_RIGHT, - PROC_SETUP_BARS_SHIFT_NONE -}; - -// set of BAR/range attribute identifiers -enum proc_setup_bars_attr_id -{ - PROC_SETUP_BARS_ATTR_ID_NM = 0, - PROC_SETUP_BARS_ATTR_ID_M = 1, - PROC_SETUP_BARS_ATTR_ID_FN = 2, - PROC_SETUP_BARS_ATTR_ID_FF = 3, - PROC_SETUP_BARS_ATTR_ID_PSI = 4, - PROC_SETUP_BARS_ATTR_ID_FSP = 5, - PROC_SETUP_BARS_ATTR_ID_FSP_MMIO = 6, - PROC_SETUP_BARS_ATTR_ID_INTP = 7, - PROC_SETUP_BARS_ATTR_ID_NX = 8, - PROC_SETUP_BARS_ATTR_ID_AS = 9, - PROC_SETUP_BARS_ATTR_ID_PCIE = 10, - PROC_SETUP_BARS_ATTR_ID_NPU = 11 -}; - -// encoding for RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR types -enum proc_setup_bars_attr_lookup_err_type -{ - PROC_SETUP_BARS_BASE_ADDR_ATTR_LOOKUP_ERR = 0, - PROC_SETUP_BARS_ENABLE_ATTR_LOOKUP_ERR = 1, - PROC_SETUP_BARS_SIZE_ATTR_LOOKUP_ERR = 2 -}; - -// structure to represent physical HW BAR register programming -struct proc_setup_bars_bar_reg_def -{ - // base address programming information - bool has_base; - proc_setup_bars_shift_base base_shift; - uint8_t base_shift_amount; - uint8_t base_start_bit; - uint8_t base_end_bit; - // enable programming information - bool has_enable; - uint8_t enable_bit; - // size programming information - bool has_size; - uint8_t size_start_bit; - uint8_t size_end_bit; - // translate logical size to register programming - const std::map<uint64_t, uint64_t>* xlate_map; - // static value/mask to be written along with BAR content - uint64_t static_data; - uint64_t static_data_mask; -}; - -//------------------------------------------------------------------------------ -// Constant definitions -//------------------------------------------------------------------------------ - -// non-mirrored range constants -const proc_setup_bars_bar_def non_mirrored_range_def = -{ - 0xFFFC0000FFFFFFFFULL, // base: RA 14:63 - PROC_SETUP_BARS_SIZE_4_GB, // size (min): 4 GB - PROC_SETUP_BARS_SIZE_4_TB, // size (max): 4 TB - false -}; - -// mirrored range constants -const proc_setup_bars_bar_def mirrored_range_def = -{ - 0xFFFC0000FFFFFFFFULL, // base: RA 14:63 - PROC_SETUP_BARS_SIZE_2_GB, // size (min): 2 GB - PROC_SETUP_BARS_SIZE_2_TB, // size (max): 2 TB - false -}; - -// shared non-foreign BAR design (mirrored/non-mirrored regions) constants -const proc_setup_bars_bar_def common_nf_scope_bar_def = -{ - 0xFFFC0000FFFFFFFFULL, // base: RA 14:31 - PROC_SETUP_BARS_SIZE_4_GB, // size (min): 4 GB - PROC_SETUP_BARS_SIZE_64_TB, // size (min): 64 TB - true -}; - -const proc_setup_bars_bar_reg_def common_nf_scope_bar_reg_def = -{ - true, // base: bits 15:32 - PROC_SETUP_BARS_SHIFT_RIGHT, - 1, - 15, - 32, - true, // enable: bit 0 - 0, - true, // size: bits 1:14 - 1, - 14, - &proc_setup_bars_nf_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// shared foreign BAR design (near/far regions) constants -const fapi::AttributeId f_near_range_base_addr_attr = fapi::ATTR_PROC_FOREIGN_NEAR_BASE; -const fapi::AttributeId f_near_range_size_attr = fapi::ATTR_PROC_FOREIGN_NEAR_SIZE; - -const fapi::AttributeId f_far_range_base_addr_attr = fapi::ATTR_PROC_FOREIGN_FAR_BASE; -const fapi::AttributeId f_far_range_size_attr = fapi::ATTR_PROC_FOREIGN_FAR_SIZE; - -const proc_setup_bars_bar_def common_f_scope_bar_def = -{ - 0xFFFC000000FFFFFFULL, // base: RA 14:39 - PROC_SETUP_BARS_SIZE_16_MB, // size (min): 16 MB - PROC_SETUP_BARS_SIZE_8_TB, // size (min): 8 TB - true -}; - -const proc_setup_bars_bar_reg_def common_f_scope_bar_reg_def = -{ - true, // base: bits 20:45 - PROC_SETUP_BARS_SHIFT_RIGHT, - 6, - 20, - 45, - true, // enable: bit 0 - 0, - true, // size: bits 1:19 - 1, - 19, - &proc_setup_bars_f_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// PSI BAR constants -const fapi::AttributeId psi_bridge_bar_base_addr_attr = fapi::ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR; -const fapi::AttributeId psi_bridge_bar_en_attr = fapi::ATTR_PROC_PSI_BRIDGE_BAR_ENABLE; - -const proc_setup_bars_bar_def psi_bridge_bar_def = -{ - 0xFFFC0000000FFFFFULL, // base: RA 14:43 - PROC_SETUP_BARS_SIZE_1_MB, // size (min): 1 MB - PROC_SETUP_BARS_SIZE_1_MB, // size (max): 1 MB - true -}; - -const proc_setup_bars_bar_reg_def psi_bridge_bar_reg_def = -{ - true, // base: bits 14:43 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 43, - true, // enable: bit 63 - 63, - false, // size: implied - 0, - 0, - NULL, - 0x0ULL, - 0x0ULL -}; - -// FSP BAR constants -const fapi::AttributeId fsp_bar_base_addr_attr = fapi::ATTR_PROC_FSP_BAR_BASE_ADDR; -const fapi::AttributeId fsp_bar_en_attr = fapi::ATTR_PROC_FSP_BAR_ENABLE; -const fapi::AttributeId fsp_bar_size_attr = fapi::ATTR_PROC_FSP_BAR_SIZE; - -const proc_setup_bars_bar_def fsp_bar_def = -{ - 0xFFFC0000000FFFFFULL, // base: RA 14:43 - PROC_SETUP_BARS_SIZE_1_MB, // size (min): 1 MB - PROC_SETUP_BARS_SIZE_4_GB, // size (max): 4 GB - true -}; - -const proc_setup_bars_bar_reg_def fsp_bar_reg_def = -{ - true, // base: bits 14:43 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 43, - false, // enable: other reg - 0, - false, // size: other reg - 0, - 0, - NULL, - 0x0ULL, - 0x0ULL -}; - -const proc_setup_bars_bar_reg_def fsp_bar_mask_reg_def = -{ - false, // base: other reg - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 0, - 0, - false, // enable: other reg - 0, - true, // size: 32:43 - 32, - 43, - &proc_setup_bars_fsp_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -const proc_setup_bars_bar_reg_def fsp_bar_en_reg_def = -{ - false, // base: other reg - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 0, - 0, - true, // enable: bit 1 - 1, - false, // size: other reg - 0, - 0, - NULL, - 0x0ULL, - 0x0ULL -}; - -// FSP MMIO mask constants -const fapi::AttributeId fsp_mmio_mask_size_attr = fapi::ATTR_PROC_FSP_MMIO_MASK_SIZE; - -const proc_setup_bars_bar_def fsp_mmio_mask_def = -{ - 0xFFFFFFFFFFFFFFFFULL, // base: unused - PROC_SETUP_BARS_SIZE_256_MB, // size (min): 256 MB - PROC_SETUP_BARS_SIZE_4_GB, // size (max): 4 GB - true -}; - -const proc_setup_bars_bar_reg_def fsp_mmio_mask_reg_def = -{ - false, // base: unused - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 0, - 0, - false, // enable: unused - 0, - true, // size: bits 8:11 - 8, - 11, - &proc_setup_bars_fsp_mmio_mask_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// INTP BAR constants -const fapi::AttributeId intp_bar_base_addr_attr = fapi::ATTR_PROC_INTP_BAR_BASE_ADDR; -const fapi::AttributeId intp_bar_en_attr = fapi::ATTR_PROC_INTP_BAR_ENABLE; - -const proc_setup_bars_bar_def intp_bar_def = -{ - 0xFFFC0000000FFFFFULL, // base: RA 14:43 - PROC_SETUP_BARS_SIZE_1_MB, // size (min): 1 MB - PROC_SETUP_BARS_SIZE_1_MB, // size (max): 1 MB - true -}; - -const proc_setup_bars_bar_reg_def intp_bar_reg_def = -{ - true, // base: bits 0:29 - PROC_SETUP_BARS_SHIFT_LEFT, - 14, - 0, - 29, - true, // enable: bit 30 - 30, - false, // size: implied - 0, - 0, - NULL, - 0x0ULL, - 0x0ULL -}; - -// L3 BAR constants -const uint32_t L3_BAR12_BASE_ADDR_LEFT_SHIFT_AMOUNT = 14; -const uint32_t L3_BAR12_SIZE_END_BIT = 34; -const uint32_t L3_BAR2_ENABLE_BIT = 35; - -const uint32_t L3_BAR_GROUP_MASK_RA_DIFF_START_BIT = 18; -const uint32_t L3_BAR_GROUP_MASK_RA_DIFF_END_BIT = 31; - -const uint32_t L3_BAR_GROUP_MASK_NON_MIRROR_MASK_START_BIT = 3; -const uint32_t L3_BAR_GROUP_MASK_NON_MIRROR_MASK_END_BIT = 16; - -const uint32_t L3_BAR_GROUP_MASK_MIRROR_MASK_START_BIT = 20; -const uint32_t L3_BAR_GROUP_MASK_MIRROR_MASK_END_BIT = 33; -const uint32_t L3_BAR_GROUP_MASK_MIRROR_ENABLE_BIT = 34; - -// NX MMIO BAR constants -const fapi::AttributeId nx_mmio_bar_base_addr_attr = fapi::ATTR_PROC_NX_MMIO_BAR_BASE_ADDR; -const fapi::AttributeId nx_mmio_bar_en_attr = fapi::ATTR_PROC_NX_MMIO_BAR_ENABLE; -const fapi::AttributeId nx_mmio_bar_size_attr = fapi::ATTR_PROC_NX_MMIO_BAR_SIZE; - -const proc_setup_bars_bar_def nx_mmio_bar_def = -{ - 0xFFFC000000000FFFULL, // base: RA 14:51 - PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB - PROC_SETUP_BARS_SIZE_16_GB, // size (max): 16 GB - true -}; - -const proc_setup_bars_bar_reg_def nx_mmio_bar_reg_def = -{ - true, // base: bits 14:51 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 51, - true, // enable: bit 52 - 52, - true, // size: bits 53:55 - 53, - 55, - &proc_setup_bars_nx_mmio_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// AS MMIO BAR constants -const fapi::AttributeId as_mmio_bar_base_addr_attr = fapi::ATTR_PROC_AS_MMIO_BAR_BASE_ADDR; -const fapi::AttributeId as_mmio_bar_en_attr = fapi::ATTR_PROC_AS_MMIO_BAR_ENABLE; -const fapi::AttributeId as_mmio_bar_size_attr = fapi::ATTR_PROC_AS_MMIO_BAR_SIZE; - -const proc_setup_bars_bar_def as_mmio_bar_def = -{ - 0xFFFC000000000FFFULL, // base: RA 14:51 - PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB - PROC_SETUP_BARS_SIZE_16_GB, // size (max): 16 GB - true -}; - -const proc_setup_bars_bar_reg_def as_mmio_bar_reg_def = -{ - true, // base: bits 14:51 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 51, - true, // enable: bit 52 - 52, - true, // size: bits 53:55 - 53, - 55, - &proc_setup_bars_as_mmio_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// NPU BAR constants -const uint32_t PROC_SETUP_BARS_NPU_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] = -{ - NPU0_NODAL_BAR0_0x08013C04, - NPU1_NODAL_BAR0_0x08013C44, - NPU2_NODAL_BAR0_0x08013D04, - NPU3_NODAL_BAR0_0x08013D44 -}; - -const uint32_t PROC_SETUP_BARS_NPU_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] = -{ - NPU0_NODAL_BAR1_0x08013C05, - NPU1_NODAL_BAR1_0x08013C45, - NPU2_NODAL_BAR1_0x08013D05, - NPU3_NODAL_BAR1_0x08013D45 -}; - -const uint32_t PROC_SETUP_BARS_NPU_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] = -{ - NPU0_GROUP_BAR0_0x08013C06, - NPU1_GROUP_BAR0_0x08013C46, - NPU2_GROUP_BAR0_0x08013D06, - NPU3_GROUP_BAR0_0x08013D46 -}; - -const uint32_t PROC_SETUP_BARS_NPU_NODE_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] = -{ - NPU0_GROUP_BAR1_0x08013C07, - NPU1_GROUP_BAR1_0x08013C47, - NPU2_GROUP_BAR1_0x08013D07, - NPU3_GROUP_BAR1_0x08013D47 -}; - -// NPU MMIO BAR constants -const uint32_t PROC_SETUP_BARS_NPU_MMIO_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS][PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT] = -{ - { - NPU0_MMIO_BAR0_0x08013C02, - NPU0_MMIO_BAR1_0x08013C03 - }, - { - NPU1_MMIO_BAR0_0x08013C42, - NPU1_MMIO_BAR1_0x08013C43 - }, - { - NPU2_MMIO_BAR0_0x08013D02, - NPU2_MMIO_BAR1_0x08013D03 - }, - { - NPU3_MMIO_BAR0_0x08013D42, - NPU3_MMIO_BAR1_0x08013D43 - } -}; - -const fapi::AttributeId npu_mmio_bar_base_addr_attr = fapi::ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR; -const fapi::AttributeId npu_mmio_bar_en_attr = fapi::ATTR_PROC_NPU_MMIO_BAR_ENABLE; -const fapi::AttributeId npu_mmio_bar_size_attr = fapi::ATTR_PROC_NPU_MMIO_BAR_SIZE; - -const proc_setup_bars_bar_def npu_mmio_bar_def = -{ - 0xFFFC000000000FFFULL, // base: RA 14:51 - PROC_SETUP_BARS_SIZE_64_KB, // size (min): 64 KB - PROC_SETUP_BARS_SIZE_2_MB, // size (max): 2 MB - true -}; - -const proc_setup_bars_bar_reg_def npu_mmio_bar_reg_def = -{ - true, // base: bits 14:51 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 51, - true, // enable: bit 52 - 52, - true, // size: bits 53:55 - 53, - 55, - &proc_setup_bars_npu_mmio_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// HCA BAR and Range register constants -const proc_setup_bars_bar_reg_def hca_nm_bar_reg_def = -{ - true, // base: bits 14:31 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 31, - false, // enable: bit 63 (off for SW258328) - 63, - true, // size: bits 32:40 - 32, - 40, - &proc_setup_bars_hca_nm_bar_size::xlate_map, - 0x0ULL, - 0x0ULL -}; - -// HCA Mirror BAR and Range register constants -const proc_setup_bars_bar_reg_def hca_m_bar_reg_def = -{ - true, // base: bits 14:32 - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 14, - 32, - false, // enable: bit 63 (off for SW258328) - 63, - false, // size: other reg - 0, - 0, - NULL, - 0x0ULL, - 0x0ULL -}; - -// MCD Configuration Register constants -const proc_setup_bars_bar_reg_def mcd_nf_bar_reg_def = -{ - true, // base: bits 30:55 - PROC_SETUP_BARS_SHIFT_RIGHT, - 16, - 30, - 55, - true, // enable: bit 0 - 0, - true, // size: bits 9:29 - 9, - 29, - &proc_setup_bars_mcd_bar_size::xlate_map, - 0x4000000000000000ULL, // 1 config/group, system scope - 0x780000000000001CULL -}; - -const proc_setup_bars_bar_reg_def mcd_f0_bar_reg_def = -{ - true, // base: bits 30:55 - PROC_SETUP_BARS_SHIFT_RIGHT, - 16, - 30, - 55, - true, // enable: bit 0 - 0, - true, // size: bits 9:29 - 9, - 29, - &proc_setup_bars_mcd_bar_size::xlate_map, - 0x4000000000000010ULL, // 1 config/group, foreign scope, f0 link - 0x780000000000001CULL -}; - -const proc_setup_bars_bar_reg_def mcd_f1_bar_reg_def = -{ - true, // base: bits 30:55 - PROC_SETUP_BARS_SHIFT_RIGHT, - 16, - 30, - 55, - true, // enable: bit 0 - 0, - true, // size: bits 9:29 - 9, - 29, - &proc_setup_bars_mcd_bar_size::xlate_map, - 0x4000000000000014ULL, // 1 config/group, foreign scope, f1 link - 0x780000000000001CULL -}; - -// MCD FIR Register constants -const uint64_t MCD_FIR_MASK_RUNTIME_VAL = 0x2FC0000000000000ULL; - -// MCD Evn/Odd Recovery Control Register field/bit definitions -const uint8_t PROC_SETUP_BARS_NUM_MCD_CFG = 4; - -const uint64_t MCD_RECOVERY_ENABLE_BIT = 0; -const uint64_t MCD_RECOVERY_CFG_EN_BIT[PROC_SETUP_BARS_NUM_MCD_CFG] = {40,41,42,43}; - -// PCIe BAR constants -const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - PCIE0_NODAL_BAR0_0x02012010, - PCIE1_NODAL_BAR0_0x02012410, - PCIE2_NODAL_BAR0_0x02012810, - PCIE3_NODAL_BAR0_0x02012C10, -}; - -const uint32_t PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - PCIE0_NODAL_BAR1_0x02012011, - PCIE1_NODAL_BAR1_0x02012411, - PCIE2_NODAL_BAR1_0x02012811, - PCIE3_NODAL_BAR1_0x02012C11 -}; - -const uint32_t PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - PCIE0_GROUP_BAR0_0x02012012, - PCIE1_GROUP_BAR0_0x02012412, - PCIE2_GROUP_BAR0_0x02012812, - PCIE3_GROUP_BAR0_0x02012C12 -}; - -const uint32_t PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - PCIE0_GROUP_BAR1_0x02012013, - PCIE1_GROUP_BAR1_0x02012413, - PCIE2_GROUP_BAR1_0x02012813, - PCIE3_GROUP_BAR1_0x02012C13 -}; - -const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] = -{ - { - PCIE0_NEAR_BAR_F0_0x02012014, - PCIE0_NEAR_BAR_F1_0x02012016 - }, - { - PCIE1_NEAR_BAR_F0_0x02012414, - PCIE1_NEAR_BAR_F1_0x02012416 - }, - { - PCIE2_NEAR_BAR_F0_0x02012814, - PCIE2_NEAR_BAR_F1_0x02012816 - }, - { - PCIE3_NEAR_BAR_F0_0x02012C14, - PCIE3_NEAR_BAR_F1_0x02012C16 - } -}; - -const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] = -{ - { - PCIE0_FAR_BAR_F0_0x02012015, - PCIE0_FAR_BAR_F1_0x02012017 - }, - { - PCIE1_FAR_BAR_F0_0x02012415, - PCIE1_FAR_BAR_F1_0x02012417 - }, - { - PCIE2_FAR_BAR_F0_0x02012815, - PCIE2_FAR_BAR_F1_0x02012817 - }, - { - PCIE3_FAR_BAR_F0_0x02012C15, - PCIE3_FAR_BAR_F1_0x02012C17 - } -}; - -const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO = 2; -const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_PHB = 1; -const uint8_t PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE = 2; - -const uint8_t PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT] = -{ - true, // BAR 0 = MMIO (primary) - true, // BAR 1 = MMIO (backup/failover) - false, // BAR 2 = PHB -}; - -const fapi::AttributeId pcie_mmio_bar_base_addr_attr = fapi::ATTR_PROC_PCIE_BAR_BASE_ADDR; -const fapi::AttributeId pcie_mmio_bar_en_attr = fapi::ATTR_PROC_PCIE_BAR_ENABLE; -const fapi::AttributeId pcie_mmio_bar_size_attr = fapi::ATTR_PROC_PCIE_BAR_SIZE; - -const proc_setup_bars_bar_def pcie_mmio_bar_def = -{ - 0xFFFC00000000FFFFULL, // base: RA 14:47 - PROC_SETUP_BARS_SIZE_64_KB, // size (min): 64 KB - PROC_SETUP_BARS_SIZE_1_PB, // size (min): 1 PB - true -}; - -const proc_setup_bars_bar_reg_def pcie_mmio_bar_reg_def = -{ - true, // base: bits 0:33 - PROC_SETUP_BARS_SHIFT_LEFT, - 14, - 0, - 33, - false, // enable: other reg - 0, - false, // size: other reg - 0, - 0, - NULL, - 0x0ULL, - 0x0ULL -}; - -const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO] = -{ - { - PCIE0_IO_BAR0_0x02012040, - PCIE0_IO_BAR1_0x02012041 - }, - { - PCIE1_IO_BAR0_0x02012440, - PCIE1_IO_BAR1_0x02012441 - }, - { - PCIE2_IO_BAR0_0x02012840, - PCIE2_IO_BAR1_0x02012841 - }, - { - PCIE3_IO_BAR0_0x02012C40, - PCIE3_IO_BAR1_0x02012C41 - } -}; - -const proc_setup_bars_bar_reg_def pcie_mmio_bar_mask_reg_def = -{ - false, // base: other reg - PROC_SETUP_BARS_SHIFT_NONE, - 0, - 0, - 0, - false, // enable: other reg - 0, - true, // size: bits 0:33 - 0, - 33, - &proc_setup_bars_pcie_bar_size::xlate_map, - 0x0ULL, - 0x0ULL, -}; - -const uint32_t PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO] = -{ - { - PCIE0_IO_MASK0_0x02012043, - PCIE0_IO_MASK1_0x02012044 - }, - { - PCIE1_IO_MASK0_0x02012443, - PCIE1_IO_MASK1_0x02012444 - }, - { - PCIE2_IO_MASK0_0x02012843, - PCIE2_IO_MASK1_0x02012844 - }, - { - PCIE3_IO_MASK0_0x02012C43, - PCIE3_IO_MASK1_0x02012C44 - } -}; - -const proc_setup_bars_bar_def pcie_phb_bar_def = -{ - 0xFFFC000000000FFFULL, // base: RA 14:51 - PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB - PROC_SETUP_BARS_SIZE_4_KB, // size (min): 4 KB - true -}; - -const proc_setup_bars_bar_reg_def pcie_phb_bar_reg_def = -{ - true, // base: bits 0:37 - PROC_SETUP_BARS_SHIFT_LEFT, - 14, - 0, - 37, - false, // enable: other reg - 0, - false, // size: implied - 0, - 33, - NULL, - 0x0ULL, - 0x0ULL -}; - -const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE] = -{ - { - PCIE0_IO_BAR2_0x02012042, - PCIE0_ASB_BAR_0x0901200B - }, - { - PCIE1_IO_BAR2_0x02012442, - PCIE1_ASB_BAR_0x0901240B - }, - { - PCIE2_IO_BAR2_0x02012842, - PCIE2_ASB_BAR_0x0901280B - }, - { - PCIE3_IO_BAR2_0x02012C42, - PCIE3_ASB_BAR_0x09012C0B - } -}; - -const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_BIT[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - 0x0, - 0x1, - 0x2 -}; - -const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - PCIE0_IO_BAR_EN_0x02012045, - PCIE1_IO_BAR_EN_0x02012445, - PCIE2_IO_BAR_EN_0x02012845, - PCIE3_IO_BAR_EN_0x02012C45 -}; - -// ETU Reset register field/bit definitions -const uint32_t PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS] = -{ - PCIE0_ETU_RESET_0x0901200A, - PCIE1_ETU_RESET_0x0901240A, - PCIE2_ETU_RESET_0x0901280A, - PCIE3_ETU_RESET_0x09012C0A -}; - - -#endif // _PROC_SETUP_BARS_DEFS_H_ diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C b/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C deleted file mode 100755 index 4f6f18953..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C +++ /dev/null @@ -1,261 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_throttle_sync.C,v 1.6 2013/12/19 22:22:03 bellows Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_throttle_sync.C,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! Licensed material - Program property of IBM -// *! Refer to copyright instructions form no. G120-2083 -// *! Created on Tue Nov 12 2013 at 13:42:15 -//------------------------------------------------------------------------------ -// *! TITLE : proc_throttle_sync -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Bellows Mark D.Email: bellows@us.ibm.com -// *! BACKUP NAME : Email: ______@us.ibm.com - -// *! ADDITIONAL COMMENTS : -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.6 | bellows |19-DEC-13| Fixed the minor (not functional) setting of rc_ecmd = for next set of data buffer commands -// 1.5 | bellows |13-DEC-13| One missed firmware review comment -// 1.4 | bellows |13-DEC-13| Firmware review updates -// 1.3 | bellows |06-DEC-13| Handle the MCS functional but no centaur case -// 1.2 | bellows |25-NOV-13| Functional Debug Performed -// 1.1 | bellows |12-NOV-13| Created. -#include <fapi.H> -#include <proc_throttle_sync.H> -#include <p8_scom_addresses.H> - -extern "C" { - - using namespace fapi; - - const uint32_t MAX_SYNC_RETRIES = 1000; -// run on one processor - ReturnCode proc_throttle_sync(fapi::Target & i_target_proc) { - - ReturnCode rc; - ecmdDataBufferBase mask_buffer_64(64); - ecmdDataBufferBase data_buffer_64(64); - uint8_t l_attr_cen_ec_throttle_sync_possible; - uint32_t rc_ecmd; - uint8_t l_proc_attached_centaurs=0; - uint8_t l_summary_sync_possible=true; - uint32_t i=0; - std::vector<fapi::Target> l_target_attached_mcs; - fapi::Target cen_target; - - do { - // determine how far into the IPL we have gone - rc = fapiGetChildChiplets( i_target_proc, TARGET_TYPE_MCS_CHIPLET, l_target_attached_mcs ); - if (rc) - { - FAPI_ERR("Failed to find attached mcs\n"); - break; - } - -// find the one mcs -// also form the centaur vector - uint8_t theonemcs=0xff; // index into the MCS vector for the one MCS - uint8_t l_functional; - uint8_t unit_num[8]; - uint8_t pos_attr_data; - - for(i=0; i<8; i++) unit_num[i]=0xff; - for(i=0; i < l_target_attached_mcs.size(); i++) { - FAPI_INF("working on mcs %s\n", l_target_attached_mcs[i].toEcmdString()); - - rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_target_attached_mcs[i], pos_attr_data); - if(rc) { - FAPI_ERR("ERROR: Unable to get ATTR_CHIP_UNIT_POS\n"); - break; - } - - - rc = fapiGetOtherSideOfMemChannel( l_target_attached_mcs[i], cen_target ); - if (rc) - { - FAPI_INF("--> this mcs does not have an attached centaur!\n"); - rc=fapi::FAPI_RC_SUCCESS; - } - else { - unit_num[pos_attr_data] = i; // save in index back into the uint_num array - - cen_target.setType(TARGET_TYPE_MEMBUF_CHIP); - - // find out if this centaur can do a sync. They should all be the same. Give up if any aren't - // capable - rc = FAPI_ATTR_GET(ATTR_CEN_EC_THROTTLE_SYNC_POSSIBLE, &cen_target, l_attr_cen_ec_throttle_sync_possible); - if(rc) break; - - if( ! l_attr_cen_ec_throttle_sync_possible) { // one or more are not DD2 - FAPI_INF("--> the attached centaur is not capable of this type of sync\n"); - l_summary_sync_possible=false; - } - - // all functional centaurs form a vector to do a sync on - rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &cen_target, l_functional); - if(rc) { - FAPI_ERR("Could not get ATTR_FUNCTIONAL"); - break; - } - if(l_functional) { - l_proc_attached_centaurs |= ( 0x80 >> pos_attr_data ); - } - } - - } - - - - if(l_summary_sync_possible) { - FAPI_INF("--> Because sync possible, running procedure\n"); - -// SYNC PROCEDURE: -// 1.) Determined the MCS to be the master -// Choose MC2.MCS0, since its on both Murano and Venice. -// However, if its deconfigured then the code will have to determine the next master per processor chip. -// [ This is determined by the platform. The suggestion is to use MC2.MCS0, but if that is not available, pick a different one ] - // select the one - if(unit_num[4] != 0xFF) theonemcs=unit_num[4]; - else if(unit_num[5] != 0xFF) theonemcs=unit_num[5]; - else if(unit_num[6] != 0xFF) theonemcs=unit_num[6]; - else if(unit_num[7] != 0xFF) theonemcs=unit_num[7]; - else if(unit_num[0] != 0xFF) theonemcs=unit_num[0]; - else if(unit_num[1] != 0xFF) theonemcs=unit_num[1]; - else if(unit_num[2] != 0xFF) theonemcs=unit_num[2]; - else if(unit_num[3] != 0xFF) theonemcs=unit_num[3]; - else { - FAPI_IMP("Did not find a valid MCS on this processor %s\n", i_target_proc.toEcmdString()); - break; - } - - FAPI_INF("--> the one mcs is %s\n", l_target_attached_mcs[theonemcs].toEcmdString() ); -// 2.) Select which MCS to be the targets per processor. You'll want to select the configured MCS's with Centaur attached, but it might still work if you select all of them. -// Bits 0:7 of MCSYNC Register (Scom addr 201180B) are the select bits. These bits should be set on the master only. They tell the master, which targets to send the sync commands. -// -// Here's the mapping, if you wish to select the configured MCS's only. The red MCS's below are only on Venice chips. -// Bit 0: MC0.MCS0 -// Bit 1: MC0.MCS1 -// Bit 2: MC1.MCS0 -// Bit 3: MC1.MCS1 -// Bit 4: MC2.MCS0 -// Bit 5: MC2.MCS1 -// Bit 6: MC3.MCS0 -// Bit 7: MC3.MCS1 - bool l_sync_complete=false; - uint32_t l_tries=0; - while ( l_sync_complete == false && l_tries < 1000 ) { - rc_ecmd = ECMD_DBUF_SUCCESS; - FAPI_INF("--> Doing the sync sequence try is %d\n", l_tries ); - rc_ecmd |= data_buffer_64.clearBit(0,64); - rc_ecmd |= mask_buffer_64.clearBit(0,64); - - FAPI_INF("--> the vector of attached centaurs is %02x\n", l_proc_attached_centaurs ); - for(i=0; i<8; i++) { - if((l_proc_attached_centaurs>>(7-i)) & 0x1) { - rc_ecmd |= data_buffer_64.setBit(i); - } - rc_ecmd |= mask_buffer_64.setBit(i); - } - -// 3.) Setup the sync commands to issue to centaur on the master MCS -// Bit 12 of MCSYNC Register is N/M Sync (Scom addr 201180B) -// Bit 15 of MCSYNC Register is PC Sync (Scom addr 201180B) - - rc_ecmd |= data_buffer_64.setBit(12); - rc_ecmd |= mask_buffer_64.setBit(12); - rc_ecmd |= data_buffer_64.setBit(15); - rc_ecmd |= mask_buffer_64.setBit(15); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScomUnderMask(l_target_attached_mcs[theonemcs], MCS_MCSYNC_0x0201180B, data_buffer_64, mask_buffer_64); - if(rc) break; - -// 4.) Generate the Sync Command to Centaur from the master MCS -// Bit 0 of MCS Mode3 Register (Scom addr 201180A) -// (This bit needs a reset before another set, it does not reset automatically) - rc_ecmd = data_buffer_64.clearBit(0,64); - rc_ecmd |= data_buffer_64.setBit(0); - rc_ecmd |= mask_buffer_64.clearBit(0,64); - rc_ecmd |= mask_buffer_64.setBit(0); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - break; - } - - rc = fapiPutScomUnderMask(l_target_attached_mcs[theonemcs], MCS_MODE3_REGISTER_0x0201180A, data_buffer_64, mask_buffer_64); - if(rc) break; - - // this resets the before mentioned bit - rc_ecmd = data_buffer_64.clearBit(0); - if(rc_ecmd) { - rc.setEcmdError(rc_ecmd); - break; - } - rc = fapiPutScomUnderMask(l_target_attached_mcs[theonemcs], MCS_MODE3_REGISTER_0x0201180A, data_buffer_64, mask_buffer_64); - if(rc) break; - -// 5.) Read the SYNC status register on the master MCS -// Bits 1:7 of MCS Mode3 Register (Scom addr 201180A) -// If any status bit is set, this indicates that a replay has occurred on the DMI channel, repeat steps 3 and 4 above. -// (actually to build the register back up, we go to step 2 to pick up the centaurs again) - rc = fapiGetScom(l_target_attached_mcs[theonemcs], MCS_MODE3_REGISTER_0x0201180A, data_buffer_64); - if(rc) break; - - if(data_buffer_64.isBitClear(1,7) == true) { - l_sync_complete=true; - } - else { - l_tries++; - FAPI_INF("--> Not all ready, reissue the sync, tries are %d\n", l_tries ); - l_sync_complete=false; - } - } - if(rc) break; - if (l_tries == MAX_SYNC_RETRIES) { - FAPI_ERR("This processor did not see a successful MCSYNC\n"); - FAPI_SET_HWP_ERROR(rc, RC_PROC_MCSYNC_THERMAL_RETRY_EXCEEDED); - break; - } - FAPI_INF("--> Success in running the sync sequence tries were %d\n", l_tries ); - - } - } while(0); - - return rc; - } - -} // extern "C" diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H b/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H deleted file mode 100755 index 825758003..000000000 --- a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H +++ /dev/null @@ -1,74 +0,0 @@ -/* IBM_PROLOG_BEGIN_TAG */ -/* This is an automatically generated prolog. */ -/* */ -/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H $ */ -/* */ -/* OpenPOWER HostBoot Project */ -/* */ -/* Contributors Listed Below - COPYRIGHT 2013,2014 */ -/* [+] International Business Machines Corp. */ -/* */ -/* */ -/* Licensed under the Apache License, Version 2.0 (the "License"); */ -/* you may not use this file except in compliance with the License. */ -/* You may obtain a copy of the License at */ -/* */ -/* http://www.apache.org/licenses/LICENSE-2.0 */ -/* */ -/* Unless required by applicable law or agreed to in writing, software */ -/* distributed under the License is distributed on an "AS IS" BASIS, */ -/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ -/* implied. See the License for the specific language governing */ -/* permissions and limitations under the License. */ -/* */ -/* IBM_PROLOG_END_TAG */ -// $Id: proc_throttle_sync.H,v 1.2 2013/11/25 21:13:13 bellows Exp $ -// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_throttle_sync.H,v $ -//------------------------------------------------------------------------------ -// *! (C) Copyright International Business Machines Corp. 2013 -// *! All Rights Reserved -- Property of IBM -// *! *** *** -// *! Licensed material - Program property of IBM -// *! Refer to copyright instructions form no. G120-2083 -// *! Created on Tue Nov 12 2013 at 13:42:15 -//------------------------------------------------------------------------------ -// *! TITLE : proc_throttle_sync -// *! DESCRIPTION : see additional comments below -// *! OWNER NAME : Bellows Mark D.Email: bellows@us.ibm.com -// *! BACKUP NAME : Email: ______@us.ibm.com - -// *! ADDITIONAL COMMENTS : -// -//------------------------------------------------------------------------------ -// Don't forget to create CVS comments when you check in your changes! -//------------------------------------------------------------------------------ -// CHANGE HISTORY: -//------------------------------------------------------------------------------ -// Version:| Author: | Date: | Comment: -//---------|----------|---------|----------------------------------------------- -// 1.2 | bellows |25-NOV-13| Updated call to procedure -// 1.1 | bellows |12-NOV-13| Created. -#ifndef __PROC_THROTTLE_SYNC_H -#define __PROC_THROTTLE_SYNC_H - -#include <fapi.H> -#include <p8_scom_addresses.H> - -typedef fapi::ReturnCode (*proc_throttle_sync_FP_t)(fapi::Target & i_target_proc ); - -extern "C" -{ - using namespace fapi; - -/** - * @brief proc_throttle_sync procedure. Sync all MBA below this processor when changing thermal parameters - * - * @param[in] fapi::Target i_target_proc, // Platform runs this on each processor * - * @return ReturnCode - */ - - ReturnCode proc_throttle_sync(fapi::Target & i_target_proc ); - -} // extern "C" - -#endif |
