Remove last of old hwpf directory

Remove all of the old fapi1 HWPs from P8
Update makefiles/code to not include old hwpf headers

Change-Id: Idc840554721f68b0af3b6ee6c7ad84f5df258e60
RTC: 146345
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28844
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>

371 files changed, 35 insertions, 163853 deletions

diff --git a/src/usr/devtree/makefile b/src/usr/devtree/makefile
index 48468421e..9532e1ae8 100644
--- a/src/usr/devtree/makefile
+++ b/src/usr/devtree/makefile
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2013,2015
+# Contributors Listed Below - COPYRIGHT 2013,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -34,9 +34,6 @@ MODULE = devtree
 
 ##      support for fapi
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 
 
 OBJS += devtree.o
diff --git a/src/usr/diag/mdia/makefile b/src/usr/diag/mdia/makefile
index b06304ff4..1afb6ea15 100644
--- a/src/usr/diag/mdia/makefile
+++ b/src/usr/diag/mdia/makefile
@@ -30,8 +30,6 @@ EXTRAINCDIR += ${ROOTPATH}/src/include/usr/diag
 ##########################################################
 EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils
 ##########################################################
 # Following is needed to include memdiags.H
diff --git a/src/usr/diag/mdia/test/makefile b/src/usr/diag/mdia/test/makefile
index c439400d5..63dc21d67 100644
--- a/src/usr/diag/mdia/test/makefile
+++ b/src/usr/diag/mdia/test/makefile
@@ -26,17 +26,12 @@ ROOTPATH = ../../../../..
 
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/diag
 
-##########################################################
-# Following are needed to include hwpf/hwp/fapi.H
-##########################################################
-EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/utils
 ##########################################################
 # Following is needed to include memdiags.H
 ##########################################################
+EXTRAINCDIR += ${ROOTPATH}/src/import/hwpf/fapi2/include
 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/common/include
 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/memory
 EXTRAINCDIR += ${ROOTPATH}/src/import/chips/p9/procedures/hwp/memory/lib/mcbist
diff --git a/src/usr/ecmddatabuffer/makefile b/src/usr/ecmddatabuffer/makefile
index 00c91a30f..eb414da97 100644
--- a/src/usr/ecmddatabuffer/makefile
+++ b/src/usr/ecmddatabuffer/makefile
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2011,2014
+# Contributors Listed Below - COPYRIGHT 2011,2016
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -23,8 +25,6 @@
 ROOTPATH = ../../..
 MODULE = ecmddatabuffer
 
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
 
 CFLAGS += -DPRDF_COMPRESSBUFFER_COMPRESS_FUNCTIONS=1
diff --git a/src/usr/htmgt/htmgt.C b/src/usr/htmgt/htmgt.C
index fb23ee008..a7895ee65 100644
--- a/src/usr/htmgt/htmgt.C
+++ b/src/usr/htmgt/htmgt.C
@@ -42,7 +42,7 @@
 #include <targeting/common/targetservice.H>
 
 // HBOCC support
-#include <hwpf/hwp/occ/occ_common.H>
+#include <occ/occ_common.H>
 
 #include <sys/time.h>
 #include <targeting/common/attributeTank.H>
diff --git a/src/usr/htmgt/htmgt_common.mk b/src/usr/htmgt/htmgt_common.mk
index 1be6ad42e..043af9334 100644
--- a/src/usr/htmgt/htmgt_common.mk
+++ b/src/usr/htmgt/htmgt_common.mk
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2014,2015
+# Contributors Listed Below - COPYRIGHT 2014,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -24,12 +24,6 @@
 # IBM_PROLOG_END_TAG
 
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/pstates/pstates
 
 # common objects between hostboot and hbrt
 OBJS += htmgt.o
diff --git a/src/usr/htmgt/htmgt_occ.C b/src/usr/htmgt/htmgt_occ.C
index ee9639dfe..7fd212ac3 100644
--- a/src/usr/htmgt/htmgt_occ.C
+++ b/src/usr/htmgt/htmgt_occ.C
@@ -38,9 +38,9 @@
 #include <console/consoleif.H>
 #include <sys/time.h>
 #include <ecmdDataBufferBase.H>
-#include <hwpf/hwp/occ/occAccess.H>
-#include <hwpf/hwp/occ/occ.H>
-#include <hwpf/hwp/occ/occ_common.H>
+#include <occ/occAccess.H>
+#include <occ/occ.H>
+#include <occ/occ_common.H>
 #include <errl/errludlogregister.H>
 
 namespace HTMGT
diff --git a/src/usr/htmgt/htmgt_occcmd.C b/src/usr/htmgt/htmgt_occcmd.C
index 934cf0ec1..83e950bdc 100644
--- a/src/usr/htmgt/htmgt_occcmd.C
+++ b/src/usr/htmgt/htmgt_occcmd.C
@@ -36,7 +36,7 @@
 #include <targeting/common/targetservice.H>
 
 #include <ecmdDataBufferBase.H>
-#include <hwpf/hwp/occ/occAccess.H>
+#include <occ/occAccess.H>
 
 #include <sys/time.h>
 #include <trace/interface.H>
diff --git a/src/usr/htmgt/makefile b/src/usr/htmgt/makefile
index 81f6b1196..e73d02705 100644
--- a/src/usr/htmgt/makefile
+++ b/src/usr/htmgt/makefile
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2014,2015
+# Contributors Listed Below - COPYRIGHT 2014,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -25,8 +25,6 @@
 ROOTPATH = ../../..
 MODULE = htmgt
 
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ
-
 # objects common to hostboot and hbrt
 include htmgt_common.mk
 
diff --git a/src/usr/htmgt/occError.C b/src/usr/htmgt/occError.C
index 9af585c17..c07dd0be6 100644
--- a/src/usr/htmgt/occError.C
+++ b/src/usr/htmgt/occError.C
@@ -30,7 +30,7 @@
 #include "htmgt_occcmd.H"
 
 #include <ecmdDataBufferBase.H>
-#include <hwpf/hwp/occ/occAccess.H>
+#include <occ/occAccess.H>
 #include <console/consoleif.H>
 #include <targeting/targplatutil.H>
 
diff --git a/src/usr/htmgt/test/makefile b/src/usr/htmgt/test/makefile
index cd03f5636..251c0fe41 100644
--- a/src/usr/htmgt/test/makefile
+++ b/src/usr/htmgt/test/makefile
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2014
+# Contributors Listed Below - COPYRIGHT 2014,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -24,13 +24,7 @@
 # IBM_PROLOG_END_TAG
 ROOTPATH = ../../../..
 
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/pstates/pstates
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config
 EXTRAINCDIR += ${ROOTPATH}/src/usr/htmgt
 
 MODULE = testhtmgt
diff --git a/src/usr/hwas/makefile b/src/usr/hwas/makefile
index 1617df6e8..ed768478d 100644
--- a/src/usr/hwas/makefile
+++ b/src/usr/hwas/makefile
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2015
+# Contributors Listed Below - COPYRIGHT 2011,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -26,19 +26,11 @@ ROOTPATH = ../../..
 
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwas
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwas/common
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
 
 ##      support for Targeting and fapi
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 EXTRAINCDIR += ${ROOTPATH}/src/usr/sbe
 
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
 VPATH += ${ROOTPATH}/src/usr/hwas/plat
 VPATH += ${ROOTPATH}/src/usr/hwas/common
 
diff --git a/src/usr/hwas/test/makefile b/src/usr/hwas/test/makefile
index 84d9bd9a1..be5bcb9bb 100644
--- a/src/usr/hwas/test/makefile
+++ b/src/usr/hwas/test/makefile
@@ -5,7 +5,9 @@
 #
 # OpenPOWER HostBoot Project
 #
-# COPYRIGHT International Business Machines Corp. 2011,2014
+# Contributors Listed Below - COPYRIGHT 2011,2016
+# [+] International Business Machines Corp.
+#
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
 # you may not use this file except in compliance with the License.
@@ -22,9 +24,6 @@
 # IBM_PROLOG_END_TAG
 ROOTPATH = ../../../..
 
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
 
 MODULE = testhwas
diff --git a/src/usr/hwpf/hwp/HBconfig b/src/usr/hwpf/hwp/HBconfig
deleted file mode 100644
index 217706e59..000000000
--- a/src/usr/hwpf/hwp/HBconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-config PCIE_HOTPLUG_CONTROLLER
-    default y
-    help
-        Turn PCIe Hot Plug Controller on and off during IPL
diff --git a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.H b/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.H
deleted file mode 100644
index 512194975..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.H
+++ /dev/null
@@ -1,102 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/activate_powerbus.H $      */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-#ifndef  __ACTIVATE_POWERBUS_ACTIVATE_POWERBUS_H
-#define  __ACTIVATE_POWERBUS_ACTIVATE_POWERBUS_H
-
-/**
- *  @file activate_powerbus.H
- *
- *  Activate PowerBus
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  *****************************************************************
- *  THIS FILE WAS GENERATED ON 2012-04-11:1607
- *  *****************************************************************
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
- /*  @tag isteplist
- *  @docversion     v1.28 (12/03/12)
- *  @istepname      activate_powerbus
- *  @istepnum       09
- *  @istepdesc      Activate PowerBus
- *
- *  @{
- *      @substepnum     1
- *      @substepname    proc_build_smp
- *      @substepdesc    : Integrate PgP Islands into SMP
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    host_slave_sbe_update
- *      @substepdesc    : execute p8_customize_image
- *          @target_sched   serial
- *  @}
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-namespace   ACTIVATE_POWERBUS
-{
-
-
-
-/**
- *  @brief   proc_build_smp
- *
- *           Integrate PgP Islands into SMP
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*   call_proc_build_smp( void    *io_pArgs );
-
-/**
- *  @brief  host_slave_sbe_update 
- *
- *          Placeholder for secureboot where Hostboot must update
- *          SEEPROM because FSP cannot.
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*   call_host_slave_sbe_update( void * io_pArgs );
-
-};   // end namespace
-
-#endif
-
diff --git a/src/usr/hwpf/hwp/activate_powerbus/makefile b/src/usr/hwpf/hwp/activate_powerbus/makefile
deleted file mode 100644
index 6e7bce2ad..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/makefile
+++ /dev/null
@@ -1,67 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/activate_powerbus/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = activate_powerbus
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars
-
-##  NOTE: add the base istep dir here.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += proc_build_smp.o
-OBJS += proc_build_smp_adu.o
-OBJS += proc_build_smp_epsilon.o
-OBJS += proc_build_smp_fbc_ab.o
-OBJS += proc_build_smp_fbc_cd.o
-OBJS += proc_build_smp_fbc_nohp.o
-OBJS += proc_adu_utils.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/<HWP_dir>
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C
deleted file mode 100644
index c2c40db64..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C
+++ /dev/null
@@ -1,710 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_adu_utils.C,v 1.9 2014/02/12 05:13:49 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_adu_utils.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_adu_utils.C
-// *! DESCRIPTION : ADU library functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Kevin Reick   Email: reick@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_adu_utils.H>
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-fapi::ReturnCode proc_adu_utils_get_adu_lock_id(
-    const fapi::Target& i_target,
-    uint8_t& o_lock_id)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data(64);
-    uint8_t lock_id;
-
-    FAPI_DBG("proc_adu_utils_get_adu_lock_id: Start");
-
-    do
-    {
-        // read ADU Command register
-        FAPI_DBG("proc_adu_utils_get_adu_lock_id: Reading ADU Command register to retreive lock ID");
-        rc = fapiGetScom(i_target, ADU_COMMAND_0x02020001, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_get_adu_lock_id: fapiGetScom error (ADU_COMMAND_0x02020001)");
-            break;
-        }
-
-        // extract lock ID field
-        rc_ecmd |= data.extractToRight(&lock_id,
-                                       ADU_COMMAND_LOCK_ID_START_BIT,
-                                       (ADU_COMMAND_LOCK_ID_END_BIT-
-                                        ADU_COMMAND_LOCK_ID_START_BIT)+1);
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_get_adu_lock_id: Error 0x%x extracting lock id from data buffer",
-                     rc_ecmd);
-            break;
-        }
-        o_lock_id = lock_id & ADU_COMMAND_LOCK_ID_MAX_VALUE;
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_get_adu_lock_id: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_clear_adu_auto_inc(
-    const fapi::Target& i_target)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data(64);
-
-    FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: Start");
-
-    do
-    {
-        // retreive ADU Command register
-        FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: Reading ADU Command register");
-        rc = fapiGetScom(i_target, ADU_COMMAND_0x02020001, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_clear_adu_auto_inc: fapiGetScom error (ADU_COMMAND_0x02020001)");
-            break;
-        }
-
-        // clear auto-increment bit
-        rc_ecmd |= data.clearBit(ADU_COMMAND_AUTO_INC_BIT);
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_clear_adu_auto_inc: Error 0x%x forming auto-increment clear data buffer",
-                     rc_ecmd);
-            break;
-        }
-
-        // write ADU Command register
-        FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: Writing ADU Command register");
-        rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_clear_adu_auto_inc: fapiPutScom error (ADU_COMMAND_0x02020001)");
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_clear_adu_auto_inc: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_manage_adu_lock(
-    const fapi::Target& i_target,
-    const proc_adu_utils_adu_lock_operation i_lock_operation,
-    const uint32_t i_num_attempts)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase lock_control(64);
-    uint32_t attempt_count = 1;
-
-    FAPI_DBG("proc_adu_utils_manage_adu_lock: Start");
-
-    do
-    {
-        // validate input parameters
-        if (i_num_attempts == 0)
-        {
-            FAPI_ERR("proc_adu_utils_manage_adu_lock: Invalid value %d for number of lock manipulation attempts",
-                     i_num_attempts);
-            const fapi::Target & TARGET = i_target;
-            const uint32_t & ATTEMPTS = i_num_attempts;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS);
-            break;
-        }
-
-        // set up data buffer to perform desired lock manipulation operation
-        if (i_lock_operation == ADU_LOCK_ACQUIRE)
-        {
-            FAPI_DBG("proc_adu_utils_manage_adu_lock: Configuring lock manipulation control data buffer to perform lock acquisition");
-            rc_ecmd |= lock_control.setBit(ADU_COMMAND_LOCKED_BIT);
-        }
-        else if (i_lock_operation == ADU_LOCK_FORCE_ACQUIRE)
-        {
-            FAPI_DBG("proc_adu_utils_manage_adu_lock: Configuring lock manipulation control data buffer to perform lock acquisition/pick");
-            rc_ecmd |= lock_control.setBit(ADU_COMMAND_LOCKED_BIT);
-            rc_ecmd |= lock_control.setBit(ADU_COMMAND_LOCK_PICK_BIT);
-        }
-        else if (i_lock_operation == ADU_LOCK_RELEASE)
-        {
-            FAPI_DBG("proc_adu_utils_manage_adu_lock: Configuring lock manipulation control data buffer to perform lock release");
-        }
-        else
-        {
-            FAPI_ERR("proc_adu_utils_manage_adu_lock: Internal error (unsupported lock operation enum value %d)",
-                     i_lock_operation);
-            const fapi::Target & TARGET = i_target;
-            const uint32_t & OPERATION = i_lock_operation;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION);
-            break;
-        }
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_manage_adu_lock: Error 0x%x setting up lock manipulation control data buffer",
-                     rc_ecmd);
-            break;
-        }
-
-        // perform lock management operation
-        while (1)
-        {
-            // write ADU command register to attempt lock manipulation
-            FAPI_DBG("proc_adu_utils_manage_adu_lock: Writing ADU Command register to attempt lock manipulation");
-            rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, lock_control);
-            // pass back return code to caller unless it specifically indicates
-            // that the ADU lock manipulation was unsuccessful and we're going
-            // to try again
-            if ((rc != fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED) ||
-                (attempt_count == i_num_attempts))
-            {
-                // rc does not indicate success
-                if (!rc.ok())
-                {
-                    // rc does not indicate lock held, exit
-                    if (rc != fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED)
-                    {
-                        FAPI_ERR("proc_adu_utils_manage_adu_lock: fapiPutScom error (ADU_COMMAND_0x02020001)");
-                        break;
-                    }
-                    // rc indicates lock held, out of attempts
-                    if (attempt_count == i_num_attempts)
-                    {
-                        FAPI_ERR("proc_adu_utils_manage_adu_lock: Desired ADU lock manipulation was not successful after %d attempts",
-                                 i_num_attempts);
-                        break;
-                    }
-                }
-                // rc clean, lock management operation successful
-                FAPI_DBG("proc_adu_utils_manage_adu_lock: Lock manipulation successful");
-                break;
-            }
-
-            // delay to provide time for ADU lock to be released
-            rc = fapiDelay(PROC_ADU_UTILS_ADU_HW_NS_DELAY,
-                           PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_adu_utils_manage_adu_lock: fapiDelay error");
-                break;
-            }
-
-            // increment attempt count, loop again
-            attempt_count++;
-            FAPI_DBG("proc_adu_utils_manage_adu_lock: Attempt %d of %d",
-                     attempt_count, i_num_attempts);
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_manage_adu_lock: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_reset_adu(
-    const fapi::Target& i_target)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data(64);
-
-    FAPI_DBG("proc_adu_utils_reset_adu: Start");
-
-    do
-    {
-        // assert status clear & state machine bits
-        // leave lock bit asserted
-        FAPI_DBG("proc_adu_utils_reset_adu: Writing ADU Command register to reset ADU");
-        rc_ecmd |= data.setBit(ADU_COMMAND_CLEAR_STATUS_BIT);
-        rc_ecmd |= data.setBit(ADU_COMMAND_RESET_BIT);
-        rc_ecmd |= data.setBit(ADU_COMMAND_LOCKED_BIT);
-        if (rc_ecmd)
-        {
-   	    rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_reset_adu: Error 0x%x setting up reset control data buffer",
-                     rc_ecmd);
-            break;
-        }
-
-        // write ADU Command register
-        rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_reset_adu: fapiPutScom error (ADU_COMMAND_0x02020001)");
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_reset_adu: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_send_fbc_op(
-    const fapi::Target& i_target,
-    const proc_adu_utils_fbc_op i_adu_ctl,
-    const bool i_use_hp,
-    const proc_adu_utils_fbc_op_hp_ctl i_adu_hp_ctl)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase ctl_data(64);
-    ecmdDataBufferBase cmd_data(64);
-    uint8_t struct_data_to_insert;
-
-    FAPI_DBG("proc_adu_utils_send_fbc_op: Start");
-
-    do
-    {
-        // validate input parameters
-        if (i_adu_ctl.address > PROC_FBC_UTILS_FBC_MAX_ADDRESS)
-        {
-            FAPI_ERR("proc_adu_utils_send_fbc_op: Out-of-range value %016llX specified for fabric address argument",
-                     i_adu_ctl.address);
-            const fapi::Target & TARGET = i_target;
-            const uint64_t & ADDRESS = i_adu_ctl.address;
-            const proc_adu_utils_fbc_op & FBC_OP = i_adu_ctl;
-            const proc_adu_utils_fbc_op_hp_ctl & FBC_OP_HP_CTL = i_adu_hp_ctl;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_FBC_OP);
-            break;
-        }
-        if (i_use_hp &&
-            (i_adu_hp_ctl.post_quiesce_delay >
-             PROC_ADU_UTILS_ADU_MAX_POST_QUIESCE_DELAY))
-        {
-            FAPI_ERR("proc_adu_utils_send_fbc_op: Out-of-range value %d specified for hotplug post-quiesce delay argument",
-                     i_adu_hp_ctl.post_quiesce_delay);
-            const fapi::Target & TARGET = i_target;
-            const uint64_t & ADDRESS = i_adu_ctl.address;
-            const proc_adu_utils_fbc_op & FBC_OP = i_adu_ctl;
-            const proc_adu_utils_fbc_op_hp_ctl & FBC_OP_HP_CTL = i_adu_hp_ctl;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_FBC_OP);
-            break;
-        }
-        if (i_use_hp &&
-            (i_adu_hp_ctl.pre_init_delay >
-             PROC_ADU_UTILS_ADU_MAX_PRE_INIT_DELAY))
-        {
-            FAPI_ERR("proc_adu_utils_send_fbc_op: Out-of-range value %d specified for hotplug pre-init delay argument",
-                     i_adu_hp_ctl.pre_init_delay);
-	        const fapi::Target & TARGET = i_target;
-            const uint64_t & ADDRESS = i_adu_ctl.address;
-            const proc_adu_utils_fbc_op & FBC_OP = i_adu_ctl;
-            const proc_adu_utils_fbc_op_hp_ctl & FBC_OP_HP_CTL = i_adu_hp_ctl;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_ADU_UTILS_INVALID_FBC_OP);
-            break;
-        }
-
-        // build ADU Control register content
-        FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU Control register");
-        // ttype field
-        struct_data_to_insert = i_adu_ctl.ttype;
-        rc_ecmd |= ctl_data.insertFromRight(
-            &struct_data_to_insert,
-            ADU_CONTROL_FBC_TTYPE_START_BIT,
-            (ADU_CONTROL_FBC_TTYPE_END_BIT-
-             ADU_CONTROL_FBC_TTYPE_START_BIT+1));
-        // read/write bit
-        if (i_adu_ctl.cmd_type == ADU_FBC_OP_CMD_RD_ADDR_DATA)
-        {
-            rc_ecmd |= ctl_data.setBit(ADU_CONTROL_FBC_RNW_BIT);
-        }
-        // tsize field
-        struct_data_to_insert = i_adu_ctl.tsize;
-        rc_ecmd |= ctl_data.insertFromRight(
-            &struct_data_to_insert,
-            ADU_CONTROL_FBC_TSIZE_START_BIT,
-            (ADU_CONTROL_FBC_TSIZE_END_BIT-
-             ADU_CONTROL_FBC_TSIZE_START_BIT+1));
-        // address field
-        rc_ecmd |= ctl_data.insertFromRight((uint32_t)
-            (i_adu_ctl.address >>
-             ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT),
-            ADU_CONTROL_FBC_ADDRESS_START_BIT,
-            (ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT-1-
-             ADU_CONTROL_FBC_ADDRESS_START_BIT+1));
-        rc_ecmd |= ctl_data.insertFromRight((uint32_t)
-            (i_adu_ctl.address &
-             ADU_CONTROL_FBC_ADDRESS_SPLIT_MASK),
-            ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT,
-            (ADU_CONTROL_FBC_ADDRESS_END_BIT-
-             ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT+1));
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_send_fbc_op: Error 0x%x setting up ADU Control register data buffer",
-                     rc_ecmd);
-            break;
-        }
-        // write ADU Control register content
-        rc = fapiPutScom(i_target, ADU_CONTROL_0x02020000, ctl_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_send_fbc_op: fapiPutScom error (ADU_CONTROL_0x02020000)");
-            break;
-        }
-
-        // build ADU Command register content
-        FAPI_DBG("proc_adu_utils_send_fbc_op: Writing ADU Command register");
-        // start operation bit
-        rc_ecmd |= cmd_data.setBit(ADU_COMMAND_START_OP_BIT);
-        // address only bit
-        if (i_adu_ctl.cmd_type == ADU_FBC_OP_CMD_ADDR_ONLY)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_ADDRESS_ONLY_BIT);
-        }
-        // lock bit
-        rc_ecmd |= cmd_data.setBit(ADU_COMMAND_LOCKED_BIT);
-        // scope field
-        struct_data_to_insert = i_adu_ctl.scope;
-        rc_ecmd |= cmd_data.insertFromRight(
-            &struct_data_to_insert,
-            ADU_COMMAND_FBC_SCOPE_START_BIT,
-            (ADU_COMMAND_FBC_SCOPE_END_BIT-
-             ADU_COMMAND_FBC_SCOPE_START_BIT+1));
-        // auto-increment bit
-        if (i_adu_ctl.use_autoinc)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_AUTO_INC_BIT);
-        }
-        // drop priority
-        struct_data_to_insert = i_adu_ctl.drop_priority;
-        rc_ecmd |= cmd_data.insertFromRight(
-            &struct_data_to_insert,
-            ADU_COMMAND_FBC_DROP_PRIORITY_START_BIT,
-            (ADU_COMMAND_FBC_DROP_PRIORITY_END_BIT-
-             ADU_COMMAND_FBC_DROP_PRIORITY_START_BIT+1));
-        // fabric init policy controls
-        if (i_adu_ctl.init_policy == ADU_FBC_OP_FBC_INIT_OVERRIDE)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_INIT_OVERRIDE_BIT);
-        }
-        else if (i_adu_ctl.init_policy == ADU_FBC_OP_FBC_INIT_WAIT_LOW)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_INIT_WAIT_LOW_BIT);
-        }
-        // perform token manager quiesce?
-        if (i_use_hp && i_adu_hp_ctl.do_tm_quiesce)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_TM_QUIESCE_BIT);
-        }
-        // send fabric queisce command before programmed command?
-        // set cycle delay to apply after quiesce before programmed command
-        if (i_use_hp && i_adu_hp_ctl.do_pre_quiesce)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_PRE_QUIESCE_BIT);
-            rc_ecmd |= cmd_data.insertFromRight(
-                &i_adu_hp_ctl.post_quiesce_delay,
-                ADU_COMMAND_FBC_POST_QUIESCE_COUNT_START_BIT,
-                (ADU_COMMAND_FBC_POST_QUIESCE_COUNT_END_BIT-
-                 ADU_COMMAND_FBC_POST_QUIESCE_COUNT_START_BIT+1));
-        }
-        // send fabric init command after programmed command?
-        // set cycle delay to apply after programmed command before init
-        if (i_use_hp && i_adu_hp_ctl.do_post_init)
-        {
-            rc_ecmd |= cmd_data.setBit(ADU_COMMAND_FBC_POST_INIT_BIT);
-            rc_ecmd |= cmd_data.insertFromRight(
-                &i_adu_hp_ctl.pre_init_delay,
-                ADU_COMMAND_FBC_PRE_INIT_COUNT_START_BIT,
-                (ADU_COMMAND_FBC_PRE_INIT_COUNT_END_BIT-
-                 ADU_COMMAND_FBC_PRE_INIT_COUNT_START_BIT+1));
-        }
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_send_fbc_op: Error 0x%x forming data buffer",
-                     rc_ecmd);
-            break;
-        }
-
-        // write ADU Command register content
-        rc = fapiPutScom(i_target, ADU_COMMAND_0x02020001, cmd_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_send_fbc_op: fapiPutScom error (ADU_COMMAND_0x02020001)");
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_send_fbc_op: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_get_adu_status(
-    const fapi::Target& i_target,
-    proc_adu_utils_adu_status& o_status_act)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase status_data(64);
-
-    FAPI_DBG("proc_adu_utils_get_adu_status: Start");
-
-    do
-    {
-        // read ADU Status register
-        FAPI_DBG("proc_adu_utils_get_adu_status: Reading ADU Status register");
-        rc = fapiGetScom(i_target, ADU_STATUS_0x02020002, status_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_get_adu_status: fapiGetScom error (ADU_STATUS_0x02020002)");
-            break;
-        }
-
-        // fill actual structure
-        o_status_act.busy =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_BUSY_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.wait_cmd_arbit =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_WAIT_CMD_ARBIT_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.addr_done =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_ADDR_DONE_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.data_done =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_DATA_DONE_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.wait_resp =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_WAIT_RESP_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.overrun_err =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_OVERRUN_ERR_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.autoinc_err =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_AUTOINC_ERR_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.command_err =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_COMMAND_ERR_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.address_err =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_ADDRESS_ERR_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.command_hang_err =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_COMMAND_HANG_ERR_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.data_hang_err =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_DATA_HANG_ERR_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-        o_status_act.pbinit_missing =
-            status_data.isBitSet(ADU_STATUS_FBC_ALTD_INIT_MISSING_BIT) ?
-            ADU_STATUS_BIT_SET :
-            ADU_STATUS_BIT_CLEAR;
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_get_adu_status: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_set_adu_data_registers(
-    const fapi::Target& i_target,
-    const uint64_t i_write_data,
-    const bool i_override_itag,
-    const bool i_write_itag,
-    const bool i_override_ecc,
-    const uint8_t i_write_ecc)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase ecc_data(64);
-
-    FAPI_DBG("proc_adu_utils_set_adu_data_registers: Start");
-
-    do
-    {
-        // write ADU Force ECC Register first if directed
-        // this ordering is required to fully support auto-increment mode
-        if (i_override_itag ||
-            i_override_ecc)
-        {
-            FAPI_DBG("proc_adu_utils_set_adu_data_registers: Writing ADU Force ECC register");
-            if (i_override_itag)
-            {
-                rc_ecmd |= ecc_data.setBit(ADU_FORCE_ECC_DATA_ITAG_BIT);
-            }
-            if (i_override_ecc)
-            {
-                // set ECC override bit, duplicate override ECC
-                rc_ecmd |= ecc_data.setBit(ADU_FORCE_ECC_DATA_TX_ECC_OVERWRITE_BIT);
-                rc_ecmd |= ecc_data.insertFromRight(
-                    i_write_ecc,
-                    ADU_FORCE_ECC_DATA_TX_ECC_HI_START_BIT,
-                    ADU_FORCE_ECC_DATA_TX_ECC_HI_END_BIT-
-                    ADU_FORCE_ECC_DATA_TX_ECC_HI_START_BIT+1);
-                rc_ecmd |= ecc_data.insertFromRight(
-                    i_write_ecc,
-                    ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT,
-                    ADU_FORCE_ECC_DATA_TX_ECC_LO_END_BIT-
-                    ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT+1);
-            }
-            if (rc_ecmd)
-            {
-                rc.setEcmdError(rc_ecmd);
-                FAPI_ERR("proc_adu_utils_set_adu_data_registers: Error 0x%x forming override ECC data buffer",
-                         rc_ecmd);
-                break;
-            }
-
-            // write ADU Force ECC register
-            rc = fapiPutScom(i_target, ADU_FORCE_ECC_0x02020010, ecc_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_adu_utils_set_adu_data_registers: fapiPutScom error (ADU_FORCE_ECC_0x02020010)");
-                break;
-            }
-        }
-
-        // write ADU Data register
-        // this will generate new command in auto-increment mode
-        FAPI_DBG("proc_adu_utils_set_adu_data_registers: Writing ADU Data register");
-        rc_ecmd |= data.insertFromRight((uint32_t)
-            (i_write_data >> ADU_DATA_SPLIT_BIT),
-            ADU_DATA_START_BIT,
-            (ADU_DATA_SPLIT_BIT-1-
-             ADU_DATA_START_BIT+1));
-        rc_ecmd |= data.insertFromRight((uint32_t)
-            (i_write_data & ADU_DATA_SPLIT_MASK),
-            ADU_DATA_SPLIT_BIT,
-            (ADU_DATA_END_BIT-
-             ADU_DATA_SPLIT_BIT+1));
-        if (rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            FAPI_ERR("proc_adu_utils_set_adu_data_registers: Error 0x%x forming data buffer",
-                     rc_ecmd);
-            break;
-        }
-
-        // write ADU Data register
-        rc = fapiPutScom(i_target, ADU_DATA_0x02020003, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_set_adu_data_registers: fapiPutScom error (ADU_DATA_0x02020003)");
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_set_adu_data_registers: End");
-    return rc;
-}
-
-
-fapi::ReturnCode proc_adu_utils_get_adu_data_registers(
-    const fapi::Target& i_target,
-    const bool i_get_itag,
-    uint64_t& o_read_data,
-    bool& o_read_itag)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase ecc_data(64);
-
-    FAPI_DBG("proc_adu_utils_get_adu_data_registers: Start");
-
-    do
-    {
-        // read ADU Force ECC Register first if directed
-        // this ordering is required to fully support auto-increment mode
-        if (i_get_itag)
-        {
-            // read ADU Force ECC register
-            FAPI_DBG("proc_adu_utils_get_adu_data_registers: Reading ADU Force ECC register");
-            rc = fapiGetScom(i_target, ADU_FORCE_ECC_0x02020010, ecc_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_adu_utils_get_adu_data_registers: fapiGetScom error (ADU_FORCE_ECC_0x02020010)");
-                break;
-            }
-            o_read_itag = ecc_data.isBitSet(ADU_FORCE_ECC_DATA_ITAG_BIT);
-        }
-
-        // read ADU Data register
-        // this will generate new command in auto-increment mode
-        FAPI_DBG("proc_adu_utils_get_adu_data_registers: Reading ADU Data register");
-        rc = fapiGetScom(i_target, ADU_DATA_0x02020003, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_adu_utils_get_adu_data_registers: fapiGetScom error (ADU_DATA_0x02020003)");
-            break;
-        }
-        o_read_data = data.getDoubleWord(0);
-
-    } while(0);
-
-    FAPI_DBG("proc_adu_utils_get_adu_data_registers: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H
deleted file mode 100644
index 1f1533805..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H
+++ /dev/null
@@ -1,524 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_adu_utils.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_adu_utils.H,v 1.9 2014/09/11 21:57:13 aalugore Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_adu_utils.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_adu_utils.H
-// *! DESCRIPTION : ADU library functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Kevin Reick   Email: reick@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-// *! The functions contained in this library provide a mechanism to issue
-// *! fabric commands from the P8 Alter Display Unit (ADU).
-// *!
-// *! To perform a read operation on the fabric:
-// *!   o Obtain lock protecting ADU resources:
-// *!         proc_adu_utils_manage_adu_lock()
-// *!   o Clear ADU Status registers, reset ADU state machine:
-// *!         proc_adu_utils_reset_adu()
-// *!   o Program fabric command/address into ADU control logic & issue command
-// *!         proc_adu_utils_send_fbc_op()
-// *!   o Poll ADU status bits to ensure read data has arrived:
-// *!         proc_adu_utils_get_adu_status()
-// *!   o Read ADU data registers to retrieve data:
-// *!         proc_adu_utils_get_adu_data_registers()
-// *!   o Clear ADU lock:
-// *!         proc_adu_utils_manage_adu_lock()
-// *!
-// *! To perform a write operation on the fabric:
-// *!   o Obtain lock protecting ADU resources:
-// *!         proc_adu_utils_manage_adu_lock()
-// *!   o Clear ADU Status registers, reset ADU state machine:
-// *!         proc_adu_utils_reset_adu()
-// *!   o Write ADU data registers to set data to be written:
-// *!         proc_adu_utils_set_adu_data_registers()
-// *!   o Program fabric command/address into ADU control logic & issue command
-// *!         proc_adu_utils_send_fbc_op()
-// *!   o Poll ADU status bits to ensure read data has arrived:
-// *!         proc_adu_utils_get_adu_status()
-// *!   o Clear ADU lock:
-// *!         proc_adu_utils_manage_adu_lock()
-// *!
-// *! Additional functions are provided to:
-// *!   o Check ADU lock owner:
-// *!         proc_adu_utils_get_adu_lock_id()
-// *!   o Manage ADU auto-increment function
-// *!         proc_adu_utils_clear_adu_auto_inc()
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_ADU_UTILS_H_
-#define _PROC_ADU_UTILS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <proc_fbc_utils.H>
-#include <p8_scom_addresses.H>
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// ADU status bit comparison constants
-enum proc_adu_utils_status_bit
-{
-    ADU_STATUS_BIT_CLEAR = 0,    // status bit is clear (=0)
-    ADU_STATUS_BIT_SET = 1,      // status bit is set (=1)
-    ADU_STATUS_BIT_DONT_CARE = 2 // status bit is a don't care (=0 or =1)
-};
-
-// ADU fabric operation type
-enum proc_adu_utils_fbc_op_type
-{
-    ADU_FBC_OP_CMD_RD_ADDR_DATA = 0, // read command, address & data phase
-    ADU_FBC_OP_CMD_ADDR_ONLY = 1,    // address phase only
-    ADU_FBC_OP_CMD_WR_ADDR_DATA = 2  // write command, address & data phase
-};
-
-// ADU fabric init command issue policy control
-enum proc_adu_utils_fbc_init_policy
-{
-    ADU_FBC_OP_FBC_INIT_NO_OVERRIDE = 0x0, // don't issue command if fabric
-                                           // init line is low
-    ADU_FBC_OP_FBC_INIT_OVERRIDE = 0x1,    // issue command even if fabric
-                                           // init line is low
-    ADU_FBC_OP_FBC_INIT_WAIT_LOW = 0x2     // wait until fabric init line is
-                                           // low to issue command
-};
-
-// ADU supported fabric ttypes
-enum proc_adu_utils_fbc_ttype
-{
-    ADU_FBC_OP_TTYPE_PBOP = 0x3F,     // PB operation
-    ADU_FBC_OP_TTYPE_PMISC = 0x31,    // pervasive misc
-    ADU_FBC_OP_TTYPE_CI_PR_W = 0x37,  // cache-inhibited partial write
-    ADU_FBC_OP_TTYPE_DMA_PR_W = 0x26, // DMA partial write
-    ADU_FBC_OP_TTYPE_CI_PR_RD = 0x34, // cache-inhibited partial read
-    ADU_FBC_OP_TTYPE_DMA_PR_RD = 0x35 // DMA partial read
-};
-
-// ADU supported fabric tsize encodings
-enum proc_adu_utils_fbc_tsize
-{
-    ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_EN = 0x08,   // pbop disable_all
-                                                  // (dis command, dis data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_PBOP_EN_RCMD_FP_EN = 0x09,   // pbop enable_rcmd_only
-                                                  // (en command, dis data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_PBOP_EN_DATA_FP_EN = 0x0A,   // pbop enable_data_only
-                                                  // (dis command, en data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_PBOP_EN_ALL_FP_EN = 0x0B,    // pbop enable_all
-                                                  // (en command, en data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_DIS = 0x00,  // pbop disable_all
-                                                  // (dis command, dis data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_PBOP_EN_RCMD_FP_DIS = 0x01,  // pbop enable_rcmd_only
-                                                  // (en command, dis data)
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_PBOP_EN_DATA_FP_DIS = 0x02,  // pbop enable_data_only
-                                                  // (dis command, en data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_PBOP_EN_ALL_FP_DIS = 0x03,   // pbop enable_all
-                                                  // (en command, en data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_FPBOP_DIS_ALL_FP_EN = 0x48,  // fpbop disable_all
-                                                  // (dis command, dis data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_FPBOP_EN_RCMD_FP_EN = 0x49,  // fpbop enable_rcmd_only
-                                                  // (en command, dis data)
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_FPBOP_EN_DATA_FP_EN = 0x4A,  // fpbop enable_data_only
-                                                  // (dis command, en data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_FPBOP_EN_ALL_FP_EN = 0x4B,   // fpbop enable_all
-                                                  // (en command, en data),
-                                                  // MC fast-path enable
-    ADU_FBC_OP_TSIZE_FPBOP_DIS_ALL_FP_DIS = 0x40, // fpbop disable_all
-                                                  // (dis command, dis data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_FPBOP_EN_RCMD_FP_DIS = 0x41, // fpbop enable_rcmd_only
-                                                  // (en command, dis data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_FPBOP_EN_DATA_FP_DIS = 0x42, // fpbop enable_data_only
-                                                  // (dis command, en data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_FPBOP_EN_ALL_FP_DIS  = 0x43, // fpbop enable_all
-                                                  // (en command, en data),
-                                                  // MC fast-path disable
-    ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB = 0x01,      // pervasive misc switch AB
-    ADU_FBC_OP_TSIZE_1B = 0x01,                   // one byte transfer size
-    ADU_FBC_OP_TSIZE_2B = 0x02,                   // two byte transfer size
-    ADU_FBC_OP_TSIZE_3B = 0x03,                   // three byte transfer size
-    ADU_FBC_OP_TSIZE_4B = 0x04,                   // four byte transfer size
-    ADU_FBC_OP_TSIZE_8B = 0x08,                   // eight byte transfer size
-    ADU_FBC_OP_TSIZE_CI_PR_W_1B = 0x01,           // one byte transfer size
-    ADU_FBC_OP_TSIZE_CI_PR_W_2B = 0x02,           // two byte transfer size
-    ADU_FBC_OP_TSIZE_CI_PR_W_4B = 0x03,           // four byte transfer size
-    ADU_FBC_OP_TSIZE_CI_PR_W_8B = 0x04            // eight byte transfer size
-};
-
-
-// ADU supported fabric priority encodings
-enum proc_adu_utils_fbc_drop_priority
-{
-    ADU_FBC_OP_DROP_PRIORITY_LOW = 0x0, // lowest priority command request
-                                        // (highest issue rate, first to be
-                                        // dropped)
-    ADU_FBC_OP_DROP_PRIORITY_MED = 0x1, // medium priority command request
-                                        // (next highest issue rate, can be
-                                        // dropped after low priority commands)
-    ADU_FBC_OP_DROP_PRIORITY_HIGH = 0x2 // high priority command request
-                                        // (slowest issue rate, can only be
-                                        // dropped after low & medium priority
-                                        // commands)
-};
-
-// ADU suppored fabric scope encodings
-enum proc_adu_utils_fbc_scope
-{
-    ADU_FBC_OP_SCOPE_NODAL = 0x0,         // nodal scope, physical broadcast to
-                                          // all units on local chip
-    ADU_FBC_OP_SCOPE_GROUP = 0x1,         // group scope, physical broadcast to
-                                          // all units on local physical group
-    ADU_FBC_OP_SCOPE_SYSTEM = 0x2,        // system scope, physical broadcast to
-                                          // all units in SMP
-    ADU_FBC_OP_SCOPE_REMOTE_GROUP = 0x3,  // remote group scope, physical
-                                          // broadcast to all units in remote
-                                          // group
-    ADU_FBC_OP_SCOPE_FOREIGN_LINK0 = 0x4, // foreign scope, physical broadcast
-                                          // is all units on the local chip on
-                                          // local SMP and remote chip on
-                                          // remote SMP (foreign link ID 0)
-    ADU_FBC_OP_SCOPE_FOREIGN_LINK1 = 0x5, // foreign scope, physical broadcast
-                                          // is all units on the local chip on
-                                          // local SMP and remote chip on
-                                          // remote SMP (foreign link ID 1)
-    ADU_FBC_OP_SCOPE_FOREIGN_LINK2 = 0x6, // foreign scope, physical broadcast
-                                          // is all units on the local chip on
-                                          // local SMP and remote chip on
-                                          // remote SMP (foreign link ID 2)
-    ADU_FBC_OP_SCOPE_FOREIGN_LINK3 = 0x7  // foreign scope, physical broadcast
-                                          // is all units on the local chip on
-                                          // local SMP and remote chip on
-                                          // remote SMP (foreign link ID 3)
-};
-
-// ADU lock operations
-enum proc_adu_utils_adu_lock_operation
-{
-    ADU_LOCK_ACQUIRE,       // acquire lock
-    ADU_LOCK_FORCE_ACQUIRE, // acquire lock (with lock pick)
-    ADU_LOCK_RELEASE        // release lock
-};
-
-// ADU fabric operation control information
-struct proc_adu_utils_fbc_op {
-    proc_adu_utils_fbc_ttype ttype;                 // fabric ttype
-    proc_adu_utils_fbc_tsize tsize;                 // fabric tsize
-    uint64_t address;                               // fabric address
-    proc_adu_utils_fbc_scope scope;                 // fabric scope
-    proc_adu_utils_fbc_drop_priority drop_priority; // fabric drop priority
-    proc_adu_utils_fbc_op_type cmd_type;            // command type
-    proc_adu_utils_fbc_init_policy init_policy;     // fabric init issue policy
-    bool use_autoinc;                               // use ADU auto-increment?
-};
-
-// ADU fabric hotplug operation control information
-struct proc_adu_utils_fbc_op_hp_ctl {
-    bool do_tm_quiesce;          // quiesce fabric token manager prior to
-                                 // issuing programmed command?
-    bool do_pre_quiesce;         // send fabric quiesce command prior to
-                                 // issuing programmed command?
-    bool do_post_init;           // send fabric init command after issuing
-                                 // programmed command
-    uint32_t post_quiesce_delay; // cycle delay to pause after pre-quiesce
-                                 // command (clean cresp) before issuing
-                                 // programmed command
-    uint32_t pre_init_delay;     // cycle delay to pause after programmed
-                                 // command (clean cresp) before issuing
-                                 // post-init command
-
-//Constructor
-    proc_adu_utils_fbc_op_hp_ctl() {
-        do_tm_quiesce = false;
-        do_pre_quiesce = false;
-        do_post_init = false;
-        post_quiesce_delay = 0;
-        pre_init_delay = 0;
-    }
-
-};
-
-// ADU status structure
-struct proc_adu_utils_adu_status {
-    proc_adu_utils_status_bit busy;             // altd_busy
-    proc_adu_utils_status_bit wait_cmd_arbit;   // altd_wait_cmd_arbit
-    proc_adu_utils_status_bit addr_done;        // altd_addr_done
-    proc_adu_utils_status_bit data_done;        // altd_data_done
-    proc_adu_utils_status_bit wait_resp;        // altd_wait_resp
-    proc_adu_utils_status_bit overrun_err;      // altd_overrun_error
-    proc_adu_utils_status_bit autoinc_err;      // altd_autoinc_error
-    proc_adu_utils_status_bit command_err;      // altd_command_error
-    proc_adu_utils_status_bit address_err;      // altd_address_error
-    proc_adu_utils_status_bit command_hang_err; // altd_pb_op_hang_error
-    proc_adu_utils_status_bit data_hang_err;    // altd_pb_data_hang_error
-    proc_adu_utils_status_bit pbinit_missing;   // altd_pbinit_missing
-};
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// ADU operation delay times for HW/sim
-const uint32_t PROC_ADU_UTILS_ADU_HW_NS_DELAY = 10000;
-const uint32_t PROC_ADU_UTILS_ADU_SIM_CYCLE_DELAY = 10000;
-
-// field width definitions
-const uint32_t PROC_ADU_UTILS_ADU_MAX_POST_QUIESCE_DELAY = ((1 << 20)-1);
-const uint32_t PROC_ADU_UTILS_ADU_MAX_PRE_INIT_DELAY = ((1 << 10)-1);
-
-// auto-increment constant definitions
-const uint32_t PROC_ADU_UTILS_AUTO_INCREMENT_BOUNDARY_MASK = 0x7FFFF;
-const uint32_t PROC_ADU_UTILS_AUTO_INCREMENT_BOUNDARY = 0x7FFF8;
-
-// Security Switch register field/bit definitions
-const uint32_t OTPC_M_SECURITY_SWITCH_TRUSTED_BOOT_BIT = 1;
-
-// ADU Control register field/bit definitions
-const uint32_t ADU_CONTROL_FBC_TTYPE_START_BIT = 0;
-const uint32_t ADU_CONTROL_FBC_TTYPE_END_BIT = 5;
-const uint32_t ADU_CONTROL_FBC_RNW_BIT = 6;
-const uint32_t ADU_CONTROL_FBC_TSIZE_START_BIT = 7;
-const uint32_t ADU_CONTROL_FBC_TSIZE_END_BIT = 13;
-const uint32_t ADU_CONTROL_FBC_ADDRESS_START_BIT = 14;
-const uint32_t ADU_CONTROL_FBC_ADDRESS_END_BIT = 63;
-
-const uint32_t ADU_CONTROL_FBC_ADDRESS_SPLIT_BIT = 32;
-const uint32_t ADU_CONTROL_FBC_ADDRESS_SPLIT_MASK = 0xFFFFFFFF;
-
-// ADU Command register field/bit definitions
-const uint32_t ADU_COMMAND_START_OP_BIT = 2;
-const uint32_t ADU_COMMAND_CLEAR_STATUS_BIT = 3;
-const uint32_t ADU_COMMAND_RESET_BIT = 4;
-const uint32_t ADU_COMMAND_ADDRESS_ONLY_BIT = 6;
-const uint32_t ADU_COMMAND_LOCK_PICK_BIT = 10;
-const uint32_t ADU_COMMAND_LOCKED_BIT = 11;
-const uint32_t ADU_COMMAND_LOCK_ID_START_BIT = 12;
-const uint32_t ADU_COMMAND_LOCK_ID_END_BIT = 15;
-const uint32_t ADU_COMMAND_LOCK_ID_MAX_VALUE = 0xF;
-const uint32_t ADU_COMMAND_FBC_SCOPE_START_BIT = 16;
-const uint32_t ADU_COMMAND_FBC_SCOPE_END_BIT = 18;
-const uint32_t ADU_COMMAND_AUTO_INC_BIT = 19;
-const uint32_t ADU_COMMAND_FBC_DROP_PRIORITY_START_BIT = 20;
-const uint32_t ADU_COMMAND_FBC_DROP_PRIORITY_END_BIT = 21;
-const uint32_t ADU_COMMAND_FBC_INIT_OVERRIDE_BIT = 23;
-const uint32_t ADU_COMMAND_FBC_INIT_WAIT_LOW_BIT = 25;
-const uint32_t ADU_COMMAND_FBC_TM_QUIESCE_BIT = 26;
-const uint32_t ADU_COMMAND_FBC_PRE_QUIESCE_BIT = 27;
-const uint32_t ADU_COMMAND_FBC_POST_QUIESCE_COUNT_START_BIT = 28;
-const uint32_t ADU_COMMAND_FBC_POST_QUIESCE_COUNT_END_BIT = 47;
-const uint32_t ADU_COMMAND_FBC_PRE_INIT_COUNT_START_BIT = 50;
-const uint32_t ADU_COMMAND_FBC_PRE_INIT_COUNT_END_BIT = 59;
-const uint32_t ADU_COMMAND_FBC_POST_INIT_BIT = 63;
-
-// ADU Status register field/bit definitions
-const uint32_t ADU_STATUS_FBC_ALTD_BUSY_BIT = 0;
-const uint32_t ADU_STATUS_FBC_ALTD_WAIT_CMD_ARBIT_BIT = 1;
-const uint32_t ADU_STATUS_FBC_ALTD_ADDR_DONE_BIT = 2;
-const uint32_t ADU_STATUS_FBC_ALTD_DATA_DONE_BIT = 3;
-const uint32_t ADU_STATUS_FBC_ALTD_WAIT_RESP_BIT = 4;
-const uint32_t ADU_STATUS_FBC_ALTD_OVERRUN_ERR_BIT = 5;
-const uint32_t ADU_STATUS_FBC_ALTD_AUTOINC_ERR_BIT = 6;
-const uint32_t ADU_STATUS_FBC_ALTD_COMMAND_ERR_BIT = 7;
-const uint32_t ADU_STATUS_FBC_ALTD_ADDRESS_ERR_BIT = 8;
-const uint32_t ADU_STATUS_FBC_ALTD_COMMAND_HANG_ERR_BIT = 9;
-const uint32_t ADU_STATUS_FBC_ALTD_DATA_HANG_ERR_BIT = 10;
-const uint32_t ADU_STATUS_FBC_ALTD_INIT_MISSING_BIT = 18;
-
-// ADU Force ECC register field/bit definitions
-const uint32_t ADU_FORCE_ECC_DATA_ITAG_BIT = 0;
-const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_HI_START_BIT = 1;
-const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_HI_END_BIT = 8;
-const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_LO_START_BIT = 9;
-const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_LO_END_BIT = 16;
-const uint32_t ADU_FORCE_ECC_DATA_TX_ECC_OVERWRITE_BIT = 17;
-
-// ADU Data register field/bit definitions
-const uint32_t ADU_DATA_START_BIT = 0;
-const uint32_t ADU_DATA_END_BIT = 63;
-
-const uint32_t ADU_DATA_SPLIT_BIT = 32;
-const uint32_t ADU_DATA_SPLIT_MASK = 0xFFFFFFFF;
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// function: read ADU Command register, get ADU lock identifier
-// parameters: i_target  => P8 chip target
-//             o_lock_id => lock ID read
-// returns: FAPI_RC_SUCCESS if SCOM read is successful,
-//          else error
-fapi::ReturnCode proc_adu_utils_get_adu_lock_id(
-    const fapi::Target& i_target,
-    uint8_t& o_lock_id);
-
-// function: read-modify-write ADU Command register to clear auto-increment
-//           mode (necessary to complete operation at 0.5M boundary)
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target => P8 chip target
-// returns: FAPI_RC_SUCCESS if read-modify-write sequence is successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          else error
-fapi::ReturnCode proc_adu_utils_clear_adu_auto_inc(
-    const fapi::Target& i_target);
-
-// function: manipulate state of ADU atomic lock (set/pick/clear)
-// parameters: i_target         => P8 chip target
-//             i_lock_operation => lock operation to perform
-//             i_num_attempts   => number of lock manipulation attempts to
-//                                 make before giving up (will only
-//                                 continue to attempt if SCOM return code
-//                                 indicates failure due to lock state)
-// returns: FAPI_RC_SUCCESS if lock manipulation is successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          else error
-fapi::ReturnCode proc_adu_utils_manage_adu_lock(
-    const fapi::Target& i_target,
-    const proc_adu_utils_adu_lock_operation i_lock_operation,
-    const uint32_t i_num_attempts);
-
-// function: write ADU Command register to clear the ADU Status register and
-//           reset the ADU state machine
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target => P8 chip target
-// returns: FAPI_RC_SUCCESS if ADU reset is successful
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          else error
-fapi::ReturnCode proc_adu_utils_reset_adu(
-    const fapi::Target& i_target);
-
-// function: initiate fabric command via writes to ADU Command & Control
-//           registers
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target     => P8 chip target
-//             i_adu_ctl    => struct defining fabric command type & ADU control
-//                             parameters
-//             i_use_hp     => perform actions specified in hotplug control
-//                             argument?
-//             i_adu_hp_ctl => struct defining hotplug control parameters
-// returns: FAPI_RC_SUCCESS if ADU Command/Control register writes are
-//              successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation
-//              parameters are specified,
-//          else error
-fapi::ReturnCode proc_adu_utils_send_fbc_op(
-    const fapi::Target& i_target,
-    const proc_adu_utils_fbc_op i_adu_ctl,
-    const bool i_use_hp,
-    const proc_adu_utils_fbc_op_hp_ctl i_adu_hp_ctl);
-
-// function: read ADU Status register, return structure encapsulating
-//           error/status bits
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target      => P8 chip target
-//             o_status_act  => struct defining state of status/error bits
-// returns: FAPI_RC_SUCCESS if status register read is successful,
-//          else error
-fapi::ReturnCode proc_adu_utils_get_adu_status(
-    const fapi::Target& i_target,
-    proc_adu_utils_adu_status& o_status_act);
-
-// function: write ADU Data & Force ECC registers (to set outbound data to be
-//           delivered to the fabric)
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target        => P8 chip target
-//             i_write_data    => 64-bits of data to be written
-//             i_override_itag => set value of itag (65th) bit?
-//             i_write_itag    => value of itag (65th) bit to be written if
-//                                i_override_itag=true
-//             i_override_ecc  => set override ECC value?
-//             i_write_ecc     => value of ECC to be written if
-//                                i_override_ecc=true
-// returns: FAPI_RC_SUCCESS if register writes are successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          else error
-fapi::ReturnCode proc_adu_utils_set_adu_data_registers(
-    const fapi::Target& i_target,
-    const uint64_t i_write_data,
-    const bool i_override_itag,
-    const bool i_write_itag,
-    const bool i_override_ecc,
-    const uint8_t i_write_ecc);
-
-// function: read ADU Data & Force ECC registers (to get inbound data
-//           delivered from the fabric)
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target     => P8 chip target
-//             i_get_itag   => get value of itag (65th) bit?
-//             o_read_data  => 64-bits of data read
-//             o_read_itag  => value of itag (65th) bit read (only valid
-//                             if i_get_itag=true)
-// returns: FAPI_RC_SUCCESS if register reads are successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          else error
-fapi::ReturnCode proc_adu_utils_get_adu_data_registers(
-    const fapi::Target& i_target,
-    const bool i_get_itag,
-    uint64_t& o_read_data,
-    bool& o_read_itag);
-
-} // extern "C"
-
-#endif // _PROC_ADU_UTILS_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
deleted file mode 100644
index 6517d1fae..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C
+++ /dev/null
@@ -1,1479 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp.C,v 1.20 2015/02/09 22:36:45 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp.C
-// *! DESCRIPTION : Perform fabric configuration (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp.H>
-#include <proc_build_smp_epsilon.H>
-#include <proc_build_smp_fbc_nohp.H>
-#include <proc_build_smp_fbc_ab.H>
-#include <proc_build_smp_fbc_cd.H>
-#include <proc_build_smp_adu.H>
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to call all system attribute query functions
-//           (fabric configuration/frequencies/etc)
-// parameters: io_smp_chip => structure encapsulating single chip in SMP topology
-// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
-//              are valid,
-//          RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_PUMP_TYPE_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR if invalid relationship exists
-//              between ceiling/nominal/floor core frequency attributes,
-//          RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is
-//              invalid,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_process_system(
-    proc_build_smp_system& io_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // temporary attribute storage
-    uint8_t temp_attr;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_process_system: Start");
-
-    do
-    {
-        io_smp.avp_mode = false;
-
-        // get PB frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying PB frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_PB_MHZ,
-                           NULL,
-                           io_smp.freq_pb);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_PB_MHZ");
-            break;
-        }
-
-        // get A bus frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying A bus frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_A_MHZ,
-                           NULL,
-                           io_smp.freq_a);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_A_MHZ");
-            break;
-        }
-
-        // get X bus frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying X bus frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_X_MHZ,
-                           NULL,
-                           io_smp.freq_x);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_X_MHZ");
-            break;
-        }
-
-        // get core floor frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying core floor frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_FLOOR_MHZ,
-                           NULL,
-                           io_smp.freq_core_floor);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_FLOOR_MHZ)");
-            break;
-        }
-
-        // get core nominal frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying core nominal frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_NOMINAL_MHZ,
-                           NULL,
-                           io_smp.freq_core_nom);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_NOMINAL_MHZ)");
-            break;
-        }
-
-        // get core ceiling frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying core ceiling frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_MAX,
-                           NULL,
-                           io_smp.freq_core_ceiling);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_CORE_MAX)");
-            break;
-        }
-
-        if (!((io_smp.freq_core_ceiling >= io_smp.freq_core_nom) &&
-              (io_smp.freq_core_nom     >= io_smp.freq_core_floor)))
-        {
-            const uint32_t& FREQ_CORE_CEILING = io_smp.freq_core_ceiling;
-            const uint32_t& FREQ_CORE_NOM = io_smp.freq_core_nom;
-            const uint32_t& FREQ_CORE_FLOOR = io_smp.freq_core_floor;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR);
-            break;
-        }
-
-        // get PCIe frequency attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying PCIe frequency attribute");
-        rc = FAPI_ATTR_GET(ATTR_FREQ_PCIE_MHZ,
-                           NULL,
-                           io_smp.freq_pcie);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_FREQ_PCIE_MHZ");
-            break;
-        }
-
-        // get X bus width attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying X bus width attribute");
-        rc = FAPI_ATTR_GET(ATTR_PROC_X_BUS_WIDTH,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_X_BUS_WIDTH)");
-            break;
-        }
-
-        // translate to output value
-        switch (temp_attr)
-        {
-            case 1:
-                io_smp.x_bus_8B = false;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_X_BUS_WIDTH = 4B");
-                break;
-            case 2:
-                io_smp.x_bus_8B = true;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_X_BUS_WIDTH = 8B");
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_process_system: Invalid X bus width attribute value 0x%02X",
-                         temp_attr);
-                const uint8_t& ATTR_DATA = temp_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // get PB pump type attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying PB pump mode attribute");
-        rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_PUMP_MODE,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_PUMP_MODE)");
-            break;
-        }
-
-        // translate to output value
-        switch (temp_attr)
-        {
-            case 1:
-                io_smp.pump_mode = PROC_FAB_SMP_PUMP_MODE1;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_PUMP_MODE = NODAL_IS_CHIP_GROUP_IS_GROUP");
-                break;
-            case 2:
-                io_smp.pump_mode = PROC_FAB_SMP_PUMP_MODE2;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_PUMP_MODE = NODAL_AND_GROUP_IS_GROUP");
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_process_system: Invalid fabric pump mode attribute value 0x%02X",
-                         temp_attr);
-                const uint8_t& ATTR_DATA = temp_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_PUMP_MODE_ATTR_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // get MCS interleaving attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying MC interleave attribute");
-        rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_ALL_MCS_IN_INTERLEAVING_GROUP)");
-            break;
-        }
-
-        // translate to output value
-        switch (temp_attr)
-        {
-            case 0:
-                io_smp.all_mcs_interleaved = false;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_ALL_MCS_IN_INTERLEAVING_GROUP = false");
-                break;
-            case 1:
-                FAPI_DBG("proc_build_smp_process_system: ATTR_ALL_MCS_IN_INTERLEAVING_GROUP = true");
-                io_smp.all_mcs_interleaved = true;
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_process_system: Invalid MCS interleaving value 0x%02X",
-                         temp_attr);
-                const uint8_t& ATTR_DATA = temp_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // get epsilon attributes
-        FAPI_DBG("proc_build_smp_process_system: Querying epsilon table type attribute");
-        rc = FAPI_ATTR_GET(ATTR_PROC_EPS_TABLE_TYPE,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_EPS_TABLE_TYPE)");
-            break;
-        }
-
-        // translate to output value
-        switch (temp_attr)
-        {
-            case 1:
-                io_smp.eps_cfg.table_type = PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_TABLE_TYPE = LE");
-                break;
-            case 2:
-                io_smp.eps_cfg.table_type = PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_TABLE_TYPE = HE");
-                break;
-            case 3:
-                io_smp.eps_cfg.table_type = PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_TABLE_TYPE = 1S");
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_process_system: Invalid epsilon table type attribute value 0x%02X",
-                         temp_attr);
-                const uint8_t& ATTR_DATA = temp_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_process_system: Querying epsilon guardband attributes");
-        // set default value (+20%)
-        temp_attr = 0x0;
-        rc = FAPI_ATTR_SET(ATTR_PROC_EPS_GB_DIRECTION,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_SET (ATTR_PROC_EPS_GB_DIRECTION)");
-            break;
-        }
-
-        io_smp.eps_cfg.gb_percentage = 20;
-        rc = FAPI_ATTR_SET(ATTR_PROC_EPS_GB_PERCENTAGE,
-                           NULL,
-                           io_smp.eps_cfg.gb_percentage);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_SET (ATTR_PROC_EPS_GB_PERCENTAGE)");
-            break;
-        }
-
-        // retrieve guardband attributes
-        // if user overrides are set, the user overrides will take presedence over writes above
-        rc = FAPI_ATTR_GET(ATTR_PROC_EPS_GB_DIRECTION,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_EPS_GB_DIRECTION)");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_EPS_GB_PERCENTAGE,
-                           NULL,
-                           io_smp.eps_cfg.gb_percentage);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_EPS_GB_PERCENTAGE)");
-            break;
-        }
-
-        // print attribute values
-        FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_GB_PERCENTAGE = 0x%X",
-                 io_smp.eps_cfg.gb_percentage);
-
-        // translate to output value
-        switch (temp_attr)
-        {
-            case 0:
-                io_smp.eps_cfg.gb_positive = true;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_GB_DIRECTION = +");
-                break;
-            case 1:
-                io_smp.eps_cfg.gb_positive = false;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_EPS_GB_DIRECTION = -");
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_process_system: Invalid epsilon guardband direction attribute value 0x%02X",
-                         temp_attr);
-                const uint8_t& ATTR_DATA = temp_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // manage safe mode attribute
-        FAPI_DBG("proc_build_smp_process_system: Querying async safe mode attribute");
-        // set default value (performance mode)
-        temp_attr = 0x0;
-        rc = FAPI_ATTR_SET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_SET (ATTR_PROC_FABRIC_ASYNC_SAFE_MODE)");
-            break;
-        }
-
-        // retrieve safe mode attribute
-        // if user overrides is set, it will take precedence over write above
-        rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE,
-                           NULL,
-                           temp_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_system: Error from FAPI_ATTR_GET (ATTR_PROC_FABRIC_ASYNC_SAFE_MODE)");
-            break;
-        }
-
-        // translate to output value
-        switch (temp_attr)
-        {
-            case 0:
-                io_smp.async_safe_mode = false;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_ASYNC_SAFE_MODE = false");
-                break;
-            case 1:
-                io_smp.async_safe_mode = true;
-                FAPI_DBG("proc_build_smp_process_system: ATTR_PROC_FABRIC_ASYNC_SAFE_MODE = true");
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_process_system: Invalid fabric async safe mode attribute value 0x%02X",
-                         temp_attr);
-                const uint8_t& ATTR_DATA = temp_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // determine epsilon table index based on pb/core floor frequency ratio
-        // breakpoint ratio: core floor 4.8, pb 2.4 (cache floor :: pb = 8/8)
-        FAPI_DBG("proc_build_smp_process_system: Calculating core floor to nest frequency ratio");
-        if ((io_smp.freq_core_floor) >= (2 * io_smp.freq_pb))
-        {
-            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_8_8;
-        }
-        // breakpoint ratio: core floor 4.2, pb 2.4 (cache floor :: pb = 7/8)
-        else if ((4 * io_smp.freq_core_floor) >= (7 * io_smp.freq_pb))
-        {
-            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_7_8;
-        }
-        // breakpoint ratio: core floor 3.6, pb 2.4 (cache floor :: pb = 6/8)
-        else if ((2 * io_smp.freq_core_floor) >= (3 * io_smp.freq_pb))
-        {
-            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_6_8;
-        }
-        // breakpoint ratio: core floor 3.0, pb 2.4 (cache floor :: pb = 5/8)
-        else if ((4 * io_smp.freq_core_floor) >= (5 * io_smp.freq_pb))
-        {
-            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_5_8;
-        }
-        // breakpoint ratio: core floor 2.4, pb 2.4 (cache floor :: pb = 4/8)
-        else if (io_smp.freq_core_floor >= io_smp.freq_pb)
-        {
-            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_4_8;
-        }
-        // breakpoint ratio: core floor 1.2, pb 2.4 (cache floor :: pb = 2/8)
-        else if ((2 * io_smp.freq_core_floor) >= io_smp.freq_pb)
-        {
-            io_smp.core_floor_ratio = PROC_BUILD_SMP_CORE_RATIO_2_8;
-        }
-        // under-range, raise error
-        else
-        {
-            FAPI_ERR("proc_build_smp_process_system: Unsupported core floor/PB frequency ratio (=%d/%d)",
-                     io_smp.freq_core_floor, io_smp.freq_pb);
-            const uint32_t& FREQ_PB = io_smp.freq_pb;
-            const uint32_t& FREQ_CORE_FLOOR = io_smp.freq_core_floor;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR);
-            break;
-        }
-
-        // determine table index based on pb/core ceiling frequency ratio
-        // breakpoint ratio: core ceiling 4.8, pb 2.4 (cache ceiling :: pb = 8/8)
-        FAPI_DBG("proc_build_smp_process_system: Calculating core ceiling to nest frequency ratio");
-        if ((io_smp.freq_core_ceiling) >= (2 * io_smp.freq_pb))
-        {
-            io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_8_8;
-        }
-        // breakpoint ratio: core ceiling 4.2, pb 2.4 (cache ceiling :: pb = 7/8)
-        else if ((4 * io_smp.freq_core_ceiling) >= (7 * io_smp.freq_pb))
-        {
-            io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_7_8;
-        }
-        // breakpoint ratio: core ceiling 3.6, pb 2.4 (cache ceiling :: pb = 6/8)
-        else if ((2 * io_smp.freq_core_ceiling) >= (3 * io_smp.freq_pb))
-        {
-            io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_6_8;
-        }
-        // breakpoint ratio: core ceiling 3.0, pb 2.4 (cache ceiling :: pb = 5/8)
-        else if ((4 * io_smp.freq_core_ceiling) >= (5 * io_smp.freq_pb))
-        {
-            io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_5_8;
-        }
-        // breakpoint ratio: core ceiling 2.4, pb 2.4 (cache ceiling :: pb = 4/8)
-        else if (io_smp.freq_core_ceiling >= io_smp.freq_pb)
-        {
-            io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_4_8;
-        }
-        // breakpoint ratio: core ceiling 1.2, pb 2.4 (cache ceiling :: pb = 2/8)
-        else if ((2 * io_smp.freq_core_ceiling) >= io_smp.freq_pb)
-        {
-            io_smp.core_ceiling_ratio = PROC_BUILD_SMP_CORE_RATIO_2_8;
-        }
-        // under-range, raise error
-        else
-        {
-            FAPI_ERR("proc_build_smp_process_system: Unsupported core ceiling/PB frequency ratio (=%d/%d)",
-                     io_smp.freq_core_ceiling, io_smp.freq_pb);
-            const uint32_t& FREQ_PB = io_smp.freq_pb;
-            const uint32_t& FREQ_CORE_CEILING = io_smp.freq_core_ceiling;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR);
-            break;
-        }
-
-        // determine full CPU delay settings
-        FAPI_DBG("proc_build_smp_process_system: Calculating full CPU delay settings:");
-        if ((2400 * io_smp.freq_core_ceiling) >= (4800 * io_smp.freq_pb))
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4800_2400;
-        }
-        else if ((2400 * io_smp.freq_core_ceiling) >= (4431 * io_smp.freq_pb))
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4431_2400;
-        }
-        else if ((2400 * io_smp.freq_core_ceiling) >= (4114 * io_smp.freq_pb))
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4114_2400;
-        }
-        else if ((2400 * io_smp.freq_core_ceiling) >= (3840 * io_smp.freq_pb))
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3840_2400;
-        }
-        else if ((2400 * io_smp.freq_core_ceiling) >= (3338 * io_smp.freq_pb))
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3338_2400;
-        }
-        else if ((2400 * io_smp.freq_core_ceiling) >= (3032 * io_smp.freq_pb))
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3032_2400;
-        }
-        else
-        {
-            io_smp.full_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2743_2400;
-        }
-
-        // determine nominal CPU delay settings
-        FAPI_DBG("proc_build_smp_process_system: Calculating nominal CPU delay settings:");
-        if ((2400 * io_smp.freq_core_nom) >= (4800 * io_smp.freq_pb))
-        {
-            // shift to avoid equivalent index
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4431_2400;
-        }
-        else if ((2400 * io_smp.freq_core_nom) >= (4431 * io_smp.freq_pb))
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4431_2400;
-            // shift to avoid equivalent index
-            if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay)
-            {
-                io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4114_2400;
-            }
-        }
-        else if ((2400 * io_smp.freq_core_nom) >= (4114 * io_smp.freq_pb))
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_4114_2400;
-            // shift to avoid equivalent index
-            if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay)
-            {
-                io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3840_2400;
-            }
-        }
-        else if ((2400 * io_smp.freq_core_nom) >= (3840 * io_smp.freq_pb))
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3840_2400;
-            // shift to avoid equivalent index
-            if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay)
-            {
-                io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3338_2400;
-            }
-        }
-        else if ((2400 * io_smp.freq_core_nom) >= (3338 * io_smp.freq_pb))
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3338_2400;
-            // shift to avoid equivalent index
-            if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay)
-            {
-                io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3032_2400;
-            }
-        }
-        else if ((2400 * io_smp.freq_core_nom) >= (3032 * io_smp.freq_pb))
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_3032_2400;
-            // shift to avoid equivalent index
-            if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay)
-            {
-                io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2743_2400;
-            }
-        }
-        else if ((2400 * io_smp.freq_core_nom) >= (2743 * io_smp.freq_pb))
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2743_2400;
-            // shift to avoid equivalent index
-            if (io_smp.nom_cpu_delay == io_smp.full_cpu_delay)
-            {
-                io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2504_2400;
-            }
-        }
-        else
-        {
-            io_smp.nom_cpu_delay = PROC_BUILD_SMP_CPU_DELAY_2504_2400;
-        }
-
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_process_system: End");
-    return rc;
-};
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to call all chip attribute query functions
-//           (fabric configuration/node/position)
-// parameters: i_proc_chip => pointer to HWP input structure for this chip
-//             io_smp_chip => structure encapsulating single chip in SMP topology
-// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
-//              are valid,
-//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_process_chip(
-    proc_build_smp_proc_chip* i_proc_chip,
-    proc_build_smp_chip& io_smp_chip)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint8_t nv_present;
-    uint8_t dual_capp_present;
-    uint8_t pcie_enabled;
-    uint8_t nx_enabled;
-    uint8_t x_enabled;
-    uint8_t a_enabled;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_process_chip: Start");
-
-    do
-    {
-        // set HWP input pointer
-        io_smp_chip.chip = i_proc_chip;
-
-        // display target information for this chip
-        FAPI_DBG("proc_build_smp_process_chip: Target: %s",
-                 io_smp_chip.chip->this_chip.toEcmdString());
-
-        // get NV link presence attribute
-        FAPI_DBG("proc_build_smp_process_chip: Querying NV chiplet/link feature attribute");
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NV_PRESENT,
-                           &(io_smp_chip.chip->this_chip),
-                           nv_present);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_CHIP_EC_FEATURE_NV_PRESENT");
-            break;
-        }
-        io_smp_chip.nv_present = (nv_present != 0);
-
-        // get dual CAPP presence attribute
-        FAPI_DBG("proc_build_smp_process_chip: Querying dual CAPP feature attribute");
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT,
-                           &(io_smp_chip.chip->this_chip),
-                           dual_capp_present);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT");
-            break;
-        }
-        io_smp_chip.dual_capp_present = (dual_capp_present != 0);
-
-        // get PCIe PHB configuration
-        FAPI_DBG("proc_build_smp_process_chip: Querying PCIe PHB configuration");
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
-                           &(io_smp_chip.chip->this_chip),
-                           io_smp_chip.num_phb);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_PCIE_NUM_PHB");
-            break;
-        }
-
-        // get PCIe/DSMP mux attributes
-        FAPI_DBG("proc_build_smp_process_chip: Querying PCIe/DSMP mux attribute");
-        rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip),
-                                                  io_smp_chip.pcie_not_f_link);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_pcie_dsmp_mux_attrs");
-            break;
-        }
-
-        // get node ID attribute
-        FAPI_DBG("proc_build_smp_process_chip: Querying node ID attribute");
-        rc = proc_fab_smp_get_node_id_attr(&(io_smp_chip.chip->this_chip),
-                                           io_smp_chip.node_id);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_node_id_attr");
-            break;
-        }
-
-        // get chip ID attribute
-        FAPI_DBG("proc_build_smp_process_chip: Querying chip ID attribute");
-        rc = proc_fab_smp_get_chip_id_attr(&(io_smp_chip.chip->this_chip),
-                                           io_smp_chip.chip_id);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error from proc_fab_smp_get_chip_id_attr");
-            break;
-        }
-
-        // query NX partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE,
-                           &(io_smp_chip.chip->this_chip),
-                           nx_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_NX_ENABLE");
-            break;
-        }
-
-        // query X partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE,
-                           &(io_smp_chip.chip->this_chip),
-                           x_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_X_ENABLE");
-            break;
-        }
-
-        // query A partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
-                           &(io_smp_chip.chip->this_chip),
-                           a_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_A_ENABLE");
-            break;
-        }
-
-        // query PCIE partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
-                           &(io_smp_chip.chip->this_chip),
-                           pcie_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_process_chip: Error querying ATTR_PROC_PCIE_ENABLE");
-            break;
-        }
-
-        io_smp_chip.nx_enabled =
-            (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE);
-
-        io_smp_chip.x_enabled =
-            (x_enabled == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE);
-
-        // NV link replaces A & F link support
-        io_smp_chip.a_enabled =
-            ((a_enabled == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE) &&
-             !nv_present);
-
-        io_smp_chip.pcie_enabled =
-            ((pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE) &&
-             !nv_present);
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_process_chip: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set chip master status (node/system) for PB operations
-// parameters: i_first_chip_in_node   => first chip processed in node?
-//             i_op                   => procedure operation phase/mode
-//             io_smp_chip            => structure encapsulating single chip in
-//                                       SMP topology
-//             io_smp                 => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges
-//              are valid,
-//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
-//              error is detected based on chip state and input paramters,
-//          RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation
-//              is specified
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
-//              equivalent,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_master_config(
-    const bool i_first_chip_in_node,
-    const proc_build_smp_operation i_op,
-    proc_build_smp_chip& io_smp_chip,
-    proc_build_smp_system& io_smp)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase data(64);
-    bool error = false;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_master_config: Start");
-
-    do
-    {
-        // retrieve CURR state of node/system master designation from HW
-        rc = proc_build_smp_get_hotplug_curr_reg(io_smp_chip,
-                                                 true,
-                                                 data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_master_config: Error from proc_build_smp_get_hotplug_curr_reg");
-            break;
-        }
-
-        io_smp_chip.master_chip_sys_curr =
-            (data.isBitSet(PB_HP_MODE_MASTER_CHIP_BIT));
-
-        io_smp_chip.master_chip_node_curr =
-            (data.isBitSet(PB_HP_MODE_CHG_RATE_GP_MASTER_BIT));
-
-         // check/set expectation for CURR/NEXT states based on HW state
-        // as well as input parameters
-        // HBI
-        if (i_op == SMP_ACTIVATE_PHASE1)
-        {
-            // each chip should match the flush state of the fabric logic
-            if (!io_smp_chip.master_chip_sys_curr ||
-                io_smp_chip.master_chip_node_curr)
-            {
-                error = true;
-                break;
-            }
-
-            // set next state
-            io_smp_chip.master_chip_node_next = i_first_chip_in_node;
-        }
-        // FSP
-        else if (i_op == SMP_ACTIVATE_PHASE2)
-        {
-            // set next state
-            io_smp_chip.master_chip_node_next = io_smp_chip.master_chip_node_curr;
-        }
-        // unsupported operation
-        else
-        {
-            FAPI_ERR("proc_build_smp_set_master_config: Unsupported operation presented");
-            const uint8_t& OP = i_op;
-            FAPI_SET_HWP_ERROR(
-                rc,
-                RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR);
-            break;
-        }
-
-        // mark system master for launching fabric reconfiguration operations
-        // also track which slave fabrics will be quiesced
-        if (io_smp_chip.chip->master_chip_sys_next)
-        {
-            // this chip will not be quiesced, to enable switch AB
-            io_smp_chip.issue_quiesce_next = false;
-
-            // in both activation scenarios, we expect that:
-            //   - only a single chip is designated to be the new master
-            //   - the newly designated master is currently configured
-            //     as a master within the scope of its current enclosing fabric
-            if (!io_smp.master_chip_curr_set &&
-                io_smp_chip.master_chip_sys_curr)
-            {
-                io_smp.master_chip_curr_set = true;
-                io_smp.master_chip_curr_node_id = io_smp_chip.node_id;
-                io_smp.master_chip_curr_chip_id = io_smp_chip.chip_id;
-            }
-            else
-            {
-                error = true;
-                break;
-            }
-        }
-        else
-        {
-            // this chip will not be the new master, but is one now
-            // use it to quisece all chips in its fabric
-            if (io_smp_chip.master_chip_sys_curr)
-            {
-                io_smp_chip.issue_quiesce_next = true;
-            }
-            else
-            {
-                io_smp_chip.issue_quiesce_next = false;
-            }
-        }
-
-    } while(0);
-
-    // error for supported operation
-    if (rc.ok() && error)
-    {
-       FAPI_ERR("proc_build_smp_set_master_config: Node/system master designation error");
-       const fapi::Target& TARGET = io_smp_chip.chip->this_chip;
-       const uint8_t& OP = i_op;
-       const bool& MASTER_CHIP_SYS_CURR = io_smp_chip.master_chip_sys_curr;
-       const bool& MASTER_CHIP_NODE_CURR = io_smp_chip.master_chip_node_curr;
-       const bool& MASTER_CHIP_SYS_NEXT = io_smp_chip.chip->master_chip_sys_next;
-       const bool& MASTER_CHIP_NODE_NEXT = io_smp_chip.master_chip_node_next;
-       const bool& SYS_RECONFIG_MASTER_SET = io_smp.master_chip_curr_set;
-       FAPI_SET_HWP_ERROR(
-           rc,
-           RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR);
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_master_config: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: insert chip structure into proper position within SMP model based
-//           on its fabric node/chip ID
-// parameters: io_smp_chip          => structure encapsulating single chip in
-//                                     SMP topology
-//             i_op                 => procedure operation phase/mode
-//             io_smp               => structure encapsulating full SMP
-// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges
-//              are valid,
-//          RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails,
-//          RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
-//              fabric node/chip IDs are detected,
-//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
-//              is detected based on chip state and input paramters,
-//          RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation
-//              is specified
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
-//              equivalent,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_insert_chip(
-    proc_build_smp_chip& io_smp_chip,
-    const proc_build_smp_operation i_op,
-    proc_build_smp_system& io_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // node/chip ID
-    proc_fab_smp_node_id node_id = io_smp_chip.node_id;
-    proc_fab_smp_chip_id chip_id = io_smp_chip.chip_id;
-    // first chip found in node?
-    bool first_chip_in_node  = false;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_insert_chip: Start");
-
-    do
-    {
-        FAPI_DBG("proc_build_smp_insert_chip: Inserting n%d p%d",
-                 node_id, chip_id);
-
-        // search to see if node structure already exists for the node ID
-        // associated with this chip
-        std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator
-            n_iter;
-        n_iter = io_smp.nodes.find(node_id);
-        // no matching node found, create one
-        if (n_iter == io_smp.nodes.end())
-        {
-            FAPI_DBG("proc_build_smp_insert_chip: No matching node found, inserting new node structure");
-            proc_build_smp_node n;
-            n.node_id = io_smp_chip.node_id;
-            std::pair<
-                std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator,
-                bool> ret;
-            ret = io_smp.nodes.insert(
-                std::pair<proc_fab_smp_node_id, proc_build_smp_node>
-                (node_id, n));
-            n_iter = ret.first;
-            if (!ret.second)
-            {
-                FAPI_ERR("proc_build_smp_insert_chip: Error encountered adding node to SMP");
-                const fapi::Target & TARGET = io_smp_chip.chip->this_chip;
-                const proc_fab_smp_node_id & NODE_ID = node_id;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR);
-                break;
-            }
-            // first chip in node
-            first_chip_in_node = true;
-        }
-
-        // search to see if match exists in this node for the chip ID associated
-        // with this chip
-        std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator
-            p_iter;
-        p_iter = io_smp.nodes[node_id].chips.find(chip_id);
-        // matching chip ID & node ID already found, flag an error
-        if (p_iter != io_smp.nodes[node_id].chips.end())
-        {
-            FAPI_ERR("proc_build_smp_insert_chip: Duplicate fabric node ID / chip ID found");
-            const fapi::Target & TARGET1 = io_smp_chip.chip->this_chip;
-            const fapi::Target & TARGET2 = p_iter->second.chip->this_chip;
-            const proc_fab_smp_node_id & NODE_ID = node_id;
-            const proc_fab_smp_chip_id & CHIP_ID = chip_id;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR);
-            break;
-        }
-
-        // determine node/system master status
-        FAPI_DBG("proc_build_smp_insert_chip: Determining node/system master status");
-        rc = proc_build_smp_set_master_config(first_chip_in_node,
-                                              i_op,
-                                              io_smp_chip,
-                                              io_smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_insert_chip: Error from proc_build_smp_set_master_config");
-            break;
-        }
-
-        // insert chip into SMP
-        io_smp.nodes[node_id].chips[chip_id] = io_smp_chip;
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_insert_chip: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to process all HWP input structures and build
-//           SMP data structure
-// parameters: i_proc_chips => vector of HWP input structures (one entry per
-//                             chip in SMP)
-//             i_op         => procedure operation phase/mode
-//             io_smp       => fully specified structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if all processing is successful,
-//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails,
-//          RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
-//              fabric node/chip IDs are detected,
-//          RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR if input parameters
-//              do not specify a new fabric system master,
-//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
-//              error is detected based on chip state and input paramters,
-//          RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation
-//              is specified
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
-//              equivalent,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          RC_PROC_BUILD_SMP_INVALID_TOPOLOGY if specified fabric topology
-//              is illegal,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_process_chips(
-    std::vector<proc_build_smp_proc_chip>& i_proc_chips,
-    const proc_build_smp_operation i_op,
-    proc_build_smp_system& io_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_process_chips: Start");
-
-    // loop over all chips passed from platform to HWP
-    std::vector<proc_build_smp_proc_chip>::iterator i;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-    io_smp.master_chip_curr_set = false;
-
-    do
-    {
-
-        for (i = i_proc_chips.begin(); i != i_proc_chips.end(); i++)
-        {
-            // process platform provided data in chip argument,
-            // query chip specific attributes
-            proc_build_smp_chip smp_chip;
-            rc = proc_build_smp_process_chip(&(*i),
-                                             smp_chip);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_process_chip");
-                break;
-            }
-
-            // insert chip into SMP data structure given node & chip ID
-            rc = proc_build_smp_insert_chip(smp_chip,
-                                            i_op,
-                                            io_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_insert_chip");
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // ensure that new master was designated
-        if (!io_smp.master_chip_curr_set)
-        {
-            FAPI_ERR("proc_build_smp_process_chips: No system master specified!");
-            const uint8_t& OP = i_op;
-            FAPI_SET_HWP_ERROR(
-                rc,
-                RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR);
-            break;
-        }
-
-        // based on master designation, and operation phase,
-        // determine whether each chip will be quiesced as a result
-        // of switch activity
-        for (n_iter = io_smp.nodes.begin();
-             n_iter != io_smp.nodes.end();
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 p_iter != n_iter->second.chips.end();
-                 p_iter++)
-            {
-                if (((i_op == SMP_ACTIVATE_PHASE1) &&
-                     (p_iter->second.issue_quiesce_next)) ||
-                     ((i_op == SMP_ACTIVATE_PHASE2) &&
-                      (n_iter->first != io_smp.master_chip_curr_node_id)))
-                {
-                    p_iter->second.quiesced_next = true;
-                }
-                else
-                {
-                    p_iter->second.quiesced_next = false;
-                }
-            }
-        }
-
-        // check that fabric topology is logically valid
-        // 1) in a given node, all chips are connected to every other
-        //    chip in the node, by an X bus
-        // 2) each chip is connected to its partner chip (with same chip id)
-        //    in every other node, by an A bus
-
-        // build set of all valid node ids in system
-        FAPI_DBG("proc_build_smp_process_chips: Checking fabric topology");
-        ecmdDataBufferBase node_ids_in_system(PROC_FAB_SMP_NUM_NODE_IDS); 
-        for (n_iter = io_smp.nodes.begin();
-             n_iter != io_smp.nodes.end();
-             n_iter++)
-        {
-            FAPI_DBG("proc_build_smp_process_chips: Adding n%d", n_iter->first);
-            rc_ecmd |= node_ids_in_system.setBit(n_iter->first);
-        }
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_process_chips: Error 0x%x forming system node ID set data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // iterate over all nodes
-        for (n_iter = io_smp.nodes.begin();
-             n_iter != io_smp.nodes.end();
-             n_iter++)
-        {
-            // build set of all valid chip ids in node
-            ecmdDataBufferBase chip_ids_in_node(PROC_FAB_SMP_NUM_CHIP_IDS);
-            for (p_iter = n_iter->second.chips.begin();
-                 p_iter != n_iter->second.chips.end();
-                 p_iter++)
-            {
-                FAPI_DBG("proc_build_smp_process_chips: Adding n%d:p%d",
-                         n_iter->first, p_iter->first);
-                rc_ecmd |= chip_ids_in_node.setBit(p_iter->first);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_build_smp_process_chips: Error 0x%x forming node %d chip ID set data buffer",
-                         rc_ecmd, n_iter->first);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            // iterate over all chips in current node
-            for (p_iter = n_iter->second.chips.begin();
-                 p_iter != n_iter->second.chips.end();
-                 p_iter++)
-            {
-                FAPI_DBG("proc_build_smp_process_chips: Processing links for n%d:p%d",
-                         n_iter->first, p_iter->first);
-                std::vector<fapi::Target *> x_link_targets;
-                x_link_targets.push_back(&(p_iter->second.chip->x0_chip));
-                x_link_targets.push_back(&(p_iter->second.chip->x1_chip));
-                x_link_targets.push_back(&(p_iter->second.chip->x2_chip));
-                x_link_targets.push_back(&(p_iter->second.chip->x3_chip));
-
-                std::vector<fapi::Target *> a_link_targets;
-                a_link_targets.push_back(&(p_iter->second.chip->a0_chip));
-                a_link_targets.push_back(&(p_iter->second.chip->a1_chip));
-                a_link_targets.push_back(&(p_iter->second.chip->a2_chip));
-
-                // process X-connected chips
-                ecmdDataBufferBase x_connected_chip_ids(PROC_FAB_SMP_NUM_CHIP_IDS);
-                for (std::vector<fapi::Target*>::iterator l = x_link_targets.begin();
-                     l != x_link_targets.end();
-                     l++)
-                {
-                    bool link_is_enabled;
-                    proc_fab_smp_node_id dest_node_id;
-                    proc_fab_smp_chip_id dest_chip_id;
-                    rc = proc_build_smp_query_link_state(p_iter->second,
-                                                         (l - x_link_targets.begin()),
-                                                         *l,
-                                                         link_is_enabled,
-                                                         dest_node_id,
-                                                         dest_chip_id);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_query_link_state (X)");
-                        break;
-                    }
-
-                    if (link_is_enabled)
-                    {
-                        rc_ecmd |= x_connected_chip_ids.writeBit(
-                            (uint8_t) dest_chip_id, 
-                            ((((uint8_t) dest_node_id) == n_iter->first)?(1):(0)));
-                        if (rc_ecmd)
-                        {
-                            FAPI_ERR("proc_build_smp_process_chips: Error 0x%x writing n%d:p%d X connected chip ID set data buffer",
-                                     rc_ecmd, n_iter->first, p_iter->first);
-                            rc.setEcmdError(rc_ecmd);
-                            break;
-                        }
-
-                        FAPI_DBG("proc_build_smp_process_chips: n%d:p%d X%zd -> n%d:p%d",
-                                 n_iter->first, p_iter->first, (l - x_link_targets.begin()),
-                                 dest_node_id, dest_chip_id);
-                    }
-                }
-                if (!rc.ok())
-                {
-                    break;
-                }
-
-                // process A-connected chips
-                ecmdDataBufferBase a_connected_node_ids(PROC_FAB_SMP_NUM_NODE_IDS);
-                for (std::vector<fapi::Target*>::iterator l = a_link_targets.begin();
-                     l != a_link_targets.end();
-                     l++)
-                {
-                    bool link_is_enabled;
-                    proc_fab_smp_node_id dest_node_id;
-                    proc_fab_smp_chip_id dest_chip_id;
-                    rc = proc_build_smp_query_link_state(p_iter->second,
-                                                         (l - a_link_targets.begin()),
-                                                         *l,
-                                                         link_is_enabled,
-                                                         dest_node_id,
-                                                         dest_chip_id);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_process_chips: Error from proc_build_smp_query_link_state (A)");
-                        break;
-                    }
-
-                    if (link_is_enabled)
-                    {
-                        rc_ecmd |= a_connected_node_ids.writeBit(
-                            (uint8_t) dest_node_id,
-                            ((((uint8_t) dest_chip_id) == p_iter->first)?(1):(0)));
-                        if (rc_ecmd)
-                        {
-                            FAPI_ERR("proc_build_smp_process_chips: Error 0x%x writing n%d:p%d A connected node ID set data buffer",
-                                     rc_ecmd, n_iter->first, p_iter->first);
-                            rc.setEcmdError(rc_ecmd);
-                            break;
-                        }
-
-                        FAPI_DBG("proc_build_smp_process_chips: n%d:p%d A%zd -> n%d:p%d",
-                                 n_iter->first, p_iter->first, (l - a_link_targets.begin()),
-                                 dest_node_id, dest_chip_id);
-                    }
-                }
-                if (!rc.ok())
-                {
-                    break;
-                }
-
-                // add IDs associated with current chip, to make direct set comparison easy
-                FAPI_DBG("proc_build_smp_process_chips: Checking connectivity for n%d:p%d",
-                         n_iter->first, p_iter->first);
-                rc_ecmd |= a_connected_node_ids.setBit(n_iter->first);
-                rc_ecmd |= x_connected_chip_ids.setBit(p_iter->first);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("proc_build_smp_process_chips: Error 0x%x writing n%d:p%d connected ID set data buffer (self)",
-                             rc_ecmd, n_iter->first, p_iter->first);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-
-                // compare ID sets, exit if they don't match
-                bool internode_set_match = (node_ids_in_system == a_connected_node_ids);
-                bool intranode_set_match = (chip_ids_in_node == x_connected_chip_ids);
-                if (!internode_set_match ||
-                    !intranode_set_match)
-                {
-                    FAPI_ERR("proc_build_smp_process_chips: Invalid fabric topology detected!");
-                    if (!intranode_set_match)
-                    {
-                        FAPI_ERR("proc_build_smp_process_chips: Target %s is not fully connected (X) to all other chips in its node",
-                                 p_iter->second.chip->this_chip.toEcmdString());
-                    }
-                    if (!internode_set_match)
-                    {
-                        FAPI_ERR("proc_build_smp_process_chips: Target %s is not fully connected (A) to all other nodes",
-                                 p_iter->second.chip->this_chip.toEcmdString());
-                    }
-
-                    const fapi::Target& TARGET = p_iter->second.chip->this_chip;
-                    const bool& A_CONNECTIONS_OK = internode_set_match;
-                    const ecmdDataBufferBase& A_CONNECTED_NODE_IDS = a_connected_node_ids;
-                    const bool& X_CONNECTIONS_OK = intranode_set_match;
-                    const ecmdDataBufferBase& X_CONNECTED_CHIP_IDS = x_connected_chip_ids;
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_INVALID_TOPOLOGY);
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }        
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_process_chips: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: proc_setup_bars HWP entry point
-//           NOTE: see comments above function prototype in header
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp(
-    std::vector<proc_build_smp_proc_chip> & i_proc_chips,
-    const proc_build_smp_operation i_op)
-{
-    fapi::ReturnCode rc;
-    proc_build_smp_system smp;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp: Start");
-
-    do
-    {
-        // query system specific attributes
-        rc = proc_build_smp_process_system(smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp: Error from proc_build_smp_process_system");
-            break;
-        }
-
-        // process HWP input vector of chip structures
-        rc = proc_build_smp_process_chips(i_proc_chips, i_op, smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp: Error from proc_build_smp_process_chips");
-            break;
-        }
-
-        // initialize fabric configuration
-        if (i_op == SMP_ACTIVATE_PHASE1)
-        {
-            // program nest epsilon attributes/registers
-            rc = proc_build_smp_set_epsilons(smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_epsilons");
-                break;
-            }
-
-            // set fabric configuration registers (non-hotplug)
-            rc = proc_build_smp_set_fbc_nohp(smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_nohp");
-                break;
-            }
-
-            // set fabric configuration registers (hotplug, switch CD set)
-            rc = proc_build_smp_set_fbc_cd(smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_cd");
-                break;
-            }
-        }
-
-        // set fabric trace configuration registers (non-hotplug)
-        rc = proc_build_smp_set_fbc_nohp_trace(smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_nohp_trace");
-            break;
-        }
-
-        // activate SMP
-        // set fabric configuration registers (hotplug, switch AB set)
-        rc = proc_build_smp_set_fbc_ab(smp, i_op);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp: Error from proc_build_smp_set_fbc_ab");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
deleted file mode 100644
index c06efa782..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H
+++ /dev/null
@@ -1,366 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp.H,v 1.16 2014/11/18 17:41:03 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp.H
-// *! DESCRIPTION : Perform fabric configuration (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *! Perform fabric SMP build/reconfiguration operations.
-// *!
-// *! Platform Notes:
-// *!     This HWP has multiple IPL use cases.  In all all cases the HWP input
-// *!     is expected to contain an entry for each chip within the scope of
-// *!     the new SMP to be constructed (with valid information for all
-// *!     active links that are fully contained within the new SMP).
-// *!
-// *!     The proc_build_smp_operation HWP input defines the desired
-// *!     reconfiguration option to be performed:
-// *!
-// *!         SMP_ACTIVATE_PHASE1 (HBI):
-// *!             o init epsilon registers,
-// *!             o program FBC configuration dependent registers (switch C/D)
-// *!             o join all single chip 'island' fabrics into drawer level
-// *!               SMP (switch A/B)
-// *!
-// *!         SMP_ACTIVATE_PHASE2 (FSP):
-// *!             o join collection of drawer level SMPs into full system SMP
-// *!               (switch A/B)
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BUILD_SMP_H_
-#define _PROC_BUILD_SMP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <vector>
-#include <map>
-#include <fapi.H>
-#include <proc_fab_smp.H>
-#include <p8_scom_addresses.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// HWP argument, define supported execution modes
-enum proc_build_smp_operation
-{
-    // call from HBI (init epsilons, switch C/D + A/B)
-    // used to initialize scope of HBI drawer
-    SMP_ACTIVATE_PHASE1 = 1,
-    // call from FSP (only switch A/B)
-    // used to stitch drawers/CCM
-    SMP_ACTIVATE_PHASE2 = 2
-};
-
-// HWP argument structure defining properties of this chip
-// and links which should be considered
-struct proc_build_smp_proc_chip
-{
-    // target for this chip
-    fapi::Target this_chip;
-    // set if this chip should be designated fabric
-    // master post-reconfiguration
-    // NOTE: this chip must currently be designated a
-    //       master in its enclosing fabric
-    //       PHASE1/HBI: any chip
-    //       PHASE2/FSP: any current drawer master
-    bool master_chip_sys_next;
-
-    // chiplet targets connected to A links
-    fapi::Target a0_chip;
-    fapi::Target a1_chip;
-    fapi::Target a2_chip;
-
-    // chiplet targets connected to X links
-    fapi::Target x0_chip;
-    fapi::Target x1_chip;
-    fapi::Target x2_chip;
-    fapi::Target x3_chip;
-
-    // parameters defining F link connected SMPs
-    bool enable_f0;
-    proc_fab_smp_node_id f0_node_id;
-    bool enable_f1;
-    proc_fab_smp_node_id f1_node_id;
-};
-
-
-// structure to represent fabric connectivty & properites for a single chip
-// in the SMP topology
-struct proc_build_smp_chip
-{
-    // associated HWP input structure
-    proc_build_smp_proc_chip* chip;
-
-    // chip properties/attributes:
-    bool nv_present;
-    bool dual_capp_present;
-    uint8_t num_phb;
-    // fabric chip/node ID
-    proc_fab_smp_chip_id chip_id;
-    proc_fab_smp_node_id node_id;
-    // partial good attributes
-    bool nx_enabled;
-    bool x_enabled;
-    bool a_enabled;
-    bool pcie_enabled;
-    // node/system master designation (curr)
-    bool master_chip_node_curr;
-    bool master_chip_sys_curr;
-    // node/system master designation (next)
-    bool master_chip_node_next;
-    bool issue_quiesce_next;
-    bool quiesced_next;
-    // select for PCIe/DSMP mux (one per link)
-    bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS];
-};
-
-// structure to represent properties for a single node in the SMP topology
-struct proc_build_smp_node
-{
-    // chips which reside in this node
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip> chips;
-
-    // node properties/attributes:
-    // fabric node ID
-    proc_fab_smp_node_id node_id;
-};
-
-// structure to encapsulate system epsilon configuration
-struct proc_build_smp_eps_cfg
-{
-    // epsilon configuration inputs
-    bool gb_positive;
-    uint8_t gb_percentage;
-    proc_fab_smp_eps_table_type table_type;
-    // target epsilon values
-    uint32_t r_t0;    // read, tier0 (np)
-    uint32_t r_t1;    // read, tier1 (gp)
-    uint32_t r_t2;    // read, tier2 (sp)
-    uint32_t r_f;     // read, foreign (f)
-    uint32_t w_t2;    // write, tier2 (sp)
-    uint32_t w_f;     // write, foreign (f)
-    uint32_t p;       // pre
-};
-
-// core/nest frequency ratio cutpoints (epsilon)
-enum proc_build_smp_core_ratio
-{
-    PROC_BUILD_SMP_CORE_RATIO_8_8 = 0,
-    PROC_BUILD_SMP_CORE_RATIO_7_8 = 1,
-    PROC_BUILD_SMP_CORE_RATIO_6_8 = 2,
-    PROC_BUILD_SMP_CORE_RATIO_5_8 = 3,
-    PROC_BUILD_SMP_CORE_RATIO_4_8 = 4,
-    PROC_BUILD_SMP_CORE_RATIO_2_8 = 5
-};
-
-// core floor/nest frequency ratio cutpoints (CPU delay)
-enum proc_build_smp_cpu_delay
-{
-    PROC_BUILD_SMP_CPU_DELAY_4800_2400 = 0,
-    PROC_BUILD_SMP_CPU_DELAY_4431_2400 = 1,
-    PROC_BUILD_SMP_CPU_DELAY_4114_2400 = 2,
-    PROC_BUILD_SMP_CPU_DELAY_3840_2400 = 3,
-    PROC_BUILD_SMP_CPU_DELAY_3600_2400 = 4,
-    PROC_BUILD_SMP_CPU_DELAY_3338_2400 = 5,
-    PROC_BUILD_SMP_CPU_DELAY_3200_2400 = 6,
-    PROC_BUILD_SMP_CPU_DELAY_3032_2400 = 7,
-    PROC_BUILD_SMP_CPU_DELAY_2880_2400 = 8,
-    PROC_BUILD_SMP_CPU_DELAY_2743_2400 = 9,
-    PROC_BUILD_SMP_CPU_DELAY_2618_2400 = 10,
-    PROC_BUILD_SMP_CPU_DELAY_2504_2400 = 11,
-    PROC_BUILD_SMP_CPU_DELAY_2400_2400 = 12
-};
-
-// structure to represent collection of nodes in SMP topology
-struct proc_build_smp_system
-{
-    // nodes which reside in this SMP
-    std::map<proc_fab_smp_node_id, proc_build_smp_node> nodes;
-    // current system master for the purpose of launching
-    // fabric reconfiguration operations
-    bool master_chip_curr_set;
-    proc_fab_smp_node_id master_chip_curr_node_id;
-    proc_fab_smp_chip_id master_chip_curr_chip_id;
-
-    // system properties/attributes:
-    // system frequencies (MHz):
-    uint32_t freq_pb;
-    uint32_t freq_a;
-    uint32_t freq_x;
-    uint32_t freq_core_floor;
-    uint32_t freq_core_nom;
-    uint32_t freq_core_ceiling;
-    uint32_t freq_pcie;
-    // core/pb frequency ratios
-    proc_build_smp_core_ratio core_floor_ratio;
-    proc_build_smp_core_ratio core_ceiling_ratio;
-    // CPU delay/RCMD highwater settings
-    proc_build_smp_cpu_delay nom_cpu_delay;
-    proc_build_smp_cpu_delay full_cpu_delay;
-
-    // program async boundary crossings to safe mode
-    bool async_safe_mode;
-    // X bus width
-    bool x_bus_8B;
-    // fabric pump mode
-    proc_fab_smp_pump_mode pump_mode;
-    // AVP test modes
-    bool avp_mode;
-    // MCS interleaving configuration
-    bool all_mcs_interleaved;
-    // system epsilon configuration
-    proc_build_smp_eps_cfg eps_cfg;
-};
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_build_smp_FP_t)(std::vector<proc_build_smp_proc_chip>&,
-                       const proc_build_smp_operation);
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// PB shadow register constant definition
-const uint8_t PROC_BUILD_SMP_NUM_SHADOWS = 3;
-
-// core floor/nest frequency ratio cutpoints (CPU delay)
-const uint8_t PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS = 13;
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: perform fabric SMP reconfiguration operations
-// parameters: i_proc_chips => vector of structures defining properties of each
-//                             chip and its connected links
-//             i_op  => enumerated type representing SMP build phase
-//                      (SMP_ACTIVATE_PHASE1 = HBI,
-//                       SMP_ACTIVATE_PHASE2 = FSP)
-// returns: FAPI_RC_SUCCESS if SMP build operation is successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation
-//              parameters are specified,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
-//              for switch operation,
-//          RC_PROC_FAB_SMP_X_BUS_WIDTH_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_PUMP_MODE_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_MCS_INTERLEAVED_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_EPSILON_TABLE_TYPE_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_EPSILON_GB_DIRECTION_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_CORE_FLOOR_FREQ_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          RC_PROC_BUILD_SMP_CORE_FREQ_RANGE_ERR if invalid relationship exists
-//              between ceiling/nominal/floor core frequency attributes,
-//          RC_PROC_BUILD_SMP_CORE_CEILING_FREQ_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          RC_PROC_FAB_SMP_ASYNC_SAFE_MODE_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_NODE_ADD_INTERNAL_ERR if node map insert fails,
-//          RC_PROC_BUILD_SMP_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
-//              fabric node/chip IDs are detected,
-//          RC_PROC_BUILD_SMP_NO_MASTER_SPECIFIED_ERR if input parameters
-//              do not specify a new fabric system master,
-//          RC_PROC_BUILD_SMP_MASTER_DESIGNATION_ERR if node/system master
-//              error is detected based on chip state and input paramters,
-//          RC_PROC_BUILD_SMP_INVALID_OPERATION_ERR if an unsupported operation
-//              is specified
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if HP shadow registers are not
-//              equivalent,
-//          RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR if invalid epsilon
-//              table type/content is detected,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
-//              small/large,
-//          RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR if pacing rate table lookup
-//              is unsuccessful,
-//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
-//              specifies invalid aggregate link setup,
-//          RC_PROC_BUILD_SMP_A_CMD_RATE_ERR if calculated A link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          RC_PROC_BUILD_SMP_INVALID_TOPOLOGY if specified fabric topology
-//              is illegal,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp(
-    std::vector<proc_build_smp_proc_chip> & i_proc_chips,
-    const proc_build_smp_operation i_op);
-
-
-} // extern "C"
-
-#endif // _PROC_BUILD_SMP_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
deleted file mode 100644
index 4a46449d2..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C
+++ /dev/null
@@ -1,1046 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_adu.C,v 1.11 2014/11/18 17:41:03 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_adu.C
-// *! DESCRIPTION : Interface for ADU operations required to support fabric
-// *!               configuration actions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp_adu.H>
-#include <proc_adu_utils.H>
-
-//------------------------------------------------------------------------------
-// Constants
-//------------------------------------------------------------------------------
-
-const uint32_t PROC_BUILD_SMP_MAX_STATUS_POLLS = 5;
-
-const uint32_t PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS = 1;
-const bool PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK = false;
-const uint32_t PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY = 128;
-const uint32_t PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY = 128;
-
-const uint32_t PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS = 5;
-const bool PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK = true;
-const uint32_t PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY = 4096;
-const uint32_t PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY = 512;
-
-// ADU pMISC Mode register field/bit definitions
-const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT = 30;
-const uint32_t ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT = 31;
-
-// FFDC logging on ADU switch fails
-const uint8_t PROC_BUILD_SMP_FFDC_NUM_REGS = 11;
-const uint32_t PROC_BUILD_SMP_FFDC_REGS[PROC_BUILD_SMP_FFDC_NUM_REGS] =
-{
-    PB_MODE_CENT_0x02010C4A,
-    PB_HP_MODE_NEXT_CENT_0x02010C4B,
-    PB_HP_MODE_CURR_CENT_0x02010C4C,
-    PB_HPX_MODE_NEXT_CENT_0x02010C4D,
-    PB_HPX_MODE_CURR_CENT_0x02010C4E,
-    X_GP0_0x04000000,
-    PB_X_MODE_0x04010C0A,
-    A_GP0_0x08000000,
-    ADU_IOS_LINK_EN_0x02020019,
-    PB_A_MODE_0x0801080A,
-    ADU_PMISC_MODE_0x0202000B
-};
-enum proc_build_smp_ffdc_reg_index
-{
-    PB_MODE_CENT_DATA_INDEX = 0,
-    PB_HP_MODE_NEXT_CENT_DATA_INDEX = 1,
-    PB_HP_MODE_CURR_CENT_DATA_INDEX = 2,
-    PB_HPX_MODE_NEXT_CENT_DATA_INDEX = 3,
-    PB_HPX_MODE_CURR_CENT_DATA_INDEX = 4,
-    X_GP0_DATA_INDEX = 5,
-    PB_X_MODE_DATA_INDEX = 6,
-    A_GP0_DATA_INDEX = 7,
-    ADU_IOS_LINK_EN_DATA_INDEX = 8,
-    PB_A_MODE_DATA_INDEX = 9,
-    ADU_PMISC_MODE_DATA_INDEX = 10
-};
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: set action which will occur on fabric pmisc switch command
-// parameters: i_target    => P8 chip target
-//             i_switch_ab => perform switch AB operation?
-//             i_switch_cd => perform switch CD operation?
-// returns: FAPI_RC_SUCCESS if action is configured successfully,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_adu_set_switch_action(
-    const fapi::Target& i_target,
-    const bool i_switch_ab,
-    const bool i_switch_cd)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase pmisc_data(64), pmisc_mask(64);
-
-    FAPI_DBG("proc_build_smp_adu_set_switch_action: Start");
-    do
-    {
-        // build ADU pMisc Mode register content
-        FAPI_DBG("proc_build_smp_adu_set_switch_action: Writing ADU pMisc Mode register");
-        // switch AB bit
-        rc_ecmd |= pmisc_data.writeBit(
-            ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT,
-            i_switch_ab);
-        rc_ecmd |= pmisc_mask.setBit(
-            ADU_PMISC_MODE_ENABLE_PB_SWITCH_AB_BIT);
-        // switch CD bit
-        rc_ecmd |= pmisc_data.writeBit(
-            ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT,
-            i_switch_cd);
-        rc_ecmd |= pmisc_mask.setBit(
-            ADU_PMISC_MODE_ENABLE_PB_SWITCH_CD_BIT);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_adu_set_switch_action: Error 0x%x setting up ADU pMisc Mode register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        // write ADU pMisc Mode register content
-        rc = fapiPutScomUnderMask(i_target,
-                                  ADU_PMISC_MODE_0x0202000B,
-                                  pmisc_data,
-                                  pmisc_mask);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_adu_set_switch_action: fapiPutScomUnderMask error (ADU_PMISC_MODE_0x0202000B)");
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_build_smp_adu_set_switch_action: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: acquire ADU atomic lock to guarantee exclusive use of its
-//           resources
-// parameters: i_target         => P8 chip target
-//             i_adu_lock_tries => number of lock acquisistions to attempt
-//             i_adu_pick_lock  => attempt lock pick if lock acquisition
-//                                 is unsuccessful after i_adu_lock_tries?
-// returns: FAPI_RC_SUCCESS if lock is successfully acquired,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_adu_acquire_lock(
-    const fapi::Target& i_target,
-    const uint32_t& i_adu_lock_tries,
-    const bool& i_adu_pick_lock)
-{
-    fapi::ReturnCode rc;
-    proc_adu_utils_adu_lock_operation lock_op = ADU_LOCK_ACQUIRE;
-
-    FAPI_DBG("proc_build_smp_adu_acquire_lock: Start");
-
-    do
-    {
-        // attempt ADU lock acquisition
-        FAPI_DBG("proc_build_smp_adu_acquire_lock: Calling library to acquire ADU lock");
-        rc = proc_adu_utils_manage_adu_lock(i_target,
-                                            lock_op,
-                                            i_adu_lock_tries);
-
-        // return code specifically indicates lock acquisition was not
-        // successful because ADU lock is held by another entity
-        if (rc == fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED)
-        {
-            FAPI_INF("proc_build_smp_adu_acquire_lock: Unable to acquire ADU lock after %d tries",
-                     i_adu_lock_tries);
-
-            // give up if lock pick is not specified
-            if (!i_adu_pick_lock)
-            {
-                FAPI_ERR("proc_build_smp_adu_acquire_lock: ADU lock acquisition unsuccessful, giving up without attempting to pick lock");
-                break;
-            }
-            // otherwise make single lock pick attempt
-            else
-            {
-                FAPI_DBG("proc_build_smp_adu_acquire_lock: Calling library to pick ADU lock");
-                lock_op = ADU_LOCK_FORCE_ACQUIRE;
-                rc = proc_adu_utils_manage_adu_lock(i_target,
-                                                    lock_op,
-                                                    1);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_adu_acquire_lock: Error from proc_adu_utils_manage_adu_lock");
-                    break;
-                }
-            }
-        }
-        // flag error on any other return code that is not OK
-        else if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_adu_acquire_lock: Error from proc_adu_utils_manage_adu_lock");
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_build_smp_adu_acquire_lock: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: reset ADU state machines and status register
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target => P8 chip target
-// returns: FAPI_RC_SUCCESS if fabric is not stopped,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_adu_reset(
-    const fapi::Target& i_target)
-{
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_build_smp_adu_reset: Start");
-    do
-    {
-        // call ADU library function
-        FAPI_DBG("proc_build_smp_adu_reset: Calling library to reset ADU");
-        rc = proc_adu_utils_reset_adu(i_target);
-        if (!rc.ok()) {
-            FAPI_ERR("proc_build_smp_adu_reset: Error from proc_adu_utils_reset_adu");
-        }
-    } while(0);
-
-    FAPI_DBG("proc_build_smp_adu_reset: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: release ADU atomic lock
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target           => P8 chip target
-//             i_adu_unlock_tries => number of lock releases to attempt
-// returns: FAPI_RC_SUCCESS if lock is successfully released,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_adu_release_lock(
-    const fapi::Target& i_target,
-    const uint32_t& i_adu_unlock_tries)
-{
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_build_smp_adu_release_lock: Start");
-
-    do
-    {
-        // attempt ADU lock acquisition
-        FAPI_DBG("proc_build_smp_adu_release_lock: Calling library to release ADU lock");
-        rc = proc_adu_utils_manage_adu_lock(i_target,
-                                            ADU_LOCK_RELEASE,
-                                            i_adu_unlock_tries);
-
-        // return code specifically indicates lock release was not
-        // successful because ADU lock is held by another entity
-        if (rc == fapi::FAPI_RC_PLAT_ERR_ADU_LOCKED)
-        {
-            FAPI_INF("proc_build_smp_adu_release_lock: Unable to release ADU lock after %d tries",
-                     i_adu_unlock_tries);
-            FAPI_ERR("proc_build_smp_adu_release_lock: ADU lock release unsuccessful");
-            break;
-        }
-        // flag error on any other return code that is not OK
-        else if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_adu_release_lock: Error from proc_adu_utils_manage_adu_lock");
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_build_smp_adu_release_lock: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: check ADU status matches expected state/value
-//           NOTE: intended to be run while holding ADU lock
-// parameters: i_target           => P8 chip target
-//             i_smp              => structure encapsulating SMP topology
-//             i_dump_all_targets => dump FFDC for all targets in SMP?
-//                                   true=yes, false=no, only for i_target
-// returns: FAPI_RC_SUCCESS if status matches expected value,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if status mismatches,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_adu_check_status(
-    const fapi::Target& i_target,
-    proc_build_smp_system& i_smp,
-    const bool i_dump_all_targets)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    proc_adu_utils_adu_status status;
-    bool match = false;
-    uint8_t num_polls = 0;
-
-    FAPI_DBG("proc_build_smp_adu_check_status: Start");
-    do
-    {
-        // retreive actual status value
-        while (num_polls < PROC_BUILD_SMP_MAX_STATUS_POLLS)
-        {
-            FAPI_DBG("proc_build_smp_adu_check_status: Calling library to read ADU status (poll %d)",
-                     num_polls+1);
-            rc = proc_adu_utils_get_adu_status(i_target,
-                                               status);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_adu_check_status: Error from proc_adu_utils_get_adu_status");
-                break;
-            }
-
-            // status reported as busy, poll again
-            if (status.busy)
-            {
-                num_polls++;
-            }
-            // not busy, check for expected status
-            else
-            {
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // check status bits versus expected pattern
-        match =
-            ((status.busy == ADU_STATUS_BIT_CLEAR) &&
-             (status.wait_cmd_arbit == ADU_STATUS_BIT_CLEAR) &&
-             (status.addr_done == ADU_STATUS_BIT_SET) &&
-             (status.data_done == ADU_STATUS_BIT_CLEAR) &&
-             (status.wait_resp == ADU_STATUS_BIT_CLEAR) &&
-             (status.overrun_err == ADU_STATUS_BIT_CLEAR) &&
-             (status.autoinc_err == ADU_STATUS_BIT_CLEAR) &&
-             (status.command_err == ADU_STATUS_BIT_CLEAR) &&
-             (status.address_err == ADU_STATUS_BIT_CLEAR) &&
-             (status.command_hang_err == ADU_STATUS_BIT_CLEAR) &&
-             (status.data_hang_err == ADU_STATUS_BIT_CLEAR));
-        if (!match)
-        {
-            FAPI_ERR("proc_adu_utils_check_adu_status: Status mismatch detected");
-            FAPI_ERR("proc_adu_utils_check_adu_status: ADU Status bits:");
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_BUSY           = %d",
-                     (status.busy == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_WAIT_CMD_ARBIT = %d",
-                     (status.wait_cmd_arbit == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_ADDR_DONE      = %d",
-                     (status.addr_done == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_DATA_DONE      = %d",
-                     (status.data_done == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_WAIT_RESP      = %d",
-                     (status.wait_resp == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status: ADU Error bits:");
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_OVERRUN_ERROR        = %d",
-                     (status.overrun_err == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_AUTOINC_ERROR        = %d",
-                     (status.autoinc_err == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_COMMAND_ERROR        = %d",
-                     (status.command_err == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_ADDRESS_ERROR        = %d",
-                     (status.address_err == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_COMMAND_HANG_ERROR   = %d",
-                     (status.command_hang_err == ADU_STATUS_BIT_SET)?(1)
-                                                                        :(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_DATA_HANG_ERROR      = %d",
-                     (status.data_hang_err == ADU_STATUS_BIT_SET)?(1):(0));
-            FAPI_ERR("proc_adu_utils_check_adu_status:   FBC_ALTD_PBINIT_MISSING_ERROR = %d",
-                     (status.pbinit_missing == ADU_STATUS_BIT_SET)?(1):(0));
-
-            // dump FFDC
-            // there is no clean way to represent the collection in XML (given an arbitrary number of chips),
-            // so collect manually and store into data buffers which can be post-processed from the error log
-            std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-            std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-            std::vector<fapi::Target*> targets_to_collect;
-            std::vector<bool> nv_present;
-            ecmdDataBufferBase scom_data(64);
-            ecmdDataBufferBase chip_ids;
-            ecmdDataBufferBase ffdc_reg_data[PROC_BUILD_SMP_FFDC_NUM_REGS];
-            bool ffdc_scom_error = false;
-
-            // determine set of chips to collect
-            for (n_iter = i_smp.nodes.begin();
-                 n_iter != i_smp.nodes.end();
-                 n_iter++)
-            {
-                for (p_iter = n_iter->second.chips.begin();
-                     p_iter != n_iter->second.chips.end();
-                     p_iter++)
-                {
-                    if (i_dump_all_targets ||
-                        (p_iter->second.chip->this_chip == i_target))
-                    {
-                        nv_present.push_back(p_iter->second.nv_present);
-                        targets_to_collect.push_back(&(p_iter->second.chip->this_chip));
-                    }
-                }
-            }
-
-            // size FFDC buffers
-            rc_ecmd |= chip_ids.setByteLength(targets_to_collect.size());
-            for (uint8_t i = 0; i < PROC_BUILD_SMP_FFDC_NUM_REGS; i++)
-            {
-                rc_ecmd |= ffdc_reg_data[i].setDoubleWordLength(targets_to_collect.size());
-            }
-
-            // extract FFDC data
-            std::vector<bool>::iterator n = nv_present.begin();
-            for (std::vector<fapi::Target*>::iterator t = targets_to_collect.begin();
-                 t != targets_to_collect.end();
-                 t++, n++)
-            {
-                // log node/chip ID
-                for (n_iter = i_smp.nodes.begin();
-                     n_iter != i_smp.nodes.end();
-                     n_iter++)
-                {
-                    for (p_iter = n_iter->second.chips.begin();
-                         p_iter != n_iter->second.chips.end();
-                         p_iter++)
-                    {
-                        if ((&(p_iter->second.chip->this_chip)) == *t)
-                        {
-                            uint8_t id = ((n_iter->first & 0x3) << 4) |
-                                (p_iter->first & 0x3);
-
-                            rc_ecmd |= chip_ids.setByte(t - targets_to_collect.begin(), id);
-                        }
-                    }
-                }
-
-                // collect SCOM data
-                for (uint8_t i = 0; i < PROC_BUILD_SMP_FFDC_NUM_REGS; i++)
-                {
-                    // skip A / F link registers if NV link logic is present
-                    if ((*n) &&
-                        ((i == static_cast<uint8_t>(A_GP0_DATA_INDEX)) ||
-                         (i == static_cast<uint8_t>(ADU_IOS_LINK_EN_DATA_INDEX)) ||
-                         (i == static_cast<uint8_t>(PB_A_MODE_DATA_INDEX))))
-                    {
-                        rc_ecmd |= scom_data.flushTo1();
-                    }
-                    else
-                    {
-                        rc = fapiGetScom(*(*t), PROC_BUILD_SMP_FFDC_REGS[i], scom_data);
-                        if (!rc.ok())
-                        {
-                            ffdc_scom_error = true;
-                        }
-                    }
-
-                    rc_ecmd |= scom_data.extractPreserve(
-                        ffdc_reg_data[i],
-                        0, 64,
-                        64*(t - targets_to_collect.begin()));
-                }
-            }
-
-            const fapi::Target& TARGET = i_target;
-            const proc_adu_utils_adu_status& ADU_STATUS_DATA = status;
-            const uint8_t& ADU_NUM_POLLS = num_polls;
-            const uint8_t& NUM_CHIPS = targets_to_collect.size();
-            const uint8_t& FFDC_VALID = !rc_ecmd && !ffdc_scom_error;
-            const ecmdDataBufferBase& CHIP_IDS = chip_ids;
-            const ecmdDataBufferBase& PB_MODE_CENT_DATA = ffdc_reg_data[0];
-            const ecmdDataBufferBase& PB_HP_MODE_NEXT_CENT_DATA = ffdc_reg_data[1];
-            const ecmdDataBufferBase& PB_HP_MODE_CURR_CENT_DATA = ffdc_reg_data[2];
-            const ecmdDataBufferBase& PB_HPX_MODE_NEXT_CENT_DATA = ffdc_reg_data[3];
-            const ecmdDataBufferBase& PB_HPX_MODE_CURR_CENT_DATA = ffdc_reg_data[4];
-            const ecmdDataBufferBase& X_GP0_DATA = ffdc_reg_data[5];
-            const ecmdDataBufferBase& PB_X_MODE_DATA = ffdc_reg_data[6];
-            const ecmdDataBufferBase& A_GP0_DATA = ffdc_reg_data[7];
-            const ecmdDataBufferBase& ADU_IOS_LINK_EN_DATA = ffdc_reg_data[8];
-            const ecmdDataBufferBase& PB_A_MODE_DATA = ffdc_reg_data[9];
-            const ecmdDataBufferBase& ADU_PMISC_MODE_DATA = ffdc_reg_data[10];
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH);
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_build_smp_adu_check_status: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_switch_cd(
-    proc_build_smp_chip& i_smp_chip,
-    proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    // ADU status/control information
-    proc_adu_utils_fbc_op adu_ctl;
-    proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl;
-    bool adu_is_dirty = false;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_switch_cd: Start");
-
-    do
-    {
-        FAPI_DBG("proc_build_smp_switch_cd: Acquiring lock for ADU");
-        // acquire ADU lock
-        // only required to obtain lock for this chip, as this function will
-        // only be executed when fabric is configured as single chip island
-        rc = proc_build_smp_adu_acquire_lock(
-            i_smp_chip.chip->this_chip,
-            PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS,
-            PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_acquire_lock");
-            break;
-        }
-        // NOTE: lock is now held, if an operation fails from this point
-        //       to the end of the procedure:
-        //       o attempt to cleanup/release lock (so that procedure does not
-        //         leave the ADU in a locked state)
-        //       o return rc of original fail
-        adu_is_dirty = true;
-
-        // reset ADU
-        rc = proc_build_smp_adu_reset(i_smp_chip.chip->this_chip);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_reset");
-            break;
-        }
-        FAPI_DBG("proc_build_smp_switch_cd: ADU lock held");
-
-        // condition for switch CD operation
-        rc = proc_build_smp_adu_set_switch_action(
-            i_smp_chip.chip->this_chip,
-            false,
-            true);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_set_switch_action (set)");
-            break;
-        }
-
-        // build ADU control structure
-        adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC;
-        adu_ctl.tsize = ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB;
-        adu_ctl.address = 0x0ULL;
-        adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM;
-        adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH;
-        adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY;
-        adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE;
-        adu_ctl.use_autoinc = false;
-
-        adu_hp_ctl.do_tm_quiesce = true;
-        adu_hp_ctl.do_pre_quiesce = true;
-        adu_hp_ctl.do_post_init = true;
-        adu_hp_ctl.post_quiesce_delay = PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY;
-        adu_hp_ctl.pre_init_delay = PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY;
-
-        // launch command
-        FAPI_DBG("proc_build_smp_switch_cd: Issuing switch CD from %s",
-                 i_smp_chip.chip->this_chip.toEcmdString());
-        rc = proc_adu_utils_send_fbc_op(i_smp_chip.chip->this_chip,
-                                        adu_ctl,
-                                        true,
-                                        adu_hp_ctl);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_adu_utils_send_fbc_op");
-            break;
-        }
-
-        // check status
-        rc = proc_build_smp_adu_check_status(i_smp_chip.chip->this_chip, i_smp, false);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_check_status");
-            break;
-        }
-
-        // reset switch controls
-        rc = proc_build_smp_adu_set_switch_action(
-            i_smp_chip.chip->this_chip,
-            false,
-            false);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_set_switch_action (reset)");
-            break;
-        }
-
-        // release ADU lock
-        FAPI_DBG("proc_build_smp_switch_cd: Releasing lock for ADU");
-        rc = proc_build_smp_adu_release_lock(
-            i_smp_chip.chip->this_chip,
-            PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_cd: Error from proc_build_smp_adu_release_lock");
-            break;
-        }
-        FAPI_DBG("proc_build_smp_switch_cd: ADU lock released");
-    } while(0);
-
-    // if error has occurred and ADU is dirty,
-    // attempt to reset ADU and free lock (propogate rc of original fail)
-    if (!rc.ok() && adu_is_dirty)
-    {
-        FAPI_INF("proc_build_smp_switch_cd: Attempting to reset/free lock on ADU");
-        (void) proc_build_smp_adu_set_switch_action(i_smp_chip.chip->this_chip, false, false);
-        (void) proc_build_smp_adu_reset(i_smp_chip.chip->this_chip);
-        (void) proc_build_smp_adu_release_lock(i_smp_chip.chip->this_chip, 1);
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_switch_cd: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_quiesce_pb(
-    proc_build_smp_system& i_smp,
-    const proc_build_smp_operation i_op)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-    std::vector<proc_build_smp_chip*>::iterator quiesce_iter;
-    // ADU status/control information
-    proc_adu_utils_fbc_op adu_ctl;
-    proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl;
-    bool adu_is_dirty = false;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_quiesce_pb: Start");
-
-    do
-    {
-        FAPI_DBG("proc_build_smp_quiesce_pb: Acquiring lock for all ADU units in fabric");
-        // loop through all chips, lock & reset ADU
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                // acquire ADU lock
-                rc = proc_build_smp_adu_acquire_lock(
-                    p_iter->second.chip->this_chip,
-                    ((i_op == SMP_ACTIVATE_PHASE1)?
-                     (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS):
-                     (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS)),
-                    ((i_op == SMP_ACTIVATE_PHASE1)?
-                     (PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK):
-                     (PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK)));
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_acquire_lock");
-                    break;
-                }
-                // NOTE: lock is now held, if an operation fails from this point
-                //       to the end of the procedure:
-                //       o attempt to cleanup/release lock (so that procedure does not
-                //         leave the ADU in a locked state)
-                //       o return rc of original fail
-                adu_is_dirty = true;
-
-                // reset ADU
-                rc = proc_build_smp_adu_reset(p_iter->second.chip->this_chip);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_reset");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-        FAPI_DBG("proc_build_smp_quiesce_pb: All ADU locks held");
-
-        // build ADU control structure
-        adu_ctl.ttype = ADU_FBC_OP_TTYPE_PBOP;
-        adu_ctl.tsize = ADU_FBC_OP_TSIZE_PBOP_DIS_ALL_FP_EN;
-        adu_ctl.address = 0x0ULL;
-        adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM;
-        adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH;
-        adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY;
-        adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE;
-        adu_ctl.use_autoinc = false;
-
-        adu_hp_ctl.do_tm_quiesce = true;
-        adu_hp_ctl.do_pre_quiesce = false;
-        adu_hp_ctl.do_post_init = false;
-        adu_hp_ctl.post_quiesce_delay = 0x0;
-        adu_hp_ctl.pre_init_delay = 0x0;
-
-        // issue quiesce on all specified chips
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                if (p_iter->second.issue_quiesce_next)
-                {
-                    FAPI_DBG("proc_build_smp_quiesce_pb: Issuing quiesce from %s",
-                             p_iter->second.chip->this_chip.toEcmdString());
-                    // launch command
-                    rc = proc_adu_utils_send_fbc_op(p_iter->second.chip->this_chip,
-                                                    adu_ctl,
-                                                    true,
-                                                    adu_hp_ctl);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_adu_utils_send_fbc_op");
-                        break;
-                    }
-
-                    // check status
-                    rc = proc_build_smp_adu_check_status(
-                        p_iter->second.chip->this_chip,
-                        i_smp,
-                        (i_op == SMP_ACTIVATE_PHASE2));
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_check_status");
-                        break;
-                    }
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_quiesce_pb: Releasing lock for all ADU units in drawer");
-        // loop through all chips, unlock ADUs
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                // release ADU lock
-                rc = proc_build_smp_adu_release_lock(
-                    p_iter->second.chip->this_chip,
-                    ((i_op == SMP_ACTIVATE_PHASE1)?
-                     (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS):
-                     (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS)));
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_quiesce_pb: Error from proc_build_smp_adu_release_lock");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-        FAPI_DBG("proc_build_smp_quiesce_pb: All ADU locks released");
-    } while(0);
-
-
-    // if error has occurred and any ADU is dirty,
-    // attempt to reset all ADUs and free locks (propogate rc of original fail)
-    if (!rc.ok() && adu_is_dirty)
-    {
-        FAPI_INF("proc_build_smp_quiesce_pb: Attempting to reset/free lock on all ADUs");
-        // loop through all chips, unlock ADUs
-        for (n_iter = i_smp.nodes.begin();
-             n_iter != i_smp.nodes.end();
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 p_iter != n_iter->second.chips.end();
-                 p_iter++)
-            {
-                (void) proc_build_smp_adu_reset(p_iter->second.chip->this_chip);
-                (void) proc_build_smp_adu_release_lock(
-                    p_iter->second.chip->this_chip,
-                    1);
-            }
-        }
-    }
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_quiesce_pb: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_switch_ab(
-    proc_build_smp_system& i_smp,
-    const proc_build_smp_operation i_op)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-    // ADU status/control information
-    proc_adu_utils_fbc_op adu_ctl;
-    proc_adu_utils_fbc_op_hp_ctl adu_hp_ctl;
-    bool adu_is_dirty = false;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_switch_ab: Start");
-
-    do
-    {
-        FAPI_DBG("proc_build_smp_switch_ab: Acquiring lock for all ADU units in fabric");
-        // loop through all chips, lock & reset ADU
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                // acquire ADU lock
-                rc = proc_build_smp_adu_acquire_lock(
-                    p_iter->second.chip->this_chip,
-                    ((i_op == SMP_ACTIVATE_PHASE1)?
-                     (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS):
-                     (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS)),
-                    ((i_op == SMP_ACTIVATE_PHASE1)?
-                     (PROC_BUILD_SMP_PHASE1_ADU_PICK_LOCK):
-                     (PROC_BUILD_SMP_PHASE2_ADU_PICK_LOCK)));
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_acquire_lock");
-                    break;
-                }
-                // NOTE: lock is now held, if an operation fails from this point
-                //       to the end of the procedure:
-                //       o attempt to cleanup/release lock (so that procedure does not
-                //         leave the ADU in a locked state)
-                //       o return rc of original fail
-                adu_is_dirty = true;
-
-                // reset ADU
-                rc = proc_build_smp_adu_reset(p_iter->second.chip->this_chip);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_reset");
-                    break;
-                }
-
-                // condition for switch AB operation
-                // all chips which were not quiesced prior to switch AB will
-                // need to observe the switch
-                rc = proc_build_smp_adu_set_switch_action(
-                    p_iter->second.chip->this_chip,
-                    !p_iter->second.quiesced_next,
-                    false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_set_switch_action (set)");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-        FAPI_DBG("proc_build_smp_switch_ab: All ADU locks held");
-
-        // build ADU control structure
-        adu_ctl.ttype = ADU_FBC_OP_TTYPE_PMISC;
-        adu_ctl.tsize = ADU_FBC_OP_TSIZE_PMISC_SWITCH_AB;
-        adu_ctl.address = 0x0ULL;
-        adu_ctl.scope = ADU_FBC_OP_SCOPE_SYSTEM;
-        adu_ctl.drop_priority = ADU_FBC_OP_DROP_PRIORITY_HIGH;
-        adu_ctl.cmd_type = ADU_FBC_OP_CMD_ADDR_ONLY;
-        adu_ctl.init_policy = ADU_FBC_OP_FBC_INIT_OVERRIDE;
-        adu_ctl.use_autoinc = false;
-
-        adu_hp_ctl.do_tm_quiesce = true;
-        adu_hp_ctl.do_pre_quiesce = true;
-        adu_hp_ctl.do_post_init = true;
-        adu_hp_ctl.post_quiesce_delay = ((i_op == SMP_ACTIVATE_PHASE1)?
-                                         (PROC_BUILD_SMP_PHASE1_POST_QUIESCE_DELAY):
-                                         (PROC_BUILD_SMP_PHASE2_POST_QUIESCE_DELAY));
-        adu_hp_ctl.pre_init_delay = ((i_op == SMP_ACTIVATE_PHASE1)?
-                                     (PROC_BUILD_SMP_PHASE1_PRE_INIT_DELAY):
-                                     (PROC_BUILD_SMP_PHASE2_PRE_INIT_DELAY));
-
-        // launch command
-        FAPI_DBG("proc_build_smp_switch_ab: Issuing switch AB from %s",
-                 i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip.toEcmdString());
-        rc = proc_adu_utils_send_fbc_op(i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip,
-                                        adu_ctl,
-                                        true,
-                                        adu_hp_ctl);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_ab: Error from proc_adu_utils_send_fbc_op");
-            break;
-        }
-
-        // check status
-        rc = proc_build_smp_adu_check_status(
-            i_smp.nodes[i_smp.master_chip_curr_node_id].chips[i_smp.master_chip_curr_chip_id].chip->this_chip,
-            i_smp,
-            true);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_check_status");
-            break;
-        }
-
-        // loop through all chips, unlock ADUs
-        FAPI_DBG("proc_build_smp_switch_ab: Releasing lock for all ADU units in drawer");
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                // reset switch action
-                rc = proc_build_smp_adu_set_switch_action(
-                    p_iter->second.chip->this_chip,
-                    false,
-                    false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_set_switch_action (clear)");
-                    break;
-                }
-
-                // release ADU lock
-                rc = proc_build_smp_adu_release_lock(
-                    p_iter->second.chip->this_chip,
-                    ((i_op == SMP_ACTIVATE_PHASE1)?
-                     (PROC_BUILD_SMP_PHASE1_ADU_LOCK_ATTEMPTS):
-                     (PROC_BUILD_SMP_PHASE2_ADU_LOCK_ATTEMPTS)));
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_switch_ab: Error from proc_build_smp_adu_release_lock");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-        FAPI_DBG("proc_build_smp_switch_ab: All ADU locks released");
-    } while(0);
-
-    // if error has occurred and any ADU is dirty,
-    // attempt to reset all ADUs and free locks (propogate rc of original fail)
-    if (!rc.ok() && adu_is_dirty)
-    {
-        FAPI_INF("proc_build_smp_switch_ab: Attempting to reset/free lock on all ADUs");
-        // loop through all chips, unlock ADUs
-        for (n_iter = i_smp.nodes.begin();
-             n_iter != i_smp.nodes.end();
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 p_iter != n_iter->second.chips.end();
-                 p_iter++)
-            {
-                (void) proc_build_smp_adu_set_switch_action(p_iter->second.chip->this_chip, false, false);
-                (void) proc_build_smp_adu_reset(p_iter->second.chip->this_chip);
-                (void) proc_build_smp_adu_release_lock(
-                    p_iter->second.chip->this_chip,
-                    1);
-            }
-        }
-    }
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_switch_ab: End");
-    return rc;
-}
-
-
-} // extern "C"
-
-
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
deleted file mode 100644
index 233995cde..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H
+++ /dev/null
@@ -1,128 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_adu.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_adu.H,v 1.5 2014/02/23 21:41:06 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_adu.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_adu.H
-// *! DESCRIPTION : Interface for ADU operations required to support fabric
-// *!               configuration actions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BUILD_SMP_ADU_H_
-#define _PROC_BUILD_SMP_ADU_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <proc_build_smp.H>
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: perform fabric C/D configuration switch on a single chip
-// parameters: i_smp_chip => structure encapsulating chip
-//             i_smp      => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
-//              for switch operation,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_switch_cd(
-    proc_build_smp_chip& i_smp_chip,
-    proc_build_smp_system& i_smp);
-
-
-//------------------------------------------------------------------------------
-// function: quiesce slave fabrics by issuing fabric quiesce operation on
-//           specified chips
-//           NOTE: ADU atomic lock will be obtained for all chips prior
-//                 to issuing quiesce operation on specified chips
-// parameters: i_smp => structure encapsulating SMP
-//             i_op  => enumerated type representing SMP build phase
-//                      (SMP_ACTIVATE_PHASE1 = HBI,
-//                       SMP_ACTIVATE_PHASE2 = FSP)
-// returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
-//              for switch operation,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_quiesce_pb(
-    proc_build_smp_system& i_smp,
-    const proc_build_smp_operation i_op);
-
-
-//------------------------------------------------------------------------------
-// function: perform fabric A/B configuration switch on all chips present in SMP
-//           NOTE: ADU atomic lock will be obtained for all chips prior to
-//                 issuing switch from master chip (defined by
-//                 i_master_smp_chip)
-// parameters: i_smp => structure encapsulating SMP
-//             i_op  => enumerated type representing SMP build phase
-//                      (SMP_ACTIVATE_PHASE1 = HBI,
-//                       SMP_ACTIVATE_PHASE2 = FSP)
-// returns: FAPI_RC_SUCCESS if fabric reconfiguration is successful,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
-//              for switch operation,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_switch_ab(
-    proc_build_smp_system& i_smp,
-    const proc_build_smp_operation i_op);
-
-
-} // extern "C"
-
-#endif // _PROC_BUILD_SMP_ADU_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
deleted file mode 100644
index 71e876c37..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C
+++ /dev/null
@@ -1,1727 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_epsilon.C,v 1.13 2015/01/26 15:06:30 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_epsilon.C
-// *! DESCRIPTION : Epsilon calculation/application functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp_epsilon.H>
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//
-// table of base epsilon values
-//
-
-const uint32_t PROC_BUILD_SMP_EPSILON_MIN_VALUE = 0x1;
-const uint32_t PROC_BUILD_SMP_EPSILON_MAX_VALUE = 0xFFFFFFFF;
-
-// HE epsilon (4 chips per-group)
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_HE[] = {    6,    6,    7,    8,    9,   15 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_HE[] = {   56,   58,   60,   62,   65,   84 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_HE[] = {  102,  104,  105,  108,  111,  130 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_F_HE[]  = {   66,   67,   69,   71,   75,   93 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_HE[]    = {   46,   47,   47,   48,   50,   55 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_F_HE[]  = {   37,   38,   39,   40,   40,   46 };
-
-// LE epsilon (2 chips per-group)
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_LE[] = {    6,    6,    7,    8,    9,   15 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_LE[] = {   47,   49,   50,   53,   56,   75 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_LE[] = {   93,   95,   96,   99,  102,  120 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_F_LE[]  = {   66,   67,   69,   71,   75,   93 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_LE[]    = {   46,   47,   47,   48,   50,   55 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_F_LE[]  = {   37,   38,   39,   40,   40,   46 };
-
-// Stradale epsilon (1 chip per-group)
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T0_1S[] = {    6,    6,    7,    8,    9,   15 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T1_1S[] = {    6,    6,    7,    8,    9,   15 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_T2_1S[] = {   63,   64,   65,   68,   72,   90 };
-const uint32_t PROC_BUILD_SMP_EPSILON_R_F_1S[]  = {   66,   67,   69,   71,   75,   93 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_1S[]    = {   14,   14,   15,   15,   16,   23 };
-const uint32_t PROC_BUILD_SMP_EPSILON_W_F_1S[]  = {   37,   38,   39,   40,   40,   46 };
-
-
-//
-// unit specific epsilon range constants
-//
-
-enum proc_build_smp_epsilon_unit
-{
-    PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_L2_W_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T0,
-    PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T1,
-    PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_L3_W_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T0,
-    PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T1,
-    PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T0,
-    PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T1,
-    PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_F,
-    PROC_BUILD_SMP_EPSILON_UNIT_NX_W_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_NPU_W_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_HCA_W_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_CAPP_W_T2,
-    PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T0,
-    PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T1,
-    PROC_BUILD_SMP_EPSILON_UNIT_MCD_P
-};
-
-// L2
-const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2 = 2048;
-const uint32_t PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2 = 128;
-
-// L3
-const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2 = 2048;
-const uint32_t PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2 = 128;
-
-// MCS
-const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0 = 1016;
-const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1 = 1016;
-const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2 = 1016;
-const uint32_t PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F  = 1016;
-
-const uint8_t  PROC_BUILD_SMP_EPSILON_MCS_JITTER = 0x1;
-
-// NX
-const uint32_t PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2 = 448;
-
-// NPU
-const uint32_t PROC_BUILD_SMP_EPSILON_NPU_MAX_VALUE_W_T2 = 448;
-
-// HCA
-const uint32_t PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2 = 512;
-
-// CAPP
-const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2 = 512;
-const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2 = 128;
-
-const uint32_t PROC_BUILD_SMP_EPSILON_CAPP_FORCE_T2 = 0x1;
-
-// MCD
-const uint32_t PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P = 65520;
-
-
-//
-// unit specific register field/bit definition constants
-//
-
-// MCS MCEPS register field/bit definitions
-const uint32_t MCEPS_JITTER_EPSILON_START_BIT = 0;
-const uint32_t MCEPS_JITTER_EPSILON_END_BIT = 7;
-const uint32_t MCEPS_NODAL_EPSILON_START_BIT = 8;
-const uint32_t MCEPS_NODAL_EPSILON_END_BIT = 15;
-const uint32_t MCEPS_GROUP_EPSILON_START_BIT = 16;
-const uint32_t MCEPS_GROUP_EPSILON_END_BIT = 23;
-const uint32_t MCEPS_SYSTEM_EPSILON_START_BIT = 24;
-const uint32_t MCEPS_SYSTEM_EPSILON_END_BIT = 31;
-const uint32_t MCEPS_FOREIGN_EPSILON_START_BIT = 32;
-const uint32_t MCEPS_FOREIGN_EPSILON_END_BIT = 39;
-
-// NX CQ Epsilon Scale register field/bit definitions
-const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_START_BIT = 0;
-const uint32_t NX_CQ_EPSILON_SCALE_EPSILON_END_BIT = 5;
-
-// NPU CQ Epsilon Scale register field/bit definitions
-const uint8_t NPU_NUM_EPS_REGS = 4;
-const uint32_t NPU_CQ_EPSILON_REGS[NPU_NUM_EPS_REGS] =
-{
-    NPU0_CQ_EPS_0x08013C08,
-    NPU1_CQ_EPS_0x08013C48,
-    NPU2_CQ_EPS_0x08013D08,
-    NPU3_CQ_EPS_0x08013D48
-};
-
-const uint32_t NPU_CQ_EPSILON_SCALE_EPSILON_START_BIT = 0;
-const uint32_t NPU_CQ_EPSILON_SCALE_EPSILON_END_BIT = 5;
-
-// HCA Mode register field/bit definitions
-const uint32_t HCA_MODE_EPSILON_START_BIT = 21;
-const uint32_t HCA_MODE_EPSILON_END_BIT = 29;
-
-// CAPP CXA Snoop Control register field/bit definitions
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT = 3;
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT = 11;
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT = 15;
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT = 23;
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT = 25;
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT = 35;
-const uint32_t CAPP_CXA_SNP_READ_EPSILON_MODE_BIT = 0;
-
-// CAPP APC Master PB Control register field/bit definitions
-const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT = 39;
-const uint32_t CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT = 45;
-
-// MCD Recovery Pre Epsilon Configuration register field/bit definitions
-const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT = 52;
-const uint32_t MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT = 63;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility function to round to ceiling
-// parameters: i_n => numerator
-//             i_d => denominator
-// returns: ceiling of i_n / i_d (integer)
-//------------------------------------------------------------------------------
-uint32_t proc_build_smp_round_ceiling(
-    uint32_t i_n,
-    uint32_t i_d)
-{
-    return((i_n / i_d) + ((i_n % i_d)?(1):(0)));
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to apply positive/negative scaing factor
-//           to base epsilon value
-// parameters: i_gb_positive   => set guardband direction (true=positive,
-//                                false=negative)
-//             i_gb_percentage => scaling factor (e.g. 20% = 20)
-//             io_target_value => target epsilon value, after
-//                                application of scaling factor
-//                                NOTE: scaling will be clamped to
-//                                minimum/maximum value
-// returns: void
-//------------------------------------------------------------------------------
-void proc_build_smp_guardband_epsilon(
-    const bool i_gb_positive,
-    const uint8_t i_gb_percentage,
-    uint32_t & io_target_value)
-{
-    uint32_t delta = proc_build_smp_round_ceiling(io_target_value * i_gb_percentage, 100);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_guardband_epsilon: Start");
-
-    // apply guardband
-    if (i_gb_positive)
-    {
-        // clamp to maximum value if necessary
-        if (delta > (PROC_BUILD_SMP_EPSILON_MAX_VALUE - io_target_value))
-        {
-            FAPI_DBG("proc_build_smp_guardband_epsilon: Guardband application generated out-of-range target value, clamping to maximum value!");
-            io_target_value = PROC_BUILD_SMP_EPSILON_MAX_VALUE;
-        }
-        else
-        {
-            io_target_value += delta;
-        }
-    }
-    else
-    {
-        // clamp to minimum value if necessary
-        if (delta >= io_target_value)
-        {
-            FAPI_DBG("proc_build_smp_guardband_epsilon: Guardband application generated out-of-range target value, clamping to minimum value!");
-            io_target_value = PROC_BUILD_SMP_EPSILON_MIN_VALUE;
-        }
-        else
-        {
-            io_target_value -= delta;
-        }
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_guardband_epsilon: End");
-    return;
-}
-
-
-//------------------------------------------------------------------------------
-// function: check if target epsilon value is less than maximum realizable
-//           value given underlying register storage
-// parameters: i_target_value => desired epsilon value
-//             i_max_hw_value => largest value which can be represented by
-//                               underlying register storage
-//             i_must_fit     => raise error if true and target value
-//                               cannot be represented in underlying storage
-//             i_unit         => unit enum for FFDC
-//             o_does_fit     => boolean indicating comparison result
-// returns: FAPI_RC_SUCCESS if value can be represented in HW storage (or
-//              i_must_fit is false)
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if value is out of range and
-//              i_must_fit is true
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_check_epsilon(
-    const uint32_t i_target_value,
-    const uint32_t i_max_hw_value,
-    const bool i_must_fit,
-    const proc_build_smp_epsilon_unit i_unit,
-    bool& o_does_fit)
-{
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_check_epsilon: Start");
-
-    do
-    {
-        o_does_fit = (i_max_hw_value > i_target_value);
-
-        if (i_must_fit && !o_does_fit)
-        {
-            FAPI_ERR("proc_build_smp_check_epsilon: Desired value (= %d) is greater than maximum value supported by HW (= %d)",
-                     i_target_value, i_max_hw_value);
-            const uint32_t& VALUE = i_target_value;
-            const uint32_t& MAX_HW_VALUE = i_max_hw_value;
-            const proc_build_smp_epsilon_unit& UNIT = i_unit;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR);
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_check_epsilon: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set L2 unit epsilon configuration attributes
-// parameters: i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all attributes are set to valid values,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_l2(
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    bool r_t0_fits = false;
-    bool r_t1_fits = false;
-    bool r_t2_fits = false;
-    bool w_t2_fits = false;
-    uint8_t l2_force_t2_attr_value;
-    uint32_t l2_r_t0_attr_value;
-    uint32_t l2_r_t1_attr_value;
-    uint32_t l2_r_t2_attr_value;
-    uint32_t l2_w_attr_value;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_l2: Start");
-
-    do
-    {
-        //
-        // NOTE: L2 epsilon valus will only be pushed into attributes by
-        //       this procedure.  Hostboot will run on scan flush (safe) values,
-        //       and runtime values pushed into attributes will be applied
-        //       via winkle image.
-        //
-        // 10012814 = L2 Epsilon Config Register
-        //   0:8  = r_t0 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //   9:17 = r_t1 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //  18:28 = r_t2 (MAX = all 0s = 2048, MIN = 1, HW = target_value+1)
-        //  29:35 = w_t2 (MAX = all 0s =  128, MIN = 1, HW = target_value+1)
-        //     36 = force t2 (0 = MODE1 = use scope to choose tier,
-        //                    1 = MODE2 = use r_t2 value for all read protection
-        //
-
-        // target read tier2 & write tier2 epsilon values must be representable
-        // in HW storage, error out if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t2,
-            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T2,
-            r_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from proc_build_smp_check_epsilon (r_t2)");
-            break;
-        }
-
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.w_t2,
-            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_L2_W_T2,
-            w_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from proc_build_smp_check_epsilon (w_t2)");
-            break;
-        }
-
-        // check read tier0, read tier1 target values
-        // don't error if these don't fit, as we will just force use of tier2
-        // in this case
-        (void) proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t0,
-            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0,
-            false,
-            PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T0,
-            r_t0_fits);
-        (void) proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t1,
-            PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1,
-            false,
-            PROC_BUILD_SMP_EPSILON_UNIT_L2_R_T1,
-            r_t1_fits);
-
-        // set attributes based on unit implementation
-        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T2_EPS");
-        l2_r_t2_attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T2)?
-                              (0):(i_eps_cfg.r_t2+1));
-        rc = FAPI_ATTR_SET(
-            ATTR_L2_R_T2_EPS,
-            NULL,
-            l2_r_t2_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T2_EPS)");
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_W_EPS");
-        l2_w_attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_W_T2)?
-                           (0):(i_eps_cfg.w_t2+1));
-        rc = FAPI_ATTR_SET(
-            ATTR_L2_W_EPS,
-            NULL,
-            l2_w_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_W_EPS)");
-            break;
-        }
-
-        // force tier2 if necessary
-        if (!r_t0_fits || !r_t1_fits)
-        {
-            l2_force_t2_attr_value = fapi::ENUM_ATTR_L2_FORCE_R_T2_EPS_ON;
-            l2_r_t0_attr_value = 0;
-            l2_r_t1_attr_value = 0;
-        }
-        // otherwise, write explicit read tier0, read tier1 attribute values
-        else
-        {
-            l2_force_t2_attr_value = fapi::ENUM_ATTR_L2_FORCE_R_T2_EPS_OFF;
-            l2_r_t0_attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T0)?
-                                  (0):(i_eps_cfg.r_t0+1));
-            l2_r_t1_attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L2_MAX_VALUE_R_T1)?
-                                  (0):(i_eps_cfg.r_t1+1));
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_FORCE_R_T2_EPS");
-        rc = FAPI_ATTR_SET(
-            ATTR_L2_FORCE_R_T2_EPS,
-            NULL,
-            l2_force_t2_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_FORCE_R_T2_EPS)");
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T0_EPS");
-        rc = FAPI_ATTR_SET(
-            ATTR_L2_R_T0_EPS,
-            NULL,
-            l2_r_t0_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T0_EPS)");
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l2: Writing ATTR_L2_R_T1_EPS");
-        rc = FAPI_ATTR_SET(
-            ATTR_L2_R_T1_EPS,
-            NULL,
-            l2_r_t1_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l2: Error from FAPI_ATTR_SET (ATTR_L2_R_T1_EPS)");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons_l2: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set L3 unit epsilon configuration attributes
-// parameters: i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all attributes are set to valid values,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_l3(
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    bool r_t0_fits = false;
-    bool r_t1_fits = false;
-    bool r_t2_fits = false;
-    bool w_t2_fits = false;
-
-    uint8_t l3_force_t2_attr_value;
-    uint32_t l3_r_t0_attr_value;
-    uint32_t l3_r_t1_attr_value;
-    uint32_t l3_r_t2_attr_value;
-    uint32_t l3_w_attr_value;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_l3: Start");
-
-    do
-    {
-        //
-        // NOTE: L3 epsilon valus will only be pushed into attributes by
-        //       this procedure.  Hostboot will run on scan flush (safe) values,
-        //       and runtime values pushed into attributes will be applied
-        //       via winkle image.
-        //
-        // 10010829 = L3 Read Epsilon Config Register
-        //    0:8 = r_t0 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //   9:17 = r_t1 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //  18:28 = r_t2 (MAX = all 0s = 2048, MIN = 1, HW = target_value+1)
-        //  29:30 = force t2 (00 = MODE1 = use scope to choose tier,
-        //                    01 = MODE2 = use r_t2 value for all read protection
-        //
-        // 1001082A = L3 Write Epsilon Config Register
-        //    0:6 = w_t2 (MAX = all 0s =  128, MIN = 1, HW = target value+1)
-        //
-
-        // target read tier2 & write epsilon values must be representable
-        // in HW storage, error if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t2,
-            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T2,
-            r_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from proc_build_smp_check_epsilon (r_t2)");
-            break;
-        }
-
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.w_t2,
-            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_L3_W_T2,
-            w_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from proc_build_smp_check_epsilon (w_t2)");
-            break;
-        }
-
-        // check read tier0, read tier1 target values
-        // don't error if these don't fit, as we will just force use of tier2
-        // in this case
-        (void) proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t0,
-            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0,
-            false,
-            PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T0,
-            r_t0_fits);
-        (void) proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t1,
-            PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1,
-            false,
-            PROC_BUILD_SMP_EPSILON_UNIT_L3_R_T1,
-            r_t1_fits);
-
-        // set attributes based on unit implementation
-        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T2_EPS");
-        l3_r_t2_attr_value = ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T2)?
-                              (0):(i_eps_cfg.r_t2+1));
-        rc = FAPI_ATTR_SET(
-            ATTR_L3_R_T2_EPS,
-            NULL,
-            l3_r_t2_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T2_EPS)");
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_W_EPS");
-        l3_w_attr_value = ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_W_T2)?
-                           (0):(i_eps_cfg.w_t2+1));
-        rc = FAPI_ATTR_SET(
-            ATTR_L3_W_EPS,
-            NULL,
-            l3_w_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_W_EPS");
-            break;
-        }
-
-        // force tier2 if necessary
-        if (!r_t0_fits || !r_t1_fits)
-        {
-            l3_force_t2_attr_value = fapi::ENUM_ATTR_L3_FORCE_R_T2_EPS_ON;
-            l3_r_t0_attr_value = 0;
-            l3_r_t1_attr_value = 0;
-        }
-        // otherwise, write explicit read tier0, read tier1 attribute values
-        else
-        {
-            l3_force_t2_attr_value = fapi::ENUM_ATTR_L2_FORCE_R_T2_EPS_OFF;
-            l3_r_t0_attr_value = ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T0)?
-                                  (0):(i_eps_cfg.r_t0+1));
-            l3_r_t1_attr_value = ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_L3_MAX_VALUE_R_T1)?
-                                  (0):(i_eps_cfg.r_t1+1));
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_FORCE_R_T2_EPS");
-        rc = FAPI_ATTR_SET(
-            ATTR_L3_FORCE_R_T2_EPS,
-            NULL,
-            l3_force_t2_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_FORCE_R_T2_EPS)");
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T0_EPS");
-        rc = FAPI_ATTR_SET(
-            ATTR_L3_R_T0_EPS,
-            NULL,
-            l3_r_t0_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T0_EPS)");
-            break;
-        }
-
-        FAPI_DBG("proc_build_smp_set_epsilons_l3: Writing ATTR_L3_R_T1_EPS");
-        rc = FAPI_ATTR_SET(
-            ATTR_L3_R_T1_EPS,
-            NULL,
-            l3_r_t1_attr_value);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_l3: Error from FAPI_ATTR_SET (ATTR_L3_R_T1_EPS)");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons_l3: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set MCS unit epsilon registers for all configured chiplets
-//           on target chip
-// parameters: i_target  => chip target
-//             i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all settings are programmed correctly,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_mcs(
-    fapi::Target & i_target,
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    bool r_t0_fits = false;
-    bool r_t1_fits = false;
-    bool r_t2_fits = false;
-    bool r_f_fits  = false;
-    ecmdDataBufferBase data(64);
-    std::vector<fapi::Target> mcs_chiplets;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_mcs: Start");
-
-    do
-    {
-        //
-        // 02011816 = MCS Epsilon Register
-        //    0:7 = jitter (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
-        //   8:15 = r_t0   (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
-        //  16:23 = r_t1   (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
-        //  24:31 = r_t2   (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
-        //  32:39 = r_f    (MAX = all 1s = 1016, MIN = all 0s = 0, HW = [target value/4]+1)
-        //
-
-        // all target values must be representable in HW storage, error if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t0,
-            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T0,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T0,
-            r_t0_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_t0)");
-            break;
-        }
-
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t1,
-            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T1,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T1,
-            r_t1_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_t1)");
-            break;
-        }
-
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t2,
-            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_T2,
-            r_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_t2)");
-            break;
-        }
-
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_f,
-            PROC_BUILD_SMP_EPSILON_MCS_MAX_VALUE_R_F,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_MCS_R_F,
-            r_f_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from proc_build_smp_check_epsilon (r_f)");
-            break;
-        }
-
-        // form data buffer
-        rc_ecmd |= data.insertFromRight(
-            PROC_BUILD_SMP_EPSILON_MCS_JITTER,
-            MCEPS_JITTER_EPSILON_START_BIT,
-            (MCEPS_JITTER_EPSILON_END_BIT-
-             MCEPS_JITTER_EPSILON_START_BIT+1));
-
-        rc_ecmd |= data.insertFromRight(
-            proc_build_smp_round_ceiling(i_eps_cfg.r_t0, 4)+1,
-            MCEPS_NODAL_EPSILON_START_BIT,
-            (MCEPS_NODAL_EPSILON_END_BIT-
-             MCEPS_NODAL_EPSILON_START_BIT+1));
-
-        rc_ecmd |= data.insertFromRight(
-            proc_build_smp_round_ceiling(i_eps_cfg.r_t1, 4)+1,
-            MCEPS_GROUP_EPSILON_START_BIT,
-            (MCEPS_GROUP_EPSILON_END_BIT-
-             MCEPS_GROUP_EPSILON_START_BIT+1));
-
-        rc_ecmd |= data.insertFromRight(
-            proc_build_smp_round_ceiling(i_eps_cfg.r_t2, 4)+1,
-            MCEPS_SYSTEM_EPSILON_START_BIT,
-            (MCEPS_SYSTEM_EPSILON_END_BIT-
-             MCEPS_SYSTEM_EPSILON_START_BIT+1));
-
-        rc_ecmd |= data.insertFromRight(
-            proc_build_smp_round_ceiling(i_eps_cfg.r_f, 4)+1,
-            MCEPS_FOREIGN_EPSILON_START_BIT,
-            (MCEPS_FOREIGN_EPSILON_END_BIT-
-             MCEPS_FOREIGN_EPSILON_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error 0x%x setting up MCEPS data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // determine configured MCS chiplets
-        rc = fapiGetChildChiplets(i_target,
-                                  fapi::TARGET_TYPE_MCS_CHIPLET,
-                                  mcs_chiplets);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcs: Error from fapiGetChildChiplets");
-            break;
-
-        }
-
-        // loop over configured MCS chiplets and set epsilon configuration
-        for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin();
-             i != mcs_chiplets.end();
-             i++)
-        {
-            rc = fapiPutScom(*i, MCS_MCEPS_0x02011816, data);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_mcs: fapiPutScom error (MCS_MCEPS_0x02011816)");
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons_mcs: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set NX CQ (NX/AS) unit epsilon registers
-// parameters: i_target  => chip target
-//             i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all settings are programmed correctly,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_nx(
-    fapi::Target & i_target,
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    bool w_t2_fits = false;
-    ecmdDataBufferBase data(64), mask(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_nx: Start");
-
-    do
-    {
-        //
-        // 0201309D = NX CQ Epsilon Scale register
-        //    0:5 = w_t2 (MAX = all 0s =  448, MIN = 1, HW = target_value/7)
-        //
-
-        // target write tier2 epsilon value must be representable
-        // in HW storage, error out if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.w_t2,
-            PROC_BUILD_SMP_EPSILON_NX_MAX_VALUE_W_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_NX_W_T2,
-            w_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_nx: Error from proc_build_smp_check_epsilon (w_t2)");
-            break;
-        }
-
-        // program write epsilon register based on unit implementation
-        uint32_t hw_value = proc_build_smp_round_ceiling(i_eps_cfg.w_t2, 7);
-        if (hw_value == 64)
-        {
-            hw_value = 0;
-        }
-
-        rc_ecmd |= data.insertFromRight(
-            hw_value,
-            NX_CQ_EPSILON_SCALE_EPSILON_START_BIT,
-            (NX_CQ_EPSILON_SCALE_EPSILON_END_BIT-
-             NX_CQ_EPSILON_SCALE_EPSILON_START_BIT+1));
-        rc_ecmd |= mask.setBit(
-            NX_CQ_EPSILON_SCALE_EPSILON_START_BIT,
-            (NX_CQ_EPSILON_SCALE_EPSILON_END_BIT-
-             NX_CQ_EPSILON_SCALE_EPSILON_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_nx: Error 0x%x setting up NX CQ Epsilon Scale register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register (use mask to avoid overriding other configuration
-        // settings in register)
-        rc = fapiPutScomUnderMask(i_target,
-                                  NX_CQ_EPS_0x0201309D,
-                                  data,
-                                  mask);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_nx: fapiPutScomUnderMask error (NX_CQ_EPS_0x0201309D)");
-            break;
-        }
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_nx: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set NPU unit epsilon registers
-// parameters: i_target  => chip target
-//             i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all settings are programmed correctly,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_npu(
-    fapi::Target & i_target,
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    bool w_t2_fits = false;
-    ecmdDataBufferBase data(64), mask(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_npu: Start");
-
-    do
-    {
-        //
-        // NPU CQ Epsilon Scale register
-        //    0:5 = w_t2 (MAX = all 0s =  448, MIN = 1, HW = target_value/7)
-        //
-
-        // target write tier2 epsilon value must be representable
-        // in HW storage, error out if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.w_t2,
-            PROC_BUILD_SMP_EPSILON_NPU_MAX_VALUE_W_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_NPU_W_T2,
-            w_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_npu: Error from proc_build_smp_check_epsilon (w_t2)");
-            break;
-        }
-
-        // program write epsilon register based on unit implementation
-        uint32_t hw_value = proc_build_smp_round_ceiling(i_eps_cfg.w_t2, 7);
-        if (hw_value == 64)
-        {
-            hw_value = 0;
-        }
-
-        rc_ecmd |= data.insertFromRight(
-            hw_value,
-            NPU_CQ_EPSILON_SCALE_EPSILON_START_BIT,
-            (NPU_CQ_EPSILON_SCALE_EPSILON_END_BIT-
-             NPU_CQ_EPSILON_SCALE_EPSILON_START_BIT+1));
-        rc_ecmd |= mask.setBit(
-            NPU_CQ_EPSILON_SCALE_EPSILON_START_BIT,
-            (NPU_CQ_EPSILON_SCALE_EPSILON_END_BIT-
-             NPU_CQ_EPSILON_SCALE_EPSILON_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_npu: Error 0x%x setting up NPU CQ Epsilon Scale register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        for (uint8_t i = 0; i < NPU_NUM_EPS_REGS; i++)
-        {
-            // write register (use mask to avoid overriding other configuration
-            // settings in register)
-            rc = fapiPutScomUnderMask(i_target,
-                                      NPU_CQ_EPSILON_REGS[i],
-                                      data,
-                                      mask);
-            
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_npu: fapiPutScomUnderMask error (NPU%d_CQ_EPS_0x%08X)",
-                         i, NPU_CQ_EPSILON_REGS[i]);
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_npu: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set HCA unit epsilon registers
-// parameters: i_target  => chip target
-//             i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all settings are programmed correctly,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_hca(
-    fapi::Target & i_target,
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    bool w_t2_fits = false;
-    ecmdDataBufferBase data(64), mask(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_hca: Start");
-
-    do
-    {
-        //
-        // 0201094F = HCA Mode Register
-        //  21:29 = w_t2 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //
-
-        // all target values must be representable in HW storage, error if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.w_t2,
-            PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_HCA_W_T2,
-            w_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_hca: Error from proc_build_smp_check_epsilon (w_t2)");
-            break;
-        }
-
-        // form data buffer
-        rc_ecmd |= data.insertFromRight(
-            ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_HCA_MAX_VALUE_W_T2)?
-             (0):(i_eps_cfg.w_t2+1)),
-            HCA_MODE_EPSILON_START_BIT,
-            (HCA_MODE_EPSILON_END_BIT-
-             HCA_MODE_EPSILON_START_BIT+1));
-        rc_ecmd |= mask.setBit(
-            HCA_MODE_EPSILON_START_BIT,
-            (HCA_MODE_EPSILON_END_BIT-
-             HCA_MODE_EPSILON_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_hca: Error 0x%x setting up HCA Mode data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register (use mask to avoid overriding other configuration
-        // settings in register)
-        rc = fapiPutScomUnderMask(i_target, HCA_MODE_0x0201094F, data, mask);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_hca: fapiPutScomUnderMask error (HCA_MODE_0x0201094F)");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons_hca: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set CAPP unit epsilon registers
-// parameters: i_target            => chip target
-//             i_dual_capp_present => indicate presence of 2nd CAPP unit
-//             i_eps_cfg           => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all settings are programmed correctly,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_capp(
-    fapi::Target & i_target,
-    const bool i_dual_capp_present,
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    bool r_t0_fits = false;
-    bool r_t1_fits = false;
-    bool r_t2_fits = false;
-    bool w_t2_fits = false;
-    ecmdDataBufferBase data(64), mask(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_capp: Start");
-
-    do
-    {
-        //
-        // 0201301B = CAPP CXA Snoop Control register
-        //   3:11 = r_t0 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //  15:23 = r_t1 (MAX = all 0s =  512, MIN = 1, HW = target_value+1)
-        //  25:35 = r_t2 (MAX = all 0s = 2048, MIN = 1, HW = target_value+1)
-        //      0 = force t2 (0 = MODE1 = use scope to choose tier,
-        //                    0 = MODE2 = use r_t2 value for all read protection
-        //
-        // 02013018 = CAPP APC Master PB Control register
-        //  39:45 = w_t2 (MAX = all 0s =  128, MIN = 1, HW = target value+1)
-        //
-
-        // target read tier2 & write tier2 epsilon values must be representable
-        // in HW storage, error out if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t2,
-            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T2,
-            r_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error from proc_build_smp_check_epsilon (r_t2)");
-            break;
-        }
-
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.w_t2,
-            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_CAPP_W_T2,
-            w_t2_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error from proc_build_smp_check_epsilon (w_t2)");
-            break;
-        }
-
-        // check read tier0, read tier1 target values
-        // don't error if these don't fit, as we will just force use of tier2
-        // in this case
-        (void) proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t0,
-            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0,
-            false,
-            PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T0,
-            r_t0_fits);
-        (void) proc_build_smp_check_epsilon(
-            i_eps_cfg.r_t1,
-            PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1,
-            false,
-            PROC_BUILD_SMP_EPSILON_UNIT_CAPP_R_T1,
-            r_t1_fits);
-
-        // program write epsilon register based on unit implementation
-        rc_ecmd |= data.insertFromRight(
-            ((i_eps_cfg.w_t2 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_W_T2)?
-             (0):(i_eps_cfg.w_t2+1)),
-            CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT,
-            (CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT-
-             CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT+1));
-        rc_ecmd |= mask.setBit(
-            CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT,
-            (CAPP_APC_MASTER_CONTROL_EPSILON_END_BIT-
-             CAPP_APC_MASTER_CONTROL_EPSILON_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error 0x%x setting up CAPP APC Master Control register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register (use mask to avoid overriding other configuration
-        // settings in register)
-        rc = fapiPutScomUnderMask(i_target,
-                                  CAPP_APC_MASTER_PB_CTL_0x02013018,
-                                  data,
-                                  mask);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP_APC_MASTER_PB_CTL_0x02013018)");
-            break;
-        }
-
-        if (i_dual_capp_present)
-        {
-            rc = fapiPutScomUnderMask(i_target,
-                                      CAPP1_APC_MASTER_PB_CTL_0x02013198,
-                                      data,
-                                      mask);
-            
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP1_APC_MASTER_PB_CTL_0x02013198)");
-                break;
-            }
-        }
-
-
-        // program read epsilon register based on unit implementation
-        rc_ecmd = data.flushTo0();
-        rc_ecmd |= mask.flushTo0();
-
-        rc_ecmd |= data.insertFromRight(
-            ((i_eps_cfg.r_t2 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T2)?
-             (0):(i_eps_cfg.r_t2+1)),
-            CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT,
-            (CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT-
-             CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT+1));
-        rc_ecmd |= mask.setBit(
-            CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT,
-            (CAPP_CXA_SNP_READ_EPSILON_TIER2_END_BIT-
-             CAPP_CXA_SNP_READ_EPSILON_TIER2_START_BIT+1));
-
-        // force tier2 if necessary
-        if (!r_t0_fits || !r_t1_fits)
-        {
-            rc_ecmd |= data.writeBit(
-                CAPP_CXA_SNP_READ_EPSILON_MODE_BIT,
-                PROC_BUILD_SMP_EPSILON_CAPP_FORCE_T2);
-            rc_ecmd |= mask.setBit(
-                CAPP_CXA_SNP_READ_EPSILON_MODE_BIT);
-        }
-        else
-        {
-            rc_ecmd |= data.insertFromRight(
-                ((i_eps_cfg.r_t0 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T0)?
-                 (0):(i_eps_cfg.r_t0+1)),
-                CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT,
-                (CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT-
-                 CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT+1));
-            rc_ecmd |= mask.setBit(
-                CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT,
-                (CAPP_CXA_SNP_READ_EPSILON_TIER0_END_BIT-
-                 CAPP_CXA_SNP_READ_EPSILON_TIER0_START_BIT+1));
-
-            rc_ecmd |= data.insertFromRight(
-                ((i_eps_cfg.r_t1 == PROC_BUILD_SMP_EPSILON_CAPP_MAX_VALUE_R_T1)?
-                 (0):(i_eps_cfg.r_t1+1)),
-                CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT,
-                (CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT-
-                 CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT+1));
-            rc_ecmd |= mask.setBit(
-                CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT,
-                (CAPP_CXA_SNP_READ_EPSILON_TIER1_END_BIT-
-                 CAPP_CXA_SNP_READ_EPSILON_TIER1_START_BIT+1));
-        }
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_capp: Error 0x%x setting up CAPP CXA Snoop Control register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register (use mask to avoid overriding other configuration
-        // settings in register)
-        rc = fapiPutScomUnderMask(i_target,
-                                  CAPP_CXA_SNOOP_CTL_0x0201301B,
-                                  data,
-                                  mask);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP_CXA_SNOOP_CTL_0x0201301B)");
-            break;
-        }
-
-        if (i_dual_capp_present)
-        {
-            rc = fapiPutScomUnderMask(i_target,
-                                      CAPP1_CXA_SNOOP_CTL_0x0201319B,
-                                      data,
-                                      mask);
-            
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_epsilons_capp: fapiPutScomUnderMask error (CAPP1_CXA_SNOOP_CTL_0x0201319B)");
-                break;
-            }
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons_capp: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: set MCD unit epsilon registers
-// parameters: i_target  => chip target
-//             i_eps_cfg => system epsilon configuration structure
-// returns: ECMD_SUCCESS if all settings are programmed correctly,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons_mcd(
-    fapi::Target & i_target,
-    const proc_build_smp_eps_cfg & i_eps_cfg)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    bool p_fits = false;
-    ecmdDataBufferBase data(64), mask(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons_mcd: Start");
-
-    do
-    {
-        //
-        // 0201340B = MCD Recovery Pre Epsilon Configuration register
-        //  52:63 = p (MAX = all 1s = 66520, MIN = 0, HW = target_value/16)
-        //
-
-        // target pre epsilon value must be representable
-        // in HW storage, error out if not
-        rc = proc_build_smp_check_epsilon(
-            i_eps_cfg.p,
-            PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P,
-            true,
-            PROC_BUILD_SMP_EPSILON_UNIT_MCD_P,
-            p_fits);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcd: Error from proc_build_smp_check_epsilon (p)");
-            break;
-        }
-
-        // program write epsilon register based on unit implementation
-        rc_ecmd |= data.insertFromRight(
-            proc_build_smp_round_ceiling(i_eps_cfg.p, 16),
-            MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT,
-            (MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT-
-             MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT+1));
-        rc_ecmd |= mask.setBit(
-            MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT,
-            (MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_END_BIT-
-             MCD_RECOVERY_PRE_EPS_CONFIG_EPSILON_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcd: Error 0x%x setting up MCD Recovery Pre Epsilon Configuration register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register (use mask to avoid overriding other configuration
-        // settings in register)
-        rc = fapiPutScomUnderMask(i_target,
-                                  MCD_PRE_EPS_0x0201340B,
-                                  data,
-                                  mask);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons_mcd: fapiPutScomUnderMask error (MCD_PRE_EPS_0x0201340B)");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons_mcd: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: calculate target epsilon settings to apply based on
-//           system configuration
-// parameters: io_smp => structure encapsulating SMP (including system
-//                       frequency/epsilon configuration parameter values),
-//                       target epsilon values will be filled by this subroutine
-// returns: FAPI_RC_SUCCESS if target settings are valid,
-//          RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR if invalid epsilon
-//              table type/content is detected,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_calc_epsilons(
-    proc_build_smp_system & io_smp)
-{
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_calc_epsilons: Start");
-
-    do
-    {
-        // perform table lookup based on system table type
-        FAPI_DBG("proc_build_smp_calc_epsilons: core floor freq = %d, PB freq = %d, table index = %d",
-                 io_smp.freq_core_floor,
-                 io_smp.freq_pb,
-                 io_smp.core_floor_ratio);
-
-        switch(io_smp.eps_cfg.table_type)
-        {
-            case PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE:
-                if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1)
-                {
-                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T0_HE[io_smp.core_floor_ratio];
-                }
-                else
-                {
-                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T1_HE[io_smp.core_floor_ratio];
-                }
-                io_smp.eps_cfg.r_t1 = PROC_BUILD_SMP_EPSILON_R_T1_HE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.r_t2 = PROC_BUILD_SMP_EPSILON_R_T2_HE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.r_f  = PROC_BUILD_SMP_EPSILON_R_F_HE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_HE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.w_f  = PROC_BUILD_SMP_EPSILON_W_F_HE[io_smp.core_floor_ratio];
-                break;
-            case PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE:
-                if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1)
-                {
-                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T0_LE[io_smp.core_floor_ratio];
-                }
-                else
-                {
-                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T1_LE[io_smp.core_floor_ratio];
-                }
-                io_smp.eps_cfg.r_t1 = PROC_BUILD_SMP_EPSILON_R_T1_LE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.r_t2 = PROC_BUILD_SMP_EPSILON_R_T2_LE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.r_f  = PROC_BUILD_SMP_EPSILON_R_F_LE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_LE[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.w_f  = PROC_BUILD_SMP_EPSILON_W_F_LE[io_smp.core_floor_ratio];
-                break;
-            case PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S:
-                if (io_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE1)
-                {
-                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T0_1S[io_smp.core_floor_ratio];
-                }
-                else
-                {
-                    io_smp.eps_cfg.r_t0 = PROC_BUILD_SMP_EPSILON_R_T1_1S[io_smp.core_floor_ratio];
-                }
-                io_smp.eps_cfg.r_t1 = PROC_BUILD_SMP_EPSILON_R_T1_1S[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.r_t2 = PROC_BUILD_SMP_EPSILON_R_T2_1S[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.r_f  = PROC_BUILD_SMP_EPSILON_R_F_1S[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.w_t2 = PROC_BUILD_SMP_EPSILON_W_1S[io_smp.core_floor_ratio];
-                io_smp.eps_cfg.w_f  = PROC_BUILD_SMP_EPSILON_W_F_1S[io_smp.core_floor_ratio];
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_calc_epsilons: Invalid epsilon table type");
-                const proc_fab_smp_eps_table_type& TABLE_TYPE = io_smp.eps_cfg.table_type;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // dump base epsilon values
-        FAPI_DBG("proc_build_smp_calc_epsilons: Base epsilon values read from table:");
-        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T0 = %d", io_smp.eps_cfg.r_t0);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T1 = %d", io_smp.eps_cfg.r_t1);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T2 = %d", io_smp.eps_cfg.r_t2);
-        FAPI_DBG("proc_build_smp_calc_epsilons:   R_F = %d", io_smp.eps_cfg.r_f);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  W_T2 = %d", io_smp.eps_cfg.w_t2);
-        FAPI_DBG("proc_build_smp_calc_epsilons:   W_F = %d", io_smp.eps_cfg.w_f);
-
-        // scale base epsilon values if core is running 2x nest frequency
-        if (io_smp.core_ceiling_ratio == PROC_BUILD_SMP_CORE_RATIO_8_8)
-        {
-            FAPI_DBG("proc_build_smp_calc_epsilons: Scaling based on ceiling frequency");
-            uint8_t scale_percentage =
-                100 *
-                io_smp.freq_core_ceiling /
-                (2 * io_smp.freq_pb);
-            scale_percentage -= 100;
-
-            proc_build_smp_guardband_epsilon(
-                io_smp.eps_cfg.gb_positive,
-                scale_percentage,
-                io_smp.eps_cfg.r_t0);
-            proc_build_smp_guardband_epsilon(
-                io_smp.eps_cfg.gb_positive,
-                scale_percentage,
-                io_smp.eps_cfg.r_t1);
-            proc_build_smp_guardband_epsilon(
-                io_smp.eps_cfg.gb_positive,
-                scale_percentage,
-                io_smp.eps_cfg.r_t2);
-            proc_build_smp_guardband_epsilon(
-                io_smp.eps_cfg.gb_positive,
-                scale_percentage,
-                io_smp.eps_cfg.r_f);
-            proc_build_smp_guardband_epsilon(
-                io_smp.eps_cfg.gb_positive,
-                scale_percentage,
-                io_smp.eps_cfg.w_t2);
-            proc_build_smp_guardband_epsilon(
-                io_smp.eps_cfg.gb_positive,
-                scale_percentage,
-                io_smp.eps_cfg.w_f);
-        }
-
-        // apply guardband to epsilon values
-        proc_build_smp_guardband_epsilon(
-            io_smp.eps_cfg.gb_positive,
-            io_smp.eps_cfg.gb_percentage,
-            io_smp.eps_cfg.r_t0);
-        proc_build_smp_guardband_epsilon(
-            io_smp.eps_cfg.gb_positive,
-            io_smp.eps_cfg.gb_percentage,
-            io_smp.eps_cfg.r_t1);
-        proc_build_smp_guardband_epsilon(
-            io_smp.eps_cfg.gb_positive,
-            io_smp.eps_cfg.gb_percentage,
-            io_smp.eps_cfg.r_t2);
-        proc_build_smp_guardband_epsilon(
-            io_smp.eps_cfg.gb_positive,
-            io_smp.eps_cfg.gb_percentage,
-            io_smp.eps_cfg.r_f);
-        proc_build_smp_guardband_epsilon(
-            io_smp.eps_cfg.gb_positive,
-            io_smp.eps_cfg.gb_percentage,
-            io_smp.eps_cfg.w_t2);
-        proc_build_smp_guardband_epsilon(
-            io_smp.eps_cfg.gb_positive,
-            io_smp.eps_cfg.gb_percentage,
-            io_smp.eps_cfg.w_f);
-
-        // max pre-epsilon counter
-        io_smp.eps_cfg.p = PROC_BUILD_SMP_EPSILON_MCD_MAX_VALUE_P-1;
-
-        // dump scaled epsilon values
-        FAPI_DBG("proc_build_smp_calc_epsilons: Scaled epsilon values based on %s%d percent guardband:",
-                 (io_smp.eps_cfg.gb_positive)?("+"):("-"),
-                 io_smp.eps_cfg.gb_percentage);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T0 = %d", io_smp.eps_cfg.r_t0);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T1 = %d", io_smp.eps_cfg.r_t1);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  R_T2 = %d", io_smp.eps_cfg.r_t2);
-        FAPI_DBG("proc_build_smp_calc_epsilons:   R_F = %d", io_smp.eps_cfg.r_f);
-        FAPI_DBG("proc_build_smp_calc_epsilons:  W_T2 = %d", io_smp.eps_cfg.w_t2);
-        FAPI_DBG("proc_build_smp_calc_epsilons:   W_F = %d", io_smp.eps_cfg.w_f);
-        FAPI_DBG("proc_build_smp_calc_epsilons:     P = %d", io_smp.eps_cfg.p);
-
-        // check relationship of epsilon counters
-        // rules:
-        //   read tier values are strictly increasing
-        //   read tier2 value is greater than read foreign value
-        //   write tier2 value is greater than write foreign value
-        if ((io_smp.eps_cfg.r_t0 > io_smp.eps_cfg.r_t1) ||
-            (io_smp.eps_cfg.r_t1 > io_smp.eps_cfg.r_t2) ||
-            ((io_smp.eps_cfg.r_f  > io_smp.eps_cfg.r_t2) && (io_smp.eps_cfg.table_type != PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S)) ||
-            ((io_smp.eps_cfg.w_f  > io_smp.eps_cfg.w_t2) && (io_smp.eps_cfg.table_type != PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S)))
-        {
-            FAPI_ERR("proc_build_smp_calc_epsilons: Invalid relationship between base epsilon values");
-            const proc_fab_smp_eps_table_type& TABLE_TYPE = io_smp.eps_cfg.table_type;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR);
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_calc_epsilons: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_set_epsilons(
-    proc_build_smp_system & i_smp)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_epsilons: Start");
-
-    do
-    {
-        // calculate epsilons
-        rc = proc_build_smp_calc_epsilons(i_smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_calc_epsilons");
-            break;
-        }
-
-        // set system level attributes
-        // L2
-        rc = proc_build_smp_set_epsilons_l2(i_smp.eps_cfg);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_l2");
-            break;
-        }
-
-        // L3
-        rc = proc_build_smp_set_epsilons_l3(i_smp.eps_cfg);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_l3");
-            break;
-        }
-
-        // process each chip in SMP, program unit epsilon registers
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                fapi::Target target = p_iter->second.chip->this_chip;
-
-                // MCS
-                rc = proc_build_smp_set_epsilons_mcs(target, i_smp.eps_cfg);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_mcs");
-                    break;
-                }
-
-                // HCA
-                rc = proc_build_smp_set_epsilons_hca(target, i_smp.eps_cfg);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_hca");
-                    break;
-                }
-
-                // set epsilons for NX regions only if partial good attribute is set
-                if (p_iter->second.nx_enabled)
-                {
-                    // NX
-                    rc = proc_build_smp_set_epsilons_nx(target, i_smp.eps_cfg);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_nx");
-                        break;
-                    }
-
-                    // CAPP
-                    rc = proc_build_smp_set_epsilons_capp(target, p_iter->second.dual_capp_present, i_smp.eps_cfg);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_capp");
-                        break;
-                    }
-                }
-
-                // set epsilons for NPU if present
-                if (p_iter->second.nv_present)
-                {
-                    // NPU
-                    rc = proc_build_smp_set_epsilons_npu(target, i_smp.eps_cfg);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_npu");
-                        break;
-                    }
-                }
-
-                // MCD
-                rc = proc_build_smp_set_epsilons_mcd(target, i_smp.eps_cfg);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_epsilons: Error from proc_build_smp_set_epsilons_mcd");
-                    break;
-                }
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_epsilons: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
deleted file mode 100644
index 53ff190b3..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H
+++ /dev/null
@@ -1,82 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_epsilon.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_epsilon.H,v 1.8 2014/02/23 21:41:06 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_epsilon.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_epsilon.H
-// *! DESCRIPTION : Epsilon calculation/application functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BUILD_SMP_EPSILON_H_
-#define _PROC_BUILD_SMP_EPSILON_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp.H>
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: utility function to round to ceiling
-// parameters: i_n => numerator
-//             i_d => denominator
-// returns: ceiling of i_n / i_d (integer)
-//------------------------------------------------------------------------------
-uint32_t proc_build_smp_round_ceiling(
-    uint32_t i_n,
-    uint32_t i_d);
-
-
-//------------------------------------------------------------------------------
-// function: set target epsilon values into system attributes/HW
-// parameters: i_smp => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if application is successful
-//          RC_PROC_BUILD_SMP_EPSILON_INVALID_TABLE_ERR if invalid epsilon
-//              table type/content is detected,
-//          RC_PROC_BUILD_SMP_EPSILON_RANGE_ERR if any target value is out of
-//              range given underlying HW storage,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_epsilons(
-    proc_build_smp_system & i_smp);
-
-} // extern "C"
-
-#endif // _PROC_BUILD_SMP_EPSILON_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C
deleted file mode 100644
index 7fbdaa9fb..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C
+++ /dev/null
@@ -1,1859 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_ab.C,v 1.14 2015/04/21 22:29:53 jhuynh1 Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.C,v $
-
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *|
-// *! TITLE       : proc_build_smp_fbc_ab.C
-// *! DESCRIPTION : Fabric configuration (hotplug, AB) functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp_fbc_ab.H>
-#include <proc_build_smp_epsilon.H>
-#include <proc_build_smp_adu.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// PB Hotplug Mode register field/bit definitions
-const uint32_t PB_HP_MODE_LINK_A_EN_BIT[PROC_FAB_SMP_NUM_A_LINKS]       = {  1,  2,  3 };
-const uint32_t PB_HP_MODE_LINK_A_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_A_LINKS] = {  4,  5,  6 };
-const uint32_t PB_HP_MODE_LINK_A_ID_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = {  7, 10, 13 };
-const uint32_t PB_HP_MODE_LINK_A_ID_END_BIT[PROC_FAB_SMP_NUM_A_LINKS]   = {  9, 12, 15 };
-
-const uint32_t PB_HP_MODE_PCIE_NOT_DSMP_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 38, 39 };
-const uint32_t PB_HP_MODE_LINK_F_MASTER_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 42, 43 };
-const uint32_t PB_HP_MODE_LINK_F_EN_BIT[PROC_FAB_SMP_NUM_F_LINKS]       = { 44, 45 };
-const uint32_t PB_HP_MODE_LINK_F_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 46, 47 };
-const uint32_t PB_HP_MODE_LINK_F_ID_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 48, 51 };
-const uint32_t PB_HP_MODE_LINK_F_ID_END_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 50, 53 };
-
-const uint32_t PB_HP_MODE_A_AGGREGATE_BIT = 16;
-const uint32_t PB_HP_MODE_TM_MASTER_BIT = 17;
-const uint32_t PB_HP_MODE_CHG_RATE_SP_MASTER_BIT = 19;
-const uint32_t PB_HP_MODE_PUMP_MODE_BIT = 20;
-const uint32_t PB_HP_MODE_SINGLE_MC_BIT = 21;
-const uint32_t PB_HP_MODE_DCACHE_CAPP_MODE_BIT = 22;
-const uint32_t PB_HP_MODE_A_CMD_RATE_START_BIT = 24;
-const uint32_t PB_HP_MODE_A_CMD_RATE_END_BIT = 31;
-const uint32_t PB_HP_MODE_A_CMD_RATE_MIN_VALUE = 1;
-const uint32_t PB_HP_MODE_A_CMD_RATE_MAX_VALUE = 0x7F;
-const uint32_t PB_HP_MODE_A_GATHER_ENABLE_BIT = 32;
-const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT = 33;
-const uint32_t PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT = 37;
-const uint32_t PB_HP_MODE_CFG_P2_X8TOK = 39;
-const uint32_t PB_HP_MODE_CFG_P3_X8TOK = 40;
-const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_PRESENT = 41;
-const uint32_t PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_NOT_PRESENT = 40;
-const uint32_t PB_HP_MODE_F_AGGREGATE_BIT = 55;
-const uint32_t PB_HP_MODE_F_CMD_RATE_START_BIT = 56;
-const uint32_t PB_HP_MODE_F_CMD_RATE_END_BIT = 63;
-const uint32_t PB_HP_MODE_F_CMD_RATE_MIN_VALUE = 1;
-const uint32_t PB_HP_MODE_F_CMD_RATE_MAX_VALUE = 0x7F;
-
-const bool PB_HP_MODE_DCACHE_CAPP_EN = false;
-const bool PB_HP_MODE_A_GATHER_ENABLE = true;
-const uint8_t PB_HP_MODE_A_GATHER_DLY_CNT = 0x04;
-const bool PB_HP_MODE_GATHER_ENABLE = true;
-
-const uint32_t PB_HP_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
-{
-    PB_HP_MODE_NEXT_WEST_0x02010C0B,
-    PB_HP_MODE_NEXT_CENT_0x02010C4B,
-    PB_HP_MODE_NEXT_EAST_0x02010C8B
-};
-const uint32_t PB_HP_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
-{
-    PB_HP_MODE_CURR_WEST_0x02010C0C,
-    PB_HP_MODE_CURR_CENT_0x02010C4C,
-    PB_HP_MODE_CURR_EAST_0x02010C8C
-};
-
-// PB Hotplug Extension Mode register field/bit definitions
-const uint32_t PB_HPX_MODE_LINK_X_EN_BIT[PROC_FAB_SMP_NUM_X_LINKS]           = {  0,  1,  2,  3 };
-const uint32_t PB_HPX_MODE_LINK_X_ADDR_DIS_BIT[PROC_FAB_SMP_NUM_X_LINKS]     = {  5,  6,  7,  8 };
-const uint32_t PB_HPX_MODE_LINK_X_CHIPID_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 10, 13, 16, 19 };
-const uint32_t PB_HPX_MODE_LINK_X_CHIPID_END_BIT[PROC_FAB_SMP_NUM_X_LINKS]   = { 12, 15, 18, 21 };
-
-const uint32_t PB_HPX_MODE_X_AGGREGATE_BIT = 25;
-const uint32_t PB_HPX_MODE_X_INDIRECT_EN_BIT = 26;
-const uint32_t PB_HPX_MODE_X_GATHER_ENABLE_BIT = 32;
-const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT = 33;
-const uint32_t PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT = 37;
-const uint32_t PB_HPX_MODE_X_ONNODE_12QUEUES_BIT = 38;
-const uint32_t PB_HPX_MODE_GROUP_EQ_CHIP_BIT = 39;
-const uint32_t PB_HPX_MODE_X_CMD_RATE_START_BIT = 56;
-const uint32_t PB_HPX_MODE_X_CMD_RATE_END_BIT = 63;
-const uint32_t PB_HPX_MODE_X_CMD_RATE_MIN_VALUE = 1;
-const uint32_t PB_HPX_MODE_X_CMD_RATE_MAX_VALUE = 0x7F;
-
-const bool PB_HPX_MODE_X_INDIRECT_EN = true;
-const bool PB_HPX_MODE_X_GATHER_ENABLE = true;
-const uint8_t PB_HPX_MODE_X_GATHER_DLY_CNT = 0x04;
-const bool PB_HPX_MODE_X_ONNODE_12QUEUES = true;
-
-const uint32_t PB_HPX_MODE_NEXT_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
-{
-    PB_HPX_MODE_NEXT_WEST_0x02010C0D,
-    PB_HPX_MODE_NEXT_CENT_0x02010C4D,
-    PB_HPX_MODE_NEXT_EAST_0x02010C8D
-};
-const uint32_t PB_HPX_MODE_CURR_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
-{
-    PB_HPX_MODE_CURR_WEST_0x02010C0E,
-    PB_HPX_MODE_CURR_CENT_0x02010C4E,
-    PB_HPX_MODE_CURR_EAST_0x02010C8E
-};
-
-// PB X Link Mode register field/bit definitions
-const uint32_t PB_X_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_X_LINKS] = { 24, 32, 40, 48 };
-const uint32_t PB_X_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_X_LINKS]   = { 31, 39, 47, 55 };
-
-// PB A Link Mode register field/bit definitions
-const uint32_t PB_A_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_A_LINKS] = { 40, 48, 56 };
-const uint32_t PB_A_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_A_LINKS]   = { 47, 55, 63 };
-
-// PB A Link Framer Configuration register field/bit definitions
-const uint32_t PB_A_FMR_CFG_OW_PACK_BIT = 24;
-const uint32_t PB_A_FMR_CFG_OW_PACK_PRIORITY_BIT = 25;
-
-// PB IOF Link Mode register field/bit definitions
-const uint32_t PB_IOF_MODE_LINK_DELAY_START_BIT[PROC_FAB_SMP_NUM_F_LINKS] = { 32, 48 };
-const uint32_t PB_IOF_MODE_LINK_DELAY_END_BIT[PROC_FAB_SMP_NUM_F_LINKS]   = { 47, 63 };
-
-// PB F Link Framer Configuration register field/bit definitions
-const uint32_t PB_F_FMR_CFG_OW_PACK_BIT = 20;
-const uint32_t PB_F_FMR_CFG_OW_PACK_PRIORITY_BIT = 21;
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: read PB A Link Framer Configuration register and determine
-//           OW packing setup
-// parameters: i_smp_chip        => structure encapsulating SMP chip
-//             o_owpack          => OW packing enabled?
-//             o_owpack_priority => OW pack priority enabled?
-// returns: FAPI_RC_SUCCESS if SCOM is successful & output pack values are
-//              valid,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_get_a_owpack_config(
-    const proc_build_smp_chip& i_smp_chip,
-    bool & o_owpack,
-    bool & o_owpack_priority)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_get_a_owpack_config: Start");
-
-    do
-    {
-        // read PB A Link Framer Configuration register
-        rc = fapiGetScom(i_smp_chip.chip->this_chip,
-                         PB_A_FMR_CFG_0x08010813,
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_get_a_owpack_config: fapiGetScom error (PB_A_FMR_CFG_0x08010813)");
-            break;
-        }
-
-        // set outputs
-        o_owpack = data.isBitSet(PB_A_FMR_CFG_OW_PACK_BIT);
-        o_owpack_priority = data.isBitSet(PB_A_FMR_CFG_OW_PACK_PRIORITY_BIT);
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_get_a_owpack_config: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: read PB F Link Framer Configuration register and determine
-//           OW packing setup
-// parameters: i_smp_chip        => structure encapsulating SMP chip
-//             o_owpack          => OW packing enabled?
-//             o_owpack_priority => OW pack priority enabled?
-// returns: FAPI_RC_SUCCESS if SCOM is successful & output pack values are
-//              valid,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_get_f_owpack_config(
-    const proc_build_smp_chip& i_smp_chip,
-    bool & o_owpack,
-    bool & o_owpack_priority)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_get_f_owpack_config: Start");
-
-    do
-    {
-        // read PB F Link Framer Configuration register
-        rc = fapiGetScom(i_smp_chip.chip->this_chip,
-                         PB_F_FMR_CFG_0x09010813,
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_get_f_owpack_config: fapiGetScom error (PB_F_FMR_CFG_0x09010813)");
-            break;
-        }
-
-        // set outputs
-        o_owpack = data.isBitSet(PB_F_FMR_CFG_OW_PACK_BIT);
-        o_owpack_priority = data.isBitSet(PB_F_FMR_CFG_OW_PACK_PRIORITY_BIT);
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_get_f_owpack_config: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: read PB Link Mode register and extract per-link training delays
-// parameters: i_smp_chip            => structure encapsulating SMP chip
-//             i_num_links           => number of links to process
-//             i_scom_addr           => address for SCOM register containing link
-//                                      delay values
-//             i_link_delay_start    => per-link delay field start bit offsets
-//             i_link_delay_end      => per-link delay field end bit offsets
-//             i_link_en             => per-link enable values
-//             i_link_target         => link endpoint targets
-//             o_link_delay_local    => array of link round trip delay values
-//                                      (measured by local chip)
-//             o_link_delay_remote   => array of link round trip delay values
-//                                      (measured by remote chips)
-//             o_link_number_remote  => array of link numbers
-// returns: FAPI_RC_SUCCESS if SCOM is successful & output link delays are
-//              valid,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_get_link_delays(
-    const proc_build_smp_chip& i_smp_chip,
-    const uint8_t i_num_links,
-    const uint32_t i_scom_addr,
-    const uint32_t i_link_delay_start[],
-    const uint32_t i_link_delay_end[],
-    const bool i_link_en[],
-    fapi::Target* i_link_target[],
-    uint16_t o_link_delay_local[],
-    uint16_t o_link_delay_remote[],
-    uint8_t o_link_number_remote[])
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_get_link_delays: Start");
-
-    do
-    {
-        // read PB Link Mode register on local chip
-        rc = fapiGetScom(i_smp_chip.chip->this_chip,
-                         i_scom_addr,
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_get_link_delays: fapiGetScom error (%08X)",
-                     i_scom_addr);
-            break;
-        }
-
-        // extract & return link training delays
-        for (uint8_t l = 0; l < i_num_links; l++)
-        {
-            if (!i_link_en[l])
-            {
-                o_link_delay_local[l] = 0xFF;
-            }
-            else
-            {
-               rc_ecmd |= data.extractToRight(
-                   &(o_link_delay_local[l]),
-                   i_link_delay_start[l],
-                   (i_link_delay_end[l]-
-                    i_link_delay_start[l]+1));
-               
-               if (rc_ecmd)
-               {
-                   FAPI_ERR("proc_build_smp_get_link_delays: Error 0x%x accessing data buffer",
-                            rc_ecmd);
-                   rc.setEcmdError(rc_ecmd);
-                   break;
-               }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // process remote links
-        for (uint8_t l = 0; l < i_num_links; l++)
-        {
-            if (!i_link_en[l])
-            {
-                o_link_delay_remote[l] = 0xFF;
-            }
-            else
-            {
-                fapi::Target parent_target;
-                uint8_t remote_link_number = 0x0;
-                
-                // determine link number on remote end (equivalent to chiplet #)
-                rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,
-                                   i_link_target[l],
-                                   remote_link_number);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_get_link_delays: Error querying ATTR_CHIP_UNIT_POS");
-                    break;
-                }
-                o_link_number_remote[l] = remote_link_number;
-                
-                // obtain parent chip target
-                rc = fapiGetParentChip(*(i_link_target[l]),
-                                       parent_target);
-                
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_get_link_delays: Error from fapiGetParentChip");
-                    break;
-                }
-                
-                // read PB link Mode Register using parent target
-                rc = fapiGetScom(parent_target,
-                                 i_scom_addr,
-                                 data);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_get_link_delays: fapiGetScom error (%08X)",
-                             i_scom_addr);
-                    break;
-                }
-                
-                // extract proper data
-                rc_ecmd |= data.extractToRight(
-                    &(o_link_delay_remote[l]),
-                    i_link_delay_start[remote_link_number],
-                    (i_link_delay_end[remote_link_number]-
-                     i_link_delay_start[remote_link_number]+1));
-                
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("proc_build_smp_get_link_delays: Error 0x%x accessing data buffer",
-                             rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_get_link_delays: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: determine paramters of link/destination chip
-// parameters: i_smp_chip            => structure encapsulating SMP chip
-//             i_source_link_id      => link identifier for FFDC
-//             i_dest_target         => pointer to destination link endpoint target
-//             o_link_is_enabled     => true=link enabled, false=link disabled
-//             o_dest_target_node_id => node ID of destination chip
-//             o_dest_target_chip_id => chip ID of destination chip
-// returns: FAPI_RC_SUCCESS if output values are valid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_query_link_state(
-    const proc_build_smp_chip& i_smp_chip,
-    const uint8_t i_source_link_id,
-    fapi::Target* i_dest_target,
-    bool& o_link_is_enabled,
-    proc_fab_smp_node_id& o_dest_target_node_id,
-    proc_fab_smp_chip_id& o_dest_target_chip_id)
-{
-    fapi::ReturnCode rc;
-    fapi::TargetType dest_target_type = i_dest_target->getType();
-    bool src_link_region_pg = false;
-    uint8_t src_link_chiplet_id = 0xFF;
-
-    FAPI_DBG("proc_build_smp_query_link_state: Start");
-
-    do
-    {
-        switch (dest_target_type)
-        {
-            case (fapi::TARGET_TYPE_NONE):
-                o_link_is_enabled = false;
-                o_dest_target_node_id = FBC_NODE_ID_0;
-                o_dest_target_chip_id = FBC_CHIP_ID_0;
-                break;
-            case (fapi::TARGET_TYPE_ABUS_ENDPOINT):
-            case (fapi::TARGET_TYPE_XBUS_ENDPOINT):
-                // destination target is valid, so mark link as enabled
-                o_link_is_enabled = true;
-        
-                // extract chip/node ID from destination chip
-                rc = proc_fab_smp_get_node_id_attr(i_dest_target, o_dest_target_node_id);
-                if (rc)
-                {
-                    FAPI_ERR("proc_build_smp_query_link_state: Error from proc_fab_smp_get_node_id_attr");
-                    break;
-                }
-        
-                rc = proc_fab_smp_get_chip_id_attr(i_dest_target, o_dest_target_chip_id);
-                if (rc)
-                {
-                    FAPI_ERR("proc_build_smp_query_link_state: Error from proc_fab_smp_get_chip_id_attr");
-                    break;
-                }
-        
-                // perform partial good attribute checking
-                // ABUS
-                if (dest_target_type == fapi::TARGET_TYPE_ABUS_ENDPOINT)
-                {
-                    src_link_region_pg = i_smp_chip.a_enabled;
-                    src_link_chiplet_id = 0x8;
-                }
-                // XBUS
-                else
-                {
-                    src_link_region_pg = i_smp_chip.x_enabled;
-                    src_link_chiplet_id = 0x4;
-                }
-
-                // destination target is valid, but region on source chip containing
-                // connected link logic is not enabled, given state of partial good
-                // attributes
-                if (!src_link_region_pg)
-                {
-                    // obtain VPD partial good attribute for FFDC
-                    uint64_t src_link_region_pg_attr[32];
-                    rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE,
-                                       &(i_smp_chip.chip->this_chip),
-                                       src_link_region_pg_attr);
-                
-                    FAPI_ERR("proc_build_smp_query_link_state: Partial good attribute error (chiplet ID = 0x%02X)",
-                             src_link_chiplet_id);
-                    const fapi::Target& SOURCE_CHIP_TARGET = i_smp_chip.chip->this_chip;
-                    const uint8_t& CHIPLET_ID = src_link_chiplet_id;
-                    const uint8_t& SOURCE_LINK_ID = i_source_link_id;
-                    const bool& REGION_ENABLED = src_link_region_pg;
-                    const uint64_t& REGIONS_TO_ENABLE = src_link_region_pg_attr[src_link_chiplet_id];
-                    const bool& REGIONS_TO_ENABLE_VALID = rc.ok();
-                    const fapi::Target& DEST_LINK_TARGET = *(i_dest_target);
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR);
-                    break;
-                }
-                break;
-            default:
-                FAPI_ERR("proc_build_smp_query_link_state: Unsupported destination link target type!");
-                const fapi::Target& SOURCE_CHIP_TARGET = i_smp_chip.chip->this_chip;
-                const uint8_t& SOURCE_LINK_ID = i_source_link_id;
-                const fapi::Target& DEST_LINK_TARGET = *(i_dest_target);
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR);
-                break;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_build_smp_query_link_state: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: determine link address/data & aggregate mode setup
-// parameters: i_smp_chip         => structure encapsulating SMP chip
-//             i_num_links        => number of links to process
-//             i_num_ids          => maximum number of ID values
-//             i_scom_addr        => address for SCOM register containing link
-//                                   delay values
-//             i_link_delay_start => per-link delay field start bit offsets
-//             i_link_delay_end   => per-link delay field end bit offsets
-//             i_link_en          => per-link enable values
-//             i_link_id          => per-link destination chip/node ID values
-//             i_link_target      => per-link destination targets
-//             i_allow_aggregate  => permit aggregate configuration?
-//             i_x_not_a          => link type (true=X, false=A)
-//             o_link_addr_dis    => per-link address disable values
-//                                   (true=address only, false=address/data)
-//             o_link_aggregate   => enable aggregate link mode?
-// returns: FAPI_RC_SUCCESS if output values are valid,
-//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
-//              specifies invalid aggregate link setup,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_calc_link_setup(
-    const proc_build_smp_chip& i_smp_chip,
-    const uint8_t i_num_links,
-    const uint8_t i_num_ids,
-    const uint32_t i_scom_addr,
-    const uint32_t i_link_delay_start[],
-    const uint32_t i_link_delay_end[],
-    const bool i_link_en[],
-    const uint8_t i_link_id[],
-    fapi::Target * i_link_target[],
-    const bool i_allow_aggregate,
-    const bool i_x_not_a,
-    bool o_link_addr_dis[],
-    bool &o_link_aggregate)
-{
-    fapi::ReturnCode rc;
-    // mark number of links targeting each ID
-    uint8_t id_active_count[i_num_ids];
-    // link round trip delay values
-    uint16_t link_delay_local[i_num_links];
-    uint16_t link_delay_remote[i_num_links];
-    uint8_t link_number_remote[i_num_links];
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_calc_link_setup: Start");
-
-    do
-    {
-        // init local arrays
-        for (uint8_t id = 0; id < i_num_ids; id++)
-        {
-            id_active_count[id] = 0;
-        }
-
-        // process all links
-        for (uint8_t l = 0; l < i_num_links; l++)
-        {
-            // mark link ID
-            if (i_link_en[l])
-            {
-                id_active_count[i_link_id[l]]++;
-            }
-            // set default value for link address disable (enable coherency)
-            o_link_addr_dis[l] = false;
-        }
-
-        // calculate aggregate setting, check for errors
-        o_link_aggregate = false;
-        for (uint8_t id = 0; id < i_num_ids; id++)
-        {
-            // more than one link pointed at current destination ID
-            if (id_active_count[id] > 1)
-            {
-                // design only supports one set of aggregate links per chip
-                // currently procedure does not support aggregate F links
-                if (!i_allow_aggregate || o_link_aggregate)
-                {
-                    uint8_t first_id = 0;
-                    for (first_id = 0; first_id < id; first_id++)
-                    {
-                        if (id_active_count[first_id] > 1)
-                        {
-                            break;
-                        }
-                    }
-
-                    FAPI_ERR("proc_build_smp_calc_link_setup: Invalid aggregate link configuration");
-                    const fapi::Target& TARGET = i_smp_chip.chip->this_chip;
-                    const bool& X_NOT_A = i_x_not_a;
-                    const bool& ALLOW_AGGREGATE = i_allow_aggregate;
-                    const uint8_t& AGGREGATE_DEST_ID1 = first_id;
-                    const uint8_t& AGGREGATE_DEST_ID2 = id;
-                    FAPI_SET_HWP_ERROR(
-                        rc,
-                        RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR);
-                    break;
-                }
-                o_link_aggregate = true;
-
-                // flip default value for link address disable
-                // (disable coherency)
-                for (uint8_t l = 0; l < i_num_links; l++)
-                {
-                    if (i_link_en[l])
-                    {
-                        o_link_addr_dis[l] = true;
-                    }
-                }
-
-                // select link with the lowest round trip latency value
-                // to carry coherency
-                rc = proc_build_smp_get_link_delays(i_smp_chip,
-                                                    i_num_links,
-                                                    i_scom_addr,
-                                                    i_link_delay_start,
-                                                    i_link_delay_end,
-                                                    i_link_en,
-                                                    i_link_target,
-                                                    link_delay_local,
-                                                    link_delay_remote,
-                                                    link_number_remote);
-                if (rc)
-                {
-                    FAPI_ERR("proc_build_smp_calc_link_setup: Error from proc_build_smp_get_link_delays");
-                    break;
-                }
-
-                for (uint8_t l = 0; l < i_num_links; l++)
-                {
-                    FAPI_DBG("proc_build_smp_calc_link_setup: link_delay_local[%d]: %d", l, link_delay_local[l]);
-                }
-                for (uint8_t l = 0; l < i_num_links; l++)
-                {
-                    FAPI_DBG("proc_build_smp_calc_link_setup: link_delay_remote[%d]: %d", l, link_delay_remote[l]);
-                }
-                for (uint8_t l = 0; l < i_num_links; l++)
-                {
-                    FAPI_DBG("proc_build_smp_calc_link_setup: link_number_remote[%d]: %d", l, link_number_remote[l]);
-                }
-
-                // sum local/remote delay factors & scan for smallest value
-                uint32_t link_delay_total[i_num_links];
-                uint8_t coherent_link_index = 0xFF;
-                uint32_t coherent_link_delay = 0xFFFFFFFF;
-                for (uint8_t l = 0; l < i_num_links; l++)
-                {
-                    link_delay_total[l] = link_delay_local[l] + link_delay_remote[l];
-                    if (i_link_en[l] &&
-                        (link_delay_total[l] < coherent_link_delay))
-                    {
-                        coherent_link_delay = link_delay_total[l];
-                        FAPI_DBG("proc_build_smp_calc_link_setup: Setting coherent_link_delay = %d", coherent_link_delay);
-                    }
-                }
-
-                // ties must be broken consistently on both connected chips
-                // search if a tie has occurred
-                uint8_t matches = 0;
-                for (uint8_t l = 0; l < i_num_links; l++)
-                {
-                    if (i_link_en[l] &&
-                        (link_delay_total[l] == coherent_link_delay))
-                    {
-                        matches++;
-                        coherent_link_index = l;
-                    }
-                }
-
-                // if no ties, we're done
-                // mark lowest aggregate latency link as coherent link
-                // else, break tie
-                // select link with lowest link number on chip with smaller ID
-                // (chip ID if X links, node ID if A links)
-                uint8_t id_local = ((i_x_not_a)?((uint8_t) i_smp_chip.chip_id):((uint8_t) i_smp_chip.node_id));
-                if (matches != 1)
-                {
-                    FAPI_DBG("proc_build_smp_calc_link_setup: Breaking tie");
-                    if (id_local < id)
-                    {
-                        for (uint8_t l = 0; l < i_num_links; l++)
-                        {
-                            if (i_link_en[l] &&
-                                (link_delay_total[l] == coherent_link_delay))
-                            {
-                                coherent_link_index = l;
-                                break;
-                            }
-                        }
-                        FAPI_DBG("proc_build_smp_calc_link_setup: Selecting coherent link = link %d baaed on this chip (%d)", coherent_link_index, id_local);
-                    }
-                    else
-                    {
-                        uint8_t lowest_remote_link_number = 0xFF;
-                        for (uint8_t l = 0; l < i_num_links; l++)
-                        {
-                            if ((i_link_en[l]) &&
-                                (link_delay_total[l] == coherent_link_delay) &&
-                                (link_number_remote[l] < lowest_remote_link_number))
-                            {
-                                lowest_remote_link_number= link_number_remote[l];
-                                coherent_link_index = l;
-                            }
-                        }
-                        FAPI_DBG("proc_build_smp_calc_link_setup: Selecting coherent link = linkd %d based on remote chip ID (%d)", coherent_link_index, id);
-                    }
-                }
-                o_link_addr_dis[coherent_link_index] = false;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_calc_link_setup: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to calculate X link reflected command rate
-// parameters: i_freq_x      => X-bus frequency
-//             i_freq_pb     => PB frequency
-//             i_x_is_8B     => boolean representing X bus width
-//                              (true=8B, false=4B)
-//             i_x_aggregate => X aggregate mode enabled?
-//             o_x_cmd_rate  => output X link command rate
-// returns: FAPI_RC_SUCCESS if output command rate is in range,
-//          else RC_PROC_BUILD_SMP_X_CMD_RATE_ERR
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_calc_x_cmd_rate(
-    const uint32_t i_freq_x,
-    const uint32_t i_freq_pb,
-    const bool i_x_is_8B,
-    const bool i_x_aggregate,
-    uint8_t & o_x_cmd_rate)
-{
-    fapi::ReturnCode rc;
-    uint32_t n = i_freq_pb;
-    uint32_t d = i_freq_x / 2;
-    uint32_t cmd_rate;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_calc_x_cmd_rate: Start");
-
-    do
-    {
-        if (i_x_is_8B)
-        {
-            d *= 2;
-        }
-
-        if (i_x_aggregate)
-        {
-            n *= 5;
-        }
-        else
-        {
-            n *= 7;
-        }
-
-        cmd_rate = proc_build_smp_round_ceiling(n, d);
-        if ((cmd_rate < PB_HPX_MODE_X_CMD_RATE_MIN_VALUE) ||
-            (cmd_rate > PB_HPX_MODE_X_CMD_RATE_MAX_VALUE))
-        {
-            FAPI_ERR("proc_build_smp_calc_x_cmd_rate: X link command rate is out of range");
-            const uint32_t& FREQ_PB = i_freq_pb;
-            const uint32_t& FREQ_X = i_freq_x;
-            const bool& X_IS_8B = i_x_is_8B;
-            const bool& X_AGGREGATE = i_x_aggregate;
-            const uint32_t& N = n;
-            const uint32_t& D = d;
-            const uint32_t& CMD_RATE = cmd_rate;
-            const uint32_t& MIN_CMD_RATE = PB_HPX_MODE_X_CMD_RATE_MIN_VALUE;
-            const uint32_t& MAX_CMD_RATE = PB_HPX_MODE_X_CMD_RATE_MAX_VALUE;
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_BUILD_SMP_X_CMD_RATE_ERR);
-            break;
-        }
-    } while(0);
-
-    o_x_cmd_rate = (uint8_t) cmd_rate;
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_calc_x_cmd_rate: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to calculate A link reflected command rate
-// parameters: i_freq_a             => A-bus frequency
-//             i_freq_pb            => PB frequency
-//             i_a_ow_pack          => A link OW packing enabled?
-//             i_a_ow_pack_priority => A link OW packing priority set?
-//             i_a_aggregate        => A aggregate mode enabled?
-//             o_a_cmd_rate         => output A link command rate
-// returns: FAPI_RC_SUCCESS if output command rate is in range,
-//          else RC_PROC_BUILD_SMP_A_CMD_RATE_ERR
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_calc_a_cmd_rate(
-    const uint32_t i_freq_a,
-    const uint32_t i_freq_pb,
-    const bool i_a_ow_pack,
-    const bool i_a_ow_pack_priority,
-    const bool i_a_aggregate,
-    uint8_t & o_a_cmd_rate)
-{
-    fapi::ReturnCode rc;
-    uint32_t n = i_freq_pb;
-    uint32_t d = i_freq_a / 4;
-    uint32_t n_ow_pack = 0;
-    uint32_t cmd_rate;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_calc_a_cmd_rate: Start");
-
-    do
-    {
-        if (i_a_ow_pack)
-        {
-            n_ow_pack = (i_a_ow_pack_priority?1:0) + 3;
-        }
-        if (i_a_aggregate)
-        {
-            n_ow_pack += 3;
-        }
-        else
-        {
-            n_ow_pack += 4;
-        }
-
-        n *= (2 * n_ow_pack);
-
-        cmd_rate = proc_build_smp_round_ceiling(n, d);
-        if ((cmd_rate < PB_HP_MODE_A_CMD_RATE_MIN_VALUE) ||
-            (cmd_rate > PB_HP_MODE_A_CMD_RATE_MAX_VALUE))
-        {
-            FAPI_ERR("proc_build_smp_calc_a_cmd_rate: A link command rate is out of range");
-            const uint32_t& FREQ_PB = i_freq_pb;
-            const uint32_t& FREQ_A = i_freq_a;
-            const bool& A_OW_PACK = i_a_ow_pack;
-            const bool& A_OW_PACK_PRIORITY = i_a_ow_pack_priority;
-            const bool& A_AGGREGATE = i_a_aggregate;
-            const uint32_t& N = n;
-            const uint32_t& D = d;
-            const uint32_t& CMD_RATE = cmd_rate;
-            const uint32_t& MIN_CMD_RATE = PB_HP_MODE_A_CMD_RATE_MIN_VALUE;
-            const uint32_t& MAX_CMD_RATE = PB_HP_MODE_A_CMD_RATE_MAX_VALUE;
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_BUILD_SMP_A_CMD_RATE_ERR);
-            break;
-        }
-    } while(0);
-
-    o_a_cmd_rate = (uint8_t) cmd_rate;
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_calc_a_cmd_rate: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to calculate F link reflected command rate
-// parameters: i_freq_f             => F-bus frequency
-//             i_freq_pb            => PB frequency
-//             i_f_ow_pack          => F link OW packing enabled?
-//             i_f_ow_pack_priority => F link OW packing priority set?
-//             i_f_aggregate        => F aggregate mode enabled?
-//             o_f_cmd_rate         => output F link command rate
-// returns: FAPI_RC_SUCCESS if output command rate is in range,
-//          else RC_PROC_BUILD_SMP_F_CMD_RATE_ERR
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_calc_f_cmd_rate(
-    const uint32_t i_freq_f,
-    const uint32_t i_freq_pb,
-    const bool i_f_ow_pack,
-    const bool i_f_ow_pack_priority,
-    const bool i_f_aggregate,
-    uint8_t & o_f_cmd_rate)
-{
-    fapi::ReturnCode rc;
-    uint32_t n = i_freq_pb;
-    uint32_t d = i_freq_f;
-    uint32_t n_ow_pack = 0;
-    uint32_t cmd_rate;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_calc_f_cmd_rate: Start");
-
-    do
-    {
-        if (i_f_ow_pack)
-        {
-            n_ow_pack = (i_f_ow_pack_priority?1:0) + 3;
-        }
-        if (i_f_aggregate)
-        {
-            n_ow_pack += 3;
-            n_ow_pack *= 30;
-        }
-        else
-        {
-            n_ow_pack += 4;
-            n_ow_pack *= 29;
-        }
-
-        n *= (2 * n_ow_pack);
-        d *= 25;
-
-        cmd_rate = proc_build_smp_round_ceiling(n, d);
-        if ((cmd_rate < PB_HP_MODE_F_CMD_RATE_MIN_VALUE) ||
-            (cmd_rate > PB_HP_MODE_F_CMD_RATE_MAX_VALUE))
-        {
-            FAPI_ERR("proc_build_smp_calc_f_cmd_rate: F link command rate is out of range");
-            const uint32_t& FREQ_PB = i_freq_pb;
-            const uint32_t& FREQ_F = i_freq_f;
-            const bool& F_OW_PACK = i_f_ow_pack;
-            const bool& F_OW_PACK_PRIORITY = i_f_ow_pack_priority;
-            const bool& F_AGGREGATE = i_f_aggregate;
-            const uint32_t& N = n;
-            const uint32_t& D = d;
-            const uint32_t& CMD_RATE = cmd_rate;
-            const uint32_t& MIN_CMD_RATE = PB_HP_MODE_F_CMD_RATE_MIN_VALUE;
-            const uint32_t& MAX_CMD_RATE = PB_HP_MODE_F_CMD_RATE_MAX_VALUE;
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_BUILD_SMP_F_CMD_RATE_ERR);
-            break;
-        }
-
-    } while(0);
-
-    o_f_cmd_rate = (uint8_t) cmd_rate;
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_calc_f_cmd_rate: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to program set of PB hotplug registers
-// parameters: i_smp_chip      => structure encapsulating SMP chip
-//             i_curr_not_next => choose CURR/NEXT register set (true=CURR,
-//                                false=NEXT)
-//             i_hp_not_hpx    => choose HP/HPX register set (true=HP,
-//                                false=HPX)
-//             i_data          => data buffer containing write data
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_hotplug_reg(
-    const proc_build_smp_chip& i_smp_chip,
-    const bool i_curr_not_next,
-    const bool i_hp_not_hpx,
-    ecmdDataBufferBase& i_data)
-{
-    fapi::ReturnCode rc;
-    uint32_t scom_addr;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_hotplug_reg: Start");
-
-    // write west/center/east register copies
-    for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
-    {
-        // set target scom address based on input parameters
-        if (i_curr_not_next)
-        {
-            if (i_hp_not_hpx)
-            {
-                scom_addr = PB_HP_MODE_CURR_SHADOWS[r];
-            }
-            else
-            {
-                scom_addr = PB_HPX_MODE_CURR_SHADOWS[r];
-            }
-        }
-        else
-        {
-            if (i_hp_not_hpx)
-            {
-                scom_addr = PB_HP_MODE_NEXT_SHADOWS[r];
-            }
-            else
-            {
-                scom_addr = PB_HPX_MODE_NEXT_SHADOWS[r];
-            }
-        }
-
-        // write register
-        rc = fapiPutScom(i_smp_chip.chip->this_chip,
-                         scom_addr,
-                         i_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_hotplug_reg: fapiPutScom error (%08X)",
-                     scom_addr);
-            break;
-        }
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_hotplug_reg: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg(
-    const proc_build_smp_chip& i_smp_chip,
-    const bool i_hp_not_hpx,
-    ecmdDataBufferBase& o_data)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_get_hotplug_curr_reg: Start");
-
-    // check consistency of west/center/east register copies
-    for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
-    {
-        // get current (working) register
-        rc = fapiGetScom(i_smp_chip.chip->this_chip,
-                         ((i_hp_not_hpx)?
-                          (PB_HP_MODE_CURR_SHADOWS[r]):
-                          (PB_HPX_MODE_CURR_SHADOWS[r])),
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_get_hotplug_curr_reg: fapiGetScom error (%08X)",
-                     ((i_hp_not_hpx)?
-                      (PB_HP_MODE_CURR_SHADOWS[r]):
-                      (PB_HPX_MODE_CURR_SHADOWS[r])));
-            break;
-        }
-
-        // raise error if shadow copies aren't equal
-        if ((r != 0) &&
-            (o_data != data))
-        {
-            FAPI_ERR("proc_build_smp_get_hotplug_curr_reg: Shadow copies are not equivalent");
-            const uint32_t& ADDRESS0 = ((i_hp_not_hpx)?
-                                        (PB_HP_MODE_CURR_SHADOWS[r-1]):
-                                        (PB_HPX_MODE_CURR_SHADOWS[r-1]));
-            const uint32_t& ADDRESS1 = ((i_hp_not_hpx)?
-                                        (PB_HP_MODE_CURR_SHADOWS[r]):
-                                        (PB_HPX_MODE_CURR_SHADOWS[r]));
-            const uint64_t& DATA0 = o_data.getDoubleWord(0);
-            const uint64_t& DATA1 = data.getDoubleWord(0);
-            FAPI_SET_HWP_ERROR(
-                rc,
-                RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR);
-            break;
-        }
-
-        // set output (will be used to compare with next HW read)
-        rc_ecmd |= data.copy(o_data);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_get_hotplug_curr_reg: Error 0x%x copying register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_get_hotplug_curr_reg: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: reset (copy CURR->NEXT) PB Hotplug Mode/Mode Extension register
-// parameters: i_smp_chip   => structure encapsulating SMP chip
-//             i_hp_not_hpx => choose HP/HPX register set (true=HP,
-//                             false=HPX)
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
-//              equivalent,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_reset_hotplug_next_reg(
-    const proc_build_smp_chip& i_smp_chip,
-    const bool i_hp_not_hpx)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_reset_hotplug_next_reg: Start");
-
-    do
-    {
-        // read CURR state
-        rc = proc_build_smp_get_hotplug_curr_reg(i_smp_chip,
-                                                 i_hp_not_hpx,
-                                                 data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_reset_hotplug_next_reg: proc_build_smp_get_hotplug_curr_reg");
-            break;
-        }
-
-        // write NEXT state
-        rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
-                                            false,
-                                            i_hp_not_hpx,
-                                            data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_reset_hotplug_next_reg: proc_build_smp_set_hotplug_reg");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_reset_hotplug_next_reg: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB Hotplug Mode register
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP topology
-//             i_set_curr => set CURR register set?
-//             i_set_next => set NEXT register set?
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
-//              specifies invalid aggregate link setup,
-//          RC_PROC_BUILD_SMP_A_CMD_RATE_ERR if calculated A link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_pb_hp_mode(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp,
-    const bool i_set_curr,
-    const bool i_set_next)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    // set of per-link destination chip targets
-    fapi::Target * a_target[PROC_FAB_SMP_NUM_A_LINKS];
-    fapi::Target * f_target[PROC_FAB_SMP_NUM_F_LINKS];
-    // per-link enables
-    bool a_en[PROC_FAB_SMP_NUM_A_LINKS];
-    bool f_en[PROC_FAB_SMP_NUM_F_LINKS];
-    // per-link destination IDs
-    uint8_t a_id[PROC_FAB_SMP_NUM_A_LINKS];
-    uint8_t f_id[PROC_FAB_SMP_NUM_F_LINKS];
-    // per-link address disable values
-    bool a_addr_dis[PROC_FAB_SMP_NUM_A_LINKS] = { false, false, false };
-    bool f_addr_dis[PROC_FAB_SMP_NUM_F_LINKS] = { false, false };
-    // aggregate link settings
-    bool a_link_aggregate = false;
-    bool f_link_aggregate = false;
-    // link ow pack settings
-    bool a_link_owpack = false;
-    bool a_link_owpack_priority = false;
-    bool f_link_owpack = false;
-    bool f_link_owpack_priority = false;
-    // link command rates
-    uint8_t a_cmd_rate = 0x00;
-    uint8_t f_cmd_rate = 0x00;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_pb_hp_mode: Start");
-
-    do
-    {
-        // process all A links
-        a_target[0] = &(i_smp_chip.chip->a0_chip);
-        a_target[1] = &(i_smp_chip.chip->a1_chip);
-        a_target[2] = &(i_smp_chip.chip->a2_chip);
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_A_LINKS; l++)
-        {
-            // determine link enable/ID
-            proc_fab_smp_node_id dest_node_id;
-            proc_fab_smp_chip_id dest_chip_id;
-            rc = proc_build_smp_query_link_state(i_smp_chip,
-                                                 l,
-                                                 a_target[l],
-                                                 a_en[l],
-                                                 dest_node_id,
-                                                 dest_chip_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_query_link_state");
-                break;
-            }
-            a_id[l] = (uint8_t) dest_node_id;
-        }
-        if (rc)
-        {
-            break;
-        }
-
-
-        // process all F links
-        f_en[0] = i_smp_chip.chip->enable_f0;
-        f_id[0] = i_smp_chip.chip->f0_node_id;
-        f_en[1] = i_smp_chip.chip->enable_f1;
-        f_id[1] = i_smp_chip.chip->f1_node_id;
-        f_target[0] = NULL;
-        f_target[1] = NULL;
-
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
-        {
-            if (f_en[l] && !i_smp_chip.pcie_enabled)
-            {
-                // obtain partial good attribute for FFDC
-                uint8_t src_link_chiplet_id = 0x9;
-                uint64_t src_link_region_pg_attr[32];
-                rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE,
-                                   &(i_smp_chip.chip->this_chip),
-                                   src_link_region_pg_attr);
-
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Partial good attribute error (PCIE)");
-                const fapi::Target& SOURCE_CHIP_TARGET = i_smp_chip.chip->this_chip;
-                const uint8_t& CHIPLET_ID = src_link_chiplet_id;
-                const uint8_t& SOURCE_LINK_ID = l;
-                const bool& REGION_ENABLED = i_smp_chip.pcie_enabled;
-                const uint64_t& REGIONS_TO_ENABLE = src_link_region_pg_attr[src_link_chiplet_id];
-                const bool& REGIONS_TO_ENABLE_VALID = rc.ok();
-                const uint8_t& DEST_NODE_ID = f_id[l];
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR);
-                break;
-            }
-        }
-        if (rc)
-        {
-            break;
-        }
-
-        // determine address/data assignents, aggregate mode programming &
-        // link command rates (A)
-        if (i_smp_chip.a_enabled)
-        {
-            rc = proc_build_smp_calc_link_setup(i_smp_chip,
-                                                PROC_FAB_SMP_NUM_A_LINKS,
-                                                PROC_FAB_SMP_NUM_NODE_IDS,
-                                                PB_A_MODE_0x0801080A,
-                                                PB_A_MODE_LINK_DELAY_START_BIT,
-                                                PB_A_MODE_LINK_DELAY_END_BIT,
-                                                a_en,
-                                                a_id,
-                                                a_target,
-                                                true,
-                                                false,
-                                                a_addr_dis,
-                                                a_link_aggregate);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (A)");
-                break;
-            }
-
-            rc = proc_build_smp_get_a_owpack_config(i_smp_chip,
-                                                    a_link_owpack,
-                                                    a_link_owpack_priority);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_a_owpack_config");
-                break;
-            }
-
-            rc = proc_build_smp_calc_a_cmd_rate(i_smp.freq_a,
-                                                i_smp.freq_pb,
-                                                a_link_owpack,
-                                                a_link_owpack_priority,
-                                                a_link_aggregate,
-                                                a_cmd_rate);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_a_cmd_rate");
-                break;
-            }
-        }
-
-        if (i_smp_chip.pcie_enabled)
-        {
-            // determine address/data assignents, aggregate mode programming &
-            // link command rates (F)
-            rc = proc_build_smp_calc_link_setup(i_smp_chip,
-                                                PROC_FAB_SMP_NUM_F_LINKS,
-                                                PROC_FAB_SMP_NUM_NODE_IDS,
-                                                PB_IOF_MODE_0x09011C0A,
-                                                PB_IOF_MODE_LINK_DELAY_START_BIT,
-                                                PB_IOF_MODE_LINK_DELAY_END_BIT,
-                                                f_en,
-                                                f_id,
-                                                f_target,
-                                                false,
-                                                false,
-                                                f_addr_dis,
-                                                f_link_aggregate);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_link_setup (F)");
-                break;
-            }
-
-            rc = proc_build_smp_get_f_owpack_config(i_smp_chip,
-                                                    f_link_owpack,
-                                                    f_link_owpack_priority);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_get_f_owpack_config");
-                break;
-            }
-
-            rc = proc_build_smp_calc_f_cmd_rate(i_smp.freq_pcie,
-                                                i_smp.freq_pb,
-                                                f_link_owpack,
-                                                f_link_owpack_priority,
-                                                f_link_aggregate,
-                                                f_cmd_rate);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_calc_f_cmd_rate");
-                break;
-            }
-        }
-
-        // build data buffer with per-link values
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_A_LINKS; l++)
-        {
-            // pb_cfg_link_a#_en
-            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_A_EN_BIT[l],
-                                     a_en[l]?1:0);
-
-            // pb_cfg_link_na#_addr_dis
-            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_A_ADDR_DIS_BIT[l],
-                                     a_addr_dis[l]?1:0);
-            // pb_cfg_link_a#_chipid
-            rc_ecmd |= data.insertFromRight(
-                a_id[l],
-                PB_HP_MODE_LINK_A_ID_START_BIT[l],
-                (PB_HP_MODE_LINK_A_ID_END_BIT[l]-
-                 PB_HP_MODE_LINK_A_ID_START_BIT[l]+1));
-        }
-
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
-        {
-            // pb_cfg_link_f#_master
-            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_F_MASTER_BIT[l],
-                                     f_en[l]?1:0);
-
-            // pb_cfg_link_f#_en
-            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_F_EN_BIT[l],
-                                     f_en[l]?1:0);
-
-            // pb_cfg_link_nf#_addr_dis
-            rc_ecmd |= data.writeBit(PB_HP_MODE_LINK_F_ADDR_DIS_BIT[l],
-                                     f_addr_dis[l]?1:0);
-
-            // pb_cfg_link_f#_chipid
-            rc_ecmd |= data.insertFromRight(
-                f_id[l],
-                PB_HP_MODE_LINK_F_ID_START_BIT[l],
-                (PB_HP_MODE_LINK_F_ID_END_BIT[l]-
-                 PB_HP_MODE_LINK_F_ID_START_BIT[l]+1));
-
-            // pb_cfg_p#_x8tok
-            rc_ecmd |= data.writeBit(
-                PB_HP_MODE_PCIE_NOT_DSMP_BIT[l],
-                i_smp_chip.pcie_not_f_link[l]);
-        }
-
-        // pb_cfg_master_chip
-        rc_ecmd |= data.writeBit(PB_HP_MODE_MASTER_CHIP_BIT,
-                                 i_smp_chip.chip->master_chip_sys_next?1:0);
-
-        // pb_cfg_a_aggregate
-        rc_ecmd |= data.writeBit(PB_HP_MODE_A_AGGREGATE_BIT,
-                                 a_link_aggregate?1:0);
-
-        // pb_cfg_tm_master
-        rc_ecmd |= data.writeBit(PB_HP_MODE_TM_MASTER_BIT,
-                                 i_smp_chip.chip->master_chip_sys_next?1:0);
-
-        // pb_cfg_chg_rate_gp_master
-        rc_ecmd |= data.writeBit(PB_HP_MODE_CHG_RATE_GP_MASTER_BIT,
-                                 i_smp_chip.master_chip_node_next?1:0);
-
-        // pb_cfg_chg_rate_sp_master
-        rc_ecmd |= data.writeBit(PB_HP_MODE_CHG_RATE_SP_MASTER_BIT,
-                                 i_smp_chip.chip->master_chip_sys_next?1:0);
-
-        // pb_cfg_pump_mode
-        rc_ecmd |= data.writeBit(PB_HP_MODE_PUMP_MODE_BIT,
-            (i_smp.pump_mode == PROC_FAB_SMP_PUMP_MODE2)?1:0);
-
-        // pb_cfg_single_mc
-        rc_ecmd |= data.writeBit(PB_HP_MODE_SINGLE_MC_BIT,
-            (i_smp.all_mcs_interleaved == false)?1:0);
-
-        // pb_cfg_dcache_capp_mode
-        rc_ecmd |= data.writeBit(PB_HP_MODE_DCACHE_CAPP_MODE_BIT,
-                                 PB_HP_MODE_DCACHE_CAPP_EN?1:0);
-
-        // pb_cfg_a_cmd_rate
-        rc_ecmd |= data.insertFromRight(
-            a_cmd_rate,
-            PB_HP_MODE_A_CMD_RATE_START_BIT,
-            (PB_HP_MODE_A_CMD_RATE_END_BIT-
-             PB_HP_MODE_A_CMD_RATE_START_BIT+1));
-
-        // pb_cfg_a_gather_enable
-        rc_ecmd |= data.writeBit(PB_HP_MODE_A_GATHER_ENABLE_BIT,
-                                 PB_HP_MODE_A_GATHER_ENABLE?1:0);
-
-        // pb_cfg_a_dly_cnt
-        rc_ecmd |= data.insertFromRight(
-            PB_HP_MODE_A_GATHER_DLY_CNT,
-            PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT,
-            (PB_HP_MODE_A_GATHER_DLY_CNT_END_BIT-
-             PB_HP_MODE_A_GATHER_DLY_CNT_START_BIT+1));
-
-        if (i_smp_chip.num_phb > 3)
-        {
-            // pb_cfg_p2_x8tok
-            rc_ecmd |= data.clearBit(PB_HP_MODE_CFG_P2_X8TOK);
-
-            // pb_cfg_p3_x8tok
-            rc_ecmd |= data.clearBit(PB_HP_MODE_CFG_P3_X8TOK);
-
-            // pb_cfg_gather_enable
-            rc_ecmd |= data.writeBit(PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_PRESENT,
-                                     PB_HP_MODE_GATHER_ENABLE?1:0);
-        }
-        else
-        {
-            // pb_cfg_gather_enable
-            rc_ecmd |= data.writeBit(PB_HP_MODE_GATHER_ENABLE_BIT_PCIE3_NOT_PRESENT,
-                                     PB_HP_MODE_GATHER_ENABLE?1:0);
-        }
-
-        // pb_cfg_f_aggregate
-        rc_ecmd |= data.writeBit(PB_HP_MODE_F_AGGREGATE_BIT,
-                                 f_link_aggregate?1:0);
-
-        // pb_cfg_f_cmd_rate
-        rc_ecmd |= data.insertFromRight(
-            f_cmd_rate,
-            PB_HP_MODE_F_CMD_RATE_START_BIT,
-            (PB_HP_MODE_F_CMD_RATE_END_BIT-
-             PB_HP_MODE_F_CMD_RATE_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error 0x%x setting up PB Hotplug Mode register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write current (working) registers
-        if (i_set_curr)
-        {
-            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
-                                                true,
-                                                true,
-                                                data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_set_hotplug_reg (CURR)");
-                break;
-            }
-        }
-
-        // write next (switch) registers
-        if (i_set_next)
-        {
-            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
-                                                false,
-                                                true,
-                                                data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hp_mode: Error from proc_build_smp_set_hotplug_reg (NEXT)");
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_pb_hp_mode: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB Hotplug Extension Mode register
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP topology
-//             i_set_curr => set CURR register set?
-//             i_set_next => set NEXT register set?
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
-//              specifies invalid aggregate link setup,
-//          RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_pb_hpx_mode(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp,
-    const bool i_set_curr,
-    const bool i_set_next)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    // set of per-link destination chip targets
-    fapi::Target * x_target[PROC_FAB_SMP_NUM_X_LINKS];
-    // per-link enables
-    bool x_en[PROC_FAB_SMP_NUM_X_LINKS];
-    // per-link destination IDs
-    uint8_t x_id[PROC_FAB_SMP_NUM_X_LINKS];
-    // per-link address disable values
-    bool x_addr_dis[PROC_FAB_SMP_NUM_X_LINKS] = { false, false, false, false };
-    // aggregate link setting
-    bool x_link_aggregate = false;
-    // link command rate
-    uint8_t x_cmd_rate = 0x00;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_pb_hpx_mode: Start");
-
-    do
-    {
-        // process all links
-        x_target[0] = &(i_smp_chip.chip->x0_chip);
-        x_target[1] = &(i_smp_chip.chip->x1_chip);
-        x_target[2] = &(i_smp_chip.chip->x2_chip);
-        x_target[3] = &(i_smp_chip.chip->x3_chip);
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_X_LINKS; l++)
-        {
-            // determine link enable/ID
-            proc_fab_smp_node_id dest_node_id;
-            proc_fab_smp_chip_id dest_chip_id;
-            rc = proc_build_smp_query_link_state(i_smp_chip,
-                                                 l,
-                                                 x_target[l],
-                                                 x_en[l],
-                                                 dest_node_id,
-                                                 dest_chip_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_query_link_state");
-                break;
-            }
-            x_id[l] = (uint8_t) dest_chip_id;
-        }
-        if (rc)
-        {
-            break;
-        }
-
-        if (i_smp_chip.x_enabled)
-        {
-            // determine address/data assignents & aggregate mode programming
-            rc = proc_build_smp_calc_link_setup(i_smp_chip,
-                                                PROC_FAB_SMP_NUM_X_LINKS,
-                                                PROC_FAB_SMP_NUM_CHIP_IDS,
-                                                PB_X_MODE_0x04010C0A,
-                                                PB_X_MODE_LINK_DELAY_START_BIT,
-                                                PB_X_MODE_LINK_DELAY_END_BIT,
-                                                x_en,
-                                                x_id,
-                                                x_target,
-                                                true,
-                                                true,
-                                                x_addr_dis,
-                                                x_link_aggregate);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_link_setup (X)");
-                break;
-            }
-
-            // determine link command rate
-            rc = proc_build_smp_calc_x_cmd_rate(i_smp.freq_x,
-                                                i_smp.freq_pb,
-                                                i_smp.x_bus_8B,
-                                                x_link_aggregate,
-                                                x_cmd_rate);
-            if (rc)
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_calc_x_cmd_rate");
-                break;
-            }
-        }
-
-        // build data buffer with per-link values
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_X_LINKS; l++)
-        {
-            // pb_cfg_link_x#_en
-            rc_ecmd |= data.writeBit(PB_HPX_MODE_LINK_X_EN_BIT[l],
-                                     x_en[l]?1:0);
-
-            // pb_cfg_link_nx#_addr_dis
-            rc_ecmd |= data.writeBit(PB_HPX_MODE_LINK_X_ADDR_DIS_BIT[l],
-                                     x_addr_dis[l]?1:0);
-
-            // pb_cfg_link_x#_chipid
-            rc_ecmd |= data.insertFromRight(
-                x_id[l],
-                PB_HPX_MODE_LINK_X_CHIPID_START_BIT[l],
-                (PB_HPX_MODE_LINK_X_CHIPID_END_BIT[l]-
-                 PB_HPX_MODE_LINK_X_CHIPID_START_BIT[l]+1));
-        }
-
-        // pb_cfg_x_aggregate
-        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_AGGREGATE_BIT,
-                                 x_link_aggregate);
-
-        // pb_cfg_x_indirect_en
-        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_INDIRECT_EN_BIT,
-                                 PB_HPX_MODE_X_INDIRECT_EN?1:0);
-
-        // pb_cfg_x_gather_enable
-        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_GATHER_ENABLE_BIT,
-                                 PB_HPX_MODE_X_GATHER_ENABLE?1:0);
-
-        // pb_cfg_x_dly_cnt
-        rc_ecmd |= data.insertFromRight(
-            PB_HPX_MODE_X_GATHER_DLY_CNT,
-            PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT,
-            (PB_HPX_MODE_X_GATHER_DLY_CNT_END_BIT-
-             PB_HPX_MODE_X_GATHER_DLY_CNT_START_BIT+1));
-
-        // pb_cfg_x_onnode_12queues
-        rc_ecmd |= data.writeBit(PB_HPX_MODE_X_ONNODE_12QUEUES_BIT,
-                                 PB_HPX_MODE_X_ONNODE_12QUEUES?1:0);
-
-        // pb_cfg_group_eq_chip
-        rc_ecmd |= data.writeBit(PB_HPX_MODE_GROUP_EQ_CHIP_BIT,
-                                 i_smp_chip.nv_present?1:0);
-
-        // pb_cfg_x_cmd_rate
-        rc_ecmd |= data.insertFromRight(
-            x_cmd_rate,
-            PB_HPX_MODE_X_CMD_RATE_START_BIT,
-            (PB_HPX_MODE_X_CMD_RATE_END_BIT-
-             PB_HPX_MODE_X_CMD_RATE_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error 0x%x setting up PB Hotplug Extension Mode register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write current (working) registers
-        if (i_set_curr)
-        {
-            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
-                                                true,
-                                                false,
-                                                data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_set_hotplug_reg (CURR)");
-                break;
-            }
-        }
-
-        // write next (switch) registers
-        if (i_set_next)
-        {
-            rc = proc_build_smp_set_hotplug_reg(i_smp_chip,
-                                                false,
-                                                false,
-                                                data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_hpx_mode: Error from proc_build_smp_set_hotplug_reg (NEXT)");
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_pb_hpx_mode: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_set_fbc_ab(
-    proc_build_smp_system& i_smp,
-    const proc_build_smp_operation i_op)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_fbc_ab: Start");
-
-    do
-    {
-        // quiesce 'slave' fabrics in preparation for joining
-        //   PHASE1 -> quiesce all chips except the chip which is the new fabric master
-        //   PHASE2 -> quiesce all drawers except the drawer containing the new fabric master
-        rc = proc_build_smp_quiesce_pb(i_smp, i_op);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_quiesce_pb");
-            break;
-        }
-
-        // program CURR register set only for chips which were just quiesced
-        // program NEXT register set for all chips
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                rc = proc_build_smp_set_pb_hp_mode(
-                    p_iter->second,
-                    i_smp,
-                    p_iter->second.quiesced_next,
-                    true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_set_pb_hp_mode");
-                    break;
-                }
-
-                rc = proc_build_smp_set_pb_hpx_mode(
-                    p_iter->second,
-                    i_smp,
-                    p_iter->second.quiesced_next,
-                    true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_set_pb_hpx_mode");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // issue switch AB reconfiguration from chip designated as new master
-        // (which is guaranteed to be a master now)
-        rc = proc_build_smp_switch_ab(i_smp, i_op);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_switch_ab");
-            break;
-        }
-
-        // reset NEXT register set (copy CURR->NEXT) for all chips
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                rc = proc_build_smp_reset_hotplug_next_reg(p_iter->second, true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_reset_pb_hp_mode");
-                    break;
-                }
-
-                rc = proc_build_smp_reset_hotplug_next_reg(p_iter->second, false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_ab: Error from proc_build_smp_reset_pb_hpx_mode");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_fbc_ab: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H
deleted file mode 100644
index 115ce8daf..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H
+++ /dev/null
@@ -1,157 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_ab.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_ab.H,v 1.3 2014/02/23 21:41:07 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_ab.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_fbc_ab.H
-// *! DESCRIPTION : Fabric configuration (hotplug, AB) functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BUILD_SMP_FBC_AB_H_
-#define _PROC_BUILD_SMP_FBC_AB_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp.H>
-#include <p8_scom_addresses.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// PB Hotplug Mode register field/bit definitions
-const uint32_t PB_HP_MODE_MASTER_CHIP_BIT = 0;
-const uint32_t PB_HP_MODE_CHG_RATE_GP_MASTER_BIT = 18;
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: determine paramters of link/destination chip
-// parameters: i_smp_chip            => structure encapsulating SMP chip
-//             i_source_link_id      => link identifier for FFDC
-//             i_dest_target         => pointer to destination link endpoint target
-//             o_link_is_enabled     => true=link enabled, false=link disabled
-//             o_dest_target_node_id => node ID of destination chip
-//             o_dest_target_chip_id => chip ID of destination chip
-// returns: FAPI_RC_SUCCESS if output values are valid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_query_link_state(
-    const proc_build_smp_chip& i_smp_chip,
-    const uint8_t i_source_link_id,
-    fapi::Target* i_dest_target,
-    bool& o_link_is_enabled,
-    proc_fab_smp_node_id& o_dest_target_node_id,
-    proc_fab_smp_chip_id& o_dest_target_chip_id);
-
-
-//------------------------------------------------------------------------------
-// function: utility function to read set of PB CURR hotplug registers
-// parameters: i_smp_chip   => structure encapsulating SMP chip
-//             i_hp_not_hpx => choose HP/HPX register set (true=HP,
-//                             false=HPX)
-//             o_data       => data buffer containing read data
-// returns: FAPI_RC_SUCCESS if register reads are successful and all shadow
-//               registers are equivalent,
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
-//              equivalent,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_get_hotplug_curr_reg(
-    const proc_build_smp_chip& i_smp_chip,
-    const bool i_hp_not_hpx,
-    ecmdDataBufferBase& o_data);
-
-
-//------------------------------------------------------------------------------
-// function: program fabric configuration register (hotplug, A/B set)
-// parameters: i_smp => structure encapsulating SMP topology
-//             i_op  => enumerated type representing SMP build phase
-// returns: FAPI_RC_SUCCESS if register reads are successful and all shadow
-//               registers are equivalent,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation
-//              parameters are specified,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
-//              for switch operation,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          RC_PROC_BUILD_SMP_HOTPLUG_SHADOW_ERR if shadow registers are not
-//              equivalent,
-//          RC_PROC_BUILD_SMP_INVALID_AGGREGATE_CONFIG_ERR if configuration
-//              specifies invalid aggregate link setup,
-//          RC_PROC_BUILD_SMP_A_CMD_RATE_ERR if calculated A link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_F_CMD_RATE_ERR if calculated F link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_X_CMD_RATE_ERR if calculated X link command rate
-//              is invalid,
-//          RC_PROC_BUILD_SMP_AX_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_PCIE_PARTIAL_GOOD_ERR if partial good attribute
-//              state does not allow for action on target,
-//          RC_PROC_BUILD_SMP_LINK_TARGET_TYPE_ERR if link target type is
-//              unsupported,
-//          RC_PROC_BUILD_SMP_INVALID_TOPOLOGY if specified fabric topology
-//              is illegal,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_fbc_ab(
-    proc_build_smp_system& i_smp,
-    const proc_build_smp_operation i_op);
-
-} // extern "C"
-
-#endif // _PROC_BUILD_SMP_FBC_AB_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
deleted file mode 100644
index 442661046..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C
+++ /dev/null
@@ -1,2417 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_cd.C,v 1.17 2014/11/16 23:23:37 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_fbc_cd.C
-// *! DESCRIPTION : Fabric configuration (hotplug, CD) functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp_fbc_cd.H>
-#include <proc_build_smp_adu.H>
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// structure encapsulating serial configuration load programming
-struct proc_build_smp_sconfig_def
-{
-    uint8_t select;                               // ID/select for chain
-    uint8_t length;                               // number of bits to load
-    bool use_slow_clock;                          // use 16:1 slow clock? (EX)
-    bool use_shadow[PROC_BUILD_SMP_NUM_SHADOWS];  // define which shadows to set
-};
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//
-// PB Serial Configuration Load register field/bit definitions
-//
-
-// hang level constants
-const uint8_t PB_SCONFIG_NUM_HANG_LEVELS = 7;
-
-// CPU ratio constants
-const uint8_t PB_SCONFIG_NUM_CPU_RATIOS = 4;
-
-
-const uint32_t PB_SCONFIG_LOAD[PROC_BUILD_SMP_NUM_SHADOWS] =
-{
-    PB_SCONFIG_LOAD_WEST_0x02010C16,
-    PB_SCONFIG_LOAD_CENT_0x02010C6D,
-    PB_SCONFIG_LOAD_EAST_0x02010C96
-};
-
-const uint32_t PB_SCONFIG_LOAD_START_BIT = 0;
-const uint32_t PB_SCONFIG_LOAD_SLOW_BIT = 1;
-const uint32_t PB_SCONFIG_SHIFT_COUNT_START_BIT = 2;
-const uint32_t PB_SCONFIG_SHIFT_COUNT_END_BIT = 7;
-const uint32_t PB_SCONFIG_SELECT_START_BIT = 8;
-const uint32_t PB_SCONFIG_SELECT_END_BIT = 11;
-const uint32_t PB_SCONFIG_SHIFT_DATA_START_BIT = 12;
-const uint32_t PB_SCONFIG_SHIFT_DATA_END_BIT = 63;
-
-
-//
-// PBH_CMD_SNOOPER (center, chain #4) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C4_DEF = { 0x4, 50, false, { false, true, false} };
-
-const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT = 14;
-const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_END_BIT = 23;
-const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT = 24;
-const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_END_BIT = 33;
-const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT = 34;
-const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_END_BIT = 43;
-const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT = 44;
-const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_END_BIT = 53;
-const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT = 54;
-const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_END_BIT = 63;
-
-const uint32_t PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD = 0x7;
-const uint32_t PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD = 0x5;
-const uint32_t PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD = 0x5;
-const uint32_t PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD = 0x4;
-const uint32_t PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD = 0x5;
-
-
-//
-// PBH_CMD_SNOOPER (center, chain #5) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C5_DEF = { 0x5, 46, false, { false, true, false} };
-
-const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT = 18;
-const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_END_BIT = 27;
-const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT = 28;
-const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_END_BIT = 39;
-const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT = 40;
-const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_END_BIT = 51;
-const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT = 52;
-const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_END_BIT = 63;
-
-const uint32_t PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD = 0x4;
-const uint32_t PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME = 321;
-const uint32_t PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME = 539;
-const uint32_t PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME = 781;
-
-
-//
-// PBH_CMD_SNOOPER (center, chain #6) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C6_DEF = { 0x6, 42, false, { false, true, false} };
-
-const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT = 22;
-const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_END_BIT = 33;
-const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT = 34;
-const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_END_BIT = 45;
-const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_START_BIT = 46;
-const uint32_t PB_SCONFIG_C6_GP_LO_JUMP_END_BIT = 48;
-const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_START_BIT = 49;
-const uint32_t PB_SCONFIG_C6_GP_HI_JUMP_END_BIT = 51;
-const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_START_BIT = 52;
-const uint32_t PB_SCONFIG_C6_SP_LO_JUMP_END_BIT = 54;
-const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_START_BIT = 55;
-const uint32_t PB_SCONFIG_C6_SP_HI_JUMP_END_BIT = 57;
-const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT = 58;
-const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP_END_BIT = 60;
-const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT = 61;
-const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP_END_BIT = 63;
-
-const uint32_t PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME = 1024;
-const uint32_t PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME = 1024;
-const uint32_t PB_SCONFIG_C6_GP_LO_JUMP = 0x2;
-const uint32_t PB_SCONFIG_C6_GP_HI_JUMP = 0x2;
-const uint32_t PB_SCONFIG_C6_SP_LO_JUMP = 0x2;
-const uint32_t PB_SCONFIG_C6_SP_HI_JUMP = 0x2;
-const uint32_t PB_SCONFIG_C6_RGP_LO_JUMP = 0x2;
-const uint32_t PB_SCONFIG_C6_RGP_HI_JUMP = 0x2;
-
-
-//
-// PBH_CMD_SNOOPER (center, chain #7) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C7_DEF = { 0x7, 36, false, { false, true, false } };
-
-const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS] = { 28, 33, 38, 43, 48, 53, 58 };
-const uint32_t PB_SCONFIG_C7_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS]   = { 32, 37, 42, 47, 52, 57, 62 };
-const uint32_t PB_SCONFIG_C7_SLOW_GO_RATE_BIT = 63;
-
-// PB_CFG_HANG0_CMD_RATE = 0x00 = 127/128
-// PB_CFG_HANG1_CMD_RATE = 0x06 = 1/2
-// PB_CFG_HANG2_CMD_RATE = 0x0D = 1/512
-// PB_CFG_HANG3_CMD_RATE = 0x00 = 127/128
-// PB_CFG_HANG4_CMD_RATE = 0x1E = 1/4096 (toad mode)
-// PB_CFG_HANG5_CMD_RATE = 0x19 = 1/8 (toad mode)
-// PB_CFG_HANG6_CMD_RATE = 0x00 = 127/128
-const uint8_t PB_SCONFIG_C7_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x06, 0x0D, 0x00, 0x1E, 0x19, 0x00 };
-const bool    PB_SCONFIG_C7_SLOW_GO_RATE = true;
-
-
-//
-// PBH_CMD_SNOOPER (center, chain #8) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER1 = { 0x8, 37, false, { false, true, false } };
-const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER2 = { 0x8, 39, false, { false, true, false } };
-const proc_build_smp_sconfig_def PB_SCONFIG_C8_DEF_VER3 = { 0x8, 43, false, { false, true, false } };
-
-const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS] = { 27, 31, 35, 39, 43, 47, 51 };
-const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER1[PB_SCONFIG_NUM_HANG_LEVELS]   = { 30, 34, 38, 42, 46, 50, 54 };
-const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER1 = 55;
-const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER1 = 57;
-const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER1 = 58;
-const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER1 = 63;
-
-const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS] = { 25, 29, 33, 37, 41, 45, 49 };
-const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER2[PB_SCONFIG_NUM_HANG_LEVELS]   = { 28, 32, 36, 40, 44, 48, 52 };
-const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER2 = 53;
-const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER2 = 55;
-const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER2 = 56;
-const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER2 = 61;
-const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER2 = 62;
-const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER2 = 63;
-
-const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS] = { 21, 25, 29, 33, 37, 41, 45 };
-const uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER3[PB_SCONFIG_NUM_HANG_LEVELS]   = { 24, 28, 32, 36, 40, 44, 48 };
-const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER3 = 49;
-const uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER3 = 51;
-const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER3 = 52;
-const uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER3 = 57;
-const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER3 = 58;
-const uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER3 = 59;
-const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT_VER3 = 60;
-const uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT_VER3 = 62;
-const uint32_t PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT_VER3 = 63;
-
-const uint8_t PB_SCONFIG_C8_HANG_CMD_RATE[PB_SCONFIG_NUM_HANG_LEVELS] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
-const uint8_t PB_SCONFIG_C8_CPO_JUMP_LEVEL = 0x7;
-const uint8_t PB_SCONFIG_C8_CPO_RTY_LEVEL = 0x4;
-
-const uint8_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF = 0x2; // backoff_1k
-
-const uint8_t PB_SCONFIG_C8_RTY_PERCENTAGE  = 0x0;  // 000
-const uint8_t PB_SCONFIG_C8_INCLUDE_LPC_RTY = 0x0;  // off
-
-//
-// PBH_CMD_CENTRAL_ARB (center, chain #9) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C9_DEF = { 0x9, 44, false, { false, true, false } };
-
-const uint32_t PB_SCONFIG_C9_CP_STARVE_LIMIT_START_BIT = 20;
-const uint32_t PB_SCONFIG_C9_CP_STARVE_LIMIT_END_BIT = 27;
-const uint32_t PB_SCONFIG_C9_GP_STARVE_LIMIT_START_BIT = 28;
-const uint32_t PB_SCONFIG_C9_GP_STARVE_LIMIT_END_BIT = 35;
-const uint32_t PB_SCONFIG_C9_RGP_STARVE_LIMIT_START_BIT = 36;
-const uint32_t PB_SCONFIG_C9_RGP_STARVE_LIMIT_END_BIT = 43;
-const uint32_t PB_SCONFIG_C9_SP_STARVE_LIMIT_START_BIT = 44;
-const uint32_t PB_SCONFIG_C9_SP_STARVE_LIMIT_END_BIT = 51;
-const uint32_t PB_SCONFIG_C9_FP_STARVE_LIMIT_START_BIT = 52;
-const uint32_t PB_SCONFIG_C9_FP_STARVE_LIMIT_END_BIT = 59;
-const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_START_BIT = 60;
-const uint32_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_END_BIT = 61;
-const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_START_BIT = 62;
-const uint32_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_END_BIT = 63;
-
-const uint8_t PB_SCONFIG_C9_CP_STARVE_LIMIT  = 0x10;
-const uint8_t PB_SCONFIG_C9_GP_STARVE_LIMIT  = 0x10;
-const uint8_t PB_SCONFIG_C9_RGP_STARVE_LIMIT = 0x10;
-const uint8_t PB_SCONFIG_C9_SP_STARVE_LIMIT  = 0x10;
-const uint8_t PB_SCONFIG_C9_FP_STARVE_LIMIT  = 0x10;
-const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR = 0x0;                       // LFSR_ONLY
-const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_RR = 0x1;                         // RR_ONLY
-const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR_ON_STARVATION_ELSE_RR = 0x2; // LFSR_ON_STARVATION_ELSE_RR
-const uint8_t PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_RR_ON_STARVATION_ELSE_LFSR = 0x3; // RR_ON_STARVATION_ELSE_LFSR
-const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_LFSR = 0x0;                       // LFSR_ONLY
-const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_RR = 0x1;                         // RR_ONLY
-const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_LFSR_ON_STARVATION_ELSE_RR = 0x2; // LFSR_ON_STARVATION_ELSE_RR
-const uint8_t PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_RR_ON_STARVATION_ELSE_LFSR = 0x3; // RR_ON_STARVATION_ELSE_LFSR
-
-
-//
-// PBH_CMD_CENTRAL_ARB (center, chain #10) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER1 = { 0xA, 20, false, { false, true, false } };
-const proc_build_smp_sconfig_def PB_SCONFIG_C10_DEF_VER2 = { 0xA, 23, false, { false, true, false } };
-
-const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 };
-const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER1[PB_SCONFIG_NUM_CPU_RATIOS]   = { 63, 58, 53, 48 };
-
-const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS] = { 56, 51, 46, 41 };
-const uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER2[PB_SCONFIG_NUM_CPU_RATIOS]   = { 60, 55, 50, 45 };
-const uint32_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT_VER2 = 61;
-const uint32_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT_VER2 = 62;
-const uint32_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT_VER2 = 63;
-
-const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 15, 14, 13, 12, 11, 11, 10, 10,  9,  9,  8,  8,  7 };
-
-const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_QUARTER = 3;
-const uint8_t PB_SCONFIG_C10_CMD_CPU_RATIO_HALF    = 7;
-const uint8_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE   = 0x0; // disable
-const uint8_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE   = 0x0; // disable
-const uint8_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER = 0x0; // x2
-
-
-//
-// PBH_RSP_CRESP_ARB (center, chain #11) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_C11_DEF = { 0xB, 20, false, { false, true, false } };
-
-const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS] = { 59, 54, 49, 44 };
-const uint32_t PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS]   = { 63, 58, 53, 48 };
-
-const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 16, 15, 14, 13, 12, 12, 11, 11, 10, 10,  9,  9,  8 };
-
-const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_QUARTER = 4;
-const uint8_t PB_SCONFIG_C11_RSP_CPU_RATIO_HALF    = 8;
-
-//
-// PBH_PBIEX_EH (east/west, chain #0) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_WE0_DEF = { 0x0, 52, false, { true, false, true } };
-
-const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT = 12;
-const uint32_t PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_END_BIT = 14;
-const uint32_t PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE_BIT = 15;
-const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT = 16;
-const uint32_t PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_END_BIT = 17;
-const uint32_t PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE_BIT = 18;
-const uint32_t PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH_BIT = 19;
-const uint32_t PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS_BIT = 20;
-const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT = 21;
-const uint32_t PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_END_BIT = 22;
-const uint32_t PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE_BIT = 23;
-const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT = 24;
-const uint32_t PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_END_BIT = 25;
-const uint32_t PB_SCONFIG_WE0_CRSP_I2C_HSHAKE_BIT = 26;
-const uint32_t PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE_BIT = 27;
-const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT = 28;
-const uint32_t PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_END_BIT = 29;
-const uint32_t PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE_BIT = 30;
-const uint32_t PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC_BIT = 31;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT = 32;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_END_BIT = 33;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT = 34;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_END_BIT = 36;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT = 37;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_END_BIT = 38;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT_BIT = 39;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE_BIT = 40;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION_BIT = 41;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID_BIT = 42;
-const uint32_t PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE_BIT = 43;
-const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT = 44;
-const uint32_t PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_END_BIT = 45;
-const uint32_t PB_SCONFIG_WE0_RCMD_I2C_HSHAKE_BIT = 46;
-const uint32_t PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE_BIT = 47;
-const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT = 48;
-const uint32_t PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_END_BIT = 49;
-const uint32_t PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT = 50;
-const uint32_t PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT  = 51;
-const uint32_t PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT = 52;
-const uint32_t PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT = 53;
-const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT = 54;
-const uint32_t PB_SCONFIG_WE0_CPU_DELAY_FULL_END_BIT = 58;
-const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT  = 59;
-const uint32_t PB_SCONFIG_WE0_CPU_DELAY_NOM_END_BIT = 63;
-
-const bool     PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE = true;             // on
-const uint8_t  PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD = 0x0;               // rc_p1
-const bool     PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE = false;              // spare
-const uint8_t  PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH = 0x0;              // rc_p1
-const bool     PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS = true;            // on
-const uint8_t  PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE = 0x0;                 // 16c
-const bool     PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE = false;             // spare
-const bool     PB_SCONFIG_WE0_CRSP_I2C_HSHAKE = false;                 // off
-const bool     PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE = false;             // spare
-const bool     PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE = false;             // spare
-const bool     PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC = false;         // off
-const uint8_t  PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY = 0x7;          // 7c
-const bool     PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT = false;  // 8
-const bool     PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE = false; // FA
-const bool     PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION = true;     // on
-const bool     PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID = true;          // on
-const bool     PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE = false;             // spare
-const bool     PB_SCONFIG_WE0_RCMD_I2C_HSHAKE = false;                 // off
-const bool     PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE = false;             // spare
-const uint8_t  PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH = 0x0;                // wc_p1
-const uint8_t  PB_SCONFIG_WE0_FP_I2C_HSHAKE = false;                   // off
-const bool     PB_SCONFIG_WE0_FP_I2C_SPARE_MODE = false;               // spare
-const uint8_t  PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH = 0x0;                // rc_p1
-const bool     PB_SCONFIG_WE0_FP_C2I_SPARE_MODE = false;               // spare
-
-const uint8_t PB_SCONFIG_WE0_CPU_DELAY_TABLE[PROC_BUILD_SMP_CPU_DELAY_NUM_SETPOINTS] = { 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 };
-
-
-//
-// PBH_PBIEX_EX (east/west, chain #1) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_WE1_DEF = { 0x1, 38, true, { true, false, true } };
-
-const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT = 26;
-const uint32_t PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_END_BIT = 27;
-const uint32_t PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE_BIT = 28;
-const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_BIT = 29;
-const uint32_t PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE_BIT = 30;
-const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT = 31;
-const uint32_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_END_BIT = 32;
-const uint32_t PB_SCONFIG_WE1_PRSP_C2I_HSHAKE_BIT = 33;
-const uint32_t PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE_BIT = 34;
-const uint32_t PB_SCONFIG_WE1_CRSP_I2C_DONE_LAUNCH_BIT = 35;
-const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT = 36;
-const uint32_t PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_END_BIT = 37;
-const uint32_t PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE_BIT = 38;
-const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT = 39;
-const uint32_t PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_END_BIT = 40;
-const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT = 41;
-const uint32_t PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_END_BIT = 42;
-const uint32_t PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE_BIT = 43;
-const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT = 44;
-const uint32_t PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_END_BIT = 45;
-const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT = 46;
-const uint32_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_END_BIT = 47;
-const uint32_t PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE_BIT = 48;
-const uint32_t PB_SCONFIG_WE1_RCMD_I2C_DONE_LAUNCH_BIT = 49;
-const uint32_t PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL_BIT = 50;
-const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT = 51;
-const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_END_BIT = 52;
-const uint32_t PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT_BIT = 53;
-const uint32_t PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE_BIT = 54;
-const uint32_t PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH_BIT = 55;
-const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_BIT = 56;
-const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT = 57;
-const uint32_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_END_BIT = 58;
-const uint32_t PB_SCONFIG_WE1_FP_I2C_SPARE_MODE_BIT = 59;
-const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT = 60;
-const uint32_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_END_BIT = 61;
-const uint32_t PB_SCONFIG_WE1_FP_C2I_HSHAKE_BIT = 62;
-const uint32_t PB_SCONFIG_WE1_FP_C2I_SPARE_MODE_BIT = 63;
-
-const bool    PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE = false;           // off
-const bool    PB_SCONFIG_WE1_CMD_C2I_SPARE = false;                    // spare
-const bool    PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE = false;               // spare
-const uint8_t PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH = 0x0;               // rc_p1
-const bool    PB_SCONFIG_WE1_PRSP_C2I_HSHAKE = false;                  // off
-const bool    PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE = false;              // spare
-const bool    PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE = false;              // spare
-const bool    PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE = false;              // spare
-const uint8_t PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH = 0x0;               // rc_d3
-const bool    PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE = false;              // off
-const bool    PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL = false;        // off
-const bool    PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT = false;              // off
-const bool    PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE = false;              // off
-const bool    PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH = false;               // rc_p1
-const bool    PB_SCONFIG_WE1_FP_I2C_SPARE = false;                     // spare
-const uint8_t PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE = 0x0;              // rc
-const bool    PB_SCONFIG_WE1_FP_I2C_SPARE_MODE = false;                // off
-const uint8_t PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH = 0x0;                 // wc_p1
-const bool    PB_SCONFIG_WE1_FP_C2I_HSHAKE = false;                    // off
-const bool    PB_SCONFIG_WE1_FP_C2I_SPARE_MODE = false;                // spare
-
-
-//
-// PBH_DAT_ARB_EM (east/west, chain #5) field/bit definitions
-//
-
-const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER1 = { 0x5, 51, false, { true, false, true } };
-const proc_build_smp_sconfig_def PB_SCONFIG_WE5_DEF_VER2 = { 0x5, 52, false, { true, false, true } };
-
-const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER1 = 13;
-const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 14;
-const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 17;
-const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 18;
-const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 21;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 22;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 25;
-const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1 = 26;
-const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1 = 29;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER1 = 30;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER1 = 33;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER1 = 34;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER1 = 35;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER1 = 42;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER1 = 43;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER1 = 50;
-const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER1 = 51;
-const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER1 = 54;
-const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER1 = 55;
-const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER1 = 58;
-const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER1 = 59;
-const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER1 = 60;
-const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER1 = 61;
-const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER1 = 62;
-const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER1 = 63;
-
-const uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER2 = 12;
-const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 13;
-const uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 16;
-const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 17;
-const uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 20;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 21;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 24;
-const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2 = 25;
-const uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2 = 28;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER2 = 29;
-const uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER2 = 32;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER2 = 33;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER2 = 34;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER2 = 41;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER2 = 42;
-const uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER2 = 49;
-const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER2 = 50;
-const uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER2 = 53;
-const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER2 = 54;
-const uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER2 = 57;
-const uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER2 = 58;
-const uint32_t PB_SCONFIG_WE5_SPARE_START_BIT_VER2 = 59;
-const uint32_t PB_SCONFIG_WE5_SPARE_END_BIT_VER2 = 59;
-const uint32_t PB_SCONFIG_WE5_A_IND_THRESHOLD_BIT_VER2 = 60;
-const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER2 = 61;
-const uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER2 = 62;
-const uint32_t PB_SCONFIG_WE5_X_OFF_SEL_BIT_VER2 = 63;
-
-const bool    PB_SCONFIG_WE5_LOCK_ON_LINKS = true;                   // lock
-const uint8_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD = 0x4;      // cnt_4
-const uint8_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD = 0x4;     // cnt_4
-const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD = 0x4;         // cnt_4
-const uint8_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD = 0x0;         // cnt_0
-const uint8_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD = 0x2;         // cnt_2
-const bool    PB_SCONFIG_WE5_PASSTHRU_ENABLE = true;                 // enable
-const uint8_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY = 0xFE;             // cnt_7to1
-const uint8_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY = 0xFE;             // cnt_7to1
-const uint8_t PB_SCONFIG_WE5_A_TOK_INIT = 0x8;                       // cnt_8
-const uint8_t PB_SCONFIG_WE5_F_TOK_INIT = 0x4;                       // cnt_4
-const bool    PB_SCONFIG_WE5_EM_FP_ENABLE = true;                    // enable
-const uint8_t PB_SCONFIG_WE5_SPARE = 0x0;                            // spare
-const uint8_t PB_SCONFIG_WE5_MEM_STV_PRIORITY = 0x2;                 // stv
-
-const uint8_t PB_SCONFIG_WE5_A_IND_THRESHOLD = 0x0;                  // gt4
-const uint8_t PB_SCONFIG_WE5_X_OFF_SEL = 0x0;                        // disable
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility function to program PB serial SCOM chain
-// parameters: i_smp_chip    => structure encapsulating SMP chip
-//             i_sconfig_def => structure defining properties of chain
-//                              to be written
-//             i_chain_data  => data buffer containing chain write data
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_sconfig_def & i_sconfig_def,
-    const ecmdDataBufferBase& i_chain_data)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig: Start");
-
-    do
-    {
-        // pb_cfg_sconfig_load
-        rc_ecmd |= data.setBit(PB_SCONFIG_LOAD_START_BIT);
-
-        // pb_cfg_sconfig_slow
-        if (i_sconfig_def.use_slow_clock)
-        {
-            rc_ecmd |= data.setBit(PB_SCONFIG_LOAD_SLOW_BIT);
-        }
-
-        // pb_cfg_sconfig_shift_count
-        rc_ecmd |= data.insertFromRight(
-            i_sconfig_def.length,
-            PB_SCONFIG_SHIFT_COUNT_START_BIT,
-            (PB_SCONFIG_SHIFT_COUNT_END_BIT-
-             PB_SCONFIG_SHIFT_COUNT_START_BIT+1));
-
-        // pb_cfg_sconfig_shift_select
-        rc_ecmd |= data.insertFromRight(
-            i_sconfig_def.select,
-            PB_SCONFIG_SELECT_START_BIT,
-            (PB_SCONFIG_SELECT_END_BIT-
-             PB_SCONFIG_SELECT_START_BIT+1));
-
-        // pb_cfg_sconfig_shift_data
-        rc_ecmd |= i_chain_data.extractPreserve(
-            data,
-            PB_SCONFIG_SHIFT_DATA_START_BIT,
-            (PB_SCONFIG_SHIFT_DATA_END_BIT-
-             PB_SCONFIG_SHIFT_DATA_START_BIT+1),
-            PB_SCONFIG_SHIFT_DATA_START_BIT);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write specified register copies
-        for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
-        {
-            if (i_sconfig_def.use_shadow[r])
-            {
-                // write register
-                rc = fapiPutScom(i_smp_chip.chip->this_chip,
-                                 PB_SCONFIG_LOAD[r],
-                                 data);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_sconfig: fapiPutScom error (%08X)",
-                             PB_SCONFIG_LOAD[r]);
-                    break;
-                }
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #4)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c4(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c4: Start");
-
-    do
-    {
-        // build register content
-        // gp_lo_rty_threshold
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD,
-            PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT,
-            (PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_END_BIT-
-             PB_SCONFIG_C4_GP_LO_RTY_THRESHOLD_START_BIT+1));
-
-        // gp_hi_rty_threshold
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD,
-            PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT,
-            (PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_END_BIT-
-             PB_SCONFIG_C4_GP_HI_RTY_THRESHOLD_START_BIT+1));
-
-        // rgp_lo_rty_threshold
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD,
-            PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT,
-            (PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_END_BIT-
-             PB_SCONFIG_C4_RGP_LO_RTY_THRESHOLD_START_BIT+1));
-
-        // rgp_hi_rty_threshold
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD,
-            PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT,
-            (PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_END_BIT-
-             PB_SCONFIG_C4_RGP_HI_RTY_THRESHOLD_START_BIT+1));
-
-        // sp_lo_rty_threshold
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD,
-            PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT,
-            (PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_END_BIT-
-             PB_SCONFIG_C4_SP_LO_RTY_THRESHOLD_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c4: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C4_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c4: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c4: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #5)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c5(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c5: Start");
-
-    do
-    {
-        // build register content
-        // sp_hi_rty_threshold
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD,
-            PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT,
-            (PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_END_BIT-
-             PB_SCONFIG_C5_SP_HI_RTY_THRESHOLD_START_BIT+1));
-
-        // gp_cresp_sample_time
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME,
-            PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT,
-            (PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_END_BIT-
-             PB_SCONFIG_C5_GP_CRESP_SAMPLE_TIME_START_BIT+1));
-
-        // rgp_cresp_sample_time
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME,
-            PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT,
-            (PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_END_BIT-
-             PB_SCONFIG_C5_RGP_CRESP_SAMPLE_TIME_START_BIT+1));
-
-        // sp_cresp_sample_time
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME,
-            PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT,
-            (PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_END_BIT-
-             PB_SCONFIG_C5_SP_CRESP_SAMPLE_TIME_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c5: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C5_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c5: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c5: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #6)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c6(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c6: Start");
-
-    do
-    {
-        // build register content
-        // gp_req_sample_time
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME,
-            PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT,
-            (PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_END_BIT-
-             PB_SCONFIG_C6_GP_REQ_SAMPLE_TIME_START_BIT+1));
-
-        // sp_req_sample_time
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME,
-            PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT,
-            (PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_END_BIT-
-             PB_SCONFIG_C6_SP_REQ_SAMPLE_TIME_START_BIT+1));
-
-        // gp_lo_jump
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_GP_LO_JUMP,
-            PB_SCONFIG_C6_GP_LO_JUMP_START_BIT,
-            (PB_SCONFIG_C6_GP_LO_JUMP_END_BIT-
-             PB_SCONFIG_C6_GP_LO_JUMP_START_BIT+1));
-
-        // gp_hi_jump
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_GP_HI_JUMP,
-            PB_SCONFIG_C6_GP_HI_JUMP_START_BIT,
-            (PB_SCONFIG_C6_GP_HI_JUMP_END_BIT-
-             PB_SCONFIG_C6_GP_HI_JUMP_START_BIT+1));
-
-        // sp_lo_jump
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_SP_LO_JUMP,
-            PB_SCONFIG_C6_SP_LO_JUMP_START_BIT,
-            (PB_SCONFIG_C6_SP_LO_JUMP_END_BIT-
-             PB_SCONFIG_C6_SP_LO_JUMP_START_BIT+1));
-
-        // sp_hi_jump
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_SP_HI_JUMP,
-            PB_SCONFIG_C6_SP_HI_JUMP_START_BIT,
-            (PB_SCONFIG_C6_SP_HI_JUMP_END_BIT-
-             PB_SCONFIG_C6_SP_HI_JUMP_START_BIT+1));
-
-        // rgp_lo_jump
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_RGP_LO_JUMP,
-            PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT,
-            (PB_SCONFIG_C6_RGP_LO_JUMP_END_BIT-
-             PB_SCONFIG_C6_RGP_LO_JUMP_START_BIT+1));
-
-        // rgp_hi_jump
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C6_RGP_HI_JUMP,
-            PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT,
-            (PB_SCONFIG_C6_RGP_HI_JUMP_END_BIT-
-             PB_SCONFIG_C6_RGP_HI_JUMP_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c6: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C6_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c6: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c6: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #7)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c7(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c7: Start");
-
-    do
-    {
-        // build register content
-        // program hang command rates
-        for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
-        {
-            rc_ecmd |= data.insertFromRight(
-                PB_SCONFIG_C7_HANG_CMD_RATE[l],
-                PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[l],
-                (PB_SCONFIG_C7_HANG_CMD_RATE_END_BIT[l]-
-                 PB_SCONFIG_C7_HANG_CMD_RATE_START_BIT[l]+1));
-        }
-
-        // slow_go_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_C7_SLOW_GO_RATE_BIT,
-            PB_SCONFIG_C7_SLOW_GO_RATE?1:0);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c7: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C7_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c7: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c7: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #8)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c8(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    uint8_t ver2 = 0x0;
-    uint8_t ver3 = 0x0;
-    uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[PB_SCONFIG_NUM_HANG_LEVELS];
-    uint32_t PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[PB_SCONFIG_NUM_HANG_LEVELS];
-    uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT;
-    uint32_t PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT;
-    uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT;
-    uint32_t PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT;
-    uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT;
-    uint32_t PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT;
-    uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT;
-    uint32_t PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT;
-    uint32_t PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT;
-    proc_build_smp_sconfig_def pb_sconfig_c8_def;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c8: Start");
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER2,
-                           &(i_smp_chip.chip->this_chip),
-                           ver2);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER2");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER3,
-                           &(i_smp_chip.chip->this_chip),
-                           ver3);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C8_VER3");
-            break;
-        }
-
-        if (ver3)
-        {
-            for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
-            {
-                PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER3[l];
-                PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l]   = PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER3[l];
-            }
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT   = PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER3;
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT     = PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER3;
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT    = PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER3;
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT      = PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER3;
-            PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER3;
-            PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT   = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER3;
-            PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT   = PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT_VER3;
-            PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT     = PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT_VER3;
-            PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT        = PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT_VER3;
-            pb_sconfig_c8_def                        = PB_SCONFIG_C8_DEF_VER3;
-        }
-        else if (ver2)
-        {
-            for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
-            {
-                PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER2[l];
-                PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l]   = PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER2[l];
-            }
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT   = PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER2;
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT     = PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER2;
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT    = PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER2;
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT      = PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER2;
-            PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT_VER2;
-            PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT   = PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT_VER2;
-            PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT   = 0xFF;
-            PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT     = 0xFF;
-            PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT        = 0xFF;
-            pb_sconfig_c8_def                        = PB_SCONFIG_C8_DEF_VER2;
-        }
-        else
-        {
-            for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
-            {
-                PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l] = PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT_VER1[l];
-                PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l]   = PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT_VER1[l];
-            }
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT   = PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT_VER1;
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT     = PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT_VER1;
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT    = PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT_VER1;
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT      = PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT_VER1;
-            PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT = 0xFF;
-            PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT   = 0xFF;
-            PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT   = 0xFF;
-            PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT     = 0xFF;
-            PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT        = 0xFF;
-            pb_sconfig_c8_def                        = PB_SCONFIG_C8_DEF_VER1;
-        }
-
-        // build register content
-        // program hang command rates
-        for (uint8_t l = 0; l < PB_SCONFIG_NUM_HANG_LEVELS; l++)
-        {
-            rc_ecmd |= data.insertFromRight(
-                PB_SCONFIG_C8_HANG_CMD_RATE[l],
-                PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l],
-                (PB_SCONFIG_C8_HANG_CMD_RATE_END_BIT[l]-
-                 PB_SCONFIG_C8_HANG_CMD_RATE_START_BIT[l]+1));
-        }
-
-        // cpo_jump_level
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL,
-            PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT,
-            (PB_SCONFIG_C8_CPO_JUMP_LEVEL_END_BIT-
-             PB_SCONFIG_C8_CPO_JUMP_LEVEL_START_BIT+1));
-
-        // cpo_rty_level
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C8_CPO_RTY_LEVEL,
-            PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT,
-            (PB_SCONFIG_C8_CPO_RTY_LEVEL_END_BIT-
-             PB_SCONFIG_C8_CPO_RTY_LEVEL_START_BIT+1));
-
-        // p7_sleep_backoff
-        if (ver2 || ver3)
-        {
-            rc_ecmd |= data.insertFromRight(
-                PB_SCONFIG_C8_P7_SLEEP_BACKOFF,
-                PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT,
-                (PB_SCONFIG_C8_P7_SLEEP_BACKOFF_END_BIT-
-                 PB_SCONFIG_C8_P7_SLEEP_BACKOFF_START_BIT+1));
-        }
-
-        // rty_percentage
-        // include_lpc_rty
-        if (ver3)
-        {
-            rc_ecmd |= data.insertFromRight(
-                PB_SCONFIG_C8_RTY_PERCENTAGE,
-                PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT,
-                (PB_SCONFIG_C8_RTY_PERCENTAGE_END_BIT-
-                 PB_SCONFIG_C8_RTY_PERCENTAGE_START_BIT+1));
-
-            rc_ecmd |= data.writeBit(
-                PB_SCONFIG_C8_INCLUDE_LPC_RTY_BIT,
-                PB_SCONFIG_C8_INCLUDE_LPC_RTY?1:0);
-        }
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c8: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(
-            i_smp_chip,
-            pb_sconfig_c8_def,
-            data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c8: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c8: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #9)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c9(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    uint8_t ux_scope_arb_mode_lfsr_on_starvation_else_rr = 0;
-    uint8_t ux_scope_arb_mode_rr = 0;
-    uint8_t ux_scope_arb_mode;
-    uint8_t ux_local_arb_mode_rr = 0;
-    uint8_t ux_local_arb_mode;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c9: Start");
-
-    do
-    {
-        // build register content
-        // cp_starve_limit
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C9_CP_STARVE_LIMIT,
-            PB_SCONFIG_C9_CP_STARVE_LIMIT_START_BIT,
-            (PB_SCONFIG_C9_CP_STARVE_LIMIT_END_BIT-
-             PB_SCONFIG_C9_CP_STARVE_LIMIT_START_BIT+1));
-
-        // gp_starve_limit
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C9_GP_STARVE_LIMIT,
-            PB_SCONFIG_C9_GP_STARVE_LIMIT_START_BIT,
-            (PB_SCONFIG_C9_GP_STARVE_LIMIT_END_BIT-
-             PB_SCONFIG_C9_GP_STARVE_LIMIT_START_BIT+1));
-
-        // rgp_starve_limit
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C9_RGP_STARVE_LIMIT,
-            PB_SCONFIG_C9_RGP_STARVE_LIMIT_START_BIT,
-            (PB_SCONFIG_C9_RGP_STARVE_LIMIT_END_BIT-
-             PB_SCONFIG_C9_RGP_STARVE_LIMIT_START_BIT+1));
-
-        // sp_starve_limit
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C9_SP_STARVE_LIMIT,
-            PB_SCONFIG_C9_SP_STARVE_LIMIT_START_BIT,
-            (PB_SCONFIG_C9_SP_STARVE_LIMIT_END_BIT-
-             PB_SCONFIG_C9_SP_STARVE_LIMIT_START_BIT+1));
-
-        // fp_starve_limit
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C9_FP_STARVE_LIMIT,
-            PB_SCONFIG_C9_FP_STARVE_LIMIT_START_BIT,
-            (PB_SCONFIG_C9_FP_STARVE_LIMIT_END_BIT-
-             PB_SCONFIG_C9_FP_STARVE_LIMIT_START_BIT+1));
-
-        // ux_scope_arb_mode
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_LFSR_ON_STARVATION_ELSE_RR,
-                           &(i_smp_chip.chip->this_chip),
-                           ux_scope_arb_mode_lfsr_on_starvation_else_rr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_LFSR_ON_STARVATION_ELSE_RR");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_RR,
-                           &(i_smp_chip.chip->this_chip),
-                           ux_scope_arb_mode_rr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_UX_SCOPE_ARB_RR");
-            break;
-        }
-
-        if (ux_scope_arb_mode_lfsr_on_starvation_else_rr)
-        {
-            ux_scope_arb_mode = PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR_ON_STARVATION_ELSE_RR;
-        }
-        else if (ux_scope_arb_mode_rr)
-        {
-            ux_scope_arb_mode = PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_RR;
-        }
-        else
-        {
-            ux_scope_arb_mode = PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_LFSR;
-        }
-
-        rc_ecmd |= data.insertFromRight(
-            ux_scope_arb_mode,
-            PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_START_BIT,
-            (PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_END_BIT-
-             PB_SCONFIG_C9_UX_SCOPE_ARB_MODE_START_BIT+1));
-
-        // ux_local_arb_mode
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_UX_LOCAL_ARB_RR,
-                           &(i_smp_chip.chip->this_chip),
-                           ux_local_arb_mode_rr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_UX_LOCAL_ARB_RR");
-            break;
-        }
-
-        if (ux_local_arb_mode_rr)
-        {
-            ux_local_arb_mode = PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_RR;
-        }
-        else
-        {
-            ux_local_arb_mode = PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_LFSR_ON_STARVATION_ELSE_RR;
-        }
-
-        rc_ecmd |= data.insertFromRight(
-            ux_local_arb_mode,
-            PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_START_BIT,
-            (PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_END_BIT-
-             PB_SCONFIG_C9_UX_LOCAL_ARB_MODE_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c9: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C9_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c9: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c9: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #10)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c10(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    uint8_t ver2;
-    uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[PB_SCONFIG_NUM_CPU_RATIOS];
-    uint32_t PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[PB_SCONFIG_NUM_CPU_RATIOS];
-    uint32_t PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT;
-    uint32_t PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT;
-    uint32_t PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT;
-    proc_build_smp_sconfig_def pb_sconfig_c10_def;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c10: Start");
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2,
-                           &(i_smp_chip.chip->this_chip),
-                           ver2);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_C10_VER2");
-            break;
-        }
-
-        if (ver2)
-        {
-            for (uint8_t l = 0; l < PB_SCONFIG_NUM_CPU_RATIOS; l++)
-            {
-                PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[l] = PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER2[l];
-                PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[l]   = PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER2[l];
-            }
-            PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT   = PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT_VER2;
-            PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT   = PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT_VER2;
-            PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT = PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT_VER2;
-            pb_sconfig_c10_def = PB_SCONFIG_C10_DEF_VER2;
-        }
-        else
-        {
-            for (uint8_t l = 0; l < PB_SCONFIG_NUM_CPU_RATIOS; l++)
-            {
-                PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[l] = PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT_VER1[l];
-                PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[l]   = PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT_VER1[l];
-            }
-            PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT   = 0xFF;
-            PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT   = 0xFF;
-            PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT = 0xFF;
-            pb_sconfig_c10_def = PB_SCONFIG_C10_DEF_VER1;
-        }
-
-        // build register content
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C10_CMD_CPU_RATIO_QUARTER,
-            PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[0],
-            (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[0]-
-             PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[0]+1));
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C10_CMD_CPU_RATIO_HALF,
-            PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[1],
-            (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[1]-
-             PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[1]+1));
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[i_smp.nom_cpu_delay],
-            PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[2],
-            (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[2]-
-             PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[2]+1));
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C10_CMD_CPU_RATIO_TABLE[i_smp.full_cpu_delay],
-            PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[3],
-            (PB_SCONFIG_C10_CMD_CPU_RATIO_END_BIT[3]-
-             PB_SCONFIG_C10_CMD_CPU_RATIO_START_BIT[3]+1));
-
-        // x_link_holdoff_enable
-        // a_link_holdoff_enable
-        // link_holdoff_mutlipler
-        if (ver2)
-        {
-            rc_ecmd |= data.writeBit(
-                PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE_BIT,
-                PB_SCONFIG_C10_DAT_X_LINK_HOLDOFF_ENABLE);
-
-            rc_ecmd |= data.writeBit(
-                PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE_BIT,
-                PB_SCONFIG_C10_DAT_A_LINK_HOLDOFF_ENABLE);
-
-            rc_ecmd |= data.writeBit(
-                PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER_BIT,
-                PB_SCONFIG_C10_DAT_LINK_HOLDOFF_MULTIPLIER);
-        }
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c10: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, pb_sconfig_c10_def, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c10: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c10: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (center #11)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_c11(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_c11: Start");
-
-    do
-    {
-        // build register content
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C11_RSP_CPU_RATIO_QUARTER,
-            PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[0],
-            (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[0]-
-             PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[0]+1));
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C11_RSP_CPU_RATIO_HALF,
-            PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[1],
-            (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[1]-
-             PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[1]+1));
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[i_smp.nom_cpu_delay],
-            PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[2],
-            (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[2]-
-             PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[2]+1));
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_C11_RSP_CPU_RATIO_TABLE[i_smp.full_cpu_delay],
-            PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[3],
-            (PB_SCONFIG_C11_RSP_CPU_RATIO_END_BIT[3]-
-             PB_SCONFIG_C11_RSP_CPU_RATIO_START_BIT[3]+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c11: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_C11_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_c11: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_c11: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (west/east #0)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_we0(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_we0: Start");
-
-    // set "safe" mode defaults
-    uint8_t cmd_c2i_done_launch  = 0x0;              // rc_p1
-    uint8_t crsp_i2c_dval_launch = 0x0;              // wc_p1
-    uint8_t data_i2c_dval_launch = 0x0;              // wc_p1
-    uint8_t data_c2i_done_launch = 0x0;              // rc_p1
-    uint8_t data_c2i_dctr_launch = 0x0;              // rc_p1
-    uint8_t rcmd_i2c_dval_launch = 0x0;              // wc_p1
-
-    do
-    {
-        // build register content
-        if (!i_smp.async_safe_mode)
-        {
-            // "performance" mode settings
-            cmd_c2i_done_launch  = 0x6;              // rc_m1
-            crsp_i2c_dval_launch = 0x3;              // wc
-            data_i2c_dval_launch = 0x2;              // wc_m1
-            data_c2i_done_launch = 0x3;              // rc
-            data_c2i_dctr_launch = 0x3;              // rc
-            rcmd_i2c_dval_launch = 0x3;              // wc
-
-            switch (i_smp.core_ceiling_ratio)
-            {
-                // dial back if ceiling is over 2x
-                case PROC_BUILD_SMP_CORE_RATIO_8_8:
-                    if (i_smp.freq_core_ceiling > (2 * i_smp.freq_pb))
-                    {
-                        FAPI_DBG("proc_build_smp_set_sconfig_we0: Clamping CRSP/RCMD/DATA i2c dval to safe mode based on ceiling frequency");
-                        crsp_i2c_dval_launch = 0x0;  // rc_p1
-                        rcmd_i2c_dval_launch = 0x0;  // rc_p1
-                        data_i2c_dval_launch = 0x3;  // wc
-                    }
-                    break;
-                case PROC_BUILD_SMP_CORE_RATIO_7_8:
-                case PROC_BUILD_SMP_CORE_RATIO_6_8:
-                case PROC_BUILD_SMP_CORE_RATIO_5_8:
-                case PROC_BUILD_SMP_CORE_RATIO_4_8:
-                case PROC_BUILD_SMP_CORE_RATIO_2_8:
-                    break;
-                default:
-                    FAPI_ERR("proc_build_smp_set_sconfig_we0: Unsupported core ceiling frequency ratio enum (%d)",
-                             i_smp.core_ceiling_ratio);
-                    const uint32_t& FREQ_PB = i_smp.freq_pb;
-                    const uint32_t& FREQ_CORE_CEILING = i_smp.freq_core_ceiling;
-                    const uint32_t& CORE_CEILING_RATIO = i_smp.core_ceiling_ratio;
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR);
-                    break;
-            }
-        }
-        if (rc)
-        {
-            break;
-        }
-
-        // cmd_c2i_done_launch
-        rc_ecmd |= data.insertFromRight(
-            cmd_c2i_done_launch,
-            PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_CMD_C2I_DONE_LAUNCH_START_BIT+1));
-
-        // cmd_c2i_late_rd_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE_BIT,
-            PB_SCONFIG_WE0_CMD_C2I_LATE_RD_MODE?1:0);
-
-        // cmd_c2i_delay_sp_rd
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD,
-            PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT,
-            (PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_END_BIT-
-             PB_SCONFIG_WE0_CMD_C2I_DELAY_SP_RD_START_BIT+1));
-
-        // cmd_c2i_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_CMD_C2I_SPARE_MODE?1:0);
-
-        // prsp_c2i_done_launch
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH_BIT,
-            PB_SCONFIG_WE0_PRSP_C2I_DONE_LAUNCH);
-
-        // prsp_c2i_hw070772_dis
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS_BIT,
-            PB_SCONFIG_WE0_PRSP_C2I_HW070772_DIS?1:0);
-
-        // prsp_c2i_nop_mode
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE,
-            PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT,
-            (PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_END_BIT-
-             PB_SCONFIG_WE0_PRSP_C2I_NOP_MODE_START_BIT+1));
-
-        // prsp_c2i_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_PRSP_C2I_SPARE_MODE?1:0);
-
-        // crsp_i2c_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            crsp_i2c_dval_launch,
-            PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_CRSP_I2C_DVAL_LAUNCH_START_BIT+1));
-
-        // crsp_i2c_hshake
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_CRSP_I2C_HSHAKE_BIT,
-            PB_SCONFIG_WE0_CRSP_I2C_HSHAKE?1:0);
-
-        // crsp_i2c_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_CRSP_I2C_SPARE_MODE?1:0);
-
-        // data_i2c_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            data_i2c_dval_launch,
-            PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_DATA_I2C_DVAL_LAUNCH_START_BIT+1));
-
-        // data_i2c_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_DATA_I2C_SPARE_MODE?1:0);
-
-        // data_i2c_force_fa_alloc
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC_BIT,
-            PB_SCONFIG_WE0_DATA_I2C_FORCE_FA_ALLOC?1:0);
-
-        // data_c2i_done_launch
-        rc_ecmd |= data.insertFromRight(
-            data_c2i_done_launch,
-            PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_DATA_C2I_DONE_LAUNCH_START_BIT+1));
-
-        // data_c2i_initial_req_dly_launch
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY,
-            PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT,
-            (PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_END_BIT-
-             PB_SCONFIG_WE0_DATA_C2I_INITIAL_REQ_DLY_START_BIT+1));
-
-        // data_c2i_dctr_launch
-        rc_ecmd |= data.insertFromRight(
-            data_c2i_dctr_launch,
-            PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_DATA_C2I_DCTR_LAUNCH_START_BIT+1));
-
-        // data_c2i_outstanding_req_count
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT_BIT,
-            PB_SCONFIG_WE0_DATA_C2I_OUTSTANDING_REQ_COUNT?1:0);
-
-        // data_c2i_req_id_assignment_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE_BIT,
-            PB_SCONFIG_WE0_DATA_C2I_REQ_ID_ASSIGNMENT_MODE?1:0);
-
-        // data_c2i_allow_fragmentation_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION_BIT,
-            PB_SCONFIG_WE0_DATA_C2I_ALLOW_FRAGMENTATION?1:0);
-
-        // data_c2i_serial_dreq_id_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID_BIT,
-            PB_SCONFIG_WE0_DATA_C2I_SERIAL_DREQ_ID?1:0);
-
-        // data_c2i_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_DATA_C2I_SPARE_MODE?1:0);
-
-        // rcmd_i2c_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            rcmd_i2c_dval_launch,
-            PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_RCMD_I2C_DVAL_LAUNCH_START_BIT+1));
-
-        // rcmd_i2c_hshake
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_RCMD_I2C_HSHAKE_BIT,
-            PB_SCONFIG_WE0_RCMD_I2C_HSHAKE?1:0);
-
-        // rcmd_i2c_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_RCMD_I2C_SPARE_MODE?1:0);
-
-        // fp_i2c_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH,
-            PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE0_FP_I2C_DVAL_LAUNCH_START_BIT+1));
-
-        // fp_i2c_hshake
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_FP_I2C_HSHAKE_BIT,
-            PB_SCONFIG_WE0_FP_I2C_HSHAKE?1:0);
-
-        // fp_i2c_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_FP_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_FP_I2C_SPARE_MODE?1:0);
-
-        // fp_c2i_done_launch
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH_BIT,
-            PB_SCONFIG_WE0_FP_C2I_DONE_LAUNCH);
-
-        // fp_c2i_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE0_FP_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE0_FP_C2I_SPARE_MODE?1:0);
-
-        // cpu_delay_full
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE0_CPU_DELAY_TABLE[i_smp.full_cpu_delay],
-            PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT,
-            (PB_SCONFIG_WE0_CPU_DELAY_FULL_END_BIT-
-             PB_SCONFIG_WE0_CPU_DELAY_FULL_START_BIT+1));
-
-        // cpu_delay_nom
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE0_CPU_DELAY_TABLE[i_smp.nom_cpu_delay],
-            PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT,
-            (PB_SCONFIG_WE0_CPU_DELAY_NOM_END_BIT-
-             PB_SCONFIG_WE0_CPU_DELAY_NOM_START_BIT+1));
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we0: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_WE0_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we0: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_we0: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (west/east #1)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_we1(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_we1: Start");
-
-    // set "safe" mode defaults
-    uint8_t cmd_c2i_dval_launch = 0x0;               // wc_p1
-    uint8_t crsp_i2c_done_launch = 0x0;              // rc_p1
-    uint8_t crsp_i2c_pty_rd_capture = 0x0;           // rc
-    uint8_t data_i2c_done_launch = 0x0;              // rc_p1
-    uint8_t data_i2c_dctr_launch = 0x0;              // rc_p1
-    uint8_t data_c2i_dval_launch = 0x0;              // wc_p1
-    uint8_t rcmd_i2c_done_launch = 0x0;              // rc_p1
-    uint8_t rcmd_i2c_pty_rd_capture = 0x0;           // rc
-    uint8_t attr_proc_pbiex_async_sel = fapi::ENUM_ATTR_PROC_PBIEX_ASYNC_SEL_SEL0;
-
-    do
-    {
-        // build register content
-        if (!i_smp.async_safe_mode)
-        {
-            // "performance" mode settings
-            crsp_i2c_done_launch = 0x1;              // rc
-            crsp_i2c_pty_rd_capture = 0x1;           // rc_p1
-            data_i2c_done_launch = 0x2;              // rc_m1
-            rcmd_i2c_done_launch = 0x1;              // rc
-            rcmd_i2c_pty_rd_capture = 0x1;           // rc_p1
-
-            switch (i_smp.core_floor_ratio)
-            {
-                case PROC_BUILD_SMP_CORE_RATIO_8_8:
-                case PROC_BUILD_SMP_CORE_RATIO_7_8:
-                case PROC_BUILD_SMP_CORE_RATIO_6_8:
-                case PROC_BUILD_SMP_CORE_RATIO_5_8:
-                    cmd_c2i_dval_launch = 0x3;       // wc
-                    data_i2c_dctr_launch = 0x1;      // rc_m2
-                    data_c2i_dval_launch = 0x2;      // wc_m1
-                    attr_proc_pbiex_async_sel = fapi::ENUM_ATTR_PROC_PBIEX_ASYNC_SEL_SEL0;
-                    break;
-                case PROC_BUILD_SMP_CORE_RATIO_4_8:
-                    cmd_c2i_dval_launch = 0x3;       // wc
-                    data_i2c_dctr_launch = 0x2;      // rc_m1
-                    data_c2i_dval_launch = 0x3;      // wc
-                    attr_proc_pbiex_async_sel = fapi::ENUM_ATTR_PROC_PBIEX_ASYNC_SEL_SEL1;
-                    break;
-                case PROC_BUILD_SMP_CORE_RATIO_2_8:
-                    cmd_c2i_dval_launch = 0x0;       // wc_p1
-                    data_i2c_dctr_launch = 0x3;      // rc
-                    data_c2i_dval_launch = 0x0;      // wc_p1
-                    attr_proc_pbiex_async_sel = fapi::ENUM_ATTR_PROC_PBIEX_ASYNC_SEL_SEL2;
-                    break;
-                default:
-                    FAPI_ERR("proc_build_smp_set_sconfig_we1: Unsupported core floor frequency ratio enum (%d)",
-                             i_smp.core_floor_ratio);
-                    const uint32_t& FREQ_PB = i_smp.freq_pb;
-                    const uint32_t& FREQ_CORE_FLOOR = i_smp.freq_core_floor;
-                    const uint32_t& CORE_FLOOR_RATIO = i_smp.core_floor_ratio;
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR);
-                    break;
-            }
-        }
-        if (rc)
-        {
-            break;
-        }
-
-        // write async select attribute
-        rc = FAPI_ATTR_SET(ATTR_PROC_PBIEX_ASYNC_SEL,
-                           NULL,
-                           attr_proc_pbiex_async_sel);
-        if (rc)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we1: Error writing ATTR_PROC_PBIEX_ASYNC_SEL");
-            break;
-        }
-
-        // cmd_c2i_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            cmd_c2i_dval_launch,
-            PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_CMD_C2I_DVAL_LAUNCH_START_BIT+1));
-
-        // cmd_c2i_early_req_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE_BIT,
-            PB_SCONFIG_WE1_CMD_C2I_EARLY_REQ_MODE?1:0);
-
-        // cmd_c2i_spare_bit
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_CMD_C2I_SPARE_BIT,
-            PB_SCONFIG_WE1_CMD_C2I_SPARE?1:0);
-
-        // cmd_c2i_spare_mode_bit
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_CMD_C2I_SPARE_MODE?1:0);
-
-        // prsp_c2i_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH,
-            PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_PRSP_C2I_DVAL_LAUNCH_START_BIT+1));
-
-        // prsp_c2i_hshake
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_PRSP_C2I_HSHAKE_BIT,
-            PB_SCONFIG_WE1_PRSP_C2I_HSHAKE?1:0);
-
-        // prsp_c2i_spare mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_PRSP_C2I_SPARE_MODE?1:0);
-
-        // crsp_i2c_done_launch
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_CRSP_I2C_DONE_LAUNCH_BIT,
-            crsp_i2c_done_launch);
-
-        // crsp_i2c_pty_rd_capture
-        rc_ecmd |= data.insertFromRight(
-            crsp_i2c_pty_rd_capture,
-            PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT,
-            (PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_END_BIT-
-             PB_SCONFIG_WE1_CRSP_I2C_PTY_RD_CAPTURE_START_BIT+1));
-
-        // crsp_i2c_spare mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_CRSP_I2C_SPARE_MODE?1:0);
-
-        // data_i2c_done_launch
-        rc_ecmd |= data.insertFromRight(
-            data_i2c_done_launch,
-            PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_DATA_I2C_DONE_LAUNCH_START_BIT+1));
-
-        // data_i2c_dctr_launch
-        rc_ecmd |= data.insertFromRight(
-            data_i2c_dctr_launch,
-            PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_DATA_I2C_DCTR_LAUNCH_START_BIT+1));
-
-        // data_i2c_spare mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_DATA_I2C_SPARE_MODE?1:0);
-
-        // data_c2i_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            data_c2i_dval_launch,
-            PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_DATA_C2I_DVAL_LAUNCH_START_BIT+1));
-
-        // data_c2i_dreq_launch
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH,
-            PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_DATA_C2I_DREQ_LAUNCH_START_BIT+1));
-
-        // data_c2i_spare mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_DATA_C2I_SPARE_MODE?1:0);
-
-        // rcmd_i2c_done_launch
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_RCMD_I2C_DONE_LAUNCH_BIT,
-            rcmd_i2c_done_launch);
-
-        // rcmd_i2c_l3_not_use_dcbfl
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL_BIT,
-            PB_SCONFIG_WE1_RCMD_I2C_L3_NOT_USE_DCBFL?1:0);
-
-        // rcmd_i2c_pty_rd_capture_launch
-        rc_ecmd |= data.insertFromRight(
-            rcmd_i2c_pty_rd_capture,
-            PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT,
-            (PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_END_BIT-
-             PB_SCONFIG_WE1_RCMD_I2C_PTY_RD_CAPTURE_START_BIT+1));
-
-        // rcmd_i2c_pty_inject
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT_BIT,
-            PB_SCONFIG_WE1_RCMD_I2C_PTY_INJECT?1:0);
-
-        // rcmd_i2c_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_RCMD_I2C_SPARE_MODE?1:0);
-
-        // fp_i2c_done_launch
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH_BIT,
-            PB_SCONFIG_WE1_FP_I2C_DONE_LAUNCH?1:0);
-
-        // fp_i2c_spare
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_FP_I2C_SPARE_BIT,
-            PB_SCONFIG_WE1_FP_I2C_SPARE?1:0);
-
-        // fp_i2c_pty_rd_capture_launch
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE,
-            PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT,
-            (PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_END_BIT-
-             PB_SCONFIG_WE1_FP_I2C_PTY_RD_CAPTURE_START_BIT+1));
-
-        // fp_i2c_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_FP_I2C_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_FP_I2C_SPARE_MODE?1:0);
-
-        // fp_c2i_dval_launch
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH,
-            PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT,
-            (PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_END_BIT-
-             PB_SCONFIG_WE1_FP_C2I_DVAL_LAUNCH_START_BIT+1));
-
-        // fp_c2i_hshake
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_FP_C2I_HSHAKE_BIT,
-            PB_SCONFIG_WE1_FP_C2I_HSHAKE?1:0);
-
-        // fp_c2i_spare_mode
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE1_FP_C2I_SPARE_MODE_BIT,
-            PB_SCONFIG_WE1_FP_C2I_SPARE_MODE?1:0);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we1: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(i_smp_chip, PB_SCONFIG_WE1_DEF, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we1: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_we1: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB serial SCOM chain (west/east #5)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_sconfig_we5(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    uint8_t ver2 = 0x0;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_sconfig_we5: Start");
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2,
-                           &(i_smp_chip.chip->this_chip),
-                           ver2);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_FBC_SERIAL_SCOM_WE5_VER2");
-            break;
-        }
-
-        // build register content
-        // pb_cfg_lock_on_links
-        uint32_t PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER2):
-            (PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT_VER1);
-
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE5_LOCK_ON_LINKS_BIT,
-            PB_SCONFIG_WE5_LOCK_ON_LINKS?1:0);
-
-        // pb_cfg_x_on_link_tok_agg_threshold
-        uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2):
-            (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2):
-            (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD,
-            PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT,
-            (PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_END_BIT-
-             PB_SCONFIG_WE5_X_ON_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
-
-        // pb_cfg_x_off_link_tok_agg_threshold
-        uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2):
-            (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2):
-            (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD,
-            PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT,
-            (PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_END_BIT-
-             PB_SCONFIG_WE5_X_OFF_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
-
-        // pb_cfg_x_a_link_tok_agg_threshold
-        uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2):
-            (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2):
-            (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD,
-            PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT,
-            (PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_END_BIT-
-             PB_SCONFIG_WE5_A_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
-
-        // pb_cfg_x_f_link_tok_agg_threshold
-        uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER2):
-            (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER2):
-            (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD,
-            PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT,
-            (PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_END_BIT-
-             PB_SCONFIG_WE5_F_LINK_TOK_AGG_THRESHOLD_START_BIT+1));
-
-        // pb_cfg_x_a_link_tok_ind_threshold
-        uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER2):
-            (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER2):
-            (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD,
-            PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT,
-            (PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_END_BIT-
-             PB_SCONFIG_WE5_A_LINK_TOK_IND_THRESHOLD_START_BIT+1));
-
-        // pb_cfg_passthru_enable
-        uint32_t PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER2):
-            (PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT_VER1);
-
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE5_PASSTHRU_ENABLE_BIT,
-            PB_SCONFIG_WE5_PASSTHRU_ENABLE?1:0);
-
-        // pb_cfg_passthru_x_priority
-        uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER2):
-            (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER2):
-            (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY,
-            PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT,
-            (PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_END_BIT-
-             PB_SCONFIG_WE5_PASSTHRU_X_PRIORITY_START_BIT+1));
-
-        // pb_cfg_passthru_a_priority
-        uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER2):
-            (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER2):
-            (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY,
-            PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT,
-            (PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_END_BIT-
-             PB_SCONFIG_WE5_PASSTHRU_A_PRIORITY_START_BIT+1));
-
-        // pb_cfg_a_tok_init
-        uint32_t PB_SCONFIG_WE5_A_TOK_INIT_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER2):
-            (PB_SCONFIG_WE5_A_TOK_INIT_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_A_TOK_INIT_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER2):
-            (PB_SCONFIG_WE5_A_TOK_INIT_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_A_TOK_INIT,
-            PB_SCONFIG_WE5_A_TOK_INIT_START_BIT,
-            (PB_SCONFIG_WE5_A_TOK_INIT_END_BIT-
-             PB_SCONFIG_WE5_A_TOK_INIT_START_BIT+1));
-
-        // pb_cfg_f_tok_init
-        uint32_t PB_SCONFIG_WE5_F_TOK_INIT_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER2):
-            (PB_SCONFIG_WE5_F_TOK_INIT_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_F_TOK_INIT_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER2):
-            (PB_SCONFIG_WE5_F_TOK_INIT_END_BIT_VER1);
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_F_TOK_INIT,
-            PB_SCONFIG_WE5_F_TOK_INIT_START_BIT,
-            (PB_SCONFIG_WE5_F_TOK_INIT_END_BIT-
-             PB_SCONFIG_WE5_F_TOK_INIT_START_BIT+1));
-
-        // pb_cfg_em_fp_enable
-        uint32_t PB_SCONFIG_WE5_EM_FP_ENABLE_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER2):
-            (PB_SCONFIG_WE5_EM_FP_ENABLE_BIT_VER1);
-
-        rc_ecmd |= data.writeBit(
-            PB_SCONFIG_WE5_EM_FP_ENABLE_BIT,
-            PB_SCONFIG_WE5_EM_FP_ENABLE?1:0);
-
-        // spare
-        uint32_t PB_SCONFIG_WE5_SPARE_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_SPARE_START_BIT_VER2):
-            (PB_SCONFIG_WE5_SPARE_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_SPARE_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_SPARE_END_BIT_VER2):
-            (PB_SCONFIG_WE5_SPARE_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_SPARE,
-            PB_SCONFIG_WE5_SPARE_START_BIT,
-            (PB_SCONFIG_WE5_SPARE_END_BIT-
-             PB_SCONFIG_WE5_SPARE_START_BIT+1));
-
-        // pb_cfg_a_ind_threshold
-        if (ver2)
-        {
-            rc_ecmd |= data.writeBit(
-                PB_SCONFIG_WE5_A_IND_THRESHOLD_BIT_VER2,
-                PB_SCONFIG_WE5_A_IND_THRESHOLD?1:0);
-        }
-
-        // pb_cfg_mem_stv_priority
-        uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER2):
-            (PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT_VER1);
-
-        uint32_t PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT =
-            (ver2)?
-            (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER2):
-            (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT_VER1);
-
-        rc_ecmd |= data.insertFromRight(
-            PB_SCONFIG_WE5_MEM_STV_PRIORITY,
-            PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT,
-            (PB_SCONFIG_WE5_MEM_STV_PRIORITY_END_BIT-
-             PB_SCONFIG_WE5_MEM_STV_PRIORITY_START_BIT+1));
-
-        // pb_cfg_x_off_set
-        if (ver2)
-        {
-            rc_ecmd |= data.writeBit(
-                PB_SCONFIG_WE5_X_OFF_SEL_BIT_VER2,
-                PB_SCONFIG_WE5_X_OFF_SEL?1:0);
-        }
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we5: Error 0x%x setting up PB Serial Configuration load register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // call common routine to program chain
-        rc = proc_build_smp_set_sconfig(
-            i_smp_chip,
-            (ver2)?(PB_SCONFIG_WE5_DEF_VER2):(PB_SCONFIG_WE5_DEF_VER1),
-            data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_sconfig_we5: Error from proc_build_smp_set_sconfig");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_sconfig_we5: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_set_fbc_cd(
-    proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_fbc_cd: Start");
-
-    for (n_iter = i_smp.nodes.begin();
-         (n_iter != i_smp.nodes.end()) && (rc.ok());
-         n_iter++)
-    {
-        for (p_iter = n_iter->second.chips.begin();
-             (p_iter != n_iter->second.chips.end()) && (rc.ok());
-             p_iter++)
-        {
-            // program center chains
-            rc = proc_build_smp_set_sconfig_c4(p_iter->second);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c4");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c5(p_iter->second);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c5");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c6(p_iter->second);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c6");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c7(p_iter->second);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c7");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c8(p_iter->second);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c8");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c9(p_iter->second);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c9");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c10(p_iter->second, i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c10");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_c11(p_iter->second, i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_c11");
-                break;
-            }
-
-            // program east/west chains
-            rc = proc_build_smp_set_sconfig_we0(p_iter->second, i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_we0");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_we1(p_iter->second, i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_we1");
-                break;
-            }
-
-            rc = proc_build_smp_set_sconfig_we5(p_iter->second, i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_set_sconfig_we5");
-                break;
-            }
-
-            // issue single switch CD to force all updates to occur
-            rc = proc_build_smp_switch_cd(p_iter->second, i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_cd: Error from proc_build_smp_switch_cd");
-                break;
-            }
-        }
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_fbc_cd: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
deleted file mode 100644
index 6d7d9e738..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H
+++ /dev/null
@@ -1,84 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_cd.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_cd.H,v 1.17 2014/02/23 21:41:07 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_cd.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_fbc_cd.H
-// *! DESCRIPTION : Fabric configuration (hotplug, CD) functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BUILD_SMP_FBC_CD_H_
-#define _PROC_BUILD_SMP_FBC_CD_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp.H>
-#include <p8_scom_addresses.H>
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: program fabric configuration register (hotplug, C/D set)
-// parameters: i_smp => structure encapsulating SMP topology
-// returns: FAPI_RC_SUCCESS if register reads are successful and all shadow
-//               registers are equivalent,
-//          FAPI_RC_PLAT_ERR_ADU_LOCKED if operation failed due to state of
-//              ADU atomic lock,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_OPERATION if an unsupported operation
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_LOCK_ATTEMPTS if invalid number of attempts
-//              is specified,
-//          RC_PROC_ADU_UTILS_INVALID_FBC_OP if invalid fabric operation
-//              parameters are specified,
-//          RC_PROC_BUILD_SMP_ADU_STATUS_MISMATCH if ADU status mismatches
-//              for switch operation,
-//          RC_PROC_BUILD_SMP_CORE_FLOOR_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          RC_PROC_BUILD_SMP_CORE_CEILING_RATIO_ERR if cache/nest frequency
-//              ratio is unsupported,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_fbc_cd(
-    proc_build_smp_system& i_smp);
-
-
-} // extern "C"
-
-#endif // _PROC_BUILD_SMP_FBC_CD_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C
deleted file mode 100644
index c6ed7fbac..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C
+++ /dev/null
@@ -1,966 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_nohp.C,v 1.7 2015/02/09 22:37:59 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_fbc_nohp.C
-// *! DESCRIPTION : Fabric configuration (non-hotplug) functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp_fbc_nohp.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// enumerate chips per group configurations
-enum proc_build_smp_chips_per_group {
-    PROC_BUILD_SMP_1CPG = 0x0,
-    PROC_BUILD_SMP_2CPG = 0x1,
-    PROC_BUILD_SMP_4CPG = 0x2
-};
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//
-// PB Mode register field/bit definitions
-//
-
-const uint32_t PB_MODE_CHIP_IS_SYSTEM_BIT = 4;
-
-const uint32_t PB_MODE_SHADOWS[PROC_BUILD_SMP_NUM_SHADOWS] =
-{
-    PB_MODE_WEST_0x02010C0A,
-    PB_MODE_CENT_0x02010C4A,
-    PB_MODE_EAST_0x02010C8A
-};
-
-
-//
-// Group/Remote Group/System Command Pacing Rate register field/bit definitions
-//
-
-const uint8_t PROC_BUILD_SMP_DP_LEVELS = 8;
-
-const uint8_t PB_GP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   1,   2,   3,   4,   5,   6,   7,   8 };
-const uint8_t PB_GP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   2,   4,   6,   8,   8,   8,   8,   8 };
-const uint8_t PB_RGP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,   9,   9,   9,  10,  10,  11,  12 };
-const uint8_t PB_RGP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,  10,  11,  12,  13,  14,  15,  16 };
-const uint8_t PB_SP_CMD_RATE_DP_LO_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   9,  10,  11,  12,  13,  14,  15,  16 };
-const uint8_t PB_SP_CMD_RATE_DP_HI_1CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  12,  13,  14,  16,  18,  20,  22,  24 };
-
-const uint8_t PB_GP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   3,   4,   5,   6,   7,   8,  10,  16 };
-const uint8_t PB_GP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   4,   5,   6,   7,   8,  10,  12,  16 };
-const uint8_t PB_RGP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,  10,  11,  12,  13,  14,  16,  32 };
-const uint8_t PB_RGP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS] = {  12,  13,  14,  15,  16,  20,  32,  32 };
-const uint8_t PB_SP_CMD_RATE_DP_LO_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  12,  13,  14,  15,  16,  20,  32,  64 };
-const uint8_t PB_SP_CMD_RATE_DP_HI_2CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  20,  22,  24,  26,  32,  40,  64,  64 };
-
-const uint8_t PB_GP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   3,   4,   5,   6,   8,  10,  16,  32 };
-const uint8_t PB_GP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {   4,   6,   8,  12,  16,  20,  32,  32 };
-const uint8_t PB_RGP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS] = {   9,  10,  11,  12,  16,  20,  32,  64 };
-const uint8_t PB_RGP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS] = {  12,  14,  16,  24,  32,  40,  64,  64 };
-const uint8_t PB_SP_CMD_RATE_DP_LO_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  12,  14,  16,  24,  32,  40,  64, 128 };
-const uint8_t PB_SP_CMD_RATE_DP_HI_4CPG[PROC_BUILD_SMP_DP_LEVELS]  = {  20,  24,  32,  48,  64,  80, 128, 128 };
-
-const uint32_t PB_SCOPE_COMMAND_PACING_LVL_START_BIT[PROC_BUILD_SMP_DP_LEVELS] = {  0,  8, 16, 24, 32, 40, 48, 56 };
-const uint32_t PB_SCOPE_COMMAND_PACING_LVL_END_BIT[PROC_BUILD_SMP_DP_LEVELS]   = {  7, 15, 23, 31, 39, 47, 55, 63 };
-
-
-// define set of group scope command pacing rate settings
-struct proc_build_smp_gp_low_pacing_table
-{
-    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
-    {
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
-        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_LO_1CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_LO_2CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_LO_4CPG));
-        return m;
-    }
-    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
-};
-
-struct proc_build_smp_gp_high_pacing_table
-{
-    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
-    {
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
-        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_GP_CMD_RATE_DP_HI_1CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_GP_CMD_RATE_DP_HI_2CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_GP_CMD_RATE_DP_HI_4CPG));
-        return m;
-    }
-    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
-};
-
-struct proc_build_smp_sp_low_pacing_table
-{
-    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
-    {
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
-        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_LO_1CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_LO_2CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_LO_4CPG));
-        return m;
-    }
-    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
-};
-
-struct proc_build_smp_sp_high_pacing_table
-{
-    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
-    {
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
-        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_SP_CMD_RATE_DP_HI_1CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_SP_CMD_RATE_DP_HI_2CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_SP_CMD_RATE_DP_HI_4CPG));
-        return m;
-    }
-    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
-};
-
-struct proc_build_smp_rgp_low_pacing_table
-{
-    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
-    {
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
-        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_LO_1CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_LO_2CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_LO_4CPG));
-        return m;
-    }
-    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
-};
-
-struct proc_build_smp_rgp_high_pacing_table
-{
-    static std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> create_map()
-    {
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> m;
-        m.insert(std::make_pair(PROC_BUILD_SMP_1CPG, &PB_RGP_CMD_RATE_DP_HI_1CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_2CPG, &PB_RGP_CMD_RATE_DP_HI_2CPG));
-        m.insert(std::make_pair(PROC_BUILD_SMP_4CPG, &PB_RGP_CMD_RATE_DP_HI_4CPG));
-        return m;
-    }
-    static const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> xlate_map;
-};
-
-
-
-const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_gp_low_pacing_table::xlate_map =
-    proc_build_smp_gp_low_pacing_table::create_map();
-
-const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_gp_high_pacing_table::xlate_map =
-    proc_build_smp_gp_high_pacing_table::create_map();
-
-const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_sp_low_pacing_table::xlate_map =
-    proc_build_smp_sp_low_pacing_table::create_map();
-
-const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_sp_high_pacing_table::xlate_map =
-    proc_build_smp_sp_high_pacing_table::create_map();
-
-const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_rgp_low_pacing_table::xlate_map =
-    proc_build_smp_rgp_low_pacing_table::create_map();
-
-const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]> proc_build_smp_rgp_high_pacing_table::xlate_map =
-    proc_build_smp_rgp_high_pacing_table::create_map();
-
-
-//
-// X Link Mode register field/bit definitions
-//
-
-const uint32_t PB_X_MODE_TRACE_ENABLE_BIT = 4;
-const uint32_t PB_X_MODE_TRACE_SELECT_START_BIT = 5;
-const uint32_t PB_X_MODE_TRACE_SELECT_END_BIT = 7;
-
-
-//
-// A Link Trace register field/bit definitions
-//
-
-const uint32_t PB_A_TRACE_A0_OUT_SEL0_START_BIT = 0;
-const uint32_t PB_A_TRACE_A0_OUT_SEL0_END_BIT = 1;
-const uint32_t PB_A_TRACE_A0_OUT_SEL1_START_BIT = 2;
-const uint32_t PB_A_TRACE_A0_OUT_SEL1_END_BIT = 3;
-const uint32_t PB_A_TRACE_A0_OUT_SEL2_START_BIT = 4;
-const uint32_t PB_A_TRACE_A0_OUT_SEL2_END_BIT = 5;
-const uint32_t PB_A_TRACE_A1_OUT_SEL0_START_BIT = 6;
-const uint32_t PB_A_TRACE_A1_OUT_SEL0_END_BIT = 7;
-const uint32_t PB_A_TRACE_A1_OUT_SEL1_START_BIT = 8;
-const uint32_t PB_A_TRACE_A1_OUT_SEL1_END_BIT = 9;
-const uint32_t PB_A_TRACE_A1_OUT_SEL2_START_BIT = 10;
-const uint32_t PB_A_TRACE_A1_OUT_SEL2_END_BIT = 11;
-const uint32_t PB_A_TRACE_A2_OUT_SEL0_START_BIT = 12;
-const uint32_t PB_A_TRACE_A2_OUT_SEL0_END_BIT = 13;
-const uint32_t PB_A_TRACE_A2_OUT_SEL1_START_BIT = 14;
-const uint32_t PB_A_TRACE_A2_OUT_SEL1_END_BIT = 15;
-const uint32_t PB_A_TRACE_A2_OUT_SEL2_START_BIT = 16;
-const uint32_t PB_A_TRACE_A2_OUT_SEL2_END_BIT = 17;
-
-//
-// F Link Trace register field/bit definitions
-//
-
-const uint32_t PB_F_TRACE_F0_OUT_SEL0_START_BIT = 0;
-const uint32_t PB_F_TRACE_F0_OUT_SEL0_END_BIT = 3;
-const uint32_t PB_F_TRACE_F0_OUT_SEL1_START_BIT = 8;
-const uint32_t PB_F_TRACE_F0_OUT_SEL1_END_BIT = 11;
-const uint32_t PB_F_TRACE_F1_OUT_SEL0_START_BIT = 16;
-const uint32_t PB_F_TRACE_F1_OUT_SEL0_END_BIT = 19;
-const uint32_t PB_F_TRACE_F1_OUT_SEL1_START_BIT = 24;
-const uint32_t PB_F_TRACE_F1_OUT_SEL1_END_BIT = 27;
-const uint32_t PB_F_TRACE_F0_OBS_SEL = 32;
-const uint32_t PB_F_TRACE_F1_OBS_SEL = 33;
-
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility function to determine number of chips present
-//           in enclosing group
-// parameters: i_smp_chip        => structure encapsulating SMP chip
-//             i_smp             => structure encapsulating SMP topology
-//             o_chips_per_group => enum representing number of chips in
-//                                  group enclosing i_smp_chip
-// returns: FAPI_RC_SUCCESS if output group size is valid,
-//          else RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
-//              small/large
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_calc_chips_per_group(
-    const proc_build_smp_chip& i_smp_chip,
-    proc_build_smp_system& i_smp,
-    proc_build_smp_chips_per_group& o_chips_per_group)
-{
-    fapi::ReturnCode rc;
-    uint8_t chips_per_group_exact;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_calc_chips_per_group: Start");
-
-    chips_per_group_exact = i_smp.nodes[i_smp_chip.node_id].chips.size();
-    switch(chips_per_group_exact)
-    {
-        case 1:
-            o_chips_per_group = PROC_BUILD_SMP_1CPG;
-            break;
-        case 2:
-            o_chips_per_group = PROC_BUILD_SMP_2CPG;
-            break;
-        case 3:
-        case 4:
-            o_chips_per_group = PROC_BUILD_SMP_4CPG;
-            break;
-        default:
-            FAPI_ERR("proc_build_smp_calc_chips_per_group: Unsupported group size (=%d)",
-                     chips_per_group_exact);
-            const fapi::Target& TARGET = i_smp_chip.chip->this_chip;
-            const uint8_t& GROUP_SIZE = chips_per_group_exact;
-            const proc_fab_smp_node_id & NODE_ID = i_smp_chip.node_id;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR);
-            break;
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_calc_chips_per_group: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to program one command scope drop priority
-//           register
-// parameters: i_smp_chip        => structure encapsulating SMP chip
-//             i_chips_per_group => enum representing chips in group enclosing
-//                                  i_smp_chip
-//             i_map_table       => map defining drop priority programming rates
-//             i_scom_addr       => target SCOM register
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR if pacing rate table lookup
-//              is unsuccessful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_pacing_rate(
-    const proc_build_smp_chip& i_smp_chip,
-    const proc_build_smp_chips_per_group& i_chips_per_group,
-    const std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]>& i_map_table,
-    const uint32_t i_scom_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_pacing_rate: Start");
-
-    do
-    {
-        // access map table
-        std::map<uint8_t, const uint8_t(*)[PROC_BUILD_SMP_DP_LEVELS]>::const_iterator m =
-            i_map_table.find(i_chips_per_group);
-
-        if (m == i_map_table.end())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rate: Pacing rate map table lookup failed");
-            const fapi::Target& TARGET = i_smp_chip.chip->this_chip;
-            const proc_build_smp_chips_per_group& GROUP_SIZE = i_chips_per_group;
-            const proc_fab_smp_node_id& NODE_ID = i_smp_chip.node_id;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR);
-            break;
-        }
-
-        // set all drop priority level fields
-        for (uint8_t l = 0; l < PROC_BUILD_SMP_DP_LEVELS; l++)
-        {
-            // pb_cfg_##_cmd_rate_dp#_lvl#
-            rc_ecmd |= data.insertFromRight(
-                (*(m->second))[l],
-                PB_SCOPE_COMMAND_PACING_LVL_START_BIT[l],
-                (PB_SCOPE_COMMAND_PACING_LVL_END_BIT[l]-
-                 PB_SCOPE_COMMAND_PACING_LVL_START_BIT[l]+1));
-        }
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rate: Error 0x%x setting up data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register
-        rc = fapiPutScom(i_smp_chip.chip->this_chip, i_scom_addr, data);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rate: fapiPutScom error (%08X)",
-                     i_scom_addr);
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_pacing_rate: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program all command scope drop priority registers
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP topology
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
-//              small/large,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_pacing_rates(
-    const proc_build_smp_chip& i_smp_chip,
-    proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    proc_build_smp_chips_per_group chips_per_group;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_pacing_rates: Start");
-
-    do
-    {
-        // determine number of chips in enclosing group (use to index proper
-        // drop priority table)
-        rc = proc_build_smp_calc_chips_per_group(i_smp_chip,
-                                                 i_smp,
-                                                 chips_per_group);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_calc_chips_per_group");
-            break;
-        }
-
-        // group (low)
-        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
-                                            chips_per_group,
-                                            proc_build_smp_gp_low_pacing_table::xlate_map,
-                                            PB_GP_CMD_RATE_DP_LO_0x02010C62);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (GP low)");
-            break;
-        }
-
-        // group (high)
-        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
-                                            chips_per_group,
-                                            proc_build_smp_gp_high_pacing_table::xlate_map,
-                                            PB_GP_CMD_RATE_DP_HI_0x02010C63);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (GP high)");
-            break;
-        }
-
-        // remote group (low)
-        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
-                                            chips_per_group,
-                                            proc_build_smp_rgp_low_pacing_table::xlate_map,
-                                            PB_RGP_CMD_RATE_DP_LO_0x02010C64);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (RGP low)");
-            break;
-        }
-
-        // remote group (high)
-        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
-                                            chips_per_group,
-                                            proc_build_smp_rgp_high_pacing_table::xlate_map,
-                                            PB_RGP_CMD_RATE_DP_HI_0x02010C65);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (RGP high)");
-            break;
-        }
-
-        // system (low)
-        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
-                                            chips_per_group,
-                                            proc_build_smp_sp_low_pacing_table::xlate_map,
-                                            PB_SP_CMD_RATE_DP_LO_0x02010C66);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (SP low)");
-            break;
-        }
-
-        // system (high)
-        rc = proc_build_smp_set_pacing_rate(i_smp_chip,
-                                            chips_per_group,
-                                            proc_build_smp_sp_high_pacing_table::xlate_map,
-                                            PB_SP_CMD_RATE_DP_HI_0x02010C67);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_pacing_rates: Error from proc_build_smp_set_pacing_rate (SP high)");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_pacing_rates: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB mode register
-// parameters: i_smp_chip => structure encapsulating SMP chip
-//             i_smp      => structure encapsulating SMP topology
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_pb_mode(
-    const proc_build_smp_chip& i_smp_chip,
-    proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64), mask(64);
-    bool chip_is_system = false;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_pb_mode: Start");
-
-    do
-    {
-        // compute derived register fields
-        // pb_cfg_chip_is_system
-        // set for single chip SMP, only if AVP mode is off
-        chip_is_system = ((i_smp.nodes.size() == 1) &&
-                          (i_smp.nodes[i_smp_chip.node_id].chips.size() == 1) &&
-                          (!i_smp.avp_mode));
-
-        // pb_cfg_chip_is_system
-        rc_ecmd |= data.writeBit(PB_MODE_CHIP_IS_SYSTEM_BIT,
-                                 chip_is_system?1:0);
-        rc_ecmd |= mask.setBit(PB_MODE_CHIP_IS_SYSTEM_BIT);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_pb_mode: Error 0x%x setting up PB Mode register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write west/center/east register copies (use mask to avoid overriding
-        // other configuration settings in register)
-        for (uint8_t r = 0; r < PROC_BUILD_SMP_NUM_SHADOWS; r++)
-        {
-            rc = fapiPutScomUnderMask(i_smp_chip.chip->this_chip,
-                                      PB_MODE_SHADOWS[r],
-                                      data,
-                                      mask);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_pb_mode: fapiPutScomUnderMask error (%08X)",
-                         PB_MODE_SHADOWS[r]);
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_pb_mode: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB X Link Mode register (configure trace selection based
-//           on first active link)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_x_trace(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64), mask(64);
-    bool trace_enable = false;
-    uint8_t trace_sel = 0x0;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_x_trace: Start");
-
-    do
-    {
-        // find first configured link, set to trace outbound traffic
-        if (i_smp_chip.chip->x0_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            trace_enable = true;
-            trace_sel = 0x4;
-        }
-        else if (i_smp_chip.chip->x1_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            trace_enable = true;
-            trace_sel = 0x5;
-        }
-        else if (i_smp_chip.chip->x2_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            trace_enable = true;
-            trace_sel = 0x6;
-        }
-        else if (i_smp_chip.chip->x3_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            trace_enable = true;
-            trace_sel = 0x7;
-        }
-
-        // build data buffer
-        // trace enable
-        rc_ecmd |= data.writeBit(
-            PB_X_MODE_TRACE_ENABLE_BIT,
-            trace_enable?1:0);
-        rc_ecmd |= mask.setBit(
-            PB_X_MODE_TRACE_ENABLE_BIT);
-
-        // trace select
-        rc_ecmd |= data.insertFromRight(
-            trace_sel,
-            PB_X_MODE_TRACE_SELECT_START_BIT,
-            (PB_X_MODE_TRACE_SELECT_END_BIT-
-             PB_X_MODE_TRACE_SELECT_START_BIT)+1);
-        rc_ecmd |= mask.setBit(
-            PB_X_MODE_TRACE_SELECT_START_BIT,
-            (PB_X_MODE_TRACE_SELECT_END_BIT-
-             PB_X_MODE_TRACE_SELECT_START_BIT)+1);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_x_trace: Error 0x%x setting up X Link Mode register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register
-        rc = fapiPutScomUnderMask(i_smp_chip.chip->this_chip,
-                                  PB_X_MODE_0x04010C0A,
-                                  data,
-                                  mask);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_x_trace: fapiPutScomUnderMask error (PB_X_MODE_0x04010C0A)");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_x_trace: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB A Link Trace register (configure trace selection based
-//           on first active link)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_a_trace(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64);
-    uint8_t a0_out_sel = 0x0;
-    uint8_t a1_out_sel = 0x0;
-    uint8_t a2_out_sel = 0x0;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_a_trace: Start");
-
-    do
-    {
-        // find first configured link, set to trace outbound traffic
-        if (i_smp_chip.chip->a0_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            a0_out_sel = 0x1;
-            a1_out_sel = 0x0;
-            a2_out_sel = 0x0;
-        }
-        else if (i_smp_chip.chip->a1_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            a0_out_sel = 0x0;
-            a1_out_sel = 0x1;
-            a2_out_sel = 0x0;
-        }
-        else if (i_smp_chip.chip->a2_chip.getType() != fapi::TARGET_TYPE_NONE)
-        {
-            a0_out_sel = 0x0;
-            a1_out_sel = 0x0;
-            a2_out_sel = 0x1;
-        }
-
-        // build data buffer (clear previous configuration)
-        // A0 outbound trace select
-        rc_ecmd |= data.insertFromRight(
-            a0_out_sel,
-            PB_A_TRACE_A0_OUT_SEL0_START_BIT,
-            (PB_A_TRACE_A0_OUT_SEL0_END_BIT-
-             PB_A_TRACE_A0_OUT_SEL0_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            a0_out_sel,
-            PB_A_TRACE_A0_OUT_SEL1_START_BIT,
-            (PB_A_TRACE_A0_OUT_SEL1_END_BIT-
-             PB_A_TRACE_A0_OUT_SEL1_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            a0_out_sel,
-            PB_A_TRACE_A0_OUT_SEL2_START_BIT,
-            (PB_A_TRACE_A0_OUT_SEL2_END_BIT-
-             PB_A_TRACE_A0_OUT_SEL2_START_BIT)+1);
-
-        // A1 outbound trace select
-        rc_ecmd |= data.insertFromRight(
-            a1_out_sel,
-            PB_A_TRACE_A1_OUT_SEL0_START_BIT,
-            (PB_A_TRACE_A1_OUT_SEL0_END_BIT-
-             PB_A_TRACE_A1_OUT_SEL0_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            a1_out_sel,
-            PB_A_TRACE_A1_OUT_SEL1_START_BIT,
-            (PB_A_TRACE_A1_OUT_SEL1_END_BIT-
-             PB_A_TRACE_A1_OUT_SEL1_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            a1_out_sel,
-            PB_A_TRACE_A1_OUT_SEL2_START_BIT,
-            (PB_A_TRACE_A1_OUT_SEL2_END_BIT-
-             PB_A_TRACE_A1_OUT_SEL2_START_BIT)+1);
-
-        // A2 outbound trace select
-        rc_ecmd |= data.insertFromRight(
-            a2_out_sel,
-            PB_A_TRACE_A2_OUT_SEL0_START_BIT,
-            (PB_A_TRACE_A2_OUT_SEL0_END_BIT-
-             PB_A_TRACE_A2_OUT_SEL0_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            a2_out_sel,
-            PB_A_TRACE_A2_OUT_SEL1_START_BIT,
-            (PB_A_TRACE_A2_OUT_SEL1_END_BIT-
-             PB_A_TRACE_A2_OUT_SEL1_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            a2_out_sel,
-            PB_A_TRACE_A2_OUT_SEL2_START_BIT,
-            (PB_A_TRACE_A2_OUT_SEL2_END_BIT-
-             PB_A_TRACE_A2_OUT_SEL2_START_BIT)+1);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_a_trace: Error 0x%x setting up A Link Trace register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register
-        rc = fapiPutScom(i_smp_chip.chip->this_chip,
-                         PB_A_TRACE_0x08010812,
-                         data);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_a_trace: fapiPutScom error (PB_A_TRACE_0x08010812)");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_a_trace: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: program PB F Link Trace register (configure trace selection based
-//           on first active link)
-// parameters: i_smp_chip => structure encapsulating SMP chip
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_f_trace(
-    const proc_build_smp_chip& i_smp_chip)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    ecmdDataBufferBase data(64), mask(64);
-    uint8_t f0_out_sel = 0x0;
-    uint8_t f1_out_sel = 0x0;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_f_trace: Start");
-
-    do
-    {
-        // find first configured link, set to trace outbound traffic
-        if (i_smp_chip.chip->enable_f0)
-        {
-            f0_out_sel = 0x1;
-            f1_out_sel = 0x0;
-        }
-        else if (i_smp_chip.chip->enable_f1)
-        {
-            f0_out_sel = 0x0;
-            f1_out_sel = 0x1;
-        }
-
-        // build data buffer (clear previous configuration)
-        // F0 outbound trace select
-        rc_ecmd |= data.insertFromRight(
-            f0_out_sel,
-            PB_F_TRACE_F0_OUT_SEL0_START_BIT,
-            (PB_F_TRACE_F0_OUT_SEL0_END_BIT-
-             PB_F_TRACE_F0_OUT_SEL0_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            f0_out_sel,
-            PB_F_TRACE_F0_OUT_SEL1_START_BIT,
-            (PB_F_TRACE_F0_OUT_SEL1_END_BIT-
-             PB_F_TRACE_F0_OUT_SEL1_START_BIT)+1);
-
-        // F1 outbound trace select
-        rc_ecmd |= data.insertFromRight(
-            f1_out_sel,
-            PB_F_TRACE_F1_OUT_SEL0_START_BIT,
-            (PB_F_TRACE_F1_OUT_SEL0_END_BIT-
-             PB_F_TRACE_F1_OUT_SEL0_START_BIT)+1);
-        rc_ecmd |= data.insertFromRight(
-            f1_out_sel,
-            PB_F_TRACE_F1_OUT_SEL1_START_BIT,
-            (PB_F_TRACE_F1_OUT_SEL1_END_BIT-
-             PB_F_TRACE_F1_OUT_SEL1_START_BIT)+1);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_build_smp_set_f_trace: Error 0x%x setting up F Link Trace register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register
-        rc = fapiPutScom(i_smp_chip.chip->this_chip,
-                         PB_F_TRACE_0x09010812,
-                         data);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_build_smp_set_f_trace: fapiPutScom error (PB_F_TRACE_0x09010812)");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_f_trace: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_set_fbc_nohp_trace(
-    proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_fbc_nohp_trace: Start");
-
-    // process each chip in SMP, program unit non-hotplug registers
-    for (n_iter = i_smp.nodes.begin();
-         (n_iter != i_smp.nodes.end()) && (rc.ok());
-         n_iter++)
-    {
-        for (p_iter = n_iter->second.chips.begin();
-             (p_iter != n_iter->second.chips.end()) && (rc.ok());
-             p_iter++)
-        {
-            fapi::Target target = p_iter->second.chip->this_chip;
-
-            // X link trace setup
-            if (p_iter->second.x_enabled)
-            {
-                rc = proc_build_smp_set_x_trace(p_iter->second);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_x_trace");
-                    break;
-                }
-            }
-
-            // A link trace setup
-            if (p_iter->second.a_enabled)
-            {
-                rc = proc_build_smp_set_a_trace(p_iter->second);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_a_trace");
-                    break;
-                }
-            }
-
-            // F link trace setup
-            if (p_iter->second.pcie_enabled)
-            {
-                rc = proc_build_smp_set_f_trace(p_iter->second);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_f_trace");
-                    break;
-                }
-            }
-	}
-    }
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_fbc_nohp_trace: End");
-    return rc;
-}
-
-
-// NOTE: see comments above function prototype in header
-fapi::ReturnCode proc_build_smp_set_fbc_nohp(
-    proc_build_smp_system& i_smp)
-{
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_build_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_build_smp_chip>::iterator p_iter;
-
-    // mark function entry
-    FAPI_DBG("proc_build_smp_set_fbc_nohp: Start");
-
-    // process each chip in SMP, program unit non-hotplug registers
-    for (n_iter = i_smp.nodes.begin();
-         (n_iter != i_smp.nodes.end()) && (rc.ok());
-         n_iter++)
-    {
-        for (p_iter = n_iter->second.chips.begin();
-             (p_iter != n_iter->second.chips.end()) && (rc.ok());
-             p_iter++)
-        {
-            fapi::Target target = p_iter->second.chip->this_chip;
-
-            // PB Mode register
-            rc = proc_build_smp_set_pb_mode(p_iter->second,
-                                            i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_pb_mode");
-                break;
-            }
-
-            // command scope drop priority registers
-            rc = proc_build_smp_set_pacing_rates(p_iter->second,
-                                                 i_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_build_smp_set_fbc_nohp: Error from proc_build_smp_set_pacing_rates");
-                break;
-            }
-        }
-    }
-
-    // mark function exit
-    FAPI_DBG("proc_build_smp_set_fbc_nohp: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H
deleted file mode 100644
index 11b4c8b66..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H
+++ /dev/null
@@ -1,81 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_build_smp_fbc_nohp.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_build_smp_fbc_nohp.H,v 1.4 2015/02/09 22:37:59 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_build_smp_fbc_nohp.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_build_smp_fbc_nohp.H
-// *! DESCRIPTION : Fabric configuration (non-hotplug) functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BUILD_SMP_FBC_NOHP_H_
-#define _PROC_BUILD_SMP_FBC_NOHP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_build_smp.H>
-#include <p8_scom_addresses.H>
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: program fabric trace configuration registers (non-hotplug)
-// parameters: i_smp => structure encapsulating SMP topology
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_fbc_nohp_trace(
-    proc_build_smp_system& i_smp);
-
-//------------------------------------------------------------------------------
-// function: program fabric configuration registers (non-hotplug)
-// parameters: i_smp => structure encapsulating SMP topology
-// returns: FAPI_RC_SUCCESS if register programming is successful,
-//          RC_PROC_BUILD_SMP_INVALID_GROUP_SIZE_ERR if group size is too
-//              small/large,
-//          RC_PROC_BUILD_SMP_PACING_RATE_TABLE_ERR if pacing rate table lookup
-//              is unsuccessful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_build_smp_set_fbc_nohp(
-    proc_build_smp_system& i_smp);
-
-} // extern "C"
-
-#endif // _PROC_BUILD_SMP_FBC_NOHP_H_
diff --git a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H b/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H
deleted file mode 100644
index ab0ecdf30..000000000
--- a/src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H
+++ /dev/null
@@ -1,90 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_build_smp/proc_fbc_utils.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_fbc_utils.H,v 1.3 2014/01/19 17:34:51 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_fbc_utils.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_fbc_utils.H
-// *! DESCRIPTION : Fabric library functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_FBC_UTILS_H_
-#define _PROC_FBC_UTILS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// address range definitions
-const uint64_t PROC_FBC_UTILS_FBC_MAX_ADDRESS = ((1ULL << 50)-1ULL);
-const uint64_t PROC_FBC_UTILS_CACHELINE_MASK = 0x7FULL;
-const uint64_t PROC_FBC_UTILS_LAST_ADDR_IN_CACHELINE = 0x78ULL;
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// function: read PB Mode & ADU pMisc Mode registers to check state of fabric
-//           init and stop control signals
-// parameters: i_target         => P8 chip target
-//             o_is_initialized => return state of fabric init signal
-//             o_is_running     => return state of fabric pervasive stop control
-// returns: FAPI_RC_SUCCESS if SCOM reads are successful,
-//          else error
-fapi::ReturnCode proc_fbc_utils_get_fbc_state(
-    const fapi::Target& i_target,
-    bool& o_is_initialized,
-    bool& o_is_running);
-
-
-// function: read-modify-write ADU pMisc Mode register to clear fabric stop
-//           signal (override stop caused by checkstop)
-// parameters: i_target         => P8 chip target
-// returns: FAPI_RC_SUCCESS if SCOM sequence is successful,
-//          else error
-fapi::ReturnCode proc_fbc_utils_override_fbc_stop(
-    const fapi::Target& i_target);
-
-
-} // extern "C"
-
-#endif // _PROC_FBC_UTILS_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C b/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
deleted file mode 100644
index f07654b38..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C
+++ /dev/null
@@ -1,857 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/build_winkle_images.C $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file build_winkle_images.C
- *
- *  Support file for IStep: build_winkle_images
- *   Build Winkle Images
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-#include    <sys/misc.h>            //  cpu_thread_count(), P8_MAX_PROCS
-#include    <vfs/vfs.H>             // PORE image
-#include    <sys/mm.h>            // mm_block_map
-#include    <sys/mmio.h>          // THIRTYTWO_GB
-
-#include    <trace/interface.H>
-#include    <initservice/taskargs.H>
-#include    <errl/errlentry.H>
-
-#include    <isteps/hwpisteperror.H>
-#include    <errl/errludtarget.H>
-
-#include    <initservice/isteps_trace.H>
-#include    <initservice/initsvcreasoncodes.H>
-
-//  targeting support
-#include    <targeting/common/commontargeting.H>
-#include    <targeting/common/utilFilter.H>
-#include    <targeting/namedtarget.H>
-
-#include <pnor/pnorif.H>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-
-#include    <devicefw/userif.H>
-#include    <vpd/mvpdenums.H>
-#include    <vpd/vpdreasoncodes.H>
-
-#include    <hwpf/istepreasoncodes.H>
-
-#include    "build_winkle_images.H"
-
-#include    "p8_slw_build/p8_slw_build.H"
-#include    "p8_slw_build/p8_pore_table_gen_api.H"
-#include    "p8_set_pore_bar/p8_set_pore_bar.H"
-#include    "p8_set_pore_bar/p8_pba_bar_config.H"
-#include    "p8_pm.H"                               //  PM_INIT
-#include    "p8_set_pore_bar/p8_poreslw_init.H"
-#include    "p8_slw_build/sbe_xip_image.h"
-#include    <runtime/runtime.H>
-#include    "p8_slw_build/p8_image_help_base.H"
-
-
-namespace   BUILD_WINKLE_IMAGES
-{
-
-using   namespace   ISTEP;
-using   namespace   ISTEP_ERROR;
-using   namespace   ERRORLOG;
-using   namespace   TARGETING;
-using   namespace   fapi;
-using   namespace   DeviceFW;
-
-
-// @@@@@    CUSTOM BLOCK:   @@@@@
-
-/**
- *  @brief Load PORE image and return a pointer to it, or NULL
- *
- *  @param[out] -   address of the PORE image
- *  @param[out] -   size of the PORE image
- *
- *  @return      NULL if success, errorlog if failure
- *
- */
-errlHndl_t  loadPoreImage(  char                    *& o_rporeAddr,
-                            uint32_t                 & o_rporeSize )
-{
-    errlHndl_t l_errl = NULL;
-    PNOR::SectionInfo_t l_info;
-    int64_t rc = 0;
-    o_rporeSize = 0;
-
-    do
-    {
-        // Get WINK PNOR section info from PNOR RP
-        l_errl = PNOR::getSectionInfo( PNOR::WINK, l_info );
-        if( l_errl )
-        {
-            break;
-        }
-
-//         rc = sbe_xip_image_size(reinterpret_cast<void*>(l_info.vaddr),
-//                                 &o_rporeSize);
-//         if((rc !=0) || (o_rporeSize == 0) || o_rporeSize > l_info.size)
-//         {
-//             TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-//                    "ERROR: invalid WINK image rc[%d] slwSize[%d] part size[%d]",
-//                        rc, o_rporeSize, l_info.size);
-//             l_errl =
-//               new ERRORLOG::ErrlEntry( ERRORLOG::ERRL_SEV_UNRECOVERABLE,
-//                                        ISTEP::ISTEP_BUILD_WINKLE_IMAGES,
-//                                        ISTEP::ISTEP_LOAD_SLW_FROM_PNOR_FAILED,
-//                                        (rc<<32)|o_rporeSize,
-//                                        l_info.size );
-//             break;
-//         }
-
-        o_rporeAddr = reinterpret_cast<char*>(l_info.vaddr);
-
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "WINK addr = 0x%p, size=0x%x",
-                   o_rporeAddr,
-                   o_rporeSize  );
-
-    } while ( 0 );
-
-    return  l_errl;
-}
-
-
-
-/**
- * @brief   apply cpu reg information to the SLW image using
- *          p8_pore_gen_cpureg() .
- *
- * @param i_procChipTarg   -   proc target
- * @param io_image      -   pointer to the SLW image
- * @param i_sizeImage   -   size of the SLW image
- *
- * @return errorlog if error, NULL otherwise.
- *
- */
-errlHndl_t  applyPoreGenCpuRegs(   TARGETING::Target *i_procChipTarg,
-                                   void      *io_image,
-                                   uint32_t  i_sizeImage )
-{
-    errlHndl_t  l_errl      =   NULL;
-
-    TARGETING::TargetHandleList l_coreIds;
-    getChildChiplets(   l_coreIds,
-                        i_procChipTarg,
-                        TYPE_CORE,
-                        false );
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "applyPoreGenCpuRegs: Process cores=0x%x, threads=0x%x",
-               l_coreIds.size(),
-               cpu_thread_count() );
-
-    const size_t l_cpu_thread_count = cpu_thread_count();
-    TARGETING::ATTR_CHIP_UNIT_type l_coreId    =   0;
-    size_t      l_threadId  =   0;
-    uint32_t    l_rc        =   0;
-    uint32_t    l_failAddr  =   0;
-
-    uint64_t    l_msrVal    =   cpu_spr_value(CPU_SPR_MSR) ;
-
-    uint64_t    l_lpcrVal   =   cpu_spr_value( CPU_SPR_LPCR);
-    //  Per Greg Still,
-    //  Decrementer exceptions (bit 50) should be disabled when the system
-    // comes out of winkle.
-    // See LPCR def, PECE "reg" in Power ISA AS Version: Power8 June 27, 2012
-    //  and 23.7.3.5 - 6 in Murano Book 4
-    l_lpcrVal   &=  ~(0x0000000000002000) ;
-
-    // Core FIR Action1 Register value from Nick
-    const uint64_t action1_reg = 0xEA5C139705980000;
-
-    TARGETING::Target* sys = NULL;
-    TARGETING::targetService().getTopLevelTarget(sys);
-    assert( sys != NULL );
-    uint64_t en_threads = sys->getAttr<ATTR_ENABLED_THREADS>();
-
-    uint64_t    l_hrmorVal  =   cpu_spr_value(CPU_SPR_HRMOR);
-    for (TargetHandleList::const_iterator
-            l_coreIds_iter = l_coreIds.begin();
-            l_coreIds_iter != l_coreIds.end();
-            ++l_coreIds_iter)
-    {
-        //  make a local copy of the target for ease of use
-        const TARGETING::Target* l_core = *l_coreIds_iter;
-
-        // write the HUID of the core we are writing to
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "target HUID %.8X", TARGETING::get_huid(l_core));
-
-        l_coreId = l_core->getAttr<ATTR_CHIP_UNIT>();
-
-        //  msr and hrmor are common across all threads, only set for thread 0
-        //  on each core
-        l_threadId  =   0;
-        l_rc =  p8_pore_gen_cpureg_fixed( io_image,
-                                          P8_SLW_MODEBUILD_IPL,
-                                          P8_MSR_MSR,
-                                          l_msrVal,
-                                          l_coreId,
-                                          l_threadId);
-        if ( l_rc )
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "ERROR: MSR: core=0x%x,thread=0x%x,l_rc=0x%x",
-                       l_coreId, l_threadId, l_rc );
-            l_failAddr = P8_MSR_MSR;
-            break;
-        }
-
-        l_rc =  p8_pore_gen_cpureg_fixed( io_image,
-                                          P8_SLW_MODEBUILD_IPL,
-                                          P8_SPR_HRMOR,
-                                          l_hrmorVal,
-                                          l_coreId,
-                                          l_threadId);
-        if ( l_rc ){
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "ERROR: HRMOR: core=0x%x,thread=0x%x,l_rc=0x%x",
-                       l_coreId, l_threadId, l_rc );
-            l_failAddr = P8_SPR_HRMOR;
-            break;
-        }
-
-        //  fill in lpcr for each thread
-        for ( l_threadId=0; l_threadId < l_cpu_thread_count; l_threadId++ )
-        {
-            // Skip threads that we shouldn't be starting
-            if( !(en_threads & (0x8000000000000000>>l_threadId)) )
-            {
-                continue;
-            }
-
-            TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "applyPoreGenCpuRegs: core=0x%x,thread=0x%x: ",
-                       l_coreId, l_threadId );
-            TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "applyPoreGenCpuRegs: msrc=0x%x,lpcr=0x%x,hrmor=0x%x",
-                       l_msrVal, l_lpcrVal, l_hrmorVal  );
-
-            l_rc =  p8_pore_gen_cpureg_fixed( io_image,
-                                              P8_SLW_MODEBUILD_IPL,
-                                              P8_SPR_LPCR,
-                                              l_lpcrVal,
-                                              l_coreId,
-                                              l_threadId);
-            if ( l_rc )
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "ERROR: LPCR: core=0x%x,thread=0x%x,l_rc=0x%x",
-                           l_coreId, l_threadId, l_rc );
-                l_failAddr = P8_SPR_LPCR;
-                break;
-            }
-        }   // end for l_threadId
-
-        //  if error writing thread break out of l_coreId loop
-        if ( l_rc )
-        {
-            break;
-        }
-
-        // Need to force core checkstops to escalate to a system checkstop
-        //  by telling the SLW to update the ACTION1 register when it
-        //  comes out of winkle  (see HW286670)
-        l_rc = p8_pore_gen_scom_fixed( io_image,
-                                       P8_SLW_MODEBUILD_IPL,
-                                       EX_CORE_FIR_ACTION1_0x10013107,
-                                       l_coreId,
-                                       action1_reg,
-                                       P8_PORE_SCOM_REPLACE,
-                                       P8_SCOM_SECTION_NC );
-        if( l_rc )
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "ERROR: ACTION1: core=0x%x,l_rc=0x%x",
-                       l_coreId, l_rc );
-            l_failAddr = EX_CORE_FIR_ACTION1_0x10013107;
-            break;
-        }
-
-    }   // end for l_coreIds
-
-//     if ( l_rc ){
-//         TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-//                    "ERROR: p8_pore_gen api fail core=0x%x, thread=0x%x, l_rc=0x%x",
-//                    l_coreId, l_threadId, l_rc );
-//         l_errl = new ERRORLOG::ErrlEntry(ERRORLOG::ERRL_SEV_UNRECOVERABLE,
-//                                 ISTEP::ISTEP_BUILD_WINKLE_IMAGES,
-//                                 ISTEP::ISTEP_BAD_RC,
-//                                 TWO_UINT32_TO_UINT64(l_rc,l_failAddr),
-//                                 TWO_UINT32_TO_UINT64(l_coreId,l_threadId) );
-//         l_errl->collectTrace(FAPI_TRACE_NAME,256);
-//         l_errl->collectTrace(FAPI_IMP_TRACE_NAME,256);
-//         l_errl->collectTrace("ISTEPS_TRACE",256);
-//     }
-
-    return  l_errl;
-}
-
-//
-// Utility function to obtain the highest known address in the system
-//
-uint64_t get_top_mem_addr(void)
-{
-    uint64_t top_addr = 0;
-
-    do
-    {
-        // Get all functional proc chip targets
-        TARGETING::TargetHandleList l_cpuTargetList;
-        getAllChips(l_cpuTargetList, TYPE_PROC);
-
-        for ( size_t proc = 0; proc < l_cpuTargetList.size(); proc++ )
-        {
-            TARGETING::Target * l_pProc = l_cpuTargetList[proc];
-
-            //Not checking success here as fail results in no change to
-            // top_addr
-            uint64_t l_mem_bases[8] = {0,};
-            uint64_t l_mem_sizes[8] = {0,};
-            l_pProc->tryGetAttr<TARGETING::ATTR_PROC_MEM_BASES>(l_mem_bases);
-            l_pProc->tryGetAttr<TARGETING::ATTR_PROC_MEM_SIZES>(l_mem_sizes);
-
-            for (size_t i=0; i< 8; i++)
-            {
-                if(l_mem_sizes[i]) //non zero means that there is memory present
-                {
-                    top_addr = std::max(top_addr,
-                                        l_mem_bases[i] + l_mem_sizes[i]);
-                }
-            }
-        }
-    }while(0);
-
-    return top_addr;
-}
-
-//
-//  Wrapper function to call host_build_winkle
-//
-void*    call_host_build_winkle( void    *io_pArgs )
-{
-    errlHndl_t  l_errl  =   NULL;
-
-    char  *l_pPoreImage   =   NULL;
-    uint32_t    l_poreSize      =   0;
-    void        *l_pRealMemBase = NULL;
-    void* l_pVirtMemBase        = NULL;
-
-    ISTEP_ERROR::IStepError     l_StepError;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_host_build_winkle entry" );
-
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-
-    // allocate some working buffers
-    void* l_rs4_tmp = malloc(FIXED_RING_BUF_SIZE);
-    void* l_wf_tmp = malloc(FIXED_RING_BUF_SIZE);
-
-
-    do  {
-        // Get the node-offset for our instance by looking at the HRMOR
-        uint64_t l_memBase = cpu_spr_value(CPU_SPR_HRMOR);
-        // mask off the secureboot offset
-        l_memBase = 0xFFFFF00000000000 & l_memBase;
-
-        // Now offset up to our hardcoded region
-        l_memBase += VMM_HOMER_REGION_START_ADDR;
-
-        //  Get a chunk of real memory big enough to store all the possible
-        //  SLW images.
-
-        assert(VMM_HOMER_REGION_SIZE <= THIRTYTWO_GB,
-               "host_build_winkle: Unsupported HOMER Region size");
-
-        //If running Sapphire need to place this at the top of memory instead
-        if(is_sapphire_load())
-        {
-            l_memBase = get_top_mem_addr();
-            assert (l_memBase != 0,
-                    "host_build_winkle: Top of memory was 0!");
-            l_memBase -= VMM_ALL_HOMER_OCC_MEMORY_SIZE;
-        }
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "HOMER base = %x", l_memBase);
-
-        l_pRealMemBase = reinterpret_cast<void * const>(l_memBase );
-
-        l_pVirtMemBase =
-              mm_block_map(l_pRealMemBase, VMM_HOMER_REGION_SIZE);
-
-        TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "Got virtual mem  buffer for %d cpus = 0x%p",
-                   P8_MAX_PROCS,
-                   l_pVirtMemBase  );
-
-        //  Continue, build SLW images
-
-
-        //Load the reference image from PNOR
-        l_errl  =   loadPoreImage(  l_pPoreImage,
-                                    l_poreSize );
-        if ( l_errl )
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "host_build_winkle ERROR : errorlog PLID=0x%x",
-                      l_errl->plid() );
-
-            // drop out of do block with errorlog.
-            break;
-        }
-
-
-        //  Loop through all functional Procs and generate images for them.
-        TARGETING::TargetHandleList l_procChips;
-        getAllChips( l_procChips,
-                     TARGETING::TYPE_PROC   );
-
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "Found %d procs in system",
-                   l_procChips.size()   );
-
-        for ( TargetHandleList::const_iterator
-              l_iter = l_procChips.begin();
-              l_iter != l_procChips.end();
-              ++l_iter )
-        {
-            TARGETING::Target * l_procChip  =   (*l_iter) ;
-
-            do  {
-
-                // write the HUID of the core we are writing to
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                        "Build SLW image for proc "
-                        "target HUID %.8X", TARGETING::get_huid(l_procChip));
-
-
-                //  calculate size and location of the SLW output buffer
-                uint32_t    l_procNum =
-                  l_procChip->getAttr<TARGETING::ATTR_POSITION>();
-                uint64_t    l_procOffsetAddr =
-                  ( l_procNum *VMM_HOMER_INSTANCE_SIZE ) + HOMER_SLW_IMG_OFFSET;
-
-                uint64_t    l_procRealMemAddr  =
-                  reinterpret_cast<uint64_t>(l_pRealMemBase)
-                  + l_procOffsetAddr;
-
-                void *l_pImageOut =
-                  reinterpret_cast<void * const>
-                  (reinterpret_cast<uint64_t>(l_pVirtMemBase)
-                   + l_procOffsetAddr) ;
-
-                uint32_t    l_sizeImageOut  =
-                  (HOMER_MAX_SLW_IMG_SIZE_IN_MB*MEGABYTE);
-
-                //  set default values, p8_slw_build will provide actual size
-                l_procChip->setAttr<TARGETING::ATTR_SLW_IMAGE_ADDR>
-                                                        ( l_procRealMemAddr );
-                l_procChip->setAttr<TARGETING::ATTR_SLW_IMAGE_SIZE>
-                                                        ( l_sizeImageOut ) ;
-
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "Real mem  buffer for cpu 0x%08x = %p, virtAddr=%p",
-                           l_procNum,
-                           l_procRealMemAddr,
-                           l_pImageOut);
-
-                // cast OUR type of target to a FAPI type of target.
-                const fapi::Target l_fapi_cpu_target( TARGET_TYPE_PROC_CHIP,
-                                                (const_cast<TARGETING::Target*>
-                                                     (l_procChip)) );
-
-                //  call the HWP with each fapi::Target
-                FAPI_INVOKE_HWP( l_errl,
-                                 p8_slw_build_fixed,
-                                 l_fapi_cpu_target, //Proc chip target.
-                                 reinterpret_cast<void*>(l_pPoreImage),
-                                 l_pImageOut,
-                                 l_sizeImageOut,
-                                 P8_SLW_MODEBUILD_IPL, //i_modeBuild
-                                 l_rs4_tmp,//RS4
-                                 FIXED_RING_BUF_SIZE,
-                                 l_wf_tmp,//WF
-                                 FIXED_RING_BUF_SIZE );
-                if ( l_errl )
-                {
-                    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                              "host_build_winkle ERROR : errorlog PLID=0x%x",
-                              l_errl->plid() );
-
-                    //  drop out of block with errorlog.
-                    break;
-                }
-                else
-                {
-                    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "host_build_winkle SUCCESS : image size = 0x%x ",
-                               l_sizeImageOut );
-                }
-
-                //  set the actual size of the image now.
-                l_procChip->setAttr<TARGETING::ATTR_SLW_IMAGE_SIZE>
-                ( l_sizeImageOut );
-
-                //  apply the cpu reg information to the image.
-                l_errl =   applyPoreGenCpuRegs( l_procChip,
-                                                l_pImageOut,
-                                                l_sizeImageOut );
-                if ( l_errl )
-                {
-                    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                              "applyPoreGenCpuRegs ERROR : errorlog PLID=0x%x",
-                              l_errl->plid() );
-
-                    //  drop out of block with errorlog.
-                    break;
-                }
-                else
-                {
-                    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "applyPoreGenCpuRegs SUCCESS " );
-                }
-
-            }   while (0) ;
-
-            // broke out due to an error, store all the details away, store
-            //  the errlog in IStepError, and continue to next proc
-            if (l_errl)
-            {
-                // capture the target data in the elog
-                ErrlUserDetailsTarget(l_procChip).addToLog( l_errl );
-
-                // Create IStep error log and cross ref error that occurred
-                l_StepError.addErrorDetails( l_errl );
-
-                // Commit Error
-                errlCommit( l_errl, HWPF_COMP_ID );
-            }
-
-        } ;  // endfor
-
-    }  while (0);
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
-
-    if (l_errl)
-    {
-        // Create IStep error log and cross ref error that occurred
-        l_StepError.addErrorDetails( l_errl );
-
-        // Commit Error
-        errlCommit( l_errl, HWPF_COMP_ID );
-    }
-
-    // delete working buffers
-    if( l_rs4_tmp ) { free(l_rs4_tmp); }
-    if( l_wf_tmp ) { free(l_wf_tmp); }
-
-    if(l_pVirtMemBase)
-    {
-        int rc = 0;
-        rc =  mm_block_unmap(l_pVirtMemBase);
-//         if (rc != 0)
-//         {
-//             l_errl =
-//               new ERRORLOG::ErrlEntry(
-//                                       ERRORLOG::ERRL_SEV_UNRECOVERABLE,
-//                                       ISTEP::ISTEP_BUILD_WINKLE_IMAGES,
-//                                       ISTEP::ISTEP_MM_UNMAP_ERR,
-//                                       rc,
-//                                       reinterpret_cast<uint64_t>
-//                                       (l_pVirtMemBase));
-//
-//             // Create IStep error log and cross reference error that occurred
-//             l_StepError.addErrorDetails( l_errl );
-//
-//             // Commit error
-//             errlCommit( l_errl, ISTEP_COMP_ID );
-//         }
-    }
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_host_build_winkle exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_StepError.getErrorHandle();
-}
-
-
-
-//
-//  Wrapper function to call p8_set_pore_bar
-//
-void*    call_proc_set_pore_bar( void    *io_pArgs )
-{
-    errlHndl_t  l_errl      =   NULL;
-
-    ISTEP_ERROR::IStepError     l_stepError;
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_proc_set_pore_bar entry" );
-
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-
-    TARGETING::TargetHandleList l_procChips;
-    getAllChips( l_procChips,
-                 TARGETING::TYPE_PROC   );
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "Found %d procs in system",
-               l_procChips.size()   );
-
-    for ( TargetHandleList::const_iterator
-          l_iter = l_procChips.begin();
-          l_iter != l_procChips.end();
-          ++l_iter )
-    {
-        const TARGETING::Target * l_procChip  =   (*l_iter) ;
-
-        // write the HUID of the core we are writing to
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "Set pore bar for "
-                "target HUID %.8X", TARGETING::get_huid(l_procChip));
-
-        // cast OUR type of target to a FAPI type of target.
-        const fapi::Target l_fapi_cpu_target( TARGET_TYPE_PROC_CHIP,
-                            (const_cast<TARGETING::Target*>(l_procChip)) );
-
-        //  fetch image location and size, written by host_build_winkle above
-
-        //  Note that the "i_mem_bar" input to p8_set_pore_bar is the physical
-        //  address of the PORE image, this is the image that will get executed
-        //  at winkle.
-        uint64_t l_imageAddr =
-        l_procChip->getAttr<TARGETING::ATTR_SLW_IMAGE_ADDR>();
-
-
-        //  Size (in MB) of the region where image is located.
-        //  This is rounded up to the nearest power of 2 by the HWP.
-        //  Easiest way to insure this works right is to set it to a power
-        //  of 2;  see vmmconst.H
-        uint64_t l_mem_size =  HOMER_MAX_SLW_IMG_SIZE_IN_MB ;
-
-        //  defined in p8_set_pore_bar.H
-        uint32_t        l_mem_type  =   SLW_L3 ;
-
-
-        //  call the HWP with each fapi::Target
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                   "p8_set_pore_bar, mem=0x%lx, sz=0x%lx, msk=0x%lx, type=0x%x",
-                   l_imageAddr,
-                   (l_procChip->getAttr<ATTR_SLW_IMAGE_SIZE>()),
-                   l_mem_size,
-                   l_mem_type );
-
-
-        // Map image.
-        void * const l_pImage = reinterpret_cast<void* const>(
-                        mm_block_map(reinterpret_cast<void*>(l_imageAddr),
-                                     HOMER_MAX_SLW_IMG_SIZE_IN_MB*MEGABYTE));
-
-        FAPI_INVOKE_HWP( l_errl,
-                         p8_set_pore_bar,
-                         l_fapi_cpu_target,
-                         l_pImage,
-                         l_imageAddr,
-                         l_mem_size,
-                         l_mem_type
-                       );
-
-        // Unmap
-        int rc = mm_block_unmap(l_pImage);
-        if ((rc != 0) && (NULL == l_errl)) // The bad rc is lower priority
-                                           // than any other error, so just
-                                           // ignore it if something else
-                                           // happened.
-        {
-            l_errl =
-              new ERRORLOG::ErrlEntry(
-                                      ERRORLOG::ERRL_SEV_UNRECOVERABLE,
-                                      ISTEP::ISTEP_PROC_SET_PORE_BAR,
-                                      ISTEP::ISTEP_MM_UNMAP_ERR,
-                                      rc,
-                                      reinterpret_cast<uint64_t>
-                                      (l_pImage));
-        }
-
-        if (l_errl)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR : p8_set_pore_bar, PLID=0x%x",
-                      l_errl->plid()  );
-        }
-        else
-        {
-            //No error on previous call, make sure to
-            //init PBA BAR 0 to 0s.  This is required on MPIPLs
-            //so sapphire can determine when OCC is active.  FSPless
-            //it will be active before hostboot hands over control
-            //FSP mode it will be loaded in sapphire
-
-            FAPI_INVOKE_HWP( l_errl,
-                             p8_pba_bar_config,
-                             l_fapi_cpu_target,
-                             0,                 //PBA BAR 0
-                             0,                 //Addr 0
-                             0,                 //Size 0
-                             0);                //Cmd 0
-
-            if (l_errl)
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                          "ERROR : p8_pba_bar_config, PLID=0x%x",
-                          l_errl->plid()  );
-            }
-        }
-
-
-        if ( l_errl )
-        {
-            // capture the target data in the elog
-            ErrlUserDetailsTarget(l_procChip).addToLog( l_errl );
-
-            // Create IStep error log and cross reference error that occurred
-            l_stepError.addErrorDetails( l_errl );
-
-            // Commit error
-            errlCommit( l_errl, HWPF_COMP_ID );
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "SUCCESS : p8_set_pore_bar" );
-        }
-
-    }   // end for
-
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
-
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_proc_set_pore_bar exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_stepError.getErrorHandle();
-}
-
-//
-//  Wrapper function to call p8_poreslw_init
-//
-void*    call_p8_poreslw_init( void    *io_pArgs )
-{
-    errlHndl_t  l_errl      =   NULL;
-
-    ISTEP_ERROR::IStepError     l_stepError;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_p8_poreslw_init entry" );
-
-    // @@@@@    CUSTOM BLOCK:   @@@@@
-
-
-    TARGETING::TargetHandleList l_procChips;
-    getAllChips( l_procChips,
-                 TARGETING::TYPE_PROC   );
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "Found %d procs in system",
-               l_procChips.size()   );
-
-    for ( TargetHandleList::const_iterator
-          l_iter = l_procChips.begin();
-          l_iter != l_procChips.end();
-          ++l_iter )
-    {
-        const TARGETING::Target * l_procChip  =   (*l_iter) ;
-
-        // write the HUID of the core we are writing to
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "target HUID %.8X", TARGETING::get_huid(l_procChip));
-
-        // cast OUR type of target to a FAPI type of target.
-        const fapi::Target l_fapi_cpu_target( TARGET_TYPE_PROC_CHIP,
-                           (const_cast<TARGETING::Target*>(l_procChip)) );
-
-        //
-        //  Configure the SLW PORE and related functions to enable idle
-        //  operations
-        //
-        FAPI_INVOKE_HWP( l_errl,
-                         p8_poreslw_init,
-                         l_fapi_cpu_target,
-                         PM_INIT  );
-        if ( l_errl )
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR : p8_poreslw_init, PLID=0x%x",
-                      l_errl->plid()  );
-
-            // capture the target data in the elog
-            ErrlUserDetailsTarget(l_procChip).addToLog( l_errl );
-
-            // Create IStep error log and cross reference error that occurred
-            l_stepError.addErrorDetails( l_errl );
-
-            // Commit error
-            errlCommit( l_errl, HWPF_COMP_ID );
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "SUCCESS : p8_poreslw_init " );
-        }
-
-    }   // end for
-
-    // @@@@@    END CUSTOM BLOCK:   @@@@@
-
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_p8_poreslw_init exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_stepError.getErrorHandle();
-}
-
-
-};   // end namespace
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.C b/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.C
deleted file mode 100644
index 9a5536343..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.C
+++ /dev/null
@@ -1,165 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_block_wakeup_intr.C,v 1.1 2013/08/27 16:13:05 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_block_wakeup_intr.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-/**
-  * OWNER NAME:   Greg Still         Email: stillgs@us.ibm.com
-  * BACKUP NAME : Michael Olsen      Email: cmolsen@us.ibm.com
-  *
-  * @file p8_block_wakeup_intr.C
-  * @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PCBS-PM associated 
-  *         with an EX chiplet
-  *
-  * @verbatim
-  * High-level procedure flow:
-  *
-  *  With set/reset enum parameter, either set or clear PMGP0(53)
-  *
-  *  Procedure Prereq:
-  *     - System clocks are running
-  * @endverbatim
-  */
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-
-#include "p8_block_wakeup_intr.H"
-
-extern "C" {
-
-using namespace fapi;
-
-
-/**
- * p8_block_wakeup_intr
- *
- * @param[in] i_ex_target EX target
- * @param[in] i_operation  SET, RESET
- *
- * @retval ECMD_SUCCESS
- * @retval ERROR only those from called functions or MACROs
- */
-fapi::ReturnCode
-p8_block_wakeup_intr(  const fapi::Target& i_ex_target,
-                        PROC_BLKWKUP_OPS i_operation )
-
-{
-    fapi::ReturnCode    rc;
-    uint32_t            e_rc = 0;
-    uint64_t            address;
-    uint64_t            offset;
-    ecmdDataBufferBase  data(64);
-
-    fapi::Target        l_parentTarget;
-    uint8_t             attr_chip_unit_pos = 0;
-    
-    // PMGP0 Bit definitions
-    const uint32_t      BLOCK_REG_WKUP_SOURCES = 53;
-
-    // This must stay in sync with enum defined the .H file
-    const char* PROC_BLKWKUP_OPS_NAMES[] =
-    {
-        "SET",
-        "RESET"
-    };
-
-    do
-    {
-
-        FAPI_INF("Executing p8_block_wakeup_intr with operation %s to EX %s...",
-                    PROC_BLKWKUP_OPS_NAMES[i_operation],
-                    i_ex_target.toEcmdString());
-      
-
-        // Get the parent chip to target the registers
-        rc = fapiGetParentChip(i_ex_target, l_parentTarget);
-        if (rc)
-        {
-            FAPI_ERR("fapiGetParentChip with rc = 0x%x", (uint32_t)rc);
-            break;
-        }
-
-        // Get the core number
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_ex_target, attr_chip_unit_pos);
-        if (rc)
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc);
-            break;
-        }
-
-        FAPI_DBG("Core number = %d", attr_chip_unit_pos);
-        offset = attr_chip_unit_pos * 0x01000000;
-
-        if (i_operation == BLKWKUP_SET)
-        {
-            FAPI_INF("Setting Block Interrupt Sources...");
-            
-            address =  EX_PMGP0_OR_0x100F0102 + offset;                                        
-            
-            e_rc |= data.flushTo0();
-            e_rc |= data.setBit(BLOCK_REG_WKUP_SOURCES);
-            E_RC_CHECK(e_rc, rc);
-
-            PUTSCOM(rc, l_parentTarget, address, data);
-
-            
-        }
-        else if (i_operation == BLKWKUP_RESET)
-        {
-
-            FAPI_INF("Clearing Block Interrupt Sources...");
-            
-            address =  EX_PMGP0_AND_0x100F0101 + offset;                                        
-            
-            e_rc |= data.flushTo1();
-            e_rc |= data.clearBit(BLOCK_REG_WKUP_SOURCES);
-            E_RC_CHECK(e_rc, rc);
-
-            PUTSCOM(rc, l_parentTarget, address, data);
-
-        }
-        else
-        {
-            FAPI_ERR("Invalid parameter specified. Operation %x", i_operation );
-            const fapi::Target & EX_TARGET = i_ex_target;
-            PROC_BLKWKUP_OPS & OPERATION = i_operation ;
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_BLKWKUP_CODE_BAD_OP);
-            break;
-        }
-        
-    } while (0);
-    
-    return rc;   
-}
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.H b/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.H
deleted file mode 100644
index 5f805216f..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.H
+++ /dev/null
@@ -1,90 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr/p8_block_wakeup_intr.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_block_wakeup_intr.H,v 1.1 2013/08/27 16:13:07 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_block_wakeup_intr.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-/**
-  * OWNER NAME:   Greg Still         Email: stillgs@us.ibm.com
-  * BACKUP NAME : Michael Olsen      Email: cmolsen@us.ibm.com
-  *
-  * @file p8_block_wakeup_intr.C
-  * @brief Set/reset the BLOCK_REG_WKUP_SOURCES bit in the PCBS-PM associated 
-  *         with an EX chiplet
- */  
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_BLKWKUP_H_
-#define _PROC_BLKWKUP_H_
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-#define NUM_BLKWKUP_OPS 2
-enum PROC_BLKWKUP_OPS 
-{
-    BLKWKUP_SET,
-    BLKWKUP_RESET
-};
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include "p8_pm.H"
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_block_wakeup_intr_FP_t) (
-                            const fapi::Target&, 
-                            PROC_BLKWKUP_OPS);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-
-/**
- * p8_block_wakeup_intr
- *
- * @param[in] i_target EX target
- * @param[in] i_operation  SET, RESET
- *
- * @retval ECMD_SUCCESS
- * @retval ERROR only those from called functions or MACROs
- */
-fapi::ReturnCode 
-p8_block_wakeup_intr(  const fapi::Target& i_target, 
-                        PROC_BLKWKUP_OPS i_operation);
-
-} // extern "C"
-
-#endif // _PROC_BLKWKUP_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_homer_map.h b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_homer_map.h
deleted file mode 100644
index bae728ee3..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_homer_map.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_homer_map.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_homer_map.h,v 1.2 2014/07/26 13:58:54 jmcgill Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! OWNER NAME  : Frank Campisano Email: campisan@us.ibm.com
-
-/**
- *  @file p8_homer_map.h
- *
- *  @brief Defines the memory layout for the 4MB HOMER space for OCC, SLW, CPM, and other 
- *
- * Start	End     	Size	Description
- *============= =============== ======= ===================================================
- * 0x00000000	0x000FFFFF	1 MB	OCC Image (Bootloader, OCC Image, OCC Applets)
- * 0x00100000	0x0011FFFF	128 kB	OCC Host Data Area (nest freq, config) (per chip)
- * 0x00120000	0x001EFFFF	832 kB	Unused Pad for OCC
- * 0x001F0000	0x001F7FFF	32 kB 	PowerProxy Trace Records
- * 0x001F8000	0x001FFFFF	32 kB 	Sapphire Data
- * 0x00200000	0x002FFFFF	1 MB	SLW Image
- * 0x00300000	0x0031FFFF	128 kB	SLW Spill over
- * 0x00320000	0x0039FFFF	512 kB	SLW 24x7 Counters Data Area (per chip)
- * 0x003A0000	0x003AFFFF	64 kB	SLW<->PHYP I2C Offload Comm Buffers (per chip)
- * 0x003B0000	0x003BFFFF	64 kB	CPM Calibration Data Buffer Block 
- * 0x003C0000	0x003C0FFF	4 kB	CPM Control Vector Block
- * 0x003C1000	0x003C1FFF	4 kB	PTS debug/FFDC assist data
- * 0x003C2000	0x003FFFFF	248 kB	Unused Pad for PBABAR
- */
-
-#ifndef _P8_HOMER_MAP_H_
-#define _P8_HOMER_MAP_H_
-
-// Offset Addresses from HOMER BAR address (per chip)
-
-CONST_UINT64_T( HOMER_OCC_IMAGE_OFFSET_ADDR                , ULL(0x00000000) );
-CONST_UINT64_T( HOMER_OCC_HOST_DATA_OFFSET_ADDR            , ULL(0x00100000) );
-CONST_UINT64_T( HOMER_OCC_PAD_OFFSET_ADDR                  , ULL(0x00120000) );
-CONST_UINT64_T( HOMER_POWERPROXY_TRACE_OFFSET_ADDR         , ULL(0x001F0000) );
-CONST_UINT64_T( HOMER_SAPPHIRE_DATA_OFFSET_ADDR            , ULL(0x001F8000) );
-CONST_UINT64_T( HOMER_SLW_IMAGE_OFFSET_ADDR                , ULL(0x00200000) );
-CONST_UINT64_T( HOMER_SLW_SPILL_BUFFER_OFFSET_ADDR         , ULL(0x00300000) );
-CONST_UINT64_T( HOMER_SLW_24X7_COUNTER_OFFSET_ADDR         , ULL(0x00320000) );
-CONST_UINT64_T( HOMER_SLW_PHYP_I2C_OFFOAD_OFFSET_ADDR      , ULL(0x003A0000) );
-CONST_UINT64_T( HOMER_CPM_CAL_DATA_VECTOR_OFFSET_ADDR      , ULL(0x003B0000) );
-CONST_UINT64_T( HOMER_CPM_CAL_CTRL_VECTOR_OFFSET_ADDR      , ULL(0x003C0000) );
-CONST_UINT64_T( HOMER_CPM_CAL_GOLD_CTRL_VECTOR_OFFSET_ADDR , ULL(0x003C0080) );
-CONST_UINT64_T( HOMER_PTS_DATA                             , ULL(0x003C1000) );
-CONST_UINT64_T( HOMER_PAD_OFFSET_ADDR                      , ULL(0x003C2000) );
-
-// Buffer sizes for HOMER sections
-
-CONST_UINT64_T( HOMER_OCC_IMAGE_BUFFER_SIZE                , ULL(0x00100000) );
-CONST_UINT64_T( HOMER_OCC_HOST_DATA_BUFFER_SIZE            , ULL(0x00020000) );
-CONST_UINT64_T( HOMER_OCC_PAD_BUFFER_SIZE                  , ULL(0x000D0000) );
-CONST_UINT64_T( HOMER_POWERPROXY_TRACE_RECORD_BUFFER_SIZE  , ULL(0x00008000) );
-CONST_UINT64_T( HOMER_SAPPHIRE_DATA_BUFFER_SIZE            , ULL(0x00008000) );
-CONST_UINT64_T( HOMER_SLW_IMAGE_BUFFER_SIZE                , ULL(0x00100000) );
-CONST_UINT64_T( HOMER_SLW_SPILL_BUFFER_BUFFER_SIZE         , ULL(0x00020000) );
-CONST_UINT64_T( HOMER_SLW_24X7_COUNTER_BUFFER_SIZE         , ULL(0x00080000) );
-CONST_UINT64_T( HOMER_SLW_PHYP_I2C_OFFOAD_BUFFER_SIZE      , ULL(0x00010000) );
-CONST_UINT64_T( HOMER_CPM_CAL_DATA_BUFFER_BUFFER_SIZE      , ULL(0x00010000) );
-CONST_UINT64_T( HOMER_CPM_CAL_CTRL_VECTOR_BUFFER_SIZE      , ULL(0x00001000) );
-CONST_UINT64_T( HOMER_CPM_CAL_GOLD_CTRL_VECTOR_BUFFER_SIZE , ULL(0x00000080) );
-CONST_UINT64_T( HOMER_PTS_DATA_SIZE                        , ULL(0x00001000) );
-CONST_UINT64_T( HOMER_PAD_BUFFER_SIZE                      , ULL(0x0003E000) );
-
-#endif  // _P8_HOMER_MAP_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C
deleted file mode 100644
index 04943d3eb..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C
+++ /dev/null
@@ -1,317 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pba_bar_config.C,v 1.6 2015/01/23 14:57:37 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pba_bar_config.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
-// *!
-// *!
-// *! To build  -  buildfapiprcd -e ../../xml/error_info/p8_pba_bar_config_errors.xml p8_pba_bar_config.C
-// *!
-/// \file p8_pba_bar_config.C
-/// \brief Initialize PAB and PAB_MSK of PBA
-///
-/// \verbatim
-///     The purpose of this procedure is to set the PBA BAR, PBA BAR Mask and
-///     PBA scope value / registers
-///
-///     Following proposals here: pass values for one set of pbabar, pass reference to structure for one set of pbabar, pass struct of struct containing
-///     all setup values
-///
-///     High-level procedure flow:
-///       parameter checking
-///       set PBA_BAR
-///      set PBA_BARMSK
-///
-///    Procedure Prereq:
-///      o System clocks are running
-///
-///  CQ Class:  power_management
-/// \endverbatim
-///
-///   list of changes
-///     2011/11/2   all variables / passing calling parameters are uint64_t,    
-///                 cmd_scope is enum, MASK is not bitmask parameter but size    
-///                 structure for init contain uint64_t only.                    
-///
-///     2012/10/0   made isPowerofTwo() and PowerOfTwoRoundedup() inline
-///                 included pba_firmware_registers.h vs pba_firmware_register.H  
-///
-///     2012/10/18  Added support for BAR reset (BAR=0, Size=0) as being legal
-///                 Added 1M alignment checking
-///
-//------------------------------------------------------------------------------
-
-
-// -----------------------------------------------------------------------------
-// Includes
-// -----------------------------------------------------------------------------
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-#include "p8_pba_init.H"
-#include "p8_pba_bar_config.H"
-//#include "pba_firmware_register.H"
-#include "pba_firmware_registers.h"
-#include "p8_pm.H"
-
-
-extern "C" {
-
-
-using namespace fapi;
-
-// -----------------------------------------------------------------------------
-// Constant definitions
-// -----------------------------------------------------------------------------
-
-// for range checking            0x0123456701234567
-#define BAR_ADDR_RANGECHECK_     0x0003FFFFFFF00000ull
-#define BAR_ADDR_RANGECHECK_HIGH 0xFFFC000000000000ull
-#define BAR_ADDR_RANGECHECK_LOW  0x00000000000FFFFFull
-
-// -----------------------------------------------------------------------------
-// Global variables
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-// Prototypes
-// -----------------------------------------------------------------------------
-
-// -----------------------------------------------------------------------------
-// Function definitions
-// -----------------------------------------------------------------------------
-
-inline bool isPowerOfTwo (uint64_t value);
-inline uint64_t PowerOf2Roundedup (uint64_t value);
-
-
-/// --------------------------------------------- p8_pba_bar_config ------------
-/// Initialize a specific set of PBA_BAR (=cmd_scope and address),
-///  PBA_BARMSK (mask/size)
-///
-///  @param i_target the target
-///  @param i_index specifies which set of BAR/BARMSK registers to set. [0..3]
-///  @param i_pba_bar_addr PBA base address - 1MB grandularity
-///  @param i_pba_bar_size PBA region size in MB;  if not a power of two value,
-///          the value will be rounded up to the next power of 2 for setting the
-///          hardware mask
-///  @param i_pba_cmd_scope command scope according to pba spec
-fapi::ReturnCode
-p8_pba_bar_config (const Target&  i_target,
-		             uint32_t       i_index,
-		             uint64_t       i_pba_bar_addr,
-		             uint64_t       i_pba_bar_size,
-		             uint64_t       i_pba_cmd_scope
-                     )
-{
-
-
-    ecmdDataBufferBase  data(64);
-    fapi::ReturnCode    l_rc;
-    uint32_t            l_ecmdRc = 0;
-
-    pba_barn_t          bar;
-    pba_barmskn_t       barmask;
-
-    uint64_t            work_size;
-
-    FAPI_DBG("Called with index %x, address 0x%08llX, size 0x%04llX scope 0x%04llX",
-                       i_index, i_pba_bar_addr, i_pba_bar_size, i_pba_cmd_scope);
-
-    // check if pba_bar scope in range
-    if ( i_pba_cmd_scope > PBA_CMD_SCOPE_FOREIGN1 )
-    {
-        FAPI_ERR("ERROR: PB Command Scope out of Range: 0x%04llX > 0x%04X", i_pba_cmd_scope, PBA_CMD_SCOPE_FOREIGN1 );
-        const uint64_t exp_PBA_CMD_SCOPE_FOREIGN1 = PBA_CMD_SCOPE_FOREIGN1;
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SCOPE_OUT_OF_RANGE);
-        return l_rc;
-    }
-
-    // Check if pba_addr amd pba_size are within range,
-    // High order bits checked to ensure a valid real address
-    if ( (BAR_ADDR_RANGECHECK_HIGH & i_pba_bar_addr) != 0x0ull )
-    {
-        FAPI_ERR("ERROR: Address out of Range : i_pba_bar_addr=0x%08llX", i_pba_bar_addr);
-        const uint64_t exp_BAR_ADDR_RANGECHECK_HIGH = BAR_ADDR_RANGECHECK_HIGH;
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_OUT_OF_RANGE);
-        return l_rc;
-    }
-
-    // Low order bits checked for alignment
-    if ( (BAR_ADDR_RANGECHECK_LOW & i_pba_bar_addr) != 0x0ull )
-    {
-        FAPI_ERR("ERROR: Address must be on a 1MB boundary : i_pba_bar_addr=0x%08llX",i_pba_bar_addr);
-        const uint64_t exp_BAR_ADDR_RANGECHECK_LOW = BAR_ADDR_RANGECHECK_LOW;
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_ADDR_ALIGNMENT_ERROR);
-        return l_rc;
-    }
-
-    // Check if the BAR size is 0 but the BAR addr is not zero.  If so, return error.
-    // The combination of both the BAR size and addr being zero is legal.
-    if ( (i_pba_bar_size == 0) && (i_pba_bar_addr != 0) )
-    {
-        FAPI_ERR("ERROR: Bar size must be >=1MB for PBABAR%d but i_pba_bar_size=0x%08llx",
-                    i_index, i_pba_bar_size);
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_PBA_BAR_SIZE_INVALID);
-        return l_rc;
-    }
-
-    // Check that the image address passed is within the memory region that
-    // is also passed.
-    //
-    // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
-    // enabled to be passed from the OCI addresses.  Inverting this mask
-    // indicates which address bits are going to come from the PBA BAR value.
-    // The image address (the starting address) must match these post mask bits
-    // to be resident in the range.
-    //
-    // Starting bit number: 64 bit Big Endian
-    //                                          12223344
-    //                                          60482604
-    // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
-
-    // Set bits 14:22 as these are unconditional address bits
-    //region_inverted_mask = region_inverted_mask | BAR_ADDR_UNMASKED;
-    //computed_image_address = region_inverted_mask && image_address;
-    // Need to AND the address
-    //if (computed_image_address != i_mem_bar )
-    //{
-    //    FAPI_ERR("SLW image address check failure. ");
-    //    FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR);
-    //    return rc;
-    //}
-
-
-
-    // put the parameters into the correct fields
-    bar.value=0;
-    bar.fields.cmd_scope = i_pba_cmd_scope;
-    bar.fields.addr = i_pba_bar_addr >> 20;
-
-    FAPI_DBG("\tbar.fields addr  0x%16llX, scope  0x%llX",
-                        bar.fields.addr, bar.fields.cmd_scope);
-    FAPI_DBG("\tbar.value        0x%16llX", bar.value);
-
-    // Write the BAR
-    l_ecmdRc |= data.setDoubleWord(0, bar.value);
-    if (l_ecmdRc)
-    {
-       FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-       l_rc.setEcmdError(l_ecmdRc);
-       return l_rc;
-    }
-
-    FAPI_DBG("\tPBA_BAR%x:        0x%16llX", i_index,  data.getDoubleWord(0));
-    l_rc = fapiPutScom(i_target, PBA_BARs[i_index], data);
-    if(l_rc)
-    {
-        FAPI_ERR("PBA_BAR Putscom failed");
-        return l_rc;
-    }
-
-    // Compute and write the mask based on passed region size.
-
-    // If the size is already a power of 2, then set the mask to that value - 1.
-    // If the size is not a power of 2, then set the maskto  the rounded up power of 2
-    // value - 1.
-    // If the size is zero, then treat as if equal to 1 and then do the round up check.
-
-    if (i_pba_bar_size!=0)
-    {
-        work_size = PowerOf2Roundedup(i_pba_bar_size);
-        FAPI_INF("\ti_pba_bar_size: 0x%llX.  Final work_size: 0x%llX", 
-                    i_pba_bar_size, work_size);
-    }
-    else
-    { // If bar_size==0, treat as if ==1. Otherwize, range will max out to 2TB.
-        work_size = PowerOf2Roundedup(1ull);
-        FAPI_INF("\ti_pba_bar_size: 0x%llX but treated as if bar_size=1. Final work_size: 0x%llX", 
-                    i_pba_bar_size, work_size);
-    }
-
-    barmask.value=0;
-    barmask.fields.mask = work_size-1;
-
-    FAPI_DBG("\tbar.fields mask  0x%16llX", barmask.fields.mask);
-    FAPI_DBG("\tbar.value        0x%16llX", barmask.value);
-
-    // Write the MASK
-    l_ecmdRc |= data.setDoubleWord(0, barmask.value);
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-    FAPI_DBG("  PBA_BARMSK%x:     0x%16llX", i_index,  data.getDoubleWord(0));
-    l_rc = fapiPutScom(i_target, PBA_BARMSKs[i_index], data);
-    if(l_rc)
-    {
-        FAPI_ERR("PBA_MASK Putscom failed");
-        return l_rc;
-    }
-
-    return l_rc;
-}
-
-///-----------------------------------------------------------------------------
-/// Determine if a number is a power of two or not
-///-----------------------------------------------------------------------------
-inline bool
-isPowerOfTwo(uint64_t value)
-{
-    // if value ANDed with the value-1 is 0, then value is a power of 2.
-    // if value is 0, this is considered not a power of 2 and will return false.
-
-    return !(value & (value - 1));
-
-}
-
-///-----------------------------------------------------------------------------
-/// Round up to next higher power of 2 (return value if it's already a power of
-/// 2).
-///-----------------------------------------------------------------------------
-inline uint64_t
-PowerOf2Roundedup (uint64_t value)
-{
-    if (value < 0)
-        return 0;
-    --value;
-    value |= value >> 1;
-    value |= value >> 2;
-    value |= value >> 4;
-    value |= value >> 8;
-    value |= value >> 16;
-    return value+1;
-}
-
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.H
deleted file mode 100644
index 08ceaa157..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.H
+++ /dev/null
@@ -1,57 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_bar_config.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pba_bar_config.H,v 1.1 2012/09/25 20:18:52 stillgs Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
-// *!
-// *! General Description:
-// *!        
-// *! include file for p8_pba_bar_config 
-// *!
-//------------------------------------------------------------------------------
-// 
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_pba_bar_config_FP_t) (const fapi::Target&, 
-                                                            uint32_t, 
-                                                            uint64_t, 
-                                                            uint64_t, 
-                                                            uint64_t);
-
-extern "C" 
-{				
-
-fapi::ReturnCode 
-p8_pba_bar_config   (const fapi::Target&    i_target, 
-		             uint32_t               index, 
-		             uint64_t               pba_bar_addr,
-		             uint64_t               pba_bar_size,
-		             uint64_t               pba_cmd_scope);
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H
deleted file mode 100644
index 1fa234c10..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H
+++ /dev/null
@@ -1,233 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pba_init.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-// $Id: p8_pba_init.H,v 1.8 2014/03/17 23:16:35 stillgs Exp $
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Klaus P. Gungl         Email: kgungl@de.ibm.com
-// *!
-// *! General Description:
-// *!
-// *!  include file for pba_init with constants, definitions, prototypes
-// *!
-//------------------------------------------------------------------------------
-//
-
-#ifndef _P8_PBAINIT_H_
-#define _P8_PBAINIT_H_
-
-#include "p8_scom_addresses.H"
-
-typedef fapi::ReturnCode (*p8_pba_init_FP_t) (const fapi::Target& , uint64_t );
-
-// constant definitions for valid command scope. LIMIT is used by setup routine
-// for plausibility checking.
-
-#define PBA_CMD_SCOPE_NODAL    0x00
-#define PBA_CMD_SCOPE_GROUP    0x01
-#define PBA_CMD_SCOPE_SYSTEM   0x02
-#define PBA_CMD_SCOPE_RGP      0x03
-#define PBA_CMD_SCOPE_FOREIGN0 0x04
-#define PBA_CMD_SCOPE_FOREIGN1 0x05
-#define PBA_CMD_SCOPE_LIMIT    0x06
-
-enum cmd_scope_t
-{
-    CMD_SCOPE_NODAL,
-    CMD_SCOPE_GROUP,
-    CMD_SCOPE_SYSTEM,
-    CMD_SCOPE_RGP,
-    CMD_SCOPE_FOREIGN0,
-    CMD_SCOPE_FOREIGN1
-};
-// enum cmd_scope_type {NODAL, GROUP, SYSTEM, RGP, FOREIGN0, FOREIGN1 };
-
-
-// addresses of PBA and PBABAR, actually a duplicate of definitions in
-// "p8_scom_addresses.H" but here an array to be indexed.
-const uint64_t PBA_BARs[4] =
-{
-    PBA_BAR0_0x02013F00,
-    PBA_BAR1_0x02013F01,
-    PBA_BAR2_0x02013F02,
-    PBA_BAR3_0x02013F03
-};
-
-const uint64_t PBA_BARMSKs[4] =
-{
-    PBA_BARMSK0_0x02013F04,
-    PBA_BARMSK1_0x02013F05,
-    PBA_BARMSK2_0x02013F06,
-    PBA_BARMSK3_0x02013F07
-};
-
-const uint64_t PBA_SLVCTLs[4] =
-{
-    PBA_SLVCTL0_0x00064004,
-    PBA_SLVCTL1_0x00064005,
-    PBA_SLVCTL2_0x00064006,
-    PBA_SLVCTL3_0x00064007
-};
-
-const uint64_t PBA_SLVRESETs[4] =
-{
-    0x8000000000000000ull,
-    0xA000000000000000ull,
-    0xC000000000000000ull,
-    0xE000000000000000ull
-};
-
-// Maximum number of Polls for PBA slave reset
-#define MAX_PBA_RESET_POLLS     16
-#define PBA_RESET_POLL_DELAY    1       // in microseconds
-
-// Maximum number of Polls for PBA Block Copy Stopping - 500ms timeout
-#define MAX_PBA_BC_STOP_POLLS     256
-#define PBA_BC_STOP_POLL_DELAY    10    // in microseconds
-
-// bar mask is valid for bits 23 to 43, in a 64bit value this is
-//           1         2         3         4         5         6
-// 0123456789012345678901234567890123456789012345678901234567890123
-// 0000000000000000000000011111111111111111111100000000000000000000
-//    0   0   0   0   0   1   F   F   F   F   F   0   0   0   0   0
-// 0000000000000011111111111111111111111111111100000000000000000000
-//    0   0   0   3   F   F   F   F   F   F   F   0   0   0   0   0
-//                       0123456701234567
-#define BAR_MASK_LIMIT 0x000001FFFFF00000ull
-#define BAR_ADDR_LIMIT 0x0003FFFFFFF00000ull
-
-// structure of values for cmd_scope, pba and pbabar initialization
-typedef struct {
-  cmd_scope_t cmd_scope;
-  uint64_t addr;
-  uint64_t size;
-} struct_pba_bar_msk_scope_init_type;
-
-typedef struct {
-  struct_pba_bar_msk_scope_init_type regs0;
-  struct_pba_bar_msk_scope_init_type regs1;
-  struct_pba_bar_msk_scope_init_type regs2;
-  struct_pba_bar_msk_scope_init_type regs3;
-} pba_init_type;
-
-typedef struct {
-  unsigned long reserved_3:20;
-  unsigned long addr:30;
-  unsigned short reserved_2:10;
-  char reserved_1:1;
-  uint8_t cmd_scope:3;
-} struct_pba_bar_fields_type;
-
-typedef struct {
-  unsigned long reserved_1:23;
-  unsigned long mask:21;
-  unsigned long reserved_2:20;
-} struct_pba_barmsk_fields_type;
-
-typedef union {
-  struct_pba_bar_fields_type fields;
-  uint64_t value;
-} bar_reg_type;
-
-typedef union {
-  struct_pba_barmsk_fields_type fields ;
-  uint64_t value;
-} barmsk_reg_type;
-
-typedef struct {
-  bar_reg_type     bar_reg;
-  barmsk_reg_type  barmsk_reg;
-} struct_pba_bar_init_type;
-
-
-typedef struct {
-  struct struct_pba_bar{
-    char cmd_scope:3;
-    char reserved_1:1;
-    unsigned short reserved_2:10;
-    unsigned long addr:30;
-    unsigned long reserved_3:20;
-  };
-  struct struct_pba_barmsk{
-    unsigned long reserved_1:23;
-    unsigned long mask:21;
-    unsigned long reserved_2:20;
-  };
-} struct_pba_bar_init_type_1;
-
-typedef struct {
-  struct_pba_bar_init_type pba_bar0_init;
-  struct_pba_bar_init_type pba_bar1_init;
-  struct_pba_bar_init_type pba_bar2_init;
-  struct_pba_bar_init_type pba_bar3_init;
-} struct_all_pba_bar_init_type;
-
-
-typedef uint64_t pba_slvctl_type;
-
-
-typedef union pbaxcfg_typ{
-   uint64_t value;
-   struct {
-     unsigned long  reserved_0 :20;
-     unsigned char  ATTR_PM_PBAX_RCV_RESERV_TIMEOUT :5 ;
-     unsigned long  reserved_1 :2;
-     unsigned char  ATTR_PM_PBAX_SND_RETRY_COUNT_OVERCOMMIT_ENABLE :1 ;
-     unsigned short ATTR_PM_PBAX_SND_RETRY_THRESHOLD :8 ;
-     unsigned short ATTR_PM_PBAX_SND_RESERV_TIMEOUT  :5 ;
-     unsigned long  reserved_2 :23 ;
-   } fields;
-} pbaxcfg_t;
-
-// BCDE and BCUE Status registers bits
-#define PBA_BC_STAT_RUNNING  0
-#define PBA_BC_STAT_STOPPED 29
-#define PBA_BC_STAT_ERROR   30
-#define PBA_BC_STAT_DONE    31
-
-
-// ----------------------------------------------------------------------
-// Function prototypes
-// ----------------------------------------------------------------------
-
-extern "C"
-{
-
-fapi::ReturnCode
-p8_pba_init (const fapi::Target& i_target,
-                     uint64_t mode
-              );
-
-
-} // extern "C"
-
-
-
-#endif // _P8_PBAINITQ_H_
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H
deleted file mode 100755
index 33bd0e19f..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H
+++ /dev/null
@@ -1,61 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pcb_scom_errors.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pcb_scom_errors.H,v 1.3 2013/02/16 20:26:51 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pcb_scom_errors.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Gebhard Weber       Email: gweber@de.ibm.com
-// *!
-// *! General Description: Defines FFDC error codes for the procedures
-// *!                      proc_timeout_error and proc_parity_error
-//------------------------------------------------------------------------------
-
-#ifndef P8_PCB_SCOM_ERRORS_H_
-#define P8_PCB_SCOM_ERRORS_H_
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C" {
-
-    enum PCB_ERRORS {
-            PIB_NO_ERROR      = 0x0,
-            PIB_XSCOM_ERROR   = 0x1,
-            PIB_OFFLINE_ERROR = 0x2,
-            PIB_PARTIAL_ERROR = 0x3,
-            PIB_ADDRESS_ERROR = 0x4,
-            PIB_CLOCK_ERROR   = 0x5,
-            PIB_PARITY_ERROR  = 0x6,
-            PIB_TIMEOUT_ERROR = 0x7
-    };
-
-} // extern "C"
-
-#endif // P8_PCB_SCOM_ERRORS_H_
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C
deleted file mode 100644
index 7ebdb394b..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C
+++ /dev/null
@@ -1,2372 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pfet_control.C,v 1.16 2015/05/13 03:47:51 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_control.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
-// *!
-/// \file p8_pfet_control.C
-/// \brief Perform override operations to the EX PFET headers
-///
-/// High-level procedure flow:
-/// \verbatim
-///
-///  Procedure Prereq:
-///     - System clocks are running
-/// \endverbatim
-///
-///   PFVddCntlStat (0x106) layout
-///     Control
-///       0:1 - core_vdd_pfet_force_state 00: nop; 01: Voff; 10: Vret; 11: Von (4:5 must be 00)
-///       2:3 - eco_vdd_pfet_force_state  00: nop; 01: Voff; 10: Vret; 11: Von (6:7 must be 00)
-///       4   - core_vdd_pfet_val_override 0: disable; 1: enable  (0 enables 0:1)
-///       5   - core_vdd_pfet_sel_override 0: disable; 1: enable        (0 enables 0:1)
-///       6   - eco_vdd_pfet_val_override  0: disable; 1: enable  (0 enables 2:3)
-///       7   - eco_vdd_pfet_sel_override  0: disable; 1: enable        (0 enables 2:3)
-///
-///     Status
-///       42:45 - core_vdd_pfet_state (42: Idle; 43: Increment; 44: Decrement; 45: Wait)
-///       46:49 - not relevant
-///       50:53 - eco_vdd_pfet_state (50: Idle; 51: Increment; 52: Decrement; 53: Wait)
-///       54:57 - not relevant
-///
-///   PFVcsCntlStat (0x10E) layout
-///     Control
-///       0:1 - core_vcs_pfet_force_state 00: nop; 01: Voff; 10: Vret; 11: Von (4:5 must be 00)
-///       2:3 - eco_vcs_pfet_force_state  00: nop; 01: Voff; 10: Vret; 11: Von (6:7 must be 00)
-///       4   - core_vcs_pfet_val_override 0: disable; 1: enable  (0 enables 0:1)
-///       5   - core_vcs_pfet_sel_override 0: disable; 1: enable        (0 enables 0:1)
-///       6   - eco_vcs_pfet_val_override  0: disable; 1: enable  (0 enables 2:3)
-///       7   - eco_vcs_pfet_sel_override  0: disable; 1: enable        (0 enables 2:3)
-///     Status
-///       42:45 - core_vcs_pfet_state (42: Idle; 43: Increment; 44: Decrement; 45: Wait)
-///       46:49 - not relevant
-///       50:53 - eco_vcs_pfet_state (50: Idle; 51: Increment; 52: Decrement; 53: Wait)
-///       54:57 - not relevant
-///
-///  buildfapiprcd -e "../../xml/error_info/p8_pfet_errors.xml" -C p8_pm_utils.C p8_pfet_control.C
-///
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-#include "p8_pm.H"
-#include "p8_pm_utils.H"
-#include "p8_pfet_control.H"
-
-
-extern "C" {
-
-
-using namespace fapi;
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Global variables
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-const uint32_t      CORE_FORCE_STATE        = 0;
-const uint32_t      CORE_FORCE_LENGTH       = 2;  // 0:1
-const uint32_t      ECO_FORCE_STATE         = 2;
-const uint32_t      ECO_FORCE_LENGTH        = 2;  // 2:3
-const uint32_t      CORE_OVERRIDE_STATE     = 4;
-const uint32_t      CORE_OVERRIDE_LENGTH    = 2;  // 4:5
-const uint32_t      ECO_OVERRIDE_STATE      = 6;
-const uint32_t      ECO_OVERRIDE_LENGTH     = 2;  // 6:7
-const uint32_t      CORE_OVERRIDE_SEL       = 22;
-const uint32_t      CORE_OVERRIDE_SEL_LENGTH = 4; // 22:25
-const uint32_t      ECO_OVERRIDE_SEL        = 38;
-const uint32_t      ECO_OVERRIDE_SEL_LENGTH = 4;  // 38:41
-const uint32_t      CORE_FSM_IDLE_BIT       = 42;
-const uint32_t      ECO_FSM_IDLE_BIT        = 50;
-const uint32_t      PFET_MAX_IDLE_POLLS     = 16;
-const uint32_t      PFET_POLL_WAIT          = 1000000;  // 100us (in ns units)
-const uint32_t      PFET_POLL_WAIT_SIM      = 1000;     // 100us (in sim cycles)
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode p8_pfet_on (const fapi::Target& i_target,
-                             uint8_t             i_ex_number,
-                             pfet_dom_t          i_domain);
-
-fapi::ReturnCode p8_pfet_off(const fapi::Target& i_target,
-                             uint8_t             i_ex_number,
-                             pfet_dom_t          i_domain);
-
-fapi::ReturnCode p8_pfet_off_override( const fapi::Target& i_target,
-                             uint8_t             i_ex_number,
-                             pfet_dom_t          i_domain);
-
-fapi::ReturnCode p8_pfet_poll(const fapi::Target& i_target,
-                            uint8_t              i_ex_number,
-                            uint64_t             i_address,
-                            pfet_dom_t           i_domain);
-
-fapi::ReturnCode p8_pfet_read_state(const fapi::Target& i_target,
-                            const uint64_t      i_address,
-                            const uint32_t      i_bitoffset,
-                            char *              o_state);
-
-fapi::ReturnCode p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target,
-                            uint8_t             i_ex_number,
-                            pfet_dom_t          i_domain,
-                            pfet_force_t        i_op);
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-/// \param[in] i_target     Chip target
-/// \param[in] i_ex_number  EX number
-/// \param[in] i_domain     Domain: BOTH, ECO, CORE
-/// \param[in] i_op         Operation: VON, VOFF, VOFF_OVERRIDE
-///
-/// \retval FAPI_RC_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode
-p8_pfet_control(  const fapi::Target&   i_target,
-                    uint8_t             i_ex_number,
-                    pfet_dom_t          i_domain,
-                    pfet_force_t        i_op
-                 )
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data(64);
-    ecmdDataBufferBase          pmgp0(64);
-    ecmdDataBufferBase          gp3(64);
-    uint64_t                    address = 0;
-    bool                        restore_pmgp0 = false;
-    bool                        restore_gp3 = false;
-
-    // valid domain options
-    const char * pfet_dom_names[] =
-    {
-      "BOTH", // write to both domains
-      "ECO",  // eco only
-      "CORE"  // core only
-    };
-
-    do
-    {
-
-        uint8_t ipl_mode = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode);
-        if (!l_rc.ok())
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)l_rc);
-            break;
-        }
-        FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL");
-
-        l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number,
-                                "start of p8_pfet_control");
-        if (!l_rc.ok()) { break; }
-
-        // Check for valid operation parameter
-        if ((i_op != VON) && (i_op != VOFF) && (i_op != VOFF_OVERRIDE))
-        {
-            FAPI_ERR("\tInvalid operation parm 0x%x", i_op);
-            const uint8_t & EX = i_ex_number;
-            const pfet_dom_t & DOMAIN = i_domain;
-            const pfet_force_t & OPERATION = i_op;
-            FAPI_SET_HWP_ERROR(l_rc, RC_PMPROC_PFETLIB_BAD_OP);
-            break;
-        }
-
-        // Check for valid domain parameter
-        if ((i_domain != CORE) && (i_domain != ECO) && (i_domain != BOTH))
-        {
-            FAPI_ERR("\tInvalid domain parm 0x%x", i_domain);
-            const uint8_t & EX = i_ex_number;
-            const pfet_dom_t & DOMAIN = i_domain;
-            FAPI_SET_HWP_ERROR(l_rc, RC_PMPROC_PFETLIB_BAD_DOMAIN);
-            break;
-        }
-
-        FAPI_INF("Processing target %s", i_target.toEcmdString());
-
-        // Check the PM controls and Pervasive clocks are enabled.
-        FAPI_DBG("\tChecking PMGP0(0) for enablement on EX %d ", i_ex_number);
-        address = EX_PMGP0_0x100F0100 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        // If not, enable them.
-        if (data.isBitSet(0))
-        {
-            FAPI_INF("\tPM controls not enabled; enabling to allow control");
-            restore_pmgp0 = true;
-            pmgp0 = data;
-
-            address = EX_PMGP0_AND_0x100F0101 + (0x01000000 * i_ex_number);
-            e_rc |= data.flushTo1();
-            e_rc |= data.clearBit(0);   // PM disable
-            e_rc |= data.clearBit(39);  // Remove logical pervasive/pcbs-pm fence
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number,
-                                "after of PM enablement");
-            if (!l_rc.ok()) { break; }
-
-            // Read to allow for Cronus 5.1 or 5.6 to look at the resultant setting
-            address = EX_PMGP0_0x100F0100 + (0x01000000 * i_ex_number);
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-
-            // Clear PCB_EP_RESET and the Winkle Electrical Fence to allow
-            // settings to take on non-reset values
-            address = EX_GP3_0x100F0012 + (0x01000000 * i_ex_number);
-
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-            FAPI_DBG("\tEX_GP3_0x%08llX before  0x%16llX",
-                                    address,
-                                    data.getDoubleWord(0));
-
-            if (data.isBitSet(1))
-            {
-                restore_gp3 = true;
-                gp3 = data;
-
-                // --- Glitchless Mux reset
-                FAPI_DBG("\tClearing glitchless mux reset in GP3");
-                address = EX_GP3_AND_0x100F0013 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo1();
-                e_rc |= data.clearBit(2);   // Glitchless Mux reset
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                // --- Test override
-                FAPI_DBG("\tSetting test override in GP3");
-                address = EX_GP3_OR_0x100F0014 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo0();
-                e_rc |= data.setBit(20);    // Test override
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                // --- End point reset
-                FAPI_DBG("\tClearing PCB endpoint reset for allow for non-reset values.");
-                address = EX_GP3_AND_0x100F0013 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo1();
-                e_rc |= data.clearBit(1);   // End point reset
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                     FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                // GP3
-                address = EX_GP3_0x100F0012 + (0x01000000 * i_ex_number);
-                l_rc = fapiGetScom(i_target, address, data);
-                if (l_rc) {
-                  FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                  break;
-                }
-
-                FAPI_DBG("\tDebug Info:  GP3      (addr: 0x%08llX) - 0x%016llX", address, data.getDoubleWord(0));
-
-                // --- Chiplet enable
-                FAPI_DBG("\tTemporarily setting chiplet enable in GP3");
-                address = EX_GP3_OR_0x100F0014 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo0();
-                e_rc |= data.setBit(0);   // Chiplet enable
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                // --- Vital THOLD, Winkle Fence
-                FAPI_DBG("\tSetting Vital THOLD and Winkle Fence in GP3");
-                address = EX_GP3_OR_0x100F0014 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo0();
-                e_rc |= data.setBit(16);    // Vital THOLD
-                e_rc |= data.setBit(27);    // Electrical Winkle Fence for PM
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                FAPI_DBG("\tSetting DPLL, PERV THOLD and Perv ECO Fence in PMGP0");
-                address = EX_PMGP0_OR_0x100F0102 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo0();
-                e_rc |= data.setBit(3);     // DPLL THOLD
-                e_rc |= data.setBit(4);     // PERV THOLD
-                e_rc |= data.setBit(22);    // PERVASIVE_ECO_FENCE
-                e_rc |= data.setBit(39);    // Remove logical pervasive/pcbs-pm fence/
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                FAPI_DBG("\tClearing old winkle fence to match SBE implementation in PMGP0");
-                address = EX_PMGP0_AND_0x100F0101 + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo1();
-                e_rc |= data.clearBit(23);  // Old
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                // Clear Special Wakeups present in uninitialized chiplets
-                FAPI_DBG("\tClear Special Wakeups present in uninitialized chiplets");
-                address = EX_PMSpcWkupOCC_REG_0x100F010C + (0x01000000 * i_ex_number);
-                e_rc |= data.flushTo0();
-
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                l_rc=fapiPutScom( i_target, address, data );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("PutScom error 0x%08llX", address);
-                    break;
-                }
-
-                l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number,
-                                "after of GP3(0) handling");
-                if (!l_rc.ok()) { break; }
-            }
-        }
-
-        // Reads to allow for Cronus 5.1 or 5.6 to look at the resultant setting
-        address = EX_PMGP0_0x100F0100 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        address = EX_GP3_0x100F0012 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number,
-                                "before transition choice");
-        if (!l_rc.ok()) { break; }
-
-        // Off
-        if (i_op == VOFF)
-        {
-            l_rc=p8_pfet_off(i_target, i_ex_number, i_domain);
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("\tPFET turn off of %s domains failed",
-                            pfet_dom_names[i_domain]);
-                break;
-            }
-        }
-        else if (i_op == VOFF_OVERRIDE)
-        {
-            l_rc=p8_pfet_off_override(i_target, i_ex_number, i_domain);
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("\tPFET turn off of %s domains failed",
-                            pfet_dom_names[i_domain]);
-                break;
-            }
-        }
-        // On
-        else if (i_op == VON)
-        {
-            l_rc=p8_pfet_on(i_target, i_ex_number, i_domain);
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("\tPFET turn on of %s domains failed",
-                            pfet_dom_names[i_domain]);
-                break;
-            }
-
-            l_rc = p8_pm_pcbs_fsm_trace (i_target, i_ex_number,
-                                "after VON handling");
-            if (!l_rc.ok()) { break; }
-
-        }
-
-        // Restore GP3 except for reinit_endp as this will force power on
-        if (restore_gp3)
-        {
-            address = EX_GP3_0x100F0012 + (0x01000000 * i_ex_number);
-            e_rc |= gp3.clearBit(1);   // End point reset
-
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-            FAPI_DBG("\tRestoring GP3 with the exception of endpoint reset:  0x%16llX", gp3.getDoubleWord(0));
-            l_rc=fapiPutScom( i_target, address, gp3 );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-        }
-
-        // Restore PMGP0 settings
-        if (restore_pmgp0)
-        {
-            address = EX_PMGP0_0x100F0100 + (0x01000000 * i_ex_number);
-            FAPI_DBG("\tRestoring PMGP0: 0x%16llX", pmgp0.getDoubleWord(0));
-            l_rc=fapiPutScom( i_target, address, pmgp0 );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-        }
-
-
-    } while(0);
-
-
-
-    return l_rc;
-}
-
-///-----------------------------------------------------------------------------
-/// Turn a chiplet domain on - VCS first, then VDD
-///
-/// \param[in] i_target     Chip target
-/// \param[in] i_ex_number  EX number
-/// \param[in] i_domain     Domain: ECO, CORE, BOTH
-///
-/// \retval FAPI_RC_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode
-p8_pfet_on( const fapi::Target& i_target,
-            uint8_t             i_ex_number,
-            pfet_dom_t          i_domain
-          )
-{
-
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data(64);
-    uint64_t                    address;
-    bool                        b_core = false;
-    bool                        b_eco = false;
-
-    do
-    {
-        if ((i_domain == CORE) || (i_domain == BOTH))
-        {
-            b_core = true;
-        }
-        if ((i_domain == ECO) || (i_domain == BOTH))
-        {
-            b_eco = true;
-        }
-
-        uint8_t  chipHasPFETPoweroffBug = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_PFET_POWEROFF_BUG,
-                             &i_target,
-                             chipHasPFETPoweroffBug);
-        if(!l_rc.ok())
-        {
-     		FAPI_ERR("Error querying Chip EC feature: "
-                     "ATTR_CHIP_EC_PFET_POWEROFF_BUG");
-            break;
-        }
-
-        if (chipHasPFETPoweroffBug)
-        {
-            l_rc = p8_pfet_ivrm_fsm_fix(i_target,
-                                        i_ex_number,
-                                        i_domain,
-                                        VON);
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PFET IVMR fix error");
-                break;
-            }
-
-        }
-        // VCS ---------------------
-
-        FAPI_INF("Turning on VCS");
-        address = EX_PFET_CTL_REG_0x100F010E + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        if (b_core)
-        {
-            FAPI_DBG("\tEnabling turn on of Core VDD");
-            e_rc |= data.clearBit(CORE_OVERRIDE_STATE, CORE_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VON, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30);
-        }
-
-        if (b_eco)
-        {
-            FAPI_DBG("\tEnabling turn on of ECO VDD");
-            e_rc |= data.clearBit(ECO_OVERRIDE_STATE, ECO_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VON, ECO_FORCE_STATE, ECO_FORCE_LENGTH, 30);
-        }
-
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Poll for completion
-        l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PFET poll timeout turning on VCS");
-            break;
-        }
-
-        // Put the controls back to a Nop state
-        e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-        e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // VDD ---------------------
-
-        FAPI_INF("Turning on VDD for EX %d", i_ex_number);
-        address = EX_PFET_CTL_REG_0x100F0106 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        if (b_core)
-        {
-            FAPI_DBG("\tEnabling turn on of Core VDD");
-            e_rc |= data.clearBit(CORE_OVERRIDE_STATE, CORE_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VON, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30);
-        }
-
-        if (b_eco)
-        {
-            FAPI_DBG("\tEnabling turn on of ECO VDD");
-            e_rc |= data.clearBit(ECO_OVERRIDE_STATE, ECO_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VON, ECO_FORCE_STATE, ECO_FORCE_LENGTH, 30);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Poll for completion
-        l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PFET poll timeout turning on VDD");
-            break;
-        }
-
-        // Put the controls back to a Nop state
-        e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-        e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-    } while(0);
-    return l_rc;
-}
-
-///-----------------------------------------------------------------------------
-/// Turn a chiplet domain off - VDD first, then VCS
-///
-/// \param[in] i_target     Chip target
-/// \param[in] i_ex_number  EX number
-/// \param[in] i_domain     Domain: ECO, CORE, BOTH
-///
-/// \retval FAPI_RC_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode
-p8_pfet_off( const fapi::Target& i_target,
-             uint8_t             i_ex_number,
-             pfet_dom_t          i_domain
-           )
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data(64);
-    uint64_t                    address;
-    bool                        b_core = false;
-    bool                        b_eco = false;
-
-    uint8_t                     core_vret_voff_value;
-    uint8_t                     eco_vret_voff_value;
-
-    do
-    {
-        if ((i_domain == CORE) || (i_domain == BOTH))
-        {
-            b_core = true;
-        }
-        if ((i_domain == ECO) || (i_domain == BOTH))
-        {
-            b_eco = true;
-        }
-
-        uint8_t  chipHasPFETPoweroffBug = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_PFET_POWEROFF_BUG,
-                             &i_target,
-                             chipHasPFETPoweroffBug);
-        if(!l_rc.ok())
-        {
-     		FAPI_ERR("Error querying Chip EC feature: "
-                     "ATTR_CHIP_EC_PFET_POWEROFF_BUG");
-            break;
-        }
-
-        if (chipHasPFETPoweroffBug)
-        {
-            l_rc = p8_pfet_ivrm_fsm_fix(i_target,
-                                        i_ex_number,
-                                        i_domain,
-                                        VOFF);
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PFET IVMR fix error");
-                break;
-            }
-        }
-
-        // Check if iVRM Bypasses are active
-        address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 +
-                        (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tEX_PCBS_iVRM_Control_Status_Reg_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        e_rc |= data.flushTo0();
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tEX_PCBS_iVRM_Control_Status_Reg_0x%08llX after  0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-
-        // As we need to turn the PFETs off, ensure the stage pointers to the
-        // OFF value are in place (and not assumed).
-        core_vret_voff_value = 0xBB;
-        eco_vret_voff_value = 0xBB;
-
-        // -------------------------------------------------------------
-        FAPI_DBG("\tSetting Core Voff Settings");
-        e_rc |= data.insertFromRight(core_vret_voff_value, 0, 8);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        address = EX_CorePFVRET_REG_0x100F0130 + (0x01000000 * i_ex_number);
-        l_rc=fapiPutScom(i_target, address, data );
-        if (l_rc)
-        {
-            FAPI_ERR("PutScom error 0x%08llu", address);
-            break;
-        }
-
-        // -------------------------------------------------------------
-        FAPI_DBG("\tSetting ECO Voff Settings");
-        e_rc |= data.insertFromRight(eco_vret_voff_value, 0, 8);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        address = EX_ECOPFVRET_REG_0x100F0150 + (0x01000000 * i_ex_number);
-        l_rc=fapiPutScom(i_target, address, data );
-        if (l_rc)
-        {
-            FAPI_ERR("PutScom error 0x%08llu", address);
-            break;
-        }
-
-        // Ensure that the chiplet is electrically fenced before shutting down
-        // the power
-        FAPI_INF("Force EX electrical fence ON before turning off power");
-        e_rc |= data.flushTo0();
-        e_rc |= data.setBit(27);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        address = EX_GP3_OR_0x100F0014 + (0x01000000 * i_ex_number);
-        l_rc=fapiPutScom( i_target, address, data);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-        
-        address = EX_GP3_0x100F0012 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tEX_GP3_0x%08llX with electrical fence set 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        // VDD ---------------------
-
-        FAPI_INF("Turning off VDD");
-
-        address = EX_PFET_CTL_REG_0x100F0106 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        if (b_core)
-        {
-            FAPI_DBG("\tClearing overrides to enable turn off of Core VDD");
-            e_rc |= data.clearBit(CORE_OVERRIDE_STATE, CORE_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VOFF, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30);
-        }
-
-        if (b_eco)
-        {
-            FAPI_DBG("\tClearing overrides to enable turn off of ECO VDD");
-            e_rc |= data.clearBit(ECO_OVERRIDE_STATE, ECO_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VOFF, ECO_FORCE_STATE, ECO_FORCE_LENGTH, 30);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX after  0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Poll for completion
-        l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PFET poll timeout turning off VDD");
-            break;
-        }
-
-        FAPI_DBG("Put the controls back to a Nop state");
-        e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-        e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("\tNOP 0x%16llX", data.getDoubleWord(0));
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Read to allow for Cronus 5.1 or 5.6 to look at the resultant setting
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        // VCS ---------------------
-
-        FAPI_INF("Turning off VCS");
-        address = EX_PFET_CTL_REG_0x100F010E + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        if (b_core)
-        {
-            FAPI_DBG("\tClearing overrides to enable turn off of Core VDD");
-            e_rc |= data.clearBit(CORE_OVERRIDE_STATE, CORE_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VOFF, CORE_FORCE_STATE, CORE_FORCE_LENGTH, 30);
-        }
-
-        if (b_eco)
-        {
-            FAPI_DBG("\tClearing overrides to enable turn off of ECO VDD");
-            e_rc |= data.clearBit(ECO_OVERRIDE_STATE, ECO_OVERRIDE_LENGTH);
-            e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-            e_rc |= data.insert((uint32_t)VOFF, ECO_FORCE_STATE, ECO_FORCE_LENGTH, 30);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX after  0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Poll for completion
-        l_rc=p8_pfet_poll(i_target, i_ex_number, address, i_domain);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PFET poll timeout turning on VCS");
-            break;
-        }
-
-        FAPI_DBG("\tPut the controls back to a Nop state");
-        e_rc |= data.clearBit(CORE_FORCE_STATE, CORE_FORCE_LENGTH);
-        e_rc |= data.clearBit(ECO_FORCE_STATE, ECO_FORCE_LENGTH);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("\tNOP 0x%16llX", data.getDoubleWord(0));
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Read to allow for Cronus 5.1 or 5.6 to look at the resultant setting
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-    } while(0);
-    return l_rc;
-}
-
-///-----------------------------------------------------------------------------
-/// Turn a chiplet domain off - VDD first, then VCS
-///
-/// \param[in] i_target     Chip target
-/// \param[in] i_ex_number  EX number
-/// \param[in] i_domain     Domain: ECO, CORE, BOTH
-///
-/// \retval FAPI_RC_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode
-p8_pfet_off_override( const fapi::Target& i_target,
-             uint8_t             i_ex_number,
-             pfet_dom_t          i_domain
-           )
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data(64);
-    uint64_t                    address;
-    bool                        b_core = false;
-    bool                        b_eco = false;
-    const uint32_t              core_regulation_finger = 10;
-    const uint32_t              eco_regulation_finger = 26;
-
-    do
-    {
-         if ((i_domain == CORE) || (i_domain == BOTH))
-        {
-            b_core = true;
-        }
-        if ((i_domain == ECO) || (i_domain == BOTH))
-        {
-            b_eco = true;
-        }
-
-        uint8_t  chipHasPFETPoweroffBug = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_PFET_POWEROFF_BUG,
-                             &i_target,
-                             chipHasPFETPoweroffBug);
-        if(!l_rc.ok())
-        {
-     		FAPI_ERR("Error querying Chip EC feature: "
-                     "ATTR_CHIP_EC_PFET_POWEROFF_BUG");
-            break;
-        }
-
-        if (chipHasPFETPoweroffBug)
-        {
-            l_rc = p8_pfet_ivrm_fsm_fix(i_target,
-                                        i_ex_number,
-                                        i_domain,
-                                        VOFF);
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PFET IVMR fix error");
-                break;
-            }
-        }
-
-        // Check if iVRM Bypasses are active
-        address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 +
-                        (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tEX_PCBS_iVRM_Control_Status_Reg_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        e_rc |= data.flushTo0();
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tEX_PCBS_iVRM_Control_Status_Reg_0x%08llX after  0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        // VDD ---------------------
-
-        FAPI_INF("Turning off VDD with controller override");
-
-        address = EX_PFET_CTL_REG_0x100F0106 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        // Turn off the non-regulation fingers (relative bits 1:11)
-        for (int i = 1; i <= 11; i++)
-        {
-            if (b_core)
-            {
-                FAPI_DBG("\tClearing Core VDD finger %d", core_regulation_finger+i);
-                e_rc |= data.clearBit(core_regulation_finger+i);
-            }
-
-            if (b_eco)
-            {
-                FAPI_DBG("\tClearing ECO VDD finger %d", eco_regulation_finger+i);
-                e_rc |= data.clearBit(eco_regulation_finger+i);
-            }
-
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-            FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX after  0x%16llX",
-                                    address,
-                                    data.getDoubleWord(0));
-
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            // Read to allow for Cronus 5.1 or 5.6 to look at the resultant setting
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-        }
-
-        // Turn off the regulation finger:  core first, then ECO
-        if (b_core)
-        {
-            FAPI_DBG("\tClearing Core VDD regulation finger %d", core_regulation_finger);
-            e_rc |= data.clearBit(core_regulation_finger);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        if (b_eco)
-        {
-            FAPI_DBG("\tClearing ECO regulation VDD finger %d", eco_regulation_finger);
-            e_rc |= data.clearBit(eco_regulation_finger);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-
-
-
-        // VCS ---------------------
-
-        FAPI_INF("Turning off VCS with controller override");
-
-        address = EX_PFET_CTL_REG_0x100F010E + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX before 0x%16llX",
-                                address,
-                                data.getDoubleWord(0));
-
-        // Turn off the non-regulation fingers (relative bits 1:11)
-        for (int i = 1; i <= 11; i++)
-        {
-            if (b_core)
-            {
-                FAPI_DBG("\tClearing Core VCS finger %d", core_regulation_finger+i);
-                e_rc |= data.clearBit(core_regulation_finger+i);
-            }
-
-            if (b_eco)
-            {
-                FAPI_DBG("\tClearing ECO VCS finger %d", eco_regulation_finger+i);
-                e_rc |= data.clearBit(eco_regulation_finger+i);
-            }
-
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-            FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX after  0x%16llX",
-                                    address,
-                                    data.getDoubleWord(0));
-
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-        }
-
-        // Turn off the regulation finger:  core first, then ECO
-        if (b_core)
-        {
-            FAPI_DBG("\tClearing Core VCS regulation finger %d", core_regulation_finger);
-            e_rc |= data.clearBit(core_regulation_finger);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        if (b_eco)
-        {
-            FAPI_DBG("\tClearing ECO regulation VCS finger %d", eco_regulation_finger);
-            e_rc |= data.clearBit(eco_regulation_finger);
-        }
-
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        if (b_core)
-        {
-            FAPI_DBG("\tClearing Core VCS overrides %d", core_regulation_finger);
-            e_rc |= data.clearBit(core_regulation_finger);
-
-            FAPI_DBG("\tSetting the select value to indicate OFF for ECO VCS");
-            e_rc |= data.setBit(5);
-            e_rc |= data.insert((uint32_t)0xB, CORE_OVERRIDE_SEL, CORE_OVERRIDE_SEL_LENGTH, 28);
-        }
-
-
-        // Read to allow for Cronus 5.1 or 5.6 to look at the resultant setting
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-    } while(0);
-    return l_rc;
-}
-
-/// \param[in] i_target     Chip target
-/// \param[in] i_address    Address to poll for PFET State
-/// \param[in] i_domain     Domain: BOTH, ECO, CORE
-///
-/// \retval FAPI_RC_SUCCESS
-/// \retval RC_PROCPM_PFET_TIMEOUT otherwise
-fapi::ReturnCode
-p8_pfet_poll(   const fapi::Target& i_target,
-                uint8_t             i_ex_number,
-                uint64_t            i_address,
-                pfet_dom_t          i_domain)
-{
-    fapi::ReturnCode            l_rc;
-    ecmdDataBufferBase          data(64);
-    uint32_t                    i = 0;
-    bool                        b_core_idle = false;
-    bool                        b_eco_idle = false;
-    char                        core_state_buffer[32];
-    char                        eco_state_buffer[32];
-
-    uint32_t                    CORE_PFET_IDLE_STATE_START_BIT = 46;
-    uint32_t                    ECO_PFET_IDLE_STATE_START_BIT = 54;
-
-    do
-    {
-        FAPI_DBG("\tPoll for FSM to go back to idle");
-        for (i=0; i<=PFET_MAX_IDLE_POLLS; i++)
-        {
-            l_rc=fapiGetScom(i_target, i_address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", i_address);
-                break;
-            }
-
-            if ((i_domain == CORE) || (i_domain == BOTH))
-            {
-                if (data.isBitSet(CORE_FSM_IDLE_BIT))
-                {
-                    FAPI_DBG("\tCore domain idle");
-                    b_core_idle=true;
-                }
-            }
-            if ((i_domain == ECO) || (i_domain == BOTH))
-            {
-                if (data.isBitSet(ECO_FSM_IDLE_BIT))
-                {
-                    FAPI_DBG("\tECO domain idle");
-                    b_eco_idle=true;
-                }
-            }
-
-            // Exit the polling loop if selected are idle
-            if ( ((i_domain == BOTH) && b_core_idle && b_eco_idle) ||
-                 ((i_domain == CORE) && b_core_idle) ||
-                 ((i_domain == ECO) && b_eco_idle) )
-            {
-                FAPI_DBG("\tPoll complete");
-
-                // Check for Core State
-                l_rc = p8_pfet_read_state(   i_target,
-                                        i_address,
-                                        CORE_PFET_IDLE_STATE_START_BIT,
-                                        core_state_buffer );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("pfet_read_state Core error 0x%08llX", i_address);
-                    break;
-                }
-
-                // Check for ECO State
-                l_rc = p8_pfet_read_state(   i_target,
-                                        i_address,
-                                        ECO_PFET_IDLE_STATE_START_BIT,
-                                        eco_state_buffer );
-                if(!l_rc.ok())
-                {
-                    FAPI_ERR("pfet_read_state ECO error 0x%08llX", i_address);
-                    break;
-                }
-
-                FAPI_DBG("\tCore State: %s; ECO State: %s", core_state_buffer, eco_state_buffer);
-                break;
-            }
-
-            // Delay between polls
-            l_rc=fapiDelay( PFET_POLL_WAIT, PFET_POLL_WAIT_SIM );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("fapiDelay error");
-                break;
-            }
-        }
-
-        if (l_rc)
-        {
-            // Error in for loop
-            break;
-        }
-
-        if (i >= PFET_MAX_IDLE_POLLS)
-        {
-            // Poll timeout
-            FAPI_ERR("\tERROR: Polling timeout ");
-            const uint64_t& ADDRESS = i_address;
-            const uint64_t& PFETCONTROLVALUE = data.getDoubleWord(0);
-            const uint64_t& DOMAIN = i_domain;
-            const fapi::Target & PROC_CHIP_IN_ERROR = i_target;
-            const uint8_t & EX_NUMBER_IN_ERROR = i_ex_number;
-            FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFETLIB_TIMEOUT);
-            break;
-        }
-    } while(0);
-    return l_rc;
-}
-
-//------------------------------------------------------------------------------
-/// p8_pfet_read_state
-///
-/// \param[in]  i_target     Chip target
-/// \param[in]  i_address    Address to poll for PFET State
-/// \param[in]  i_bitoffset  Bit to poll on
-/// \param[out] o_state      String representing the state of the controller
-///                             "OFF", "ON", "REGULATION", "UNDEFINED"
-fapi::ReturnCode
-p8_pfet_read_state(const fapi::Target& i_target,
-                const uint64_t      i_address,
-                const uint32_t      i_bitoffset,
-                char *              o_state)
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data;
-    uint32_t                    value;
-
-    do
-    {
-        l_rc=fapiGetScom( i_target, i_address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", i_address);
-            break;
-        }
-
-        FAPI_DBG("\tEX_PFET_CTL_REG_0x%08llX 0x%16llX",
-                                i_address,
-                                data.getDoubleWord(0));
-
-
-        e_rc = data.extractToRight(&value,i_bitoffset,4);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-
-        if (value == 0xB)
-        {
-            strcpy(o_state, "OFF");
-        }
-        else if (value == 0)
-        {
-            strcpy(o_state, "ON");
-        }
-        else if (value == 8)
-        {
-            strcpy(o_state, "REGULATION");
-        }
-        else
-        {
-            strcpy(o_state, "UNDEFINED");
-        }
-
-   } while(0);
-   return l_rc;
-}
-
-//------------------------------------------------------------------------------
-/// p8_pfet_ivrm_fsm_fix
-///  Fix ivrm FSM interference with PFET power off
-/// \param[in] i_target     Chip target
-/// \param[in] i_ex_number  EX number
-/// \param[in] i_domain     Domain: BOTH, ECO, CORE
-/// \param[in] i_op         Operation: VON, VOFF, NONE
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-p8_pfet_ivrm_fsm_fix(const fapi::Target& i_target,
-                     uint8_t             i_ex_number,
-                     pfet_dom_t          i_domain,
-                     pfet_force_t        i_op)
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data(64);
-    uint64_t                    address;
-    uint32_t                    value;
-
-    ecmdDataBufferBase          gp3(64);
-
-    ecmdDataBufferBase          pmgp0(64);
-    const uint32_t              PM_DISABLE_BIT = 0;
-    const uint32_t              PFET_WORKAROUND_MARK_PMGP0_BIT = 47;
-
-    ecmdDataBufferBase          pcbspm_mode(64);
-    const uint32_t              TIMER_MODE_BIT = 7;
-
-    ecmdDataBufferBase          cpm_dpll_parm(64);
-    const uint32_t              DPLL_LOCK_TIMER_BIT = 15;
-    const uint32_t              DPLL_LOCK_TIMER_BITS = 9;
-
-    ecmdDataBufferBase          pmgp1(64);
-    const uint32_t              WINKLE_POWER_DN_EN_BIT = 3;
-    const uint32_t              WINKLE_POWER_OFF_SEL_BIT = 5;
-
-    ecmdDataBufferBase          ivrm_control_status(64);
-    const uint32_t              GOTO_WINKLE_BIT = 3;
-    const uint32_t              GOTO_WAKEUP_BIT = 4;
-    const uint32_t              BABYSTEPPER_WINKLE_TIMEOUT = 10;
-    const uint32_t              BABYSTEPPER_WAKEUP_TIMEOUT = 10;
-
-    ecmdDataBufferBase          core_voff_vret(64);
-    ecmdDataBufferBase          eco_voff_vret(64);
-
-
-
-
-    FAPI_INF("Beginning FET work-around for IVRM FSM");
-    do
-    {
-
-        // ---------------------------------------------------------------------
-
-        // Determine if Pstates have been previously enabled.  If so, the
-        // work-around was previously run and cannot be run again.
-        address = EX_PCBSPM_MODE_REG_0x100F0156 + 0x01000000*i_ex_number;
-
-        l_rc=fapiGetScom( i_target, address, pmgp0 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        if (gp3.isBitSet(0))
-        {
-            FAPI_INF("Skipping PFET work-around as Pstate have already been enabled");
-            break;
-        }
-
-        // Adding another layer of protection.
-        // Set PMGP0(47) [a spare bit in chips that have this bug]
-        // to indicated that this work-around has already been run
-        // to avoid contaminating the PState mechanism in the event
-        // that it was not first disabled.
-
-        address = EX_PMGP0_0x100F0100 + (0x01000000 * i_ex_number);
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        if (data.isBitSet(PFET_WORKAROUND_MARK_PMGP0_BIT))
-        {
-            FAPI_INF("Skipping PFET work-around as iVRM/FFET work-around has previously run on %s EX:%d",
-                            i_target.toEcmdString(),
-                            i_ex_number);
-            break;
-
-        }
-        else
-        {
-            e_rc |= data.flushTo0();
-            e_rc |= data.setBit(PFET_WORKAROUND_MARK_PMGP0_BIT);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            address = EX_PMGP0_OR_0x100F0102 + (0x01000000 * i_ex_number);
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-             FAPI_INF("Setting flag that PFET work-around cannot be run again on %s EX:%d",
-                            i_target.toEcmdString(),
-                            i_ex_number);
-            // This can set the PMGP0 snitch bit (PMErr(12)).  It is cleared,
-            // though, in p8_pfet_init.C (the caller)
-        }
-
-        address = EX_GP3_0x100F0012 + 0x01000000*i_ex_number;
-
-        // Save the setting for later restoration
-        l_rc=fapiGetScom( i_target, address, gp3 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        address = EX_PMGP0_0x100F0100 + 0x01000000*i_ex_number;
-
-        // Save the setting for possible setting later
-        l_rc=fapiGetScom( i_target, address, pmgp0 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-
-        if (gp3.isBitClear(0))
-        {
-            FAPI_INF("Set PMGP0 access mode, fence the PCB, raise PB electrical fence");
-            e_rc |= data.flushTo0();
-            e_rc |= data.setBit(20);
-            e_rc |= data.setBit(26);
-            e_rc |= data.setBit(27);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            // Set the bit
-            address = EX_GP3_OR_0x100F0014 + 0x01000000*i_ex_number;
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            // ----------------------
-            // Read back for debug
-            address = EX_GP3_0x100F0012 + 0x01000000*i_ex_number;
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-            FAPI_DBG("\tGP3 value: 0x%016llX", data.getDoubleWord(0));
-
-            // ----------------------
-            FAPI_INF("Set Slave Winkle fence");
-            e_rc |= data.flushTo0();
-            e_rc |= data.setBit(39);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            // Set the bit
-            address = EX_PMGP0_OR_0x100F0102 + 0x01000000*i_ex_number;
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            // ----------------------
-            // Read back for debug
-            address = EX_PMGP0_0x100F0100 + 0x01000000*i_ex_number;
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-            FAPI_DBG("\tPMGP0 value: 0x%016llX", data.getDoubleWord(0));
-
-            FAPI_INF("Temporarily enable the chiplet");
-            e_rc |= data.flushTo0();
-            e_rc |= data.setBit(0);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            // Set the bit
-            address = EX_GP3_OR_0x100F0014 + 0x01000000*i_ex_number;
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            // ----------------------
-            // Read back for debug
-            address = EX_GP3_OR_0x100F0014 + 0x01000000*i_ex_number;
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-            FAPI_DBG("\tGP3 value: 0x%016llX", data.getDoubleWord(0));
-
-            address = EX_PMGP0_0x100F0100 + 0x01000000*i_ex_number;
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-            FAPI_DBG("\tPMGP0 value: 0x%016llX", data.getDoubleWord(0));
-            // ----------------------
-        }
-
-        // ---------------------------------------------------------------------
-
-        if (pmgp0.isBitSet(PM_DISABLE_BIT))
-        {
-            FAPI_INF("Enabling Power Management as it is needed");
-            e_rc |= data.flushTo1();
-            e_rc |= data.clearBit(PM_DISABLE_BIT);
-            if (e_rc)
-            {
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            // Clear the bit
-            address = EX_PMGP0_AND_0x100F0101 + 0x01000000*i_ex_number;
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Set timer Mode");
-        address = EX_PCBSPM_MODE_REG_0x100F0156 + 0x01000000*i_ex_number;
-
-        // Save the setting
-        l_rc=fapiGetScom( i_target, address, pcbspm_mode );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        data = pcbspm_mode;
-        e_rc |= data.setBit(TIMER_MODE_BIT);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Clear dpll_lock_timer_replacement value to disable waiting");
-        address = EX_DPLL_CPM_PARM_REG_0x100F0152 + 0x01000000*i_ex_number;
-
-        // Save the setting
-        l_rc=fapiGetScom( i_target, address, cpm_dpll_parm );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        data = cpm_dpll_parm;
-        e_rc |= data.clearBit(DPLL_LOCK_TIMER_BIT, DPLL_LOCK_TIMER_BITS);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Set Local Pstate Table VID value to > 0");
-        // Set address to 0 to be sure
-        address = EX_PCBS_PSTATE_TABLE_CTRL_REG_0x100F015E + 0x01000000*i_ex_number;
-        e_rc |= data.flushTo0();
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        address = EX_PCBS_PSTATE_TABLE_REG_0x100F015F + 0x01000000*i_ex_number;
-        value = 1;
-        e_rc |= data.insertFromRight(&value, 0, 7);
-        e_rc |= data.insertFromRight(&value, 7, 7);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Writing Local Pstate Table Size");
-        address = EX_PCBS_Power_Management_Bounds_Reg_0x100F015D +
-                                0x01000000*i_ex_number;
-
-        uint32_t lpsi_min     = 0;
-        uint32_t lpsi_entries_minus_1 = 0;  // one entry
-        uint32_t lpsi_min_index = lpsi_min + 128;   // converted into index space
-
-
-        e_rc |= data.flushTo0();
-        e_rc |= data.insertFromRight(&lpsi_min_index, 0, 8);
-        e_rc |= data.insertFromRight(&lpsi_entries_minus_1, 8, 7);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Enable IVRM FSM and then PState mode");
-
-        // IVRM Enable
-        address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 +
-                                0x01000000*i_ex_number;
-
-
-        l_rc=fapiGetScom( i_target, address, ivrm_control_status );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        data = ivrm_control_status;
-        e_rc |= data.setBit(0);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Pstate mode
-        address = EX_PCBSPM_MODE_REG_0x100F0156 + 0x01000000*i_ex_number;
-
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        e_rc |= data.setBit(0);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // ---------------------------------------------------------------------
-        // Setup the appropriate off action when triggering  the babystepper to
-        // winkle entry (fast without off for configured chiplets; deep with
-        // power loss for deconfigured chiplets).
-
-        address = EX_CorePFVRET_REG_0x100F0130 + 0x01000000*i_ex_number;
-        l_rc=fapiGetScom( i_target, address, core_voff_vret );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        address = EX_ECOPFVRET_REG_0x100F0150 + 0x01000000*i_ex_number;
-        l_rc=fapiGetScom( i_target, address, eco_voff_vret );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        address = EX_PMGP1_0x100F0103 + 0x01000000*i_ex_number;
-        l_rc=fapiGetScom( i_target, address, pmgp1 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-
-        data = pmgp1;
-
-        if (i_op == VOFF)
-        {
-            FAPI_INF("Set winkle power off select to deep");
-            e_rc |= data.setBit(WINKLE_POWER_OFF_SEL_BIT);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-        }
-        else if (i_op == VON)
-        {
-            FAPI_INF("Set winkle power off select to fast with no power change");
-            e_rc |= data.clearBit(WINKLE_POWER_OFF_SEL_BIT);
-            e_rc |= data.clearBit(WINKLE_POWER_DN_EN_BIT);
-
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            // Don't let the power go off
-            e_rc |= data.flushTo0();
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-            address = EX_CorePFVRET_REG_0x100F0130 + 0x01000000*i_ex_number;
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-
-            address = EX_ECOPFVRET_REG_0x100F0150 + 0x01000000*i_ex_number;
-            l_rc=fapiPutScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llX", address);
-                break;
-            }
-        }
-        else
-        {
-            FAPI_ERR("Unsupported i_op to iVRM fix");
-            break;
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Trigger winkle to synchronize the iVRM babystepper");
-
-        address = EX_IDLEGOTO_0x100F0114 + 0x01000000*i_ex_number;
-
-        e_rc |= data.flushTo0();
-        e_rc |= data.setBit(GOTO_WINKLE_BIT);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        uint32_t i = 0;
-        do
-        {
-            FAPI_DBG("Poll for completion:  %d", i);
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-
-            if  (data.isBitClear(GOTO_WINKLE_BIT))
-            {
-                break;
-            }
-
-            l_rc = fapiDelay(10000, 1000);
-            if (l_rc)
-            {
-                FAPI_ERR("Error from fapiDelay");
-                break;
-            }
-
-            i++;
-
-        } while (data.isBitSet(GOTO_WINKLE_BIT) &&  i < BABYSTEPPER_WINKLE_TIMEOUT);
-
-        if (i >=  BABYSTEPPER_WINKLE_TIMEOUT)
-        {
-            // This is a workaround for early chip EC levels, just trace and do
-            // not return error
-            FAPI_ERR("\tBaby Stepper Timeout %d", i_ex_number);
-        }
-
-        // ---------------------------------------------------------------------
-        FAPI_INF("Trigger winkle wakeup to get get the FSM back to idle");
-        // IVRM Enable
-        address = EX_IDLEGOTO_0x100F0114 + 0x01000000*i_ex_number;
-
-        e_rc |= data.flushTo0();
-        e_rc |= data.setBit(GOTO_WAKEUP_BIT);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-        l_rc=fapiPutScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        i = 0;
-        do
-        {
-            l_rc=fapiGetScom( i_target, address, data );
-            if(!l_rc.ok())
-            {
-                FAPI_ERR("GetScom error 0x%08llX", address);
-                break;
-            }
-
-            if  (data.isBitClear(GOTO_WAKEUP_BIT))
-            {
-                break;
-            }
-
-            i++;
-
-            // No delay needed, hardware reacton should be nearly immediate and
-            // this is a workaround for early chip EC levels
-
-        } while (data.isBitSet(GOTO_WAKEUP_BIT) &&  i < BABYSTEPPER_WAKEUP_TIMEOUT);
-        if (i >=  BABYSTEPPER_WAKEUP_TIMEOUT)
-        {
-            // This is a workaround for early chip EC levels, just trace and do
-            // not return error
-            FAPI_ERR("\tBaby Stepper Timeout on Wakeup %d", i_ex_number);
-        }
-
-
-        // ----- Debug registers   -----
-        address = EX_PCBS_FSM_MONITOR1_REG_0x100F0170 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tPCBS Monitor1 for Core %d:  0x%16llX", i_ex_number, data.getDoubleWord(0));
-
-        address = EX_PCBS_FSM_MONITOR2_REG_0x100F0171 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiGetScom( i_target, address, data );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("GetScom error 0x%08llX", address);
-            break;
-        }
-        FAPI_DBG("\tPCBS Monitor2 for Core %d:  0x%16llX", i_ex_number, data.getDoubleWord(0));
-
-
-        // ----- Restore registers -----
-
-        // DPLL_CPM_PARM_REG
-        FAPI_DBG("Restore DPLL_CPM_PARM_REG:  0x%16llX", cpm_dpll_parm.getDoubleWord(0));
-
-        address = EX_DPLL_CPM_PARM_REG_0x100F0152 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, cpm_dpll_parm );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // Core OFF/VRET
-        FAPI_DBG("Restore Core OFF/VRET pointers:  0x%16llX", core_voff_vret.getDoubleWord(0));
-
-        address = EX_CorePFVRET_REG_0x100F0130 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, core_voff_vret );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // ECO OFF/VRET
-        FAPI_DBG("Restore ECO OFF/VRET pointers:  0x%16llX", eco_voff_vret.getDoubleWord(0));
-
-        address = EX_ECOPFVRET_REG_0x100F0150 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, eco_voff_vret );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // PM MODE
-        FAPI_DBG("Restore PM MODE:  0x%16llX", pcbspm_mode.getDoubleWord(0));
-
-        address = EX_PCBSPM_MODE_REG_0x100F0156 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, pcbspm_mode );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // iVRM_Control_Status
-        FAPI_DBG("Restore IVRM Control / Status:  0x%16llX", ivrm_control_status.getDoubleWord(0));
-
-        address = EX_PCBS_iVRM_Control_Status_Reg_0x100F0154 +
-                        0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, ivrm_control_status );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-        // PMGP1
-        FAPI_DBG("Restore PMGP1:  0x%16llX", pmgp1.getDoubleWord(0));
-
-        address = EX_PMGP1_0x100F0103 + 0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, pmgp1 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        // PMGP0
-        FAPI_DBG("Restore PMGP0:  0x%16llX", pmgp0.getDoubleWord(0));
-
-        address = EX_PMGP0_0x100F0100 + 0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, pmgp0 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-        //  GP3
-        FAPI_DBG("Restore GP3:  0x%16llX", gp3.getDoubleWord(0));
-
-        address = EX_GP3_0x100F0012 + 0x01000000*i_ex_number;
-
-        l_rc=fapiPutScom( i_target, address, gp3 );
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("PutScom error 0x%08llX", address);
-            break;
-        }
-
-   } while(0);
-
-   FAPI_INF("Completing PFET work-around for IVRM FSM");
-   return l_rc;
-}
-
-} //end extern
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.H
deleted file mode 100644
index 7698264fe..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.H
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_control.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pfet_control.H,v 1.5 2014/02/25 04:30:36 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_control.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_pfet_control.H
-// *! DESCRIPTION : General routines for controlling EX chiplet PFET headers
-// *!
-// *! OWNER NAME  : Ralf Maier    Email: ralf.maier@de.ibm.com
-// *! BACKUP NAME : Greg Still    Email: stillgs@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _P8_PFETCTL_H_
-#define _P8_PFETCTL_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "p8_pfet_types.H"
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_pfet_control_FP_t) (const fapi::Target&,
-                                                  uint8_t,
-                                                  pfet_dom_t,
-                                                  pfet_force_t);
-
-extern "C" {
-
-/// Controls the pfets for the specified EX chiplet
-///
-/// \param[in] i_target    Processor Chip target
-/// \param[in] i_ex_number EX number
-/// \param[in] i_domain    Domain: BOTH, ECO, CORE
-/// \param[in] i_op        Operation:
-///                          VON: Turns a chiplet domain on, VCS then VDD
-///                          VOFF: Turns a chiplet domain off, VDD then VCS
-//                           VOFF_OVERRIDE: Turns a chiplet domain off with
-///                                         controller override
-///
-/// \retval SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode p8_pfet_control(const fapi::Target& i_target,
-                                 uint8_t             i_ex_number,
-                                 pfet_dom_t          i_domain,
-                                 pfet_force_t        i_op);
-
-} // extern "C"
-
-#endif // _P8_PFETCTL_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C
deleted file mode 100644
index 9ca323e68..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C
+++ /dev/null
@@ -1,825 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pfet_init.C,v 1.15 2014/08/05 15:17:49 kahnevan Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_init.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
-// *!
-// *! Build cmd:  buildfapiprcd -e "../../xml/error_info/p8_pfet_init_errors.xml" p8_pfet_init.C
-// *!
-/// \file p8_pfet_init.C
-/// \brief Configure and initialize the EX PFET controllers based on
-///     attribute information and removes the override function.
-///
-/// High-level procedure flow:
-/// \verbatim
-///
-///     Check for valid parameters
-///     if PM_CONFIG {
-///         Nop (all the work is done in PM_INIT as this procedure is not run
-///         for the PM Reset path (eg, only done at IPL)
-///     else if PM_INIT {
-///         Get the delay setting held in platform attributes
-///         Convert these to hardware values
-///         for each EX chiplet {
-///             Store the Core VDD delay and VRET/VOFF values
-///             Store the Core VCS delay and VRET/VOFF values
-///             Store the ECO VDD delay and VRET/VOFF values
-///             Store the ECO VCS delay and VRET/VOFF values
-///         }
-///     } else if PM_RESET {
-///         for each EX chiplet {
-///             Restore the Core VDD delay and VRET/VOFF values
-///             Restore the Core VCS delay and VRET/VOFF values
-///             Restore the ECO VDD delay and VRET/VOFF values
-///             Restore the ECO VCS delay and VRET/VOFF values
-///     }
-///
-///  Procedure Prereq:
-///     - System clocks are running
-/// \endverbatim
-///
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-#include "p8_pm.H"
-#include "p8_pm_utils.H"
-#include "p8_pfet_init.H"
-#include "p8_pfet_control.H"
-
-//#ifdef FAPIECMD
-extern "C" {
-//#endif
-
-
-using namespace fapi;
-
-// ----------------------------------------------------------------------
-// Constant definitions
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Global variables
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Function prototypes
-// ----------------------------------------------------------------------
-
-fapi::ReturnCode pfet_init(const Target& i_target, uint32_t i_mode);
-fapi::ReturnCode pfet_config(const Target& i_target);
-fapi::ReturnCode pfet_set_delay( const fapi::Target& i_target,
-                                 const uint64_t      i_address,
-                                 const uint8_t       i_delay0,
-                                 const uint8_t       i_delay1,
-                                 const uint32_t      i_select);
-uint8_t convert_delay_to_value ( uint32_t   i_delay,
-                                 uint32_t   i_attr_proc_nest_frequency);
-
-// ----------------------------------------------------------------------
-// Function definitions
-// ----------------------------------------------------------------------
-
-
-/// \param[in] i_target EX target
-/// \param[in] i_mode   Control mode for the procedure
-///                     (PM_CONFIG, PM_INIT, PM_RESET,
-///                      PM_OVERRIDE)
-///
-/// \retval FAPI_RC_SUCCESS
-/// \retval ERROR defined in xml
-
-fapi::ReturnCode
-p8_pfet_init(const Target& i_target, uint32_t i_mode)
-{
-    fapi::ReturnCode      l_rc;
-
-    FAPI_INF("Executing p8_pfet_init in mode %x ....", i_mode);
-
-    /// -------------------------------
-    /// Configuration:  perform translation of any Platform Attributes
-    /// into Feature Attributes that are applied during Initalization
-    if (i_mode == PM_CONFIG)
-    {
-        FAPI_INF("PFET config...");
-        FAPI_INF("---> None is defined...");
-    }
-
-    /// -------------------------------
-    /// Initialization:  perform order or dynamic operations to initialize
-    /// the SLW using necessary Platform or Feature attributes.
-    else if (i_mode == PM_INIT || i_mode == PM_INIT_SPECIAL)
-    {
-        FAPI_INF("PFET init...");
-        l_rc = pfet_init(i_target, i_mode);
-    }
-
-    /// -------------------------------
-    /// Reset:  perform reset of PFETs so that it can reconfigured and
-    /// reinitialized
-    else if (i_mode == PM_RESET)
-    {
-        FAPI_INF("PFET reset...");
-        FAPI_INF("---> None is defined...");
-    }
-
-    /// -------------------------------
-    /// Unsupported Mode
-    else
-    {
-
-        FAPI_ERR("Unknown mode passed to p8_pfet_init. Mode %x ....", i_mode);
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_CODE_BAD_MODE);
-
-    }
-
-    return l_rc;
-}
-
-//------------------------------------------------------------------------------
-// PFET Configuration Function
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-pfet_init(const Target& i_target, uint32_t i_mode)
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data(64);
-
-    std::vector<fapi::Target>   l_exChiplets;
-    uint8_t                     l_functional = 0;
-    uint8_t                     l_ex_number = 0;
-
-    uint64_t                    address;
-
-    uint8_t                     core_vret_voff_value;
-    uint8_t                     eco_vret_voff_value;
-
-    pfet_force_t                off_mode;
-    
-    // detect PCBS Error Reset capaiblity
-    uint8_t                     chipHasPcbsErrReset = 0;
-
-    uint32_t                    attr_proc_refclk_frequency;
-
-    uint32_t                    attr_pm_pfet_powerup_core_delay0;
-    uint32_t                    attr_pm_pfet_powerup_core_delay1;
-    uint32_t                    attr_pm_pfet_powerdown_core_delay0;
-    uint32_t                    attr_pm_pfet_powerdown_core_delay1;
-    uint32_t                    attr_pm_pfet_powerup_eco_delay0;
-    uint32_t                    attr_pm_pfet_powerup_eco_delay1;
-    uint32_t                    attr_pm_pfet_powerdown_eco_delay0;
-    uint32_t                    attr_pm_pfet_powerdown_eco_delay1;
-
-    uint8_t                     attr_pm_pfet_powerup_core_delay0_value;
-    uint8_t                     attr_pm_pfet_powerup_core_delay1_value;
-    uint32_t                    attr_pm_pfet_powerup_core_sequence_delay_select;
-    uint8_t                     attr_pm_pfet_powerdown_core_delay0_value;
-    uint8_t                     attr_pm_pfet_powerdown_core_delay1_value;
-    uint32_t                    attr_pm_pfet_powerdown_core_sequence_delay_select;
-    uint8_t                     attr_pm_pfet_powerup_eco_delay0_value;
-    uint8_t                     attr_pm_pfet_powerup_eco_delay1_value;
-    uint32_t                    attr_pm_pfet_powerup_eco_sequence_delay_select;
-    uint8_t                     attr_pm_pfet_powerdown_eco_delay0_value;
-    uint8_t                     attr_pm_pfet_powerdown_eco_delay1_value;
-    uint32_t                    attr_pm_pfet_powerdown_eco_sequence_delay_select;
-
-    /// PFET Sequencing Delays
-    ///      convert_pfet_delays() - Convert the following delays from platform
-    ///         attributes (binary in nano/ seconds) to PFET delay value feature
-    //          attributes.  The conversion uses ATTR_PROC_NEST_FREQUENCY.
-    ///       Input platform attributes
-    ///            ATTR_PM_PFET_POWERUP_CORE_DELAY0
-    ///            ATTR_PM_PFET_POWERUP_CORE_DELAY1
-    ///            ATTR_PM_PFET_POWERUP_ECO_DELAY0
-    ///            ATTR_PM_PFET_POWERUP_ECO_DELAY1
-    ///            ATTR_PM_PFET_POWERDOWN_CORE_DELAY0
-    ///            ATTR_PM_PFET_POWERDOWN_CORE_DELAY1
-    ///            ATTR_PM_PFET_POWERDOWN_ECO_DELAY0
-    ///            ATTR_PM_PFET_POWERDOWN_ECO_DELAY1
-    ///       Output feature attributes
-    ///            ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE
-    ///            ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE
-    ///            ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT
-    ///            ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE
-    ///            ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE
-    ///            ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT
-    ///            ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE
-    ///            ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE
-    ///            ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT
-    ///            ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE
-    ///            ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE
-    ///            ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT
-
-    do
-    {
-
-        FAPI_INF("Executing pfet_config...");
-
-        // VRET settings need to be "ON" as PFET VRET is not supported
-        // The iVRM hardware will tell the PFET controller to go 'OFF"
-        // in its support of Vret.  These values do not pertain in that
-        // case.
-        core_vret_voff_value = 0x00;
-        eco_vret_voff_value = 0x00;
-
-        //  ******************************************************************
-        //  Get Attributes for pFET Delay
-        //  ******************************************************************
-
-        // Hardcoded values (if needed)
-        //  attr_pm_pfet_powerup_core_delay0            = 100;
-        //  attr_pm_pfet_powerup_core_delay1            = 100;
-        //  attr_pm_pfet_powerdown_core_delay0          = 100;
-        //  attr_pm_pfet_powerdown_core_delay1          = 100;
-        //  attr_pm_pfet_powerup_eco_delay0             = 100;
-        //  attr_pm_pfet_powerup_eco_delay1             = 100;
-        //  attr_pm_pfet_powerdown_eco_delay0           = 100;
-        //  attr_pm_pfet_powerdown_eco_delay1           = 100;
-
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_FREQ_PROC_REFCLOCK,
-                                NULL,
-                                attr_proc_refclk_frequency);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_FREQ_PROC_REFCLOCK");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERUP_CORE_DELAY0,
-                                &i_target,
-                                attr_pm_pfet_powerup_core_delay0);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_CORE_DELAY0");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERUP_CORE_DELAY1,
-                                &i_target,
-                                attr_pm_pfet_powerup_core_delay1);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_CORE_DELAY1");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERDOWN_CORE_DELAY0,
-                                &i_target,
-                                attr_pm_pfet_powerdown_core_delay0);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_CORE_DELAY0");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERDOWN_CORE_DELAY1,
-                                &i_target,
-                                attr_pm_pfet_powerdown_core_delay1);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_CORE_DELAY1");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERUP_ECO_DELAY0,
-                                &i_target,
-                                attr_pm_pfet_powerup_eco_delay0);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_ECO_DELAY0");
-            break;
-        }
-
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERUP_ECO_DELAY1,
-                                &i_target,
-                                attr_pm_pfet_powerup_eco_delay1);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERUP_ECO_DELAY1");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERDOWN_ECO_DELAY0,
-                                &i_target,
-                                attr_pm_pfet_powerdown_eco_delay0);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_ECO_DELAY0");
-            break;
-        }
-
-        /// ----------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(   ATTR_PM_PFET_POWERDOWN_ECO_DELAY1,
-                                &i_target,
-                                attr_pm_pfet_powerdown_eco_delay1);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute ATTR_PM_PFET_POWERDOWN_ECO_DELAY1");
-            break;
-        }
-
-
-        //  ******************************************************************
-        //  Calculate Delay values out of pFET Delays
-        //  ******************************************************************
-        FAPI_DBG("*************************************");
-        FAPI_DBG("Calculates Delay values out of pFET Delays");
-        FAPI_DBG("*************************************");
-        FAPI_DBG("Calculate:");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_CORE_DELAY0_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_CORE_DELAY1_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_ECO_DELAY0_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_ECO_DELAY1_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_CORE_DELAY0_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_CORE_DELAY1_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_ECO_DELAY0_VALUE");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_ECO_DELAY1_VALUE");
-        FAPI_DBG("using:");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_CORE_DELAY0");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_CORE_DELAY1");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_ECO_DELAY0");
-        FAPI_DBG("        ATTR_PM_PFET_POWERUP_ECO_DELAY1");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_CORE_DELAY0");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_CORE_DELAY1");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_ECO_DELAY0");
-        FAPI_DBG("        ATTR_PM_PFET_POWERDOWN_ECO_DELAY1");
-        FAPI_DBG("**************************************************************************");
-        FAPI_DBG("        Set  ATTR_PM_PFET_POWERUP_CORE_SEQUENCE_DELAY_SELECT    to 0 (choosing always pfetdelay0 )");
-        FAPI_DBG("        Set  ATTR_PM_PFET_POWERDOWN_CORE_SEQUENCE_DELAY_SELECT  to 0 (choosing always pfetdelay0 )");
-        FAPI_DBG("        Set  ATTR_PM_PFET_POWERUP_ECO_SEQUENCE_DELAY_SELECT     to 0 (choosing always pfetdelay0 )");
-        FAPI_DBG("        Set  ATTR_PM_PFET_POWERDOWN_ECO_SEQUENCE_DELAY_SELECT   to 0 (choosing always pfetdelay0 )");
-        FAPI_DBG("**************************************************************************");
-
-        //value = 15 - log2(delay * refclk);
-        attr_pm_pfet_powerup_core_delay0_value          =
-                convert_delay_to_value( attr_pm_pfet_powerup_core_delay0,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerup_core_delay1_value          =
-                convert_delay_to_value( attr_pm_pfet_powerup_core_delay1,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerdown_core_delay0_value        =
-                convert_delay_to_value( attr_pm_pfet_powerdown_core_delay0 ,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerdown_core_delay1_value        =
-                convert_delay_to_value( attr_pm_pfet_powerdown_core_delay1 ,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerup_eco_delay0_value           =
-                convert_delay_to_value( attr_pm_pfet_powerup_eco_delay0 ,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerup_eco_delay1_value           =
-                convert_delay_to_value( attr_pm_pfet_powerup_eco_delay1 ,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerdown_eco_delay0_value         =
-                convert_delay_to_value( attr_pm_pfet_powerdown_eco_delay0 ,
-                                        attr_proc_refclk_frequency);
-
-        attr_pm_pfet_powerdown_eco_delay1_value         =
-                convert_delay_to_value( attr_pm_pfet_powerdown_eco_delay1 ,
-                                        attr_proc_refclk_frequency);
-
-        // Choosing always delay0
-        attr_pm_pfet_powerup_core_sequence_delay_select         = 0;
-        attr_pm_pfet_powerdown_core_sequence_delay_select       = 0;
-        attr_pm_pfet_powerup_eco_sequence_delay_select          = 0;
-        attr_pm_pfet_powerdown_eco_sequence_delay_select        = 0;
-
-        FAPI_DBG("*************************************");
-        FAPI_DBG("attr_pm_pfet_powerup_core_delay0_value           :  %X", attr_pm_pfet_powerup_core_delay0_value);
-        FAPI_DBG("attr_pm_pfet_powerup_core_delay1_value           :  %X", attr_pm_pfet_powerup_core_delay1_value);
-        FAPI_DBG("attr_pm_pfet_powerup_core_sequence_delay_select  :  %X", attr_pm_pfet_powerup_core_sequence_delay_select);
-        FAPI_DBG("attr_pm_pfet_powerdown_core_delay0_value         :  %X", attr_pm_pfet_powerdown_core_delay0_value);
-        FAPI_DBG("attr_pm_pfet_powerdown_core_delay1_value         :  %X", attr_pm_pfet_powerdown_core_delay1_value);
-        FAPI_DBG("attr_pm_pfet_powerdown_core_sequence_delay_select:  %X", attr_pm_pfet_powerdown_core_sequence_delay_select);
-        FAPI_DBG("attr_pm_pfet_powerup_eco_delay0_value            :  %X", attr_pm_pfet_powerup_eco_delay0_value);
-        FAPI_DBG("attr_pm_pfet_powerup_eco_delay1_value            :  %X", attr_pm_pfet_powerup_eco_delay1_value);
-        FAPI_DBG("attr_pm_pfet_powerup_eco_sequence_delay_select   :  %X", attr_pm_pfet_powerup_eco_sequence_delay_select);
-        FAPI_DBG("attr_pm_pfet_powerdown_eco_delay0_value          :  %X", attr_pm_pfet_powerdown_eco_delay0_value);
-        FAPI_DBG("attr_pm_pfet_powerdown_eco_delay1_value          :  %X", attr_pm_pfet_powerdown_eco_delay1_value);
-        FAPI_DBG("attr_pm_pfet_powerdown_eco_sequence_delay_select :  %X", attr_pm_pfet_powerdown_eco_sequence_delay_select);
-        FAPI_DBG("*************************************");
-
-        //  ******************************************************************
-        //  Install in the hardware
-        //      Loop through all the functional chiplets
-        //  ******************************************************************
-
-        l_rc = fapiGetChildChiplets(i_target,
-                                    TARGET_TYPE_EX_CHIPLET,
-                                    l_exChiplets,
-                                    TARGET_STATE_PRESENT);
-        if (l_rc)
-        {
-            FAPI_ERR("Error from fapiGetChildChiplets!");
-            break;
-        }
-
-        FAPI_DBG("\tNumber of EX chiplets present => %zu", l_exChiplets.size());
-
-        // Iterate through the returned chiplets
-        for (uint8_t j=0; j < l_exChiplets.size(); j++)
-        {
-            // Determine if it's functional
-            l_rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &l_exChiplets[j], l_functional);
-            if (l_rc)
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_FUNCTIONAL error");
-                break;
-            }
-
-            // Get the core number
-            l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_exChiplets[j], l_ex_number);
-            if (l_rc)
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS error");
-                break;
-            }
-
-
-            FAPI_INF("Set PFET attribute values into EX %X", l_ex_number);
-
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting Core Power up Delays");
-            address = EX_CorePFPUDly_REG_0x100F012C + (0x01000000 * l_ex_number);
-            l_rc=pfet_set_delay(i_target,
-                                address,
-                                attr_pm_pfet_powerup_core_delay0_value,
-                                attr_pm_pfet_powerup_core_delay1_value,
-                                attr_pm_pfet_powerup_core_sequence_delay_select
-                               );
-            if (l_rc)
-            {
-                FAPI_ERR("pfet_set_delay error 0x%08llu", address);
-                break;
-            }
-
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting Core Power down Delays");
-            address = EX_CorePFPDDly_REG_0x100F012D + (0x01000000 * l_ex_number);
-            l_rc=pfet_set_delay(i_target,
-                                address,
-                                attr_pm_pfet_powerup_core_delay0_value,
-                                attr_pm_pfet_powerup_core_delay1_value,
-                                attr_pm_pfet_powerup_core_sequence_delay_select
-                               );
-            if (l_rc)
-            {
-                FAPI_ERR("pfet_set_delay error 0x%08llu", address);
-                break;
-            }
-
-
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting Core Voff Settings");
-            e_rc |= data.setBitLength(64);
-            e_rc |= data.insertFromRight(core_vret_voff_value, 0, 8);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            address = EX_CorePFVRET_REG_0x100F0130 + (0x01000000 * l_ex_number);
-            l_rc=fapiPutScom(i_target, address, data );
-            if (l_rc)
-            {
-                FAPI_ERR("PutScom error 0x%08llu", address);
-                break;
-            }
-
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting ECO Power up Delays");
-            address = EX_ECOPFPUDly_REG_0x100F014C + (0x01000000 * l_ex_number);
-            l_rc=pfet_set_delay(i_target,
-                                address,
-                                attr_pm_pfet_powerup_eco_delay0_value,
-                                attr_pm_pfet_powerup_eco_delay1_value,
-                                attr_pm_pfet_powerup_eco_sequence_delay_select
-                               );
-            if (l_rc)
-            {
-                FAPI_ERR("pfet_set_delay error 0x%08llu", address);
-                break;
-            }
-
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting ECO Power down Delays");
-            address = EX_ECOPFPDDly_REG_0x100F014D + (0x01000000 * l_ex_number);
-            l_rc=pfet_set_delay(i_target,
-                                address,
-                                attr_pm_pfet_powerdown_eco_delay0_value,
-                                attr_pm_pfet_powerdown_eco_delay1_value,
-                                attr_pm_pfet_powerdown_eco_sequence_delay_select
-                               );
-            if (l_rc)
-            {
-                FAPI_ERR("pfet_set_delay error 0x%08llu", address);
-                break;
-            }
-
-
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting ECO Voff Settings");
-            e_rc |= data.setBitLength(64);
-            e_rc |= data.insertFromRight(eco_vret_voff_value, 0, 8);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                l_rc.setEcmdError(e_rc);
-                break;
-            }
-
-            address = EX_ECOPFVRET_REG_0x100F0150 + (0x01000000 * l_ex_number);
-            l_rc=fapiPutScom(i_target, address, data );
-            if (l_rc)
-            {
-                FAPI_ERR("PutScom error 0x%08llu", address);
-                break;
-            }
-
-            // Make a note of PMGP0-invalid-write-snitch bit PMErr_REG(12).
-            address = EX_PMErr_REG_0x100F0109 + (l_ex_number * 0x01000000);
-            l_rc=fapiGetScom(i_target, address, data);
-            if (l_rc)
-            {
-                FAPI_ERR("GetScom error 0x%08llu", address);
-                break;
-            }
-            FAPI_DBG("PMErr_REG (before calling p8_pfet_control): 0x%016llx",data.getDoubleWord(0));
-            
-            // Functional - run any work-arounds necessary
-            if (l_functional)
-            {
-                l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
-                                "before p8_pfet_control functional");
-                if (!l_rc.ok()) { break; }
-            
-                // \todo:  make DD1 relevent
-                FAPI_INF("Perform iVRM work-around on configured EX %d", l_ex_number);
-
-                FAPI_EXEC_HWP(l_rc, p8_pfet_control,    i_target,
-                                                        l_ex_number,
-                                                           BOTH,
-                                                          VON);
-                if(l_rc)
-                {
-                    FAPI_ERR("iVRM / PFET Controller error");
-                    break;
-                }
-                
-                l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
-                                "after p8_pfet_control functional");
-                if (!l_rc.ok()) { break; }
-
-            }
-            // Not Functional - disable the PFETs
-            // Only done on hardware as this can cause sim issue for unpopulated
-            // chiplest
-            uint8_t is_sim;
-
-            l_rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-            if (l_rc)
-            {
-                FAPI_ERR("fapi_attr_get(ATTR_IS_SIMULATION ) failed. "
-                 "With rc = 0x%x", (uint32_t) l_rc );
-                break;
-            }
-            if(!is_sim)
-            {
-                if (!l_functional )
-                {
-                
-                    l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
-                                "before p8_pfet_control non-functional");
-                    if (!l_rc.ok()) { break; }
-                
-                    FAPI_INF("Turn off PFETs on EX %d", l_ex_number);
-                    off_mode = VOFF;
-                    if (i_mode == PM_INIT_SPECIAL)
-                    {
-                        FAPI_INF("\tUsing PFET override mode");
-                        off_mode = VOFF_OVERRIDE;
-                    }
-
-                   FAPI_EXEC_HWP(l_rc, p8_pfet_control,    i_target,
-                       l_ex_number,
-                       BOTH,
-                       off_mode);
-
-                    if(l_rc)
-                    {
-                        FAPI_ERR("PFET Controller error");
-                        break;
-                    }
-                    
-                    l_rc = p8_pm_pcbs_fsm_trace (i_target, l_ex_number, 
-                                "after p8_pfet_control non-functional");
-                    if (!l_rc.ok()) { break; }
-                }
-            }
-            else
-            {
-                FAPI_INF("Simulation detected: Not disabling PFETs in deconfigured chiplets");
-            }
-            
-            // Make a note of PMGP0-invalid-write-snitch bit PMErr_REG(12).
-            // And, if bit12 set, clear all of PMErr_REG.
-            // Note, even though we attempt below to only clear the PMErr_REG(12) bit,
-            // the mere write action to PMErr_REG will cause the whole register to clear.
-            
-            l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET,
-                                &i_target,
-                                chipHasPcbsErrReset);
-            if(l_rc)
-            {
-     		    FAPI_ERR("Error querying Chip EC feature: "
-                         "ATTR_CHIP_EC_FEATURE_PCBS_ERR_RESET");
-                break;
-            }
-                        
-            address = EX_PMErr_REG_0x100F0109 + (l_ex_number * 0x01000000);
-            l_rc=fapiGetScom(i_target, address, data);
-            if (l_rc)
-            {
-                FAPI_ERR("GetScom error 0x%08llu", address);
-                break;
-            }
-            FAPI_DBG("PMErr_REG (after returning from p8_pfet_control): 0x%016llx",data.getDoubleWord(0));
-            if (data.getBit(12))
-            {
-                e_rc |= data.clearBit(12);
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                    l_rc.setEcmdError(e_rc);
-                    break;
-                }
-                
-                FAPI_INF("PCBS Error Reset is %s being performed",
-                         (chipHasPcbsErrReset ? "" : "NOT"));      
-
-                if (chipHasPcbsErrReset)
-                {                         
-                    l_rc = fapiPutScom(i_target, address, data);
-                    if (l_rc)
-                    {
-                        FAPI_ERR("PutScom error 0x%08llu", address);
-                        break;
-                    }
-                    l_rc=fapiGetScom(i_target, address, data);
-                    if (l_rc)
-                    {
-                        FAPI_ERR("GetScom error 0x%08llu", address);
-                        break;
-                    }
-                    FAPI_DBG("PMErr_REG (after clearing it): 0x%016llx",data.getDoubleWord(0));
-                }
-            }
-
-        } // chiplet loop
-
-    } while(0);
-
-    return l_rc;
-}
-
-
-
-//------------------------------------------------------------------------------
-// pfet_set_delay
-//  Helper function to set delay registers
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-pfet_set_delay( const fapi::Target& i_target,
-                const uint64_t      i_address,
-                const uint8_t       i_delay0,
-                const uint8_t       i_delay1,
-                const uint32_t      i_select)
-{
-    fapi::ReturnCode            l_rc;
-    uint32_t                    e_rc = 0;
-    ecmdDataBufferBase          data;
-
-    do
-    {
-
-        e_rc |= data.setBitLength(64);
-        e_rc |= data.insertFromRight(i_delay0, 0, 4);   // bits 0:3
-        e_rc |= data.insertFromRight(i_delay1, 4, 4);   // bits 4:7
-        e_rc |= data.insertFromRight(i_select, 8, 12);  // bits 8:19
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-            l_rc.setEcmdError(e_rc);
-            break;
-        }
-
-        l_rc=fapiPutScom(i_target, i_address, data );
-        if (l_rc)
-        {
-            FAPI_ERR("PutScom error 0x%08llu", i_address);
-            break;
-        }
-
-    } while(0);
-    return l_rc;
-}
-
-
-//------------------------------------------------------------------------------
-// convert_delay_to_value
-//  Helper function to convert time values (binary in ns)to hardware delays
-//------------------------------------------------------------------------------
-uint8_t
-convert_delay_to_value (uint32_t i_delay,
-                        uint32_t i_attr_proc_nest_frequency)
-{
-    uint8_t   pfet_delay_value;
-    float     dly;
-    //  attr_proc_nest_frequency [MHz]
-    //  delay [ns]
-    //  pfet_delay_value = 15 - log2( i_delay * i_attr_proc_nest_frequency/1000);
-    //  since log2 function is not available, this is done manual
-    //  pfet_delay_value = 15 - log2( dly );
-    dly = ( i_delay * i_attr_proc_nest_frequency/1000);
-
-    if                          ( dly <= 1.4 )    {pfet_delay_value = 15 - 0 ;}
-    else if (( 1.4   < dly ) && ( dly <= 2.8 )  ) {pfet_delay_value = 15 - 1 ;}
-    else if (( 2.8   < dly ) && ( dly <= 5.6 )  ) {pfet_delay_value = 15 - 2 ;}
-    else if (( 5.6   < dly ) && ( dly <= 11.5 ) ) {pfet_delay_value = 15 - 3 ;}
-    else if (( 11.5  < dly ) && ( dly <= 23 )   ) {pfet_delay_value = 15 - 4 ;}
-    else if (( 23    < dly ) && ( dly <= 46 )   ) {pfet_delay_value = 15 - 5 ;}
-    else if (( 46    < dly ) && ( dly <= 92 )   ) {pfet_delay_value = 15 - 6 ;}
-    else if (( 92    < dly ) && ( dly <= 182 )  ) {pfet_delay_value = 15 - 7 ;}
-    else if (( 182   < dly ) && ( dly <= 364 )  ) {pfet_delay_value = 15 - 8 ;}
-    else if (( 364   < dly ) && ( dly <= 728 )  ) {pfet_delay_value = 15 - 9 ;}
-    else if (( 728   < dly ) && ( dly <= 1456 ) ) {pfet_delay_value = 15 - 10;}
-    else if (( 1456  < dly ) && ( dly <= 2912 ) ) {pfet_delay_value = 15 - 11;}
-    else if (( 2912  < dly ) && ( dly <= 5824 ) ) {pfet_delay_value = 15 - 12;}
-    else if (( 5824  < dly ) && ( dly <= 11648 )) {pfet_delay_value = 15 - 13;}
-    else if (( 11648 < dly ) && ( dly <= 23296 )) {pfet_delay_value = 15 - 14;}
-    else if  ( 23296 < dly )                      {pfet_delay_value = 15 - 15;}
-    else                                          {pfet_delay_value = 15 - 15;}
-
-    return (pfet_delay_value);
-}
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-
-
-*/
-
-
-
-} //end extern
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.H
deleted file mode 100644
index 92b098920..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.H
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pfet_init.H,v 1.2 2013/08/02 19:06:05 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_init.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_pfet_init.H
-// *! DESCRIPTION : Initialization and reset the EX chiplet PFET controller
-// *!
-// *! OWNER NAME  : Ralf Maier    Email: ralf.maier@de.ibm.com
-// *! BACKUP NAME : Greg Still    Email: stillgs@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _P8_PFET_INIT_H_
-#define _P8_PFET_INIT_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_pfet_init_FP_t) (const fapi::Target&, uint32_t);
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Parameter structure definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-/// \param[in] i_target  Chip target
-/// \param[in] mode      Control mode (PM_CONFIG, PM_INIT, PM_RESET)
-
-/// \retval FAPI_RC_SUCCESS if something good happens,
-/// \retval RC per p8_pfet_init_errors.xml otherwise
-fapi::ReturnCode 
-p8_pfet_init(const fapi::Target& i_target, uint32_t i_mode);
-
-} // extern "C"
-
-#endif // _P8_PFET_INIT_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_types.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_types.H
deleted file mode 100644
index c7ca82f30..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_types.H
+++ /dev/null
@@ -1,80 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_types.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pfet_types.H,v 1.3 2013/05/17 20:15:44 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pfet_types.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_pfet_types.H
-// *! DESCRIPTION : General routines for controlling EX chiplet PFET headers
-// *!
-// *! OWNER NAME  : Ralf Maier    Email: ralf.maier@de.ibm.com
-// *! BACKUP NAME : Greg Still    Email: stillgs@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _P8_PFETTYPE_H_
-#define _P8_PFETTYPE_H_
-
-
-extern "C" {
-
-// valid domain options
-typedef enum  pfet_dom_type
-{
-  BOTH,         // write to both domains
-  ECO,          // eco only
-  CORE,         // core only
-} pfet_dom_t;
-
-
-// valid force options
-typedef enum  pfet_force_type
-{
-  NONE,          // no operation (00)
-  VOFF,          // voff (01)
-  VRET,          // Vret (10)... not supported
-  VON,           // von (11)
-  NO_FORCE_PARM, // use this when not writing to reg.
-  VOFF_OVERRIDE
-} pfet_force_t;
-
-// valid read options
-typedef enum  pfet_read_type
-{
-  PFET_READ_VOFF,
-  PFET_READ_VREG,
-  PFET_READ_VON,
-  PFET_READ_VBETWEEN,
-  PFET_READ_VOFFOVRD
-} pfet_read_t;
-
-
-} // extern "C"
-
-#endif // _P8_PFETTYPE_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H
deleted file mode 100644
index d97d757a7..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H
+++ /dev/null
@@ -1,176 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pm.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pm.H,v 1.9 2013/10/30 17:13:12 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pm.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_pm.H
-// *! DESCRIPTION : Common header for Power Manangement procedures
-// *!
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Jim Yacynych  Email: jimyac@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _P8_PM_H_
-#define _P8_PM_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-#include "p8_scom_addresses.H"
-
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-#ifndef _P8_PM_FLOW_MODE
-#define _P8_PM_FLOW_MODE
-enum p8_PM_FLOW_MODE 
-{
-    PM_CONFIG       = 0x1,
-    PM_RESET        = 0x2,
-    PM_INIT         = 0x3,
-    PM_SETUP        = 0x4,
-    PM_SETUP_PIB    = 0x5,
-    PM_SETUP_ALL    = 0x6,
-    PM_RESET_SOFT   = 0x7,
-    PM_CONFIG_SOFT  = PM_CONFIG,
-    PM_INIT_SOFT    = 0x8,
-    PM_INIT_SPECIAL = 0x9,
-    PM_INIT_PMC     = 0xA
-};
-        
-// This storage is contained in p8_pm_utils.C which must be included
-// in the compilation of all procs that use the PM_MODE_NAME macro     
-extern const char * p8_PM_FLOW_MODE_NAME[]; 
-
-#define PM_FLOW_MODE_NAME   \
-{                           \
-    "PM_CONFIG",            \
-    "PM_RESET",             \
-    "PM_INIT",              \
-    "PM_SETUP",             \
-    "PM_SETUP_PIB",         \
-    "PM_SETUP_ALL",         \
-    "PM_RESET_SOFT",        \
-    "PM_INIT_SOFT",         \
-    "PM_INIT_SPECIAL",      \
-    "PM_INIT_PMC",          \
-    "PM_CONFIG_SOFT"        \
-}
-
-// Necessary definition to allocated enum string array storage.
-// Typical declaration:  
-// const char *        PM_MODE_NAME_VAR; // Defines storage for PM_MODE_NAME
-#define PM_MODE_NAME_VAR p8_PM_FLOW_MODE_NAME[] = PM_FLOW_MODE_NAME
-
-#define PM_MODE_NAME(_mi_mode)(         \
-    p8_PM_FLOW_MODE_NAME[_mi_mode-1]    \
-)
-       
-#endif  // _P8_PM_FLOW_MODE
-
-
-// Macros to enhance readability yet provide for error handling
-// Assume the error path is to break out of the current loop.  If nested loops
-// are employed, the error_flag can be used to break out of the necessary
-// levels.
-#define PUTSCOM(_mi_rc, _mi_target, _mi_address, _mi_buffer){		    \
-    _mi_rc = fapiPutScom(_mi_target, _mi_address, _mi_buffer);          \
-    if(!_mi_rc.ok())                                                    \
-    {                                                                   \
-        FAPI_ERR("PutScom error to address 0x%08llx", _mi_address);     \
-        break;                                                          \
-    }                                                                   \
-}
-
-#define GETSCOM(_mi_rc, _mi_target, _mi_address, _mi_buffer){		    \
-    _mi_rc = fapiGetScom(_mi_target, _mi_address, _mi_buffer);          \
-    if(!_mi_rc.ok())                                                    \
-    {                                                                   \
-        FAPI_ERR("GetScom error to address 0x%08llx", _mi_address);     \
-        break;                                                          \
-    }                                                                   \
-}
-
-#define E_RC_CHECK(_mi_e_rc, _mi_l_rc){                                 \
-    if (_mi_e_rc)                                                       \
-    {                                                                   \
-        FAPI_ERR("Error (0x%x) accessing ecmdDataBufferBase", _mi_e_rc);\
-        _mi_l_rc.setEcmdError(_mi_e_rc);                                \
-        break;                                                          \
-    }                                                                   \
-}
-
-#define GETATTR_DEFAULT(_mi_rc, _mi_attr, _mi_attr_name, _mi_target, _mi_value, _mi_default){\
-        _mi_rc = FAPI_ATTR_GET(_mi_attr, _mi_target, _mi_value); \
-        if (_mi_rc) \
-        { \
-            FAPI_ERR("fapiGetAttribute of %s with rc = 0x%x", _mi_attr_name, (uint32_t)_mi_rc); \
-            break; \
-        } \
-        FAPI_INF (" value read from attribute %s = 0x%x",  _mi_attr_name,  _mi_value ); \
-        if (!_mi_value) \
-        { \
-            FAPI_DBG(" setting value of read attribute %s to default = 0x%x",  _mi_attr_name,  _mi_default ); \
-             _mi_value = _mi_default;\
-        } \
-}
-
-#define GETATTR(_mi_rc, _mi_attr, _mi_attr_name, _mi_target, _mi_value){\
-        _mi_rc = FAPI_ATTR_GET(_mi_attr, _mi_target, _mi_value); \
-        if (_mi_rc) \
-        { \
-             FAPI_ERR("fapiGetAttribute of %s with rc = 0x%x",  _mi_attr_name, (uint32_t)rc); \
-            break; \
-        } \
-        FAPI_INF (" value read from attribute %s = 0x%x", _mi_attr_name, _mi_value ); \
-}
-
-#define SETATTR(_mi_rc, _mi_attr, _mi_attr_name, _mi_target, _mi_value){\
-        _mi_rc = FAPI_ATTR_SET(_mi_attr, _mi_target, _mi_value); \
-        if (_mi_rc) \
-        { \
-            FAPI_ERR("fapiSetAttribute of %s with rc = 0x%x",  _mi_attr_name, (uint32_t)_mi_rc); \
-            break; \
-        } \
-        FAPI_INF (" value written to attribute %s = 0x%x",  _mi_attr_name,  _mi_value ); \
-}
-
-} // extern "C"
-
-#endif // _P8_PM_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C
deleted file mode 100755
index 0b753db89..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C
+++ /dev/null
@@ -1,187 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pmc_deconfig_setup.C,v 1.11 2014/08/05 15:18:24 kahnevan Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_deconfig_setup.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
-// *!
-/// \file p8_pmc_deconfig_setup.C
-/// \brief Setup PMC Deconfig based on EX chiplet enable bit (GP0(0))
-///
-///
-/// High-level procedure flow:
-/// \verbatim
-///
-///     Loop over Functional EX chiplets
-///     {
-///         Read GP0(0)
-///         if ( clear )  // disabled
-///         {
-///             Set the respective core bit in PMC_CORE_DECONFIGURATION_REG
-///             // Cores are held in 0:15
-///         }
-///     }
-///
-///  Procedure Prereq:
-///     - System clocks are running
-/// \endverbatim
-///
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-#include "p8_pmc_deconfig_setup.H"
-
-extern "C" {
-
-using namespace fapi;
-
-//------------------------------------------------------------------------------
-/**
- * p8_pmc_deconfig_setup -  Set PMC Deconfig register based on chiplet GP3(0)
- *
- * @param[in] i_target Chip target
- *
- *
- * @retval FAPI_RC_SUCCESS
- * @retval ERROR defined in xml
- */
-ReturnCode
-p8_pmc_deconfig_setup(const Target& i_target)
-{
-
-    fapi::ReturnCode                rc;
-    uint32_t                        e_rc = 0;
-    uint64_t                        address = 0;
-    ecmdDataBufferBase              data(64);
-    ecmdDataBufferBase              config_data(64);
-    std::vector<fapi::Target>       l_exChiplets;
-    uint8_t                         l_ex_number = 0;
-
-    
-    do
-    {
-        FAPI_INF("Executing p8_pmc_deconfig_setup on target %s...", i_target.toEcmdString());
-
-        rc = fapiGetChildChiplets ( i_target, 
-                                    TARGET_TYPE_EX_CHIPLET, 
-                                    l_exChiplets, 
-                                    TARGET_STATE_FUNCTIONAL);
-        if (rc)
-        {   
-            FAPI_ERR("Error from fapiGetChildChiplets!");
-            break;
-        }
-
-        FAPI_DBG("\tChiplet vector size  => %zu ", l_exChiplets.size());
-
-        // Set the buffer to assume that all chiplets are deconfigured.  Validly configured
-        // chiplets will then turn off this deconfiguration.
-        FAPI_INF("\tAssuming all cores are non-functional");
-        e_rc |= config_data.flushTo0();
-        e_rc |= config_data.setBit(0, 16);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) flushing ecmdDataBufferBase", e_rc);
-            rc.setEcmdError(e_rc);
-            return rc;
-        }
-
-        // Iterate through the returned chiplets
-        for (uint8_t j=0; j < l_exChiplets.size(); j++)
-        {
-                 
-            // Get the core number
-            rc = FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS, 
-                                &l_exChiplets[j], 
-                                l_ex_number);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS error");
-                break;
-            }
-
-            FAPI_INF(" Working on ex chiplet number %d", l_ex_number);
-            
-            address = EX_GP3_0x100F0012 + (l_ex_number * 0x01000000);
-            rc=fapiGetScom(i_target, address, data);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom address 0x%08llX failed. rc = 0x%x", 
-                            address,
-                            (uint32_t)rc);
-                break;
-            }
-
-            FAPI_DBG("\tGP0(0) from core %x (@ %08llx) => 0x%16llx",
-                            l_ex_number,
-                            address,
-                            data.getDoubleWord(0));
-
-            // Check if chiplet enable bit is set (configured);  If so,
-            // clear the chiplet bit in PMC Core Deconfig Register (0:15)
-            // indexed by ex number
-            if ( data.isBitSet(0) )
-            {
-                FAPI_INF("\tSetting Core %X as functional", l_ex_number);
-                e_rc |= config_data.clearBit(l_ex_number);
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting bit in ecmdDataBufferBase", e_rc);
-                    rc.setEcmdError(e_rc);
-                    break;
-                }
-            }                            
-        }
-        
-        address = PMC_CORE_DECONFIG_REG_0x0006200D;
-        rc = fapiPutScom(i_target, address , config_data);
-        if(rc)
-        {
-            FAPI_ERR("fapiPutScom address 0x%08llX failed. rc = 0x%x", 
-                        address, 
-                        (uint32_t)rc);
-            break;
-        }
-        
-        FAPI_INF("\tWriting PMC Core Deconfig Register with 0x%16llx", 
-                        config_data.getDoubleWord(0));      
-           
-    } while (0);
-    
-    return rc;
-}
-
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.H
deleted file mode 100644
index 09f1ee1be..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.H
+++ /dev/null
@@ -1,77 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pmc_deconfig_setup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pmc_deconfig_setup.H,v 1.1 2012/09/19 11:43:46 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_pmc_deconfig_setup.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *| \file p8_pmc_deconfig_setup.C
-// *| \brief Setup PMC Deconfig based on EX chiplet enable bit (GP0(0))
-// *!
-// *! OWNER NAME  : Greg Still      Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Pradeep CN      Email: pradeepcn@in.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_PMCDECONFIG_H_
-#define _PROC_PMCDECONFIG_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_pmc_deconfig_setup_FP_t) (const fapi::Target&);
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Parameter structure definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-/// \param[in] i_target Chip target
-
-/// \retval ECMD_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode 
-p8_pmc_deconfig_setup(const fapi::Target& i_target);
-
-
-} // extern "C"
-
-#endif // _PROC_PMCDECONFIG_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C
deleted file mode 100644
index 47df1b219..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C
+++ /dev/null
@@ -1,888 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_poreslw_init.C,v 1.27 2014/08/05 15:17:12 kahnevan Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poreslw_init.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
-// *! BACKUP:     Mike Olsen         Email: cmolsen@us.ibm.com
-// *!
-// *! Build cmd:  buildfapiprcd -e "../../xml/error_info/p8_poreslw_errors.xml,../../xml/error_info/p8_slw_registers.xml" -C p8_pm_utils.C p8_poreslw_init.C
-// *!
-/// \file p8_poreslw_init.C
-/// \brief Configure or reset the SLW PORE and related functions to enable idle
-///         operations
-///
-/// High-level procedure flow:
-/// \verbatim
-///
-///     Check for valid parameters
-///     if PM_CONFIG {
-///         None (see p8_set_pore_bars.C)
-///     else if PM_INIT {
-///         Synchronize the PMC Deconfiguration Register
-///         Activate the PMC Idle seequencer
-///         For each functional EX chiplet
-///             Activate the PCBS-PM macro to enable idle operations
-///             Clear the OCC Special Wake-up bit that is blocking idles until
-///                 the SLW image is installed
-///     } else if PM_RESET {
-///         Set and then reset bit 0 in the SLW_RESET_REGISTER
-///
-///     }
-///
-///  Procedure Prereq:
-///     - System clocks are running
-/// \endverbatim
-///
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-#include "p8_pm.H"
-#include "p8_pm_utils.H"
-#include "p8_poreslw_init.H"
-#include "p8_pfet_init.H"
-#include "p8_pmc_deconfig_setup.H"
-#include "p8_cpu_special_wakeup.H"
-#include "p8_pcb_scom_errors.H"
-
-extern "C" {
-
-using namespace fapi;
-
-// ----------------------------------------------------------------------
-// Constant definitions
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Global variables
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Function prototypes
-// ----------------------------------------------------------------------
-
-fapi::ReturnCode 
-poreslw_init(const Target& i_target, uint32_t i_mode);
-
-fapi::ReturnCode 
-poreslw_reset(const Target& i_target);
-
-fapi::ReturnCode 
-poreslw_ex_setup(const Target& i_target);
-
-fapi::ReturnCode
-p8_pm_pcbs_fsm_trace_chip(const fapi::Target& i_target,           
-                            const char *        i_msg);
-
-// ----------------------------------------------------------------------
-// Function definitions
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-/**
- * p8_pcbs_init calls the underlying routine based on mode parameter
- *
- * @param[in] i_target Chip target
- * @param[in] mode     Control mode for the procedure
- *                     PM_INIT, PM_CONFIG, PM_RESET
- *
- * @retval FAPI_RC_SUCCESS
- * @retval ERROR defined in xml
- */
-fapi::ReturnCode
-p8_poreslw_init(const Target& i_target, uint32_t mode)
-{
-    fapi::ReturnCode      rc;
-    const char *        PM_MODE_NAME_VAR; // Defines storage for PM_MODE_NAME
-
-    FAPI_INF("Executing p8_poreslw_init in mode %s", PM_MODE_NAME(mode));
-
-    /// -------------------------------
-    /// Configuration:  perform translation of any Platform Attributes
-    /// into Feature Attributes that are applied during Initalization
-    if (mode == PM_CONFIG)
-    {
-      FAPI_INF("PORE-SLW configuration...");
-      // None is defined
-    }
-
-    /// -------------------------------
-    /// Initialization:  perform order or dynamic operations to initialize
-    /// the SLW using necessary Platform or Feature attributes.
-    else if (mode == PM_INIT || mode == PM_INIT_PMC )
-    {
-      rc = poreslw_init(i_target, mode);
-    }
-
-    /// -------------------------------
-    /// Reset:  perform reset of SLW engine so that it can reconfigured and
-    /// reinitialized
-    else if (mode == PM_RESET)
-    {
-      rc = poreslw_reset(i_target);
-    }
-
-    /// -------------------------------
-    /// Unsupported Mode
-    else {
-
-      FAPI_ERR("Unknown mode passed to p8_poreslw_init. Mode %x ....", mode);
-      uint32_t & IMODE = mode;
-      FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PORESLW_CODE_BAD_MODE);
-
-    }
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// PORE SLW Initialization Function
-//------------------------------------------------------------------------------
-/**
- * poreslw_init Initializes the slw function on a chip
- *
- * @param[in] i_target Chip target
- *
- * @retval FAPI_RC_SUCCESS
- * @retval ERROR defined in xml
- */
-fapi::ReturnCode
-poreslw_init(const Target& i_target, uint32_t i_mode)
-{
-    fapi::ReturnCode      rc;
-    uint32_t              e_rc = 0;
-    ecmdDataBufferBase    data(64);
-
-    FAPI_INF("PORE-SLW initialization...");
-
-    do
-    {
-
-        uint8_t ipl_mode = 0;
-        rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, ipl_mode);
-        if (!rc.ok())
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL rc = 0x%x", (uint32_t)rc);
-            break;
-        }
-        
-        FAPI_INF("IPL mode = %s", ipl_mode ? "MPIPL" : "NORMAL");
-                
-        uint8_t trace_en_flag = 1;  
-        FAPI_INF("PM FAPI Global FIR Tracing set to ENABLED");    
-        SETATTR(rc,
-                ATTR_PM_GLOBAL_FIR_TRACE_EN,
-                "ATTR_PM_GLOBAL_FIR_TRACE_EN",
-                NULL,
-                trace_en_flag);
-        
-        FAPI_INF("PM FAPI PCBS FSM Tracing set to ENABLED");   
-        SETATTR(rc,
-                ATTR_PM_PCBS_FSM_TRACE_EN,
-                "ATTR_PM_PCBS_FSM_TRACE_EN",
-                NULL,
-                trace_en_flag);               
-
-        rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init at entry");
-        if (!rc.ok()) { break; }
-
-        // Synchronize the PMC Deconfiguration Register with the currently
-        // enabled EX chiplets.
-        FAPI_EXEC_HWP(rc,  p8_pmc_deconfig_setup, i_target);
-        if(rc)
-        {
-            FAPI_ERR("PMC Deconfig Setup error");
-            break;
-        }
-
-        FAPI_DBG("Activate the PMC Idle seequencer by making sure the Halt bit is clear");
-        const uint32_t HALT_IDLE_STATE_MASTER_FSM = 14;
-        rc = fapiGetScom(i_target, PMC_MODE_REG_0x00062000, data);
-        if(!rc.ok())
-        {
-            FAPI_ERR("Scom error reading PMC_MODE");
-            break;
-        }
-
-        e_rc |= data.clearBit(HALT_IDLE_STATE_MASTER_FSM);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            rc.setEcmdError(e_rc);
-            break;
-        }
-
-        rc = fapiPutScom(i_target, PMC_MODE_REG_0x00062000, data);
-        if(!rc.ok())
-        {
-            FAPI_ERR("Scom error writing PMC_MODE");
-            break;
-        }
-
-        FAPI_DBG("Activate the PMC Idle seequencer by making sure the Halt bit is clear");
-
-        if (i_mode == PM_INIT)
-        {
-            // Setup up each of the EX chiplets
-            rc = poreslw_ex_setup(i_target);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Error from poreslw_ex_setup n");
-                break;
-            }
-        }
-
-    } while(0);
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// PORE SLW Reset Function
-//------------------------------------------------------------------------------
-/**
- * poreslw_reset Resets the slw function on a chip
- *
- * @param[in] i_target Chip target
- *
- * @retval FAPI_RC_SUCCESS
- * @retval ERROR defined in xml
- */
-fapi::ReturnCode
-poreslw_reset(const Target& i_target)
-{
-    fapi::ReturnCode      rc;
-    uint32_t              e_rc = 0;
-    ecmdDataBufferBase    data(64);
-    ecmdDataBufferBase    polldata(64);
-    const uint32_t        max_polls = 8;
-    uint32_t              poll_count;
-    bool                  wait_state_detected;
-    bool                  poll_loop_error = false;
-
-    FAPI_INF("PORE-SLW reset...");
-
-    do
-    {
-        //  Reset the SLWs using the Reset Register bit 0.
-        //  Note:  Resets ALL registers (including debug registers) with the
-        //  exception of Error Maskbuild_node_slw
-
-        // set PORE run bit to stop
-        rc = fapiGetScom(i_target, PORE_SLW_CONTROL_0x00068001, data);
-        if(!rc.ok())
-        {
-            FAPI_ERR("Scom error reading PORE_SLW_CONTROL");
-            break;
-        }
-
-        e_rc |= data.setBit(0);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            rc.setEcmdError(e_rc);
-            break;
-        }
-
-        rc = fapiPutScom(i_target, PORE_SLW_CONTROL_0x00068001, data);
-        if(!rc.ok())
-        {
-            FAPI_ERR("Scom error writing PORE_SLW_CONTROL");
-            break;
-        }
-
-        // Reset PORE (state machines and PIBMS_DBG registers) and PIB2OCI
-        // interface write Reset_Register(0:1) with 0b11 to trigger the reset.
-        e_rc |= data.flushTo0();
-        e_rc |= data.setBit(0, 2);
-        if (e_rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-            rc.setEcmdError(e_rc);
-            break;
-        }
-
-        FAPI_DBG("PORE-SLW Reset value: 0x%16llX", data.getDoubleWord(0));
-
-        rc = fapiPutScom(i_target, PORE_SLW_RESET_0x00068002, data);
-        if(!rc.ok())
-        {
-            FAPI_ERR("Scom error writing PORE_SLW_RESET");
-            break;
-        }
-
-        // poll until PORE has returned to WAIT state 3:6=0b0001
-        wait_state_detected = false;
-        for (poll_count=0; poll_count<max_polls; poll_count++)
-        {
-            rc = fapiGetScom(i_target, PORE_SLW_STATUS_0x00068000, polldata);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error reading PORE_SLW_STATUS");
-                poll_loop_error = true;
-                break;
-            }
-
-            if(polldata.isBitClear(3, 3) && polldata.isBitSet(6))
-            {
-               wait_state_detected = true;
-               break;
-            }
-            else
-            {
-              fapiDelay(1000, 10);
-            }
-        }
-
-        // Break if a FAPI error occured in the polling loop
-        if (poll_loop_error)
-        {
-             break;
-        }
-
-        if(!wait_state_detected)
-        {
-          FAPI_ERR("PORE SLW reset failed ");
-          const fapi::Target & CHIP = i_target;
-          uint32_t           & POLLCOUNT = poll_count;
-          const uint32_t     & MAXPOLLS = max_polls;
-          FAPI_SET_HWP_ERROR(rc, RC_PROCPM_SLW_RESET_TIMEOUT);
-        }
-
-    } while (0);
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// EX Idle Setup Function
-//  Note:   PMGP0 and OCC Special Wakeup actions could be done with multicast in
-//          the future.
-//------------------------------------------------------------------------------
-/**
- * poreslw_ex_setup Resets the slw function for each EX chiplet
- *
- * @param[in] i_target Chip target
- *
- * @retval FAPI_RC_SUCCESS
- * @retval ERROR defined in xml
- */
-fapi::ReturnCode
-poreslw_ex_setup(const Target& i_target)
-{
-    fapi::ReturnCode                rc;
-    uint32_t                        e_rc = 0;
-    ecmdDataBufferBase              data(64);
-    ecmdDataBufferBase              config_data(64);
-    ecmdDataBufferBase              set_data(64);
-    ecmdDataBufferBase              clear_data(64);
-    std::vector<fapi::Target>       l_exChiplets;
-    uint8_t                         l_ex_number = 0;
-    uint64_t                        address;
-
-    uint8_t                         pm_sleep_type;
-    uint8_t                         pm_sleep_entry ;
-    uint8_t                         pm_sleep_exit ;
-    uint8_t                         pm_winkle_type  ;
-    uint8_t                         pm_winkle_entry ;
-    uint8_t                         pm_winkle_exit ;
-    
-    uint8_t                         core_vret_voff_value;
-    uint8_t                         eco_vret_voff_value;
-
-
-    // These enums must match the enum values in pm_hwp_attributes.xml
-    enum IDLE_TYPE
-    {
-        FAST        = 0,
-        DEEP        = 1
-    };
-
-    enum IDLE_TRANSITION_MODE
-    {
-        HARDWARE    = 0,
-        ASSISTED    = 1
-    };
-
-    // Give relevant bits a name
-    // PMGP1 bits
-    const uint32_t                  PM_SLEEP_POWER_DOWN_EN_BIT  = 0;
-    const uint32_t                  PM_SLEEP_POWER_UP_EN_BIT    = 1;
-    const uint32_t                  PM_SLEEP_POWER_OFF_SEL_BIT  = 2;
-    const uint32_t                  PM_WINKLE_POWER_DOWN_EN_BIT = 3;
-    const uint32_t                  PM_WINKLE_POWER_UP_EN_BIT   = 4;
-    const uint32_t                  PM_WINKLE_POWER_OFF_SEL_BIT = 5;
-
-    const uint32_t                  PM_DISABLE = 0;
-
-    do
-    {
-
-        FAPI_INF("Executing poreslw_ex_setup...");
-        
-        // --------------------------------------
-        // Initialize the PFET controllers
-        //   This HWP loops across the chiplet but uses chip level attributes so
-        //   it is invoked prior to the chiplet loop below.
-        FAPI_INF("\tInitialize the PFET controllers");
-        
-        rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init before PFET initialization");
-        if (!rc.ok()) { break; }
-
-        FAPI_EXEC_HWP(rc,  p8_pfet_init, i_target, PM_INIT);
-        if(rc)
-        {
-            FAPI_ERR("PFET Controller Setup error");
-            break;
-        }
-        
-        rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init after PFET init");
-        if (!rc.ok()) { break; }
-
-        // Read the attributes
-
-        // \todo Hardcoded values until platform control of attributes is in place.
-        FAPI_INF("\tWARNING:  !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
-        FAPI_INF("\tWARNING:  Hardcoded idle config values set until platform support of attributes available");
-        FAPI_INF("\tWARNING:  !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!");
-
-        pm_sleep_entry      = 0;   // 0=assisted, 1=HW
-        pm_sleep_exit       = 0;   // 0=assisted, 1=HW
-        pm_sleep_type       = 1;   // 0=fast, 1=deep
-
-
-        // Due to L3 High Availability Write Pointers that must be
-        // saved upon a Deep Winkle Entry, this transition must be
-        // assisted.
-        pm_winkle_entry     = 0;   // 0=assisted, 1=HW
-        pm_winkle_exit      = 0;   // 0=assisted, 1=HW
-        pm_winkle_type      = 1;   // 0=fast, 1=deep
-        
-        core_vret_voff_value = 0x0B;    // Default PFET control values for Deep
-        eco_vret_voff_value = 0x0B;     // Default PFET control values for Deep
-
-        // Sleep
-        /*
-        GETATTR(ATTR_PM_SLEEP_TYPE,
-                "ATTR_PM_SLEEP_TYPE",
-                &i_target,
-                pm_sleep_type);
-
-        GETATTR(ATTR_PM_SLEEP_ENTRY,
-                "ATTR_PM_SLEEP_ENTRY",
-                &i_target,
-                pm_sleep_entry);
-
-        GETATTR(ATTR_PM_SLEEP_EXIT,
-                "ATTR_PM_SLEEP_EXIT",
-                &i_target,
-                pm_sleep_exit);
-
-        // Winkle
-        GETATTR(ATTR_PM_WINKLE_TYPE,
-                "ATTR_PM_WINKLE_TYPE",
-                &i_target,
-                pm_winkle_type);
-
-        GETATTR(ATTR_PM_WINKLE_ENTRY,
-                "ATTR_PM_WINKLE_ENTRY",
-                &i_target,
-                pm_winkle_entry);
-
-        GETATTR(ATTR_PM_WINKLE_EXIT,
-                "ATTR_PM_WINKLE_EXIT",
-                &i_target,
-                pm_winkle_exit);
-
-        */
-        
-        // 9/16/13: L3 High Availablity is not supported on P8 any longer.  Removing.
-        // Due to L3 High Availability Write Pointers that must be
-        // saved upon a Deep Winkle Entry, this transition must be
-        // assisted.
-        // If ever supported, would need an Attribute for L3 HA enabled.  GA1 = NO
-        //if (pm_winkle_entry != ASSISTED)
-        //{
-        //    FAPI_INF("Winkle Entry is not configured in ASSISTED mode.  L3 High Availability functions"
-        //             " are not supported");
-        //    FAPI_INF("Continuing anyway....");
-        //}
-
-        // --------------------------------------
-        // Walk the configured chiplets
-        rc = fapiGetChildChiplets (   i_target,
-                                        TARGET_TYPE_EX_CHIPLET,
-                                        l_exChiplets,
-                                        TARGET_STATE_FUNCTIONAL);
-        if (rc)
-        {
-            FAPI_ERR("Error from fapiGetChildChiplets!");
-            break;
-        }
-
-        FAPI_DBG("\tChiplet vector size  => %zu ", l_exChiplets.size());
-
-
-        // Iterate through the returned chiplets
-        for (uint8_t j=0; j < l_exChiplets.size(); j++)
-        {
-
-            // Get the core number
-            rc = FAPI_ATTR_GET(  ATTR_CHIP_UNIT_POS,
-                                   &l_exChiplets[j],
-                                   l_ex_number);
-            if(!rc.ok())
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS error");
-                break;
-            }
-
-            FAPI_INF("\tSetting up Core %X ", l_ex_number);
-
-            //  ******************************************************************
-            //  Set PMGP1_REG
-            //  ******************************************************************
-
-            FAPI_DBG("\t-----------------------------------------------------");
-            FAPI_DBG("\tPMGP1_REG Configuration                  ");
-            FAPI_DBG("\t-----------------------------------------------------");
-            FAPI_DBG("\t  pm_sleep_entry          => %d ", pm_sleep_entry );
-            FAPI_DBG("\t  pm_sleep_exit           => %d ", pm_sleep_exit  );
-            FAPI_DBG("\t  pm_sleep_type           => %d ", pm_sleep_type  );
-            FAPI_DBG("\t  pm_winkle_entry         => %d ", pm_winkle_entry  );
-            FAPI_DBG("\t  pm_winkle_exit          => %d ", pm_winkle_exit  );
-            FAPI_DBG("\t  pm_winkle_type          => %d ", pm_winkle_type  );
-            FAPI_DBG("\t-----------------------------------------------------");
-
-
-            FAPI_DBG("\t*************************************");
-            FAPI_INF("\tSetup PMGP1_REG for EX %x", l_ex_number);
-            FAPI_DBG("\t*************************************");
-
-            // Initialize the set and clear vectors
-            e_rc |= clear_data.flushTo1();  // Set to 1s to be used for WAND
-            e_rc |= set_data.flushTo0();    // Set to 0s to be used for WOR
-
-            // If   sleep entry = 1 (hardware), sleep power down enable = 1
-            // else sleep entry = 0 (assisted), sleep power down enable = 0
-            if (pm_sleep_entry)
-            {
-                e_rc |= set_data.setBit(PM_SLEEP_POWER_DOWN_EN_BIT);
-            }
-            else
-            {
-                e_rc |= clear_data.clearBit(PM_SLEEP_POWER_DOWN_EN_BIT);
-            }
-
-            // If   sleep exit  = 1 (hardware), sleep power up enable = 1
-            // else sleep exit  = 0 (assisted), sleep power up enable = 0
-            if (pm_sleep_exit)
-            {
-                e_rc |= set_data.setBit(PM_SLEEP_POWER_UP_EN_BIT);
-            }
-            else
-            {
-                e_rc |= clear_data.clearBit(PM_SLEEP_POWER_UP_EN_BIT);
-            }
-
-            // If   sleep type  = 1 (deep), sleep power up sel = 1
-            // else sleep type  = 0 (fast), sleep power up sel = 0
-            if (pm_sleep_type)
-            {
-                e_rc |= set_data.setBit(PM_SLEEP_POWER_OFF_SEL_BIT);            
-
-            }
-            else
-            {
-                e_rc |= clear_data.clearBit(PM_SLEEP_POWER_OFF_SEL_BIT);
-                core_vret_voff_value = 0x00;
-                eco_vret_voff_value = 0x00;
-            }
-
-            // If   winkle entry = 1 (hardware), winkle power down enable = 1
-            // else winkle entry = 0 (assisted), winkle power down enable = 0
-            if (pm_winkle_entry)
-            {
-                e_rc |= set_data.setBit(PM_WINKLE_POWER_DOWN_EN_BIT);
-            }
-            else
-            {
-                e_rc |= clear_data.clearBit(PM_WINKLE_POWER_DOWN_EN_BIT);
-            }
-
-            // If   winkle exit  = 1 (hardware), winkle power up enable = 1
-            // else winkle exit  = 0 (assisted), winkle power up enable = 0
-            if (pm_winkle_exit)
-            {
-                e_rc |= set_data.setBit(PM_WINKLE_POWER_UP_EN_BIT);
-            }
-            else
-            {
-                e_rc |= clear_data.clearBit(PM_WINKLE_POWER_UP_EN_BIT);
-            }
-
-            // If   winkle type  = 1 (deep), winkle power up sel = 1
-            // else winkle type  = 0 (fast), winkle power up sel = 0
-            if (pm_winkle_type)
-            {
-                e_rc |= set_data.setBit(PM_WINKLE_POWER_OFF_SEL_BIT);
-
-            }
-            else
-            {
-                e_rc |= clear_data.clearBit(PM_WINKLE_POWER_OFF_SEL_BIT);
-                core_vret_voff_value = 0x00;
-                eco_vret_voff_value = 0x00;
-            }
-
-            // Check for any errors from set/clear ops into the buffers
-            if (e_rc)
-            {
-                FAPI_ERR("eCmdDataBuffer operation failed. rc = 0x%x", (uint32_t)e_rc);
-                rc.setEcmdError(e_rc);
-                break;
-            }
-
-            // The set and clear vectors are built.  Write them to
-            // the respective addresses.
-            FAPI_DBG("\tEX_PMGP1_WOR  0x%16llx" , set_data.getDoubleWord(0));
-            address = EX_PMGP1_REG_0_WORx100F0105 + (l_ex_number * 0x01000000);
-            rc=fapiPutScom(i_target, address, set_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. rc = 0x%x", (uint32_t)rc);
-                break;
-            }
-
-            FAPI_DBG("\tEX_PMGP1_WAND 0x%16llx" , clear_data.getDoubleWord(0));
-            address = EX_PMGP1_REG_0_WANDx100F0104 + (l_ex_number * 0x01000000);
-            rc=fapiPutScom(i_target, address, clear_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiPutScom(EX_PMGP1_REG_0_WORx100F0105) failed. rc = 0x%x", (uint32_t)rc);
-                break;
-            }
-
-            FAPI_INF("\tDisable the PCBS Heartbeat EX %x", l_ex_number);
-            address = EX_SLAVE_CONFIG_0x100F001E + (l_ex_number * 0x01000000);
-            rc = fapiGetScom(i_target, address, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error reading PCBS Slave Config");
-                break;
-            }
-
-            e_rc |= data.setBit(4);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-                rc.setEcmdError(e_rc);
-                break;
-            }
-
-            rc=fapiPutScom(i_target, address, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error writing PCBS Slave Config");
-                break;
-            }
-
-            // --------------------------------------
-            FAPI_INF("\tSet PMGP0(46) to deal with HW259509 - winkle Pstate stepping hang");
-
-            // This is a spare bit in Murano and Venice DD1s but
-            // is necessary to set in Murano and Venice DD2 to deal
-            // the hang condition that is fixed.  As bit 46 is spare
-            // in the previous levels, setting it on all levels is not
-            // harmful.
-            // While setting bit46, also set the PM_disable bit0 to prevent the
-            // PMGP0-invalid-write-snitch bit PMErr_REG(12) to light up.
-            // Note, PM_Disable will get disabled by the PM_Disable check
-            // immediately after this code.
-            address = EX_PMGP0_OR_0x100F0102 + (l_ex_number * 0x01000000);
-
-            e_rc |= data.flushTo0();
-            e_rc |= data.setBit(46);
-            e_rc |= data.setBit(0);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-                rc.setEcmdError(e_rc);
-                break;
-            }
-
-            rc=fapiPutScom(i_target, address, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error setting PMGP0");
-                break;
-            }
-
-            // --------------------------------------
-            // Check that PM function is enabled (eg not disabled).
-            // If not, remove the disable
-
-            address = EX_PMGP0_0x100F0100 + (l_ex_number * 0x01000000);
-            rc=fapiGetScom(i_target, address, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error reading PMGP0");
-                break;
-            }           
-
-            rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init before PM enablement check");
-            if (!rc.ok()) { break; }
-
-            if (data.isBitSet(PM_DISABLE))
-            {
-
-                // Activate the PCBS-PM macro by clearing the PM_DISABLE bit
-                FAPI_INF("\tActivate the PCBS-PM for EX %x", l_ex_number);
-
-                e_rc |= data.flushTo1();
-                e_rc |= data.clearBit(PM_DISABLE);
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-                    rc.setEcmdError(e_rc);
-                    break;
-                }
-                                
-                address = EX_PMGP0_AND_0x100F0101 + (l_ex_number * 0x01000000);
-                rc=fapiPutScom(i_target, address, data);
-                if(!rc.ok())
-                {
-                    FAPI_ERR("Scom error writing EX_PMGP0_OR");
-                    break;
-                }
-                
-                rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init after PM enablement");
-                if (!rc.ok()) { break; }
-
-            }
-
-            // --------------------------------------
-            // Clear OCC Special Wake-up bit - only 1 bit in the register
-            address = EX_PMSpcWkupOCC_REG_0x100F010C + (l_ex_number * 0x01000000);
-            rc=fapiGetScom(i_target, address, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error clearing EX_OCC_SPWKUP");
-                break;
-            }
-
-            rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init before OCC clearing Special Wakeup check");
-            if (!rc.ok()) { break; }
-
-            if (data.isBitSet(0))
-            {
-                FAPI_INF("\tClear OCC Special Wake-up for EX %x", l_ex_number);
-                e_rc |= data.flushTo0();
-                if (e_rc)
-                {
-                    FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc);
-                    rc.setEcmdError(e_rc);
-                    break;
-                }
-
-                rc=fapiPutScom(i_target, address, data);
-                if(!rc.ok())
-                {
-                    FAPI_ERR("Scom error clearing EX_OCC_SPWKUP");
-                    break;
-                }
-                
-                rc = p8_pm_pcbs_fsm_trace_chip(i_target, "poreslw_init after OCC clearing Special Wakeup");
-                if (!rc.ok()) { break; }
-            }
-            
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting Core Voff Settings");
-            e_rc |= data.flushTo0();
-            e_rc |= data.insertFromRight(core_vret_voff_value, 0, 8);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                rc.setEcmdError(e_rc);
-                break;
-            }
-
-            address = EX_CorePFVRET_REG_0x100F0130 + (0x01000000 * l_ex_number);
-            rc = fapiPutScom(i_target, address, data );
-            if(!rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llu", address);
-                break;
-            }
-           
-            // -------------------------------------------------------------
-            FAPI_DBG("\tSetting ECO Voff Settings");
-            e_rc |= data.flushTo0();
-            e_rc |= data.insertFromRight(eco_vret_voff_value, 0, 8);
-            if (e_rc)
-            {
-                FAPI_ERR("Error (0x%x) setting up  ecmdDataBufferBase", e_rc);
-                rc.setEcmdError(e_rc);
-                break;
-            }
-
-            address = EX_ECOPFVRET_REG_0x100F0150 + (0x01000000 * l_ex_number);
-            rc = fapiPutScom(i_target, address, data );
-            if(!rc.ok())
-            {
-                FAPI_ERR("PutScom error 0x%08llu", address);
-                break;
-            }
-
-            // --------------------------------------
-            // Initialize the special wake-up tracking attributes
-            FAPI_INF("\tInitialize the special wake-up tracking attributes");
-
-            FAPI_EXEC_HWP(rc,  p8_cpu_special_wakeup,
-                                l_exChiplets[j],
-                                SPCWKUP_INIT,
-                                SPW_ALL);
-            if(rc)
-            {
-                FAPI_ERR("Special wake-up initialization error");
-                break;
-            }
-
-        }  // chiplet loop
-    } while(0);
-
-    return rc;
-}
-
-
-} //end extern
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.H
deleted file mode 100644
index f5eadf31a..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.H
+++ /dev/null
@@ -1,80 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_poreslw_init.H,v 1.1 2012/08/23 04:58:51 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_poreslw_init.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_poreslw_init.H
-// *! DESCRIPTION : Initialize the PORE SLW Engines in the OCC
-// *!
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Jim Yacynych  Email: jimyac@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _P8_PORESLW_H_
-#define _P8_PORESLW_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_poreslw_init_FP_t) (const fapi::Target&, uint32_t);
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Parameter structure definitions
-//------------------------------------------------------------------------------
-
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-/// \param[in] i_target Chip target
-/// \param[in] mode     Control mode for the procedure (PM_CONFIG, PM_INIT, PM_RESET)
-
-/// \retval ECMD_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode 
-p8_poreslw_init(const fapi::Target& i_target, uint32_t mode);
-
-
-} // extern "C"
-
-#endif // _P8_PORESLW_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
deleted file mode 100644
index 1e7b93106..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C
+++ /dev/null
@@ -1,785 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_set_pore_bar.C,v 1.10 2014/11/07 18:26:34 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_set_pore_bar.C,v $
-//-------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//-------------------------------------------------------------------------------
-// *! OWNER NAME: Greg Still         Email: stillgs@us.ibm.com
-// *!
-// *! *** IMPORTANT *** 
-// *! For P9, this proc should be changed to setup HOMER in PBABAR0 and then setup
-// *! SLW in PBABAR2 by calculating BAR2 = BAR0 + HOMER_SLW_IMAGE_OFFSET_ADDR.
-// *! *** IMPORTANT ***
-// *!
-// *! To build -  buildfapiprcd -e ../../xml/error_info/p8_set_pore_bar_errors.xml p8_set_pore_bar.C
-// *!
-/// \file p8_set_pore_bar.C
-/// \brief Set up the Sleep/Winkle (SLW) PORE Memory Relocation (MRR) and
-/// Table Base Address (TBA) for accessing the SLW image
-///
-/// High-level procedure flow:
-/// \verbatim
-///
-///     Address and size of SLW image for the target (chip) is passed based on
-///     where the caller has placed the image for this target in the platform
-///     memory.
-///
-///     The Base Address (BAR) and a mask for the region in which the SLW
-///     image is placed is passed.  This is used to establish the PBA BAR and
-///     mask hardware to set the legal bounds for SLW accesses.
-///
-///     The BAR defines address bits 14:43 in natural bit alignment (eg no
-///     shifting)
-///
-///     The Size (in MB) of the region where image is located.
-///         If not a power of two value, the value will be rounded up to the
-///         next power of 2 for setting the hardware mask
-///
-///         If 0 is defined and the BAR is also defined as 0, then the BAR
-///         is set (to 0) but no image accessing is done as this is considered
-///         a BAR reset condition.  The TBA and MRR values in the PORE-SLW are
-///         not altered.
-///
-///         If 0 is defined and the BAR is NOT 0, an error is returned as this
-///         is defining a zero sized, real region.
-///
-///     Flow (given BAR and Size are ok per the above)
-///        Check that passed address is within the 50 bit real address range
-///        Check that image address + image size does not extend past the 50 bit
-///            boundary
-///
-///        Read image link address at image offset 0x10
-///        Link Address(0:1) is the OCI region that will invoke the MRR.  These
-///            are set into MRR(30:31).
-///        Calculate MRR address (32:63) = image address - link address (32 bit)
-///        Store MRR to PORE SLW
-///
-///        Call p8_pba_bar_config to set up PBA BAR 2 with the address and
-///            size of the SLW region as passed via calling parameters
-///         i_mem_bar and i_mem_mask.
-///
-///  Procedure Prereq:
-///     - SLW image memory region has been allocated and XIP image loaded.
-///
-///  CQ Class:  power_management
-/// \endverbatim
-///
-//-------------------------------------------------------------------------------
-
-
-// ------------------------------------------------------------------------------
-// Includes
-// ------------------------------------------------------------------------------
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-#include "pgp_common.h"
-#include "p8_set_pore_bar.H"
-#include "p8_pm.H"
-#include "p8_pba_init.H"
-#include "p8_pba_bar_config.H"
-#include "pgp_pba.h"
-#include "sbe_xip_image.h"
-#include "p8_homer_map.h"
-
-
-extern "C" {
-
-using namespace fapi;
-
-// ------------------------------------------------------------------------------
-// Constant definitions
-// ------------------------------------------------------------------------------
-
-// ------------------------------------------------------------------------------
-// Global variables
-// ------------------------------------------------------------------------------
-
-// ------------------------------------------------------------------------------
-// Function prototypes
-// ------------------------------------------------------------------------------
-
-fapi::ReturnCode bar_pba_slave_reset( const fapi::Target& i_target,
-                                      uint32_t id );
-
-// ------------------------------------------------------------------------------
-// Function definitions
-// ------------------------------------------------------------------------------
-
-
-/// \param[in] i_target     Procesor Chip target
-/// \param[in] i_image      Platform memory pointer where image is
-///                         located
-/// \param[in] i_mem_bar    Base address of the region where image is located
-/// \param[in] i_mem_size   Size (in MB) of the region where image is located
-///                         if not a power of two value, the value will be
-///                         rounded up to the next power of 2 for setting the
-///                         hardware mask.  The value of 0 is only legal if
-///                         i_mem_bar is also 0;  else an error is indicated.
-/// \param[in] i_mem_type   Defines where the SLW image was loaded.  See
-///                         p8_set_pore_bar.H enum for valid values.
-///
-/// \retval SUCCESS
-/// \retval RC_PROCPM_POREBAR_IMAGE_BRANCH_VALUE_ERROR
-/// \retval RC_PROCPM_POREBAR_LOC_ERROR
-/// \retval RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR (future version)
-/// \retval RC_PROCPM_POREBAR_IMAGE_PLACEMENT_ERROR (future version)
-fapi::ReturnCode
-p8_set_pore_bar(      const fapi::Target& i_target,
-                        void                *i_image,
-                        uint64_t            i_mem_bar,
-                        uint64_t            i_mem_size,
-                        uint32_t            i_mem_type)
-{
-    fapi::ReturnCode    rc;
-    uint32_t            l_ecmdRc = 0;
-    ecmdDataBufferBase  data(64);
-
-    uint64_t            image_address;
-    uint64_t            image_size;
-//    uint64_t            region_begin_address;
-//    uint64_t            region_end_address;
-    uint64_t            region_masked_address;
-//    uint64_t            region_inverted_mask;
-//    uint64_t            computed_image_address;
-//    uint64_t            computed_last_image_address;
-
-    uint64_t            slw_branch_table_address;
-
-    pba_slvctln_t       ps;                         // PBA Slave
-
-    // Hardcoded use of PBA BAR and Slave
-    const uint32_t      pba_bar = PBA_BAR2;
-    const uint32_t      pba_bar_slw = PBA_SLW_BAR2;
-    const uint32_t      pba_slave = PBA_SLAVE2;
-
-    const uint64_t      slw_pba_cmd_scope = 0x2;   // Set to SYSTEM
-    
-    const uint32_t      occ_pba_bar = PBA_BAR0;
-    uint64_t            occ_mem_bar = 0x0;         // Set later when sure SLW in MS/L3.
-    const uint64_t      occ_mem_size = 0x4;
-    const uint64_t      occ_pba_cmd_scope = 0x0;   // Set to NODAL
-
-    SbeXipItem          slw_control_vector_info;
-    uint32_t            slw_control_vector_offset;
-    
-    SbeXipItem          slw_deep_winkle_exit_good_halt_info;
-    uint32_t            slw_deep_winkle_exit_good_halt_offset;
-    
-    SbeXipItem          slw_deep_sleep_exit_good_halt_info;
-    uint32_t            slw_deep_sleep_exit_good_halt_offset;
-
-
-
-    // -----------------------------------------------------------------
-    do
-    {
-        FAPI_INF("Executing p8_set_pore_bar...");
-        image_address = (uint64_t) i_image;
-        FAPI_DBG("Passed address 0x%16llX ", image_address);
-
-        // Check if this is a BAR reset case.
-        if (i_mem_size == 0)
-        {
-            if(i_mem_bar != 0)
-            {
-                FAPI_ERR("SLW Size is 0 but BAR is non-zero:  0x%16llx", i_mem_bar );
-                const fapi::Target & CHIP = i_target;
-                const uint64_t     & IMAGEADDR = (uint64_t)i_image;
-                const uint32_t     & MEMSIZE = i_mem_size;
-                const uint64_t     & MEMBAR = i_mem_bar;
-                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_SIZE0_ERROR);
-                break;
-            }
-            else
-            {
-                FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
-                           pba_bar, i_mem_bar, i_mem_size);
-
-                // Set the PBA BAR for the SLW region
-                FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
-                                                       pba_bar,
-                                                       i_mem_bar,
-                                                       i_mem_size,
-                                                       slw_pba_cmd_scope);
-
-                // No rc check is made as we're exiting anyway.
-
-                // Exit the procedure as we don't want to access the image nor
-                // touch the SLW TBA or MRR settings.
-                break;
-            }
-        }
-
-
-        // Get the Table Base Address from the image
-        l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
-                                                "slw_branch_table",
-                                                &slw_branch_table_address);
-        if (l_ecmdRc)
-        {
-            FAPI_ERR("Get XIP of slw_branch_table failed. rc = %x\n", l_ecmdRc);
-            const fapi::Target & CHIP = i_target;
-            const uint64_t     & IMAGEADDR = (uint64_t)i_image;
-            const uint32_t     & XIPRC = l_ecmdRc;
-            const uint64_t     & BRANCHTABLEADDRESS = slw_branch_table_address;
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_BRANCH_VALUE_ERROR);
-            break;
-        }
-        FAPI_DBG("slw_branch_table_address:   %16llX", slw_branch_table_address);
-
-        // Get the SLW Control Vector offset from the image
-        l_ecmdRc = sbe_xip_find((void*)   i_image,
-                                          "slw_control_vector",
-                                          &slw_control_vector_info);
-        if (l_ecmdRc)
-        {
-            FAPI_ERR("XIP Find of slw_control_vector failed. rc = %x\n", l_ecmdRc);
-            const fapi::Target & CHIP = i_target;
-            const uint64_t     & IMAGEADDR = (uint64_t)i_image;
-            const uint32_t     & XIPRC = l_ecmdRc;
-            const uint64_t     & SLWCONTROLVECTOR = (uint64_t)slw_control_vector_info.iv_address;
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SLW_CONTROL_VECTOR_ERROR);
-            break;
-        }
-        
-        slw_control_vector_offset = slw_control_vector_info.iv_address;
-        FAPI_DBG("slw_control_vector offset:  %16llX", (uint64_t)slw_control_vector_info.iv_address);
-       
-       
-        SETATTR(rc,
-                ATTR_PM_SLW_CONTROL_VECTOR_OFFSET,
-                "ATTR_PM_SLW_CONTROL_VECTOR_OFFSET",
-                NULL,
-                slw_control_vector_offset);
-
-        
-        // Get the Deep Winkle Good Exit halt offset from the image to save in 
-        // at attribute for other HWP use.
-        l_ecmdRc = sbe_xip_find((void*)   i_image,
-                                          "slw_deep_winkle_exit_good_halt",
-                                          &slw_deep_winkle_exit_good_halt_info);
-        if (l_ecmdRc)
-        {
-            FAPI_ERR("XIP Find of slw_deep_winkle_exit_good_halt failed. rc = %x\n", l_ecmdRc);
-            const fapi::Target & CHIP = i_target;
-            const uint64_t     & IMAGEADDR = (uint64_t)i_image;
-            const uint32_t     & XIPRC = l_ecmdRc;
-            const uint64_t     & SLWDEEPWINKLEEXITHALT = (uint64_t)slw_deep_winkle_exit_good_halt_info.iv_address;
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SLW_DEEP_WINKLE_EXIT_HALT_ERROR);
-            break;
-        }
-        
-        slw_deep_winkle_exit_good_halt_offset = slw_deep_winkle_exit_good_halt_info.iv_address;
-        FAPI_DBG("slw_deep_winkle_exit_good_halt offset: %16llX", (uint64_t)slw_deep_winkle_exit_good_halt_info.iv_address);
-             
-        SETATTR(rc,
-                ATTR_PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR,
-                "ATTR_PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR",
-                NULL,
-                slw_deep_winkle_exit_good_halt_offset);
-        
-        // Get the Deep Sleep Good Exit halt offset from the image to save in 
-        // at attribute for other HWP use.
-        l_ecmdRc = sbe_xip_find((void*)   i_image,
-                                          "slw_deep_sleep_exit_good_halt",
-                                          &slw_deep_sleep_exit_good_halt_info);
-        if (l_ecmdRc)
-        {
-            FAPI_ERR("XIP Find of slw_deep_sleep_exit_good_halt failed. rc = %x\n", l_ecmdRc);
-            const fapi::Target & CHIP = i_target;
-            const uint64_t     & IMAGEADDR = (uint64_t)i_image;
-            const uint32_t     & XIPRC = l_ecmdRc;
-            const uint64_t     & SLWDEEPSLEEPEXITHALT = (uint64_t)slw_deep_sleep_exit_good_halt_info.iv_address;
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_SLW_DEEP_SLEEP_EXIT_HALT_ERROR);
-            break;
-        }
-        
-        slw_deep_sleep_exit_good_halt_offset = slw_deep_sleep_exit_good_halt_info.iv_address;
-        FAPI_DBG("slw_deep_sleep_exit_good_halt offset:  %16llX", (uint64_t)slw_deep_sleep_exit_good_halt_info.iv_address);
-             
-        SETATTR(rc,
-                ATTR_PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR,
-                "ATTR_PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR",
-                NULL,
-                slw_deep_sleep_exit_good_halt_offset);
-
-               
-
-        // Setup the the table base address register
-        //
-        //  Table Base Address Register layout
-        //  16      Interface (0=PIB, 1=OCI)
-        //  17      Reserved
-        //  18:23   Chiplet ID (used only for PIB fetch; unused for OCI)-SLW unused
-        //  24:27   PIB ID (used only for PIB fetch; unused for OCI)-SLW unused
-        //  28:31   PORT ID (used only for PIB fetch; unused for OCI)-SLW unused
-        //  32:64   Table base address for jump table
-        //
-        //  1   2         3  3     6
-        //  6789012345678901 2-----3
-        //  1                           OCI
-        //   0
-        //    000000                    Chiplet ID
-        //          0000                PIB  ID
-        //              0000            PORT ID
-        //
-        //  For SLW images that will run on PORE-SLW, the PORT ID is set to C
-        //
-        //
-
-        // Set the table base address (32:63) with passed value
-        l_ecmdRc |= data.setDoubleWord( 0, slw_branch_table_address);
-        if(l_ecmdRc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-            rc.setEcmdError(l_ecmdRc);
-            break;
-        }
-        rc = fapiPutScom(i_target, PORE_SLW_TABLE_BASE_ADDR_0x00068008, data);
-        if (rc)
-        {
-            FAPI_ERR("Put SCOM error for Table Base Address");
-            break;
-        }
-        FAPI_INF("SLW PORE Table Base Address set to 0x%16llx", data.getDoubleWord(0));
-
-
-
-        // Setup the memory relocation register
-        //
-        // This is hardcoded as the SLW image build process has all images to be:
-        //  1) Relocatable and thus must have the region match bits set
-        //  2) Built for region 0x80000XXX
-        //
-        //  MRR Layout
-        //      30:31:  Memory Reloc Region - 2 MSbs of 32 bit address that
-        //          defines the region match
-        //      32:51   Memory Relocation Base Address added to 0:19 of the OCI
-        //              address
-        //
-        //    Table Base Address Register layout
-        //    16      Interface (0=PIB, 1=OCI)
-        //    17      Reserved
-        //    18:23   Chiplet ID (used only for PIB fetch; unused for OCI)-SLW unused
-        //    24:27   PIB ID (used only for PIB fetch; unused for OCI)-SLW unused
-        //    28:31   PORT ID (used only for PIB fetch; unused for OCI)-SLW unused
-        //    32:64   Table base address for jump table
-        //
-        //    1   2         3  3     6
-        //    6789012345678901 2-----3
-        //    1                           OCI
-        //     0
-        //      000000                    Chiplet ID
-        //            0000                PIB  ID
-        //                0000            PORT ID
-        //
-        //    For SLW images that will run on PORE-SLW, the PORT ID is set to C in
-        //    the image but this is unused by the hardware.
-
-        l_ecmdRc |= data.flushTo0();
-
-        // Set 30:31 to 10 to yield a region of 0x8XXXXXXX (eg unused OCI region)
-        l_ecmdRc |= data.setBit( 30, 1);
-
-        if(l_ecmdRc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", l_ecmdRc);
-            rc.setEcmdError(l_ecmdRc);
-            break;
-        }
-
-        // SLW image has effective addresses in the form of 0x8XXXXXXX.
-        // The PORE memory relocation function adds the mem_reloc(32:52) to
-        // effective address 0:19 to form the real address where:
-        //      effective address(0:1) defines the region: 00 = memory/L3, 11 = SRAM
-        //      effective address(2:3) defines the PBA BAR to use (if memory/L3)
-
-        // Set the Memory Relocation Base based on the placement of the SLW image
-        if (i_mem_type == SLW_SRAM)
-        {
-            // Set the beginning of 512KB SRAM tank.
-
-            FAPI_DBG("SLW PORE Memory Relocation Register before SRAM 0x%16llx", data.getDoubleWord(0));
-
-            l_ecmdRc |= data.setOr(0x7FF80<<12, 32, 20);
-            if(l_ecmdRc)
-            {
-                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase", l_ecmdRc);
-                rc.setEcmdError(l_ecmdRc);
-                break;
-            }
-        }
-        else if (i_mem_type == SLW_MEMORY || i_mem_type == SLW_L3)
-        {
-            // The 00 (from the buffer flush) in 0:1 goes toward PBA (memory or L3)
-            // Set to use the PBA with BAR(0:3) encoded in bits 2:3 (eg shift of 30)
-            // 0x80000 + 0xA0000 => 20000 (upper overflow discarded)
-            // The 00 in 0:1 goes toward PBA; 2:3 for PBA BAR 2
-            FAPI_DBG("SLW PORE PBA BAR %x", pba_bar_slw);
-            FAPI_DBG("SLW PORE Memory Relocation Register before MEM 0x%16llx", data.getDoubleWord(0));
-
-            l_ecmdRc |= data.setOr(pba_bar_slw<<28, 32, 20);
-            if(l_ecmdRc)
-            {
-                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase", l_ecmdRc);
-                rc.setEcmdError(l_ecmdRc);
-                break;
-            }
-
-            FAPI_DBG("SLW PORE Memory Relocation Register after MEM 0x%16llx", data.getDoubleWord(0));
-
-            // Check that the bar address passed is 1MB aligned (eg bits 44:63 are zero)
-            //
-            region_masked_address = i_mem_bar & 0x00000000000FFFFF;
-            if (region_masked_address != 0 )
-            {
-                FAPI_ERR("SLW BAR address is not 1MB aligned:  0x%16llx", i_mem_bar );
-                const fapi::Target & CHIP = i_target;
-                const uint64_t     & MEMBAR = i_mem_bar;
-                const uint64_t     & REGIONMASKEDADDR = region_masked_address;
-                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_PBABAR_ERROR);
-                break;
-            }
-
-
-            // Check that the image address passed is within the memory region that
-            // is also passed.
-            //
-            // The PBA Mask indicates which bits from 23:43 (1MB grandularity) are
-            // enabled to be passed from the OCI addresses.  Inverting this mask
-            // indicates which address bits are going to come from the PBA BAR value.
-            // The image address (the starting address) must match these post mask bits
-            // to be resident in the range.
-            //
-            // Starting bit number: 64 bit Big Endian
-            //                                          12223344
-            //                                          60482604
-            // region_inverted_mask = i_mem_mask ^ BAR_MASK_LIMIT;  // XOR
-
-            // Set bits 14:22 as these are unconditional address bits
-            //region_inverted_mask = region_inverted_mask | BAR_ADDR_UNMASKED;
-            //computed_image_address = region_inverted_mask && image_address;
-            // Need to AND the address
-            //if (computed_image_address != i_mem_bar )
-            //{
-            //    FAPI_ERR("SLW image address check failure. ");
-            //    FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_ADDR_ERROR);
-            //    return rc;
-            //}
-
-
-            // Additionally, the size of the image must not extend beyond the above
-            // masked range either.
-
-            // Get the image size from the image itself
-            l_ecmdRc = sbe_xip_get_scalar((void*)   i_image,
-                                                    "image_size",
-                                                     &image_size);
-
-            if (l_ecmdRc)
-            {
-                FAPI_ERR("Get of XIP Image size failed");
-                const fapi::Target & CHIP = i_target;
-                const uint64_t     & IMAGEADDR = (uint64_t)i_image;
-                const uint32_t     & XIPRC = l_ecmdRc;
-                const uint64_t     & IMAGESIZE = image_size;
-                FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_XIP_IMAGE_SIZE_ERROR);
-                break;
-            }
-
-            FAPI_DBG("SLW image size: 0x%08llX", image_size );
-            //  computed_last_image_address = image_address + image_size;
-            //
-            //  if (computed_last_image_address > region_end_address)
-            //    {
-            //        FAPI_ERR("SLW image placement error.");
-            //        FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_IMAGE_PLACEMENT_ERROR);
-            //        return rc;
-            //    }
-
-        }
-        else
-        {
-            FAPI_ERR("Invalid image location passed %x ", i_mem_type);
-            const fapi::Target & CHIP = i_target;
-            const uint64_t     & MEMLOC = i_mem_type;
-            FAPI_SET_HWP_ERROR(rc, RC_PROCPM_POREBAR_LOC_ERROR);
-            break;
-        }
-
-        FAPI_INF("SLW PORE Memory Relocation Register set to 0x%16llx", data.getDoubleWord(0));
-        rc = fapiPutScom(i_target, PORE_SLW_MEMORY_RELOC_0x00068016, data);
-        if (rc)
-        {
-            FAPI_ERR("Put SCOM error for Memory Relocation Address");
-            break;
-        }
-
-        if (i_mem_type == SLW_MEMORY || i_mem_type == SLW_L3)
-        {
-
-            FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
-                            pba_bar, i_mem_bar, i_mem_size);
-
-            // Set the PBA BAR for the SLW region
-            FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
-                                                   pba_bar,
-                                                   i_mem_bar,
-                                                   i_mem_size,
-                                                   slw_pba_cmd_scope);
-            if(rc)
-            {
-                break;
-            }
-
-            // Set the PBA Slave to use the above BAR
-            // \todo Does not yet comprehend the 24x7 setting to allow writing!!
-            //
-            // enable = 1;                 // Enable the slave
-            // mid_match_value=0x4;        // PORE-SLW engine
-            // mid_care_mask=0x7;          // Only the PORE-SLW
-            // write_ttype=0;              // DMA - though NA
-            // read_ttype=0;               // CL_RD_NC
-            // read_prefetch_ctl=0;        // Auto Early
-            // buf_invalidate_ctl=0;       // Disabled
-            // buf_alloc_w=0;              // SLW does not write.  24x7 will
-            // buf_alloc_a=1;              // SLW uses Buf A
-            // buf_alloc_b=0;              // SLW does not use buffer B
-            // buf_alloc_c=0;              // SLW does not use buffer C
-            // dis_write_gather=0;         // SLW does not write.  \todo 24x7
-            // wr_gather_timeout=0;        // SLW does not write   \todo 24x7
-            // write_tsize=0;              // SLW does not write   \todo 24x7
-            // extaddr=0;                  // Bits 23:36.  NA for SLW
-            //
-
-            // Slave 2 (PORE-SLW).  This is a read/write slave. Write gathering is
-            // allowed, but with the shortest possible timeout.  The slave is set up
-            // to allow normal reads and writes at initialization.  The 24x7 code may
-            // reprogram this slave for IMA writes using special code sequences that
-            // restore normal DMA writes after each IMA sequence.
-
-            rc = bar_pba_slave_reset(i_target, PBA_SLAVE2);
-            if (rc)
-            {
-                FAPI_ERR("PBA Slave Reset failed");
-                // \todo add FFDC
-                 break;
-            }
-
-
-            ps.value = 0;
-            ps.fields.enable = 1;
-            ps.fields.mid_match_value = OCI_MASTER_ID_PORE_SLW;
-            ps.fields.mid_care_mask = 0x7;
-            ps.fields.read_ttype = PBA_READ_TTYPE_CL_RD_NC;
-            ps.fields.read_prefetch_ctl = PBA_READ_PREFETCH_NONE;
-            ps.fields.write_ttype = PBA_WRITE_TTYPE_DMA_PR_WR;
-            ps.fields.wr_gather_timeout = PBA_WRITE_GATHER_TIMEOUT_2_PULSES;
-            ps.fields.buf_alloc_a = 1;
-            ps.fields.buf_alloc_b = 1;
-            ps.fields.buf_alloc_c = 1;
-            ps.fields.buf_alloc_w = 1;
-
-            l_ecmdRc |=  data.setDoubleWord(0, ps.value);
-            if(l_ecmdRc)
-            {
-                FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBASLVCTL", l_ecmdRc);
-                rc.setEcmdError(l_ecmdRc);
-                return rc;
-            }
-
-            FAPI_DBG("  PBA_SLVCTL%x: 0x%16llx", pba_slave, data.getDoubleWord(0));
-            rc = fapiPutScom(i_target, PBA_SLVCTLs[pba_slave], data);
-            if (rc)
-            {
-                FAPI_ERR("Put SCOM error for PBA Slave Control");
-                return rc;
-            }
-
-            // While here, also setup of OCC PBABAR0 to indicate the location and size
-            //   of HOMER. This is to support PTS/24x7 launch before OCC startup.
-            // The address to use is 2MB below the SLW image location. This offset is
-            //   represented by HOMER_SLW_IMAGE_OFFSET_ADDR.
-            // The memory size is 4MB.
-            occ_mem_bar = i_mem_bar - HOMER_SLW_IMAGE_OFFSET_ADDR;
-            FAPI_DBG("Calling pba_bar_config to BAR %x Addr: 0x%16llX  Size: 0x%16llX",
-                        occ_pba_bar, occ_mem_bar, occ_mem_size);
-
-            // Set the PBA BAR for the OCC region
-            FAPI_EXEC_HWP(rc, p8_pba_bar_config, i_target,
-                                                 occ_pba_bar,
-                                                 occ_mem_bar,
-                                                 occ_mem_size,
-                                                 occ_pba_cmd_scope);
-            if(rc)
-            {
-                break;
-            }
-
-        } // PBA setup for Memory or L3
-    } while (0);
-    return rc;
-}
-
-/// Reset a PBA slave with explicit timeout.
-///
-/// \param id A PBA slave id in the range 0..3
-///
-/// \param timeout A value of SsxInterval type.  The special value
-/// SSX_WAIT_FOREVER indicates no timeout.
-///
-/// This form of bar_pba_slave_reset() gives the caller control over timeouts and
-/// error handling.
-///
-/// \retval 0 Succes
-///
-/// \retval RC_PROCPM_PBA_SLVRST_TIMED_OUT The procedure timed out waiting for the PBA
-/// to reset the slave.
-
-fapi::ReturnCode
-bar_pba_slave_reset(const fapi::Target& i_target, uint32_t id)
-{
-
-    pba_slvrst_t        psr;
-    fapi::ReturnCode    rc;
-    uint32_t            e_rc = 0;
-    ecmdDataBufferBase  data(64);
-    
-    bool                poll_failure = false;
-    uint32_t            p;
-    
-    uint8_t             ec_has_pba_slvrest_bug = 0;
-    uint8_t             attr_mpipl = 0;
-
-
-    // Tell PBA to reset the slave, then poll for completion with timeout.
-    // The PBA is always polled at least twice to guarantee that we always
-    // poll once after a timeout.
-    
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_HW_BUG_PBASLVRESET,
-                                   &i_target,
-                                   ec_has_pba_slvrest_bug);
-        if(rc)
-        {
-     	    FAPI_ERR("Error querying Chip EC feature: "
-                     "ATTR_CHIP_EC_FEATURE_HW_BUG_PBASLVRESET");
-            break;
-        }
-        
-        rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, attr_mpipl);
-        if(rc)
-        {
-     	    FAPI_ERR("Error querying attribute ATTR_IS_MPIPL");
-            break;
-        }
-
-        psr.value = 0;
-        psr.fields.set = PBA_SLVRST_SET(id);
-
-        FAPI_DBG("  PBA_SLVRST%x: 0x%16llx", id, psr.value);
-
-        e_rc |= data.setDoubleWord(0, psr.value);
-        if(e_rc)
-        {
-            FAPI_ERR("Error (0x%x) manipulating ecmdDataBufferBase for PBA_SLVRST", e_rc);
-            rc.setEcmdError(e_rc);
-            return rc;
-        }
-
-        rc = fapiPutScom(i_target, PBA_SLVRST_0x00064001, data);
-        if (rc)
-        {
-            FAPI_ERR("Put SCOM error for PBA Slave Reset");
-            break;
-        }
-        
-        // Due to HW228485, skip the check of the in-progress bits for MPIPL 
-        // (after the PBA channels have been used at runtime) as they
-        // are unreliable in Murano 1.x.
-        if (attr_mpipl && ec_has_pba_slvrest_bug)
-        {
-            FAPI_INF("PBA Reset Polling being skipped due to MPIPL on a chip with PBA reset bug");
-        }
-        else
-        {                                          
-            poll_failure = true;
-            for (p=0; p<MAX_PBA_RESET_POLLS; p++)
-            {
-                // Read the reset register to check for reset completion
-                rc = fapiGetScom(i_target, PBA_SLVRST_0x00064001 , data);
-                if (rc)
-                {
-                     FAPI_ERR("fapiGetPutScom( PBA_SLVRST_0x00064001 ) failed. With rc = 0x%x", (uint32_t)rc);
-                     break;
-                }
-                FAPI_DBG("Slave %x reset poll data = 0x%016llX", id, data.getDoubleWord(0));
-
-                // If slave reset in progress, wait and then poll
-                if (data.isBitClear(4+id))
-                {
-                    FAPI_INF("PBA Reset complete for Slave %d", id);
-                    poll_failure = false;
-                    break;
-                }
-                else
-                {
-                    rc = fapiDelay(PBA_RESET_POLL_DELAY*1000, 200000);   // In microseconds
-                    if (rc)
-                    {
-                         FAPI_ERR("fapiDelay failed. With rc = 0x%x", (uint32_t)rc);
-                         break;
-                    }
-                }
-            } 
-
-            // Error exit from above loop
-            if (!rc.ok())
-            {
-                 break;
-            }
-
-            if (poll_failure)
-            {
-                 FAPI_ERR("PBA Slave Reset Timout");
-                 const fapi::Target & CHIP = i_target;
-                 const uint32_t     & POLLCOUNT = MAX_PBA_RESET_POLLS;
-                 const uint32_t     & POLLVALUE = PBA_RESET_POLL_DELAY;
-                 const uint64_t     & PSR = data.getDoubleWord(0);
-                 const uint32_t     & SLVID = id;
-	             FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PBA_SLVRST_TIMED_OUT);
-                 break;
-            }
-        }
-    } while(0);
-    return rc;
-}
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.H
deleted file mode 100644
index c32581113..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.H
+++ /dev/null
@@ -1,126 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_set_pore_bar.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_set_pore_bar.H,v 1.2 2014/11/07 18:27:55 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_set_pore_bar.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_set_pore_bar.H
-// *! DESCRIPTION : Establish the BAR setup for the SLW image in the PBA as
-// *!               well as setting up the SLW engine with table base address
-// *!               and memory relocation regs in the SLW
-// *!
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Jim Yacynych  Email: jimyac@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_SET_PORE_BAR_H_
-#define _PROC_SET_PORE_BAR_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*p8_set_pore_bar_FP_t) (const fapi::Target&, 
-                                                    void*, 
-                                                    uint64_t,
-                                                    uint64_t,
-                                                    uint32_t                                                    
-                                                    );
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-enum PORE_SLW_LOC {
-        SLW_MEMORY  = 0x0,
-        SLW_L3      = 0x1,
-        SLW_SRAM    = 0x2
-        };
-
-// The value here will yield the appropriate nibble for accessing the PowerBus
-// Regions (eg 0:1 = 00) when added to 0x8 (the SLW image effective address upper 
-// nibble) - 4 bit math only.
-enum PORE_SLW_PBA_BAR {
-        PBA_SLW_BAR0    = 0x8,  // 0x8 + 0x8 = 0x0
-        PBA_SLW_BAR1    = 0x9,  // 0x8 + 0x9 = 0x1
-        PBA_SLW_BAR2    = 0xA,  // 0x8 + 0xA = 0x2
-        PBA_SLW_BAR3    = 0xB   // 0x8 + 0xB = 0x3
-        };
-       
-enum PORE_PBA_BAR {
-        PBA_BAR0    = 0x0,
-        PBA_BAR1    = 0x1,
-        PBA_BAR2    = 0x2,
-        PBA_BAR3    = 0x3
-        };
-        
-enum PORE_PBA_SLAVE {
-        PBA_SLAVE0    = 0x0,
-        PBA_SLAVE1    = 0x1,
-        PBA_SLAVE2    = 0x2,
-        PBA_SLAVE3    = 0x3
-        };
-
-//------------------------------------------------------------------------------
-// Parameter structure definitions
-//------------------------------------------------------------------------------
-
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-/// \param[in] i_target     Procesor Chip target
-/// \param[in] i_image      Platform memory pointer where image is
-///                         located
-/// \param[in] i_mem_bar    Base address of the region where image is located
-/// \param[in] i_mem_size   Size (in MB) of the region where image is located
-///                         if not a power of two value, the value will be 
-///                         rounded up to the next power of 2 for setting the 
-///                         hardware mask
-/// \param[in] i_mem_type   Defines where the SLW image was loaded.  See
-///                         p8_set_pore_bar.H enum for valid values.
-
-fapi::ReturnCode 
-p8_set_pore_bar(  const fapi::Target& i_target, 
-                    void *i_image, 
-                    uint64_t i_mem_bar, 
-                    uint64_t i_mem_size, 
-                    uint32_t i_mem_type);
-
-
-} // extern "C"
-
-#endif // _PROC_SET_PORE_BAR_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_register.H b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_register.H
deleted file mode 100644
index 1553651e2..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_register.H
+++ /dev/null
@@ -1,1436 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_register.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// Subversion Repositories OCC
-// (root)/ssx/trunk/pgp/registers/pba_firmware_registers.h - Rev 1095
-// Rev
-
-// Rev 1077 | Blame | Compare with Previous | Last modification | View Log | RSS feed
-#ifndef __PBA_FIRMWARE_REGISTERS_H__
-#define __PBA_FIRMWARE_REGISTERS_H__
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-// $Id: pba_firmware_register.H,v 1.1 2012/01/09 13:46:34 kgungl Exp $
-
-/// \file pba_firmware_registers.h
-/// \brief C register structs for the PBA unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#include <stdint.h>
-
-
-typedef union pba_barn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t cmd_scope : 3;
-        uint64_t reserved0 : 1;
-        uint64_t reserved1 : 10;
-        uint64_t addr : 30;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t addr : 30;
-        uint64_t reserved1 : 10;
-        uint64_t reserved0 : 1;
-        uint64_t cmd_scope : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_barn_t;
-
-
-
-typedef union pba_barmskn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t reserved0 : 23;
-        uint64_t mask : 21;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t mask : 21;
-        uint64_t reserved0 : 23;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_barmskn_t;
-
-
-
-typedef union pba_fir {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t oci_apar_err : 1;
-        uint64_t pb_rdadrerr_fw : 1;
-        uint64_t pb_rddatato_fw : 1;
-        uint64_t pb_sue_fw : 1;
-        uint64_t pb_ue_fw : 1;
-        uint64_t pb_ce_fw : 1;
-        uint64_t oci_slave_init : 1;
-        uint64_t oci_wrpar_err : 1;
-        uint64_t oci_rereqto : 1;
-        uint64_t pb_unexpcresp : 1;
-        uint64_t pb_unexpdata : 1;
-        uint64_t pb_parity_err : 1;
-        uint64_t pb_wradrerr_fw : 1;
-        uint64_t pb_badcresp : 1;
-        uint64_t pb_ackdead_fw : 1;
-        uint64_t pb_crespto : 1;
-        uint64_t bcue_setup_err : 1;
-        uint64_t bcue_pb_ack_dead : 1;
-        uint64_t bcue_pb_adrerr : 1;
-        uint64_t bcue_oci_dataerr : 1;
-        uint64_t bcde_setup_err : 1;
-        uint64_t bcde_pb_ack_dead : 1;
-        uint64_t bcde_pb_adrerr : 1;
-        uint64_t bcde_rddatato_err : 1;
-        uint64_t bcde_sue_err : 1;
-        uint64_t bcde_ue_err : 1;
-        uint64_t bcde_ce : 1;
-        uint64_t bcde_oci_dataerr : 1;
-        uint64_t internal_err : 1;
-        uint64_t illegal_cache_op : 1;
-        uint64_t oci_bad_reg_addr : 1;
-        uint64_t axpush_wrerr : 1;
-        uint64_t axrcv_dlo_err : 1;
-        uint64_t axrcv_dlo_to : 1;
-        uint64_t axrcv_rsvdata_to : 1;
-        uint64_t axflow_err : 1;
-        uint64_t axsnd_dhi_rtyto : 1;
-        uint64_t axsnd_dlo_rtyto : 1;
-        uint64_t axsnd_rsvto : 1;
-        uint64_t axsnd_rsverr : 1;
-        uint64_t reserved : 4;
-        uint64_t fir_parity_error : 1;
-        uint64_t _reserved0 : 19;
-#else
-        uint64_t _reserved0 : 19;
-        uint64_t fir_parity_error : 1;
-        uint64_t reserved : 4;
-        uint64_t axsnd_rsverr : 1;
-        uint64_t axsnd_rsvto : 1;
-        uint64_t axsnd_dlo_rtyto : 1;
-        uint64_t axsnd_dhi_rtyto : 1;
-        uint64_t axflow_err : 1;
-        uint64_t axrcv_rsvdata_to : 1;
-        uint64_t axrcv_dlo_to : 1;
-        uint64_t axrcv_dlo_err : 1;
-        uint64_t axpush_wrerr : 1;
-        uint64_t oci_bad_reg_addr : 1;
-        uint64_t illegal_cache_op : 1;
-        uint64_t internal_err : 1;
-        uint64_t bcde_oci_dataerr : 1;
-        uint64_t bcde_ce : 1;
-        uint64_t bcde_ue_err : 1;
-        uint64_t bcde_sue_err : 1;
-        uint64_t bcde_rddatato_err : 1;
-        uint64_t bcde_pb_adrerr : 1;
-        uint64_t bcde_pb_ack_dead : 1;
-        uint64_t bcde_setup_err : 1;
-        uint64_t bcue_oci_dataerr : 1;
-        uint64_t bcue_pb_adrerr : 1;
-        uint64_t bcue_pb_ack_dead : 1;
-        uint64_t bcue_setup_err : 1;
-        uint64_t pb_crespto : 1;
-        uint64_t pb_ackdead_fw : 1;
-        uint64_t pb_badcresp : 1;
-        uint64_t pb_wradrerr_fw : 1;
-        uint64_t pb_parity_err : 1;
-        uint64_t pb_unexpdata : 1;
-        uint64_t pb_unexpcresp : 1;
-        uint64_t oci_rereqto : 1;
-        uint64_t oci_wrpar_err : 1;
-        uint64_t oci_slave_init : 1;
-        uint64_t pb_ce_fw : 1;
-        uint64_t pb_ue_fw : 1;
-        uint64_t pb_sue_fw : 1;
-        uint64_t pb_rddatato_fw : 1;
-        uint64_t pb_rdadrerr_fw : 1;
-        uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_t;
-
-
-
-typedef union pba_fir_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t oci_apar_err : 1;
-        uint64_t pb_rdadrerr_fw : 1;
-        uint64_t pb_rddatato_fw : 1;
-        uint64_t pb_sue_fw : 1;
-        uint64_t pb_ue_fw : 1;
-        uint64_t pb_ce_fw : 1;
-        uint64_t oci_slave_init : 1;
-        uint64_t oci_wrpar_err : 1;
-        uint64_t oci_rereqto : 1;
-        uint64_t pb_unexpcresp : 1;
-        uint64_t pb_unexpdata : 1;
-        uint64_t pb_parity_err : 1;
-        uint64_t pb_wradrerr_fw : 1;
-        uint64_t pb_badcresp : 1;
-        uint64_t pb_ackdead_fw : 1;
-        uint64_t pb_crespto : 1;
-        uint64_t bcue_setup_err : 1;
-        uint64_t bcue_pb_ack_dead : 1;
-        uint64_t bcue_pb_adrerr : 1;
-        uint64_t bcue_oci_dataerr : 1;
-        uint64_t bcde_setup_err : 1;
-        uint64_t bcde_pb_ack_dead : 1;
-        uint64_t bcde_pb_adrerr : 1;
-        uint64_t bcde_rddatato_err : 1;
-        uint64_t bcde_sue_err : 1;
-        uint64_t bcde_ue_err : 1;
-        uint64_t bcde_ce : 1;
-        uint64_t bcde_oci_dataerr : 1;
-        uint64_t internal_err : 1;
-        uint64_t illegal_cache_op : 1;
-        uint64_t oci_bad_reg_addr : 1;
-        uint64_t axpush_wrerr : 1;
-        uint64_t axrcv_dlo_err : 1;
-        uint64_t axrcv_dlo_to : 1;
-        uint64_t axrcv_rsvdata_to : 1;
-        uint64_t axflow_err : 1;
-        uint64_t axsnd_dhi_rtyto : 1;
-        uint64_t axsnd_dlo_rtyto : 1;
-        uint64_t axsnd_rsvto : 1;
-        uint64_t axsnd_rsverr : 1;
-        uint64_t reserved : 4;
-        uint64_t fir_parity_error : 1;
-        uint64_t _reserved0 : 19;
-#else
-        uint64_t _reserved0 : 19;
-        uint64_t fir_parity_error : 1;
-        uint64_t reserved : 4;
-        uint64_t axsnd_rsverr : 1;
-        uint64_t axsnd_rsvto : 1;
-        uint64_t axsnd_dlo_rtyto : 1;
-        uint64_t axsnd_dhi_rtyto : 1;
-        uint64_t axflow_err : 1;
-        uint64_t axrcv_rsvdata_to : 1;
-        uint64_t axrcv_dlo_to : 1;
-        uint64_t axrcv_dlo_err : 1;
-        uint64_t axpush_wrerr : 1;
-        uint64_t oci_bad_reg_addr : 1;
-        uint64_t illegal_cache_op : 1;
-        uint64_t internal_err : 1;
-        uint64_t bcde_oci_dataerr : 1;
-        uint64_t bcde_ce : 1;
-        uint64_t bcde_ue_err : 1;
-        uint64_t bcde_sue_err : 1;
-        uint64_t bcde_rddatato_err : 1;
-        uint64_t bcde_pb_adrerr : 1;
-        uint64_t bcde_pb_ack_dead : 1;
-        uint64_t bcde_setup_err : 1;
-        uint64_t bcue_oci_dataerr : 1;
-        uint64_t bcue_pb_adrerr : 1;
-        uint64_t bcue_pb_ack_dead : 1;
-        uint64_t bcue_setup_err : 1;
-        uint64_t pb_crespto : 1;
-        uint64_t pb_ackdead_fw : 1;
-        uint64_t pb_badcresp : 1;
-        uint64_t pb_wradrerr_fw : 1;
-        uint64_t pb_parity_err : 1;
-        uint64_t pb_unexpdata : 1;
-        uint64_t pb_unexpcresp : 1;
-        uint64_t oci_rereqto : 1;
-        uint64_t oci_wrpar_err : 1;
-        uint64_t oci_slave_init : 1;
-        uint64_t pb_ce_fw : 1;
-        uint64_t pb_ue_fw : 1;
-        uint64_t pb_sue_fw : 1;
-        uint64_t pb_rddatato_fw : 1;
-        uint64_t pb_rdadrerr_fw : 1;
-        uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_and_t;
-
-
-
-typedef union pba_fir_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t oci_apar_err : 1;
-        uint64_t pb_rdadrerr_fw : 1;
-        uint64_t pb_rddatato_fw : 1;
-        uint64_t pb_sue_fw : 1;
-        uint64_t pb_ue_fw : 1;
-        uint64_t pb_ce_fw : 1;
-        uint64_t oci_slave_init : 1;
-        uint64_t oci_wrpar_err : 1;
-        uint64_t oci_rereqto : 1;
-        uint64_t pb_unexpcresp : 1;
-        uint64_t pb_unexpdata : 1;
-        uint64_t pb_parity_err : 1;
-        uint64_t pb_wradrerr_fw : 1;
-        uint64_t pb_badcresp : 1;
-        uint64_t pb_ackdead_fw : 1;
-        uint64_t pb_crespto : 1;
-        uint64_t bcue_setup_err : 1;
-        uint64_t bcue_pb_ack_dead : 1;
-        uint64_t bcue_pb_adrerr : 1;
-        uint64_t bcue_oci_dataerr : 1;
-        uint64_t bcde_setup_err : 1;
-        uint64_t bcde_pb_ack_dead : 1;
-        uint64_t bcde_pb_adrerr : 1;
-        uint64_t bcde_rddatato_err : 1;
-        uint64_t bcde_sue_err : 1;
-        uint64_t bcde_ue_err : 1;
-        uint64_t bcde_ce : 1;
-        uint64_t bcde_oci_dataerr : 1;
-        uint64_t internal_err : 1;
-        uint64_t illegal_cache_op : 1;
-        uint64_t oci_bad_reg_addr : 1;
-        uint64_t axpush_wrerr : 1;
-        uint64_t axrcv_dlo_err : 1;
-        uint64_t axrcv_dlo_to : 1;
-        uint64_t axrcv_rsvdata_to : 1;
-        uint64_t axflow_err : 1;
-        uint64_t axsnd_dhi_rtyto : 1;
-        uint64_t axsnd_dlo_rtyto : 1;
-        uint64_t axsnd_rsvto : 1;
-        uint64_t axsnd_rsverr : 1;
-        uint64_t reserved : 4;
-        uint64_t fir_parity_error : 1;
-        uint64_t _reserved0 : 19;
-#else
-        uint64_t _reserved0 : 19;
-        uint64_t fir_parity_error : 1;
-        uint64_t reserved : 4;
-        uint64_t axsnd_rsverr : 1;
-        uint64_t axsnd_rsvto : 1;
-        uint64_t axsnd_dlo_rtyto : 1;
-        uint64_t axsnd_dhi_rtyto : 1;
-        uint64_t axflow_err : 1;
-        uint64_t axrcv_rsvdata_to : 1;
-        uint64_t axrcv_dlo_to : 1;
-        uint64_t axrcv_dlo_err : 1;
-        uint64_t axpush_wrerr : 1;
-        uint64_t oci_bad_reg_addr : 1;
-        uint64_t illegal_cache_op : 1;
-        uint64_t internal_err : 1;
-        uint64_t bcde_oci_dataerr : 1;
-        uint64_t bcde_ce : 1;
-        uint64_t bcde_ue_err : 1;
-        uint64_t bcde_sue_err : 1;
-        uint64_t bcde_rddatato_err : 1;
-        uint64_t bcde_pb_adrerr : 1;
-        uint64_t bcde_pb_ack_dead : 1;
-        uint64_t bcde_setup_err : 1;
-        uint64_t bcue_oci_dataerr : 1;
-        uint64_t bcue_pb_adrerr : 1;
-        uint64_t bcue_pb_ack_dead : 1;
-        uint64_t bcue_setup_err : 1;
-        uint64_t pb_crespto : 1;
-        uint64_t pb_ackdead_fw : 1;
-        uint64_t pb_badcresp : 1;
-        uint64_t pb_wradrerr_fw : 1;
-        uint64_t pb_parity_err : 1;
-        uint64_t pb_unexpdata : 1;
-        uint64_t pb_unexpcresp : 1;
-        uint64_t oci_rereqto : 1;
-        uint64_t oci_wrpar_err : 1;
-        uint64_t oci_slave_init : 1;
-        uint64_t pb_ce_fw : 1;
-        uint64_t pb_ue_fw : 1;
-        uint64_t pb_sue_fw : 1;
-        uint64_t pb_rddatato_fw : 1;
-        uint64_t pb_rdadrerr_fw : 1;
-        uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_or_t;
-
-
-
-typedef union pba_fir_mask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t mask : 44;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t mask : 44;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_mask_t;
-
-
-
-typedef union pba_fir_mask_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t mask : 44;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t mask : 44;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_mask_and_t;
-
-
-
-typedef union pba_fir_mask_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t mask : 44;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t mask : 44;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_mask_or_t;
-
-
-
-typedef union pba_fir_action0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t fir_action0 : 44;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t fir_action0 : 44;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_action0_t;
-
-
-
-typedef union pba_fir_action1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t fir_action1 : 44;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t fir_action1 : 44;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_action1_t;
-
-
-
-typedef union pba_occ_action {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t occ_action_set : 44;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t occ_action_set : 44;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_occ_action_t;
-
-
-
-typedef union pba_rbufvaln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t rd_slvnum : 2;
-        uint64_t cur_rd_addr : 23;
-        uint64_t spare1 : 3;
-        uint64_t prefetch : 1;
-        uint64_t spare2 : 2;
-        uint64_t abort : 1;
-        uint64_t spare3 : 1;
-        uint64_t buffer_status : 7;
-        uint64_t spare4 : 4;
-        uint64_t _reserved0 : 20;
-#else
-        uint64_t _reserved0 : 20;
-        uint64_t spare4 : 4;
-        uint64_t buffer_status : 7;
-        uint64_t spare3 : 1;
-        uint64_t abort : 1;
-        uint64_t spare2 : 2;
-        uint64_t prefetch : 1;
-        uint64_t spare1 : 3;
-        uint64_t cur_rd_addr : 23;
-        uint64_t rd_slvnum : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_rbufvaln_t;
-
-
-
-typedef union pba_wbufvaln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t wr_slvnum : 2;
-        uint64_t start_wr_addr : 30;
-        uint64_t spare1 : 3;
-        uint64_t wr_buffer_status : 5;
-        uint64_t spare2 : 1;
-        uint64_t wr_byte_count : 7;
-        uint64_t spare3 : 16;
-#else
-        uint64_t spare3 : 16;
-        uint64_t wr_byte_count : 7;
-        uint64_t spare2 : 1;
-        uint64_t wr_buffer_status : 5;
-        uint64_t spare1 : 3;
-        uint64_t start_wr_addr : 30;
-        uint64_t wr_slvnum : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_wbufvaln_t;
-
-
-
-typedef union pba_mode {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t reserved0 : 4;
-        uint64_t dis_rearb : 1;
-        uint64_t reserved1 : 1;
-        uint64_t dis_slave_rdpipe : 1;
-        uint64_t dis_slave_wrpipe : 1;
-        uint64_t en_marker_ack : 1;
-        uint64_t dis_slvmatch_order : 1;
-        uint64_t en_second_wrbuf : 1;
-        uint64_t dis_rerequest_to : 1;
-        uint64_t inject_type : 2;
-        uint64_t inject_mode : 2;
-        uint64_t pba_region : 2;
-        uint64_t oci_marker_space : 3;
-        uint64_t bcde_ocitrans : 2;
-        uint64_t bcue_ocitrans : 2;
-        uint64_t dis_master_rd_pipe : 1;
-        uint64_t dis_master_wr_pipe : 1;
-        uint64_t en_slave_fairness : 1;
-        uint64_t en_ecvent_count : 1;
-        uint64_t pb_noci_event_sel : 1;
-        uint64_t slv_event_mux : 2;
-        uint64_t enable_debug_bus : 1;
-        uint64_t debug_pb_not_oci : 1;
-        uint64_t debug_oci_mode : 5;
-        uint64_t reserved2 : 1;
-        uint64_t ocislv_fairness_mask : 5;
-        uint64_t ocislv_rereq_hang_div : 5;
-        uint64_t dis_chgrate_count : 1;
-        uint64_t pbreq_event_mux : 2;
-        uint64_t _reserved0 : 11;
-#else
-        uint64_t _reserved0 : 11;
-        uint64_t pbreq_event_mux : 2;
-        uint64_t dis_chgrate_count : 1;
-        uint64_t ocislv_rereq_hang_div : 5;
-        uint64_t ocislv_fairness_mask : 5;
-        uint64_t reserved2 : 1;
-        uint64_t debug_oci_mode : 5;
-        uint64_t debug_pb_not_oci : 1;
-        uint64_t enable_debug_bus : 1;
-        uint64_t slv_event_mux : 2;
-        uint64_t pb_noci_event_sel : 1;
-        uint64_t en_ecvent_count : 1;
-        uint64_t en_slave_fairness : 1;
-        uint64_t dis_master_wr_pipe : 1;
-        uint64_t dis_master_rd_pipe : 1;
-        uint64_t bcue_ocitrans : 2;
-        uint64_t bcde_ocitrans : 2;
-        uint64_t oci_marker_space : 3;
-        uint64_t pba_region : 2;
-        uint64_t inject_mode : 2;
-        uint64_t inject_type : 2;
-        uint64_t dis_rerequest_to : 1;
-        uint64_t en_second_wrbuf : 1;
-        uint64_t dis_slvmatch_order : 1;
-        uint64_t en_marker_ack : 1;
-        uint64_t dis_slave_wrpipe : 1;
-        uint64_t dis_slave_rdpipe : 1;
-        uint64_t reserved1 : 1;
-        uint64_t dis_rearb : 1;
-        uint64_t reserved0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_mode_t;
-
-
-
-typedef union pba_slvrst {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t set : 3;
-        uint64_t notimp1 : 1;
-        uint64_t in_prog : 4;
-        uint64_t busy_status : 4;
-        uint64_t _reserved0 : 52;
-#else
-        uint64_t _reserved0 : 52;
-        uint64_t busy_status : 4;
-        uint64_t in_prog : 4;
-        uint64_t notimp1 : 1;
-        uint64_t set : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_slvrst_t;
-
-
-
-typedef union pba_slvctln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t enable : 1;
-        uint64_t mid_match_value : 3;
-        uint64_t _reserved0 : 1;
-        uint64_t mid_care_mask : 3;
-        uint64_t write_ttype : 3;
-        uint64_t _reserved1 : 4;
-        uint64_t read_ttype : 1;
-        uint64_t read_prefetch_ctl : 2;
-        uint64_t buf_invalidate_ctl : 1;
-        uint64_t buf_alloc_w : 1;
-        uint64_t buf_alloc_a : 1;
-        uint64_t buf_alloc_b : 1;
-        uint64_t buf_alloc_c : 1;
-        uint64_t _reserved2 : 1;
-        uint64_t dis_write_gather : 1;
-        uint64_t wr_gather_timeout : 3;
-        uint64_t write_tsize : 7;
-        uint64_t extaddr : 14;
-        uint64_t _reserved3 : 15;
-#else
-        uint64_t _reserved3 : 15;
-        uint64_t extaddr : 14;
-        uint64_t write_tsize : 7;
-        uint64_t wr_gather_timeout : 3;
-        uint64_t dis_write_gather : 1;
-        uint64_t _reserved2 : 1;
-        uint64_t buf_alloc_c : 1;
-        uint64_t buf_alloc_b : 1;
-        uint64_t buf_alloc_a : 1;
-        uint64_t buf_alloc_w : 1;
-        uint64_t buf_invalidate_ctl : 1;
-        uint64_t read_prefetch_ctl : 2;
-        uint64_t read_ttype : 1;
-        uint64_t _reserved1 : 4;
-        uint64_t write_ttype : 3;
-        uint64_t mid_care_mask : 3;
-        uint64_t _reserved0 : 1;
-        uint64_t mid_match_value : 3;
-        uint64_t enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_slvctln_t;
-
-
-
-typedef union pba_bcde_ctl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t stop : 1;
-        uint64_t start : 1;
-        uint64_t _reserved0 : 62;
-#else
-        uint64_t _reserved0 : 62;
-        uint64_t start : 1;
-        uint64_t stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_ctl_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_bcde_set {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t _reserved0 : 2;
-        uint64_t copy_length : 6;
-        uint64_t _reserved1 : 56;
-#else
-        uint64_t _reserved1 : 56;
-        uint64_t copy_length : 6;
-        uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_set_t;
-
-
-
-typedef union pba_bcde_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t running : 1;
-        uint64_t waiting : 1;
-        uint64_t wrcmp : 6;
-        uint64_t _reserved0 : 6;
-        uint64_t rdcmp : 6;
-        uint64_t debug : 9;
-        uint64_t stopped : 1;
-        uint64_t error : 1;
-        uint64_t done : 1;
-        uint64_t _reserved1 : 32;
-#else
-        uint64_t _reserved1 : 32;
-        uint64_t done : 1;
-        uint64_t error : 1;
-        uint64_t stopped : 1;
-        uint64_t debug : 9;
-        uint64_t rdcmp : 6;
-        uint64_t _reserved0 : 6;
-        uint64_t wrcmp : 6;
-        uint64_t waiting : 1;
-        uint64_t running : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_status_t;
-
-
-
-typedef union pba_bcde_pbadr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t _reserved0 : 2;
-        uint64_t pb_offset : 23;
-        uint64_t _reserved1 : 2;
-        uint64_t extaddr : 14;
-        uint64_t _reserved2 : 23;
-#else
-        uint64_t _reserved2 : 23;
-        uint64_t extaddr : 14;
-        uint64_t _reserved1 : 2;
-        uint64_t pb_offset : 23;
-        uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_pbadr_t;
-
-
-
-typedef union pba_bcde_ocibar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t addr : 25;
-        uint64_t _reserved0 : 39;
-#else
-        uint64_t _reserved0 : 39;
-        uint64_t addr : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_ocibar_t;
-
-
-
-typedef union pba_bcue_ctl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t stop : 1;
-        uint64_t start : 1;
-        uint64_t _reserved0 : 62;
-#else
-        uint64_t _reserved0 : 62;
-        uint64_t start : 1;
-        uint64_t stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_ctl_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_bcue_set {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t _reserved0 : 2;
-        uint64_t copy_length : 6;
-        uint64_t _reserved1 : 56;
-#else
-        uint64_t _reserved1 : 56;
-        uint64_t copy_length : 6;
-        uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_set_t;
-
-
-
-typedef union pba_bcue_status {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t running : 1;
-        uint64_t waiting : 1;
-        uint64_t wrcmp : 6;
-        uint64_t _reserved0 : 6;
-        uint64_t rdcmp : 6;
-        uint64_t debug : 9;
-        uint64_t stopped : 1;
-        uint64_t error : 1;
-        uint64_t done : 1;
-        uint64_t _reserved1 : 32;
-#else
-        uint64_t _reserved1 : 32;
-        uint64_t done : 1;
-        uint64_t error : 1;
-        uint64_t stopped : 1;
-        uint64_t debug : 9;
-        uint64_t rdcmp : 6;
-        uint64_t _reserved0 : 6;
-        uint64_t wrcmp : 6;
-        uint64_t waiting : 1;
-        uint64_t running : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_status_t;
-
-
-
-typedef union pba_bcue_pbadr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t _reserved0 : 2;
-        uint64_t pb_offset : 23;
-        uint64_t _reserved1 : 2;
-        uint64_t extaddr : 14;
-        uint64_t _reserved2 : 23;
-#else
-        uint64_t _reserved2 : 23;
-        uint64_t extaddr : 14;
-        uint64_t _reserved1 : 2;
-        uint64_t pb_offset : 23;
-        uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_pbadr_t;
-
-
-
-typedef union pba_bcue_ocibar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t addr : 25;
-        uint64_t _reserved0 : 39;
-#else
-        uint64_t _reserved0 : 39;
-        uint64_t addr : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_ocibar_t;
-
-
-
-typedef union pba_pbocrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t _reserved0 : 16;
-        uint64_t event : 16;
-        uint64_t _reserved1 : 12;
-        uint64_t accum : 20;
-#else
-        uint64_t accum : 20;
-        uint64_t _reserved1 : 12;
-        uint64_t event : 16;
-        uint64_t _reserved0 : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_pbocrn_t;
-
-
-
-typedef union pba_xsndtx {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t snd_scope : 3;
-        uint64_t snd_qid : 1;
-        uint64_t snd_type : 1;
-        uint64_t snd_reservation : 1;
-        uint64_t spare1 : 2;
-        uint64_t snd_nodeid : 3;
-        uint64_t snd_chipid : 3;
-        uint64_t spare2 : 2;
-        uint64_t _reserved0 : 48;
-#else
-        uint64_t _reserved0 : 48;
-        uint64_t spare2 : 2;
-        uint64_t snd_chipid : 3;
-        uint64_t snd_nodeid : 3;
-        uint64_t spare1 : 2;
-        uint64_t snd_reservation : 1;
-        uint64_t snd_type : 1;
-        uint64_t snd_qid : 1;
-        uint64_t snd_scope : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsndtx_t;
-
-
-
-typedef union pba_xcfg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t pbax_en : 1;
-        uint64_t reservation_en : 1;
-        uint64_t snd_reset : 1;
-        uint64_t rcv_reset : 1;
-        uint64_t rcv_nodeid : 3;
-        uint64_t rcv_chipid : 3;
-        uint64_t spare1 : 2;
-        uint64_t rcv_brdcst_group : 8;
-        uint64_t rcv_datalo_thresh : 8;
-        uint64_t snd_retry_thresh : 8;
-        uint64_t snd_rsv_req_thresh : 2;
-        uint64_t snd_retry_count_overcom : 1;
-        uint64_t _reserved0 : 25;
-#else
-        uint64_t _reserved0 : 25;
-        uint64_t snd_retry_count_overcom : 1;
-        uint64_t snd_rsv_req_thresh : 2;
-        uint64_t snd_retry_thresh : 8;
-        uint64_t rcv_datalo_thresh : 8;
-        uint64_t rcv_brdcst_group : 8;
-        uint64_t spare1 : 2;
-        uint64_t rcv_chipid : 3;
-        uint64_t rcv_nodeid : 3;
-        uint64_t rcv_reset : 1;
-        uint64_t snd_reset : 1;
-        uint64_t reservation_en : 1;
-        uint64_t pbax_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xcfg_t;
-
-
-
-typedef union pba_xsndstat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t snd_in_progress : 1;
-        uint64_t snd_error : 1;
-        uint64_t snd_status : 6;
-        uint64_t snd_retry_count : 8;
-        uint64_t _reserved0 : 48;
-#else
-        uint64_t _reserved0 : 48;
-        uint64_t snd_retry_count : 8;
-        uint64_t snd_status : 6;
-        uint64_t snd_error : 1;
-        uint64_t snd_in_progress : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsndstat_t;
-
-
-
-typedef union pba_xsnddat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t pbax_datahi : 32;
-        uint64_t pbax_datalo : 32;
-#else
-        uint64_t pbax_datalo : 32;
-        uint64_t pbax_datahi : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsnddat_t;
-
-
-
-typedef union pba_xrcvstat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t rcv_in_progress : 1;
-        uint64_t rcv_error : 1;
-        uint64_t rcv_write_in_progress : 1;
-        uint64_t rcv_reservation_set : 1;
-        uint64_t rcv_capture : 14;
-        uint64_t _reserved0 : 46;
-#else
-        uint64_t _reserved0 : 46;
-        uint64_t rcv_capture : 14;
-        uint64_t rcv_reservation_set : 1;
-        uint64_t rcv_write_in_progress : 1;
-        uint64_t rcv_error : 1;
-        uint64_t rcv_in_progress : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xrcvstat_t;
-
-
-
-typedef union pba_xshbrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t push_start : 29;
-        uint64_t _reserved0 : 35;
-#else
-        uint64_t _reserved0 : 35;
-        uint64_t push_start : 29;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshbrn_t;
-
-
-
-typedef union pba_xshcsn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t push_full : 1;
-        uint64_t push_empty : 1;
-        uint64_t spare1 : 2;
-        uint64_t push_intr_action : 2;
-        uint64_t push_length : 5;
-        uint64_t notimp1 : 2;
-        uint64_t push_write_ptr : 5;
-        uint64_t notimp2 : 3;
-        uint64_t push_read_ptr : 5;
-        uint64_t notimp3 : 5;
-        uint64_t push_enable : 1;
-        uint64_t _reserved0 : 32;
-#else
-        uint64_t _reserved0 : 32;
-        uint64_t push_enable : 1;
-        uint64_t notimp3 : 5;
-        uint64_t push_read_ptr : 5;
-        uint64_t notimp2 : 3;
-        uint64_t push_write_ptr : 5;
-        uint64_t notimp1 : 2;
-        uint64_t push_length : 5;
-        uint64_t push_intr_action : 2;
-        uint64_t spare1 : 2;
-        uint64_t push_empty : 1;
-        uint64_t push_full : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshcsn_t;
-
-
-
-typedef union pba_xshincn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint64_t reserved : 64;
-#else
-        uint64_t reserved : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshincn_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PBA_FIRMWARE_REGISTERS_H__
-
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_registers.h b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_registers.h
deleted file mode 100644
index 1d0e60340..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_registers.h
+++ /dev/null
@@ -1,2107 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pba_firmware_registers.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __PBA_FIRMWARE_REGISTERS_H__
-#define __PBA_FIRMWARE_REGISTERS_H__
-
-#ifndef SIXTYFOUR_BIT_CONSTANT
-#ifdef __ASSEMBLER__
-#define SIXTYFOUR_BIT_CONSTANT(x) x
-#else
-#define SIXTYFOUR_BIT_CONSTANT(x) x##ull
-#endif
-#endif
-
-#ifndef __ASSEMBLER__
-
-// $Id$
-
-/// \file pba_firmware_registers.h
-/// \brief C register structs for the PBA unit
-
-// *** WARNING *** - This file is generated automatically, do not edit.
-
-#include <stdint.h>
-
-
-
-typedef union pba_barn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t cmd_scope : 3;
-	uint64_t reserved0 : 1;
-	uint64_t reserved1 : 10;
-	uint64_t addr : 30;
-	uint64_t _reserved0 : 20;
-#else
-	uint64_t _reserved0 : 20;
-	uint64_t addr : 30;
-	uint64_t reserved1 : 10;
-	uint64_t reserved0 : 1;
-	uint64_t cmd_scope : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_barn_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000)
-#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_barmskn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved0 : 23;
-	uint64_t mask : 21;
-	uint64_t _reserved0 : 20;
-#else
-	uint64_t _reserved0 : 20;
-	uint64_t mask : 21;
-	uint64_t reserved0 : 23;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_barmskn_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_fir {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_t;
-
-#endif // __ASSEMBLER__
-#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000)
-#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000)
-#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000)
-#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000)
-#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000)
-#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000)
-#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000)
-#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000)
-#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000)
-#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000)
-#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000)
-#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000)
-#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000)
-#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000)
-#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000)
-#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000)
-#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000)
-#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000)
-#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000)
-#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000)
-#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000)
-#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000)
-#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000)
-#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000)
-#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000)
-#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000)
-#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000)
-#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000)
-#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000)
-#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000)
-#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000)
-#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000)
-#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000)
-#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000)
-#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000)
-#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000)
-#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000)
-#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000)
-#define PBA_FIR_FIR_PARITY_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000000080000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_fir_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_and_t;
-
-
-
-typedef union pba_fir_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_fir_or_t;
-
-
-
-typedef union pba_firmask {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firmask_t;
-
-
-
-typedef union pba_firmask_and {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firmask_and_t;
-
-
-
-typedef union pba_firmask_or {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firmask_or_t;
-
-
-
-typedef union pba_firact0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firact0_t;
-
-
-
-typedef union pba_firact1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_firact1_t;
-
-
-
-typedef union pba_occact {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t oci_apar_err : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t internal_err : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t reserved : 4;
-	uint64_t fir_parity_error : 1;
-	uint64_t _reserved0 : 19;
-#else
-	uint64_t _reserved0 : 19;
-	uint64_t fir_parity_error : 1;
-	uint64_t reserved : 4;
-	uint64_t axsnd_rsverr : 1;
-	uint64_t axsnd_rsvto : 1;
-	uint64_t axsnd_dlo_rtyto : 1;
-	uint64_t axsnd_dhi_rtyto : 1;
-	uint64_t axflow_err : 1;
-	uint64_t axrcv_rsvdata_to : 1;
-	uint64_t axrcv_dlo_to : 1;
-	uint64_t axrcv_dlo_err : 1;
-	uint64_t axpush_wrerr : 1;
-	uint64_t oci_bad_reg_addr : 1;
-	uint64_t illegal_cache_op : 1;
-	uint64_t internal_err : 1;
-	uint64_t bcde_oci_dataerr : 1;
-	uint64_t bcde_ce : 1;
-	uint64_t bcde_ue_err : 1;
-	uint64_t bcde_sue_err : 1;
-	uint64_t bcde_rddatato_err : 1;
-	uint64_t bcde_pb_adrerr : 1;
-	uint64_t bcde_pb_ack_dead : 1;
-	uint64_t bcde_setup_err : 1;
-	uint64_t bcue_oci_dataerr : 1;
-	uint64_t bcue_pb_adrerr : 1;
-	uint64_t bcue_pb_ack_dead : 1;
-	uint64_t bcue_setup_err : 1;
-	uint64_t pb_crespto : 1;
-	uint64_t pb_ackdead_fw : 1;
-	uint64_t pb_badcresp : 1;
-	uint64_t pb_wradrerr_fw : 1;
-	uint64_t pb_parity_err : 1;
-	uint64_t pb_unexpdata : 1;
-	uint64_t pb_unexpcresp : 1;
-	uint64_t oci_rereqto : 1;
-	uint64_t oci_wrpar_err : 1;
-	uint64_t oci_slave_init : 1;
-	uint64_t pb_ce_fw : 1;
-	uint64_t pb_ue_fw : 1;
-	uint64_t pb_sue_fw : 1;
-	uint64_t pb_rddatato_fw : 1;
-	uint64_t pb_rdadrerr_fw : 1;
-	uint64_t oci_apar_err : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_occact_t;
-
-
-
-typedef union pba_cfg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t writable : 48;
-	uint64_t _reserved0 : 16;
-#else
-	uint64_t _reserved0 : 16;
-	uint64_t writable : 48;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_cfg_t;
-
-
-
-typedef union pba_errpt0 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t cerr_pb_rddatato_fw : 6;
-	uint64_t cerr_pb_rdadrerr_fw : 6;
-	uint64_t cerr_pb_wradrerr_fw : 6;
-	uint64_t cerr_pb_ackdead_fw : 6;
-	uint64_t cerr_pb_unexpcresp : 11;
-	uint64_t cerr_pb_unexpdata : 6;
-	uint64_t _reserved0 : 23;
-#else
-	uint64_t _reserved0 : 23;
-	uint64_t cerr_pb_unexpdata : 6;
-	uint64_t cerr_pb_unexpcresp : 11;
-	uint64_t cerr_pb_ackdead_fw : 6;
-	uint64_t cerr_pb_wradrerr_fw : 6;
-	uint64_t cerr_pb_rdadrerr_fw : 6;
-	uint64_t cerr_pb_rddatato_fw : 6;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_errpt0_t;
-
-
-
-typedef union pba_errpt1 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t cerr_pb_badcresp : 12;
-	uint64_t cerr_pb_crespto : 12;
-	uint64_t cerr_oci_rereqto : 6;
-	uint64_t cerr_bcde_setup_err : 2;
-	uint64_t cerr_bcue_setup_err : 2;
-	uint64_t cerr_bcue_oci_dataerr : 2;
-	uint64_t _reserved0 : 28;
-#else
-	uint64_t _reserved0 : 28;
-	uint64_t cerr_bcue_oci_dataerr : 2;
-	uint64_t cerr_bcue_setup_err : 2;
-	uint64_t cerr_bcde_setup_err : 2;
-	uint64_t cerr_oci_rereqto : 6;
-	uint64_t cerr_pb_crespto : 12;
-	uint64_t cerr_pb_badcresp : 12;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_errpt1_t;
-
-
-
-typedef union pba_errpt2 {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t cerr_slv_internal_err : 8;
-	uint64_t cerr_bcde_internal_err : 4;
-	uint64_t cerr_bcue_internal_err : 4;
-	uint64_t cerr_bar_parity_err : 4;
-	uint64_t cerr_pbdout_parity_err : 1;
-	uint64_t cerr_pb_parity_err : 3;
-	uint64_t cerr_axflow_err : 5;
-	uint64_t cerr_axpush_wrerr : 2;
-	uint64_t _reserved0 : 33;
-#else
-	uint64_t _reserved0 : 33;
-	uint64_t cerr_axpush_wrerr : 2;
-	uint64_t cerr_axflow_err : 5;
-	uint64_t cerr_pb_parity_err : 3;
-	uint64_t cerr_pbdout_parity_err : 1;
-	uint64_t cerr_bar_parity_err : 4;
-	uint64_t cerr_bcue_internal_err : 4;
-	uint64_t cerr_bcde_internal_err : 4;
-	uint64_t cerr_slv_internal_err : 8;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_errpt2_t;
-
-
-
-typedef union pba_rbufvaln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t rd_slvnum : 2;
-	uint64_t cur_rd_addr : 23;
-	uint64_t spare1 : 3;
-	uint64_t prefetch : 1;
-	uint64_t spare2 : 2;
-	uint64_t abort : 1;
-	uint64_t spare3 : 1;
-	uint64_t buffer_status : 7;
-	uint64_t spare4 : 4;
-	uint64_t _reserved0 : 20;
-#else
-	uint64_t _reserved0 : 20;
-	uint64_t spare4 : 4;
-	uint64_t buffer_status : 7;
-	uint64_t spare3 : 1;
-	uint64_t abort : 1;
-	uint64_t spare2 : 2;
-	uint64_t prefetch : 1;
-	uint64_t spare1 : 3;
-	uint64_t cur_rd_addr : 23;
-	uint64_t rd_slvnum : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_rbufvaln_t;
-
-
-
-typedef union pba_wbufvaln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t wr_slvnum : 2;
-	uint64_t start_wr_addr : 30;
-	uint64_t spare1 : 3;
-	uint64_t wr_buffer_status : 5;
-	uint64_t spare2 : 1;
-	uint64_t wr_byte_count : 7;
-	uint64_t spare3 : 16;
-#else
-	uint64_t spare3 : 16;
-	uint64_t wr_byte_count : 7;
-	uint64_t spare2 : 1;
-	uint64_t wr_buffer_status : 5;
-	uint64_t spare1 : 3;
-	uint64_t start_wr_addr : 30;
-	uint64_t wr_slvnum : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_wbufvaln_t;
-
-
-
-typedef union pba_mode {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved0 : 4;
-	uint64_t dis_rearb : 1;
-	uint64_t reserved1 : 1;
-	uint64_t dis_slave_rdpipe : 1;
-	uint64_t dis_slave_wrpipe : 1;
-	uint64_t en_marker_ack : 1;
-	uint64_t dis_slvmatch_order : 1;
-	uint64_t en_second_wrbuf : 1;
-	uint64_t dis_rerequest_to : 1;
-	uint64_t inject_type : 2;
-	uint64_t inject_mode : 2;
-	uint64_t pba_region : 2;
-	uint64_t oci_marker_space : 3;
-	uint64_t bcde_ocitrans : 2;
-	uint64_t bcue_ocitrans : 2;
-	uint64_t dis_master_rd_pipe : 1;
-	uint64_t dis_master_wr_pipe : 1;
-	uint64_t en_slave_fairness : 1;
-	uint64_t en_ecvent_count : 1;
-	uint64_t pb_noci_event_sel : 1;
-	uint64_t slv_event_mux : 2;
-	uint64_t enable_debug_bus : 1;
-	uint64_t debug_pb_not_oci : 1;
-	uint64_t debug_oci_mode : 5;
-	uint64_t reserved2 : 1;
-	uint64_t ocislv_fairness_mask : 5;
-	uint64_t ocislv_rereq_hang_div : 5;
-	uint64_t dis_chgrate_count : 1;
-	uint64_t pbreq_event_mux : 2;
-	uint64_t _reserved0 : 11;
-#else
-	uint64_t _reserved0 : 11;
-	uint64_t pbreq_event_mux : 2;
-	uint64_t dis_chgrate_count : 1;
-	uint64_t ocislv_rereq_hang_div : 5;
-	uint64_t ocislv_fairness_mask : 5;
-	uint64_t reserved2 : 1;
-	uint64_t debug_oci_mode : 5;
-	uint64_t debug_pb_not_oci : 1;
-	uint64_t enable_debug_bus : 1;
-	uint64_t slv_event_mux : 2;
-	uint64_t pb_noci_event_sel : 1;
-	uint64_t en_ecvent_count : 1;
-	uint64_t en_slave_fairness : 1;
-	uint64_t dis_master_wr_pipe : 1;
-	uint64_t dis_master_rd_pipe : 1;
-	uint64_t bcue_ocitrans : 2;
-	uint64_t bcde_ocitrans : 2;
-	uint64_t oci_marker_space : 3;
-	uint64_t pba_region : 2;
-	uint64_t inject_mode : 2;
-	uint64_t inject_type : 2;
-	uint64_t dis_rerequest_to : 1;
-	uint64_t en_second_wrbuf : 1;
-	uint64_t dis_slvmatch_order : 1;
-	uint64_t en_marker_ack : 1;
-	uint64_t dis_slave_wrpipe : 1;
-	uint64_t dis_slave_rdpipe : 1;
-	uint64_t reserved1 : 1;
-	uint64_t dis_rearb : 1;
-	uint64_t reserved0 : 4;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_mode_t;
-
-
-
-typedef union pba_slvrst {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t set : 3;
-	uint64_t notimp1 : 1;
-	uint64_t in_prog : 4;
-	uint64_t busy_status : 4;
-	uint64_t _reserved0 : 52;
-#else
-	uint64_t _reserved0 : 52;
-	uint64_t busy_status : 4;
-	uint64_t in_prog : 4;
-	uint64_t notimp1 : 1;
-	uint64_t set : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_slvrst_t;
-
-
-
-typedef union pba_slvctln {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t enable : 1;
-	uint64_t mid_match_value : 3;
-	uint64_t _reserved0 : 1;
-	uint64_t mid_care_mask : 3;
-	uint64_t write_ttype : 3;
-	uint64_t _reserved1 : 4;
-	uint64_t read_ttype : 1;
-	uint64_t read_prefetch_ctl : 2;
-	uint64_t buf_invalidate_ctl : 1;
-	uint64_t buf_alloc_w : 1;
-	uint64_t buf_alloc_a : 1;
-	uint64_t buf_alloc_b : 1;
-	uint64_t buf_alloc_c : 1;
-	uint64_t _reserved2 : 1;
-	uint64_t dis_write_gather : 1;
-	uint64_t wr_gather_timeout : 3;
-	uint64_t write_tsize : 7;
-	uint64_t extaddr : 14;
-	uint64_t _reserved3 : 15;
-#else
-	uint64_t _reserved3 : 15;
-	uint64_t extaddr : 14;
-	uint64_t write_tsize : 7;
-	uint64_t wr_gather_timeout : 3;
-	uint64_t dis_write_gather : 1;
-	uint64_t _reserved2 : 1;
-	uint64_t buf_alloc_c : 1;
-	uint64_t buf_alloc_b : 1;
-	uint64_t buf_alloc_a : 1;
-	uint64_t buf_alloc_w : 1;
-	uint64_t buf_invalidate_ctl : 1;
-	uint64_t read_prefetch_ctl : 2;
-	uint64_t read_ttype : 1;
-	uint64_t _reserved1 : 4;
-	uint64_t write_ttype : 3;
-	uint64_t mid_care_mask : 3;
-	uint64_t _reserved0 : 1;
-	uint64_t mid_match_value : 3;
-	uint64_t enable : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_slvctln_t;
-
-
-
-typedef union pba_bcde_ctl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t stop : 1;
-	uint64_t start : 1;
-	uint64_t _reserved0 : 62;
-#else
-	uint64_t _reserved0 : 62;
-	uint64_t start : 1;
-	uint64_t stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_ctl_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_bcde_set {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t _reserved0 : 2;
-	uint64_t copy_length : 6;
-	uint64_t _reserved1 : 56;
-#else
-	uint64_t _reserved1 : 56;
-	uint64_t copy_length : 6;
-	uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_set_t;
-
-
-
-typedef union pba_bcde_stat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t running : 1;
-	uint64_t waiting : 1;
-	uint64_t wrcmp : 6;
-	uint64_t _reserved0 : 6;
-	uint64_t rdcmp : 6;
-	uint64_t debug : 9;
-	uint64_t stopped : 1;
-	uint64_t error : 1;
-	uint64_t done : 1;
-	uint64_t _reserved1 : 32;
-#else
-	uint64_t _reserved1 : 32;
-	uint64_t done : 1;
-	uint64_t error : 1;
-	uint64_t stopped : 1;
-	uint64_t debug : 9;
-	uint64_t rdcmp : 6;
-	uint64_t _reserved0 : 6;
-	uint64_t wrcmp : 6;
-	uint64_t waiting : 1;
-	uint64_t running : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_stat_t;
-
-
-
-typedef union pba_bcde_pbadr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t _reserved0 : 2;
-	uint64_t pb_offset : 23;
-	uint64_t _reserved1 : 2;
-	uint64_t extaddr : 14;
-	uint64_t _reserved2 : 23;
-#else
-	uint64_t _reserved2 : 23;
-	uint64_t extaddr : 14;
-	uint64_t _reserved1 : 2;
-	uint64_t pb_offset : 23;
-	uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_pbadr_t;
-
-
-
-typedef union pba_bcde_ocibar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t addr : 25;
-	uint64_t _reserved0 : 39;
-#else
-	uint64_t _reserved0 : 39;
-	uint64_t addr : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcde_ocibar_t;
-
-
-
-typedef union pba_bcue_ctl {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t stop : 1;
-	uint64_t start : 1;
-	uint64_t _reserved0 : 62;
-#else
-	uint64_t _reserved0 : 62;
-	uint64_t start : 1;
-	uint64_t stop : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_ctl_t;
-
-#endif // __ASSEMBLER__
-#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000)
-#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000)
-#ifndef __ASSEMBLER__
-
-
-typedef union pba_bcue_set {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t _reserved0 : 2;
-	uint64_t copy_length : 6;
-	uint64_t _reserved1 : 56;
-#else
-	uint64_t _reserved1 : 56;
-	uint64_t copy_length : 6;
-	uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_set_t;
-
-
-
-typedef union pba_bcue_stat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t running : 1;
-	uint64_t waiting : 1;
-	uint64_t wrcmp : 6;
-	uint64_t _reserved0 : 6;
-	uint64_t rdcmp : 6;
-	uint64_t debug : 9;
-	uint64_t stopped : 1;
-	uint64_t error : 1;
-	uint64_t done : 1;
-	uint64_t _reserved1 : 32;
-#else
-	uint64_t _reserved1 : 32;
-	uint64_t done : 1;
-	uint64_t error : 1;
-	uint64_t stopped : 1;
-	uint64_t debug : 9;
-	uint64_t rdcmp : 6;
-	uint64_t _reserved0 : 6;
-	uint64_t wrcmp : 6;
-	uint64_t waiting : 1;
-	uint64_t running : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_stat_t;
-
-
-
-typedef union pba_bcue_pbadr {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t _reserved0 : 2;
-	uint64_t pb_offset : 23;
-	uint64_t _reserved1 : 2;
-	uint64_t extaddr : 14;
-	uint64_t _reserved2 : 23;
-#else
-	uint64_t _reserved2 : 23;
-	uint64_t extaddr : 14;
-	uint64_t _reserved1 : 2;
-	uint64_t pb_offset : 23;
-	uint64_t _reserved0 : 2;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_pbadr_t;
-
-
-
-typedef union pba_bcue_ocibar {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t addr : 25;
-	uint64_t _reserved0 : 39;
-#else
-	uint64_t _reserved0 : 39;
-	uint64_t addr : 25;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_bcue_ocibar_t;
-
-
-
-typedef union pba_pbocrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t _reserved0 : 16;
-	uint64_t event : 16;
-	uint64_t _reserved1 : 12;
-	uint64_t accum : 20;
-#else
-	uint64_t accum : 20;
-	uint64_t _reserved1 : 12;
-	uint64_t event : 16;
-	uint64_t _reserved0 : 16;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_pbocrn_t;
-
-
-
-typedef union pba_xsndtx {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t snd_scope : 3;
-	uint64_t snd_qid : 1;
-	uint64_t snd_type : 1;
-	uint64_t snd_reservation : 1;
-	uint64_t spare1 : 2;
-	uint64_t snd_nodeid : 3;
-	uint64_t snd_chipid : 3;
-	uint64_t spare2 : 2;
-	uint64_t _reserved0 : 48;
-#else
-	uint64_t _reserved0 : 48;
-	uint64_t spare2 : 2;
-	uint64_t snd_chipid : 3;
-	uint64_t snd_nodeid : 3;
-	uint64_t spare1 : 2;
-	uint64_t snd_reservation : 1;
-	uint64_t snd_type : 1;
-	uint64_t snd_qid : 1;
-	uint64_t snd_scope : 3;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsndtx_t;
-
-
-
-typedef union pba_xcfg {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t pbax_en : 1;
-	uint64_t reservation_en : 1;
-	uint64_t snd_reset : 1;
-	uint64_t rcv_reset : 1;
-	uint64_t rcv_nodeid : 3;
-	uint64_t rcv_chipid : 3;
-	uint64_t spare1 : 2;
-	uint64_t rcv_brdcst_group : 8;
-	uint64_t rcv_datalo_thresh : 8;
-	uint64_t snd_retry_thresh : 8;
-	uint64_t snd_rsv_req_thresh : 2;
-	uint64_t snd_retry_count_overcom : 1;
-	uint64_t _reserved0 : 25;
-#else
-	uint64_t _reserved0 : 25;
-	uint64_t snd_retry_count_overcom : 1;
-	uint64_t snd_rsv_req_thresh : 2;
-	uint64_t snd_retry_thresh : 8;
-	uint64_t rcv_datalo_thresh : 8;
-	uint64_t rcv_brdcst_group : 8;
-	uint64_t spare1 : 2;
-	uint64_t rcv_chipid : 3;
-	uint64_t rcv_nodeid : 3;
-	uint64_t rcv_reset : 1;
-	uint64_t snd_reset : 1;
-	uint64_t reservation_en : 1;
-	uint64_t pbax_en : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xcfg_t;
-
-
-
-typedef union pba_xsndstat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t snd_in_progress : 1;
-	uint64_t snd_error : 1;
-	uint64_t snd_status : 6;
-	uint64_t snd_retry_count : 8;
-	uint64_t _reserved0 : 48;
-#else
-	uint64_t _reserved0 : 48;
-	uint64_t snd_retry_count : 8;
-	uint64_t snd_status : 6;
-	uint64_t snd_error : 1;
-	uint64_t snd_in_progress : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsndstat_t;
-
-
-
-typedef union pba_xsnddat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t pbax_datahi : 32;
-	uint64_t pbax_datalo : 32;
-#else
-	uint64_t pbax_datalo : 32;
-	uint64_t pbax_datahi : 32;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xsnddat_t;
-
-
-
-typedef union pba_xrcvstat {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t rcv_in_progress : 1;
-	uint64_t rcv_error : 1;
-	uint64_t rcv_write_in_progress : 1;
-	uint64_t rcv_reservation_set : 1;
-	uint64_t rcv_capture : 14;
-	uint64_t _reserved0 : 46;
-#else
-	uint64_t _reserved0 : 46;
-	uint64_t rcv_capture : 14;
-	uint64_t rcv_reservation_set : 1;
-	uint64_t rcv_write_in_progress : 1;
-	uint64_t rcv_error : 1;
-	uint64_t rcv_in_progress : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xrcvstat_t;
-
-
-
-typedef union pba_xshbrn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t push_start : 29;
-	uint64_t _reserved0 : 35;
-#else
-	uint64_t _reserved0 : 35;
-	uint64_t push_start : 29;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshbrn_t;
-
-
-
-typedef union pba_xshcsn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t push_full : 1;
-	uint64_t push_empty : 1;
-	uint64_t spare1 : 2;
-	uint64_t push_intr_action : 2;
-	uint64_t push_length : 5;
-	uint64_t notimp1 : 2;
-	uint64_t push_write_ptr : 5;
-	uint64_t notimp2 : 3;
-	uint64_t push_read_ptr : 5;
-	uint64_t notimp3 : 5;
-	uint64_t push_enable : 1;
-	uint64_t _reserved0 : 32;
-#else
-	uint64_t _reserved0 : 32;
-	uint64_t push_enable : 1;
-	uint64_t notimp3 : 5;
-	uint64_t push_read_ptr : 5;
-	uint64_t notimp2 : 3;
-	uint64_t push_write_ptr : 5;
-	uint64_t notimp1 : 2;
-	uint64_t push_length : 5;
-	uint64_t push_intr_action : 2;
-	uint64_t spare1 : 2;
-	uint64_t push_empty : 1;
-	uint64_t push_full : 1;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshcsn_t;
-
-
-
-typedef union pba_xshincn {
-
-    uint64_t value;
-    struct {
-#ifdef _BIG_ENDIAN
-        uint32_t high_order;
-        uint32_t low_order;
-#else
-        uint32_t low_order;
-        uint32_t high_order;
-#endif // _BIG_ENDIAN
-    } words;
-    struct {
-#ifdef _BIG_ENDIAN
-	uint64_t reserved : 64;
-#else
-	uint64_t reserved : 64;
-#endif // _BIG_ENDIAN
-    } fields;
-} pba_xshincn_t;
-
-
-#endif // __ASSEMBLER__
-#endif // __PBA_FIRMWARE_REGISTERS_H__
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h
deleted file mode 100644
index ba1b3eaac..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h
+++ /dev/null
@@ -1,356 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/pgp_pba.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __PGP_PBA_H__
-#define __PGP_PBA_H__
-
-// $Id: pgp_pba.h,v 1.2 2012/10/05 18:42:15 pchatnah Exp $
-
-/// \file pgp_pba.h
-/// \brief PBA unit header.  Local and mechanically generated macros.
-
-/// \todo Add Doxygen grouping to constant groups
-
-//#include "pba_register_addresses.h"
-#include "pba_firmware_register.H"
-
-#define POWERBUS_CACHE_LINE_SIZE 128
-#define LOG_POWERBUS_CACHE_LINE_SIZE 7
-
-/// The PBA OCI region is always either 0 or 3
-#define PBA_OCI_REGION 0
-
-// It is assumed the the PBA BAR sets will be assigned according to the
-// following scheme.  There are still many open questions concerning PBA
-// setup. 
-
-/// The number of PBA Base Address Registers (BARS)
-#define PBA_BARS 4
-
-#define PBA_BAR_CHIP    0
-#define PBA_BAR_NODE    1
-#define PBA_BAR_SYSTEM  2
-#define PBA_BAR_CENTAUR 3
-
-// Standard PBA slave assignments, set up by FAPI procedure prior to releasing
-// OCC from reset.
-
-#define PBA_SLAVE_PORE_GPE 0    /* GPE0/1, but only 1 can access mainstore */
-#define PBA_SLAVE_OCC      1	/* 405 I- and D-cache */
-#define PBA_SLAVE_PORE_SLW 2	
-#define PBA_SLAVE_OCB      3	
-
-/// The maximum number of bytes a PBA block-copy engine can transfer at once
-#define PBA_BCE_SIZE_MAX 4096
-
-/// The base-2 log of the minimum PBA translation window size in bytes
-#define PBA_LOG_SIZE_MIN 20
-
-/// The base-2 log of the maximum PBA translation window size in bytes
-///
-/// Note that windows > 2**27 bytes require the extended address.
-#define PBA_LOG_SIZE_MAX 41
-
-/// The number of PBA slaves
-#define PBA_SLAVES 4
-
-/// The number of PBA read buffers
-#define PBA_READ_BUFFERS 6
-
-/// The number of PBA write buffers
-#define PBA_WRITE_BUFFERS 2
-
-
-////////////////////////////////////
-// Macros for fields of PBA_SLVCTLn
-////////////////////////////////////
-
-// PBA write Ttypes
-
-#define PBA_WRITE_TTYPE_DMA_PR_WR    0x0 /// DMA Partial Write
-#define PBA_WRITE_TTYPE_LCO_M        0x1 /// L3 LCO, Tsize denotes chiplet
-#define PBA_WRITE_TTYPE_ATOMIC_RMW   0x2 /// Atomic operations
-#define PBA_WRITE_TTYPE_CACHE_INJECT 0x3 /// ?
-#define PBA_WRITE_TTYPE_CI_PR_W      0x4 /// Cache-inhibited partial write for Centaur putscom().
-
-#define PBA_WRITE_TTYPE_DC PBA_WRITE_TTYPE_DMA_PR_WR // Don't care
-
-
-// PBA write Tsize is only required for PBA_WRITE_TTYPE_LCO_M (where it
-// actually specifies a core chiplet id) and PBA_WRITE_TTYPE_ATOMIC_RMW.
-
-#define PBA_WRITE_TSIZE_CHIPLET(chiplet) (chiplet)
-
-#define PBA_WRITE_TSIZE_ARMW_ADD 0x03
-#define PBA_WRITE_TSIZE_ARMW_AND 0x13
-#define PBA_WRITE_TSIZE_ARMW_OR  0x23
-#define PBA_WRITE_TSIZE_ARMW_XOR 0x33
-
-#define PBA_WRITE_TSIZE_DC 0x0
-
-
-// PBA write gather timeouts are defined in terms of the number of 'pulses'. A
-// pulse occurs every 64 OCI cycles. The timing of the last write of a
-// sequence is variable, so the timeout will occur somewhere between (N - 1) *
-// 64 and N * 64 OCI cycles.  If write gather timeouts are disabled, the PBA
-// holds the data until some condition occurs that causes it to disgorge the
-// data. Slaves using cache-inhibited partial write never gather write
-// data. Note from spec. : "Write gather timeouts must NOT be disabled if
-// multiple masters are enabled to write through the PBA".  The only case
-// where write gather timeouts will be disabled is for the IPL-time injection
-// of data into the L3 caches.
-
-#define PBA_WRITE_GATHER_TIMEOUT_DISABLE   0x0
-#define PBA_WRITE_GATHER_TIMEOUT_2_PULSES  0x4
-#define PBA_WRITE_GATHER_TIMEOUT_4_PULSES  0x5
-#define PBA_WRITE_GATHER_TIMEOUT_8_PULSES  0x6
-#define PBA_WRITE_GATHER_TIMEOUT_16_PULSES 0x7
-
-/// PBA write gather timeout don't care assignment
-#define PBA_WRITE_GATHER_TIMEOUT_DC PBA_WRITE_GATHER_TIMEOUT_2_PULSES
-
-
-// PBA read Ttype
-
-#define PBA_READ_TTYPE_CL_RD_NC      0x0 /// Cache line read
-#define PBA_READ_TTYPE_CI_PR_RD      0x1 /// Cache-inhibited partial read for Centaur getscom().
-
-/// PBA read TTYPE don't care assignment
-#define PBA_READ_TTYPE_DC PBA_READ_TTYPE_CL_RD_NC      
-
-
-// PBA read prefetch options
-
-#define PBA_READ_PREFETCH_AUTO_EARLY  0x0 /// Aggressive prefetch
-#define PBA_READ_PREFETCH_NONE        0x1 /// No prefetch
-#define PBA_READ_PREFETCH_AUTO_LATE   0x2 /// Non-aggressive prefetch
-
-/// PBA read prefetch don't care assignment
-#define PBA_READ_PREFETCH_DC PBA_READ_PREFETCH_NONE        
-
-
-// PBA PowerBus command scope and priority, and PBA defaults
-
-/// Nodal, Local Node
-#define POWERBUS_COMMAND_SCOPE_NODAL 0x0 
-
-/// Group, Local 4-chip, (aka, node pump)
-#define POWERBUS_COMMAND_SCOPE_GROUP 0x1
-
-/// System,  All units in the system
-#define POWERBUS_COMMAND_SCOPE_SYSTEM 0x2ss
-
-/// RGP, All units in the system (aka, system pump)
-#define POWERBUS_COMMAND_SCOPE_RGP 0x3
-
-/// Foreign, All units on the local chip, local SMP, and remote chip (pivot
-/// nodes), In P8, only 100 and 101 are valid.
-#define POWERBUS_COMMAND_SCOPE_FOREIGN0 0x4 
-
-/// Foreign, All units on the local chip, local SMP, and remote chip (pivot
-/// nodes), In P8, only 100 and 101 are valid.
-#define POWERBUS_COMMAND_SCOPE_FOREIGN1 0x5
-
-
-/// Default command scope for BCDE/BCUE transfers
-#define PBA_POWERBUS_COMMAND_SCOPE_DEFAULT POWERBUS_COMMAND_SCOPE_NODAL
-
-
-
-// Abstract fields of the PBA Slave Reset register used in pba_slave_reset(),
-// which checks 'n' for validity.p
-
-#define PBA_SLVRST_SET(n) (4 + (n))
-#define PBA_SLVRST_IN_PROG(n) (0x8 >> (n))
-
-/// The default timeout for pba_slave_reset().
-///
-/// Currently the procedure pba_slave_reset() is thought to be an
-/// initialization-only and/or lab-only procedure, so this long polling
-/// timeout is not a problem.  In the lab, a SCOM poll is ~1us to this
-/// value is in ~us units
-#ifndef PBA_SLAVE_RESET_TIMEOUT
-#define PBA_SLAVE_RESET_TIMEOUT 100 
-#endif 
-
-
-// PBA Error/Panic codes
-
-#define PBA_SCOM_ERROR       0x00722001
-#define PBA_SLVRST_TIMED_OUT 0x00722002
-
-#ifndef __ASSEMBLER__
-
-/// The PBA extended address in the form of a 'firmware register'
-///
-/// The extended address covers only bits 23:36 of the 50-bit PowerBus address.
-
-typedef union pba_extended_address {
-
-    uint64_t value;
-    uint32_t word[2];
-    struct {
-	uint64_t reserved0        : 23;
-	uint64_t extended_address : 14;
-	uint64_t reserved1        : 27;
-    } fields;
-} pba_extended_address_t;
-
-
-int 
-pba_barset_initialize(int idx, uint64_t base, int log_size);
-
-
-
-////////////////////////////////////////////////////////////////////////////
-// PBAX
-////////////////////////////////////////////////////////////////////////////
-
-// PBAX error/panic codes
-
-#define PBAX_SEND_TIMEOUT  0x00722901
-#define PBAX_SEND_ERROR    0x00722902
-#define PBAX_RECEIVE_ERROR 0x00722903
-
-/// The number of receive queues implemented by PBAX
-#define PBAX_QUEUES 2
-
-/// The number of PBAX Node Ids
-#define PBAX_NODES 8
-
-/// The number of PBAX Chip Ids (and group Ids)
-#define PBAX_CHIPS 8
-#define PBAX_GROUPS PBAX_CHIPS
-
-/// The maximum legal PBAX group mask
-#define PBAX_GROUP_MASK_MAX 0xff
-
-// PBAX Send Message Scope
-
-#define PBAX_GROUP  1
-#define PBAX_SYSTEM 2
-
-// PBAX Send Type
-
-#define PBAX_UNICAST   0
-#define PBAX_BROADCAST 1
-
-// Default timeout for pbax_send()
-
-#ifndef PBAX_SEND_DEFAULT_TIMEOUT
-#define PBAX_SEND_DEFAULT_TIMEOUT SSX_MICROSECONDS(15)
-#endif
-
-/*
-/// An abstract target for PBAX send operations
-///
-/// This structure contains an abstraction of a communication target for PBAX
-/// send operations.  An application using PBAX to transmit data first creates
-/// an instance of the PbaxTarget for each abstract target using
-/// pbax_target_create(), then calls pbax_send() or _pbax_send() with a
-/// PbaxTarget and an 8-byte data packet to effect a transmission.
-///
-/// For applications that use GPE programs to implement PBAX sends, a pointer
-/// to this object could also be passed to the GPE program.
-
-typedef struct {
-
-    /// The abstract target
-    ///
-    /// pbax_target_create() condenses the target parameters into a copy of
-    /// the PBAXSNDTX register used to configure the transmission.
-    pba_xsndtx_t target;
-
-} PbaxTarget;
-
-
-int
-pbax_target_create(PbaxTarget* target,
-                   int type, int scope, int queue, 
-                   int node, int chip_or_group);
-
-int
-pbax_configure(int master, int node, int chip, int group_mask);
-
-int
-_pbax_send(PbaxTarget* target, uint64_t data, SsxInterval timeout);
-
-int
-pbax_send(PbaxTarget* target, uint64_t data);
-
-
-/// Enable the PBAX send mechanism
-
-static inline void
-pbax_send_enable()
-{
-    pba_xcfg_t pxc;
-
-    pxc.words.high_order = in32(PBA_XCFG);
-    pxc.fields.pbax_en = 1;
-    out32(PBA_XCFG, pxc.words.high_order);
-    
-}
-
-
-/// Disable the PBAX send mechanism
-
-static inline void
-pbax_send_disable()
-{
-    pba_xcfg_t pxc;
-
-    pxc.words.high_order = in32(PBA_XCFG);
-    pxc.fields.pbax_en = 0;
-    out32(PBA_XCFG, pxc.words.high_order);
-    
-}
-
-
-/// Clear the PBAX send error condition
-
-static inline void
-pbax_clear_send_error()
-{
-    pba_xcfg_t pxc;
-
-    pxc.words.high_order = in32(PBA_XCFG);
-    pxc.fields.snd_reset = 1;
-    out32(PBA_XCFG, pxc.words.high_order);
-}    
-
-
-/// Clear the PBAX receive error condition
-
-static inline void
-pbax_clear_receive_error()
-{
-    pba_xcfg_t pxc;
-
-    pxc.words.high_order = in32(PBA_XCFG);
-    pxc.fields.rcv_reset = 1;
-    out32(PBA_XCFG, pxc.words.high_order);
-}    
-*/
-#endif /* __ASSEMBLER__ */
-
-#endif	/* __PGP_PBA_H__ */
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h
deleted file mode 100644
index 0cc4a42ea..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h
+++ /dev/null
@@ -1,476 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_delta_scan_rw.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_delta_scan_rw.h,v 1.55 2015/05/28 20:28:31 jmcgill Exp $
-#define OVERRIDE_OFFSET 8            // Byte offset of forward pointer's addr relative 
-                                     //   to base forward pointer's addr.
-#define SIZE_IMAGE_BUF_MAX      5000000 // Max ~5MB image buffer size.
-#define SIZE_IMAGE_CENTAUR_MAX  5000000 // Max ~5MB image buffer size.
-#define SIZE_REPR_RING_MAX        50000 // Max ~50kB repr ring buffer size.
-#define SCOM_REG_MASK   0x00ffffff   // Scom register mask (within a chiplet)
-#define CID_MASK        0xff000000   // Chiplet ID mask
-#define CID_EX_LOW      0x10         // Lowest EX chiplet addr
-#define CID_EX_HIGH     0x1f         // Highest EX chiplet addr
-
-/*****  Xip customize support ****/
-#define COMBINED_GOOD_VECTORS_TOC_NAME    "combined_good_vectors"
-#define L2_SINGLE_MEMBER_ENABLE_TOC_NAME  "l2_single_member_enable_mask"
-#define PROC_PIB_REPR_VECTOR_TOC_NAME     "proc_sbe_pibmem_repair_vector"
-#define NEST_SKEWADJUST_VECTOR_TOC_NAME   "proc_sbe_nest_skewadjust_vector"
-#define SECURITY_SETUP_VECTOR_TOC_NAME    "proc_sbe_security_setup_vector"
-#define PB_BNDY_DMIPLL_REFCLK_SEL_TOC_NAME "pb_bndy_dmipll_refclk_sel_mod"
-#define PB_BNDY_DMIPLL_PFD360_TOC_NAME    "pb_bndy_dmipll_pfd360_mod"
-#define AB_BNDY_PLL_REFCLK_SEL_TOC_NAME   "ab_bndy_pll_refclk_sel_mod"
-#define AB_BNDY_PLL_PFD360_TOC_NAME       "ab_bndy_pll_pfd360_mod"
-#define VALID_BOOT_CORES_MASK_TOC_NAME    "valid_boot_cores_mask"
-#define PERV_BNDY_PLL_RING_SIZE           128 // Bytes
-#define PERV_BNDY_PLL_RING_TOC_NAME       "perv_bndy_pll_ring"
-#define PERV_BNDY_PLL_RING_ALT_TOC_NAME   "perv_bndy_pll_ring_alt"
-#define PB_BNDY_DMIPLL_RING_SIZE          240 // Bytes
-#define PB_BNDY_DMIPLL_RING_TOC_NAME      "pb_bndy_dmipll_ring"
-#define PB_BNDY_DMIPLL_RING_ALT_TOC_NAME  "pb_bndy_dmipll_ring_alt"
-#define AB_BNDY_PLL_RING_SIZE             110 // Bytes
-#define AB_BNDY_PLL_RING_TOC_NAME         "ab_bndy_pll_ring"
-#define AB_BNDY_PLL_RING_ALT_TOC_NAME     "ab_bndy_pll_ring_alt"
-#define PCI_BNDY_PLL_RING_SIZE            110 // Bytes
-#define PCI_BNDY_PLL_RING_TOC_NAME        "pci_bndy_pll_ring"
-#define PCI_BNDY_PLL_RING_ALT_TOC_NAME    "pci_bndy_pll_ring_alt"
-#define MAX_FUNC_L3_RING_LIST_ENTRIES     64
-#define MAX_FUNC_L3_RING_SIZE             7000 // Bytes
-#define MAX_FARY_L2_RING_LIST_ENTRIES     2
-#define MAX_FARY_L2_RING_SIZE             10500 // Bytes
-#define FUNC_L3_RING_TOC_NAME             "ex_func_l3_ring"
-#define FARY_L2_RING_TOC_NAME             "ex_fary_l2_ring"
-#define MAX_CEN_PLL_RING_SIZE               80 // Bytes
-#define TP_PLL_BNDY_RING_ALT_TOC_NAME     "tp_pll_bndy_ring_alt"
-#define STANDALONE_MBOX0_VALUE_TOC_NAME   "standalone_mbox0_value"
-#define STANDALONE_MBOX1_VALUE_TOC_NAME   "standalone_mbox1_value"
-#define STANDALONE_MBOX2_VALUE_TOC_NAME   "standalone_mbox2_value"
-#define STANDALONE_MBOX3_VALUE_TOC_NAME   "standalone_mbox3_value"
-#define UNTRUSTED_BAR_TOC_NAME            "fabric_config"
-#define UNTRUSTED_PBA_BAR_TOC_NAME        "fabric_config_pba"
-#define REFCLOCK_TERM_TOC_NAME            "refclock_term"
-#define PM_SLEEP_ENABLE_TOC_NAME          "pm_sleep_enable"
-#define INTR_DECREMENTER_DELAY_CYCLES_NAME "intr_decrementer_delay_cycles"
-#define INTR_DECREMENTER_DELAY_US_NAME     "intr_decrementer_delay_us"
-
-
-/*****  Scan setting  *****/
-#define OPCG_SCAN_RATIO                     4
-#define P8_OPCG_SCAN_RATIO_BITS             (uint64_t(OPCG_SCAN_RATIO-1)<<(63-8))
-#define P8_OPCG_GO_BITS                     (uint64_t(0x40000000)<<32)
-#define P8_SCAN_POLL_MASK_BIT15             (uint64_t(0x00010000)<<32)
-
-/*****  Scan Control Regs  *****/
-#define P8_PORE_OPCG_CTRL_REG0_0x00030002   0x00030002 // OPCG control reg 0
-#define P8_PORE_OPCG_CTRL_REG1_0x00030003   0x00030003 // OPCG control reg 1
-#define P8_PORE_OPCG_CTRL_REG2_0x00030004   0x00030004 // OPCG control reg 2
-#define P8_PORE_OPCG_START_REG3_0x00030005  0x00030005 // OPCG start reg 3
-#define P8_PORE_CLOCK_REGION_0x00030006     0x00030006 // Clock region control
-#define P8_PORE_CLOCK_CONTROLLER_REG        0x00030007 // Addr of clock ctrl scom reg
-#define P8_PORE_CLOCK_STATUS_0x00030008     0x00030008 // Status of clocks running
-#define P8_PORE_SHIFT_REG                   0x00038000 // Addr of scom reg that does scan ring shifting
-#define P8_SCAN_CHECK_WORD                  0xA5A55A5A // Header check word
-
-/*****  Ring state *****/
-#define MAX_RING_SIZE 500000   // 500kbits is the max ring size in bits
-
-/***** Return codes *****/
-#define DSLWB_RING_SEARCH_MATCH               0
-#define DSLWB_RING_SEARCH_EXHAUST_MATCH      30
-#define DSLWB_RING_SEARCH_NO_MATCH           31
-#define DSLWB_RING_SEARCH_MESS               32
-#define DSLWB_SLWB_SUCCESS                    0
-#define DSLWB_SLWB_NO_RING_MATCH             40
-#define DSLWB_SLWB_DX_ERROR                  41
-#define DSLWB_SLWB_WF_ERROR                  42
-#define DSLWB_SLWB_WF_IMAGE_ERROR            43
-#define DSLWB_SLWB_IMAGE_ERROR               44
-#define DSLWB_SLWB_UNKNOWN_ERROR             45
-#define IMGBUILD_SUCCESS                      0  // Successful img build.
-#define IMGBUILD_ERR_GENERIC                  1  // Non-specific error code.
-#define IMGBUILD_ERR_FILE_ACCESS              2  // Unable to access/open file.
-#define IMGBUILD_ERR_CHIPLET_ID_MESS          4  // Chiplet ID mess(mostly for VPD rings).
-#define IMGBUILD_NO_RINGS_FOUND               5  // Successful img build but no rings found.
-#define IMGBUILD_BAD_ARGS                     6  // Bad function arguments.
-#define IMGBUILD_ERR_MEMORY                   7  // Memory allocation error.
-#define IMGBUILD_ERR_RING_TOO_LARGE           8  // Ring size exceeds HB/PHYP's buffer.
-#define IMGBUILD_ERR_CHECK_CODE               9  // Coding or image data problem.
-#define IMGBUILD_INVALID_IMAGE               10  // Invalid image.
-#define IMGBUILD_IMAGE_SIZE_MISMATCH         11  // Mismatch between image sizes.
-#define IMGBUILD_IMAGE_SIZE_MESS             12  // Messed up image or section sizes.
-#define IMGBUILD_RINGTYPE_NOT_ALLOWED        13  // Ringtype not allowed.
-#define IMGBUILD_BUFFER_TOO_SMALL            14  // Buffer too small.
-#define IMGBUILD_ERR_PORE_INLINE             20  // Pore inline error.
-#define IMGBUILD_ERR_PORE_INLINE_ASM         21  // Err assoc w/inline assembler.
-#define IMGBUILD_RING_SEARCH_MATCH            0
-#define IMGBUILD_RING_SEARCH_EXHAUST_MATCH   30
-#define IMGBUILD_RING_SEARCH_NO_MATCH        31
-#define IMGBUILD_RING_SEARCH_MESS            32
-#define IMGBUILD_ERR_RING_SEARCH             33  // Err assoc w/ring retrieval.
-#define IMGBUILD_ERR_DATACARE_RING_MESS      34  // Err assoc w/datacare & vpd ring sizes.
-#define IMGBUILD_ERR_WF_CREATE               45  // Err assoc w/create_wiggle_flip_prg.
-#define IMGBUILD_ERR_RING_WRITE_TO_IMAGE     46  // Err assoc w/wr_ring_block_to_img.
-#define IMGBUILD_ERR_SECTION_SIZING          48  // Err assoc w/section sizing.
-#define IMGBUILD_ERR_GET_SECTION             49  // Err assoc w/getting section ID.
-#define IMGBUILD_ERR_SECTION_DELETE          50  // Err assoc w/deleting ELF section.
-#define IMGBUILD_ERR_APPEND                  51  // Err assoc w/appending to ELF section.
-#define IMGBUILD_ERR_INCOMPLETE_IMG_BUILD    52  // The image was built, but with errors.
-#define IMGBUILD_ERR_FWD_BACK_PTR_MESS       53  // Forward or backward pointer mess.
-#define IMGBUILD_ERR_KEYWORD_NOT_FOUND       54  // Image keyword not found.
-#define IMGBUILD_ERR_MISALIGNED_RING_LAYOUT  55  // Ring layout is misaligned.
-#define IMGBUILD_ERR_IMAGE_TOO_LARGE         56  // Image too large. Exceeded max size.
-#define IMGBUILD_ERR_XIP_MISC                57  // Miscellaneous XIP image error.
-#define IMGBUILD_ERR_XIP_UNKNOWN             58  // Unknown XIP image error.
-#define IMGBUILD_ERR_RS4_DECOMPRESS          59  // Error during RS4 decompression.
-#define IMGBUILD_ERR_RS4_COMPRESS            60  // Error during RS4 compression.
-#define IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED     61  // Ram headers not synchronized.
-#define IMGBUILD_ERR_RAM_TABLE_FULL          63  // Ram table is full.       
-#define IMGBUILD_ERR_RAM_CODE                64  // Code error in Ram API code.
-#define IMGBUILD_ERR_RAM_INVALID_PARM        65  // Invalid Ramming parameter.
-#define IMGBUILD_WARN_RAM_TABLE_CONTAMINATION 66 // Ram table contamination
-#define IMGBUILD_ERR_RAM_TABLE_FAIL          67  // Unsuccessful RAM table build.
-#define IMGBUILD_ERR_RAM_TABLE_END_NOT_FOUND 68  // Table entry end bit not found.
-#define IMGBUILD_ERR_SCOM_INVALID_PARM       70  // Invalid Scomming parameter.
-#define IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD     72  // Scom headers out of sync.
-#define IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND    74  // Scom entry not found (OR/AND oper.)
-#define IMGBUILD_ERR_SCOM_REPEAT_ENTRIES     76  // Repeat entries not allow.
-#define IMGBUILD_ERR_SCOM_INVALID_SUBSECTION 77  // Invalid subsection value.
-#define IMGBUILD_ERR_SCOM_TABLE_FAIL         79  // Unsuccessful SCOM table build.
-
-#if defined SLW_COMMAND_LINE_RAM || defined XIPC_COMMAND_LINE
-#define SLW_COMMAND_LINE
-#endif
-
-#if defined __FAPI && !(defined __P8_PORE_TABLE_GEN_API_C)
-#define MY_INF(_fmt_, _args_...) FAPI_INF(_fmt_, ##_args_)
-#ifndef SLW_COMMAND_LINE
-#define MY_ERR(_fmt_, _args_...) FAPI_ERR(_fmt_, ##_args_)
-#else
-#define MY_ERR(_fmt_, _args_...) FAPI_INF(_fmt_, ##_args_)
-#endif // End of SLW_COMMAND_LINE
-#define MY_DBG(_fmt_, _args_...) FAPI_DBG(_fmt_, ##_args_)
-#else  // End of __FAPI
-#ifdef SLW_COMMAND_LINE
-#define MY_INF(_fmt_, _args_...) printf(_fmt_, ##_args_)
-#define MY_ERR(_fmt_, _args_...) printf(_fmt_, ##_args_)
-#define MY_DBG(_fmt_, _args_...) printf(_fmt_, ##_args_)
-#else  // End of SLW_COMMAND_LINE
-#define MY_INF(_fmt_, _args_...)
-#define MY_ERR(_fmt_, _args_...)
-#define MY_DBG(_fmt_, _args_...)
-#endif  // End of not(__FAPI) & not(SLW_COMMAND_LINE)
-#endif
-
-#ifdef SLW_COMMAND_LINE
-// Debug and development stuff
-//#define IGNORE_FOR_NOW  // Causes code sections to be ignored.
-#define DEBUG_SUPPORT   // Activates sbe-xip debug support.
-#endif
-
-//#include <stdio.h>
-//#include <stdint.h>
-//#include <stdlib.h>
-#include <p8_pore_api_custom.h>
-#include <string.h>
-
-#if defined SLW_COMMAND_LINE
-#include <stdint.h> // May be in conflict with p8_pore_api_custom.h
-#include <stdlib.h> // May be in conflict with p8_pore_api_custom.h
-#include <stdio.h>
-#include <sys/mman.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/stat.h>
-#endif //End of SLW_COMMAND_LINE
-
-// Not needed by:
-// - Done: p8_pore_table_gen_api, p8_slw_build, p8_xip_customize, sbe_xip_tool,
-//   p8_delta_scan, p8_ipl_build, p8_centaur_build.
-// - So, what was this used for?
-//#include <pore_bitmanip.H>
-
-#include <p8_image_help_base.H>
-
-#if !(defined __P8_PORE_TABLE_GEN_API_C) && !(defined __CEN_XIP_CUSTOMIZE_C) && !(defined SLW_COMMAND_LINE_RAM)
-// We don't need this include for gen_cpureg/scom or slw ramming.
-#include <p8_scan_compression.H>
-#endif
-
-#undef __PORE_INLINE_ASSEMBLER_C__
-#include <pore_inline.h>
-
-#if( defined(__cplusplus) && !defined(PLIC_MODULE) )
-extern "C" {
-#endif
-
-
-#if !(defined __P8_PORE_TABLE_GEN_API_C) && !(defined SLW_COMMAND_LINE_RAM)
-
-// Info:
-// DeltaRingLayout describes the sequential order of the content in the compressed delta
-//   ring blocks in the .initf section in the SBE-XIP images.
-// When creating the .initf delta ring blocks, the following rules must be followed:
-// - Everything must be stored in BE format.
-// - {entryOffset; sizeOfThis; sizeOfMeta; metaData} must be word-aligned to ensure 
-//   that the {rs4Launch} starts on a word boundary.
-// - {rs4Launch} must start on a word boundary (see earlier rule how to do that).
-// - {entryOffset; sizeOfThis; sizeOfMeta; metaData; rs4Launch} must be double-word-
-//   aligned to ensure that {rs4Delta} starts on a double-word boundary.
-// - {rs4Delta} must start on a double-word bournday (see earlier rule how to do that).
-//
-typedef struct {
-  uint64_t entryOffset;
-  uint64_t backItemPtr;
-  uint32_t sizeOfThis;
-  uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
-  uint32_t ddLevel;
-  uint8_t  sysPhase;
-  uint8_t  override;
-  uint8_t  reserved1;
-  uint8_t  reserved2;
-  char     *metaData;  // Arbitrary size. Extra bytes to next alignment are random or 0s.
-  uint32_t *rs4Launch; // Code. Must be 4-byte aligned. Actually should be 8-B align!
-  uint32_t *rs4Delta;  // Data. Must be 8-byte aligned.
-  uint32_t *wfInline;  // Code. Must be 4-byte aligned. Actually should be 8-B align!
-} DeltaRingLayout;
-
-typedef struct {
-  uint32_t sizeOfData;
-  char     data[];
-} MetaData;
-
-int calc_ring_delta_state(  
-              const uint32_t  *i_init,
-							const uint32_t  *i_alter,
-							uint32_t        *o_delta,
-							const uint32_t  i_ringLen);
-
-int  create_wiggle_flip_prg(  
-              uint32_t   *i_deltaRing,
-              uint32_t   i_ringBitLen,
-              uint32_t   i_scanSelectData,
-              uint32_t   i_chipletID,
-              uint32_t   **o_wfInline,
-              uint32_t   *o_wfInlineLenInWords,
-              uint8_t    i_flushOptimization,
-							uint32_t   i_scanMaxRotate,
-              uint32_t   i_waitsScanDelay,
-              uint8_t   i_usePollingProt);
-
-uint64_t calc_ring_layout_entry_offset(
-							uint8_t  i_typeRingLayout,
-							uint32_t i_sizeMetaData);
-
-int write_ring_block_to_image(  
-							void             *io_image,
-							const char       *i_ringName,    // NULL if no name.
-              DeltaRingLayout  *i_ringBlock,
-							const uint8_t    i_idxVector,   // [0-15] - Ignored if ringName==NULL
-							const uint8_t    i_override,    // [0,1]  - Ignored if ringName==NULL
-							const uint8_t    i_overridable, // [0,1]  - Ignored if ringName==NULL
-              const uint32_t   i_sizeImageMax,
-              const uint8_t    i_xipSectionId,
-              void             *i_bufTmp,
-              const uint32_t   i_sizeBufTmp);
-
-#if !(defined __CEN_XIP_CUSTOMIZE_C)
-
-int p8_centaur_build( 
-							void      *i_imageIn,
-              uint32_t  i_ddLevel,
-              void      *i_imageOut,
-              uint32_t  i_sizeImageOutMax);
-
-int p8_ipl_build(     
-							void      *i_imageIn,
-              uint32_t  i_ddLevel,
-              void      *i_imageOut,
-              uint32_t  i_sizeImageOutMax);
-
-int get_ring_layout_from_image2(  
-							const void  *i_imageIn,
-              uint32_t    i_ddLevel,
-              uint8_t      i_sysPhase,
-              DeltaRingLayout  **o_rs4RingLayout,
-              void        **nextRing,
-              uint8_t     i_xipSectionId);
-
-int gen_ring_delta_state(  
-              uint32_t   bitLen, 
-              uint32_t   *i_init, 
-              uint32_t   *i_alter,
-              uint32_t   *o_delta,
-              uint32_t   verbose);
-
-int write_rs4_ring_to_ref_image(  
-              char       *i_fnImage,
-              CompressedScanData *i_RS4,
-              uint32_t   i_ddLevel,
-              uint8_t    i_sysPhase,
-              uint8_t    i_override,
-							uint8_t    i_ringType,
-              char       *i_varName,
-              char       *i_fnMetaData,
-							void       *i_bufTmp,
-							uint32_t   i_sizeBufTmp,
-              uint32_t   verbose);
-
-int write_vpd_ring_to_ipl_image(
-              void       *io_image,
-							uint32_t   &io_sizeImageOut,
-							CompressedScanData *i_bufRs4Ring,
-							uint32_t   i_ddLevel,
-							uint8_t    i_sysPhase,
-              char       *i_ringName,
-							void       *i_bufTmp,
-							uint32_t   i_sizeBufTmp,
-              uint8_t    i_xipSection);
-
-int write_vpd_ring_to_slw_image(
-              void       *io_image,
-							uint32_t   &io_sizeImageOut,
-							CompressedScanData *i_bufRs4Ring,
-							uint32_t   i_ddLevel,
-              uint8_t i_usePollingProt,
-							uint8_t    i_sysPhase,
-              char       *i_ringName,
-							void       *i_bufTmp,
-							uint32_t   i_sizeBufTmp,
-              uint8_t    i_bWcSpace);
-
-int check_and_perform_ring_datacare( 
-						  void      *i_imageRef,
-							void      *io_buf1,
-							uint8_t   i_ddLevel,
-						  uint8_t   i_sysPhase,
-							char      *i_ringName,
-							void      *i_buf2,
-							uint32_t  i_sizeBuf2);
-							
-int get_delta_ring_from_image(
-              char       *i_fnImage,
-              char       *i_varName,
-              uint32_t   i_ddLevel,
-              uint8_t    i_sysPhase,
-              uint8_t    i_override,
-              MetaData  **o_metaData,
-              CompressedScanData  **o_deltaRingRS4,
-              uint32_t   verbose);
-
-int write_wiggle_flip_to_image(
-              void       *io_imageOut,
-              uint32_t   *i_sizeImageMaxNew,
-              DeltaRingLayout *i_ringLayout,
-              uint32_t   *i_wfInline,
-              uint32_t   i_wfInlineLenInWords);
-
-int get_ring_layout_from_image(  
-              const void *i_imageIn,
-              uint32_t   i_ddLevel,
-              uint8_t    i_sysPhase,
-              DeltaRingLayout  *o_rs4RingLayout,
-              void       **nextRing);
-
-int append_empty_section(
-              void      *io_image,
-              int       *i_sizeImageMaxNew,
-              uint32_t  i_sectionId,
-              int       *i_sizeSection,
-							uint8_t   i_bFixed);
-
-int initialize_slw_section(
-              void      *io_image,
-              uint32_t  *i_sizeImageMaxNew);
-
-int create_and_initialize_fixed_image(
-              void      *io_image);
-
-int update_runtime_scom_pointer(
-							void			*io_image);
-
-void cleanup(
-              void *buf1=NULL,
-              void *buf2=NULL,
-              void *buf3=NULL,
-              void *buf4=NULL,
-              void *buf5=NULL);
-              
-#endif  // End of !(defined __CEN_XIP_CUSTOMIZE_C)
-
-#endif  // End of !(defined __P8_PORE_TABLE_GEN_API_C) && !(defined SLW_COMMAND_LINE_RAM)
-
-// Byte-reverse a 32-bit integer if on an LE machine
-inline uint32_t myRev32(const uint32_t i_x)
-{
-    uint32_t rx;
-
-#ifdef _BIG_ENDIAN
-    rx = i_x;
-#else
-    uint8_t *pix = (uint8_t*)(&i_x);
-    uint8_t *prx = (uint8_t*)(&rx);
-
-    prx[0] = pix[3];
-    prx[1] = pix[2];
-    prx[2] = pix[1];
-    prx[3] = pix[0];
-#endif
-
-    return rx;
-}
-
-// Byte-reverse a 64-bit integer if on a little-endian machine
-inline uint64_t myRev64(const uint64_t i_x)
-{
-    uint64_t rx;
-
-#ifdef _BIG_ENDIAN
-    rx = i_x;
-#else
-    uint8_t *pix = (uint8_t*)(&i_x);
-    uint8_t *prx = (uint8_t*)(&rx);
-
-    prx[0] = pix[7];
-    prx[1] = pix[6];
-    prx[2] = pix[5];
-    prx[3] = pix[4];
-    prx[4] = pix[3];
-    prx[5] = pix[2];
-    prx[6] = pix[1];
-    prx[7] = pix[0];
-#endif
-
-    return rx;
-}
-
-// N-byte align an address, offset or size (aos)
-inline uint64_t myByteAlign( const uint8_t nBytes, const uint64_t aos)
-{
-  return ((aos+nBytes-1)/nBytes)*nBytes;
-}
-
-#if( defined(__cplusplus) && !defined(PLIC_MODULE) )
-}
-#endif
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C
deleted file mode 100644
index 8d2988a14..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C
+++ /dev/null
@@ -1,2016 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_image_help.C,v 1.65 2014/09/11 21:41:26 aalugore Exp $
-//
-/*------------------------------------------------------------------------------*/
-/* *! TITLE : p8_image_help.C                                                   */
-/* *! DESCRIPTION : Helper functions for building and extracting information    */
-//                  from SBE-XIP images.
-/* *! OWNER NAME :  Michael Olsen                  cmolsen@us.ibm.com           */
-//
-/* *! EXTENDED DESCRIPTION :                                                    */
-//
-/* *! USAGE :                                                                   */
-//
-/* *! ASSUMPTIONS :                                                             */
-//
-/* *! COMMENTS :                                                                */
-//
-/*------------------------------------------------------------------------------*/
-
-#include <p8_delta_scan_rw.h>
-#include <p8_pore_table_gen_api.H>
-#include <common_scom_addresses.H>
-
-#ifdef __FAPI
-#include <fapi.H>
-#endif
-extern "C"  {
-
-
-
-// calc_ring_delta_state() parms:
-// i_init - init (flush) ring state
-// i_alter - altered (desired) ring state
-// o_delta - ring delta state, caller allocates buffer
-// i_ringLen - length of ring in bits
-int calc_ring_delta_state( const uint32_t  *i_init,
-													 const uint32_t  *i_alter,
-													 uint32_t        *o_delta,
-													 const uint32_t  i_ringLen )
-{
-  int      i=0, count=0, remainder=0, remainingBits=0;
-  uint32_t init, alter;
-  uint32_t mask=0;
-
-  // Do some checking of input parms
-  if ( (i_init==NULL) || (i_alter==NULL) || (o_delta==NULL) || (i_ringLen==0) )  {
-  	MY_ERR("Bad input arguments.\n");
-    return IMGBUILD_BAD_ARGS;
-  }
-
-  // Check how many 32-bit shift ops are needed and if we need final shift of remaining bit.
-  count = i_ringLen/32;
-  remainder = i_ringLen%32;
-	if (remainder>0)
-	    count = count + 1;
-	remainingBits = i_ringLen;
-	MY_DBG("count=%i  rem=%i  remBits=%i\n",count,remainder,remainingBits);
-
-  // XOR flush and init values 32 bits at a time.  Store result in o_delta buffer.
-	for (i=0; i<count; i++)  {
-
-		if (remainingBits<=0)  {
-			MY_ERR("remaingBits can not be negative.\n");
-			return IMGBUILD_ERR_CHECK_CODE;
-		}
-
-    init  = i_init[i];
-    alter = i_alter[i];
-
-    if (remainingBits>=32)
-      remainingBits = remainingBits-32;
-	  else  {  //If remaining bits are less than 32 bits, mask unused bits
-		  MY_DBG("remainingBits=%i<32. Padding w/zeros. True bit length unaltered. (@word count=%i)\n",remainingBits,count);
-      mask = BITS32(0,remainingBits); // BE mask
-      mask = myRev32(mask);           // Convert to LE if on LE machine
-	    init  = init & mask;
-	    alter = alter & mask;
-	    remainingBits = 0;
-	  }
-
-    // Do the XORing.
-		o_delta[i]  = init ^ alter;
-	}
-
-  return IMGBUILD_SUCCESS;
-}
-
-
-
-// create_wiggle_flip_prg() function
-// Notes:
-// - WF routine implements dynamic P1 multicast bit set based on P0 status.
-// - WF routine checks header word on scan complete.
-// - WF routine is 8-byte aligned.
-int create_wiggle_flip_prg( uint32_t *i_deltaRing,          // scan ring delta state (in BE format)
-                            uint32_t i_ringBitLen,          // length of ring
-                            uint32_t i_scanSelectData,      // Scan ring modifier data
-                            uint32_t i_chipletID,           // Chiplet ID
-                            uint32_t **o_wfInline,          // location of the PORE instructions data stream
-                            uint32_t *o_wfInlineLenInWords, // final length of data stream
-                            uint8_t  i_flushOptimization,   // flush optimize or not
-                            uint32_t i_scanMaxRotate,       // Max rotate bit len on 38xxx, or polling threshold on 39xxx.
-                            uint32_t i_waitsScanDelay,      // Temporary debug support.
-                            uint8_t i_usePollingProt)             // Use Polling Protocol( s1, p8>=20, n1>=10)
-{
-  uint32_t rc=0;
-  uint32_t i=0;
-  uint32_t scanSelectAddr=0;
-  uint32_t scanRing_baseAddr=0;
-  uint32_t scanRing_poreAddr=0;
-  uint32_t scanRingCheckWord=0;
-  uint32_t bitShift=0;
-  uint32_t count=0;
-  uint32_t rotateLen=0, remainder=0, remainingBits=0;
-  uint32_t clear_excess_dirty_bits_mask=0xffffffff;
-  uint32_t clean_up_shift_reg_mask=0xffffffff;
-  uint64_t pore_imm64b=0;
-  uint32_t maxWfInlineLenInWords;
-  PoreInlineContext ctx;
-  uint32_t waitsScanPoll=0;
-  uint32_t scanRing_baseAddr_long=0;
-
-	maxWfInlineLenInWords = *o_wfInlineLenInWords;
-
-  pore_inline_context_create(&ctx, *o_wfInline, maxWfInlineLenInWords * 4, 0, 0);
-
-  //
-  // Set Default scanselq addr and scanring addr vars
-  //
-
-  // 0x00030007: port 3 - clock cotrol endpt, x07- scanselq (regin & types)
-  scanSelectAddr = P8_PORE_CLOCK_CONTROLLER_REG;
-
-  // Addr of clock control SCOM register(s) for short and long rotates.
-  //
-  // Short: 0x00038000: port 3, addr bit 16 must be set to 1 and bit 19 to 0.
-  scanRing_baseAddr = P8_PORE_SHIFT_REG;
-  scanRing_poreAddr = scanRing_baseAddr;
-
-  // Long (poll): 0x00039000: port 3, addr bit 16 must be set to 1 and bit 19 to 1.
-  scanRing_baseAddr_long = P8_PORE_SHIFT_REG | 0x00001000;
-
-  // Header check word for checking ring write was successful
-  scanRingCheckWord = P8_SCAN_CHECK_WORD;
-
-  // This fix is a direct copy of the setp1_mcreadand macro in ./ipl/sbe/p8_slw.H
-  uint64_t CLEAR_MC_TYPE_MASK=0x47;
-  PoreInlineLocation src1=0, src2=0, tgt1=0, tgt2=0;
-  pore_MR( &ctx, D1, P0);
-  pore_ANDI( &ctx, D1, D1, BIT(57));
-  PORE_LOCATION( &ctx, src1);
-  pore_BRANZ( &ctx, D1, src1);
-  pore_MR( &ctx, P1, P0);
-  PORE_LOCATION( &ctx, src2);
-  pore_BRA( &ctx, tgt2);
-  PORE_LOCATION( &ctx, tgt1);
-  pore_MR( &ctx, D1, P0);
-  pore_ANDI( &ctx, D1, D1, CLEAR_MC_TYPE_MASK);
-  pore_ORI( &ctx, D1, D1, BIT(60));
-  pore_MR( &ctx, P1, D1);
-  PORE_LOCATION( &ctx, tgt2);
-  if (ctx.error > 0)  {
-    MY_ERR("***setp1_mcreadand rc = %d", ctx.error);
-    return ctx.error;
-  }
-  pore_inline_branch_fixup( &ctx, src1, tgt1);
-  if (ctx.error > 0)  {
-    MY_ERR("***inline_branch_fixup error (1) rc = %d", ctx.error);
-    return ctx.error;
-  }
-  pore_inline_branch_fixup( &ctx, src2, tgt2);
-  if (ctx.error > 0)  {
-    MY_ERR("***inline_branch_fixup error (2) rc = %d", ctx.error);
-    return ctx.error;
-  }
-
-  // Program scanselq reg for scan clock control setup before ring scan
-  pore_imm64b = ((uint64_t)i_scanSelectData) << 32;
-  pore_STI(&ctx, scanSelectAddr, P0, pore_imm64b);
-  if (ctx.error > 0)  {
-    MY_ERR("***STI rc = %d", ctx.error);
-    return ctx.error;
-  }
-
-	// Preload the scan data/shift reg with the scan header check word.
-  //
-  pore_imm64b = ((uint64_t)scanRingCheckWord) << 32;
-	pore_STI(&ctx, scanRing_baseAddr, P0, pore_imm64b);
-  if (i_waitsScanDelay)  {
-    pore_WAITS(&ctx, i_waitsScanDelay);
-  }
-  if (ctx.error > 0)  {
-    MY_ERR("***STI(1) rc = %d", ctx.error);
-    return ctx.error;
-  }
-
-  // Check how many 32-bit shift ops are needed and if we need final shift of remaining bit.
-  count = i_ringBitLen/32;
-  remainder = i_ringBitLen%32;
-  if (remainder >0)
-      count = count + 1;
-
-  remainingBits = i_ringBitLen;
-
-  MY_DBG("count=%i  rem=%i  remBits=%i",count,remainder,remainingBits);
-
-  for (i=0; i<count; i++)  {
-
-    if (i==(count-1))  {
-      // Cleanup any leftover bits in dirty buffer. (Only applies to last word.)
-      MY_DBG("Clearing any dirty bits in last WF word:\n");
-      MY_DBG("i_deltaRing[%i] (before)     = 0x%08x\n",i,i_deltaRing[i]);
-      MY_DBG("remainingBits                = %i\n",remainingBits);
-      clear_excess_dirty_bits_mask = BITS32(0,remainingBits); // BE mask
-      clear_excess_dirty_bits_mask = myRev32(clear_excess_dirty_bits_mask); // Convert to LE if on LE machine
-      i_deltaRing[i] = i_deltaRing[i]&clear_excess_dirty_bits_mask;
-      MY_DBG("clear_excess_dirty_bits_mask = 0x%08x\n",clear_excess_dirty_bits_mask);
-      MY_DBG("i_deltaRing[%i] (after)      = 0x%08x\n",i,i_deltaRing[i]);
-    }
-
-    //====================================================================================
-    // If flush & init values are identical, increase the read count, no code needed.
-    // When the discrepancy is found, read (rotate the ring) up to current address
-    // then scan/write in the last 32 bits
-    //====================================================================================
-    if (i_deltaRing[i] > 0)  {
-
-      if (rotateLen > 0)  {
-
-              if (i_usePollingProt!=0x00)  {   // Use polling protocol.
-                      MY_DBG("create_wiggle_flip: using polling protocol\n");                              
-          PoreInlineLocation  srcp1=0,tgtp1=0;
-
-          pore_imm64b = uint64_t(rotateLen)<<32;
-				  pore_STI(&ctx, scanRing_baseAddr_long, P0, pore_imm64b);
-
-          waitsScanPoll = rotateLen/OVER_SAMPLING_POLL;
-          if (waitsScanPoll<WAITS_POLL_MIN)
-            waitsScanPoll = WAITS_POLL_MIN;
-				  PORE_LOCATION(&ctx, tgtp1);
-				  pore_WAITS(&ctx, waitsScanPoll);
-				  pore_LDANDI(&ctx, D0, GENERIC_GP1_0x00000001, P1, P8_SCAN_POLL_MASK_BIT15);
-				  PORE_LOCATION(&ctx, srcp1);
-				  pore_BRAZ(&ctx, D0, tgtp1);
-				  pore_inline_branch_fixup(&ctx, srcp1, tgtp1);
-          if (ctx.error > 0)  {
-            MY_ERR("***POLLING PROT(2) rc = %d", ctx.error);
-            return ctx.error;
-          }
-        }
-        else  {                   // Do not use polling protocol.
-              MY_DBG("create_wiggle_flip: not using polling protocol\n");  
-          scanRing_poreAddr = scanRing_baseAddr | rotateLen;
-          pore_LD(&ctx, D0, scanRing_poreAddr, P1);
-          if (ctx.error > 0)  {
-            MY_ERR("***LD D0 rc = %d", ctx.error);
-            return ctx.error;
-          }
-
-        }
-
-      } // End of if (rotateLen>0)
-
-      //
-      // Shift in the delta state word, or parts of it if last word.
-      //
-      if (remainingBits>32)
-        bitShift = 32;
-      else
-        bitShift = remainingBits;
-      scanRing_poreAddr = scanRing_baseAddr | bitShift;
-
-      if (i==(count-1) && bitShift<32)  {
-        // --------------------------------------------------------------------
-        // Be very careful shifting in last word content as it can mess up the
-        //   current shift register content when loaded.
-        // --------------------------------------------------------------------
-        // Take snapshot of present content of shift reg and put in D1.
-        if (i_flushOptimization)  {
-          pore_LD(&ctx, D1, scanRing_baseAddr, P1);
-          // Calculate shift reg cleanup mask and put in D0. The intent is to
-          //   clear bit in the ring data positions while keeping any header
-          //   check word content untouched.
-          clean_up_shift_reg_mask = 0xffffffff>>bitShift;
-          pore_imm64b = ((uint64_t)clean_up_shift_reg_mask) << 32;
-          pore_LI(&ctx, D0, pore_imm64b );
-          // Cleanup shift register snapshot and put in D1.
-          pore_AND(&ctx, D1, D0, D1);
-          // Put ring data in D0.
-          // Note, any dirty content was removed earlier.
-          pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32;
-          pore_LI(&ctx, D0, pore_imm64b );
-          // Finally, combine the ring data and the shift reg content and put in D0.
-          pore_OR(&ctx, D0, D0, D1);
-				  pore_STD(&ctx, D0, scanRing_poreAddr, P0);
-        }
-        else  {
-          pore_LD(&ctx, D1, scanRing_baseAddr, P1);
-          // Bring ring data in as an immediate.
-          // Note, any dirty content was removed earlier.
-          pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32;
-          pore_XORI(&ctx, D0, D1, pore_imm64b);
-          pore_STD(&ctx, D0, scanRing_poreAddr, P0);
-        }
-      }
-      else  {
-        // --------------------------------------------------------------------
-        // Not the last word OR the last word has exactly 32-bit of ring data.
-        // --------------------------------------------------------------------
-        if (i_flushOptimization)  {
-          pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32;
-        // Shift it in by bitShift bits.
-		  		pore_STI(&ctx, scanRing_poreAddr, P0, pore_imm64b);
-        }
-        else  {
-          pore_LD(&ctx, D1, scanRing_baseAddr, P1);
-          pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32;
-          pore_XORI(&ctx, D0, D1, pore_imm64b);
-          pore_STD(&ctx, D0, scanRing_poreAddr, P0);
-        }
-      }
-      if (i_waitsScanDelay)  {
-        pore_WAITS(&ctx, i_waitsScanDelay);
-      }
-      if (ctx.error > 0)  {
-        MY_ERR("***STI(2) (or STD) rc = %d", ctx.error);
-        return ctx.error;
-      }
-
-      rotateLen=0;  //reset rotate length
-
-		}
-    else  {  // i_deltaRing[i]==0 (i.e., init and alter states are identical).
-      if (remainingBits>32)
-        rotateLen = rotateLen + 32;
-      else
-        rotateLen = rotateLen + remainingBits;
-
-      if (i_usePollingProt!=0x00)  {    // Use polling protocol.
-          MY_DBG("create_wiggle_flip: using polling protocol\n");
-          PoreInlineLocation  srcp2=0,tgtp2=0;
-
-        // Max rotate length is 2^20-1, i.e., data BITS(12-31)=>0x000FFFFF
-          if (rotateLen>=SCAN_MAX_ROTATE_LONG)  {
-                  MY_INF("Scanning should never be here since max possible ring length is\n");
-                  MY_INF("480,000 bits but MAX_LONG_ROTATE=0x%0x and rotateLen=0x%0x\n",
-                         SCAN_MAX_ROTATE_LONG, rotateLen);
-          pore_imm64b = uint64_t(SCAN_MAX_ROTATE_LONG)<<32;
-				  pore_STI(&ctx, scanRing_baseAddr_long, P0, pore_imm64b);
-	        if (ctx.error > 0)  {
-	          MY_ERR("***POLLING PROT(3a) rc = %d", ctx.error);
-	          return ctx.error;
-  	      }
-		  	  waitsScanPoll = rotateLen/OVER_SAMPLING_POLL;
-          if (waitsScanPoll<WAITS_POLL_MIN)
-            waitsScanPoll = WAITS_POLL_MIN;
-	  		  PORE_LOCATION(&ctx, tgtp2);
-    			pore_WAITS(&ctx, waitsScanPoll);
-				  pore_LDANDI(&ctx, D0, GENERIC_GP1_0x00000001, P1, P8_SCAN_POLL_MASK_BIT15);
-			   	PORE_LOCATION(&ctx, srcp2);
-		  	  pore_BRAZ(&ctx, D0, tgtp2);
-    			pore_inline_branch_fixup(&ctx, srcp2, tgtp2);
-  	      if (ctx.error > 0)  {
-	          MY_ERR("***POLLING PROT(3) rc = %d", ctx.error);
-	          return ctx.error;
-	        }
-          rotateLen = rotateLen - SCAN_MAX_ROTATE_LONG;
-      	}
-
-      }
-      else  {                   // Do not use polling protocol.
-              MY_DBG("create_wiggle_flip: not using polling protocol\n");
-        if (rotateLen>i_scanMaxRotate)  {
-          scanRing_poreAddr = scanRing_baseAddr | i_scanMaxRotate;
-          pore_LD(&ctx, D0, scanRing_poreAddr, P1);
-          if (ctx.error > 0)  {
-            MY_ERR("***LD D0 rc = %d", ctx.error);
-            return ctx.error;
-          }
-          rotateLen = rotateLen - i_scanMaxRotate;
-        }
-
-      }
-
-    } //end of else (i_deltaRing==0)
-
-    if (remainingBits>32)
-      remainingBits = remainingBits - 32;
-    else
-      remainingBits = 0;
-
-  } // End of for loop
-
-  // If the scan ring has not been rotated to the original position
-  // shift the ring by remaining shift bit length.
-  if (rotateLen>0)  {
-    if (i_usePollingProt!=0x00)  {   // Use polling protocol.
-
-      PoreInlineLocation  srcp3=0,tgtp3=0;
-      MY_DBG("create_wiggle_flip: using polling protocol\n");
-      
-      pore_imm64b = uint64_t(rotateLen)<<32;
-		  pore_STI(&ctx, scanRing_baseAddr_long, P0, pore_imm64b);
-
-      waitsScanPoll = rotateLen/OVER_SAMPLING_POLL;
-      if (waitsScanPoll<WAITS_POLL_MIN)
-        waitsScanPoll = WAITS_POLL_MIN;
-      PORE_LOCATION(&ctx, tgtp3);
-	    pore_WAITS(&ctx, waitsScanPoll);
-  		pore_LDANDI(&ctx, D0, GENERIC_GP1_0x00000001, P1, P8_SCAN_POLL_MASK_BIT15);
-	   	PORE_LOCATION(&ctx, srcp3);
-	    pore_BRAZ(&ctx, D0, tgtp3);
-    	pore_inline_branch_fixup(&ctx, srcp3, tgtp3);
-      if (ctx.error > 0)  {
-        MY_ERR("***POLLING PROT(4) rc = %d", ctx.error);
-        return ctx.error;
-      }
-	  	rotateLen=0;
-
-    }
-    else  {                   // Do not use polling protocol.
-      MY_DBG("create_wiggle_flip: not using polling protocol\n");
-
-      scanRing_poreAddr=scanRing_baseAddr | rotateLen;
-      pore_LD(&ctx, D0, scanRing_poreAddr, P1);
-      if (ctx.error > 0)  {
-        MY_ERR("***LD D0 rc = %d", ctx.error);
-        return ctx.error;
-      }
-      rotateLen=0;
-
-    }
-  }
-
-  // Finally, check that our header check word went through in one piece.
-  // Note, we first do the MC-READ-AND check, then the MC-READ-OR check
-  //
-  // ...First, do the MC-READ-AND check
-  //    (Reference: setp1_mcreadand macro in ./ipl/sbe/p8_slw.H)
-  //
-  PoreInlineLocation src3=0, src5=0, src7=0, src8=0, tgt3=0, tgt5=0, tgt7=0, tgt8=0;
-  pore_MR( &ctx, D1, P0);
-  pore_ANDI( &ctx, D1, D1, BIT(57));
-  PORE_LOCATION( &ctx, src3);
-  pore_BRANZ( &ctx, D1, src3);
-  pore_MR( &ctx, P1, P0); // If here, MC=0. Omit MC check in OR case.
-  PORE_LOCATION( &ctx, src7);
-  pore_BRA( &ctx, tgt7);
-  PORE_LOCATION( &ctx, tgt3);
-  pore_MR( &ctx, D1, P0);
-  pore_ANDI( &ctx, D1, D1, CLEAR_MC_TYPE_MASK);
-  pore_ORI( &ctx, D1, D1, BIT(60));
-  pore_MR( &ctx, P1, D1);
-  if (ctx.error > 0)  {
-    MY_ERR("***setp1_mcreadand rc = %d", ctx.error);
-    return ctx.error;
-  }
-  pore_inline_branch_fixup( &ctx, src3, tgt3);
-  if (ctx.error > 0)  {
-    MY_ERR("***inline_branch_fixup error (3) rc = %d", ctx.error);
-    return ctx.error;
-  }
-  // ...Load the output check word...
-  pore_LD(&ctx, D0, scanRing_baseAddr, P1);
-  // Compare against the reference header check word...
-  pore_XORI( &ctx, D0, D0, ((uint64_t)scanRingCheckWord) << 32);
-  PORE_LOCATION( &ctx, src5);
-  pore_BRAZ( &ctx, D0, tgt5);
-  pore_inline_instruction1( &ctx, 0x34, 0x616C74);
-  pore_inline_instruction1( &ctx, 0x00, 0xCB0DA9);
-  PORE_LOCATION( &ctx, tgt5);
-  if (ctx.error > 0)  {
-    MY_ERR("***LD, XORI, BRANZ, RET or HALT went wrong  rc = %d", ctx.error);
-    return ctx.error;
-  }
-  pore_inline_branch_fixup( &ctx, src5, tgt5);
-  if (ctx.error > 0)  {
-    MY_ERR("***inline_branch_fixup error (5) rc = %d", ctx.error);
-    return ctx.error;
-  }
-  //
-  // ...Now do the MC-READ-OR check
-  //    (Reference: setp1_mcreador macro in ./ipl/sbe/p8_slw.H)
-  //    Note. If we made is this far, we know that MC=1 already, so don't check for it.
-  //
-  pore_MR( &ctx, D1, P0);
-  pore_ANDI( &ctx, D1, D1, CLEAR_MC_TYPE_MASK); // This also clears bit-60.
-  pore_MR( &ctx, P1, D1);
-  PORE_LOCATION( &ctx, tgt7);
-  if (ctx.error > 0)  {
-    MY_ERR("***setp1_mcreadand rc = %d", ctx.error);
-    return ctx.error;
-  }
-  pore_inline_branch_fixup( &ctx, src7, tgt7);
-  if (ctx.error > 0)  {
-    MY_ERR("***inline_branch_fixup error (7) rc = %d", ctx.error);
-    return ctx.error;
-  }
-  // ...Load the output check word...
-  pore_LD(&ctx, D0, scanRing_baseAddr, P1);
-  pore_XORI( &ctx, D0, D0, ((uint64_t)scanRingCheckWord) << 32);
-  PORE_LOCATION( &ctx, src8);
-  pore_BRAZ( &ctx, D0, tgt8);
-  pore_inline_instruction1( &ctx, 0x34, 0x616C74);
-  pore_inline_instruction1( &ctx, 0x00, 0xCB0DA9);
-  PORE_LOCATION( &ctx, tgt8);
-	pore_STI(&ctx, GENERIC_CLK_SCAN_UPDATEDR_0x0003A000, P0, 0x0);
-	pore_RET( &ctx);
-  if (ctx.error > 0)  {
-    MY_ERR("***LD, XORI, BRANZ, RET or HALT went wrong  rc = %d", ctx.error);
-    return ctx.error;
-  }
-  pore_inline_branch_fixup( &ctx, src8, tgt8);
-  if (ctx.error > 0)  {
-    MY_ERR("***inline_branch_fixup error (8) rc = %d", ctx.error);
-    return ctx.error;
-  }
-
-  *o_wfInlineLenInWords = ctx.lc/4;
-
-  // 8-byte align code, just as a precaution.
-  if ((*o_wfInlineLenInWords*4)%8)  {
-    // Insert 4-byte NOP at end.
-    pore_NOP( &ctx);
-    if (ctx.error > 0)  {
-      MY_ERR("***NOP went wrong rc = %d", ctx.error);
-      return ctx.error;
-    }
-    *o_wfInlineLenInWords = ctx.lc/4;
-  }
-
-  return rc;
-}
-
-
-#if !(defined IMGBUILD_PPD_CEN_XIP_CUSTOMIZE)
-
-// get_ring_layout_from_image()
-//
-int get_ring_layout_from_image( const void  *i_imageIn,
-                                uint32_t    i_ddLevel,
-                                uint8_t     i_sysPhase,
-                                DeltaRingLayout  *o_rs4RingLayout,
-                                void        **nextRing)
-{
-  uint32_t rc=0, rcLoc=0;
-  uint8_t bRingFound=0, bRingEOS=0;
-  DeltaRingLayout *thisRingLayout, *nextRingLayout; //Pointers into memory mapped image. DO NOT CHANGE MEMBERS!
-  uint32_t sizeInitf;
-  SbeXipSection hostSection;
-  void     *initfHostAddress0;
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  // Always first get the .initf stats from the TOC:
-  // - .initf host address offset and
-  // - .initf size
-  //
-  rc = sbe_xip_get_section( i_imageIn, SBE_XIP_SECTION_RINGS, &hostSection);
-  if (rc)   {
-      MY_ERR("sbe_xip_get_section() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-      MY_ERR("Probable cause:");
-      MY_ERR("\tThe section (=SBE_XIP_SECTION_RINGS=%i) was not found.",SBE_XIP_SECTION_RINGS);
-      return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  if (hostSection.iv_offset==0)  {
-    MY_INF("INFO : No ring data exists for the section ID = SBE_XIP_SECTION_RINGS (ID=%i).",SBE_XIP_SECTION_RINGS);
-    return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well.
-  }
-  initfHostAddress0 = (void*)((uintptr_t)i_imageIn + hostSection.iv_offset);
-  sizeInitf = hostSection.iv_size;
-
-  // On first call, get the base offset to the .initf section.
-  // On subsequent calls, we're into the search for ddLevel and sysPhase, so use nextRing instead.
-  //
-  if (*nextRing==NULL)
-    nextRingLayout = (DeltaRingLayout*)initfHostAddress0;
-  else
-    nextRingLayout = (DeltaRingLayout*)*nextRing;
-
-  MY_DBG("initfHostAddress0 = 0x%016llx",(uint64_t)initfHostAddress0);
-  MY_DBG("sizeInitf = %i", sizeInitf);
-  MY_DBG("nextRingLayout = 0x%016llx",(uint64_t)nextRingLayout);
-
-  // Populate the output RS4 ring BE layout structure as well as local structure in host LE format where needed.
-  // Note! Entire memory content is in BE format. So we do LE conversions where needed.
-  //
-  bRingFound = 0;
-  bRingEOS = 0;
-
-  // SEARCH loop:  Parse ring blocks successively until we find a ring that matches:
-  //     ddLevel == i_ddLevel
-  //     sysPhase == i_sysPhase
-  //
-  while (!bRingFound && !bRingEOS)  {
-    thisRingLayout = nextRingLayout;
-    MY_DBG("Next backItemPtr = 0x%016llx",myRev64(thisRingLayout->backItemPtr));
-    MY_DBG("Next ddLevel = 0x%02x",myRev32(thisRingLayout->ddLevel));
-    MY_DBG("Next sysPhase = %i",thisRingLayout->sysPhase);
-    MY_DBG("Next override = %i",thisRingLayout->override);
-    MY_DBG("Next reserved1 = %i",thisRingLayout->reserved1);
-    MY_DBG("Next reserved2 = %i",thisRingLayout->reserved2);
-
-    if (myRev32(thisRingLayout->ddLevel)==i_ddLevel)  { // Is there a non-specific DD level, like for sys phase?
-      if ((thisRingLayout->sysPhase==0 && i_sysPhase==0) ||
-          (thisRingLayout->sysPhase==1 && i_sysPhase==1) ||
-          (thisRingLayout->sysPhase==2 && (i_sysPhase==0 || i_sysPhase==1)))  {
-        bRingFound = 1;
-        MY_DBG("\tRing match found!");
-      }
-    }
-    nextRingLayout = (DeltaRingLayout*)((uintptr_t)thisRingLayout + myRev32(thisRingLayout->sizeOfThis));
-    *nextRing = (void*)nextRingLayout;
-    if (nextRingLayout>=(DeltaRingLayout*)((uintptr_t)initfHostAddress0+sizeInitf))  {
-      bRingEOS = 1;
-      *nextRing = NULL;
-      MY_DBG("\tRing search exhausted!");
-    }
-
-  }  // End of SEARCH.
-
-  if (bRingFound)  {
-    if (bRingEOS)
-      rcLoc = DSLWB_RING_SEARCH_EXHAUST_MATCH;
-    else
-      rcLoc = DSLWB_RING_SEARCH_MATCH;
-  }
-  else  {
-    *nextRing = NULL;
-    if (bRingEOS)
-      return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well.
-    else  {
-      MY_ERR("Messed up ring search. Check code and .rings content. Returning nothing.");
-      return DSLWB_RING_SEARCH_MESS;
-    }
-  }
-
-  o_rs4RingLayout->entryOffset = thisRingLayout->entryOffset;
-  o_rs4RingLayout->backItemPtr = thisRingLayout->backItemPtr;
-  o_rs4RingLayout->sizeOfThis  = thisRingLayout->sizeOfThis;
-  o_rs4RingLayout->sizeOfMeta  = thisRingLayout->sizeOfMeta;
-  o_rs4RingLayout->ddLevel     = thisRingLayout->ddLevel;
-  o_rs4RingLayout->sysPhase    = thisRingLayout->sysPhase;
-  o_rs4RingLayout->override    = thisRingLayout->override;
-  o_rs4RingLayout->reserved1   = thisRingLayout->reserved1;
-  o_rs4RingLayout->reserved2   = thisRingLayout->reserved2;
-  o_rs4RingLayout->metaData      =  (char*)(&thisRingLayout->reserved2 +
-                                            sizeof(thisRingLayout->reserved2));
-  o_rs4RingLayout->rs4Launch    = (uint32_t*)((uintptr_t)thisRingLayout +
-                                                myRev64(thisRingLayout->entryOffset));
-  // entryOffset, rs4Launch and ASM_RS4_LAUNCH_BUF_SIZE should already be 8-byte aligned.
-  o_rs4RingLayout->rs4Delta      = (uint32_t*)( (uintptr_t)thisRingLayout +
-                                                myRev64(thisRingLayout->entryOffset) +
-                                                ASM_RS4_LAUNCH_BUF_SIZE );
-
-  // Check that the ring layout structure in the memory is 8-byte aligned. This must
-	// be so because:
-  // - The entryOffset address must be on an 8-byte boundary because the start of the
-	//   .rings section must be 8-byte aligned AND because the rs4Delta member is the
-	//   last member and which must itself be 8-byte aligned.
-  // - These two things together means that both the beginning and end of the delta
-	//   ring layout must be 8-byte aligned, and thus the whole block, i.e. sizeOfThis,
-	//   must therefore automatically be 8-byte aligned.
-  // Also check that the RS4 delta ring is 8-byte aligned.
-  // Also check that the RS4 launcher is 8-byte aligned.
-  //
-  if (((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)%8 ||
-      myRev32(o_rs4RingLayout->sizeOfThis)%8 ||
-      myRev64(o_rs4RingLayout->entryOffset)%8 ||
-      ASM_RS4_LAUNCH_BUF_SIZE%8)  {
-    MY_ERR("Ring block or layout structure is not 8-byte aligned:");
-    MY_ERR("  thisRingLayout-imageIn = %i",(uintptr_t)thisRingLayout-(uintptr_t)i_imageIn);
-    MY_ERR("  o_rs4RingLayout->sizeOfThis = %i",myRev32(o_rs4RingLayout->sizeOfThis));
-    MY_ERR("  o_rs4RingLayout->entryOffset = %i",(uint32_t)myRev64(o_rs4RingLayout->entryOffset));
-    MY_ERR("  ASM_RS4_LAUNCH_BUF_SIZE = %i",(uint32_t)ASM_RS4_LAUNCH_BUF_SIZE);
-    return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT;
-  }
-
-  if (*nextRing > (void*)((uintptr_t)initfHostAddress0 + sizeInitf))  {
-    MY_INF("INFO : Book keeping got messed up during .initf search. Initf section does not appear aligned.");
-    MY_INF("initfHostAddress0+sizeInitf = 0x%016llx",(uint64_t)initfHostAddress0+sizeInitf);
-    MY_INF("nextRing = %i",*(uint32_t*)nextRing);
-    MY_INF("Continuing...");
-  }
-
-  return rcLoc;
-}
-
-
-
-// write_wiggle_flip_to_image()
-int write_wiggle_flip_to_image( void *io_imageOut,
-                                uint32_t  *i_sizeImageMaxNew,
-                                DeltaRingLayout *i_ringLayout,
-                                uint32_t  *i_wfInline,
-                                uint32_t  i_wfInlineLenInWords)
-{
-  uint32_t rc=0, bufLC;
-	int      deltaLC, i;
-  uint32_t sizeImageIn, sizeNewDataBlock;
-  uint32_t sizeImageOutThisEst=0, sizeImageOutThis=0;
-  void *ringsBuffer=NULL;
-  uint32_t ringRingsOffset=0;
-  uint64_t ringPoreAddress=0,backPtr=0,fwdPtr=0,fwdPtrCheck;
-
-	SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  MY_DBG("wfInlineLenInWords=%i", i_wfInlineLenInWords);
-
-  // Modify the input ring layout content
-  // - Remove the qualifier section: ddLevel, sysPhase, override and reserved1+2.
-  //   This means reducing the entryOffset by the size of these qualifiers.
-  // - The new WF ring block and start of WF code must both be 8-byte aligned.
-  //   - RS4 entryOffset is already 8-byte aligned.
-  //   - The WF code section, i.e. wfInlineLenInWords, is already 8-byte aligned.
-  //
-  i_ringLayout->entryOffset  =
-    myRev64(  myByteAlign(8, myRev64(i_ringLayout->entryOffset) -
-                             sizeof(i_ringLayout->ddLevel) -
-                             sizeof(i_ringLayout->sysPhase) -
-                             sizeof(i_ringLayout->override) -
-                             sizeof(i_ringLayout->reserved1) -
-                             sizeof(i_ringLayout->reserved2) ) );
-  i_ringLayout->sizeOfThis   =
-    myRev32( myRev64(i_ringLayout->entryOffset) + i_wfInlineLenInWords*4 );
-
-  // Not really any need for this. Just being consistent. Once we have transitioned completely to new
-  //  headers, then ditch i_wfInline from parm list and assign wfInline to layout in main program.
-  i_ringLayout->wfInline    = i_wfInline;
-
-  if (myRev64(i_ringLayout->entryOffset)%8 || myRev32(i_ringLayout->sizeOfThis)%8)  {
-    MY_ERR("Ring block or WF code origin not 8-byte aligned.");
-    return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT;
-  }
-
-  // Calc the size of the data section we're adding and the resulting output image.
-  //
-  rc = sbe_xip_image_size( io_imageOut, &sizeImageIn);
-  if (rc)  {
-    MY_ERR("sbe_xip_image_size() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  sizeNewDataBlock = myRev32(i_ringLayout->sizeOfThis);
-  // ...estimate max size of new image
-  sizeImageOutThisEst = sizeImageIn + sizeNewDataBlock + SBE_XIP_MAX_SECTION_ALIGNMENT; //
-
-  if (sizeImageOutThisEst>*i_sizeImageMaxNew)  {
-    MY_ERR("Estimated new image size (=%i) would exceed max allowed size (=%i).",
-      sizeImageOutThisEst, *i_sizeImageMaxNew);
-    *i_sizeImageMaxNew = sizeImageOutThisEst;
-    return IMGBUILD_ERR_IMAGE_TOO_LARGE;
-  }
-
-  MY_DBG("Input image size\t\t= %6i\n\tNew rings data block size\t= %6i\n\tOutput image size (max)\t\t<=%6i",
-    sizeImageIn, sizeNewDataBlock, sizeImageOutThisEst);
-  MY_DBG("entryOffset = %i\n\tsizeOfThis = %i\n\tMeta data size = %i",
-    (uint32_t)myRev64(i_ringLayout->entryOffset), myRev32(i_ringLayout->sizeOfThis), myRev32(i_ringLayout->sizeOfMeta));
-  MY_DBG("Back item ptr = 0x%016llx",myRev64(i_ringLayout->backItemPtr));
-  MY_DBG("DD level = 0x%02x\n\tSys phase = %i\n\tOverride = %i\n\tReserved1+2 = %i",
-    myRev32(i_ringLayout->ddLevel), i_ringLayout->sysPhase, i_ringLayout->override, i_ringLayout->reserved1|i_ringLayout->reserved2);
-
-  // Combine rs4RingLayout members into a unified buffer (ringsBuffer).
-  //
-  ringsBuffer = malloc((size_t)sizeNewDataBlock);
-  if (ringsBuffer == NULL)  {
-    MY_ERR("malloc() of initf buffer failed.");
-    return IMGBUILD_ERR_MEMORY;
-  }
-  // ... First, copy WF ring layout header into ringsBuffer in BIG-ENDIAN format.
-  bufLC = 0;
-  deltaLC =  (uintptr_t)&i_ringLayout->ddLevel-(uintptr_t)&i_ringLayout->entryOffset;
-  memcpy( (uint8_t*)ringsBuffer+bufLC, &i_ringLayout->entryOffset, deltaLC);
-  // ... then meta data
-  bufLC = bufLC + deltaLC;
-  deltaLC = myRev32(i_ringLayout->sizeOfMeta);
-  memcpy( (uint8_t*)ringsBuffer+bufLC, i_ringLayout->metaData, deltaLC);
-  // ... Is this padding or WF buffer?
-  bufLC = bufLC + deltaLC;
-  deltaLC = (uint32_t)myRev64(i_ringLayout->entryOffset) - bufLC;
-  if (deltaLC<0 || deltaLC>=8)  {
-	  MY_ERR("Ring layout mess. Check code or delta_scan(). deltaLC=%i",deltaLC);
-      if(ringsBuffer) free(ringsBuffer);
-	  return IMGBUILD_ERR_CHECK_CODE;
-	}
-  if (deltaLC>0)  {
-    // OK, it's padding time.
-    for (i=0; i<deltaLC; i++)
-      *(uint8_t*)((uint8_t*)ringsBuffer+bufLC+i) = 0;
-  }
-  // ... now do the WF buffer
-  bufLC = bufLC + deltaLC;
-  if (bufLC!=(uint32_t)myRev64(i_ringLayout->entryOffset))  {
-    MY_ERR("Ring layout messup. Check code or delta_scan().");
-    return IMGBUILD_ERR_CHECK_CODE;
-  }
-  deltaLC = i_wfInlineLenInWords*4;
-  memcpy( (uint8_t*)ringsBuffer+bufLC, i_wfInline, deltaLC);
-
-  // Append WF ring layout to .rings section of in-memory input image.
-  //   Note! All layout members should already be 8-byte aligned.
-  //
-  rc = sbe_xip_append( io_imageOut,
-                       SBE_XIP_SECTION_RINGS,
-                       (void*)ringsBuffer,
-                       sizeNewDataBlock,
-                       sizeImageOutThisEst,
-                       &ringRingsOffset);
-  MY_DBG("ringRingsOffset=0x%08x",ringRingsOffset);
-  if (rc)   {
-    MY_ERR("sbe_xip_append() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    if (ringsBuffer)  free(ringsBuffer);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  // ...get new image size, update return size, and test if successful update.
-  sbe_xip_image_size( io_imageOut, &sizeImageOutThis);
-  MY_DBG("Output image size (final)\t=%i",sizeImageOutThis);
-  *i_sizeImageMaxNew = sizeImageOutThis;
-  rc = sbe_xip_validate( io_imageOut, sizeImageOutThis);
-  if (rc)   {
-    MY_ERR("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    if (ringsBuffer)  free(ringsBuffer);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  MY_DBG("Successful append of RS4 ring to .rings. Next, update forward ptr...");
-
-  // Update forward pointer associated with the ring/var name + any override offset.
-  //
-  // Convert the ring offset (wrt .rings address) to an PORE address
-  rc = sbe_xip_section2pore(io_imageOut, SBE_XIP_SECTION_RINGS, ringRingsOffset, &ringPoreAddress);
-  fwdPtr = ringPoreAddress;
-  MY_DBG("fwdPtr=0x%016llx", fwdPtr);
-  if (rc)   {
-    MY_ERR("sbe_xip_section2pore() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    if (ringsBuffer)  free(ringsBuffer);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  // ...then update the forward pointer, i.e. the old "variable/ring name's" pointer.
-  //    DO NOT add any 8-byte offset if override ring. The backItemPtr already has this
-  //    from p8_delta_scan.
-  //
-  backPtr = myRev64(i_ringLayout->backItemPtr);
-  MY_DBG("backPtr = 0x%016llx",  backPtr);
-  rc = sbe_xip_write_uint64(  io_imageOut,
-                              backPtr,
-                              fwdPtr);
-  rc = rc+sbe_xip_read_uint64(io_imageOut,
-                              backPtr,
-                              &fwdPtrCheck);
-  if (rc)  {
-    MY_ERR("sbe_xip_[write,read]_uint64() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    if (ringsBuffer)  free(ringsBuffer);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  if (fwdPtrCheck!=ringPoreAddress || backPtr!=myRev64(i_ringLayout->backItemPtr))  {
-    MY_ERR("Forward or backward pointer mess. Check code.");
-    MY_ERR("fwdPtr       =0x%016llx",fwdPtr);
-    MY_ERR("fwdPtrCheck  =0x%016llx",fwdPtrCheck);
-    MY_ERR("layout bckPtr=0x%016llx",myRev64(i_ringLayout->backItemPtr));
-    MY_ERR("backPtr      =0x%016llx",backPtr);
-    if (ringsBuffer)  free(ringsBuffer);
-    return IMGBUILD_ERR_FWD_BACK_PTR_MESS;
-  }
-  // ...test if successful update.
-  rc = sbe_xip_validate( io_imageOut, sizeImageOutThis);
-  if (rc)   {
-    MY_ERR("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tsbe_xip_write_uint64() updated at the wrong address (=0x%016llx)",
-      myRev64(i_ringLayout->backItemPtr));
-    if (ringsBuffer)  free(ringsBuffer);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-
-  if (ringsBuffer)  free(ringsBuffer);
-
-  return rc;
-}
-
-
-
-// append_empty_section()
-int append_empty_section( void      *io_image,
-                          int       *i_sizeImageMaxNew,
-                          uint32_t  i_sectionId,
-                          int       *i_sizeSection,
-													uint8_t   i_bFixed)
-{
-  int      rc=0;
-  uint32_t sizeImageIn=0, sizeImageOutThis=0;
-	int      sizeImageOutThisEst=0;
-  uint32_t offsetCheck=1;
- 	SbeXipSection xipSection;
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  rc = 0;
-
-  if (*i_sizeSection==0)  {
-    MY_INF("INFO : Requested append size = 0. Nothing to do.");
-    return rc;
-  }
-
-  // Check if there is enough room in the new image to add section.
-  //
-  sbe_xip_image_size( io_image, &sizeImageIn);
-  // ...estimate max size of new image
-	if (i_bFixed)
-  	sizeImageOutThisEst = sizeImageIn + *i_sizeSection;
-  else
-		sizeImageOutThisEst = sizeImageIn + *i_sizeSection + SBE_XIP_MAX_SECTION_ALIGNMENT;
-  if (sizeImageOutThisEst>*i_sizeImageMaxNew)  {
-    MY_ERR("Estimated new image size (=%i) would exceed max allowed size (=%i).",
-      sizeImageOutThisEst, *i_sizeImageMaxNew);
-    *i_sizeImageMaxNew = sizeImageOutThisEst;
-    return IMGBUILD_ERR_IMAGE_TOO_LARGE;
-  }
-
-  // Add the NULL buffer as a section append. sbe_xip_append() initializes with 0s.
-  //
-  rc = sbe_xip_append( io_image,
-                       i_sectionId,
-                       NULL,
-                       *i_sizeSection,
-                       sizeImageOutThisEst,
-                       &offsetCheck);
-  if (rc)  {
-    MY_ERR("xip_append() failed: %s\n",SBE_XIP_ERROR_STRING(errorStrings, rc));
-    return DSLWB_SLWB_IMAGE_ERROR;
-  }
-  if (offsetCheck)
-    MY_INF("INFO : Section was not empty at time of xip_append(). It contained %i bytes.",offsetCheck);
-  // ...get new image size, update return size, and test if successful update.
-  sbe_xip_image_size( io_image, &sizeImageOutThis);
-  MY_DBG("Output image size (after section append) = %i\n",sizeImageOutThis);
-  *i_sizeImageMaxNew = sizeImageOutThis;
-  rc = sbe_xip_validate( io_image, sizeImageOutThis);
-  if (rc)   {
-    MY_ERR("xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-
-	// Return final section size.
-	//
-  rc = sbe_xip_get_section( io_image, i_sectionId, &xipSection);
- 	*i_sizeSection = xipSection.iv_size;
-
-  return rc;
-}
-
-
-
-// initialize_slw_section()
-// - allocate space for Ramming and Scomming
-// - populate Scomming table with ret/nop/nop/nop (RNNN) inline asm instructions
-// - update Scomming vector
-int initialize_slw_section( void      *io_image,
-                            uint32_t  *i_sizeImageMaxNew)
-{
-  uint32_t rc=0, i_coreId=0, i_iis=0;
-  PoreInlineContext ctx;
-  SbeXipSection  xipSection;
-  SbeXipItem     xipTocItem;
-	int    sizeSectionChk=0;
-  void   *hostScomTableNext, *hostScomVectorNext;
-	void   *hostScomVectorFirstNC, *hostScomVectorFirstL2, *hostScomVectorFirstL3;
-	void   *hostScomTableNC, *hostScomTableL2, *hostScomTableL3;
-  uint64_t xipScomTableNC, xipScomTableL2, xipScomTableL3;
-  uint8_t  bufRNNN[XIPSIZE_SCOM_ENTRY];
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  sizeSectionChk = FIXED_SLW_SECTION_SIZE;
-  rc = append_empty_section( io_image,
-                             (int*)i_sizeImageMaxNew,
-                             SBE_XIP_SECTION_SLW,
-                             &sizeSectionChk,
-														 0);
-  if (rc)
-    return rc;
-  if (sizeSectionChk!=FIXED_SLW_SECTION_SIZE)  {
-    MY_ERR("Section size of .slw (=%i) not equal to requested size (=%zi).\n",
-      sizeSectionChk, FIXED_SLW_SECTION_SIZE);
-    return IMGBUILD_ERR_SECTION_SIZING;
-  }
-
-  //
-  // Ramming table:  Nothing to do.  Already 0-initialized in append_empty_section().
-  //
-
-  //
-  // Scomming table:  Fill with RNNN (16-byte) instruction sequences.
-  //
-
-  // ... create RNNN instruction sequence.
-  pore_inline_context_create( &ctx, (void*)bufRNNN, XIPSIZE_SCOM_ENTRY, 0, 0);
-  pore_RET( &ctx);
-  pore_NOP( &ctx);
-  pore_NOP( &ctx);
-  pore_NOP( &ctx);
-  if (ctx.error > 0)  {
-    MY_ERR("***_RET or _NOP generated rc = %d", ctx.error);
-    return IMGBUILD_ERR_PORE_INLINE_ASM;
-  }
-
-  // ... get host and pore location of Scom table in .slw section.
-	// Note that we will assume, further down, that the NC section goes first,
-	//   then the L2 section and then the L3 section.
-  rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-  if (rc)   {
-    MY_ERR("sbe_xip_get_section() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe section (=SBE_XIP_SECTION_SLW=%i) was not found.",SBE_XIP_SECTION_SLW);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  hostScomTableNC = (void*)((uintptr_t)io_image + xipSection.iv_offset + SLW_RAM_TABLE_SIZE);
-
-  // ... populate entire Scom table with RNNN IIS, incl NC, L2 and L3 sections.
-  for (i_iis=0; i_iis<SLW_SCOM_TABLE_SIZE_ALL; i_iis=i_iis+XIPSIZE_SCOM_ENTRY)  {
-    hostScomTableNext = (void*)( (uintptr_t)hostScomTableNC + i_iis);
-    memcpy( hostScomTableNext, (void*)bufRNNN, XIPSIZE_SCOM_ENTRY);
-  }
-
-	hostScomTableL2 = (void*)((uintptr_t)hostScomTableNC + SLW_SCOM_TABLE_SIZE_NC);
-	hostScomTableL3 = (void*)((uintptr_t)hostScomTableL2 + SLW_SCOM_TABLE_SIZE_L2);
-
-	// ... get location of  ----> Scom NC <----  vector from TOC.
-  rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_SCOM_NC_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVectorFirstNC);
-
-  // ... update Scom NC vector.
-	sbe_xip_host2pore( io_image, hostScomTableNC, &xipScomTableNC);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostScomVectorNext = (void*)( (uint64_t*)hostScomVectorFirstNC + i_coreId);
-    *(uint64_t*)hostScomVectorNext = myRev64( xipScomTableNC +
-                                              SLW_SCOM_TABLE_SPACE_PER_CORE_NC*i_coreId);
-  }
-
-	// ... get location of  ----> Scom L2 <----  vector from TOC.
-  rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L2_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_SCOM_L2_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVectorFirstL2);
-
-  // ... update Scom L2 vector.
-	sbe_xip_host2pore( io_image, hostScomTableL2, &xipScomTableL2);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostScomVectorNext = (void*)( (uint64_t*)hostScomVectorFirstL2 + i_coreId);
-    *(uint64_t*)hostScomVectorNext = myRev64( xipScomTableL2 +
-                                              SLW_SCOM_TABLE_SPACE_PER_CORE_L2*i_coreId);
-  }
-
-	// ... get location of  ----> Scom L3 <----  vector from TOC.
-  rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L3_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_SCOM_L3_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVectorFirstL3);
-
-  // ... update Scom L3 vector.
-	sbe_xip_host2pore( io_image, hostScomTableL3, &xipScomTableL3);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostScomVectorNext = (void*)( (uint64_t*)hostScomVectorFirstL3 + i_coreId);
-    *(uint64_t*)hostScomVectorNext = myRev64( xipScomTableL3 +
-                                              SLW_SCOM_TABLE_SPACE_PER_CORE_L3*i_coreId);
-  }
-
-  return rc;
-}
-
-
-
-// create_and_initialize_fixed_image()
-// - swell image to fixed size of 1MB by:
-//   - appending elastic section .fit
-//   - appending fixed section .slw
-//     - allocate space for Ramming and Scomming
-//   - appending fixed section .ffdc
-// - populate Scomming table with ret/nop/nop/nop (RNNN) inline asm instructions
-// - update Scomming vector
-int create_and_initialize_fixed_image( void      *io_image)
-{
-  int      rc=0;
-  uint32_t i_coreId=0, i_iis=0;
-  uint32_t sizeImageIn=0;
-	int      sizeImageChk=0;
-  int      sizeSectionFit=0, sizeSectionReq=0, sizeSectionChk=0;
-  PoreInlineContext ctx;
-  SbeXipSection  xipSection;
-  SbeXipItem     xipTocItem;
-  void   *hostRamVectorFirst, *hostRamVectorNext, *hostRamTable;
-	void   *hostScomVectorFirstNC, *hostScomVectorFirstL2, *hostScomVectorFirstL3;
-	void   *hostScomVectorNext;
-	void   *hostScomTableNC, *hostScomTableL2, *hostScomTableL3;
-	void   *hostScomTableNext;
-  uint64_t xipRamTable, xipScomTableNC, xipScomTableL2, xipScomTableL3;
-  uint8_t  bufRNNN[XIPSIZE_SCOM_ENTRY];
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  sbe_xip_image_size( io_image, &sizeImageIn);
-
-	// Ensure, to play it safe, that last two sections (.slw & .ffdc) are both on
-	// 128-byte boundaries. The max [fixed] image size must itself already be
-	// 128-byte aligned.
-  sizeSectionFit  = (int) ( FIXED_SLW_IMAGE_SIZE -
-                    				sizeImageIn -
-                    				FIXED_SLW_SECTION_SIZE -
-                    				FIXED_FFDC_SECTION_SIZE );
-  if (sizeSectionFit<0)  {
-    MY_ERR("Size of .fit section (=%i) can not be negative.\n",sizeSectionFit);
-    MY_ERR("Size of fixed image   = %i\n",FIXED_SLW_IMAGE_SIZE);
-    MY_ERR("Size of input image   = %i\n",sizeImageIn);
-    MY_ERR("Size of .slw section  = %zi\n",FIXED_SLW_SECTION_SIZE);
-    MY_ERR("Size of .ffdc section = %i\n",FIXED_FFDC_SECTION_SIZE);
-    return IMGBUILD_ERR_SECTION_SIZING;
-  }
-
-  // Append .fit
-  //
-  sizeImageChk = FIXED_SLW_IMAGE_SIZE;
-	sizeSectionReq = sizeSectionFit;
-	sizeSectionChk = sizeSectionReq;
-	MY_INF("Appending .fit w/size=%i\n",sizeSectionReq);
-  rc = append_empty_section( io_image,
-                             &sizeImageChk,
-                             SBE_XIP_SECTION_FIT,
-                             &sizeSectionChk,
-														 1);
-  if (rc)
-    return rc;
-	if (sizeSectionChk!=sizeSectionReq)  {
-		MY_ERR("Section size of .fit (=%i) not equal to requested size (=%i).\n",
-		  sizeSectionChk, sizeSectionReq);
-		return IMGBUILD_ERR_SECTION_SIZING;
-	}
-
-  // Append .slw
-  //
-  sizeImageChk = FIXED_SLW_IMAGE_SIZE;
-	sizeSectionReq = FIXED_SLW_SECTION_SIZE;
-	sizeSectionChk = sizeSectionReq;
-	MY_INF("Appending .slw w/size=%i\n",sizeSectionReq);
-  rc = append_empty_section( io_image,
-                             &sizeImageChk,
-                             SBE_XIP_SECTION_SLW,
-                             &sizeSectionChk,
-														 1);
-  if (rc)
-    return rc;
-	if (sizeSectionChk!=sizeSectionReq)  {
-		MY_INF("Section size of .slw (=%i) not equal to requested size (=%i).\n",
-		  sizeSectionChk, sizeSectionReq);
-		return IMGBUILD_ERR_SECTION_SIZING;
-	}
-
-
-  // Append .ffdc
-  //
-  sizeImageChk = FIXED_SLW_IMAGE_SIZE;
-	sizeSectionReq = FIXED_FFDC_SECTION_SIZE;
-	sizeSectionChk = sizeSectionReq;
-	MY_ERR("Appending .ffdc w/size=%i\n",sizeSectionReq);
-  rc = append_empty_section( io_image,
-                             &sizeImageChk,
-                             SBE_XIP_SECTION_FFDC,
-                             &sizeSectionChk,
-														 1);
-  if (rc)
-    return rc;
-	if (sizeSectionChk!=sizeSectionReq)  {
-		MY_ERR("Section size of .ffdc (=%i) not equal to requested size (=%i).\n",
-		  sizeSectionChk, sizeSectionReq);
-		return IMGBUILD_ERR_SECTION_SIZING;
-	}
-
-  // --------------------------------------------------------------------------
-  // Ramming table:   Already 0-initialized in append_empty_section().
-  // --------------------------------------------------------------------------
-
-  // ... calc host ptr to Ram table in .slw section.
-  rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-  if (rc)   {
-    MY_ERR("sbe_xip_get_section() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe section (=SBE_XIP_SECTION_SLW=%i) was not found.",SBE_XIP_SECTION_SLW);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  hostRamTable = (void*)((uintptr_t)io_image + xipSection.iv_offset);
-
-	// ... get location of Ram vector.
-  rc = sbe_xip_find( io_image, SLW_HOST_REG_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_REG_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostRamVectorFirst);
-
-  // ... update Ram vector.
-	sbe_xip_host2pore( io_image, hostRamTable, &xipRamTable);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostRamVectorNext = (void*)( (uint64_t*)hostRamVectorFirst + i_coreId);
-    *(uint64_t*)hostRamVectorNext = myRev64( xipRamTable +
-                                              SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId);
-  }
-
-  // --------------------------------------------------------------------------
-  // Scomming table:  Fill with RNNN (16-byte) instruction sequences.
-  // --------------------------------------------------------------------------
-
-  // ... create RNNN instruction sequence.
-  pore_inline_context_create( &ctx, (void*)bufRNNN, XIPSIZE_SCOM_ENTRY, 0, 0);
-  pore_RET( &ctx);
-  pore_NOP( &ctx);
-  pore_NOP( &ctx);
-  pore_NOP( &ctx);
-  if (ctx.error > 0)  {
-    MY_ERR("***_RET or _NOP generated rc = %d", ctx.error);
-    return IMGBUILD_ERR_PORE_INLINE_ASM;
-  }
-
-	// ... calc host ptr to Scom NC subsection.
-	// Note that we will assume, further down, that the NC section goes first,
-	//   then the L2 section and then the L3 section.
-  rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-  if (rc)   {
-    MY_ERR("sbe_xip_get_section() failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe section (=SBE_XIP_SECTION_SLW=%i) was not found.",SBE_XIP_SECTION_SLW);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  hostScomTableNC = (void*)((uintptr_t)io_image + xipSection.iv_offset + SLW_RAM_TABLE_SIZE);
-
-  // ... populate entire Scom table with RNNN IIS, incl NC, L2 and L3 sections.
-  for (i_iis=0; i_iis<SLW_SCOM_TABLE_SIZE_ALL; i_iis=i_iis+XIPSIZE_SCOM_ENTRY)  {
-    hostScomTableNext = (void*)( (uintptr_t)hostScomTableNC + i_iis);
-    memcpy( hostScomTableNext, (void*)bufRNNN, XIPSIZE_SCOM_ENTRY);
-  }
-
-	hostScomTableL2 = (void*)((uintptr_t)hostScomTableNC + SLW_SCOM_TABLE_SIZE_NC);
-	hostScomTableL3 = (void*)((uintptr_t)hostScomTableL2 + SLW_SCOM_TABLE_SIZE_L2);
-
-	// ... get location of  ----> Scom NC <----  vector from TOC.
-  rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_SCOM_NC_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVectorFirstNC);
-
-  // ... update Scom NC vector.
-	sbe_xip_host2pore( io_image, hostScomTableNC, &xipScomTableNC);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostScomVectorNext = (void*)( (uint64_t*)hostScomVectorFirstNC + i_coreId);
-    *(uint64_t*)hostScomVectorNext = myRev64( xipScomTableNC +
-                                              SLW_SCOM_TABLE_SPACE_PER_CORE_NC*i_coreId);
-  }
-
-	// ... get location of  ----> Scom L2 <----  vector from TOC.
-  rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L2_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_SCOM_L2_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVectorFirstL2);
-
-  // ... update Scom L2 vector.
-	sbe_xip_host2pore( io_image, hostScomTableL2, &xipScomTableL2);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostScomVectorNext = (void*)( (uint64_t*)hostScomVectorFirstL2 + i_coreId);
-    *(uint64_t*)hostScomVectorNext = myRev64( xipScomTableL2 +
-                                              SLW_SCOM_TABLE_SPACE_PER_CORE_L2*i_coreId);
-  }
-
-	// ... get location of  ----> Scom L3 <----  vector from TOC.
-  rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L3_VECTOR_TOC_NAME, &xipTocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_HOST_SCOM_L3_VECTOR_TOC_NAME);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVectorFirstL3);
-
-  // ... update Scom L3 vector.
-	sbe_xip_host2pore( io_image, hostScomTableL3, &xipScomTableL3);
-  for (i_coreId=0; i_coreId<SLW_MAX_CORES; i_coreId++)  {
-    hostScomVectorNext = (void*)( (uint64_t*)hostScomVectorFirstL3 + i_coreId);
-    *(uint64_t*)hostScomVectorNext = myRev64( xipScomTableL3 +
-                                              SLW_SCOM_TABLE_SPACE_PER_CORE_L3*i_coreId);
-  }
-
-  return rc;
-}
-
-
-
-// update_runtime_scom_pointer()
-// - reprogram host_runtime_scom data to point to sub_slw_runtime_scom
-// - reprogram ex_enable_runtime_scom data to point to sub_slw_ex_enable_runtime_scom
-int update_runtime_scom_pointer( void *io_image)
-{
-  int rc=0;
-  uint64_t xipSlwRuntimeAddr;
-//	uint64_t xipSlwExEnableRuntimeAddr;
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-	// Get address of sub_slw_runtime_scom subroutine.
-	//
-	rc = sbe_xip_get_scalar( io_image, SLW_RUNTIME_SCOM_TOC_NAME, &xipSlwRuntimeAddr);
-  if (rc)  {
-    MY_ERR("sbe_xip_set_scalar() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",SLW_RUNTIME_SCOM_TOC_NAME);
-		return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-
-	// Update host_runtime_scom with sub_slw_runtime_scom's address.
-	//
-  rc = sbe_xip_set_scalar( io_image, HOST_RUNTIME_SCOM_TOC_NAME, xipSlwRuntimeAddr);
-  if (rc)  {
-    MY_ERR("sbe_xip_set_scalar() failed w/rc=%i and %s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-    MY_ERR("Probable cause:");
-    MY_ERR("\tThe keyword (=%s) was not found.",HOST_RUNTIME_SCOM_TOC_NAME);
-		return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-
-/*
-  // Get address of sub_slw_ex_enable_runtime_scom subroutine.
-	//
-	rc = sbe_xip_get_scalar( io_image, SLW_EX_ENABLE_RUNTIME_SCOM_TOC_NAME, &xipSlwExEnableRuntimeAddr);
-  if (rc)  {
-    MY_INF("WARNING : sbe_xip_get_scalar() failed w/rc=%i and msg=%s, but it's probably OK.", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-		MY_INF("Will skip trying to update ex_enable_runtime_scom.\n");
-    MY_INF("Probable cause:");
-    MY_INF("\tThe keyword (=%s) was not found.",SLW_EX_ENABLE_RUNTIME_SCOM_TOC_NAME);
-  }
-  else  {
-		// Next, update ex_enable_runtime_scom with sub_slw_ex_enable_runtime_scom's address.
-		// (Assumption is that if sub_slw_ex_enable... exists then ex_enable... exists too.)
-	  rc = sbe_xip_set_scalar( io_image, EX_ENABLE_RUNTIME_SCOM_TOC_NAME, xipSlwExEnableRuntimeAddr);
-	  if (rc)  {
-	    MY_ERR("sbe_xip_set_scalar() failed w/rc=%i and msg=%s", rc, SBE_XIP_ERROR_STRING(errorStrings, rc));
-			MY_ERR("This is an odd error, indicating messed up or old image.\n");
-	    MY_ERR("Probable cause:");
-	    MY_ERR("\tThe keyword (=%s) was not found.",EX_ENABLE_RUNTIME_SCOM_TOC_NAME);
-			return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-	  }
-	}
-*/
-
-  return 0;
-}
-
-
-// write_vpd_ring_to_ipl_image()
-// - For VPD rings, there is no notion of a base and override ring. There can only be
-//   one ring. Thus, for core ID specific rings, their vector locations are updated only
-//   by 8-bytes, unlike 16-bytes for non-VPD rings which have base+override.
-// - Any ring, including ex_ rings, that have a chipletId==0xFF will get stored at its
-//   zero-offset position, i.e. as if it was coreId=0, or chipletId=0x10.
-// - For IPL images, #R/G must be accessible through .fixed_toc since .toc is removed.
-//   and same is true for proc_sbe_decompress_scan_chiplet_address (for RS4 launch.)
-// Notes:
-// - This code has great similarity to write_delta_ring_to_image() in p8_delta_scan_w.C.
-//   Consider merging the two codes.
-int write_vpd_ring_to_ipl_image(void			*io_image,
-                                uint32_t  &io_sizeImageOut,
-														  	CompressedScanData *i_bufRs4Ring, // HB buf1. BE format.
-															  uint32_t  i_ddLevel,
-															  uint8_t   i_sysPhase,
-															  char 			*i_ringName,
-															  void      *i_bufTmp,              // HB buf2
-															  uint32_t  i_sizeBufTmp,
-                                uint8_t   i_xipSectionId)         // Used by delta_scan()
-{
-	uint32_t rc=0, bufLC;
-	uint8_t  chipletId, idxVector=0;
-	uint32_t sizeRs4Launch, sizeRs4Ring;
-	uint32_t sizeImageIn,sizeImage;
-	PoreInlineContext ctx;
-	uint32_t asmInitLC=0;
-	uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4];
-	uint64_t scanChipletAddress=0;
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-	MY_INF("i_ringName=%s; \n",	i_ringName);
-
-  if (i_bufTmp == NULL)  {
-    MY_ERR("\tTemporary ring buffer passed by caller points to NULL and is invalid.\n");
-    return IMGBUILD_ERR_MEMORY;
-  }
-
-  sbe_xip_image_size( io_image, &sizeImageIn);
-
-  chipletId = i_bufRs4Ring->iv_chipletId;
-
-	// Create RS4 launcher and store in asmBuffer.
-	//
-	rc = sbe_xip_get_scalar( io_image, "proc_sbe_decompress_scan_chiplet_address", &scanChipletAddress);
-  if (rc)   {
-      MY_INF("\tWARNING: sbe_xip_get_scalar() failed: %s\n", SBE_XIP_ERROR_STRING(errorStrings, rc));
-      if (rc==SBE_XIP_ITEM_NOT_FOUND)  {
-				MY_ERR("\tProbable cause:\n");
-				MY_ERR("\t\tThe key word (=proc_sbe_decompress_scan_chiplet_address) does not exist in the image. (No TOC record.)\n");
-				return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-			}
-			else
-      if (rc==SBE_XIP_BUG)  {
-				MY_ERR("\tProbable cause:\n");
-				MY_ERR("\t\tIllegal keyword, maybe?\n");
-				return IMGBUILD_ERR_XIP_MISC;
-			}
-			else  {
-				MY_ERR("\tUnknown cause.\n");
-  	    return IMGBUILD_ERR_XIP_UNKNOWN;
-  	  }
-  }
-  if (scanChipletAddress==0)  {
-  	MY_ERR("\tValue of key word (proc_sbe_decompress_scan_chiplet_address=0) is not permitted. Exiting.\n");
-  	return IMGBUILD_ERR_CHECK_CODE;
-  }
-  // Now, create the inline assembler code.
-	rc = pore_inline_context_create( &ctx, asmBuffer, ASM_RS4_LAUNCH_BUF_SIZE, asmInitLC, 0);
-	if (rc)  {
-		MY_ERR("\tpore_inline_context_create() failed w/rc=%i =%s\n", rc, pore_inline_error_strings[rc]);
-		return IMGBUILD_ERR_PORE_INLINE;
-	}
-	pore_MR(&ctx, A0, PC);
-	pore_ADDS(&ctx, A0, A0, ASM_RS4_LAUNCH_BUF_SIZE);
-	pore_LI(&ctx, D0, scanChipletAddress);
-	pore_BRAD(&ctx, D0);
-	if (ctx.error)  {
-		MY_ERR("\tpore_MR/ADDS/LI/BRAD() failed w/rc=%i =%s\n", ctx.error, pore_inline_error_strings[ctx.error]);
-		return IMGBUILD_ERR_PORE_INLINE_ASM;
-	}
-
-	// Check sizeRs4Launch and that sizeRs4Launch and sizeRs4Ring both are 8-byte aligned.
-	sizeRs4Launch = ctx.lc - asmInitLC;
-	sizeRs4Ring = myRev32(i_bufRs4Ring->iv_size);
-	if (sizeRs4Launch!=ASM_RS4_LAUNCH_BUF_SIZE)  {
-		MY_ERR("\tSize of RS4 launch code differs from assumed size.\n\tsizeRs4Launch=%i\n\tASM_RS4_LAUNCH_BUF_SIZE=%i\n",
-		  sizeRs4Launch,ASM_RS4_LAUNCH_BUF_SIZE);
-			return IMGBUILD_ERR_CHECK_CODE;
-	}
-	if (sizeRs4Launch%8 || sizeRs4Ring%8)  {
-		MY_ERR("\tRS4 launch code or data not 8-byte aligned.\n\tsizeRs4Launch=%i\n\tASM_RS4_LAUNCH_BUF_SIZE=%i\n\tsizeRs4Ring=%i\n",
-		  sizeRs4Launch,ASM_RS4_LAUNCH_BUF_SIZE,sizeRs4Ring);
-			return IMGBUILD_ERR_CHECK_CODE;
-	}
-
-	// Populate ring header and put ring header and Rs4 ring into
-	// proper spots in pre-allocated bufRs4RingBlock buffer (HB buf2).
-	//
-	DeltaRingLayout *bufRs4RingBlock;
-	uint64_t entryOffsetRs4RingBlock;
-	uint32_t sizeRs4RingBlock, sizeRs4RingBlockMax;
-
-	bufRs4RingBlock = (DeltaRingLayout*)i_bufTmp; //HB buf2.
-  sizeRs4RingBlockMax = i_sizeBufTmp;
-  entryOffsetRs4RingBlock      = calc_ring_layout_entry_offset( 0, 0);
-  bufRs4RingBlock->entryOffset = myRev64(entryOffsetRs4RingBlock);
-  bufRs4RingBlock->backItemPtr = 0; // Will be updated later.
-	sizeRs4RingBlock     	       =	entryOffsetRs4RingBlock +  // Must be 8-byte aligned.
-  												        sizeRs4Launch +            // Must be 8-byte aligned.
-  												        sizeRs4Ring;               // Must be 8-byte aligned.
-	// Quick check to see if final ring block size will fit in HB buffer.
-	if (sizeRs4RingBlock>sizeRs4RingBlockMax)  {
-	  MY_ERR("RS4 ring block size (=%i) exceeds HB buf2 size (=%i).",
-	    sizeRs4RingBlock, sizeRs4RingBlockMax);
-	  return IMGBUILD_ERR_RING_TOO_LARGE;
-	}
-	// Populate RS4 ring block members.
-	bufRs4RingBlock->sizeOfThis  = myRev32(sizeRs4RingBlock);
-	bufRs4RingBlock->sizeOfMeta	 = 0;
-	bufRs4RingBlock->ddLevel     = myRev32(i_ddLevel);
-	bufRs4RingBlock->sysPhase    = i_sysPhase;
-	bufRs4RingBlock->override    = 0;
-	bufRs4RingBlock->reserved1   = 0;
-	bufRs4RingBlock->reserved2   = 0;
-  // Add the RS4 launch code and RS4 ring data...
-	bufLC = (uint32_t)entryOffsetRs4RingBlock;
-	// Copy over meta data which is zero, so nothing to do in this case!
-	// Copy over RS4 launch code which is already 8-byte aligned.
-	memcpy( (uint8_t*)bufRs4RingBlock+bufLC, (uint8_t*)asmBuffer, (size_t)sizeRs4Launch);
-	bufLC = bufLC + sizeRs4Launch;
-	// Copy over RS4 delta ring which is already BE formatted.
-	memcpy( (uint8_t*)bufRs4RingBlock+bufLC, (uint8_t*)i_bufRs4Ring, (size_t)sizeRs4Ring);
-
-  // Now, some post-sanity checks on alignments.
-	if ( entryOffsetRs4RingBlock%8 ||
-	     sizeRs4RingBlock%8)  {
-		MY_ERR("Member(s) of RS4 ring block are not 8-byte aligned; \n");
-    MY_ERR("  Entry offset            = %i; \n", (uint32_t)entryOffsetRs4RingBlock);
-		MY_ERR("  Size of ring block      = %i; \n", sizeRs4RingBlock);
-		return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT;
-	}
-
-  // Calculate any vector offset, i.e., in case of ex_ chiplet common ring name.
-	if (chipletId>=CID_EX_LOW && chipletId<=CID_EX_HIGH)
-    idxVector = chipletId - CID_EX_LOW;
-	else
-  	idxVector = 0;
-
-    // Write ring block to image.
-    sbe_xip_image_size( io_image, &sizeImage);
-    rc = write_ring_block_to_image(io_image,
-                                   i_ringName,
-                                   bufRs4RingBlock,
-                                   idxVector,
-                                   0,
-                                   0,
-                                   io_sizeImageOut,
-                                   i_xipSectionId,
-                                   (void*)i_bufRs4Ring, // Reuse buffer as temp work buf.
-                                   i_sizeBufTmp);
-    if (rc)  {
-      MY_ERR("write_ring_block_to_image() failed w/rc=%i \n",rc);
-      MY_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code. \n");
-      MY_ERR("Ring name: %s\n ", i_ringName);
-      MY_ERR("Size of image before wrbti() call: %i\n ", sizeImage);
-      MY_ERR("Size of ring block being added: %i\n ", sizeRs4RingBlock);
-      MY_ERR("Max size of image allowed: %i\n ", io_sizeImageOut);
-      if (rc==SBE_XIP_WOULD_OVERFLOW) {
-        return rc;
-      } else {
-        return IMGBUILD_ERR_RING_WRITE_TO_IMAGE;
-      }
-    }
-
-	MY_INF("\tSuccessful IPL image update; \n");
-
-	return rc;
-}
-
-
-// write_vpd_ring_to_slw_image()
-// - For VPD rings, there is no notion of a base and override ring. There can only be
-//   one ring. Thus, for core ID specific rings, their vector locations are updated only
-//   by 8-bytes, unlike 16-bytes for non-VPD rings which have base+override.
-// - Any ring, including ex_ rings, that have a chipletId==0xFF will get stored at its
-//   "top" or base position, i.e. as if it was coreId=0, or chipletId=0x10.
-// - For IPL images, #R/G must be accessible through .fixed_toc since .toc is removed.
-//   and same is true for proc_sbe_decompress_scan_chiplet_address (for RS4 launch.)
-// Notes:
-int write_vpd_ring_to_slw_image(void			*io_image,
-                                uint32_t  &io_sizeImageOut,
-                                CompressedScanData *i_bufRs4Ring, // HB buf1. BE format.
-                                uint32_t  i_ddLevel,
-                                uint8_t   i_usePollingProt,
-                                uint8_t   i_sysPhase,
-                                char 			*i_ringName,
-                                void      *i_bufTmp,              // HB buf2
-                                uint32_t  i_sizeBufTmp,
-                                uint8_t 	i_bWcSpace)
-{
-	uint32_t rc=0, bufLC;
-	uint8_t  chipletId, idxVector=0;
-	uint32_t sizeRingRaw=0, sizeRingRawChk;
-	uint32_t sizeImageIn,sizeImage;
-	uint32_t *wfInline=NULL;
-	uint32_t wfInlineLenInWords;
-	uint64_t scanMaxRotate=SCAN_ROTATE_DEFAULT;
-  uint64_t waitsScanDelay=0;
-	uint64_t twinHaltOpCodes;
-	uint32_t iFill;
-
-	MY_INF("i_ringName=%s; \n",	i_ringName);
-
-  if (i_bufTmp == NULL)  {
-    MY_ERR("Temporary ring buffer passed by caller points to NULL and is invalid.\n");
-    return IMGBUILD_ERR_MEMORY;
-  }
-
-  sbe_xip_image_size( io_image, &sizeImageIn);
-
-  chipletId = i_bufRs4Ring->iv_chipletId;
-
-  // Decompress RS4 VPD ring.
-  //
-  sizeRingRaw = myRev32(i_bufRs4Ring->iv_length);
-  if ((sizeRingRaw+7)/8 > i_sizeBufTmp)  {
-    MY_ERR("Decompressed byte size of VPD ring (=%i) exceeds size of buffer (=%i).",
-      (sizeRingRaw+7)/8, i_sizeBufTmp);
-    return IMGBUILD_ERR_RING_TOO_LARGE;
-  }
-  rc = _rs4_decompress((uint8_t*)i_bufTmp,
-                       i_sizeBufTmp,
-                       &sizeRingRawChk,  // Uncompressed raw ring size in bits.
-                       i_bufRs4Ring);
-  if (rc)  {
-    MY_ERR("_rs4_decompress() failed w/rc=%i; ",rc);
-    return IMGBUILD_ERR_RS4_DECOMPRESS;
-  }
-  if (sizeRingRaw != sizeRingRawChk)  {
-    MY_ERR("Ring size from RS4 container (=%i) differs from ring size returned by _rs4_decompress (=%i).",
-      sizeRingRaw, sizeRingRawChk);
-    return IMGBUILD_ERR_RS4_DECOMPRESS;
-  }
-
-	// Create wiggle-flip program.
-	//
-	rc = sbe_xip_get_scalar( io_image, SCAN_MAX_ROTATE_38XXX_NAME, &scanMaxRotate);
-	if (rc)  {
-	  MY_ERR("Strange error from sbe_xip_get_scalar(SCAN_MAX_ROTATE_38XXX_NAME) w/rc=%i; ",rc);
-	  MY_ERR("Already retrieved SCAN_MAX_ROTATE_38XXX_NAME in slw_build() w/o trouble; ");
-	  return IMGBUILD_ERR_XIP_MISC;
-	}
-	if (scanMaxRotate<0x20 || scanMaxRotate>SCAN_MAX_ROTATE)  {
-	  MY_INF("WARNING: Value of key word SCAN_MAX_ROTATE_38XXX_NAME=0x%llx is not permitted; ",scanMaxRotate);
-    scanMaxRotate = SCAN_ROTATE_DEFAULT;
-		MY_INF("scanMaxRotate set to 0x%llx; ", scanMaxRotate);
-		MY_INF("Continuing...; ");
-	}
-
-  // Temporary support for enforcing delay after scan WF scoms.
-  // Also remove all references and usages of waitsScanDelay in this file.
-  rc = sbe_xip_get_scalar( io_image, "waits_delay_for_scan", &waitsScanDelay);
-  if (rc)  {
-    MY_ERR("Error obtaining waits_delay_for_scan keyword.\n");
-	  return IMGBUILD_ERR_XIP_MISC;
-  }
-
-	wfInline = (uint32_t*)i_bufRs4Ring;  // Reuse this buffer (HB buf1) for wiggle-flip prg.
-	wfInlineLenInWords = i_sizeBufTmp/4; // Assuming same size of both HB buf1 and buf2.
-        
-        
-	rc = create_wiggle_flip_prg((uint32_t*)i_bufTmp,
-	                            sizeRingRaw,
-	                            myRev32(i_bufRs4Ring->iv_scanSelect),
-	                            (uint32_t)i_bufRs4Ring->iv_chipletId,
-	                            &wfInline,
-	                            &wfInlineLenInWords, // Is 8-byte aligned on return.
-                              i_bufRs4Ring->iv_flushOptimization,
-	                            (uint32_t)scanMaxRotate,
-                              (uint32_t)waitsScanDelay,
-                              i_usePollingProt );
-	if (rc)  {
-	  MY_ERR("create_wiggle_flip_prg() failed w/rc=%i; ",rc);
-	  return IMGBUILD_ERR_WF_CREATE;
-	}
-
-  // Populate ring header and put ring header and Wf ring into
-  // proper spots in pre-allocated bufWfRingBlock buffer (HB buf2).
-  //
-  DeltaRingLayout *bufWfRingBlock;
-  uint64_t entryOffsetWfRingBlock;
-  uint32_t sizeWfRingBlock, sizeWfRingBlockMax;
-
-  bufWfRingBlock = (DeltaRingLayout*)i_bufTmp; // Reuse this buffer (HB buf2) for WF ring block.
-  sizeWfRingBlockMax = i_sizeBufTmp;
-  entryOffsetWfRingBlock      = calc_ring_layout_entry_offset( 1, 0);
-  bufWfRingBlock->entryOffset = myRev64(entryOffsetWfRingBlock);
-  bufWfRingBlock->backItemPtr	= 0; // Will be updated below, as we don't know yet.
-
-	// Allocate either fitted or worst-case space for the ring.  For example, the
-	// rings, ex_repr_core/eco, need worst-case space allocation.
-	if (i_bWcSpace==0)  {
-		// Fitted space sizing.
-		sizeWfRingBlock =	entryOffsetWfRingBlock +  // Must be 8-byte aligned.
-  									  wfInlineLenInWords*4;     // Must be 8-byte aligned.
-	}
-	else  {
-		// Worst-case space sizing.
-		sizeWfRingBlock = ((sizeRingRaw-1)/32 + 1) * 4 * WF_WORST_CASE_SIZE_FAC +
-											WF_ENCAP_SIZE;
-		sizeWfRingBlock = (uint32_t)myByteAlign(8, sizeWfRingBlock);
-		// Fill void with "halt" instructions, 0x02000000 (LE). Note, void is whole multiple of 8x.
-    twinHaltOpCodes = myRev64((uint64_t)0x02000000<<32 | (uint64_t)0x02000000);
-		for (iFill=0; iFill<(sizeWfRingBlock-entryOffsetWfRingBlock); iFill=iFill+8)  {
-			*(uint64_t*)((uint64_t)bufWfRingBlock+entryOffsetWfRingBlock+iFill) = twinHaltOpCodes;
-		}
-	}
-	// Quick check to see if final ring block size will fit in HB buffer.
-	if (sizeWfRingBlock>sizeWfRingBlockMax)  {
-	  MY_ERR("WF ring block size (=%i) exceeds HB buf2 size (=%i).",
-	    sizeWfRingBlock, sizeWfRingBlockMax);
-	  return IMGBUILD_ERR_RING_TOO_LARGE;
-	}
-	bufWfRingBlock->sizeOfThis  = myRev32(sizeWfRingBlock);
-	bufWfRingBlock->sizeOfMeta	=	0;
-	bufLC = (uint32_t)entryOffsetWfRingBlock;
-	// Copy over meta data which is zero, so nothing to do in this case!
-	// Copy over WF ring prg which is already 8-byte aligned.
-	memcpy( (uint8_t*)bufWfRingBlock+bufLC, wfInline, (size_t)wfInlineLenInWords*4);
-
-  // Now, some post-sanity checks on alignments.
-	if ( entryOffsetWfRingBlock%8 ||
-	     sizeWfRingBlock%8)  {
-		MY_ERR("Member(s) of WF ring block are not 8-byte aligned:");
-    MY_ERR("  Entry offset            = %i", (uint32_t)entryOffsetWfRingBlock);
-		MY_ERR("  Size of ring block      = %i", sizeWfRingBlock);
-		return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT;
-	}
-
-  // Calculate any vector offset, i.e., in case of ex_ chiplet common ring name.
-	if (chipletId>=CID_EX_LOW && chipletId<=CID_EX_HIGH)
-    idxVector = chipletId - CID_EX_LOW;
-	else
-  	idxVector = 0;
-
-    // Write ring block to image.
-    sbe_xip_image_size( io_image, &sizeImage);
-    rc = write_ring_block_to_image(io_image,
-                                   i_ringName,
-                                   bufWfRingBlock,
-                                   idxVector,
-                                   0,
-                                   0,
-                                   io_sizeImageOut,
-                                   SBE_XIP_SECTION_RINGS,
-                                   (void*)i_bufRs4Ring, // Reuse buffer as temp work buf.
-                                   i_sizeBufTmp);
-    if (rc)  {
-      MY_ERR("write_ring_block_to_image() failed w/rc=%i; \n",rc);
-      MY_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code; \n");
-      MY_ERR("Ring name: %s\n ", i_ringName);
-      MY_ERR("Size of image before wrbti() call: %i\n ", sizeImage);
-      MY_ERR("Size of ring block being added: %i\n ", sizeWfRingBlock);
-      MY_ERR("Max size of image allowed: %i\n ", io_sizeImageOut);
-      if (rc==SBE_XIP_WOULD_OVERFLOW) {
-        return rc;
-      } else {
-        return IMGBUILD_ERR_RING_WRITE_TO_IMAGE;
-      }
-    }
-
-	MY_INF("Successful SLW image update; \n");
-
-	return rc;
-}
-
-
-// check_and_perform_ring_datacare()
-//
-// Checks if the Mvpd ring passed has a datacare ring in the .dcrings image section. If it does,
-// the Mvpd's ring bits corresponding to the care bits in the 1st half of the dc cring will be
-// overwritten by the data bits in the 2nd half of the dc ring.
-int check_and_perform_ring_datacare(	void     *i_imageRef,
-																			void  	 *io_buf1, // Mvpd ring in/out. BE format.
-																			uint8_t  i_ddLevel,
-																			uint8_t  i_sysPhase,
-																			char     *i_ringName,
-																			void     *io_buf2, // Work buffer.
-																			uint32_t i_sizeBuf2)
-{
-	int         rc=0, rcLoc=0;
-	uint32_t    bitLength, ringBitLen, ringBitLenDc;
-	uint32_t    scanSelect;
-	uint8_t     ringId, chipletId, flushOpt;
-	DeltaRingLayout  *rs4Datacare=NULL;
-	void        *nextRing=NULL;
-	SbeXipItem  xipTocItem;
-	uint8_t     bMatch=0;
-	uint32_t		sizeRs4Container;
-
-
-	bitLength  = myRev32(((CompressedScanData*)io_buf1)->iv_length);
-	scanSelect = myRev32(((CompressedScanData*)io_buf1)->iv_scanSelect);
-	ringId     = ((CompressedScanData*)io_buf1)->iv_ringId;
-	chipletId  = ((CompressedScanData*)io_buf1)->iv_chipletId;
-	flushOpt   = ((CompressedScanData*)io_buf1)->iv_flushOptimization;
-
-	MY_INF("In check_and_perform_ring_datacare()...\n");
-
-	MY_DBG("Mvpd ring characteristics:\n");
-	MY_DBG("Ring name:   %s\n",i_ringName);
-	MY_DBG("Ring ID:     0x%02x\n",ringId);
-	MY_DBG("Chiplet ID:  0x%02x\n",chipletId);
-	MY_DBG("Flush Opt:   %i\n",flushOpt);
-	MY_DBG("Scan select: 0x%08x\n",scanSelect);
-
-	rc = sbe_xip_find( i_imageRef, i_ringName, &xipTocItem);
-	if (rc)  {
-		MY_ERR("_find() failed w/rc=%i\n",rc);
-		return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-	}
-	MY_DBG("xipTocItem.iv_address=0x%016llx\n",xipTocItem.iv_address);
-
-	// Now look for datacare match in .dcrings section.
-	nextRing = NULL;
-	rs4Datacare = NULL;
-	bMatch = 0;
-	do  {
-		// Retrieve ptr to next ring in .dcrings
-		rcLoc = get_ring_layout_from_image2(i_imageRef,
-																				i_ddLevel,
-																				i_sysPhase,
-																				&rs4Datacare, // Will pt to gptr overlay ring.
-																				&nextRing,
-																				SBE_XIP_SECTION_DCRINGS);
-		if (rcLoc==IMGBUILD_RING_SEARCH_MATCH ||
-				rcLoc==IMGBUILD_RING_SEARCH_EXHAUST_MATCH ||
-				rcLoc==IMGBUILD_RING_SEARCH_NO_MATCH)  {
-			MY_DBG("get_ring_layout_from_image2() returned rc=%i \n",rc);
-			rc = 0;
-		}
-		else {
-			MY_ERR("get_ring_layout_from_image2() failed w/rc=%i\n",rcLoc);
-			return IMGBUILD_ERR_RING_SEARCH;
-		}
-		// Does the rings backPtr match the Vpd ring's vector addr?
-		if (rs4Datacare)  {
-			MY_DBG("rs4Datacare->backItemPtr=0x%016llx\n",myRev64(rs4Datacare->backItemPtr));
-			if (myRev64(rs4Datacare->backItemPtr)==xipTocItem.iv_address)  {
-				MY_DBG("Found a match in .dcrings. \n");
-				bMatch = 1;
-				// TBD
-			}
-		}
-		else
-			MY_DBG("rs4Datacare=NULL (no ring matched search criteria, or empty ring section.)\n");
-	}  while (nextRing!=NULL && !bMatch);
-
-	if (bMatch)  {
-
-		// Decompress Mvpd ring.
-		MY_DBG("Decompressing Mvpd ring.\n");
-	 	rc = _rs4_decompress( (uint8_t*)io_buf2,
-	   	                    i_sizeBuf2,
-													&ringBitLen,
-	    	                  (CompressedScanData*)io_buf1);
-	 	if (rc)  {
-	 	  MY_ERR("_rs4_decompress(mvpdring...) failed: rc=%i\n",rc);
-	 	  return IMGBUILD_ERR_RS4_DECOMPRESS;
-	 	}
-
-		// Decompress datacare overlay ring.
-		MY_DBG("Decompressing datacare ring.\n");
-  	rc = _rs4_decompress( (uint8_t*)io_buf1,
-    	                    i_sizeBuf2, // Assumption is that sizeBuf2=sizeBuf1
-													&ringBitLenDc,
-        	                (CompressedScanData*)( (uintptr_t)rs4Datacare +
-																								 myRev64(rs4Datacare->entryOffset) +
-																								 ASM_RS4_LAUNCH_BUF_SIZE) );
-  	if (rc)  {
-  	  MY_ERR("_rs4_decompress(datacare...) failed: rc=%i\n",rc);
-  	  return IMGBUILD_ERR_RS4_DECOMPRESS;
-  	}
-
-		MY_DBG("bitLength=%i\n",bitLength);
-		MY_DBG("ringBitLen=%i\n",ringBitLen);
-		MY_DBG("ringBitLenDc=%i\n",ringBitLenDc);
-		if ( bitLength!=ringBitLen || (2*ringBitLen)!=ringBitLenDc )  {
-			MY_ERR("Mvpd ring length (=%i) is not exactly half of datacare ring length (=%i)\n",
-							ringBitLen, ringBitLenDc);
-			return IMGBUILD_ERR_DATACARE_RING_MESS;
-		}
-
-                // Overlay io_buf2 bits according to care and data bits in io_buf1
-
-                // Split apart the raw datacare ring into data (1st part) and care (2nd part).
-                // Note that the order is already in BE for both Datacare and Mvpd rings.
-                // Further note that the care part is fractured into two words that need to
-                //   be combined into a single word. (That's the black magic part below).
-                // Once there are less than two words left to process, care part will be
-                // less than two words from the buffer end, so go byte-by-byte at that point
-                uint32_t dataVpd, dataDc, careDc, careDc1, careDc2;
-                int32_t remBits = ringBitLen;
-                uint32_t * pDataWord = (uint32_t*)io_buf1;
-                uint32_t * pCareWord = (uint32_t*)io_buf1 + (ringBitLen/32);
-                uint32_t * pDataVPD  = (uint32_t*)io_buf2;
-                uint32_t careLeftShift = ringBitLen%32;
-                uint32_t careRightShift = 32-careLeftShift;
-                while (remBits > 64) {
-                    dataDc  = *pDataWord++;                         // Data part
-                    // Split off the care part, do BE->LE, shift the two parts properly, and finally do
-                    //   LE->BE again. It's f*kin' black magic...
-                    careDc1 = myRev32(*pCareWord++);                // Care part a
-                    careDc2 = myRev32(*pCareWord);                  // Care part b
-                    careDc  = myRev32(careDc1<<careLeftShift | careDc2>>careRightShift);
-                    dataVpd = *(pDataVPD);
-                    MY_DBG("data: %08x  remBits=%i\n",dataDc,remBits);
-                    MY_DBG("care: %08x\n",careDc);
-                    MY_DBG("orig: %08x\n",dataVpd);
-                    dataVpd = ( dataVpd & ~careDc ) | dataDc;
-                    MY_DBG("new:  %08x\n",dataVpd);
-                    *pDataVPD++ = dataVpd;
-                    // Check for data+care construction. I.e., a 1-bit in data is illegal if corresponding
-                    //   care bit is a 0-bit.
-                    if ((dataDc & ~careDc)!=0)  {
-                        MY_ERR("DataCare ring construction error:\n");
-                        MY_ERR("A data bit (in word i=%i) is set but the care bit is not set.\n",
-                               (ringBitLen-remBits)/32);
-                        return IMGBUILD_ERR_DATACARE_RING_MESS;
-                    }
-                    remBits-=32;
-                }
-                //Less than 64 bits left, so must do byte-by-byte modifications
-                uint8_t dataVpdByte, dataDcByte, careDcByte, careDc1Byte, careDc2Byte;
-                uint8_t * pDataByte = (uint8_t*)pDataWord;
-                uint8_t * pCareByte = (uint8_t*)pCareWord;
-                uint8_t * pDataVPDByte = (uint8_t*)pDataVPD;
-                careLeftShift = ringBitLen%8;
-                careRightShift = 8-careLeftShift;
-                while(remBits > 0) {
-                    dataDcByte = *pDataByte++;                     // Data part
-                    // Split off the care part and shift the two parts propoerly
-                    careDc1Byte = *pCareByte++;                    // Care part a
-                    if(remBits > 8) {
-                        careDc2Byte = *pCareByte;                  // Care part b
-                        careDcByte = ((careDc1Byte<<careLeftShift) | (careDc2Byte>>careRightShift));
-                    } else {
-                        careDcByte = careDc1Byte << careLeftShift; // There is no part b
-                    }
-                    dataVpdByte = *(pDataVPDByte);
-                    MY_DBG("data: %02x  remBits=%i\n",dataDcByte,remBits);
-                    MY_DBG("care: %02x\n",careDcByte);
-                    MY_DBG("orig: %02x\n",dataVpdByte);
-                    dataVpdByte = ( dataVpdByte & ~careDcByte ) | dataDcByte;
-                    MY_DBG("new:  %02x\n",dataVpdByte);
-                    *pDataVPDByte++ = dataVpdByte;
-                    // Check for data+care construction. I.e., a 1-bit in data is illegal if corresponding
-                    //   care bit is a 0-bit.
-                    if ((dataDcByte & ~careDcByte)!=0)  {
-                        MY_ERR("DataCare ring construction error:\n");
-                        MY_ERR("A data bit (in byte i=%i) is set but the care bit is not set.\n",
-                               (ringBitLen-remBits)/8);
-                        return IMGBUILD_ERR_DATACARE_RING_MESS;
-                    }
-                    remBits-=8;
-                  }
-
-		// Compress overlayed Mvpd ring.
-		rc = _rs4_compress(	(CompressedScanData*)io_buf1,
-												i_sizeBuf2,
-												&sizeRs4Container,
-												(uint8_t*)io_buf2,
-												bitLength,
-												(uint64_t)scanSelect<<32,
-												ringId,
-												chipletId,
-												flushOpt);
- 		if (rc)  {
- 		  MY_ERR("\t_rs4_compress() failed: rc=%i ",rc);
- 		  return IMGBUILD_ERR_RS4_DECOMPRESS;
- 		}
-
-	}
-
-	MY_INF("Leaving check_and_perform_ring_datacare()...\n");
-
-	return rc;
-}
-
-
-// CMO-20130208: Not used in:
-// - p8_image_help.C
-// - p8_image_help_base.C
-// - cen_xip_customize.C
-// - p8_pore_table_gen_api.C
-// - p8_slw_repair.C
-// - ???
-// It is used in:
-// - p8_delta_scan_w
-// - p8_delta_scan_r
-// - ???
-void cleanup( void *buf1,
-              void *buf2,
-              void *buf3,
-              void *buf4,
-              void *buf5)
-{
-  if (buf1) free(buf1);
-  if (buf2) free(buf2);
-  if (buf3) free(buf3);
-  if (buf4) free(buf4);
-  if (buf5) free(buf5);
-}
-
-#endif // End of !(defined IMGBUILD_PPD_CEN_XIP_CUSTOMIZE)
-
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C
deleted file mode 100644
index eeb55dad0..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C
+++ /dev/null
@@ -1,532 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_image_help_base.C,v 1.15 2015/09/14 17:04:35 cswenson Exp $
-/*------------------------------------------------------------------------------*/
-/* *! TITLE : p8_image_help_base.c                                              */
-/* *! DESCRIPTION : Basic helper functions for building and extracting          */
-//                  information from SBE-XIP images.
-/* *! OWNER NAME :  Michael Olsen                  cmolsen@us.ibm.com           */
-//
-/* *! EXTENDED DESCRIPTION :                                                    */
-//
-/* *! USAGE :                                                                   */
-//
-/* *! ASSUMPTIONS :                                                             */
-//
-/* *! COMMENTS :                                                                */
-//
-/*------------------------------------------------------------------------------*/
-
-#include <p8_delta_scan_rw.h>
-
-#ifdef __FAPI
-#include <fapi.H>
-#endif
-extern "C"  {
-
-
-// get_ring_layout_from_image2()
-// - This is a simplified version of get_ring_layout_from_image():
-//   - It returns a pointer to the ring layout structure in the input image.
-//   - It DOES NOT populate members of the ring layout structure!
-//   - Don't attempt to populate members either or it will bomb since there is
-//     no real structure being allocated. It's merely a pointer of type
-//     DeltaRingLayout, so you can use the non-ptr members to point to values
-//     in the image.
-//
-int get_ring_layout_from_image2(  const void      *i_imageIn,
-                                  uint32_t        i_ddLevel,
-                                  uint8_t         i_sysPhase,
-                                  DeltaRingLayout **o_rs4RingLayout,
-                                  void            **nextRing,
-																	uint8_t 				i_xipSectionId)
-{
-  uint32_t  rc=0, rcLoc=0;
-  uint8_t   bRingFound=0, bRingEOS=0;
-  DeltaRingLayout *thisRingLayout=NULL, *nextRingLayout=NULL; //Pointers into memory mapped image. DO NOT CHANGE MEMBERS!
-  uint32_t  sizeRings;
-  SbeXipSection xipSection;
-  void      *hostSection;
-  
-  SBE_XIP_ERROR_STRINGS(g_errorStrings);
-
-  // Always first get the .rings stats from the TOC:
-  // - .rings host address offset and
-  // - .rings size
-  //
-  rc = sbe_xip_get_section( i_imageIn, i_xipSectionId, &xipSection);
-  if (rc)   {
-    MY_INF("ERROR : sbe_xip_get_section() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-    MY_INF("Probable cause:");
-    MY_INF("\tThe section (=SBE_XIP_SECTION_<xyz>=%i) was not found.",i_xipSectionId);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  if (xipSection.iv_offset==0)  {
-    MY_INF("INFO : No ring data exists for the section ID = SBE_XIP_SECTION_<xyz> =%i\n",i_xipSectionId);
-    return IMGBUILD_RING_SEARCH_NO_MATCH; // Implies exhaust search as well.
-  }
-  hostSection = (void*)((uintptr_t)i_imageIn + xipSection.iv_offset); 
-  sizeRings = xipSection.iv_size;
-
-  // On first call, get the base offset to the .rings section.
-  // On subsequent calls, we're into the search for ddLevel and sysPhase, so use nextRing instead.
-  //
-  if (*nextRing==NULL)
-    nextRingLayout = (DeltaRingLayout*)hostSection;
-  else
-    nextRingLayout = (DeltaRingLayout*)*nextRing;
-
-  MY_DBG("hostSection = 0x%016llx",(uint64_t)hostSection);
-  MY_DBG("sizeRings = %i", sizeRings);
-  MY_DBG("nextRingLayout = 0x%016llx",(uint64_t)nextRingLayout);
-  MY_DBG("i_ddLevel = 0x%02x",i_ddLevel);
-  MY_DBG("i_sysPhase = %i",i_sysPhase);
-  
-  // Populate the output RS4 ring BE layout structure as well as local structure in host LE format where needed.
-  // Note! Entire memory content is in BE format. So we do LE conversions where needed.
-  //
-  bRingFound = 0;
-  bRingEOS = 0;
-  
-  // SEARCH loop:  Parse ring blocks successively until we find a ring that matches:
-  //     ddLevel == i_ddLevel
-  //     sysPhase == i_sysPhase
-  //
-  while (!bRingFound && !bRingEOS)  {
-    thisRingLayout = nextRingLayout;
-    MY_DBG("Next backItemPtr = 0x%016llx",myRev64(thisRingLayout->backItemPtr));
-    MY_DBG("Next ddLevel = 0x%02x",myRev32(thisRingLayout->ddLevel));
-    MY_DBG("Next sysPhase = %i",thisRingLayout->sysPhase);
-    MY_DBG("Next override = %i",thisRingLayout->override);
-    MY_DBG("Next reserved1 = %i",thisRingLayout->reserved1);
-    MY_DBG("Next reserved2 = %i",thisRingLayout->reserved2);
-    
-    if (myRev32(thisRingLayout->ddLevel)==i_ddLevel)  { // Is there a non-specific DD level, like for sys phase?
-      if ((thisRingLayout->sysPhase==0 && i_sysPhase==0) ||
-          (thisRingLayout->sysPhase==1 && i_sysPhase==1) ||
-          (thisRingLayout->sysPhase==2 && (i_sysPhase==0 || i_sysPhase==1)))  {
-        bRingFound = 1;
-        MY_DBG("Ring match found! \n");
-      }
-    }
-    nextRingLayout = (DeltaRingLayout*)((uintptr_t)thisRingLayout + myRev32(thisRingLayout->sizeOfThis));
-    *nextRing = (void*)nextRingLayout;
-    if (nextRingLayout>=(DeltaRingLayout*)((uintptr_t)hostSection+sizeRings))  {
-      bRingEOS = 1;
-      *nextRing = NULL;
-      MY_DBG("Ring search exhausted! \n");
-    }
-    
-  }  // End of SEARCH.
-
-  if (bRingFound)  {
-    if (bRingEOS)
-      rcLoc = IMGBUILD_RING_SEARCH_EXHAUST_MATCH;
-    else
-      rcLoc = IMGBUILD_RING_SEARCH_MATCH;
-  }    
-  else  {
-    *nextRing = NULL;
-    if (bRingEOS)
-      return IMGBUILD_RING_SEARCH_NO_MATCH; // Implies exhaust search as well.
-    else  {
-      MY_INF("Messed up ring search. Check code and .rings content. Returning nothing.");
-      return IMGBUILD_RING_SEARCH_MESS;
-    }
-  }
-
-  *o_rs4RingLayout = thisRingLayout;
-
-  // Check that the ring layout structure in the memory is 8-byte aligned:
-  //   - The entryOffset address must be on an 8-byte boundary because the start of the 
-  //     .rings section must be 8-byte aligned AND because the rs4Delta member is the 
-  //     last member and which must itself be 8-byte aligned.  These two things together 
-  //     means that both the beginning and end of the delta ring layout must be 8-byte
-  //     aligned, and thus the whole block,i.e. sizeOfThis, must be 8-byte aligned.
-  // Also check that the RS4 delta ring is 8-byte aligned.
-  // Also check that the RS4 launcher is 8-byte aligned.
-  //
-  if (((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)%8 || 
-      myRev32(thisRingLayout->sizeOfThis)%8 || 
-      myRev64(thisRingLayout->entryOffset)%8 )  {
-    MY_INF("Ring block or ring code section is not 8-byte aligned:");
-    MY_INF("  thisRingLayout-imageIn = 0x%08x",(uint32_t)((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn));
-    MY_INF("  thisRingLayout->sizeOfThis = 0x%08x",myRev32(thisRingLayout->sizeOfThis));
-    MY_INF("  thisRingLayout->entryOffset = 0x%016llx",(uint64_t)myRev64(thisRingLayout->entryOffset));
-    return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT;
-  }
-
-  if (*nextRing > (void*)((uintptr_t)hostSection + sizeRings))  {
-    MY_INF("Book keeping got messed up during .rings search. .rings section does not appear aligned.");
-    MY_INF("hostSection+sizeRings = 0x%016llx",(uint64_t)hostSection+sizeRings);
-    MY_INF("nextRing = 0x%016llx",*(uint64_t*)nextRing);
-    MY_INF("Continuing...");
-  }
-
-  return rcLoc;
-}
-
-
-
-// Function:  write_ring_block_to_image()
-// Comments:
-// - Appends an RS4 or WF ring block to the .rings section. It doesn't care
-//   what type of ring it is. The only data that might be updated in the ring
-//   block is the backItemPtr which is shared between both types of rings.
-// - If ringName=NULL:  Assumes fwd ptr already exists in .ipl_data or .data 
-//                      section. Back pointer in ring block is unchanged.
-// - If ringName!=NULL: Adds fwd ptr to .ipl_data or .data section. Updates back
-//                      pointer in input ring block.
-// - idxVector:   Contains the index number of a vector array. This is pretty much
-//                limited for ex_ chiplet IDs. It is ignored if ringName==NULL.
-// - override:    Indicates if the ring is an override ring. It is ignored if 
-//                ringName==NULL.
-// - overridable: Indicates if a ring can be overridden. It is ignored if
-//                ringName==NULL.
-// - Assumes ring block is in BE format.
-int write_ring_block_to_image(  void             *io_image,
-                                const char       *i_ringName,
-                                DeltaRingLayout  *i_ringBlock,
-                                const uint8_t    i_idxVector,
-                                const uint8_t    i_override,
-                                const uint8_t    i_overridable,
-                                const uint32_t   i_sizeImageMax,
-                                const uint8_t    i_xipSectionId,
-                                void             *i_bufTmp,
-                                const uint32_t   i_sizeBufTmp)
-{
-  uint32_t   rc=0;
-  SbeXipItem tocItem;
-  uint32_t   offsetRingBlock=1;  // Initialize to anything but zero.
-  uint32_t   sizeImage=0;
-  uint64_t   ringPoreAddress=0,backPtr=0,fwdPtrCheck;
-
-  SBE_XIP_ERROR_STRINGS(g_errorStrings);
-
-  if (myRev64(i_ringBlock->entryOffset)%8)  {
-    MY_ERR("Ring code section is not 8-byte aligned.");
-    return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT;
-  }
-
-  if (i_ringName)  {
-    // Obtain the back pointer to the .data item, i.e. the location of the ptr associated with the 
-    //   ring/var name in the TOC.
-    //
-    rc = sbe_xip_find( io_image, i_ringName, &tocItem);
-    if (rc)  {
-      MY_ERR("sbe_xip_find() failed w/rc=%i", rc);
-      MY_ERR("Probable cause: Ring name (=%s) not found in image.", i_ringName);
-      return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-    } 
-    i_ringBlock->backItemPtr = myRev64( tocItem.iv_address +
-                                        i_idxVector*8*(1+i_overridable) +
-                                        8*i_override*i_overridable );
-  }
-
-  //
-  // Insert ring block to .rings or .dcrings section.
-  // ------
-  
-  // Temporarily copy .dcrings section if inserting into .rings section.
-  SbeXipSection xipSectionDcrings = SbeXipSection();
-  void          *hostSectionDcrings=NULL;
-  
-  if (i_xipSectionId==SBE_XIP_SECTION_RINGS) {
-    rc = sbe_xip_get_section(io_image, SBE_XIP_SECTION_DCRINGS, &xipSectionDcrings);
-    if (rc)  {
-      MY_ERR("_get_section(.dcrings...) failed with rc=%i  ",rc);
-      return IMGBUILD_ERR_GET_SECTION;
-    }
-    if (!(xipSectionDcrings.iv_size==0 && xipSectionDcrings.iv_offset==0))  {
-      hostSectionDcrings = (void*)((uint64_t)io_image + (uint64_t)xipSectionDcrings.iv_offset);
-      if (xipSectionDcrings.iv_size<=i_sizeBufTmp)  {
-        memcpy(i_bufTmp, hostSectionDcrings, (size_t)xipSectionDcrings.iv_size);
-      }
-      else  {
-        MY_ERR("Size of .dcrings section (=%i) exceeds buffer size (=%i).  ",
-                xipSectionDcrings.iv_size, i_sizeBufTmp);
-        return IMGBUILD_BUFFER_TOO_SMALL;
-      }
-      rc = sbe_xip_delete_section(io_image, SBE_XIP_SECTION_DCRINGS);
-      if (rc)  {
-        MY_ERR("_delete_section(.dcrings...) failed w/rc=%i  ",rc);
-        return IMGBUILD_ERR_SECTION_DELETE;
-      }
-    }
-  }
-  
-  rc = sbe_xip_append(io_image, 
-                      i_xipSectionId, 
-                      (void*)i_ringBlock,
-                      myRev32(i_ringBlock->sizeOfThis),
-                      //don't allow ring append to use up space the .dcrings needs
-                      i_sizeImageMax - xipSectionDcrings.iv_size,
-                      &offsetRingBlock);
-  if (rc)   {
-    MY_ERR("sbe_xip_append() failed: %s  ", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-    sbe_xip_image_size(io_image,&sizeImage);
-    MY_ERR("Input image size: %i  ", sizeImage);
-    MY_ERR("Max image size allowed: %i  ", i_sizeImageMax);
-    if (rc==SBE_XIP_WOULD_OVERFLOW) {
-      return rc;
-    } else {
-      return IMGBUILD_ERR_APPEND;
-    }
-  }
-  
-  // Re-append .dcrings section if inserting into .rings section.
-  if (i_xipSectionId==SBE_XIP_SECTION_RINGS) {
-    if (!(xipSectionDcrings.iv_size==0 && xipSectionDcrings.iv_offset==0))  {
-      rc = sbe_xip_append(io_image,
-                          SBE_XIP_SECTION_DCRINGS,
-                          i_bufTmp,
-                          xipSectionDcrings.iv_size,
-                          i_sizeImageMax,
-                          NULL);
-      if (rc)  {
-        MY_ERR("_append(.dcrings...) failed: w/rc=%i  ", rc);
-        if (rc==SBE_XIP_WOULD_OVERFLOW) {
-          return rc;
-        } else {
-          return IMGBUILD_ERR_APPEND;
-        }
-      }
-    }
-  }
-
-  // ...get new image size and test if successful update.
-  rc = sbe_xip_image_size( io_image, &sizeImage);
-  MY_DBG("Updated image size (after append): %i",sizeImage);
-  if (rc)   {
-    MY_ERR("sbe_xip_image_size() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  rc = sbe_xip_validate( io_image, sizeImage);
-  if (rc)   {
-    MY_ERR("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  
-  // Update forward pointer associated with the ring/var name + any override offset.
-	// (Note, we ONLY do this for .rings as we can't have forward ptrs to [non-scannable]
-	//    rings in the .dcrings section.)
-  //
-  // Convert the ring offset to an PORE address
-	if (i_xipSectionId==SBE_XIP_SECTION_RINGS)  {
-	  rc = sbe_xip_section2pore(io_image, i_xipSectionId, offsetRingBlock, &ringPoreAddress);
-	  MY_DBG("fwdPtr=0x%016llx", ringPoreAddress);
-	  if (rc)   {
-	    MY_ERR("sbe_xip_section2pore() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-	    return IMGBUILD_ERR_XIP_MISC;
-	  }
-	}
-	else  {
-    MY_DBG("Inserting Gptr overlay ring into .dcrings section and ensuring forward ptr is cleared. ");
-		// We can not have forward ptr to [non-scannanble] rings in the .dcrings section.
-		ringPoreAddress = 0;
-  }
-  
-  // Now, update the forward pointer, making sure that it's zero for .dcrings section.
-  //
-  // First, retrieve the ring block's backPtr which tells us where the fwd ptr
-  // is located.
-  //
-  // Note that the fwd ptr's addr is the old variable/ring name's pointer location
-  // from the ref image. DO NOT add an 8-byte offset if override ring. The 
-  // backItemPtr in the input ring block already has this from the ref image, 
-  // and it shouldn't have changed after having been ported over to an 
-  // IPL/Seeprom image.
-  backPtr = myRev64(i_ringBlock->backItemPtr);
-  MY_DBG("backPtr = 0x%016llx ",  backPtr);
-  // Second, put the ring's Pore addr into the location pointed to by the back ptr.
-  rc = sbe_xip_write_uint64(  io_image, 
-                              backPtr,
-                              ringPoreAddress);
-  // Third, let's read it back to make sure we're OK a little further down.
-  rc = rc+sbe_xip_read_uint64(io_image,
-                              backPtr,
-                              &fwdPtrCheck);
-  if (rc)  {
-    MY_ERR("sbe_xip_[write,read]_uint64() failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  
-  // Check for pointer mess.
-  if (fwdPtrCheck!=ringPoreAddress || backPtr!=myRev64(i_ringBlock->backItemPtr))  {
-    MY_ERR("Forward or backward pointer mess. Check code."); 
-    MY_ERR("fwdPtr       =0x%016llx",ringPoreAddress);
-    MY_ERR("fwdPtrCheck  =0x%016llx",fwdPtrCheck);
-    MY_ERR("layout bckPtr=0x%016llx",myRev64(i_ringBlock->backItemPtr));
-    MY_ERR("backPtr      =0x%016llx",backPtr);
-    return IMGBUILD_ERR_FWD_BACK_PTR_MESS;
-  }
-  MY_DBG("fwdPtr = 0x%016llx ",fwdPtrCheck);
-  // ...test if successful update.
-  rc = sbe_xip_validate( io_image, sizeImage);
-  if (rc)   {
-    MY_ERR("sbe_xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(g_errorStrings, rc));
-    MY_ERR("Probable cause: sbe_xip_write_uint64() updated at the wrong address (=0x%016llx)",
-      myRev64(i_ringBlock->backItemPtr));
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  
-  return IMGBUILD_SUCCESS;
-}
-
-
-// calc_ring_layout_entry_offset()
-// - Calculates the entry offset from the beginning of the ring block to the
-//   first line of inline Pore code.
-//
-uint64_t calc_ring_layout_entry_offset( 
-                              uint8_t  i_typeRingLayout, // 0: RS4  1: WF
-                              uint32_t i_sizeMetaData )  // Meta data size.
-{
-  DeltaRingLayout ringBlock;
-  if (i_typeRingLayout==0)  {
-    // RS4 ring block.
-    ringBlock.entryOffset = (uint64_t)(
-                            sizeof(ringBlock.entryOffset) +
-                            sizeof(ringBlock.backItemPtr) +
-                            sizeof(ringBlock.sizeOfThis) +
-                            sizeof(ringBlock.sizeOfMeta) +
-                            sizeof(ringBlock.ddLevel) +
-                            sizeof(ringBlock.sysPhase) +
-                            sizeof(ringBlock.override) +
-                            sizeof(ringBlock.reserved1) +
-                            sizeof(ringBlock.reserved2) +
-                            myByteAlign(8, i_sizeMetaData) ); // 8-byte align RS4 launch.
-  }
-  else  
-  if (i_typeRingLayout==1)  {
-    // Wiggle-flip ring block.
-    ringBlock.entryOffset = (uint64_t)(
-                            sizeof(ringBlock.entryOffset) +
-                            sizeof(ringBlock.backItemPtr) +
-                            sizeof(ringBlock.sizeOfThis) +
-                            sizeof(ringBlock.sizeOfMeta) +
-                            myByteAlign(8, i_sizeMetaData) ); // 8-byte align WF prg.
-  }
-  else
-    return MAX_UINT64_T;
-    
-  return ringBlock.entryOffset;
-}
-
-
-
-// Function:  over_write_ring_data_in_image()
-// Comments:
-// - Overwrites RS4 or WF ring block data in the .rings section. It doesn't care
-//   what type of ring it is. The only data that might be updated in the ring
-//   block is the sizeOfThis which is shared between both types of rings.
-// - If ringName=NULL:  ? 
-// - If ringName!=NULL: ?
-// - ringData:    The actual RS4 ring data, incl container, or the WF program.
-// - sizeRingData: Byte size of ring data. This includes RS4 launch in case of RS4.
-// - idxVector:   Contains the index number of a vector array. This is pretty much
-//                limited for ex_ chiplet IDs. It is ignored if ringName==NULL.
-// - override:    Indicates if the ring is an override ring. It is ignored if 
-//                ringName==NULL.
-// - overridable: Indicates if a ring can be overridden. It is ignored if
-//                ringName==NULL.
-int over_write_ring_data_in_image(  void            *io_image,
-                                    const char      *i_ringName,
-                                    const void      *i_ringData,    // WF or RS4
-                                    const uint32_t  i_sizeRingData, // Byte size
-                                    const uint8_t   i_idxVector,
-                                    const uint8_t   i_override,
-                                    const uint8_t   i_overridable )
-{
-  uint32_t   rc=0;
-  SbeXipItem tocItem;
-  uint32_t   sizeImage=0;
-  void       *hostVectorBase, *hostVectorThis;
-  DeltaRingLayout *hostRingBlock;
-  void       *hostRingData;
-
-  // Test if valid image to start with since we're going to mess with it w/o using 
-  //   sbe_xip functions.
-  sbe_xip_image_size( io_image, &sizeImage);
-  rc = sbe_xip_validate( io_image, sizeImage);
-  if (rc)  {
-    MY_ERR("sbe_xip_validate() failed w/rc=%i\n", rc);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-
-  // Calculate the host location of the ring.
-  //
-  rc = sbe_xip_find( io_image, i_ringName, &tocItem);
-  if (rc)  {
-    MY_ERR("sbe_xip_find() failed w/rc=%i", rc);
-    MY_ERR("Probable cause: Ring name (=%s) not found in image.", i_ringName);
-    return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-  }
-  sbe_xip_pore2host( io_image, tocItem.iv_address, &hostVectorBase);
-  hostVectorThis = (void*) ( (uint64_t)hostVectorBase + 
-                             i_idxVector*8*(1+i_overridable) +
-                             8*i_override*i_overridable );
-  uint64_t tmp1 = (*(uintptr_t*)hostVectorThis);
-  sbe_xip_pore2host( io_image, tmp1, (void**)&hostRingBlock);
-  hostRingData = (void*)( (uint64_t)hostRingBlock + hostRingBlock->entryOffset );
-
-  // Over write ringData onto existing ring data content in image.
-  //
-  memcpy(hostRingData, i_ringData, i_sizeRingData);
-  
-  // Update size of new ring block.
-  //
-  hostRingBlock->sizeOfThis = hostRingBlock->entryOffset + i_sizeRingData;
-  
-  // Test if successful update.
-  rc = sbe_xip_validate( io_image, sizeImage);
-  if (rc)   {
-    MY_ERR("sbe_xip_validate() failed w/rc=%i\n", rc);
-    MY_ERR("We really screwed up the image here. This is a coding error. Here's some data:\n");
-    MY_ERR("io_image       = 0x%016llx\n",(uint64_t)io_image);
-    MY_ERR("hostVectorBase = 0x%016llx\n",(uint64_t)hostVectorBase);
-    MY_ERR("hostVectorThis = 0x%016llx\n",(uint64_t)hostVectorThis);
-    MY_ERR("hostRingBlock  = 0x%016llx\n",(uint64_t)hostRingBlock);
-    MY_ERR("hostRingData   = 0x%016llx\n",(uint64_t)hostRingData);
-    return IMGBUILD_ERR_XIP_MISC;
-  }
-  
-  MY_DBG("Dumping ring layout of over-writen ring:");
-  MY_DBG("  entryOffset     = 0x%016llx",myRev64(hostRingBlock->entryOffset));
-  MY_DBG("  backItemPtr     = 0x%016llx",myRev64(hostRingBlock->backItemPtr));
-  MY_DBG("  sizeOfThis      = %i",myRev32(hostRingBlock->sizeOfThis));
-  MY_DBG("  sizeOfMeta      = %i",myRev32(hostRingBlock->sizeOfMeta));
-  MY_DBG("  ddLevel         = %i",myRev32(hostRingBlock->ddLevel));
-  MY_DBG("  sysPhase        = %i",hostRingBlock->sysPhase);
-  MY_DBG("  override        = %i",hostRingBlock->override);
-  MY_DBG("  reserved1+2     = %i",hostRingBlock->reserved1|hostRingBlock->reserved2);
-
-	
-  return IMGBUILD_SUCCESS;
-}
-
-
-
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H
deleted file mode 100644
index 4662641ec..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H
+++ /dev/null
@@ -1,125 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help_base.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_image_help_base.H,v 1.18 2013/06/10 22:08:20 jeshua Exp $
-//------------------------------------------------------------------------------
-//  Title:  p8_image_help_base.H
-//  Description:  Contains the most basic structures and defines needed for 
-//                image building and interpretation.
-//------------------------------------------------------------------------------
-#ifndef _P8_IMAGE_HELP_BASE_H_
-#define _P8_IMAGE_HELP_BASE_H_
-
-#include <sbe_xip_image.h>
-
-//
-// Various image/ring buffer sizes. Must be used by all users (VBU, FSP, HB, HBI, Cronus)
-//
-const uint32_t  MAX_REF_IMAGE_SIZE      =   5000000; // Max reference image size.
-const uint32_t  FIXED_SEEPROM_WORK_SPACE=  128*1024; // Max work space for Seeprom img.
-const uint32_t  MAX_SEEPROM_IMAGE_SIZE  =   56*1024; // Max Seeprom image size.
-// Fixed SLW image size (Ensure 128-byte alignment.)
-const uint32_t  FIXED_SLW_IMAGE_SIZE    = 1024*1024; // Fixed SLW image size for _fixed.
-const uint32_t  FIXED_RING_BUF_SIZE     =     60000; // Fixed ring buf size for _fixed.
-
-const uint8_t   MAX_VPD_TYPES           =   2;   // #G and #R, so far.
-#define         CHIPLET_ID_MIN            0x00 
-#define         CHIPLET_ID_MAX            0x1F 
-#define         CHIPLET_ID_EX_MIN         0x10 
-#define         CHIPLET_ID_EX_MAX         0x1F 
-const uint8_t   MAX_CHIPLETS            = CHIPLET_ID_MAX-CHIPLET_ID_MIN+1;
-const uint32_t  ASM_RS4_LAUNCH_BUF_SIZE =  24; // Byte size of RS4 launch buffer. 
-const uint32_t  WF_ENCAP_SIZE           = 400; // Byte size of WF encapsulation.
-                                               // (Actually, only 304B but may change.)
-const uint32_t  WF_WORST_CASE_SIZE_FAC  =   4; // WC WF size = 3x ring length.
-                                               // (Assumes 12B per write.)
-                                               // (4x w/waits instructions.)
-const uint32_t  LISTING_STRING_SIZE     = 256;
-const uint64_t  MAX_UINT64_T            = (uint64_t)0xFFFFFFFF<<32 | (uint64_t)0xFFFFFFFF;
-
-const uint8_t RING_SECTION_ID[] = {
-  SBE_XIP_SECTION_RINGS,
-  SBE_XIP_SECTION_DCRINGS,
-};
-const uint8_t RING_SECTION_ID_SIZE = sizeof(RING_SECTION_ID) / sizeof(RING_SECTION_ID[0]);
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Base (shared) ring layout for both RS4 and Wiggle-flip layouts.
-typedef struct {
-  uint64_t entryOffset;
-  uint64_t backItemPtr;
-  uint32_t sizeOfThis;
-  uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
-} BaseRingLayout;
-
-// RS4 specific layout.
-typedef struct {
-  uint64_t entryOffset;
-  uint64_t backItemPtr;
-  uint32_t sizeOfThis;
-  uint32_t sizeOfMeta; // Exact size of meta data. Arbitrary size. Not null terminated.
-  uint32_t ddLevel;
-  uint8_t  sysPhase;
-  uint8_t  override;
-  uint8_t  reserved1;
-  uint8_t  reserved2;
-} Rs4RingLayout;
-
-// PairingInfo is used for pairing, or matching, a back pointer address of a
-// ring block with its corresponding TOC name.
-typedef struct {
-    uint64_t address;     // (in) Holds PORE backPtr addr of the ring
-    uint8_t  vectorpos;   // (in) Vector position of fwdPtr [0;31]
-                          //      max=0  for most VPD rings 
-                          //      max=1  for all non-VPD rings
-                          //      max=1  for perv_ VPD rings
-                          //      max=15 for most VPD ex_ rings
-                          //      max=31 for 16 ex_ chiplets with override
-    char     *name;       // (out) TOC name
-    uint8_t  isvpd;       // (out) 0: Non-VPD ring  1: VPD ring
-    uint8_t  overridable; // (out) 0: No (most VPD rings)  1: Yes (all non-VPD rings)
-    uint8_t  override;    // (out) 0: base  1: override
-} PairingInfo;
-
-
-///
-/// ****************************************************************************
-/// Function declares.
-/// ****************************************************************************
-///
-int over_write_ring_data_in_image(  void            *io_image,
-                                    const char      *i_ringName,
-                                    const void      *i_ringData,    // WF or RS4
-                                    const uint32_t  i_sizeRingData, // Byte size
-                                    const uint8_t   i_idxVector,
-                                    const uint8_t   i_override,
-                                    const uint8_t   i_overridable );
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //_P8_IMAGE_HELP_BASE_H_
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api.h
deleted file mode 100644
index 86e2a0e76..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api.h
+++ /dev/null
@@ -1,284 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/* $Id: p8_pore_api.h,v 1.2 2012/04/11 16:58:29 cmolsen Exp $ */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/p8_pore_api.h,v $ */
-/*------------------------------------------------------------------------------*/
-/* *! (C) Copyright International Business Machines Corp. 2010                  */
-/* *! All Rights Reserved -- Property of IBM                                    */
-/* *! ***  ***                                                  */
-/*------------------------------------------------------------------------------*/
-/* *! TITLE p8_pore_api                                                        */
-/* *! DESCRIPTION : PORE APIs                                                   */
-/* *! OWNER NAME :  Nicole Schwartz  Email: nschwart@us.ibm.com                 */
-/* *! BACKUP NAME :                                                             */
-/* *! ADDITIONAL COMMENTS :                                                     */
-
-/*------------------------------------------------------------------------------*/
-/* Don't forget to create CVS comments when you check in your changes!          */
-/*------------------------------------------------------------------------------*/
-
-#ifndef _P8P_PORE_API_H
-#define _P8P_PORE_API_H
-
-/**
- * Contains all external APIs used by firmware to generate/modify the P7+
- *  PORE image.
- */
-
-
-#include "p8_pore_api_custom.h"
-/*#include <p7p_pore_image.h>*/
-#include "p8_pore_api_const.h"
-
-typedef struct {
-  char ringName[50];
-  uint32_t ringAddress;
-  uint32_t clockControlData;
-  uint32_t length;
-} p8_pore_ringInfoStruct;
-
-
-/**
- * Generate a set of PORE instructions that will initialize a scan ring.
- *
- * @param i_ringAddr    host    Address of scan ring
- * @param i_ringBitLen  host    Number of bits in the scan ring
- * @param i_ring        host    Pointer to initialized ring data, left-aligned binary
- * @param i_flush       host    Pointer to ring data for flush state, left-aligned binary
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE image in 32-bit words
- * @param o_streamLenInWords  host    Actual size of PORE image in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into, this is
- *    the location to write the ring data into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_gen_scan( uint32_t i_ringAddr,
-			    uint32_t i_ringBitLen,
-			    uint32_t* i_ring,
-			    uint32_t* i_flush,
-			    uint32_t i_maxStreamLenInWords,
-			    uint32_t* o_streamLenInWords,
-			    uint32_t* o_streamOutput );
-
-/**
- * Generate or update a set of PORE instructions that will initialize a scom register.
- *
- * @param i_scomAddr    host    Address of scom register
- * @param i_scomData    host    Two 32-bit words of scom register data
- * @param i_operation   host    Should data be appended or existing data updated
- *     P8_PORE_SCOM_APPEND  : add scom instructions to the end of the existing image
- *     P8_PORE_SCOM_OR      : overlay scom data onto existing instruction by bitwise OR
- *     P8_PORE_SCOM_AND     : overlay scom data onto existing instruction by bitwise AND
- *     P8_PORE_SCOM_REPLACE : replace existing instructions with new data
- *     P8_PORE_SCOM_NOOP    : replace existing instructions with NOOP, i_scomData is junk
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE image in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_BAD_ARG_RC       : some input argument is nonsensical
- *     P8_PORE_ADDR_NOT_FOUND   : could not find existing scom for overlay (AND/OR) operation
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_gen_scom( uint32_t i_scomAddr,
-			    uint32_t i_scomData[2],
-			    uint32_t i_operation,
-			    uint32_t i_maxStreamLenInWords,
-			    uint32_t* o_streamOutput );
-
-/**
- * Generate or update a set of PORE instructions that will initialize an
- *  architected register in the processor, ie. SPR or GPR.  It is assumed that
- *  all updates will replace any existing data for that register.  If the data
- *  does not already exist then it will be appended.
- *
- * @param i_regName     host    Constant that determines which SPR to write (see p8_pore_const.h)
- * @param i_regData     host    Two 32-bit words of register data
- * @param i_coreIndex   host    Core to operate on
- * @param i_threadIndex   host    Thread to operate on, used for HSPRG0 and LPCR
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE image in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_gen_cpureg( uint32_t i_regName,
-			      uint32_t i_regData[2],
-			      uint32_t i_coreIndex,
-			      uint32_t i_threadIndex,
-			      uint32_t i_maxStreamLenInWords,
-			      uint32_t* o_streamOutput );
-
-/**
- * Generate a set of PORE instructions that will perform a branch operation
- *  to a relative address offset
- *
- * @param i_offset      host    Relative offset to branch to
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE instruction(s) in 32-bit words
- * @param i_branchType  host    Set to 0 for relative branch (BRA), set to 1 for branch to subroutine (BSR)
- * @param o_streamLenInWords  host    Actual size of PORE instruction(s) in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_gen_relbranch( uint32_t i_offset,
-				 uint32_t i_maxStreamLenInWords,
-				 uint32_t i_branchType,
-				 uint32_t* o_streamLenInWords,
-				 uint32_t* o_streamOutput );
-
-/**
- * Generate a set of PORE instructions that will perform a branch operation
- *  to an absolute address.
- *
- * @param i_address  host    Absolute address to branch to
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE instruction(s) in 32-bit words
- * @param o_streamLenInWords  host    Actual size of PORE instruction(s) in 32-bit words
- * @param o_streamOutput  host    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_gen_absbranch( uint32_t i_address,
-				 uint32_t i_maxStreamLenInWords,
-				 uint32_t* o_streamLenInWords,
-				 uint32_t* o_streamOutput );
-
-/**
- * Generate a set of PORE instructions that are invalid and will cause an
- *  error.  It is used to populate a region of memory that the PORE shouldn't
- *  execute.
- *
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE instruction(s) in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_fill_invalid( uint32_t i_maxStreamLenInWords,
-				uint32_t* o_streamOutput );
-
-/**
- * Generate a set of PORE instructions that are return statements.  It is used
- *  to populate a region of memory that the PORE should return from.
- *
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE instruction(s) in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_fill_return( uint32_t i_maxStreamLenInWords,
-			       uint32_t* o_streamOutput );
-
-/**
- * Generate a WAIT PORE instruction.
- *
- * @param i_wait  host    Number of pcb_nclk cycles to wait
- * @param i_maxStreamLenInWords  host    Max space available for resulting PORE instruction(s) in 32-bit words
- * @param o_streamLenInWords  host    Actual size of PORE instruction(s) in 32-bit words
- * @param o_streamOutput  BigEndian    Pointer to allocated local memory to write PORE image into
- *
- * @return uint32_t  Error return codes
- *     P8_PORE_SUCCESS_RC       : No errors
- *     P8_PORE_IMAGE_TOO_BIG_RC : size of PORE image exceeded allowed space
- *     P8_PORE_XXX_RC           : other errors...
- */
-uint32_t p8_pore_gen_wait( uint32_t i_wait,
-			    uint32_t i_maxStreamLenInWords,
-			    uint32_t* o_streamLenInWords,
-			    uint32_t* o_streamOutput );
-
-
-#endif /* _P8_PORE_H */
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-
-$Log: p8_pore_api.h,v $
-Revision 1.2  2012/04/11 16:58:29  cmolsen
-Removed #define of __PORE_INLINE_ASSEMBLER_C__
-
-Revision 1.1  2011/08/25 12:28:04  yjkim
-initial checkin
-
-Revision 1.8  2010/08/31 14:47:15  schwartz
-Changed comments about scom operations to include SCOM in the name
-
-Revision 1.7  2010/08/30 23:27:16  schwartz
-Added TRACE statements to include specified number of arguments
-Defined branch type constants
-Added constant for last scom op used to check if operation input to gen_scan is valid
-Added mult spr error constant
-Added p7p_pore_gen_wait API
-Changed additional C++ style comments to C style
-Initialized all variables to 0
-Removed FTRACE statements
-Added additional information to trace statements
-Updated gen_scom to use the defined operation constants
-Updated branch gen_relbranch to use defined branch type constants
-Added rc check for calls to p7p_pore_gen_cpureg_status and p7p_pore_span_128byte_boundary subroutines
-
-Revision 1.6  2010/08/26 03:57:02  schwartz
-Changed comments to C-style
-Changed "" to <> for #includes
-Moved RINGINFO struct and RINGINDEX constant into separate object file, includes created static_data.h file
-Put p7p_pore in front of #defines
-Removed ring length from ringInfoStruct
-Renamed scom operators to have SCOM in the name
-Fixed gen_scan to use SCANRD and SCANWR pore instructions
-Fixed compiler warnings
-
-Revision 1.5  2010/07/01 21:42:11  schwartz
-Included format (host or big endian) in parameter definitions
-
-Revision 1.4  2010/06/23 23:09:05  schwartz
-Updated ordering of include statements so p7p_pore_api_custom.h is first
-Updated definition of gen_cpureg to include coreIndex and threadIndex
-
-Revision 1.3  2010/05/24 02:32:07  schwartz
-Fixed errors that appear when using -Werrors flag
-Added in cvs logging (hopefully)
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_const.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_const.h
deleted file mode 100644
index 3c6bcaea2..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_const.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_const.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/* $Id: p8_pore_api_const.h,v 1.2 2012/06/11 20:55:00 cmolsen Exp $ */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/p8_pore_api_const.h,v $ */
-
-/**
-  * Contains any constants uses as inputs or outputs to the p7p_pore functions
-  */
-
-// CMO-20120601: SCOM Operators moved to p8_pore_table_gen_api.H
-/****************************/
-/*****  SCOM Operators  *****/
-/****************************/
-//#define P8_PORE_SCOM_APPEND  0  /* add scom instructions to the end of the existing image */
-//#define P8_PORE_SCOM_REPLACE 1  /* replace existing instructions with new data */
-//#define P8_PORE_SCOM_OR      2  /* overlay scom data onto existing instruction by bitwise OR */
-//#define P8_PORE_SCOM_AND     3  /* overlay scom data onto existing instruction by bitwise AND */
-//#define P8_PORE_SCOM_NOOP    4  /* replace existing instructions with NOP */
-//#define P8_PORE_SCOM_LAST_OP 4  /* keep track of the last op for checking correctness of op input */
-
-
-/***************************/
-/*****  CPU Registers  *****/
-/***************************/
-#define P8_PORE_HSPRG0  304
-#define P8_PORE_HRMOR   313
-#define P8_PORE_LPCR    318
-#define P8_PORE_HMEER   337
-#define P8_PORE_HID0   1008
-#define P8_PORE_HID1   1009
-#define P8_PORE_HID4   1012
-#define P8_PORE_HID5   1014
-#define P8_PORE_MSR    2000
-
-
-/****************************/
-/*****  Branch Types    *****/
-/****************************/
-#define P8_PORE_BRA_REL  0  /* generate relative branch instruction */
-#define P8_PORE_BRA_SUB  1  /* generate branch to subroutine instruction */
-
-
-/**************************/
-/*****  Return Codes  *****/
-/**************************/
-#define P8_PORE_SUCCESS_RC          0x00000000  /* Success, no errors */
-#define P8_PORE_IMAGE_TOO_BIG_RC    0x00000001  /* size of PORE image exceeded allowed space */
-#define P8_PORE_BAD_ARG_RC          0x00000002  /* some input argument is nonsensical */
-#define P8_PORE_NO_ADDR_FOUND_RC    0x00000003  /* address to overlay not found */
-#define P8_PORE_MULT_ADDR_FOUND_RC  0x00000004  /* address to replace/overlay found multiple times */
-#define P8_PORE_MULT_SPR_FOUND_RC   0x00000005  /* spr to add/replace found multiple times*/
-#define P8_PORE_BAD_RING_ADDR_RC    0x00000006  /* don't recognize the ring addr*/
-
-
-/* may need to include errors for 128byte_bound check and cpureg_status check */
-/*...etc...*/
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-
-$Log: p8_pore_api_const.h,v $
-Revision 1.2  2012/06/11 20:55:00  cmolsen
-Updated to comment out the Scom operation defines which are now defined in
-p8_pore_table_gen_api.H instead.
-
-Revision 1.1  2011/08/25 12:32:33  yjkim
-initial checkin
-
-Revision 1.7  2010/11/03 19:13:16  schwartz
-Added code to gen_cpureg to handle changes to MSR
-
-Revision 1.6  2010/08/30 23:27:16  schwartz
-Added TRACE statements to include specified number of arguments
-Defined branch type constants
-Added constant for last scom op used to check if operation input to gen_scan is valid
-Added mult spr error constant
-Added p7p_pore_gen_wait API
-Changed additional C++ style comments to C style
-Initialized all variables to 0
-Removed FTRACE statements
-Added additional information to trace statements
-Updated gen_scom to use the defined operation constants
-Updated branch gen_relbranch to use defined branch type constants
-Added rc check for calls to p7p_pore_gen_cpureg_status and p7p_pore_span_128byte_boundary subroutines
-
-Revision 1.5  2010/08/26 15:13:34  schwartz
-Fixed more C++ style comments to C style comments
-
-Revision 1.4  2010/08/26 03:57:02  schwartz
-Changed comments to C-style
-Changed "" to <> for #includes
-Moved RINGINFO struct and RINGINDEX constant into separate object file, includes created static_data.h file
-Put p7p_pore in front of #defines
-Removed ring length from ringInfoStruct
-Renamed scom operators to have SCOM in the name
-Fixed gen_scan to use SCANRD and SCANWR pore instructions
-Fixed compiler warnings
-
-Revision 1.3  2010/06/23 23:07:40  schwartz
-Updated define statements for SPRs, constant values are actual SPR values from Book IV
-
-Revision 1.2  2010/05/24 02:33:14  schwartz
-Fixed errors that appear when using -Werrors flag
-Added in cvs logging (hopefully)
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_custom.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_custom.h
deleted file mode 100644
index 649ebc0ea..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_custom.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_api_custom.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/* $Id: p8_pore_api_custom.h,v 1.5 2012/05/22 21:25:21 cmolsen Exp $ */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/p8_pore_api_custom.h,v $ */
-
-#include <stdint.h> /* for uint32_t */
-#include <stdio.h> /* for printf */
-#ifndef __HOSTBOOT_MODULE
-#include <netinet/in.h> /* for htonl */
-#endif
-
-/**
-  * This file should be modified by users to appropriately handle some
-  * environment-specific operations.
-  */
-
-
-/*********************************/
-/*****  Logging and Tracing  *****/
-/*********************************/
-/**
- * All tracing functions assume printf-style formatting
- */
-
-#ifndef __FAPI
-/* Trace an informational message */
-#define P8_PORE_ITRACE0(msg) printf("PORE> INFO: " msg "\n");
-#define P8_PORE_ITRACE1(msg, arg0) printf("PORE> INFO: " msg "\n", arg0);
-
-/* Trace an error message */
-#define P8_PORE_ETRACE0(msg) printf("PORE> ERROR: " msg "\n");
-#define P8_PORE_ETRACE1(msg, arg0) printf("PORE> ERROR: " msg "\n", arg0);
-#define P8_PORE_ETRACE2(msg, arg0, arg1) printf("PORE> ERROR: " msg "\n", arg0, arg1);
-#define P8_PORE_ETRACE3(msg, arg0, arg1, arg2) printf("PORE> ERROR: " msg "\n", arg0, arg1, arg2);
-#define P8_PORE_ETRACE4(msg, arg0, arg1, arg2, arg3) printf("PORE> ERROR: " msg "\n", arg0, arg1, arg2, arg3);
-#define P8_PORE_ETRACE5(msg, arg0, arg1, arg2, arg3, arg4) printf("PORE> ERROR: " msg "\n", arg0, arg1, arg2, arg3, arg4);
-#endif
-/* Used for debug, Cronus/FW should leave these empty */
-#define P8_PORE_DTRACE0(msg)
-#define P8_PORE_DTRACE1(msg, arg0) 
-#define P8_PORE_DTRACE2(msg, arg0, arg1) 
-#define P8_PORE_DTRACE3(msg, arg0, arg1, arg2) 
-#define P8_PORE_DTRACE4(msg, arg0, arg1, arg2, arg3) 
-
-/****** Following is only used for debug purposes ******/
-/* FW/Cronus should NOT include this section */
-/* DTRACE - Print debug statements to command line */
-/* FTRACE - Print text PORE instructions of cpureg setup to DEBUG_FILE */
-/*
-#define P8_PORE_DTRACE0(msg) printf("PORE> DEBUG: " msg "\n");
-#define P8_PORE_DTRACE1(msg, arg0) printf("PORE> DEBUG: " msg "\n", arg0);
-#define P8_PORE_DTRACE2(msg, arg0, arg1) printf("PORE> DEBUG: " msg "\n", arg0, arg1);
-#define P8_PORE_DTRACE3(msg, arg0, arg1, arg2) printf("PORE> DEBUG: " msg "\n", arg0, arg1, arg2);
-#define P8_PORE_DTRACE4(msg, arg0, arg1, arg2, arg3) printf("PORE> DEBUG: " msg "\n", arg0, arg1, arg2, arg3);
-*/
-
-/**********************************/
-/*****  Endian-ness Handling  *****/
-/**********************************/
-/**
- * Handle byte-swapping if necessary
- */
-
-/* Default to big-endian format on both sides */
-#define P8_PORE_HOST_TO_BIG32( bit32_int )  htonl(bit32_int)
-#define P8_PORE_BIG32_TO_HOST( bit32_int )  ntohl(bit32_int)
-#define P8_PORE_HOST_TO_BIG16( bit16_int )  htonl(bit16_int)
-#define P8_PORE_BIG16_TO_HOST( bit16_int )  ntohl(bit16_int)
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-
-$Log: p8_pore_api_custom.h,v $
-Revision 1.5  2012/05/22 21:25:21  cmolsen
-Updated to remove FAPI tracing, which is not allowed in plain C files.
-
-Revision 1.4  2012/05/21 14:45:41  cmolsen
-Updated to address Gerrit review II comments about printf() usage.
-
-Revision 1.3  2012/05/15 19:53:38  cmolsen
-Updated to address Gerrit review comments:
-- Hostboot doesn't support printf().
-
-Revision 1.2  2012/04/13 16:45:32  cmolsen
-Includes __HOSTBOOT_MODULE exclude of <netinit/in.h>
-
-Revision 1.1  2011/08/25 12:28:38  yjkim
-initial check in
-
-Revision 1.10  2010/08/30 23:27:17  schwartz
-Added TRACE statements to include specified number of arguments
-Defined branch type constants
-Added constant for last scom op used to check if operation input to gen_scan is valid
-Added mult spr error constant
-Added p7p_pore_gen_wait API
-Changed additional C++ style comments to C style
-Initialized all variables to 0
-Removed FTRACE statements
-Added additional information to trace statements
-Updated gen_scom to use the defined operation constants
-Updated branch gen_relbranch to use defined branch type constants
-Added rc check for calls to p7p_pore_gen_cpureg_status and p7p_pore_span_128byte_boundary subroutines
-
-Revision 1.9  2010/08/30 14:57:54  schwartz
-Removed FTRACE and associated #define statements
-Changed TRACE macros to multiple macros with specified number of args
-
-Revision 1.6  2010/08/26 15:13:34  schwartz
-Fixed more C++ style comments to C style comments
-
-Revision 1.5  2010/06/23 23:06:37  schwartz
-Defined additional trace functions to be used for debugging, not in FW or Cronus
-
-Revision 1.4  2010/05/24 02:34:07  schwartz
-Fixed errors that appear when using -Werrors flag
-Added in cvs logging (hopefully)
-
-
-*/
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H
deleted file mode 100644
index 63081ca50..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H
+++ /dev/null
@@ -1,440 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pore_table_gen_api.H,v 1.27 2014/06/02 18:21:55 cmolsen Exp $
-/*------------------------------------------------------------------------------*/
-/* *! (C) Copyright International Business Machines Corp. 2012                  */
-/* *! All Rights Reserved -- Property of IBM                                    */
-/* *! ***  ***                                                  */
-/*------------------------------------------------------------------------------*/
-/* *! TITLE :       p8_pore_table_gen_api.H                                     */
-/* *! DESCRIPTION : Contains all external APIs used by firmware (PHYP) to       */
-//                  generate/modify the P8 PORE SLW image with Ramming and
-//                  Scomming specific instructions to be executed on exit from
-//                  Sleep/Winkle. Also contains definitions for the ramming
-//                  PORE code.
-/* *! OWNER NAME :  Michael Olsen            Email: cmolsen@us.ibm.com          */
-//
-/* *! COMMENTS :    *** VERY IMPORTANT ***                                      */
-//                  The "Shared RAM section", the "Pore RAM section" and the
-//                  "C-code RAM section" must closely match eachother.
-//
-/*------------------------------------------------------------------------------*/
-
-#ifndef _P8_PORE_TABLE_GEN_API_H
-#define _P8_PORE_TABLE_GEN_API_H
-
-/********************************************************************/
-/* Shared RAM section  -  begin                                     */
-/* This section MUST perfectly match the "Pore/C-code RAM section". */
-/********************************************************************/
-// Header defs (P8&PORE 64-bit notation where bits are numbered from left-to-right).
-// (Some of these defs are used in the c-specific section further down.)
-// -----------------------------------------------------------------------------
-// Note:  SPR register numbers have a swizzle about them per PPC architecture
-// spr(instruction) <- spr5:9 || spr0:4
-//
-// For the PGAS routine, it is assumed that the API does the swizzling upon
-// building the instruction held in this structure
-//
-//    Header configuration: CPU Register Operation Header
-//    0       - End:  1=End; 0=More
-//    1       - Reserved
-//    2:3     - Type
-//                00: MTSPR
-//                01: MTMSRD
-//                10: Reserved
-//                11: Reserved
-//    4:13    - SPR number in non-swizzled form (0:9)
-//    14:15   - Reserved for SPR nunmber expansion
-//    16:18   - Thread ID
-//    19:31   - Reserved 
-
-#define RAM_HEADER_END_START      0
-#define RAM_HEADER_END_MASK      BITS(RAM_HEADER_END_START,1)
-#define RAM_HEADER_TYPE_START     2
-#define RAM_HEADER_TYPE_MASK     BITS(RAM_HEADER_TYPE_START,2)
-#define RAM_HEADER_SPRN_START     4
-#define RAM_HEADER_SPRN_MASK     BITS(RAM_HEADER_SPRN_START,10)
-#define RAM_HEADER_THREAD_START  16
-#define RAM_HEADER_THREAD_MASK   BITS(RAM_HEADER_THREAD_START,3)
-#define RAM_INSTR_START          32
-#define RAM_INSTR_MASK           BITS(RAM_INSTR_START,32)
-// MTSPR instr defs
-#define RAM_MTSPR_INSTR_TEMPL    ( ( (uint64_t)31<<(63-5) | (uint64_t)467<<(63-30) ) )
-#define RAM_MTSPR_SPR_START      11
-#define RAM_MTSPR_SPR_MASK       BITS(RAM_MTSPR_SPR_START,10)
-// Thread align defs
-#define RAM_HEADER_THREAD_RALIGN ( 61-16 )  // 3 Bit shift right amount
-#define RAM_HEADER_THREAD_LALIGN ( 61-16 )  // 3 Bit shift left amount
-/********************************************************************/
-/* Shared RAM section  -  end                                       */
-/********************************************************************/
-
-
-#ifdef FOR_PORE_RAMMING
-
-// Thread status
-CONST_UINT64_T( PROC_RAS_STAT_10013002                , ULL(0x10013002) ); 
-
-// TCTL RAS Status (for each thread)
-// Note:  the address is not included in the name to ease PGAS indexing
-// of these registers
-CONST_UINT64_T( EX_PERV_TCTL0_R_STAT                  , ULL(0x10013002) );
-CONST_UINT64_T( EX_PERV_TCTL1_R_STAT                  , ULL(0x10013012) );
-CONST_UINT64_T( EX_PERV_TCTL2_R_STAT                  , ULL(0x10013022) );
-CONST_UINT64_T( EX_PERV_TCTL3_R_STAT                  , ULL(0x10013032) );
-CONST_UINT64_T( EX_PERV_TCTL4_R_STAT                  , ULL(0x10013042) );
-CONST_UINT64_T( EX_PERV_TCTL5_R_STAT                  , ULL(0x10013052) );
-CONST_UINT64_T( EX_PERV_TCTL6_R_STAT                  , ULL(0x10013062) );
-CONST_UINT64_T( EX_PERV_TCTL7_R_STAT                  , ULL(0x10013072) );
-
-// Thread scratch registers
-// Note:  the address is not included in the name to ease PGAS indexing
-// of these registers
-CONST_UINT64_T( EX_PERV_SCRATCH0                      , ULL(0x10013283) );  
-CONST_UINT64_T( EX_PERV_SCRATCH1                      , ULL(0x10013284) );  
-CONST_UINT64_T( EX_PERV_SCRATCH2                      , ULL(0x10013285) );  
-CONST_UINT64_T( EX_PERV_SCRATCH3                      , ULL(0x10013286) );  
-CONST_UINT64_T( EX_PERV_SCRATCH4                      , ULL(0x10013287) );  
-CONST_UINT64_T( EX_PERV_SCRATCH5                      , ULL(0x10013288) );  
-CONST_UINT64_T( EX_PERV_SCRATCH6                      , ULL(0x10013289) );  
-CONST_UINT64_T( EX_PERV_SCRATCH7                      , ULL(0x1001328A) );
-
-// Ramming settings.
-CONST_UINT64_T( RAM_STATUS_REG_AFTER_RAM,       0x5000000000000000);
-CONST_UINT64_T( RAM_COMPLETE_POLLS,             0x0000000000000040);
-
-// mfspr gpr0, scratch0  opcode left-shifted 29 bits, ready for ramming.
-CONST_UINT64_T( MTSPR_SCRATCH0_GPR0_RAM_READY,  (0x000000007C1543A6<<29));
-CONST_UINT64_T( MFSPR_GPR0_SCRATCH0_RAM_READY,  (0x000000007C1542A6<<29));
-CONST_UINT64_T( MTMSRD_GPR0_RAM_READY,          (0x000000007C000164<<29));
-CONST_UINT64_T( MFMSR_GPR0_RAM_READY,           (0x000000007C0000A6<<29));
-
-// Predefined MSR content during Ramming
-CONST_UINT64_T( P8_PORE_MSR_DURING_RAM,         (0x9000000002802000) );
-
-// "reset" value of SCRATCH0 to ensure it gets updated from GPR0
-CONST_UINT64_T( SCRATCH0_RESET_VALUE,           (0xABBA99EBBA33DADA) );
-
-#ifdef __ASSEMBLER__  
-
-/***********************************************************************/
-/* Pore RAM section  -  begin                                          */
-/* This section MUST perfectly match the "Shared/C-code RAM  section". */
-/***********************************************************************/
-.set    RAM_HEADER, 0
-.set    RAM_INSTR,  4
-.set    RAM_DATA,   8 
-.set    RAM_ENTRY_LENGTH, 16 
-/***********************************************************************/
-/* Pore RAM section  -  end                                            */
-/***********************************************************************/
-
-#endif  // __ASSEMBLER__
-
-
-#else   // Not FOR_PORE_RAMMING
-
-
-//#include <stdio.h>
-#ifndef PPC_HYP
-#include <stdlib.h>
-#endif // PPC_HYP
-#ifndef __P8_PORE_TABLE_GEN_API_C
-#include <p8_pore_api_custom.h>
-#endif
-//#include <stdint.h>
-
-//#include <pore_bitmanip.H>
-// Defining local versions of BITS and BIT
-// Create a multi-bit mask of \a n bits starting at bit \a b
-#define BITS(b, n)  ((ULL(0xffffffffffffffff) << (64 - (n))) >> (b))
-#define BITS32(b,n) (uint32_t)((ULL(0xffffffff) << (32 - (n))) >> (b))
-// Create a single bit mask at bit \a b
-#define BIT(b) BITS((b), 1)
-
-// Header defs (C notation where bits are numbered from right-to-left, and reducing to 32-bit)
-#define RAM_HEADER_END_START_C    ( 31-RAM_HEADER_END_START+1-1 )
-#define RAM_HEADER_END_MASK_C      (uint32_t)(RAM_HEADER_END_MASK>>32)
-#define RAM_HEADER_TYPE_START_C    ( 31-RAM_HEADER_TYPE_START+1-2 )
-#define RAM_HEADER_TYPE_MASK_C    (uint32_t)(RAM_HEADER_TYPE_MASK>>32)
-#define RAM_HEADER_SPRN_START_C    ( 31-RAM_HEADER_SPRN_START+1-10 )
-#define RAM_HEADER_SPRN_MASK_C    (uint32_t)(RAM_HEADER_SPRN_MASK>>32)
-#define RAM_HEADER_THREAD_START_C  ( 31-RAM_HEADER_THREAD_START+1-3 )
-#define RAM_HEADER_THREAD_MASK_C  (uint32_t)(RAM_HEADER_THREAD_MASK>>32)
-// MTSPR instr defs
-#define RAM_MTSPR_INSTR_TEMPL_C    ( ( (uint32_t)31<<(31-5) | (uint32_t)467<<(31-30) ) )
-#define RAM_MTSPR_SPR_START_C      ( 31-RAM_MTSPR_SPR_START+1-10 )
-//#define RAM_MTSPR_SPR_MASK_C      (uint32_t)(BITS(RAM_MTSPR_SPR_START,10)>>32)
-#define RAM_MTSPR_SPR_MASK_C      (uint32_t)(RAM_MTSPR_SPR_MASK>>32)
-// MTMSR innstr def
-#define RAM_MTMSRD_INSTR_TEMPL_C   ( ( (uint32_t)31<<(31-5) | (uint32_t)178<<(31-30) ) )
-
-/* Other defs needed for ramming and scomming */
-// TOC names
-#define SLW_HOST_REG_VECTOR_TOC_NAME         "slw_host_reg_vector"
-#define SLW_HOST_SCOM_NC_VECTOR_TOC_NAME     "slw_host_scom_nc_vector"
-#define SLW_HOST_SCOM_L2_VECTOR_TOC_NAME     "slw_host_scom_l2_vector"
-#define SLW_HOST_SCOM_L3_VECTOR_TOC_NAME     "slw_host_scom_l3_vector"
-
-// Defines for slw_build() to update "runtime_scom" pointers w/pointer to 
-//   "sub_slw_runtime_scom" subroutines at SLW image build time.
-#define HOST_RUNTIME_SCOM_TOC_NAME           "host_runtime_scom"    // Null 1st, then fill w/addr of SLW_RUNTIME_SCOM_TOC_NAME
-#define SLW_RUNTIME_SCOM_TOC_NAME            "sub_slw_runtime_scom"
-
-// The following two provide TRANSITIONAL SUPPORT only. TO BE REMOVED ASAP.
-#define EX_ENABLE_RUNTIME_SCOM_TOC_NAME      "ex_enable_runtime_scom"
-#define SLW_EX_ENABLE_RUNTIME_SCOM_TOC_NAME  "sub_slw_ex_enable_runtime_scom"
-
-#define SCAN_MAX_ROTATE_38XXX_NAME           "scan_max_rotate_38xxx"
-#define SCAN_ROTATE_DEFAULT                  110 // Limit suggested by Tilman.
-#define SCAN_MAX_ROTATE                      0x00000FE0
-#define SCAN_MAX_ROTATE_LONG                 0x000FFFFF // All 1s in BITS 12->31.
-//#define SCAN_MAX_ROTATE_LONG                 0x000000D0 // Experimental max val
-
-#define OVER_SAMPLING_POLL                   10
-#define WAITS_POLL_MIN                       32
-
-// RAM table defines
-#define XIPSIZE_RAM_ENTRY       ( (sizeof(RamTableEntry)+7)/8*8 )
-#define SLW_MAX_CORES           16
-#define SLW_MAX_CPUREGS_CORE    10
-#define SLW_MAX_CPUREGS_THREADS  5
-#define SLW_CORE_THREADS         8
-#define SLW_MAX_CPUREGS_OPS     ( SLW_MAX_CPUREGS_CORE + \
-                                  SLW_CORE_THREADS*SLW_MAX_CPUREGS_THREADS )
-#define SLW_RAM_TABLE_SPACE_PER_CORE ( SLW_MAX_CPUREGS_OPS * XIPSIZE_RAM_ENTRY )
-#define SLW_RAM_TABLE_SIZE      ( SLW_MAX_CORES * SLW_RAM_TABLE_SPACE_PER_CORE )
-
-// SPR and MSR values for i_regName
-enum  {
-  P8_SPR_HRMOR  =  313,
-  P8_SPR_HMEER  =  337,
-  P8_SPR_PMICR  =  852,
-  P8_SPR_PMCR   =  884,
-  P8_SPR_HID0   = 1008,
-  P8_SPR_HID1   = 1009,
-  P8_SPR_HID4   = 1012,
-  P8_SPR_HID5   = 1014,
-	P8_CORE_XTRA8 =10008,
-	P8_CORE_XTRA9 =10009,
-  P8_SPR_HSPRG0 =  304,
-  P8_SPR_LPCR   =  318,
-  P8_MSR_MSR    = 2000,
-	P8_THRD_XTRA3 =20003,
-	P8_THRD_XTRA4 =20004
-};
-
-// SCOM table defines - Common
-#define XIPSIZE_SCOM_ENTRY      16
-
-// SCOM table defines - Non-cache section
-#define SLW_MAX_SCOMS_NC        32
-#define SLW_SCOM_TABLE_SPACE_PER_CORE_NC ( (SLW_MAX_SCOMS_NC+1)*XIPSIZE_SCOM_ENTRY ) // Add 1 for RNNN IIS
-#define SLW_SCOM_TABLE_SIZE_NC     (  SLW_MAX_CORES * SLW_SCOM_TABLE_SPACE_PER_CORE_NC )
-
-// SCOM table defines - L2 section
-#define SLW_MAX_SCOMS_L2        16
-#define SLW_SCOM_TABLE_SPACE_PER_CORE_L2 ( (SLW_MAX_SCOMS_L2+1)*XIPSIZE_SCOM_ENTRY ) // Add 1 for RNNN IIS
-#define SLW_SCOM_TABLE_SIZE_L2     (  SLW_MAX_CORES * SLW_SCOM_TABLE_SPACE_PER_CORE_L2 )
-
-// SCOM table defines - L3 section
-#define SLW_MAX_SCOMS_L3        16
-#define SLW_SCOM_TABLE_SPACE_PER_CORE_L3 ( (SLW_MAX_SCOMS_L3+1)*XIPSIZE_SCOM_ENTRY ) // Add 1 for RNNN IIS
-#define SLW_SCOM_TABLE_SIZE_L3     (  SLW_MAX_CORES * SLW_SCOM_TABLE_SPACE_PER_CORE_L3 )
-
-#define SLW_SCOM_TABLE_SIZE_ALL   ( SLW_SCOM_TABLE_SIZE_NC + SLW_SCOM_TABLE_SIZE_L2 + SLW_SCOM_TABLE_SIZE_L3)
-
-// RAM and SCOM sub-section offsets from beginning of .slw section.
-#define SLW_RAM_TABLE_OFFSET        0
-#define SLW_SCOM_TABLE_OFFSET_NC    (SLW_RAM_TABLE_OFFSET + SLW_RAM_TABLE_SIZE)
-#define SLW_SCOM_TABLE_OFFSET_L2    (SLW_SCOM_TABLE_OFFSET_NC + SLW_SCOM_TABLE_SIZE_NC)
-#define SLW_SCOM_TABLE_OFFSET_L3    (SLW_SCOM_TABLE_OFFSET_L2 + SLW_SCOM_TABLE_SIZE_L2)
-#define SLW_TABLE_SIZE_ALL          (SLW_RAM_TABLE_SIZE + SLW_SCOM_TABLE_SIZE_ALL)
-
-// Enumeration of Scom sections in .slw section.
-enum  {
-  P8_SCOM_SECTION_NC        =  0,
-  P8_SCOM_SECTION_L2        =  1,
-  P8_SCOM_SECTION_L3        =  2,
-  P8_SCOM_SECTION_MAX_VALUE =  2
-};
-
-// SLW section size (Ensure 128-byte alignment.)
-#define FIXED_SLW_SECTION_SIZE      (SLW_TABLE_SIZE_ALL/128+(SLW_TABLE_SIZE_ALL%128+127)/128)*128
-
-// FFDC section size (Ensure 128-byte alignment.)
-#define FIXED_FFDC_SECTION_SIZE     640*(SLW_MAX_CORES+1)
-
-// SCOM/CID masks and ranges
-#define P8_CID_EX_LOW         0x10        // Lowest EX chiplet addr
-#define P8_CID_EX_HIGH        0x1f        // Highest EX chiplet addr
-
-// SCOM Operators
-#define P8_PORE_SCOM_FIRST_OP   0  // First supported Scom operation.
-#define P8_PORE_SCOM_APPEND     0  // Add Scom to end of table or at first PORE NOP
-                                   // instruction, whichever comes first.
-#define P8_PORE_SCOM_REPLACE    1  // Repl 1st matching Scom addr or treat as APPEND
-                                   // if Scom entry is not found.
-#define P8_PORE_SCOM_OR         2  // Overlay data onto existing Scom by bitwise OR.
-#define P8_PORE_SCOM_AND        3  // Overlay data onto existing Scom by bitwise AND.
-#define P8_PORE_SCOM_NOOP       4  // Replace existing Scom with a PORE NOP instruction,
-                                   // NNNN.
-#define P8_PORE_SCOM_RESET      5  // Delete all entries for given coreID. Replace with
-                                   // PORE RET instructions, RNNN.
-#define P8_PORE_SCOM_OR_APPEND  6  // Same as OR but treat as APPEND if Scom entry is
-                                   // not found.
-#define P8_PORE_SCOM_AND_APPEND 7  // Same as AND but treat as APPEND if Scom entry is
-                                   // not found.
-#define P8_PORE_SCOM_LAST_OP    7  // Last supported Scom operation.
-
-
-// Enumeration of SLW image build modes.
-enum  {
-  P8_SLW_MODEBUILD_IPL       = 0,
-  P8_SLW_MODEBUILD_REBUILD   = 1,
-  P8_SLW_MODEBUILD_SRAM      = 2,
-  P8_SLW_MODEBUILD_MAX_VALUE = 2
-};
-
-
-// Return codes
-#define SLW_RAM_SUCCESS                      0
-#define SLW_RAM_HEADERS_NOT_SYNCED           1
-#define SLW_RAM_IMAGE_SIZE_MISMATCH          2
-#define SLW_RAM_TABLE_ENTRY_OVERFLOW         3
-#define SLW_RAM_CODE_ERROR                   4
-#define SLW_RAM_INVALID_PARAMETER            5
-#define SLW_RAM_WARNING_TABLE_CONTAMINATION  6
-
-
-#ifndef PPC_HYP
-#ifdef __cplusplus
-extern "C" {
-#endif
-#endif // PPC_HYP
-
-/********************************************************************/
-/* C-code RAM section  -  begin                                     */
-/* This section MUST perfectly match the "Shared/Pore RAM section". */
-/********************************************************************/
-typedef struct ram_instr_t  {
-  uint32_t  header;
-  uint32_t  instr;
-  uint64_t  data;
-} RamTableEntry;
-/********************************************************************/
-/* C-code RAM section  -  end                                       */
-/********************************************************************/
-
-// SLW supported SPR registers
-typedef struct {
-  const char *name;
-  uint32_t   value;
-  uint32_t   swizzled;
-} SlwSprRegs;
-
-extern const SlwSprRegs SLW_SPR_REGS[];
-extern const int SLW_SPR_REGS_SIZE;
-
-/*  Name:             p8_pore_gen_cpureg()
- *  Description:      Populates ramming entries in the .slw section
- *  Parameter list:   i_image     - pointer to SLW mainstore image
- *                    i_sizeImage - size of SLW mainstore image
- *                    i_regName   - unswizzled SPR register value
- *                    i_regData   - data to write to SPR register
- *                    i_coreId    - the core ID to operate on
- *                    i_threadId  - the thread ID to operate on
- */
-uint32_t p8_pore_gen_cpureg(void      *io_image,
-                            uint32_t  i_sizeImage,
-                            uint32_t  i_regName,
-                            uint64_t  i_regData,
-                            uint32_t  i_coreId,
-                            uint32_t  i_threadId);
-
-/*  Name:             p8_pore_gen_scom()
- *  Description:      Populates scom entries in the .slw section
- *  Parameter list:   i_image     - pointer to SLW mainstore image
- *                    i_sizeImage - size of SLW mainstore image
- *                    i_scomAddr  - scom register address
- *                    i_coreId    - the core ID [0:15]
- *                    i_scomData  - 64-bit data to put in scom register
- *                    i_operation - what to do with the scom data [0:5]
- *                    i_section   - SCOM section [0,2,3]
- */
-uint32_t p8_pore_gen_scom(void      *io_image,
-                          uint32_t  i_sizeImage,
-                          uint32_t  i_scomAddr,
-                          uint32_t  i_coreId,
-                          uint64_t  i_scomData,
-                          uint32_t  i_operation,
-                          uint32_t  i_section);
-
-
-/*  Name:             p8_pore_gen_cpureg_fixed()
- *  Description:      Populates ramming entries in the .slw section
- *  Parameter list:   i_image     - pointer to SLW mainstore image
- *                    i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
- *                    i_sizeImage - size of SLW mainstore image
- *                    i_regName   - unswizzled SPR register value
- *                    i_regData   - data to write to SPR register
- *                    i_coreId    - the core ID to operate on
- *                    i_threadId  - the thread ID to operate on
- */
-uint32_t p8_pore_gen_cpureg_fixed(void      *io_image,
-                            uint8_t   i_modeBuild, 
-                            uint32_t  i_regName,
-                            uint64_t  i_regData,
-                            uint32_t  i_coreId,
-                            uint32_t  i_threadId);
-
-/*  Name:             p8_pore_gen_scom_fixed()
- *  Description:      Populates scom entries in the .slw section
- *  Parameter list:   i_image     - pointer to SLW mainstore image
- *                    i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
- *                    i_scomAddr  - scom register address
- *                    i_coreId    - the core ID [0:15]
- *                    i_scomData  - 64-bit data to put in scom register
- *                    i_operation - what to do with the scom data [0:5]
- *                    i_section   - 0: General Scoms, 1: L2 cache, 2: L3 cache
- */
-uint32_t p8_pore_gen_scom_fixed(void      *io_image,
-                          uint8_t   i_modeBuild, 
-                          uint32_t  i_scomAddr,
-                          uint32_t  i_coreId,
-                          uint64_t  i_scomData,
-                          uint32_t  i_operation,
-                          uint32_t  i_section);
-
-#ifndef PPC_HYP
-#ifdef __cplusplus
-}
-#endif
-#endif // PPC_HYP
-
-#endif  // FOR_PORE_RAMMING
-
-#endif  // _P8_PORE_TABLE_GEN_API_H
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
deleted file mode 100644
index 47c1afeb1..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C
+++ /dev/null
@@ -1,846 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api_fixed.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_pore_table_gen_api_fixed.C,v 1.15 2014/05/30 20:31:24 cmolsen Exp $
-//
-/*------------------------------------------------------------------------------*/
-/* *! (C) Copyright International Business Machines Corp. 2012                  */
-/* *! All Rights Reserved -- Property of IBM                                    */
-/* *! ***  ***                                                  */
-/*------------------------------------------------------------------------------*/
-/* *! TITLE :       p8_pore_table_gen_api_fixed.C                               */
-/* *! DESCRIPTION : PORE SLW table generaion APIs                               */
-/* *! OWNER NAME :  Michael Olsen            Email: cmolsen@us.ibm.com          */
-//
-/* *! USAGE :       To build for PHYP command-line -                            */
-/*                  buildecmdprcd   -C "p8_pore_table_gen_api_fixed.C"   -c "p8_pore_table_static_data.c,sbe_xip_image.c,pore_inline_assembler.c"  -u "SLW_COMMAND_LINE_RAM"  p8_pore_table_gen_api_fixed_main.C                                                    */
-//
-/* *! COMMENTS :    - The DYNAMIC_RAM_TABLE_PPD was dropped in v1.12 of this    */ 
-/*                    code. See v1.12 for explanation and code implementation.  */
-//
-/*------------------------------------------------------------------------------*/
-
-#define __P8_PORE_TABLE_GEN_API_C
-#include <p8_pore_api_custom.h>
-#include <p8_pore_table_gen_api.H>
-#include <p8_delta_scan_rw.h>
-
-/*
-// io_image -      pointer to SLW image
-// i_modeBuild -   0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
-// i_regName -     unswizzled enum SPR value (NOT a name)
-// i_regData -     data to write
-// i_coreIndex -   core ID = [0:15]
-// i_threadIndex - thread to operate on = [0:7]. 
-*/
-uint32_t p8_pore_gen_cpureg_fixed(  void      *io_image,
-                              uint8_t   i_modeBuild,
-                              uint32_t  i_regName, 
-                              uint64_t  i_regData, 
-                              uint32_t  i_coreId,
-                              uint32_t  i_threadId)
-{
-  uint32_t  rc=0, rcLoc=0, iCount=0;
-  int       i=0, iReg=-1;
-  uint64_t  xipSlwRamSection;
-  void      *hostSlwRamSection;
-  void      *hostSlwSectionFixed;
-  uint64_t  xipRamTableThis;
-  void      *hostRamVector;
-  void      *hostRamTableThis=NULL;
-  void      *hostRamEntryThis=NULL, *hostRamEntryNext=NULL;
-  uint8_t   bNewTable=0, bFound=0;
-  uint8_t   bEntryEnd=1, headerType=0;
-  SbeXipSection  xipSection;
-  SbeXipItem    xipTocItem;
-  RamTableEntry ramEntryThis, *ramEntryNext;
-  uint32_t  sprSwiz=0;
-
-  // -------------------------------------------------------------------------
-  // Validate Ramming parameters.
-  //
-  // ...check mode build
-  if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE)  {
-    MY_ERR("modeBuild=%i invalid. Valid range is [0;%i].",
-      i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE);
-    rcLoc = 1;
-  }
-  // ...check register value
-  bFound = 0;
-  for (i=0;i<SLW_SPR_REGS_SIZE;i++)  {
-    if (i_regName==SLW_SPR_REGS[i].value)  {
-      bFound = 1;
-      iReg = i;
-      break;
-    }
-  }
-  if (!bFound)  {
-    MY_ERR("Register value = %i is not supported.\n",i_regName);
-    MY_ERR("The following registers are supported:\n");
-    for (i=0;i<SLW_SPR_REGS_SIZE;i++)
-      MY_ERR("\t(%s,%i)\n",SLW_SPR_REGS[i].name,SLW_SPR_REGS[i].value);
-    rcLoc = 1;
-  }
-  // ...check core ID
-  if (i_coreId>=SLW_MAX_CORES)  {
-    MY_ERR("Core ID = %i is not within valid range of [0;%i]\n",i_coreId,SLW_MAX_CORES-1);
-    rcLoc = 1;
-  }
-  // ...check thread ID
-  // - ensure it's zero if SPR is not thread scoped, i.e. if SPR is core scoped.
-  // - error out if threadId exceed max num of threads.
-  if (i_regName!=P8_SPR_HSPRG0 && i_regName!=P8_SPR_LPCR && i_regName!=P8_MSR_MSR)  {
-    i_threadId = 0;
-  }
-  if (i_threadId>=SLW_CORE_THREADS)  {
-    MY_ERR("Thread ID = %i is not within valid range of [0;%i]\n",i_threadId,SLW_CORE_THREADS-1);
-    rcLoc = 1;
-  }
-  if (rcLoc)
-    return IMGBUILD_ERR_RAM_INVALID_PARM;
-  rcLoc = 0;
-  
-  // -------------------------------------------------------------------------
-  // Check slw section location and size. (Mainly needed for fixed image.)
-  //
-  if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
-      i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
-    hostSlwSectionFixed = (void*)( (uintptr_t)io_image + 
-                                   FIXED_SLW_IMAGE_SIZE -
-                                   FIXED_FFDC_SECTION_SIZE -
-                                   FIXED_SLW_SECTION_SIZE );
-    // Even though we shouldn't call this api during a rebuild, it should be 
-    // safe to do so in this particular case since none of the info requested
-    // is supposed to be moved during a rebuild.
-    rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-    if (rc)  {
-      MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
-      return IMGBUILD_ERR_GET_SECTION;
-    }
-    hostSlwRamSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
-    if (hostSlwSectionFixed!=hostSlwRamSection)  {
-      MY_ERR("hostSlwSectionFixed != hostSlwRamSection(from image api).\n");
-      return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
-    }
-    else  {
-      MY_INF("hostSlwSectionFixed == hostSlwRamSection(from image api).\n");
-    }
-  }
-  else  {  // SRAM non-fixed image.
-    rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-    if (rc)  {
-      MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
-      return IMGBUILD_ERR_GET_SECTION;
-    }
-    hostSlwRamSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
-    sbe_xip_host2pore( io_image, hostSlwRamSection, &xipSlwRamSection);
-  }
-
-  // -------------------------------------------------------------------------
-  // Cross check SPR register and table defines
-  //
-  if (SLW_SPR_REGS_SIZE!=(SLW_MAX_CPUREGS_CORE+SLW_MAX_CPUREGS_THREADS))  {
-    MY_ERR("Defines in *.H header file not in sync.\n");
-    return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
-  }
-  if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE)  {
-    MY_ERR("Fixed SLW table size in *.H header file differs from SLW section size in image.\n"); 
-    MY_ERR("Check code or image version.\n");
-    return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED;
-  }
-
-  // -------------------------------------------------------------------------
-  // Summarize parameters and checking results.
-  //
-  MY_INF("Input parameter checks - OK\n");
-  MY_INF("\tMode build= %i\n",i_modeBuild);
-  MY_INF("\tRegister  = (%s,%i)\n",SLW_SPR_REGS[iReg].name,SLW_SPR_REGS[iReg].value);
-  MY_INF("\tCore ID   = %i\n",i_coreId);
-  MY_INF("\tThread ID = %i\n",i_threadId);
-  MY_INF("Image validation and size checks - OK\n");
-  MY_INF("\tSLW section size=  %i\n",xipSection.iv_size);
-  
-  // -------------------------------------------------------------------------
-  // Locate RAM vector and locate RAM table associated with "This" core ID.
-  //
-  if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
-      i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
-    hostRamTableThis = (void*)( (uintptr_t)io_image +
-                                FIXED_SLW_IMAGE_SIZE -
-                                FIXED_FFDC_SECTION_SIZE -
-                                FIXED_SLW_SECTION_SIZE +
-                                SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
-    if (*(uintptr_t*)hostRamTableThis)  {  // Table content NOT empty.
-      bNewTable = 0;                       // So, NOT new table.
-    }
-    else  {                                // Table content empty.
-      bNewTable = 1;                       // So, new table.
-    }
-  }
-  else  {                 // SRAM non-fixed image.
-    rc = sbe_xip_find( io_image, SLW_HOST_REG_VECTOR_TOC_NAME, &xipTocItem);
-    if (rc)  {
-      MY_ERR("Probably invalid key word for SLW_HOST_REG_VECTOR_TOC_NAME.\n");
-      return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-    }
-    sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostRamVector);
-    xipRamTableThis = myRev64(*((uint64_t*)hostRamVector + i_coreId));
-    if (xipRamTableThis)  {
-      sbe_xip_pore2host( io_image, xipRamTableThis, &hostRamTableThis);
-      bNewTable = 0;
-    }
-    else  {
-      hostRamTableThis = (void*)( (uintptr_t)hostSlwRamSection + 
-                                  SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
-      bNewTable = 1;
-    }
-  }
-
-
-	// -------------------------------------------------------------------------
-  // Create most of the RAM entry, so it can be used to find a potential existing entry to 
-	// replace. Postpone decision about bEntryEnd and assume its zero for now (not end). 
-  //
-  if (i_regName==P8_MSR_MSR)  {
-    // ...make the MSR header
-    headerType = 0x1; // MTMSRD header.
-    ramEntryThis.header = ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C   & RAM_HEADER_TYPE_MASK_C )   |
-                          (            i_threadId  << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
-    // ...make the MSR instr
-    ramEntryThis.instr =  RAM_MTMSRD_INSTR_TEMPL_C;
-  }
-  else  {
-    // ...make the SPR header
-    headerType = 0x0; // MTSPR header.
-    ramEntryThis.header = ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C   & RAM_HEADER_TYPE_MASK_C )   |
-                          (            i_regName   << RAM_HEADER_SPRN_START_C   & RAM_HEADER_SPRN_MASK_C )   |
-                          (            i_threadId  << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C );
-    // ...make the SPR instr 
-    sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5;
-    if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled)  {
-      MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n");
-      MY_ERR("\tsprSwiz (on-the-fly-calc)=%i\n",sprSwiz);
-      MY_ERR("\tSLW_SPR_REGS[%i].swizzled=%i\n",iReg,SLW_SPR_REGS[iReg].swizzled);
-      return IMGBUILD_ERR_RAM_CODE;
-    }
-    ramEntryThis.instr =  RAM_MTSPR_INSTR_TEMPL_C | ( ( sprSwiz<<RAM_MTSPR_SPR_START_C ) & RAM_MTSPR_SPR_MASK_C );
-  }
-  // ...make the data
-  ramEntryThis.data  = i_regData;
-
-
-
-  // -------------------------------------------------------------------------
-  // Determine insertion point of new RAM entry, hostRamEntryThis.  The possibilities are:
-	// - New table => First entry
-	// - Existing Ram entry => Replace said entry
-	// - Existing table, new Ram entry => Last entry
-  //
-	uint8_t 	bReplaceEntry=0;
-	uint32_t	headerNext=0;
-	uint32_t	instrNext=0;
-	
-	bReplaceEntry = 0;
-  if (bNewTable)  {
-    // Append to beginning of agreed upon static Ram table position for this coreId.
-    bEntryEnd = 1;
-	  ramEntryThis.header = ( ((uint32_t)bEntryEnd)  << RAM_HEADER_END_START_C    & RAM_HEADER_END_MASK_C )    |
-														ramEntryThis.header;
-    hostRamEntryThis = hostRamTableThis;
-    if (i_modeBuild==P8_SLW_MODEBUILD_SRAM)  {
-      // Update RAM vector (since it is currently NULL)
-      *((uint64_t*)hostRamVector + i_coreId) = 
-                           myRev64( xipSlwRamSection + SLW_RAM_TABLE_SPACE_PER_CORE*i_coreId );
-    }
-  }
-  else  {
-		// Append at end of existing Ram table for this coreId
-		//   or
-    // Replace an existing Ram entry
-    hostRamEntryNext = hostRamTableThis;
-    ramEntryNext = (RamTableEntry*)hostRamEntryNext;
-		headerNext = myRev32(ramEntryNext->header);
-		instrNext = myRev32(ramEntryNext->instr);
-    iCount = 1;
-		// Examine all entries, except last entry.
-    while ((headerNext & RAM_HEADER_END_MASK_C)==0 && bReplaceEntry==0)  {
-      if (iCount>=SLW_MAX_CPUREGS_OPS)  {
-        MY_ERR("Bad table! Header end bit not found and RAM table full (=%i entries).\n",SLW_MAX_CPUREGS_OPS);
-        return IMGBUILD_ERR_RAM_TABLE_END_NOT_FOUND;
-      }
-			if (ramEntryThis.header==headerNext && ramEntryThis.instr==instrNext)  {
-				// Its a replacement. Stop searching. Go do the replacement.
-				bReplaceEntry = 1;
-		    hostRamEntryThis = hostRamEntryNext;
-			}
-			else  {
-      	hostRamEntryNext = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY);
-      	ramEntryNext = (RamTableEntry*)hostRamEntryNext;
-				headerNext = myRev32(ramEntryNext->header);
-				instrNext = myRev32(ramEntryNext->instr);
-      	iCount++;
-			}
-    }
-		if (bReplaceEntry==0)  {
-			// Examine the last entry.
-   	 	if (headerNext & RAM_HEADER_END_MASK_C)  {
-	  		// Now we know for sure that our new Ram entry will also be the last, either as a 
-				// replace or append. So put the end bit into the new entry.
-				bEntryEnd = 1;
-			  ramEntryThis.header = ( ((uint32_t)bEntryEnd)  << RAM_HEADER_END_START_C    & RAM_HEADER_END_MASK_C )    |
-																ramEntryThis.header;
-				// Determine if to replace or append.
-				if (ramEntryThis.header==headerNext && ramEntryThis.instr==instrNext)  {
-					// Its a replacement. And it would be legal to replace the very last Ram in a completely full table.
-  	 	  	if (iCount<=SLW_MAX_CPUREGS_OPS)  {
-						bReplaceEntry = 1;
-				    hostRamEntryThis = hostRamEntryNext;
-   		  	}
-   	  		else  {
-   	    		MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS);
-   	    		return IMGBUILD_ERR_RAM_TABLE_FULL;
-	  	  	}
-				}
-				else  {
-					// Its an append. Make sure there's room for one more Ram entry.
-  	 	  	if (iCount<SLW_MAX_CPUREGS_OPS)  {
-						// Zero out the end bit in last entrys header (which will now be 2nd last).
-		     	  ramEntryNext->header = ramEntryNext->header & myRev32(~RAM_HEADER_END_MASK_C);
-				    hostRamEntryThis = (void*)((uint8_t*)hostRamEntryNext + XIPSIZE_RAM_ENTRY);
-   		  	}
-   	  		else  {
-   	    		MY_ERR("RAM table is full. Max %i entries allowed.\n",SLW_MAX_CPUREGS_OPS);
-   	    		return IMGBUILD_ERR_RAM_TABLE_FULL;
-	  	  	}
- 	    	}
-			}
- 	   	else  {
- 	   	  MY_ERR("We should never get here. Check code. Dumping data:\n");
- 	   	  MY_ERR("myRev32(ramEntryNext->header) = 0x%08x\n",myRev32(ramEntryNext->header));
- 	   	  MY_ERR("RAM_HEADER_END_MASK_C         = 0x%08x\n",RAM_HEADER_END_MASK_C);
- 	   	  return IMGBUILD_ERR_RAM_CODE;
- 	   	}
-		}
-  }
-
-
-  // Summarize new table entry data
-  MY_INF("New table entry data (host format):\n");
-  MY_INF("\theader = 0x%08x\n",ramEntryThis.header);
-  MY_INF("\tinstr  = 0x%08x\n",ramEntryThis.instr);
-  MY_INF("\tdata   = 0x%016llx\n",ramEntryThis.data);
-
-  // -------------------------------------------------------------------------
-  // Insert the new RAM entry into the table in BE format.
-  //
-  ramEntryNext = (RamTableEntry*)hostRamEntryThis;
-  // ...some redundant checking
-  if (bNewTable)  {
-    // For any new table, the insertion location should be clean. We check for this here.
-    if (myRev32(ramEntryNext->header)!=0)  {
-      MY_ERR("WARNING : Table entry location should be empty for a new table. Check code and image. Dumping data:\n");
-      MY_ERR("\theader = 0x%08x\n",myRev32(ramEntryNext->header));
-      MY_ERR("\tinstr  = 0x%08x\n",myRev32(ramEntryNext->instr));
-      MY_ERR("\tdata   = 0x%016llx\n",myRev64(ramEntryNext->data));
-      rc = IMGBUILD_WARN_RAM_TABLE_CONTAMINATION;
-    }
-  }
-	// ..insert the new Ram entry.
-  ramEntryNext->header = myRev32(ramEntryThis.header);
-  ramEntryNext->instr  = myRev32(ramEntryThis.instr);
-  ramEntryNext->data   = myRev64(ramEntryThis.data);
-
-  return rc;
-}
-
-
-/*
-// io_image -    Pointer to SLW image.
-// i_modeBuild - 0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode. 
-// i_scomAddr -  Scom address.
-// i_coreId -    The core ID [0:15].
-// i_scomData -  Data to write to scom register.
-// i_operation - What to do with the scom addr and data.
-// i_section -   0: General Scoms, 1: L2 cache, 2: L3 cache.
-*/
-uint32_t p8_pore_gen_scom_fixed(void       *io_image,
-                                uint8_t    i_modeBuild,
-                                uint32_t   i_scomAddr,
-                                uint32_t   i_coreId,     // [0:15] 
-                                uint64_t   i_scomData,
-                                uint32_t   i_operation,  // [0:7]
-                                uint32_t   i_section)    // [0,1,2]
-{
-  uint32_t  rc=0, rcLoc=0, iEntry=0;
-  uint32_t  chipletId=0;
-  uint32_t  operation=0;
-  uint32_t  entriesCount=0, entriesMatch=0, entriesNOP=0;
-  void      *hostSlwSection;
-  void      *hostSlwSectionFixed;
-  uint64_t  xipScomTableThis;
-  void      *hostScomVector, *hostScomTableThis;
-  void      *hostScomEntryNext;       // running entry pointer
-  void      *hostScomEntryMatch=NULL; // pointer to entry that matches scomAddr
-  void      *hostScomEntryRET=NULL;   // pointer to first return instr after table
-  void      *hostScomEntryNOP=NULL;   // pointer to first nop IIS
-  uint8_t   bufIIS[XIPSIZE_SCOM_ENTRY], bufNOP[4], bufRET[4];
-  SbeXipSection xipSection;
-  SbeXipItem    xipTocItem;
-  PoreInlineContext ctx;
-  
-  // -------------------------------------------------------------------------
-  // Validate Scom parameters.
-  //
-  // ...check if valid Scom register (is there anything we can do here to check?)
-  // Skipping check. We blindly trust caller.
-  //
-  // ...check mode build
-  if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE)  {
-    MY_ERR("modeBuild=%i invalid. Valid range is [0;%i].",
-      i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE);
-    rcLoc = 1;
-  }
-  // ...check Scom operation
-  if (i_operation<P8_PORE_SCOM_FIRST_OP || i_operation>P8_PORE_SCOM_LAST_OP)  {
-    MY_ERR("Scom operation = %i is not within valid range of [%d;%d]\n",
-      i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP);
-    rcLoc = 1;
-  }
-  // ...check that core ID corresponds to valid chiplet ID
-  chipletId = i_coreId + P8_CID_EX_LOW;
-  if (chipletId<P8_CID_EX_LOW || chipletId>P8_CID_EX_HIGH)  {
-    MY_ERR("Chiplet ID = 0x%02x is not within valid range of [0x%02x;0x%02x]\n",
-      chipletId, P8_CID_EX_LOW, P8_CID_EX_HIGH);
-    rcLoc = 1;
-  }
-  if (rcLoc)
-    return IMGBUILD_ERR_SCOM_INVALID_PARM;
-  rcLoc = 0;
- 
-  // -------------------------------------------------------------------------
-  // Check slw section location and size. (Mainly needed for fixed image.)
-  //
-  if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
-      i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
-    hostSlwSectionFixed = (void*)( (uintptr_t)io_image + 
-                                   FIXED_SLW_IMAGE_SIZE -
-                                   FIXED_FFDC_SECTION_SIZE -
-                                   FIXED_SLW_SECTION_SIZE );
-    // Even though we shouldn't call this api during a rebuild, it should be 
-    // safe to do so in this particular case since none of the info requested
-    // is supposed to be moved during a rebuild.
-    rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-    if (rc)  {
-      MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
-      return IMGBUILD_ERR_GET_SECTION;
-    }
-    hostSlwSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
-    if (hostSlwSectionFixed!=hostSlwSection)  {
-      MY_ERR("hostSlwSectionFixed != hostSlwSection(from image api).\n");
-      return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD;
-    }
-    else  {
-      MY_INF("hostSlwSectionFixed == hostSlwSection(from image api).\n");
-    }
-  }
-  else  {                 // SRAM non-fixed image.
-    rc = sbe_xip_get_section( io_image, SBE_XIP_SECTION_SLW, &xipSection);
-    if (rc)  {
-      MY_ERR("Probably invalid section name for SBE_XIP_SECTION_SLW.\n");
-      return IMGBUILD_ERR_GET_SECTION;
-    }
-    hostSlwSection = (void*)((uintptr_t)io_image + xipSection.iv_offset);
-  }
-
-  // -------------------------------------------------------------------------
-  // Check .slw section size and cross-check w/header define.
-  //
-  if (xipSection.iv_size!=FIXED_SLW_SECTION_SIZE)  {
-    MY_ERR("SLW table size in *.H header file (=%i) differs from SLW section size in image (=%i).\n",FIXED_SLW_SECTION_SIZE,xipSection.iv_size);
-    MY_ERR("Check code or image version.\n");
-    return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD;
-  }
-
-  // -------------------------------------------------------------------------
-  // Summarize parameters and checking results.
-  //
-  MY_INF("Input parameter checks - OK\n");
-  MY_INF("\tRegister  = 0x%08x\n",i_scomAddr);
-  MY_INF("\tOperation = %i\n",i_operation);
-  MY_INF("\tSection   = %i\n",i_section);
-  MY_INF("\tCore ID   = %i\n",i_coreId);
-  MY_INF("Image validation and size checks - OK\n");
-  MY_INF("\tSLW section size=  %i\n",xipSection.iv_size);
-  
-  // -------------------------------------------------------------------------
-  // Locate Scom vector according to i_section and then locate Scom table 
-  //   associated with "This" core ID.
-  //
-  if (i_modeBuild==P8_SLW_MODEBUILD_IPL ||
-      i_modeBuild==P8_SLW_MODEBUILD_REBUILD)  {  // Fixed image.
-    switch (i_section)  {
-    case P8_SCOM_SECTION_NC:
-      hostScomTableThis = (void*)( (uintptr_t)hostSlwSection +
-                                   SLW_RAM_TABLE_SIZE +
-                                   SLW_SCOM_TABLE_SPACE_PER_CORE_NC*i_coreId );
-      break;
-    case P8_SCOM_SECTION_L2:
-      hostScomTableThis = (void*)( (uintptr_t)hostSlwSection +
-                                   SLW_RAM_TABLE_SIZE +
-                                   SLW_SCOM_TABLE_SIZE_NC +
-                                   SLW_SCOM_TABLE_SPACE_PER_CORE_L2*i_coreId );
-      break;
-    case P8_SCOM_SECTION_L3:
-      hostScomTableThis = (void*)( (uintptr_t)hostSlwSection +
-                                   SLW_RAM_TABLE_SIZE +
-                                   SLW_SCOM_TABLE_SIZE_NC +
-                                   SLW_SCOM_TABLE_SIZE_L2 +
-                                   SLW_SCOM_TABLE_SPACE_PER_CORE_L3*i_coreId );
-      break;
-    default:
-      MY_ERR("Invalid value for i_section (=%i).\n",i_section);
-      MY_ERR("Valid values for i_section = [%i,%i,%i].\n",
-        P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3);
-      return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION;
-      break;
-    }
-  }
-  else  {                 // SRAM non-fixed image.
-    switch (i_section)  {
-    case P8_SCOM_SECTION_NC:
-      rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem);
-      if (rc)  {
-        MY_ERR("Probably invalid key word for SLW_HOST_SCOM_NC_VECTOR_TOC_NAME.\n");
-        return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-      }
-      break;
-    case P8_SCOM_SECTION_L2:
-      rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L2_VECTOR_TOC_NAME, &xipTocItem);
-      if (rc)  {
-        MY_ERR("Probably invalid key word for SLW_HOST_SCOM_L2_VECTOR_TOC_NAME.\n");
-        return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-      }
-      break;
-    case P8_SCOM_SECTION_L3:
-      rc = sbe_xip_find( io_image, SLW_HOST_SCOM_L3_VECTOR_TOC_NAME, &xipTocItem);
-      if (rc)  {
-        MY_ERR("Probably invalid key word for SLW_HOST_SCOM_L3_VECTOR_TOC_NAME.\n");
-        return IMGBUILD_ERR_KEYWORD_NOT_FOUND;
-      }
-      break;
-    default:
-      MY_ERR("Invalid value for i_section (=%i).\n",i_section);
-      MY_ERR("Valid values for i_section = [%i,%i,%i].\n",
-        P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3);
-      return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION;
-    }
-    MY_INF("xipTocItem.iv_address = 0x%016llx\n",xipTocItem.iv_address);
-    sbe_xip_pore2host( io_image, xipTocItem.iv_address, &hostScomVector);
-    MY_INF("hostScomVector = 0x%016llx\n",(uint64_t)hostScomVector);
-    xipScomTableThis = myRev64(*((uint64_t*)hostScomVector + i_coreId));
-    MY_INF("xipScomTableThis = 0x%016llx\n",xipScomTableThis);
-    if (xipScomTableThis)  {
-      sbe_xip_pore2host( io_image, xipScomTableThis, &hostScomTableThis);
-    }
-    else  {  // Should never be here.
-      MY_ERR("Code or image bug. Scom vector table entries should never be null.\n");
-      return IMGBUILD_ERR_CHECK_CODE;
-    }
-  }
-
-  //
-  // Determine where to place/do Scom action and if entry already exists.
-  // Insertion rules:
-  // - If entry doesn't exist, insert at first NOP. (Note that if you don't do
-  //   this, then the table might potentially overflow since the max table size
-  //   doesn't include NOP entries.)
-  // - If no NOP found, insert at first RET.
-  //
-  
-  //----------------------------------------------------------------------------
-  // 1. Create search strings for addr, nop and ret.
-  //----------------------------------------------------------------------------
-  // Note, the following IIS will also be used in case of
-  // - i_operation==append
-  // - i_operation==replace
-  pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0);
-  pore_LS( &ctx, P1, chipletId);
-  pore_STI( &ctx, i_scomAddr, P1, i_scomData);
-  if (ctx.error  > 0)  {
-    MY_ERR("pore_LS or _STI generated rc = %d", ctx.error);
-    return IMGBUILD_ERR_PORE_INLINE_ASM;
-  }
-  pore_inline_context_create( &ctx, (void*)bufRET, 4, 0, 0);
-  pore_RET( &ctx);
-  if (ctx.error > 0)  {
-    MY_ERR("pore_RET generated rc = %d", ctx.error);
-    return IMGBUILD_ERR_PORE_INLINE_ASM;
-  }
-  pore_inline_context_create( &ctx, (void*)bufNOP, 4, 0, 0);
-  pore_NOP( &ctx);
-  if (ctx.error > 0)  {
-    MY_ERR("pore_NOP generated rc = %d", ctx.error);
-    return IMGBUILD_ERR_PORE_INLINE_ASM;
-  }
-  
-  //----------------------------------------------------------------------------
-  // 2. Search for addr and nop in relevant coreId table until first RET.
-  //----------------------------------------------------------------------------
-  // Note:
-  // - We go through ALL entries until first RET instr. We MUST find a RET instr,
-  //   though we don't check for overrun until later. (Could be improved.)
-  // - Count number of entries, incl the NOOPs, until we find an RET.
-  // - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry.
-  // - For an append operation, if a NOP is found (before a RET obviously), the 
-  //   SCOM is replacing that NNNN sequence.
-  hostScomEntryNext = hostScomTableThis;
-  MY_INF("hostScomEntryNext (addr): 0x%016llx\n ",(uint64_t)hostScomEntryNext);
-  while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t)))  {
-    entriesCount++;
-    MY_INF("Number of SCOM entries: %i\n ",entriesCount);
-    if (*((uint32_t*)bufIIS+1)==*((uint32_t*)hostScomEntryNext+1) && entriesMatch==0)  {// +1 skips 1st word in Scom entry (which loads the PC in an LS operation.)
-      hostScomEntryMatch = hostScomEntryNext;
-      entriesMatch++;
-    }
-    if (memcmp(hostScomEntryNext, bufNOP, sizeof(uint32_t))==0 && entriesNOP==0)  {
-      hostScomEntryNOP = hostScomEntryNext;
-      entriesNOP++;
-    }
-    hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY);
-  }
-  hostScomEntryRET = hostScomEntryNext; // The last EntryNext is always the first RET.
-  
-  //----------------------------------------------------------------------------
-  // 3. Qualify (translate) operation and IIS.
-  //----------------------------------------------------------------------------
-  if (i_operation==P8_PORE_SCOM_APPEND)  
-  {
-    operation = i_operation;
-  }
-  else if (i_operation==P8_PORE_SCOM_REPLACE)  
-  {
-    if (hostScomEntryMatch)
-      // ... do a replace
-      operation = i_operation;
-    else
-      // ... do an append
-      operation = P8_PORE_SCOM_APPEND;
-  }
-  else if (i_operation==P8_PORE_SCOM_NOOP)  
-  {
-    // ...overwrite earlier bufIIS from the search step
-    pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0);
-    pore_NOP( &ctx);
-    pore_NOP( &ctx);
-    pore_NOP( &ctx);
-    pore_NOP( &ctx);
-    if (ctx.error > 0)  {
-      MY_ERR("*** _NOP generated rc = %d", ctx.error);
-      return IMGBUILD_ERR_PORE_INLINE_ASM;
-    }
-    operation = i_operation;
-  }
-  else if ( i_operation==P8_PORE_SCOM_AND        ||
-            i_operation==P8_PORE_SCOM_OR )  
-  {
-    operation = i_operation;
-  }            
-  else if ( i_operation==P8_PORE_SCOM_AND_APPEND )  
-  {
-    if (hostScomEntryMatch)
-      // ... do the AND on existing Scom
-      operation = P8_PORE_SCOM_AND;
-    else
-      // ... do an append (this better be to an _AND register type)
-      operation = P8_PORE_SCOM_APPEND;  
-  }
-  else if ( i_operation==P8_PORE_SCOM_OR_APPEND )  
-  {
-    if (hostScomEntryMatch)
-      // ... do the OR on existing Scom
-      operation = P8_PORE_SCOM_OR;
-    else
-      // ... do an append (this better be to an _OR register type)
-      operation = P8_PORE_SCOM_APPEND;  
-  }
-  else if (i_operation==P8_PORE_SCOM_RESET)  
-  {
-    // ... create RNNN instruction sequence.
-    pore_inline_context_create( &ctx, (void*)bufIIS, XIPSIZE_SCOM_ENTRY, 0, 0);
-    pore_RET( &ctx);
-    pore_NOP( &ctx);
-    pore_NOP( &ctx);
-    pore_NOP( &ctx);
-    if (ctx.error > 0)  {
-      MY_ERR("***_RET or _NOP generated rc = %d", ctx.error);
-      return IMGBUILD_ERR_PORE_INLINE_ASM;
-    }
-    operation = i_operation;
-  }
-  else  
-  {
-    MY_ERR("Scom operation = %i is not within valid range of [%d;%d]\n",
-      i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP);
-    return IMGBUILD_ERR_SCOM_INVALID_PARM;
-  }
-  
-  //----------------------------------------------------------------------------
-  // 4. Check for overrun.
-  //----------------------------------------------------------------------------
-  // Note:
-  // - An entry count exceeding the max allocated entry count will result in a code error
-  //   because the allocation is based on an agreed upon max number of entries and 
-  //   therefore either the code header file needs to change or the caller is not abiding 
-  //   by the rules.
-  // - An entry count equalling the max allocated entry count is allowed for all commands
-  //   except the APPEND command, incl the translated REPLACE->APPEND, which will result 
-  //   in the previously mentioned code error being returned.
-  // - The table can be full but still include NOOPs. If so, we can still APPEND since
-  //   we append at first occurrance of a NOOP or at the end of the table (at the RET).
-  switch (i_section)  {
-  case P8_SCOM_SECTION_NC:
-    if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_NC) &&
-           hostScomEntryNOP==NULL ) ||
-           entriesCount>SLW_MAX_SCOMS_NC )
-    {
-      MY_ERR("SCOM table NC is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_NC);
-      return IMGBUILD_ERR_CHECK_CODE;
-    }
-    break;
-  case P8_SCOM_SECTION_L2:
-    if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_L2) &&
-           hostScomEntryNOP==NULL ) ||
-           entriesCount>SLW_MAX_SCOMS_L2 )
-    {
-      MY_ERR("SCOM table L2 is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_L2);
-      return IMGBUILD_ERR_CHECK_CODE;
-    }
-    break;
-  case P8_SCOM_SECTION_L3:
-    if ( ( (operation==P8_PORE_SCOM_APPEND && entriesCount==SLW_MAX_SCOMS_L3) &&
-           hostScomEntryNOP==NULL ) ||
-           entriesCount>SLW_MAX_SCOMS_L3 )
-    {
-      MY_ERR("SCOM table L3 is full. Max %i entries allowed.\n",SLW_MAX_SCOMS_L3);
-      return IMGBUILD_ERR_CHECK_CODE;
-    }
-    break;
-  default:
-    MY_ERR("Invalid value for i_section (=%i).\n",i_section);
-    MY_ERR("Valid values for i_section = [%i,%i,%i].\n",
-        P8_SCOM_SECTION_NC,P8_SCOM_SECTION_L2,P8_SCOM_SECTION_L3);
-    return IMGBUILD_ERR_SCOM_INVALID_SUBSECTION;
-  }
-
-
-  // ---------------------------------------------------------------------------
-  // 5.  Insert the SCOM.
-  // ---------------------------------------------------------------------------
-  // Assuming pre-allocated Scom table (after pre-allocated Ram table):
-  // - Table is pre-filled with RNNN ISS.
-  // - Each core Id has dedicated space, uniformly distributed by SLW_MAX_SCOMS_NC*
-  //   XIPSIZE_SCOM_ENTRY.
-  // - Remember to check for more than SLW_MAX_SCOMS_NC entries!
-  switch (operation)  {
-
-  case P8_PORE_SCOM_APPEND:  // Append a Scom at first occurring NNNN or RNNN,  
-    if (hostScomEntryNOP)  {
-      // ... replace the NNNN
-      MY_INF("Append at NOP\n");
-      memcpy(hostScomEntryNOP,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
-    }
-    else if (hostScomEntryRET)  {
-      // ... replace the RNNN
-      MY_INF("Append at RET\n");
-      memcpy(hostScomEntryRET,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
-    }
-    else  {
-      // We should never be here.
-      MY_ERR("In case=_SCOM_APPEND: EntryRET=NULL is impossible. Check code.\n");
-      return IMGBUILD_ERR_CHECK_CODE;
-    }
-    break;
-  case P8_PORE_SCOM_REPLACE: // Replace existing Scom with new data
-    if (hostScomEntryMatch)  {
-      // ... do a vanilla replace
-      MY_INF("Replace existing Scom\n");
-      memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
-    }
-    else  {
-      // We should never be here.
-      MY_ERR("In case=_SCOM_REPLACE: EntryMatch=NULL is impossible. Check code.\n");
-      return IMGBUILD_ERR_CHECK_CODE;
-    }
-    break;
-  case P8_PORE_SCOM_NOOP:
-    if (hostScomEntryMatch)  {
-      // ... do a vanilla replace
-      MY_INF("Replace existing Scom w/NOPs\n");
-      memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY);
-    }
-    else  {
-      MY_ERR("No Scom entry found to replace NOOPs with.\n");
-      return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
-    }
-    break;
-  case P8_PORE_SCOM_OR:      // Overlay Scom data onto existing data by bitwise OR
-    if (hostScomEntryMatch)  {
-      // ... do an OR on the data (which is the 2nd DWord in the entry)
-      MY_INF("Overlay existing Scom - OR case\n");
-      *((uint64_t*)hostScomEntryMatch+1) = 
-        *((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData);
-    }
-    else  { 
-      MY_ERR("No Scom entry found to do OR operation with.\n");
-      return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
-    }
-    break;
-  case P8_PORE_SCOM_AND:     // Overlay Scom data onto existing data by bitwise AND
-    if (hostScomEntryMatch)  {
-      // ... do an AND on the data (which is the 2nd DWord in the entry)
-      MY_INF("Overlay existing Scom - AND case\n");
-      *((uint64_t*)hostScomEntryMatch+1) = 
-        *((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData);
-    }
-    else  { 
-      MY_ERR("No Scom entry found to do AND operation with.\n");
-      return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND;
-    }
-    break;
-  case P8_PORE_SCOM_RESET:   // Reset (delete) table. Refill w/RNNN ISS.
-    MY_INF("Reset table\n");
-    hostScomEntryNext = hostScomTableThis;
-    for ( iEntry=0; iEntry<entriesCount; iEntry++)  {
-      memcpy( hostScomEntryNext, (void*)bufIIS, XIPSIZE_SCOM_ENTRY);
-      hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY);
-    }
-    break;
-  default:
-    MY_ERR("Impossible value of operation (=%i). Check code.\n",operation);
-    return IMGBUILD_ERR_CHECK_CODE;
-  
-  }  // End of switch(operation)
-
-  return rc;
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c
deleted file mode 100644
index d6c35b880..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_static_data.c $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-// $Id: p8_pore_table_static_data.c,v 1.7 2013-05-23 21:10:38 dcrowell Exp $
-/*------------------------------------------------------------------------------*/
-/* *! (C) Copyright International Business Machines Corp. 2012                  */
-/* *! All Rights Reserved -- Property of IBM                                    */
-/* *! ***  ***                                                  */
-/*------------------------------------------------------------------------------*/
-/* *! TITLE :       p8_pore_table_static_data                                   */
-/* *! DESCRIPTION : Global static data declaration file.                        */
-/* *! OWNER NAME :  Michael Olsen            Email: cmolsen@us.ibm.com          */
-//
-/* *! COMMENTS :    This file is exclusively for PHYP environment.              */
-//
-/*------------------------------------------------------------------------------*/
-#include <p8_pore_table_gen_api.H>
-
-const SlwSprRegs SLW_SPR_REGS[] = {  
-  /*    name               value                    swizzled     */
-  // ...core regs
-  { "P8_SPR_HRMOR",    P8_SPR_HRMOR, ( P8_SPR_HRMOR >>5 | ( P8_SPR_HRMOR &0x1f)<<5 ) },
-  { "P8_SPR_HMEER",    P8_SPR_HMEER, ( P8_SPR_HMEER >>5 | ( P8_SPR_HMEER &0x1f)<<5 ) },
-  { "P8_SPR_PMICR",    P8_SPR_PMICR, ( P8_SPR_PMICR >>5 | ( P8_SPR_PMICR &0x1f)<<5 ) },
-  { "P8_SPR_PMCR",     P8_SPR_PMCR,  ( P8_SPR_PMCR  >>5 | ( P8_SPR_PMCR  &0x1f)<<5 ) },
-  { "P8_SPR_HID0",     P8_SPR_HID0,  ( P8_SPR_HID0  >>5 | ( P8_SPR_HID0  &0x1f)<<5 ) },
-  { "P8_SPR_HID1",     P8_SPR_HID1,  ( P8_SPR_HID1  >>5 | ( P8_SPR_HID1  &0x1f)<<5 ) },
-  { "P8_SPR_HID4",     P8_SPR_HID4,  ( P8_SPR_HID4  >>5 | ( P8_SPR_HID4  &0x1f)<<5 ) },
-  { "P8_SPR_HID5",     P8_SPR_HID5,  ( P8_SPR_HID5  >>5 | ( P8_SPR_HID5  &0x1f)<<5 ) },
-  { "P8_CORE_XTRA8",   P8_CORE_XTRA8,(            P8_CORE_XTRA8                    ) },
-  { "P8_CORE_XTRA9",   P8_CORE_XTRA9,(            P8_CORE_XTRA9                    ) },
-  // ...thread regs
-  { "P8_SPR_HSPRG0",   P8_SPR_HSPRG0,( P8_SPR_HSPRG0>>5 | ( P8_SPR_HSPRG0&0x1f)<<5 ) },
-  { "P8_SPR_LPCR",     P8_SPR_LPCR,  ( P8_SPR_LPCR  >>5 | ( P8_SPR_LPCR  &0x1f)<<5 ) },
-  { "P8_MSR_MSR",      P8_MSR_MSR,   (            P8_MSR_MSR                       ) },
-  { "P8_THRD_XTRA3",   P8_THRD_XTRA3,(            P8_THRD_XTRA3                    ) },
-  { "P8_THRD_XTRA4",   P8_THRD_XTRA4,(            P8_THRD_XTRA4                    ) },
-};
-
-const int SLW_SPR_REGS_SIZE = sizeof(SLW_SPR_REGS)/sizeof(SLW_SPR_REGS[0]);
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.H
deleted file mode 100644
index ac530366e..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.H
+++ /dev/null
@@ -1,71 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_ring_identification.H,v 1.7 2013/02/12 17:33:12 cmolsen Exp $
-/*------------------------------------------------------------------------------*/
-/* *! (C) Copyright International Business Machines Corp. 2012                  */
-/* *! All Rights Reserved -- Property of IBM                                    */
-/* *! ***  ***                                                  */
-/*------------------------------------------------------------------------------*/
-/* *! TITLE :       p8_ring_identification                                      */
-/* *! DESCRIPTION : Include file for global static #G & #R ringID vs ringName.  */
-/* *! OWNER NAME :  Michael Olsen            Email: cmolsen@us.ibm.com          */
-//
-/*------------------------------------------------------------------------------*/
-#include <p8_pore_api_custom.h>
-#include <string.h> // Why isn't this included in p8_pore_api_custom.h? PHYP
-                    //   said back in Aug that strcmp() is allowed. But it is
-                    //   not in p8_pore_api_custom.h.
-
-// Ring ID list structure.
-typedef struct {
-  const char  *ringName;
-  uint8_t     ringId;
-  uint8_t     chipIdMin;    // the min chipletId
-  uint8_t     chipIdMax;    // the max chipletId
-  const char  *ringNameImg; // Ring name in image: ringName + "_ring"
-  uint8_t     vpdKeyword;
-  uint8_t      bWcSpace;     // 0: fitted  1: worst-case space (3 x ring length)
-} RingIdList;
-
-extern const RingIdList  RING_ID_LIST_PG[], RING_ID_LIST_PR[];
-extern const uint32_t    RING_ID_LIST_PG_SIZE, RING_ID_LIST_PR_SIZE;
-extern const RingIdList  RING_ID_LIST[];
-extern const uint32_t    RING_ID_LIST_SIZE;
-
-// Enumerated VPD keyword values.
-// Note! This is DIFFERENT from the MvpdKeyword list in fapiMvpdAccess.H which
-//       can't be used in this file since it's not, per se, a fapi file. So
-//       these values need to be translated in xip_customize when passing the
-//       mvpdKeyword to getMvpdRing();
-enum VpdKeyword  {
-  VPD_KEYWORD_PDG,
-  VPD_KEYWORD_PDR,
-  NUM_OF_VPD_TYPES
-};
-
-int get_vpd_ring_list_entry(const char *i_ringName,
-                            const uint8_t i_ringId,
-                            RingIdList **i_ringIdList);
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c
deleted file mode 100644
index fc5a31f7c..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c
+++ /dev/null
@@ -1,154 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_ring_identification.c $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_ring_identification.c,v 1.18 2013/02/12 23:30:07 cmolsen Exp $
-/*------------------------------------------------------------------------------*/
-/* *! (C) Copyright International Business Machines Corp. 2012                  */
-/* *! All Rights Reserved -- Property of IBM                                    */
-/* *! ***  ***                                                  */
-/*------------------------------------------------------------------------------*/
-/* *! TITLE :       p8_ring_identification                                      */
-/* *! DESCRIPTION : Global static #G & #R ringID vs ringName.                   */
-/* *! OWNER NAME :  Michael Olsen            Email: cmolsen@us.ibm.com          */
-//
-/*------------------------------------------------------------------------------*/
-#include <p8_ring_identification.H>
-
-const RingIdList RING_ID_LIST_PG[] = {
-  /* ringName       ringId  chipletId    ringNameImg            mvpdKeyword    wc */
-  /*                        min   max                                               */
-  {"ab_gptr_ab",     0xA0, 0x08, 0x08, "ab_gptr_ab_ring",     VPD_KEYWORD_PDG, 0},
-  {"ab_gptr_ioa",    0xA1, 0x08, 0x08, "ab_gptr_ioa_ring",    VPD_KEYWORD_PDG, 0},
-  {"ab_gptr_perv",   0xA2, 0x08, 0x08, "ab_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},
-  {"ab_gptr_pll",    0xA3, 0x08, 0x08, "ab_gptr_pll_ring",    VPD_KEYWORD_PDG, 0},
-  {"ab_time",        0xA4, 0x08, 0x08, "ab_time_ring",        VPD_KEYWORD_PDG, 0},
-  {"ex_gptr_core",   0xA5, 0xFF, 0xFF, "ex_gptr_core_ring",   VPD_KEYWORD_PDG, 0},   //Chip specific
-  {"ex_gptr_dpll",   0xA6, 0xFF, 0xFF, "ex_gptr_dpll_ring",   VPD_KEYWORD_PDG, 0},   //Chip specific
-  {"ex_gptr_l2",     0xA7, 0xFF, 0xFF, "ex_gptr_l2_ring",     VPD_KEYWORD_PDG, 0},     //Chip specific
-  {"ex_gptr_l3",     0xA8, 0xFF, 0xFF, "ex_gptr_l3_ring",     VPD_KEYWORD_PDG, 0},     //Chip specific
-  {"ex_gptr_l3refr", 0xA9, 0xFF, 0xFF, "ex_gptr_l3refr_ring", VPD_KEYWORD_PDG, 0}, //Chip specific
-  {"ex_gptr_perv",   0xAA, 0xFF, 0xFF, "ex_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},   //Chip specific
-  {"ex_time_core",   0xAB, 0x10, 0x1F, "ex_time_core_ring",   VPD_KEYWORD_PDG, 0},   //Chiplet specfc
-  {"ex_time_eco",    0xAC, 0x10, 0x1F, "ex_time_eco_ring",    VPD_KEYWORD_PDG, 0},    //Chiplet specfc
-  {"pb_gptr_dmipll", 0xAD, 0x02, 0x02, "pb_gptr_dmipll_ring", VPD_KEYWORD_PDG, 0},
-  {"pb_gptr_mcr",    0xAE, 0x02, 0x02, "pb_gptr_mcr_ring",    VPD_KEYWORD_PDG, 0},
-  {"pb_gptr_nest",   0xAF, 0x02, 0x02, "pb_gptr_nest_ring",   VPD_KEYWORD_PDG, 0},
-  {"pb_gptr_nx",     0xB0, 0x02, 0x02, "pb_gptr_nx_ring",     VPD_KEYWORD_PDG, 0},
-  {"pb_gptr_pcis",   0xB1, 0x02, 0x02, "pb_gptr_pcis_ring",   VPD_KEYWORD_PDG, 0},
-  {"pb_gptr_perv",   0xB2, 0x02, 0x02, "pb_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},
-  {"pb_time",        0xB3, 0x02, 0x02, "pb_time_ring",        VPD_KEYWORD_PDG, 0},
-  {"pb_time_mcr",    0xB4, 0x02, 0x02, "pb_time_mcr_ring",    VPD_KEYWORD_PDG, 0},
-  {"pb_time_nx",     0xB5, 0x02, 0x02, "pb_time_nx_ring",     VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_iopci", 0xB6, 0x09, 0x09, "pci_gptr_iopci_ring", VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_pbf",   0xB7, 0x09, 0x09, "pci_gptr_pbf_ring",   VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_pci0",  0xB8, 0x09, 0x09, "pci_gptr_pci0_ring",  VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_pci1",  0xB9, 0x09, 0x09, "pci_gptr_pci1_ring",  VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_pci2",  0xBA, 0x09, 0x09, "pci_gptr_pci2_ring",  VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_perv",  0xBB, 0x09, 0x09, "pci_gptr_perv_ring",  VPD_KEYWORD_PDG, 0},
-  {"pci_gptr_pll",   0xBC, 0x09, 0x09, "pci_gptr_pll_ring",   VPD_KEYWORD_PDG, 0},
-  {"pci_time",       0xBD, 0x09, 0x09, "pci_time_ring",       VPD_KEYWORD_PDG, 0},
-  {"perv_gptr_net",  0xBE, 0x00, 0x00, "perv_gptr_net_ring",  VPD_KEYWORD_PDG, 0},
-  {"perv_gptr_occ",  0xBF, 0x00, 0x00, "perv_gptr_occ_ring",  VPD_KEYWORD_PDG, 0},
-  {"perv_gptr_perv", 0xC0, 0x00, 0x00, "perv_gptr_perv_ring", VPD_KEYWORD_PDG, 0},
-  {"perv_gptr_pib",  0xC1, 0x00, 0x00, "perv_gptr_pib_ring",  VPD_KEYWORD_PDG, 0},
-  {"perv_gptr_pll",  0xC2, 0x00, 0x00, "perv_gptr_pll_ring",  VPD_KEYWORD_PDG, 0},
-  {"perv_time",      0xC3, 0x00, 0x00, "perv_time_ring",      VPD_KEYWORD_PDG, 0},
-  {"xb_gptr_iopci",  0xC4, 0x04, 0x04, "xb_gptr_iopci_ring",  VPD_KEYWORD_PDG, 0},
-  {"xb_gptr_iox",    0xC5, 0x04, 0x04, "xb_gptr_iox_ring",    VPD_KEYWORD_PDG, 0},
-  {"xb_gptr_pben",   0xC6, 0x04, 0x04, "xb_gptr_pben_ring",   VPD_KEYWORD_PDG, 0},
-  {"xb_gptr_perv",   0xC7, 0x04, 0x04, "xb_gptr_perv_ring",   VPD_KEYWORD_PDG, 0},
-  {"xb_time",        0xC8, 0x04, 0x04, "xb_time_ring",        VPD_KEYWORD_PDG, 0},
-  {"pb_gptr_mcl",    0xC9, 0x02, 0x02, "pb_gptr_mcl_ring",    VPD_KEYWORD_PDG, 0},
-  {"pb_time_mcl",    0xCA, 0x02, 0x02, "pb_time_mcl_ring",    VPD_KEYWORD_PDG, 0},
-};
-
-const RingIdList RING_ID_LIST_PR[] = {
-  /*   ringName      ringId chipIdMin chipIdMax     ringNameImg        mvpdKeyword   */
-  {"ab_repr",        0xE0, 0x08, 0x08, "ab_repr_ring",        VPD_KEYWORD_PDR, 0},
-  {"ex_repr_core",   0xE1, 0x10, 0x1F, "ex_repr_core_ring",   VPD_KEYWORD_PDR, 1},
-  {"ex_repr_eco",    0xE2, 0x10, 0x1F, "ex_repr_eco_ring",    VPD_KEYWORD_PDR, 1},
-  {"pb_repr",        0xE3, 0x02, 0x02, "pb_repr_ring",        VPD_KEYWORD_PDR, 0},
-  {"pb_repr_mcr",    0xE4, 0x02, 0x02, "pb_repr_mcr_ring",    VPD_KEYWORD_PDR, 0},
-  {"pb_repr_nx",     0xE5, 0x02, 0x02, "pb_repr_nx_ring",     VPD_KEYWORD_PDR, 0},
-  {"pci_repr",       0xE6, 0x09, 0x09, "pci_repr_ring",       VPD_KEYWORD_PDR, 0},
-  {"perv_repr",      0xE7, 0x00, 0x00, "perv_repr_ring",      VPD_KEYWORD_PDR, 0},
-  {"perv_repr_net",  0xE8, 0x00, 0x00, "perv_repr_net_ring",  VPD_KEYWORD_PDR, 0},
-  {"perv_repr_pib",  0xE9, 0x00, 0x00, "perv_repr_pib_ring",  VPD_KEYWORD_PDR, 0},
-  {"xb_repr",        0xEA, 0x04, 0x04, "xb_repr_ring",        VPD_KEYWORD_PDR, 0},
-  {"pb_repr_mcl",    0xEB, 0x02, 0x02, "pb_repr_mcl_ring",    VPD_KEYWORD_PDR, 0},
-};
-
-const uint32_t RING_ID_LIST_PG_SIZE = sizeof(RING_ID_LIST_PG)/sizeof(RING_ID_LIST_PG[0]);
-const uint32_t RING_ID_LIST_PR_SIZE = sizeof(RING_ID_LIST_PR)/sizeof(RING_ID_LIST_PR[0]);
-
-// get_vpd_ring_list_entry() retrieves the MVPD list entry based on either a ringName
-//   or a ringId.  If both are supplied, only the ringName is used. If ringName==NULL,
-//   then the ringId is used. A pointer to the RingIdList is returned.
-int get_vpd_ring_list_entry(const char *i_ringName, 
-                            const uint8_t i_ringId, 
-                            RingIdList **i_ringIdList)
-{
-  int rc=0, NOT_FOUND=1, FOUND=0;
-  uint8_t iVpdType;
-  uint8_t iRing;
-  RingIdList *ring_id_list=NULL;
-  uint8_t ring_id_list_size;
-
-  rc = NOT_FOUND;
-  for (iVpdType=0; iVpdType<NUM_OF_VPD_TYPES; iVpdType++)  {
-    if (iVpdType==0)  {
-      ring_id_list = (RingIdList*)RING_ID_LIST_PG;
-      ring_id_list_size = (uint32_t)RING_ID_LIST_PG_SIZE;
-    }
-    else  {
-      ring_id_list = (RingIdList*)RING_ID_LIST_PR;
-      ring_id_list_size = (uint32_t)RING_ID_LIST_PR_SIZE;
-    }
-    // Search the MVPD reference lists for either a:
-		// - ringName match with or w/o _image in the name, or
-		// - ringId match.
-    if (i_ringName)  {
-			// Search for ringName match.
-      for (iRing=0; iRing<ring_id_list_size; iRing++)  {
-        if ( strcmp((ring_id_list+iRing)->ringName,   i_ringName)==0  ||
-             strcmp((ring_id_list+iRing)->ringNameImg,i_ringName)==0 )  {
-          *i_ringIdList = ring_id_list+iRing;
-          return FOUND;
-        }
-      }
-    }
-   	else  {  
-			// Search for ringId match (since ringName was not supplied).
-      for (iRing=0; iRing<ring_id_list_size; iRing++)  {
-        if ((ring_id_list+iRing)->ringId==i_ringId)  {
-          *i_ringIdList = ring_id_list+iRing;
-          return FOUND;
-        }
-      }
-    }
-
-  }
-  return rc;
-}
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.C
deleted file mode 100644
index d419e4010..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.C
+++ /dev/null
@@ -1,745 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scan_compression.C,v 1.7 2013/05/30 00:33:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/p8_scan_compression.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Bishop Brock  Email: Bishop Brock; bcbrock@us.ibm.com
-// *!
-// *! General Description:
-// *! 
-// *!     See below.
-//------------------------------------------------------------------------------
-//
-// Note: This file was originally named p8_scan_compression.c; See CVS archive
-// for revision history of p8_scan_compression.c.
-
-/// \file p8_scan_compression.C
-/// \brief APIs related to scan chain compression. 
-///
-/// RS4 Compression Format
-/// ======================
-///
-/// Scan strings are compressed using a simple run-length encoding called
-/// RS4. The string to be decompressed and scanned is the difference between
-/// the current state of the ring and the desired final state of the ring.  A
-/// run-time optimization supports the case that the current state of the ring
-/// is the flush state.
-///
-/// Both the data to be compressed and the final compressed data are treated
-/// as strings of 4-bit nibbles. When packaged in the scan data structure
-/// however the compressed string must begin on an 8-byte boundary and is
-/// always read 8 bytes at a time.  In the scan data structure the compressed
-/// strings are also padded with 0x0 nibbles to the next even multiple of 8
-/// bytes. The compressed string consists of control nibbles and data nibbles.
-/// The string format includes a special control/data sequence that marks the
-/// end of the string and the final bits of scan data.
-///
-/// Runs of 0x0 nibbles (rotates) are encoded using a simple variable-length
-/// integer encoding known as a "stop code".  This code treats each nibble in
-/// a variable-length integer encoding as an octal digit (the low-order 3
-/// bits) plus a stop bit (the high-order bit).  The examples below
-/// illustrate the encoding.
-///
-///     1xxx            - Rotate 0bxxx       nibbles (0 - 7)
-///     0xxx 1yyy       - Rotate 0bxxxyyy    nibbles (8 - 63)
-///     0xxx 0yyy 1zzz  - Rotate 0bxxxyyyzzz nibbles (64 - 511)
-///     etc.
-///
-/// A 0-length rotate (code 0b1000) is needed to resynchronize the state
-/// machine in the event of long scans (see below), or a string that begins
-/// with a non-0x0 nibble.
-///
-/// Runs of non-0x0 nibbles (scans) are inserted verbatim into the compressed
-/// string after a control nibble indicating the number of nibbles of
-/// uncompressed data.  If a run is longer than 15 nibbles, the compression
-/// algorithm must insert a 0-length rotate and a new scan-length control
-/// before continuing with the non-0 data nibbles.
-///
-///     xxxx - Scan 0bxxxx nibbles which follow, 0bxxxx != 0
-///
-/// The special case of a 0b0000 code where a scan count is expected marks the
-/// end of the string.  The end of string marker is always followed by a
-/// nibble that contains the terminal bit count in the range 0-3.  If the
-/// length of the original binary string was not an even multiple of 4, then a
-/// final nibble contains the final scan data left justified.
-///
-///     0000 00nn [ttt0] - Terminate 0bnn bits, data 0bttt0 if 0bnn != 0
-///
-///
-/// BNF Grammar
-/// ===========
-///
-/// Following is a BNF grammar for the strings accepted by the RS4
-/// decompression and scan algorithm. At a high level, the state machine
-/// recognizes a series of 1 or more sequences of a rotate (R) followed by a
-/// scan (S) or end-of-string marker (E), followed by the terminal count (T)
-/// and optional terminal data (D).
-///
-///     (R S)* (R E) T D?
-///
-/// \code
-/// 
-/// <rs4_string>        ::= <rotate> <terminate> |
-///                         <rotate> <scan> <rs4_string>
-/// 
-/// <rotate>            ::= <octal_stop> |
-///                         <octal_go> <rotate>
-/// 
-/// <octal_go>          ::= '0x0' | ... | '0x7'
-/// 
-/// <octal_stop>        ::= '0x8' | ... | '0xf'
-/// 
-/// <scan>              ::= <scan_count(N)> <data(N)>
-/// 
-/// <scan_count(N)>     ::= * 0bnnnn, for N = 0bnnnn, N != 0 *
-/// 
-/// <data(N)>           ::= * N nibbles of uncompressed data *
-/// 
-/// <terminate>         ::= '0x0' <terminal_count(0)> |
-///                         '0x0' <terminal_count(T, T > 0)> <terminal_data(T)>
-/// 
-/// <terminal_count(T)> ::= * 0b00nn, for T = 0bnn *
-/// 
-/// <terminal_data(1)>  ::= '0x0' | '0x8'
-///
-/// <terminal_data(2)>  ::= '0x0' | '0x4' | '0x8' | '0xc'
-///
-/// <terminal_data(3)>  ::= '0x0' | '0x2' | '0x4' | ... | '0xe'
-/// 
-/// \endcode
-
-
-#include <stdlib.h>
-#include <string.h>
-#include "p8_scan_compression.H"
-
-// Diagnostic aids for debugging
-#ifdef DEBUG_P8_SCAN_COMPRESSION
-
-#ifdef __FAPI
-
-#include "fapi.H"
-#define fprintf(stream, ...) FAPI_ERR(__VA_ARGS__)
-#define BUG_NEWLINE ""
-
-#else // __FAPI
-
-#include <stdio.h>
-#define BUG_NEWLINE "\n"
-
-#endif // __FAPI
-
-#define BUG(rc)                                                 \
-    ({                                                          \
-        fprintf(stderr,"%s:%d : Trapped rc = %d" BUG_NEWLINE,   \
-                __FILE__, __LINE__, (rc));                      \
-        (rc);                                                   \
-    })
-
-#define BUGX(rc, ...)                           \
-    ({                                          \
-        BUG(rc);                                \
-        fprintf(stderr, ##__VA_ARGS__);         \
-        (rc);                                   \
-    })
-
-#else // DEBUG_P8_SCAN_COMPRESSION
-
-#define BUG(rc) (rc)
-#define BUGX(rc, ...) (rc)
-
-#endif  // DEBUG_P8_SCAN_COMPRESSION
-
-// Note: PHYP requires that all subroutines, _even static subroutines_, have
-// unique names to support concurrent update.  Most routines defined here have
-// some variant of 'rs4' in their names; others should be inherently unique.
-
-// Note: For maximum flexibility we provide private versions of
-// endian-conversion routines rather than counting on a system-specific header
-// to provide these.
-
-// Byte-reverse a 32-bit integer if on a little-endian machine
-
-static uint32_t
-rs4_revle32(const uint32_t i_x)
-{
-    uint32_t rx;
-
-#ifndef _BIG_ENDIAN
-    uint8_t *pix = (uint8_t*)(&i_x);
-    uint8_t *prx = (uint8_t*)(&rx);
-
-    prx[0] = pix[3];
-    prx[1] = pix[2];
-    prx[2] = pix[1];
-    prx[3] = pix[0];
-#else
-    rx = i_x;
-#endif
-    return rx;
-}
-        
-
-#if COMPRESSED_SCAN_DATA_VERSION != 1
-#error This code assumes CompressedScanData structure version 1 layout
-#endif
-
-void
-compressed_scan_data_translate(CompressedScanData* o_data,
-                               CompressedScanData* i_data)
-{
-    o_data->iv_magic             = rs4_revle32(i_data->iv_magic);
-    o_data->iv_size              = rs4_revle32(i_data->iv_size);
-    o_data->iv_algorithmReserved = rs4_revle32(i_data->iv_algorithmReserved);
-    o_data->iv_length            = rs4_revle32(i_data->iv_length);
-    o_data->iv_scanSelect        = rs4_revle32(i_data->iv_scanSelect);
-    o_data->iv_headerVersion     = i_data->iv_headerVersion;
-    o_data->iv_flushOptimization = i_data->iv_flushOptimization;
-    o_data->iv_ringId            = i_data->iv_ringId;
-    o_data->iv_chipletId         = i_data->iv_chipletId;
-}
-
-
-// Return a big-endian-indexed nibble from a byte string
-
-static int
-rs4_get_nibble(const uint8_t* i_string, const uint32_t i_i)
-{
-    uint8_t byte;
-    int nibble;
-
-    byte = i_string[i_i / 2];
-    if (i_i % 2) {
-        nibble = byte & 0xf;
-    } else {
-        nibble = byte >> 4;
-    }
-    return nibble;
-}
-        
-
-// Set a big-endian-indexed nibble in a byte string
-
-static int
-rs4_set_nibble(uint8_t* io_string, const uint32_t i_i, const int i_nibble)
-{
-    uint8_t* byte;
-
-    byte = &(io_string[i_i / 2]);
-    if (i_i % 2) {
-        *byte = (*byte & 0xf0) | i_nibble;
-    } else {
-        *byte = (*byte & 0x0f) | (i_nibble << 4);
-    }
-    return i_nibble;
-}
-
-
-// Encode an unsigned integer into a 4-bit octal stop code directly into a
-// nibble stream at io_string<i_i>, returning the number of nibbles in the
-// resulting code. 
-
-static int
-rs4_stop_encode(const uint32_t i_count, uint8_t* io_string, const uint32_t i_i)
-{
-    uint32_t count;
-    int digits, offset;
-
-    // Determine the number of octal digits.  There is always at least 1.
-
-    count = i_count >> 3;
-    digits = 1;
-    while (count) {
-        count >>= 3;
-        digits++;
-    }
-
-    // First insert the stop (low-order) digit
-
-    offset = digits - 1;
-    rs4_set_nibble(io_string, i_i + offset, (i_count & 0x7) | 0x8);
-
-    // Now insert the high-order digits
-
-    count = i_count >> 3;
-    offset--;
-    while (count) {
-        rs4_set_nibble(io_string, i_i + offset, count & 0x7);
-        offset--;
-        count >>= 3;
-    }
-
-    return digits;
-}
-
-
-// Decode an unsigned integer from a 4-bit octal stop code appearing in a byte
-// string at i_string<i_i>, returning the number of nibbles decoded.
-
-static int
-stop_decode(uint32_t* o_count, const uint8_t* i_string, const uint32_t i_i)
-{
-    int digits, nibble;
-    uint32_t i, count;
-
-    digits = 0;
-    count = 0;
-    i = i_i;
-
-    do {
-        nibble = rs4_get_nibble(i_string, i);
-        count = (count * 8) + (nibble & 0x7);
-        i++;
-        digits++;
-    } while ((nibble & 0x8) == 0);
-
-    *o_count = count;
-    return digits;
-}
-
-      
-// RS4 compression algorithm notes:
-//
-// RS4 compression processes i_string as a string of nibbles.  Final
-// special-case code handles the 0-3 remaining terminal bits.
-//
-// There is a special case for 0x0 nibbles embedded in a string of non-0x0
-// nibbles. It is more efficient to encode a single 0x0 nibble as part of a
-// longer string of non 0x0 nibbles.  However it is break-even (actually a
-// slight statistical advantage) to break a scan seqeunce for 2 0x0 nibbles.
-//
-// If a run of 15 scan nibbles is found the scan is terminated and we return
-// to the rotate state.  Runs of more than 15 scans will always include a
-// 0-length rotate between the scan sequences.
-//
-// Returns the number of nibbles in the compressed string.
-
-static uint32_t
-__rs4_compress(CompressedScanData* o_data,
-               const uint8_t* i_string, 
-               const uint32_t i_length)
-{
-    int state;                  /* 0 : Rotate, 1 : Scan */
-    uint32_t n;                 /* Number of whole nibbles in i_data */
-    uint32_t r;                 /* Number of reminaing bits in i_data */
-    uint32_t i;                 /* Nibble index in i_string */
-    uint32_t j;                 /* Nibble index in data */
-    uint32_t k;                 /* Location to place scan count */
-    uint32_t count;             /* Counts rotate/scan nibbles */
-    uint8_t* data;              /* The compressed scan data area */
-
-    n = i_length / 4;
-    r = i_length % 4;
-    i = 0;
-    j = 0;
-    k = 0;                      /* Makes GCC happy */
-    data = (uint8_t*)o_data + sizeof(CompressedScanData);
-    count = 0;
-    state = 0;
-    
-    // Process the bulk of the string.  Note that state changes do not
-    // increment 'i' - the nibble at i_data<i> is always scanned again.
-
-    while (i < n) {
-        if (state == 0) {
-            if (rs4_get_nibble(i_string, i) == 0) {
-                count++;
-                i++;
-            } else {
-                j += rs4_stop_encode(count, data, j);
-                count = 0;
-                k = j;
-                j++;
-                state = 1;
-            }
-        } else {
-            if (rs4_get_nibble(i_string, i) == 0) {
-                if (((i + 1) < n) && (rs4_get_nibble(i_string, i + 1) == 0)) {
-                    rs4_set_nibble(data, k, count);
-                    count = 0;
-                    state = 0;
-                } else {
-                    rs4_set_nibble(data, j, 0);
-                    count++;
-                    i++;
-                    j++;
-                }
-            } else {
-                rs4_set_nibble(data, j, rs4_get_nibble(i_string, i));
-                count++;
-                i++;
-                j++;
-            }
-            if ((state == 1) && (count == 15)) {
-                rs4_set_nibble(data, k, 15);
-                state = 0;
-                count = 0;
-            }
-        }
-    }
-
-    // Finish the current state and insert the terminate code (scan 0).  If we
-    // finish on a scan we must insert a null rotate first.
-
-    if (state == 0) {
-        j += rs4_stop_encode(count, data, j);
-    } else {
-        rs4_set_nibble(data, k, count);
-        j += rs4_stop_encode(0, data, j);
-    }
-    rs4_set_nibble(data, j, 0);
-    j++;
-
-    // Insert the remainder count nibble, and if non-0, the remainder data
-    // nibble. 
-    
-    rs4_set_nibble(data, j, r);
-    j++;
-    if (r != 0) {
-        rs4_set_nibble(data, j, rs4_get_nibble(i_string, n));
-        j++;
-    }
-
-    // Return the number of nibbles in the compressed string. 
-
-    return j;
-}
-
-
-// The worst-case compression for RS4 requires 2 nibbles of control overhead
-// per 15 nibbles of data (17/15), plus a maximum of 2 nibbles of termination.
-// We always require this worst-case amount of memory including the header and
-// any rounding required to guarantee that the data size is a multiple of 8
-// bytes.  The final image size is also rounded up to a multiple of 8 bytes.
-
-int
-_rs4_compress(CompressedScanData* io_data,
-              uint32_t i_dataSize,
-              uint32_t* o_imageSize,
-              const uint8_t* i_string, 
-              const uint32_t i_length,
-              const uint64_t i_scanSelect,
-              const uint8_t i_ringId,
-              const uint8_t i_chipletId,
-              const uint8_t i_flushOptimization)
-{
-    int rc;
-    uint32_t nibbles, bytes;
-
-    nibbles = (((((i_length + 3) / 4) + 14) / 15) * 17) + 2;
-    bytes = ((nibbles + 1) / 2) + sizeof(CompressedScanData);
-    bytes = ((bytes + 7) / 8) * 8;
-
-    do {
-
-        if (i_dataSize < bytes) {
-            rc = BUG(SCAN_COMPRESSION_BUFFER_OVERFLOW);
-            break;
-        }
-
-        memset(io_data, 0, bytes);
-
-        nibbles = __rs4_compress(io_data, i_string, i_length);
-        bytes = ((nibbles + 1) / 2) + sizeof(CompressedScanData);
-        bytes = ((bytes + 7) / 8) * 8;
-
-        io_data->iv_magic             = rs4_revle32(RS4_MAGIC);
-        io_data->iv_size              = rs4_revle32(bytes);
-        io_data->iv_algorithmReserved = rs4_revle32(nibbles);
-        io_data->iv_length            = rs4_revle32(i_length);
-        io_data->iv_scanSelect        = rs4_revle32((uint32_t)(i_scanSelect >> 
-                                                               32));
-        io_data->iv_headerVersion     = COMPRESSED_SCAN_DATA_VERSION;
-        io_data->iv_flushOptimization = i_flushOptimization;
-        io_data->iv_ringId            = i_ringId;
-        io_data->iv_chipletId         = i_chipletId;
-
-        *o_imageSize = bytes;
-
-        rc = SCAN_COMPRESSION_OK;
-
-    } while (0);
-
-    return rc;
-}
-
-
-// The worst-case compression for RS4 requires 2 nibbles of control overhead
-// per 15 nibbles of data (17/15), plus a maximum of 2 nibbles of termination.
-// We always allocate this worst-case amount of memory including the header
-// and any rounding required to guarantee that the allocated length is a
-// multiple of 8 bytes.  The final size is also rounded up to a multiple of 8
-// bytes.
-
-int
-rs4_compress(CompressedScanData** o_data,
-             uint32_t* o_size,
-             const uint8_t* i_string, 
-             const uint32_t i_length,
-             const uint64_t i_scanSelect,
-             const uint8_t i_ringId,
-             const uint8_t i_chipletId,
-             const uint8_t i_flushOptimization)
-{
-    int rc;
-    uint32_t nibbles, bytes;
-
-    nibbles = (((((i_length + 3) / 4) + 14) / 15) * 17) + 2;
-    bytes = ((nibbles + 1) / 2) + sizeof(CompressedScanData);
-    bytes = ((bytes + 7) / 8) * 8;
-
-    *o_data = (CompressedScanData*)malloc(bytes);
-
-    if (*o_data == 0) {
-        rc = BUG(SCAN_COMPRESSION_NO_MEMORY);
-    } else {
-        rc = _rs4_compress(*o_data, bytes, o_size, i_string, i_length,
-                           i_scanSelect, i_ringId, i_chipletId,
-                           i_flushOptimization);
-    }
-
-    return rc;
-}
-
-
-// Decompress an RS4-encoded string into a output string whose length must be
-// exactly i_length bits.
-//
-// Returns a scan compression return code.
-
-static int
-__rs4_decompress(uint8_t* o_string, 
-                 const uint8_t* i_string, 
-                 const uint32_t i_length)
-{
-    int rc;
-    int state;                  /* 0 : Rotate, 1 : Scan */
-    uint32_t i;                 /* Nibble index in i_string */
-    uint32_t j;                 /* Nibble index in o_string */
-    uint32_t k;                 /* Loop index */
-    uint32_t bits;              /* Number of output bits decoded so far */
-    uint32_t count;             /* Count of rotate nibbles */
-    uint32_t nibbles;           /* Rotate encoding or scan nibbles to process */
-    int r;                      /* Remainder bits */
-
-    rc = 0;
-    i = 0;
-    j = 0;
-    bits = 0;
-    state = 0;
-
-    // Decompress the bulk of the string
-
-    do {
-        if (state == 0) {
-            nibbles = stop_decode(&count, i_string, i);
-            if ((bits + (4 * count)) > i_length) {
-                rc = BUG(SCAN_DECOMPRESSION_SIZE_ERROR);
-                break;
-            }
-            i += nibbles;
-            bits += (4 * count);
-            for (k = 0; k < count; k++) {
-                rs4_set_nibble(o_string, j, 0);
-                j++;
-            }
-            state = 1;
-        } else {
-            nibbles = rs4_get_nibble(i_string, i);
-            i++;
-            if (nibbles == 0) {
-                break;
-            }
-            if ((bits + (4 * nibbles)) > i_length) {
-                rc = BUG(SCAN_DECOMPRESSION_SIZE_ERROR);
-                break;
-            }
-            bits += (4 * nibbles);
-            for (k = 0; k < nibbles; k++) {
-                rs4_set_nibble(o_string, j, rs4_get_nibble(i_string, i));
-                i++;
-                j++;
-            }
-            state = 0;
-        }
-    } while (1);
-
-    // Now handle string termination
-
-    if (!rc) {
-        r = rs4_get_nibble(i_string, i);
-        i++;
-        if (r != 0) {
-            if ((bits + r) > i_length) {
-                rc = BUG(SCAN_DECOMPRESSION_SIZE_ERROR);
-            } else {
-                bits += r;
-                rs4_set_nibble(o_string, j, rs4_get_nibble(i_string, i));
-            }
-        }
-    }
-
-    // Final check to insure the string was valid
-
-    if (!rc) {
-        if (bits != i_length) {
-            rc = BUGX(SCAN_DECOMPRESSION_SIZE_ERROR,
-                      "bits = %zu, i_length = %zu\n",
-                      bits, i_length);
-        }
-    }
-
-    return rc;
-}
-
-
-int
-_rs4_decompress(uint8_t* io_string,
-                uint32_t i_stringSize,
-                uint32_t* o_length,
-                const CompressedScanData* i_data)
-{
-    int rc;
-    uint32_t bytes;
-
-    do {
-        if (rs4_revle32(i_data->iv_magic) != RS4_MAGIC) {
-            rc = BUG(SCAN_DECOMPRESSION_MAGIC_ERROR);
-            break;
-        }
-
-        *o_length = rs4_revle32(i_data->iv_length);
-        bytes = (*o_length + 7) / 8;
-
-        if (i_stringSize < bytes) {
-            rc = BUG(SCAN_COMPRESSION_BUFFER_OVERFLOW);
-            break;
-        }
-
-        memset(io_string, 0, bytes);
-
-        rc = __rs4_decompress(io_string, 
-                              (uint8_t*)i_data + sizeof(CompressedScanData),
-                              *o_length);
-    } while (0);
-
-    return rc;
-}
-
-
-int
-rs4_decompress(uint8_t** o_string,
-               uint32_t* o_length,
-               const CompressedScanData* i_data)
-{
-    int rc;
-    uint32_t length, bytes;
-
-    do {
-        if (rs4_revle32(i_data->iv_magic) != RS4_MAGIC) {
-            rc = BUG(SCAN_DECOMPRESSION_MAGIC_ERROR);
-            break;
-        }
-
-        length = rs4_revle32(i_data->iv_length);
-        bytes = (length + 7) / 8;
-        *o_string = (uint8_t*)malloc(bytes);
-
-        if (*o_string == 0) {
-            rc = BUG(SCAN_COMPRESSION_NO_MEMORY);
-            break;
-        }
-
-        rc = _rs4_decompress(*o_string, bytes, o_length, i_data);
-
-    } while (0);
-
-    return rc;
-}
-    
-
-int
-rs4_redundant(const CompressedScanData* i_data, int* o_redundant)
-{
-    int rc; 
-    uint8_t* data;
-    uint32_t length, stringLength, pos;
-
-    do {
-        *o_redundant = 0;
-
-        if (rs4_revle32(i_data->iv_magic) != RS4_MAGIC) {
-            rc = BUG(SCAN_DECOMPRESSION_MAGIC_ERROR);
-            break;
-        }
-
-        data = (uint8_t*)i_data + sizeof(CompressedScanData);
-        stringLength = rs4_revle32(i_data->iv_length);
-
-        // A compressed scan string is redundant if the initial rotate is
-        // followed by the end-of-string marker, and any remaining mod-4 bits
-        // are also 0.
-
-        pos = stop_decode(&length, data, 0);
-        length *= 4;
-        if (rs4_get_nibble(data, pos) == 0) {
-
-            if (rs4_get_nibble(data, pos + 1) == 0) {
-
-                *o_redundant = 1;
-
-            } else { 
-
-                length += rs4_get_nibble(data, pos + 1);
-                if (rs4_get_nibble(data, pos + 2) == 0) {
-
-                    *o_redundant = 1;
-                }
-            }
-        }
-
-        if ((length > stringLength) ||
-            (*o_redundant && (length != stringLength))) {
-
-            rc = SCAN_DECOMPRESSION_SIZE_ERROR;
-
-        } else {
-
-            rc = 0;
-        }
-    } while (0);
-
-    return rc;
-}
-    
-    
-
-
-
-                              
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.H
deleted file mode 100644
index ad185bf0c..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.H
+++ /dev/null
@@ -1,390 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_scan_compression.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __P8_SCAN_COMPRESSION_H__
-#define __P8_SCAN_COMPRESSION_H__
-
-// $Id: p8_scan_compression.H,v 1.5 2013/05/30 00:33:22 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/p8_scan_compression.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME: Bishop Brock  Email: Bishop Brock; bcbrock@us.ibm.com
-// *!
-// *! General Description:
-// *! 
-// *!     See below.
-//------------------------------------------------------------------------------
-//
-// Note: This file was originally named p8_scan_compression.c; See CVS archive
-// for revision history of p8_scan_compression.c.
-
-/// \file p8_scan_compression.H
-/// \brief Structure definitions and protoypes related to scan chain
-/// compression. 
-///
-/// This header declares and documents the entry points defined in
-/// p8_scan_compression.C.  Some constants are also required by the scan
-/// decompression PORE assembly procedures.
-
-#include "fapi_sbe_common.H"
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-/// Compressed Scan Chain Data Structure Format
-///
-/// The compressed scan ring data structure must be 8-byte aligned in
-/// memory. The container data structure consists of this 24-byte header
-/// followed by an arbitrary number of 8 byte doublewords containing the
-/// compressed scan data.  Images are always stored and processed in
-/// big-endian byte order.  This container format is common across all
-/// decompression algorithms.
-///
-/// Bytes - Content
-/// 
-/// 0:3 - A 32-bit "magic number" that identifies and validates the
-/// compression algorithm and algorithm version used to compress the data.
-///
-/// 4:7 - The 32-bit size of the entire data structure in \e bytes.  This
-/// consists of this 24-byte header plus the compressed scan data.  This value
-/// is always a multiple of 8.
-///
-/// 8:11 - This 32-bit value is reserved to the compression
-/// algorithm. Typically this field is used to record the 'size' of the
-/// compressed string in units specific to each algorithm.
-///
-/// 12:15 - The length of the original scan chain in \e bits.
-///
-/// 16:19 - The 32 high-order bits of the value written to the Scan Select
-/// register to set up the scan.  The Scan Select register only defines these
-/// bits. 
-///
-/// 20 - The Scan Chain Data Structure version number
-///
-/// 21 - Flush-optimize : Is this byte is non-zero, the ring state to be
-/// modified is the flush state of the ring.
-///
-/// 22 - The ring ID uniquely identifying the repair ring name.
-///
-/// 23 - The 7-bit pervasive chiplet Id + Multicast bit of the chiplet to
-/// scan.  This value is loaded directly into P0.  The decompression
-/// algorithms provide two entry points - one that uses this value as the
-/// chiplet Id, and another that allows the caller to specify the chiplet Id
-/// in the call.
-
-typedef struct {
-
-    /// Magic number - See \ref scan_compression_magic
-    uint32_t iv_magic;
-
-    /// Total size in bytes, including the container header
-    uint32_t iv_size;
-
-    /// Reserved to the algorithm
-    uint32_t iv_algorithmReserved;
-
-    /// Length of the original scan chain in bits
-    uint32_t iv_length;
-
-    /// The high-order 32 bits of the Scan Select Register
-    ///
-    /// Note that the Scan Select register only defines the high order 32
-    /// bits, so we only need store the 32 high-order bits.  This field is
-    /// 8-byte aligned so that the doubleword loaded by the PORE can be
-    /// directly written to the scan select register.
-    uint32_t iv_scanSelect;
-
-    /// Data structure (header) version
-    uint8_t iv_headerVersion;
-
-    /// Flush-state optimization
-    ///
-    /// Normally, modifying the state of the ring requires XOR-ing the
-    /// difference state (the compressed state) with the current ring state as
-    /// it will appear in the Scan Data Register. If the current state of the
-    /// ring is the scan-0 flush state, then by definition the Scan Data
-    /// Register is always 0. Therefore we can simply write the difference to
-    /// the Scan Data Register rather than using a read-XOR-write.
-    uint8_t iv_flushOptimization;
-
-    /// Ring ID uniquely identifying the repair name. (See the list of ring
-		/// name vs ring IDs in p8_ring_identification.c).
-    uint8_t iv_ringId;
-
-    /// 7-bit pervasive chiplet Id + Multicast bit
-    ///
-    /// This field is right-justified in an 8-byte aligned doubleword so that
-    /// the P0 register can be directly updated from the doubelword value in a
-    /// data register.
-    uint8_t iv_chipletId;
-
-} CompressedScanData;
-
-
-/// Endian-translate a CompressedScanData structure
-///
-/// \param o_data A pointer to a CompressedScanData structure to receive the
-/// endian-translated form of \a i_data.
-///
-/// \param i_data A pointer to the original CompressedScanData structure.
-///
-/// This API performs an endian-converting copy of a CompressedScanData
-/// structure. This copy is guaranteed to be done in such a way that \a i_data
-/// and \a o_data may be the same pointer for in-place conversion.  Due to the
-/// symmetry of reverse, translating a structure twice is always guaranteed to
-/// return the origial structure to its original byte order.
-void
-compressed_scan_data_translate(CompressedScanData* o_data,
-                               CompressedScanData* i_data);
-
-
-/// Compress a scan string using the RS4 compression algorithm
-///
-/// \param[in,out] io_data This is a pointer to a memory area which must be
-/// large enough to hold the worst-case result of compressing \a i_string (see
-/// below).  Note that the CompressedScanData is always created in big-endian
-/// format, however the caller can use compresed_scan_data_translate() to
-/// create a copy of the header in host format.
-///
-/// \param[in] i_dataSize The size of \a io_data in bytes.
-///
-/// \param[out] o_imageSize The effective size of the entire compressed scan
-/// data structure (header + compressed data) created in \a io_data, in bytes.
-/// This value will always be a multiple of 8.
-///
-/// \param[in] i_string The string to compress.  Scan data to compress is
-/// left-justified in this input string.
-///
-/// \param[in] i_length The length of the input string in \e bits.  It is
-/// assumed the \a i_string contains at least (\a i_length + 7) / 8 bytes.
-///
-/// \param[in] i_scanSelect The 64-bit value written to the Scan Select
-/// register to set up for the scan. Only the 32 high-order bits are actually
-/// stored.
-///
-/// \param[in] i_ringId The ring ID that uniquely identifies the ring name of
-/// a repair ring. (See p8_ring_identification.c for more info.)
-///
-/// \param[in] i_chipletId The 7-bit value for the iv_chipletId field of the
-/// CompressedScanData.
-///
-/// \param[in] i_flushOptimization This input parameter should be set to a
-/// non-0 value if it is known that this ring difference will be applied to a
-/// scan-0 flush state.  This will improve the performance of the
-/// decompress-scan routine. If the initial state of the ring is unknown, set
-/// this parameter to 0.
-///
-/// This API is required for integration with PHYP which does not support
-/// malloc().  Applications in environments supporting malloc() can use
-/// rs4_compress() instead.
-///
-/// The worst-case compression for RS4 requires 2 nibbles of control overhead
-/// per 15 nibbles of data (17/15), plus a maximum of 2 nibbles of termination.
-/// We always require this worst-case amount of memory including the header and
-/// any rounding required to guarantee that the data size is a multiple of 8
-/// bytes.  The final image size is also rounded up to a multiple of 8 bytes.
-/// If the \a i_dataSize is less than this amount (based on \a i_length) the
-/// call will fail.
-///
-/// \returns See \ref scan_compression_codes
-int
-_rs4_compress(CompressedScanData* io_data,
-              uint32_t i_dataSize,
-              uint32_t* o_imageSize,
-              const uint8_t* i_string, 
-              const uint32_t i_length,
-              const uint64_t i_scanSelect,
-              const uint8_t i_ringId,
-              const uint8_t i_chipletId,
-              const uint8_t i_flushOptimization);
-             
-
-/// Compress a scan string using the RS4 compression algorithm
-///
-/// \param[out] o_data This algorithm uses malloc() to allocate memory for the
-/// compresed data, and returns a pointer to this memory in \a o_data. After
-/// the call this memory is owned by the caller who is responsible for
-/// free()-ing the data area once it is no longer required. Note that the
-/// CompressedScanData is always created in big-endian format, however the
-/// caller can use compresed_scan_data_translate() to create a copy of the
-/// header in host format.
-///
-/// \param[out] o_size The effective size of the entire compressed scan data
-/// structure (header + compressed data) pointed to by \a o_data, in bytes.
-/// This value will always be a multiple of 8.
-///
-/// \param[in] i_string The string to compress.  Scan data to compress is
-/// left-justified in this input string.
-///
-/// \param[in] i_length The length of the input string in \e bits.  It is
-/// assumed the \a i_string contains at least (\a i_length + 7) / 8 bytes.
-///
-/// \param[in] i_scanSelect The 64-bit value written to the Scan Select
-/// register to set up for the scan. Only the 32 high-order bits are actually
-/// stored.
-///
-/// \param[in] i_ringId The ring ID that uniquely identifies the ring name of
-/// a repair ring. (See p8_ring_identification.c for more info.)
-///
-/// \param[in] i_chipletId The 7-bit value for the iv_chipletId field of the
-/// CompressedScanData.
-///
-/// \param[in] i_flushOptimization This input parameter should be set to a
-/// non-0 value if it is known that this ring difference will be applied to a
-/// scan-0 flush state.  This will improve the performance of the
-/// decompress-scan routine. If the initial state of the ring is unknown, set
-/// this parameter to 0.
-///
-/// \returns See \ref scan_compression_codes
-int
-rs4_compress(CompressedScanData** o_data,
-             uint32_t* o_size,
-             const uint8_t* i_string, 
-             const uint32_t i_length,
-             const uint64_t i_scanSelect,
-             const uint8_t i_ringId,
-             const uint8_t i_chipletId,
-             const uint8_t i_flushOptimization);
-             
-
-/// Decompress a scan string compressed using the RS4 compression algorithm
-///
-/// \param[in,out] io_string A caller-supplied data area to contain the
-/// decompressed string. The \a i_stringSize must be large enough to contain
-/// the decompressed string, which is the size of the original string in bits
-/// rounded up to the nearest byte.
-///
-/// \param[in] i_stringSize The size (in bytes) of \a i_string.
-///
-/// \param[out] o_length The length of the decompressed string in \e bits.
-///
-/// \param[in] i_data A pointer to the CompressedScanData header + data to be
-/// decompressed.
-///
-/// This API is required for integration with PHYP which does not support
-/// malloc().  Applications in environments supporting malloc() can use
-/// rs4_decompress() instead.
-///
-/// \returns See \ref scan_compression_codes
-int
-_rs4_decompress(uint8_t* i_string,
-                uint32_t i_stringSize,
-                uint32_t* o_length,
-                const CompressedScanData* i_data);
-             
-
-/// Decompress a scan string compressed using the RS4 compression algorithm
-///
-/// \param[out] o_string The API malloc()-s this data area to contain the
-/// decompressed string. After this call the caller owns \a o_string and is
-/// responsible for free()-ing this data area once it is no longer required.
-///
-/// \param[out] o_length The length of the decompressed string in \e bits.
-/// The caller may assume that \a o_string contains at least (\a o_length + 7)
-/// / 8 \e bytes.
-///
-/// \param[in] i_data A pointer to the CompressedScanData header + data to be
-/// decompressed.
-///
-/// \returns See \ref scan_compression_codes
-int
-rs4_decompress(uint8_t** o_string,
-               uint32_t* o_length,
-               const CompressedScanData* i_data);
-
-
-/// Determine if an RS4 compressed scan string is all 0
-///
-/// \param[in] i_data A pointer to the CompressedScanData header + data to be
-///
-/// \param[out] o_redundant Set to 1 if the RS4 string is the compressed form
-/// of a scan string that is all 0; Otherwise set to 0.
-///
-/// \returns See \ref scan _compression_code
-int
-rs4_redundant(const CompressedScanData* i_data, int* o_redundant);
-             
-
-#endif  // __ASSEMBLER__
-
-
-/// The current version of the CompressedScanData structure
-///
-/// This constant is required to be a #define to guarantee consistency between
-/// the header format and cmopiled code.
-#define COMPRESSED_SCAN_DATA_VERSION 1
-
-/// The size of the CompressedScanData structure
-CONST_UINT8_T(COMPRESSED_SCAN_DATA_SIZE, 24);
-
-
-/// \defgroup scan_compression_magic Scan Compression Magic Numbers
-///
-/// @ {
-
-/// RS4 Magic
-CONST_UINT32_T(RS4_MAGIC, 0x52533401);      /* "RS4" + Version 0x01 */
-
-/// @}
-
-
-/// \defgroup scan_compression_codes Scan Compression Return Codes
-///
-/// @{
-
-/// Normal return code
-CONST_UINT8_T(SCAN_COMPRESSION_OK, 0);
-
-/// The (de)compression algorithm could not allocate enough memory for the
-/// (de)compression.
-CONST_UINT8_T(SCAN_COMPRESSION_NO_MEMORY, 1);
-
-/// Magic number mismatch on scan decompression
-CONST_UINT8_T(SCAN_DECOMPRESSION_MAGIC_ERROR, 2);
-
-/// Decompression size error
-///
-/// Decompression produced a string of a size different than indicated in the
-/// header, indicating either a bug or data corruption.  Note that the entire
-/// application should be considered corrupted if this error occurs since it
-/// may not be discovered until after the decompression buffer is
-/// overrun. This error may also be returned by rs4_redundant() in the event
-/// of inconsistencies in the compressed string.
-CONST_UINT8_T(SCAN_DECOMPRESSION_SIZE_ERROR, 3);
-
-/// A buffer would overflow
-///
-/// Either the caller-supplied memory buffer to _rs4_decompress() was too
-/// small to contain the decompressed string, or a caller-supplied buffer to
-/// _rs4_compress() was not large enough to hold the worst-case compressed
-/// string.
-CONST_UINT8_T(SCAN_COMPRESSION_BUFFER_OVERFLOW, 4);
-
-/// @}
-
-#endif  //  __P8_SCAN_COMPRESSION_H__
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H
deleted file mode 100644
index 3e03d50aa..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H
+++ /dev/null
@@ -1,120 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-// $Id: p8_slw_build.H,v 1.4 2013-02-12 23:25:58 cmolsen Exp $
-
-#include <fapi.H>
-
-#include <p8_scan_compression.H>
-
-typedef fapi::ReturnCode (*p8_slw_build_FP_t) (	const fapi::Target&, 
-                                                const void*,
-                                                uint32_t,
-                                                void*,
-                                                uint32_t*);
-
-typedef fapi::ReturnCode (*p8_slw_build_fixed_FP_t) (	const fapi::Target&, 
-                                                        void*,
-                                                        void*,
-                                                        uint32_t&,
-                                                        const uint8_t, 
-                                                        void*,
-                                                        const uint32_t,
-                                                        void*,
-                                                        const uint32_t );
-
-typedef fapi::ReturnCode (*p8_slw_repair_FP_t) (const fapi::Target&, 
-                                                void*,
-                                                CompressedScanData*,
-                                                void*,
-                                                const uint32_t,
-                                                void*,
-                                                const uint32_t);
-
-
-extern "C"
-{
-	// Description:  FAPI HWP entry point.  p8_slw_build() constructs the 
-	//               Sleep-Winkle (SLW) image in mainstore during Hostboot
-	//               IPL.
-	// Parameters:   i_target:    Processor chip target.
-	//               *i_imageIn:  Pointer to location of input SBE-XIP image.
-	//               i_sizeImageIn: Size of input image.
-	//               *i_imageOut: Pointer to location of output SLW image in
-	//                            mainstore.
-	//               *io_sizeImageOut: On input, upper limit of size of output 
-	//                            image.  On output, final size of output image.
-    fapi::ReturnCode p8_slw_build( 	const fapi::Target &i_target,
-                                        const void 	*i_imageIn,
-                                        uint32_t 		i_sizeImageIn,
-                                        void 				*i_imageOut,
-                                        uint32_t 		*io_sizeImageOut);
-
-
-	// Description:  FAPI HWP entry point.  p8_slw_build_fixed() constructs the 
-	//               fixed Sleep-Winkle (SLW) image in mainstore during Hostboot
-	//               IPL, PHYP rebuild and non-fixed image for SRAM.
-	// Parameters:   i_target:    Processor chip target.
-	//               *i_imageIn:  Pointer to input Reference image (from PNOR).
-	//               *i_imageOut: Pointer to output SLW image.
-	//               &io_sizeImageOut: In: Max size of output img. 
-	//                                 Out: Final size of output img.
-  //               i_modeBuild:    0: HB/IPL mode, 1: PHYP/Rebuild mode, 
-  //                               2: SRAM mode.
-  //               *i_buf1:        Temp buffer 1 for dexed RS4 ring. (Caller 
-  //                               allocs/frees.)
-  //               i_sizeBuf1:     Size of buf1.
-  //               *i_buf2:        Temp buffer 2 for WF ring. (Caller 
-  //                               allocs/frees.)
-  //               i_sizeBuf2:     Size of buf2.
-        fapi::ReturnCode p8_slw_build_fixed( 	const fapi::Target &i_target,
-                                                void               *i_imageIn,
-                                                void               *i_imageOut,
-                                                uint32_t           &io_sizeImageOut,
-                                                const uint8_t      i_modeBuild, 
-                                                void               *i_buf1,
-                                                const uint32_t     i_sizeBuf1,
-                                                void               *i_buf2,
-                                                const uint32_t     i_sizeBuf2 );
-
-
-	// Description:  FAPI HWP entry point.  p8_slw_repair() updates the L2 (core) 
-	//               and L3 (eco) cashes during concurrent rebuilds.            
-	// Parameters:   i_target:    Processor chip target.
-	//               *io_image:   Pointer to SLW image.
-	//               *i_bufRs4:   Pointer to the RS4 ring data.
-  //               *i_buf1:        Temp buffer 1 for dexed RS4 ring. (Caller 
-  //                               allocs/frees.)
-  //               i_sizeBuf1:     Size of buf1.
-  //               *i_buf2:        Temp buffer 2 for WF ring. (Caller 
-  //                               allocs/frees.)
-  //               i_sizeBuf2:     Size of buf2.
-        fapi::ReturnCode p8_slw_repair( const fapi::Target &i_target, 
-                                        void							 *io_image,
-                                        CompressedScanData *i_bufRs4,
-                                        void							 *i_buf1,
-                                        const uint32_t		 i_sizeBuf1,
-                                        void							 *i_buf2,
-                                        const uint32_t		 i_sizeBuf2);
-
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_fixed.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_fixed.C
deleted file mode 100644
index 4c5e953c5..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_fixed.C
+++ /dev/null
@@ -1,917 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_slw_build_fixed.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_slw_build_fixed.C,v 1.24 2015/09/14 17:04:33 cswenson Exp $
-/*------------------------------------------------------------------------------*/
-/* *! TITLE : p8_slw_build_fixed                                                      */
-/* *! DESCRIPTION : Extracts and decompresses delta ring states from EPROM      */
-//                  image. Utilizes the linked list approach (LLA) to extract
-//                  and position wiggle-flip programs in .rings according to 
-//                  back pointer, DD level, phase and override settings. 
-/* *! OWNER NAME : Michael Olsen                  cmolsen@us.ibm.com            */
-//
-/* *! EXTENDED DESCRIPTION :                                                    */
-//
-/* *! USAGE : 
-              To build (for Hostboot) -
-              buildfapiprcd   -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C"   -c "sbe_xip_image.c,pore_inline_assembler.c"   -e "../../xml/error_info/p8_slw_build_errors.xml,../../xml/error_info/proc_sbe_decompress_scan_halt_codes.xml"   p8_slw_build_fixed.C
-              To build (for command-line) -
-              buildfapiprcd   -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C"   -c "sbe_xip_image.c,pore_inline_assembler.c"   -e "../../xml/error_info/p8_slw_build_errors.xml,../../xml/error_info/proc_sbe_decompress_scan_halt_codes.xml"   -u "SLW_COMMAND_LINE"   p8_slw_build_fixed.C
-              To add polling protocol to wf programs:
-                -u "IMGBUILD_PPD_WF_POLLING_PROT"
-              To NOT run xip_customize:
-                -u "IMGBUILD_PPD_IGNORE_XIPC"                                   */
-//
-/* *! ASSUMPTIONS :                                                             */
-//
-/* *! COMMENTS :                                                                */
-//
-/*------------------------------------------------------------------------------*/
-
-#include <p8_pore_api_custom.h>
-#include <p8_slw_build.H>
-#include <p8_xip_customize.H>
-#include <p8_delta_scan_rw.h>
-#include <p8_pore_table_gen_api.H>
-
-extern "C"  {
-
-using namespace fapi;
-
-//  Parameter list:
-//  fapi::Target &i_target:   Hardware target
-//  void      *i_imageIn:     Pointer to memory mapped input Reference PNOR image
-//  void      *i_imageOut:    Pointer to where to put SLW mainstore image
-//  uint32_t  &io_sizeImageOut: In: Max size of outp img. Out: Final size of outp img.
-//                            On input, this MUST be equal to FIXED_SLW_IMAGE_SIZE for
-//                            i_modeBuild={0,1}.
-//  uint8_t   i_modeBuild:    0: HB/IPL mode, 1: PHYP/Rebuild mode, 2: SRAM mode.
-//  void      *i_buf1:        Temp buffer 1 for dexed RS4 ring. (Caller allocs/frees.)
-//  uint32_t  i_sizeBuf1:     Size of buf1.
-//                            This MUST be equal to FIXED_RING_BUF_SIZE.
-//  void      *i_buf2:        Temp buffer 2 for WF ring. (Caller allocs/frees.)
-//  uint32_t  i_sizeBuf22     Size of buf2.
-//                            This MUST be equal to FIXED_RING_BUF_SIZE.
-//
-ReturnCode p8_slw_build_fixed( const fapi::Target &i_target,
-                         void               *i_imageIn,
-                         void               *i_imageOut,
-												 uint32_t           &io_sizeImageOut,
-                         const uint8_t      i_modeBuild, 
-												 void               *i_buf1,
-												 const uint32_t     i_sizeBuf1,
-												 void               *i_buf2,
-												 const uint32_t     i_sizeBuf2 )
-{
-  ReturnCode rc;
-  uint8_t   l_uint8=0;
-	uint8_t   bSearchDone=0;
-  uint32_t  ddLevel=0;
-  uint8_t   sysPhase=1; // SLW image build phase.
-  uint32_t  rcLoc=0, rcSearch=0, i, countWF=0;
-  uint32_t  sizeImage=0, sizeImageIn=0, sizeImageOutMax, sizeImageTmp;
-  CompressedScanData *deltaRingRS4=NULL;
-  DeltaRingLayout rs4RingLayout;
-  void *nextRing=NULL;
-  uint32_t  ringBitLen=0;
-  uint32_t  *wfInline=NULL;
-  uint32_t  wfInlineLenInWords;
-	uint64_t  scanMaxRotate=SCAN_ROTATE_DEFAULT;
-  uint32_t  dataTmp1, dataTmp2, dataTmp3;
-  uint64_t  ptrTmp1, ptrTmp2;
-  uint32_t  bufLC;
-  uint8_t   ffdc_temp;
- 	// Sanity checks on buffers and image.
-  // - validate image.
-	// - do pre-allocated buffers exist?
-	// - are pre-allocated buffers the correct size?
-  // - is supplied output image size the correct size?
-	// - is input image smaller than the output image size?
-	// - is modeBuild valid?
-	//
-  sbe_xip_image_size((void*)i_imageIn, &sizeImageIn);
-  rcLoc = sbe_xip_validate((void*)i_imageIn, sizeImageIn);
-  if (rcLoc)  {
-    FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_INTERNAL_IMAGE_ERR);
-    return rc;
-  }
-	if (i_imageOut==i_imageIn)  {
-		FAPI_ERR("The images, imageIn and imageOut, point to the same buffer space.");
-    ptrTmp1 = (uint64_t)i_imageIn;
-    ptrTmp2 = (uint64_t)i_imageOut;
-    uint64_t & DATA_BUF1_PTR = ptrTmp1;
-    uint64_t & DATA_BUF2_PTR = ptrTmp2;
-	  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_IMG_PTR_ERROR);
-	  return rc;
-	}
-  sizeImageOutMax = io_sizeImageOut; // This should be 1MB for mode 0 and 1.
-  FAPI_DBG("Mode build = %i\n",i_modeBuild);
-	if ((i_modeBuild==P8_SLW_MODEBUILD_IPL || 
-       i_modeBuild==P8_SLW_MODEBUILD_REBUILD) && 
-       sizeImageOutMax!=FIXED_SLW_IMAGE_SIZE)  {
-    FAPI_ERR("Supplied output image size differs from agreed upon fixed SLW image size.");
-    FAPI_ERR("Supplied output image size: %i",sizeImageOutMax);
-    FAPI_ERR("Agreed upon fixed SLW image size: %i",FIXED_SLW_IMAGE_SIZE);
-    dataTmp1 = FIXED_SLW_IMAGE_SIZE;
-    uint32_t & DATA_IMG_SIZE_MAX = sizeImageOutMax;
-		uint32_t & DATA_IMG_SIZE_FIXED = dataTmp1;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_IMAGE_SIZE_NOT_FIXED);
-    return rc;
-  }
-  if ((i_modeBuild==P8_SLW_MODEBUILD_IPL || 
-       i_modeBuild==P8_SLW_MODEBUILD_REBUILD) && 
-       sizeImageIn>sizeImageOutMax)  {
-    FAPI_ERR("Input image size exceeds fixed output image size.");
-    FAPI_ERR("Size of supplied input image: %i",sizeImageIn);
-    FAPI_ERR("Supplied output image size: %i",sizeImageOutMax);
-    uint32_t & DATA_IMG_SIZE_INP = sizeImageIn;
-		uint32_t & DATA_IMG_SIZE_MAX = sizeImageOutMax;
-		FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_INPUT_IMAGE_SIZE_MESS);
-    return rc;
-  }
-	if (!i_buf1 || !i_buf2)  {
-		FAPI_ERR("The [assumed] pre-allocated ring buffers, i_buf1/2, do not exist.");
-    ptrTmp1 = (uint64_t)i_buf1;
-    ptrTmp2 = (uint64_t)i_buf2;
-    uint64_t & DATA_BUF1_PTR = ptrTmp1;
-    uint64_t & DATA_BUF2_PTR = ptrTmp2;
-	  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_BUF_PTR_ERROR);
-	  return rc;
-	}
-	if (i_buf1==i_buf2)  {
-		FAPI_ERR("The buffers, buf1 and buf2, point to the same buffer space.");
-    ptrTmp1 = (uint64_t)i_buf1;
-    ptrTmp2 = (uint64_t)i_buf2;
-    uint64_t & DATA_BUF1_PTR = ptrTmp1;
-    uint64_t & DATA_BUF2_PTR = ptrTmp2;
-	  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_BUF_PTR_ERROR);
-	  return rc;
-	}
-	if (i_sizeBuf1!=FIXED_RING_BUF_SIZE || i_sizeBuf2!=FIXED_RING_BUF_SIZE)  {
-    FAPI_ERR("Supplied ring buffer size(s) differs from agreed upon fixed size.");
-    FAPI_ERR("Supplied ring buf1 size: %i",i_sizeBuf1);
-    FAPI_ERR("Supplied ring buf2 size: %i",i_sizeBuf2);
-    FAPI_ERR("Agreed upon fixed ring buf size: %i",FIXED_RING_BUF_SIZE);
-    dataTmp1 = i_sizeBuf1;
-    dataTmp2 = i_sizeBuf2;
-    dataTmp3 = FIXED_RING_BUF_SIZE;
-    uint32_t & DATA_BUF1_SIZE = dataTmp1;
-    uint32_t & DATA_BUF2_SIZE = dataTmp2;
-		uint32_t & DATA_BUF_SIZE_FIXED = dataTmp3;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_BUF_SIZE_NOT_FIXED);
-    return rc;
-	}
-  if (i_modeBuild>P8_SLW_MODEBUILD_MAX_VALUE)  {
-    FAPI_ERR("modeBuild=%i invalid. Valid range is [0;%i].",
-      i_modeBuild,P8_SLW_MODEBUILD_MAX_VALUE);
-    ffdc_temp = i_modeBuild;
-    uint8_t & MODE_BUILD=ffdc_temp;
-		FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_BAD_CODE_OR_PARM);
-    return rc;
-  }
-  FAPI_DBG("Reference/input image size: %i",sizeImageIn);
-  
-
-  // ==========================================================================
-  // Check and copy image to mainstore and clean it up.
-  // ==========================================================================
-  // ToDo:
-  // - Eventually, automate emptying sections in proper order (last section goes first).
-  // - For 5/15, assume following order of removal: rings, pibmem0, and halt.
-  //
-  // First, copy input image to supplied mainstore location.
-  //
-  memcpy( i_imageOut, i_imageIn, sizeImageIn);
-  sbe_xip_image_size(i_imageOut, &sizeImage);
-  rcLoc = sbe_xip_validate(i_imageOut, sizeImage);
-  if (rcLoc)  {
-    FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-		uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_MS_INTERNAL_IMAGE_ERR);
-    return rc;
-  }
-  if (sizeImage!=sizeImageIn)  {
-    FAPI_ERR("Size obtained from copied image's header (=%i) differs from input image's size (=%i).",
-      sizeImage,sizeImageIn);
-    uint32_t & DATA_IMG_SIZE = sizeImage;
-    uint32_t & DATA_IMG_SIZE_INP = sizeImageIn;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_MS_IMAGE_SIZE_MISMATCH);
-    return rc;
-  }
-
-  // Second, delete .dcrings, .rings and .pibmem0 sections (but keep .halt)
-  //
-  rcLoc = sbe_xip_delete_section( i_imageOut, SBE_XIP_SECTION_DCRINGS);
-  if (rcLoc)  {
-    FAPI_ERR("xip_delete_section(.dcrings) failed w/rcLoc=%i",rcLoc);
-    ffdc_temp=(uint8_t)SBE_XIP_SECTION_DCRINGS;
-    uint8_t & SBE_XIP_SECTION=ffdc_temp;
-	  uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_DELETE_IMAGE_SECTION_ERROR);
-    return rc;
-  }
-  sbe_xip_image_size(i_imageOut, &sizeImage);
-  rcLoc =  sbe_xip_validate(i_imageOut, sizeImage);
-  if (rcLoc)  {
-	  FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-	  uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_MS_INTERNAL_IMAGE_ERR);
-    return rc;
-  }
-  FAPI_DBG("Image size (after .dcrings delete): %i",sizeImage);
-
-  rcLoc = sbe_xip_delete_section( i_imageOut, SBE_XIP_SECTION_RINGS);
-  if (rcLoc)  {
-    FAPI_ERR("xip_delete_section(.rings) failed w/rcLoc=%i",rcLoc);
-    ffdc_temp=(uint8_t)SBE_XIP_SECTION_RINGS;
-    uint8_t & SBE_XIP_SECTION=ffdc_temp;
-	  uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_DELETE_IMAGE_SECTION_ERROR);
-    return rc;
-  }
-  sbe_xip_image_size(i_imageOut, &sizeImage);
-  rcLoc =  sbe_xip_validate(i_imageOut, sizeImage);
-  if (rcLoc)  {
-	  FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-	  uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_MS_INTERNAL_IMAGE_ERR);
-    return rc;
-  }
-  FAPI_DBG("Image size (after .rings delete): %i",sizeImage);
-
-  rcLoc = sbe_xip_delete_section( i_imageOut, SBE_XIP_SECTION_PIBMEM0);
-  if (rcLoc)  {
-    FAPI_ERR("xip_delete_section(.pibmem0) failed w/rcLoc=%i",rcLoc);
-    ffdc_temp=(uint8_t)SBE_XIP_SECTION_PIBMEM0;
-    uint8_t & SBE_XIP_SECTION=ffdc_temp;
-	  uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_DELETE_IMAGE_SECTION_ERROR);
-    return rc;
-  }
-  sbe_xip_image_size(i_imageOut, &sizeImage);
-  rcLoc =  sbe_xip_validate(i_imageOut, sizeImage);
-  if (rcLoc)  {
-	  FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-	  uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_MS_INTERNAL_IMAGE_ERR);
-    return rc;
-  }
-	FAPI_DBG("Image size (after .pibmem0 delete): %i",sizeImage);
-
-	//
-	// DD level.
-	//
-  rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, l_uint8);
-  ddLevel = (uint32_t)l_uint8;
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET_PRIVILEGED() failed w/rc=%i and  ddLevel=0x%02x",(uint32_t)rc,l_uint8);
-    return rc;
-  }
-
-
-#ifndef IMGBUILD_PPD_IGNORE_XIPC
-  // ==========================================================================
-  // Get various FAPI attributes and variables needed for ring unraveling.
-  // ==========================================================================
-	uint8_t    attrAsyncSafeMode=0, bAsyncSafeMode;
-	uint8_t    attrSleepEnable=1, bSleepEnable;
-	uint32_t   attrFuncL3RingList[MAX_FUNC_L3_RING_LIST_ENTRIES]={0};
-	uint8_t    attrFuncL3RingData[MAX_FUNC_L3_RING_SIZE]={0};
-	uint32_t   attrFaryL2RingList[MAX_FARY_L2_RING_LIST_ENTRIES]={0};
-	uint8_t    attrFaryL2RingData[MAX_FARY_L2_RING_SIZE]={0};
-	uint32_t   attrFuncL3RingLength=0;
-        uint32_t   attrFaryL2RingLength=0;
-	SbeXipItem xipTocItem;
-	uint64_t   xipFuncL3RingVector=0;
-	uint64_t   xipFaryL2RingVector=0;
-	uint32_t   iEntry;
-
-	// Safe mode status.
-	//
-  rc = FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE, NULL, attrAsyncSafeMode);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_FABRIC_ASYNC_SAFE_MODE) returned error.");
-    return rc;
-  }
-	bAsyncSafeMode = attrAsyncSafeMode;
-	
-	// Obtain ex_func_l3_ring overlay data and length from attributes.
-	// Obtain ring name and ring's vector location from image.
-	//
-	if (!bAsyncSafeMode)  {
-		// Get overlay ring from attributes.
-	  rc = FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_DELTA_DATA, &i_target, attrFuncL3RingList);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_DELTA_DATA) returned error.");
-	    return rc;
-	  }
-	  rc = FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_LENGTH, &i_target, attrFuncL3RingLength);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_EX_FUNC_L3_LENGTH) returned error.");
-	    return rc;
-	  }
-		//attrFuncL3RingLength = 0xBEBA;
-		for (iEntry=0; iEntry<MAX_FUNC_L3_RING_LIST_ENTRIES; iEntry++)  {
-			if (attrFuncL3RingList[iEntry]!=0xffff0000)  {
-				attrFuncL3RingData[attrFuncL3RingList[iEntry]>>16] =
- 																		(uint8_t)((attrFuncL3RingList[iEntry]<<24)>>24);
-			}
-			else
-				break;
-		}
-		FAPI_DBG("Overlay [raw] ring created for func L3.");
-		// Get ring name from xip image.
-		rcLoc = sbe_xip_find((void*)i_imageIn, FUNC_L3_RING_TOC_NAME, &xipTocItem);
-		if (rcLoc)  {
-	    FAPI_ERR("sbe_xip_find() failed w/rc=%i", rcLoc);
-	    FAPI_ERR("Probable cause:");
-	    FAPI_ERR("\tThe keyword (=%s) was not found.", FUNC_L3_RING_TOC_NAME);
-	    uint32_t & RC_LOCAL = rcLoc;
-	    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_KEYWORD_NOT_FOUND_ERROR);
-	    return rc;
-	  }
-		xipFuncL3RingVector = xipTocItem.iv_address;
-	}
-
-	// sleep enable/disable
-    rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_ENABLE, NULL, attrSleepEnable);
-    FAPI_DBG("--> attrSleepEnable = 0x%x ", attrSleepEnable);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_SLEEP_ENABLE) returned error.");
-      return rc;
-    }
-	bSleepEnable = attrSleepEnable;
-    FAPI_DBG("--> bSleepEnable = 0x%x ",bSleepEnable);
-	// Obtain ring name and ring's vector location from image.
-    if (bSleepEnable) {
-        uint8_t chipType;
-      rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_target, chipType);
-      if (rc)  {
-        FAPI_ERR("FAPI_ATTR_GET_PRIVILEGED() failed w/rc=%i and  chipType=0x%02x",(uint32_t)rc,chipType);
-        return rc;
-      }
-      // configure overlay ring/ring length based on CT/EC
-      if ((chipType == fapi::ENUM_ATTR_NAME_MURANO) && (ddLevel < 0x20))
-      {
-        attrFaryL2RingList[0] = 0x1E2100C0;
-        attrFaryL2RingList[1] = 0xFFFF0000;
-        attrFaryL2RingLength = 82649;
-      }
-      else if ((chipType == fapi::ENUM_ATTR_NAME_MURANO) && (ddLevel >= 0x20))
-      {
-        attrFaryL2RingList[0] = 0x1DC4000C;
-        attrFaryL2RingList[1] = 0xFFFF0000;
-        attrFaryL2RingLength = 83294;
-      }
-      else if ((chipType == fapi::ENUM_ATTR_NAME_VENICE) && (ddLevel < 0x20))
-      {
-        attrFaryL2RingList[0] = 0x1DA600C0;
-        attrFaryL2RingList[1] = 0xFFFF0000;
-        attrFaryL2RingLength = 83050;
-      }
-      else if (((chipType == fapi::ENUM_ATTR_NAME_VENICE) && (ddLevel >= 0x20)) ||
-               (chipType == fapi::ENUM_ATTR_NAME_NAPLES))
-      {
-        attrFaryL2RingList[0] = 0x1DC50003;
-        attrFaryL2RingList[1] = 0xFFFF0000;
-        attrFaryL2RingLength = 83304;
-      }
-      else
-      {
-        FAPI_ERR("Unsupported CT/EC combination in sleep processing code!");
-        const uint8_t CT = chipType;
-        const uint8_t EC = ddLevel;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_SLEEP_PROCESSING_ERROR);
-        return rc;
-      }
-
-      for (iEntry=0; iEntry<MAX_FARY_L2_RING_LIST_ENTRIES; iEntry++)  {
-        if (attrFaryL2RingList[iEntry]!=0xffff0000)  {
-          attrFaryL2RingData[attrFaryL2RingList[iEntry]>>16] = (uint8_t)((attrFaryL2RingList[iEntry]<<24)>>24);
-        }
-        else
-          break;
-      }
-      FAPI_DBG("Overlay [raw] ring created for func L3 ring.");
-
-      // Get ring name from xip image.
-      rcLoc = sbe_xip_find((void*)i_imageIn, FARY_L2_RING_TOC_NAME, &xipTocItem);
-      if (rcLoc)  {
-        FAPI_ERR("sbe_xip_find() failed w/rc=%i", rcLoc);
-        FAPI_ERR("Probable cause:");
-        FAPI_ERR("\tThe keyword (=%s) was not found.", FARY_L2_RING_TOC_NAME);
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_KEYWORD_NOT_FOUND_ERROR);
-        return rc;
-      }
-      xipFaryL2RingVector = xipTocItem.iv_address;
-    }
-#endif
-
-
-  /***************************************************************************
-   *                            SEARCH LOOP - Begin                            *
-   ***************************************************************************/
-  do  {
-
-  FAPI_DBG("nextRing (at top)=0x%016llx",(uint64_t)nextRing);
-  
-
-  // ==========================================================================
-  // Get ring layout from image
-  // ==========================================================================
-  FAPI_DBG("--> Reading RS4 delta ring info from SBE-XIP Image.");
-  rcLoc = get_ring_layout_from_image( i_imageIn,
-                                      ddLevel,
-                                      sysPhase,
-                                      &rs4RingLayout,
-                                      &nextRing);
-  rcSearch = rcLoc;
-  if (rcSearch!=DSLWB_RING_SEARCH_MATCH && 
-      rcSearch!=DSLWB_RING_SEARCH_EXHAUST_MATCH && 
-      rcSearch!=DSLWB_RING_SEARCH_NO_MATCH)  {
-    FAPI_ERR("\tGetting delta ring from image was unsuccessful (rcSearch=%i).",rcSearch);
-    FAPI_ERR("\tNo wiggle-flip programs will be stored in .rings section.");
-    FAPI_ERR("\tThe following ELF sections have been emptied: .rings, .pibmem0, .ipl_text.");
-    uint32_t & RC_LOCAL=rcLoc;
-	  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_RING_RETRIEVAL_ERROR);
-    return rc;
-  }
-  if (rcSearch==DSLWB_RING_SEARCH_MATCH || 
-      rcSearch==DSLWB_RING_SEARCH_EXHAUST_MATCH)
-  {
-    FAPI_DBG("\tRetrieving RS4 delta ring was successful.");
-  }
-
-  //
-	// Check if we're done at this point, and save status in bSearchDone.
-  //      
-  if (rcSearch==DSLWB_RING_SEARCH_NO_MATCH)  {
-
-		bSearchDone = 1;
-
-	}
-	else  {  // More rings to search...
-  
-	  deltaRingRS4 = (CompressedScanData*)rs4RingLayout.rs4Delta;
-	  
-	  FAPI_DBG("Dumping ring layout:");
-	  FAPI_DBG("\tentryOffset      = %i",(uint32_t)myRev64(rs4RingLayout.entryOffset));
-	  FAPI_DBG("\tbackItemPtr     = 0x%016llx",myRev64(rs4RingLayout.backItemPtr));
-	  FAPI_DBG("\tsizeOfThis      = %i",myRev32(rs4RingLayout.sizeOfThis));
-	  FAPI_DBG("\tsizeOfMeta      = %i",myRev32(rs4RingLayout.sizeOfMeta));
-	  FAPI_DBG("\tddLevel         = %i",myRev32(rs4RingLayout.ddLevel));
-	  FAPI_DBG("\tsysPhase        = %i",rs4RingLayout.sysPhase);
-	  FAPI_DBG("\toverride        = %i",rs4RingLayout.override);
-	  FAPI_DBG("\treserved1+2     = %i",rs4RingLayout.reserved1|rs4RingLayout.reserved2);
-	  FAPI_DBG("\tRS4 magic #     = 0x%08x",myRev32(deltaRingRS4->iv_magic));    
-	  FAPI_DBG("\tRS4 total size  = %i",myRev32(deltaRingRS4->iv_size));
-	  FAPI_DBG("\tUnXed data size = %i",myRev32(deltaRingRS4->iv_length));
-	  FAPI_DBG("\tScan select     = 0x%08x",myRev32(deltaRingRS4->iv_scanSelect));
-	  FAPI_DBG("\tHeader version  = 0x%02x",deltaRingRS4->iv_headerVersion);
-	  FAPI_DBG("\tFlush optimize  = 0x%02x (reverse of override)",deltaRingRS4->iv_flushOptimization);
-	  FAPI_DBG("\tRing ID         = 0x%02x",deltaRingRS4->iv_ringId);
-	  FAPI_DBG("\tChiplet ID      = 0x%02x",deltaRingRS4->iv_chipletId);
-	  FAPI_DBG("Dumping meta data:");
-	  FAPI_DBG("\tsizeOfData = %i",myRev32(rs4RingLayout.sizeOfMeta));
-	  FAPI_DBG("\tMeta data  = ");
-	  for (i=0; i<myRev32(rs4RingLayout.sizeOfMeta); i++)  { // String may not be null terminated.
-	    FAPI_DBG("%c",rs4RingLayout.metaData[i]);
-	  }
-	
-	
-	  // ==========================================================================
-	  // Decompress RS4 delta state.
-	  // ==========================================================================
-	  FAPI_DBG("--> Decompressing RS4 delta ring.");
-	  rcLoc = _rs4_decompress((uint8_t*)i_buf2,
-	                          i_sizeBuf2,
-														&ringBitLen,
-	                          deltaRingRS4);
-	  if (rcLoc)  {
-	    FAPI_ERR("\t_rs4_decompress() failed: rc=%i",rcLoc);
-			uint32_t & RC_LOCAL=rcLoc;
-	    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_RS4_DECOMPRESSION_ERROR);
-	    return rc;
-	  }
-	  FAPI_DBG("\tDecompression successful.\n");
-	  
-	
-#ifndef IMGBUILD_PPD_IGNORE_XIPC
-	  // ==========================================================================
-	  // CUSTOMIZE item:    Overlay ex_func_l3_ring.
-		// Retrieval method:  Attribute.
-		// Note: Check if ex_func_l3_ring's vector address matches current backPtr.
-		//       If so, perform OR operation with new attribute data for this ring.
-		// Assumptions:
-		// - Base ring only.
-		// - Correct DD level rings only.
-  	// ==========================================================================
-		uint8_t   byteExisting=0, byteOverlay=0, bGoodByte=1;
-		uint32_t  iByte, sizeRingInBytes;
-  	FAPI_DBG("--> Check if we should modify the ex_func_l3_ring with attribute data.");
-		if (!bAsyncSafeMode)  {
-			// Find ring match by comparing backItemPtr and ring lengths. Note that
-			//   we can't use fwdPtr for finding a match since we don't know which DD 
-			//   level ring it ended up pointing at.
-			if (xipFuncL3RingVector==myRev64(rs4RingLayout.backItemPtr) &&
-					attrFuncL3RingLength==myRev32(deltaRingRS4->iv_length))  {
-				// Perform OR between the existing ring and attribute ring.
-				sizeRingInBytes = (attrFuncL3RingLength-1)/8 + 1;
-				bGoodByte = 1;
-				FAPI_DBG("Byte[  # ]: ER  OR =ER? ");
-				FAPI_DBG("-----------------------");
-				for (iByte=0; (iByte<sizeRingInBytes && bGoodByte); iByte++)  {
-					if (*(attrFuncL3RingData+iByte))  {
-						// Check there are 0-bits in the existing byte where there are
-						//   1-bits in the overlay byte.
-						byteExisting = *((uint8_t*)i_buf2+iByte);
-						byteOverlay  = *(&attrFuncL3RingData[0]+iByte);
-						if (byteExisting!=(byteExisting & ~byteOverlay))  {
-							FAPI_ERR("Byte[%4i]: %02x  %02x  %02x <-violation",iByte,byteExisting,byteOverlay,byteExisting&~byteOverlay);
-							bGoodByte = 0;
-							break;
-						}
-						else  {
-							FAPI_DBG("Byte[%4i]: %02x  %02x  %02x ",iByte,byteExisting,byteOverlay,byteExisting&~byteOverlay);
-						}
-						// Only update existing ring when there's content in overlay data.
-						*((uint8_t*)i_buf2+iByte) = byteExisting | byteOverlay;
-					}
-				}
-				FAPI_DBG("-----------------------");
-				if (!bGoodByte)  {
- 				  FAPI_ERR("The existing ex_l3_func_ring has 1-bits in overlay locations. ");
-					uint32_t & DATA_FAIL_BYTE_NO = iByte;
-					uint8_t & DATA_EXISTING_RING_BYTE = byteExisting;
-					uint8_t & DATA_OVERLAY_RING_BYTE = byteOverlay; 
- 				  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_L3_FUNC_OVERLAY_ERROR);
- 				  return rc;
-				}
-			}
-		}
-#endif
-
-
-#ifndef IMGBUILD_PPD_IGNORE_XIPC
-  // ==========================================================================
-  // CUSTOMIZE item:    Overlay ex_fary_l2_ring
-  // Note: Check if ex_fary_l2_ring's vector address matches current backPtr.
-  //       If so, perform OR operation with new attribute data for this ring.
-  // Assumptions:
-  // - Base ring only.
-  // - Correct DD level rings only.
-  // ==========================================================================
-  byteExisting=0, byteOverlay=0, bGoodByte=1;
-  if (bSleepEnable) {
-	// Find ring match by comparing backItemPtr and ring lengths. Note that
-	//   we can't use fwdPtr for finding a match since we don't know which DD 
-	//   level ring it ended up pointing at.
-	if (xipFaryL2RingVector==myRev64(rs4RingLayout.backItemPtr) &&
-		attrFaryL2RingLength==myRev32(deltaRingRS4->iv_length))  {
-      // Perform OR between the existing ring and attribute ring.
-      sizeRingInBytes = (attrFaryL2RingLength-1)/8 + 1;
-      bGoodByte = 1;
-      FAPI_DBG("Byte[  # ]: ER  OR =ER? ");
-      FAPI_DBG("-----------------------");
-      for (iByte=0; (iByte<sizeRingInBytes && bGoodByte); iByte++)  {
-        if (*(attrFaryL2RingData+iByte))  {
-          // Check there are 0-bits in the existing byte where there are
-          //   1-bits in the overlay byte.
-          byteExisting = *((uint8_t*)i_buf2+iByte);
-          byteOverlay  = *(&attrFaryL2RingData[0]+iByte);
-          if (byteExisting!=(byteExisting & ~byteOverlay))  {
-          	FAPI_ERR("Byte[%4i]: %02x  %02x  %02x <-violation",iByte,byteExisting,byteOverlay,byteExisting&~byteOverlay);
-          	bGoodByte = 0;
-          	break;
-          }
-          else  {
-          	FAPI_DBG("Byte[%4i]: %02x  %02x  %02x ",iByte,byteExisting,byteOverlay,byteExisting&~byteOverlay);
-          }
-          // Only update existing ring when there's content in overlay data.
-          *((uint8_t*)i_buf2+iByte) = byteExisting | byteOverlay;
-        }
-      }
-      FAPI_DBG("-----------------------");
-      if (!bGoodByte)  {
-        FAPI_ERR("The existing ex_l2_fary_ring has 1-bits in overlay locations. ");
-      	uint32_t & DATA_FAIL_BYTE_NO = iByte;
-      	uint8_t & DATA_EXISTING_RING_BYTE = byteExisting;
-      	uint8_t & DATA_OVERLAY_RING_BYTE = byteOverlay; 
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_L2_FARY_OVERLAY_ERROR);
-        return rc;
-      }
-    }
-  }
-#endif
-
-	  // ==========================================================================
-	  // Create Wiggle-Flip Programs (but first resolve max rotate status.)
-	  // ==========================================================================
-	  FAPI_DBG("--> Creating Wiggle-Flip Program.");
- 
-	  rcLoc = sbe_xip_get_scalar( (void*)i_imageIn, SCAN_MAX_ROTATE_38XXX_NAME, &scanMaxRotate);
-	  if (rcLoc)  {
-	    FAPI_INF("WARNING: sbe_xip_get_scalar() failed...but we might wing it.");
-	    if (rcLoc==SBE_XIP_ITEM_NOT_FOUND)  {
-	      FAPI_INF("Probable cause:");
-	      FAPI_INF("\tThe key word in SCAN_MAX_ROTATE_38XXX_NAME does not exist the TOC.");
-	      scanMaxRotate = SCAN_ROTATE_DEFAULT;
-			  FAPI_INF("\tscanMaxRotate set to 0x%llx", scanMaxRotate);
-				FAPI_INF("Continuing...");
-		  }
-			else  {
-				FAPI_ERR("ERROR: Nope, couldn't wing it.");
-			  uint32_t & RC_LOCAL=rcLoc;
-			  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_UNKNOWN_XIP_ERROR);
-			  return rc;
-			}
-		}
-		if (scanMaxRotate<0x20 || scanMaxRotate>SCAN_MAX_ROTATE)  {
-		  FAPI_INF("WARNING: Value of key word SCAN_MAX_ROTATE_38XXX_NAME=0x%llx is not permitted.\n",scanMaxRotate);
-	    scanMaxRotate = SCAN_ROTATE_DEFAULT;
-			FAPI_INF("\tscanMaxRotate set to 0x%llx\n", scanMaxRotate);
-			FAPI_INF("Continuing...\n");
-		}
-
-	  // Support for enforcing delay after WF scan write scoms.
-	  uint64_t waitsScanDelay=10;
-	  rcLoc = sbe_xip_get_scalar( (void*)i_imageIn, "waits_delay_for_scan", &waitsScanDelay);
-	  if (rcLoc)  {
-			FAPI_ERR("Error obtaining waits_delay_for_scan keyword.\n");
-		  uint32_t & RC_LOCAL=rcLoc;
-		  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_UNKNOWN_XIP_ERROR);
-		  return rc;
-	  }
-	
-		wfInline = (uint32_t*)i_buf1;
-		wfInlineLenInWords = i_sizeBuf1/4;
-                //WSZ query ec feature for poolling protocol for Murano/Venice >=20, Naples >=10
-                uint8_t usePollingProt = 0x00; //true 0x01 false 0x00
-                rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT, &i_target,usePollingProt);
-                if (rc) {
-                        FAPI_ERR("p8_slw_build: fapiGetAttribute error (ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT)");
-                        return rc;
-                }
-                FAPI_DBG("p8_slw_build_fixed use PollingProt = 0x%02X (true=0x01, false=0x00)", usePollingProt);
-
-	  rcLoc = create_wiggle_flip_prg( (uint32_t*)i_buf2,  // Input buffer, buf2
-	                                  ringBitLen,
-	                                  myRev32(deltaRingRS4->iv_scanSelect),
-	                                  (uint32_t)deltaRingRS4->iv_chipletId,
-	                                  &wfInline,          // Output buffer, buf1
-	                                  &wfInlineLenInWords,
-                                          deltaRingRS4->iv_flushOptimization,
-                                          (uint32_t)scanMaxRotate,
-	                                  (uint32_t)waitsScanDelay,
-                                          usePollingProt);
-	  if (rcLoc)  {
-	    FAPI_ERR("create_wiggle_flip_prg() failed w/rcLoc=%i",rcLoc);
-			uint32_t & RC_LOCAL=rcLoc;
-	    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_WF_CREATION_ERROR);
-	    return rc;
-	  }
-	  FAPI_DBG("\tWiggle-flip programming successful.");
-	  
-	
-	  // ==========================================================================
-	  // Append Wiggle-Flip programs to .rings section. (But 1st put ring block together.)
-	  // ==========================================================================
-	  FAPI_DBG("--> Building WF ring header.");
-    //
-    // Populate ring header and put ring header and Wf ring into 
-    // proper spots in pre-allocated bufWfRingBlock buffer (HB buf1).
-    //
-    DeltaRingLayout *bufWfRingBlock;
-    uint64_t entryOffsetWfRingBlock;
-    uint32_t sizeWfRingBlock, sizeWfRingBlockMax;
-
-    bufWfRingBlock = (DeltaRingLayout*)i_buf2;  // Previously contained delta ring state.
-    sizeWfRingBlockMax = i_sizeBuf2;
-
-    entryOffsetWfRingBlock      = calc_ring_layout_entry_offset( 
-                                                    1, 
-                                                    myRev32(rs4RingLayout.sizeOfMeta) );
-    bufWfRingBlock->entryOffset = myRev64(entryOffsetWfRingBlock);
-    bufWfRingBlock->sizeOfMeta  = rs4RingLayout.sizeOfMeta;
-    bufWfRingBlock->backItemPtr = rs4RingLayout.backItemPtr;
-    sizeWfRingBlock             = entryOffsetWfRingBlock +  // Must be 8-byte aligned.
-                                  wfInlineLenInWords*4;     // Must be 8-byte aligned.
-    // Quick check to see if final ring block size will fit in HB buffer.
-    if (sizeWfRingBlock>sizeWfRingBlockMax)  {
-      FAPI_ERR("WF ring block size (=%i) exceeds pre-allocated buf1 size (=%i).",
-      sizeWfRingBlock, sizeWfRingBlockMax);
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeWfRingBlock;
-      uint32_t &DATA_SIZE_OF_BUF1=sizeWfRingBlock;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_RING_BLOCK_TOO_LARGE);
-      return rc;
-    }
-    bufWfRingBlock->sizeOfThis  = myRev32(sizeWfRingBlock);
-    // Find where meta data goes.
-    bufLC = (uint32_t)( entryOffsetWfRingBlock - 
-                        myByteAlign(8, myRev32(bufWfRingBlock->sizeOfMeta)) );
-    // Copy over meta data. Do not worry about alignment here.
-    memcpy( (uint8_t*)bufWfRingBlock+bufLC, 
-            rs4RingLayout.metaData, 
-            (size_t)myRev32(rs4RingLayout.sizeOfMeta));
-    // Find where WF prg goes.
-    bufLC = (uint32_t)entryOffsetWfRingBlock;
-    // Copy over WF ring prg which is already 8-byte aligned.
-    memcpy( (uint8_t*)bufWfRingBlock+bufLC, 
-            wfInline, 
-            (size_t)wfInlineLenInWords*4);
-
-    // Now, some post-sanity checks on alignments.
-    if ( entryOffsetWfRingBlock%8 ||
-         sizeWfRingBlock%8)  {
-      FAPI_ERR("Member(s) of WF ring block are not 8-byte aligned:");
-      FAPI_ERR("  Entry offset            = %i", (uint32_t)entryOffsetWfRingBlock);
-      FAPI_ERR("  Size of ring block      = %i", sizeWfRingBlock);
-      dataTmp1=(uint32_t)entryOffsetWfRingBlock;
-      uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=dataTmp1;
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeWfRingBlock;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_RING_BLOCK_ALIGN_ERROR);
-      return rc;
-    }
-
-	  FAPI_DBG("--> Appending WF ring to .rings section.");
-		rcLoc = write_ring_block_to_image(i_imageOut,
-                                      NULL,
-                                      bufWfRingBlock,
-                                      0,
-                                      rs4RingLayout.override,
-                                      1,
-                                      sizeImageOutMax,
-                                      SBE_XIP_SECTION_RINGS,
-                                      i_buf1,     // Use buf1 as temp buf.
-                                      i_sizeBuf1);
-    if (rcLoc)  {
-      FAPI_ERR("write_ring_block_to_image() failed w/rc=%i",rcLoc);
-      FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_IMGBUILD_ERROR);
-      return rc;
-    }
-
-	  FAPI_DBG("\tUpdating image w/WF prg + ring header was successful.");
-	  
-	  countWF++;
-
-	
-	}  // End of if (rcSearch!=DSLWB_RING_SEARCH_NO_MATCH)
-	
-  // ============================================================================
-  // Are we done now?
-  // ============================================================================
-  if (bSearchDone || rcSearch==DSLWB_RING_SEARCH_EXHAUST_MATCH)  {
-    FAPI_INF("Wiggle-flip programming done.");
-    FAPI_INF("Number of wf programs appended: %i", countWF);
-    if (countWF==0)
-      FAPI_INF("ZERO WF programs appended to .rings section.");
-#ifndef IMGBUILD_PPD_IGNORE_XIPC
-    uint32_t  bootCoreMask=0x000FFFF;
-		//
-		// Do various customizations to image.
-    //
-    sizeImageTmp = sizeImageOutMax;
-		FAPI_INF("Calling xip_customize().\n");
-		FAPI_EXEC_HWP(rc, p8_xip_customize,	
-		                  i_target,
-											i_imageIn,
-											i_imageOut,
-											sizeImageTmp,
-											sysPhase,
-											i_modeBuild,
-											i_buf1,
-											i_sizeBuf1,
-											i_buf2,
-											i_sizeBuf2,
-                      bootCoreMask);
-		if (rc!=FAPI_RC_SUCCESS)  {
-    	FAPI_ERR("Xip customization failed.");
-			return rc;
-		}
-    FAPI_INF("Xip customization done.");
-#else
-	  uint32_t sizeImageOld;
-		//
-		// Initialize .slw section, just in case we ignore xip_customize in a build.
-		//
-		switch (i_modeBuild)  {
-		// --------------------------------------------------------------------
-		// case 0:  IPL mode.
-		// - This is first time SLW image is built. Go all out.
-		// --------------------------------------------------------------------
-		case P8_SLW_MODEBUILD_IPL:  // IPL mode.
-			rcLoc = create_and_initialize_fixed_image( i_imageOut);
-    	if (rcLoc)  {
-				uint32_t & RC_LOCAL=rcLoc;
-    	  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_CREATE_FIXED_IMAGE_ERROR);
-				return rc;
-    	}
-    	FAPI_INF("IPL mode build: Fixed SLW and FFDC sections allocated and SLW section initialized for Ramming and Scomming tables.");
-			break;
-	  // --------------------------------------------------------------------
-		// case 1:  Rebuild mode - Nothing to do.
-		// - Image size already fixed at 1MB during IPL mode.
-		// - Fixed positioning of .slw and .ffdc already done during IPL mode. 
-		// --------------------------------------------------------------------
-		case P8_SLW_MODEBUILD_REBUILD:  // Rebuild mode. (Need to update Ram/Scom vectors.)
-			rcLoc = create_and_initialize_fixed_image( i_imageOut);
-    	if (rcLoc)  {
-				uint32_t & RC_LOCAL=rcLoc;
-    	  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_CREATE_FIXED_IMAGE_ERROR);
-				return rc;
-    	}
-    	FAPI_INF("Rebuild mode build: Fixed SLW and FFDC sections allocated and SLW section initialized for Ramming and Scomming tables.");
-			break;
-		// --------------------------------------------------------------------
-		// case 2:  SRAM mode.
-		// - Assumption: slw_build() called by OCC.
-		// - Need to make image as slim as possible.
-		// - Do not append .fit.
-		// - Position .slw right after .rings.
-		// - Do not append .ffdc.
-		// --------------------------------------------------------------------
-		case P8_SLW_MODEBUILD_SRAM:  // SRAM mode.
-	    sizeImageOld = sizeImageTmp;
-			sizeImageTmp = sizeImageOutMax;
-    	rcLoc = initialize_slw_section( i_imageOut,
-    	                                &sizeImageTmp);
-    	if (rcLoc)  {
-    	  if (rcLoc==IMGBUILD_ERR_IMAGE_TOO_LARGE)  {
-			    uint32_t & DATA_IMG_SIZE_OLD=sizeImageOld;
-			    uint32_t & DATA_IMG_SIZE_EST=sizeImageTmp;
-				  uint32_t & DATA_IMG_SIZE_MAX=sizeImageOutMax;
-			    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_MAX_IMAGE_SIZE_EXCEEDED);
-			  }
-				else  {
-				  uint32_t & RC_LOCAL=rcLoc;
-    	    FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_APPEND_SLW_SECTION_ERROR);
-    	  }
-				return rc;
-    	}
-    	FAPI_INF("SRAM mode build: SLW section allocated for Ramming and Scomming tables.");
-			break;
-		// Default case - Should never get here.
-		default:
-			FAPI_ERR("Bad code, or bad modeBuild (=%i) parm.",i_modeBuild);
-      ffdc_temp = i_modeBuild;
-      uint8_t & MODE_BUILD=ffdc_temp;
-			FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_BAD_CODE_OR_PARM);
-			return rc;
-		}
-#endif
-
-    // Update host_runtime_scom pointer to point to sub_slw_runtime_scom
-		rcLoc = update_runtime_scom_pointer(i_imageOut);
-		if (rcLoc==IMGBUILD_ERR_KEYWORD_NOT_FOUND)  {
-			uint32_t &RC_LOCAL=rcLoc;
-			FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_KEYWORD_NOT_FOUND_ERROR);
-			return rc;
-		}
-		// Report final size.
-		sbe_xip_image_size( i_imageOut, &io_sizeImageOut);
-    FAPI_INF("Final SLW image size (should be 1MB for modeBuild={0,1}): %i", io_sizeImageOut);
-    return FAPI_RC_SUCCESS;
-  }
-
-  FAPI_DBG("nextRing (at bottom)=0x%016llx",(uint64_t)nextRing);
-    
-  }   while (nextRing!=NULL);
-  /***************************************************************************
-   *                          RING SEARCH LOOP - End                         *
-   ***************************************************************************/
-
-  FAPI_ERR("Shouldn't be in this code section. Check code.");
-  rcLoc = IMGBUILD_ERR_CHECK_CODE;
-  uint32_t & RC_LOCAL=rcLoc;
-  FAPI_SET_HWP_ERROR(rc, RC_PROC_SLWB_UNKNOWN_ERROR);
-  return rc;
-
-}
-
-} // End of extern C
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C
deleted file mode 100644
index 886d2c8db..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C
+++ /dev/null
@@ -1,2967 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_xip_customize.C,v 1.77 2015/07/27 00:31:05 jmcgill Exp $
-/*------------------------------------------------------------------------------*/
-/* *! TITLE : p8_xip_customize                                                  */
-/* *! DESCRIPTION : Obtains repair rings from VPD and adds them to either       */
-//                  IPL or SLW mainstore images.    
-/* *! OWNER NAME : Michael Olsen                  cmolsen@us.ibm.com            */
-//
-/* *! EXTENDED DESCRIPTION :                                                    */
-//
-/* *! USAGE : 
-              To build (for Hostboot) -
-              buildfapiprcd   -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c"   -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C,p8_pore_table_gen_api_fixed.C,p8_mailbox_utils.C"   -e "../../xml/error_info/p8_xip_customize_errors.xml,../../xml/error_info/p8_mailbox_utils_errors.xml,../../xml/error_info/proc_sbe_decompress_scan_halt_codes.xml,../../../../../../hwpf/working/hwp/xml/error_info/mvpd_errors.xml"   p8_xip_customize.C
-              To build (for VBU/command-line) -
-              buildfapiprcd   -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c"   -C "p8_image_help.C,p8_image_help_base.C,p8_scan_compression.C,p8_pore_table_gen_api_fixed.C,p8_mailbox_utils.C"   -e "../../xml/error_info/p8_xip_customize_errors.xml,../../xml/error_info/p8_mailbox_utils_errors.xml,../../xml/error_info/proc_sbe_decompress_scan_halt_codes.xml,../../../../../../hwpf/working/hwp/xml/error_info/mvpd_errors.xml"   -u "XIPC_COMMAND_LINE"   p8_xip_customize.C
-              Other usages -
-                            using "IMGBUILD_PPD_IGNORE_VPD" will ignore adding MVPD rings.
-                            using "IMGBUILD_PPD_IGNORE_VPD_FIELD" will ignore using fapiGetMvpdField.
-                            using "IMGBUILD_PPD_IGNORE_PLL_UPDATE" will ignore PLL attribute ring.
-                                                                                */
-//
-/* *! ASSUMPTIONS :                                                             */
-//
-/* *! COMMENTS :                                                                */
-//
-/*------------------------------------------------------------------------------*/
-#include <p8_pore_api_custom.h>
-#include <getMvpdRing.H>
-#include <fapiMvpdAccess.H>
-#include <p8_xip_customize.H>
-#include <p8_delta_scan_rw.h>
-#include <p8_ring_identification.H>
-#include <p8_pore_table_gen_api.H>
-#include <p8_scom_addresses.H>
-#include <p8_mailbox_utils.H>
-
-#define min(a,b) ((a<b)?a:b)
-
-extern "C"  {
-
-using namespace fapi;
-
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Insert the 32-bit mailbox value into the correct spot in the image
-//
-// parameters: o_imageOut         The image to modify
-//             i_tocName          The name of the entry to modify
-//             i_value            The value to insert (in host byte order)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-  ReturnCode p8_xip_customize_insert_mbox( void *o_imageOut, const char *i_tocName, uint32_t i_value )
-  {
-    void    *hostMboxVec;
-    uint8_t *byteVector;
-    fapi::ReturnCode rc;
-    uint32_t   rcLoc=0;
-    SbeXipItem xipTocItem;
-    SBE_XIP_ERROR_STRINGS(errorStrings);
-
-    rcLoc = sbe_xip_find( o_imageOut, i_tocName, &xipTocItem);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-      FAPI_ERR("Probable cause:");
-      FAPI_ERR("\tThe keyword (=%s) was not found.",i_tocName);
-      uint32_t & RC_LOCAL = rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostMboxVec);
-    FAPI_INF("%s: Before (in BE)=0x%016llX\n",i_tocName,*((uint64_t*)hostMboxVec));
-    byteVector = (uint8_t*)hostMboxVec;
-    // Copy the bytes over one by one
-    *(byteVector+0) = (uint8_t)((i_value & 0xFF000000) >> 24);
-    *(byteVector+1) = (uint8_t)((i_value & 0x00FF0000) >> 16);
-    *(byteVector+2) = (uint8_t)((i_value & 0x0000FF00) >> 8);
-    *(byteVector+3) = (uint8_t)((i_value & 0x000000FF) >> 0);
-    FAPI_INF("                         After (in BE)=0x%016llX\n",myRev64(*(uint64_t*)hostMboxVec));
-    FAPI_INF("    field value (in host)             =0x%08X\n",i_value);
-    return rc;
-  }
-
-#ifndef IMGBUILD_PPD_IGNORE_VPD
-
-  /***************************************************************************
-   *                        CHIPLET WALK LOOP - Begin                        *
-   ***************************************************************************/
-  //
-  // Walk through #G rings first, then #R rings.
-  //   iVpdType=0 : #G Repair rings
-  //   iVpdType=1 : #R Repair rings
-  // Notes about VPD rings:
-  //   - Only space for the base ring is allocated in the TOC. No override space!
-  //   - Some ex_ rings are non-core-ID-specific and will have chipletID=0xFF.
-  //     Add these rings only once!!
-  // Notes about #G rings:
-  //   - Some ex_ rings are core ID specific. Add the fwd ptr based on the core ID.
-  // Notes about $R rings:
-  //   - The ex_ rings are core ID specific. Add the fwd ptr based on the core ID.
-  //
-//  Parameter list:
-//  const fapi::Target &i_target:  Processor chip target.
-//  void      *i_imageIn:      Ptr to input img. The IPL img for IPL and the ref img for SLW.
-//  void      *o_imageOut:     Ptr to output img.
-//  uint32_t  io_sizeImageOut: In: Max size of IPL/SRAM workspace/img. Out: Final size.
-//                             MUST equal FIXED_SEEPROM_WORK_SPACE for IPL Seeprom build.
-//  uint8_t   i_sysPhase:      0: IPL  1: SLW
-//  uint8_t   i_modeBuild:     0: HB/IPL  1: PHYP/Rebuild  2: SRAM 
-//  void      *i_buf1:         Temp buffer 1 for dexed RS4 ring. Caller allocs/frees.
-//                             Space MUST equal FIXED_RING_BUF_SIZE
-//  uint32_t  i_sizeBuf1:      Size of buf1.
-//                             MUST equal FIXED_RING_BUF_SIZE
-//  void      *i_buf2:         Temp buffer 2 for WF ring. Caller allocs/frees.
-//                             Space MUST equal FIXED_RING_BUF_SIZE
-//  uint32_t  i_sizeBuf22      Size of buf2.
-//                             MUST equal FIXED_RING_BUF_SIZE
-ReturnCode p8_xip_customize_insert_chiplet_rings( const fapi::Target &i_target,
-                                                  void               *i_imageIn,
-                                                  void               *o_imageOut,
-                                                  const uint8_t       i_sysPhase,
-                                                  void               *i_buf1,
-                                                  const uint32_t      i_sizeBuf1,
-                                                  void               *i_buf2,
-                                                  const uint32_t      i_sizeBuf2,
-                                                  const uint8_t       attrDdLevel,
-                                                  const uint32_t      sizeImageMax,
-                                                  uint8_t             chipletId,
-                                                  const SbeXipSection &xipSectionDcrings
-                                                  )
-{
-  fapi::ReturnCode rcFapi, rc=FAPI_RC_SUCCESS;
-  uint32_t   rcLoc=0;
-
-  uint8_t    iVpdType;
-  RingIdList *ring_id_list=NULL;
-  uint32_t   ring_id_list_size;
-  uint32_t   iRing;
-  uint32_t   sizeVpdRing=0;
-  uint8_t    ringId;
-  uint8_t    *bufVpdRing;
-  uint32_t   ddLevel=attrDdLevel;
-  uint32_t   sizeImageOut=sizeImageMax;
-  uint8_t    chipletIdVpd;
-	
-  // Now wade through all conceivable Mvpd rings and add any that's there to the image.
-  for (iVpdType=0; iVpdType<NUM_OF_VPD_TYPES; iVpdType++)  {
-    if (iVpdType==0)  {
-      ring_id_list = (RingIdList*)RING_ID_LIST_PG;
-      ring_id_list_size = (uint32_t)RING_ID_LIST_PG_SIZE;
-    }
-    else  {
-      ring_id_list = (RingIdList*)RING_ID_LIST_PR;
-      ring_id_list_size = (uint32_t)RING_ID_LIST_PR_SIZE;
-    }
-   
-    for (iRing=0; iRing<ring_id_list_size; iRing++)  {
-      ringId = (ring_id_list+iRing)->ringId;
-      if((chipletId>=(ring_id_list+iRing)->chipIdMin && chipletId<=(ring_id_list+iRing)->chipIdMax))  {
-        FAPI_INF("(iRing,ringId,chipletId) = (%i,0x%02X,0x%02x)",iRing,ringId,chipletId);
-
-        bufVpdRing = (uint8_t*)i_buf1;
-        sizeVpdRing = i_sizeBuf1; // We always supply max buffer space for ring.
-        // 2012-11-14: CMO- A thought: Once getMvpdRing() becomes available, add 
-        //             get_mvpd_keyword() func at bottom in this file. Then
-        //             put prototype in *.H file. The func should map the
-        //             vpd keyword (0,1,2,...) to mvpd keyword in the include
-        //             file, fapiMvpdAccess.H.
-        //rcFapi = get_mvpd_keyword((ring_id_list+iRing)->vpdKeyword, mvpdKeyword);
-        //if (rcFapi)  {
-        //  FAPI_ERR("get_mvpd_keyword() returned error.");
-        //  return rcFapi;
-        //}
-        fapi::MvpdKeyword mvpd_keyword;
-        if ((ring_id_list+iRing)->vpdKeyword==VPD_KEYWORD_PDG) 
-          mvpd_keyword = MVPD_KEYWORD_PDG;
-        else
-          if ((ring_id_list+iRing)->vpdKeyword==VPD_KEYWORD_PDR)
-            mvpd_keyword = MVPD_KEYWORD_PDR;
-          else  {
-            FAPI_ERR("Unable to resolve VPD keyword from ring list table.");
-            uint8_t & DATA_RING_LIST_VPD_KEYWORD = (ring_id_list+iRing)->vpdKeyword;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_VPD_KEYWORD_RESOLVE_ERROR);
-            return rc;
-          }
-        FAPI_EXEC_HWP(rcFapi, getMvpdRing,
-                      MVPD_RECORD_CP00,
-                      mvpd_keyword,
-                      i_target,
-                      chipletId,
-                      ringId,
-                      bufVpdRing,
-                      sizeVpdRing);
-        FAPI_INF("XIPC: Mvpd rings: rcFapi=0x%08x",(uint32_t)rcFapi);
-        if (rcFapi==RC_REPAIR_RING_NOT_FOUND)  {
-          // No match, do nothing. Next ringId.
-          FAPI_INF("XIPC: Mvpd rings: (iRing,ringId,chipletId)=(%i,0x%02X,0x%02X) not found.",iRing,ringId,chipletId);
-          rcFapi = FAPI_RC_SUCCESS;
-        }
-        else  {
-          // Couple of other checks...
-          // 1. General rc error check.
-          if (rcFapi!=FAPI_RC_SUCCESS)  {
-            FAPI_ERR("getMvpdRing() returned error.");
-            return rcFapi;
-          }
-          // 2. Checking that chipletId didn't somehow get messed up.
-          chipletIdVpd = ((CompressedScanData*)bufVpdRing)->iv_chipletId;
-          if (chipletIdVpd!=chipletId)  {
-            FAPI_ERR("VPD ring's chipletId in scan container (=0x%02X) doesn't match the requested chipletId (=0x%02X).\n",chipletIdVpd,chipletId);
-            uint8_t & DATA_CHIPLET_ID_VPD = chipletIdVpd;
-            uint8_t & DATA_CHIPLET_ID_REQ = chipletId;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_CHIPLET_ID_MESS);
-            return rc;
-          }
-          // 3. Checking for buffer overflow.
-          if (sizeVpdRing>i_sizeBuf1)  {
-            // Supplied buffer from HB/PHYP is too small. Error out. Is this right
-            //   decision or should we ignore and proceed to next ring.
-            uint32_t sizeBuf1=(uint32_t)i_sizeBuf1;
-            uint32_t & DATA_RING_SIZE_REQ = sizeVpdRing;
-            uint32_t & DATA_RING_SIZE_MAX = sizeBuf1;
-            switch (iVpdType)  {
-            case 0:
-              FAPI_ERR("#G ring too large.");
-              FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PG_RING_TOO_LARGE);
-              break;
-            case 1:
-              FAPI_ERR("#R ring too large.");
-              FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PR_RING_TOO_LARGE);
-              break;
-            default:
-              uint8_t & DATA_VPD_TYPE = iVpdType;
-              FAPI_ERR("#Invalid VPD type.");
-              FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_INVALID_VPD_TYPE);
-              break;
-            }
-            return rc;
-          }
-          else  {
-            // Enforce flush optimization for Mvpd rings.
-            ((CompressedScanData*)bufVpdRing)->iv_flushOptimization = 1;
-            // Do datacare, if needed.
-            if ( xipSectionDcrings.iv_offset!=0 )  {
-              FAPI_INF("Calling check_and_perform_ring_datacare()\n");
-              rcLoc = check_and_perform_ring_datacare( 
-                                                      i_imageIn,
-                                                      (void*)bufVpdRing,  //HB buf1
-                                                      attrDdLevel,        //Playing it safe.
-                                                      i_sysPhase,
-                                                      (char*)(ring_id_list+iRing)->ringNameImg,
-                                                      (void*)i_buf2,			//HB buf2
-                                                      i_sizeBuf2);
-              if (rcLoc)  {
-                FAPI_ERR("check_and_perform_ring_datacare() failed w/rc=%i  ",rcLoc);
-                uint32_t & RC_LOCAL = rcLoc;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PERFORM_RING_DATACARE_ERROR);
-                return rc;
-              }
-            }
-            if (i_sysPhase==0)  {
-              // Check if the VPD ring is redundant
-              int redundant = 0;
-              rcLoc = rs4_redundant((CompressedScanData*)bufVpdRing, &redundant);
-              if(rcLoc) {
-                FAPI_ERR("rs4_redundant() failed w/rc=%i  ",rcLoc);
-                uint32_t & RC_LOCAL = rcLoc;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_CHECK_REDUNDANT_ERROR);
-                return rc;
-              }
-              rcLoc = 0;
-              // Add VPD ring to image if not redundant
-              if( redundant ) {
-                FAPI_INF("Skipping VPD ring because it doesn't change the ring (iRing,ringId,chipletId)=(%i,0x%02X,0x%02X).",iRing,ringId,chipletId);
-              } else {
-                // Add VPD ring to --->>> IPL <<<--- image
-                rcLoc = write_vpd_ring_to_ipl_image(
-                                                    o_imageOut,
-                                                    sizeImageOut,
-                                                    (CompressedScanData*)bufVpdRing, //HB buf1
-                                                    ddLevel,
-                                                    i_sysPhase,
-                                                    (char*)(ring_id_list+iRing)->ringNameImg,
-                                                    (void*)i_buf2,                   //HB buf2
-                                                    i_sizeBuf2,
-                                                    SBE_XIP_SECTION_RINGS);
-                if (rcLoc) {
-                  //Check if the add failed because of space issues, and return a unique error for that
-                  if (rcLoc==SBE_XIP_WOULD_OVERFLOW) {
-                    uint32_t & RC_LOCAL   = rcLoc;
-                    uint8_t  & CHIPLET_ID = chipletId;
-                    uint8_t  & RING_ID    = ringId;
-                    uint32_t & RING_SIZE  = sizeVpdRing;
-                    uint32_t & IMAGE_SIZE = sizeImageOut;
-                    FAPI_INF("Ring %s won't fit into image. Size would be %i.", (char*)(ring_id_list+iRing)->ringNameImg, sizeImageOut);
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_WRITE_WOULD_OVERFLOW);
-                    return rc;
-                  } else {
-                    FAPI_ERR("write_vpd_ring_to_ipl_image() failed w/rc=%i",rcLoc);
-                    uint32_t & RC_LOCAL = rcLoc;
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_WRITE_VPD_RING_TO_IPL_IMAGE_ERROR);
-                    return rc;
-                  }
-                }
-              } //if not redundant
-            }
-            else  {
-              // Add VPD ring to --->>> SLW <<<--- image
-             //WSZ query ec feature for poolling protocol for Murano/Venice >=20, Naples >=10
-             uint8_t usePollingProt = 0x00; //true 0x01 false 0x00
-             rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT, &i_target,usePollingProt);
-             if (rc) {
-                     FAPI_ERR("p8_xip_customize: fapiGetAttribute error (ATTR_CHIP_EC_FEATURE_USE_POLLING_PROT)");
-                     return rc;
-             }
-             FAPI_DBG("p8_xip_customize  usePollingProt = 0x%02X (true=0x01, false=0x00)", usePollingProt);
-                    
-
-              rcLoc = write_vpd_ring_to_slw_image(
-                                                  o_imageOut,
-                                                  sizeImageOut,
-                                                  (CompressedScanData*)bufVpdRing, //HB buf1
-                                                  ddLevel,
-                                                  usePollingProt,
-                                                  i_sysPhase,
-                                                  (char*)(ring_id_list+iRing)->ringNameImg,
-                                                  (void*)i_buf2,                   //HB buf2
-                                                  i_sizeBuf2,
-                                                  (ring_id_list+iRing)->bWcSpace);
-              if (rcLoc)  {
-                FAPI_ERR("write_vpd_ring_to_slw_image() failed w/rc=%i",rcLoc);
-                uint32_t & RC_LOCAL = rcLoc;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_WRITE_VPD_RING_TO_SLW_IMAGE_ERROR);
-                return rc;
-              }
-
-            }
-          } //no buffer overflow
-        } //ring found in VPD
-      } //chiplet ID is valid for this ring name
-    } //loop on ring names
-  } //loop on VPD types
-  return rc;
-}
-#endif
-
-
-//  Parameter list:
-//  const fapi::Target &i_target:  Processor chip target.
-//  void      *i_imageIn:      Ptr to input img. The IPL img for IPL and the ref img for SLW.
-//  void      *o_imageOut:     Ptr to output img.
-//  uint32_t  io_sizeImageOut: In: Max size of IPL/SRAM workspace/img. Out: Final size.
-//                             MUST equal FIXED_SEEPROM_WORK_SPACE for IPL Seeprom build.
-//  uint8_t   i_sysPhase:      0: IPL  1: SLW
-//  uint8_t   i_modeBuild:     0: HB/IPL  1: PHYP/Rebuild  2: SRAM 
-//  void      *i_buf1:         Temp buffer 1 for dexed RS4 ring. Caller allocs/frees.
-//                             Space MUST equal FIXED_RING_BUF_SIZE
-//  uint32_t  i_sizeBuf1:      Size of buf1.
-//                             MUST equal FIXED_RING_BUF_SIZE
-//  void      *i_buf2:         Temp buffer 2 for WF ring. Caller allocs/frees.
-//                             Space MUST equal FIXED_RING_BUF_SIZE
-//  uint32_t  i_sizeBuf22      Size of buf2.
-//                             MUST equal FIXED_RING_BUF_SIZE
-//  uint32_t  &io_bootCoreMask In: Mask of the desired boot cores (bits 16:31 = EX0:EX15)
-//                                 (value is ignored when i_sysPhase != 0)
-//                             Out: Mask of the valid boot cores in the image
-//
-ReturnCode p8_xip_customize( const fapi::Target &i_target,
-                             void            *i_imageIn,
-                             void            *o_imageOut,
-                             uint32_t        &io_sizeImageOut,
-                             const uint8_t   i_sysPhase,
-                             const uint8_t   i_modeBuild,
-                             void            *i_buf1,
-                             const uint32_t  i_sizeBuf1,
-                             void            *i_buf2,
-                             const uint32_t  i_sizeBuf2,
-                             uint32_t        &io_bootCoreMask)
-{
-  fapi::ReturnCode rcFapi, rc=FAPI_RC_SUCCESS;
-  uint32_t   rcLoc=0;
-  uint32_t   sizeImage, sizeImageIn, sizeImageOutMax, sizeImageMax;
-  uint32_t   iVec=0;
-  uint8_t    attrDdLevel=0;
-  uint64_t   attrCombGoodVec[MAX_CHIPLETS]={ (uint64_t(0xfedcba98)<<32)+0x76543210 };
-  void       *hostCombGoodVec;
-  SbeXipItem xipTocItem;
-  uint32_t   attrL2RT0Eps, attrL2RT1Eps, attrL2RT2Eps, attrL2WEps;
-  uint8_t    attrL2ForceRT2Eps;
-  uint32_t   attrL3RT0Eps, attrL3RT1Eps, attrL3RT2Eps, attrL3WEps;
-  uint8_t    attrL3ForceRT2Eps;
-  uint64_t   attrL3BAR1, attrL3BAR2, attrL3BARMask;
-  uint64_t   scomData;
-  uint8_t    coreId, bScomEntry;
-  uint32_t   sizeImageTmp;
-  uint64_t   ptrTmp1, ptrTmp2;
-  uint32_t   dataTmp1, dataTmp2, dataTmp3;
-  bool       largeSeeprom = false;
-  uint8_t    seepromAddrBytes = 0;
-  const uint32_t   desiredBootCoreMask = (i_sysPhase==0)?io_bootCoreMask:0x0000FFFF;
-  uint8_t    ffdc_temp;
-
-  FAPI_INF("Desired boot core mask is 0x%08X, io_bootCoreMask is 0x%08X", desiredBootCoreMask, io_bootCoreMask);
-
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  sizeImageOutMax = io_sizeImageOut;
-  
-	// First, get the system DD level. We'll need it several places.
-  rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_EC, &i_target, attrDdLevel);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET_PRIVILEGED() failed w/rc=%i and ddLevel=0x%02x",(uint32_t)rc,attrDdLevel);
-    return rc;
-  }
-
-	// Check I2C address size to see if we need to use large seeprom support
-  rc = FAPI_ATTR_GET(ATTR_SBE_SEEPROM_I2C_ADDRESS_BYTES, &i_target, seepromAddrBytes);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET failed w/rc=%i and seepromAddrBytes=0x%02x",(uint32_t)rc,seepromAddrBytes);
-    return rc;
-  }
-  if(seepromAddrBytes > 0x02) {
-    FAPI_INF("Using large seeprom support when building seeprom image. This image will not work with real SBE");
-    largeSeeprom = true;
-  }
-
-  // ==========================================================================
-  // Check and copy (if IPL phase) image to mainstore and clean it up.
-  // ==========================================================================
-  //
-  // First, check supplied size and validation of input EPROM image.
-  //
-  sbe_xip_image_size(i_imageIn, &sizeImageIn);
-  rcLoc = sbe_xip_validate(i_imageIn, sizeImageIn);
-  if (rcLoc)  {
-    FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_INTERNAL_IMAGE_ERR);
-    return rc;
-  }
-  FAPI_INF("Input image:\n  location=0x%016llx\n  size=%i=0x%x\n",
-     (uint64_t)i_imageIn, sizeImageIn, sizeImageIn);
-
-  // Second, if IPL phase, check image and buffer sizes and copy input image to 
-  //   output mainstore [work] location.
-	// Note, we don't do this for SLW since it was already done in slw_build().
-  //    
-  if (i_sysPhase==0)  {
-    FAPI_INF("Output image:\n  location=0x%016llx\n  size (max)=%i\n",
-      (uint64_t)o_imageOut, sizeImageOutMax);
-    //
-    // First, we'll check image size.
-    //
-    if (sizeImageOutMax!=FIXED_SEEPROM_WORK_SPACE)  {
-      FAPI_ERR("Max work space for output image (=%i) is not equal to FIXED_SEEPROM_WORK_SPACE (=%i).\n",
-        sizeImageOutMax,FIXED_SEEPROM_WORK_SPACE);
-      sizeImageTmp = FIXED_SEEPROM_WORK_SPACE;
-      uint32_t & DATA_IMG_SIZE_MAX = sizeImageOutMax;
-      uint32_t & DATA_IMG_SIZE_WORK_SPACE = sizeImageTmp;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMAGE_WORK_SPACE_MESS);
-      return rc;
-    }
-    if (sizeImageOutMax<sizeImageIn)  {
-      FAPI_ERR("Max output image size (=%i) is smaller than input image size (=%i).",
-        sizeImageOutMax,sizeImageIn);
-      uint32_t & DATA_IMG_SIZE = sizeImageIn;
-      uint32_t & DATA_IMG_SIZE_MAX = sizeImageOutMax;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMAGE_SIZE_MESS);
-      return rc;
-    }
-    memcpy( o_imageOut, i_imageIn, sizeImageIn);
-    sbe_xip_image_size(o_imageOut, &sizeImage);
-    rcLoc = sbe_xip_validate(o_imageOut, sizeImage);
-    if (rcLoc)  {
-      FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-      uint32_t & RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_MS_INTERNAL_IMAGE_ERR);
-      return rc;
-    }
-    if (sizeImage!=sizeImageIn)  {
-      FAPI_ERR("Size obtained from image's header (=%i) differs from supplied size (=%i).",
-        sizeImage,sizeImageIn);
-      uint32_t & DATA_IMG_SIZE_INP = sizeImageIn;
-      uint32_t & DATA_IMG_SIZE = sizeImage;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_MS_IMAGE_SIZE_MISMATCH);
-      return rc;
-    }
-    //
-    // Next, we'll check the ring buffers.
-    //
-    if (!i_buf1 || !i_buf2)  {
-      FAPI_ERR("The [assumed] pre-allocated ring buffers, i_buf1/2, do not exist.");
-      ptrTmp1 = (uint64_t)i_buf1;
-      ptrTmp2 = (uint64_t)i_buf2;
-      uint64_t & DATA_BUF1_PTR = ptrTmp1;
-      uint64_t & DATA_BUF2_PTR = ptrTmp2;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_BUF_PTR_ERROR);
-      return rc;
-    }
-    if (i_sizeBuf1!=FIXED_RING_BUF_SIZE || i_sizeBuf2!=FIXED_RING_BUF_SIZE)  {
-      FAPI_ERR("Supplied ring buffer size(s) differs from agreed upon fixed size.");
-      FAPI_ERR("Supplied ring buf1 size: %i",i_sizeBuf1);
-      FAPI_ERR("Supplied ring buf2 size: %i",i_sizeBuf2);
-      FAPI_ERR("Agreed upon fixed ring buf size: %i",FIXED_RING_BUF_SIZE);
-      dataTmp1 = i_sizeBuf1;
-      dataTmp2 = i_sizeBuf2;
-      dataTmp3 = FIXED_RING_BUF_SIZE;
-      uint32_t & DATA_BUF1_SIZE = dataTmp1;
-      uint32_t & DATA_BUF2_SIZE = dataTmp2;
-      uint32_t & DATA_BUF_SIZE_FIXED = dataTmp3;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_BUF_SIZE_NOT_FIXED);
-      return rc;
-    }
-  }
-
-
-  // ==========================================================================
-  // ==========================================================================
-  //                                     *---------*
-  //                    CUSTOMIZATION OF | VECTORS |
-  //                                     *---------*
-  // ==========================================================================
-  // ==========================================================================  
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Combined good vectors update.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL and SLW sysPhase.
-  // Note: The 32 vectors are listed in order from chiplet 0x00 to 0x1f.
-  // Note: We will use the content of these vectors to determine if each
-  //       chiplet is functional. This is to avoid the messy "walking the
-  //       chiplets approach" using fapiGetChildChiplets().
-  // ==========================================================================
-  
-  rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE, &i_target, attrCombGoodVec);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE) returned error.\n");
-    return rc;
-  }
-  //Make sure we always enable the pervasive chiplet
-  attrCombGoodVec[0] = 0x0f18000000000000ull;
-  attrCombGoodVec[1] = 0x0f18000000000000ull;
-  rcLoc = sbe_xip_find( o_imageOut, COMBINED_GOOD_VECTORS_TOC_NAME, &xipTocItem);
-  if (rcLoc)  {
-    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-    FAPI_ERR("Probable cause:");
-    FAPI_ERR("\tThe keyword (=%s) was not found.",COMBINED_GOOD_VECTORS_TOC_NAME);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-    return rc;
-  }
-  sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostCombGoodVec);
-  FAPI_INF("Dumping [initial] global variable content of combined_good_vectors, then the updated value:\n");
-  for (iVec=0; iVec<MAX_CHIPLETS; iVec++)  {
-    FAPI_INF("combined_good_vectors[%2i]: Before=0x%016llX\n",iVec,myRev64(*((uint64_t*)hostCombGoodVec+iVec)));
-    *((uint64_t*)hostCombGoodVec+iVec) = myRev64(attrCombGoodVec[iVec]);
-    FAPI_INF("                             After=0x%016llX\n",myRev64(*((uint64_t*)hostCombGoodVec+iVec)));
-  }
-  
-  
-  // ==========================================================================
-  // CUSTOMIZE item:    L2 "single member mode" enable.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL and SLW sysPhase.
-  // Note: Governs if which cores' L2  may be flipped into single member mode.
-  // ==========================================================================
-  
-  uint32_t   attrL2SingleMember=0;
-  void       *hostL2SingleMember;
-  rc = FAPI_ATTR_GET(ATTR_EX_L2_SINGLE_MEMBER_ENABLE, &i_target, attrL2SingleMember);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_EX_L2_SINGLE_MEMBER_ENABLE) returned error.\n");
-    return rc;
-  }
-  rcLoc = sbe_xip_find( o_imageOut, L2_SINGLE_MEMBER_ENABLE_TOC_NAME, &xipTocItem);
-  if (rcLoc)  {
-    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-    FAPI_ERR("Probable cause:");
-    FAPI_ERR("\tThe keyword (=%s) was not found.",L2_SINGLE_MEMBER_ENABLE_TOC_NAME);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-    return rc;
-  }
-  sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostL2SingleMember);
-  FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-						L2_SINGLE_MEMBER_ENABLE_TOC_NAME);
-  FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostL2SingleMember));
-  *(uint64_t*)hostL2SingleMember = myRev64((uint64_t)attrL2SingleMember<<32);
-  FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostL2SingleMember));
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Sleep enable
-  // Retrieval method:  Attribute.
-  // System phase:      IPL and SLW sysPhase.
-  // ==========================================================================
-  
-  uint8_t   attrSleepEnable=1;
-  void       *hostSleepEnable;
-  rc = FAPI_ATTR_GET(ATTR_PM_SLEEP_ENABLE, NULL, attrSleepEnable);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_PM_SLEEP_ENABLE) returned error.\n");
-    return rc;
-  }
-  rcLoc = sbe_xip_find( o_imageOut, PM_SLEEP_ENABLE_TOC_NAME, &xipTocItem);
-  if (rcLoc)  {
-    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-    FAPI_ERR("Probable cause:");
-    FAPI_ERR("\tThe keyword (=%s) was not found.", PM_SLEEP_ENABLE_TOC_NAME);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-    return rc;
-  }
-  sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostSleepEnable);
-  FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-           PM_SLEEP_ENABLE_TOC_NAME);
-  FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostSleepEnable));
-  *(uint64_t*)hostSleepEnable = myRev64((uint64_t)attrSleepEnable);
-  FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostSleepEnable));
-
-  
-  // ==========================================================================
-  // CUSTOMIZE item:    Security setup.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // Note: TBD
-  // ==========================================================================
-
-	if (i_sysPhase==0)  {
-	  uint64_t   attrSecuritySetupVec=0;
-		void       *hostSecuritySetupVec;
-	  rc = FAPI_ATTR_GET(ATTR_PROC_SECURITY_SETUP_VECTOR, &i_target, attrSecuritySetupVec);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_SECURITY_SETUP_VECTOR) returned error.\n");
-	    return rc;
-	  }
-	  rcLoc = sbe_xip_find( o_imageOut, SECURITY_SETUP_VECTOR_TOC_NAME, &xipTocItem);
-	  if (rcLoc)  {
-	    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-	    FAPI_ERR("Probable cause:");
-	    FAPI_ERR("\tThe keyword (=%s) was not found.",SECURITY_SETUP_VECTOR_TOC_NAME);
-	    uint32_t & RC_LOCAL = rcLoc;
-	    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-	    return rc;
-	  }
-	  sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostSecuritySetupVec);
-	  FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-							SECURITY_SETUP_VECTOR_TOC_NAME);
-	  FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostSecuritySetupVec));
-	  *(uint64_t*)hostSecuritySetupVec = myRev64(attrSecuritySetupVec);
-	  FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostSecuritySetupVec));
-	}
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    DMI PLL ring modification offsets.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // Note: TBD
-  // ==========================================================================
-
-	if (i_sysPhase==0)  {
-        // refclk sel
-        fapi::ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset = {0};
-        void       *hostDMIRefclockSelVec;
-        uint64_t   *hostDMIRefclockSelVec_field;
-        rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset);
-        if (rc)
-        {
-            FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET) returned error.\n");
-            return rc;
-        }
-        rcLoc = sbe_xip_find( o_imageOut, PB_BNDY_DMIPLL_REFCLK_SEL_TOC_NAME, &xipTocItem);
-        if (rcLoc)
-        {
-            FAPI_INF("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-            FAPI_INF("Probable cause:");
-            FAPI_INF("\tThe keyword (=%s) was not found.", PB_BNDY_DMIPLL_REFCLK_SEL_TOC_NAME);
-            rcLoc = 0;
-        }
-        else
-        {
-            sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostDMIRefclockSelVec);
-            FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-                     PB_BNDY_DMIPLL_REFCLK_SEL_TOC_NAME);
-
-            FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostDMIRefclockSelVec));
-            hostDMIRefclockSelVec_field = (uint64_t*)hostDMIRefclockSelVec;
-
-            for (size_t i = 0; i < 8; i++)
-            {
-                *(hostDMIRefclockSelVec_field + i) = myRev64(refclksel_offset[i]);
-            }
-            FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostDMIRefclockSelVec));
-        }
-
-
-        // pfd360
-        fapi::ATTR_PROC_DMI_CUPLL_PFD360_OFFSET_Type pfd360_offset = {0};
-        void       *hostDMIPFD360Vec;
-        uint64_t   *hostDMIPFD360Vec_field;
-        rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset);
-        if (rc)
-        {
-            FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_PFD360_OFFSET) returned error.\n");
-            return rc;
-        }
-        rcLoc = sbe_xip_find( o_imageOut, PB_BNDY_DMIPLL_PFD360_TOC_NAME, &xipTocItem);
-        if (rcLoc)
-        {
-            FAPI_INF("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-            FAPI_INF("Probable cause:");
-            FAPI_INF("\tThe keyword (=%s) was not found.", PB_BNDY_DMIPLL_PFD360_TOC_NAME);
-            rcLoc = 0;
-        }
-        else
-        {
-            sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostDMIPFD360Vec);
-            FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-                     PB_BNDY_DMIPLL_PFD360_TOC_NAME);
-
-            FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostDMIPFD360Vec));
-            hostDMIPFD360Vec_field = (uint64_t*)hostDMIPFD360Vec;
-
-            for (size_t i = 0; i < 8; i++)
-            {
-                *(hostDMIPFD360Vec_field + i) = myRev64(pfd360_offset[i]);
-            }
-            FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostDMIPFD360Vec));
-        }
-    }
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    ABUS PLL ring modification offsets.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // Note: TBD
-  // ==========================================================================
-
-	if (i_sysPhase==0)  {
-        // refclk sel
-        fapi::ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset = {0};
-        void       *hostAbusRefclockSelVec;
-        uint64_t   *hostAbusRefclockSelVec_field;
-        rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset);
-        if (rc)
-        {
-            FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET) returned error.\n");
-            return rc;
-        }
-        rcLoc = sbe_xip_find( o_imageOut, AB_BNDY_PLL_REFCLK_SEL_TOC_NAME, &xipTocItem);
-        if (rcLoc)
-        {
-            FAPI_INF("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-            FAPI_INF("Probable cause:");
-            FAPI_INF("\tThe keyword (=%s) was not found.", AB_BNDY_PLL_REFCLK_SEL_TOC_NAME);
-            rcLoc = 0;
-        }
-        else
-        {
-            sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostAbusRefclockSelVec);
-            FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-                     AB_BNDY_PLL_REFCLK_SEL_TOC_NAME);
-
-            FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostAbusRefclockSelVec));
-            hostAbusRefclockSelVec_field = (uint64_t*)hostAbusRefclockSelVec;
-
-            for (size_t i = 0; i < 3; i++)
-            {
-                *(hostAbusRefclockSelVec_field + i) = myRev64(refclksel_offset[i]);
-            }
-            FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostAbusRefclockSelVec));
-        }
-
-        // pfd360
-        fapi::ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET_Type pfd360_offset = {0};
-        void       *hostAbusPFD360Vec;
-        uint64_t   *hostAbusPFD360Vec_field;
-        rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset);
-        if (rc)  {
-            FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET) returned error.\n");
-            return rc;
-        }
-        rcLoc = sbe_xip_find( o_imageOut, AB_BNDY_PLL_PFD360_TOC_NAME, &xipTocItem);
-        if (rcLoc)
-        {
-            FAPI_INF("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-            FAPI_INF("Probable cause:");
-            FAPI_INF("\tThe keyword (=%s) was not found.", AB_BNDY_PLL_PFD360_TOC_NAME);
-            rcLoc = 0;
-        }
-        else
-        {
-            sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostAbusPFD360Vec);
-            FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-                     AB_BNDY_PLL_PFD360_TOC_NAME);
-
-            FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostAbusPFD360Vec));
-            hostAbusPFD360Vec_field = (uint64_t*)hostAbusPFD360Vec;
-
-            for (size_t i = 0; i < 3; i++)
-            {
-                *(hostAbusPFD360Vec_field + i) = myRev64(pfd360_offset[i]);
-            }
-            FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostAbusPFD360Vec));
-        }
-    }
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Untrusted bar settings
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // Note: TBD
-  // ==========================================================================
-
-	if (i_sysPhase==0)  {
-	  uint64_t   attrAduUntrustedBarBase;
-    uint64_t   attrAduUntrustedBarSize;
-
-	  uint64_t   attrPbaUntrustedBarBase;
-    uint64_t   attrPbaUntrustedBarSize;
-
-	  uint64_t   attrPsiUntrustedBar0Base;
-    uint64_t   attrPsiUntrustedBar0Size;
-
-	  uint64_t   attrPsiUntrustedBar1Base;
-    uint64_t   attrPsiUntrustedBar1Size;
-    
-		void       *hostAduUntrustedBar;
-    uint64_t   *untrustbar_field;
-
-    //-------------------------------------------------------------------------------------------
-    // ADU BAR
-	  rc = FAPI_ATTR_GET(ATTR_PROC_ADU_UNTRUSTED_BAR_BASE_ADDR, &i_target, attrAduUntrustedBarBase);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_ADU_UNTRUSTED_BAR_BASE_ADDR) returned error.\n");
-	    return rc;
-	  }
-
-	  rc = FAPI_ATTR_GET(ATTR_PROC_ADU_UNTRUSTED_BAR_SIZE, &i_target, attrAduUntrustedBarSize);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_ADU_UNTRUSTED_BAR_SIZE) returned error.\n");
-	    return rc;
-	  }
-
-    //-------------------------------------------------------------------------------------------
-    // PBA BAR
-	  rc = FAPI_ATTR_GET(ATTR_PROC_PBA_UNTRUSTED_BAR_BASE_ADDR, &i_target, attrPbaUntrustedBarBase);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PBA_UNTRUSTED_BAR_BASE_ADDR) returned error.\n");
-	    return rc;
-	  }
-
-	  rc = FAPI_ATTR_GET(ATTR_PROC_PBA_UNTRUSTED_BAR_SIZE, &i_target, attrPbaUntrustedBarSize);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PBA_UNTRUSTED_BAR_SIZE) returned error.\n");
-	    return rc;
-	  }
-
-    //-------------------------------------------------------------------------------------------
-    // PSI BAR0
-	  rc = FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR, &i_target, attrPsiUntrustedBar0Base);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR0_BASE_ADDR) returned error.\n");
-	    return rc;
-	  }
-
-	  rc = FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR0_SIZE, &i_target, attrPsiUntrustedBar0Size);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR0_SIZE) returned error.\n");
-	    return rc;
-	  }
-
-    //-------------------------------------------------------------------------------------------
-    // PSI BAR1
-	  rc = FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR, &i_target, attrPsiUntrustedBar1Base);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR1_BASE_ADDR) returned error.\n");
-	    return rc;
-	  }
-
-	  rc = FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR1_SIZE, &i_target, attrPsiUntrustedBar1Size);
-	  if (rc)  {
-	    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PSI_UNTRUSTED_BAR1_SIZE) returned error.\n");
-	    return rc;
-	  }
-
-    //------------------------------------------------------------------------------------------
-    //Look up fabric_config location
-	  rcLoc = sbe_xip_find( o_imageOut, UNTRUSTED_BAR_TOC_NAME, &xipTocItem);
-	  if (rcLoc)  {
-	    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-	    FAPI_ERR("Probable cause:");
-	    FAPI_ERR("\tThe keyword (=%s) was not found.",UNTRUSTED_BAR_TOC_NAME);
-	    uint32_t & RC_LOCAL = rcLoc;
-	    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-	    return rc;
-	  }
-	  sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostAduUntrustedBar);
-    untrustbar_field = (uint64_t*)hostAduUntrustedBar;
-	  FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-							UNTRUSTED_BAR_TOC_NAME);
-
-	  *(untrustbar_field + 0) = myRev64(attrAduUntrustedBarBase);
-	  *(untrustbar_field + 1) = myRev64(attrAduUntrustedBarSize);
-
- 	  *(untrustbar_field + 2) = myRev64(attrPsiUntrustedBar0Base);
-	  *(untrustbar_field + 3) = myRev64(attrPsiUntrustedBar0Size);
-
- 	  *(untrustbar_field + 4) = myRev64(attrPsiUntrustedBar1Base);
-	  *(untrustbar_field + 5) = myRev64(attrPsiUntrustedBar1Size);
-
-   //Look up fabric_config_pba location
-	  rcLoc = sbe_xip_find( o_imageOut, UNTRUSTED_PBA_BAR_TOC_NAME, &xipTocItem);
-	  if (rcLoc)  {
-	    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-	    FAPI_ERR("Probable cause:");
-	    FAPI_ERR("\tThe keyword (=%s) was not found.",UNTRUSTED_PBA_BAR_TOC_NAME);
-	    uint32_t & RC_LOCAL = rcLoc;
-	    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-	    return rc;
-	  }
-	  sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostAduUntrustedBar);
-    untrustbar_field = (uint64_t*)hostAduUntrustedBar;
-	  FAPI_INF("Dumping [initial] global variable content of %s, and then the updated value:\n",
-							UNTRUSTED_PBA_BAR_TOC_NAME);
-
-	  *(untrustbar_field + 0) = myRev64(attrPbaUntrustedBarBase);
-	  *(untrustbar_field + 1) = myRev64(attrPbaUntrustedBarSize);
-
-	}
-
-
-#ifndef IMGBUILD_PPD_IGNORE_VPD_FIELD
-  void     *hostPibmemRepairVec, *hostNestSkewAdjVec;
-  uint8_t  *bufVpdField;
-  uint32_t sizeVpdField=0;
-  uint8_t  *byteField, *byteVector;
-  // ==========================================================================
-  // CUSTOMIZE item:    Update 20 swizzled bits for PIB repair vector.
-  // Retrieval method:  MVPD field.
-  // System phase:      IPL sysPhase.
-  // Note:  Mvpd field data is returned in BE format.
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    bufVpdField = (uint8_t*)i_buf1;
-    sizeVpdField = i_sizeBuf1; // We have to use fixed and max size buffer.
-    rcFapi = fapiGetMvpdField(  MVPD_RECORD_CP00,
-                                MVPD_KEYWORD_PB,
-                                i_target,
-                                bufVpdField,
-                                sizeVpdField);
-    if (rcFapi)  {
-      FAPI_ERR("fapiGetMvpdField() w/keyword=PB returned error.");
-      return rcFapi;
-    }
-    rcLoc = sbe_xip_find( o_imageOut, PROC_PIB_REPR_VECTOR_TOC_NAME, &xipTocItem);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-      FAPI_ERR("Probable cause:");
-      FAPI_ERR("\tThe keyword (=%s) was not found.",PROC_PIB_REPR_VECTOR_TOC_NAME);
-      uint32_t & RC_LOCAL = rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    if (sizeVpdField!=5)  {
-      FAPI_ERR("fapiGetMvpdField() w/keyword=PB returned sizeVpdField=%i but we expected size=5.",sizeVpdField);
-      uint32_t & DATA_SIZE_VPD_FIELD = sizeVpdField;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_UNEXPECTED_FIELD_SIZE);
-      return rc;
-    }
-    FAPI_INF("Dumping global variable content of pibmem_repair_vector:\n");
-    sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostPibmemRepairVec);
-    FAPI_INF("pibmem_repair_vector:Before (in BE)=0x%016llX\n",*(uint64_t*)hostPibmemRepairVec);
-    byteField  = (uint8_t*)bufVpdField;
-    byteVector = (uint8_t*)hostPibmemRepairVec;
-    // Copy the bytes over one by one, skipping first byte (version indicator). 
-    *(byteVector+0) = *(byteField+1);
-    *(byteVector+1) = *(byteField+2);
-    *(byteVector+2) = *(byteField+3);
-    *(byteVector+3) = *(byteField+4);
-    FAPI_INF("                      After (in BE)=0x%016llX\n",*(uint64_t*)hostPibmemRepairVec);
-    FAPI_INF("VPD field value (unalterd & in BE))=0x%016llX\n",*(uint64_t*)bufVpdField);
-  }
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Update nest skewadjust vector.
-  // Retrieval method:  MVPD field.
-  // System phase:      IPL sysPhase.
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    bufVpdField = (uint8_t*)i_buf1;
-    sizeVpdField = i_sizeBuf1; // We have to use fixed and max size buffer.
-    rcFapi = fapiGetMvpdField(  MVPD_RECORD_CP00,
-                                MVPD_KEYWORD_MK,
-                                i_target,
-                                bufVpdField,
-                                 sizeVpdField);
-    if (rcFapi)  {
-      FAPI_ERR("fapiGetMvpdField() w/keyword=MK returned error.");
-      return rcFapi;
-    }
-    rcLoc = sbe_xip_find( o_imageOut, NEST_SKEWADJUST_VECTOR_TOC_NAME, &xipTocItem);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-      FAPI_ERR("Probable cause:");
-      FAPI_ERR("\tThe keyword (=%s) was not found.",NEST_SKEWADJUST_VECTOR_TOC_NAME);
-      uint32_t & RC_LOCAL = rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    if (sizeVpdField!=5)  {
-      FAPI_ERR("fapiGetMvpdField() w/keyword=MK returned sizeVpdField=%i but we expected size=5.",sizeVpdField);
-      uint32_t & DATA_SIZE_VPD_FIELD = sizeVpdField;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_UNEXPECTED_FIELD_SIZE);
-      return rc;
-    }
-    FAPI_INF("Dumping global variable content of nest_skewadjust_vector:\n");
-    sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostNestSkewAdjVec);
-    FAPI_INF("nest_skewadjust_vector: Before (in BE)=0x%016llX\n",*((uint64_t*)hostNestSkewAdjVec));
-    byteField  = (uint8_t*)bufVpdField;
-    byteVector = (uint8_t*)hostNestSkewAdjVec;
-    // Copy the bytes over one by one, skipping first byte (version indicator). 
-    *(byteVector+0) = *(byteField+1);
-    *(byteVector+1) = *(byteField+2);
-    *(byteVector+2) = *(byteField+3);
-    *(byteVector+3) = *(byteField+4);
-    FAPI_INF("                         After (in BE)=0x%016llX\n",*(uint64_t*)hostNestSkewAdjVec);
-    FAPI_INF("VPD field value (unaltered & in BE)   =0x%016llX\n",*(uint64_t*)bufVpdField);
-  }
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Insert the standalone mbox 0-3 register values
-  // Retrieval method:  Attributes
-  // System phase:      IPL sysPhase
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    uint32_t mboxValue = 0;
-
-    //MBOX 0 (Note: utils functions number them 1-4, not 0-3)
-    rc = p8_mailbox_utils_get_mbox1(i_target, mboxValue);
-    if( rc ) {
-      FAPI_ERR("Getting the MBOX 0 value failed, so returning the error");
-      return rc;
-    }
-
-    rc = p8_xip_customize_insert_mbox( o_imageOut, STANDALONE_MBOX0_VALUE_TOC_NAME, mboxValue );
-    if( rc ) {
-      FAPI_ERR("Putting the MBOX 0 value into the image failed, so returning the error");
-      return rc;
-    }
-
-    //MBOX 1 (Note: utils functions number them 1-4, not 0-3)
-    rc = p8_mailbox_utils_get_mbox2(i_target, mboxValue);
-    if( rc ) {
-      FAPI_ERR("Getting the MBOX 1 value failed, so returning the error");
-      return rc;
-    }
-
-    rc = p8_xip_customize_insert_mbox( o_imageOut, STANDALONE_MBOX1_VALUE_TOC_NAME, mboxValue );
-    if( rc ) {
-      FAPI_ERR("Putting the MBOX 1 value into the image failed, so returning the error");
-      return rc;
-    }
-
-    //MBOX 2 (Note: utils functions number them 1-4, not 0-3)
-    rc = p8_mailbox_utils_get_mbox3(i_target, mboxValue);
-    if( rc ) {
-      FAPI_ERR("Getting the MBOX 2 value failed, so returning the error");
-      return rc;
-    }
-
-    rc = p8_xip_customize_insert_mbox( o_imageOut, STANDALONE_MBOX2_VALUE_TOC_NAME, mboxValue );
-    if( rc ) {
-      FAPI_ERR("Putting the MBOX 2 value into the image failed, so returning the error");
-      return rc;
-    }
-
-    //MBOX 3 (Note: utils functions number them 1-4, not 0-3)
-    //Don't want to include the fabric configuration info in the SBE image,
-    //because that would cause Stradale problems
-    rc = p8_mailbox_utils_get_mbox4(i_target, mboxValue, false);
-    if( rc ) {
-      FAPI_ERR("Getting the MBOX 3 value failed, so returning the error");
-      return rc;
-    }
-
-    rc = p8_xip_customize_insert_mbox( o_imageOut, STANDALONE_MBOX3_VALUE_TOC_NAME, mboxValue );
-    if( rc ) {
-      FAPI_ERR("Putting the MBOX 3 value into the image failed, so returning the error");
-      return rc;
-    }
-
-  } //IF sysPhase == 0
-#endif
-
-
-  // ==========================================================================
-  // ==========================================================================
-  //                                     *-------*
-  //                    CUSTOMIZATION OF | RINGS | SECTION
-  //                                     *-------*
-  // ==========================================================================
-  // ==========================================================================
-
-
-#ifndef IMGBUILD_PPD_IGNORE_PLL_UPDATE
-  // ==========================================================================
-  // CUSTOMIZE item:    Update PLL ring (perv_bndy_pll_ring_alt).
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    uint32_t  tmp32Const1, tmp32Const2;
-    uint8_t   attrRingFlush[PERV_BNDY_PLL_RING_SIZE]={0};
-    uint8_t   attrRingData[PERV_BNDY_PLL_RING_SIZE]={0};
-    uint8_t   attrChipletId=0;
-    uint32_t  attrScanSelect=0;
-    uint32_t  attrRingDataSize=0; // Ring bit size
-    uint32_t  sizeDeltaPllRingAlt=0;
-    uint32_t  sizeRs4Launch=0;
-    uint8_t   *bufDeltaPllRingAlt;
-    CompressedScanData *bufPllRingAltRs4;
-    uint32_t  sizePllRingAltRs4Max, sizePllRingAltRs4, sizePllRingAltBlockMax;
-    DeltaRingLayout *bufPllRingAltBlock;
-    uint32_t  bufLC=0;
-
-    //
-    // Retrieve the raw PLL rings state from attributes.
-    //
-    FAPI_INF("XIPC: PERV_BNDY_PLL update: Retrieve the raw PLL ring state from attributes.");
-    // Get ring size.
-    rc = FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_LENGTH, &i_target, attrRingDataSize); // This better be in bits.
-    FAPI_INF("XIPC: PLL update: PLL ring length (bits) = %i",attrRingDataSize);
-    FAPI_INF("XIPC: PLL update: Size of buf1, i_sizeBuf1 (bytes) = %i",i_sizeBuf1);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_LENGTH) returned error.");
-      return rc;
-    }
-    if (attrRingDataSize>PERV_BNDY_PLL_RING_SIZE*8 || attrRingDataSize>i_sizeBuf1*8)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_LENGTH) returned ring size =%i bits.\n",
-               attrRingDataSize);
-      FAPI_ERR("But that exceeds either:\n");
-      FAPI_ERR("  the max pll ring size =%i bits, or\n",PERV_BNDY_PLL_RING_SIZE*8);
-      FAPI_ERR("  the size of the pre-allocated buf1 =%i bits.", i_sizeBuf1*8);
-      uint32_t &DATA_ATTRIBUTE_RING_SIZE=attrRingDataSize;
-      tmp32Const1=8*PERV_BNDY_PLL_RING_SIZE;
-      tmp32Const2=8*(uint32_t)i_sizeBuf1;
-      uint32_t &DATA_MAX_PLL_RING_SIZE=tmp32Const1;
-      uint32_t &DATA_SIZE_OF_BUF1=tmp32Const2;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_SIZE_TOO_LARGE);
-      return rc;
-    }
-    sizeDeltaPllRingAlt = attrRingDataSize; // We already checked it'll fit into buf1.
-    // Get flush and alter (desired) ring state data.
-    rc = FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_FLUSH, &i_target, attrRingFlush);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_FLUSH) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_DATA, &i_target, attrRingData);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_DATA) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_CHIPLET_ID, &i_target, attrChipletId);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_CHIPLET_ID) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_SCAN_SELECT, &i_target, attrScanSelect);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PERV_BNDY_PLL_SCAN_SELECT) returned error.");
-      return rc;
-    }
-
-    //
-    // Calculate the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: Calculate the delta scan ring.");
-    bufDeltaPllRingAlt = (uint8_t*)i_buf1;
-    rcLoc = calc_ring_delta_state( (uint32_t*)attrRingFlush,
-                                   (uint32_t*)attrRingData,
-                                   (uint32_t*)bufDeltaPllRingAlt, // Pre-allocated buffer.
-                                   sizeDeltaPllRingAlt );
-    if (rcLoc)  {
-      FAPI_ERR("calc_ring_delta_state() returned error w/rc=%i",rcLoc);
-      FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-      return rc;
-    }
-
-    //
-    // RS4 compress the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: RS4 compressing the delta scan ring.");
-    bufPllRingAltRs4 = (CompressedScanData*)i_buf2;
-    sizePllRingAltRs4Max = i_sizeBuf2; // Always supply max buffer space for ring.
-    rcLoc = _rs4_compress(bufPllRingAltRs4,     // Contains PLL _alt RS4 ring on return.
-                          sizePllRingAltRs4Max, // Max size of buffer.
-                          &sizePllRingAltRs4,   // Returned final size of RS4 ring + container.
-                          bufDeltaPllRingAlt,   // Input delta scan ring.
-                          sizeDeltaPllRingAlt,  // Input delta scan ring size.
-                          (uint64_t)attrScanSelect<<32,
-                          0,
-                          attrChipletId,
-                          1 ); // Always flush optimize for base rings.
-    if (rcLoc)  {
-      FAPI_ERR("_rs4_compress() failed w/rc=%i",rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_ERROR);
-      return rc;
-    }
-    else
-    if (sizePllRingAltRs4!=myRev32(bufPllRingAltRs4->iv_size))  {
-      FAPI_ERR("_rs4_compress() problem with size of RS4 ring (incl container).");
-      FAPI_ERR("Returned size = %i", sizePllRingAltRs4);
-      FAPI_ERR("Size from container = %i", myRev32(bufPllRingAltRs4->iv_size));
-      uint32_t &DATA_SIZE_RS4_COMPRESS_RETURN=sizePllRingAltRs4;
-      tmp32Const1=myRev32(bufPllRingAltRs4->iv_size);
-      uint32_t &DATA_SIZE_RS4_COMPRESS_CONTAINER=tmp32Const1;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_SIZE_MESS);
-      return rc;
-    }
-    else
-      FAPI_INF("Compression Successful.");
-
-    //
-    // Build the PLL _alt ring block (= ring header + RS4 launcher + RS4 ring).
-    //
-    uint64_t scanChipletAddress=0;
-    uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4];
-    PoreInlineContext ctx;
-
-    FAPI_INF("XIPC: PLL update: Building the RS4 PLL ring block.");
-    // Reuse i_buf1 to hold the ring block.
-    bufPllRingAltBlock = (DeltaRingLayout*)i_buf1;
-    sizePllRingAltBlockMax = i_sizeBuf1;
-
-    // Construct RS4 launcher:
-    // ...get the RS4 decompress address.
-    rcLoc = sbe_xip_get_scalar( o_imageOut, "proc_sbe_decompress_scan_chiplet_address", &scanChipletAddress);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_get_scalar() failed w/rc=%i", rcLoc);
-      FAPI_ERR("Probable cause: Key word =proc_sbe_decompress_scan_chiplet_address not found in image.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    if (scanChipletAddress==0)  {
-      FAPI_ERR("Value of key word (=proc_sbe_decompress_scan_chiplet_address=0) not permitted.");
-      uint64_t &DATA_RS4_DECOMPRESS_ADDR=scanChipletAddress;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_ILLEGAL_RS4_DECOMPRESS_ADDR);
-      return rc;
-    }
-    // ... create inline asm code.
-    pore_inline_context_create( &ctx, asmBuffer, ASM_RS4_LAUNCH_BUF_SIZE*4, 0, 0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_inline_context_create() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_CTX_CREATE_ERROR);
-      return rc;
-    }
-    pore_MR(&ctx, A0, PC);
-    pore_ADDS(&ctx, A0, A0, ASM_RS4_LAUNCH_BUF_SIZE);
-    pore_LI(&ctx, D0, scanChipletAddress);
-    pore_BRAD(&ctx, D0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_MR/ADDS/LI/BRAD() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_RS4_LAUNCH_CREATE_ERROR);
-      return rc;
-    }
-    sizeRs4Launch = ctx.lc;
-
-    // Populate ring header and put ring header, RS4 launcher and RS4 ring into
-    // proper spots in pre-allocated bufPllRingAltBlock buffer.
-    //
-    uint64_t entryOffsetPllRingAltBlock;
-    uint32_t sizeOfThisPllRingAltBlock;
-    entryOffsetPllRingAltBlock      = calc_ring_layout_entry_offset( 0, 0);
-    bufPllRingAltBlock->entryOffset = myRev64(entryOffsetPllRingAltBlock);
-    bufPllRingAltBlock->backItemPtr  = 0; // Will be updated below, as we don't know yet.
-    sizeOfThisPllRingAltBlock       =  entryOffsetPllRingAltBlock +  // Must be 8-byte aligned.
-                                      sizeRs4Launch +               // Must be 8-byte aligned.
-                                      sizePllRingAltRs4;            // Must be 8-byte aligned.
-    bufPllRingAltBlock->sizeOfThis  = myRev32(sizeOfThisPllRingAltBlock);
-    // Quick check to see if final ring block size will fit in buf1.
-    if (sizeOfThisPllRingAltBlock>sizePllRingAltBlockMax)  {
-      FAPI_ERR("PLL _alt ring block size (=%i) exceeds pre-allocated buf1 size (=%i).",
-        sizeOfThisPllRingAltBlock, sizePllRingAltBlockMax);
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      uint32_t &DATA_SIZE_OF_BUF1=sizePllRingAltBlockMax;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_BLOCK_TOO_LARGE);
-      return rc;
-    }
-    bufPllRingAltBlock->sizeOfMeta  =  0;
-    bufPllRingAltBlock->ddLevel      = myRev32((uint32_t)attrDdLevel);
-    bufPllRingAltBlock->sysPhase     = i_sysPhase;
-    bufPllRingAltBlock->override     = 0;
-    bufPllRingAltBlock->reserved1    = 0;
-    bufPllRingAltBlock->reserved2    = 0;
-    bufLC = (uint32_t)entryOffsetPllRingAltBlock;
-    // Copy over meta data which is zero, so nothing to do in this case!
-    // Copy over RS4 launch code which is [already] BE and 8-byte aligned.
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, asmBuffer, (size_t)sizeRs4Launch);
-    // Copy over RS4 PLL _alt delta scan ring which is [already] 8-byte aligned.
-    bufLC = bufLC + sizeRs4Launch;
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, bufPllRingAltRs4, (size_t)sizePllRingAltRs4);
-
-    // Now, some post-sanity checks on alignments.
-    if ( sizeRs4Launch!=ASM_RS4_LAUNCH_BUF_SIZE ||
-         entryOffsetPllRingAltBlock%8 ||
-         sizeRs4Launch%8 ||
-         sizeOfThisPllRingAltBlock%8)  {
-      FAPI_ERR("Member(s) of PLL _alt ring block are not 8-byte aligned:");
-      FAPI_ERR("  Size of RS4 launch code = %i", sizeRs4Launch);
-      FAPI_ERR("  Entry offset            = %i", (uint32_t)entryOffsetPllRingAltBlock);
-      FAPI_ERR("  Size of ring block      = %i", sizeOfThisPllRingAltBlock);
-      uint32_t &DATA_SIZE_OF_RS4_LAUNCH=sizeRs4Launch;
-      tmp32Const1=(uint32_t)entryOffsetPllRingAltBlock;
-      uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1;
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_BLOCK_ALIGN_ERROR);
-      return rc;
-    }
-
-
-    //
-    // Append PLL _alt ring to image.
-    //
-    FAPI_INF("XIPC: PLL update: Appending RS4 PLL ring block to .rings section.");
-    rcLoc = write_ring_block_to_image( o_imageOut,
-                                       PERV_BNDY_PLL_RING_ALT_TOC_NAME,
-                                       bufPllRingAltBlock,
-                                       0,
-                                       0,
-                                       0,
-                                       largeSeeprom? sizeImageOutMax:MAX_SEEPROM_IMAGE_SIZE, // OK, since sysPhase=0.
-                                       SBE_XIP_SECTION_RINGS,
-																			 i_buf2,
-																			 i_sizeBuf2);
-    if (rcLoc)  {
-      FAPI_ERR("write_ring_block_to_image() failed w/rc=%i",rcLoc);
-      FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-      return rc;
-    }
-
-  }
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Update PLL ring (ab_bndy_pll_ring_alt).
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    uint32_t  tmp32Const1, tmp32Const2;
-    uint8_t   attrRingFlush[AB_BNDY_PLL_RING_SIZE]={0};
-    uint8_t   attrRingData[AB_BNDY_PLL_RING_SIZE]={0};
-    uint8_t   attrChipletId=0;
-    uint32_t  attrScanSelect=0;
-    uint32_t  attrRingDataSize=0; // Ring bit size
-    uint32_t  sizeDeltaPllRingAlt=0;
-    uint32_t  sizeRs4Launch=0;
-    uint8_t   *bufDeltaPllRingAlt;
-    CompressedScanData *bufPllRingAltRs4;
-    uint32_t  sizePllRingAltRs4Max, sizePllRingAltRs4, sizePllRingAltBlockMax;
-    DeltaRingLayout *bufPllRingAltBlock;
-    uint32_t  bufLC=0;
-
-    //
-    // Retrieve the raw PLL rings state from attributes.
-    //
-    FAPI_INF("XIPC: AB_BNDY_PLL update: Retrieve the raw PLL ring state from attributes.");
-    // Get ring size.
-    rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH, &i_target, attrRingDataSize); // This better be in bits.
-    FAPI_INF("XIPC: PLL update: PLL ring length (bits) = %i",attrRingDataSize);
-    FAPI_INF("XIPC: PLL update: Size of buf1, i_sizeBuf1 (bytes) = %i",i_sizeBuf1);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH) returned error.");
-      return rc;
-    }
-    if (attrRingDataSize>AB_BNDY_PLL_RING_SIZE*8 || attrRingDataSize>i_sizeBuf1*8)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH) returned ring size =%i bits.\n",
-               attrRingDataSize);
-      FAPI_ERR("But that exceeds either:\n");
-      FAPI_ERR("  the max pll ring size =%i bits, or\n",AB_BNDY_PLL_RING_SIZE*8);
-      FAPI_ERR("  the size of the pre-allocated buf1 =%i bits.", i_sizeBuf1*8);
-      uint32_t &DATA_ATTRIBUTE_RING_SIZE=attrRingDataSize;
-      tmp32Const1=8*AB_BNDY_PLL_RING_SIZE;
-      tmp32Const2=8*(uint32_t)i_sizeBuf1;
-      uint32_t &DATA_MAX_PLL_RING_SIZE=tmp32Const1;
-      uint32_t &DATA_SIZE_OF_BUF1=tmp32Const2;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_SIZE_TOO_LARGE);
-      return rc;
-    }
-    sizeDeltaPllRingAlt = attrRingDataSize; // We already checked it'll fit into buf1.
-    // Get flush and alter (desired) ring state data.
-    rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_FLUSH, &i_target, attrRingFlush);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_FLUSH) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA, &i_target, attrRingData);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_CHIPLET_ID, &i_target, attrChipletId);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_CHIPLET_ID) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_SCAN_SELECT, &i_target, attrScanSelect);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_SCAN_SELECT) returned error.");
-      return rc;
-    }
-
-    //
-    // Calculate the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: Calculate the delta scan ring.");
-    bufDeltaPllRingAlt = (uint8_t*)i_buf1;
-    rcLoc = calc_ring_delta_state( (uint32_t*)attrRingFlush,
-                                   (uint32_t*)attrRingData,
-                                   (uint32_t*)bufDeltaPllRingAlt, // Pre-allocated buffer.
-                                   sizeDeltaPllRingAlt );
-    if (rcLoc)  {
-      FAPI_ERR("calc_ring_delta_state() returned error w/rc=%i",rcLoc);
-      FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-      return rc;
-    }
-
-    //
-    // RS4 compress the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: RS4 compressing the delta scan ring.");
-    bufPllRingAltRs4 = (CompressedScanData*)i_buf2;
-    sizePllRingAltRs4Max = i_sizeBuf2; // Always supply max buffer space for ring.
-    rcLoc = _rs4_compress(bufPllRingAltRs4,     // Contains PLL _alt RS4 ring on return.
-                          sizePllRingAltRs4Max, // Max size of buffer.
-                          &sizePllRingAltRs4,   // Returned final size of RS4 ring + container.
-                          bufDeltaPllRingAlt,   // Input delta scan ring.
-                          sizeDeltaPllRingAlt,  // Input delta scan ring size.
-                          (uint64_t)attrScanSelect<<32,
-                          0,
-                          attrChipletId,
-                          1 ); // Always flush optimize for base rings.
-    if (rcLoc)  {
-      FAPI_ERR("_rs4_compress() failed w/rc=%i",rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_ERROR);
-      return rc;
-    }
-    else
-    if (sizePllRingAltRs4!=myRev32(bufPllRingAltRs4->iv_size))  {
-      FAPI_ERR("_rs4_compress() problem with size of RS4 ring (incl container).");
-      FAPI_ERR("Returned size = %i", sizePllRingAltRs4);
-      FAPI_ERR("Size from container = %i", myRev32(bufPllRingAltRs4->iv_size));
-      uint32_t &DATA_SIZE_RS4_COMPRESS_RETURN=sizePllRingAltRs4;
-      tmp32Const1=myRev32(bufPllRingAltRs4->iv_size);
-      uint32_t &DATA_SIZE_RS4_COMPRESS_CONTAINER=tmp32Const1;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_SIZE_MESS);
-      return rc;
-    }
-    else
-      FAPI_INF("Compression Successful.");
-
-    //
-    // Build the PLL _alt ring block (= ring header + RS4 launcher + RS4 ring).
-    //
-    uint64_t scanChipletAddress=0;
-    uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4];
-    PoreInlineContext ctx;
-
-    FAPI_INF("XIPC: PLL update: Building the RS4 PLL ring block.");
-    // Reuse i_buf1 to hold the ring block.
-    bufPllRingAltBlock = (DeltaRingLayout*)i_buf1;
-    sizePllRingAltBlockMax = i_sizeBuf1;
-
-    // Construct RS4 launcher:
-    // ...get the RS4 decompress address.
-    rcLoc = sbe_xip_get_scalar( o_imageOut, "proc_sbe_decompress_scan_chiplet_address", &scanChipletAddress);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_get_scalar() failed w/rc=%i", rcLoc);
-      FAPI_ERR("Probable cause: Key word =proc_sbe_decompress_scan_chiplet_address not found in image.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    if (scanChipletAddress==0)  {
-      FAPI_ERR("Value of key word (=proc_sbe_decompress_scan_chiplet_address=0) not permitted.");
-      uint64_t &DATA_RS4_DECOMPRESS_ADDR=scanChipletAddress;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_ILLEGAL_RS4_DECOMPRESS_ADDR);
-      return rc;
-    }
-    // ... create inline asm code.
-    pore_inline_context_create( &ctx, asmBuffer, ASM_RS4_LAUNCH_BUF_SIZE*4, 0, 0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_inline_context_create() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_CTX_CREATE_ERROR);
-      return rc;
-    }
-    pore_MR(&ctx, A0, PC);
-    pore_ADDS(&ctx, A0, A0, ASM_RS4_LAUNCH_BUF_SIZE);
-    pore_LI(&ctx, D0, scanChipletAddress);
-    pore_BRAD(&ctx, D0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_MR/ADDS/LI/BRAD() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_RS4_LAUNCH_CREATE_ERROR);
-      return rc;
-    }
-    sizeRs4Launch = ctx.lc;
-
-    // Populate ring header and put ring header, RS4 launcher and RS4 ring into
-    // proper spots in pre-allocated bufPllRingAltBlock buffer.
-    //
-    uint64_t entryOffsetPllRingAltBlock;
-    uint32_t sizeOfThisPllRingAltBlock;
-    entryOffsetPllRingAltBlock      = calc_ring_layout_entry_offset( 0, 0);
-    bufPllRingAltBlock->entryOffset = myRev64(entryOffsetPllRingAltBlock);
-    bufPllRingAltBlock->backItemPtr  = 0; // Will be updated below, as we don't know yet.
-    sizeOfThisPllRingAltBlock       =  entryOffsetPllRingAltBlock +  // Must be 8-byte aligned.
-                                      sizeRs4Launch +               // Must be 8-byte aligned.
-                                      sizePllRingAltRs4;            // Must be 8-byte aligned.
-    bufPllRingAltBlock->sizeOfThis  = myRev32(sizeOfThisPllRingAltBlock);
-    // Quick check to see if final ring block size will fit in buf1.
-    if (sizeOfThisPllRingAltBlock>sizePllRingAltBlockMax)  {
-      FAPI_ERR("PLL _alt ring block size (=%i) exceeds pre-allocated buf1 size (=%i).",
-        sizeOfThisPllRingAltBlock, sizePllRingAltBlockMax);
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      uint32_t &DATA_SIZE_OF_BUF1=sizePllRingAltBlockMax;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_BLOCK_TOO_LARGE);
-      return rc;
-    }
-    bufPllRingAltBlock->sizeOfMeta  =  0;
-    bufPllRingAltBlock->ddLevel      = myRev32((uint32_t)attrDdLevel);
-    bufPllRingAltBlock->sysPhase     = i_sysPhase;
-    bufPllRingAltBlock->override     = 0;
-    bufPllRingAltBlock->reserved1    = 0;
-    bufPllRingAltBlock->reserved2    = 0;
-    bufLC = (uint32_t)entryOffsetPllRingAltBlock;
-    // Copy over meta data which is zero, so nothing to do in this case!
-    // Copy over RS4 launch code which is [already] BE and 8-byte aligned.
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, asmBuffer, (size_t)sizeRs4Launch);
-    // Copy over RS4 PLL _alt delta scan ring which is [already] 8-byte aligned.
-    bufLC = bufLC + sizeRs4Launch;
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, bufPllRingAltRs4, (size_t)sizePllRingAltRs4);
-
-    // Now, some post-sanity checks on alignments.
-    if ( sizeRs4Launch!=ASM_RS4_LAUNCH_BUF_SIZE ||
-         entryOffsetPllRingAltBlock%8 ||
-         sizeRs4Launch%8 ||
-         sizeOfThisPllRingAltBlock%8)  {
-      FAPI_ERR("Member(s) of PLL _alt ring block are not 8-byte aligned:");
-      FAPI_ERR("  Size of RS4 launch code = %i", sizeRs4Launch);
-      FAPI_ERR("  Entry offset            = %i", (uint32_t)entryOffsetPllRingAltBlock);
-      FAPI_ERR("  Size of ring block      = %i", sizeOfThisPllRingAltBlock);
-      uint32_t &DATA_SIZE_OF_RS4_LAUNCH=sizeRs4Launch;
-      tmp32Const1=(uint32_t)entryOffsetPllRingAltBlock;
-      uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1;
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_BLOCK_ALIGN_ERROR);
-      return rc;
-    }
-
-    //
-    // Append PLL _alt ring to image.
-    //
-    SbeXipItem tocItem;
-    rcLoc = sbe_xip_find(o_imageOut, AB_BNDY_PLL_RING_ALT_TOC_NAME, &tocItem);
-    if (rcLoc)
-    {
-      FAPI_INF("Skipping PLL update for %s", AB_BNDY_PLL_RING_ALT_TOC_NAME);
-      rcLoc = 0;
-    }
-    else
-    {
-      FAPI_INF("XIPC: PLL update: Appending RS4 PLL ring block to .rings section.");
-      rcLoc = write_ring_block_to_image( o_imageOut,
-                                         AB_BNDY_PLL_RING_ALT_TOC_NAME,
-                                         bufPllRingAltBlock,
-                                         0,
-                                         0,
-                                         0,
-                                         largeSeeprom? sizeImageOutMax:MAX_SEEPROM_IMAGE_SIZE, // OK, since sysPhase=0.
-                                         SBE_XIP_SECTION_RINGS,
-                                         i_buf2,
-                                         i_sizeBuf2);
-      if (rcLoc)
-      {
-        FAPI_ERR("write_ring_block_to_image() failed for %s w/rc=%i", AB_BNDY_PLL_RING_ALT_TOC_NAME, rcLoc);
-        FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-        uint32_t &RC_LOCAL=rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-        return rc;
-      }
-    }
-  }
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Update PLL ring (pci_bndy_pll_ring_alt).
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    uint32_t  tmp32Const1, tmp32Const2;
-    uint8_t   attrRingFlush[PCI_BNDY_PLL_RING_SIZE]={0};
-    uint8_t   attrRingData[PCI_BNDY_PLL_RING_SIZE]={0};
-    uint8_t   attrChipletId=0;
-    uint32_t  attrScanSelect=0;
-    uint32_t  attrRingDataSize=0; // Ring bit size
-    uint32_t  sizeDeltaPllRingAlt=0;
-    uint32_t  sizeRs4Launch=0;
-    uint8_t   *bufDeltaPllRingAlt;
-    CompressedScanData *bufPllRingAltRs4;
-    uint32_t  sizePllRingAltRs4Max, sizePllRingAltRs4, sizePllRingAltBlockMax;
-    DeltaRingLayout *bufPllRingAltBlock;
-    uint32_t  bufLC=0;
-
-    //
-    // Retrieve the raw PLL rings state from attributes.
-    //
-    FAPI_INF("XIPC: PCI_BNDY_PLL update: Retrieve the raw PLL ring state from attributes.");
-    // Get ring size.
-    rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_LENGTH, &i_target, attrRingDataSize); // This better be in bits.
-    FAPI_INF("XIPC: PLL update: PLL ring length (bits) = %i",attrRingDataSize);
-    FAPI_INF("XIPC: PLL update: Size of buf1, i_sizeBuf1 (bytes) = %i",i_sizeBuf1);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_LENGTH) returned error.");
-      return rc;
-    }
-    if (attrRingDataSize>PCI_BNDY_PLL_RING_SIZE*8 || attrRingDataSize>i_sizeBuf1*8)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_LENGTH) returned ring size =%i bits.\n",
-               attrRingDataSize);
-      FAPI_ERR("But that exceeds either:\n");
-      FAPI_ERR("  the max pll ring size =%i bits, or\n",PCI_BNDY_PLL_RING_SIZE*8);
-      FAPI_ERR("  the size of the pre-allocated buf1 =%i bits.", i_sizeBuf1*8);
-      uint32_t &DATA_ATTRIBUTE_RING_SIZE=attrRingDataSize;
-      tmp32Const1=8*PCI_BNDY_PLL_RING_SIZE;
-      tmp32Const2=8*(uint32_t)i_sizeBuf1;
-      uint32_t &DATA_MAX_PLL_RING_SIZE=tmp32Const1;
-      uint32_t &DATA_SIZE_OF_BUF1=tmp32Const2;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_SIZE_TOO_LARGE);
-      return rc;
-    }
-    sizeDeltaPllRingAlt = attrRingDataSize; // We already checked it'll fit into buf1.
-    // Get flush and alter (desired) ring state data.
-    rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_FLUSH, &i_target, attrRingFlush);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_FLUSH) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_DATA, &i_target, attrRingData);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_DATA) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_CHIPLET_ID, &i_target, attrChipletId);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_CHIPLET_ID) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_SCAN_SELECT, &i_target, attrScanSelect);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_SCAN_SELECT) returned error.");
-      return rc;
-    }
-
-    //
-    // Calculate the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: Calculate the delta scan ring.");
-    bufDeltaPllRingAlt = (uint8_t*)i_buf1;
-    rcLoc = calc_ring_delta_state( (uint32_t*)attrRingFlush,
-                                   (uint32_t*)attrRingData,
-                                   (uint32_t*)bufDeltaPllRingAlt, // Pre-allocated buffer.
-                                   sizeDeltaPllRingAlt );
-    if (rcLoc)  {
-      FAPI_ERR("calc_ring_delta_state() returned error w/rc=%i",rcLoc);
-      FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-      return rc;
-    }
-
-    //
-    // RS4 compress the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: RS4 compressing the delta scan ring.");
-    bufPllRingAltRs4 = (CompressedScanData*)i_buf2;
-    sizePllRingAltRs4Max = i_sizeBuf2; // Always supply max buffer space for ring.
-    rcLoc = _rs4_compress(bufPllRingAltRs4,     // Contains PLL _alt RS4 ring on return.
-                          sizePllRingAltRs4Max, // Max size of buffer.
-                          &sizePllRingAltRs4,   // Returned final size of RS4 ring + container.
-                          bufDeltaPllRingAlt,   // Input delta scan ring.
-                          sizeDeltaPllRingAlt,  // Input delta scan ring size.
-                          (uint64_t)attrScanSelect<<32,
-                          0,
-                          attrChipletId,
-                          1 ); // Always flush optimize for base rings.
-    if (rcLoc)  {
-      FAPI_ERR("_rs4_compress() failed w/rc=%i",rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_ERROR);
-      return rc;
-    }
-    else
-    if (sizePllRingAltRs4!=myRev32(bufPllRingAltRs4->iv_size))  {
-      FAPI_ERR("_rs4_compress() problem with size of RS4 ring (incl container).");
-      FAPI_ERR("Returned size = %i", sizePllRingAltRs4);
-      FAPI_ERR("Size from container = %i", myRev32(bufPllRingAltRs4->iv_size));
-      uint32_t &DATA_SIZE_RS4_COMPRESS_RETURN=sizePllRingAltRs4;
-      tmp32Const1=myRev32(bufPllRingAltRs4->iv_size);
-      uint32_t &DATA_SIZE_RS4_COMPRESS_CONTAINER=tmp32Const1;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_SIZE_MESS);
-      return rc;
-    }
-    else
-      FAPI_INF("Compression Successful.");
-
-    //
-    // Build the PLL _alt ring block (= ring header + RS4 launcher + RS4 ring).
-    //
-    uint64_t scanChipletAddress=0;
-    uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4];
-    PoreInlineContext ctx;
-
-    FAPI_INF("XIPC: PLL update: Building the RS4 PLL ring block.");
-    // Reuse i_buf1 to hold the ring block.
-    bufPllRingAltBlock = (DeltaRingLayout*)i_buf1;
-    sizePllRingAltBlockMax = i_sizeBuf1;
-
-    // Construct RS4 launcher:
-    // ...get the RS4 decompress address.
-    rcLoc = sbe_xip_get_scalar( o_imageOut, "proc_sbe_decompress_scan_chiplet_address", &scanChipletAddress);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_get_scalar() failed w/rc=%i", rcLoc);
-      FAPI_ERR("Probable cause: Key word =proc_sbe_decompress_scan_chiplet_address not found in image.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    if (scanChipletAddress==0)  {
-      FAPI_ERR("Value of key word (=proc_sbe_decompress_scan_chiplet_address=0) not permitted.");
-      uint64_t &DATA_RS4_DECOMPRESS_ADDR=scanChipletAddress;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_ILLEGAL_RS4_DECOMPRESS_ADDR);
-      return rc;
-    }
-    // ... create inline asm code.
-    pore_inline_context_create( &ctx, asmBuffer, ASM_RS4_LAUNCH_BUF_SIZE*4, 0, 0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_inline_context_create() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_CTX_CREATE_ERROR);
-      return rc;
-    }
-    pore_MR(&ctx, A0, PC);
-    pore_ADDS(&ctx, A0, A0, ASM_RS4_LAUNCH_BUF_SIZE);
-    pore_LI(&ctx, D0, scanChipletAddress);
-    pore_BRAD(&ctx, D0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_MR/ADDS/LI/BRAD() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_RS4_LAUNCH_CREATE_ERROR);
-      return rc;
-    }
-    sizeRs4Launch = ctx.lc;
-
-    // Populate ring header and put ring header, RS4 launcher and RS4 ring into
-    // proper spots in pre-allocated bufPllRingAltBlock buffer.
-    //
-    uint64_t entryOffsetPllRingAltBlock;
-    uint32_t sizeOfThisPllRingAltBlock;
-    entryOffsetPllRingAltBlock      = calc_ring_layout_entry_offset( 0, 0);
-    bufPllRingAltBlock->entryOffset = myRev64(entryOffsetPllRingAltBlock);
-    bufPllRingAltBlock->backItemPtr  = 0; // Will be updated below, as we don't know yet.
-    sizeOfThisPllRingAltBlock       =  entryOffsetPllRingAltBlock +  // Must be 8-byte aligned.
-                                      sizeRs4Launch +               // Must be 8-byte aligned.
-                                      sizePllRingAltRs4;            // Must be 8-byte aligned.
-    bufPllRingAltBlock->sizeOfThis  = myRev32(sizeOfThisPllRingAltBlock);
-    // Quick check to see if final ring block size will fit in buf1.
-    if (sizeOfThisPllRingAltBlock>sizePllRingAltBlockMax)  {
-      FAPI_ERR("PLL _alt ring block size (=%i) exceeds pre-allocated buf1 size (=%i).",
-        sizeOfThisPllRingAltBlock, sizePllRingAltBlockMax);
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      uint32_t &DATA_SIZE_OF_BUF1=sizePllRingAltBlockMax;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_BLOCK_TOO_LARGE);
-      return rc;
-    }
-    bufPllRingAltBlock->sizeOfMeta  =  0;
-    bufPllRingAltBlock->ddLevel      = myRev32((uint32_t)attrDdLevel);
-    bufPllRingAltBlock->sysPhase     = i_sysPhase;
-    bufPllRingAltBlock->override     = 0;
-    bufPllRingAltBlock->reserved1    = 0;
-    bufPllRingAltBlock->reserved2    = 0;
-    bufLC = (uint32_t)entryOffsetPllRingAltBlock;
-    // Copy over meta data which is zero, so nothing to do in this case!
-    // Copy over RS4 launch code which is [already] BE and 8-byte aligned.
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, asmBuffer, (size_t)sizeRs4Launch);
-    // Copy over RS4 PLL _alt delta scan ring which is [already] 8-byte aligned.
-    bufLC = bufLC + sizeRs4Launch;
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, bufPllRingAltRs4, (size_t)sizePllRingAltRs4);
-
-    // Now, some post-sanity checks on alignments.
-    if ( sizeRs4Launch!=ASM_RS4_LAUNCH_BUF_SIZE ||
-         entryOffsetPllRingAltBlock%8 ||
-         sizeRs4Launch%8 ||
-         sizeOfThisPllRingAltBlock%8)  {
-      FAPI_ERR("Member(s) of PLL _alt ring block are not 8-byte aligned:");
-      FAPI_ERR("  Size of RS4 launch code = %i", sizeRs4Launch);
-      FAPI_ERR("  Entry offset            = %i", (uint32_t)entryOffsetPllRingAltBlock);
-      FAPI_ERR("  Size of ring block      = %i", sizeOfThisPllRingAltBlock);
-      uint32_t &DATA_SIZE_OF_RS4_LAUNCH=sizeRs4Launch;
-      tmp32Const1=(uint32_t)entryOffsetPllRingAltBlock;
-      uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1;
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_BLOCK_ALIGN_ERROR);
-      return rc;
-    }
-
-
-    //
-    // Append PLL _alt ring to image.
-    //
-    SbeXipItem tocItem;
-    rcLoc = sbe_xip_find(o_imageOut, PCI_BNDY_PLL_RING_ALT_TOC_NAME, &tocItem);
-    if (rcLoc)
-    {
-      FAPI_INF("Skipping PLL update for %s", PCI_BNDY_PLL_RING_ALT_TOC_NAME);
-      rcLoc = 0;
-    }
-    else
-    {
-      FAPI_INF("XIPC: PLL update: Appending RS4 PLL ring block to .rings section.");
-      rcLoc = write_ring_block_to_image( o_imageOut,
-                                         PCI_BNDY_PLL_RING_ALT_TOC_NAME,
-                                         bufPllRingAltBlock,
-                                         0,
-                                         0,
-                                         0,
-                                         largeSeeprom? sizeImageOutMax:MAX_SEEPROM_IMAGE_SIZE, // OK, since sysPhase=0.
-                                         SBE_XIP_SECTION_RINGS,
-                                         i_buf2,
-                                         i_sizeBuf2);
-      if (rcLoc)
-      {
-        FAPI_ERR("write_ring_block_to_image() failed for %s w/rc=%i", PCI_BNDY_PLL_RING_ALT_TOC_NAME, rcLoc);
-        FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-        uint32_t &RC_LOCAL=rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-        return rc;
-      }
-    }
-
-  }
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Update PLL ring (pb_bndy_dmipll_ring_alt).
-  // Retrieval method:  Attribute.
-  // System phase:      IPL sysPhase.
-  // ==========================================================================
-
-  if (i_sysPhase==0)  {
-    uint32_t  tmp32Const1, tmp32Const2;
-    uint8_t   attrRingFlush[PB_BNDY_DMIPLL_RING_SIZE]={0};
-    uint8_t   attrRingData[PB_BNDY_DMIPLL_RING_SIZE]={0};
-    uint8_t   attrChipletId=0;
-    uint32_t  attrScanSelect=0;
-    uint32_t  attrRingDataSize=0; // Ring bit size
-    uint32_t  sizeDeltaPllRingAlt=0;
-    uint32_t  sizeRs4Launch=0;
-    uint8_t   *bufDeltaPllRingAlt;
-    CompressedScanData *bufPllRingAltRs4;
-    uint32_t  sizePllRingAltRs4Max, sizePllRingAltRs4, sizePllRingAltBlockMax;
-    DeltaRingLayout *bufPllRingAltBlock;
-    uint32_t  bufLC=0;
-
-    //
-    // Retrieve the raw PLL rings state from attributes.
-    //
-    FAPI_INF("XIPC: PB_BNDY_DMIPLL update: Retrieve the raw PLL ring state from attributes.");
-    // Get ring size.
-    rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &i_target, attrRingDataSize); // This better be in bits.
-    FAPI_INF("XIPC: PLL update: PLL ring length (bits) = %i",attrRingDataSize);
-    FAPI_INF("XIPC: PLL update: Size of buf1, i_sizeBuf1 (bytes) = %i",i_sizeBuf1);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH) returned error.");
-      return rc;
-    }
-    if (attrRingDataSize>PB_BNDY_DMIPLL_RING_SIZE*8 || attrRingDataSize>i_sizeBuf1*8)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH) returned ring size =%i bits.\n",
-               attrRingDataSize);
-      FAPI_ERR("But that exceeds either:\n");
-      FAPI_ERR("  the max pll ring size =%i bits, or\n",PB_BNDY_DMIPLL_RING_SIZE*8);
-      FAPI_ERR("  the size of the pre-allocated buf1 =%i bits.", i_sizeBuf1*8);
-      uint32_t &DATA_ATTRIBUTE_RING_SIZE=attrRingDataSize;
-      tmp32Const1=8*PB_BNDY_DMIPLL_RING_SIZE;
-      tmp32Const2=8*(uint32_t)i_sizeBuf1;
-      uint32_t &DATA_MAX_PLL_RING_SIZE=tmp32Const1;
-      uint32_t &DATA_SIZE_OF_BUF1=tmp32Const2;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_SIZE_TOO_LARGE);
-      return rc;
-    }
-    sizeDeltaPllRingAlt = attrRingDataSize; // We already checked it'll fit into buf1.
-    // Get flush and alter (desired) ring state data.
-    rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_FLUSH, &i_target, attrRingFlush);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_FLUSH) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA, &i_target, attrRingData);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_CHIPLET_ID, &i_target, attrChipletId);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_CHIPLET_ID) returned error.");
-      return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_SCAN_SELECT, &i_target, attrScanSelect);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_SCAN_SELECT) returned error.");
-      return rc;
-    }
-
-    //
-    // Calculate the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: Calculate the delta scan ring.");
-    bufDeltaPllRingAlt = (uint8_t*)i_buf1;
-    rcLoc = calc_ring_delta_state( (uint32_t*)attrRingFlush,
-                                   (uint32_t*)attrRingData,
-                                   (uint32_t*)bufDeltaPllRingAlt, // Pre-allocated buffer.
-                                   sizeDeltaPllRingAlt );
-    if (rcLoc)  {
-      FAPI_ERR("calc_ring_delta_state() returned error w/rc=%i",rcLoc);
-      FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-      return rc;
-    }
-
-    //
-    // RS4 compress the delta scan ring.
-    //
-    FAPI_INF("XIPC: PLL update: RS4 compressing the delta scan ring.");
-    bufPllRingAltRs4 = (CompressedScanData*)i_buf2;
-    sizePllRingAltRs4Max = i_sizeBuf2; // Always supply max buffer space for ring.
-    rcLoc = _rs4_compress(bufPllRingAltRs4,     // Contains PLL _alt RS4 ring on return.
-                          sizePllRingAltRs4Max, // Max size of buffer.
-                          &sizePllRingAltRs4,   // Returned final size of RS4 ring + container.
-                          bufDeltaPllRingAlt,   // Input delta scan ring.
-                          sizeDeltaPllRingAlt,  // Input delta scan ring size.
-                          (uint64_t)attrScanSelect<<32,
-                          0,
-                          attrChipletId,
-                          1 ); // Always flush optimize for base rings.
-    if (rcLoc)  {
-      FAPI_ERR("_rs4_compress() failed w/rc=%i",rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_ERROR);
-      return rc;
-    }
-    else
-    if (sizePllRingAltRs4!=myRev32(bufPllRingAltRs4->iv_size))  {
-      FAPI_ERR("_rs4_compress() problem with size of RS4 ring (incl container).");
-      FAPI_ERR("Returned size = %i", sizePllRingAltRs4);
-      FAPI_ERR("Size from container = %i", myRev32(bufPllRingAltRs4->iv_size));
-      uint32_t &DATA_SIZE_RS4_COMPRESS_RETURN=sizePllRingAltRs4;
-      tmp32Const1=myRev32(bufPllRingAltRs4->iv_size);
-      uint32_t &DATA_SIZE_RS4_COMPRESS_CONTAINER=tmp32Const1;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RS4_COMPRESS_SIZE_MESS);
-      return rc;
-    }
-    else
-      FAPI_INF("Compression Successful.");
-
-    //
-    // Build the PLL _alt ring block (= ring header + RS4 launcher + RS4 ring).
-    //
-    uint64_t scanChipletAddress=0;
-    uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4];
-    PoreInlineContext ctx;
-
-    FAPI_INF("XIPC: PLL update: Building the RS4 PLL ring block.");
-    // Reuse i_buf1 to hold the ring block.
-    bufPllRingAltBlock = (DeltaRingLayout*)i_buf1;
-    sizePllRingAltBlockMax = i_sizeBuf1;
-
-    // Construct RS4 launcher:
-    // ...get the RS4 decompress address.
-    rcLoc = sbe_xip_get_scalar( o_imageOut, "proc_sbe_decompress_scan_chiplet_address", &scanChipletAddress);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_get_scalar() failed w/rc=%i", rcLoc);
-      FAPI_ERR("Probable cause: Key word =proc_sbe_decompress_scan_chiplet_address not found in image.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    if (scanChipletAddress==0)  {
-      FAPI_ERR("Value of key word (=proc_sbe_decompress_scan_chiplet_address=0) not permitted.");
-      uint64_t &DATA_RS4_DECOMPRESS_ADDR=scanChipletAddress;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_ILLEGAL_RS4_DECOMPRESS_ADDR);
-      return rc;
-    }
-    // ... create inline asm code.
-    pore_inline_context_create( &ctx, asmBuffer, ASM_RS4_LAUNCH_BUF_SIZE*4, 0, 0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_inline_context_create() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_CTX_CREATE_ERROR);
-      return rc;
-    }
-    pore_MR(&ctx, A0, PC);
-    pore_ADDS(&ctx, A0, A0, ASM_RS4_LAUNCH_BUF_SIZE);
-    pore_LI(&ctx, D0, scanChipletAddress);
-    pore_BRAD(&ctx, D0);
-    rcLoc = ctx.error;
-    if (rcLoc)  {
-      FAPI_ERR("pore_MR/ADDS/LI/BRAD() failed w/rc=%i", rcLoc);
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PORE_INLINE_RS4_LAUNCH_CREATE_ERROR);
-      return rc;
-    }
-    sizeRs4Launch = ctx.lc;
-
-    // Populate ring header and put ring header, RS4 launcher and RS4 ring into
-    // proper spots in pre-allocated bufPllRingAltBlock buffer.
-    //
-    uint64_t entryOffsetPllRingAltBlock;
-    uint32_t sizeOfThisPllRingAltBlock;
-    entryOffsetPllRingAltBlock      = calc_ring_layout_entry_offset( 0, 0);
-    bufPllRingAltBlock->entryOffset = myRev64(entryOffsetPllRingAltBlock);
-    bufPllRingAltBlock->backItemPtr  = 0; // Will be updated below, as we don't know yet.
-    sizeOfThisPllRingAltBlock       =  entryOffsetPllRingAltBlock +  // Must be 8-byte aligned.
-                                      sizeRs4Launch +               // Must be 8-byte aligned.
-                                      sizePllRingAltRs4;            // Must be 8-byte aligned.
-    bufPllRingAltBlock->sizeOfThis  = myRev32(sizeOfThisPllRingAltBlock);
-    // Quick check to see if final ring block size will fit in buf1.
-    if (sizeOfThisPllRingAltBlock>sizePllRingAltBlockMax)  {
-      FAPI_ERR("PLL _alt ring block size (=%i) exceeds pre-allocated buf1 size (=%i).",
-        sizeOfThisPllRingAltBlock, sizePllRingAltBlockMax);
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      uint32_t &DATA_SIZE_OF_BUF1=sizePllRingAltBlockMax;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_PLL_RING_BLOCK_TOO_LARGE);
-      return rc;
-    }
-    bufPllRingAltBlock->sizeOfMeta  =  0;
-    bufPllRingAltBlock->ddLevel      = myRev32((uint32_t)attrDdLevel);
-    bufPllRingAltBlock->sysPhase     = i_sysPhase;
-    bufPllRingAltBlock->override     = 0;
-    bufPllRingAltBlock->reserved1    = 0;
-    bufPllRingAltBlock->reserved2    = 0;
-    bufLC = (uint32_t)entryOffsetPllRingAltBlock;
-    // Copy over meta data which is zero, so nothing to do in this case!
-    // Copy over RS4 launch code which is [already] BE and 8-byte aligned.
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, asmBuffer, (size_t)sizeRs4Launch);
-    // Copy over RS4 PLL _alt delta scan ring which is [already] 8-byte aligned.
-    bufLC = bufLC + sizeRs4Launch;
-    memcpy( (uint8_t*)bufPllRingAltBlock+bufLC, bufPllRingAltRs4, (size_t)sizePllRingAltRs4);
-
-    // Now, some post-sanity checks on alignments.
-    if ( sizeRs4Launch!=ASM_RS4_LAUNCH_BUF_SIZE ||
-         entryOffsetPllRingAltBlock%8 ||
-         sizeRs4Launch%8 ||
-         sizeOfThisPllRingAltBlock%8)  {
-      FAPI_ERR("Member(s) of PLL _alt ring block are not 8-byte aligned:");
-      FAPI_ERR("  Size of RS4 launch code = %i", sizeRs4Launch);
-      FAPI_ERR("  Entry offset            = %i", (uint32_t)entryOffsetPllRingAltBlock);
-      FAPI_ERR("  Size of ring block      = %i", sizeOfThisPllRingAltBlock);
-      uint32_t &DATA_SIZE_OF_RS4_LAUNCH=sizeRs4Launch;
-      tmp32Const1=(uint32_t)entryOffsetPllRingAltBlock;
-      uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1;
-      uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeOfThisPllRingAltBlock;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_BLOCK_ALIGN_ERROR);
-      return rc;
-    }
-
-
-    //
-    // Append PLL _alt ring to image.
-    //
-    SbeXipItem tocItem;
-    rcLoc = sbe_xip_find(o_imageOut, PB_BNDY_DMIPLL_RING_ALT_TOC_NAME, &tocItem);
-    if (rcLoc)
-    {
-      FAPI_INF("Skipping PLL update for %s", PB_BNDY_DMIPLL_RING_ALT_TOC_NAME);
-      rcLoc = 0;
-    }
-    else
-    {
-      FAPI_INF("XIPC: PLL update: Appending RS4 PLL ring block to .rings section.");
-      rcLoc = write_ring_block_to_image( o_imageOut,
-                                         PB_BNDY_DMIPLL_RING_ALT_TOC_NAME,
-                                         bufPllRingAltBlock,
-                                         0,
-                                         0,
-                                         0,
-                                         largeSeeprom? sizeImageOutMax:MAX_SEEPROM_IMAGE_SIZE, // OK, since sysPhase=0.
-                                         SBE_XIP_SECTION_RINGS,
-                                         i_buf2,
-                                         i_sizeBuf2);
-      if (rcLoc)
-      {
-        FAPI_ERR("write_ring_block_to_image() failed for %s w/rc=%i", PB_BNDY_DMIPLL_RING_ALT_TOC_NAME, rcLoc);
-        FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-        uint32_t &RC_LOCAL=rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-        return rc;
-      }
-    }
-  }
-
-#endif
-
-
-#ifndef IMGBUILD_PPD_IGNORE_VPD
-  // ==========================================================================
-  // CUSTOMIZE item:    Add #G and #R rings.
-  // Retrieval method:  MVPD
-  // System phase:      Applies to both sysPhase modes: IPL and SLW.
-  // Notes: For SLW, only update ex_ chiplet rings.
-  // ==========================================================================
-  SbeXipSection xipSectionDcrings;
-  
-  // First, is there an .dcrings section yet in the input image?  We need this to know 
-  //   if we should do datacare on #G rings a little later.
-  // (Note, it makes no sense checking in output image since SLW has been wiped clean, and 
-  //    the same may be the case with IPL image in the future.)
-  rcLoc = sbe_xip_get_section(i_imageIn, SBE_XIP_SECTION_DCRINGS, &xipSectionDcrings);
-  if (rcLoc)  {
-    FAPI_ERR("_get_section(.dcrings...) failed with rc=%i  ",rcLoc);
-    uint32_t &RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMGBUILD_ERROR);
-    return rc;
-  }
-
-  if (i_sysPhase==0 && !largeSeeprom) {
-    // The .dcrings section will eventually be removed from the image, so set the
-    // max size to final output size max + .dcrings size if we can
-    sizeImageMax = min(MAX_SEEPROM_IMAGE_SIZE + xipSectionDcrings.iv_size, sizeImageOutMax);
-  } else {
-    sizeImageMax = sizeImageOutMax;
-  }
-
-  // First, insert the chiplet XX rings
-  rc = p8_xip_customize_insert_chiplet_rings( i_target,
-                                              i_imageIn,
-                                              o_imageOut,
-                                              i_sysPhase,
-                                              i_buf1,
-                                              i_sizeBuf1,
-                                              i_buf2,
-                                              i_sizeBuf2,
-                                              attrDdLevel,
-
-                                              sizeImageMax,
-                                              0xFF,
-                                              xipSectionDcrings
-                                              );
-  if (rc) return rc;
-
-  // Then loop through the chiplets
-  uint32_t validEXCount = 0;
-  uint8_t  chipletId;
-  io_bootCoreMask = 0;
-  for (chipletId = CHIPLET_ID_MIN; chipletId <= CHIPLET_ID_MAX; chipletId++) {
-    // Only process functional chiplets
-    // Note - currently the SBE treats bad cores (0x93) as non-functional (0x00)
-    //        so inserting rings for those wastes space. I'll assume that they
-    //        won't be in the desiredBootCoreMask and thus won't get rings,
-    //        rather than checking for that case because the SBE code may change.
-    if (attrCombGoodVec[chipletId]) {
-      // Special handling for EX chiplet IDs
-      if ((chipletId >= CHIPLET_ID_EX_MIN) && (chipletId <= CHIPLET_ID_EX_MAX)) {
-        if (desiredBootCoreMask & (0x80000000 >> chipletId)) {
-          rc = p8_xip_customize_insert_chiplet_rings( i_target,
-                                                      i_imageIn,
-                                                      o_imageOut,
-                                                      i_sysPhase,
-                                                      i_buf1,
-                                                      i_sizeBuf1,
-                                                      i_buf2,
-                                                      i_sizeBuf2,
-                                                      attrDdLevel,
-                                                      sizeImageMax,
-                                                      chipletId,
-                                                      xipSectionDcrings
-                                                      );
-          if (rc) {
-            // Check if this is just a case of trying to fit in too many EXs
-            if ((i_sysPhase == 0) &&
-                (rc == RC_PROC_XIPC_RING_WRITE_WOULD_OVERFLOW))
-            {
-
-              uint32_t MINIMUM_VALID_EXS;
-              fapi::ReturnCode lrc;
-              lrc = FAPI_ATTR_GET(ATTR_SBE_IMAGE_MINIMUM_VALID_EXS, NULL, MINIMUM_VALID_EXS);
-              if (lrc)
-              {
-                FAPI_INF("Unable to determine ATTR_SBE_IMAGE_MINIMUM_VALID_EXS, so don't know if the minimum was met");
-                fapiLogError(lrc);
-                uint32_t & VALID_COUNT = validEXCount;
-                uint32_t & MINIMUM = MINIMUM_VALID_EXS;
-                const uint32_t & DESIRED_CORES = desiredBootCoreMask;
-                uint32_t & BOOT_CORE_MASK = io_bootCoreMask;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_RING_WRITE_WOULD_OVERFLOW_ADD_INFO);
-                return rc;
-              }
-
-              if (validEXCount < MINIMUM_VALID_EXS)
-              {
-                FAPI_ERR("Was only able to put %i EXs into the IPL image (minimum is %i)", validEXCount, MINIMUM_VALID_EXS);
-                fapiLogError(rc);
-                uint32_t & VALID_COUNT = validEXCount;
-                uint32_t & MINIMUM = MINIMUM_VALID_EXS;
-                const uint32_t & DESIRED_CORES = desiredBootCoreMask;
-                uint32_t & BOOT_CORE_MASK = io_bootCoreMask;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_OVERFLOW_BEFORE_REACHING_MINIMUM_EXS);
-                return rc;
-              }
-              else
-              {
-                // out of space for this chiplet, but got enough EXs in to run
-                // so jump to the end of EXs and continue
-                rc = FAPI_RC_SUCCESS;
-                chipletId = CHIPLET_ID_EX_MAX;
-                FAPI_INF("Skipping the rest of the EX rings because image is full");
-              }
-            }
-            else
-            {
-              //This is a real error, so return it
-              FAPI_INF("Hit an error adding cores to the image");
-              return rc;
-            }
-          } else {
-            // Successfully added this chiplet
-            // Update tracking of valid EX chiplets in the image
-            io_bootCoreMask |= (0x80000000 >> chipletId);
-            validEXCount++;
-          }
-        } else {
-          FAPI_INF("Skipping EX chiplet ID 0x%X because it's not in the bootCoreMask", chipletId);
-        }
-      } else {
-        // Normal handling for non-EX chiplet IDs
-        rc = p8_xip_customize_insert_chiplet_rings( i_target,
-                                                    i_imageIn,
-                                                    o_imageOut,
-                                                    i_sysPhase,
-                                                    i_buf1,
-                                                    i_sizeBuf1,
-                                                    i_buf2,
-                                                    i_sizeBuf2,
-                                                    attrDdLevel,
-                                                    sizeImageMax,
-                                                    chipletId,
-                                                    xipSectionDcrings
-                                                    );
-        if (rc) return rc;
-      } //end else non-EX chiplet
-    } //end if valid chiplet
-  } //end loop on chiplets
-#endif
-
-  // Now, we can safely remove the .dcrings section from the output image. Though, no
-  //   need to do it for SLW which was wiped clean in slw_build().
-  //
-  if (i_sysPhase==0)  {
-    rcLoc = sbe_xip_delete_section(o_imageOut, SBE_XIP_SECTION_DCRINGS);
-    if (rcLoc)  {
-      MY_ERR("_delete_section(.dcrings...) failed w/rc=%i  ",rcLoc);
-      uint32_t & RC_LOCAL = rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_XIP_DELETE_SECTION_ERROR);
-      return rc;
-    }
-    // Now that the section is removed, lower sizeImageMax to the actual max if needed
-    if (!largeSeeprom) {
-      sizeImageMax = min(MAX_SEEPROM_IMAGE_SIZE, sizeImageOutMax);
-    }
-  }
-
-  // ==========================================================================
-  // CUSTOMIZE item:    intr_decrementer_delay*
-  // Retrieval method:  Generated by this code
-  // System phase:      IPL sysPhase.
-  // Note: Customizes SBE interrupt service
-  // ==========================================================================
-  if (i_sysPhase==0)  {
-    // target delay cycles/us
-    void *hostDelayCycles;
-    uint32_t delay_cycles;
-    void *hostDelayUs;
-    uint32_t delay_us;
-
-    // determine nest frequency
-    uint32_t freq_pb;
-    rc = FAPI_ATTR_GET(ATTR_FREQ_PB_MHZ, NULL, freq_pb);
-    if (!rc.ok())
-    {
-        FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_FREQ_PB_MHZ)");
-        return rc;
-    }
-
-    // set attributes accordingly
-    delay_us = 10;
-    if (freq_pb == 2000)
-    {
-        delay_cycles = 0x1097;
-    }
-    else
-    {
-        delay_cycles = 0x1460;
-    }
-    rc = FAPI_ATTR_SET(ATTR_SBE_MASTER_INTR_SERVICE_DELAY_CYCLES, NULL, delay_cycles);
-    if (!rc.ok())
-    {
-        FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_SBE_MASTER_INTR_SERVICE_DELAY_CYCLES)");
-        return rc;
-    }
-    rc = FAPI_ATTR_SET(ATTR_SBE_MASTER_INTR_SERVICE_DELAY_US, NULL, delay_us);
-    if (!rc.ok())
-    {
-        FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_SBE_MASTER_INTR_SERVICE_DELAY_US)");
-        return rc;
-    }
-
-    // customize image
-    rcLoc = sbe_xip_find(o_imageOut, INTR_DECREMENTER_DELAY_CYCLES_NAME, &xipTocItem);
-    if (rcLoc)
-    {
-        FAPI_INF("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-        FAPI_INF("Probable cause:");
-        FAPI_INF("\tThe keyword (=%s) was not found.", INTR_DECREMENTER_DELAY_CYCLES_NAME);
-        rcLoc = 0;
-    }
-    else
-    {
-        sbe_xip_pore2host(o_imageOut, xipTocItem.iv_address, &hostDelayCycles);
-        FAPI_INF("Dumping [initial] global variable content of %s, then the updated value:\n", INTR_DECREMENTER_DELAY_CYCLES_NAME);
-        FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostDelayCycles));
-        *(uint64_t*)hostDelayCycles = myRev64(delay_cycles);
-        FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostDelayCycles));
-    }
-
-    // delay in us
-    rcLoc = sbe_xip_find(o_imageOut, INTR_DECREMENTER_DELAY_US_NAME, &xipTocItem);
-    if (rcLoc)
-    {
-        FAPI_INF("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-        FAPI_INF("Probable cause:");
-        FAPI_INF("\tThe keyword (=%s) was not found.", INTR_DECREMENTER_DELAY_US_NAME);
-        rcLoc = 0;
-    }
-    else
-    {
-        sbe_xip_pore2host(o_imageOut, xipTocItem.iv_address, &hostDelayUs);
-        FAPI_INF("Dumping [initial] global variable content of %s, then the updated value:\n", INTR_DECREMENTER_DELAY_US_NAME);
-        FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostDelayUs));
-        *(uint64_t*)hostDelayUs = myRev64(delay_us);
-        FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostDelayUs));
-    }
-  }
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    valid_boot_cores_mask
-  // Retrieval method:  Generated by this code
-  // System phase:      IPL sysPhase.
-  // Note: Indicates which EX cores had #G and #R rings inserted
-  // ==========================================================================
-  if (i_sysPhase==0)  {
-    void       *hostValidBootCoresMask;
-    rcLoc = sbe_xip_find( o_imageOut, VALID_BOOT_CORES_MASK_TOC_NAME, &xipTocItem);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-      FAPI_ERR("Probable cause:");
-      FAPI_ERR("\tThe keyword (=%s) was not found.",VALID_BOOT_CORES_MASK_TOC_NAME);
-      uint32_t & RC_LOCAL = rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    sbe_xip_pore2host( o_imageOut, xipTocItem.iv_address, &hostValidBootCoresMask);
-    FAPI_INF("Dumping [initial] global variable content of valid_boot_cores_mask, then the updated value:\n");
-    FAPI_INF(" Before=0x%016llX\n",myRev64(*(uint64_t*)hostValidBootCoresMask));
-    *(uint64_t*)hostValidBootCoresMask = myRev64(((uint64_t)io_bootCoreMask)<<32);
-    FAPI_INF(" After =0x%016llX\n",myRev64(*(uint64_t*)hostValidBootCoresMask));
-  }
-
-
-  // ==========================================================================
-  // ==========================================================================
-  //                                     *-----*
-  //                    CUSTOMIZATION OF | SLW | SECTION
-  //                                     *-----*
-  // ==========================================================================
-  // ==========================================================================
-  
-  if (i_sysPhase==1)  {
-  
-  // ==========================================================================
-  // INITIALIZE item:   .slw section (aka runtime section).
-  // Retrieval method:  N/A
-  // System phase:      SLW sysPhase.
-  // Note: This item was originally in slw_build but has to be put here for
-  //       practical reasons.
-  // ==========================================================================
-
-  switch (i_modeBuild)  {
-	
-  // --------------------------------------------------------------------
-  // case 0:  IPL mode.
-  // - This is first time SLW image is built. Go all out.
-  // --------------------------------------------------------------------
-  case P8_SLW_MODEBUILD_IPL:  // IPL mode.
-    rcLoc = create_and_initialize_fixed_image(o_imageOut);
-    if (rcLoc)  {
-      uint32_t & RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_CREATE_FIXED_IMAGE_ERROR);
-      return rc;
-    }
-    FAPI_INF("IPL mode build: Fixed SLW and FFDC sections allocated and SLW section initialized for Ramming and Scomming tables.");
-    break;
-  // --------------------------------------------------------------------
-  // case 1:  Rebuild mode - Nothing to do.
-  // - Image size already fixed at 1MB during IPL mode.
-  // - Fixed positioning of .slw and .ffdc already done during IPL mode. 
-  // --------------------------------------------------------------------
-  case P8_SLW_MODEBUILD_REBUILD:  // Rebuild mode. (Need to update Ram/Scom vectors.)
-    rcLoc = create_and_initialize_fixed_image(o_imageOut);
-    if (rcLoc)  {
-      uint32_t & RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_CREATE_FIXED_IMAGE_ERROR);
-      return rc;
-    }
-    FAPI_INF("Rebuild mode build: Fixed SLW and FFDC sections allocated and SLW section initialized for Ramming and Scomming tables.");
-    break;
-  // --------------------------------------------------------------------
-  // case 2:  SRAM mode.
-  // - Assumption: slw_build() called by OCC.
-  // - Need to make image as slim as possible.
-  // - Do not append .fit.
-  // - Position .slw right after .rings.
-  // - Do not append .ffdc.
-  // --------------------------------------------------------------------
-  case P8_SLW_MODEBUILD_SRAM:  // SRAM mode.
-    sizeImageTmp = sizeImageOutMax;
-    rcLoc = initialize_slw_section(o_imageOut,
-                                   &sizeImageTmp);
-    if (rcLoc)  {
-      if (rcLoc==IMGBUILD_ERR_IMAGE_TOO_LARGE)  {
-        uint32_t & DATA_IMG_SIZE_NEW=sizeImageTmp;
-        uint32_t & DATA_IMG_SIZE_MAX=sizeImageOutMax;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_MAX_IMAGE_SIZE_EXCEEDED);
-      }
-      else  {
-        uint32_t & RC_LOCAL=rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_APPEND_SLW_SECTION_ERROR);
-      }
-      return rc;
-    }
-    FAPI_INF("SRAM mode build: SLW section allocated for Ramming and Scomming tables.");
-    break;
-  // Default case - Should never get here.
-  default:
-    FAPI_ERR("Bad code, or bad modeBuild (=%i) parm.",i_modeBuild);
-    ffdc_temp = i_modeBuild;
-    uint8_t & MODE_BUILD=ffdc_temp;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_BAD_CODE_OR_PARM);
-    return rc;
-  
-	}  // End of switch (i_modeBuild)
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    L2 and L3 Epsilon config register SCOM table updates.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL and SLW sysPhase.
-  // ==========================================================================
-
-  // L2
-  //  
-  rc = FAPI_ATTR_GET(ATTR_L2_R_T0_EPS, NULL, attrL2RT0Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_R_T0_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L2_R_T1_EPS, NULL, attrL2RT1Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_R_T1_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L2_R_T2_EPS, NULL, attrL2RT2Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_R_T2_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L2_W_EPS, NULL, attrL2WEps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_W_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L2_FORCE_R_T2_EPS, NULL, attrL2ForceRT2Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L2_FORCE_R_T2_EPS) returned error.\n");
-    return rc;
-  }
-  bScomEntry = 0;
-  scomData = ( (uint64_t)attrL2RT0Eps     <<(63-8)  & (uint64_t)0x1ff<<(63-8) )  |
-             ( (uint64_t)attrL2RT1Eps     <<(63-17) & (uint64_t)0x1ff<<(63-17) ) |
-             ( (uint64_t)attrL2RT2Eps     <<(63-28) & (uint64_t)0x7ff<<(63-28) ) |
-             ( (uint64_t)attrL2WEps       <<(63-35) & (uint64_t)0x07f<<(63-35) ) |
-             ( (uint64_t)attrL2ForceRT2Eps<<(63-36) & (uint64_t)0x001<<(63-36) );
-  FAPI_INF("scomData =0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_L2_CERRS_RD_EPS_REG_0x10012814, // Scom addr.
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("Updating SCOM NC table w/L2 Epsilon data unsuccessful (rcLoc=%i)\n",rcLoc);
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/L2 Epsilon data successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 Epsilon data (2).\n");
-  }
-  
-  // L3
-  //
-  rc = FAPI_ATTR_GET(ATTR_L3_R_T0_EPS, NULL, attrL3RT0Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_R_T0_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L3_R_T1_EPS, NULL, attrL3RT1Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_R_T1_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L3_R_T2_EPS, NULL, attrL3RT2Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_R_T2_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L3_FORCE_R_T2_EPS, NULL, attrL3ForceRT2Eps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_FORCE_R_T2_EPS) returned error.\n");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_L3_W_EPS, NULL, attrL3WEps);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_L3_W_EPS) returned error.\n");
-    return rc;
-  }
-  bScomEntry = 0;
-  scomData = ( (uint64_t)attrL3RT0Eps     <<(63-8)  & (uint64_t)0x1ff<<(63-8) )  |
-             ( (uint64_t)attrL3RT1Eps     <<(63-17) & (uint64_t)0x1ff<<(63-17) ) |
-             ( (uint64_t)attrL3RT2Eps     <<(63-28) & (uint64_t)0x7ff<<(63-28) ) |
-             ( (uint64_t)attrL3ForceRT2Eps<<(63-30) & (uint64_t)0x003<<(63-30) );
-  FAPI_INF("scomData =0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_L3_CERRS_RD_EPS_REG_0x10010829, // Scom addr.
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/L3 Epsilon data (1) unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/L3 Epsilon data (1) successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 Epsilon data (1).\n");
-  }
-
-  bScomEntry = 0;
-  scomData = ( (uint64_t)attrL3WEps       <<(63-6)  & (uint64_t)0x07f<<(63-6) );
-  FAPI_INF("scomData =0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_L3_CERRS_WR_EPS_REG_0x1001082A, // Scom addr.
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/L3 Epsilon data (2) unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/L3 Epsilon data (2) successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 Epsilon data (2).\n");
-  }
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    L3 BAR config register SCOM table updates. (By JoeM)
-  // Retrieval method:  Attribute.
-  // System phase:      IPL and SLW sysPhase.
-  // ==========================================================================
-  rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR1_REG, &i_target, attrL3BAR1);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_L3_BAR1_REG) returned error.\n");
-    return rc;
-  }
-
-  rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR2_REG, &i_target, attrL3BAR2);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_L3_BAR2_REG) returned error.\n");
-    return rc;
-  }
-
-  rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG, &i_target, attrL3BARMask);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG) returned error.\n");
-    return rc;
-  }
-
-  bScomEntry = 0;
-  scomData = ( (uint64_t)attrL3BAR1);
-  FAPI_INF("scomData =0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_L3_BAR1_REG_0x1001080B, // Scom addr.
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/L3 BAR data (1) unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/L3 BAR (1) successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 BAR data (1).\n");
-  }
-
-  bScomEntry = 0;
-  scomData = ( (uint64_t)attrL3BAR2);
-  FAPI_INF("scomData =0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_L3_BAR2_REG_0x10010813, // Scom addr.
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/L3 BAR data (2) unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/L3 BAR (2) successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 BAR data (2).\n");
-  }
-
-  bScomEntry = 0;
-  scomData = ( (uint64_t)attrL3BARMask);
-  FAPI_INF("scomData =0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_L3_BAR_GROUP_MASK_REG_0x10010816, // Scom addr.
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/L3 BAR data (3) unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/L3 BAR (3) successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/L3 BAR data (3).\n");
-  }
-
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    SPURR Scom table updates.
-  // Retrieval method:  Attribute.
-  // System phase:      IPL and SLW sysPhase.
-  // ==========================================================================
-
-  uint32_t    attrCoreFreq=0;     //MHz 
-  rc = FAPI_ATTR_GET(ATTR_FREQ_CORE_NOMINAL, NULL, attrCoreFreq);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_FREQ_CORE) returned error.\n");
-    return rc;
-  }
-
-  // SPURR freq ref SCOM
-  bScomEntry = 0;
-  scomData = ~((uint64_t)(attrCoreFreq/64)) + 1;
-  FAPI_INF("Fcore[MHz]=%d and SPURRBASE=0x%016llx",attrCoreFreq,scomData);
-  scomData = scomData<<(63-7) & (uint64_t)0xff<<(63-7);
-  FAPI_INF("scomData=0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_PERV_SPURR_FREQ_REF_0x100132A0,
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/SPURR freq ref unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/SPURR freq ref successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/SPURR freq ref data.\n");
-  }
-
-  // SPURR freq scale SCOM
-  bScomEntry = 0;
-  scomData = (uint64_t)0x40;
-  FAPI_INF("Fscale=0x%016llx",scomData);
-  scomData = scomData<<(63-7) & (uint64_t)0xff<<(63-7);
-  FAPI_INF("scomData=0x%016llx",scomData);
-  for (coreId=0; coreId<=15; coreId++)  {
-    if (attrCombGoodVec[P8_CID_EX_LOW+coreId])  {
-      rcLoc = p8_pore_gen_scom_fixed( 
-                      o_imageOut, 
-                      i_modeBuild,
-                      (uint32_t)EX_PERV_SPURR_FREQ_SCALE_0x1001329F,
-                      coreId,   // The core ID.
-                      scomData,
-                      P8_PORE_SCOM_REPLACE, // Repl 1st matching Scom addr, or add to EOT.
-                      P8_SCOM_SECTION_NC);  // Put in general Scom section.
-      if (rcLoc)  {
-        FAPI_ERR("\tUpdating SCOM NC table w/SPURR freq scale unsuccessful.\n");
-        uint32_t & RC_LOCAL = rcLoc;
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_GEN_SCOM_ERROR); 
-        return rc;
-      }
-      bScomEntry = 1;
-    }
-  }
-  if (bScomEntry)  {
-    FAPI_INF("Updating SCOM NC table w/SPURR freq scale successful.\n");
-  }
-  else  {
-    FAPI_INF("No active cores found. Did not update SCOM NC table w/SPURR freq scale data.\n");
-  }
-
-
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Workaround for HW273115. (By MikeO)
-  // Descr.:            If ivrm-enabled, initialize ivrm in special way for 
-  //                    winkles for S1-1.x, S1-2.0 and P8-1.x.
-  // Retrieval method:  Attribute.
-  // System phase:      SLW sysPhase.
-  // Assumptions:       ATTR_PM_IVRMS_ENABLED fully supported on FSP/HOST.
-  // ==========================================================================
-  uint8_t   attrIvrmEnabled=0, attrFixIvrmWinkleBug=1;
-  uint64_t  slwControlVector=0;
-
-  rc = FAPI_ATTR_GET(ATTR_PM_IVRMS_ENABLED, &i_target, attrIvrmEnabled);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_PM_IVRMS_ENABLED) returned error.\n");
-    return rc;
-  }
-
-#ifdef FAPIECMD  // This section only included for Cronus builds.
-  if (attrIvrmEnabled==0)  {
-    attrIvrmEnabled = 1;
-    FAPI_INF("Setting ATTR_PM_IVRMS_ENABLED = 0x%x.\n",attrIvrmEnabled);
-    rc = FAPI_ATTR_SET(ATTR_PM_IVRMS_ENABLED, &i_target, attrIvrmEnabled);
-    if (rc)  {
-      FAPI_ERR("FAPI_ATTR_SET(ATTR_PM_IVRMS_ENABLED) return error.\n");
-      return rc;
-    }
-  }
-#endif
-
-  rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_IVRM_WINKLE_BUG, &i_target, attrFixIvrmWinkleBug);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_IVRM_WINKLE_BUG) returned error.\n");
-    return rc;
-  }
-
-  if (attrIvrmEnabled && !attrFixIvrmWinkleBug)  {
-    rcLoc = sbe_xip_get_scalar( o_imageOut, "slw_control_vector", &slwControlVector);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_get_scalar() failed w/rc=%i", rcLoc);
-      FAPI_ERR("Probable cause: Key word =slw_control_vector not found in image.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    FAPI_INF("slwControlVector=0x%016llx",slwControlVector); 
-    slwControlVector = slwControlVector | BIT(63); 
-    FAPI_INF("slwControlVector=0x%016llx",slwControlVector); 
-    rcLoc = sbe_xip_set_scalar( o_imageOut, "slw_control_vector", slwControlVector);
-    if (rcLoc)  {
-      FAPI_ERR("sbe_xip_set_scalar() failed w/rc=%i", rcLoc);
-      FAPI_ERR("Probable cause: Key word =slw_control_vector not found in image.");
-      uint32_t &RC_LOCAL=rcLoc;
-      FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_KEYWORD_NOT_FOUND_ERROR);
-      return rc;
-    }
-    FAPI_INF("Updated slw_control_vector to trigger iVRM winkle bug fix.\n");
-  }
-  else  {
-    FAPI_INF("Did NOT update slw_control_vector to trigger iVRM winkle bug fix.\n");
-  }
-  
-  
-  
-  }  // End of if (i_sysPhase==1)
-
-
-  //
-  // Done customizing, yeah!!
-  //  
-
-  sbe_xip_image_size( o_imageOut, &io_sizeImageOut);
-  
-  FAPI_INF("XIPC:  Final output image:\n ");
-  FAPI_INF("  location=0x%016llx\n  size (actual)=%i\n  size (max allowed)=%i\n ", 
-    (uint64_t)o_imageOut, io_sizeImageOut, sizeImageMax);
-  FAPI_INF("XIPC:  Input image (just for reference):\n ");
-  FAPI_INF("  location=0x%016llx\n  size=%i\n ", 
-    (uint64_t)i_imageIn, sizeImageIn);
-  
-  if (io_sizeImageOut>sizeImageMax)  {
-    FAPI_ERR("XIPC: Final output image size (=%i) exceeds max size allowed (=%i).",
-      io_sizeImageOut, sizeImageMax);
-    uint32_t & DATA_IMG_SIZE = io_sizeImageOut;
-    uint32_t & DATA_IMG_SIZE_MAX = sizeImageMax;
-    FAPI_SET_HWP_ERROR(rc, RC_PROC_XIPC_IMAGE_SIZE_MESS);
-    return rc;
-  }
-
-  return FAPI_RC_SUCCESS;
-  
-}
-
-
-} // End of extern C
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H
deleted file mode 100644
index 1e9edf00d..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H
+++ /dev/null
@@ -1,76 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_xip_customize.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_xip_customize.H,v 1.9 2014/05/28 02:35:45 cmolsen Exp $
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*p8_xip_customize_FP_t) (  const fapi::Target&, 
-                                                    void*,
-                                                    void*,
-                                                    uint32_t&,
-                                                    const uint8_t,
-                                                    const uint8_t,
-                                                    void*,
-                                                    const uint32_t,
-                                                    void*,
-                                                    const uint32_t,
-                                                     uint32_t& );
-
-extern "C"
-{
-
-//
-// Function declares.
-//
-
-  // Description: 
-  // FAPI HWP entry point for p8_xip_customize().
-  // p8_xip_customize() adds VPD rings to the IPL and SLW images and updates
-  //   various vectors in the images.
-  //
-  // Parameters:  
-  // fapi::Target &i_target:        Processor chip target.
-  // void         *i_imageIn:       Ptr to input IPL or SLW image.
-  // void         *i_imageOut:      Ptr to output IPL img. (Ignored for SLW/RAM imgs.)
-  // uint32_t     &io_sizeImageOut: In: Max size of IPL/SRAM img. Out: Final size.
-  // uint8_t      i_sysPhase:       0: IPL  1: SLW
-  // uint8_t      i_modeBuild:      0: HB/IPL  1: PHYP/Rebuild  2: SRAM 
-  // void         *i_buf1:          Temp buffer1 for dexed RS4 ring. Caller allocs/frees.
-  // uint32_t     i_sizeBuf1:       Size of buf1.
-  // void         *i_buf2:          Temp buffer2 for WF ring. Caller allocs/frees.
-  // uint32_t     i_sizeBuf22       Size of buf2.
-  // uint32_t     &io_bootCoreMask  In: Mask of the desired boot cores (bits 16:31 = EX0:EX15)
-  //                                    (value is ignored when i_sysPhase != 0)
-  //                                Out: Mask of the valid boot cores in the image
-  fapi::ReturnCode p8_xip_customize( const fapi::Target &i_target,
-                                     void           *i_imageIn,
-                                     void           *i_imageOut,
-                                     uint32_t       &io_sizeImageOut,
-                                     const uint8_t  i_sysPhase,
-                                     const uint8_t  i_modeBuild, 
-                                     void           *i_buf1,
-                                     const uint32_t i_sizeBuf1,
-                                     void           *i_buf2,
-                                     const uint32_t i_sizeBuf2,
-                                     uint32_t       &io_bootCoreMask);
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h
deleted file mode 100644
index 3d985f80f..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h
+++ /dev/null
@@ -1,1169 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pgas.h $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __PGAS_H__
-#define __PGAS_H__
-
-#define __PGAS__
-
-// $Id: pgas.h,v 1.21 2013/11/20 14:06:39 bcbrock Exp $
-
-// ** WARNING : This file is maintained as part of the OCC firmware.  Do **
-// ** not edit this file in the PMX area, the hardware procedure area,   **
-// ** or the PoreVe area as any changes will be lost.                    **
-
-/// \file pgas.h
-/// \brief Pore GAS
-///
-/// PGAS is documented in a seperate standalone document entitled <em> PGAS :
-/// PORE GAS (GNU Assembler) User's and Reference Manual </em>.
-///
-/// This file defines support macros for the GNU PORE assembler, and the PORE
-/// inline assembler and disassebler which follow the PGAS assembly syntax.
-/// If the compile swith PGAS_PPC is defined in the environment then pgas.h
-/// includes pgas_ppc.h which transforms a PowerPC assembler into an assembler
-/// for PORE.
-
-// These are the opcodes and mnemonics as defined by the PORE hardware
-// manual.  Many of them will change names slightly in PGAS.  
-
-#define PORE_OPCODE_NOP     0x0f
-#define PORE_OPCODE_WAIT    0x01
-#define PORE_OPCODE_TRAP    0x02
-#define PORE_OPCODE_HOOK    0x4f
-
-#define PORE_OPCODE_BRA     0x10
-#define PORE_OPCODE_BRAZ    0x12
-#define PORE_OPCODE_BRANZ   0x13
-#define PORE_OPCODE_BRAI    0x51
-#define PORE_OPCODE_BSR     0x14
-#define PORE_OPCODE_BRAD    0x1c
-#define PORE_OPCODE_BSRD    0x1d
-#define PORE_OPCODE_RET     0x15
-#define PORE_OPCODE_CMPBRA  0x56
-#define PORE_OPCODE_CMPNBRA 0x57
-#define PORE_OPCODE_CMPBSR  0x58
-#define PORE_OPCODE_LOOP    0x1f
-
-#define PORE_OPCODE_ANDI    0x60
-#define PORE_OPCODE_ORI     0x61
-#define PORE_OPCODE_XORI    0x62
-        
-#define PORE_OPCODE_AND     0x25
-#define PORE_OPCODE_OR      0x26
-#define PORE_OPCODE_XOR     0x27
-        
-#define PORE_OPCODE_ADD     0x23
-#define PORE_OPCODE_ADDI    0x24
-#define PORE_OPCODE_SUB     0x29
-#define PORE_OPCODE_SUBI    0x28
-#define PORE_OPCODE_NEG     0x2a
-
-#define PORE_OPCODE_COPY    0x2c
-#define PORE_OPCODE_ROL     0x2e
-
-#define PORE_OPCODE_LOAD20  0x30
-#define PORE_OPCODE_LOAD64  0x71
-#define PORE_OPCODE_SCR1RD  0x32
-#define PORE_OPCODE_SCR1RDA 0x73
-#define PORE_OPCODE_SCR2RD  0x36
-#define PORE_OPCODE_SCR2RDA 0x77
-#define PORE_OPCODE_WRI     0x78
-#define PORE_OPCODE_BS      0x74
-#define PORE_OPCODE_BC      0x75
-#define PORE_OPCODE_SCR1WR  0x39
-#define PORE_OPCODE_SCR2WR  0x3a
-#define PORE_OPCODE_SCAND   0x7c
-
-
-// These are the PGAS versions of the PORE opcodes used in the legacy PGAS_PPC
-// assembler and the current PORE inline assembler/disassembler.
-
-#define PGAS_OPCODE_NOP       PORE_OPCODE_NOP     
-#define PGAS_OPCODE_WAITS     PORE_OPCODE_WAIT    
-#define PGAS_OPCODE_TRAP      PORE_OPCODE_TRAP    
-#define PGAS_OPCODE_HOOKI     PORE_OPCODE_HOOK    
-
-#define PGAS_OPCODE_BRA       PORE_OPCODE_BRA     
-#define PGAS_OPCODE_BRAZ      PORE_OPCODE_BRAZ    
-#define PGAS_OPCODE_BRANZ     PORE_OPCODE_BRANZ   
-#define PGAS_OPCODE_BRAI      PORE_OPCODE_BRAI    
-#define PGAS_OPCODE_BSR       PORE_OPCODE_BSR 
-#define PGAS_OPCODE_BRAD      PORE_OPCODE_BRAD    
-#define PGAS_OPCODE_BSRD      PORE_OPCODE_BSRD    
-#define PGAS_OPCODE_RET       PORE_OPCODE_RET     
-#define PGAS_OPCODE_CMPIBRAEQ PORE_OPCODE_CMPBRA  
-#define PGAS_OPCODE_CMPIBRANE PORE_OPCODE_CMPNBRA 
-#define PGAS_OPCODE_CMPIBSREQ PORE_OPCODE_CMPBSR  
-#define PGAS_OPCODE_LOOP      PORE_OPCODE_LOOP    
-
-#define PGAS_OPCODE_ANDI      PORE_OPCODE_ANDI    
-#define PGAS_OPCODE_ORI       PORE_OPCODE_ORI     
-#define PGAS_OPCODE_XORI      PORE_OPCODE_XORI    
-
-#define PGAS_OPCODE_AND       PORE_OPCODE_AND     
-#define PGAS_OPCODE_OR        PORE_OPCODE_OR      
-#define PGAS_OPCODE_XOR       PORE_OPCODE_XOR     
-
-#define PGAS_OPCODE_ADD       PORE_OPCODE_ADD     
-#define PGAS_OPCODE_ADDS      PORE_OPCODE_ADDI    
-#define PGAS_OPCODE_SUB       PORE_OPCODE_SUB     
-#define PGAS_OPCODE_SUBS      PORE_OPCODE_SUBI    
-#define PGAS_OPCODE_NEG       PORE_OPCODE_NEG     
-
-#define PGAS_OPCODE_MR        PORE_OPCODE_COPY    
-#define PGAS_OPCODE_ROLS      PORE_OPCODE_ROL     
-
-#define PGAS_OPCODE_LS        PORE_OPCODE_LOAD20  
-#define PGAS_OPCODE_LI        PORE_OPCODE_LOAD64  
-#define PGAS_OPCODE_LD0       PORE_OPCODE_SCR1RD  /* Used by LD */
-#define PGAS_OPCODE_LD0ANDI   PORE_OPCODE_SCR1RDA /* Used by LDANDI */
-#define PGAS_OPCODE_LD1       PORE_OPCODE_SCR2RD  /* Used by LD */
-#define PGAS_OPCODE_LD1ANDI   PORE_OPCODE_SCR2RDA /* Used by LDANDI */
-#define PGAS_OPCODE_STI       PORE_OPCODE_WRI     
-#define PGAS_OPCODE_STD0      PORE_OPCODE_SCR1WR  /* Used by STD */
-#define PGAS_OPCODE_STD1      PORE_OPCODE_SCR2WR  /* Used by STD */
-#define PGAS_OPCODE_SCAND     PORE_OPCODE_SCAND   
-
-#ifdef IGNORE_HW274735
-
-// BSI and BCI are normally redacted due to HW274735. See also pgas.h
-
-#define PGAS_OPCODE_BSI       PORE_OPCODE_BS      
-#define PGAS_OPCODE_BCI       PORE_OPCODE_BC      
-
-#endif // IGNORE_HW274735
-
-// These are the programmer-visible register names as defined by the PORE
-// hardware manual.  All of these names (except the PC) appear differently in
-// the PGAS syntax, in some cases to reduce confusion, in other cases just to
-// have more traditional short mnemonics.
-
-#define PORE_REGISTER_PRV_BASE_ADDR0  0x0
-#define PORE_REGISTER_PRV_BASE_ADDR1  0x1
-#define PORE_REGISTER_OCI_BASE_ADDR0  0x2
-#define PORE_REGISTER_OCI_BASE_ADDR1  0x3
-#define PORE_REGISTER_SCRATCH0        0x4
-#define PORE_REGISTER_SCRATCH1        0x5
-#define PORE_REGISTER_SCRATCH2        0x6
-#define PORE_REGISTER_ERROR_MASK      0x7
-#define PORE_REGISTER_EXE_TRIGGER     0x9
-#define PORE_REGISTER_DATA0           0xa
-#define PORE_REGISTER_PC              0xe
-#define PORE_REGISTER_IBUF_ID         0xf
-
-
-// PgP IBUF_ID values
-
-#define PORE_ID_GPE0 0x00
-#define PORE_ID_GPE1 0x01
-#define PORE_ID_SLW  0x08
-#define PORE_ID_SBE  0x04
-
-
-// Condition Codes
-
-#define PORE_CC_UGT 0x8000
-#define PORE_CC_ULT 0x4000
-#define PORE_CC_SGT 0x2000
-#define PORE_CC_SLT 0x1000
-#define PORE_CC_C   0x0800
-#define PORE_CC_V   0x0400
-#define PORE_CC_N   0x0200
-#define PORE_CC_Z   0x0100
-
-
-// Memory Spaces
-
-#define PORE_SPACE_UNDEFINED 0xffff
-#define PORE_SPACE_OCI       0x8000
-#define PORE_SPACE_PNOR      0x800b
-#define PORE_SPACE_OTPROM    0x0001
-#define PORE_SPACE_SEEPROM   0x800c
-#define PORE_SPACE_PIBMEM    0x0008             
-
-
-#ifdef __ASSEMBLER__
-
-////////////////////////////////////////////////////////////////////////////
-// PGAS Base Assembler Support
-////////////////////////////////////////////////////////////////////////////	
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Condition Codes
-        //////////////////////////////////////////////////////////////////////
-
-        .set    CC_UGT, PORE_CC_UGT 
-        .set    CC_ULT, PORE_CC_ULT 
-        .set    CC_SGT, PORE_CC_SGT 
-        .set    CC_SLT, PORE_CC_SLT 
-        .set    CC_C,   PORE_CC_C   
-        .set    CC_V,   PORE_CC_V   
-        .set    CC_N,   PORE_CC_N   
-        .set    CC_Z,   PORE_CC_Z
-
-
-	//////////////////////////////////////////////////////////////////////
-        // Utility Macros
-        //////////////////////////////////////////////////////////////////////
-
-        // 'Undefine' PowerPC mnemonics to trap programming errors
-
-        .macro  ..undefppc1, i
-        .ifnc   \i, ignore
-	.macro  \i, args:vararg
-	.error  "This is a PowerPC opcode - NOT a PGAS opcode or extended mnemonic"
-	.endm
-        .endif
-        .endm
-
-        .macro  .undefppc, i0, i1=ignore, i2=ignore, i3=ignore
-        ..undefppc1 \i0
-        ..undefppc1 \i1
-        ..undefppc1 \i2
-        ..undefppc1 \i3
-        .endm
-
-      
-        //////////////////////////////////////////////////////////////////////
-        // Argument Checking Macros
-        //////////////////////////////////////////////////////////////////////
-	//
-	// These macros remain in the final pgas.h file because 1) they are
-	// required for some PGAS pseudo-ops, and 2) to support robust
-	// assembler macro definitions. 
-
-	 // Check an unsigned immediate for size
-
-	.macro	..checku, x:req, bits:req, err="Unsigned value too large"
-
-	.if	(((\bits) <= 0) || ((\bits) > 63))
-	.error	"The number of bits must be in the range 0 < bits < 64"
-	.endif
-
-	.iflt	(\x)
-	.error  "An unsigned value is required here"
-        .endif
-	
-	.ifgt	((\x) - (0xffffffffffffffff >> (64 - (\bits))))
-	.error	"\err"
-	.endif
-
-	.endm
-
-        // Check unsigned 16/22-bit immediates for size
-        //
-        // In general, PGAS can check immediate values for size restrictions,
-        // but unfortunately is not able to check address offset immediates for
-        // range. 
-
-        .macro  ..check_u16, u16
-	..checku (\u16), 16, "Unsigned immediate is larger than 16 bits"
-        .endm
-
-        .macro  ..check_u24, u24
-	..checku (\u24), 24, "Unsigned immediate is larger than 24 bits"
-        .endm
-
-        // Check a 16/20/22-bit signed immediate for size
-
-        .macro  ..check_s16, s16
-        .iflt   \s16
-        .iflt   \s16 + 0x8000
-	.error  "Immediate value too small for a signed 16-bit field"
-        .endif
-        .else
-        .ifgt   \s16 - 0x7fff
-	.error  "Immediate value too large for a signed 16-bit field"
-        .endif
-        .endif
-        .endm
-
-        .macro  ..check_s20, s20
-        .iflt   \s20
-        .iflt   \s20 + 0x80000
-	.error  "Immediate value too small for a signed 20-bit field"
-        .endif
-        .else
-        .ifgt   \s20 - 0x7ffff
-	.error  "Immediate value too large for a signed 20-bit field"
-        .endif
-        .endif
-        .endm
-
-        .macro  ..check_s22, s22
-        .iflt   \s22
-        .iflt   \s22 + 0x200000
-	.error  "Immediate value too small for a signed 22-bit field"
-        .endif
-        .else
-        .ifgt   \s22 - 0x1fffff
-	.error  "Immediate value too large for a signed 22-bit field"
-        .endif
-        .endif
-        .endm
-
-	// Check a putative SCOM address for bits 0 and 8:11 == 0.
-
-	.macro	..check_scom, address
-	.if	((\address) & 0x80f00000)
-	.error	"Valid SCOM addresses must have bits 0 and 8:11 equal to 0."
-	.endif
-	.endm
-
-	// A register required to be D0
-
-	.macro	..d0, reg
-	.if	(\reg != D0)
-	.error	"Data register D0 is required here"
-	.endif
-	.endm
-
-	// A register pair required to be D0, D1 in order
-
-	.macro	..d0d1, reg1, reg2
-	.if	(((\reg1) != D0) && ((\reg2) != D1))
-	.error	"Register-Register ALU operations are only defined on the source pair D0, D1"
-	.endif
-	.endm
-
-	// A register pair required to be D0, D1 in any order
-	.macro	..dxdy, reg1, reg2, err="Expecting D0, D1 in either order"
-	.if	!((((\reg1) == D0) && ((\reg2) == D1)) || \
-		  (((\reg1) == D1) && ((\reg2) == D0)))
-	.error "\err"
-	.endif
-	.endm
-
-	// A register pair required to be A0, A1 in any order
-	.macro	..axay, reg1, reg2, err="Expecting A0, A1 in either order"
-	.if	!((((\reg1) == A0) && ((\reg2) == A1)) || \
-		  (((\reg1) == A1) && ((\reg2) == A0)))
-	.error "\err"
-	.endif
-	.endm
-
-	// A register pair required to be the same register
-
-	.macro	..same, dest, src
-	.if	((\dest) != (\src))
-	.error	"PGAS requires the src and dest register of ADDS/SUBS to be explicit and identical"
-	.endif
-	.endm
-	
-        // A "Data" register	
-
-        .macro  ..data, reg:req, err="Expecting a 'Data' register"
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .error  "\err"
-        .endif
-        .endif
-        .endm
-
-        // An "Address" register
-
-        .macro  ..address, reg:req, err=:"Expecting an 'Address' register"
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .error  "\err"
-        .endif
-        .endif
-        .endm
-
-        // A "Pervasive Chiplet ID" register
-
-        .macro  ..pervasive_chiplet_id, reg:req, err="Expecting a 'Pervasive Chiplet ID' register"
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .error  "\err"
-        .endif
-        .endif
-        .endm
-
-        // A "Branch Compare Data" register
-
-        .macro  ..branch_compare_data, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1) 
-        .if     (\reg != CTR)
-        .error  "Expecting a 'Branch Compare Data' register"
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "LS Destination" register; Also the set for ADDS/SUBS
-
-        .macro  ..ls_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .if     (\reg != CTR)
-        .error "Expecting an 'LS Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "LI Destination" register
-
-        .macro  ..li_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != CTR)
-        .error "Expecting an 'LI Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-        // An "LIA Destination" register 
-
-        .macro  ..lia_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != TBAR)
-        .error "Expecting an 'LIA Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-	// An "MR Source" register
-
-	.macro	..mr_source, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .if     (\reg != CTR)
-        .if     (\reg != PC)
-        .if     (\reg != ETR)
-        .if     (\reg != SPRG0)
-        .if     (\reg != IFR)
-	.if	(\reg != EMR)
-	.error	"Expecting an 'MR Source' register"
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endm
-
-        // An "MR Destination" register
-
-        .macro  ..mr_destination, reg
-        .if     (\reg != D0)
-        .if     (\reg != D1)
-        .if     (\reg != A0)
-        .if     (\reg != A1)
-        .if     (\reg != P0)
-        .if     (\reg != P1)
-        .if     (\reg != CTR)
-        .if     (\reg != PC)
-        .if     (\reg != ETR)
-        .if     (\reg != SPRG0)
-	.if	(\reg != EMR)
-        .error "Expecting an 'MR Destination' register"
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endif
-        .endm
-
-
-	//////////////////////////////////////////////////////////////////////
-        // PORE address spaces
-        //////////////////////////////////////////////////////////////////////
-
-        // The ..set_address_space pseudo-op defines the default address
-	// space. It must be defined in order to use BRAA, BRAIA, BSR and
-	// CMPIBSR.  Pseudo-ops are provided to set the default space of the
-	// program.  Note that code assembled for PNOR will also work in the
-	// OCI space in the Sleep/Winkle engine.
-
-        .macro  ..set_default_space, s
-	..check_u16 (\s)
-        .set    _PGAS_DEFAULT_SPACE, (\s)
-        .endm
-
-	.macro	..check_default_space
-	.if	(_PGAS_DEFAULT_SPACE == PORE_SPACE_UNDEFINED)
-	.error	"The PGAS default address space has not been defined"
-	.endif
-	.endm	
-
-	..set_default_space PORE_SPACE_UNDEFINED
-
-	.macro	.oci
-	..set_default_space PORE_SPACE_OCI
-	.endm
-
-	.macro	.pnor
-	..set_default_space PORE_SPACE_PNOR
-	.endm
-
-	.macro	.seeprom
-	..set_default_space PORE_SPACE_SEEPROM
-	.endm
-
-	.macro	.otprom
-	..set_default_space PORE_SPACE_OTPROM
-	.endm
-
-	.macro	.pibmem
-	..set_default_space PORE_SPACE_PIBMEM
-#ifndef PGAS_PPC
-	.pibmem_port (PORE_SPACE_PIBMEM & 0xf)
-#else
-        // NB: PGAS_PPC does not support relocatable PIBMEM addressing
-#endif
-	.endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Address-Generation Pseudo Ops
-        //////////////////////////////////////////////////////////////////////
-
-	// .QUADA, .QUADIA
-
-	.macro	.quada, offset:req
-	..check_default_space
-	.long   _PGAS_DEFAULT_SPACE
-	.long	(\offset)
-	.endm
-	
-	.macro	.quadia, space:req, offset:req
-	..check_u16 (\space)
-	.long	(\space)
-	.long	(\offset)
-	.endm
-
-        //////////////////////////////////////////////////////////////////////
-        // Bug workarounds
-        //////////////////////////////////////////////////////////////////////
-
-#ifndef IGNORE_HW274735
-
-        // HW274735 documents that BC and BS are broken for the PORE-GPE0/1
-        // pair. This bug is unfixed in POWER8, and by default we require BSI
-        // and BCI to be implemented as macros on all engines. For
-        // compatability we continue to require that dx == D0.
-
-        .macro  bsi, dx:req, offset:req, base:req, imm:req
-        ..d0    (\dx)
-        ld      D0, (\offset), (\base)
-        ori     D0, D0, (\imm)
-        std     D0, (\offset), (\base)
-        .endm
-
-        .macro  bci, dx:req, offset:req, base:req, imm:req
-        ..d0    (\dx)
-        ldandi  D0, (\offset), (\base), ~(\imm)
-        std     D0, (\offset), (\base)
-        .endm
-
-#endif // IGNORE_HW274735
-
-	//////////////////////////////////////////////////////////////////////
-	// "A"- and "IA"-form Instructions
-	//////////////////////////////////////////////////////////////////////
-
-        // BRAA (Branch Address) is a 'long branch' to an address in the
-	// default memory space.
-
-	.macro	braa, offset:req
-	braia	_PGAS_DEFAULT_SPACE, (\offset)
-	.endm
-
-	// LA (Load Address) loads the full address of an address in the
-	// default memory space.
-
-	.macro	la, dest:req, offset:req
-	lia	(\dest), _PGAS_DEFAULT_SPACE, (\offset)
-	.endm
-
-	// STA (Store Address) stores the full address of an address in the
-	// default memory space.
-
-	.macro	sta, mem_offset:req, base:req, addr_offset:req
-	stia	(\mem_offset), (\base), _PGAS_DEFAULT_SPACE, (\addr_offset)
-	.endm
-
-	// BSRIA is a subroutine branch into another memory space.  This has to
-	// be emulated by a local subroutine branch and a BRAIA.
-	
-	.macro	bsria, space:req, offset:req
-	bsr	27742f
-	bra	27743f
-27742:
-	braia	(\space), (\offset)
-27743:	
-	.endm             
-
-
-////////////////////////////////////////////////////////////////////////////
-// Extended Mnemonics, Macros and Special Cases
-////////////////////////////////////////////////////////////////////////////
-
-	//////////////////////////////////////////////////////////////////////
-	// TFB<c> - Test flags and branch conditionally
-	//////////////////////////////////////////////////////////////////////'
-	
-	.macro	..tfb, dest, target, flags
-	..data	(\dest)
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), (\flags)
-	branz	(\dest), (\target)
-	.endm	
-
-	.macro	..tfbn dest, target, flags
-	..data	(\dest)
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), (\flags)
-	braz	(\dest), (\target)
-	.endm	
-
-	.macro	tfbcs, dest:req, target:req
-	..tfb	 (\dest), (\target), CC_C
-	.endm
-
-	.macro	tfbcc, dest:req, target:req
-	..tfbn	(\dest), (\target), CC_C
-	.endm
-
-	.macro	tfbvs, dest:req, target:req
-	..tfb	 (\dest), (\target), CC_V
-	.endm
-
-	.macro	tfbvc, dest:req, target:req
-	..tfbn	 (\dest), (\target), CC_V
-	.endm
-
-	.macro	tfbns, dest:req, target:req
-	..tfb	 (\dest), (\target), CC_N
-	.endm
-
-	.macro	tfbnc, dest:req, target:req
-	..tfbn	 (\dest), (\target), CC_N
-	.endm
-
-	.macro	tfbeq, dest:req, target:req
-	..tfb	(\dest), (\target), CC_Z
-	.endm
-
-	.macro	tfbne, dest:req, target:req
-	..tfbn	(\dest), (\target), CC_Z
-	.endm
-
-	.macro	tfbult, dest:req, target:req
-	..tfb	(\dest), (\target), CC_ULT
-	.endm
-
-	.macro	tfbule, dest:req, target:req
-	..tfbn	(\dest), (\target), CC_UGT
-	.endm
-
-	.macro	tfbuge, dest:req, target:req
-	..tfbn	(\dest), (\target), CC_ULT
-	.endm
-
-	.macro	tfbugt, dest:req, target:req
-	..tfb	(\dest), (\target), CC_UGT
-	.endm
-
-	.macro	tfbslt, dest:req, target:req
-	..tfb	(\dest), (\target), CC_SLT
-	.endm
-
-	.macro	tfbsle, dest:req, target:req
-	..tfbn	(\dest), (\target), CC_SGT
-	.endm
-
-	.macro	tfbsge, dest:req, target:req
-	..tfbn	(\dest), (\target), CC_SLT
-	.endm
-
-	.macro	tfbsgt, dest:req, target:req
-	..tfb	(\dest), (\target), CC_SGT
-	.endm
-
-
-	//////////////////////////////////////////////////////////////////////
-	// TEB[N]<eng> - Test Engine and branch if [not] engine.
-	//////////////////////////////////////////////////////////////////////
-	//
-	// All but GPE0 use a 1-hot code.
-	
-	.macro	tebgpe0, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), 0xf
-	braz	(\dest), (\target)
-	.endm	
-
-	.macro	tebgpe1, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), PORE_ID_GPE1
-	branz	(\dest), (\target)
-	.endm	
-
-	.macro	tebslw, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), PORE_ID_SLW
-	branz	(\dest), (\target)
-	.endm	
-
-	.macro	tebsbe, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), PORE_ID_SBE
-	branz	(\dest), (\target)
-	.endm	
-
-
-	.macro	tebngpe0, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), 0xf
-	branz	(\dest), (\target)
-	.endm	
-
-	.macro	tebngpe1, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), PORE_ID_GPE1
-	braz	(\dest), (\target)
-	.endm	
-
-	.macro	tebnslw, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), PORE_ID_SLW
-	braz	(\dest), (\target)
-	.endm	
-
-	.macro	tebnsbe, dest:req, target:req
-	mr	(\dest), IFR
-	andi	(\dest), (\dest), PORE_ID_SBE
-	braz	(\dest), (\target)
-	.endm	
-
-
-        //////////////////////////////////////////////////////////////////////
-        // EXTRPRC   - Extract and right-justify the PIB/PCB return code
-        // TPRCB[N]Z - Test PIB return code and branch if [not] zero
-        // TPRCBGT   - Test PIB return code and branch if greater-than
-        // TPRCBLE   - Test PIB return code and branch if less-then or equal
-        //////////////////////////////////////////////////////////////////////
-        //
-        // To support cases where PORE code expects or must explicitly handle
-        // non-0 PIB return codes, the PIB return code and parity indication
-        // are stored in bits 32 (parity) and 33-35 (return code) of the IFR.
-        // These macros extract the four PIB/PCB status bits from the IFR and
-        // right-justifies them into the data register provided. For EXTRPRC
-        // that is the total function of the macro. The TPRCB[N]Z macros
-        // provide a simple non-destructive test and branch for zero (success)
-        // and non-zero (potential problem) codes after the extraction.
-        //
-        // In complex error handling scenarios one would typically compare the
-        // PIB return code against an upper-bound, e.g., the offline response
-        // (0x2), and then take further action. If the parity error bit is set
-        // then this would produce an aggregate "return code" higher than any
-        // that one would typically want to ignore. The TPRCBGT/TPRCBLE macros
-        // provide this function; however the test destroys the extracted
-        // return code so that if further analysis is required the code will
-        // need to be a extracted again.
-        //////////////////////////////////////////////////////////////////////
-
-        .macro  extrprc, dest:req
-        ..data  (\dest)
-        mr      (\dest), IFR
-        extrdi  (\dest), (\dest), 4, 32             
-        .endm
-
-        .macro  tprcbz, dest:req, target:req
-        extrprc (\dest)
-        braz    (\dest), (\target)
-        .endm
-        
-        .macro  tprcbnz, dest:req, target:req
-        extrprc (\dest)
-        branz   (\dest), (\target)
-        .endm
-        
-        .macro  tprcbgt, dest:req, target:req, bound:req
-        extrprc (\dest)
-        subs    (\dest), (\dest), (\bound)
-        tfbugt  (\dest), (\target)
-        .endm
-        
-        .macro  tprcble, dest:req, target:req, bound:req
-        extrprc (\dest)
-        subs    (\dest), (\dest), (\bound)
-        tfbule  (\dest), (\target)
-        .endm
-        
-	//////////////////////////////////////////////////////////////////////
-	// LPCS - Load Pervasive Chiplet from Scom address
-	//////////////////////////////////////////////////////////////////////
-
-	.macro	lpcs, dest:req, scom:req
-	..pervasive_chiplet_id (\dest)
-	..check_scom (\scom)
-	ls	(\dest), (((\scom) >> 24) & 0x7f)
-	.endm
-
-
-        //////////////////////////////////////////////////////////////////////
-        // Shift/Mask extended mnemonics
-        //////////////////////////////////////////////////////////////////////
-
-        // All of the 'dot-dot' macros assume that error and identity
-	// checking has been done on the arguments already.
-
-        // The initial register-register rotate.  If the incoming shift amount
-        // is 0 then the instruction generated is a simple MR.
-
-        .macro  ..rotlrr, ra, rs, sh
-
-        .if     (\sh) >= 32
-                rols    (\ra), (\rs), 32
-                ..rotlr  (\ra), ((\sh) - 32)
-        .elseif (\sh) >= 16
-                rols    (\ra), (\rs), 16
-                ..rotlr  (\ra), ((\sh) - 16)
-        .elseif (\sh) >= 8
-                rols    (\ra), (\rs), 8
-                ..rotlr  (\ra), ((\sh) - 8)
-        .elseif (\sh) >= 4
-                rols    (\ra), (\rs), 4
-                ..rotlr  (\ra), ((\sh) - 4)
-        .elseif (\sh) >= 1
-                rols    (\ra), (\rs), 1
-                ..rotlr  (\ra), ((\sh) - 1)
-        .else
-                mr      (\ra), (\rs)
-        .endif
-
-        .endm
-
-
-        // Subsequent rotation of the same register.  The SH should never be 0
-        // here. 
-
-        .macro  ..rotlr, ra, sh
-
-        .if     (\sh) >= 32
-                rols    (\ra), (\ra), 32
-                ..rotlr  (\ra), ((\sh) - 32)
-        .elseif (\sh) >= 16
-                rols    (\ra), (\ra), 16
-                ..rotlr  (\ra), ((\sh) - 16)
-        .elseif (\sh) >= 8
-                rols    (\ra), (\ra), 8
-                ..rotlr  (\ra), ((\sh) - 8)
-        .elseif (\sh) >= 4
-                rols    (\ra), (\ra), 4
-                ..rotlr  (\ra), ((\sh) - 4)
-        .elseif (\sh) >= 1
-                rols    (\ra), (\ra), 1
-                ..rotlr  (\ra), ((\sh) - 1)
-
-        .endif
-
-        .endm
-
-
-        // RLDINM RA, RS, SH, MB, ME
-        //
-        // Defined as if there were an equivalent PowerPC instruction. The
-        // 'word' forms of the PowerPC instructions and extended mnemonics are
-        // undefined in order to catch programming typos.
-
-        .undefppc       rlwinm, extrwi, rotlwi, rotrwi
-        .undefppc       slwi, srwi
-
-        .macro  rldinm, ra:req, rs:req, sh:req, mb:req, me:req
-
-        .if     ((\sh) < 0) || ((\sh) > 63)
-                .error  "SH must be in the range 0..63"
-        .endif
-        .if     ((\mb) < 0) || ((\mb) > 63)
-                .error  "MB must be in the range 0..63"
-        .endif
-        .if     ((\me) < 0) || ((\me) > 63)
-                .error  "ME must be in the range 0..63"
-        .endif
-        
-        .if     (((\mb) == 0) && ((\me) == 63) || ((\me) == ((\mb) - 1)))
-
-                // The mask is effectively 0..63, i.e., no mask. This is a
-                // simple rotate.
-                
-                ..rotlrr (\ra), (\rs), (\sh)
-        
-        .else
-        
-                // We need a mask step.  However if SH == 0 and RA == RS we can
-                // bypass the rotate step.
-                
-                .if     ((\sh) != 0) || ((\ra) != (\rs))
-                        ..rotlrr (\ra), (\rs), (\sh)
-                .endif
-                .if     ((\mb) <= (\me))
-
-                        // This is a straightforward masking operation with a
-                        // single mask.
-                
-                        andi    (\ra), (\ra), ((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - (\me))))
-                .else
-                
-                        // This is a wrapped mask.  
-                        // It is created as 2 masks OR-ed together - 0-ME and MB-63
-                
-                        andi    (\ra), (\ra), (((0xffffffffffffffff >> 0) & (0xffffffffffffffff << (63 - (\me)))) | ((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - 63))))
-                .endif
-        
-        .endif
-        
-        .endm           
-
-        // RLDINM Extended Mnemonics
-        //
-        // Defined as if they were equivalent to PowerPC 32-bit extended
-	// mnemonics
-
-        .macro  extldi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "EXTLDI requires N > 0"
-        .endif
-         rldinm (\ra), (\rs), (\b), 0, ((\n) - 1)
-        .endm
-
-        .macro  extrdi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "EXTRDI requires N > 0"
-        .endif
-        rldinm  (\ra), (\rs), (((\b) + (\n)) % 64), (64 - (\n)), 63
-        .endm
-
-        .macro  rotldi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (\n), 0, 63
-        .endm
-
-
-        .macro  rotrdi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (64 - (\n)), 0, 63
-        .endm
-
-
-        .macro  sldi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (\n), 0, (63 - (\n))
-        .endm
-        
-
-        .macro  srdi, ra:req, rs:req, n:req
-        rldinm  (\ra), (\rs), (64 - (\n)), (\n), 63
-        .endm
-        
-
-        // RLDIMI RA, RS, SH, MB, ME
-        //
-        // Defined as if there were an equivalent PowerPC instruction. The
-        // 'word' forms of the PowerPC instructions and extended mnemonics are
-        // undefined in order to catch programming typos.
-        //
-        // Note that unlike the PowerPC instructions, here RLDIMI must destroy
-        // RS by masking and shifting it, and RA and RS may not be the same
-	// register. 
-
-        .undefppc       rlwimi, inslwi, insrwi
-
-        .macro  rldimi, ra:req, rs:req, sh:req, mb:req, me:req
-
-	..dxdy	(\ra), (\rs)
-
-	// SH error checks are done by rldinm
-	        
-        .if     (((\mb) == 0) && ((\me) == 63) || ((\me) == ((\mb) - 1)))
-
-                // The mask is effectively 0..63, i.e., no mask. This is a
-                // simple rotate of RS into RA
-                
-		rotldi	(\ra), (\rs), (\sh)
-        
-        .else
-
-		// Rotate RS and AND with mask
-
-		rldinm	(\rs), (\rs), (\sh), (\mb), (\me)
-
-		// Mask out the significant bits of RS, clear that section of
-		// RA, and logical OR RS into RA
-        
-                .if     ((\mb) <= (\me))
-
-                        // This is a straightforward masking operation with a
-                        // single mask.
-                
-                        andi    (\ra), (\ra), \
-				 (~((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - (\me)))))
-                .else
-                
-                        // This is a wrapped mask.  
-                        // It is created as 2 masks OR-ed together - 0-ME and MB-63
-                
-                        andi    (\ra), (\ra), \
-				(~(((0xffffffffffffffff >> 0) & (0xffffffffffffffff << (63 - (\me)))) | \
-		                  ((0xffffffffffffffff >> (\mb)) & (0xffffffffffffffff << (63 - 63)))))
-                .endif
-
-		or	(\ra), D0, D1
-        
-        .endif
-
-        .endm           
-
-	// RLDIMI Extended Mnemonics
-        //
-        // Defined as if they were equivalent to PowerPC 32-bit extended
-	// mnemonics
-
-        .macro  insldi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "INSLDI requires N > 0"
-        .endif
-	rldimi	 (\ra), (\rs), (64 - (\b)), (\b), ((\b) + (\n) - 1)
-        .endm
-
-        .macro  insrdi, ra:req, rs:req, n:req, b:req
-        .if     ((\n) < 0)
-                .error  "INSRDI requires N > 0"
-        .endif
-        rldimi  (\ra), (\rs), (64 - (\b) - (\n)), (\b), ((\b) + (\n) - 1)
-        .endm
-
-
-	//////////////////////////////////////////////////////////////////////
-        // .HOOK
-	//////////////////////////////////////////////////////////////////////
-
-        // The PoreVe (PORE Virtual Environment) is a PORE simulation
-        // environment that allows the programmer to embed C/C++ code into the
-        // PORE assembler source code, and arranges for the C/C++ code to be
-        // executed in-line with the PORE assembly code.  Instances of the
-        // .hook macro are inserted into the assembler input by the
-        // hook_extractor script, to mark the locations where hooks are
-        // present.  The hook reference is a string that combines the source
-        // file name with an index number to uniquely identify the hook.
-        //
-        //     .hook <file name>_<sequence number>
-        //
-        // The .hook macro marks the location of each hook in the relocatable
-        // binaries with special symbols.  The symbol name includes the hook
-        // reference, which is used to locate the hook in the HookManager
-        // symbol table. Because hooks can be defined in macros, a hook that
-        // appears once in a source file may appear multiple times in the
-        // final binary.  For this reason each hook must also be tagged with a
-        // unique index number to avoid symbol name collisions.  The
-        // complexity of the .hook macro is due to the necessity to decode a
-        // dynamic symbol value (_PGAS_HOOK_INDEX) into its binary string form
-        // to create the unique symbol name.  The final hook symbol has the
-        // form:
-        //
-        // __hook__<unique>_<reference>
-        //
-        // where <unique> is a binary string. It is then straightforward to
-        // locate these symbols in the 'nm' output of the final link and
-        // create a map of final addresses to the hook routine to call (the
-        // <reference>) before executing the instruction at that address.
-        //
-        // Note: The maximum nesting depth of the recursive ..hook_helper
-        // macro is log2(index), and the assembler supports nesting of at
-        // least 32 which is much more than sufficient.
-
-        .set    _PGAS_HOOK_INDEX, 0
-
-        .macro  .hook, reference:req
-        .set    _PGAS_HOOK_INDEX, (_PGAS_HOOK_INDEX + 1)
-        ..hook_helper _PGAS_HOOK_INDEX, "", \reference
-        .endm
-
-        .macro  ..hook_helper, index, unique, reference
-        .ifeq   \index
-        __hook__\unique\()_\reference\():       
-        .elseif (\index % 2)
-        ..hook_helper (\index / 2), 1\unique, \reference
-        .else
-        ..hook_helper (\index / 2), 0\unique, \reference
-        .endif
-        .endm
-
-
-////////////////////////////////////////////////////////////////////////////
-// Help for Conversion from Old to New PGAS syntax
-////////////////////////////////////////////////////////////////////////////
-
-	.macro	loadp, arg:vararg
-	.error	"PGAS now implements 'lpcs' rather then 'loadp'"
-	.endm
-
-	.macro	loadx, arg:vararg
-	.error	"PGAS now implements 'la' rather than 'loadx'"
-	.endm
-
-#endif  // __ASSEMBLER__
-                    
-#ifdef PGAS_PPC
-#include "pgas_ppc.h"
-#endif
-
-#endif // __PGAS_H__
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H
deleted file mode 100644
index f8dac3e0f..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H
+++ /dev/null
@@ -1,553 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_bitmanip.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __PORE_BITMANIP_H
-#define __PORE_BITMANIP_H
-
-/// \file pore_bitmanip.H
-/// \brief Standard bit-manipulation macros (C and Assembler) for PORE code
-
-#ifdef __ASSEMBLER__
-#include "pgas.h"
-#endif
-
-#include "fapi_sbe_common.H"
-
-/// \defgroup be64_bits Bit manipulation for 64-bit Big-Endian values
-///
-/// \note These macros only work in the assembler context because we build our
-/// assemblers to do 64-bit arithmetic, which is required for PORE assembly.
-///
-/// @{
-
-/// Create a multi-bit mask of \a n bits starting at bit \a b
-#define BITS(b, n) ((ULL(0xffffffffffffffff) << (64 - (n))) >> (b))
-
-/// Create a single bit mask at bit \a b
-#define BIT(b) BITS((b), 1)
-
-#ifdef __ASSEMBLER__
-
-/// Check b, n for legality
-
-        .macro  ..checkbits, b:req, n=1
-        .if     (((\b) < 0) || ((\b) > 63))
-        .error  "Illegal bit number, must be 0,...,63"
-        .endif
-        .if     (((\n) < 1) || ((\n) > 64))
-        .error  "Illegal number of bits, must be 1,...,64"
-        .endif
-        .if     (((\b) + (\n)) > 64)
-        .error  "Illegal (b + n), must be <= 64"
-        .endif
-        .endm
-
-
-/// Set a single bit in a data register
-///
-/// \param[in,out] data A Data register (D0/D1), modified by setting bit \a b
-/// to 1.
-/// 
-/// \param[in] b The bit position (64-bit, big-endian) to set
-
-        .macro  setbit, data:req, b:req
-        ..checkbits (\b)
-        ori     (\data), (\data), BIT(\b)
-        .endm
-
-
-/// Set multiple contiguous bits in a data register
-///
-/// \param[in,out] data A Data register (D0/D1), modified by setting \a n bits
-/// starting at bit \a b to 1.
-/// 
-/// \param[in] b The bit position (64-bit, big-endian) to begin
-///
-/// \param[in] n The number of contiguous bits to set
-
-        .macro  setbits, data:req, b:req, n:req
-        ..checkbits (\b), (\n)
-        ori     (\data), (\data), BITS((\b), (\n))
-        .endm
-
-
-/// Read-modify-write a SCOM register by setting a bit
-///
-/// \param[in,out] data A Data register (D0/D1), first loaded with the value
-/// of the SCOM register, then modified by setting bit \a b to 1. The final
-/// value of \a data is then stored back to the SCOM register.
-///
-/// \param[in] address A 32-bit SCOM address
-///
-/// \param[in] prv A pervasive base register (P0/P1) which contains the
-/// chiplet ID + multicast bit to use with \a address
-///
-/// \param[in] b The bit position (64-bit, big-endian) to set
-
-        .macro  setbitscom data:req, address:req, prv:req, b:req
-        ..checkbits (\b)
-        .if     ((\data) == D0)
-        bsi     D0, (\address), (\prv), BIT(\b)
-        .else
-        ld      (\data), (\address), (\prv)
-        setbit  (\data), (\b)
-        std     (\data), (\address), (\prv)
-        .endif
-        .endm
-
-
-/// Read-modify-write a SCOM register by setting a range of contiguous bits
-///
-/// \param[in,out] data A Data register (D0/D1), first loaded with the value
-/// of the SCOM register, then modified by setting \a n bits starting at bit
-/// \a b to 1. The final value of \a data is then stored back to the SCOM
-/// register.
-///
-/// \param[in] address A 32-bit SCOM address
-///
-/// \param[in] prv A pervasive base register (P0/P1) which contains the
-/// chiplet ID + multicast bit to use with \a address
-///
-/// \param[in] b The bit position (64-bit, big-endian) to set
-///
-/// \param[in] n The number of contiguous bits to set
-
-        .macro  setbitsscom data:req, address:req, prv:req, b:req, n:req
-        ..checkbits (\b), (\n)
-        .if     ((\data) == D0)
-        bsi     D0, (\address), (\prv), BITS((\b),(\n))
-        .else
-        ld      (\data), (\address), (\prv)
-        setbits (\data), (\b), (\n)
-        std     (\data), (\address), (\prv)
-        .endif
-        .endm
-
-/// Set any number of individual bits in a data register
-///
-/// \param[in] data The Data register (D0/D1) to modify
-///
-/// \param[in] ...bits 1 or more bit positions (64-bit, big-endian) to set
-///
-/// For example:
-///
-/// - setbitmult D0, 1, 3, 13
-///
-/// sets bits 1, 3 and 13 of D0.
-
-        .macro	setbitmult, data:req, bits:vararg
-	..setbitmult 0, (\data), \bits
-	.endm
-
-	// The best I can come up with to implement this macro currently is to
-	// use a special symbol to accumulate the bit masks. I don't know of a
-	// way to do this recursively.
-
-	.macro	..accumulate_bitmask, symbol:req, bits:vararg
-	.ifb	\bits
-	.error	"At least 1 bit position must be specified"
-	.endif
-	.set	\symbol, 0
-	.irp	b, \bits
-	.if	(((\b) < 0) || ((\b) > 63))
-	.error	"Illegal bit position, must be 0 <= b < 63"
-	.endif
-	.set	\symbol, (BIT(\b) | \symbol)
-	.endr
-	.endm
-
-        .macro	..setbitmult, invert:req, data:req, bits:vararg
-	..accumulate_bitmask __SETBITMULT__, \bits
-	.if	(\invert)
-	andi	(\data), (\data), ~__SETBITMULT__
-	.else
-	ori	(\data), (\data), __SETBITMULT__
-	.endif
-	.endm
-
-	
-/// Read-modify-write a SCOM register by setting any number of individual bits
-///
-/// \param[in,out] data A Data register (D0/D1), first loaded with the value
-/// of the SCOM register, then modified by setting any number (> 0) of
-/// individual bits.
-///
-/// \param[in] address A 32-bit SCOM address
-///
-/// \param[in] prv A pervasive base register (P0/P1) which contains the
-/// chiplet ID + multicast bit to use with \a address
-///
-/// \param[in] ...bits 1 or more bit positions (64-bit, big-endian) to set
-///
-/// For example:
-///
-/// - setbitmultscom D0, OCC_CONTROL_0x0006B000, P0, 1, 3, 13
-///
-/// sets bits 1, 3 and 13 of OCC_CONTROL.
-
-        .macro	setbitmultscom, data:req, address:req, prv:req, bits:vararg
-	..setbitmultscom 0, (\data), (\address), (\prv), \bits
-	.endm
-
-	.macro	..setbitmultscom, \
-		invert:req, data:req, address:req, prv:req, bits:vararg
-	..accumulate_bitmask __SETBITMULTSCOM__, \bits
-	.if	((\data) == D0)
-	
-	.if	(\invert)
-	bci	D0, (\address), (\prv), __SETBITMULTSCOM__
-	.else
-	bsi	D0, (\address), (\prv), __SETBITMULTSCOM__
-	.endif
-
-	.else
-
-	.if	(\invert)
-	ldandi	(\data), (\address), (\prv), ~__SETBITMULTSCOM__
-	.else
-	ld	(\data), (\address), (\prv)
-	ori	(\data), (\data), __SETBITMULTSCOM__
-	.endif
-	std	(\data), (\address), (\prv)
-
-	.endif	
-	.endm
-	
-
-/// Clear a single bit in a data register
-///
-/// This macro is the bit-clearing analogue of the \c setbit macro
-
-        .macro  clrbit, data:req, b:req
-        ..checkbits (\b)
-        andi    (\data), (\data), ~BIT(\b)
-        .endm
-
-
-/// Clear multiple contiguous bits in a data register
-///
-/// This macro is the bit-clearing analogue of the \c setbits macro
-
-
-        .macro  clrbits, data:req, b:req, n:req
-        ..checkbits (\b), (\n)
-        andi    (\data), (\data), ~BITS((\b), (\n))
-        .endm
-
-
-/// Read-modify-write a SCOM register by clearing a bit
-///
-/// This macro is the bit-clearing analogue of the \c setbitscom macro
-
-        .macro  clrbitscom data:req, address:req, prv:req, b:req
-        ..checkbits (\b)
-        .if     ((\data) == D0)
-        bci     D0, (\address), (\prv), BIT(\b)
-        .else
-        ld      (\data), (\address), (\prv)
-        clrbit  (\data), (\b)
-        std     (\data), (\address), (\prv)
-        .endif
-        .endm
-
-
-/// Read-modify-write a SCOM register by clearing a range of contiguous bits
-///
-/// This macro is the bit-clearing analogue of the \c setbitsscom macro
-
-        .macro  clrbitsscom, data:req, address:req, prv:req, b:req, n:req
-        ..checkbits (\b), (\n)
-        .if     ((\data) == D0)
-        bci     D0, (\address), (\prv), BITS((\b), (\n))
-        .else
-        ld      (\data), (\address), (\prv)
-        clrbits (\data), (\b), (\n)
-        std     (\data), (\address), (\prv)
-        .endif
-        .endm
-
-
-/// Clear any number of individual bits in a data register
-///
-/// This macro is the bit-clearing analogue of the \c setbitmult macro
-
-	.macro	clrbitmult, data:req, bits:vararg
-	..setbitmult 1, (\data), \bits
-	.endm
-
-
-/// Read-modify-write a SCOM register by clearing any number of individual bits
-///
-/// This macro is the bit-clearing analogue of the \c setbitmultscom macro
-
-        .macro	clrbitmultscom, data:req, address:req, prv:req, bits:vararg
-	..setbitmultscom 1, (\data), (\address), (\prv), \bits
-	.endm
-
-
-/// Extract and right-justify an unsigned bit field
-///
-/// \param[out] dest The destination Data register (D0/D1) to receive the
-/// right-justified unsigned bit field.  
-///
-/// \param[in] src The source Data register (D0/D1) that contains the unsigned
-/// bit field to extract.
-///
-/// \param[in] b The bit positon (64-bit, big-endian) where the bit field
-/// begins. 
-///
-/// \param[in] n The number of contiguous bits beginning at bit \a b to
-/// extract. 
-///
-/// The execution of this macro computes:
-///
-/// - dest[64-n:63] <- src[b:b+n-1]
-/// - dest[0:64-n] <- 0
-///
-/// Note that the \a dest and \a src registers may be the same Data register.
-
-        .macro  extractbits, dest:req, src:req, b:req, n:req
-        ..checkbits (\b), (\n)
-        extrdi  (\dest), (\src), (\n), (\b)
-        .endm
-
-
-/// Destructively insert a right-justified immediate value into a bit field
-///
-/// \param[out] dest The destination Data register (D0/D1) to be modified.
-///
-/// \param[in] b The bit positon (64-bit, big-endian) where the bit field
-/// begins. 
-///
-/// \param[in] n The number of contiguous bits beginning at bit \a b to
-/// modify
-///
-/// The execution of this macro computes:
-///
-/// - dest <- (dest & ~BITS(b, n)) | ((imm & BITS(64 - n, n)) << (64 - n - b))
-
-        .macro  insertbits, dest:req, b:req, n:req, imm:req
-        ..checkbits (\b), (\n)
-        andi    (\dest), (\dest), ~BITS((\b), (\n))
-        ori     (\dest), (\dest), \
-                (((\imm) & BITS(64 - (\n), (\n))) << ((64 - (\n) - (\b))))
-        .endm
-        
-
-/// Destructively insert a right-justified immediate value into a bit field
-/// read out from a scom address
-///
-/// \param[out] dest The destination Data register (D0/D1) to be modified.
-///
-/// \param[in] b The bit positon (64-bit, big-endian) where the bit field
-/// begins. 
-///
-/// \param[in] n The number of contiguous bits beginning at bit \a b to
-/// modify
-///
-/// \param[in] n The scom address to read
-///
-/// \param[in] n The pervasive base register contain the correct base for
-/// the address
-///
-/// The execution of this macro computes:
-///
-/// - dest <- (dest & ~BITS(b, n)) | ((imm & BITS(64 - n, n)) << (64 - n - b))
-
-          .macro  insertbitsscom, dest:req, address:req, prv:req, b:req, n:req, imm:req
-        ..checkbits (\b), (\n)
-        ldandi  (\dest), (\address), (\prv), ~BITS((\b), (\n))
-        ori     (\dest), (\dest), \
-                (((\imm) & BITS(64 - (\n), (\n))) << ((64 - (\n) - (\b))))
-        .endm
-        
-
-/// Poll for a bit to be set in a SCOM register with timeout
-///
-/// \param[in] dest A Data register (D0/D1) to use for the polling
-///
-/// \param[in] address A 32-bit SCOM address
-///
-/// \param[in] prv A Pervasive Chiplet Id register (P0/P1) containing the
-/// chiplet ID and multicast bit to use with the \a address
-///
-/// \param[in] b The bit number of the bit to poll
-///
-/// \param[in] count The number (count > 0) of times to poll for the bit.  If
-/// the bit is not set the \a count-th time the SCOM is read then the error
-/// action occurs (see below). The maximum legal value is 0x1000000.
-///
-/// \param[in] delay The number of PORE clock cycles (delay >= 0) to wait
-/// between polls of the SCOM register.  Specify a delay of 0 to avoid waiting
-/// between polls. There is no waiting before the first poll, therefore the
-/// WAIT is only executed \a count - 1 times in the worst case. The maximum
-/// legal value is 0xffffff. The PORE engines run at nest / 4 normally, but at
-/// the reference frequency during the early IPL.
-///
-/// \param[in] error A branch target (symbol) in the event of error (see
-/// below).
-///
-/// This macro polls a SCOM register for a single set bit with a programmable
-/// timeout, branching to an error handler in the event of a timeout.  This
-/// macro always uses the \c CTR register for the poll count.  Therefore if
-/// the CTR is currently in use the caller will need to save the current
-/// contents of CTR to another register prior to invoking this macro.
-///
-/// In the event of a polling timeout the code will branch to the \a
-/// error target.  Prior to the branch, the \a dest register will be loaded
-/// with the PC to help diagnose the error.
-
-        .macro  pollbitset, dest:req, address:req, prv:req, b:req \
-                count:req, delay:req, error:req
-        ..pollbit branz, (\dest), (\address), (\prv), (\b), \
-                (\count), (\delay), (\error)
-        .endm
-
-        
-/// Poll for a bit to be clear in a SCOM register with timeout
-///
-/// This macro is analogous to the pollbitset macro
-
-        .macro  pollbitclr, dest:req, address:req, prv:req, b:req \
-                count:req, delay:req, error:req
-        ..pollbit braz, (\dest), (\address), (\prv), (\b), \
-                (\count), (\delay), (\error)
-        .endm
-
-        
-// Implements pollbitset and pollbitclr - the only difference is 'branz' vs
-// 'braz'.
-
-        .macro  ..pollbit, instr:req, dest:req, address:req, prv:req, b:req \
-                count:req, delay:req, error:req
-
-        .if     (((\count) <= 0) || ((\count) > 0x1000000))
-        .error  "The poll count must satisfy 0 < count <= 0x1000000"
-        .endif
-        .if     (((\delay) < 0) || ((\delay) >= 0x1000000))
-        .error  "The wait delay must satisfy 0 <= delay < 0x1000000"
-        .endif
-
-        ls      CTR, ((\count) - 1)
-        bra     7665249f
-7665248:
-	.if	((\delay) != 0)
-        waits   (\delay)
-	.endif
-7665249:
-        ldandi  (\dest), (\address), (\prv), BIT(\b)
-        \instr  (\dest), 7665250f
-        loop    7665248b
-        mr      (\dest), PC
-        braa    (\error)        
-7665250:
-        
-        .endm
-
-
-/// Test and branch if a bit is set in a data register
-///
-/// \param[out] scratch This Data register (D0/D1) is destroyed to perform the
-/// comparison. This may be the same as the \a data register if the \a data is
-/// no longer needed after the comparison.
-///
-/// \param[in] data This Data register (D0/D1) contains the data to be tested.
-///
-/// \param[in] b The bit number (64-bit, big-endian) to test
-///
-/// \param[in] target The branch target in the event that bit \a b is set in
-/// \a data.
-
-	.macro	ifbitset, scratch:req, data:req, b:req, target:req
-	..checkbits (\b)
-	andi	(\scratch), (\data), BIT(\b)
-	branz	(\scratch), (\target)
-	.endm
-
-
-/// Test and branch is a bit is clear in a data register
-///
-/// This macro is the bit-clear-test analogue of the ifbitset macro 
-
-	.macro	ifbitclr, scratch:req, data:req, b:req, target:req
-	..checkbits (\b)
-	andi	(\scratch), (\data), BIT(\b)
-	braz	(\scratch), (\target)
-	.endm
-             
-
-/// Read a SCOM register and branch if a bit is set
-///
-/// \param[out] scratch This Data register (D0/D1) is destroyed to perform the
-/// comparison. This may be the same as the \a data register if the \a data is
-/// no longer needed after the comparison.
-///
-/// \param[in] data This Data register (D0/D1) is first loaded from the SCOM
-/// \a address, then tested for the bit being set. If \a scratch and \a data
-/// are different register then this register will hold the original SCOM data
-/// after the execution of the macro.
-///
-/// \param[in] address A 32-bit SCOM address
-///
-/// \param[in] prv A Pervasive Chiplet Id register (P0/P1) containing the
-/// chiplet ID and multicast bit to use with the \a address
-///
-/// \param[in] b The bit number (64-bit, big-endian) to test
-///
-/// \param[in] target The branch target in the event that bit \a b is set in
-/// \a data.
-			
-	.macro	ifbitsetscom, scratch:req, data:req, address:req, prv:req, \
-		b:req, target:req
-	..checkbits (\b)
-	.if	((\scratch) == (\data))
-	ldandi	(\scratch), (\address), (\prv), BIT(\b)
-	.else
-	ld	(\data), (\address), (\prv)
-	andi	(\scratch), (\data), BIT(\b)
-	.endif	
-	branz	(\scratch), (\target)
-	.endm
-
-
-/// Read a SCOM register and branch if a bit is clear
-///
-/// This is the bit-clear-test analogue of the ifbitsetscom macro
-
-	.macro	ifbitclrscom, scratch:req, data:req, address:req, prv:req, \
-		b:req, target:req
-	..checkbits (\b)
-	.if	((\scratch) == (\data))
-	ldandi	(\scratch), (\address), (\prv), BIT(\b)
-	.else
-	ld	(\data), (\address), (\prv)
-	andi	(\scratch), (\data), BIT(\b)
-	.endif	
-	braz	(\scratch), (\target)
-	.endm
-	
-	
-/// @}
-
-#endif  // __ASSEMBLER__
-
-#endif  // __PORE_BITMANIP_H
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h
deleted file mode 100644
index 1af9199cf..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h
+++ /dev/null
@@ -1,883 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __PORE_INLINE_H__
-#define __PORE_INLINE_H__
-
-// $Id: pore_inline.h,v 1.20 2013/12/11 00:11:13 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/pore_inline.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//-----------------------------------------------------------------------------
-
-// ** WARNING : This file is maintained as part of the OCC firmware.  Do **
-// ** not edit this file in the PMX area or the hardware procedure area  **
-// ** as any changes will be lost.                                       **
-
-/// \file pore_inline.h
-/// \brief Inline assembler for PORE code
-///
-/// Note that this file defines several short macro symbols for register names
-/// and other mnemonics used by inline assembly.  For this reason it would
-/// probably be best to only include this header when it was absolutely
-/// necessary, i.e., only in C files that explicitly use inline assembly and
-/// disassembly.
-
-#ifndef PPC_HYP
-#include <ctype.h>
-#include <stddef.h>
-#include <stdint.h>
-#endif // PPC_HYP
-#include "pgas.h"
-
-#if( defined(__cplusplus) && !defined(PLIC_MODULE) ) 
-extern "C" {
-#endif
-#if 0
-} /* So __cplusplus doesn't mess w/auto-indent */
-#endif
-
-
-#ifndef __ASSEMBLER__
-
-// PHYP tools do not support 'static' functions and variables as it interferes
-// with their concurrent patch methodology.  So when compiling for PHYP the
-// PORE instruction "macros" are simply declared "inline".  This also extends
-// into the implementation C files - so under PHYP all previosuly local static
-// functions will now be global functions. We retain 'static' to reduce code
-// size and improve abstraction for OCC applications.
-
-#ifdef PPC_HYP
-#define PORE_STATIC
-#include <p8_pore_api_custom.h>
-#else
-#define PORE_STATIC static
-#endif
-
-/// Error code strings from the PORE inline assembler/disassembler
-///
-/// The PoreInlineContext object stores error codes that occur during
-/// assembly as small integers.  The '0' code indicates success. This is a
-/// table of strings that describe the codes.  It will be instantiated in
-/// pore_inline.c 
-
-extern const char *pore_inline_error_strings[];
-
-#ifdef __PORE_INLINE_ASSEMBLER_C__
-const char *pore_inline_error_strings[] = {
-    "No error",
-    "The inline assembler memory is full, or disassembly has reached the end of the memory area",
-    "The instruction requires an ImD24 operand",
-    "The LC is not aligned or the instruction requires an aligned operand",
-    "The branch target is unreachable (too distant)",
-    "A register operand is illegal for the given instruction",
-    "The instruction form requires a signed 16-bit immediate",
-    "Valid rotate lengths are 1, 4, 8, 16 and 32",
-    "The instruction requires a 20-bit signed immediate",
-    "The instruction requires a 24-bit unsigned immediate",
-    "A parameter to pore_inline_context_create() is invalid",
-    "The instruction form requires an unsigned 22-bit immediate",
-    "This error is due to a bug in the PORE inline assembler (Please report)",
-    "The 'source' label for pore_inline_branch_fixup() is illegal",
-    "The 'source' instruction for pore_inline_branch_fixup() is not a branch",
-    "The disassembler does not recognize the instruction as a PORE opcode",
-    "Instruction parity error during disassembly",
-    "The string form of the disassembly is too long to represent (Please report)`",
-    "Use HALT instead of WAIT 0 if the intention is to halt.",
-    "A putative SCOM address is illegal (has non-0 bits where 0s are expected)."
-};
-#endif	/* __PORE_INLINE_ASSEMBLER_C__ */
-
-#endif	/* __ASSEMBLER__ */
-
-#define PORE_INLINE_SUCCESS              0
-#define PORE_INLINE_NO_MEMORY            1
-#define PORE_INLINE_IMD24_ERROR          2
-#define PORE_INLINE_ALIGNMENT_ERROR      3
-#define PORE_INLINE_UNREACHABLE_TARGET   4
-#define PORE_INLINE_ILLEGAL_REGISTER     5
-#define PORE_INLINE_INT16_REQUIRED       6
-#define PORE_INLINE_ILLEGAL_ROTATE       7
-#define PORE_INLINE_INT20_REQUIRED       8
-#define PORE_INLINE_UINT24_REQUIRED      9
-#define PORE_INLINE_INVALID_PARAMETER    10
-#define PORE_INLINE_UINT22_REQUIRED      11
-#define PORE_INLINE_BUG                  12
-#define PORE_INLINE_ILLEGAL_SOURCE_LC    13
-#define PORE_INLINE_NOT_A_BRANCH         14
-#define PORE_INLINE_UNKNOWN_OPCODE       15
-#define PORE_INLINE_PARITY_ERROR         16
-#define PORE_INLINE_DISASSEMBLY_OVERFLOW 17
-#define PORE_INLINE_USE_HALT             18
-#define PORE_INLINE_ILLEGAL_SCOM_ADDRESS 19
-
-
-/// Register name strings for the PORE inline assembler/disassembler
-
-extern const char *pore_inline_register_strings[16];
-
-// C++ requires that these arrays of strings be declared 'const' to avoid
-// warnings.  But then you get warnings when the strings get stored into
-// non-const variables.  The solution is to rename these arrays inside the
-// disassembler.  If anyone has a better solution please let me know - Bishop
-
-#ifdef __PORE_INLINE_ASSEMBLER_C__
-const char* pore_inline_register_strings[16] = {
-    "P0", "P1", "A0", "A1", "CTR", "D0", "D1", "EMR",
-    "?", "ETR", "SPRG0", "?", "?", "?", "PC", "IFR"
-};
-#endif /* __PORE_INLINE_ASSEMBLER_C__ */
-
-
-// Shorthand forms of constants defined in pgas.h, defined for consistency
-// using the assembler-supported names.  These constants are defined as an
-// enum to avoid name conflicts with some firmware symbols when the PORE
-// inline facility is used to create Host Boot procedures.
-
-enum {
-
-    // Shorthand register mnemonics, defined as an enum to avoid name clashes.
-
-    P0    = PORE_REGISTER_PRV_BASE_ADDR0,
-    P1    = PORE_REGISTER_PRV_BASE_ADDR1,
-    A0    = PORE_REGISTER_OCI_BASE_ADDR0,
-    A1    = PORE_REGISTER_OCI_BASE_ADDR1,
-    CTR   = PORE_REGISTER_SCRATCH0,
-    D0    = PORE_REGISTER_SCRATCH1,
-    D1    = PORE_REGISTER_SCRATCH2,
-    EMR   = PORE_REGISTER_ERROR_MASK,
-    ETR   = PORE_REGISTER_EXE_TRIGGER,
-    SPRG0 = PORE_REGISTER_DATA0,
-    PC    = PORE_REGISTER_PC,
-    IFR   = PORE_REGISTER_IBUF_ID,
-
-    // PgP IBUF_ID values
-
-    PORE_GPE0 = PORE_ID_GPE0,
-    PORE_GPE1 = PORE_ID_GPE1,
-    PORE_SLW  = PORE_ID_SLW,
-    PORE_SBE  = PORE_ID_SBE,
-
-    // Condition Codes
-
-    CC_UGT = PORE_CC_UGT,
-    CC_ULT = PORE_CC_ULT,
-    CC_SGT = PORE_CC_SGT,
-    CC_SLT = PORE_CC_SLT,
-    CC_C   = PORE_CC_C,
-    CC_V   = PORE_CC_V,
-    CC_N   = PORE_CC_N,
-    CC_Z   = PORE_CC_Z,
-};
-
-// Pseudo-opcodes for LD/LDANDI/STD
-
-#define PORE_INLINE_PSEUDO_LD     0
-#define PORE_INLINE_PSEUDO_LDANDI 1
-#define PORE_INLINE_PSEUDO_STD    2
-
-
-// Private version of _BIG_ENDIAN
-
-#ifndef _BIG_ENDIAN
-#define PORE_BIG_ENDIAN 0
-#else
-#define PORE_BIG_ENDIAN _BIG_ENDIAN
-#endif
-
-
-/// Maximum size of disassembly strings
-///
-/// This is currently sufficient for PORE_INLINE_LISTING_MODE. We don't want
-/// to make this too long since the PoreInlineDisassembly object may be on the
-/// stack in embedded applications.
-#define PORE_INLINE_DISASSEMBLER_STRING_SIZE 128
-
-
-/// Generate PORE instruction parity
-///
-/// This flag is an option to pore_inline_context_create(). If set, PORE
-/// inline assembly sets the instruction parity bit for each assembled
-/// instruction; otherwise the instruction parity bit is always 0.
-#define PORE_INLINE_GENERATE_PARITY 0x01
-
-/// Check PORE instruction parity
-///
-/// This flag is an option to pore_inline_context_create(). If set, PORE
-/// inline disassembly checks the instruction parity bit for each disassembled
-/// instruction, failing with PORE_INLINE_PARITY_ERROR if the parify is not
-/// correct. Otherwise the instruction parity bit is ignored during
-/// disassembly.
-#define PORE_INLINE_CHECK_PARITY 0x02
-
-/// Disassemble in listing mode
-///
-/// This flag is an option to pore_inline_context_create(). If set, then
-/// generate disassembly strings in the form of a listing that contains
-/// location counters and encoded instructions as well as their diassembly.
-/// By default the disassembly strings do not contain this information and can
-/// be fed back in as source code to a PORE assembler.
-#define PORE_INLINE_LISTING_MODE 0x04
-
-/// Disassemble in data mode
-///
-/// This flag is an option to pore_inline_context_create().  If set, then
-/// generate disassembly assuming that the context contains data rather than
-/// text. Normally data is disassembled as .long directives, however if the
-/// context is unaligned or of an odd length then .byte directives may be used
-/// as well.  This option can be used in conjunction with
-/// PORE_INLINE_LISTING_MODE and PORE_INLINE_8_BYTE_DATA.
-///
-/// Note: An intelligent application can switch between the default text
-/// disassembly and data disassembly by manipulating the \a options field of
-/// the PoreInlineContext between calls of pore_inline_disassemble().
-#define PORE_INLINE_DISASSEMBLE_DATA 0x08
-
-/// Disassemble data in 8-byte format
-///
-/// This flag is an option to pore_inline_context_create().  If set, then if
-/// PORE_INLINE_DISASSEMBLE_DATA is also set then generate data disassembly as
-/// 8-byte values rather then the default 4-byte values. Normally data is
-/// disassembled as .quad directives under this option, however if the context
-/// is unaligned or of an odd length then .long and .byte directives may be
-/// used as well.  This option can be used in conjunction with
-/// PORE_INLINE_LISTING_MODE.
-///
-/// Note: An intelligent application can switch between the default text
-/// disassembly and data disassembly by manipulating the \a options field of
-/// the PoreInlineContext between calls of pore_inline_disassemble().
-#define PORE_INLINE_8_BYTE_DATA 0x10
-
-/// Disassemble unrecognized opcodes as 4-byte data
-///
-/// This flag is an option to pore_inline_context_create().  If set, then
-/// any putative instruction with an unrecognized opcode will be silently
-/// diassembled as 4-byte data.
-///
-/// This option was added to allow error-free disassembly of
-/// non-parity-protected PORE text sections that contain 0x00000000 alignment
-/// padding, and is not guaranteed to produce correct or consistent results in
-/// any other case.
-#define PORE_INLINE_DISASSEMBLE_UNKNOWN 0x20
-
-
-#ifndef __ASSEMBLER__
-
-/// The type of location counters for the PORE inline assembler
-
-typedef uint32_t PoreInlineLocation;
-
-/// PORE inline assembler context
-///
-/// See the documentation page \ref pore_inline_assembler and the function
-/// pore_inline_context_create() for futher details.
-
-typedef struct {
-
-    /// The memory area to receive the inline assembly
-    ///
-    /// This field is never modified, allowing the *reset* APIs to function.
-    ///
-    /// Note: C++ does not allow arithmetic on void* objects, so we use the
-    /// Linux convention of storing memory addresses as type 'unsigned long'. 
-    unsigned long memory;
-
-    /// The original size of the memory area to receive the inline assembly
-    ///
-    /// This field is never modified, allowing the *reset* APIs to function.
-    size_t size;
-
-    /// The original Location Counter (associated with \a memory)
-    ///
-    /// This field is never modified, allowing the *reset* APIs to function.
-    PoreInlineLocation original_lc;
-
-    /// The memory address associated with the current LC
-    ///
-    /// Note: C++ does not allow arithmetic on void* objects, so we use the
-    /// Linux convention of storing memory addresses as type 'unsigned long'. 
-    unsigned long lc_address;
-
-    /// The remaining size of the memory area to receive the inline assembly
-    size_t remaining;
-
-    /// The bytewise Location Counter of the assembled code
-    PoreInlineLocation lc;
-
-    /// Inline assembly options
-    ///
-    /// This field is never modified, allowing the *reset* APIs to function.
-    int options;
-
-    /// The last error code generated by the inline assembler
-    int error;
-
-} PoreInlineContext;
-
-
-/// PORE inline disassembler result
-///
-/// This object holds the disassembly produced by pore_inline_disassemble().
-/// See documentation for that function for complete details.
-
-typedef struct {
-
-    /// The context as it existed when the instruction was assembled
-    ///
-    /// Disassembling an instruction modifies the context provided to
-    /// pore_inline_disassemble() to point to the next instruction.  This
-    /// structure stores a copy of the context at the initial call of
-    /// pore_inline_disassemble(), that is, the context in effect when the
-    /// dissassembled instruction was assembled.
-    PoreInlineContext ctx;
-
-    /// The first 32 bits of every instruction
-    uint32_t instruction;
-
-    /// The opcode; bits 0..6 of the instruction
-    int opcode;
-
-    /// A flag - If set the opcode is for a 12-byte instruction
-    int long_instruction;
-
-    /// The parity bit; bit 7 of the instruction
-    int parity;
-
-    /// The register specifier at bits 8..11 of the instruction
-    ///
-    /// This register is sometimes called the source, sometimes the target,
-    /// depending on the opcode.
-    int r0;
-
-    /// The register specifier at bits 12..15 of the instruction
-    ///
-    /// This register is always called the 'source' but is named generically
-    /// here since sometimes the specifier at bits 8..11 is also called a
-    /// 'source'.
-    int r1;
-
-    /// 'ImD16' is the signed 16-bit immediate for short immediate adds and
-    /// subtracts.  For the rotate instruction this field also contains the
-    /// rotate count which is either 1, 4, 8, 16 or 32.
-    int16_t imd16;
-
-    /// 'ImD20' is the 20-bit signed immediate for the LOAD20 instruction
-    int32_t imd20;
-
-    /// 'ImD24' is the 24-bit unsigned immediate for the WAIT instruction
-    uint32_t imd24;
-
-    /// 'ImD64' is the 64-bit immediate for data immediates and BRAI.  This
-    /// field is only set for 3-word instructions.
-    uint64_t imd64;
-
-    /// 'ImPCO20' is a signed, 20-bit word offset for branch instructions
-    int32_t impco20;
-
-    /// 'ImPCO24' is a signed, 24-bit word offset for branch instructions
-    int32_t impco24;
-
-    /// For imA24 opcodes, this indicates memory/pib (1/0) addressing..
-    int memory_space;
-
-    /// This is the base register specifier - either a memory (OCI) base
-    /// register or a pervasive base register - for Read/Write operations.
-    /// Note that this is a PORE register index, not simply 0/1.
-    int base_register;
-
-    /// This is the 22-bit signed offset for memory (OCI) addressing.  This
-    /// unsigned offset is added to a memory base register (A0/A1) to form the
-    /// final 32-bit address.
-    uint32_t memory_offset;
-
-    /// This field contains the port number and local address portions of the
-    /// PIB/PCB address for load/store operations that target the PIB/PCB.
-    /// Note that bits 0..11 will always be 0 in this address.  Bits 1..7 (the
-    /// multicast bit and chiplet id) are sourced from the associated
-    /// pervasive base register when the instruction executes.
-    uint32_t pib_offset;
-
-    /// The update bit of the SCAND instruction
-    int update;
-
-    /// The capture bit of the SCAND instruction
-    int capture;
-
-    /// The scan length from a SCAND instruction
-    int scan_length;
-
-    /// The scan select from a SCAND instruction
-    uint32_t scan_select;
-
-    /// The address offset from a SCAND instruction
-    uint32_t scan_offset;
-
-    /// The string form of the disassembly.
-    ///
-    /// The disassembly string is \e not terminated by a newline.  In listing
-    /// mode the disassembly string \e will contain embedded newlines for long
-    /// instructions.
-    char s[PORE_INLINE_DISASSEMBLER_STRING_SIZE];
-
-    /// The data (for data disassembly)
-    ///
-    /// This is either 1, 4 or 8 bytes in host byte order.
-    uint64_t data;
-
-    /// The size of the disassembled \a data field (for data disassembly)
-    size_t data_size;
-
-    /// Was this location disassembled as an instruction (0) or as data (1)
-    int is_data;
-
-} PoreInlineDisassembly;
-
-
-// These are internal APIs - they are not needed by application code.
-
-void
-pore_inline_be32(unsigned long p, uint32_t x);
-
-void
-pore_inline_be64(unsigned long p, uint64_t x);
-
-uint32_t
-pore_inline_host32(unsigned long p);
-
-uint64_t
-pore_inline_host64(unsigned long p);
-
-int
-pore_inline_parity(uint32_t instruction, uint64_t imd64);
-
-void
-pore_inline_context_bump(PoreInlineContext *ctx, size_t bytes);
-
-int
-pore_inline_instruction1(PoreInlineContext *ctx, int opcode, uint32_t operand);
-
-int
-pore_inline_instruction3(PoreInlineContext *ctx, int opcode, uint32_t operand,
-			 uint64_t imm);
-
-int
-pore_inline_bra(PoreInlineContext *ctx, 
-                int opcode, PoreInlineLocation target);
-
-int
-pore_inline_brac(PoreInlineContext *ctx,
-		 int opcode, int reg, PoreInlineLocation target);
-
-int
-pore_inline_cmpibra(PoreInlineContext *ctx, 
-                    int opcode, int reg,
-                    PoreInlineLocation target, uint64_t imm);
-
-int
-pore_inline_brad(PoreInlineContext *ctx, int opcode, int reg);
-
-int
-pore_inline_ilogic(PoreInlineContext *ctx, 
-                   int opcode, int dest, int src, uint64_t imm);
-int
-pore_inline_alurr(PoreInlineContext *ctx, 
-                  int opcode, int dest, int src1, int src2);
-
-int
-pore_inline_adds(PoreInlineContext *ctx, 
-                 int opcode, int dest, int src, int imm);
-
-int
-pore_inline_load_store(PoreInlineContext *ctx, 
-                       int opcode, int src_dest, int32_t offset, int base,
-                       uint64_t imm);
-
-
-// These are utility APIs that may be required by special-purpose code that
-// uses the pore_inline library.
-
-void
-pore_inline_decode_instruction(PoreInlineDisassembly* dis, 
-                               uint32_t instruction);
-
-void
-pore_inline_decode_imd64(PoreInlineDisassembly* dis, uint64_t imd64);
-
-
-// These are the inline PORE instructions, extended mnemonics and pseudo-ops
-// to be used by application code.
-
-/// Set a location counter variable from a context
-///
-/// This is a macro that sets the \a var (of type PoreInlineLocation) to the
-/// current location counter of the \a ctx.  The macro produces an expression
-/// that evaluates to 0 so that it can be used in the logical-OR expressions
-/// used to define inline assembly sequences.
-
-#define PORE_LOCATION(ctx, var) (((var) = (ctx)->lc), 0)
-
-int
-pore_inline_context_create(PoreInlineContext *context,
-			   void *memory, 
-			   size_t size, 
-			   PoreInlineLocation lc, 
-			   int options);
-
-void
-pore_inline_context_reset(PoreInlineContext *context);
-
-void
-pore_inline_context_reset_excursion(PoreInlineContext *context);
-
-void
-pore_inline_context_copy(PoreInlineContext *dest, PoreInlineContext *src);
-
-
-int
-pore_inline_branch_fixup(PoreInlineContext *ctx, 
-			 PoreInlineLocation source,
-			 PoreInlineLocation target);
-
-
-int
-pore_inline_disassemble(PoreInlineContext *ctx, PoreInlineDisassembly *dis);
-
-
-// Native PORE instruction assembly, using PGAS opcode names and operand
-// ordering rules. 
-
-// NOP, TRAP, RET
-
-PORE_STATIC inline int
-pore_NOP(PoreInlineContext *ctx) 
-{
-    return pore_inline_instruction1(ctx, PGAS_OPCODE_NOP, 0);
-}
-
-
-PORE_STATIC inline int
-pore_TRAP(PoreInlineContext *ctx) 
-{
-    return pore_inline_instruction1(ctx, PGAS_OPCODE_TRAP, 0);
-}
-
-
-PORE_STATIC inline int
-pore_RET(PoreInlineContext *ctx) 
-{
-    return pore_inline_instruction1(ctx, PGAS_OPCODE_RET, 0);
-}
-
-
-// WAITS, HALT, HOOKI
-
-int
-pore_WAITS(PoreInlineContext *ctx, uint32_t cycles);
-
-PORE_STATIC inline int
-pore_HALT(PoreInlineContext *ctx)
-{
-    return pore_inline_instruction1(ctx, PGAS_OPCODE_WAITS, 0);
-}    
-
-int
-pore_HOOKI(PoreInlineContext *ctx, uint32_t index, uint64_t imm);
-
-
-// BRA, BSR, LOOP
-
-PORE_STATIC inline int
-pore_BRA(PoreInlineContext *ctx, PoreInlineLocation target)
-{
-    return pore_inline_bra(ctx, PGAS_OPCODE_BRA, target);
-}
-
-PORE_STATIC inline int
-pore_BSR(PoreInlineContext *ctx, PoreInlineLocation target)
-{
-    return pore_inline_bra(ctx, PGAS_OPCODE_BSR, target);
-}
-
-PORE_STATIC inline int
-pore_LOOP(PoreInlineContext *ctx, PoreInlineLocation target)
-{
-    return pore_inline_bra(ctx, PGAS_OPCODE_LOOP, target);
-}
-
-
-// BRAZ, BRANZ
-
-PORE_STATIC inline int
-pore_BRAZ(PoreInlineContext *ctx, int reg, PoreInlineLocation target)
-{
-    return pore_inline_brac(ctx, PGAS_OPCODE_BRAZ, reg, target);
-}
-
-
-PORE_STATIC inline int
-pore_BRANZ(PoreInlineContext *ctx, int reg, PoreInlineLocation target)
-{
-    return pore_inline_brac(ctx, PGAS_OPCODE_BRANZ, reg, target);
-}
-
-
-// CMPIBRAEQ, CMPIBRANE, CMPIBSREQ
-
-PORE_STATIC inline int
-pore_CMPIBRAEQ(PoreInlineContext *ctx, 
-               int reg, PoreInlineLocation target, uint64_t imm)
-{
-    return pore_inline_cmpibra(ctx, PGAS_OPCODE_CMPIBRAEQ, reg, target, imm);
-}
-
-
-PORE_STATIC inline int
-pore_CMPIBRANE(PoreInlineContext *ctx, 
-               int reg, PoreInlineLocation target, uint64_t imm)
-{
-    return pore_inline_cmpibra(ctx, PGAS_OPCODE_CMPIBRANE, reg, target, imm);
-}
-
-
-PORE_STATIC inline int
-pore_CMPIBSREQ(PoreInlineContext *ctx, 
-               int reg, PoreInlineLocation target, uint64_t imm)
-{
-    return pore_inline_cmpibra(ctx, PGAS_OPCODE_CMPIBSREQ, reg, target, imm);
-}
-
-
-// BRAD, BSRD
-
-PORE_STATIC inline int
-pore_BRAD(PoreInlineContext *ctx, int reg) {
-    return pore_inline_brad(ctx, PGAS_OPCODE_BRAD, reg);
-}
-
-PORE_STATIC inline int
-pore_BSRD(PoreInlineContext *ctx, int reg) {
-    return pore_inline_brad(ctx, PGAS_OPCODE_BSRD, reg);
-}
-
-
-// ANDI, ORI, XORI
-
-PORE_STATIC inline int
-pore_ANDI(PoreInlineContext *ctx, int dest, int src, uint64_t imm)
-{
-    return pore_inline_ilogic(ctx, PGAS_OPCODE_ANDI, dest, src, imm);
-}
-
-PORE_STATIC inline int
-pore_ORI(PoreInlineContext *ctx, int dest, int src, uint64_t imm)
-{
-    return pore_inline_ilogic(ctx, PGAS_OPCODE_ORI, dest, src, imm);
-}
-
-PORE_STATIC inline int
-pore_XORI(PoreInlineContext *ctx, int dest, int src, uint64_t imm)
-{
-    return pore_inline_ilogic(ctx, PGAS_OPCODE_XORI, dest, src, imm);
-}
-
-
-// AND, OR, XOR, ADD, SUB
-
-PORE_STATIC inline int
-pore_AND(PoreInlineContext *ctx, int dest, int src1, int src2)
-{
-    return pore_inline_alurr(ctx, PGAS_OPCODE_AND, dest, src1, src2);
-}
-
-PORE_STATIC inline int
-pore_OR(PoreInlineContext *ctx, int dest, int src1, int src2)
-{
-    return pore_inline_alurr(ctx, PGAS_OPCODE_OR, dest, src1, src2);
-}
-
-PORE_STATIC inline int
-pore_XOR(PoreInlineContext *ctx, int dest, int src1, int src2)
-{
-    return pore_inline_alurr(ctx, PGAS_OPCODE_XOR, dest, src1, src2);
-}
-
-PORE_STATIC inline int
-pore_ADD(PoreInlineContext *ctx, int dest, int src1, int src2)
-{
-    return pore_inline_alurr(ctx, PGAS_OPCODE_ADD, dest, src1, src2);
-}
-
-PORE_STATIC inline int
-pore_SUB(PoreInlineContext *ctx, int dest, int src1, int src2)
-{
-    return pore_inline_alurr(ctx, PGAS_OPCODE_SUB, dest, src1, src2);
-}
-
-
-// ADDS, SUBS
-
-PORE_STATIC inline int
-pore_ADDS(PoreInlineContext *ctx, int dest, int src, int imm)
-{
-    return pore_inline_adds(ctx, PGAS_OPCODE_ADDS, dest, src, imm);
-}
-
-PORE_STATIC inline int
-pore_SUBS(PoreInlineContext *ctx, int dest, int src, int imm)
-{
-    return pore_inline_adds(ctx, PGAS_OPCODE_SUBS, dest, src, imm);
-}
-
-
-// NEG, MR, ROLS, LS, LI
-
-int
-pore_NEG(PoreInlineContext *ctx, int dest, int src);
-
-int
-pore_MR(PoreInlineContext *ctx, int dest, int src);
-
-int
-pore_ROLS(PoreInlineContext *ctx, int dest, int src, int imm);
-
-int
-pore_LS(PoreInlineContext *ctx, int dest, int imm);
-
-int
-pore_LI(PoreInlineContext *ctx, int dest, uint64_t imm);
-
-
-// LD, LDANDI, STD, STI, BSI, BCI
-
-PORE_STATIC inline int
-pore_LD(PoreInlineContext *ctx, int dest, int32_t offset, int base) 
-{
-    return 
-	pore_inline_load_store(ctx, 
-			       PORE_INLINE_PSEUDO_LD, dest, offset, base, 0);
-}
-
-PORE_STATIC inline int
-pore_LDANDI(PoreInlineContext *ctx, 
-            int dest, int32_t offset, int base, uint64_t imm)
-{
-    return 
-	pore_inline_load_store(ctx, 
-			       PORE_INLINE_PSEUDO_LDANDI, 
-                               dest, offset, base, imm);
-}
-
-PORE_STATIC inline int
-pore_STD(PoreInlineContext *ctx, int src, int32_t offset, int base) 
-{
-    return 
-	pore_inline_load_store(ctx, 
-			       PORE_INLINE_PSEUDO_STD, src, offset, base, 0);
-}
-
-PORE_STATIC inline int
-pore_STI(PoreInlineContext *ctx, int32_t offset, int base, uint64_t imm)
-{
-    return 
-	pore_inline_load_store(ctx, 
-			       PGAS_OPCODE_STI, 0, offset, base, imm);
-}
-
-
-#ifdef IGNORE_HW274735
-
-// BSI and BCI are redacted as instructions and reimplemented as "macros" due
-// to HW274735, unless specifically overridden. Note that the inline assembler
-// will allow D1 to be used as scratch here, unlike the underlying hardware
-// instruction. 
-
-PORE_STATIC inline int
-pore_BSI(PoreInlineContext *ctx, 
-         int src, int32_t offset, int base, uint64_t imm) 
-{
-    return 
-	pore_inline_load_store(ctx, 
-			       PGAS_OPCODE_BSI, src, offset, base, imm);
-}
-
-PORE_STATIC inline int
-pore_BCI(PoreInlineContext *ctx, 
-         int src, int32_t offset, int base, uint64_t imm) 
-{
-    return 
-	pore_inline_load_store(ctx, 
-			       PGAS_OPCODE_BCI, src, offset, base, imm);
-}
-
-#else
-
-PORE_STATIC inline int
-pore_BSI(PoreInlineContext *ctx, 
-         int src, int32_t offset, int base, uint64_t imm) 
-{
-    return 
-        ((pore_LD(ctx, src, offset, base) ||
-          pore_ORI(ctx, src, src, imm)    ||
-          pore_STD(ctx, src, offset, base)) ? ctx->error : 0);
-}
-
-PORE_STATIC inline int
-pore_BCI(PoreInlineContext *ctx, 
-         int src, int32_t offset, int base, uint64_t imm) 
-{
-    return 
-        ((pore_LDANDI(ctx, src, offset, base, ~imm) ||
-          pore_STD(ctx, src, offset, base)) ? ctx->error : 0);
-}
-
-#endif // IGNORE_HW274735
-
-
-// BRAIA
-
-int
-pore_BRAIA(PoreInlineContext *ctx,
-           uint16_t address_space, uint32_t offset);
-
-
-// SCAND
-
-int
-pore_SCAND(PoreInlineContext *ctx,
-           int update, int capture, uint16_t length, 
-           uint32_t select, uint32_t offset);
-
-#endif	/* __ASSEMBLER__ */
-
-#if 0
-{ /* So __cplusplus doesn't mess w/auto-indent */
-#endif
-#if( defined(__cplusplus) && !defined(PLIC_MODULE) ) 
-}
-#endif
-
-#endif	/* __PORE_INLINE_H__ */
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c
deleted file mode 100644
index 4fadbc64d..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c
+++ /dev/null
@@ -1,1509 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/pore_inline_assembler.c $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: pore_inline_assembler.c,v 1.22 2013/12/11 00:11:14 bcbrock Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/pore_inline_assembler.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//-----------------------------------------------------------------------------
-
-// ** WARNING : This file is maintained as part of the OCC firmware.  Do **
-// ** not edit this file in the PMX area or the hardware procedure area  **
-// ** as any changes will be lost.                                       **
-
-/// \file pore_inline_assembler.c
-/// \brief Inline PGAS assembler for PgP/Stage1 PORE
-///
-/// \page pore_inline_assembler PORE Inline Assembler and Disassembler
-///
-/// Several procedures targeting the PORE engine require inline assembly and
-/// disassembly of PORE code, that is, they require that PORE instructions be
-/// assembled/disassembled directly into/from a host memory buffer. This page
-/// describes these facilities.  The APIs described here are implemented in
-/// the files pore_inline.h, pore_inline_assembler.c and
-/// pore_inline_disassembler.c.  Both the inline assembelr and disassembler
-/// conform to the PGAS assembly format for PORE.
-///
-/// Both inline assembly and disassembly make use of a PoreInlineContext
-/// structure. This structure represents the state of a memory area being
-/// targeted for inline assembly and disassembly.  The context is initialized
-/// with the pore_inline_context_create() API, and a pointer to an instance of
-/// this structure appears as the first argument of all assembler/disassembler
-/// APIs. As assembly/disassembly progresses the PoreInlineContext keeps
-/// track of how much host memory area has been filled by assembled code or
-/// scanned by the disassebler.
-///
-/// Assembler/disassembler APIs are predicates that return 0 for success and a
-/// non-zero error code for failure.  In the event of failure, the error code
-/// (a small integer) is also stored in the \a error field of the context
-/// structure.  String forms of the error codes are also available in the
-/// global array pore_inline_error_strings[].
-///
-/// The assembler always produces PORE code in the PORE-native big-endian
-/// format.  Likewise, the diassembler assumes the host memory to be
-/// disassembled contains PORE code in big-endian format.
-///
-/// \section Initialization
-///
-/// Before invoking inline assembly/disassembly APIs, an instance of a
-/// PoreInlineContext structure must be initialized using the
-/// pore_inline_context_create() API.  For assembly, the context describes the
-/// host memory buffer that will contain the assembled code.  For disassembly,
-/// the context describes the host memory area that contains the code to be
-/// disassembled. Full documentation is available for
-/// pore_inline_context_create(), including documentation for options that
-/// control assembly and disassembly.  The implementation also provides a
-/// 'copy operator' for the context, pore_inline_context_copy().
-///
-/// An example of initializing a context for inline assembly with parity
-/// checking appears below.
-///
-/// \code 
-///
-/// PoreInlineContext ctx;
-/// uint32_t buf[BUFSIZE];
-///
-/// rc = pore_inline_context_create(&ctx, buf, BUFSIZE * 4, 0,
-///                                 PORE_INLINE_CHECK_PARITY);
-/// if (rc) . . . Handle Error
-///
-/// \endcode
-///
-/// Applications that reuse the same memory buffer for assembling and
-/// processing multiple PORE programs can 'reset' the context between uses by
-/// using the pore_inline_context_reset() API.  pore_inline_context_reset()
-/// resets the location counter and memory extent to their initial (creation)
-/// values, and the context error code is cleared.  Any options specified at
-/// creation remain as they were.
-///
-/// \section Assembler
-///
-/// The inline assembler implements each PORE/PGAS instruction as individual
-/// function calls.  The APIs are consistently named \c pore_\<OPCODE\>, where
-/// \c \<OPCODE\> is a PGAS mnemonic in upper case.  The arguments to each
-/// opcode appear in the same order that they appear in the source-level
-/// assembler, with appropriate C-language types. The supported opcode APIs
-/// are defined in pore_inline.h
-/// 
-/// Since the PORE instruction APIs are effectivly predicates, linear code
-/// sequences are easily assembled using the C-language logical OR construct.
-/// Any non-0 return code will immediatly break the sequence and set the
-/// expression value to 1.  The failure code can then be recovered from the \a
-/// error field of the context.  This coding technique is illustrated in the
-/// following example of assembling a memory-memory copy sequence.
-///
-/// \code 
-///
-/// PoreInlineContext ctx;
-/// int error;
-///
-/// . . . // Initialize context
-///
-/// error =
-///     pore_LD(&ctx, D0, 0, A0) ||
-///     pore_STD(&ctx, D0, 0, A1);
-///
-/// if (error) <. . . Handle error based on ctx.error>
-///
-/// \endcode
-///
-/// The above example generates code equivalent to
-///
-/// \code
-///
-///         ld      D0, 0, A0
-///         std     D0, 0, A1
-///
-/// \endcode
-///
-/// Again, if an error were to occur during assembly, inline assembly would
-/// stop (and the logical OR would terminate) at the point of failure. In
-/// particular, the inline assembler will never allow assembled code to exceed
-/// the bounds of the memory area defined by the initial call of
-/// pore_inline_context_create() that defines the assembler memory space.
-///
-///
-/// \subsection Register Names and Other Mnemonics
-///
-/// The header file pore_inline.h defines macros for the register mnemonics.
-///
-/// - D0, D1 : 64-bit data registers
-/// - A0, A1 : 32-bit address registers
-/// - P0, P1 : 7-bit Pervasive chiplet id registers
-/// - CTR : 24-bit ounter register
-/// - PC : 48-bit Program Counter
-/// - ETR : 64-bit EXE-Trigger Register (Low-order 32 bits are writable)
-/// - EMR : The Error Mask Register
-/// - IFR : ID/Flags Register
-/// - SPRG0 : 32-bit Special-Purpose General Register 0
-///
-/// Mnemonics for the condition code bits are also defined by pore_inline.h
-/// using the PGAS mnemonics.
-///
-///
-/// \subsection Assembling Branches
-///
-/// Opcodes that implement relative branches require that the branch target be
-/// specified as a <em> location counter </em>. Once initialized, the current
-/// location counter is available as the \a lc field of the PoreInlineContext
-/// object controlling the assembly.  The \a lc field is the only field
-/// (besides the error code held in the \a error field) that application code
-/// should ever reference. The inline assembler also provides a typedef
-/// PoreInlineLocation to use for location counters, as well as the macro
-/// PORE_LOCATION() to define a location variable inline with the code flow.
-/// 
-/// \subsubsection Backward Branches
-///
-/// Backward branches are straightforward.  For example, the memory-memory
-/// copy example from earlier can be converted into a loop as shown below.  The
-/// \a loop_target variable is initialized with the location counter of the
-/// first instruction of the loop.  The final instruction of the loop then
-/// branches back to the \a loop_target.
-///
-/// \code
-///
-/// PoreInlineContext ctx;
-/// PoreInlineLocation loop_target = 0; // See ** below the example
-/// int error;
-///
-/// . . . // Initialize context
-///
-/// error =
-///     PORE_LOCATION(&ctx, loop_target) ||
-///     pore_LD(&ctx, D0, 0, A0)         ||
-///     pore_STD(&ctx, D0, 0, A1)      	 ||
-///     pore_ADDS(&ctx, A0, A0, 8)     	 ||
-///     pore_ADDS(&ctx, A1, A1, 8)     	 ||
-///     pore_LOOP(&ctx, loop_target);
-///
-/// if (error) <. . . Handle error based on ctx.error>
-///
-/// \endcode
-///
-/// The above inline assembler sequence is equivalent to the PGAS code
-/// sequence:
-///
-/// \code
-///
-/// loop_target:
-///        ld      D0, 0, A0
-///        std     D0, 0, A1
-///        adds    A0, A0, 8
-///        adds    A1, A1, 8
-///        loop    loop_target
-///
-/// \endcode
-///
-/// ** Location counters used as loop targets may need to be initialized,
-/// otherwise the compiler may issue a warning that the variable "may be used
-/// uninitialized", although in well-written code this would never happen.
-///
-///
-/// \subsubsection Forward Branches
-///
-/// Forward branches are more complex.  Since the target location counter is
-/// not known until the target has been assembled, the inline assembler
-/// provides the API pore_inline_branch_fixup() to fix up forward branches
-/// once the actual target is known.  This is illustrated in the simple code
-/// sequence below, where an instruction is conditionally skipped.
-///
-/// \code
-///
-/// PoreInlineContext ctx;
-/// PoreInlineLocation source = 0, target = 0;
-/// int error, rc;
-///
-/// . . . // Initialize context
-///
-/// error = 
-///     PORE_LOCATION(&ctx, source)  ||
-///     pore_BRANZ(&ctx, D0, source) ||
-///     pore_ADDS(&ctx, D1, D1, 1)   ||
-///     PORE_LOCATION(&ctx, target)  ||
-///     pore_LD(&ctx, D0, 0, A0);
-///
-/// if (error) <. . . Handle assembly error based on ctx->error>
-/// rc = pore_inline_branch_fixup(&ctx, source, target);
-/// if (rc) <. . . Handle branch fixup error>
-///
-/// \endcode
-///
-/// In the above code, the branch instruction is initially assembled as a
-/// branch-to-self - the recommended idiom for forward branch source
-/// instructions.  Once the entire sequence has been assembled,
-/// pore_inline_branch_fixup() reassembles the \c source instruction as a
-/// branch to the \c target instruction. The above instruction sequence is
-/// equivalent to the PGAS code below:
-///
-/// \code
-///
-/// source:
-///         branz   D0, target
-///         adds    D1, D1, 1
-/// target:
-///         ld      D0, 0, A0
-///
-/// \endcode
-///
-///
-/// \subsubsection Absolute Branches
-///
-/// It is unlikely that a typical application of the PORE inline assembler
-/// would ever need to include an absolute branch, since the branch target in
-/// this case is a fixed absolute address that must be known at assembly
-/// time. However the inline assembler does provide the pore_BRAIA() API for
-/// this purpose.  This opcode requires a 16-bit address space constant and a
-/// 32-bit absoulte address (offset) within the memory space to specify the
-/// branch. 
-///
-///
-/// \section Disassembly
-///
-/// Inline disassembly is implemented by a single API,
-/// pore_inline_disassemble(). The idea is similar to assembly: A host memory
-/// context containing PORE code (or data) is described by a PoreInlineContext
-/// structure.  Each call of pore_inline_disassemble() disassembles the next
-/// instruction (or datum) in the context into a PoreInlineDisassembly
-/// structure provided by the caller.  The disassembly object contains both
-/// binary and string forms of the disassembled instruction (or data). The
-/// next call of pore_inline_disassemble() proceses the next instruction (or
-/// datum) and so on.
-///
-/// \subsection Text (Code) Disassembly
-///
-/// In the example below the inline disassembler is used to completely
-/// disassemble a memory area containing text (code) to \a stdout until an
-/// error occurs, assumed to be either due to disassembling the entire memory
-/// area or finding an illegal instruction.
-///
-/// \code
-///
-/// PoreInlineContext ctx;
-/// PoreInlineDisassembly dis;
-///
-/// . . . // Initialize context
-///
-/// while (pore_inline_disassemble(&ctx, &dis) == 0) {
-///     printf("%s\n", dis.s);
-/// }
-///
-/// \endcode
-///
-/// To illustrate binary disassembly, the following example uses the
-/// disassembler to search for a RET statement in a block of PORE code, in
-/// order to extend an inline subroutine with more code.  Note that the field
-/// \a dis->ctx contains the context that existed at the time the instruction
-/// was assembled.  By copying this context back into the global context,
-/// inline assembly will continue by overwriting the RET with new
-/// instructions. If the copy had \e not been done, then newly assembled code
-/// would have \e followed the RET.
-///
-/// \code
-///
-/// PoreInlineContext ctx;
-/// PoreInlineDisassembly dis;
-///
-/// . . . // Initialize context
-///
-/// while ((pore_inline_disassemble(&ctx, &dis) == 0) &&
-///        (dis.opcode != PORE_OPCODE_RET));
-/// if (ctx.error != 0) {
-///     . . . // Handle error
-/// } else {
-///     pore_inline_context_copy(&ctx, &dis.ctx);
-///     . . . // Continue assembly by overwriting the RET
-/// }
-///
-/// \endcode
-///
-/// A special type of context reset is available to simplify applications that
-/// need to disassemble a just-assembled code sequence, e.g. for debugging.
-/// pore_inline_context_reset_excursion() resets the context such that the
-/// effective size of the context only covers the just-assembled code,
-/// allowing a dissassembly loop to cleanly stop once all code has been
-/// disassembled. The use is illustrated below - note that the disassembly
-/// stops on the expected error code PORE_INLINE_NO_MEMORY once the
-/// (effective) end of the buffer is reached.
-///
-/// \code
-///
-/// PoreInlineContext ctx;
-/// PoreInlineDisassembly dis;
-///
-/// . . . // Initialize context
-/// . . . // Assemble code into context
-///
-/// pore_inline_context_reset_excursion(&ctx);
-///
-/// while (pore_inline_disassemble(&ctx, &dis) == 0) {
-///     printf("%s\n", dis.s);
-/// }
-/// if (ctx.error != PORE_INLINE_NO_MEMORY) {
-///     . . . // Handle error
-/// }
-///
-/// \endcode
-///
-/// \subsection Data Disassembly
-///
-/// If the PoreInlineContext is created with the flag
-/// PORE_INLINE_DISASSEMBLE_DATA, then the context is disassembled as data. If
-/// the PoreInlineContext is created with the flag
-/// PORE_INLINE_DISASSEMBLE_UNKNOWN then putative data embedded in a text
-/// section will be disassembled as data.  For complete information see the
-/// documentation for pore_inline_disassemble().
-
-
-#define __PORE_INLINE_ASSEMBLER_C__
-#include "pore_inline.h"
-#undef __PORE_INLINE_ASSEMBLER_C__
-
-// Definitions of PORE register classes.  These are predicates that return
-// 1 if the register is a member of the class, else 0.
-
-PORE_STATIC int
-pore_data(int reg)
-{
-    return 
-	(reg == D0) ||
-	(reg == D1);
-}
-
-
-PORE_STATIC int
-pore_address(int reg)
-{
-    return
-	(reg == A0) ||
-	(reg == A1);
-}
-
-
-PORE_STATIC int
-pore_pervasive_chiplet_id(int reg)
-{
-    return
-	(reg == P0) ||
-	(reg == P1);
-}
-
-
-PORE_STATIC int
-pore_branch_compare_data(int reg)
-{
-    return 
-	(reg == D0) ||
-	(reg == D1) ||
-	(reg == CTR);
-}
-
-
-PORE_STATIC int
-pore_ls_destination(int reg)
-{
-    return
-        (reg == D0) ||
-        (reg == D1) ||
-        (reg == A0) ||
-        (reg == A1) ||
-        (reg == P0) ||
-        (reg == P1) ||
-        (reg == CTR);
-}
-
-
-PORE_STATIC int
-pore_li_destination(int reg)
-{
-    return 
-        (reg == D0)   ||
-        (reg == D1)   ||
-        (reg == A0)   ||
-        (reg == A1)   ||
-        (reg == P0)   ||
-        (reg == P1)   ||
-        (reg == CTR);
-}
-
-
-PORE_STATIC int
-pore_mr_source(int reg)
-{
-    return
-        (reg == D0)    ||
-        (reg == D1)    ||
-        (reg == A0)    ||
-        (reg == A1)    ||
-        (reg == P0)    ||
-        (reg == P1)    ||
-        (reg == CTR)   ||
-        (reg == PC)    ||
-        (reg == ETR)   ||
-        (reg == SPRG0) ||
-        (reg == IFR)   ||
-        (reg == EMR);
-}
-
-PORE_STATIC int
-pore_mr_destination(int reg)
-{
-    return
-        (reg == D0)   ||
-        (reg == D1)   ||
-        (reg == A0)   ||
-        (reg == A1)   ||
-        (reg == P0)   ||
-        (reg == P1)   ||
-        (reg == CTR)  ||
-        (reg == PC)   ||
-        (reg == SPRG0)||
-        (reg == EMR);
-}                    
-
-
-/// Portable store of a 32-bit integer in big-endian format
-///
-/// The address \a p to receive the data is in the form of an unsigned long.
-
-void
-pore_inline_be32(unsigned long p, uint32_t x)
-{
-    uint8_t *p8 = (uint8_t *)p;
-    uint8_t *px = (uint8_t *)(&x);
-    int i, j;
-
-    if (!PORE_BIG_ENDIAN) {
-	for (i = 0, j = 3; i < 4; i++, j--) {
-	    p8[i] = px[j];
-	}
-    } else {
-	*((uint32_t *)p) = x;
-    }
-}
-	
-	
-/// Portable store of a 64-bit integer in big-endian format
-///
-/// The address \a p to receive the data is in the form of an unsigned long.
-
-void
-pore_inline_be64(unsigned long p, uint64_t x)
-{
-    uint8_t *p8 = (uint8_t *)p;
-    uint8_t *px = (uint8_t *)(&x);
-    int i, j;
-
-    if (!PORE_BIG_ENDIAN) {
-	for (i = 0, j = 7; i < 8; i++, j--) {
-	    p8[i] = px[j];
-	}
-    } else {
-	*((uint64_t *)p) = x;
-    }
-}
-
-
-// Portable load of a 32-bit integer in big-endian format
-
-uint32_t
-pore_inline_host32(unsigned long p)
-{
-    uint32_t x;
-    uint8_t *p8 = (uint8_t *)p;
-    uint8_t *px = (uint8_t *)(&x);
-    int i, j;
-
-    if (!PORE_BIG_ENDIAN) {
-	for (i = 0, j = 3; i < 4; i++, j--) {
-	    px[j] = p8[i];
-	}
-    } else {
-	x = *((uint32_t *)p);
-    }
-
-    return x;
-}
-	
-	
-// Portable load of a 64-bit integer in big-endian format
-
-uint64_t
-pore_inline_host64(unsigned long p)
-{
-    uint64_t x;
-    uint8_t *p8 = (uint8_t *)p;
-    uint8_t *px = (uint8_t *)(&x);
-    int i, j;
-
-    if (!PORE_BIG_ENDIAN) {
-	for (i = 0, j = 7; i < 8; i++, j--) {
-	    px[j] = p8[i];
-	}
-    } else {
-	x = *((uint64_t *)p);
-    }
-
-    return x;
-}
-
-
-// 32-bit population count
-//
-// This is a well-known divide-and-conquer algorithm.  The idea is to compute
-// sums of adjacent bit segments in parallel, in place.
-
-PORE_STATIC int
-pore_popcount32(uint32_t x)
-{
-    uint32_t m1 = 0x55555555;
-    uint32_t m2 = 0x33333333;
-    uint32_t m4 = 0x0f0f0f0f;
-    x -= (x >> 1) & m1;		   /* Sum pairs of bits */
-    x = (x & m2) + ((x >> 2) & m2);/* Sum 4-bit segments */
-    x = (x + (x >> 4)) & m4;	   /* Sum 8-bit segments */
-    x += x >>  8;		   /* Sum 16-bit segments */
-    return (x + (x >> 16)) & 0x3f; /* Final sum */
-}
-
-
-// 64-bit population count
-
-PORE_STATIC int
-pore_popcount64(uint64_t x)
-{
-    return pore_popcount32(x & 0xffffffff) + pore_popcount32(x >> 32);
-}
-
-
-// Compute the parity of a PORE instruction as 0 or 1
-
-int
-pore_inline_parity(uint32_t instruction, uint64_t imd64)
-{
-    return (pore_popcount32(instruction) + pore_popcount64(imd64)) % 2;
-}
-	
-	
-/// Reset a PORE inline assembler context to its creation state
-///
-/// \param ctx A pointer to an initialized (and likely 'used')
-/// PoreInlineContext object.
-///
-/// This API resets a PoreInlineContext object to it's \e creation state, that
-/// is, the state it was in after the call of pore_inline_context_create().
-/// This API is designed for applications that reuse a memory buffer to
-/// assemble multiple PORE code sequences.  After each sequence has been fully
-/// assembled and processed, calling pore_inline_context_reset() sets the
-/// context back as it was when the context was initially created so that the
-/// memory area can be reused.  In particular, this API resets the location
-/// counter and memory extent to their initial values, and the error code is
-/// cleared.  Any options specified at creation remain as they were.
-///
-/// For a slightly different type of reset, see
-/// pore_inline_context_reset_excursion().  
-
-void
-pore_inline_context_reset(PoreInlineContext *ctx)
-{
-    ctx->lc_address = ctx->memory;
-    ctx->remaining = ctx->size;
-    ctx->lc = ctx->original_lc;
-    ctx->error = 0;
-}
-
-
-
-/// Reset a PORE inline assembler context to a special state for disassembly
-///
-/// \param ctx A pointer to an initialized (and almost certainly 'used')
-/// PoreInlineContext object.
-///
-/// This API resets a PoreInlineContext object to it's \e creation state, that
-/// is, the state it was in after the call of pore_inline_context_create(), \e
-/// except that the effective size of the memory area has been reduced to the
-/// size that was actually used during assembly.  This API is designed for
-/// applications that assemble into a memory buffer and then want to easily
-/// disassemble the code (e.g., for debugging).  After a code sequence has
-/// been assembled, calling pore_inline_context_reset_excursion() sets the
-/// context back as it was when the context was initially created, but with a
-/// (typically) shorter effective length, so that the disassembly will cleanly
-/// stop once the entire sequence has been disassembled. Once disassembled,
-/// the buffer can be fully resued after a subsequent call of
-/// pore_inline_context_reset().  In particular, this API resets the location
-/// counter to its initial value, clears the error code, and sets the
-/// effective size of the context to the amount of memory currently used.  Any
-/// options specified at creation remain as they were.
-///
-/// For a full context reset see pore_inline_context_reset(). For an example
-/// see the \b Disassembly section of \ref pore_inline_assembler.
-
-void
-pore_inline_context_reset_excursion(PoreInlineContext *ctx)
-{
-    ctx->lc_address = ctx->memory;
-    ctx->remaining = ctx->size - ctx->remaining;
-    ctx->lc = ctx->original_lc;
-    ctx->error = 0;
-}
-
-
-/// Create a PORE inline assembler context
-///
-/// \param ctx A pointer to a PoreInlineContext object to be initialized
-/// and used for inline assembly. or disassembly.
-///
-/// \param memory A pointer to the host memory area to receive the assembled
-/// code, or contain the code to disassemble. In general the inline assembler
-/// will expect this memory area to be 4-byte aligned. This pointer may be
-/// NULL (0) only if the associated \a size is also 0.
-///
-/// \param size The size (in bytes) of the host memory area. The inline
-/// assembler will generate the PORE_INLINE_NO_MEMORY error if an attempt is
-/// made to assemble an instruction that would overflow the buffer, or
-/// disassemble past the end of the buffer. A 0 size is valid.
-///
-/// \param lc The initial, bytewise, target location counter for the assembled
-/// or disassembled code. This paramater will normally be initialized to 0 for
-/// assembling relocatable programs. The parameter would only need to be
-/// specified as non-0 for special cases, such as creating a context for
-/// disassembly.
-///
-/// \param options Option flags.  Option flags are OR-ed together to create
-/// the final set of options. Valid options are
-///
-/// - PORE_INLINE_GENERATE_PARITY : Generate the proper parity bit for each
-/// instruction during assembly.
-///
-/// - PORE_INLINE_CHECK_PARITY : Check for correct instruction parity during
-/// disassembly.
-///
-/// - PORE_INLINE_LISTING_MODE : Generate disassembly strings in the form of a
-/// listing that contains location counters and encoded instructions as well
-/// as their diassembly.  By default the disassembly strings do not contain
-/// this information and can be fed back in as source code to a PORE
-/// assembler.
-///
-/// - PORE_INLINE_DISASSEMBLE_DATA : generate disassembly assuming that the
-/// context contains data rather than text. Normally data is disassembled as
-/// .long directives, however if the context is unaligned or of an odd length
-/// then .byte directives may be used as well.  This option can be used in
-/// conjunction with PORE_INLINE_LISTING_MODE.
-///
-/// - PORE_INLINE_8_BYTE_DATA : generate data disassembly using 8-byte values
-/// rather than the default 4-byte values.  Normally data is disassembled as
-/// .quad directives under this option, however if the context is unaligned or
-/// of an odd length then .long and .byte directives may be used as well.
-/// This option can be used in conjunction with PORE_INLINE_LISTING_MODE.
-///
-/// A PoreInlineContext describes a memory area and assembler context for
-/// inline assembly and disassembly.  Assembly/disassembly begins at the host
-/// memory location and virtual location counter described in the parameters.
-/// As instructions are assembled/disassembled the PoreInlineContext keeps
-/// track of where in the host memory and virtual PORE memory areas to place
-/// new instructions during assembly, or from where to fetch the next
-/// instruction to disassemble.
-///
-/// \retval 0 Success
-///
-/// \retval PORE_INLINE_INVALID_PARAMETER Either the \a context pointer is
-/// NULL (0), the \a memory pointer is NULL (0) with a non-0 size, or the \a
-/// options include invalid options.  The error code is also stored as the
-/// value of ctx->error, and in the event of an error the ctx->size field is
-/// set to 0, effectively preventing the context from being used.
-
-int
-pore_inline_context_create(PoreInlineContext *ctx,
-			   void *memory, size_t size, 
-			   PoreInlineLocation lc, int options)
-{
-    int rc;
-
-    int valid_options = 
-	PORE_INLINE_GENERATE_PARITY  |
-	PORE_INLINE_CHECK_PARITY     |
-	PORE_INLINE_LISTING_MODE     |
-        PORE_INLINE_DISASSEMBLE_DATA |
-        PORE_INLINE_8_BYTE_DATA      |
-        PORE_INLINE_DISASSEMBLE_UNKNOWN;
-
-    if ((ctx == 0) || ((memory == 0) && (size != 0)) || 
-	((options & ~valid_options) != 0)) {
-	rc = PORE_INLINE_INVALID_PARAMETER;
-    } else {
-	rc = 0;
-	ctx->memory = (unsigned long)memory;
-	ctx->size = size;
-	ctx->original_lc = lc;
-	ctx->options = options;
-	pore_inline_context_reset(ctx);
-    }
-
-    if (ctx != 0) {
-        ctx->error = rc;
-        if (rc) {
-            ctx->size = 0;      /* Effectively prevents using the ctx */
-        }
-    }
-
-    return rc;
-}
-	
-	
-/// Copy a PORE inline assembler context
-///
-/// \param dest A pointer to a PoreInlineContext object to be initialized
-/// as a copy of the \a src context.
-///
-/// \param src A pointer to a PoreInlineContext object to be used as the
-/// source of the copy.
-///
-/// This API copies one PoreInlineContext structure to another.  An example
-/// use appears in \ref pore_inline_assembler in the section discussing
-/// disassembly.
-
-void
-pore_inline_context_copy(PoreInlineContext *dest, PoreInlineContext *src)
-{
-    *dest = *src;
-}
-
-
-// 'Bump' a context forward by a given number of bytes.  This an internal API
-// and the bump is always known to be legal.
-
-void
-pore_inline_context_bump(PoreInlineContext *ctx, size_t bytes)
-{
-    ctx->remaining -= bytes;
-    ctx->lc += bytes;
-    ctx->lc_address += bytes;
-}    
-
-
-// Allocate space in the inline assembler context
-//
-// Allocation is specified and implemented in bytes.  Both the physical
-// memory and the virtual LC are required to be 4-byte aligned. The allocator
-// returns a pointer to the memory area, or 0 if allocation fails.
-// Allocation failure sets the context error code to either
-// PORE_INLINE_NO_MEMORY or PORE_INLINE_ALIGNMENT_ERROR.
-
-PORE_STATIC unsigned long
-pore_inline_allocate(PoreInlineContext *ctx, size_t bytes)
-{
-    unsigned long p = 0;
-
-    if (((ctx->lc % 4) != 0) || 
-	((ctx->lc_address % 4) != 0)) {
-	ctx->error = PORE_INLINE_ALIGNMENT_ERROR;
-
-    } else if (bytes > ctx->remaining) {
-	ctx->error = PORE_INLINE_NO_MEMORY;
-
-    } else {
-	p = ctx->lc_address;
-	pore_inline_context_bump(ctx, bytes);
-    }
-    return p;
-}
-
-
-// Assemble a 1-word instruction
-//
-// The opcode and operand are assumed to be legal, having come from
-// abstractions that check their arguments.  This call may fail with
-// PORE_INLINE_NO_MEMORY if there is no more room in the memory buffer. A
-// non-zero return indicates failure.
-
-int
-pore_inline_instruction1(PoreInlineContext *ctx, int opcode, uint32_t operand)
-{
-    uint32_t instruction;
-    unsigned long p;
-
-    p = pore_inline_allocate(ctx, 4);
-    if (p != 0) {
-
-	instruction = (opcode << 25) | operand;
-	if (ctx->options & PORE_INLINE_GENERATE_PARITY) {
-	    instruction |= (1 - pore_inline_parity(instruction, 0)) << 24;
-	}
-
-	pore_inline_be32(p, instruction);
-	ctx->error = 0;
-    }
-    return p == 0;
-}
-	    
-
-// Assemble a 3-word instruction
-//
-// The opcode and operand are assumed to be legal, having come from
-// abstractions that check their arguments.  This call may fail with
-// PORE_INLINE_NO_MEMORY if there is no more room in the memory buffer.  A
-// non-zero return indicates failure.
-
-int
-pore_inline_instruction3(PoreInlineContext *ctx, int opcode, uint32_t operand,
-			 uint64_t immediate)
-{
-    uint32_t instruction;
-    unsigned long p;
-
-    p = pore_inline_allocate(ctx, 12);
-    if (p != 0) {
-
-	instruction = (opcode << 25) | operand;
-	if (ctx->options & PORE_INLINE_GENERATE_PARITY) {
-	    instruction |= (1 - pore_inline_parity(instruction, immediate)) << 24;
-	}
-
-	pore_inline_be32(p, instruction);
-	pore_inline_be64(p + 4, immediate);
-	ctx->error = 0;
-    }
-    return p == 0;
-}
-
-
-// Assemble WAIT
-//
-// The cycle count must be an unsigned 24-bit immediate otherwise the error
-// PORE_INLINE_UINT24_REQUIRED is signalled.  PGAS requires that HALT be used
-// if the intention is to halt 
-
-int
-pore_WAITS(PoreInlineContext *ctx, uint32_t cycles)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_WAITS;
-
-    if (cycles == 0) {
-        ctx->error = PORE_INLINE_USE_HALT;
-    } else if ((cycles & 0xffffff) != cycles) {
-	ctx->error = PORE_INLINE_UINT24_REQUIRED;
-    } else {
-	operand = cycles;
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-
-// Assemble HOOKI
-//
-// The hook index must be an unsigned 24-bit immediate otherwise the error
-// PORE_INLINE_UINT24_REQUIRED is signalled.
-
-int
-pore_HOOKI(PoreInlineContext *ctx, uint32_t index, uint64_t imm)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_HOOKI;
-
-    if ((index & 0xffffff) != index) {
-	ctx->error = PORE_INLINE_UINT24_REQUIRED;
-    } else {
-	operand = index;
-	pore_inline_instruction3(ctx, opcode, operand, imm);
-    }
-    return ctx->error;
-}
-
-
-// Assemble BRA, BSR and LOOP
-//
-// The branch target here is a bytewise location counter.  The target must be
-// 4-byte aligned and must be within the legal signed 24-bit word offset of
-// the current LC. Unaligned targets cause PORE_INLINE_ALIGNMENT_ERROR.
-// Unreachable targets cause PORE_INLINE_UNREACHABLE_TARGET.
-
-int
-pore_inline_bra(PoreInlineContext *ctx, int opcode, PoreInlineLocation target)
-{
-    int32_t offset;
-    uint32_t operand;
-
-    if (target % 4) {
-	ctx->error = PORE_INLINE_ALIGNMENT_ERROR;
-    } else {
-	offset = (int32_t)(target - ctx->lc) / 4;
-	if ((offset >= (1 << 23)) ||
-	    (offset < -(1 << 23))) {
-	    ctx->error = PORE_INLINE_UNREACHABLE_TARGET;
-	} else {
-	    operand = offset & 0xffffff;
-	    pore_inline_instruction1(ctx, opcode, operand);
-	}
-    }
-    return ctx->error;
-}
-	    
-
-// Assemble BRAZ and BRANZ
-//
-// The branch target here is a bytewise location counter.  The target must be
-// 4-byte aligned and must be within the legal signed 20-bit word offset of
-// the current LC. Unaligned targets cause PORE_INLINE_ALIGNMENT_ERROR.
-// Unreachable targets cause PORE_INLINE_UNREACHABLE_TARGET.  Illegal
-// operands cause PORE_INLINE_ILLEGAL_REGISTER.
-
-int
-pore_inline_brac(PoreInlineContext *ctx, int opcode, int reg, 
-		 PoreInlineLocation target)
-{
-    int32_t offset;
-    uint32_t operand;
-
-    if (target % 4) {
-	ctx->error = PORE_INLINE_ALIGNMENT_ERROR;
-    } else if (!pore_branch_compare_data(reg)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	offset = (int32_t)(target - ctx->lc) / 4;
-	if ((offset >= (1 << 20)) ||
-	    (offset < -(1 << 20))) {
-	    ctx->error = PORE_INLINE_UNREACHABLE_TARGET;
-	} else {
-	    operand = (offset & 0xfffff) | (reg << 20);
-	    pore_inline_instruction1(ctx, opcode, operand);
-	}
-    }
-    return ctx->error;
-}
-
-
-// Assemble CMPIBRAEQ, CMPIBRANE, CMPIBSREQ
-//
-// The branch target here is a bytewise location counter.  The target must be
-// 4-byte aligned and must be within the legal signed 24-bit word offset of
-// the current LC. Unaligned targets cause PORE_INLINE_ALIGNMENT_ERROR.
-// Unreachable targets cause PORE_INLINE_UNREACHABLE_TARGET. Illegal
-// operands cause PORE_INLINE_ILLEGAL_REGISTER.
-
-int
-pore_inline_cmpibra(PoreInlineContext *ctx, int opcode, int reg,
-                    PoreInlineLocation target, uint64_t imm)
-{
-    int32_t offset;
-    uint32_t operand;
-
-    if (target % 4) {
-	ctx->error = PORE_INLINE_ALIGNMENT_ERROR;
-    } else if (reg != D0) {
-        ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	offset = (int32_t)(target - ctx->lc) / 4;
-	if ((offset >= (1 << 23)) ||
-	    (offset < -(1 << 23))) {
-	    ctx->error = PORE_INLINE_UNREACHABLE_TARGET;
-	} else {
-	    operand = offset & 0xffffff;
-	    pore_inline_instruction3(ctx, opcode, operand, imm);
-	}
-    }
-    return ctx->error;
-}
-
-
-// Assemble BRAD and BSRD
-//
-// Illegal operands cause PORE_INLINE_ILLEGAL_REGISTER.
-
-int
-pore_inline_brad(PoreInlineContext *ctx, int opcode, int reg)
-{
-    uint32_t operand;
-
-    if (!pore_data(reg)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	operand = reg << 20;
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-
-// Assemble ANDI, ORI, XORI
-//
-// Source and destination must be of class 'data' otherwise the
-// PORE_INLINE_ILLEGAL_REGISTER error is generated.
-
-int
-pore_inline_ilogic(PoreInlineContext *ctx, int opcode, 
-		   int dest, int src, uint64_t imm)
-{
-    uint32_t operand;
-
-    if (!pore_data(dest) || !pore_data(src)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	operand = (dest << 20) | (src << 16);
-	pore_inline_instruction3(ctx, opcode, operand, imm);
-    }
-    return ctx->error;
-}
-
-
-// Assemble AND, OR, XOR, ADD, SUB
-//
-// Destination must be of class 'data' otherwise the
-// PORE_INLINE_ILLEGAL_REGISTER error is generated.  src1 and src2 must be D0,
-// D1 respectively otherwise the PORE_INLINE_ILLEGAL_REGISTER error is
-// generated.
-
-int
-pore_inline_alurr(PoreInlineContext *ctx, 
-                  int opcode, int dest, int src1, int src2)
-{
-    uint32_t operand;
-
-    if (!pore_data(dest) || (src1 != D0) || (src2 != D1)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	operand = (dest << 20);
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-
-// Assemble ADDS and SUBS
-//
-// Destination must be of class 'ls_destination' and must be equal to source,
-// otherwise the PORE_INLINE_ILLEGAL_REGISTER error is generated.  If the
-// immediate is not a signed 16-bit immediate then the
-// PORE_INLINE_INT16_REQUIRED error is generated.
-
-int
-pore_inline_adds(PoreInlineContext *ctx, 
-                 int opcode, int dest, int src, int imm)
-{
-    uint32_t operand;
-
-    if (!pore_ls_destination(dest) || (dest != src)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	if ((imm >= (1 << 15)) ||
-	    (imm < -(1 << 15))) {
-	    ctx->error = PORE_INLINE_INT16_REQUIRED;
-	} else {
-	    operand = (dest << 20) | (imm & 0xffff);
-	    pore_inline_instruction1(ctx, opcode, operand);
-	}
-    }
-    return ctx->error;
-}
-
-
-// Assemble NEG
-//
-// Source and destination must be of class 'data' otherwise the
-// PORE_INLINE_ILLEGAL_REGISTER error is generated.
-
-int
-pore_NEG(PoreInlineContext *ctx, int dest, int src)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_NEG;
-
-    if (!pore_data(dest) || !pore_data(src)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	operand = (dest << 20) | (src << 16);
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-
-// Assemble MR
-//
-// The source must be an 'mr_source' and the destination must be an
-// 'mr_destination' otherwise the PORE_INLINE_ILLEGAL_REGISTER error is
-// generated.
-
-int
-pore_MR(PoreInlineContext *ctx, int dest, int src)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_MR;
-
-    if (!pore_mr_destination(dest) || !pore_mr_source(src)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	operand = (dest << 20) | (src << 16);
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-	    
-
-// Assemble ROLS
-//
-// Source and destination must be of class 'data' otherwise the
-// PORE_INLINE_ILLEGAL_REGISTER error is generated.  Illegal shifts yield the
-// PORE_INLINE_ILLEGAL_ROTATE error.
-
-int
-pore_ROLS(PoreInlineContext *ctx, int dest, int src, int imm)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_ROLS;
-    
-    if (!pore_data(dest) || !pore_data(src)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else if ((imm != 1) &&
-	       (imm != 4) &&
-	       (imm != 8) &&
-	       (imm != 16) &&
-	       (imm != 32)) {
-	ctx->error = PORE_INLINE_ILLEGAL_ROTATE;
-    } else {
-	operand = (dest << 20) | (src << 16) | imm;
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-
-// Assemble LS
-//
-// The destination must be an 'ls_destination' otherwise the
-// PORE_INLINE_ILLEGAL_REGISTER error is generated.  If the immediate is not
-// a signed 20-bit immediate then the PORE_INLINE_INT20_REQUIRED error is
-// generated. 
-
-int
-pore_LS(PoreInlineContext *ctx, int dest, int imm)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_LS;
-    
-    if (!pore_ls_destination(dest)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else if ((imm >= (1 << 19)) ||
-               (imm < -(1 << 19))) {
-        ctx->error = PORE_INLINE_INT20_REQUIRED;
-    } else {
-	operand = (dest << 20) | (imm & 0xfffff);
-	pore_inline_instruction1(ctx, opcode, operand);
-    }
-    return ctx->error;
-}
-
-
-// Assemble LI
-//
-// The destination must be an 'li destination' otherwise the
-// PORE_INLINE_ILLEGAL_REGISTER error is generated.
-
-int
-pore_LI(PoreInlineContext *ctx, int dest, uint64_t imm)
-{
-    uint32_t operand;
-    int opcode = PGAS_OPCODE_LI;
-    
-    if (!pore_li_destination(dest)) {
-	ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    } else {
-	operand = dest << 20;
-	pore_inline_instruction3(ctx, opcode, operand, imm);
-    }
-    return ctx->error;
-}
-
-
-// BSI and BCI are normally redacted as instructions due to HW274735
-
-// LD, LDANDI, STD, STI, BSI, BCI
-
-PORE_STATIC void
-pervasive_ima24(PoreInlineContext *ctx, 
-                int opcode, uint32_t offset, int base, uint64_t imm)
-{
-    uint32_t operand;
-
-    if ((offset & 0x80f00000) != 0) {
-        ctx->error = PORE_INLINE_ILLEGAL_SCOM_ADDRESS;
-    } else {
-        operand = ((base % 2) << 22) | (offset & 0xfffff);
-        switch (opcode) {
-        case PGAS_OPCODE_LD0:
-        case PGAS_OPCODE_LD1:
-        case PGAS_OPCODE_STD0:
-        case PGAS_OPCODE_STD1:
-            pore_inline_instruction1(ctx, opcode, operand);
-            break;
-        default:
-            pore_inline_instruction3(ctx, opcode, operand, imm);
-            break;
-        }
-    }
-}            
-        
-
-PORE_STATIC void
-memory_ima24(PoreInlineContext *ctx, 
-             int opcode, uint32_t offset, int base, uint64_t imm)
-{
-    uint32_t operand;
-
-    if ((offset & 0x3fffff) != offset) {
-        ctx->error = PORE_INLINE_UINT22_REQUIRED;
-    } else if ((offset % 8) != 0) {
-        ctx->error = PORE_INLINE_ALIGNMENT_ERROR;
-    } else {
-        operand = 0x800000 | ((base % 2) << 22) | (offset & 0x3fffff);
-        switch (opcode) {
-        case PGAS_OPCODE_LD0:
-        case PGAS_OPCODE_LD1:
-        case PGAS_OPCODE_STD0:
-        case PGAS_OPCODE_STD1:
-            pore_inline_instruction1(ctx, opcode, operand);
-            break;
-        default:
-            pore_inline_instruction3(ctx, opcode, operand, imm);
-            break;
-        }
-    }
-}
-
-
-PORE_STATIC void
-ima24(PoreInlineContext *ctx, 
-      int opcode, uint32_t offset, int base, uint64_t imm)
-{
-    if (pore_pervasive_chiplet_id(base)) {
-        pervasive_ima24(ctx, opcode, offset, base, imm);
-    } else if (pore_address(base)) {
-        memory_ima24(ctx, opcode, offset, base, imm);
-    } else {
-        ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-    }
-}
-
-
-int
-pore_inline_load_store(PoreInlineContext *ctx, 
-		       int opcode, int src_dest, int32_t offset, int base,
-		       uint64_t imm)
-{
-    switch (opcode) {
-
-    case PORE_INLINE_PSEUDO_LD:
-    case PORE_INLINE_PSEUDO_LDANDI:
-    case PORE_INLINE_PSEUDO_STD:
-
-        // These three pick the real opcode based on the dest. register
-
-        if (!pore_data(src_dest)) {
-            ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-        } else {
-            switch (opcode) {
-            case PORE_INLINE_PSEUDO_LD:
-                opcode = (src_dest == D0) ? 
-                    PGAS_OPCODE_LD0 : PGAS_OPCODE_LD1;
-                break;
-            case PORE_INLINE_PSEUDO_LDANDI:
-                opcode = (src_dest == D0) ? 
-                    PGAS_OPCODE_LD0ANDI : PGAS_OPCODE_LD1ANDI;
-                break;
-            case PORE_INLINE_PSEUDO_STD:
-                opcode = (src_dest == D0) ? 
-                    PGAS_OPCODE_STD0 : PGAS_OPCODE_STD1;
-                break;
-            }
-        }
-        break;
-
-#ifdef IGNORE_HW274735
-
-        // BSI and BCI are normally redacted as instructions due to HW274735
-        
-        case PGAS_OPCODE_BSI:
-        case PGAS_OPCODE_BCI:
-        
-            if (src_dest != D0) {
-                ctx->error = PORE_INLINE_ILLEGAL_REGISTER;
-            }
-            break;
-
-#endif // IGNORE_HW274735
-
-    case PGAS_OPCODE_STI:
-        break;
-
-    default:
-        ctx->error = PORE_INLINE_BUG;
-    }
-
-    if (ctx->error == 0) {
-        ima24(ctx, opcode, offset, base, imm);
-    }
-
-    return ctx->error;
-}
-
-
-// Assemble BRAIA
-
-int
-pore_BRAIA(PoreInlineContext *ctx,
-           uint16_t address_space, uint32_t offset)
-{
-    int opcode = PGAS_OPCODE_BRAI;
-    uint32_t operand = 0;
-    uint64_t imm = ((uint64_t)address_space << 32) | offset;
-
-    pore_inline_instruction3(ctx, opcode, operand, imm);
-
-    return ctx->error;
-}
-
-
-// Assemble SCAND
-
-int
-pore_SCAND(PoreInlineContext *ctx,
-           int update, int capture, uint16_t length, 
-           uint32_t select, uint32_t offset)
-{
-    int opcode = PGAS_OPCODE_SCAND;
-    uint32_t operand;
-    uint64_t imm = ((uint64_t)select << 32) | offset;
-
-    if ((update < 0) ||
-        (update > 1) ||
-        (capture < 0) ||
-        (capture > 1)) {
-        ctx->error = PORE_INLINE_INVALID_PARAMETER;
-    } else {
-        opcode = PGAS_OPCODE_SCAND;
-        operand = (update << 23) | (capture << 22) | length;
-        pore_inline_instruction3(ctx, opcode, operand, imm);
-    }
-    return ctx->error;
-}
-        
-
-/// Fix up a PORE inline assembler forward branch instruction
-///
-/// \param ctx A pointer to the initialized PoreInlineContext object
-/// controlling inline assembly.
-///
-/// \param source The PORE inline location counter associated with the source
-/// instruction of the forward branch.
-///
-/// \param target The PORE inline location counter associated with the target
-/// instruction of the forward branch.
-///
-/// For usage examples, see the documentation \ref pore_inline_assembler.
-/// Although intended for forward branches, this API could be used to create
-/// backward branches as well.  Note however the limitation that the \a source
-/// must be in the current context, since the source instruction needs to be
-/// reassembled with the branch target. In theory the \a target could be
-/// anywhere, as long as the location counter of the target is known.
-///
-/// \retval 0 Success
-///
-/// \retval code Failure.  Any non-zero return is the PORE inline assmebler
-/// error code. The failure code is also stored in the PoreInlineContext
-/// object \a error field.  The most likely causes of failure include a source
-/// location that is not in the current context or not associated with a
-/// branch instruction.
-
-int
-pore_inline_branch_fixup(PoreInlineContext *ctx, 
-			 PoreInlineLocation source,
-			 PoreInlineLocation target)
-{
-    uint32_t instruction;
-    int32_t distance;
-    uint64_t imm;
-    int opcode, reg;
-    PoreInlineContext source_ctx;
-
-    if ((source < ctx->original_lc) ||
-	(source > ctx->lc)) {
-	ctx->error = PORE_INLINE_ILLEGAL_SOURCE_LC;
-    } else {
-
-	// Create a context as it existed when the source instruction was
-	// initially assembled, and then reassemble the instruction in that
-	// context with the actual target.
-
-	distance = ctx->lc - source;
-
-	source_ctx = *ctx;
-	source_ctx.lc = source;
-	source_ctx.remaining += distance;
-	source_ctx.lc_address -= distance;
-	source_ctx.error = 0;
-	
-	instruction = pore_inline_host32(source_ctx.lc_address);
-	opcode = (instruction >> 25);
-	reg = (instruction >> 20) & 0xf;
-	
-	switch (opcode) {
-	case PGAS_OPCODE_BRA:
-	    pore_BRA(&source_ctx, target);
-	    break;
-	case PGAS_OPCODE_BSR:
-	    pore_BSR(&source_ctx, target);
-	    break;
-	case PGAS_OPCODE_LOOP:
-	    pore_LOOP(&source_ctx, target);
-	    break;
-	case PGAS_OPCODE_BRAZ:
-	    pore_BRAZ(&source_ctx, reg, target);
-	    break;
-	case PGAS_OPCODE_BRANZ:
-	    pore_BRANZ(&source_ctx, reg, target);
-	    break;
-	case PGAS_OPCODE_CMPIBRAEQ:
-	    imm = pore_inline_host64(source_ctx.lc_address + 4);
-	    pore_CMPIBRAEQ(&source_ctx, D0, target, imm);
-	    break;
-	case PGAS_OPCODE_CMPIBRANE:
-	    imm = pore_inline_host64(source_ctx.lc_address + 4);
-	    pore_CMPIBRANE(&source_ctx, D0, target, imm);
-	    break;
-	case PGAS_OPCODE_CMPIBSREQ:
-	    imm = pore_inline_host64(source_ctx.lc_address + 4);
-	    pore_CMPIBSREQ(&source_ctx, D0, target, imm);
-	    break;
-	default:
-	    source_ctx.error = PORE_INLINE_NOT_A_BRANCH;
-	    break;
-	}
-
-	ctx->error = source_ctx.error;
-    }
-    return ctx->error;
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c
deleted file mode 100644
index b3b344137..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c
+++ /dev/null
@@ -1,2563 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.c $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: sbe_xip_image.c,v 1.31 2015/07/29 23:40:06 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/sbe/sbe_xip_image.c,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//-----------------------------------------------------------------------------
-// *! OWNER NAME: Bishop Brock          Email: bcbrock@us.ibm.com
-//------------------------------------------------------------------------------
-
-/// \file sbe_xip_image.c 
-/// \brief APIs for validating, normalizing, searching and manipulating
-/// SBE-XIP images.
-///
-/// The background, APIs and implementation details are documented in the
-/// document "SBE-XIP Binary format" currently available at this link:
-///
-/// - https://mcdoc.boeblingen.de.ibm.com/out/out.ViewDocument.php?documentid=2678
-///
-/// \bug The sbe_xip_validate() API should be carefully reviewed to ensure
-/// that validating even a corrupt image can not lead to a segfault, i.e., to
-/// ensure that no memory outside of the putative bounds of the image is ever
-/// referenced during validation.
-
-#ifndef PLIC_MODULE
-#include <stddef.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#endif // PLIC_MODULE
-
-#include <stddef.h>
-#include <stdint.h>
-#include <stdlib.h>
-#include <string.h>
-#include "sbe_xip_image.h"
-
-
-////////////////////////////////////////////////////////////////////////////
-// Local Functions
-////////////////////////////////////////////////////////////////////////////
-
-// PHYP has their own way of implementing the <string.h> functions. PHYP also
-// does not allow static functions or data, so all of the XIP_STATIC functions
-// defined here are global to PHYP.
-
-#ifdef PPC_HYP
-
-#ifdef PLIC_MODULE
-
-#define strcpy(dest, src) hvstrcpy(dest, src)
-#define strlen(s) hvstrlen(s)
-#define strcmp(s1, s2) hvstrcmp(s1, s2)
-#endif //PLIC_MODULE
-
-#define XIP_STATIC
-        
-#else // PPC_HYP
-
-#define XIP_STATIC static
-
-#endif // PPC_HYP
-
-
-#ifdef DEBUG_SBE_XIP_IMAGE
-
-// Debugging support, normally disabled. All of the formatted I/O you see in
-// the code is effectively under this switch.
-
-#ifdef __FAPI
-
-#include "fapi.H"
-#define fprintf(stream, ...) FAPI_ERR(__VA_ARGS__)
-#define printf(...) FAPI_INF(__VA_ARGS__)
-#define TRACE_NEWLINE ""
-
-#else // __FAPI
-
-#include <stdio.h>
-#define TRACE_NEWLINE "\n"
-
-#endif // __FAPI
-
-// Portable formatting of uint64_t.  The ISO C99 standard requires
-// __STDC_FORMAT_MACROS to be defined in order for PRIx64 etc. to be defined. 
-
-#define __STDC_FORMAT_MACROS
-#include <inttypes.h>
-
-#define F0x016llx "0x%016" PRIx64
-#define F0x012llx "0x%012" PRIx64
-
-XIP_STATIC SBE_XIP_ERROR_STRINGS(sbe_xip_error_strings);
-
-#define TRACE_ERROR(x)                                                  \
-    ({                                                                  \
-        fprintf(stderr, "%s:%d : Returning error code %d : %s" TRACE_NEWLINE, \
-                __FILE__, __LINE__, (x),                                \
-                SBE_XIP_ERROR_STRING(sbe_xip_error_strings, (x)));      \
-        (x);                                                            \
-    })
-
-#define TRACE_ERRORX(x, ...)                    \
-    ({                                          \
-        TRACE_ERROR(x);                         \
-        fprintf(stderr, ##__VA_ARGS__);         \
-        (x);                                    \
-    })
-
-
-// Uncomment these if required for debugging, otherwise we get warnings from
-// GCC as they are not otherwise used.
-
-#if 0
-
-XIP_STATIC uint32_t xipRevLe32(const uint32_t i_x);
-
-XIP_STATIC SBE_XIP_TYPE_STRINGS(type_strings);
-
-XIP_STATIC void
-dumpToc(int index, SbeXipToc* toc)
-{
-    printf("TOC entry %d @ %p\n" 
-           "    iv_id       = 0x%08x\n"
-           "    iv_data     = 0x%08x\n"
-           "    iv_type     = %s\n"
-           "    iv_section  = 0x%02x\n"
-           "    iv_elements = %d\n",
-           index, toc, 
-           xipRevLe32(toc->iv_id), 
-           xipRevLe32(toc->iv_data), 
-           SBE_XIP_TYPE_STRING(type_strings, toc->iv_type), 
-           toc->iv_section, 
-           toc->iv_elements);
-}
-
-#endif
-
-#if 0
-
-XIP_STATIC void
-dumpItem(SbeXipItem* item)
-{
-    printf("SbeXipItem @ %p\n"
-           "    iv_toc       = %p\n"
-           "    iv_address   = " F0x016llx "\n"
-           "    iv_imageData = %p\n"
-           "    iv_id        = %s\n"
-           "    iv_type      = %s\n"
-           "    iv_elements  = %d\n",
-           item,
-           item->iv_toc,
-           item->iv_address,
-           item->iv_imageData,
-           item->iv_id,
-           SBE_XIP_TYPE_STRING(type_strings, item->iv_type),
-           item->iv_elements);
-    dumpToc(-1, item->iv_toc);
-}
-
-#endif  /* 0 */
-
-XIP_STATIC void
-dumpSectionTable(const void* i_image)
-{
-    int i, rc;
-    SbeXipSection section;
-
-    printf("Section table dump of image @ %p\n"
-           "  Entry    Offset        Size\n"
-           "-------------------------------\n",
-           i_image);
-
-    for (i = 0; i < SBE_XIP_SECTIONS; i++) {
-        rc = sbe_xip_get_section(i_image, i, &section);
-        if (rc) {
-            printf(">>> dumpSectionTable got error at entry %d : %s\n",
-                   i, SBE_XIP_ERROR_STRING(sbe_xip_error_strings, rc));
-            break;
-        }
-        printf("%7d  0x%08x  0x%08x\n",
-               i, section.iv_offset, section.iv_size);
-    }
-}
-          
-#else
-
-#define TRACE_ERROR(x) (x)
-#define TRACE_ERRORX(x, ...) (x)
-#define dumpToc(...)
-#define dumpItem(...)
-#define dumpSectionTable(...)
-
-#endif
-
-
-// Note: For maximum flexibility we provide private versions of
-// endian-conversion routines rather than counting on a system-specific header
-// to provide these. 
-
-/// Byte-reverse a 16-bit integer if on a little-endian machine
-
-XIP_STATIC uint16_t
-xipRevLe16(const uint16_t i_x)
-{
-    uint16_t rx;
-
-#ifndef _BIG_ENDIAN
-    uint8_t *pix = (uint8_t*)(&i_x);
-    uint8_t *prx = (uint8_t*)(&rx);
-
-    prx[0] = pix[1];
-    prx[1] = pix[0];
-#else
-    rx = i_x;
-#endif
-
-    return rx;
-}
-
-
-/// Byte-reverse a 32-bit integer if on a little-endian machine
-
-XIP_STATIC uint32_t
-xipRevLe32(const uint32_t i_x)
-{
-    uint32_t rx;
-
-#ifndef _BIG_ENDIAN
-    uint8_t *pix = (uint8_t*)(&i_x);
-    uint8_t *prx = (uint8_t*)(&rx);
-
-    prx[0] = pix[3];
-    prx[1] = pix[2];
-    prx[2] = pix[1];
-    prx[3] = pix[0];
-#else
-    rx = i_x;
-#endif
-
-    return rx;
-}
-
-
-/// Byte-reverse a 64-bit integer if on a little-endian machine
-
-XIP_STATIC uint64_t
-xipRevLe64(const uint64_t i_x)
-{
-    uint64_t rx;
-
-#ifndef _BIG_ENDIAN
-    uint8_t *pix = (uint8_t*)(&i_x);
-    uint8_t *prx = (uint8_t*)(&rx);
-
-    prx[0] = pix[7];
-    prx[1] = pix[6];
-    prx[2] = pix[5];
-    prx[3] = pix[4];
-    prx[4] = pix[3];
-    prx[5] = pix[2];
-    prx[6] = pix[1];
-    prx[7] = pix[0];
-#else
-    rx = i_x;
-#endif
-
-    return rx;
-}
-
-
-/// What is the image link address?
-
-XIP_STATIC uint64_t
-xipLinkAddress(const void* i_image)
-{
-    return xipRevLe64(((SbeXipHeader*)i_image)->iv_linkAddress);
-}
-
-
-/// What is the image size?
-
-XIP_STATIC uint32_t
-xipImageSize(const void* i_image)
-{
-    return xipRevLe32(((SbeXipHeader*)i_image)->iv_imageSize);
-}
-
-
-/// Set the image size
-
-XIP_STATIC void
-xipSetImageSize(void* io_image, const size_t i_size)
-{
-    ((SbeXipHeader*)io_image)->iv_imageSize = xipRevLe32(i_size);
-}
-
-
-/// Re-establish the required final alignment
-
-XIP_STATIC void
-xipFinalAlignment(void* io_image)
-{
-    uint32_t size;
-
-    size = xipImageSize(io_image);
-
-    if ((size % SBE_XIP_FINAL_ALIGNMENT) != 0) {
-        xipSetImageSize(io_image, 
-                        size + (SBE_XIP_FINAL_ALIGNMENT -
-                                (size % SBE_XIP_FINAL_ALIGNMENT)));
-    }
-}
-
-
-/// Compute a host address from an image address and offset
-
-XIP_STATIC void*
-xipHostAddressFromOffset(const void* i_image, const uint32_t offset)
-{
-    return (void*)((unsigned long)i_image + offset);
-}
-
-
-/// Convert a PORE address to a host address
-
-XIP_STATIC void*
-xipPore2Host(const void* i_image, const uint64_t i_poreAddress)
-{
-    return xipHostAddressFromOffset(i_image, 
-                                    i_poreAddress - xipLinkAddress(i_image));
-}
-
-
-XIP_STATIC int
-xipValidatePoreAddress(const void* i_image, 
-                       const uint64_t i_poreAddress, 
-                       const uint32_t size)
-{
-    int rc;
-
-    if ((i_poreAddress < xipLinkAddress(i_image)) ||
-        (i_poreAddress > (xipLinkAddress(i_image) + 
-                          xipImageSize(i_image) - 
-                          size))) {
-        rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT,
-                          "The PORE address " F0x012llx 
-                          " is outside the bounds "
-                          "of the image (" 
-                          F0x012llx ":" F0x012llx 
-                          ") for %u-byte access.\n",
-                          i_poreAddress,
-                          xipLinkAddress(i_image),
-                          xipLinkAddress(i_image) + xipImageSize(i_image) - 1,
-                          size);
-    } else {
-        rc = 0;
-    }
-    return rc;
-}
-
-
-/// Get the magic number from the image
-
-XIP_STATIC uint64_t
-xipMagic(const void* i_image)
-{
-    return xipRevLe64(((SbeXipHeader*)i_image)->iv_magic);
-}
-
-
-/// Get the header version from the image
-
-XIP_STATIC uint8_t
-xipHeaderVersion(const void* i_image)
-{
-    return ((SbeXipHeader*)i_image)->iv_headerVersion;
-}
-
-
-/// Has the image been normalized?
-
-XIP_STATIC uint8_t
-xipNormalized(const void* i_image)
-{
-    return ((SbeXipHeader*)i_image)->iv_normalized;
-}
-
-
-/// Has the image TOC been sorted?
-
-XIP_STATIC uint8_t
-xipSorted(const void* i_image)
-{
-    return ((SbeXipHeader*)i_image)->iv_tocSorted;
-}
-
-
-/// A quick check that the image exists, has the correct magic and header
-/// version, and optionally is normalized.
-
-XIP_STATIC int 
-xipQuickCheck(const void* i_image, const int i_normalizationRequired)
-{
-    int rc;
-
-    do {
-        rc = 0;
-
-        if (i_image == 0) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, 
-                              "Image pointer is NULL (0)\n");
-            break;
-        }
-        if ((xipMagic(i_image) >> 32) != SBE_XIP_MAGIC) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "Magic number mismatch; Found "
-                              "" F0x016llx ", expected 0x%08x........\n",
-                              xipMagic(i_image), SBE_XIP_MAGIC);
-            break;
-        }
-        if ((xipHeaderVersion(i_image)) != SBE_XIP_HEADER_VERSION) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "Header version mismatch; Expecting %d, "
-                              "found %d\n",
-                              SBE_XIP_HEADER_VERSION, 
-                              xipHeaderVersion(i_image));
-            break;
-        }
-        if (i_normalizationRequired && !xipNormalized(i_image)) {
-            rc = TRACE_ERRORX(SBE_XIP_NOT_NORMALIZED,
-                              "Image not normalized\n");
-            break;
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-/// Convert a 32-bit relocatable offset to a full PORE 48-bit address
-
-XIP_STATIC uint64_t 
-xipFullAddress(const void* i_image, uint32_t offset)
-{
-    return (xipLinkAddress(i_image) & 0x0000ffff00000000ull) + offset;
-}
-
-
-/// Translate a section table entry
- 
-XIP_STATIC void
-xipTranslateSection(SbeXipSection* o_dest, const SbeXipSection* i_src)
-{
-#ifndef _BIG_ENDIAN
-
-#if SBE_XIP_HEADER_VERSION != 8
-#error This code assumes the SBE-XIP header version 8 layout
-#endif
-
-    o_dest->iv_offset = xipRevLe32(i_src->iv_offset);
-    o_dest->iv_size = xipRevLe32(i_src->iv_size);
-    o_dest->iv_alignment = i_src->iv_alignment;
-    o_dest->iv_reserved8[0] = 0;
-    o_dest->iv_reserved8[1] = 0;
-    o_dest->iv_reserved8[2] = 0;
-#else
-    if (o_dest != i_src) {
-        *o_dest = *i_src;
-    }
-#endif  /* _BIG_ENDIAN */
-}    
-
-
-/// Translate a TOC entry
-
-XIP_STATIC void
-xipTranslateToc(SbeXipToc* o_dest, SbeXipToc* i_src)
-{
-#ifndef _BIG_ENDIAN
-
-#if SBE_XIP_HEADER_VERSION != 8
-#error This code assumes the SBE-XIP header version 8 layout
-#endif
-
-    o_dest->iv_id = xipRevLe32(i_src->iv_id);
-    o_dest->iv_data = xipRevLe32(i_src->iv_data);
-    o_dest->iv_type = i_src->iv_type;
-    o_dest->iv_section = i_src->iv_section;
-    o_dest->iv_elements = i_src->iv_elements;
-    o_dest->iv_pad = 0;
-#else
-    if (o_dest != i_src) {
-        *o_dest = *i_src;
-    }
-#endif  /* _BIG_ENDIAN */
-}
-
-
-/// Find the final (highest-address) section of the image
-
-XIP_STATIC int
-xipFinalSection(const void* i_image, int* o_sectionId)
-{
-    int i, rc, found;
-    uint32_t offset;
-    SbeXipHeader hostHeader;
-    
-    sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image);
-
-    found = 0;
-    offset = 0;
-    *o_sectionId = 0;           /* Make GCC -O3 happy */
-    for (i = 0; i < SBE_XIP_SECTIONS; i++) {
-        if ((hostHeader.iv_section[i].iv_size != 0) && 
-            (hostHeader.iv_section[i].iv_offset >= offset)) {
-            *o_sectionId = i;
-            offset = hostHeader.iv_section[i].iv_offset;
-            found = 1;
-        }
-    }
-    if (!found) {
-        rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR, "The image is empty\n");
-    } else {
-        rc = 0;
-    }
-    return rc;
-}
-
-
-/// Return a pointer to an image-format section table entry
-
-XIP_STATIC int
-xipGetSectionPointer(const void* i_image,
-                     const int i_sectionId,
-                     SbeXipSection** o_imageSection)
-{
-    int rc;
-
-    if ((i_sectionId < 0) || (i_sectionId >= SBE_XIP_SECTIONS)) {
-        rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
-    } else {
-        *o_imageSection = 
-            &(((SbeXipHeader*)i_image)->iv_section[i_sectionId]);
-        rc = 0;
-    }
-    return rc;
-}
-
-
-/// Restore a section table entry from host format to image format.
-
-XIP_STATIC int
-xipPutSection(const void* i_image,
-              const int i_sectionId,
-              SbeXipSection* i_hostSection)
-{
-    int rc;
-    SbeXipSection *imageSection = NULL;
-
-    rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection);
-
-    if (!rc) {
-        xipTranslateSection(imageSection, i_hostSection);
-    }
-
-    return rc;
-}
-
-
-/// Set the offset of a section
-
-XIP_STATIC int
-xipSetSectionOffset(void* io_image, const int i_section, 
-                    const uint32_t i_offset)
-{
-    SbeXipSection* section = NULL;
-    int rc;
-
-    rc = xipGetSectionPointer(io_image, i_section, &section);
-    if (!rc) {
-        section->iv_offset = xipRevLe32(i_offset);
-    }
-    return rc;
-}
-
-
-/// Set the size of a section
-
-XIP_STATIC int
-xipSetSectionSize(void* io_image, const int i_section, const uint32_t i_size)
-{
-    SbeXipSection* section = NULL;
-    int rc;
-
-    rc = xipGetSectionPointer(io_image, i_section, &section);
-    if (!rc) {
-        section->iv_size = xipRevLe32(i_size);
-    }
-    return rc;
-}
-
-
-/// Translate a PORE address in the image to a section and offset
-
-// We first check to be sure that the PORE address is contained in the image,
-// using the full 48-bit form.  Then we scan the section table to see which
-// section contains the address - if none then the image is corrupted. We can
-// (must) use the 32-bit offset form of the address here.
-
-XIP_STATIC int
-xipPore2Section(const void* i_image, 
-                const uint64_t i_poreAddress,
-                int* o_section,
-                uint32_t* o_offset)
-{
-    int rc, sectionId;
-    SbeXipSection section;
-    uint32_t addressOffset;
-
-    do {
-        rc = 0;
-
-        if ((i_poreAddress < xipLinkAddress(i_image)) ||
-            (i_poreAddress > 
-             (xipLinkAddress(i_image) + xipImageSize(i_image)))) {
-            rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT,
-                              "pore2section: The i_poreAddress argument "
-                              "(" F0x016llx ")\nis outside the bounds of the "
-                              "image (" F0x016llx ":" F0x016llx ")\n",
-                              i_poreAddress,
-                              xipLinkAddress(i_image),
-                              xipLinkAddress(i_image) + xipImageSize(i_image));
-            break;
-        }
-
-        addressOffset = (i_poreAddress - xipLinkAddress(i_image)) & 0xffffffff;
-
-        for (sectionId = 0; sectionId < SBE_XIP_SECTIONS; sectionId++) {
-            rc = sbe_xip_get_section(i_image, sectionId, &section);
-            if (rc) {
-                rc = TRACE_ERROR(SBE_XIP_BUG); /* Can't happen */
-                break;
-            }
-            if ((section.iv_size != 0) &&
-                (addressOffset >= section.iv_offset) &&
-                (addressOffset < (section.iv_offset + section.iv_size))) {
-                break;
-            }
-        }
-        if (rc) break;
-
-        if (sectionId == SBE_XIP_SECTIONS) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "Error processing PORE address " F0x016llx ". "
-                              "The address is not mapped in any section.\n"
-                              "A section table dump appears below\n",
-                              i_poreAddress);
-            dumpSectionTable(i_image);
-            break;
-        }
-
-        *o_section = sectionId;
-        *o_offset = addressOffset - section.iv_offset;
-
-    } while(0);
-
-    return rc;
-}
-
-
-/// Get the information required to search the TOC.  
-///
-/// All return values are optional.
-
-XIP_STATIC int
-xipGetToc(void* i_image,
-          SbeXipToc** o_toc,
-          size_t* o_entries,
-          int* o_sorted,
-          char** o_strings)
-{
-    int rc;
-    SbeXipSection tocSection, stringsSection;
-
-    do {
-        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_TOC, &tocSection);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_STRINGS,
-                                 &stringsSection);
-        if (rc) break;
-
-        if (o_toc) {
-            *o_toc = (SbeXipToc*)((uint8_t*)i_image + tocSection.iv_offset);
-        }
-        if (o_entries) {
-            *o_entries = tocSection.iv_size / sizeof(SbeXipToc);
-        }
-        if (o_sorted) {
-            *o_sorted = xipSorted(i_image);
-        }
-        if (o_strings) {
-            *o_strings = (char*)i_image + stringsSection.iv_offset;
-        }
-    } while (0);
-    return rc;
-}
-
-
-/// Compare two normalized TOC entries for sorting.
-
-XIP_STATIC int
-xipCompareToc(const SbeXipToc* i_a, const SbeXipToc* i_b, 
-              const char* i_strings)
-{
-    return strcmp(i_strings + xipRevLe32(i_a->iv_id),
-                  i_strings + xipRevLe32(i_b->iv_id));
-}
-
-
-/// Iterative quicksort of the TOC
-
-// Note: The stack requirement is limited to 256 bytes + minor local storage.
-
-XIP_STATIC void
-xipQuickSort(SbeXipToc* io_toc, int i_left, int i_right,
-             const char* i_strings)
-{
-    int i, j, left, right, sp;
-    SbeXipToc pivot, temp;
-    uint32_t stack[64];
-
-    sp = 0;
-    stack[sp++] = i_left;
-    stack[sp++] = i_right;
-
-    while (sp) {
-
-        right = stack[--sp];
-        left = stack[--sp];
-
-        i = left;
-        j = right;
-
-        pivot = io_toc[(i + j) / 2];
-
-        while (i <= j) {
-            while (xipCompareToc(&(io_toc[i]), &pivot, i_strings) < 0) {
-                i++;
-            }
-            while (xipCompareToc(&(io_toc[j]), &pivot, i_strings) > 0) {
-                j--;
-            }
-            if (i <= j) {
-                temp = io_toc[i];
-                io_toc[i] = io_toc[j];
-                io_toc[j] = temp;
-                i++;
-                j--;
-            }
-        }
-        if (left < j) {
-            stack[sp++] = left;
-            stack[sp++] = j;
-        }
-        if (i < right) {
-            stack[sp++] = i;
-            stack[sp++] = right;
-        }
-    }
-}
-
-
-/// TOC linear search
-
-XIP_STATIC int
-xipLinearSearch(void* i_image, const char* i_id, SbeXipToc** o_entry)
-{
-    int rc;
-    SbeXipToc *imageToc, hostToc;
-    size_t entries;
-    char* strings;
-
-    *o_entry = 0;
-    rc = xipGetToc(i_image, &imageToc, &entries, 0, &strings);
-    if (!rc) {
-        for (; entries; entries--, imageToc++) {
-            xipTranslateToc(&hostToc, imageToc);
-            if (strcmp(i_id, strings + hostToc.iv_id) == 0) {
-                break;
-            }
-        }
-        if (entries) {
-            *o_entry = imageToc;
-            rc = 0;
-        } else {
-            *o_entry = 0;
-            rc = TRACE_ERROR(SBE_XIP_ITEM_NOT_FOUND);
-        }
-    }
-    return rc;
-}
-
-
-/// A classic binary search of a (presumed) sorted array
-
-XIP_STATIC int
-xipBinarySearch(void* i_image, const char* i_id, SbeXipToc** o_entry)
-{
-    int rc;
-    SbeXipToc *imageToc;
-    size_t entries;
-    char* strings;
-    int sorted, left, right, next, sort;
-
-    do {
-        *o_entry = 0;
-
-        rc = xipGetToc(i_image, &imageToc, &entries, &sorted, &strings);
-        if (rc) break;
-
-        if (!sorted) {
-            rc = TRACE_ERROR(SBE_XIP_BUG);
-            break;
-        }
-
-        left = 0;
-        right = entries - 1;
-        while (left <= right) {
-            next = (left + right) / 2;
-            sort = strcmp(i_id, strings + xipRevLe32(imageToc[next].iv_id));
-            if (sort == 0) {
-                *o_entry = &(imageToc[next]);
-                break;
-            } else if (sort < 0) {
-                right = next - 1;
-            } else {
-                left = next + 1;
-            }
-        }
-        if (*o_entry == 0) {
-            rc = TRACE_ERROR(SBE_XIP_ITEM_NOT_FOUND);
-            break;
-        }
-    } while (0);
-    return rc;
-}
-
-
-/// Validate a TOC entry as a mapping function
-///
-/// The TOC is validated by searching for the entry, which will uncover
-/// duplicate entries or problems with sorting/searching.
-
-XIP_STATIC int
-xipValidateTocEntry(void* io_image, const SbeXipItem* i_item, void* io_arg)
-{
-    int rc;
-    SbeXipItem found;
-
-    do {
-        rc = sbe_xip_find(io_image, i_item->iv_id, &found);
-        if (rc) {
-            rc = TRACE_ERRORX(rc, "TOC entry for %s not found\n", 
-                              i_item->iv_id);
-        } else if (found.iv_toc != i_item->iv_toc) {
-            rc = TRACE_ERRORX(SBE_XIP_TOC_ERROR,
-                              "Duplicate TOC entry for '%s'\n", i_item->iv_id);
-        }
-        break;
-    } while (0);
-    return rc;
-}
-    
-
-// This is the FNV-1a hash, used for hashing symbol names in the .fixed
-// section into 32-bit hashes for the mini-TOC.
-
-// According to the authors:
-
-// "FNV hash algorithms and source code have been released into the public
-// domain. The authors of the FNV algorithmm look deliberate steps to disclose
-// the algorhtm (sic) in a public forum soon after it was invented. More than
-// a year passed after this public disclosure and the authors deliberatly took
-// no steps to patent the FNV algorithm. Therefore it is safe to say that the
-// FNV authors have no patent claims on the FNV algorithm as published."
-
-#define FNV_OFFSET_BASIS 2166136261u
-#define FNV_PRIME32 16777619u
-
-uint32_t
-xipHash32(const char* s) 
-{
-    uint32_t hash;
-
-    hash = FNV_OFFSET_BASIS;
-    while (*s) {
-        hash ^= *s++;
-        hash *= FNV_PRIME32;
-    }
-    return hash;
-}
-
-
-// Normalize a TOC entry
-
-// Normalize the TOC entry by converting relocatable pointers into 32-bit
-// offsets from the beginning of the section containing the data. All
-// addresses in the TOC are actually 32-bit offsets in the address space named
-// in bits 16:31 of the link address of the image.
-
-XIP_STATIC int
-xipNormalizeToc(void* io_image, SbeXipToc *io_imageToc,
-                SbeXipHashedToc** io_fixedTocEntry,
-                size_t* io_fixedEntriesRemaining)
-{
-    SbeXipToc hostToc;
-    int idSection, dataSection;
-    uint32_t idOffset, dataOffset;
-    char* hostString;
-    int rc;
-
-    do {
-
-        // Translate the TOC entry to host format.  Then locate the
-        // sections/offsets of the Id string (which must be in .strings) and
-        // the data.
-
-        xipTranslateToc(&hostToc, io_imageToc);
-
-        hostString = 
-            (char*)xipPore2Host(io_image, 
-                                xipFullAddress(io_image, hostToc.iv_id));
-
-        rc = xipPore2Section(io_image,
-                             xipFullAddress(io_image, hostToc.iv_id),
-                             &idSection,
-                             &idOffset);
-        if (rc) break;
-
-        if (idSection != SBE_XIP_SECTION_STRINGS) {
-            rc = TRACE_ERROR(SBE_XIP_IMAGE_ERROR);
-            break;
-        }
-
-        rc = xipPore2Section(io_image,
-                             xipFullAddress(io_image, hostToc.iv_data),
-                             &dataSection,
-                             &dataOffset);
-        if (rc) break;
-
-        // Now replace the Id and data pointers with their offsets, and update
-        // the data section in the TOC entry.
-
-        hostToc.iv_id = idOffset;
-        hostToc.iv_data = dataOffset;
-        hostToc.iv_section = dataSection;
-
-        // If this TOC entry is from .fixed, create a new record in .fixed_toc
-
-        if (hostToc.iv_section == SBE_XIP_SECTION_FIXED) {
-
-            if (*io_fixedEntriesRemaining == 0) {
-                rc = TRACE_ERRORX(SBE_XIP_TOC_ERROR,
-                                  "Too many TOC entries for .fixed\n");
-                break;
-            }
-            if (hostToc.iv_data != (uint16_t)hostToc.iv_data) {
-                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                                  "The .fixed section is too big to index\n");
-                break;
-            }
-
-            (*io_fixedTocEntry)->iv_hash = xipRevLe32(xipHash32(hostString));
-            (*io_fixedTocEntry)->iv_offset = xipRevLe16(hostToc.iv_data);
-            (*io_fixedTocEntry)->iv_type = hostToc.iv_type;
-            (*io_fixedTocEntry)->iv_elements = hostToc.iv_elements;
-            
-            (*io_fixedTocEntry)++;
-            (*io_fixedEntriesRemaining)--;
-        }            
-
-        // Finally update the TOC entry
-
-        xipTranslateToc(io_imageToc, &hostToc);
-
-    } while (0);
-
-    return rc;
-}
-
-
-// Check for hash collisions in the .fixed mini-TOC.  Note that endianness is
-// not an issue here, as we're comparing for equality.
-
-XIP_STATIC int
-xipHashCollision(SbeXipHashedToc* i_fixedToc, size_t i_entries)
-{
-    int rc;
-    size_t i, j;
-
-    rc = 0;
-
-    for (i = 0; i < i_entries; i++) {
-        for (j = i + 1; j < i_entries; j++) {
-            if (i_fixedToc[i].iv_hash == i_fixedToc[j].iv_hash) {
-                rc = TRACE_ERRORX(SBE_XIP_HASH_COLLISION,
-                                  "Hash collision at index %zd\n",
-                                  i);
-                break;
-            }
-        }
-        if (rc) break;
-    }
-    
-    return rc;
-}
-
-
-/// Decode a normalized image-format TOC entry into a host-format SbeXipItem
-/// structure
-
-XIP_STATIC int
-xipDecodeToc(void* i_image, 
-             SbeXipToc* i_imageToc, 
-             SbeXipItem* o_item)
-{
-    int rc;
-    SbeXipToc hostToc;
-    SbeXipSection dataSection, stringsSection;
-
-    do {
-        if (!xipNormalized(i_image)) {
-            rc = TRACE_ERROR(SBE_XIP_NOT_NORMALIZED);
-            break;
-        }
-
-
-        // Translate the TOC entry and set the TOC pointer, data type and
-        // number of elements in the outgoing structure. The Id string is
-        // always located in the TOC_STRINGS section.
-
-        xipTranslateToc(&hostToc, i_imageToc);
-
-        o_item->iv_toc = i_imageToc;
-        o_item->iv_type = hostToc.iv_type;
-        o_item->iv_elements = hostToc.iv_elements;
-    
-        sbe_xip_get_section(i_image, SBE_XIP_SECTION_STRINGS, &stringsSection);
-        o_item->iv_id = 
-            (char*)i_image + stringsSection.iv_offset + hostToc.iv_id;
-        
-
-        // The data (or text address) are addressed by relative offsets from
-        // the beginning of their section.  The TOC entry may remain in the TOC
-        // even though the section has been removed from the image, so this
-        // case needs to be covered. 
-        
-        rc = sbe_xip_get_section(i_image, hostToc.iv_section, &dataSection);
-        if (rc) break;
-
-        if (dataSection.iv_size == 0) {
-            rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT);
-            break;
-        }
-
-        o_item->iv_imageData = 
-            (void*)((uint8_t*)i_image + 
-                    dataSection.iv_offset + hostToc.iv_data);
-
-        o_item->iv_address = 
-            xipLinkAddress(i_image) + dataSection.iv_offset + hostToc.iv_data;
-
-        o_item->iv_partial = 0;
-            
-    } while (0);
-    return rc;
-}    
-
-
-/// Sort the TOC
-
-XIP_STATIC int
-xipSortToc(void* io_image)
-{
-    int rc;
-    SbeXipToc *hostToc;
-    size_t entries;
-    char* strings;
-
-    do {
-        rc = xipQuickCheck(io_image, 1);
-        if (rc) break;
-
-        if (xipSorted(io_image)) break;
-
-        rc = xipGetToc(io_image, &hostToc, &entries, 0, &strings);
-        if (rc) break;
-
-        xipQuickSort(hostToc, 0, entries - 1, strings);
-
-        ((SbeXipHeader*)io_image)->iv_tocSorted = 1;
-        
-    } while (0);
-
-    return rc;
-}
-
-
-// Pad the image with 0 to a given power-of-2 alignment.  The image size is
-// modified to reflect the pad, but the caller must modify the section size to
-// reflect the pad.
-
-XIP_STATIC int
-xipPadImage(void* io_image, uint32_t i_allocation, 
-            uint32_t i_align, uint32_t* pad)
-{
-    int rc;
-
-    do {
-        rc = 0;
-
-        if ((i_align == 0) || ((i_align & (i_align - 1)) != 0)) {
-            rc = TRACE_ERRORX(SBE_XIP_INVALID_ARGUMENT,
-                              "Alignment specification (%u) "
-                              "not a power-of-2\n",
-                              i_align);
-            break;
-        }
-
-        *pad = xipImageSize(io_image) % i_align;
-        if (*pad != 0) {
-            *pad = i_align - *pad;
-
-            if ((xipImageSize(io_image) + *pad) > i_allocation) {
-                rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW);
-                break;
-            }
-
-            memset((void*)((unsigned long)io_image + xipImageSize(io_image)), 
-                   0, *pad);
-            xipSetImageSize(io_image, xipImageSize(io_image) + *pad);
-        }
-    } while (0);
-
-    return rc;
-}
-
-
-//  Get the .fixed_toc section
-
-XIP_STATIC int
-xipGetFixedToc(void* io_image, 
-               SbeXipHashedToc** o_imageToc, 
-               size_t* o_entries)
-{
-    int rc;
-    SbeXipSection section;
-
-    rc = sbe_xip_get_section(io_image, SBE_XIP_SECTION_FIXED_TOC, &section);
-    if (!rc) {
-
-        *o_imageToc = 
-            (SbeXipHashedToc*)((unsigned long)io_image + section.iv_offset);  
-
-        *o_entries = section.iv_size / sizeof(SbeXipHashedToc);
-    }
-
-    return rc;
-}
-
-
-// Search for an item in the fixed TOC, and populate a partial TOC entry if
-// requested. This table is small and unsorted so a linear search is
-// adequate. The TOC structures are also small so all byte-reversal is done
-// 'by hand' rather than with a translate-type API.
-
-XIP_STATIC int
-xipFixedFind(void* i_image, const char* i_id, SbeXipItem* o_item)
-{
-    int rc;
-    SbeXipHashedToc* toc;
-    size_t entries;
-    uint32_t hash;
-    SbeXipSection fixedSection;
-    uint32_t offset;
-
-    do {
-        rc = xipGetFixedToc(i_image, &toc, &entries);
-        if (rc) break;
-
-        for (hash = xipRevLe32(xipHash32(i_id)); entries != 0; entries--, toc++) {
-            if (toc->iv_hash == hash) break;
-        }
-
-        if (entries == 0) {
-            rc = SBE_XIP_ITEM_NOT_FOUND;
-            break;
-        } else {
-            rc = 0;
-        }
-
-        // The caller may have requested a lookup only (o_item == 0), in which
-        // case we're done.  Otherwise we create a partial SbeXipItem and
-        // populate the non-0 fields analogously to the xipDecodeToc()
-        // routine. The data resides in the .fixed section in this case.
-
-        if (o_item == 0) break;
-
-        o_item->iv_partial = 1;
-        o_item->iv_toc = 0;
-        o_item->iv_id = 0;
-
-        o_item->iv_type = toc->iv_type;
-        o_item->iv_elements = toc->iv_elements;
-
-        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_FIXED, &fixedSection);
-        if (rc) break;
-
-        if (fixedSection.iv_size == 0) {
-            rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT);
-            break;
-        }
-
-        offset = fixedSection.iv_offset + xipRevLe16(toc->iv_offset);
-
-        o_item->iv_imageData = (void*)((uint8_t*)i_image + offset);
-        o_item->iv_address = xipLinkAddress(i_image) + offset;
-
-    } while (0);
-
-    return rc;
-}
-
-
-// Search for an item in the special built-in TOC of header fields, and
-// populate a partial TOC entry if requested. 
-//
-// This facility was added to allow header data to be searched by name even
-// when the TOC has been stripped. This API will only be used in the case of a
-// stripped TOC since the header fields are also indexed in the main TOC.
-//
-// The table is allocated on the stack in order to make this code concurrently
-// patchable in PHYP (although PHYP applications will never use this code).
-// The table is small and unsorted so a linear search is adequate, and the
-// stack requirememts are small.
-
-XIP_STATIC int
-xipHeaderFind(void* i_image, const char* i_id, SbeXipItem* o_item)
-{
-    int rc;
-    unsigned i;
-    uint32_t offset;
-    SbeXipSection headerSection;
-
-#define HEADER_TOC(id, field, type)             \
-    {#id, offsetof(SbeXipHeader, field), type}
-
-    struct HeaderToc {
-
-        const char* iv_id;
-        uint16_t iv_offset;
-        uint8_t iv_type;
-
-    } toc[] = {
-
-        HEADER_TOC(magic,        iv_magic,       SBE_XIP_UINT64),
-        HEADER_TOC(entry_offset, iv_entryOffset, SBE_XIP_UINT64),
-        HEADER_TOC(link_address, iv_linkAddress, SBE_XIP_UINT64),
-
-        HEADER_TOC(image_size, iv_imageSize, SBE_XIP_UINT32),
-        HEADER_TOC(build_date, iv_buildDate, SBE_XIP_UINT32),
-        HEADER_TOC(build_time, iv_buildTime, SBE_XIP_UINT32),
-
-        HEADER_TOC(header_version, iv_headerVersion, SBE_XIP_UINT8),
-        HEADER_TOC(toc_normalized, iv_normalized,    SBE_XIP_UINT8),
-        HEADER_TOC(toc_sorted,     iv_tocSorted,     SBE_XIP_UINT8),
-
-        HEADER_TOC(build_user, iv_buildUser, SBE_XIP_STRING),
-        HEADER_TOC(build_host, iv_buildHost, SBE_XIP_STRING),
-
-    };
-
-    do {
-
-        rc = SBE_XIP_ITEM_NOT_FOUND;
-        for (i = 0; i < (sizeof(toc) / sizeof(struct HeaderToc)); i++) {
-            if (strcmp(i_id, toc[i].iv_id) == 0) {
-                rc = 0;
-                break;
-            }
-        }
-
-        if (rc) break;
-
-        // The caller may have requested a lookup only (o_item == 0), in which
-        // case we're done.  Otherwise we create a partial SbeXipItem and
-        // populate the non-0 fields analogously to the xipDecodeToc()
-        // routine. The data resides in the .fixed section in this case.
-
-        if (o_item == 0) break;
-
-        o_item->iv_partial = 1;
-        o_item->iv_toc = 0;
-        o_item->iv_id = 0;
-
-        o_item->iv_type = toc[i].iv_type;
-        o_item->iv_elements = 1; /* True for now... */
-
-        rc = sbe_xip_get_section(i_image, SBE_XIP_SECTION_HEADER, 
-                                 &headerSection);
-        if (rc) break;
-
-        if (headerSection.iv_size == 0) {
-            rc = TRACE_ERROR(SBE_XIP_DATA_NOT_PRESENT);
-            break;
-        }
-
-        offset = headerSection.iv_offset + toc[i].iv_offset;
-
-        o_item->iv_imageData = (void*)((uint8_t*)i_image + offset);
-        o_item->iv_address = xipLinkAddress(i_image) + offset;
-
-    } while (0);
-
-    return rc;
-}
-        
-
-////////////////////////////////////////////////////////////////////////////
-// Published API
-////////////////////////////////////////////////////////////////////////////
-
-int
-sbe_xip_validate(void* i_image, const uint32_t i_size)
-{          
-    SbeXipHeader hostHeader;
-    int rc = 0, i;
-    uint32_t linkAddress, imageSize, extent, offset, size;
-    uint8_t alignment;
-
-    sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image);
-
-    do {
-        
-        // Validate C/Assembler constraints.
-
-        if (sizeof(SbeXipSection) != SIZE_OF_SBE_XIP_SECTION) {
-            rc = TRACE_ERRORX(SBE_XIP_BUG,
-                              "C/Assembler size mismatch(%zd/%d) "
-                              "for SbeXipSection\n",
-                              sizeof(SbeXipSection), SIZE_OF_SBE_XIP_SECTION);
-            break;
-        }
-                              
-        if (sizeof(SbeXipToc) != SIZE_OF_SBE_XIP_TOC) {
-            rc = TRACE_ERRORX(SBE_XIP_BUG,
-                              "C/Assembler size mismatch(%zd/%d) "
-                              "for SbeXipToc\n",
-                              sizeof(SbeXipToc), SIZE_OF_SBE_XIP_TOC);
-            break;
-        }
-
-        if (sizeof(SbeXipHashedToc) != SIZE_OF_SBE_XIP_HASHED_TOC) {
-            rc = TRACE_ERRORX(SBE_XIP_BUG,
-                              "C/Assembler size mismatch(%zd/%d) "
-                              "for SbeXipHashedToc\n",
-                              sizeof(SbeXipHashedToc), 
-                              SIZE_OF_SBE_XIP_HASHED_TOC);
-            break;
-        }
-
-        // Validate the image pointer and magic number
-
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        // Validate the image size
-
-        linkAddress = hostHeader.iv_linkAddress;
-        imageSize = hostHeader.iv_imageSize;
-        extent = linkAddress + imageSize;
-
-        if (imageSize < sizeof(SbeXipHeader)) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "sbe_xip_validate(%p, %u) : "
-                              "The image size recorded in the image "
-                              "(%u) is smaller than the header size.\n",
-                              i_image, i_size, imageSize);
-            break;
-        }
-        if (imageSize != i_size) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "sbe_xip_validate(%p, %u) : "
-                              "The image size recorded in the image "
-                              "(%u) does not match the i_size parameter.\n",
-                              i_image, i_size, imageSize);
-            break;
-        }
-        if (extent <= linkAddress) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "sbe_xip_validate(%p, %u) : "
-                              "Given the link address (%u) and the "
-                              "image size, the image wraps the address space\n",
-                              i_image, i_size, linkAddress);
-            break;
-        }
-        if ((imageSize % SBE_XIP_FINAL_ALIGNMENT) != 0) {
-            rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
-                              "sbe_xip_validate(%p, %u) : "
-                              "The image size (%u) is not a multiple of %u\n",
-                              i_image, i_size, imageSize, 
-                              SBE_XIP_FINAL_ALIGNMENT);
-            break;
-        }
-
-        // Validate that all sections appear to be within the image
-        // bounds, and are aligned correctly.
-
-        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
-
-            offset = hostHeader.iv_section[i].iv_offset;
-            size = hostHeader.iv_section[i].iv_size;
-            alignment = hostHeader.iv_section[i].iv_alignment;
-
-            if ((offset > imageSize) || 
-                ((offset + size) > imageSize) ||
-                ((offset + size) < offset)) {
-                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                                  "Section %d does not appear to be within "
-                                  "the bounds of the image\n"
-                                  "offset = %u, size = %u, image size = %u\n",
-                                  i, offset, size, imageSize);
-                break;
-            }
-            if ((offset % alignment) != 0) {
-                rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
-                                  "Section %d requires %d-byte initial "
-                                  "alignment but the section offset is %u\n",
-                                  i, alignment, offset);
-                break;
-            }
-        }
-        if (rc) break;
-
-        // If the TOC exists and the image is normalized, validate each TOC
-        // entry. 
-
-        size = hostHeader.iv_section[SBE_XIP_SECTION_TOC].iv_size; 
-        if (size != 0) {
-            if (xipNormalized(i_image)) {
-                rc = sbe_xip_map_toc(i_image, xipValidateTocEntry, 0);
-                if (rc) break;
-            }
-        }
-    } while (0);
-    return rc;
-}
-
-
-int
-sbe_xip_validate2(void* i_image, const uint32_t i_size, const uint32_t i_maskIgnores)
-{          
-    SbeXipHeader hostHeader;
-    int rc = 0, i;
-    uint32_t linkAddress, imageSize, extent, offset, size;
-    uint8_t alignment;
-
-    sbe_xip_translate_header(&hostHeader, (SbeXipHeader*)i_image);
-
-    do {
-        
-        // Validate C/Assembler constraints.
-
-        if (sizeof(SbeXipSection) != SIZE_OF_SBE_XIP_SECTION) {
-            rc = TRACE_ERRORX(SBE_XIP_BUG,
-                              "C/Assembler size mismatch(%zd/%d) "
-                              "for SbeXipSection\n",
-                              sizeof(SbeXipSection), SIZE_OF_SBE_XIP_SECTION);
-            break;
-        }
-                              
-        if (sizeof(SbeXipToc) != SIZE_OF_SBE_XIP_TOC) {
-            rc = TRACE_ERRORX(SBE_XIP_BUG,
-                              "C/Assembler size mismatch(%zd/%d) "
-                              "for SbeXipToc\n",
-                              sizeof(SbeXipToc), SIZE_OF_SBE_XIP_TOC);
-            break;
-        }
-
-        if (sizeof(SbeXipHashedToc) != SIZE_OF_SBE_XIP_HASHED_TOC) {
-            rc = TRACE_ERRORX(SBE_XIP_BUG,
-                              "C/Assembler size mismatch(%zd/%d) "
-                              "for SbeXipHashedToc\n",
-                              sizeof(SbeXipHashedToc), 
-                              SIZE_OF_SBE_XIP_HASHED_TOC);
-            break;
-        }
-
-        // Validate the image pointer and magic number
-
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        // Validate the image size
-
-        linkAddress = hostHeader.iv_linkAddress;
-        imageSize = hostHeader.iv_imageSize;
-        extent = linkAddress + imageSize;
-
-        if (imageSize < sizeof(SbeXipHeader)) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "sbe_xip_validate2(%p, %u) : "
-                              "The image size recorded in the image "
-                              "(%u) is smaller than the header size.\n",
-                              i_image, i_size, imageSize);
-            break;
-        }
-        if (imageSize != i_size && !(i_maskIgnores & SBE_XIP_IGNORE_FILE_SIZE)) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "sbe_xip_validate2(%p, %u) : "
-                              "The image size recorded in the image "
-                              "(%u) does not match the i_size parameter.\n",
-                              i_image, i_size, imageSize);
-            break;
-        }
-        if (extent <= linkAddress) {
-            rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                              "sbe_xip_validate2(%p, %u) : "
-                              "Given the link address (%u) and the "
-                              "image size, the image wraps the address space\n",
-                              i_image, i_size, linkAddress);
-            break;
-        }
-        if ((imageSize % SBE_XIP_FINAL_ALIGNMENT) != 0) {
-            rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
-                              "sbe_xip_validate2(%p, %u) : "
-                              "The image size (%u) is not a multiple of %u\n",
-                              i_image, i_size, imageSize, 
-                              SBE_XIP_FINAL_ALIGNMENT);
-            break;
-        }
-
-        // Validate that all sections appear to be within the image
-        // bounds, and are aligned correctly.
-
-        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
-
-            offset = hostHeader.iv_section[i].iv_offset;
-            size = hostHeader.iv_section[i].iv_size;
-            alignment = hostHeader.iv_section[i].iv_alignment;
-
-            if ((offset > imageSize) || 
-                ((offset + size) > imageSize) ||
-                ((offset + size) < offset)) {
-                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                                  "Section %d does not appear to be within "
-                                  "the bounds of the image\n"
-                                  "offset = %u, size = %u, image size = %u\n",
-                                  i, offset, size, imageSize);
-                break;
-            }
-            if ((offset % alignment) != 0) {
-                rc = TRACE_ERRORX(SBE_XIP_ALIGNMENT_ERROR,
-                                  "Section %d requires %d-byte initial "
-                                  "alignment but the section offset is %u\n",
-                                  i, alignment, offset);
-                break;
-            }
-        }
-        if (rc) break;
-
-        // If the TOC exists and the image is normalized, validate each TOC
-        // entry. 
-
-        size = hostHeader.iv_section[SBE_XIP_SECTION_TOC].iv_size; 
-        if (size != 0) {
-            if (xipNormalized(i_image)) {
-                rc = sbe_xip_map_toc(i_image, xipValidateTocEntry, 0);
-                if (rc) break;
-            }
-        }
-    } while (0);
-    return rc;
-}
-
-
-// Normalization:
-//
-// 1. Normalize the TOC, unless the image is already normalized.  The image
-// must be marked as normalized before sorting.
-//
-// 2. Sort the TOC.
-//
-// 3. Clear the section offsets of any empty sections to make the section
-// table reports less confusing.
-//
-// 4. Clear normalization status on any failure.
-
-int
-sbe_xip_normalize(void* io_image)
-{
-    int rc, i;
-    SbeXipSection section;
-    SbeXipToc* imageToc;
-    SbeXipHashedToc* fixedImageToc;
-    SbeXipHashedToc* fixedTocEntry;
-    size_t tocEntries, fixedTocEntries, fixedEntriesRemaining;
-       
-    do {
-        rc = xipQuickCheck(io_image, 0);
-        if (rc) break;
-
-        if (!xipNormalized(io_image)) {
-
-            rc = xipGetToc(io_image, &imageToc, &tocEntries, 0, 0);
-            if (rc) break;
-
-            rc = xipGetFixedToc(io_image, &fixedImageToc, &fixedTocEntries);
-            if (rc) break;
-
-            fixedTocEntry = fixedImageToc;
-            fixedEntriesRemaining = fixedTocEntries;
-
-            for (; tocEntries--; imageToc++) {
-                rc = xipNormalizeToc(io_image, imageToc, 
-                                     &fixedTocEntry, &fixedEntriesRemaining);
-                if (rc) break;
-                                  
-            }
-            if (rc) break;
-
-            if (fixedEntriesRemaining != 0) {
-                rc = TRACE_ERRORX(SBE_XIP_TOC_ERROR,
-                                  "Not enough TOC entries for .fixed");
-                break;
-            }
-
-            rc = xipHashCollision(fixedImageToc, fixedTocEntries);
-            if (rc) break;
-
-            ((SbeXipHeader*)io_image)->iv_normalized = 1;
-        }
-
-        rc = xipSortToc(io_image);
-        if (rc) break;
-
-        for (i = 0; i < SBE_XIP_SECTIONS; i++) {
-            rc = sbe_xip_get_section(io_image, i, &section);
-            if (rc) break;
-            if (section.iv_size == 0) {
-                xipSetSectionOffset(io_image, i, 0);
-            }
-        }
-        if (rc) break;
-
-    } while(0);
-
-    ((SbeXipHeader*)io_image)->iv_normalized = (rc == 0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_image_size(void* io_image, uint32_t* o_size)
-{
-    int rc;
-
-    rc = xipQuickCheck(io_image, 0);
-    if (!rc) {
-        *o_size = xipImageSize(io_image);
-    }
-    return rc;
-}
-
-
-int
-sbe_xip_get_section(const void* i_image,
-                    const int i_sectionId,
-                    SbeXipSection* o_hostSection)
-{
-    int rc;
-    SbeXipSection *imageSection = NULL;
-
-    rc = xipGetSectionPointer(i_image, i_sectionId, &imageSection);
-
-    if (!rc) {
-        xipTranslateSection(o_hostSection, imageSection);
-    }
-
-    return rc;
-}
-
-
-// If the 'big' TOC is not present, search the mini-TOCs that only index the
-// .fixed and .header sections.
-
-int
-sbe_xip_find(void* i_image, 
-             const char* i_id,
-             SbeXipItem* o_item)
-{
-    int rc;
-    SbeXipToc* toc;
-    SbeXipItem item, *pitem;
-    SbeXipSection* tocSection;
-
-    do {
-        rc = xipQuickCheck(i_image, 1);
-        if (rc) break;
-
-        rc = xipGetSectionPointer(i_image, SBE_XIP_SECTION_TOC, &tocSection);
-        if (rc) break;
-
-        if (tocSection->iv_size == 0) {
-            rc = xipFixedFind(i_image, i_id, o_item);
-            if (rc) {
-                rc = xipHeaderFind(i_image, i_id, o_item);
-            }
-            break;
-        }
-
-        if (xipSorted(i_image)) {
-            rc = xipBinarySearch(i_image, i_id, &toc);
-        } else {
-            rc = xipLinearSearch(i_image, i_id, &toc);
-        }
-        if (rc) break;
-
-        if (o_item) {
-            pitem = o_item;
-        } else {
-            pitem = &item;
-        }
-        rc = xipDecodeToc(i_image, toc, pitem);
-        if (rc) break;
-
-    } while (0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_map_halt(void* io_image, 
-                 int (*i_fn)(void* io_image, 
-                             const uint64_t i_poreAddress,
-                             const char* i_rcString,
-                             void* io_arg),
-                 void* io_arg)
-{
-    int rc;
-    SbeXipSection haltSection;
-    SbeXipHalt *halt;
-    uint32_t size;
-    uint32_t actualSize;
-
-    do {
-        rc = xipQuickCheck(io_image, 0);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(io_image, SBE_XIP_SECTION_HALT, &haltSection);
-        if (rc) break;
-
-        halt = (SbeXipHalt*)((unsigned long)io_image + haltSection.iv_offset);
-        size = haltSection.iv_size;
-        
-        while (size) {
-
-            rc = i_fn(io_image, 
-                      xipRevLe64(halt->iv_address),
-                      halt->iv_string,
-                      io_arg);
-            if (rc) break;
-
-            // The SbeXipHalt structure claims a 4-character string.  The
-            // computation below computes the actual record size based on the
-            // actual length of the string, including the 0-byte termination.
-
-            actualSize = 8 + (((strlen(halt->iv_string) + 4) / 4) * 4);
-
-            if (size < actualSize) {
-                rc = TRACE_ERRORX(SBE_XIP_IMAGE_ERROR,
-                                  "The .halt section is improperly formed\n");
-                break;
-            }
-
-            size -= actualSize;
-            halt = (SbeXipHalt*)((unsigned long)halt + actualSize);
-        };
-
-        if (rc) break;
-
-    } while (0);
-
-    return rc;
-}
-
-        
-typedef struct {
-    uint64_t iv_address;
-    const char* iv_string;
-} GetHaltStruct;
-
-
-XIP_STATIC int
-xipGetHaltMap(void* io_image, 
-              const uint64_t i_poreAddress,
-              const char* i_rcString,
-              void* io_arg)
-{
-    int rc;
-
-    GetHaltStruct* s = (GetHaltStruct*)io_arg;
-
-    if (i_poreAddress == s->iv_address) {
-        s->iv_string = i_rcString;
-        rc = -1;
-    } else {
-        rc = 0;
-    }
-
-    return rc;
-}
-
-
-int
-sbe_xip_get_halt(void* io_image, 
-                 const uint64_t i_poreAddress,
-                 const char** o_rcString)
-{
-    int rc;
-    GetHaltStruct s;
-
-    s.iv_address = i_poreAddress;
-    do {
-        rc = xipQuickCheck(io_image, 0);
-        if (rc) break;
-
-        rc = sbe_xip_map_halt(io_image, xipGetHaltMap, &s);
-        if (rc == 0) {
-            rc = TRACE_ERRORX(SBE_XIP_ITEM_NOT_FOUND,
-                              "sbe_xip_get_halt: No HALT code is associated "
-                              "with address " F0x012llx "\n", i_poreAddress);
-        } else if (rc < 0) {
-            *o_rcString = s.iv_string;
-            rc = 0;
-        }
-    } while (0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_get_scalar(void *i_image, const char* i_id, uint64_t* o_data)
-{
-    int rc;
-    SbeXipItem item;
-    
-    rc = sbe_xip_find(i_image, i_id, &item);
-    if (!rc) {
-        switch (item.iv_type) {
-        case SBE_XIP_UINT8:
-            *o_data = *((uint8_t*)(item.iv_imageData));
-            break;
-        case SBE_XIP_UINT32:
-            *o_data = xipRevLe32(*((uint32_t*)(item.iv_imageData)));
-            break;
-        case SBE_XIP_UINT64:
-            *o_data = xipRevLe64(*((uint64_t*)(item.iv_imageData)));
-            break;
-        case SBE_XIP_ADDRESS:
-            *o_data = item.iv_address;
-            break;
-        default:
-            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
-            break;
-        }
-    }
-    return rc;
-}
-
-
-int
-sbe_xip_get_element(void *i_image, 
-                    const char* i_id,
-                    const uint32_t i_index,
-                    uint64_t* o_data)
-{
-    int rc;
-    SbeXipItem item;
-    
-    do {
-        rc = sbe_xip_find(i_image, i_id, &item);
-        if (rc) break;
-
-        if ((item.iv_elements != 0) && (i_index >= item.iv_elements)) {
-            rc = TRACE_ERROR(SBE_XIP_BOUNDS_ERROR);
-            break;
-        }
-
-        switch (item.iv_type) {
-        case SBE_XIP_UINT8:
-            *o_data = ((uint8_t*)(item.iv_imageData))[i_index];
-            break;
-        case SBE_XIP_UINT32:
-            *o_data = xipRevLe32(((uint32_t*)(item.iv_imageData))[i_index]);
-            break;
-        case SBE_XIP_UINT64:
-            *o_data = xipRevLe64(((uint64_t*)(item.iv_imageData))[i_index]);
-            break;
-        default:
-            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
-            break;
-        }
-        if (rc) break;
-
-    } while (0);
-    return rc;
-}
-
-
-int
-sbe_xip_get_string(void *i_image, const char* i_id, char** o_data)
-{
-    int rc;
-    SbeXipItem item;
-    
-    rc = sbe_xip_find(i_image, i_id, &item);
-    if (!rc) {
-        switch (item.iv_type) {
-        case SBE_XIP_STRING:
-            *o_data = (char*)(item.iv_imageData);
-            break;
-        default:
-            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
-            break;
-        }
-    }
-    return rc;
-}
-
-
-int
-sbe_xip_read_uint64(const void *i_image, 
-                    const uint64_t i_poreAddress,
-                    uint64_t* o_data)
-{
-    int rc;
-
-    do {
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        rc = xipValidatePoreAddress(i_image, i_poreAddress, 8);
-        if (rc) break;
-
-        if (i_poreAddress % 8) {
-            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
-            break;
-        }
-
-        *o_data = 
-            xipRevLe64(*((uint64_t*)xipPore2Host(i_image, i_poreAddress)));
-
-    } while(0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_set_scalar(void* io_image, const char* i_id, const uint64_t i_data)
-{
-    int rc;
-    SbeXipItem item;
-
-    rc = sbe_xip_find(io_image, i_id, &item);
-    if (!rc) {
-        switch(item.iv_type) {
-        case SBE_XIP_UINT8:
-            *((uint8_t*)(item.iv_imageData)) = (uint8_t)i_data;
-            break;
-        case SBE_XIP_UINT32:
-            *((uint32_t*)(item.iv_imageData)) = xipRevLe32((uint32_t)i_data);
-            break;
-        case SBE_XIP_UINT64:
-            *((uint64_t*)(item.iv_imageData)) = xipRevLe64((uint64_t)i_data);
-            break;
-        default:
-            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
-            break;
-        }
-    }
-    return rc;
-}
-
-
-int
-sbe_xip_set_element(void *i_image, 
-                    const char* i_id,
-                    const uint32_t i_index,
-                    const uint64_t i_data)
-{
-    int rc;
-    SbeXipItem item;
-    
-    do {
-        rc = sbe_xip_find(i_image, i_id, &item);
-        if (rc) break;
-
-        if ((item.iv_elements != 0) && (i_index >= item.iv_elements)) {
-            rc = TRACE_ERROR(SBE_XIP_BOUNDS_ERROR);
-            break;
-        }
-
-        switch (item.iv_type) {
-        case SBE_XIP_UINT8:
-            ((uint8_t*)(item.iv_imageData))[i_index] = (uint8_t)i_data;
-            break;
-        case SBE_XIP_UINT32:
-            ((uint32_t*)(item.iv_imageData))[i_index] = 
-                xipRevLe32((uint32_t)i_data);
-            break;
-        case SBE_XIP_UINT64:
-            ((uint64_t*)(item.iv_imageData))[i_index] = 
-                xipRevLe64((uint64_t)i_data);
-            break;
-        default:
-            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
-            break;
-        }
-        if (rc) break;
-
-    } while (0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_set_string(void *i_image, const char* i_id, const char* i_data)
-{
-    int rc;
-    SbeXipItem item;
-    char* dest;
-    
-    rc = sbe_xip_find(i_image, i_id, &item);
-    if (!rc) {
-        switch (item.iv_type) {
-        case SBE_XIP_STRING:
-            dest = (char*)(item.iv_imageData);
-            if (strlen(dest) < strlen(i_data)) {
-                memcpy(dest, i_data, strlen(dest));
-            } else {
-                strcpy(dest, i_data);
-            }
-            break;
-        default:
-            rc = TRACE_ERROR(SBE_XIP_TYPE_ERROR);
-            break;
-        }
-    }
-    return rc;
-}
-
-
-int
-sbe_xip_write_uint64(void *io_image, 
-                     const uint64_t i_poreAddress,
-                     const uint64_t i_data)
-{
-    int rc;
-
-    do {
-        rc = xipQuickCheck(io_image, 0);
-        if (rc) break;
-
-        rc = xipValidatePoreAddress(io_image, i_poreAddress, 8);
-        if (rc) break;
-
-        if (i_poreAddress % 8) {
-            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
-            break;
-        }
-
-        *((uint64_t*)xipPore2Host(io_image, i_poreAddress)) = 
-            xipRevLe64(i_data);
-
-    } while(0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_delete_section(void* io_image, const int i_sectionId)
-{
-    int rc, final;
-    SbeXipSection section;
-
-    do {
-        rc = xipQuickCheck(io_image, 1);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(io_image, i_sectionId, &section);
-        if (rc) break;
-
-
-        // Deleting an empty section is a NOP.  Otherwise the section must be
-        // the final section of the image. Update the sizes and re-establish
-        // the final image alignment.
-
-        if (section.iv_size == 0) break;
-
-        rc = xipFinalSection(io_image, &final);
-        if (rc) break;
-
-        if (final != i_sectionId) {
-            rc = TRACE_ERRORX(SBE_XIP_SECTION_ERROR,
-                              "Attempt to delete non-final section %d\n",
-                              i_sectionId);
-            break;
-        }
-
-        xipSetSectionOffset(io_image, i_sectionId, 0);
-        xipSetSectionSize(io_image, i_sectionId, 0);
-
-
-        // For cleanliness we also remove any alignment padding that had been
-        // appended between the now-last section and the deleted section, then
-        // re-establish the final alignment. The assumption is that all images
-        // always have the correct final alignment, so there is no way this
-        // could overflow a designated buffer space since the image size is
-        // the same or has been reduced.
-
-        rc = xipFinalSection(io_image, &final);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(io_image, final, &section);
-        if (rc) break;
-
-        xipSetImageSize(io_image, section.iv_offset + section.iv_size);
-        xipFinalAlignment(io_image);
-
-    } while (0);
-
-    return rc;
-}
-
-
-#ifndef PPC_HYP
-
-// This API is not needed by PHYP procedures, and is elided since PHYP does
-// not support malloc().
-
-int
-sbe_xip_duplicate_section(const void* i_image, 
-                          const int i_sectionId,
-                          void** o_duplicate,
-                          uint32_t* o_size)
-{
-    SbeXipSection section;
-    int rc;
-
-    *o_duplicate = 0;
-
-    do {
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(i_image, i_sectionId, &section);
-        if (rc) break;
-
-        if (section.iv_size == 0) {
-            rc = TRACE_ERRORX(SBE_XIP_SECTION_ERROR,
-                              "Attempt to duplicate empty section %d\n",
-                              i_sectionId);
-            break;
-        }
-
-        *o_duplicate = malloc(section.iv_size);
-        *o_size = section.iv_size;
-
-        if (*o_duplicate == 0) {
-            rc = TRACE_ERROR(SBE_XIP_NO_MEMORY);
-            break;
-        }
-
-        memcpy(*o_duplicate, 
-               xipHostAddressFromOffset(i_image, section.iv_offset),
-               section.iv_size);
-        
-        
-    } while (0);
-
-    if (rc) {
-        free(*o_duplicate);
-        *o_duplicate = 0;
-        *o_size = 0;
-    }
-
-    return rc;
-}
-
-#endif // PPC_HYP
-
-
-// The append must be done in such a way that if the append fails, the image
-// is not modified. This behavior is required by applications that
-// speculatively append until the allocation fails, but still require the
-// final image to be valid. To accomplish this the initial image size and
-// section statistics are captured at entry, and restored in the event of an
-// error.
-
-int
-sbe_xip_append(void* io_image,
-               const int i_sectionId,
-               const void* i_data,
-               const uint32_t i_size,
-               const uint32_t i_allocation,
-               uint32_t* o_sectionOffset)
-{
-    SbeXipSection section, initialSection;
-    int rc, final, restoreOnError;
-    void* hostAddress;
-    uint32_t pad;
-    uint32_t initialSize = 0;
-
-    do {
-        restoreOnError = 0;
-
-        rc = xipQuickCheck(io_image, 1);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(io_image, i_sectionId, &section);
-        if (rc) break;
-
-        if (i_size == 0) break;
-
-        initialSection = section;
-        initialSize = xipImageSize(io_image);
-        restoreOnError = 1;
-
-        if (section.iv_size == 0) {
-
-            // The section is empty, and now becomes the final section. Pad
-            // the image to the specified section alignment.  Note that the
-            // size of the previously final section does not change.
-
-            rc = xipPadImage(io_image, i_allocation, section.iv_alignment, 
-                             &pad);
-            if (rc) break;
-            section.iv_offset = xipImageSize(io_image);
-
-        } else {
-
-            // Otherwise, the section must be the final section in order to
-            // continue. Remove any padding from the image.
-
-            rc = xipFinalSection(io_image, &final);
-            if (rc) break;
-
-            if (final != i_sectionId) {
-                rc = TRACE_ERRORX(SBE_XIP_SECTION_ERROR,
-                                  "Attempt to append to non-final section "
-                                  "%d\n", i_sectionId);
-                break;
-            }
-            xipSetImageSize(io_image, section.iv_offset + section.iv_size);
-        }
-
-
-        // Make sure the allocated space won't overflow. Set the return
-        // parameter o_sectionOffset and copy the new data into the image (or
-        // simply clear the space).
-
-        if ((xipImageSize(io_image) + i_size) > i_allocation) {
-            rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW);
-            break;
-        }            
-        if (o_sectionOffset != 0) {
-            *o_sectionOffset = section.iv_size;
-        }
-
-        hostAddress = 
-            xipHostAddressFromOffset(io_image, xipImageSize(io_image));
-        if (i_data == 0) {
-            memset(hostAddress, 0, i_size);
-        } else {
-            memcpy(hostAddress, i_data, i_size);
-        }
-
-
-        // Update the image size and section table. Note that the final
-        // alignment may push out of the allocation.
-
-        xipSetImageSize(io_image, xipImageSize(io_image) + i_size);
-        xipFinalAlignment(io_image);
-
-        if (xipImageSize(io_image) > i_allocation) {
-            rc = TRACE_ERROR(SBE_XIP_WOULD_OVERFLOW);
-            break;
-        }            
-
-        section.iv_size += i_size;
-
-        if (xipPutSection(io_image, i_sectionId, &section) != 0) {
-            rc = TRACE_ERROR(SBE_XIP_BUG); /* Can't happen */
-            break;
-        }
-
-
-        // Special case
-
-        if (i_sectionId == SBE_XIP_SECTION_TOC) {
-            ((SbeXipHeader*)io_image)->iv_tocSorted = 0;
-        }
-
-    } while (0);
-
-    if (rc && restoreOnError) {
-        if (xipPutSection(io_image, i_sectionId, &initialSection) != 0) {
-            rc = TRACE_ERROR(SBE_XIP_BUG); /* Can't happen */
-        }
-        xipSetImageSize(io_image, initialSize);
-    }
-     
-    return rc;
-}
-
-
-int
-sbe_xip_section2pore(const void* i_image, 
-                     const int i_sectionId,
-                     const uint32_t i_offset,
-                     uint64_t* o_poreAddress)
-{
-    int rc;
-    SbeXipSection section;
-
-    do {
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        rc = sbe_xip_get_section(i_image, i_sectionId, &section);
-        if (rc) break;
-
-        if (section.iv_size == 0) {
-            rc = TRACE_ERROR(SBE_XIP_SECTION_ERROR);
-            break;
-        }
-
-        if (i_offset > (section.iv_offset + section.iv_size)) {
-            rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
-            break;
-        }
-
-        *o_poreAddress = xipLinkAddress(i_image) + section.iv_offset + i_offset;
-
-        if (*o_poreAddress % 4) {
-            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
-            break;
-        }
-
-    } while(0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_pore2section(const void* i_image, 
-                     const uint64_t i_poreAddress,
-                     int* i_section,
-                     uint32_t* i_offset)
-{
-    int rc;
-
-    do {
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        rc = xipPore2Section(i_image, i_poreAddress, i_section, i_offset);
-
-    } while(0);
-
-    return rc;
-}
-
-
-int
-sbe_xip_pore2host(const void* i_image, 
-                  const uint64_t i_poreAddress,
-                  void** o_hostAddress)
-{
-    int rc;
-
-    do {
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        if ((i_poreAddress < xipLinkAddress(i_image)) ||
-            (i_poreAddress > 
-             (xipLinkAddress(i_image) + xipImageSize(i_image)))) {
-            rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
-            break;
-        }
-
-        *o_hostAddress = 
-            xipHostAddressFromOffset(i_image, 
-                                     i_poreAddress - xipLinkAddress(i_image));
-    } while(0);
-
-    return rc;
-}
-    
-    
-int
-sbe_xip_host2pore(const void* i_image, 
-                  void* i_hostAddress,
-                  uint64_t* o_poreAddress)
-{
-    int rc;
-
-    do {
-        rc = xipQuickCheck(i_image, 0);
-        if (rc) break;
-
-        if ((i_hostAddress < i_image) ||
-            (i_hostAddress > 
-             xipHostAddressFromOffset(i_image, xipImageSize(i_image)))) {
-            rc = TRACE_ERROR(SBE_XIP_INVALID_ARGUMENT);
-            break;
-        }
-
-        *o_poreAddress = xipLinkAddress(i_image) + 
-            ((unsigned long)i_hostAddress - (unsigned long)i_image);
-        if (*o_poreAddress % 4) {
-            rc = TRACE_ERROR(SBE_XIP_ALIGNMENT_ERROR);
-            break;
-        }
-    } while(0);
-
-    return rc;
-}
-        
-
-void
-sbe_xip_translate_header(SbeXipHeader* o_dest, const SbeXipHeader* i_src)
-{
-#ifndef _BIG_ENDIAN
-    int i;
-    SbeXipSection* destSection;
-    const SbeXipSection* srcSection;
-
-#if SBE_XIP_HEADER_VERSION != 8
-#error This code assumes the SBE-XIP header version 8 layout
-#endif
-
-    o_dest->iv_magic = xipRevLe64(i_src->iv_magic);
-    o_dest->iv_entryOffset = xipRevLe64(i_src->iv_entryOffset);
-    o_dest->iv_linkAddress = xipRevLe64(i_src->iv_linkAddress);
-    o_dest->iv_ptsVersion = xipRevLe64(i_src->iv_ptsVersion);
-
-    for (i = 0; i < 4; i++) {
-        o_dest->iv_reserved64[i] = 0;
-    }
-
-    for (i = 0, destSection = o_dest->iv_section, 
-             srcSection = i_src->iv_section;
-         i < SBE_XIP_SECTIONS; 
-         i++, destSection++, srcSection++) {
-        xipTranslateSection(destSection, srcSection);
-    }
-
-    o_dest->iv_imageSize = xipRevLe32(i_src->iv_imageSize);
-    o_dest->iv_buildDate = xipRevLe32(i_src->iv_buildDate);
-    o_dest->iv_buildTime = xipRevLe32(i_src->iv_buildTime);
-
-    for (i = 0; i < 5; i++) {
-        o_dest->iv_reserved32[i] = 0;
-    }
-
-    o_dest->iv_headerVersion = i_src->iv_headerVersion;
-    o_dest->iv_normalized = i_src->iv_normalized;
-    o_dest->iv_tocSorted = i_src->iv_tocSorted;
-
-    for (i = 0; i < 3; i++) {
-        o_dest->iv_reserved8[i] = 0;
-    }
-
-    memcpy(o_dest->iv_buildUser, i_src->iv_buildUser, 
-           sizeof(i_src->iv_buildUser));
-    memcpy(o_dest->iv_buildHost, i_src->iv_buildHost, 
-           sizeof(i_src->iv_buildHost));
-    memcpy(o_dest->iv_reservedChar, i_src->iv_reservedChar, 
-           sizeof(i_src->iv_reservedChar));
-
-#else
-    if (o_dest != i_src) {
-        *o_dest = *i_src;
-    }
-#endif  /* _BIG_ENDIAN */
-}
-    
-
-int
-sbe_xip_map_toc(void* io_image, 
-                int (*i_fn)(void* io_image,
-                            const SbeXipItem* i_item, 
-                            void* io_arg),
-                void* io_arg)
-{
-    int rc;
-    SbeXipToc *imageToc;
-    SbeXipItem item;
-    size_t entries;
-
-    do {
-        rc = xipQuickCheck(io_image, 0);
-        if (rc) break;
-
-        rc = xipGetToc(io_image, &imageToc, &entries, 0, 0);
-        if (rc) break;
-
-        for (; entries--; imageToc++) {
-            rc = xipDecodeToc(io_image, imageToc, &item);
-            if (rc) break;
-            rc = i_fn(io_image, &item, io_arg);
-            if (rc) break;
-        }
-    } while(0);
-
-    return rc;
-}
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h
deleted file mode 100644
index ef6dd236f..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h
+++ /dev/null
@@ -1,1794 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/sbe_xip_image.h $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __SBE_XIP_IMAGE_H
-#define __SBE_XIP_IMAGE_H
-
-// $Id: sbe_xip_image.h,v 1.26 2015/07/29 23:40:17 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/sbe/sbe_xip_image.h,v $
-//-----------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//-----------------------------------------------------------------------------
-// *! OWNER NAME: Bishop Brock          Email: bcbrock@us.ibm.com
-//------------------------------------------------------------------------------
-
-/// \file sbe_xip_image.h
-/// \brief Everything related to creating and manipulating SBE-XIP binary
-/// images.
-
-#include "fapi_sbe_common.H"
-
-/// Current version (fields, layout, sections) of the SBE_XIP header
-///
-/// If any changes are made to this file or to sbe_xip_header.H, please update
-/// the header version and follow-up on all of the error messages.
-
-#define SBE_XIP_HEADER_VERSION 8
-
-/// \defgroup sbe_xip_magic_numbers SBE-XIP magic numbers
-///
-/// An SBE-XIP magic number is a 64-bit constant.  The 4 high-order bytes
-/// contain the ASCII characters "XIP " and identify the image as an SBE-XIP
-/// image, while the 4 low-order bytes identify the type of the image.
-///
-/// @{
-
-#define SBE_XIP_MAGIC     0x58495020               // "XIP "
-#define SBE_BASE_MAGIC    ULL(0x5849502042415345)  // "XIP BASE"
-#define SBE_SEEPROM_MAGIC ULL(0x584950205345504d)  // "XIP SEPM"
-#define SBE_CENTAUR_MAGIC ULL(0x58495020434e5452)  // "XIP CNTR"
-
-/// @}
-
-
-/// \defgroup sbe_xip_sections SBE-XIP Image Section Indexes
-///
-/// These constants define the order that the SbeXipSection structures appear
-/// in the header, which is not necessarily the order the sections appear in
-/// the binary image.  Given that SBE-XIP image contents are tightly
-/// controlled, we use this simple indexing scheme for the allowed sections
-/// rather than a more general approach, e.g., allowing arbitrary sections
-/// identified by their names.
-///
-/// @{
-
-// -*- DO NOT REORDER OR EDIT THIS SET OF CONSTANTS WITHOUT ALSO EDITING -*-
-// -*- THE ASSEMBLER LAYOUT IN sbe_xip_header.H.                         -*-
-
-#define SBE_XIP_SECTION_HEADER      0
-#define SBE_XIP_SECTION_FIXED       1
-#define SBE_XIP_SECTION_FIXED_TOC   2
-#define SBE_XIP_SECTION_IPL_TEXT    3
-#define SBE_XIP_SECTION_IPL_DATA    4
-#define SBE_XIP_SECTION_TEXT        5
-#define SBE_XIP_SECTION_DATA        6
-#define SBE_XIP_SECTION_TOC         7
-#define SBE_XIP_SECTION_STRINGS     8
-#define SBE_XIP_SECTION_HALT        9
-#define SBE_XIP_SECTION_PIBMEM0    10
-#define SBE_XIP_SECTION_DCRINGS    11
-#define SBE_XIP_SECTION_RINGS      12
-#define SBE_XIP_SECTION_SLW        13
-#define SBE_XIP_SECTION_FIT        14
-#define SBE_XIP_SECTION_FFDC       15
-
-#define SBE_XIP_SECTIONS 16
-
-/// @}
-
-
-/// \defgroup sbe_xip_validate() ignore masks.
-///
-/// These defines, when matched in sbe_xip_validate(), cause the validation
-/// to skip the check of the corresponding property. The purpose is to more
-/// effectively debug images that may be damaged and which have excess info
-/// before or after the image. The latter will be the case when dumping the
-/// image as a memory block without knowing where the image starts and ends.
-///
-/// @{
-
-#define SBE_XIP_IGNORE_FILE_SIZE (uint32_t)0x00000001
-#define SBE_XIP_IGNORE_ALL       (uint32_t)0x80000000
-
-/// @}
-
-
-#ifndef __ASSEMBLER__
-
-/// Applications can expand this macro to create an array of section names.
-#define SBE_XIP_SECTION_NAMES(var)              \
-    const char* var[] = {                       \
-        ".header",                              \
-        ".fixed",                               \
-        ".fixed_toc",                           \
-        ".ipl_text",                            \
-        ".ipl_data",                            \
-        ".text",                                \
-        ".data",                                \
-        ".toc",                                 \
-        ".strings",                             \
-        ".halt",                                \
-        ".pibmem0",                             \
-        ".dcrings",                             \
-        ".rings",                               \
-        ".slw",                                 \
-        ".fit",                                 \
-        ".ffdc",                                \
-    }
-
-/// Applications can use this macro to safely index the array of section
-/// names. 
-#define SBE_XIP_SECTION_NAME(var, n)                                   \
-    ((((n) < 0) || ((n) > (int)(sizeof(var) / sizeof(char*)))) ?        \
-     "Bug : Invalid SBE-XIP section name" : var[n])
-
-
-#endif  /* __ASSEMBLER__ */
-
-
-/// Define the PTS version
-///
-/// Note that this should only be done on per PHYP instruction and only here
-#define PTS_VERSION 1
-
-/// Maximum section alignment for SBE-XIP sections
-#define SBE_XIP_MAX_SECTION_ALIGNMENT 128
-
-/// \defgroup sbe_xip_toc_types SBE-XIP Table of Contents data types
-///
-/// These are the data types stored in the \a iv_type field of the SbeXipToc
-/// objects.  These must be defined as manifest constants because they are
-/// required to be recognized as manifest constants in C (as opposed to C++)
-/// code.
-///
-/// NB: The 0x0 code is purposefully left undefined to catch bugs.
-///
-/// @{
-
-/// Data is a single unsigned byte
-#define SBE_XIP_UINT8 0x01
-
-/// Data is a 32-bit unsigned integer
-#define SBE_XIP_UINT32 0x02
-
-/// Data is a 64-bit unsigned integer
-#define SBE_XIP_UINT64 0x03
-
-/// Data is a 0-byte terminated ASCII string
-#define SBE_XIP_STRING 0x04
-
-/// Data is an address
-#define SBE_XIP_ADDRESS 0x05
-
-/// The maximum type number
-#define SBE_XIP_MAX_TYPE_INDEX 0x05
-
-/// Applications can expand this macro to get access to string forms of the
-/// SBE-XIP data types if desired.
-#define SBE_XIP_TYPE_STRINGS(var)               \
-    const char* var[] = {                       \
-        "Illegal 0 Code",                       \
-        "SBE_XIP_UINT8",                        \
-        "SBE_XIP_UINT32",                       \
-        "SBE_XIP_UINT64",                       \
-        "SBE_XIP_STRING",                       \
-        "SBE_XIP_ADDRESS",                      \
-    }
-
-/// Applications can expand this macro to get access to abbreviated string
-/// forms of the SBE-XIP data types if desired.
-#define SBE_XIP_TYPE_ABBREVS(var)               \
-    const char* var[] = {                       \
-        "Illegal 0 Code",                       \
-        "u8 ",                                  \
-        "u32",                                  \
-        "u64",                                  \
-        "str",                                  \
-        "adr",                                  \
-    }
-
-/// Applications can use this macro to safely index either array of SBE-XIP
-/// type strings.
-#define SBE_XIP_TYPE_STRING(var, n)                     \
-    (((n) > (sizeof(var) / sizeof(char*))) ?            \
-     "Invalid SBE-XIP type specification" : var[n])
-
-/// @}
-
-
-/// Final alignment constraint for SBE-XIP images.
-///
-/// PORE images are required to be multiples of 8 bytes in length, to
-/// gaurantee that the PoreVe will be able to complete any 8-byte load/store.
-#define SBE_XIP_FINAL_ALIGNMENT 8
-
-
-////////////////////////////////////////////////////////////////////////////
-// C Definitions
-////////////////////////////////////////////////////////////////////////////
-
-#ifndef __ASSEMBLER__
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if 0
-} /* So __cplusplus doesn't mess w/auto-indent */
-#endif
-
-/// SBE-XIP Section information
-///
-/// This structure defines the data layout of section table entries in the
-/// SBE-XIP image header.
-
-// -*- DO NOT REORDER OR EDIT THIS STRUCTURE DEFINITION WITHOUT ALSO    -*-
-// -*- EDITING THE ASSEMBLER LAYOUT IN sbe_xip_header.H                 -*-
-
-typedef struct {
-
-    /// The offset (in bytes) of the section from the beginning of the image
-    ///
-    /// In normalized images the section offset will always be 0 if the
-    /// section size is also 0.
-    uint32_t iv_offset;
-
-    /// The size of the section in bytes, exclusive of alignment padding
-    ///
-    /// This is the size of the program-significant data in the section,
-    /// exclusive of any alignment padding or reserved or extra space.  The
-    /// alignment padding (reserved space) is not represented explicitly, but
-    /// is only implied by the offset of any subsequent non-empty section, or
-    /// in the case of the final section in the image, the image size.
-    ///
-    /// Regardless of the \a iv_offset, if the \a iv_size of a section is 0 it
-    /// should be considered "not present" in the image.  In normalized images
-    /// the section offset will always be 0 if the section size is also 0.
-    uint32_t iv_size;
-
-    /// The required initial alignment for the section offset
-    ///
-    /// The PORE and the applications using SBE-XIP images have strict
-    /// alignment/padding requirements.  The PORE does not handle any type of
-    /// unaligned instruction or data fetches.  Some sections and subsections
-    /// must also be POWER cache-line aligned. The \a iv_alignment applies to
-    /// the first byte of the section. PORE images are also required to be
-    /// multiples of 8 bytes in length, to gaurantee that the PoreVe will be
-    /// able to complete any 8-byte load/store.  These constraints are checked
-    /// by sbe_xip_validate() and enforced by sbe_xip_append(). The alignment
-    /// constraints may force a section to be padded, which may create "holes"
-    /// in the image as explained in the comments for the \a iv_size field.
-    ///
-    /// Note that alignment constraints are always checked relative to the
-    /// first byte of the image for in-memory images, not relative to the host
-    /// address. Alignment specifications are required to be a power-of-2.
-    uint8_t iv_alignment;
-
-    /// Reserved structure alignment padding; Pad to 12 bytes
-    uint8_t iv_reserved8[3];
-
-} SbeXipSection;
-
-/// The SbeXipSection structure is created by assembler code and is expected
-/// to have the same size in C code.  This constraint is checked in
-/// sbe_xip_validate(). 
-#define SIZE_OF_SBE_XIP_SECTION 12
-
-
-/// SBE-XIP binary image header
-///
-/// This header occupies the initial bytes of an SBE-XIP binary image.
-/// The header contents are documented here, however the structure is actually
-/// defined in the file sbe_xip_header.S, and these two definitions must be
-/// kept consistent.
-///
-/// The header is a fixed-format representation of the most critical
-/// information about the image.  The large majority of information about the
-/// image and its contents are available through the searchable table of
-/// contents. PORE code itself normally accesses the data directly through
-/// global symbols. 
-///
-/// The header only contains information 1) required by OTPROM code (e.g., the
-/// entry point); 2) required by search and updating APIs (e.g., the
-/// locations and sizes of all of the sections.); a few pieces of critical
-/// meta-data (e.g., information about the image build process).
-///
-/// Any entries that are accessed by PORE code are required to be 64 bits, and
-/// will appear at the beginning of the header.
-///
-/// The header also contains bytewise offsets and sizes of all of the sections
-/// that are assembled to complete the image.  The offsets are relative to the
-/// start of the image (where the header is loaded).  The sizes include any
-/// padding inserted by the link editor to guarantee section alignment.
-///
-/// Every field of the header is also accesssible through the searchable table
-/// of contents as documented in sbe_xip_header.S.
-
-// -*- DO NOT REORDER OR EDIT THIS STRUCTURE DEFINITION WITHOUT ALSO     -*-
-// -*- EDITING THE ASSEMBLER LAYOUT IN sbe_xip_header.S, AND WITHOUT     -*-
-// -*- UPDATING THE sbe_xip_translate_header() API IN sbe_xip_image.c.   -*-
-
-typedef struct {
-
-    //////////////////////////////////////////////////////////////////////
-    // Identification - 8-byte aligned; 8 entries
-    //////////////////////////////////////////////////////////////////////
-
-    /// Contains SBE_XIP_MAGIC to identify an SBE-XIP image
-    uint64_t iv_magic;
-
-    /// The offset of the SBE-XIP entry point from the start of the image
-    uint64_t iv_entryOffset;
-
-    /// The base address used to link the image, as a full relocatable PORE
-    /// address 
-    uint64_t iv_linkAddress;
-
-    /// PTS version
-    uint64_t iv_ptsVersion;
-
-    /// Reserved for future expansion
-    uint64_t iv_reserved64[4];
-
-    //////////////////////////////////////////////////////////////////////
-    // Section Table - 4-byte aligned; 16 entries
-    //////////////////////////////////////////////////////////////////////
-
-    SbeXipSection iv_section[SBE_XIP_SECTIONS];
-
-    //////////////////////////////////////////////////////////////////////
-    // Other information - 4-byte aligned; 8 entries
-    //////////////////////////////////////////////////////////////////////
-
-    /// The size of the image (including padding) in bytes
-    uint32_t iv_imageSize;
-
-    /// Build date generated by `date +%Y%m%d`, e.g., 20110630	
-    uint32_t iv_buildDate;
-
-    /// Build time generated by `date +%H%M`, e.g., 0756
-    uint32_t iv_buildTime;
-
-    /// Reserved for future expansion
-    uint32_t iv_reserved32[5];
-
-    //////////////////////////////////////////////////////////////////////
-    // Other Information - 1-byte aligned; 8 entries
-    //////////////////////////////////////////////////////////////////////
-
-    /// Header format version number
-    uint8_t iv_headerVersion;
-
-    /// Indicates whether the image has been normalized (0/1)
-    uint8_t iv_normalized;
-
-    /// Indicates whether the TOC has been sorted to speed searching (0/1)
-    uint8_t iv_tocSorted;
-
-    /// Reserved for future expansion
-    uint8_t iv_reserved8[5];
-
-    //////////////////////////////////////////////////////////////////////
-    // Strings; 64 characters allocated
-    //////////////////////////////////////////////////////////////////////
-
-    /// Build user, generated by `id -un`
-    char iv_buildUser[16];
-
-    /// Build host, generated by `hostname`
-    char iv_buildHost[24];
-
-    /// Reserved for future expansion
-    char iv_reservedChar[24];
-    
-} SbeXipHeader;
-
-
-/// A C-structure form of the SBE-XIP Table of Contents (TOC) entries
-///
-/// The .toc section consists entirely of an array of these structures.
-/// TOC entries are never accessed by PORE code. 
-///
-/// These structures store indexing information for global data required to be
-/// manipulated by external tools.  The actual data is usually allocated in a
-/// data section and manipulated by the SBE code using global or local symbol
-/// names.  Each TOC entry contains a pointer to a keyword string naming the
-/// data, the address of the data (or the data itself), the data type,
-/// meta-information about the data, and for vectors the vector size.
-
-// -*- DO NOT REORDER OR EDIT THIS STRUCTURE DEFINITION WITHOUT ALSO     -*-
-// -*- EDITING THE ASSEMBLER MACROS (BELOW) THAT CREATE THE TABLE OF     -*-
-// -*- CONTENTS ENTRIES.                                                 -*-
-
-typedef struct {
-
-    /// A pointer to a 0-byte terminated ASCII string identifying the data.
-    ///
-    /// When allocated by the .xip_toc macro this is a pointer to the string
-    /// form of the symbol name for the global or local symbol associated with
-    /// the data which is allocated in the .strings section. This pointer is
-    /// not aligned.
-    ///
-    /// When the image is normalized this pointer is replaced by the offset of
-    /// the string in the .strings section.
-    uint32_t iv_id;
-
-    /// A 32-bit pointer locating the data
-    ///
-    /// This field is initially populated by the link editor.  For scalar,
-    /// vector and string types this is the final relocated address of the
-    /// first byte of the data.  For address types, this is the relocated
-    /// address.  When the image is normalized, these addresses are converted
-    /// into the equivalent offsets from the beginning of the section holding
-    /// the data.
-    uint32_t iv_data;
-
-    /// The type of the data; See \ref sbe_xip_toc_types.
-    uint8_t iv_type;
-
-    /// The section containing the data; See \ref sbe_xip_sections.
-    uint8_t iv_section;
-
-    /// The number of elements for vector types, otherwise 1 for scalar types
-    /// and addresses.
-    ///
-    /// Vectors are naturally limited in size, e.g. to the number of cores,
-    /// chips in a node, DD-levels etc.  If \a iv_elements is 0 then no bounds
-    /// checking is done on get/set accesses of the data.
-    uint8_t iv_elements;
-
-    /// Structure alignment padding; Pad to 12 bytes
-    uint8_t iv_pad;
-
-} SbeXipToc;
-
-/// The SbeXipToc structure is created by assembler code and is expected
-/// to have the same size in C code.  This constraint is checked in
-/// sbe_xip_validate(). 
-#define SIZE_OF_SBE_XIP_TOC 12
-
-
-/// A C-structure form of hashed SBE-XIP Table of Contents (TOC) entries
-///
-/// This structure was introduced in order to allow a small TOC for the .fixed
-/// section to support minimum-sized SEEPROM images in which the global TOC
-/// and all strings have been stripped out.  In this structure the index
-/// string has been replaced by a 32-bit hash, and there is no longer a record
-/// of the original data name other then the hash.  The section of the data is
-/// assumed to be .fixed, with a maximum 16-bit offset.
-///
-/// These structures are created when entries are made in the .fixed section.
-/// They are created empty, then filled in during image normalization.
-///
-/// This structure allows the sbe_xip_get*() and sbe_xip_set*() APIs to work
-/// even on highly-stripped SEEPROM images.  
-
-typedef struct {
-
-    /// A 32-bit hash (FNV-1a) of the Id string.
-    uint32_t iv_hash;
-
-    /// The offset in bytes from the start of the (implied) section of the data
-    uint16_t iv_offset;
-
-    /// The type of the data; See \ref sbe_xip_toc_types.
-    uint8_t iv_type;
-
-    /// The number of elements for vector types, otherwise 1 for scalar types
-    /// and addresses.
-    ///
-    /// Vectors are naturally limited in size, e.g. to the number of cores,
-    /// chips in a node, DD-levels etc.  If \a iv_elements is 0 then no bounds
-    /// checking is done on get/set accesses of the data.
-    uint8_t iv_elements;
-
-} SbeXipHashedToc;
-
-/// The SbeXipHashedToc structure is created by assembler code and is expected
-/// to have the same size in C code.  This constraint is checked in
-/// sbe_xip_validate().
-#define SIZE_OF_SBE_XIP_HASHED_TOC 8
-
-
-/// A decoded TOC entry for use by applications
-///
-/// This structure is a decoded form of a normalized TOC entry, filled in by
-/// the sbe_xip_decode_toc() and sbe_xip_find() APIs.  This structure is
-/// always returned with data elements in host-endian format. 
-///
-/// In the event that the TOC has been removed from the image, this structure
-/// will also be returned by sbe_xip_find() with information populated from
-/// the .fixed_toc section if possible.  In this case the field \a iv_partial
-/// will be set and only the fields \a iv_address, \a iv_imageData, \a iv_type
-/// and \a iv_elements will be populated (all other fields will be set to 0).
-///
-/// \note Only special-purpose applications will ever need to use this
-/// structure given that the higher-level APIs sbe_xip_get_*() and
-/// sbe_xip_set_*() are provided and should be used if possible, especially
-/// given that the information may be truncated as described above.
-
-typedef struct {
-
-    /// A pointer to the associated TOC entry as it exists in the image
-    ///
-    ///  If \a iv_partial is set this field is returned as 0.
-    SbeXipToc* iv_toc;
-
-    /// The full relocatable PORE address
-    ///
-    /// All relocatable addresses are computed from the \a iv_linkAddress
-    /// stored in the header. For scalar and string data, this is the
-    /// relocatable address of the data.  For address-only entries, this is
-    /// the indexed address itself. 
-    uint64_t iv_address;
-
-    /// A host pointer to the first byte of text or data within the image
-    ///
-    /// For scalar or string types this is a host pointer to the first byte of
-    /// the data.  For code pointers (addresses) this is host pointer to the
-    /// first byte of code.  Note that any use of this field requires the
-    /// caller to handle conversion of the data to host endian-ness if
-    /// required.  Only 8-bit and string data can be used directly on all
-    /// hosts.
-    void* iv_imageData;
-
-    /// The item name
-    ///
-    /// This is a pointer in host memory to a string that names the TOC entry
-    /// requested.  This field is set to a pointer to the ID string of the TOC
-    /// entry inside the image. If \a iv_partial is set this field is returned
-    /// as 0.
-    char* iv_id;
-
-    /// The data type, one of the SBE_XIP_* constants
-    uint8_t iv_type;
-
-    /// The number of elements in a vector
-    ///
-    /// This field is set from the TOC entry when the TOC entry is
-    /// decoded. This value is stored as 1 for scalar declarations, and may be
-    /// set to 0 for vectors with large or undeclared sizes.  Otherwise it is
-    /// used to bounds check indexed accesses.
-    uint8_t iv_elements;
-
-    /// Is this record only partially populated?
-    ///
-    /// This field is set to 0 normally, and only set to 1 if a lookup is made
-    /// in an image that only has the fixed TOC and the requested Id hashes to
-    /// the fixed TOC.
-    uint8_t iv_partial;
-
-} SbeXipItem;
-
-
-/// Prototype entry in the .halt section
-///
-/// The .halt section is generated by the 'reqhalt' macro.  This structure
-/// associates the address of each halt with the string form of the FAPI
-/// return code associated with the halt.  The string form is used because the
-/// FAPI error return code is not constant.  The .halt section is 4-byte
-/// aligned, and each address/string entry is always padded to a multiple of 4
-/// bytes. 
-///
-/// In the .halt section the \a iv_string may be any length, thus the size of
-/// each actual record is variable (although guaranteed to always be a
-/// multiple of 4 bytes). Although the C compiler might natuarlly align
-/// instances of this structure on a 64-bit boundary, the APIs that allow
-/// access to the .halt section assume that the underlying machine can do
-/// non-aligned loads from a pointer to this structure.
-
-typedef struct {
-
-    /// The 64-bit relocatable address of the halt
-    ///
-    /// This is the address found in the PC (Status Register bits 16:63) when
-    /// the PORE halts.  The full 64-bit form is used rather than the simple
-    /// 32-bit offset to support merging SEEPROM and PIBMEM .halt sections in
-    /// the SEEPROM IPL images.
-    uint64_t iv_address;
-
-    /// A C-prototype for a variable-length 0-terminated ASCII string
-    ///
-    /// This is a prototype only to simplify C programming.  The actual string
-    /// may be any length.
-    char iv_string[4];
-
-} SbeXipHalt;
-
-
-/// Validate an SBE-XIP image
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory. 
-/// 
-/// \param[in] i_size The putative size of the image
-///
-/// \param[in] i_maskIgnores Array of ignore bits representing which properties
-/// should not be checked for in sbe_xip_validate2().
-///
-/// This API should be called first by all applications that manipulate
-/// SBE-XIP images in host memory.  The magic number is validated, and 
-/// the image is checked for consistency of the section table and table of
-/// contents.  The \a iv_imageSize field of the header must also match the
-/// provided \a i_size parameter.  Validation does not modify the image.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_validate(void* i_image, const uint32_t i_size);
-
-int
-sbe_xip_validate2(void* i_image, const uint32_t i_size, const uint32_t i_maskIgnores);
-
-
-/// Normalize the SBE-XIP image
-///
-/// \param[in] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections. 
-///
-/// SBE-XIP images must be normalized before any other APIs are allowed to
-/// operate on the image.  Since normalization modifies the image, an explicit
-/// call to normalize the image is required.  Briefly, normalization modifies
-/// the TOC entries created by the final link to simplify search, updates,
-/// modification and relocation of the image.  Normalization is explained in
-/// the written documentation of the SBE-XIP binary format. Normalization does
-/// not modify the size of the image.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_normalize(void* io_image);
-
-
-/// Return the size of an SBE-XIP image from the image header
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[out] o_size A pointer to a variable returned as the size of the
-/// image in bytes, as recorded in the image header.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_image_size(void* i_image, uint32_t* o_size);
-
-
-/// Locate a section table entry and translate into host format
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.
-///
-/// \param[in] i_sectionId Identifies the section to be queried.  See \ref
-/// sbe_xip_sections.
-///
-/// \param[out] o_hostSection Updated to contain the section table entry
-/// translated to host byte order.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_get_section(const void* i_image,
-                    const int i_sectionId,
-                    SbeXipSection* o_hostSection);
-
-
-/// Endian translation of an SbeXipHeader object
-///
-/// \param[out] o_hostHeader The destination object.
-///
-/// \param[in] i_imageHeader The source object.
-///
-/// Translation of a SbeXipHeader includes translation of all data members
-/// including traslation of the embedded section table.  This translation
-/// works even if \a o_src == \a o_dest, i.e., in the destructive case.
-void
-sbe_xip_translate_header(SbeXipHeader* o_hostHeader, 
-                         const SbeXipHeader* i_imageHeader);
-
-
-/// Get scalar data from an SBE-XIP image
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
-/// requested. 
-///
-/// \param[out] o_data A pointer to an 8-byte integer to receive the scalar
-/// data. Assuming the item is located this variable is assigned by the call.
-/// In the event of an error the final state of \a o_data is not specified.
-///
-/// This API searches the SBE-XIP Table of Contents (TOC) for the item named
-/// \a i_id, assigning \a o_data from the image if the item is found and is a
-/// scalar value.  Scalar values include 8- 32- and 64-bit integers and PORE
-/// addresses.  Image data smaller than 64 bits are extracted as unsigned
-/// types, and it is the caller's responsibility to cast or convert the
-/// returned data as appropriate.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_get_scalar(void *i_image, const char* i_id, uint64_t* o_data);
-
-
-/// Get an integral element from a vector held in an SBE-XIP image
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
-/// requested. 
-///
-/// \param[in] i_index  The index of the vector element to return.
-///
-/// \param[out] o_data A pointer to an 8-byte integer to receive the
-/// data. Assuming the item is located this variable is assigned by the call.
-/// In the event of an error the final state of \a o_data is not specified.
-///
-/// This API searches the SBE-XIP Table of Contents (TOC) for the \a i_index
-/// element of the item named \a i_id, assigning \a o_data from the image if
-/// the item is found, is a vector of an integral type, and the \a i_index is
-/// in bounds.  Vector elements smaller than 64 bits are extracted as unsigned
-/// types, and it is the caller's responsibility to cast or convert the
-/// returned data as appropriate.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_get_element(void *i_image, 
-                    const char* i_id, 
-                    const uint32_t i_index,
-                    uint64_t* o_data);
-
-
-/// Get string data from an SBE-XIP image
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
-/// requested. 
-///
-/// \param[out] o_data A pointer to a character pointer.  Assuming the
-/// item is located this variable is assigned by the call to point to the
-/// string as it exists in the \a i_image.  In the event of an error the final
-/// state of \a o_data is not specified.
-///
-/// This API searches the SBE-XIP Table of Contents (TOC) for the item named
-/// \a i_id, assigning \a o_data if the item is found and is a string.  It is
-/// the caller's responsibility to copy the string from the \a i_image memory
-/// space if necessary.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_get_string(void *i_image, const char* i_id, char** o_data);
-
-
-/// Directly read 64-bit data from the image based on a PORE address
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_poreAddress A relocatable PORE address contained in the
-/// image, presumably of an 8-byte data area.  The \a i_poreAddress is
-/// required to be 8-byte aligned, otherwise the SBE_XIP_ALIGNMENT_ERROR code
-/// is returned.
-///
-/// \param[out] o_data The 64 bit data in host format that was found at \a
-/// i_poreAddress.
-///
-/// This API is provided for applications that need to manipulate SBE-XIP
-/// images in terms of their relocatable PORE addresses.  The API checks that
-/// the \a i_poreAddress is properly aligned and contained in the image, then
-/// reads the contents of \a i_poreAddress into \a o_data, performing
-/// image-to-host endianess conversion if required.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_read_uint64(const void *i_image, 
-                    const uint64_t i_poreAddress,
-                    uint64_t* o_data);
-
-
-/// Set scalar data in an SBE-XIP image
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.
-/// The image is assumed to be consistent with the information contained in
-/// the header regarding the presence of and sizes of all sections.  The image
-/// is also required to have been normalized.
-///
-/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
-/// to be modified. 
-///
-/// \param[in] i_data The new scalar data. 
-///
-/// This API searches the SBE-XIP Table of Contents (TOC) for the item named
-/// by \a i_id, updating the image from \a i_data if the item is found, has
-/// a scalar type and can be modified.  For this API the scalar types include
-/// 8- 32- and 64-bit integers.  Although PORE addresses are considered a
-/// scalar type for sbe_xip_get_scalar(), PORE addresses can not be modified
-/// by this API.  The caller is responsible for ensuring that the \a i_data is
-/// of the correct size for the underlying data element in the image.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_set_scalar(void* io_image, const char* i_id, const uint64_t i_data);
-
-
-/// Set an integral element in a vector held in an SBE-XIP image
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
-/// to be updated.
-///
-/// \param[in] i_index  The index of the vector element to update.
-///
-/// \param[out] i_data The new vector element.
-///
-/// This API searches the SBE-XIP Table of Contents (TOC) for the \a i_index
-/// element of the item named \a i_id, update the image from \a i_data if the
-/// item is found, is a vector of an integral type, and the \a i_index is in
-/// bounds.  The caller is responsible for ensuring that the \a i_data is of
-/// the correct size for the underlying data element in the image.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_set_element(void *i_image, 
-                    const char* i_id, 
-                    const uint32_t i_index,
-                    const uint64_t i_data);
-
-
-/// Set string data in an SBE-XIP image
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_id A pointer to a 0-terminated ASCII string naming the item
-/// to be modified.
-///
-/// \param[in] i_data A pointer to the new string data.
-///
-/// This API searches the SBE-XIP Table of Contents (TOC) for the item named
-/// \a i_id, which must be a string variable.  If found, then the string data
-/// in the image is overwritten with \a i_data.  Strings are held 0-terminated
-/// in the image, and the SBE-XIP format does not maintain a record of the
-/// amount of memory allocated for an individual string.  If a string is
-/// overwritten by a shorter string then the 'excess' storage is effectively
-/// lost.  If the length of \a i_data is longer that the current strlen() of
-/// the string data then \a i_data is silently truncated to the first
-/// strlen(old_string) characters.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_set_string(void *io_image, const char* i_id, const char* i_data);
-
-
-/// Directly write 64-bit data into the image based on a PORE address
-///
-/// \param[in, out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_poreAddress A relocatable PORE address contained in the
-/// image, presumably of an 8-byte data area.  The \a i_poreAddress is
-/// required to be 8-byte aligned, otherwise the SBE_XIP_ALIGNMENT_ERROR code
-/// is returned.
-///
-/// \param[in] i_data The 64 bit data in host format to be written to \a
-/// i_poreAddress. 
-///
-/// This API is provided for applications that need to manipulate SBE-XIP
-/// images in terms of their relocatable PORE addresses.  The API checks that
-/// the \a i_poreAddress is properly aligned and contained in the image, then
-/// updates the contents of \a i_poreAddress with \a i_data, performing
-/// host-to-image endianess conversion if required.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_write_uint64(void *io_image, 
-                     const uint64_t i_poreAddress,
-                     const uint64_t i_data);
-
-
-/// Map over an SBE-XIP image Table of Contents
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_fn A pointer to a function to call on each TOC entry.  The
-/// function has the prototype:
-///
-/// \code
-/// int (*i_fn)(void* io_image,
-///             const SbeXipItem* i_item, 
-///             void* io_arg)
-/// \endcode
-///
-/// \param[in,out] io_arg The private argument of \a i_fn.
-///
-/// This API iterates over each entry of the TOC, calling \a i_fn with
-/// pointers to the image, an SbeXipItem* pointer, and a private argument. The
-/// iteration terminates either when all TOC entries have been mapped, or \a
-/// i_fn returns a non-zero code.
-///
-/// \retval 0 Success; All TOC entries were mapped, including the case that
-/// the .toc section is empty.
-///
-/// \retval non-0 May be either one of the SBE-XIP image error codes (see \ref
-/// sbe_xip_image_errors), or a non-zero code from \a i_fn. Since the standard
-/// SBE_XIP return codes are > 0, application-defined codes should be < 0.
-int
-sbe_xip_map_toc(void* io_image, 
-                 int (*i_fn)(void* io_image, 
-                             const SbeXipItem* i_item, 
-                             void* io_arg),
-                 void* io_arg);
-
-
-/// Find an SBE-XIP TOC entry
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.  The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_id A 0-byte terminated ASCII string naming the item to be
-/// searched for.
-///
-/// \param[out] o_item If the search is successful, then the object
-/// pointed to by \a o_item is filled in with the decoded form of the
-/// TOC entry for \a i_id.  If the API returns a non-0 error code then the
-/// final state of the storage at \a o_item is undefined.  This parameter may
-/// be suppied as 0, in which case sbe_xip_find() serves as a simple predicate
-/// on whether an item is indexded in the TOC.
-///
-/// This API searches the TOC of a normalized SBE-XIP image for the item named
-/// \a i_id, and if found, fills in the structure pointed to by \a
-/// o_item with a decoded form of the TOC entry.  If the item is not found,
-/// the following two return codes may be considered non-error codes:
-///
-/// - SBE_XIP_ITEM_NOT_FOUND : No TOC record for \a i_id was found.
-///
-/// - SBE_XIP_DATA_NOT_PRESENT : The item appears in the TOC, however the
-/// section containing the data is no longer present in the image.
-///
-/// If the TOC section has been deleted from the image, then the search is
-/// restricted to the abbreviated TOC that indexes data in the .fixed section.
-/// In this case the \a o_item structure is marked with a 1 in the \a
-/// iv_partial field since the abbreviated TOC can not populate the entire
-/// SbeXipItem structure.
-///
-/// \note This API should typically only be used as a predicate, not as a way
-/// to access the image via the returned SbeXipItem structure. To obtain data
-/// from the image or update data in the image use the sbe_xip_get_*() and
-/// sbe_xip_set_*() APIs respectively.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_find(void* i_image, 
-             const char* i_id, 
-             SbeXipItem* o_item);
-
-
-/// Map over an SBE-XIP image .halt section
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_fn A pointer to a function to call on each entry in .halt.
-/// The function has the prototype:
-///
-/// \code
-/// int (*i_fn)(void* io_image,
-///             const uint64_t i_poreAddress,
-///             const char* i_rcString,
-///             void* io_arg)
-///
-/// \endcode
-///
-/// \param[in,out] io_arg The private argument of \a i_fn.
-///
-/// This API iterates over each entry of the .halt section, calling \a i_fn
-/// with each HALT address, the string form of the return code associated with
-/// that HALT address, and a private argument. The iteration terminates either
-/// when all .halt entries have been mapped, or \a i_fn returns a non-zero
-/// code.  The \a i_poreAddddress passed to \a i_fn is the full 48-bit
-/// relocatable PORE address.
-///
-/// \retval 0 Success, including the case that the image has no .halt section.
-///
-/// \retval non-0 May be either one of the SBE-XIP image error codes (see \ref
-/// sbe_xip_image_errors), or any non-zero code from \a i_fn.  Since the
-/// standard SBE_XIP return codes are \> 0, application-defined codes should
-/// be \< 0.
-int
-sbe_xip_map_halt(void* io_image, 
-                 int (*i_fn)(void* io_image, 
-                             const uint64_t i_poreAddress,
-                             const char* i_rcString,
-                             void* io_arg),
-                 void* io_arg);
-
-
-/// Get the string from of a HALT code from an SBE-XIP image .halt section
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_poreAddress This is the 48-bit address found in the PC when
-/// the PORE halts.  This address is actually 4 bytes beyond the actual HALT
-/// instruction, however for simplicity this is the address used to index the
-/// HALT. 
-///
-/// \param[out] o_rcString The caller provides the address of a string-pointer
-/// variable which is updated with a pointer to the string form of the halt
-/// code associated with \a i_poreAddress (assuming a successful completion).
-///
-/// \retval 0 Success
-///
-/// \revtal SBE_XIP_ITEM_NOT_FOUND The \a i_poreAddress is not associated
-/// with a halt code in .halt.
-///
-/// \revtal Other See \ref sbe_xip_image_errors
-int
-sbe_xip_get_halt(void* io_image, 
-                 const uint64_t i_poreAddress,
-                 const char** o_rcString);
-
-
-/// Delete a section from an SBE-XIP image in host memory
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections. The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_sectionId Identifies the section to be deleted.  See \ref
-/// sbe_xip_sections.
-///
-/// This API effectively deletes a section from an SBE-XIP image held in host
-/// memory.  Unless the requested section \a i_section is already empty, only
-/// the final (highest address offset) section of the image may be deleted.
-/// Deleting the final section of the image means that the section size is set
-/// to 0, and the size of the image recorded in the header is reduced by the
-/// section size.  Any alignment padding of the now-last section is also
-/// removed.
-///
-/// \note This API does not check for or warn if other sections in the image
-/// reference the deleted section.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_delete_section(void* io_image, const int i_sectionId);
-
-
-#ifndef PPC_HYP
-
-/// Duplicate a section from an SBE-XIP image in host memory
-///
-/// \param[in,out] i_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections.
-///
-/// \param[in] i_sectionId Identifies the section to be duplicated.  See \ref
-/// sbe_xip_sections.
-///
-/// \param[out] o_duplicate At exit, points to the newly allocated and
-/// initialized duplicate of the given section. The caller is responsible for
-/// free()-ing this memory when no longer required.
-///
-/// \param[out] o_size At exit, contains the size (in bytes) of the duplicated
-/// section.  
-///
-/// This API creates a bytewise duplicate of a non-empty section into newly
-/// malloc()-ed memory. At exit \a o_duplicate points to the duplicate, and \a
-/// o_size is set the the size of the duplicated section. The caller is
-/// responsible for free()-ing the memory when no longer required.  The
-/// pointer at \a o_duplicate is set to NULL (0) and the \a o_size is set to 0
-/// in the event of any failure.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_duplicate_section(const void* i_image, 
-                          const int i_sectionId,
-                          void** o_duplicate,
-                          uint32_t* o_size);
-
-#endif // PPC_HYP
-
-
-/// Append binary data to an SBE-XIP image held in host memory
-///
-/// \param[in,out] io_image A pointer to an SBE-XIP image in host memory.  The
-/// image is assumed to be consistent with the information contained in the
-/// header regarding the presence of and sizes of all sections. The image is
-/// also required to have been normalized.
-///
-/// \param[in] i_sectionId Identifies the section to contain the new data.
-///
-/// \param[in] i_data A pointer to the data to be appended to the image.  If
-/// this pointer is NULL (0), then the effect is as if \a i_data were a
-/// pointer to an \a i_size array of 0 bytes.
-///
-/// \param[in] i_size The size of the data to be appended in bytes.  If \a
-/// i_data is 0, then this is the number of bytes to clear.
-///
-/// \param[in] i_allocation The size of the memory region containing the
-/// image, measured from the first byte of the image.  The call will fail if
-/// appending the new data plus any alignment padding would overflow the
-/// allocated memory.
-///
-/// \param[out] o_sectionOffset If non-0 at entry, then the API updates the
-/// location pointed to by \a o_sectionOffset with the offset of the first
-/// byte of the appended data within the indicated section. This return value
-/// is invalid in the event of a non-0 return code.
-///
-/// This API copies data from \a i_data to the end of the indicated \a
-/// i_section.  The section \a i_section must either be empty, or must be the
-/// final (highest address) section in the image.  If the section is initially
-/// empty and \a i_size is non-0 then the section is created at the end of the
-/// image.  The size of \a i_section and the size of the image are always
-/// adjusted to reflect the newly added data.  This is a simple binary copy
-/// without any interpretation (e.g., endian-translation) of the copied data.
-/// The caller is responsible for insuring that the host memory area
-/// containing the SBE-XIP image is large enough to hold the newly appended
-/// data without causing addressing errors or buffer overrun errors.
-///
-/// The final parameter \a o_sectionOffset is optional, and may be passed as
-/// NULL (0) if the application does not require the information.  This return
-/// value is provided to simplify typical use cases of this API:
-///
-/// - A scan program is appended to the image, or a run-time data area is
-/// allocated and cleared at the end of the image.
-///
-/// - Pointer variables in the image are updated with PORE addresses obtained
-/// via sbe_xip_section2pore(), or
-/// other procedure code initializes a newly allocated and cleared data area
-/// via host addresses obtained from sbe_xip_section2host().
-///
-/// Regarding alignment, note that the SBE-XIP format requires that sections
-/// maintain an initial alignment that varies by section, and the API will
-/// enforce these alignment constraints for all sections created by the API.
-/// All alignment is relative to the first byte of the image (\a io_image) -
-/// \e not to the current in-memory address of the image. By specification
-/// SBE-XIP images must be loaded at a 4K alignment in order for PORE hardware
-/// relocation to work, however the APIs don't require this 4K alignment for
-/// in-memory manipulation of images.  Images to be executed on PoreVe will
-/// normally require at least 8-byte final aligment in order to guarantee that
-/// the PoreVe can execute an 8-byte fetch or load/store of the final
-/// doubleword.
-///
-/// \note If the TOC section is modified then the image is marked as having an
-/// unsorted TOC.
-///
-/// \note If the call fails for any reason (other than a bug in the API
-/// itself) then the \a io_image data is returned unmodified.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_append(void* io_image,
-               const int i_sectionId,
-               const void* i_data,
-               const uint32_t i_size,
-               const uint32_t i_allocation,
-               uint32_t* o_sectionOffset);
-
-
-/// Convert an SBE-XIP section offset to a relocatable PORE address
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory
-///
-/// \param[in] i_sectionId A valid SBE-XIP section identifier; The section
-/// must be non-empty.
-///
-/// \param[in] i_offset An offset (in bytes) within the section.  At least one
-/// byte at \a i_offset must be currently allocated in the section.
-///
-/// \param[in] o_poreAddress The equivalent relocatable PORE address is
-/// returned via this pointer. Since valid PORE addresses are always either
-/// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
-/// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the PORE
-/// address is not at least 4-byte aligned.  Note that the translated address
-/// is still returned even if incorrectly aligned.
-///
-/// This API is typically used to translate section offsets returned from
-/// sbe_xip_append() into relocatable PORE addresses.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_section2pore(const void* i_image, 
-                     const int i_sectionId,
-                     const uint32_t i_offset,
-                     uint64_t* o_poreAddress);
-
-
-/// Convert an SBE-XIP relocatable PORE address to a host memory address
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.
-///
-/// \param[in] i_poreAddress A relocatable PORE address putatively addressing
-/// relocatable memory contained in the image.
-///
-/// \param[out] o_hostAddress The API updates the location pointed to by \a
-/// o_hostAddress with the host address of the memory addressed by \a
-/// i_poreAddress.  In the event of an error (non-0 return code) the final
-/// content of \a o_hostAddress is undefined.
-///
-/// This API is typically used to translate relocatable PORE addresses stored
-/// in the SBE-XIP image into the equivalent host address of the in-memory
-/// image, allowing host-code to manipulate arbitrary data structures in the
-/// image. If the \a i_poreAddress does not refer to memory within the image
-/// (as determined by the link address and image size) then the
-/// SBE_XIP_INVALID_ARGUMENT error code is returned.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_pore2host(const void* i_image, 
-                  const uint64_t i_poreAddress,
-                  void** o_hostAddress);
-
-
-/// Convert an SBE-XIP relocatable PORE address to section Id and offset
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory.
-///
-/// \param[in] i_poreAddress A relocatable PORE address putatively addressing
-/// relocatable memory contained in the image.
-///
-/// \param[out] o_section The API updates the location pointed to by \a
-/// o_section with the section Id of the memory addressed by \a
-/// i_poreAddress.  In the event of an error (non-0 return code) the final
-/// content of \a o_section is undefined.
-///
-/// \param[out] o_offset The API updates the location pointed to by \a
-/// o_offset with the byte offset of the memory addressed by \a i_poreAddress
-/// within \a o_section.  In the event of an error (non-0 return code) the
-/// final content of \a o_offset is undefined.
-///
-/// This API is typically used to translate relocatable PORE addresses stored
-/// in the SBE-XIP image into the equivalent section + offset form, allowing
-/// host-code to manipulate arbitrary data structures in the image. If the \a
-/// i_poreAddress does not refer to memory within the image (as determined by
-/// the link address and image size) then the SBE_XIP_INVALID_ARGUMENT error
-/// code is returned.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_pore2section(const void* i_image, 
-                     const uint64_t i_poreAddress,
-                     int* o_section,
-                     uint32_t* o_offset);
-
-
-/// Convert an in-memory SBE-XIP host address to a relocatable PORE address
-///
-/// \param[in] i_image A pointer to an SBE-XIP image in host memory
-///
-/// \param[in] i_hostAddress A host address addressing data within the image.
-///
-/// \param[out] o_poreAddress The API updates the location pointed to by \a
-/// o_poreAddress with the equivelent relocatable PORE address of the memory
-/// addressed by i_hostAddress.  Since valid PORE addresses are always either
-/// 4-byte (code) or 8-byte (data) aligned, this API checks the aligment of
-/// the translated address and returns SBE_XIP_ALIGNMENT_ERROR if the PORE
-/// address is not at least 4-byte aligned.  Note that the translated address
-/// is still returned evn if incorrectly aligned.
-///
-/// This API is provided as a convenient way to convert host memory addresses
-/// for an in-memory SBE-XIP image into PORE addresses correctly relocated for
-/// the image, for example to update pointer variables in the image.  If the
-/// \a i_hostAddress does not refer to memory within the image (as determined
-/// by the image address and image size) then the SBE_XIP_INVALID_ARGUMENT
-/// error code is returned.
-///
-/// \retval 0 Success
-///
-/// \retval non-0 See \ref sbe_xip_image_errors
-int
-sbe_xip_host2pore(const void* i_image, 
-                  void* i_hostAddress,
-                  uint64_t* o_poreAddress);
-
-
-/// \defgroup sbe_xip_image_errors Error codes from SBE-XIP image APIs
-///
-/// @{
-
-/// A putative SBE-XIP image does not have the correct magic number, or
-/// contains some other major inconsistency.
-#define SBE_XIP_IMAGE_ERROR 1
-
-/// The TOC may be missing, partially present or may have an alignment problem.
-#define SBE_XIP_TOC_ERROR 2
-
-/// A named item was not found in the SBE-XIP TOC, or a putative HALT address
-/// is not associated with a halt code in .halt.
-#define SBE_XIP_ITEM_NOT_FOUND 3
-
-/// A named item appears in the SBE-XIP TOC, but the data is not present in
-/// the image.  This error can occur if sections have been deleted from the
-/// image.
-#define SBE_XIP_DATA_NOT_PRESENT 4
-
-/// A named item appears in the SBE-XIP TOC, but the data can not be
-/// modified. This error will occur if an attempt is made to modify an
-/// address-only entry.
-#define SBE_XIP_CANT_MODIFY 5
-
-/// A direct or implied argument is invalid, e.g. an illegal data type or
-/// section identifier, or an address not contained within the image.
-#define SBE_XIP_INVALID_ARGUMENT 6
-
-/// A data type mismatch or an illegal type was specified or implied for an
-/// operation. 
-#define SBE_XIP_TYPE_ERROR 7
-
-/// A bug in an SBE-XIP image API
-#define SBE_XIP_BUG 8
-
-/// The image must first be normalized with sbe_xip_normalize().
-#define SBE_XIP_NOT_NORMALIZED 9
-
-/// Attempt to delete a non-empty section that is not the final section of the
-/// image, or an attempt to append data to a non-empty section that is not the
-/// final section of the image, or an attempt to operate on an empty section
-/// for those APIs that prohibit this.
-#define SBE_XIP_SECTION_ERROR 10
-
-/// An address translation API returned a PORE address that was not at least
-/// 4-byte aligned, or alignment violations were observed by
-/// sbe_xip_validate() or sbe_xip_append().
-#define SBE_XIP_ALIGNMENT_ERROR 11
-
-/// An API that performs dynamic memory allocation was unable to allocate
-/// memory. 
-#define SBE_XIP_NO_MEMORY 12
-
-/// Attempt to get or set a vector element with an index that is outside of
-/// the declared bounds of the vector.
-#define SBE_XIP_BOUNDS_ERROR 13
-
-/// Attempt to grow the image past its defined memory allocation
-#define SBE_XIP_WOULD_OVERFLOW 14
-
-/// Error associated with the disassembler occured.
-#define SBE_XIP_DISASSEMBLER_ERROR 15
-
-/// hash collision creating the .fixed_toc section
-#define SBE_XIP_HASH_COLLISION 16
-
-/// Applications can expand this macro to declare an array of string forms of
-/// the error codes if desired.
-#define SBE_XIP_ERROR_STRINGS(var)              \
-    const char* var[] = {                       \
-        "Success",                              \
-        "SBE_XIP_IMAGE_ERROR",                  \
-        "SBE_XIP_TOC_ERROR",                    \
-        "SBE_XIP_ITEM_NOT_FOUND",               \
-        "SBE_XIP_DATA_NOT_PRESENT",             \
-        "SBE_XIP_CANT_MODIFY",                  \
-        "SBE_XIP_INVALID_ARGUMENT",             \
-        "SBE_XIP_TYPE_ERROR",                   \
-        "SBE_XIP_BUG",                          \
-        "SBE_XIP_NOT_NORMALIZED",               \
-        "SBE_XIP_SECTION_ERROR",                \
-        "SBE_XIP_ALIGNMENT_ERROR",              \
-        "SBE_XIP_NO_MEMORY",                    \
-        "SBE_XIP_BOUNDS_ERROR",                 \
-        "SBE_XIP_WOULD_OVERFLOW",               \
-        "SBE_XIP_DISASSEMBLER_ERROR",           \
-        "SBE_XIP_HASH_COLLISION",               \
-    }
-
-/// Applications can use this macro to safely index the array of error
-/// strings. 
-#define SBE_XIP_ERROR_STRING(var, n)                                   \
-    ((((n) < 0) || ((n) > (int)(sizeof(var) / sizeof(char*)))) ?        \
-     "Bug : Invalid SBE-XIP error code" : var[n])
-
-/// @}
-
-/// Disassembler error codes.
-#define DIS_IMAGE_ERROR                   1
-#define DIS_MEMORY_ERROR                  2
-#define DIS_DISASM_ERROR                  3
-#define DIS_RING_NAME_ADDR_MATCH_SUCCESS  4
-#define DIS_RING_NAME_ADDR_MATCH_FAILURE  5
-#define DIS_TOO_MANY_DISASM_WARNINGS      6
-#define DIS_DISASM_TROUBLES               7
-
-#define DIS_ERROR_STRINGS(var)              \
-    const char* var[] = {                   \
-        "Success",                          \
-        "DIS_IMAGE_ERROR",                  \
-        "DIS_MEMORY_ERROR",                 \
-        "DIS_DISASM_ERROR",                 \
-        "DIS_RING_NAME_ADDR_MATCH_SUCCESS", \
-        "DIS_RING_NAME_ADDR_MATCH_FAILURE", \
-        "DIS_TOO_MANY_DISASM_WARNINGS",     \
-        "DIS_DISASM_TROUBLES",              \
-    }
-
-#define DIS_ERROR_STRING(var, n)                                   \
-    ((((n) < 0) || ((n) > (int)(sizeof(var) / sizeof(char*)))) ?        \
-     "Bug : Invalid DIS error code" : var[n])
-
-#if 0
-{ /* So __cplusplus doesn't mess w/auto-indent */
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif  // __ASSEMBLER__
-
-
-////////////////////////////////////////////////////////////////////////////
-// Assembler Definitions
-////////////////////////////////////////////////////////////////////////////
-
-#ifdef __ASSEMBLER__
-
-/// Create an XIP TOC entry
-///
-/// \param[in] index The string form of the \a index symbol is created and
-/// linked from the TOC entry to allow external search procedures to locate
-/// the \a address.
-///
-/// \param[in] type One of the SBE_XIP_* type constants; See \ref
-/// sbe_xip_toc_types.
-///
-/// \param[in] address The address of the idexed code or data; This wlll
-/// typically be a symbol.
-///
-/// \param[in] elements <Optional> For vector types, number of elements in the
-/// vector, which is limited to an 8-bit unsigned integer.  This parameter
-/// defaults to 1 which indicates a scalar type. Declaring a vector with 0
-/// elements disables bounds checking on vector accesses, and can be used if
-/// very large or indeterminate sized vectors are required. The TOC format
-/// does not support vectors of strings or addresses.
-///
-/// The \c .xip_toc macro creates a XIP Table of Contents (TOC) structure in
-/// the \c .toc section, as specified by the parameters.  This macro is
-/// typically not used directly in assembly code.  Instead programmers should
-/// use .xip_quad, .xip_quada, .xip_quadia, .xip_address, .xip_string or
-/// .xip_cvs_revision.
-
-        .macro  .xip_toc, index:req, type:req, address:req, elements=1
-
-	.if	(((\type) < 1) || ((\type) > SBE_XIP_MAX_TYPE_INDEX))
-	.error	".xip_toc : Illegal type index"
-	.endif
-
-        // First push into the .strings section to lay down the
-        // string form of the index name under a local label.
-
-        .pushsection .strings
-7667862:        
-        .asciz  "\index"
-        .popsection
-
-        // Now the 12-byte TOC entry is created.  Push into the .toc section
-	// and lay down the first 4 bytes which are always a pointer to the
-	// string just declared.  The next 4 bytes are the address of the data
-	// (or the address itself in the case of address types). The final 4
-	// bytes are the type, section (always 0 prior to normalization),
-	// number of elements, and a padding byte.
-
-	.pushsection .toc
-	
-	.long	7667862b, (\address)
-	.byte	(\type), 0, (\elements), 0
-
-	.popsection
-
-	.endm
-
-
-/// Allocate and initialize 64-bit global scalar or vector data and create the
-/// TOC entry.
-///
-/// \param[in] symbol The name of the scalar or vector; this name is also used
-/// as the TOC index of the data.
-///
-/// \param[in] init The initial value of (each element of) the data.
-/// This is a 64-bit integer; To allocate address pointers use .xip_quada.
-///
-/// \param[in] elements The number of 64-bit elements in the data structure,
-/// defaulting to 1, with a maximum value of 255.
-///
-/// \param[in] section The section where the data will be allocated,
-/// default depends on the memory space
-
-	.macro	.xip_quad, symbol:req, init:req, elements=1, section
-
-        ..xip_quad_helper .quad, \symbol, (\init), (\elements), \section
-
-	.endm
-
-
-/// Allocate and initialize 64-bit global scalar or vector data containing a
-/// relocatable address in and create the TOC entry.
-///
-/// \param[in] symbol The name of the scalar or vector; this name is also used
-/// as the TOC index of the data.
-///
-/// \param[in] init The initial value of (each element of) the data.  This
-/// will typically be a symbolic address. If the intention is to define an
-/// address that will always be filled in later by image manipulation tools,
-/// then use the .xip_quad macro with a 0 initial value.
-///
-/// \param[in] elements The number of 64-bit elements in the data structure,
-/// defaulting to 1, with a maximum value of 255.
-///
-/// \param[in] section The section where the data will be allocated,
-/// default depends on the memory space
-
-	.macro	.xip_quada, symbol:req, offset:req, elements=1, section
-
-	..xip_quad_helper .quada, \symbol, (\offset), (\elements), \section
-
-	.endm
-
-
-/// Helper for .xip_quad and .xip_quada
-
-        .macro	..xip_quad_helper, directive, symbol, init, elements, section
-	
-	.if	(((\elements) < 1) || ((\elements) > 255))
-	.error	"The number of vector elements must be in the range 1..255"
-	.endif
-
-	..xip_pushsection \section
-	.balign 8
-
-	.global	\symbol
-\symbol\():
-	.rept	(\elements)
-        \directive (\init)
-	.endr
-
-	.popsection
-
-	.xip_toc \symbol, SBE_XIP_UINT64, \symbol, (\elements)
-
-	.endm
-
-
-/// Allocate and initialize 64-bit global scalar or vector data containing
-/// full 64-bit addresses and create a TOC entry
-///
-/// \param[in] symbol The name of the scalar or vector; this name is also used
-/// as the TOC index of the data.
-///
-/// \param[in] space A valid PORE memory space descriptor
-///
-/// \param[in] offset A 32-bit relocatable offset
-///
-/// \param[in] elements The number of 64-bit elements in the data structure,
-/// defaulting to 1, with a maximum value of 255.
-///
-/// \param[in] section The section where the data will be allocated,
-/// default depends on the memory space
-
-         .macro	.xip_quadia, symbol:req, space:req, offset:req, \
-		 elements=1, section
-
-	.if	(((\elements) < 1) || ((\elements) > 255))
-	.error	"The number of vector elements must be in the range 1..255"
-	.endif
-
-	..xip_pushsection \section
-	.balign	8
-
-	.global	\symbol
-\symbol\():	
-	.rept	(\elements)
-	.quadia	(\space), (\offset)
-	.endr
-	
-	.popsection
-
-	.xip_toc \symbol, SBE_XIP_UINT64, \symbol, (\elements)
-
-	.endm
-
-/// Default push into .ipl_data unless in an OCI space, then .data
-
-	.macro	..xip_pushsection, section
-
-	.ifnb	\section
-	.pushsection \section
-	.else
-	.if	(_PGAS_DEFAULT_SPACE == PORE_SPACE_OCI)
-	.pushsection .data
-	.else
-	.pushsection .ipl_data
-	.endif
-	.endif
-             
-	.balign	8            
-
-	.endm
-
-/// Allocate and initialize a string in .strings
-///
-/// \param[in] index The string will be stored in the TOC using this index
-/// symbol.
-///
-/// \param[in] string The string to be allocated in .strings. String space is
-/// fixed once allocated.  Strings designed to be overwritten by external tools
-/// should be allocated to be as long as eventually needed (e.g., by a string
-/// of blanks.)
-
-	.macro	.xip_string, index:req, string:req
-
-	.pushsection .strings
-7874647:                       
-	.asciz	"\string"
-	.popsection
-
-	.xip_toc \index, SBE_XIP_STRING, 7874647b
-
-	.endm
-
-
-/// Allocate and initialize a CVS Revison string in .strings
-///
-/// \param[in] index The string will be stored in the TOC using this index
-/// symbol.
-///
-/// \param[in] string A CVS revision string to be allocated in .strings.  CVS
-/// revision strings are formatted by stripping out and only storing the
-/// actual revision number :
-///
-/// \code
-///     "$Revision <n>.<m> $" -> "<n>.<m>"
-/// \endcode
-	
-
-	.macro	.xip_cvs_revision, index:req, string:req
-
-	.pushsection .strings
-7874647:        
-	..cvs_revision_string "\string"
-	.popsection
-
-	.xip_toc \index, SBE_XIP_STRING, 7874647b
-
-	.endm
-
-
-/// Shorthand to create a TOC entry for an address
-/// 
-/// \param[in] index The symbol will be indexed as this name
-///
-/// \param[in] symbol <Optional> The symbol to index; by default the same as
-/// the index.
-
-	.macro	.xip_address, index:req, symbol
-             
-	.ifb	\symbol
-	.xip_toc \index, SBE_XIP_ADDRESS, \index
-	.else
-	.xip_toc \index, SBE_XIP_ADDRESS, \symbol
-	.endif
-
-	.endm
-
-
-/// Edit and allocate a CVS revision string
-///
-/// CVS revision strings are formatted by stripping out and only storing the
-/// actual revision number :
-/// \code
-///     "$Revision <n>.<m> $" -> "<n>.<m>"
-/// \endcode
-	
-	.macro	..cvs_revision_string, rev:req
-	.irpc	c, \rev
-	.ifnc	"\c", "$"
-	.ifnc	"\c", "R"
-	.ifnc	"\c", "e"
-	.ifnc	"\c", "v"
-	.ifnc	"\c", "i"
-	.ifnc	"\c", "s"
-	.ifnc	"\c", "i"
-	.ifnc	"\c", "o"
-	.ifnc	"\c", "n"
-	.ifnc	"\c", ":"
-	.ifnc	"\c", " "
-	.ascii	"\c"
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endif
-	.endr
-	.byte	0
-	.endm
-
-#endif // __ASSEMBLER__
-
-#endif  // __SBE_XIP_TOC_H
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C b/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C
deleted file mode 100644
index 963ae13d8..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C
+++ /dev/null
@@ -1,844 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: p8_mailbox_utils.C,v 1.10 2015/08/13 14:22:22 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_mailbox_utils.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *|
-// *! TITLE       : proc_mailbox_utils.C
-// *! DESCRIPTION : Functions to calculate the mailbox values
-// *!
-// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
-// *! BACKUP NAME : TBD                     Email: TBD@us.ibm.com
-// *!
-// *! Overview:
-// *!    Utility functions to calculate each mailbox value
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "p8_mailbox_utils.H"
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-using namespace fapi;
-
-//------------------------------------------------------------------------------
-// function:
-//      Translate a VRM-11 VID code to a voltage value
-//
-//
-// parameters: i_vid_7_0    VRM-11 VID code
-//              o_voltage   Voltage in .01mv units
-//
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode vid2mv(uint8_t i_vid_7_0, uint32_t &o_voltage)
-{
-    fapi::ReturnCode l_fapirc;
-
-    switch(i_vid_7_0)
-    {
-        case      0x1   : o_voltage =  0    ; break;
-        case      0x2   : o_voltage =160000 ; break;
-        case      0x3   : o_voltage =159375 ; break;
-        case      0x4   : o_voltage =158750 ; break;
-        case      0x5   : o_voltage =158125 ; break;
-        case      0x6   : o_voltage =157500 ; break;
-        case      0x7   : o_voltage =156875 ; break;
-        case      0x8   : o_voltage =156250 ; break;
-        case      0x9   : o_voltage =155625 ; break;
-        case      0xA   : o_voltage =155000 ; break;
-        case      0xB   : o_voltage =154375 ; break;
-        case      0xC   : o_voltage =153750 ; break;
-        case      0xD   : o_voltage =153125 ; break;
-        case      0xE   : o_voltage =152500 ; break;
-        case      0xF   : o_voltage =151875 ; break;
-        case      0x10  : o_voltage =151250 ; break;
-        case      0x11  : o_voltage =150625 ; break;
-        case      0x12  : o_voltage =150000 ; break;
-        case      0x13  : o_voltage =149375 ; break;
-        case      0x14  : o_voltage =148750 ; break;
-        case      0x15  : o_voltage =148125 ; break;
-        case      0x16  : o_voltage =147500 ; break;
-        case      0x17  : o_voltage =146875 ; break;
-        case      0x18  : o_voltage =146250 ; break;
-        case      0x19  : o_voltage =145625 ; break;
-        case      0x1A  : o_voltage =145000 ; break;
-        case      0x1B  : o_voltage =144375 ; break;
-        case      0x1C  : o_voltage =143750 ; break;
-        case      0x1D  : o_voltage =143125 ; break;
-        case      0x1E  : o_voltage =142500 ; break;
-        case      0x1F  : o_voltage =141875 ; break;
-        case      0x20  : o_voltage =141250 ; break;
-        case      0x21  : o_voltage =140625 ; break;
-        case      0x22  : o_voltage =140000 ; break;
-        case      0x23  : o_voltage =139375 ; break;
-        case      0x24  : o_voltage =138750 ; break;
-        case      0x25  : o_voltage =138125 ; break;
-        case      0x26  : o_voltage =137500 ; break;
-        case      0x27  : o_voltage =136875 ; break;
-        case      0x28  : o_voltage =136250 ; break;
-        case      0x29  : o_voltage =135625 ; break;
-        case      0x2a  : o_voltage =135000 ; break;
-        case      0x2b  : o_voltage =134375 ; break;
-        case      0x2c  : o_voltage =133750 ; break;
-        case      0x2d  : o_voltage =133125 ; break;
-        case      0x2e  : o_voltage =132500 ; break;
-        case      0x2f  : o_voltage =131875 ; break;
-        case      0x30  : o_voltage =131250 ; break;
-        case      0x31  : o_voltage =130625 ; break;
-        case      0x32  : o_voltage =130000 ; break;
-        case      0x33  : o_voltage =129375 ; break;
-        case      0x34  : o_voltage =128750 ; break;
-        case      0x35  : o_voltage =128125 ; break;
-        case      0x36  : o_voltage =127500 ; break;
-        case      0x37  : o_voltage =126875 ; break;
-        case      0x38  : o_voltage =126250 ; break;
-        case      0x39  : o_voltage =125625 ; break;
-        case      0x3a  : o_voltage =125000 ; break;
-        case      0x3b  : o_voltage =124375 ; break;
-        case      0x3c  : o_voltage =123750 ; break;
-        case      0x3d  : o_voltage =123125 ; break;
-        case      0x3e  : o_voltage =122500 ; break;
-        case      0x3f  : o_voltage =121875 ; break;
-        case      0x40  : o_voltage =121250 ; break;
-        case      0x41  : o_voltage =120625 ; break;
-        case      0x42  : o_voltage =120000 ; break;
-        case      0x43  : o_voltage =119375 ; break;
-        case      0x44  : o_voltage =118750 ; break;
-        case      0x45  : o_voltage =118125 ; break;
-        case      0x46  : o_voltage =117500 ; break;
-        case      0x47  : o_voltage =116875 ; break;
-        case      0x48  : o_voltage =116250 ; break;
-        case      0x49  : o_voltage =115625 ; break;
-        case      0x4a  : o_voltage =115000 ; break;
-        case      0x4b  : o_voltage =114375 ; break;
-        case      0x4c  : o_voltage =113750 ; break;
-        case      0x4d  : o_voltage =113125 ; break;
-        case      0x4e  : o_voltage =112500 ; break;
-        case      0x4f  : o_voltage =111875 ; break;
-        case      0x50  : o_voltage =111250 ; break;
-        case      0x51  : o_voltage =110625 ; break;
-        case      0x52  : o_voltage =110000 ; break;
-        case      0x53  : o_voltage =109375 ; break;
-        case      0x54  : o_voltage =108750 ; break;
-        case      0x55  : o_voltage =108125 ; break;
-        case      0x56  : o_voltage =107500 ; break;
-        case      0x57  : o_voltage =106875 ; break;
-        case      0x58  : o_voltage =106250 ; break;
-        case      0x59  : o_voltage =105625 ; break;
-        case      0x5a  : o_voltage =105000 ; break;
-        case      0x5b  : o_voltage =104375 ; break;
-        case      0x5c  : o_voltage =103750 ; break;
-        case      0x5d  : o_voltage =103125 ; break;
-        case      0x5e  : o_voltage =102500 ; break;
-        case      0x5f  : o_voltage =101875 ; break;
-        case      0x60  : o_voltage =101250 ; break;
-        case      0x61  : o_voltage =100625 ; break;
-        case      0x62  : o_voltage =100000 ; break;
-        case      0x63  : o_voltage = 99375 ; break;
-        case      0x64  : o_voltage = 98750 ; break;
-        case      0x65  : o_voltage = 98125 ; break;
-        case      0x66  : o_voltage = 97500 ; break;
-        case      0x67  : o_voltage = 96875 ; break;
-        case      0x68  : o_voltage = 96250 ; break;
-        case      0x69  : o_voltage = 95625 ; break;
-        case      0x6a  : o_voltage = 95000 ; break;
-        case      0x6b  : o_voltage = 94375 ; break;
-        case      0x6c  : o_voltage = 93750 ; break;
-        case      0x6d  : o_voltage = 93125 ; break;
-        case      0x6e  : o_voltage = 92500 ; break;
-        case      0x6f  : o_voltage = 91875 ; break;
-        case      0x70  : o_voltage = 91250 ; break;
-        case      0x71  : o_voltage = 90625 ; break;
-        case      0x72  : o_voltage = 90000 ; break;
-        case      0x73  : o_voltage = 89375 ; break;
-        case      0x74  : o_voltage = 88750 ; break;
-        case      0x75  : o_voltage = 88125 ; break;
-        case      0x76  : o_voltage = 87500 ; break;
-        case      0x77  : o_voltage = 86875 ; break;
-        case      0x78  : o_voltage = 86250 ; break;
-        case      0x79  : o_voltage = 85625 ; break;
-        case      0x7a  : o_voltage = 85000 ; break;
-        case      0x7b  : o_voltage = 84375 ; break;
-        case      0x7c  : o_voltage = 83750 ; break;
-        case      0x7d  : o_voltage = 83125 ; break;
-        case      0x7e  : o_voltage = 82500 ; break;
-        case      0x7f  : o_voltage = 81875 ; break;
-        case      0x80  : o_voltage = 81250 ; break;
-        case      0x81  : o_voltage = 80625 ; break;
-        case      0x82  : o_voltage = 80000 ; break;
-        case      0x83  : o_voltage = 79375 ; break;
-        case      0x84  : o_voltage = 78750 ; break;
-        case      0x85  : o_voltage = 78125 ; break;
-        case      0x86  : o_voltage = 77500 ; break;
-        case      0x87  : o_voltage = 76875 ; break;
-        case      0x88  : o_voltage = 76250 ; break;
-        case      0x89  : o_voltage = 75625 ; break;
-        case      0x8a  : o_voltage = 75000 ; break;
-        case      0x8b  : o_voltage = 74375 ; break;
-        case      0x8c  : o_voltage = 73750 ; break;
-        case      0x8d  : o_voltage = 73125 ; break;
-        case      0x8e  : o_voltage = 72500 ; break;
-        case      0x8f  : o_voltage = 71875 ; break;
-        case      0x90  : o_voltage = 71250 ; break;
-        case      0x91  : o_voltage = 70625 ; break;
-        case      0x92  : o_voltage = 70000 ; break;
-        case      0x93  : o_voltage = 69375 ; break;
-        case      0x94  : o_voltage = 68750 ; break;
-        case      0x95  : o_voltage = 68125 ; break;
-        case      0x96  : o_voltage = 67500 ; break;
-        case      0x97  : o_voltage = 66875 ; break;
-        case      0x98  : o_voltage = 66250 ; break;
-        case      0x99  : o_voltage = 65625 ; break;
-        case      0x9a  : o_voltage = 65000 ; break;
-        case      0x9b  : o_voltage = 64375 ; break;
-        case      0x9c  : o_voltage = 63750 ; break;
-        case      0x9d  : o_voltage = 63125 ; break;
-        case      0x9e  : o_voltage = 62500 ; break;
-        case      0x9f  : o_voltage = 61875 ; break;
-        case      0xa0  : o_voltage = 61250 ; break;
-        case      0xa1  : o_voltage = 60625 ; break;
-        case      0xa2  : o_voltage = 60000 ; break;
-        case      0xa3  : o_voltage = 59375 ; break;
-        case      0xa4  : o_voltage = 58750 ; break;
-        case      0xa5  : o_voltage = 58125 ; break;
-        case      0xa6  : o_voltage = 57500 ; break;
-        case      0xa7  : o_voltage = 56875 ; break;
-        case      0xa8  : o_voltage = 56250 ; break;
-        case      0xa9  : o_voltage = 55625 ; break;
-        case      0xaa  : o_voltage = 55000 ; break;
-        case      0xab  : o_voltage = 54375 ; break;
-        case      0xac  : o_voltage = 53750 ; break;
-        case      0xad  : o_voltage = 53125 ; break;
-        case      0xae  : o_voltage = 52500 ; break;
-        case      0xaf  : o_voltage = 51875 ; break;
-        case      0xb0  : o_voltage = 51250 ; break;
-        case      0xb1  : o_voltage = 50625 ; break;
-        case      0xb2  : o_voltage = 50000 ; break;
-        case      0xb3  : o_voltage = 49375 ; break;
-        case      0xb4  : o_voltage = 48750 ; break;
-        case      0xb5  : o_voltage = 48125 ; break;
-        case      0xb6  : o_voltage = 47500 ; break;
-        case      0xb7  : o_voltage = 46875 ; break;
-        case      0xb8  : o_voltage = 46250 ; break;
-        case      0xb9  : o_voltage = 45625 ; break;
-        case      0xba  : o_voltage = 45000 ; break;
-        case      0xbb  : o_voltage = 44375 ; break;
-        case      0xbc  : o_voltage = 43750 ; break;
-        case      0xbd  : o_voltage = 43125 ; break;
-        case      0xbe  : o_voltage = 42500 ; break;
-        case      0xbf  : o_voltage = 41875 ; break;
-        case      0xc0  : o_voltage = 41250 ; break;
-        case      0xc1  : o_voltage = 40625 ; break;
-        case      0xc2  : o_voltage = 40000 ; break;
-        case      0xc3  : o_voltage = 39375 ; break;
-        case      0xc4  : o_voltage = 38750 ; break;
-        case      0xc5  : o_voltage = 38125 ; break;
-        case      0xc6  : o_voltage = 37500 ; break;
-        case      0xc7  : o_voltage = 36875 ; break;
-        case      0xc8  : o_voltage = 36250 ; break;
-        case      0xc9  : o_voltage = 35625 ; break;
-        case      0xca  : o_voltage = 35000 ; break;
-        case      0xcb  : o_voltage = 34375 ; break;
-        case      0xcc  : o_voltage = 33750 ; break;
-        case      0xcd  : o_voltage = 33125 ; break;
-        case      0xce  : o_voltage = 32500 ; break;
-        case      0xcf  : o_voltage = 31875 ; break;
-        case      0xd0  : o_voltage = 31250 ; break;
-        case      0xd1  : o_voltage = 30625 ; break;
-        case      0xd2  : o_voltage = 30000 ; break;
-        case      0xd3  : o_voltage = 29375 ; break;
-        case      0xd4  : o_voltage = 28750 ; break;
-        case      0xd5  : o_voltage = 28125 ; break;
-        case      0xd6  : o_voltage = 27500 ; break;
-        case      0xd7  : o_voltage = 26875 ; break;
-        case      0xd8  : o_voltage = 26250 ; break;
-        case      0xd9  : o_voltage = 25625 ; break;
-        case      0xda  : o_voltage = 25000 ; break;
-        case      0xdb  : o_voltage = 24375 ; break;
-        case      0xdc  : o_voltage = 23750 ; break;
-        case      0xdd  : o_voltage = 23125 ; break;
-        case      0xde  : o_voltage = 22500 ; break;
-        case      0xdf  : o_voltage = 21875 ; break;
-        case      0xe0  : o_voltage = 21250 ; break;
-        case      0xe1  : o_voltage = 20625 ; break;
-        case      0xe2  : o_voltage = 20000 ; break;
-        case      0xe3  : o_voltage = 19375 ; break;
-        case      0xe4  : o_voltage = 18750 ; break;
-        case      0xe5  : o_voltage = 18125 ; break;
-        case      0xe6  : o_voltage = 17500 ; break;
-        case      0xe7  : o_voltage = 16875 ; break;
-        case      0xe8  : o_voltage = 16250 ; break;
-        case      0xe9  : o_voltage = 15625 ; break;
-        case      0xea  : o_voltage = 15000 ; break;
-        case      0xeb  : o_voltage = 14375 ; break;
-        case      0xec  : o_voltage = 13750 ; break;
-        case      0xed  : o_voltage = 13125 ; break;
-        case      0xee  : o_voltage = 12500 ; break;
-        case      0xef  : o_voltage = 11875 ; break;
-        case      0xf0  : o_voltage = 11250 ; break;
-        case      0xf1  : o_voltage = 10625 ; break;
-        case      0xf2  : o_voltage = 10000 ; break;
-        case      0xf3  : o_voltage = 9375  ; break;
-        case      0xf4  : o_voltage = 8750  ; break;
-        case      0xf5  : o_voltage = 8125  ; break;
-        case      0xf6  : o_voltage = 7500  ; break;
-        case      0xf7  : o_voltage = 6875  ; break;
-        case      0xf8  : o_voltage = 6250  ; break;
-        case      0xf9  : o_voltage = 5625  ; break;
-        case      0xfa  : o_voltage = 5000  ; break;
-        case      0xfb  : o_voltage = 4375  ; break;
-        case      0xfc  : o_voltage = 3750  ; break;
-        case      0xfd  : o_voltage = 3125  ; break;
-      //case      0xfe  : o_voltage = 0     ; break;
-      //case      0xff  : o_voltage = 0     ; break;
-        default         : o_voltage = 100000;
-    }
-
-    return l_fapirc;
-}
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 1
-//      (standalone_mbox0_value)
-//
-//  Mailbox scratch 1 (CFAM 2838, SCOM 0x50038)
-//
-//  Bytes 0,1   Boot frequency
-//  Boot Frequency info (power management def file DPS min (% drop from
-//  nominal), must cross checking between f_vmin and DPS min)
-//  This is a multiplier of the processor refclk frequency based on the
-//  the DPLL DIVIDER.
-//
-//  Bytes 2,3 EX Gard records
-//  FSP provides a vector for SBE to communicate the guareded EX chiplets
-//  Bits    0..3    4..7    8..11   12..15  16..19  20..23  24..27  28..31
-//                  0x0000                          EX guard bits
-//  One Guard bit per EX chiplet, bit location aligned to chiplet ID
-//  (bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
-//  Guarded EX chiplets are marked by a '0'.
-//
-// parameters: i_target           Reference to the processor chip target
-//             o_set_data         The 32-bit mailbox value
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox1( const fapi::Target &i_target, uint32_t & o_set_data )
-{
-    fapi::ReturnCode l_fapirc;
-
-    const uint32_t  BOOT_FREQ_BIT_POSITION      =   0;
-    const uint32_t  BOOT_FREQ_BIT_LENGTH        =   16;
-    const uint32_t  EX_GARD_BITS_BIT_POSITION   =   16;
-    const uint32_t  EX_GARD_BITS_BIT_LENGTH     =   16;
-
-    do
-    {
-        o_set_data = 0;
-
-        //  boot freq should have been calculated earlier
-        //  and stored in system attribute ATTR_BOOT_FREQ_MHZ
-        fapi::ATTR_BOOT_FREQ_MHZ_Type l_boot_freq =   0 ;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_BOOT_FREQ_MHZ,
-                                    NULL,
-                                    l_boot_freq );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_BOOT_FREQ_MHZ failed");
-            break;
-        }
-        FAPI_INF(   "ATTR_BOOT_FREQ_MHZ = 0x%08x => %dMHz",
-                        l_boot_freq, l_boot_freq);
-                        
-        uint32_t l_refclk_freq =   0;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_FREQ_PROC_REFCLOCK, NULL, l_refclk_freq );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_FREQ_PROC_REFCLOCK failed");
-            break;
-        }
-
-        FAPI_INF(   "ATTR_FREQ_PROC_REFCLOCK = 0x%08x  => %dMHz",
-                        l_refclk_freq, l_refclk_freq );
-
-        if (!l_refclk_freq)
-        {
-            FAPI_ERR("Attribute ATTR_FREQ_PROC_REFCLOCK failed must be non-zero");
-            uint32_t & REF_FREQ = l_refclk_freq;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_P8_MAILBOX_UTILS_PROC_REFCLK_ZERO_ERROR);
-            break;
-        }
-
-        uint32_t l_dpll_divider = 4;
-        FAPI_DBG("Setting DPLL divider to %01x", l_dpll_divider);
-        l_fapirc = FAPI_ATTR_SET(ATTR_PROC_DPLL_DIVIDER, &i_target, l_dpll_divider );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiSetAttribute of ATTR_PROC_DPLL_DIVIDER failed");
-            break;
-        }
-
-        // Calculate the multiplier that is stored into the mailbox
-
-        // Check bounds and avoid unnecessary fp math
-//         uint32_t l_freq_mult = (uint32_t)floor(
-//                                     ( float)l_boot_freq /
-//                                     ((float)l_refclk_freq / l_dpll_divider));
-        uint64_t l_result = (((uint64_t)l_dpll_divider)*l_boot_freq)/l_refclk_freq;
-        if( l_result >> BOOT_FREQ_BIT_LENGTH )
-        {
-            FAPI_ERR("DPLL multiplier (%lld) won't fit in the bit field (%i bits max)", 
-                     l_result, BOOT_FREQ_BIT_LENGTH);
-            uint32_t & BOOT_FREQ = l_boot_freq;
-            uint32_t & REF_FREQ  = l_refclk_freq;
-            uint32_t & DPLL_DIV  = l_dpll_divider;
-            uint64_t & FREQ_MULT = l_result;
-            const uint32_t & MAX_BITS  = BOOT_FREQ_BIT_LENGTH;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_P8_MAILBOX_UTILS_FREQ_MULT_OOB_ERROR);
-            break;
-        }
-        uint32_t l_freq_mult = (uint32_t)l_result;
-
-        FAPI_DBG("Boot frequency multiplier %04x", l_freq_mult);
-
-        o_set_data = l_freq_mult << (sizeof(o_set_data)*8 -
-                                     BOOT_FREQ_BIT_POSITION -
-                                     BOOT_FREQ_BIT_LENGTH);
-
-
-        //  Calculate the gard record here, ATTR_EX_GARD_BITS is probably not
-        //  needed.
-        uint32_t l_ex_gard_bits    =   0x0000ffff;
-        std::vector<fapi::Target>  l_fapiCores;
-        l_fapirc = fapiGetChildChiplets( i_target,
-                                         fapi::TARGET_TYPE_EX_CHIPLET,
-                                         l_fapiCores,
-                                         fapi::TARGET_STATE_FUNCTIONAL );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetChildChiplets failed");
-            break;
-        }
-
-        FAPI_INF( "Found %zd EX cores",
-                  l_fapiCores.size()    );
-
-        //  Note: Functional chips are marked with a 0 bit; NOT a one bit.
-        //  CLEAR a bit for all functional EX chiplets in the vector:
-        //  (bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
-
-        //  HWAS will eventually take into account Mfg Partial Good,
-        //  Mfg Core Overrride, and Gard data records from previous fails;
-        //  we should only have to filter for functional chips here.
-        for ( uint32_t l_coreNum=0; l_coreNum<l_fapiCores.size(); l_coreNum++ )
-        {
-            fapi::ATTR_CHIP_UNIT_POS_Type  l_unit  =   0;
-            l_fapirc    =   FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS,
-                                           &l_fapiCores[l_coreNum],
-                                           l_unit  );
-            if ( l_fapirc )
-            {
-                // oops, bail out of loop with fapirc set
-                break;
-            }
-            l_ex_gard_bits &=   ~(( 0x00008000 >> l_unit ));
-        }   // endfor
-
-        if ( l_fapirc )
-        {
-            FAPI_ERR( "FAILED to retrieve ATTR_CHIP_UNIT_POS" );
-            break;
-        }
-
-        FAPI_INF( "l_ex_gard_bits = 0x%08x", l_ex_gard_bits );
-
-        o_set_data |= l_ex_gard_bits << (sizeof(o_set_data)*8 -
-                                         EX_GARD_BITS_BIT_POSITION -
-                                         EX_GARD_BITS_BIT_LENGTH);
-
-        FAPI_INF(   "Return Mailbox 1 value (standalone_mbox0_value) =  0x%08x",
-                    o_set_data   );
-    } while (0);
-
-    return l_fapirc;
-}
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 2
-//      (standalone_mbox1_value)
-//
-//  Bit 0 in this register is used to indicate a MPIPL
-//  - The MPI flag will be evaluated by proc_sbe_ipl_seeprom to distinguish
-//    between a normal and a memory preserving IPL
-//  - attribute ATTR_IS_MPIPL will indicate MPIPL or not.
-//  FSP provides a MPI (Memory Preserving IPL) flag and settings for the I2C
-//  master bus speed calculation
-//  Bits    | 0     |   1 2 3   |   4..7    8..11   12..15                    |
-//          | MPI   |   000     | PIB I2C master Bit Rate Divisor (@refclock) |
-//
-//          |    16..19             20..23  24..27  28..31                    |
-//          |               PIB I2C master Bit Rate Divisor (@PLL)            |
-//
-// parameters: i_target           Reference to the chip target
-//             o_set_data         The 32-bit mailbox value
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox2( const fapi::Target &i_target, uint32_t & o_set_data )
-{
-    fapi::ReturnCode l_fapirc;
-
-    const uint32_t  PIB_I2C_REFCLOCK_BIT_POSITION   =   4;
-    const uint32_t  PIB_I2C_REFCLOCK_BIT_LENGTH     =   12;
-    const uint32_t  PIB_I2C_NEST_PLL_BIT_POSITION   =   16;
-    const uint32_t  PIB_I2C_NEST_PLL_BIT_LENGTH     =   16;
-
-
-    do
-    {
-        //  get system attribute ATTR_IS_MPIPL
-        fapi::ATTR_IS_MPIPL_Type    l_isMpIpl   =   0x00;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_IS_MPIPL,
-                                    NULL,
-                                    l_isMpIpl );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_IS_MPIPL failed");
-            break;
-        }
-
-        FAPI_INF(   "ATTR_IS_MPIPL=0x%08x",
-                    l_isMpIpl );
-
-        if ( l_isMpIpl )
-        {
-            o_set_data = 1 << (sizeof(o_set_data)*8 - 1);
-        }
-        else
-        {
-            o_set_data = 0;
-        }
-
-        //  get system attribute ATTR_PIB_I2C_REFCLOCK
-        fapi::ATTR_PIB_I2C_REFCLOCK_Type    l_pib_i2c_refclock =   0;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_PIB_I2C_REFCLOCK,
-                                    NULL,
-                                    l_pib_i2c_refclock );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_PIB_I2C_REFCLOCK failed");
-            break;
-        }
-
-        FAPI_INF(   "ATTR_PIB_I2C_REFCLOCK=0x%08x",
-                    l_pib_i2c_refclock );
-
-        //  get system attribute ATTR_PIB_I2C_NEST_PLL
-        fapi::ATTR_PIB_I2C_NEST_PLL_Type    l_pib_i2c_nest_pll  =   0;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_PIB_I2C_NEST_PLL,
-                                    NULL,
-                                    l_pib_i2c_nest_pll );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_PIB_I2C_NEST_PLL failed");
-            break;
-        }
-
-        FAPI_INF(   "ATTR_PIB_I2C_NEST_PLL=0x%08x",
-                    l_pib_i2c_nest_pll );
-
-
-        //For normal IPLs set initial SBE I2C freq to ref clock
-        //For MPIPL set initial SBE I2C freq to nest clock 
-        if ( !l_isMpIpl )
-        {
-            o_set_data |= l_pib_i2c_refclock << (sizeof(o_set_data)*8 -
-                                                 PIB_I2C_REFCLOCK_BIT_POSITION -
-                                                 PIB_I2C_REFCLOCK_BIT_LENGTH);
-        }
-        else
-        {
-            o_set_data |= l_pib_i2c_nest_pll << (sizeof(o_set_data)*8 -
-                                                PIB_I2C_REFCLOCK_BIT_POSITION -
-                                                PIB_I2C_REFCLOCK_BIT_LENGTH);
-        }
-
-        //Nest ref clock is the same between Normal and MPIPLs
-        o_set_data |= l_pib_i2c_nest_pll << (sizeof(o_set_data)*8 -
-                                             PIB_I2C_NEST_PLL_BIT_POSITION -
-                                             PIB_I2C_NEST_PLL_BIT_LENGTH    );
-
-        FAPI_INF(   "Return Mailbox 2 value (standalone_mbox1_value) =  0x%08x",
-                    o_set_data   );
-
-    } while (0);
-
-    return l_fapirc;
-}
-
-
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 3
-//      (standalone_mbox2_value)
-//
-//  32bit address of location of Hostboot image header (first block of data)
-//  This is offset using an algorithm to compensate for ECC -
-//  see Feature 862671 (fips810): hb pnor offset
-//
-// parameters: i_target           Reference to the chip target
-//             o_set_data         The 32-bit mailbox value
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox3( const fapi::Target &i_target, uint32_t & o_set_data )
-{
-    fapi::ReturnCode l_fapirc;
-
-    const uint32_t  SBE_IMAGE_OFFSET_BIT_POSITION   =   0;
-    const uint32_t  SBE_IMAGE_OFFSET_BIT_LENGTH     =   32;
-
-    do {
-
-        //  get system attribute ATTR_SBE_IMAGE_OFFSET
-        fapi::ATTR_SBE_IMAGE_OFFSET_Type    l_sbe_image_offset  =   0 ;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_SBE_IMAGE_OFFSET,
-                                    NULL,
-                                    l_sbe_image_offset );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_SBE_IMAGE_OFFSET failed");
-            break;
-        }
-
-        FAPI_INF(   "ATTR_SBE_IMAGE_OFFSET=0x%08x",
-                    l_sbe_image_offset );
-
-        o_set_data = l_sbe_image_offset << (sizeof(o_set_data)*8 -
-                                             SBE_IMAGE_OFFSET_BIT_POSITION -
-                                             SBE_IMAGE_OFFSET_BIT_LENGTH    );
-
-        FAPI_INF(   "Return Mailbox 3 (standalone_mbox2_value) =  0x%08x",
-                    o_set_data   );
-
-    } while (0);
-
-    return l_fapirc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 4
-//
-//  Write Boot Voltage info to scratch pad 4
-//
-//  0:2   -> port enables (3b - system design based:
-//          port 0 for non-redundant systems (100); all ports for non-redundant (111))
-//  3     -> Unused
-//  - current recommended default = 1000b
-//  4:7   -> phase enables (4b - defined by the system power design)
-//  - current recommended default = 0000b
-//  8:15  -> VDD voltage (1B in VRM-11 encoded form - 6.25mV increments)
-//          note: VPD is in 5mV increments
-//  - current recommended default   =   0x52
-//  16:23 -> VCS voltage (1B in VRM-11 encoded form - 6.25mV increments)
-//          note: VPD is in 5mV increments
-//  -current recommended default    =   0x4a
-//  24    -> Force use of SBE scan service for slave chips
-//  25    -> Skip use of SBE interrupt service on master chip
-//  25:27 -> Unused                 =   0x0
-//  28    -> Fabric wrap test       =   MNFG wrap test attribute
-//  29:31 -> Fabric node ID         =   Node ID attribute
-//
-// parameters: i_target           Reference to the chip target
-//             o_set_data         The 32-bit mailbox value
-//             i_write_fbc_data   True if the mailbox value should include fabric wrap
-//                                test/node ID information
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox4( const fapi::Target &i_target, uint32_t & o_set_data,
-                                             bool i_write_fbc_data)
-{
-    fapi::ReturnCode l_fapirc;
-
-    const uint32_t  BOOT_VOLTAGE_INFO_BIT_POSITION   =   0;
-    const uint32_t  BOOT_VOLTAGE_INFO_BIT_LENGTH     =   32;
-    const uint32_t  FORCE_USE_SBE_SLAVE_SCAN_SERVICE = 24;
-    const uint32_t  FORCE_SKIP_SBE_MASTER_INTR_SERVICE = 25;
-    const uint32_t  WRAP_TEST_BIT  = 28;
-    const uint32_t  NODE_ID_BIT_POSITION   = 29;
-    const uint32_t  NODE_ID_BIT_LENGTH     = 3;
-
-    do
-    {
-        //  get system attribute ATTR_PROC_BOOT_VOLTAGE_VID
-        fapi::ATTR_PROC_BOOT_VOLTAGE_VID_Type    l_boot_voltage_info =   0  ;
-        l_fapirc =  FAPI_ATTR_GET(  ATTR_PROC_BOOT_VOLTAGE_VID,
-                                    &i_target,
-                                    l_boot_voltage_info );
-        if  (l_fapirc )
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_PROC_BOOT_VOLTAGE_VID failed");
-            break;
-        }
-
-        FAPI_INF(   "ATTR_PROC_BOOT_VOLTAGE_VID=0x%08x",
-                    l_boot_voltage_info );
-
-        o_set_data = l_boot_voltage_info << (sizeof(o_set_data)*8 -
-                                             BOOT_VOLTAGE_INFO_BIT_POSITION -
-                                             BOOT_VOLTAGE_INFO_BIT_LENGTH    );
-
-        // Decode the value for those interested
-        uint32_t    l_vdd_mv;
-        uint32_t    l_vcs_mv;
-        uint8_t     l_vdd_vid;
-        uint8_t     l_vcs_vid;
-
-        // Extract the VID
-        l_vdd_vid = (uint8_t)(l_boot_voltage_info >> 16 & 0xFF);
-
-        // Translate to voltage
-        l_fapirc = vid2mv(l_vdd_vid, l_vdd_mv);
-        if  (l_fapirc )
-        {
-            FAPI_ERR("Translate of VDD VID to Voltage Failed");
-            break;
-        }
-
-        // Extract the VID
-        l_vcs_vid = (uint8_t)(l_boot_voltage_info >>  8 & 0xFF);
-
-        // Translate to voltage
-        l_fapirc = vid2mv(l_vcs_vid, l_vcs_mv);
-        if  (l_fapirc )
-        {
-            FAPI_ERR("Translate of VCS VID to Voltage Failed");
-            break;
-        }
-
-        FAPI_INF("Boot VRM-11 VIDs:  VDD = %02X,         VCS = %02X",
-                    l_vdd_vid, l_vcs_vid);
-
-        FAPI_INF("Boot Voltage:      VDD = %1.2f mV, VCS = %1.2f mV",
-                   (float)l_vdd_mv / 100, (float)l_vcs_mv / 100);
-
-
-        fapi::ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE_Type force_use_scan_service = 0;
-        l_fapirc = FAPI_ATTR_GET(ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE, NULL, force_use_scan_service);
-        if (l_fapirc)
-        {
-                FAPI_ERR("fapiGetAttribute of  ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE failed");
-                break;
-        }
-        FAPI_INF(   "ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE => %d", force_use_scan_service);
-        if (force_use_scan_service == fapi::ENUM_ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE_TRUE)
-        {
-                o_set_data |= 1 << (sizeof(o_set_data)*8 - FORCE_USE_SBE_SLAVE_SCAN_SERVICE - 1);
-        }
-
-        fapi::ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE_Type force_skip_intr_service = 0;
-        l_fapirc = FAPI_ATTR_GET(ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE, NULL, force_skip_intr_service);
-        if (l_fapirc)
-        {
-                FAPI_ERR("fapiGetAttribute of ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE failed");
-                break;
-        }
-        FAPI_INF(   "ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE => %d", force_skip_intr_service);
-        if (force_skip_intr_service == fapi::ENUM_ATTR_FORCE_SKIP_SBE_MASTER_INTR_SERVICE_TRUE)
-        {
-                o_set_data |= 1 << (sizeof(o_set_data)*8 - FORCE_SKIP_SBE_MASTER_INTR_SERVICE - 1);
-        }
-
-        if (i_write_fbc_data)
-        {
-
-            // set wrap test flag (FSP boot)
-            fapi::ATTR_MNFG_FLAGS_Type l_mnfg_flags = 0;
-            l_fapirc =  FAPI_ATTR_GET(  ATTR_MNFG_FLAGS,
-                                        NULL,
-                                        l_mnfg_flags );
-            if (l_fapirc )
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_MNFG_FLAGS failed");
-                break;
-            }
-            FAPI_INF(   "ATTR_MNFG_FLAGS => %016llX", l_mnfg_flags);
-
-            // set legacy node ID valid bit
-            uint8_t set_legacy_node_id_valid = 0;
-            l_fapirc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_SET_LEGACY_NODE_ID_VALID_MBOX_BIT, &i_target, set_legacy_node_id_valid);
-            if (l_fapirc)
-            {
-                FAPI_ERR("fapiGetAttribute of  ATTR_CHIP_EC_FEATURE_SET_LEGACY_NODE_ID_VALID_MBOX_BIT failed");
-                break;
-            }
-
-            if (((l_mnfg_flags & fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_BRAZOS_WRAP_CONFIG) ==
-                 fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_BRAZOS_WRAP_CONFIG) ||
-                (set_legacy_node_id_valid != 0))
-            {
-                o_set_data |= 1 << (sizeof(o_set_data)*8 - WRAP_TEST_BIT - 1);
-            }
-
-            // set node ID (FSP boot)
-            fapi::ATTR_FABRIC_NODE_ID_Type l_node_id =   0 ;
-            l_fapirc =  FAPI_ATTR_GET(  ATTR_FABRIC_NODE_ID,
-                                        &i_target,
-                                        l_node_id );
-            if  (l_fapirc )
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_FABRIC_NODE_ID failed");
-                break;
-            }
-            FAPI_INF(   "ATTR_FABRIC_NODE_ID => %d", l_node_id);
-
-            o_set_data |= l_node_id << (sizeof(o_set_data)*8 -
-                                        NODE_ID_BIT_POSITION -
-                                        NODE_ID_BIT_LENGTH    );
-        }
-
-        FAPI_INF(   "Return Mailbox 4 value (standalone_mbox3_value) =  0x%08x",
-                    o_set_data   );
-
-    } while (0);
-
-    return l_fapirc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.H b/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.H
deleted file mode 100644
index c7715cf3d..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.H
+++ /dev/null
@@ -1,184 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils/p8_mailbox_utils.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: p8_mailbox_utils.H,v 1.2 2014/02/26 04:58:11 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/p8_mailbox_utils.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_mailbox_utils.H
-// *! DESCRIPTION : Functions to calculate the mailbox values
-// *!
-// *! OWNER NAME  : Jeshua Smith            Email: jeshua@us.ibm.com
-// *! BACKUP NAME : TBD                     Email: TBD@us.ibm.com
-// *!
-// *! Overview:
-// *!    Utility functions to calculate each mailbox value
-//------------------------------------------------------------------------------
-
-#ifndef _P8_MAILBOX_UTILS_H_
-#define _P8_MAILBOX_UTILS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Translate a VRM-11 VID code to a voltage value
-//
-//
-// parameters: i_vid_7_0    VRM-11 VID code
-//              o_voltage   Voltage in .01mv units
-//
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode vid2mv(uint8_t i_vid_7_0, uint32_t &o_voltage);
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 1
-//      (standalone_mbox0_value)
-//
-//  Mailbox scratch 1 (CFAM 2838, SCOM 0x50038)
-//
-//  Bytes 0,1   Boot frequency
-//  Boot Frequency info (power management def file DPS min (% drop from
-//  nominal), must cross checking between f_vmin and DPS min)
-//  This is a multiplier of the processor refclk frequency based on the
-//  the DPLL DIVIDER.
-//
-//  Bytes 2,3 EX Gard records
-//  FSP provides a vector for SBE to communicate the guareded EX chiplets
-//  Bits    0..3    4..7    8..11   12..15  16..19  20..23  24..27  28..31
-//                  0x0000                          EX guard bits
-//  One Guard bit per EX chiplet, bit location aligned to chiplet ID
-//  (bit 16: EX00, bit 17: EX01, bit 18: EX02 ... bit 31: EX15)
-//  Guarded EX chiplets are marked by a '0'.
-//
-// parameters: i_target           Reference to the processor chip target
-//             o_set_data         The 32-bit mailbox value
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox1( const fapi::Target &i_target, uint32_t & o_set_data );
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 2
-//      (standalone_mbox1_value)
-//
-//  Bit 0 in this register is used to indicate a MPIPL
-//  - The MPI flag will be evaluated by proc_sbe_ipl_seeprom to distinguish
-//    between a normal and a memory preserving IPL
-//  - attribute ATTR_IS_MPIPL will indicate MPIPL or not.
-//  Bit 1 in this register indicates standalone/FSPless mode
-//  - 0b0 = FSP present, 0b1 = standalone/FSPless mode
-//  FSP provides a MPI (Memory Preserving IPL) flag and settings for the I2C
-//  master bus speed calculation
-//  Bits    | 0     |   1 2 3   |   4..7    8..11   12..15                    |
-//          | MPI   |   000     | PIB I2C master Bit Rate Divisor (@refclock) |
-//
-//          |    16..19             20..23  24..27  28..31                    |
-//          |               PIB I2C master Bit Rate Divisor (@PLL)            |
-//
-// parameters: i_target           Reference to the chip target
-//             o_set_data         The 32-bit mailbox value
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox2( const fapi::Target &i_target, uint32_t & o_set_data );
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 3
-//      (standalone_mbox2_value)
-//
-//  32bit address of location of Hostboot image header (first block of data)
-//  This is offset using an algorithm to compensate for ECC -
-//  see Feature 862671 (fips810): hb pnor offset
-//
-// parameters: i_target           Reference to the chip target
-//             o_set_data         The 32-bit mailbox value
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox3( const fapi::Target &i_target, uint32_t & o_set_data );
-
-//------------------------------------------------------------------------------
-// function:
-//      set up sbe configuration values in mbox scratch reg 4
-//
-//  Write Boot Voltage info to scratch pad 4
-//
-//  0:2   -> port enables (3b - system design based:
-//          port 0 for non-redundant systems (100); all ports for non-redundant (111))
-//  3     -> Unused
-//  - current recommended default = 1000b
-//  4:7   -> phase enables (4b - defined by the system power design)
-//  - current recommended default = 0000b
-//  8:15  -> VDD voltage (1B in VRM-11 encoded form - 6.25mV increments)
-//          note: VPD is in 5mV increments
-//  - current recommended default   =   0x52
-//  16:23 -> VCS voltage (1B in VRM-11 encoded form - 6.25mV increments)
-//          note: VPD is in 5mV increments
-//  -current recommended default    =   0x4a
-//  24:27 -> Unused                 =   0x00
-//  28    -> Fabric wrap test       =   MNFG wrap test attribute
-//  29:31 -> Fabric node ID         =   Node ID attribute
-//
-// parameters: i_target           Reference to the chip target
-//             o_set_data         The 32-bit mailbox value
-//             i_write_fbc_data   True if the mailbox value should include fabric wrap
-//                                test/node ID information                             
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_mailbox_utils_get_mbox4( const fapi::Target &i_target, uint32_t & o_set_data,
-                                             bool i_write_fbc_data);
-
-} // extern "C"
-
-
-#endif // _P8_MAILBOX_UTILS_H_
-
diff --git a/src/usr/hwpf/hwp/build_winkle_images/runtime/makefile b/src/usr/hwpf/hwp/build_winkle_images/runtime/makefile
deleted file mode 100644
index 258967060..000000000
--- a/src/usr/hwpf/hwp/build_winkle_images/runtime/makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/build_winkle_images/runtime/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2012,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../../..
-
-HOSTBOOT_RUNTIME = 1
-
-MODULE = build_winkle_images_rt
-
-# objects unique to HBRT - currently none
-# OBJS +=
-
-# include objs common to HBRT and HB IPL
-include ../build_winkle_images.mk
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/bus_training/edi_regs.h b/src/usr/hwpf/hwp/bus_training/edi_regs.h
deleted file mode 100644
index 618c8d11d..000000000
--- a/src/usr/hwpf/hwp/bus_training/edi_regs.h
+++ /dev/null
@@ -1,4979 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/edi_regs.h $                    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-//----------------------------------------------------- 
-//      ____  ____     _   ______  ______ 
-//     / __ \/ __ \   / | / / __ \/_  __/ 
-//    / / / / / / /  /  |/ / / / / / /    
-//   / /_/ / /_/ /  / /|  / /_/ / / /     
-//  /_____/\____/  /_/ |_/\____/ /_/      
-//                                    
-//      __________  __________
-//     / ____/ __ \/  _/_  __/
-//    / __/ / / / // /  / /   
-//   / /___/ /_/ // /  / /    
-//  /_____/_____/___/ /_/     
-//                                    
-//    ________  ___________    ____________    ________
-//   /_  __/ / / /  _/ ___/   / ____/  _/ /   / ____/ /
-//    / / / /_/ // / \__ \   / /_   / // /   / __/ / / 
-//   / / / __  // / ___/ /  / __/ _/ // /___/ /___/_/  
-//  /_/ /_/ /_/___//____/  /_/   /___/_____/_____(_)   
-//----------------------------------------------------- 
-// Constant file for edi_reg_attribute.txt_fixed
-// File generated at 16:23 on 8/31/2011 using system_pervasive/common/tools/CreateConstantsH.pl
-// $Id: edi_regs.h,v 1.10 2014/02/20 13:27:29 varkeykv Exp $
-// $URL: $
-//
-// *!**************************************************************************
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME    : /afs/apd.pok.ibm.com/func/vlsi/eclipz/c22/verif/p8dd1/system_pervasive/common/include/edi_regs.h
-//
-// *! PERL SCRIPT OWNER NAME             : Jim Goldade      Email: goldade@us.ibm.com
-// *! edi_reg_attribute.txt_fixed
-//-----------------------------------------------------------------------------------------------------------------------------
-// EDI Register Def
-//-----------------------------------------------------------------------------------------------------------------------------
-#ifndef _edi_regs_h
-#define _edi_regs_h
-//FROM EDI_REGS
-
-typedef enum {
-tx_mode_pl,
-	tx_cntl_stat_pl,
-	tx_spare_mode_pl,
-	tx_bist_stat_pl,
-	tx_prbs_mode_pl,
-	tx_data_cntl_gcrmsg_pl,
-	tx_sync_pattern_gcrmsg_pl,
-	tx_fir_pl,
-	tx_fir_mask_pl,
-	tx_fir_error_inject_pl,
-	tx_mode_fast_pl,
-	tx_tdr_stat_pl,
-	tx_cntl_gcrmsg_pl,
-	tx_clk_mode_pg,
-	tx_spare_mode_pg,
-	tx_cntl_stat_pg,
-	tx_mode_pg,
-	tx_bus_repair_pg,
-	tx_grp_repair_vec_0_15_pg,
-	tx_grp_repair_vec_16_31_pg,
-	tx_reset_act_pg,
-	tx_bist_stat_pg,
-	tx_fir_pg,
-	tx_fir_mask_pg,
-	tx_fir_error_inject_pg,
-	tx_id1_pg,
-	tx_id2_pg,
-	tx_id3_pg,
-	tx_clk_cntl_gcrmsg_pg,
-	tx_ffe_mode_pg,
-	tx_ffe_main_pg,
-	tx_ffe_post_pg,
-	tx_ffe_margin_pg,
-	tx_bad_lane_enc_gcrmsg_pg,
-	tx_sls_lane_enc_gcrmsg_pg,
-	tx_wt_seg_enable_pg,
-	tx_lane_disabled_vec_0_15_pg,
-	tx_lane_disabled_vec_16_31_pg,
-	tx_sls_lane_mux_gcrmsg_pg,
-	tx_dyn_rpr_pg,
-	tx_slv_mv_sls_ln_req_gcrmsg_pg,
-	tx_wiretest_pp,
-	tx_mode_pp,
-	tx_sls_gcrmsg_pp,
-	tx_ber_cntl_a_pp,
-	tx_ber_cntl_b_pp,
-	tx_dyn_recal_timeouts_pp,
-	tx_bist_cntl_pp,
-	tx_ber_cntl_sls_pp,
-	tx_cntl_pp,
-	tx_reset_cfg_pp,
-	tx_tdr_cntl1_pp,
-	tx_tdr_cntl2_pp,
-	tx_tdr_cntl3_pp,
-	tx_impcal_pb,
-	tx_impcal_nval_pb,
-	tx_impcal_pval_pb,
-	tx_impcal_p_4x_pb,
-	tx_impcal_swo1_pb,
-	tx_impcal_swo2_pb,
-	tx_analog_iref_pb,
-	tx_minikerf_pb,
-	tx_init_version_pb,
-	tx_scratch_reg_pb,
-	rx_mode_pl,
-	rx_cntl_pl,
-	rx_spare_mode_pl,
-	rx_prot_edge_status_pl,
-	rx_bist_stat_pl,
-	rx_offset_even_pl,
-	rx_offset_odd_pl,
-	rx_amp_val_pl,
-	rx_amp_cntl_pl,
-	rx_prot_status_pl,
-	rx_prot_mode_pl,
-	rx_prot_cntl_pl,
-	rx_fifo_stat_pl,
-	rx_ap_pl,
-	rx_an_pl,
-	rx_amin_pl,
-	rx_h1_even_pl,
-	rx_h1_odd_pl,
-	rx_prbs_mode_pl,
-	rx_stat_pl,
-	rx_deskew_stat_pl,
-	rx_fir_pl,
-	rx_fir_mask_pl,
-	rx_fir_error_inject_pl,
-	rx_sls_pl,
-	rx_wt_status_pl,
-	rx_fifo_cntl_pl,
-	rx_ber_status_pl,
-	rx_ber_timer_0_15_pl,
-	rx_ber_timer_16_31_pl,
-	rx_ber_timer_32_39_pl,
-	rx_servo_cntl_pl,
-	rx_fifo_diag_0_15_pl,
-	rx_fifo_diag_16_31_pl,
-	rx_fifo_diag_32_47_pl,
-	rx_eye_width_status_pl,
-	rx_eye_width_cntl_pl,
-	rx_dfe_clkadj_pl,
-	rx_trace_pl,
-	rx_servo_ber_count_pl,
-	rx_eye_opt_stat_pl,
-	rx_clk_mode_pg,
-	rx_spare_mode_pg,
-	rx_stop_cntl_stat_pg,
-	rx_mode_pg,
-	rx_bus_repair_pg,
-	rx_grp_repair_vec_0_15_pg,
-	rx_grp_repair_vec_16_31_pg,
-	rx_stop_addr_lsb_pg,
-	rx_stop_mask_lsb_pg,
-	rx_reset_act_pg,
-	rx_id1_pg,
-	rx_id2_pg,
-	rx_id3_pg,
-	rx_minikerf_pg,
-	rx_sls_mode_pg,
-	rx_training_start_pg,
-	rx_training_status_pg,
-	rx_recal_status_pg,
-	rx_timeout_sel_pg,
-	rx_fifo_mode_pg,
-	rx_sls_status_pg,
-	rx_fir1_pg,
-	rx_fir2_pg,
-	rx_fir1_mask_pg,
-	rx_fir2_mask_pg,
-	rx_fir1_error_inject_pg,
-	rx_fir2_error_inject_pg,
-	rx_fir_training_pg,
-	rx_fir_training_mask_pg,
-	rx_timeout_sel1_pg,
-	rx_lane_bad_vec_0_15_pg,
-	rx_lane_bad_vec_16_31_pg,
-	rx_lane_disabled_vec_0_15_pg,
-	rx_lane_disabled_vec_16_31_pg,
-	rx_lane_swapped_vec_0_15_pg,
-	rx_lane_swapped_vec_16_31_pg,
-	rx_init_state_pg,
-	rx_wiretest_state_pg,
-	rx_wiretest_laneinfo_pg,
-	rx_wiretest_gcrmsgs_pg,
-	rx_deskew_gcrmsgs_pg,
-	rx_deskew_state_pg,
-	rx_deskew_mode_pg,
-	rx_deskew_status_pg,
-	rx_bad_lane_enc_gcrmsg_pg,
-	rx_static_repair_state_pg,
-	rx_tx_bus_info_pg,
-	rx_sls_lane_enc_gcrmsg_pg,
-	rx_fence_pg,
-	rx_timeout_sel2_pg,
-	rx_misc_analog_pg,
-	rx_dyn_rpr_pg,
-	rx_dyn_rpr_gcrmsg_pg,
-	rx_dyn_rpr_err_tallying1_pg,
-	rx_eo_final_l2u_gcrmsgs_pg,
-	rx_gcr_msg_debug_dest_ids_pg,
-	rx_gcr_msg_debug_src_ids_pg,
-	rx_gcr_msg_debug_dest_addr_pg,
-	rx_gcr_msg_debug_write_data_pg,
-	rx_dyn_recal_pg,
-	rx_wt_clk_status_pg,
-	rx_dyn_recal_config_pg,
-	rx_dyn_recal_gcrmsg_pg,
-	rx_wiretest_pll_cntl_pg,
-	rx_eo_step_cntl_pg,
-	rx_eo_step_stat_pg,
-	rx_eo_step_fail_pg,
-	rx_ap_pg,
-	rx_an_pg,
-	rx_amin_pg,
-	rx_amax_pg,
-	rx_amp_val_pg,
-	rx_amp_offset_pg,
-	rx_eo_convergence_pg,
-	rx_sls_rcvy_pg,
-	rx_sls_rcvy_gcrmsg_pg,
-	rx_tx_lane_info_gcrmsg_pg,
-	rx_err_tallying_gcrmsg_pg,
-	rx_trace_pg,
-	rx_rc_step_cntl_pg,
-	rx_eo_recal_pg,
-	rx_servo_ber_count_pg,
-	rx_func_state_pg,
-	rx_dyn_rpr_debug_pg,
-	rx_dyn_rpr_err_tallying2_pg,
-	rx_result_chk_pg,
-	rx_ber_chk_pg,
-	rx_sls_rcvy_fin_gcrmsg_pg,
-	rx_wiretest_pp,
-	rx_mode1_pp,
-	rx_cntl_pp,
-	rx_dyn_recal_timeouts_pp,
-	rx_mode2_pp,
-	rx_ber_cntl_pp,
-	rx_ber_mode_pp,
-	rx_servo_to1_pp,
-	rx_servo_to2_pp,
-	rx_servo_to3_pp,
-	rx_dfe_config_pp,
-	rx_dfe_timers_pp,
-	rx_reset_cfg_pp,
-	rx_recal_to1_pp,
-	rx_recal_to2_pp,
-	rx_recal_to3_pp,
-	rx_recal_cntl_pp,
-	rx_trace_pp,
-	rx_bist_gcrmsg_pp,
-	rx_scope_cntl_pp,
-	rx_fir_reset_pb,
-	rx_fir_pb,
-	rx_fir_mask_pb,
-	rx_fir_error_inject_pb,
-	rx_fir_msg_pb,
-	
-	ei4_tx_mode_pl,
-	ei4_tx_cntl_stat_pl,
-	ei4_tx_spare_mode_pl,
-	ei4_tx_bist_stat_pl,
-	ei4_tx_prbs_mode_pl,
-	ei4_tx_data_cntl_gcrmsg_pl,
-	ei4_tx_sync_pattern_gcrmsg_pl,
-	ei4_tx_fir_pl,
-	ei4_tx_fir_mask_pl,
-	ei4_tx_fir_error_inject_pl,
-	ei4_tx_mode_fast_pl,
-	ei4_tx_clk_mode_pg,
-	ei4_tx_spare_mode_pg,
-	ei4_tx_cntl_stat_pg,
-	ei4_tx_mode_pg,
-	ei4_tx_bus_repair_pg,
-	ei4_tx_grp_repair_vec_0_15_pg,
-	ei4_tx_grp_repair_vec_16_31_pg,
-	ei4_tx_reset_act_pg,
-	ei4_tx_bist_stat_pg,
-	ei4_tx_fir_pg,
-	ei4_tx_fir_mask_pg,
-	ei4_tx_fir_error_inject_pg,
-	ei4_tx_id1_pg,
-	ei4_tx_id2_pg,
-	ei4_tx_id3_pg,
-	ei4_tx_clk_cntl_gcrmsg_pg,
-	ei4_tx_bad_lane_enc_gcrmsg_pg,
-	ei4_tx_sls_lane_enc_gcrmsg_pg,
-	ei4_tx_wt_seg_enable_pg,
-	ei4_tx_pc_ffe_pg,
-	ei4_tx_misc_analog_pg,
-	ei4_tx_lane_disabled_vec_0_15_pg,
-	ei4_tx_lane_disabled_vec_16_31_pg,
-	ei4_tx_sls_lane_mux_gcrmsg_pg,
-	ei4_tx_dyn_rpr_pg,
-	ei4_tx_slv_mv_sls_ln_req_gcrmsg_pg,
-	ei4_tx_rdt_cntl_pg,
-	ei4_rx_dll_cal_cntl_pg,
-	ei4_rx_dll1_setpoint1_pg,
-	ei4_rx_dll1_setpoint2_pg,
-	ei4_rx_dll1_setpoint3_pg,
-	ei4_rx_dll2_setpoint1_pg,
-	ei4_rx_dll2_setpoint2_pg,
-	ei4_rx_dll2_setpoint3_pg,
-	ei4_rx_dll_filter_mode_pg,
-	ei4_rx_dll_analog_tweaks_pg,
-	ei4_tx_wiretest_pp,
-	ei4_tx_mode_pp,
-	ei4_tx_sls_gcrmsg_pp,
-	ei4_tx_ber_cntl_a_pp,
-	ei4_tx_ber_cntl_b_pp,
-	ei4_tx_bist_cntl_pp,
-	ei4_tx_ber_cntl_sls_pp,
-	ei4_tx_cntl_pp,
-	ei4_tx_reset_cfg_pp,
-	ei4_tx_tdr_cntl2_pp,
-	ei4_tx_tdr_cntl3_pp,
-	ei4_rx_mode_pl,
-	ei4_rx_cntl_pl,
-	ei4_rx_spare_mode_pl,
-	ei4_rx_bist_stat_pl,
-	ei4_rx_offset_even_pl,
-	ei4_rx_offset_odd_pl,
-	ei4_rx_amp_val_pl,
-	ei4_rx_prot_status_pl,
-	ei4_rx_prot_mode_pl,
-	ei4_rx_prot_cntl_pl,
-	ei4_rx_fifo_stat_pl,
-	ei4_rx_prbs_mode_pl,
-	ei4_rx_vref_pl,
-	ei4_rx_stat_pl,
-	ei4_rx_deskew_stat_pl,
-	ei4_rx_fir_pl,
-	ei4_rx_fir_mask_pl,
-	ei4_rx_fir_error_inject_pl,
-	ei4_rx_sls_pl,
-	ei4_rx_wt_status_pl,
-	ei4_rx_fifo_cntl_pl,
-	ei4_rx_ber_status_pl,
-	ei4_rx_ber_timer_0_15_pl,
-	ei4_rx_ber_timer_16_31_pl,
-	ei4_rx_ber_timer_32_39_pl,
-	ei4_rx_servo_cntl_pl,
-	ei4_rx_fifo_diag_0_15_pl,
-	ei4_rx_fifo_diag_16_31_pl,
-	ei4_rx_fifo_diag_32_47_pl,
-	ei4_rx_eye_width_status_pl,
-	ei4_rx_eye_width_cntl_pl,
-	ei4_rx_trace_pl,
-	ei4_rx_servo_ber_count_pl,
-	ei4_rx_eye_opt_stat_pl,
-	ei4_rx_clk_mode_pg,
-	ei4_rx_spare_mode_pg,
-	ei4_rx_stop_cntl_stat_pg,
-	ei4_rx_mode_pg,
-	ei4_rx_bus_repair_pg,
-	ei4_rx_grp_repair_vec_0_15_pg,
-	ei4_rx_grp_repair_vec_16_31_pg,
-	ei4_rx_stop_addr_lsb_pg,
-	ei4_rx_stop_mask_lsb_pg,
-	ei4_rx_reset_act_pg,
-	ei4_rx_id1_pg,
-	ei4_rx_id2_pg,
-	ei4_rx_id3_pg,
-	ei4_rx_sls_mode_pg,
-	ei4_rx_training_start_pg,
-	ei4_rx_training_status_pg,
-	ei4_rx_recal_status_pg,
-	ei4_rx_timeout_sel_pg,
-	ei4_rx_fifo_mode_pg,
-	ei4_rx_sls_status_pg,
-	ei4_rx_fir1_pg,
-	ei4_rx_fir2_pg,
-	ei4_rx_fir1_mask_pg,
-	ei4_rx_fir2_mask_pg,
-	ei4_rx_fir1_error_inject_pg,
-	ei4_rx_fir2_error_inject_pg,
-	ei4_rx_fir_training_pg,
-	ei4_rx_fir_training_mask_pg,
-	ei4_rx_timeout_sel1_pg,
-	ei4_rx_lane_bad_vec_0_15_pg,
-	ei4_rx_lane_bad_vec_16_31_pg,
-	ei4_rx_lane_disabled_vec_0_15_pg,
-	ei4_rx_lane_disabled_vec_16_31_pg,
-	ei4_rx_lane_swapped_vec_0_15_pg,
-	ei4_rx_lane_swapped_vec_16_31_pg,
-	ei4_rx_init_state_pg,
-	ei4_rx_wiretest_state_pg,
-	ei4_rx_wiretest_laneinfo_pg,
-	ei4_rx_wiretest_gcrmsgs_pg,
-	ei4_rx_deskew_gcrmsgs_pg,
-	ei4_rx_deskew_state_pg,
-	ei4_rx_deskew_mode_pg,
-	ei4_rx_deskew_status_pg,
-	ei4_rx_bad_lane_enc_gcrmsg_pg,
-	ei4_rx_static_repair_state_pg,
-	ei4_rx_ei4_tx_bus_info_pg,
-	ei4_rx_sls_lane_enc_gcrmsg_pg,
-	ei4_rx_fence_pg,
-	ei4_rx_term_pg,
-	ei4_rx_timeout_sel2_pg,
-	ei4_rx_dyn_rpr_pg,
-	ei4_rx_dyn_rpr_gcrmsg_pg,
-	ei4_rx_dyn_rpr_err_tallying1_pg,
-	ei4_rx_eo_final_l2u_gcrmsgs_pg,
-	ei4_rx_gcr_msg_debug_dest_ids_pg,
-	ei4_rx_gcr_msg_debug_src_ids_pg,
-	ei4_rx_gcr_msg_debug_dest_addr_pg,
-	ei4_rx_gcr_msg_debug_write_data_pg,
-	ei4_rx_wt_clk_status_pg,
-	ei4_rx_wiretest_pll_cntl_pg,
-	ei4_rx_eo_step_cntl_pg,
-	ei4_rx_eo_step_stat_pg,
-	ei4_rx_eo_step_fail_pg,
-	ei4_rx_amp_val_pg,
-	ei4_rx_sls_rcvy_pg,
-	ei4_rx_sls_rcvy_gcrmsg_pg,
-	ei4_rx_ei4_tx_lane_info_gcrmsg_pg,
-	ei4_rx_err_tallying_gcrmsg_pg,
-	ei4_rx_trace_pg,
-	ei4_rx_rdt_cntl_pg,
-	ei4_rx_rc_step_cntl_pg,
-	ei4_rx_eo_recal_pg,
-	ei4_rx_servo_ber_count_pg,
-	ei4_rx_func_state_pg,
-	ei4_rx_dyn_rpr_debug_pg,
-	ei4_rx_dyn_rpr_err_tallying2_pg,
-	ei4_rx_result_chk_pg,
-	ei4_rx_sls_rcvy_fin_gcrmsg_pg,
-	ei4_rx_wiretest_pp,
-	ei4_rx_mode1_pp,
-	ei4_rx_cntl_pp,
-	ei4_rx_ei4_cal_cntl_pp,
-	ei4_rx_ei4_cal_inc_a_d_pp,
-	ei4_rx_ei4_cal_inc_e_h_pp,
-	ei4_rx_ei4_cal_dec_a_d_pp,
-	ei4_rx_ei4_cal_dec_e_h_pp,
-	ei4_rx_mode2_pp,
-	ei4_rx_ber_cntl_pp,
-	ei4_rx_ber_mode_pp,
-	ei4_rx_servo_to1_pp,
-	ei4_rx_servo_to2_pp,
-	ei4_rx_reset_cfg_pp,
-	ei4_rx_recal_to1_pp,
-	ei4_rx_recal_to2_pp,
-	ei4_rx_recal_cntl_pp,
-	ei4_rx_trace_pp,
-	ei4_rx_bist_gcrmsg_pp,
-	ei4_rx_fir_reset_pb,
-	ei4_rx_fir_pb,
-	ei4_rx_fir_mask_pb,
-	ei4_rx_fir_error_inject_pb,
-	ei4_rx_fir_msg_pb,
-        ei4_rx_dcd_adj_pl,
-NUM_REGS
-} GCR_sub_registers;
-
-
-// merged ei4 and edi ext addresses
-const uint32_t  GCR_sub_reg_ext_addr[] =     { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF,
-											   0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF,0x02E};
-//merged ei4 and edi 
-const char* const GCR_sub_reg_names[] = {
-	"TX Lane Mode Reg",
-	"TX Cntl and Status Reg",
-	"TX Per-Lane Spare Mode Reg",
-	"TX BIST Status Reg",
-	"TX Per-Lane PRBS Mode Reg",
-	"TX Data Control Reg",
-	"TX Sync Pattern Control Reg",
-	"TX Per-Lane FIR Error Source-Isolation Reg",
-	"TX Per-Lane FIR Error Mask Reg",
-	"TX Per-Lane FIR Error Injection Reg",
-	"TX Per-Lane Fast-Clocked Mode Reg",
-	"TX TDR Capture status",
-	"TX Cntl Reg via GCR Messages",
-	"TX Per-Group Clk Mode Reg",
-	"TX Per-Group Spare Mode Reg",
-	"TX Cntl and Status Reg",
-	"TX Mode Reg",
-	"TX Bus Repair Reg",
-	"TX Clkgrp Repair Lanes 0-15 Reg",
-	"TX Clkgrp Repair Lanes 16-31 Reg",
-	"TX Reset Control Action Register (RCAR)",
-	"TX BIST CLK Status Reg",
-	"TX Per-Group FIR Error Source-Isolation Reg",
-	"TX Per-Group FIR Error Source-Isolation Reg",
-	"TX Per-Group FIR Error Injection Reg",
-	"TX Clock Group Identification 1 Reg",
-	"TX Clock Group Identification 2 Reg",
-	"TX Clock Group Identification 3 Reg",
-	"TX Clock Control Reg",
-	"TX FFE Test Mode Reg",
-	"TX FFE Main Reg",
-	"TX FFE Post Reg",
-	"TX FFE Margin Reg",
-	"TX Bad Lanes Encoded",
-	"TX SLS Lane Encoded",
-	"TX Wiretest Driver Segment Enable",
-	"TX Lane Disable(d) 0 to 15 Reg",
-	"TX Lane Disable(d) 16 to 31 Reg",
-	"TX SLS Lane TX Mux Setting",
-	"TX Dynamic Repair & Recalibration Status",
-	"TX Dynamic Repair & Recalibration Messages",
-	"TX Wiretest Per-Group & Pack Shadow Reg",
-	"TX Mode Per-Pack Shadow Reg",
-	"TX SLS Command",
-	"TX Bit Error Injection Control A Shadow Reg",
-	"TX Bit Error Injection Control B Shadow Reg",
-	"TX Dynamic Recalibration Timeout Selects",
-	"TX BIST Cntl Reg",
-	"TX Bit Error Injection Control SLS Shadow Reg",
-	"TX Cntl Per-Pack Reg",
-	"TX Configurable Reset Control Register (CRCR)",
-	"TX TDR Control Register",
-	"TX TDR Control Register",
-	"TX TDR Control Register",
-	"TX Impedance Cal Cntl and Status Reg",
-	"TX Impedance Cal N Value Reg",
-	"TX Impedance Cal P Value Reg",
-	"TX Impedance Cal P 4x Value Reg",
-	"TX Impedance Cal SW Workaround 1 Reg",
-	"TX Impedance Cal SW Workaround 2 Reg",
-	"TX Iref bias code input",
-	"TX Minikerf Cntl Reg",
-	"TX Initfile Version Reg",
-	"TX Scratch Reg",
-	"RX Lane Mode Reg",
-	"RX Cntl and Status Reg",
-	"RX Per-lane Spare Mode Reg",
-	"RX Phase Rotator Edge Status Reg",
-	"RX BIST Status Reg",
-	"RX Even Sample Latch Offset Cntl Reg",
-	"RX Odd Sample Latch Offset Cntl Reg",
-	"RX Preamp value Reg",
-	"RX Preamp value Reg",
-	"RX Phase Rotator Status Reg",
-	"RX Phase Rotator Mode Reg",
-	"RX Phase Rotator Control Reg",
-	"RX FIFO Status Reg",
-	"RX Ap Even/Odd Sampler Reg",
-	"RX An Even/Odd Sampler Reg",
-	"RX Amin Reg",
-	"RX H1 Even Sampler Reg",
-	"RX H1 Odd Sampler Reg",
-	"RX Per-Lane PRBS Mode Reg",
-	"RX Per-Lane Deskew Status Reg",
-	"RX FIFO deskew status/error register",
-	"RX Per-Lane FIR Error Source-Isolation Reg",
-	"RX Per-Lane FIR Error Source-Isolation Mask Reg",
-	"RX Per-Lane FIR Error Injection Reg",
-	"RX SLS Settings Register",
-	"RX Wiretest Status register  ",
-	"RX FIFO control Reg",
-	"RX BER Status Reg",
-	"RX BER Current Timer Value Reg - Bits 0 to 15",
-	"RX BER Current Timer Value Reg - Bits 16 to 31",
-	"RX BER Current Timer Value Reg - Bits 32 to 39",
-	"RX Servo Operation command and control",
-	"RX FIFO output 0 to 15 for diag",
-	"RX FIFO output 16 to 31 for diag",
-	"RX FIFO output 32 to 47 for diag",
-	"RX Current and historic minimum eye width",
-	"RX historic minimum eye width reset control",
-	"RX dfe clock adjust register",
-	"RX Trace Per Lane Settings",
-	"RX servo-based BER count PL",
-	"RX Eye optimization error register",
-	"RX Per-Group Clk Mode Reg",
-	"RX Per-Group Spare Mode Reg",
-	"RX Trace/State stop control/status/ MSB Reg",
-	"RX Mode Reg",
-	"RX Bus Repair Reg",
-	"RX Clkgrp Repair Lanes 0-15 Reg",
-	"RX Clkgrp Repair Lanes 16-31 Reg",
-	"RX Trace/State stop address 4-19  Reg",
-	"RX Trace/State stop mask    4-19  Reg",
-	"RX Reset Control Action Register (RCAR)",
-	"RX Clock Group Identification 1 Reg",
-	"RX Clock Group Identification 2 Reg",
-	"RX Clock Group Identification 3 Reg",
-	"RX Minikerf Cntl Reg",
-	"RX Spare Lane Signaling Mode Reg",
-	"RX Training State Start Reg",
-	"RX Training State Status Reg",
-	"RX Recal Status Reg",
-	"RX Timeout Select Reg",
-	"RX FIFO Mode Reg",
-	"RX Spare Lane Signalling Status Reg",
-	"RX Per-Group FIR Error Source-Isolation Reg",
-	"RX Per-Group FIR Error Source-Isolation Reg",
-	"RX Per-Group FIR Error Source-Isolation Mask Reg",
-	"RX Per-Group FIR Error Source-Isolation Mask Reg",
-	"RX Per-Group FIR Error Injection Reg",
-	"RX Per-Group FIR Error Injection Reg",
-	"RX Per-Group Training FIR Error Reg",
-	"RX Per-Group Training FIR Error Mask Reg",
-	"RX Timeout Select Reg 1",
-	"RX Bad Lanes 0 to 15 Reg",
-	"RX Bad Lanes 16 to 31 Reg",
-	"RX Lane Disable(d) 0 to 15 Reg",
-	"RX Lane Disable(d) 16_31 Reg",
-	"RX P & N Lanes Swapped 0 to 15 Reg",
-	"RX P & N Lanes Swapped 16 to 31 Reg",
-	"RX Init Machine Status",
-	"RX Wiretest State Machine Reg",
-	"RX Wiretest Lane Info Reg",
-	"RX Wiretest GCR Message Reg",
-	"RX Deskew GCR Message Reg",
-	"RX Deskew State Machine Status Reg",
-	"RX Deskew State Machine Control Reg",
-	"RX Deskew State Machine Status Values",
-	"RX Bad Lanes Encoded",
-	"RX Static Repair State Machine Reg",
-	"TX Bus info for RX Ctl Macs",
-	"RX SLS Lane Encoded",
-	"RX Per Group Fence",
-	"RX Timeout Select Reg 2",
-	"RX Misc Analog Reg",
-	"RX Dynamic Repair & Recalibration Status",
-	"CRC/ECC Dynamic Repair GCR Message Reg",
-	"CRC/ECC Dynamic Repair Lane Error Frequency Settings",
-	"RX Final Load to Unload GCR Messages",
-	"RX SW Initiated GCR Message Destination IDs",
-	"RX SW Initiated GCR Message Source IDs",
-	"RX SW Initiated GCR Message Destination Addr",
-	"RX SW Initiated GCR Message Write Data",
-	"RX Dynamic Recalibration Status",
-	"RX Clock Wiretest Status",
-	"RX Dynamic Recalibration Configuration",
-	"RX Dynamic Recalibration GCR Messages",
-	"RX PLL or DLL reset and calibration controls",
-	"RX Eye optimization step control",
-	"RX Eye optimization step status",
-	"RX Eye optimization step fail flags",
-	"RX Eye optimization Ap   working registers",
-	"RX Eye optimization An   working registers",
-	"RX Eye optimization Amin working registers",
-	"RX Eye optimization Amax limit   registers",
-	"RX Eye optimization Amp  working registers",
-	"RX Eye optimization Amp  Offset limts     ",
-	"RX Eye optimization Convergence control regs",
-	"RX SLS Handshake Recovery Register",
-	"RX SLS Handshake Recovery GCR Messages",
-	"RX: TX Lane Info",
-	"CRC/ECC Syndrome Tallying GCR Message Reg",
-	"RX Trace Mode Reg",
-	"RX Recalibraton     step control",
-	"RX Eye Opt and Recal Status",
-	"RX Recal Bit Error Rate Count Working Register",
-	"RX Func Mode Status",
-	"Dynamic Repair Testfloor/Debug Register",
-	"CRC/ECC Dynamic Repair Bus Error Frequency Settings",
-	"Eye widhth/height results check limits",
-	"Bit error rate check max rate k limits",
-	"RX SLS Handshake Recovery Finish GCR Messages",
-	"RX Wiretest Per-Pack Shadow Reg",
-	"RX Mode Per-Pack Shadow Reg",
-	"RX Cntl Per-Pack Shadow Reg",
-	"RX Dynamic Recalibration Timeout Selects",
-	"RX Mode Per-Pack Shadow Reg",
-	"RX BER Control Reg",
-	"RX BER Mode Reg",
-	"RX Servo Timeout Select Regs 1",
-	"RX Servo Timeout Select Regs 2",
-	"RX Servo Timeout Select Regs 3",
-	"RX DFE Configuration Register",
-	"RX DFE timers Configuration Register",
-	"RX Configurable Reset Control Register (CRCR)",
-	"RX Recal Servo Timeout Select Regs 1",
-	"RX Recal Servo Timeout Select Regs 2",
-	"RX Recal Servo Timeout Select Regs 3",
-	"RX Recal in progress control",
-	"RX Trace Per Pack Settings",
-	"RX BIST Cntl Reg",
-	"RX Scope Cntl Reg",
-	"Per-Bus BUSCTL FIR Error Reset Reg",
-	"Per-Bus FIR Error Source-Isolation Reg",
-	"Per-Bus FIR Error Source-Isolation Mask Reg",
-	"Per-Bus FIR Error Injection Reg",
-    "Per-Bus FIR Register Write Alias",
-	"TX Lane Mode Reg",
-	"TX Cntl and Status Reg",
-	"TX Per-Lane Spare Mode Reg",
-	"TX BIST Status Reg",
-	"TX Per-Lane PRBS Mode Reg",
-	"TX Data Control Reg",
-	"TX Sync Pattern Control Reg",
-	"TX Per-Lane FIR Error Source-Isolation Reg",
-	"TX Per-Lane FIR Error Mask Reg",
-	"TX Per-Lane FIR Error Injection Reg",
-	"TX Per-Lane Fast-Clocked Mode Reg",
-	"TX Per-Group Clk Mode Reg",
-	"TX Per-Group Spare Mode Reg",
-	"TX Cntl and Status Reg",
-	"TX Mode Reg",
-	"TX Bus Repair Reg",
-	"TX Clkgrp Repair Lanes 0-15 Reg",
-	"TX Clkgrp Repair Lanes 16-31 Reg",
-	"TX Reset Control Action Register (RCAR)",
-	"TX BIST CLK Status Reg",
-	"TX Per-Group FIR Error Source-Isolation Reg",
-	"TX Per-Group FIR Error Source-Isolation Reg",
-	"TX Per-Group FIR Error Injection Reg",
-	"TX Clock Group Identification 1 Reg",
-	"TX Clock Group Identification 2 Reg",
-	"TX Clock Group Identification 3 Reg",
-	"TX Clock Control Reg",
-	"TX Bad Lanes Encoded",
-	"TX SLS Lane Encoded",
-	"TX Wiretest Driver Segment Enable",
-	"TX Precomp and Impedance Reg",
-	"TX Misc Analog Reg",
-	"TX Lane Disable(d) 0 to 15 Reg",
-	"TX Lane Disable(d) 16 to 31 Reg",
-	"TX SLS Lane TX Mux Setting",
-	"TX Dynamic Repair & Recalibration Status",
-	"TX Dynamic Repair & Recalibration Messages",
-	"TX control for RDT (EI3-Mode only)",
-	"RX DLL Calibration Sequence Status",
-	"RX DLL 1 Manual Delay/Vreg DAC Coarse Override",
-	"RX DLL 1 Manual Vreg DAC Fine Override",
-	"RX DLL 1 Manual Vreg DAC Fine Override",
-	"RX DLL 2 Manual Delay/Vreg DAC Coarse Override",
-	"RX DLL 2 Manual Vreg DAC Fine Override",
-	"RX DLL 2 Manual Vreg DAC Fine Override",
-	"RX DLL Clock Phase Detector Filtering",
-	"RX DLL Analog Fine Tuning",
-	"TX Wiretest Per-Group & Pack Shadow Reg",
-	"TX Mode Per-Pack Shadow Reg",
-	"TX SLS Command",
-	"TX Bit Error Injection Control A Shadow Reg",
-	"TX Bit Error Injection Control B Shadow Reg",
-	"TX BIST Cntl Reg",
-	"TX Bit Error Injection Control SLS Shadow Reg",
-	"TX Cntl Per-Pack Reg",
-	"TX Configurable Reset Control Register (CRCR)",
-	"TX TDR Control Register",
-	"TX TDR Control Register",
-	"RX Lane Mode Reg",
-	"RX Cntl and Status Reg",
-	"RX Per-lane Spare Mode Reg",
-	"RX BIST Status Reg",
-	"RX Even Sample Latch Offset Cntl Reg",
-	"RX Odd Sample Latch Offset Cntl Reg",
-	"RX Preamp value Reg",
-	"RX Phase Rotator Status Reg",
-	"RX Phase Rotator Mode Reg",
-	"RX Phase Rotator Control Reg",
-	"RX FIFO Status Reg",
-	"RX Per-Lane PRBS Mode Reg",
-	"RX Voltage Reference Reg",
-	"RX Per-Lane Deskew Status Reg",
-	"RX FIFO deskew status/error register",
-	"RX Per-Lane FIR Error Source-Isolation Reg",
-	"RX Per-Lane FIR Error Source-Isolation Mask Reg",
-	"RX Per-Lane FIR Error Injection Reg",
-	"RX SLS Settings Register",
-	"RX Wiretest Status register  ",
-	"RX FIFO control Reg",
-	"RX BER Status Reg",
-	"RX BER Current Timer Value Reg - Bits 0 to 15",
-	"RX BER Current Timer Value Reg - Bits 16 to 31",
-	"RX BER Current Timer Value Reg - Bits 32 to 39",
-	"RX Servo Operation command and control",
-	"RX FIFO output 0 to 15 for diag",
-	"RX FIFO output 16 to 31 for diag",
-	"RX FIFO output 32 to 47 for diag",
-	"RX Current and historic minimum eye width",
-	"RX historic minimum eye width reset control",
-	"RX Trace Per Lane Settings",
-	"RX servo-based BER count PL",
-	"RX Eye optimization error register",
-	"RX Per-Group Clk Mode Reg",
-	"RX Per-Group Spare Mode Reg",
-	"RX Trace/State stop control/status/ MSB Reg",
-	"RX Mode Reg",
-	"RX Bus Repair Reg",
-	"RX Clkgrp Repair Lanes 0-15 Reg",
-	"RX Clkgrp Repair Lanes 16-31 Reg",
-	"RX Trace/State stop address 4-19  Reg",
-	"RX Trace/State stop mask    4-19  Reg",
-	"RX Reset Control Action Register (RCAR)",
-	"RX Clock Group Identification 1 Reg",
-	"RX Clock Group Identification 2 Reg",
-	"RX Clock Group Identification 3 Reg",
-	"RX Spare Lane Signaling Mode Reg",
-	"RX Training State Start Reg",
-	"RX Training State Status Reg",
-	"RX Recal Status Reg",
-	"RX Timeout Select Reg",
-	"RX FIFO Mode Reg",
-	"RX Spare Lane Signalling Status Reg",
-	"RX Per-Group FIR Error Source-Isolation Reg",
-	"RX Per-Group FIR Error Source-Isolation Reg",
-	"RX Per-Group FIR Error Source-Isolation Mask Reg",
-	"RX Per-Group FIR Error Source-Isolation Mask Reg",
-	"RX Per-Group FIR Error Injection Reg",
-	"RX Per-Group FIR Error Injection Reg",
-	"RX Per-Group Training FIR Error Reg",
-	"RX Per-Group Training FIR Error Mask Reg",
-	"RX Timeout Select Reg 1",
-	"RX Bad Lanes 0 to 15 Reg",
-	"RX Bad Lanes 16 to 31 Reg",
-	"RX Lane Disable(d) 0 to 15 Reg",
-	"RX Lane Disable(d) 16_31 Reg",
-	"RX P & N Lanes Swapped 0 to 15 Reg",
-	"RX P & N Lanes Swapped 16 to 31 Reg",
-	"RX Init Machine Status",
-	"RX Wiretest State Machine Reg",
-	"RX Wiretest Lane Info Reg",
-	"RX Wiretest GCR Message Reg",
-	"RX Deskew GCR Message Reg",
-	"RX Deskew State Machine Status Reg",
-	"RX Deskew State Machine Control Reg",
-	"RX Deskew State Machine Status Values",
-	"RX Bad Lanes Encoded",
-	"RX Static Repair State Machine Reg",
-	"TX Bus info for RX Ctl Macs",
-	"RX SLS Lane Encoded",
-	"RX Per Group Fence",
-	"RX Termination Reg",
-	"RX Timeout Select Reg 2",
-	"RX Dynamic Repair & Recalibration Status",
-	"CRC/ECC Dynamic Repair GCR Message Reg",
-	"CRC/ECC Dynamic Repair Lane Error Frequency Settings",
-	"RX Final Load to Unload GCR Messages",
-	"RX SW Initiated GCR Message Destination IDs",
-	"RX SW Initiated GCR Message Source IDs",
-	"RX SW Initiated GCR Message Destination Addr",
-	"RX SW Initiated GCR Message Write Data",
-	"RX Clock Wiretest Status",
-	"RX PLL or DLL reset and calibration controls",
-	"RX Eye optimization step control",
-	"RX Eye optimization step status",
-	"RX Eye optimization step fail flags",
-	"RX Eye optimization Amp  working registers",
-	"RX SLS Handshake Recovery Register",
-	"RX SLS Handshake Recovery GCR Messages",
-	"RX: TX Lane Info",
-	"CRC/ECC Syndrome Tallying GCR Message Reg",
-	"RX Trace Mode Reg",
-	"RX control for RDT (EI3-Mode only)",
-	"RX Recalibraton     step control",
-	"RX Eye Opt and Recal Status",
-	"RX Recal Bit Error Rate Count Working Register",
-	"RX Func Mode Status",
-	"Dynamic Repair Testfloor/Debug Register",
-	"CRC/ECC Dynamic Repair Bus Error Frequency Settings",
-	"Eye widhth/height results check limits",
-	"RX SLS Handshake Recovery Finish GCR Messages",
-	"RX Wiretest Per-Pack Shadow Reg",
-	"RX Mode Per-Pack Shadow Reg",
-	"RX Cntl Per-Pack Shadow Reg",
-	"RX Cal Cntl Per-Pack Shadow Reg",
-	"RX Cal Accum inc value Reg",
-	"RX Cal Accum inc value Reg",
-	"RX Cal Accum dec value Reg",
-	"RX Cal Accum dec value Reg",
-	"RX Mode Per-Pack Shadow Reg",
-	"RX BER Control Reg",
-	"RX BER Mode Reg",
-	"RX Servo Timeout Select Regs 1",
-	"RX Servo Timeout Select Regs 2",
-	"RX Configurable Reset Control Register (CRCR)",
-	"RX Recal Servo Timeout Select Regs 1",
-	"RX Recal Servo Timeout Select Regs 2",
-	"RX Recal in progress control",
-	"RX Trace Per Pack Settings",
-	"RX BIST Cntl Reg",
-	"Per-Bus BUSCTL FIR Error Reset Reg",
-	"Per-Bus FIR Error Source-Isolation Reg",
-	"Per-Bus FIR Error Source-Isolation Mask Reg",
-	"Per-Bus FIR Error Injection Reg",
-	"Per-Bus FIR Register Write Alias",
-        "RX Clock Duty Cycle Adjust register"
-};
-
-// tx_mode_pl Register field name                                       data value   Description
-#define     tx_lane_pdwn                                      0x8000     //Used to drive inhibit (tristate) and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (tx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance.  Also note that per-group registers tx_lane_disabled_vec_0_15 and tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. 
-#define     tx_lane_pdwn_clear                                0x7FFF     // Clear mask
-#define     tx_lane_invert                                    0x4000     //Used to invert the polarity of a lane.
-#define     tx_lane_invert_clear                              0xBFFF     // Clear mask
-#define     tx_lane_quiesce_p_quiesce_to_0                    0x1000     //Used to force the output of the positive differential leg of a lane to a particular value.  Quiesce Lane to a Static 0 value
-#define     tx_lane_quiesce_p_quiesce_to_1                    0x2000     //Used to force the output of the positive differential leg of a lane to a particular value.  Quiesce Lane to a Static 1 value
-#define     tx_lane_quiesce_p_quiesce_to_z                    0x3000     //Used to force the output of the positive differential leg of a lane to a particular value.  Tri-State Lane Output
-#define     tx_lane_quiesce_p_clear                           0xCFFF     // Clear mask
-#define     tx_lane_quiesce_n_quiesce_to_0                    0x0400     //Used to force the output of the negative differential leg of a lane to a particular value.  Quiesce Lane to a Static 0 value
-#define     tx_lane_quiesce_n_quiesce_to_1                    0x0800     //Used to force the output of the negative differential leg of a lane to a particular value.  Quiesce Lane to a Static 1 value
-#define     tx_lane_quiesce_n_quiesce_to_z                    0x0C00     //Used to force the output of the negative differential leg of a lane to a particular value.  Tri-State Lane Output
-#define     tx_lane_quiesce_n_clear                           0xF3FF     // Clear mask
-#define     tx_lane_scramble_disable                          0x0200     //Used to disable the TX scrambler on a specific lane or all lanes by using a per-lane/per-group global write.
-#define     tx_lane_scramble_disable_clear                    0xFDFF     // Clear mask
-
-// tx_cntl_stat_pl Register field name                                  data value   Description
-#define     tx_fifo_err                                       0x8000     //Indicates an error condition in the TX FIFO.
-#define     tx_fifo_err_clear                                 0x7FFF     // Clear mask
-
-// tx_spare_mode_pl Register field name                                 data value   Description
-#define     tx_pl_spare_mode_0                                0x8000     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     tx_pl_spare_mode_1                                0x4000     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     tx_pl_spare_mode_2                                0x2000     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     tx_pl_spare_mode_3                                0x1000     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     tx_pl_spare_mode_4                                0x0800     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     tx_pl_spare_mode_5                                0x0400     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     tx_pl_spare_mode_6                                0x0200     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     tx_pl_spare_mode_7                                0x0100     //Per-lane spare mode latch
-#define     tx_pl_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// tx_bist_stat_pl Register field name                                  data value   Description
-#define     tx_lane_bist_err                                  0x8000     //Indicates a TXBIST error occurred.
-#define     tx_lane_bist_err_clear                            0x7FFF     // Clear mask
-#define     tx_lane_bist_done                                 0x4000     //Indicates TXBIST has completed. 
-#define     tx_lane_bist_done_clear                           0xBFFF     // Clear mask
-
-// tx_prbs_mode_pl Register field name                                  data value   Description
-#define     tx_prbs_tap_id_pattern_b                          0x2000     //TX Per-Lane PRBS Tap Selector  PRBS tap point B
-#define     tx_prbs_tap_id_pattern_c                          0x4000     //TX Per-Lane PRBS Tap Selector  PRBS tap point C
-#define     tx_prbs_tap_id_pattern_d                          0x6000     //TX Per-Lane PRBS Tap Selector  PRBS tap point D
-#define     tx_prbs_tap_id_pattern_e                          0x8000     //TX Per-Lane PRBS Tap Selector  PRBS tap point E
-#define     tx_prbs_tap_id_pattern_f                          0xA000     //TX Per-Lane PRBS Tap Selector  PRBS tap point F
-#define     tx_prbs_tap_id_pattern_g                          0xC000     //TX Per-Lane PRBS Tap Selector  PRBS tap point G
-#define     tx_prbs_tap_id_pattern_h                          0xE000     //TX Per-Lane PRBS Tap Selector  PRBS tap point H
-#define     tx_prbs_tap_id_clear                              0x1FFF     // Clear mask
-
-// tx_data_cntl_gcrmsg_pl Register field name                           data value   Description
-#define     tx_drv_data_pattern_gcrmsg_drv_wt                 0x1000     //GCR Message: TX Per Data Lane Drive Patterns  Drive Wiretest Pattern
-#define     tx_drv_data_pattern_gcrmsg_drv_1s                 0x2000     //GCR Message: TX Per Data Lane Drive Patterns  Drive All 1s Pattern
-#define     tx_drv_data_pattern_gcrmsg_drv_simple_A           0x3000     //GCR Message: TX Per Data Lane Drive Patterns  Drive Simple Pattern A
-#define     tx_drv_data_pattern_gcrmsg_drv_simple_B           0x4000     //GCR Message: TX Per Data Lane Drive Patterns  Drive Simple Pattern B
-#define     tx_drv_data_pattern_gcrmsg_drv_full_prbs23        0x5000     //GCR Message: TX Per Data Lane Drive Patterns  PRBS-23 Full Speed Scramble Pattern A thru H
-#define     tx_drv_data_pattern_gcrmsg_drv_red_prbs23         0x6000     //GCR Message: TX Per Data Lane Drive Patterns  PRBS-23 Reduced Density Scramble Pattern A thru H
-#define     tx_drv_data_pattern_gcrmsg_drv_9th_prbs23         0x7000     //GCR Message: TX Per Data Lane Drive Patterns  PRBS-23 9th pattern
-#define     tx_drv_data_pattern_gcrmsg_drv_ei3_iap            0x8000     //GCR Message: TX Per Data Lane Drive Patterns  EI-3 Busy IAP Pattern (EI4 only
-#define     tx_drv_data_pattern_gcrmsg_drv_ei3_prbs12         0x9000     //GCR Message: TX Per Data Lane Drive Patterns  Drive EI-3 PRBS-12 Shifted RDT Pattern (EI4 only
-#define     tx_drv_data_pattern_gcrmsg_TDR_square_wave        0xA000     //GCR Message: TX Per Data Lane Drive Patterns  Drives TDR Pulse-Square waves
-#define     tx_drv_data_pattern_gcrmsg_k28_5                  0xB000     //GCR Message: TX Per Data Lane Drive Patterns  Drives 20-bit K28.5 pattern - padded to 32 bits
-#define     tx_drv_data_pattern_gcrmsg_unused_A               0xC000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     tx_drv_data_pattern_gcrmsg_unused_B               0xD000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     tx_drv_data_pattern_gcrmsg_unused_C               0xE000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     tx_drv_data_pattern_gcrmsg_unused_D               0xF000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     tx_drv_data_pattern_gcrmsg_clear                  0x0FFF     // Clear mask
-#define     tx_drv_func_data_gcrmsg                           0x0800     //GCR Message: Functional Data
-#define     tx_drv_func_data_gcrmsg_clear                     0xF7FF     // Clear mask
-#define     tx_sls_lane_sel_gcrmsg                            0x0400     //GCR Message: SLS Commands & Recalibration
-#define     tx_sls_lane_sel_gcrmsg_clear                      0xFBFF     // Clear mask
-
-// tx_sync_pattern_gcrmsg_pl Register field name                        data value   Description
-#define     tx_drv_sync_patt_gcrmsg                           0x4000     //Sync Pattern
-#define     tx_drv_sync_patt_gcrmsg_clear                     0xBFFF     // Clear mask
-
-// tx_fir_pl Register field name                                        data value   Description
-#define     tx_pl_fir_errs                                    0x8000     //A 1 in this field indicates that a register or state machine parity error has occurred in per-lane logic.
-#define     tx_pl_fir_errs_clear                              0x7FFF     // Clear mask
-
-// tx_fir_mask_pl Register field name                                   data value   Description
-#define     tx_pl_fir_errs_mask                               0x8000     //FIR mask for all per-lane register or per-lane state machine parity errors.
-#define     tx_pl_fir_errs_mask_clear                         0x7FFF     // Clear mask
-
-// tx_fir_error_inject_pl Register field name                           data value   Description
-#define     tx_pl_fir_err_inj                                 0x8000     //TX Per-Lane Parity Error Injection
-#define     tx_pl_fir_err_inj_clear                           0x7FFF     // Clear mask
-
-// tx_mode_fast_pl Register field name                                  data value   Description
-#define     tx_err_inject                                     0x0000     //Software-only controlled register to inject one or more errors for one deserialized clock pulse on one or more specified beats on this lane.  Set bit position X to inject on beat X of a cycle.  Bits 0:3 are used in EDI and 0:1 are used in EI4. 
-#define     tx_err_inject_clear                               0x0FFF     // Clear mask
-#define     tx_err_inj_A_enable                               0x0800     //Control to enable the random bit error injection pattern A for this lane.(default)
-#define     tx_err_inj_A_enable_clear                         0xF7FF     // Clear mask
-#define     tx_err_inj_B_enable                               0x0400     //Control to enable the random bit error injection pattern B for this lane.(default)
-#define     tx_err_inj_B_enable_clear                         0xFBFF     // Clear mask
-
-// tx_tdr_stat_pl Register field name                                   data value   Description
-#define     tx_tdr_capt_val                                   0x8000     //value captured by TDR function, 1-bit shared over a pack, so this value should be the same for each bit (dmb)
-#define     tx_tdr_capt_val_clear                             0x7FFF     // Clear mask
-
-// tx_cntl_gcrmsg_pl Register field name                                data value   Description
-#define     tx_pdwn_lite_gcrmsg                               0x8000     //GCR Message: When set, gates TX data path (post FIFO) to 0s on unused spare lanes when not being recalibrated
-#define     tx_pdwn_lite_gcrmsg_clear                         0x7FFF     // Clear mask
-
-// tx_clk_mode_pg Register field name                                   data value   Description
-#define     tx_clk_pdwn                                       0x8000     //Used to disable the TX clock and put it into a low power state.
-#define     tx_clk_pdwn_clear                                 0x7FFF     // Clear mask
-#define     tx_clk_invert                                     0x4000     //Used to invert the polarity of the clock.
-#define     tx_clk_invert_clear                               0xBFFF     // Clear mask
-#define     tx_clk_quiesce_p_quiesce_to_0                     0x1000     //Used to force the output of the positive differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 0 value
-#define     tx_clk_quiesce_p_quiesce_to_1                     0x2000     //Used to force the output of the positive differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 1 value
-#define     tx_clk_quiesce_p_quiesce_to_z                     0x3000     //Used to force the output of the positive differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Tri-State Clock Lane Output
-#define     tx_clk_quiesce_p_clear                            0xCFFF     // Clear mask
-#define     tx_clk_quiesce_n_quiesce_to_0                     0x0400     //Used to force the output of the negative differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 0 value
-#define     tx_clk_quiesce_n_quiesce_to_1                     0x0800     //Used to force the output of the negative differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 1 value
-#define     tx_clk_quiesce_n_quiesce_to_z                     0x0C00     //Used to force the output of the negative differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Tri-State Clock Lane Output
-#define     tx_clk_quiesce_n_clear                            0xF3FF     // Clear mask
-#define     tx_clk_ddr_mode                                   0x0200     //Used to select TX clock QDR mode or DDR mode. 
-#define     tx_clk_ddr_mode_clear                             0xFDFF     // Clear mask
-
-// tx_spare_mode_pg Register field name                                 data value   Description
-#define     tx_pg_spare_mode_0                                0x8000     //Per-group spare mode latch
-#define     tx_pg_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     tx_pg_spare_mode_1                                0x4000     //Per-group spare mode latch
-#define     tx_pg_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     tx_pg_spare_mode_2                                0x2000     //Per-group spare mode latch
-#define     tx_pg_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     tx_pg_spare_mode_3                                0x1000     //Per-group spare mode latch
-#define     tx_pg_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     tx_pg_spare_mode_4                                0x0800     //Per-group spare mode latch
-#define     tx_pg_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     tx_pg_spare_mode_5                                0x0400     //Per-group spare mode latch
-#define     tx_pg_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     tx_pg_spare_mode_6                                0x0200     //Per-group spare mode latch
-#define     tx_pg_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     tx_pg_spare_mode_7                                0x0100     //Per-group spare mode latch
-#define     tx_pg_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// tx_cntl_stat_pg Register field name                                  data value   Description
-#define     tx_fifo_init                                      0x4000     //Used to initialize the TX FIFO and put it into a known reset state. This will cause the load to unload delay of the FIFO to be set to the value in the TX_FIFO_L2U_DLY field of the TX_FIFO_Mode register.
-#define     tx_fifo_init_clear                                0xBFFF     // Clear mask
-
-// tx_mode_pg Register field name                                       data value   Description
-#define     tx_max_bad_lanes                                  0x0000     //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus (NOTE: should match RX side)
-#define     tx_max_bad_lanes_clear                            0x07FF     // Clear mask
-#define     tx_msbswap                                        0x0400     //Used to enable end-for-end or msb swap of TX lanes.  For example, lanes 0 and N-1 swap, lanes 1 and N-2 swap, etc. 
-#define     tx_msbswap_clear                                  0xFBFF     // Clear mask
-#define     tx_pdwn_lite_disable                              0x0200     //Disables the power down lite feature of unused spare lanes (generally should match rx_pdwn_lite_disable)
-#define     tx_pdwn_lite_disable_clear                        0xFDFF     // Clear mask
-
-// tx_bus_repair_pg Register field name                                 data value   Description
-#define     tx_bus_repair_count                               0x0000     //This field is used to TBD.
-#define     tx_bus_repair_count_clear                         0x3FFF     // Clear mask
-#define     tx_bus_repair_pos_0                               0x0000     //This field is used to TBD.
-#define     tx_bus_repair_pos_0_clear                         0xC07F     // Clear mask
-#define     tx_bus_repair_pos_1                               0x0000     //This field is used to TBD.
-#define     tx_bus_repair_pos_1_clear                         0x3F80     // Clear mask
-
-// tx_grp_repair_vec_0_15_pg Register field name                        data value   Description
-#define     tx_grp_repair_vec_0_15                            0x0000     //This field is used to TBD.
-#define     tx_grp_repair_vec_0_15_clear                      0x0000     // Clear mask
-
-// tx_grp_repair_vec_16_31_pg Register field name                       data value   Description
-#define     tx_grp_repair_vec_16_31                           0x0000     //This field is used to TBD.
-#define     tx_grp_repair_vec_16_31_clear                     0x0000     // Clear mask
-
-// tx_reset_act_pg Register field name                                  data value   Description
-#define     tx_reset_cfg_ena                                  0x8000     //Enable Configurable Group Reset
-#define     tx_reset_cfg_ena_clear                            0x7FFF     // Clear mask
-#define     tx_clr_par_errs                                   0x0002     //Clear All TX Parity Error Latches
-#define     tx_clr_par_errs_clear                             0xFFFD     // Clear mask
-#define     tx_fir_reset                                      0x0001     //FIR Reset
-#define     tx_fir_reset_clear                                0xFFFE     // Clear mask
-
-// tx_bist_stat_pg Register field name                                  data value   Description
-#define     tx_clk_bist_err                                   0x4000     //Indicates a TXBIST error occurred.
-#define     tx_clk_bist_err_clear                             0xBFFF     // Clear mask
-#define     tx_clk_bist_done                                  0x1000     //Indicates TXBIST has completed. 
-#define     tx_clk_bist_done_clear                            0xEFFF     // Clear mask
-
-// tx_fir_pg Register field name                                        data value   Description
-#define     tx_pg_fir_errs_clear                              0x00FF     // Clear mask
-#define     tx_pl_fir_err                                     0x0001     //Summary bit indicating a TX per-lane register or state machine parity error has occurred in one or more lanes. The tx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane.
-#define     tx_pl_fir_err_clear                               0xFFFE     // Clear mask
-
-// tx_fir_mask_pg Register field name                                   data value   Description
-#define     tx_pg_fir_errs_mask_clear                         0x00FF     // Clear mask
-#define     tx_pl_fir_err_mask                                0x0001     //FIR mask for the summary bit that indicates a per-lane TX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane TX parity errors from causing a FIR error.\pmt
-#define     tx_pl_fir_err_mask_clear                          0xFFFE     // Clear mask
-
-// tx_fir_error_inject_pg Register field name                           data value   Description
-#define     tx_pg_fir_err_inj_inj_par_err                     0x1000     //TX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     tx_pg_fir_err_inj_clear                           0x00FF     // Clear mask
-
-// tx_id1_pg Register field name                                        data value   Description
-#define     tx_bus_id                                         0x0000     //This field is used to programmably set the bus number that a clkgrp belongs to.
-#define     tx_bus_id_clear                                   0x03FF     // Clear mask
-#define     tx_group_id                                       0x0000     //This field is used to programmably set the clock group number within a bus.
-#define     tx_group_id_clear                                 0xFE07     // Clear mask
-
-// tx_id2_pg Register field name                                        data value   Description
-#define     tx_last_group_id                                  0x0000     //This field is used to programmably set the last clock group number within a bus.
-#define     tx_last_group_id_clear                            0x03FF     // Clear mask
-
-// tx_id3_pg Register field name                                        data value   Description
-#define     tx_start_lane_id                                  0x0000     //This field is used to programmably set the first lane position in the group but relative to the bus.
-#define     tx_start_lane_id_clear                            0x80FF     // Clear mask
-#define     tx_end_lane_id                                    0x0000     //This field is used to programmably set the last lane position in the group but relative to the bus.
-#define     tx_end_lane_id_clear                              0x7F80     // Clear mask
-
-// tx_clk_cntl_gcrmsg_pg Register field name                            data value   Description
-#define     tx_drv_clk_pattern_gcrmsg_drv_wt                  0x4000     //TX Clock Drive Patterns  Drive Wiretest Pattern
-#define     tx_drv_clk_pattern_gcrmsg_drv_c4                  0x8000     //TX Clock Drive Patterns  Drive Clock Pattern
-#define     tx_drv_clk_pattern_gcrmsg_unused                  0xC000     //TX Clock Drive Patterns  Unused
-#define     tx_drv_clk_pattern_gcrmsg_clear                   0x3FFF     // Clear mask
-
-// tx_ffe_mode_pg Register field name                                   data value   Description
-#define     tx_ffe_test_mode_seg_test                         0x1000     //Driver Segment Test mode  Driver Output Test Mode
-#define     tx_ffe_test_mode_unused1                          0x2000     //Driver Segment Test mode  Reserved
-#define     tx_ffe_test_mode_unused2                          0x3000     //Driver Segment Test mode  Reserved
-#define     tx_ffe_test_mode_clear                            0xCFFF     // Clear mask
-#define     tx_ffe_test_override1r                            0x0200     //Driver Segment Test 1R Override
-#define     tx_ffe_test_override1r_clear                      0xFDFF     // Clear mask
-#define     tx_ffe_test_override2r                            0x0100     //Driver Segment Test 2R Override
-#define     tx_ffe_test_override2r_clear                      0xFEFF     // Clear mask
-
-// tx_ffe_main_pg Register field name                                   data value   Description
-#define     tx_ffe_main_p_enc                                 0x0000     //TBD
-#define     tx_ffe_main_p_enc_clear                           0x80FF     // Clear mask
-#define     tx_ffe_main_n_enc                                 0x0000     //TBD
-#define     tx_ffe_main_n_enc_clear                           0x7F80     // Clear mask
-
-// tx_ffe_post_pg Register field name                                   data value   Description
-#define     tx_ffe_post_p_enc                                 0x0000     //TBD This field is updated during TX BIST by logic temporarily
-#define     tx_ffe_post_p_enc_clear                           0x00FF     // Clear mask
-#define     tx_ffe_post_n_enc                                 0x0000     //TBD
-#define     tx_ffe_post_n_enc_clear                           0x1FE0     // Clear mask
-
-// tx_ffe_margin_pg Register field name                                 data value   Description
-#define     tx_ffe_margin_p_enc                               0x0000     //TBD
-#define     tx_ffe_margin_p_enc_clear                         0x00FF     // Clear mask
-#define     tx_ffe_margin_n_enc                               0x0000     //TBD
-#define     tx_ffe_margin_n_enc_clear                         0x1FE0     // Clear mask
-
-// tx_bad_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     tx_bad_lane1_gcrmsg                               0x0000     //GCR Message: Encoded bad lane one in relation to the entire TX bus
-#define     tx_bad_lane1_gcrmsg_clear                         0x01FF     // Clear mask
-#define     tx_bad_lane2_gcrmsg                               0x0000     //GCR Message: Encoded bad lane two in relation to the entire TX bus
-#define     tx_bad_lane2_gcrmsg_clear                         0xFE03     // Clear mask
-#define     tx_bad_lane_code_gcrmsg_bad_ln1_val               0x0001     //GCR Message: TX Bad Lane Code  Bad Lane 1 Valid
-#define     tx_bad_lane_code_gcrmsg_bad_lns12_val             0x0002     //GCR Message: TX Bad Lane Code  Bad Lanes 1 and 2 Valid
-#define     tx_bad_lane_code_gcrmsg_3plus_bad_lns             0x0003     //GCR Message: TX Bad Lane Code  3+ bad lanes
-#define     tx_bad_lane_code_gcrmsg_clear                     0xFFF0     // Clear mask
-
-// tx_sls_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     tx_sls_lane_gcrmsg                                0x0000     //GCR Message: Encoded SLS lane in relation to the entire TX bus
-#define     tx_sls_lane_gcrmsg_clear                          0x01FF     // Clear mask
-#define     tx_sls_lane_val_gcrmsg                            0x0100     //GCR Message: TX SLS Lane Valid
-#define     tx_sls_lane_val_gcrmsg_clear                      0xFEFF     // Clear mask
-
-// tx_wt_seg_enable_pg Register field name                              data value   Description
-#define     tx_wt_en_all_clk_segs_gcrmsg                      0x8000     //TX Clock Wiretest driver segnments enable
-#define     tx_wt_en_all_clk_segs_gcrmsg_clear                0x7FFF     // Clear mask
-#define     tx_wt_en_all_data_segs_gcrmsg                     0x4000     //TX Data  Wiretest driver segnments enable
-#define     tx_wt_en_all_data_segs_gcrmsg_clear               0xBFFF     // Clear mask
-
-// tx_lane_disabled_vec_0_15_pg Register field name                     data value   Description
-#define     tx_lane_disabled_vec_0_15                         0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     tx_lane_disabled_vec_0_15_clear                   0x0000     // Clear mask
-
-// tx_lane_disabled_vec_16_31_pg Register field name                    data value   Description
-#define     tx_lane_disabled_vec_16_31                        0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     tx_lane_disabled_vec_16_31_clear                  0x0000     // Clear mask
-
-// tx_sls_lane_mux_gcrmsg_pg Register field name                        data value   Description
-#define     tx_sls_lane_shdw_gcrmsg                           0x8000     //GCR Message: SLS lane shadowing or unshadowing functional data (used to set up TX mux controls)
-#define     tx_sls_lane_shdw_gcrmsg_clear                     0x7FFF     // Clear mask
-
-// tx_dyn_rpr_pg Register field name                                    data value   Description
-#define     tx_sls_hndshk_state_clear                         0x07FF     // Clear mask
-
-// tx_slv_mv_sls_ln_req_gcrmsg_pg Register field name                   data value   Description
-#define     tx_slv_mv_sls_shdw_req_gcrmsg                     0x8000     //GCR Message: Request to TX Slave to Move SLS Lane
-#define     tx_slv_mv_sls_shdw_req_gcrmsg_clear               0x7FFF     // Clear mask
-#define     tx_slv_mv_sls_shdw_rpr_req_gcrmsg                 0x4000     //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register
-#define     tx_slv_mv_sls_shdw_rpr_req_gcrmsg_clear           0xBFFF     // Clear mask
-#define     tx_slv_mv_sls_unshdw_req_gcrmsg                   0x2000     //GCR Message: Request to TX Slave to Move SLS Lane
-#define     tx_slv_mv_sls_unshdw_req_gcrmsg_clear             0xDFFF     // Clear mask
-#define     tx_slv_mv_sls_unshdw_rpr_req_gcrmsg               0x1000     //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register
-#define     tx_slv_mv_sls_unshdw_rpr_req_gcrmsg_clear         0xEFFF     // Clear mask
-#define     tx_bus_width                                      0x0000     //GCR Message: TX Bus Width
-#define     tx_bus_width_clear                                0xF01F     // Clear mask
-#define     tx_slv_mv_sls_rpr_req_gcrmsg                      0x0010     //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register
-#define     tx_slv_mv_sls_rpr_req_gcrmsg_clear                0xFFEF     // Clear mask
-#define     tx_sls_lane_sel_lg_gcrmsg                         0x0008     //GCR Message: Sets the tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios
-#define     tx_sls_lane_sel_lg_gcrmsg_clear                   0xFFF7     // Clear mask
-#define     tx_sls_lane_unsel_lg_gcrmsg                       0x0004     //GCR Message: Clears the tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios
-#define     tx_sls_lane_unsel_lg_gcrmsg_clear                 0xFFFB     // Clear mask
-#define     tx_spr_lns_pdwn_lite_gcrmsg                       0x0002     //GCR Message: Signals the TX side to Power Down Lite (data gate) unused spare lanes at the end of static repair
-#define     tx_spr_lns_pdwn_lite_gcrmsg_clear                 0xFFFD     // Clear mask
-
-// tx_wiretest_pp Register field name                                   data value   Description
-#define     tx_wt_pattern_length_256                          0x4000     //TX Wiretest Pattern Length  256
-#define     tx_wt_pattern_length_512                          0x8000     //TX Wiretest Pattern Length  512
-#define     tx_wt_pattern_length_1024                         0xC000     //TX Wiretest Pattern Length  1024
-#define     tx_wt_pattern_length_clear                        0x3FFF     // Clear mask
-
-// tx_mode_pp Register field name                                       data value   Description
-#define     tx_reduced_scramble_mode_full_1                   0x4000     //Enables/Disables and sets reduced density of scramble pattern.   Full density 
-#define     tx_reduced_scramble_mode_div2                     0x8000     //Enables/Disables and sets reduced density of scramble pattern.   Enable Div2 Reduced Density 
-#define     tx_reduced_scramble_mode_div4                     0xC000     //Enables/Disables and sets reduced density of scramble pattern.   Enable Div4 Reduced Density.
-#define     tx_reduced_scramble_mode_clear                    0x3FFF     // Clear mask
-#define     tx_fifo_l2u_dly_4_to_6_ui                         0x0800     //This field is used to read or set the TX FIFO load to unload delay according to the following.  4 to 6 UI (default
-#define     tx_fifo_l2u_dly_8_to_10_ui                        0x1000     //This field is used to read or set the TX FIFO load to unload delay according to the following.  8 to 10 UI
-#define     tx_fifo_l2u_dly_12_to_14_ui                       0x1800     //This field is used to read or set the TX FIFO load to unload delay according to the following.  12 to 14 UI 
-#define     tx_fifo_l2u_dly_16_to_18_ui                       0x2000     //This field is used to read or set the TX FIFO load to unload delay according to the following.  16 to 18 UI 
-#define     tx_fifo_l2u_dly_20_to_22_ui                       0x2800     //This field is used to read or set the TX FIFO load to unload delay according to the following.  20 to 22 UI
-#define     tx_fifo_l2u_dly_24_to_26_ui                       0x3000     //This field is used to read or set the TX FIFO load to unload delay according to the following.  24 to 26 UI
-#define     tx_fifo_l2u_dly_28_to_30_ui                       0x3800     //This field is used to read or set the TX FIFO load to unload delay according to the following.  28 to 30 UI
-#define     tx_fifo_l2u_dly_clear                             0xC7FF     // Clear mask
-
-// tx_sls_gcrmsg_pp Register field name                                 data value   Description
-#define     tx_snd_sls_cmd_gcrmsg                             0x8000     //GCR Message: Send SLS Command or Recalibration Data
-#define     tx_snd_sls_cmd_gcrmsg_clear                       0x7FFF     // Clear mask
-#define     tx_dyn_recal_tsr_ignore_gcrmsg                    0x4000     //GCR Message: Send Dynamic Recal SLS Commands all the time (not just during the Status Reporting interval)
-#define     tx_dyn_recal_tsr_ignore_gcrmsg_clear              0xBFFF     // Clear mask
-#define     tx_sls_cmd_gcrmsg                                 0x0000     //GCR Message: TX SLS Command
-#define     tx_sls_cmd_gcrmsg_clear                           0xC0FF     // Clear mask
-#define     tx_snd_sls_cmd_prev_gcrmsg                        0x0080     //GCR Message: Revert to sending previous SLS Command or Recalibration Data after recovery repair made
-#define     tx_snd_sls_cmd_prev_gcrmsg_clear                  0xFF7F     // Clear mask
-#define     tx_snd_sls_using_reg_scramble                     0x0040     //GCR Message: Send SLS command using normal scramble pattern instead of 9th pattern
-#define     tx_snd_sls_using_reg_scramble_clear               0xFFBF     // Clear mask
-
-// tx_ber_cntl_a_pp Register field name                                 data value   Description
-#define     tx_err_inj_a_rand_beat_dis                        0x8000     //Used to disable randomization of error inject on different beats of data for pattern A.
-#define     tx_err_inj_a_rand_beat_dis_clear                  0x7FFF     // Clear mask
-#define     tx_err_inj_a_fine_sel_1_16                        0x1000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-16 cycles
-#define     tx_err_inj_a_fine_sel_1_8                         0x2000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-8 cycles
-#define     tx_err_inj_a_fine_sel_1_4                         0x3000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-4 cycles
-#define     tx_err_inj_a_fine_sel_1_2                         0x4000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-2 cycles
-#define     tx_err_inj_a_fine_sel_fixed1                      0x5000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 1 cycle
-#define     tx_err_inj_a_fine_sel_fixed3                      0x6000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 3 cycles 
-#define     tx_err_inj_a_fine_sel_fixed7                      0x7000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 7 cycles.
-#define     tx_err_inj_a_fine_sel_clear                       0x8FFF     // Clear mask
-#define     tx_err_inj_a_coarse_sel_9_24                      0x0100     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 9-24, mean of 16.5
-#define     tx_err_inj_a_coarse_sel_13_20                     0x0200     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 13-20, mean of 16.5
-#define     tx_err_inj_a_coarse_sel_16_19                     0x0300     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-19, mean of 16.5
-#define     tx_err_inj_a_coarse_sel_17_18                     0x0400     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-17, mean of 16.5
-#define     tx_err_inj_a_coarse_sel_1_8                       0x0500     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 1-8, mean of 4.5
-#define     tx_err_inj_a_coarse_sel_3_6                       0x0600     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 3-6, mean of 4.5
-#define     tx_err_inj_a_coarse_sel_4_5                       0x0700     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 4-5, mean of 4.5
-#define     tx_err_inj_a_coarse_sel_fixed1                    0x0800     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 1
-#define     tx_err_inj_a_coarse_sel_fixed3                    0x0900     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 3
-#define     tx_err_inj_a_coarse_sel_fixed5                    0x0A00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 5
-#define     tx_err_inj_a_coarse_sel_fixed6                    0x0B00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 6
-#define     tx_err_inj_a_coarse_sel_fixed7                    0x0C00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 7
-#define     tx_err_inj_a_coarse_sel_fixed17                   0x0D00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 17
-#define     tx_err_inj_a_coarse_sel_fixed21                   0x0E00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 21
-#define     tx_err_inj_a_coarse_sel_fixed25                   0x0F00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 25
-#define     tx_err_inj_a_coarse_sel_clear                     0xF0FF     // Clear mask
-#define     tx_err_inj_a_ber_sel                              0x0000     //Used to set the random bit error injection rate for pattern A.  When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). 
-#define     tx_err_inj_a_ber_sel_clear                        0x3FC0     // Clear mask
-
-// tx_ber_cntl_b_pp Register field name                                 data value   Description
-#define     tx_err_inj_b_rand_beat_dis                        0x8000     //Used to disable randomization of error inject on different beats of data for pattern B.
-#define     tx_err_inj_b_rand_beat_dis_clear                  0x7FFF     // Clear mask
-#define     tx_err_inj_b_fine_sel_1_16                        0x1000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-16 cycles
-#define     tx_err_inj_b_fine_sel_1_8                         0x2000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-8 cycles
-#define     tx_err_inj_b_fine_sel_1_4                         0x3000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-4 cycles
-#define     tx_err_inj_b_fine_sel_1_2                         0x4000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-2 cycles
-#define     tx_err_inj_b_fine_sel_fixed1                      0x5000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 1 cycle
-#define     tx_err_inj_b_fine_sel_fixed3                      0x6000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 3 cycles 
-#define     tx_err_inj_b_fine_sel_fixed7                      0x7000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 7 cycles.
-#define     tx_err_inj_b_fine_sel_clear                       0x8FFF     // Clear mask
-#define     tx_err_inj_b_coarse_sel_9_24                      0x0100     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 9-24, mean of 16.5
-#define     tx_err_inj_b_coarse_sel_13_20                     0x0200     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 13-20, mean of 16.5
-#define     tx_err_inj_b_coarse_sel_16_19                     0x0300     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-19, mean of 16.5
-#define     tx_err_inj_b_coarse_sel_17_18                     0x0400     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-17, mean of 16.5
-#define     tx_err_inj_b_coarse_sel_1_8                       0x0500     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 1-8, mean of 4.5
-#define     tx_err_inj_b_coarse_sel_3_6                       0x0600     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 3-6, mean of 4.5
-#define     tx_err_inj_b_coarse_sel_4_5                       0x0700     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 4-5, mean of 4.5
-#define     tx_err_inj_b_coarse_sel_fixed1                    0x0800     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 1
-#define     tx_err_inj_b_coarse_sel_fixed3                    0x0900     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 3
-#define     tx_err_inj_b_coarse_sel_fixed5                    0x0A00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 5
-#define     tx_err_inj_b_coarse_sel_fixed6                    0x0B00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 6
-#define     tx_err_inj_b_coarse_sel_fixed7                    0x0C00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 7
-#define     tx_err_inj_b_coarse_sel_fixed17                   0x0D00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 17
-#define     tx_err_inj_b_coarse_sel_fixed21                   0x0E00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 21
-#define     tx_err_inj_b_coarse_sel_fixed25                   0x0F00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 25
-#define     tx_err_inj_b_coarse_sel_clear                     0xF0FF     // Clear mask
-#define     tx_err_inj_b_ber_sel                              0x0000     //Used to set the random bit error injection rate for pattern B.  When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). 
-#define     tx_err_inj_b_ber_sel_clear                        0x3FC0     // Clear mask
-
-// tx_dyn_recal_timeouts_pp Register field name                         data value   Description
-#define     tx_dyn_recal_interval_timeout_sel_tap1            0x1000     //TX Dynamic Recalibration Interval Timeout Selects  16kUI or 1.7us
-#define     tx_dyn_recal_interval_timeout_sel_tap2            0x2000     //TX Dynamic Recalibration Interval Timeout Selects  32kUI or 3.4us
-#define     tx_dyn_recal_interval_timeout_sel_tap3            0x3000     //TX Dynamic Recalibration Interval Timeout Selects  64kUI or 6.8us
-#define     tx_dyn_recal_interval_timeout_sel_tap4            0x4000     //TX Dynamic Recalibration Interval Timeout Selects  128kUI or 106.5ns
-#define     tx_dyn_recal_interval_timeout_sel_tap5            0x5000     //TX Dynamic Recalibration Interval Timeout Selects  256kUI or 1.7us
-#define     tx_dyn_recal_interval_timeout_sel_tap6            0x6000     //TX Dynamic Recalibration Interval Timeout Selects  8192kUI or 872.4us
-#define     tx_dyn_recal_interval_timeout_sel_tap7            0x7000     //TX Dynamic Recalibration Interval Timeout Selects  infinite
-#define     tx_dyn_recal_interval_timeout_sel_clear           0x8FFF     // Clear mask
-#define     tx_dyn_recal_status_rpt_timeout_sel_tap1          0x0400     //TX Dynamic Recalibration Status Reporting Timeout Selects  1024UI or 106.5ns
-#define     tx_dyn_recal_status_rpt_timeout_sel_tap2          0x0800     //TX Dynamic Recalibration Status Reporting Timeout Selects  2048UI or 212.9ns
-#define     tx_dyn_recal_status_rpt_timeout_sel_tap3          0x0C00     //TX Dynamic Recalibration Status Reporting Timeout Selects  4096UI or 426.0ns
-#define     tx_dyn_recal_status_rpt_timeout_sel_clear         0xF3FF     // Clear mask
-
-// tx_bist_cntl_pp Register field name                                  data value   Description
-#define     tx_bist_en                                        0x8000     //TBD. jgr
-#define     tx_bist_en_clear                                  0x7FFF     // Clear mask
-#define     tx_bist_clr                                       0x4000     //TBD. jgr
-#define     tx_bist_clr_clear                                 0xBFFF     // Clear mask
-#define     tx_bist_prbs7_en                                  0x2000     //TBD. This field is updated by the TX BIST logic when BIST is running. jgr
-#define     tx_bist_prbs7_en_clear                            0xDFFF     // Clear mask
-
-// tx_ber_cntl_sls_pp Register field name                               data value   Description
-#define     tx_err_inj_sls_mode                               0x8000     //Used to set the random bit error injection for pattern A to work during SLS transmission only. 
-#define     tx_err_inj_sls_mode_clear                         0x7FFF     // Clear mask
-#define     tx_err_inj_sls_all_cmd                            0x4000     //Used to qualify the SLS mode error injection for pattern A, to inject on all SLS command transmissions. 
-#define     tx_err_inj_sls_all_cmd_clear                      0xBFFF     // Clear mask
-#define     tx_err_inj_sls_recal                              0x2000     //Used to qualify the SLS mode error injection for pattern A, to inject on the calibration lane only when not sending an SLS command. See workbook for details.
-#define     tx_err_inj_sls_recal_clear                        0xDFFF     // Clear mask
-#define     tx_err_inj_sls_cmd                                0x0000     //Used to qualify the SLS mode error injection for pattern A, to inject on only this SLS command transmission. See workbook for SLS command codes.
-#define     tx_err_inj_sls_cmd_clear                          0xFFC0     // Clear mask
-
-// tx_cntl_pp Register field name                                       data value   Description
-#define     tx_enable_reduced_scramble                        0x8000     //Enables reduced density of scramble pattern. 
-#define     tx_enable_reduced_scramble_clear                  0x7FFF     // Clear mask
-
-// tx_reset_cfg_pp Register field name                                  data value   Description
-#define     tx_reset_cfg_hld_clear                            0x0000     // Clear mask
-
-// tx_tdr_cntl1_pp Register field name                                  data value   Description
-#define     tx_tdr_dac_cntl                                   0x0000     //Controls Variable Threshold Receiver for TDR function
-#define     tx_tdr_dac_cntl_clear                             0x00FF     // Clear mask
-#define     tx_tdr_phase_sel                                  0x0040     //Controls Phase Select for TDR function, 0 is for _n loeg, 1 is for _p leg.
-#define     tx_tdr_phase_sel_clear                            0xFFBF     // Clear mask
-
-// tx_tdr_cntl2_pp Register field name                                  data value   Description
-#define     tx_tdr_pulse_offset                               0x0000     //Offset value for TDR pulse.
-#define     tx_tdr_pulse_offset_clear                         0x000F     // Clear mask
-
-// tx_tdr_cntl3_pp Register field name                                  data value   Description
-#define     tx_tdr_pulse_width                                0x0000     //With of TDR pulse.
-#define     tx_tdr_pulse_width_clear                          0x000F     // Clear mask
-
-// tx_impcal_pb Register field name                                     data value   Description
-#define     tx_zcal_req                                       0x4000     //Impedance Calibration Sequence Enable
-#define     tx_zcal_req_clear                                 0xBFFF     // Clear mask
-#define     tx_zcal_done                                      0x2000     //Impedance Calibration Sequence Complete
-#define     tx_zcal_done_clear                                0xDFFF     // Clear mask
-#define     tx_zcal_error                                     0x1000     //Impedance Calibration Sequence Error
-#define     tx_zcal_error_clear                               0xEFFF     // Clear mask
-#define     tx_zcal_busy                                      0x0800     //Impedance Calibration Sequence Busy
-#define     tx_zcal_busy_clear                                0xF7FF     // Clear mask
-#define     tx_zcal_force_sample                              0x0400     //Impedance Comparison Sample Force
-#define     tx_zcal_force_sample_clear                        0xFBFF     // Clear mask
-#define     tx_zcal_cmp_out                                   0x0200     //Calibration Circuit Unqualified Sample
-#define     tx_zcal_cmp_out_clear                             0xFDFF     // Clear mask
-#define     tx_zcal_sample_cnt_clear                          0xFE00     // Clear mask
-
-// tx_impcal_nval_pb Register field name                                data value   Description
-#define     tx_zcal_n                                         0x0000     //Calibration Circuit NSeg Enable Value This holds the current value of the enabled segments and is 4x multiple of the actual segment count. May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices).
-#define     tx_zcal_n_clear                                   0x007F     // Clear mask
-
-// tx_impcal_pval_pb Register field name                                data value   Description
-#define     tx_zcal_p                                         0x0000     //Calibration Circuit PSeg Enable Value This holds the current value of the enabled segments and is 4x multiple of the actual segment count. May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0xA1 is maximum slices).
-#define     tx_zcal_p_clear                                   0x007F     // Clear mask
-
-// tx_impcal_p_4x_pb Register field name                                data value   Description
-#define     tx_zcal_p_4x                                      0x0000     //Calibration Circuit PSeg-4X Enable Value This holds the current value of the enabled segments and is 2x multiple of the actual segment count. May be read for current calibration result set during Calibration Sequence. May be written to immediately update circuit enables on each write. Used with tx_zcal_swo_* for manual calibration. Do not write when tx_zcal_req = 1. (binary code - 0x00 is zero slices and 0x15 is maximum slices).
-#define     tx_zcal_p_4x_clear                                0x07FF     // Clear mask
-
-// tx_impcal_swo1_pb Register field name                                data value   Description
-#define     tx_zcal_swo_en                                    0x8000     //Impedance Calibration Software Override
-#define     tx_zcal_swo_en_clear                              0x7FFF     // Clear mask
-#define     tx_zcal_swo_cal_segs                              0x4000     //Impedance Calibration Software Bank Select
-#define     tx_zcal_swo_cal_segs_clear                        0xBFFF     // Clear mask
-#define     tx_zcal_swo_cmp_inv                               0x2000     //Impedance Calibration Software Compare Invert
-#define     tx_zcal_swo_cmp_inv_clear                         0xDFFF     // Clear mask
-#define     tx_zcal_swo_cmp_offset                            0x1000     //Impedance Calibration Software Offset Flush
-#define     tx_zcal_swo_cmp_offset_clear                      0xEFFF     // Clear mask
-#define     tx_zcal_swo_cmp_reset                             0x0800     //Impedance Calibration Software Comparator reset
-#define     tx_zcal_swo_cmp_reset_clear                       0xF7FF     // Clear mask
-#define     tx_zcal_swo_powerdown                             0x0400     //Impedance Calibration Software Circuit Powerdown
-#define     tx_zcal_swo_powerdown_clear                       0xFBFF     // Clear mask
-#define     tx_zcal_cya_data_inv                              0x0200     //Impedance Calibration CYA Sample Inversion
-#define     tx_zcal_cya_data_inv_clear                        0xFDFF     // Clear mask
-#define     tx_zcal_test_ovr_2r                               0x0100     //Impedance Calibration Test-Only 2R segment override
-#define     tx_zcal_test_ovr_2r_clear                         0xFEFF     // Clear mask
-#define     tx_zcal_debug_mode_Filters                        0x0001     //Calibration Circuit Debug Mode Select  probeA=rcin_p, probeB=rcin_n Observe filter input nodes, rcin_n is off-chip.
-#define     tx_zcal_debug_mode_Comparators                    0x0002     //Calibration Circuit Debug Mode Select  probeA=comp_in_p, probeB=comp_in_n  Observe comparator inputs.
-#define     tx_zcal_debug_mode_disabled11                     0x0003     //Calibration Circuit Debug Mode Select  Debug mode disabled
-#define     tx_zcal_debug_mode_clear                          0xFFF0     // Clear mask
-
-// tx_impcal_swo2_pb Register field name                                data value   Description
-#define     tx_zcal_sm_min_val                                0x0000     //Impedance Calibration Minimum Search Threshold Low-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices).
-#define     tx_zcal_sm_min_val_clear                          0x01FF     // Clear mask
-#define     tx_zcal_sm_max_val                                0x0000     //Impedance Calibration Maximum Search Threshold High-side segment count limit used in calibration process. See circuit spec (binary code - 0x00 is zero slices and 0x50 is maximum slices).
-#define     tx_zcal_sm_max_val_clear                          0xFE03     // Clear mask
-
-// tx_analog_iref_pb Register field name                                data value   Description
-#define     tx_iref_bc                                        0x0000     //Bias Code for the Iref macros on the TX side. All eight 3 bit codes enable current out. The cml voltage swings of the output current will vary with this code.
-#define     tx_iref_bc_clear                                  0x1FFF     // Clear mask
-
-// tx_minikerf_pb Register field name                                   data value   Description
-#define     tx_minikerf                                       0x0000     //Used to configure the TX Minikerf for analog characterization.
-#define     tx_minikerf_clear                                 0x0000     // Clear mask
-
-// tx_init_version_pb Register field name                               data value   Description
-#define     tx_init_version_clear                             0x0000     // Clear mask
-
-// tx_scratch_reg_pb Register field name                                data value   Description
-#define     tx_scratch_reg_clear                              0x0000     // Clear mask
-
-// rx_mode_pl Register field name                                       data value   Description
-#define     rx_lane_pdwn                                      0x8000     //Used to receive inhibit and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (rx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance.  Also note that per-group registers rx_lane_disabled_vec_0_15 and rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. 
-#define     rx_lane_pdwn_clear                                0x7FFF     // Clear mask
-#define     rx_lane_scramble_disable                          0x0200     //Used to disable the RX descrambler on a specific lane or all lanes by using a per-lane/per-group global write.
-#define     rx_lane_scramble_disable_clear                    0xFDFF     // Clear mask
-
-// rx_cntl_pl Register field name                                       data value   Description
-#define     rx_block_lock_lane                                0x8000     //Enables rotation and checking for block lock. 
-#define     rx_block_lock_lane_clear                          0x7FFF     // Clear mask
-#define     rx_check_skew_lane                                0x4000     //Per-Lane Initialization controls. Checks skew request
-#define     rx_check_skew_lane_clear                          0xBFFF     // Clear mask
-#define     rx_pdwn_lite                                      0x2000     //GCR Message: When set, partially powers down unused spare lanes when not being recalibrated
-#define     rx_pdwn_lite_clear                                0xDFFF     // Clear mask
-
-// rx_spare_mode_pl Register field name                                 data value   Description
-#define     rx_pl_spare_mode_0                                0x8000     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     rx_pl_spare_mode_1                                0x4000     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     rx_pl_spare_mode_2                                0x2000     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     rx_pl_spare_mode_3                                0x1000     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     rx_pl_spare_mode_4                                0x0800     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     rx_pl_spare_mode_5                                0x0400     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     rx_pl_spare_mode_6                                0x0200     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     rx_pl_spare_mode_7                                0x0100     //Per-lane spare mode latch
-#define     rx_pl_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// rx_prot_edge_status_pl Register field name                           data value   Description
-#define     rx_phaserot_left_edge                             0x0000     //RX Phase Rotator left edge.
-#define     rx_phaserot_left_edge_clear                       0xC0FF     // Clear mask
-#define     rx_phaserot_right_edge                            0x0000     //RX Phase Rotator right edge.
-#define     rx_phaserot_right_edge_clear                      0xFF03     // Clear mask
-
-// rx_bist_stat_pl Register field name                                  data value   Description
-#define     rx_bist_err                                       0x8000     //Indicates a RXBIST error occurred.
-#define     rx_bist_err_clear                                 0x7FFF     // Clear mask
-#define     rx_bist_done                                      0x4000     //Indicates a RXBIST has completed. 
-#define     rx_bist_done_clear                                0xBFFF     // Clear mask
-
-// rx_offset_even_pl Register field name                                data value   Description
-#define     rx_offset_even_samp1                              0x0000     //This is the vertical offset of the even sampling latch.
-#define     rx_offset_even_samp1_clear                        0x80FF     // Clear mask
-#define     rx_offset_even_samp0                              0x0000     //This is the vertical offset of the even sampling latch.
-#define     rx_offset_even_samp0_clear                        0x7F80     // Clear mask
-
-// rx_offset_odd_pl Register field name                                 data value   Description
-#define     rx_offset_odd_samp1                               0x0000     //This is the vertical offset of the odd sampling latch.
-#define     rx_offset_odd_samp1_clear                         0x00FF     // Clear mask
-#define     rx_offset_odd_samp0                               0x0000     //This is the vertical offset of the odd sampling latch.
-#define     rx_offset_odd_samp0_clear                         0x7F80     // Clear mask
-
-// rx_amp_val_pl Register field name                                    data value   Description
-#define     rx_amp_peak                                       0x0000     //This is the vertical offset of the pre-amp.
-#define     rx_amp_peak_clear                                 0x0FFF     // Clear mask
-#define     rx_amp_gain                                       0x0000     //This is the gain setting of the pre-amp.
-#define     rx_amp_gain_clear                                 0xF0FF     // Clear mask
-#define     rx_amp_offset                                     0x0000     //This is the peaking setting of the pre-amp.
-#define     rx_amp_offset_clear                               0x3FC0     // Clear mask
-
-// rx_amp_cntl_pl Register field name                                   data value   Description
-#define     rx_amp_adj_done                                   0x8000     //VGA adjust is complete for this lane.
-#define     rx_amp_adj_done_clear                             0x7FFF     // Clear mask
-#define     rx_amp_adj_all_done_b                             0x4000     //VGA adjust is complete for this lane--qualified and asserted low for dot-OR reading.
-#define     rx_amp_adj_all_done_b_clear                       0xBFFF     // Clear mask
-
-// rx_prot_status_pl Register field name                                data value   Description
-#define     rx_phaserot_val                                   0x0000     //RX Phase Rotator current value.
-#define     rx_phaserot_val_clear                             0xC0FF     // Clear mask
-#define     rx_phaserot_ddc_complete                          0x0080     //RX DDC State Machine completion indicator.
-#define     rx_phaserot_ddc_complete_clear                    0xFF7F     // Clear mask
-#define     rx_phaserot_block_lock_err                        0x0040     //RX DDC State Machine block lock error indicator.
-#define     rx_phaserot_block_lock_err_clear                  0xFFBF     // Clear mask
-
-// rx_prot_mode_pl Register field name                                  data value   Description
-#define     rx_phaserot_offset                                0x0000     //RX Phase Rotator fixed offset from learned value.
-#define     rx_phaserot_offset_clear                          0xC0FF     // Clear mask
-
-// rx_prot_cntl_pl Register field name                                  data value   Description
-#define     rx_bump_left_half_ui                              0x8000     //Per-Lane Bump left 1/2 UI control (Self-Clearing)
-#define     rx_bump_left_half_ui_clear                        0x7FFF     // Clear mask
-#define     rx_bump_right_half_ui                             0x4000     //Per-Lane Bump right 1/2 UI control (Self-Clearing)
-#define     rx_bump_right_half_ui_clear                       0xBFFF     // Clear mask
-#define     rx_bump_one_ui                                    0x2000     //Per-Lane Bump 1 UI control (Self-Clearing)
-#define     rx_bump_one_ui_clear                              0xDFFF     // Clear mask
-#define     rx_bump_two_ui                                    0x1000     //Per-Lane Bump 2 UI control (Self-Clearing)
-#define     rx_bump_two_ui_clear                              0xEFFF     // Clear mask
-#define     rx_ext_sr                                         0x0800     //RX Manual Phase Rotator Shift Right Pulse
-#define     rx_ext_sr_clear                                   0xF7FF     // Clear mask
-#define     rx_ext_sl                                         0x0400     //RX Manual Phase Rotator Shift Left Pulse
-#define     rx_ext_sl_clear                                   0xFBFF     // Clear mask
-
-// rx_fifo_stat_pl Register field name                                  data value   Description
-#define     rx_fifo_l2u_dly                                   0x0000     //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine.  For setting X, the latency is 4*X to 4*X+4 UI.  Default is 20-24 UI.
-#define     rx_fifo_l2u_dly_clear                             0x0FFF     // Clear mask
-#define     rx_fifo_init                                      0x0800     //Initializes the fifo unload counter with the load counter and initializes the fifo load to unload delay
-#define     rx_fifo_init_clear                                0xF7FF     // Clear mask
-
-// rx_ap_pl Register field name                                         data value   Description
-#define     rx_ap_even_samp                                   0x0000     //TBD
-#define     rx_ap_even_samp_clear                             0x00FF     // Clear mask
-#define     rx_ap_odd_samp                                    0x0000     //TBD
-#define     rx_ap_odd_samp_clear                              0xFF00     // Clear mask
-
-// rx_an_pl Register field name                                         data value   Description
-#define     rx_an_even_samp                                   0x0000     //TBD
-#define     rx_an_even_samp_clear                             0x00FF     // Clear mask
-#define     rx_an_odd_samp                                    0x0000     //TBD
-#define     rx_an_odd_samp_clear                              0xFF00     // Clear mask
-
-// rx_amin_pl Register field name                                       data value   Description
-#define     rx_amin_even                                      0x0000     //TBD
-#define     rx_amin_even_clear                                0x00FF     // Clear mask
-#define     rx_amin_odd                                       0x0000     //TBD
-#define     rx_amin_odd_clear                                 0xFF00     // Clear mask
-
-// rx_h1_even_pl Register field name                                    data value   Description
-#define     rx_h1_even_samp1                                  0x0000     //TBD
-#define     rx_h1_even_samp1_clear                            0x00FF     // Clear mask
-#define     rx_h1_even_samp0                                  0x0000     //TBD
-#define     rx_h1_even_samp0_clear                            0x7F80     // Clear mask
-
-// rx_h1_odd_pl Register field name                                     data value   Description
-#define     rx_h1_odd_samp1                                   0x0000     //TBD
-#define     rx_h1_odd_samp1_clear                             0x00FF     // Clear mask
-#define     rx_h1_odd_samp0                                   0x0000     //TBD
-#define     rx_h1_odd_samp0_clear                             0x7F80     // Clear mask
-
-// rx_prbs_mode_pl Register field name                                  data value   Description
-#define     rx_prbs_tap_id_pattern_b                          0x2000     //Per-Lane PRBS Tap Selector  PRBS tap point B
-#define     rx_prbs_tap_id_pattern_c                          0x4000     //Per-Lane PRBS Tap Selector  PRBS tap point C
-#define     rx_prbs_tap_id_pattern_d                          0x6000     //Per-Lane PRBS Tap Selector  PRBS tap point D
-#define     rx_prbs_tap_id_pattern_e                          0x8000     //Per-Lane PRBS Tap Selector  PRBS tap point E
-#define     rx_prbs_tap_id_pattern_F                          0xA000     //Per-Lane PRBS Tap Selector  PRBS tap point F
-#define     rx_prbs_tap_id_pattern_g                          0xC000     //Per-Lane PRBS Tap Selector  PRBS tap point G
-#define     rx_prbs_tap_id_pattern_h                          0xE000     //Per-Lane PRBS Tap Selector  PRBS tap point H
-#define     rx_prbs_tap_id_clear                              0x1FFF     // Clear mask
-
-// rx_stat_pl Register field name                                       data value   Description
-#define     rx_some_block_locked                              0x8000     //Per-Lane Block Lock Indicator
-#define     rx_some_block_locked_clear                        0x7FFF     // Clear mask
-#define     rx_all_block_locked_b                             0x4000     //Per-Lane Block Lock Indicator
-#define     rx_all_block_locked_b_clear                       0xBFFF     // Clear mask
-#define     rx_some_skew_valid                                0x2000     //Per-Lane Deskew Pattern B Detect Indicator
-#define     rx_some_skew_valid_clear                          0xDFFF     // Clear mask
-#define     rx_all_skew_valid_b                               0x1000     //Per-Lane Deskew Pattern B Detect Indicato (Active Low)r
-#define     rx_all_skew_valid_b_clear                         0xEFFF     // Clear mask
-#define     rx_some_prbs_synced                               0x0800     //Per-Lane PRBS Synchronization Indicator
-#define     rx_some_prbs_synced_clear                         0xF7FF     // Clear mask
-#define     rx_prbs_synced_b                                  0x0400     //Per-Lane PRBS Synchronization Indicator (Active Low)
-#define     rx_prbs_synced_b_clear                            0xFBFF     // Clear mask
-#define     rx_skew_value                                     0x0000     //Per-Lane PRBS Synchronization Count
-#define     rx_skew_value_clear                               0xFC0F     // Clear mask
-
-// rx_deskew_stat_pl Register field name                                data value   Description
-#define     rx_bad_block_lock                                 0x8000     //Deskew Step block lock not established--lane marked bad
-#define     rx_bad_block_lock_clear                           0x7FFF     // Clear mask
-#define     rx_bad_skew                                       0x4000     //Deskew Step skew value not detected--lane marked bad
-#define     rx_bad_skew_clear                                 0xBFFF     // Clear mask
-#define     rx_bad_deskew                                     0x2000     //Deskew Step deskew value
-#define     rx_bad_deskew_clear                               0xDFFF     // Clear mask
-
-// rx_fir_pl Register field name                                        data value   Description
-#define     rx_pl_fir_errs_clear                              0x3FFF     // Clear mask
-
-// rx_fir_mask_pl Register field name                                   data value   Description
-#define     rx_pl_fir_errs_mask_err_pl_mask_ddc_sm            0x4000     //FIR mask for register or state machine parity checkers in per-lane logic. A value of 1 masks the error from generating a FIR error.  Per-Lane DDC SM Parity Error.
-#define     rx_pl_fir_errs_mask_clear                         0x3FFF     // Clear mask
-
-// rx_fir_error_inject_pl Register field name                           data value   Description
-#define     rx_pl_fir_err_inj_inj_par_err                     0x4000     //RX Per-Lane Parity Error Injection  While this value is a 1, the parity bit is inverted in the specific parity checker.
-#define     rx_pl_fir_err_inj_clear                           0x3FFF     // Clear mask
-
-// rx_sls_pl Register field name                                        data value   Description
-#define     rx_sls_lane_sel                                   0x8000     //Selects which lane to receive SLS Commands and Recalibration Data on
-#define     rx_sls_lane_sel_clear                             0x7FFF     // Clear mask
-#define     rx_9th_pattern_en                                 0x4000     //Sets RX Descrabmler to use 9th Scramble Pattern
-#define     rx_9th_pattern_en_clear                           0xBFFF     // Clear mask
-
-// rx_wt_status_pl Register field name                                  data value   Description
-#define     rx_wt_lane_disabled                               0x8000     //Per-Lane Wiretest lane disabled status
-#define     rx_wt_lane_disabled_clear                         0x7FFF     // Clear mask
-#define     rx_wt_lane_inverted                               0x4000     //Per-Lane Wiretest lane inverted/swapped status
-#define     rx_wt_lane_inverted_clear                         0xBFFF     // Clear mask
-#define     rx_wt_lane_bad_code_n_stuck_1                     0x0800     //Per-Lane Wiretest Lane Bad code  N-leg stuck at 1.
-#define     rx_wt_lane_bad_code_n_stuck_0                     0x1000     //Per-Lane Wiretest Lane Bad code  N-leg stuck at 0.
-#define     rx_wt_lane_bad_code_p_stuck_1                     0x1800     //Per-Lane Wiretest Lane Bad code  P-leg stuck at 1.
-#define     rx_wt_lane_bad_code_p_stuck_0                     0x2000     //Per-Lane Wiretest Lane Bad code  P-leg stuck at 0.
-#define     rx_wt_lane_bad_code_n_or_p_floating               0x2800     //Per-Lane Wiretest Lane Bad code  N- or P- leg floating-swapping undetermined.
-#define     rx_wt_lane_bad_code_p_or_n_floating               0x3000     //Per-Lane Wiretest Lane Bad code  P or N leg floating--swapping undetermined.
-#define     rx_wt_lane_bad_code_unknown                       0x3800     //Per-Lane Wiretest Lane Bad code  Unknown failure.
-#define     rx_wt_lane_bad_code_clear                         0xC7FF     // Clear mask
-
-// rx_fifo_cntl_pl Register field name                                  data value   Description
-#define     rx_fifo_inc_l2u_dly                               0x8000     //Increment existing FIFO load-to-unload delay register.
-#define     rx_fifo_inc_l2u_dly_clear                         0x7FFF     // Clear mask
-#define     rx_fifo_dec_l2u_dly                               0x4000     //Decrement existing FIFO load-to-unload delay register.
-#define     rx_fifo_dec_l2u_dly_clear                         0xBFFF     // Clear mask
-#define     rx_clr_skew_valid                                 0x2000     //Clear skew valid registers                            
-#define     rx_clr_skew_valid_clear                           0xDFFF     // Clear mask
-
-// rx_ber_status_pl Register field name                                 data value   Description
-#define     rx_ber_count                                      0x0000     //Per-Lane (PL) Diagnostic Bit Error Rate (BER) error counter. Increments when in diagnostic BER mode AND the output of the descrambler is non-zero. This counter counts errors on every UI so it is a true BER counter.
-#define     rx_ber_count_clear                                0x00FF     // Clear mask
-#define     rx_ber_count_saturated                            0x0080     //PL Diag BER Error Counter saturation indicator. When '1' indicates that the error counter has saturated to the selected max value. A global per-lane read of this field will indicate if any lane error counters in the group are saturated.
-#define     rx_ber_count_saturated_clear                      0xFF7F     // Clear mask
-#define     rx_ber_count_frozen_by_lane                       0x0040     //PL Diag BER Error Counter and or PP Timer has been frozen by another lane's error counter being saturated.
-#define     rx_ber_count_frozen_by_lane_clear                 0xFFBF     // Clear mask
-#define     rx_ber_count_frozen_by_timer                      0x0020     //PL Diag BER Error Counter has been frozen by a diag BER timer becoming saturated.
-#define     rx_ber_count_frozen_by_timer_clear                0xFFDF     // Clear mask
-#define     rx_ber_timer_saturated                            0x0010     //PL Diag BER Timer saturation indicator. When '1' indicates that the pack BER timer has saturated to the max value. A global per-lane read of this field will indicate if any timer in the group has saturated.
-#define     rx_ber_timer_saturated_clear                      0xFFEF     // Clear mask
-
-// rx_ber_timer_0_15_pl Register field name                             data value   Description
-#define     rx_ber_timer_value_0_15                           0x0000     //PL Diag BER Timer value for this lane, bits 0-15. All lanes in a pack share a timer and will have the same timer value. The value can either be read on one lane in a pack to save data collection time or all lanes can be read.
-#define     rx_ber_timer_value_0_15_clear                     0x0000     // Clear mask
-
-// rx_ber_timer_16_31_pl Register field name                            data value   Description
-#define     rx_ber_timer_value_16_31                          0x0000     //PL Diag BER Timer value, bits 16-31.
-#define     rx_ber_timer_value_16_31_clear                    0x0000     // Clear mask
-
-// rx_ber_timer_32_39_pl Register field name                            data value   Description
-#define     rx_ber_timer_value_32_39                          0x0000     //PL Diag BER Timer value, bits 32-39.
-#define     rx_ber_timer_value_32_39_clear                    0x00FF     // Clear mask
-
-// rx_servo_cntl_pl Register field name                                 data value   Description
-#define     rx_servo_op_done                                  0x8000     //Servo Op completed
-#define     rx_servo_op_done_clear                            0x7FFF     // Clear mask
-#define     rx_servo_op_all_done_b                            0x4000     //All Servo Op (asserted low for global dot-Or reading)
-#define     rx_servo_op_all_done_b_clear                      0xBFFF     // Clear mask
-#define     rx_servo_op                                       0x0000     //Servo Operation code
-#define     rx_servo_op_clear                                 0xC1FF     // Clear mask
-#define     rx_scope_en                                       0x0100     //Set this bit to enable per lane scope mode
-#define     rx_scope_en_clear                                 0xFEFF     // Clear mask
-
-// rx_fifo_diag_0_15_pl Register field name                             data value   Description
-#define     rx_fifo_out_0_15                                  0x0000     //Diag Capture: fifo entries 0 to 15
-#define     rx_fifo_out_0_15_clear                            0x0000     // Clear mask
-
-// rx_fifo_diag_16_31_pl Register field name                            data value   Description
-#define     rx_fifo_out_16_31                                 0x0000     //Diag Capture: fifo entries 16 to 31
-#define     rx_fifo_out_16_31_clear                           0x0000     // Clear mask
-
-// rx_fifo_diag_32_47_pl Register field name                            data value   Description
-#define     rx_fifo_out_32_47                                 0x0000     //Diag Capture: fifo entries 32 to 47
-#define     rx_fifo_out_32_47_clear                           0x0000     // Clear mask
-
-// rx_eye_width_status_pl Register field name                           data value   Description
-#define     rx_eye_width                                      0x0000     //RX Current Eye Width (in PR steps).
-#define     rx_eye_width_clear                                0x00FF     // Clear mask
-#define     rx_hist_min_eye_width_valid                       0x0080     //RX Historic Eye Minimum is valid for this lane.
-#define     rx_hist_min_eye_width_valid_clear                 0xFF7F     // Clear mask
-#define     rx_hist_min_eye_width                             0x0000     //RX Historic Eye Minimum--per-pack register valid for this lane if rx_hist_eye_min_valid is asserted for this lane.
-#define     rx_hist_min_eye_width_clear                       0xDFC0     // Clear mask
-
-// rx_eye_width_cntl_pl Register field name                             data value   Description
-#define     rx_reset_hist_eye_width_min                       0x8000     //RX Historic Eye Minimum Reset--reset historic min to maximum value and clears valid bits.
-#define     rx_reset_hist_eye_width_min_clear                 0x7FFF     // Clear mask
-
-// rx_dfe_clkadj_pl Register field name                                 data value   Description
-#define     rx_dfe_clkadj                                     0x0000     //TBD
-#define     rx_dfe_clkadj_clear                               0x0FFF     // Clear mask
-
-// rx_trace_pl Register field name                                      data value   Description
-#define     rx_ln_trc_en                                      0x8000     //Enable tracing of this lane
-#define     rx_ln_trc_en_clear                                0x7FFF     // Clear mask
-
-// rx_servo_ber_count_pl Register field name                            data value   Description
-#define     rx_servo_ber_count                                0x0000     //Servo-based bit error count.
-#define     rx_servo_ber_count_clear                          0x000F     // Clear mask
-
-// rx_eye_opt_stat_pl Register field name                               data value   Description
-#define     rx_bad_eye_opt_ber                                0x8000     //Eye opt Step failed BER test--lane marked bad
-#define     rx_bad_eye_opt_ber_clear                          0x7FFF     // Clear mask
-#define     rx_bad_eye_opt_width                              0x4000     //Eye opt Step failed width test--lane marked bad
-#define     rx_bad_eye_opt_width_clear                        0xBFFF     // Clear mask
-#define     rx_bad_eye_opt_height                             0x2000     //Eye opt Step failed height test--lane marked bad
-#define     rx_bad_eye_opt_height_clear                       0xDFFF     // Clear mask
-#define     rx_bad_eye_opt_ddc                                0x1000     //Eye opt Step failed dynamic data centering--lane marked bad
-#define     rx_bad_eye_opt_ddc_clear                          0xEFFF     // Clear mask
-
-// rx_clk_mode_pg Register field name                                   data value   Description
-#define     rx_clk_pdwn                                       0x8000     //Used to disable the rx clock and put it into a low power state.
-#define     rx_clk_pdwn_clear                                 0x7FFF     // Clear mask
-#define     rx_clk_invert                                     0x4000     //Used to invert the polarity of the clock.
-#define     rx_clk_invert_clear                               0xBFFF     // Clear mask
-
-// rx_spare_mode_pg Register field name                                 data value   Description
-#define     rx_pg_spare_mode_0                                0x8000     //Per-group spare mode latch
-#define     rx_pg_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     rx_pg_spare_mode_1                                0x4000     //Per-group spare mode latch
-#define     rx_pg_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     rx_pg_spare_mode_2                                0x2000     //Per-group spare mode latch
-#define     rx_pg_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     rx_pg_spare_mode_3                                0x1000     //Per-group spare mode latch
-#define     rx_pg_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     rx_pg_spare_mode_4                                0x0800     //Per-group spare mode latch
-#define     rx_pg_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     rx_pg_spare_mode_5                                0x0400     //Per-group spare mode latch
-#define     rx_pg_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     rx_pg_spare_mode_6                                0x0200     //Per-group spare mode latch
-#define     rx_pg_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     rx_pg_spare_mode_7                                0x0100     //Per-group spare mode latch
-#define     rx_pg_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// rx_stop_cntl_stat_pg Register field name                             data value   Description
-#define     rx_stop_state_enable                              0x8000     //Enable State machine stop of address
-#define     rx_stop_state_enable_clear                        0x7FFF     // Clear mask
-#define     rx_state_stopped                                  0x4000     //State Machines stopped
-#define     rx_state_stopped_clear                            0xBFFF     // Clear mask
-#define     rx_resume_from_stop                               0x2000     //Resume stopped state machines and /or counters
-#define     rx_resume_from_stop_clear                         0xDFFF     // Clear mask
-#define     rx_stop_addr_msb                                  0x0000     //Stop address Most-significant four bits 0 to 3
-#define     rx_stop_addr_msb_clear                            0xFF0F     // Clear mask
-#define     rx_stop_mask_msb                                  0x0000     //Stop mask    Most-significant four bits 0 to 3
-#define     rx_stop_mask_msb_clear                            0xF0F0     // Clear mask
-
-// rx_mode_pg Register field name                                       data value   Description
-#define     rx_master_mode                                    0x8000     //Master Mode
-#define     rx_master_mode_clear                              0x7FFF     // Clear mask
-#define     rx_disable_fence_reset                            0x4000     //Set to disable clearing of the RX and TX fence controls at the end of training. 
-#define     rx_disable_fence_reset_clear                      0xBFFF     // Clear mask
-#define     rx_pdwn_lite_disable                              0x2000     //Disables the power down lite feature of unused spare lanes (generally should match tx_pdwn_lite_disable)
-#define     rx_pdwn_lite_disable_clear                        0xDFFF     // Clear mask
-#define     rx_use_sls_as_spr                                 0x1000     //Determines whether the RX SLS lane can be used as a spare lane on the bus to repair bad lanes (NOTE: if yes, recal is disabled once the SLS lane has been used as a spare lane.)
-#define     rx_use_sls_as_spr_clear                           0xEFFF     // Clear mask
-
-// rx_bus_repair_pg Register field name                                 data value   Description
-#define     rx_bus_repair_count                               0x0000     //TBD
-#define     rx_bus_repair_count_clear                         0x3FFF     // Clear mask
-#define     rx_bus_repair_pos_0                               0x0000     //TBD
-#define     rx_bus_repair_pos_0_clear                         0xC07F     // Clear mask
-#define     rx_bus_repair_pos_1                               0x0000     //TBD
-#define     rx_bus_repair_pos_1_clear                         0x3F80     // Clear mask
-
-// rx_grp_repair_vec_0_15_pg Register field name                        data value   Description
-#define     rx_grp_repair_vec_0_15                            0x0000     //TBD
-#define     rx_grp_repair_vec_0_15_clear                      0x0000     // Clear mask
-
-// rx_grp_repair_vec_16_31_pg Register field name                       data value   Description
-#define     rx_grp_repair_vec_16_31                           0x0000     //TBD
-#define     rx_grp_repair_vec_16_31_clear                     0x0000     // Clear mask
-
-// rx_stop_addr_lsb_pg Register field name                              data value   Description
-#define     rx_stop_addr_lsb                                  0x0000     //Stop address least-significant 16 bits 4 to 19 
-#define     rx_stop_addr_lsb_clear                            0x0000     // Clear mask
-
-// rx_stop_mask_lsb_pg Register field name                              data value   Description
-#define     rx_stop_mask_lsb                                  0x0000     //Stop mask    least-significant 16 bits 4 to 19
-#define     rx_stop_mask_lsb_clear                            0x0000     // Clear mask
-
-// rx_reset_act_pg Register field name                                  data value   Description
-#define     rx_reset_cfg_ena                                  0x8000     //Enable Configurable Group Reset
-#define     rx_reset_cfg_ena_clear                            0x7FFF     // Clear mask
-#define     rx_clr_par_errs                                   0x0002     //Clear All RX Parity Error Latches
-#define     rx_clr_par_errs_clear                             0xFFFD     // Clear mask
-#define     rx_fir_reset                                      0x0001     //FIR Reset
-#define     rx_fir_reset_clear                                0xFFFE     // Clear mask
-
-// rx_id1_pg Register field name                                        data value   Description
-#define     rx_bus_id                                         0x0000     //This field is used to programmably set the bus number that a clkgrp belongs to.
-#define     rx_bus_id_clear                                   0x03FF     // Clear mask
-#define     rx_group_id                                       0x0000     //This field is used to programmably set the clock group number within a bus.
-#define     rx_group_id_clear                                 0xFE07     // Clear mask
-
-// rx_id2_pg Register field name                                        data value   Description
-#define     rx_last_group_id                                  0x0000     //This field is used to programmably set the last clock group number within a bus.
-#define     rx_last_group_id_clear                            0x03FF     // Clear mask
-
-// rx_id3_pg Register field name                                        data value   Description
-#define     rx_start_lane_id                                  0x0000     //This field is used to programmably set the first lane position in the group but relative to the bus.
-#define     rx_start_lane_id_clear                            0x80FF     // Clear mask
-#define     rx_end_lane_id                                    0x0000     //This field is used to programmably set the last lane position in the group but relative to the bus.
-#define     rx_end_lane_id_clear                              0x7F80     // Clear mask
-
-// rx_minikerf_pg Register field name                                   data value   Description
-#define     rx_minikerf                                       0x0000     //Used to configure the rx Minikerf for analog characterization.
-#define     rx_minikerf_clear                                 0x0000     // Clear mask
-
-// rx_sls_mode_pg Register field name                                   data value   Description
-#define     rx_sls_disable                                    0x8000     //Disables receiving & decoding of SLS commands
-#define     rx_sls_disable_clear                              0x7FFF     // Clear mask
-#define     tx_sls_disable                                    0x4000     //Disables the sending of SLS commands
-#define     tx_sls_disable_clear                              0xBFFF     // Clear mask
-#define     rx_sls_cntr_tap_pts_tap2                          0x1000     //How Long the SLS RX Command Needs to be Stable for.  EDI - 32 c8 clks; EI4 - 64 c4 clks
-#define     rx_sls_cntr_tap_pts_tap3                          0x2000     //How Long the SLS RX Command Needs to be Stable for.  EDI - 64 c8 clks; EI4 - 128 c4 clks
-#define     rx_sls_cntr_tap_pts_tap4                          0x3000     //How Long the SLS RX Command Needs to be Stable for.  EDI - 128 c8 clks; EI4 - 256 c4 clks
-#define     rx_sls_cntr_tap_pts_clear                         0xCFFF     // Clear mask
-#define     rx_nonsls_cntr_tap_pts_tap2                       0x0400     //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data).  EDI - 64 c8 clks; EI4 - 128 c4 clks
-#define     rx_nonsls_cntr_tap_pts_tap3                       0x0800     //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data).  EDI - 128 c8 clks; EI4 - 256 c4 clks
-#define     rx_nonsls_cntr_tap_pts_tap4                       0x0C00     //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data).  EDI - 256 c8 clks; EI4 - 512 c4 clks
-#define     rx_nonsls_cntr_tap_pts_clear                      0xF3FF     // Clear mask
-#define     rx_sls_err_chk_run                                0x0200     //Run SLS error check counter
-#define     rx_sls_err_chk_run_clear                          0xFDFF     // Clear mask
-
-// rx_training_start_pg Register field name                             data value   Description
-#define     rx_start_wiretest                                 0x8000     //When this register is written to a 1 the training state machine will run the wiretest portion of the training states.
-#define     rx_start_wiretest_clear                           0x7FFF     // Clear mask
-#define     rx_start_deskew                                   0x4000     //When this register is written to a 1 the training state machine will run the deskew portion of the training states.
-#define     rx_start_deskew_clear                             0xBFFF     // Clear mask
-#define     rx_start_eye_opt                                  0x2000     //When this register is written to a 1 the training state machine will run the data eye optimization portion of the training states.
-#define     rx_start_eye_opt_clear                            0xDFFF     // Clear mask
-#define     rx_start_repair                                   0x1000     //When this register is written to a 1 the training state machine will run the static lane repair portion of the training states.
-#define     rx_start_repair_clear                             0xEFFF     // Clear mask
-#define     rx_start_func_mode                                0x0800     //When this register is written to a 1 the training state machine will run the transition to functional data portion of the training states.
-#define     rx_start_func_mode_clear                          0xF7FF     // Clear mask
-#define     rx_start_bist                                     0x0400     //Run initializations for BIST before enabling the BIST state machine. 
-#define     rx_start_bist_clear                               0xFBFF     // Clear mask
-#define     rx_start_offset_cal                               0x0200     //Run offset cal. 
-#define     rx_start_offset_cal_clear                         0xFDFF     // Clear mask
-#define     rx_start_wt_bypass                                0x0100     //Run wiretest bypass. 
-#define     rx_start_wt_bypass_clear                          0xFEFF     // Clear mask
-
-// rx_training_status_pg Register field name                            data value   Description
-#define     rx_wiretest_done                                  0x8000     //When this bit is read as a 1, the wiretest training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     rx_wiretest_done_clear                            0x7FFF     // Clear mask
-#define     rx_deskew_done                                    0x4000     //When this bit is read as a 1, the deskew training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     rx_deskew_done_clear                              0xBFFF     // Clear mask
-#define     rx_eye_opt_done                                   0x2000     //When this bit is read as a 1, the eye optimization training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     rx_eye_opt_done_clear                             0xDFFF     // Clear mask
-#define     rx_repair_done                                    0x1000     //When this bit is read as a 1, the static lane repair training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     rx_repair_done_clear                              0xEFFF     // Clear mask
-#define     rx_func_mode_done                                 0x0800     //When this bit is read as a 1, the transition to functional data training state has completed. Check the corresponding rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     rx_func_mode_done_clear                           0xF7FF     // Clear mask
-#define     rx_bist_started                                   0x0400     //When this bit is read as a 1, the RX BIST initialization has finished and RX BIST has started running. 
-#define     rx_bist_started_clear                             0xFBFF     // Clear mask
-#define     rx_offset_cal_done                                0x0200     //When this bit is read as a 1, offset cal has completed. 
-#define     rx_offset_cal_done_clear                          0xFDFF     // Clear mask
-#define     rx_wt_bypass_done                                 0x0100     //When this bit is read as a 1, wiretest bypass has completed. 
-#define     rx_wt_bypass_done_clear                           0xFEFF     // Clear mask
-#define     rx_wiretest_failed                                0x0080     //When this bit is read as a 1, the wiretest training state encountered an error.
-#define     rx_wiretest_failed_clear                          0xFF7F     // Clear mask
-#define     rx_deskew_failed                                  0x0040     //When this bit is read as a 1, the deskew training state encountered an error.
-#define     rx_deskew_failed_clear                            0xFFBF     // Clear mask
-#define     rx_eye_opt_failed                                 0x0020     //When this bit is read as a 1, the eye optimization training state encountered an error.
-#define     rx_eye_opt_failed_clear                           0xFFDF     // Clear mask
-#define     rx_repair_failed                                  0x0010     //When this bit is read as a 1, the static lane repair training state encountered an error.
-#define     rx_repair_failed_clear                            0xFFEF     // Clear mask
-#define     rx_func_mode_failed                               0x0008     //When this bit is read as a 1, the transition to functional data training state encountered an error.
-#define     rx_func_mode_failed_clear                         0xFFF7     // Clear mask
-#define     rx_start_bist_failed                              0x0004     //When this bit is read as a 1, the RX BIST initialization has encountered and error. 
-#define     rx_start_bist_failed_clear                        0xFFFB     // Clear mask
-#define     rx_offset_cal_failed                              0x0002     //When this bit is read as a 1, offset cal has encountered an error. 
-#define     rx_offset_cal_failed_clear                        0xFFFD     // Clear mask
-#define     rx_wt_bypass_failed                               0x0001     //When this bit is read as a 1, wiretest bypass has encountered an error. 
-#define     rx_wt_bypass_failed_clear                         0xFFFE     // Clear mask
-
-// rx_recal_status_pg Register field name                               data value   Description
-#define     rx_recal_status                                   0x0000     //RX Recalibration Status
-#define     rx_recal_status_clear                             0x0000     // Clear mask
-
-// rx_timeout_sel_pg Register field name                                data value   Description
-#define     rx_sls_timeout_sel_tap1                           0x2000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  54.6us 
-#define     rx_sls_timeout_sel_tap2                           0x4000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  109.2us 
-#define     rx_sls_timeout_sel_tap3                           0x6000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  218.4us 
-#define     rx_sls_timeout_sel_tap4                           0x8000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  436.7us 
-#define     rx_sls_timeout_sel_tap5                           0xA000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  873.5us 
-#define     rx_sls_timeout_sel_tap6                           0xC000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  28.0ms 
-#define     rx_sls_timeout_sel_tap7                           0xE000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  infinite
-#define     rx_sls_timeout_sel_clear                          0x1FFF     // Clear mask
-#define     rx_ds_bl_timeout_sel_tap1                         0x0400     //Selects Deskew Block Lock Timeout value.   128k UI or 13.6us 
-#define     rx_ds_bl_timeout_sel_tap2                         0x0800     //Selects Deskew Block Lock Timeout value.   256k UI or 27.3us 
-#define     rx_ds_bl_timeout_sel_tap3                         0x0C00     //Selects Deskew Block Lock Timeout value.   1M UI or 109.2us 
-#define     rx_ds_bl_timeout_sel_tap4                         0x1000     //Selects Deskew Block Lock Timeout value.   2M UI or 218.5us 
-#define     rx_ds_bl_timeout_sel_tap5                         0x1400     //Selects Deskew Block Lock Timeout value.   4M UI or 436.9us 
-#define     rx_ds_bl_timeout_sel_tap6                         0x1800     //Selects Deskew Block Lock Timeout value.   8M UI or 873.8us 
-#define     rx_ds_bl_timeout_sel_tap7                         0x1C00     //Selects Deskew Block Lock Timeout value.   infinite
-#define     rx_ds_bl_timeout_sel_clear                        0xE3FF     // Clear mask
-#define     rx_cl_timeout_sel_tap1                            0x0080     //Selects Clock Lock Timeout value.   128k UI or 13.6us 
-#define     rx_cl_timeout_sel_tap2                            0x0100     //Selects Clock Lock Timeout value.   256k UI or 27.3us 
-#define     rx_cl_timeout_sel_tap3                            0x0180     //Selects Clock Lock Timeout value.   1M UI or 109.2us 
-#define     rx_cl_timeout_sel_tap4                            0x0200     //Selects Clock Lock Timeout value.   2M UI or 218.5us 
-#define     rx_cl_timeout_sel_tap5                            0x0280     //Selects Clock Lock Timeout value.   4M UI or 436.9us 
-#define     rx_cl_timeout_sel_tap6                            0x0300     //Selects Clock Lock Timeout value.   8M UI or 873.8us 
-#define     rx_cl_timeout_sel_tap7                            0x0380     //Selects Clock Lock Timeout value.   infinite
-#define     rx_cl_timeout_sel_clear                           0xFC7F     // Clear mask
-#define     rx_wt_timeout_sel_tap1                            0x0010     //Selects Wiretest Timeout value.   128k UI or 13.6us 
-#define     rx_wt_timeout_sel_tap2                            0x0020     //Selects Wiretest Timeout value.   256k UI or 27.3us 
-#define     rx_wt_timeout_sel_tap3                            0x0030     //Selects Wiretest Timeout value.   1M UI or 109.2us 
-#define     rx_wt_timeout_sel_tap4                            0x0040     //Selects Wiretest Timeout value.   2M UI or 218.5us 
-#define     rx_wt_timeout_sel_tap5                            0x0050     //Selects Wiretest Timeout value.   4M UI or 436.9us 
-#define     rx_wt_timeout_sel_tap6                            0x0060     //Selects Wiretest Timeout value.   8M UI or 873.8us 
-#define     rx_wt_timeout_sel_tap7                            0x0070     //Selects Wiretest Timeout value.   infinite
-#define     rx_wt_timeout_sel_clear                           0xC78F     // Clear mask
-#define     rx_ds_timeout_sel_tap1                            0x0002     //Selects Deskew  Timeout value.   128k UI or 13.6us 
-#define     rx_ds_timeout_sel_tap2                            0x0004     //Selects Deskew  Timeout value.   256k UI or 27.3us 
-#define     rx_ds_timeout_sel_tap3                            0x0006     //Selects Deskew  Timeout value.   1M UI or 109.2us 
-#define     rx_ds_timeout_sel_tap4                            0x0008     //Selects Deskew  Timeout value.   2M UI or 218.5us 
-#define     rx_ds_timeout_sel_tap5                            0x000A     //Selects Deskew  Timeout value.   4M UI or 436.9us 
-#define     rx_ds_timeout_sel_tap6                            0x000C     //Selects Deskew  Timeout value.   8M UI or 873.8us 
-#define     rx_ds_timeout_sel_tap7                            0x000E     //Selects Deskew  Timeout value.   infinite
-#define     rx_ds_timeout_sel_clear                           0xFF11     // Clear mask
-
-// rx_fifo_mode_pg Register field name                                  data value   Description
-#define     rx_fifo_initial_l2u_dly                           0x0000     //RX FIFO Initial Load to Unload Delay. For setting X, the latency is 4*X to 4*X+4 UI.  Default is 16-20 UI.
-#define     rx_fifo_initial_l2u_dly_clear                     0x0FFF     // Clear mask
-#define     rx_fifo_final_l2u_dly                             0x0000     //RX FIFO Final Load to Unload Delay. For setting X, the latency is 4*X to 4*X+4 UI.  Default is 8-12 UI.
-#define     rx_fifo_final_l2u_dly_clear                       0xF0FF     // Clear mask
-#define     rx_fifo_max_deskew                                0x0000     //RX FIFO Max Deskew Control Value. TBD
-#define     rx_fifo_max_deskew_clear                          0xFF0F     // Clear mask
-#define     rx_fifo_final_l2u_min_err_thresh_tap1             0x0004     //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel.   16 errors 
-#define     rx_fifo_final_l2u_min_err_thresh_tap2             0x0008     //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel.   128 errors 
-#define     rx_fifo_final_l2u_min_err_thresh_tap3             0x000C     //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by rx_eo_final_l2u_timeout_sel.   255 errors
-#define     rx_fifo_final_l2u_min_err_thresh_clear            0xFF33     // Clear mask
-
-// rx_sls_status_pg Register field name                                 data value   Description
-#define     rx_sls_cmd_val                                    0x8000     //Current SLS Command Valid
-#define     rx_sls_cmd_val_clear                              0x7FFF     // Clear mask
-#define     rx_sls_cmd_encode_shadow_request                  0x0100     //Current SLS Command  Driven by the RX side to request shadowing of its receive lane from lane n-1 to lane n
-#define     rx_sls_cmd_encode_shadow_done                     0x0200     //Current SLS Command  Driven by the RX side to signal now receiving lane n-1s data on lane n
-#define     rx_sls_cmd_encode_shadow_repair_request           0x0300     //Current SLS Command  Driven by the RX side to request shadowing and repair of its receive lane from lane n-1 to n.
-#define     rx_sls_cmd_encode_shadow_repair_done              0x0400     //Current SLS Command  Driven by the RX side to signal lane n-1 is repaired.
-#define     rx_sls_cmd_encode_unshadow_request                0x0500     //Current SLS Command  Driven by the RX side to request shadowing of receive lane from lane n+1 to lane n.
-#define     rx_sls_cmd_encode_unshadow_done                   0x0600     //Current SLS Command  Driven by the RX side to signal now receiving lane n+1 data on lane n
-#define     rx_sls_cmd_encode_unshadow_repair_request         0x0700     //Current SLS Command  Driven by the RX side to request unshadowing and repair of its receive lane from lane n+1 to lane n.
-#define     rx_sls_cmd_encode_unshadow_repair_done            0x0800     //Current SLS Command  Driven by the RX side to signal lane n+1 is repaired.
-#define     rx_sls_cmd_encode_sls_exception                   0x0900     //Current SLS Command  Driven by the RX side to indicate to the other side of the bus its RX SLS lane is broken.
-#define     rx_sls_cmd_encode_init_done                       0x0A00     //Current SLS Command  Driven to signal the CTLE/DFE/offset (re-
-#define     rx_sls_cmd_encode_recal_request                   0x0B00     //Current SLS Command  Driven on recalibration lane x to request a recalibration of its receive recalibration lane y.
-#define     rx_sls_cmd_encode_recal_running                   0x0C00     //Current SLS Command  Driven during the status reporting interval of recalibration to indicate recalibration has not completed
-#define     rx_sls_cmd_encode_recal_done                      0x0D00     //Current SLS Command  Driven to indicate its recalibration is complete.
-#define     rx_sls_cmd_encode_recal_failed                    0x0E00     //Current SLS Command  Driven to indicate recalibration has failed on its receive recalibration lane
-#define     rx_sls_cmd_encode_recal_abort                     0x0F00     //Current SLS Command  Abort recalibration.
-#define     rx_sls_cmd_encode_reserved2                       0x1000     //Current SLS Command  Reserved.010001
-#define     rx_sls_cmd_encode_reserved4                       0x1200     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved5                       0x1300     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved6                       0x1400     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved7                       0x1500     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved8                       0x1600     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved9                       0x1700     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved10                      0x1800     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_init_ack_done                   0x1900     //Current SLS Command  Driven in response to an init_done (not currently used
-#define     rx_sls_cmd_encode_reserved11                      0x1A00     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_recal_ack                       0x1B00     //Current SLS Command  Driven on recalibration lane y in response to a recal_request on its receive recalibration lane x
-#define     rx_sls_cmd_encode_reserved12                      0x1C00     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved13                      0x1D00     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_reserved14                      0x1E00     //Current SLS Command  Reserved.
-#define     rx_sls_cmd_encode_recal_abort_ack                 0x1F00     //Current SLS Command  Abort recalibration acknowledge.
-#define     rx_sls_cmd_encode_clear                           0xC0FF     // Clear mask
-#define     rx_sls_err_chk_cnt                                0x0000     //Error count result for SLS error checking mode
-#define     rx_sls_err_chk_cnt_clear                          0xFF00     // Clear mask
-
-// rx_fir1_pg Register field name                                       data value   Description
-#define     rx_pg_fir1_errs_par_err_rx_rpr_state              0x0800     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     rx_pg_fir1_errs_par_err_rx_eyeopt_state           0x0C00     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     rx_pg_fir1_errs_par_err_dsm_state                 0x0400     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     rx_pg_fir1_errs_par_err_rxdsm_state               0x0400     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     rx_pg_fir1_errs_clear                             0x0003     // Clear mask
-#define     rx_pl_fir_err                                     0x0001     //Summary bit indicating an RX per-lane register or state machine parity error has occurred in one or more lanes. The rx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane.
-#define     rx_pl_fir_err_clear                               0xFFFE     // Clear mask
-
-// rx_fir2_pg Register field name                                       data value   Description
-#define     rx_pg_fir2_errs_err_sls_hndshk_sm                 0x0200     //A Per-Group Register or State Machine Parity Error has occurred.  RXCTL SLS Handshake SM Parity Error.
-#define     rx_pg_fir2_errs_clear                             0x01FF     // Clear mask
-
-// rx_fir1_mask_pg Register field name                                  data value   Description
-#define     rx_pg_fir1_errs_mask_clear                        0x0003     // Clear mask
-#define     rx_pl_fir_err_mask                                0x0001     //FIR mask for the summary bit that indicates an RX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane parity errors from causing a FIR error.
-#define     rx_pl_fir_err_mask_clear                          0xFFFE     // Clear mask
-
-// rx_fir2_mask_pg Register field name                                  data value   Description
-#define     rx_pg_fir2_errs_mask_mask_sls_hndshk_sm           0x0200     //FIR mask for register or state machine parity checkers in per-group RX logic. A value of 1 masks the error from generating a FIR error.  RXCTL SLS Handshake SM Parity Error Mask.
-#define     rx_pg_fir2_errs_mask_clear                        0x01FF     // Clear mask
-
-// rx_fir1_error_inject_pg Register field name                          data value   Description
-#define     rx_pg_fir1_err_inj_1                              0x4000     //RX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     rx_pg_fir1_err_inj_inj_rpr_sm                     0x0800     //RX Per-Group Parity Error Injection  RXCTL Repair SM Parity Error Inject.
-#define     rx_pg_fir1_err_inj_inj_eyeopt_sm                  0x0C00     //RX Per-Group Parity Error Injection  RXCTL Eyeopt SM Parity Error Inject.
-#define     rx_pg_fir1_err_inj_inj_dsm_sm                     0x0400     //RX Per-Group Parity Error Injection  RXCTL Deskew SM Parity Error Inject.
-#define     rx_pg_fir1_err_inj_inj_rxdsm_sm                   0x0400     //RX Per-Group Parity Error Injection  RXCTL RX Deskew SM Parity Error Inject.
-#define     rx_pg_fir1_err_inj_clear                          0x0003     // Clear mask
-
-// rx_fir2_error_inject_pg Register field name                          data value   Description
-#define     rx_pg_fir2_err_inj_1                              0x2000     //RX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     rx_pg_fir2_err_inj_inj_sls_hndshk_sm              0x0200     //RX Per-Group Parity Error Injection  RXCTL SLS Handshake SM Parity Error Inject.
-#define     rx_pg_fir2_err_inj_clear                          0x01FF     // Clear mask
-
-// rx_fir_training_pg Register field name                               data value   Description
-#define     rx_pg_fir_training_error                          0x8000     //This field is now defunct and is permanently masked in the rx_fir_training_mask_pg FIR isolation register.
-#define     rx_pg_fir_training_error_clear                    0x7FFF     // Clear mask
-#define     rx_pg_fir_static_spare_deployed                   0x4000     //A spare lane has been deployed during training to heal a lane that was detected as bad. rx_Static_Spare_Deployed (SSD) will be set after the repair training step if during training either wiretest, deskew, eyeopt or repair has detected one or more bad lanes have been detected. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed and the rx_bad_lane.
-#define     rx_pg_fir_static_spare_deployed_clear             0xBFFF     // Clear mask
-#define     rx_pg_fir_static_max_spares_exceeded              0x2000     //A lane has been detected as bad during training but there are no spare lanes available to heal it. THIS FIR WILL NOT BE SET UNTIL THE REPAIR TRAINING STEP HAS BEEN RUN. THIS IS A CATASTROPHIC FAILURE FOR THE BUS WHEN IN MISSION MODE BUT ALL TRAINING STEPS WILL STILL BE RUN ON WHATEVER GOOD LANES THERE ARE. rx_static_max_spares_exceeded will be set if wiretest, deskew, eyeopt or repair find the excessive number of bad lanes.
-#define     rx_pg_fir_static_max_spares_exceeded_clear        0xDFFF     // Clear mask
-#define     rx_pg_fir_dynamic_repair_error                    0x1000     //A Dynamic Repair error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic.
-#define     rx_pg_fir_dynamic_repair_error_clear              0xEFFF     // Clear mask
-#define     rx_pg_fir_dynamic_spare_deployed                  0x0800     //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed.
-#define     rx_pg_fir_dynamic_spare_deployed_clear            0xF7FF     // Clear mask
-#define     rx_pg_fir_dynamic_max_spares_exceeded             0x0400     //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS.
-#define     rx_pg_fir_dynamic_max_spares_exceeded_clear       0xFBFF     // Clear mask
-#define     rx_pg_fir_recal_error                             0x0200     //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic.
-#define     rx_pg_fir_recal_error_clear                       0xFDFF     // Clear mask
-#define     rx_pg_fir_recal_spare_deployed                    0x0100     //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed.
-#define     rx_pg_fir_recal_spare_deployed_clear              0xFEFF     // Clear mask
-#define     rx_pg_fir_recal_max_spares_exceeded               0x0080     //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS.
-#define     rx_pg_fir_recal_max_spares_exceeded_clear         0xFF7F     // Clear mask
-#define     rx_pg_fir_too_many_bus_errors                     0x0040     //More than one lane has been detected as having too many errors during functional operation. THIS IS A CATASTROPHIC FAILURE FOR THE BUS.
-#define     rx_pg_fir_too_many_bus_errors_clear               0xFFBF     // Clear mask
-
-// rx_fir_training_mask_pg Register field name                          data value   Description
-#define     rx_pg_fir_training_error_mask                     0x8000     //FIR mask for rx_pg_fir_training_error.
-#define     rx_pg_fir_training_error_mask_clear               0x7FFF     // Clear mask
-#define     rx_pg_fir_static_spare_deployed_mask              0x4000     //FIR mask for rx_pg_fir_static_spare_deployed.
-#define     rx_pg_fir_static_spare_deployed_mask_clear        0xBFFF     // Clear mask
-#define     rx_pg_fir_static_max_spares_exceeded_mask         0x2000     //FIR mask for rx_pg_fir_static_max_spares_exceeded
-#define     rx_pg_fir_static_max_spares_exceeded_mask_clear   0xDFFF     // Clear mask
-#define     rx_pg_fir_dynamic_repair_error_mask               0x1000     //FIR mask for rx_pg_fir_dynamic_repair_error
-#define     rx_pg_fir_dynamic_repair_error_mask_clear         0xEFFF     // Clear mask
-#define     rx_pg_fir_dynamic_spare_deployed_mask             0x0800     //FIR mask for rx_pg_fir_dynamic_spare_deployed.
-#define     rx_pg_fir_dynamic_spare_deployed_mask_clear       0xF7FF     // Clear mask
-#define     rx_pg_fir_dynamic_max_spares_exceeded_mask        0x0400     //FIR mask for rx_pg_fir_dynamic_max_spares_exceeded.
-#define     rx_pg_fir_dynamic_max_spares_exceeded_mask_clear  0xFBFF     // Clear mask
-#define     rx_pg_fir_recal_error_mask                        0x0200     //FIR mask for rx_pg_fir_recal_error.
-#define     rx_pg_fir_recal_error_mask_clear                  0xFDFF     // Clear mask
-#define     rx_pg_fir_recal_spare_deployed_mask               0x0100     //FIR mask for rx_pg_fir_recal_spare_deployed.
-#define     rx_pg_fir_recal_spare_deployed_mask_clear         0xFEFF     // Clear mask
-#define     rx_pg_fir_recal_max_spares_exceeded_mask          0x0080     //FIR mask for rx_pg_fir_recal_max_spares_exceeded.
-#define     rx_pg_fir_recal_max_spares_exceeded_mask_clear    0xFF7F     // Clear mask
-#define     rx_pg_fir_too_many_bus_errors_mask                0x0040     //FIR mask for rx_pg_fir_too_many_bus_errors.
-#define     rx_pg_fir_too_many_bus_errors_mask_clear          0xFFBF     // Clear mask
-
-// rx_timeout_sel1_pg Register field name                               data value   Description
-#define     rx_eo_offset_timeout_sel_tap1                     0x2000     //Selects Latch offset timeout.   128k UI or 13.6us 
-#define     rx_eo_offset_timeout_sel_tap2                     0x4000     //Selects Latch offset timeout.   256k UI or 27.3us 
-#define     rx_eo_offset_timeout_sel_tap3                     0x6000     //Selects Latch offset timeout.   1M UI or 109.2us 
-#define     rx_eo_offset_timeout_sel_tap4                     0x8000     //Selects Latch offset timeout.   2M UI or 218.5us 
-#define     rx_eo_offset_timeout_sel_tap5                     0xA000     //Selects Latch offset timeout.   4M UI or 436.9us 
-#define     rx_eo_offset_timeout_sel_tap6                     0xC000     //Selects Latch offset timeout.   8M UI or 873.8us 
-#define     rx_eo_offset_timeout_sel_tap7                     0xE000     //Selects Latch offset timeout.   infinite
-#define     rx_eo_offset_timeout_sel_clear                    0x1FFF     // Clear mask
-#define     rx_eo_amp_timeout_sel_tap1                        0x0400     //Selects  Amplitude measurement watchdog timeout.   128k UI or 13.6us 
-#define     rx_eo_amp_timeout_sel_tap2                        0x0800     //Selects  Amplitude measurement watchdog timeout.   256k UI or 27.3us 
-#define     rx_eo_amp_timeout_sel_tap3                        0x0C00     //Selects  Amplitude measurement watchdog timeout.   1M UI or 109.2us 
-#define     rx_eo_amp_timeout_sel_tap4                        0x1000     //Selects  Amplitude measurement watchdog timeout.   2M UI or 218.5us 
-#define     rx_eo_amp_timeout_sel_tap5                        0x1400     //Selects  Amplitude measurement watchdog timeout.   4M UI or 436.9us 
-#define     rx_eo_amp_timeout_sel_tap6                        0x1800     //Selects  Amplitude measurement watchdog timeout.   8M UI or 873.8us 
-#define     rx_eo_amp_timeout_sel_tap7                        0x1C00     //Selects  Amplitude measurement watchdog timeout.   infinite
-#define     rx_eo_amp_timeout_sel_clear                       0xE3FF     // Clear mask
-#define     rx_eo_ctle_timeout_sel_tap1                       0x0080     //Selects  CTLE ajdust watchdog timeout.   128k UI or 13.6us 
-#define     rx_eo_ctle_timeout_sel_tap2                       0x0100     //Selects  CTLE ajdust watchdog timeout.   256k UI or 27.3us 
-#define     rx_eo_ctle_timeout_sel_tap3                       0x0180     //Selects  CTLE ajdust watchdog timeout.   1M UI or 109.2us 
-#define     rx_eo_ctle_timeout_sel_tap4                       0x0200     //Selects  CTLE ajdust watchdog timeout.   2M UI or 218.5us 
-#define     rx_eo_ctle_timeout_sel_tap5                       0x0280     //Selects  CTLE ajdust watchdog timeout.   4M UI or 436.9us 
-#define     rx_eo_ctle_timeout_sel_tap6                       0x0300     //Selects  CTLE ajdust watchdog timeout.   8M UI or 873.8us 
-#define     rx_eo_ctle_timeout_sel_tap7                       0x0380     //Selects  CTLE ajdust watchdog timeout.   infinite
-#define     rx_eo_ctle_timeout_sel_clear                      0xFC7F     // Clear mask
-#define     rx_eo_h1ap_timeout_sel_tap1                       0x0010     //Selects  H1Ap ajdust watchdog timeout.   128k UI or 13.6us 
-#define     rx_eo_h1ap_timeout_sel_tap2                       0x0020     //Selects  H1Ap ajdust watchdog timeout.   256k UI or 27.3us 
-#define     rx_eo_h1ap_timeout_sel_tap3                       0x0030     //Selects  H1Ap ajdust watchdog timeout.   1M UI or 109.2us 
-#define     rx_eo_h1ap_timeout_sel_tap4                       0x0040     //Selects  H1Ap ajdust watchdog timeout.   2M UI or 218.5us 
-#define     rx_eo_h1ap_timeout_sel_tap5                       0x0050     //Selects  H1Ap ajdust watchdog timeout.   4M UI or 436.9us 
-#define     rx_eo_h1ap_timeout_sel_tap6                       0x0060     //Selects  H1Ap ajdust watchdog timeout.   8M UI or 873.8us 
-#define     rx_eo_h1ap_timeout_sel_tap7                       0x0070     //Selects  H1Ap ajdust watchdog timeout.   infinite
-#define     rx_eo_h1ap_timeout_sel_clear                      0xC78F     // Clear mask
-#define     rx_eo_ddc_timeout_sel_tap1                        0x0002     //Selects  DDC watchdog timeout (EDI ONLY).   128k UI or 13.6us 
-#define     rx_eo_ddc_timeout_sel_tap2                        0x0004     //Selects  DDC watchdog timeout (EDI ONLY).   256k UI or 27.3us 
-#define     rx_eo_ddc_timeout_sel_tap3                        0x0006     //Selects  DDC watchdog timeout (EDI ONLY).   1M UI or 109.2us 
-#define     rx_eo_ddc_timeout_sel_tap4                        0x0008     //Selects  DDC watchdog timeout (EDI ONLY).   2M UI or 218.5us 
-#define     rx_eo_ddc_timeout_sel_tap5                        0x000A     //Selects  DDC watchdog timeout (EDI ONLY).   4M UI or 436.9us 
-#define     rx_eo_ddc_timeout_sel_tap6                        0x000C     //Selects  DDC watchdog timeout (EDI ONLY).   8M UI or 873.8us 
-#define     rx_eo_ddc_timeout_sel_tap7                        0x000E     //Selects  DDC watchdog timeout (EDI ONLY).   infinite
-#define     rx_eo_ddc_timeout_sel_clear                       0xFF11     // Clear mask
-#define     rx_eo_final_l2u_timeout_sel                       0x0001     //Selects Final Load to Unload Delay qualification time per step. 
-#define     rx_eo_final_l2u_timeout_sel_clear                 0xFFFE     // Clear mask
-
-// rx_lane_bad_vec_0_15_pg Register field name                          data value   Description
-#define     rx_lane_bad_vec_0_15_clear                        0x0000     // Clear mask
-
-// rx_lane_bad_vec_16_31_pg Register field name                         data value   Description
-#define     rx_lane_bad_vec_16_31                             0x0000     //Lanes found bad by HW (status) or method to force lane bad from software (control).
-#define     rx_lane_bad_vec_16_31_clear                       0x0000     // Clear mask
-
-// rx_lane_disabled_vec_0_15_pg Register field name                     data value   Description
-#define     rx_lane_disabled_vec_0_15                         0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     rx_lane_disabled_vec_0_15_clear                   0x0000     // Clear mask
-
-// rx_lane_disabled_vec_16_31_pg Register field name                    data value   Description
-#define     rx_lane_disabled_vec_16_31                        0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     rx_lane_disabled_vec_16_31_clear                  0x0000     // Clear mask
-
-// rx_lane_swapped_vec_0_15_pg Register field name                      data value   Description
-#define     rx_lane_swapped_vec_0_15                          0x0000     //Wiretest found that the P & N wire legs have been swapped on the lane indicated. Has the effect of basically inverting the signal.  Note that this status is invalid if the lane is marked bad.
-#define     rx_lane_swapped_vec_0_15_clear                    0x0000     // Clear mask
-
-// rx_lane_swapped_vec_16_31_pg Register field name                     data value   Description
-#define     rx_lane_swapped_vec_16_31                         0x0000     //Wiretest found that the P & N wire legs have been swapped on the lane indicated. Has the effect of basically inverting the signal.  Note that this status is invalid if the lane is marked bad.
-#define     rx_lane_swapped_vec_16_31_clear                   0x0000     // Clear mask
-
-// rx_init_state_pg Register field name                                 data value   Description
-#define     rx_main_init_state_1                              0x1000     //Main Initialization State Machine(RJR):  Wiretest Running
-#define     rx_main_init_state_2                              0x2000     //Main Initialization State Machine(RJR):  Deskew Running
-#define     rx_main_init_state_3                              0x3000     //Main Initialization State Machine(RJR):  Eye Optimization Running
-#define     rx_main_init_state_4                              0x4000     //Main Initialization State Machine(RJR):  Repair Running
-#define     rx_main_init_state_5                              0x5000     //Main Initialization State Machine(RJR):  Go Functional Running
-#define     rx_main_init_state_6                              0x9000     //Main Initialization State Machine(RJR):  Wiretest Failed
-#define     rx_main_init_state_7                              0x5000     //Main Initialization State Machine(RJR):  Deskew Failed
-#define     rx_main_init_state_8                              0xB000     //Main Initialization State Machine(RJR):  Eye Optimization Failed
-#define     rx_main_init_state_9                              0xC000     //Main Initialization State Machine(RJR):  Repair Failed
-#define     rx_main_init_state_10                             0xD000     //Main Initialization State Machine(RJR):  Go Functional Failed
-#define     rx_main_init_state_clear                          0x0FFF     // Clear mask
-
-// rx_wiretest_state_pg Register field name                             data value   Description
-#define     rx_wtm_state_clear                                0x07FF     // Clear mask
-#define     rx_wtr_state_clear                                0xF87F     // Clear mask
-#define     rx_wtl_state_clear                                0x0FE0     // Clear mask
-
-// rx_wiretest_laneinfo_pg Register field name                          data value   Description
-#define     rx_wtr_cur_lane                                   0x0000     //Wiretest Current Lane Under Test(RJR)
-#define     rx_wtr_cur_lane_clear                             0x07FF     // Clear mask
-#define     rx_wtr_max_bad_lanes_clear                        0xF83F     // Clear mask
-#define     rx_wtr_bad_lane_count                             0x0000     //Wiretest Current Number Of Bad Lanes in This Clk Group(RJR)
-#define     rx_wtr_bad_lane_count_clear                       0x07E0     // Clear mask
-
-// rx_wiretest_gcrmsgs_pg Register field name                           data value   Description
-#define     rx_wt_prev_done_gcrmsg                            0x8000     //GCR Message: Previous Clk Group Has Completed Wiretest
-#define     rx_wt_prev_done_gcrmsg_clear                      0x7FFF     // Clear mask
-#define     rx_wt_all_done_gcrmsg                             0x4000     //GCR Message: All Clk Groups Have Completed Wiretest
-#define     rx_wt_all_done_gcrmsg_clear                       0xBFFF     // Clear mask
-
-// rx_deskew_gcrmsgs_pg Register field name                             data value   Description
-#define     rx_deskew_seq_gcrmsg_dsalldeskewed                0x2000     //GCR Message: RX Deskew Sequencer GCR messages  Indicate all groups deskewed.
-#define     rx_deskew_seq_gcrmsg_dsprevdone                   0x4000     //GCR Message: RX Deskew Sequencer GCR messages  Indicate prior group completed deskew.
-#define     rx_deskew_seq_gcrmsg_dsalldone                    0x6000     //GCR Message: RX Deskew Sequencer GCR messages  Indicate all groups completed deskew.
-#define     rx_deskew_seq_gcrmsg_dsprevskew                   0x8000     //GCR Message: RX Deskew Sequencer GCR messages  Transmit skew values from prior group.
-#define     rx_deskew_seq_gcrmsg_dsmaxskew                    0xA000     //GCR Message: RX Deskew Sequencer GCR messages  Transmit max skew values to all groups.
-#define     rx_deskew_seq_gcrmsg_unused                       0xC000     //GCR Message: RX Deskew Sequencer GCR messages  Unused.
-#define     rx_deskew_seq_gcrmsg_dsnomsg                      0xE000     //GCR Message: RX Deskew Sequencer GCR messages  No message.
-#define     rx_deskew_seq_gcrmsg_clear                        0x1FFF     // Clear mask
-#define     rx_deskew_skmin_gcrmsg                            0x0000     //GCR Message: Min Skew Value for deskew sequence.
-#define     rx_deskew_skmin_gcrmsg_clear                      0xF03F     // Clear mask
-#define     rx_deskew_skmax_gcrmsg                            0x0000     //GCR Message: Max Skew Value for deskew sequence.
-#define     rx_deskew_skmax_gcrmsg_clear                      0x0FC0     // Clear mask
-
-// rx_deskew_state_pg Register field name                               data value   Description
-#define     rx_dsm_state_clear                                0x00FF     // Clear mask
-#define     rx_rxdsm_state_clear                              0x7F80     // Clear mask
-
-// rx_deskew_mode_pg Register field name                                data value   Description
-#define     rx_deskew_max_limit                               0x0000     //Maximum Deskewable Skew Fail Threshold
-#define     rx_deskew_max_limit_clear                         0x03FF     // Clear mask
-
-// rx_deskew_status_pg Register field name                              data value   Description
-#define     rx_deskew_minskew_grp                             0x0000     //Deskew Per-Group Raw Skew Min
-#define     rx_deskew_minskew_grp_clear                       0x03FF     // Clear mask
-#define     rx_deskew_maxskew_grp                             0x0000     //Deskew Per-Group Raw Skew Max
-#define     rx_deskew_maxskew_grp_clear                       0xFC0F     // Clear mask
-
-// rx_bad_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     rx_bad_lane1_gcrmsg                               0x0000     //GCR Message: Encoded bad lane one in relation to the entire RX bus
-#define     rx_bad_lane1_gcrmsg_clear                         0x01FF     // Clear mask
-#define     rx_bad_lane2_gcrmsg                               0x0000     //GCR Message: Encoded bad lane two in relation to the entire RX bus
-#define     rx_bad_lane2_gcrmsg_clear                         0xFE03     // Clear mask
-#define     rx_bad_lane_code_gcrmsg_bad_ln1_val               0x0001     //GCR Message: RX Bad Lane Code  Bad Lane 1 Valid
-#define     rx_bad_lane_code_gcrmsg_bad_lns12_val             0x0002     //GCR Message: RX Bad Lane Code  Bad Lanes 1 and 2 Valid
-#define     rx_bad_lane_code_gcrmsg_3plus_bad_lns             0x0003     //GCR Message: RX Bad Lane Code  3+ bad lanes
-#define     rx_bad_lane_code_gcrmsg_clear                     0xFFF0     // Clear mask
-
-// rx_static_repair_state_pg Register field name                        data value   Description
-#define     rx_rpr_state_clear                                0x03FF     // Clear mask
-
-// rx_tx_bus_info_pg Register field name                                data value   Description
-#define     rx_tx_bus_width                                   0x0000     //TX Bus Width
-#define     rx_tx_bus_width_clear                             0x01FF     // Clear mask
-#define     rx_rx_bus_width                                   0x0000     //RX Bus Width
-#define     rx_rx_bus_width_clear                             0xFE03     // Clear mask
-
-// rx_sls_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     rx_sls_lane_gcrmsg                                0x0000     //GCR Message: Encoded SLS lane in relation to the entire RX bus
-#define     rx_sls_lane_gcrmsg_clear                          0x01FF     // Clear mask
-#define     rx_sls_lane_val_gcrmsg                            0x0100     //GCR Message: RX SLS Lane Valid
-#define     rx_sls_lane_val_gcrmsg_clear                      0xFEFF     // Clear mask
-
-// rx_fence_pg Register field name                                      data value   Description
-#define     rx_fence                                          0x8000     //RX fence bit
-#define     rx_fence_clear                                    0x7FFF     // Clear mask
-
-// rx_timeout_sel2_pg Register field name                               data value   Description
-#define     rx_func_mode_timeout_sel_tap1                     0x2000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   128k UI or 13.7us 
-#define     rx_func_mode_timeout_sel_tap2                     0x4000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   256k UI or 27.3us 
-#define     rx_func_mode_timeout_sel_tap3                     0x6000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   512k UI or 54.6us 
-#define     rx_func_mode_timeout_sel_tap4                     0x8000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   1M UI or 109.2us 
-#define     rx_func_mode_timeout_sel_tap5                     0xA000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   2M UI or 218.5us 
-#define     rx_func_mode_timeout_sel_tap6                     0xC000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   64M UI or 7ms
-#define     rx_func_mode_timeout_sel_tap7                     0xE000     //Selects Functional Mode wait timeout. Note that his should be longer than rx_sls_timeout_sel.   infinite
-#define     rx_func_mode_timeout_sel_clear                    0x1FFF     // Clear mask
-#define     rx_rc_slowdown_timeout_sel_tap1                   0x0400     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   128k UI or 13.7us 
-#define     rx_rc_slowdown_timeout_sel_tap2                   0x0800     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   256k UI or 27.3us 
-#define     rx_rc_slowdown_timeout_sel_tap3                   0x0C00     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   512k UI or 54.6us 
-#define     rx_rc_slowdown_timeout_sel_tap4                   0x1000     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   1M UI or 109.2us 
-#define     rx_rc_slowdown_timeout_sel_tap5                   0x1400     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   2M UI or 218.5us 
-#define     rx_rc_slowdown_timeout_sel_tap6                   0x1800     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   64M UI or 7ms
-#define     rx_rc_slowdown_timeout_sel_tap7                   0x1C00     //Selects Recal  Slowdown      timeout. Note that his should be longer than rx_sls_timeout_sel.   infinite
-#define     rx_rc_slowdown_timeout_sel_clear                  0xE3FF     // Clear mask
-#define     rx_pup_lite_wait_sel_tap1                         0x0100     //How long to wait for analog logic to power up an unused spare lane for recal/repair  107ns (default value
-#define     rx_pup_lite_wait_sel_tap2                         0x0200     //How long to wait for analog logic to power up an unused spare lane for recal/repair  213ns
-#define     rx_pup_lite_wait_sel_tap3                         0x0300     //How long to wait for analog logic to power up an unused spare lane for recal/repair  427ns
-#define     rx_pup_lite_wait_sel_clear                        0xFCFF     // Clear mask
-
-// rx_misc_analog_pg Register field name                                data value   Description
-#define     rx_c4_sel                                         0x0000     //Select 1 of 4 possible phases for the C4 clock to send along with the data for integration flexibility and tuning for slack into the Rx FIFO.
-#define     rx_c4_sel_clear                                   0x3FFF     // Clear mask
-#define     rx_negz_en                                        0x2000     //Turns on a gyrator stage in the CTLE pushing up the high freq corner
-#define     rx_negz_en_clear                                  0xDFFF     // Clear mask
-#define     rx_prot_speed_slct                                0x1000     //TBD (Enable the flux capacitor?)
-#define     rx_prot_speed_slct_clear                          0xEFFF     // Clear mask
-#define     rx_iref_bc                                        0x0000     //Bias Code for the Iref macros on the RX side. All eight 3 bit codes enable current out. The cml voltage swings of the output current will vary with this code.
-#define     rx_iref_bc_clear                                  0xF1FF     // Clear mask
-
-// rx_dyn_rpr_pg Register field name                                    data value   Description
-#define     rx_dyn_rpr_state_clear                            0xC0FF     // Clear mask
-#define     rx_sls_hndshk_state_clear                         0xFF00     // Clear mask
-
-// rx_dyn_rpr_gcrmsg_pg Register field name                             data value   Description
-#define     rx_dyn_rpr_req_gcrmsg                             0x8000     //GCR Message: CRC/ECC Tallying logic has a Dynamic Repair Request
-#define     rx_dyn_rpr_req_gcrmsg_clear                       0x7FFF     // Clear mask
-#define     rx_dyn_rpr_lane2rpr_gcrmsg                        0x0000     //GCR Message: CRC/ECC Tallying logic bad lane to repair
-#define     rx_dyn_rpr_lane2rpr_gcrmsg_clear                  0x80FF     // Clear mask
-#define     rx_dyn_rpr_ip_gcrmsg                              0x0080     //GCR Message: CRC/ECC Bad Lane Repair In Progress
-#define     rx_dyn_rpr_ip_gcrmsg_clear                        0xFF7F     // Clear mask
-#define     rx_dyn_rpr_complete_gcrmsg                        0x0040     //GCR Message: CRC/ECC Bad Lane Repaired
-#define     rx_dyn_rpr_complete_gcrmsg_clear                  0xFFBF     // Clear mask
-
-// rx_dyn_rpr_err_tallying1_pg Register field name                      data value   Description
-#define     rx_dyn_rpr_bad_lane_max                           0x0000     //CRC/ECC Dynamic Repair: Max number of times a lane can be found bad before repaired
-#define     rx_dyn_rpr_bad_lane_max_clear                     0x01FF     // Clear mask
-#define     rx_dyn_rpr_err_cntr1_duration_tap1                0x0020     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  853.0ns & 1.3uS
-#define     rx_dyn_rpr_err_cntr1_duration_tap2                0x0040     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  27.3uS & 41.0uS
-#define     rx_dyn_rpr_err_cntr1_duration_tap3                0x0060     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  873.5uS & 1.3mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap4                0x0080     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  1.7mS & 2.6mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap5                0x00A0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  3.5mS & 5.1mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap6                0x00C0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  7.0mS & 10.5mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap7                0x00E0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  14.0mS & 21.0mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap8                0x0100     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  28.0mS & 41.9mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap9                0x0120     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  55.9mS & 83.9mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap10               0x0140     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  111.8mS & 167.8mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap11               0x0160     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  223.6mS & 335.5mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap12               0x0180     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  447.2mS & 671.1mS
-#define     rx_dyn_rpr_err_cntr1_duration_tap13               0x01A0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  894.4mS & 1.3 S
-#define     rx_dyn_rpr_err_cntr1_duration_tap14               0x01C0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  1.8 S & 2.7 S
-#define     rx_dyn_rpr_err_cntr1_duration_tap15               0x01E0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  infinite
-#define     rx_dyn_rpr_err_cntr1_duration_clear               0x3E1F     // Clear mask
-#define     rx_dyn_rpr_clr_err_cntr1                          0x0010     //CRC/ECC Dynamic Repair: Firmware-based clear of lane error counter1 register
-#define     rx_dyn_rpr_clr_err_cntr1_clear                    0xFFEF     // Clear mask
-#define     rx_dyn_rpr_disable                                0x0008     //CRC/ECC Dynamic Repair: When set, disables dynamic repair error tallying (both per lane and per bus error counters...cntr1 & cntr2)
-#define     rx_dyn_rpr_disable_clear                          0xFFF7     // Clear mask
-#define     rx_dyn_rpr_enc_bad_data_lane_width                0x0000     //CRC/ECC Dynamic Repair: Width of the enc_bad_data_lane vector used to determine number of 1s in clear code
-#define     rx_dyn_rpr_enc_bad_data_lane_width_clear          0xFFB8     // Clear mask
-
-// rx_eo_final_l2u_gcrmsgs_pg Register field name                       data value   Description
-#define     rx_eo_final_l2u_dly_seq_gcrmsg_fl2uallchg         0x4000     //GCR Message: RX Final Load to Unload Delay GCR messages  Indicate all groups have calculated max load to unload change.
-#define     rx_eo_final_l2u_dly_seq_gcrmsg_unused             0x8000     //GCR Message: RX Final Load to Unload Delay GCR messages  Unused.
-#define     rx_eo_final_l2u_dly_seq_gcrmsg_fl2unomsg          0xC000     //GCR Message: RX Final Load to Unload Delay GCR messages  No message.
-#define     rx_eo_final_l2u_dly_seq_gcrmsg_clear              0x3FFF     // Clear mask
-#define     rx_eo_final_l2u_dly_maxchg_gcrmsg                 0x0000     //GCR Message: Max change in miniumum load to unload delay.
-#define     rx_eo_final_l2u_dly_maxchg_gcrmsg_clear           0xC0FF     // Clear mask
-#define     rx_eo_final_l2u_dly_chg                           0x0000     //GCR Message: Local change in miniumum load to unload delay.
-#define     rx_eo_final_l2u_dly_chg_clear                     0x3FC0     // Clear mask
-
-// rx_gcr_msg_debug_dest_ids_pg Register field name                     data value   Description
-#define     rx_gcr_msg_debug_dest_bus_id_clear                0x03FF     // Clear mask
-#define     rx_gcr_msg_debug_dest_group_id_clear              0xFC0F     // Clear mask
-
-// rx_gcr_msg_debug_src_ids_pg Register field name                      data value   Description
-#define     rx_gcr_msg_debug_src_bus_id_clear                 0x03FF     // Clear mask
-#define     rx_gcr_msg_debug_src_group_id_clear               0xFC0F     // Clear mask
-
-// rx_gcr_msg_debug_dest_addr_pg Register field name                    data value   Description
-#define     rx_gcr_msg_debug_dest_addr_clear                  0x007F     // Clear mask
-#define     rx_gcr_msg_debug_send_msg                         0x0001     //GCR Messaging Debug: Send GCR Message on rising edge of this bit.
-#define     rx_gcr_msg_debug_send_msg_clear                   0xFFFE     // Clear mask
-
-// rx_gcr_msg_debug_write_data_pg Register field name                   data value   Description
-#define     rx_gcr_msg_debug_write_data_clear                 0x0000     // Clear mask
-
-// rx_dyn_recal_pg Register field name                                  data value   Description
-#define     rx_servo_recal_ip                                 0x8000     //RX Servo Lane Calibration In Progress
-#define     rx_servo_recal_ip_clear                           0x7FFF     // Clear mask
-#define     rx_dyn_recal_main_state_clear                     0xC0FF     // Clear mask
-#define     rx_dyn_recal_hndshk_state_clear                   0x7F80     // Clear mask
-
-// rx_wt_clk_status_pg Register field name                              data value   Description
-#define     rx_wt_clk_lane_inverted                           0x4000     //Clock Wiretest lane inverted/swapped status 
-#define     rx_wt_clk_lane_inverted_clear                     0xBFFF     // Clear mask
-#define     rx_wt_clk_lane_bad_code_n_stuck_1                 0x0800     //Clock Wiretest Lane Bad code  N leg stuck at 1 
-#define     rx_wt_clk_lane_bad_code_n_stuck_0                 0x1000     //Clock Wiretest Lane Bad code  N leg stuck at 0 
-#define     rx_wt_clk_lane_bad_code_p_stuck_1                 0x1800     //Clock Wiretest Lane Bad code  P leg stuck at 1 
-#define     rx_wt_clk_lane_bad_code_p_stuck_0                 0x2000     //Clock Wiretest Lane Bad code  P leg stuck at 0 
-#define     rx_wt_clk_lane_bad_code_n_or_p_floating           0x2800     //Clock Wiretest Lane Bad code  N  or P leg floating or swapping undetermined 
-#define     rx_wt_clk_lane_bad_code_NOT_USED_110              0x3000     //Clock Wiretest Lane Bad code Unused.
-#define     rx_wt_clk_lane_bad_code_NOT_USED_111              0x3800     //Clock Wiretest Lane Bad code Unused.
-#define     rx_wt_clk_lane_bad_code_clear                     0xC7FF     // Clear mask
-
-// rx_dyn_recal_config_pg Register field name                           data value   Description
-#define     rx_dyn_recal_overall_timeout_sel_tap1             0x2000     //Dynamic Recalibration Overall Timeout Selects  436.73us - smallest value for normal operation
-#define     rx_dyn_recal_overall_timeout_sel_tap2             0x4000     //Dynamic Recalibration Overall Timeout Selects  873.46uS
-#define     rx_dyn_recal_overall_timeout_sel_tap3             0x6000     //Dynamic Recalibration Overall Timeout Selects  1.75mS
-#define     rx_dyn_recal_overall_timeout_sel_tap4             0x8000     //Dynamic Recalibration Overall Timeout Selects  3.49mS - Recal should be around 2mS
-#define     rx_dyn_recal_overall_timeout_sel_tap5             0xA000     //Dynamic Recalibration Overall Timeout Selects  13.97mS
-#define     rx_dyn_recal_overall_timeout_sel_tap6             0xC000     //Dynamic Recalibration Overall Timeout Selects  55.90mS - largest value for normal operation
-#define     rx_dyn_recal_overall_timeout_sel_tap7             0xE000     //Dynamic Recalibration Overall Timeout Selects  Infinite- For debug purposes
-#define     rx_dyn_recal_overall_timeout_sel_clear            0x1FFF     // Clear mask
-#define     rx_dyn_recal_suspend                              0x1000     //Suspend Dynamic Recalibration; otherwise starts automatically after link training
-#define     rx_dyn_recal_suspend_clear                        0xEFFF     // Clear mask
-
-// rx_dyn_recal_gcrmsg_pg Register field name                           data value   Description
-#define     rx_dyn_recal_ip_gcrmsg                            0x8000     //GCR Message: RX Dynamic Recalibration In Progress
-#define     rx_dyn_recal_ip_gcrmsg_clear                      0x7FFF     // Clear mask
-#define     rx_dyn_recal_failed_gcrmsg                        0x4000     //GCR Message: RX Dynamic Recalibration Failed
-#define     rx_dyn_recal_failed_gcrmsg_clear                  0xBFFF     // Clear mask
-#define     rx_dyn_recal_ripple_gcrmsg                        0x2000     //GCR Message: RX Dynamic Recalibration: Reached end of bus...ripple back down to the beginning
-#define     rx_dyn_recal_ripple_gcrmsg_clear                  0xDFFF     // Clear mask
-#define     rx_dyn_recal_timeout_gcrmsg                       0x1000     //GCR Message: RX Dynamic Recalibration: Recal Handshake Timed Out
-#define     rx_dyn_recal_timeout_gcrmsg_clear                 0xEFFF     // Clear mask
-
-// rx_wiretest_pll_cntl_pg Register field name                          data value   Description
-#define     rx_wt_cu_pll_pgood                                0x8000     //RX PLL/DLL Enable
-#define     rx_wt_cu_pll_pgood_clear                          0x7FFF     // Clear mask
-#define     rx_wt_cu_pll_reset                                0x4000     //RX PLL/DLL Enable Request
-#define     rx_wt_cu_pll_reset_clear                          0xBFFF     // Clear mask
-#define     rx_wt_cu_pll_pgooddly_50ns                        0x0800     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   Nominal 50ns Reset per PLL Spec 
-#define     rx_wt_cu_pll_pgooddly_100ns                       0x1000     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   Double Nominal 50ns Reset per PLL Spec 
-#define     rx_wt_cu_pll_pgooddly_960ui                       0x1800     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   Typical simulation delay exceeding TX PLL 40-refclk locking period 
-#define     rx_wt_cu_pll_pgooddly_unused_100                  0x2000     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   Reserved 
-#define     rx_wt_cu_pll_pgooddly_unused_101                  0x2800     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   Reserved 
-#define     rx_wt_cu_pll_pgooddly_MAX                         0x3000     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   1024 UI  
-#define     rx_wt_cu_pll_pgooddly_disable                     0x3800     //RX PLL/DLL PGOOD Delay Selects length of reset period after rx_wt_cu_pll_reset is set.   Disable rx_wt_cu_pll_reset
-#define     rx_wt_cu_pll_pgooddly_clear                       0xC7FF     // Clear mask
-#define     rx_wt_cu_pll_lock                                 0x0400     //RX PLL/DLL Locked
-#define     rx_wt_cu_pll_lock_clear                           0xFBFF     // Clear mask
-#define     rx_wt_pll_refclksel                               0x0200     //Select between IO clock and BIST/Refclock
-#define     rx_wt_pll_refclksel_clear                         0xFDFF     // Clear mask
-#define     rx_pll_refclksel_scom_en                          0x0100     //Selects between PLL controls and GCR register to select refclk
-#define     rx_pll_refclksel_scom_en_clear                    0xFEFF     // Clear mask
-
-// rx_eo_step_cntl_pg Register field name                               data value   Description
-#define     rx_eo_enable_latch_offset_cal                     0x8000     //RX eye optimization latch offset adjustment enable
-#define     rx_eo_enable_latch_offset_cal_clear               0x7FFF     // Clear mask
-#define     rx_eo_enable_ctle_cal                             0x4000     //RX eye optimization CTLE/Peakin enable
-#define     rx_eo_enable_ctle_cal_clear                       0xBFFF     // Clear mask
-#define     rx_eo_enable_vga_cal                              0x2000     //RX eye optimization VGA gainand offset adjust enable
-#define     rx_eo_enable_vga_cal_clear                        0xDFFF     // Clear mask
-#define     rx_eo_enable_dfe_h1_cal                           0x0800     //RX eye optimization DFE H1  adjust enable
-#define     rx_eo_enable_dfe_h1_cal_clear                     0xF7FF     // Clear mask
-#define     rx_eo_enable_h1ap_tweak                           0x0400     //RX eye optimization H1/AN PR adjust enable
-#define     rx_eo_enable_h1ap_tweak_clear                     0xFBFF     // Clear mask
-#define     rx_eo_enable_ddc                                  0x0200     //RX eye optimization Dynamic data centering enable
-#define     rx_eo_enable_ddc_clear                            0xFDFF     // Clear mask
-#define     rx_eo_enable_final_l2u_adj                        0x0080     //RX eye optimization Final RX FIFO load-to-unload delay adjustment enable
-#define     rx_eo_enable_final_l2u_adj_clear                  0xFF7F     // Clear mask
-#define     rx_eo_enable_ber_test                             0x0040     //RX eye optimization Bit error rate test enable
-#define     rx_eo_enable_ber_test_clear                       0xFFBF     // Clear mask
-#define     rx_eo_enable_result_check                         0x0020     //RX eye optimization Final results check enable
-#define     rx_eo_enable_result_check_clear                   0xFFDF     // Clear mask
-#define     rx_eo_enable_ctle_edge_track_only                 0x0010     //RX eye optimization CTLE/Peakin enable with edge tracking only
-#define     rx_eo_enable_ctle_edge_track_only_clear           0xFFEF     // Clear mask
-
-// rx_eo_step_stat_pg Register field name                               data value   Description
-#define     rx_eo_latch_offset_done                           0x8000     //RX eye optimization latch offset adjustment done
-#define     rx_eo_latch_offset_done_clear                     0x7FFF     // Clear mask
-#define     rx_eo_ctle_done                                   0x4000     //RX eye optimization CTLE/Peaking done
-#define     rx_eo_ctle_done_clear                             0xBFFF     // Clear mask
-#define     rx_eo_vga_done                                    0x2000     //RX eye optimization VGA gain/offset adjust done
-#define     rx_eo_vga_done_clear                              0xDFFF     // Clear mask
-#define     rx_eo_dfe_h1_done                                 0x0800     //RX eye optimization DFE H1  adjust done
-#define     rx_eo_dfe_h1_done_clear                           0xF7FF     // Clear mask
-#define     rx_eo_h1ap_tweak_done                             0x0400     //RX eye optimization H1/AN PR adjust done
-#define     rx_eo_h1ap_tweak_done_clear                       0xFBFF     // Clear mask
-#define     rx_eo_ddc_done                                    0x0200     //RX eye optimization Dynamic data centering done
-#define     rx_eo_ddc_done_clear                              0xFDFF     // Clear mask
-#define     rx_eo_final_l2u_adj_done                          0x0080     //RX eye optimization Final RX FIFO load-to-unload adjust done
-#define     rx_eo_final_l2u_adj_done_clear                    0xFF7F     // Clear mask
-#define     rx_eo_dfe_flag                                    0x0040     //RX eye optimization DFE mode flag              
-#define     rx_eo_dfe_flag_clear                              0xFFBF     // Clear mask
-#define     rx_eo_ber_test_done                               0x0020     //RX eye optimization Bit Error rate test done
-#define     rx_eo_ber_test_done_clear                         0xFFDF     // Clear mask
-#define     rx_eo_result_check_done                           0x0010     //RX eye optimization Eye width/heightER check done 
-#define     rx_eo_result_check_done_clear                     0xFFEF     // Clear mask
-
-// rx_eo_step_fail_pg Register field name                               data value   Description
-#define     rx_eo_latch_offset_failed                         0x8000     //RX eye optimization latch offset adjustment  failed
-#define     rx_eo_latch_offset_failed_clear                   0x7FFF     // Clear mask
-#define     rx_eo_ctle_failed                                 0x4000     //RX eye optimization CTLE/Peaking  failed
-#define     rx_eo_ctle_failed_clear                           0xBFFF     // Clear mask
-#define     rx_eo_vga_failed                                  0x2000     //RX eye optimization VGA gain/offset adjust  failed
-#define     rx_eo_vga_failed_clear                            0xDFFF     // Clear mask
-#define     rx_eo_dfe_h1_failed                               0x0800     //RX eye optimization DFE H1  adjust failed
-#define     rx_eo_dfe_h1_failed_clear                         0xF7FF     // Clear mask
-#define     rx_eo_h1ap_tweak_failed                           0x0400     //RX eye optimization H1/AN PR adjust failed
-#define     rx_eo_h1ap_tweak_failed_clear                     0xFBFF     // Clear mask
-#define     rx_eo_ddc_failed                                  0x0200     //RX eye optimization Dynamic data centering failed
-#define     rx_eo_ddc_failed_clear                            0xFDFF     // Clear mask
-#define     rx_eo_final_l2u_adj_failed                        0x0080     //RX eye optimization Final RX FIFO load-to-unload adjust  failed
-#define     rx_eo_final_l2u_adj_failed_clear                  0xFF7F     // Clear mask
-#define     rx_eo_result_check_failed                         0x0040     //RX eye optimization Final Result checking failed
-#define     rx_eo_result_check_failed_clear                   0xFFBF     // Clear mask
-
-// rx_ap_pg Register field name                                         data value   Description
-#define     rx_ap_even_work                                   0x0000     //RX Ap even working register
-#define     rx_ap_even_work_clear                             0x00FF     // Clear mask
-#define     rx_ap_odd_work                                    0x0000     //Rx Ap odd  working register
-#define     rx_ap_odd_work_clear                              0xFF00     // Clear mask
-
-// rx_an_pg Register field name                                         data value   Description
-#define     rx_an_even_work                                   0x0000     //RX An even working register
-#define     rx_an_even_work_clear                             0x00FF     // Clear mask
-#define     rx_an_odd_work                                    0x0000     //Rx An odd  working register
-#define     rx_an_odd_work_clear                              0xFF00     // Clear mask
-
-// rx_amin_pg Register field name                                       data value   Description
-#define     rx_amin_even_work                                 0x0000     //RX Amin even working register
-#define     rx_amin_even_work_clear                           0x00FF     // Clear mask
-#define     rx_amin_odd_work                                  0x0000     //Rx Amin odd  working register
-#define     rx_amin_odd_work_clear                            0xFF00     // Clear mask
-
-// rx_amax_pg Register field name                                       data value   Description
-#define     rx_amax_high                                      0x0000     //RX Amax high limit default 125
-#define     rx_amax_high_clear                                0x00FF     // Clear mask
-#define     rx_amax_low                                       0x0000     //Rx Amax low limit  default 75
-#define     rx_amax_low_clear                                 0xFF00     // Clear mask
-
-// rx_amp_val_pg Register field name                                    data value   Description
-#define     rx_amp_peak_work                                  0x0000     //Rx amp peak working register
-#define     rx_amp_peak_work_clear                            0x0FFF     // Clear mask
-#define     rx_amp_gain_work                                  0x0000     //Rx Amp gain working register
-#define     rx_amp_gain_work_clear                            0xF0FF     // Clear mask
-#define     rx_amp_offset_work                                0x0000     //Rx amp offset working register
-#define     rx_amp_offset_work_clear                          0x3FC0     // Clear mask
-
-// rx_amp_offset_pg Register field name                                 data value   Description
-#define     rx_amp_offset_max                                 0x0000     //Rx amp maximum allowable offset
-#define     rx_amp_offset_max_clear                           0x03FF     // Clear mask
-#define     rx_amp_offset_min                                 0x0000     //Rx Amp minimum allowable offset
-#define     rx_amp_offset_min_clear                           0xFC0F     // Clear mask
-
-// rx_eo_convergence_pg Register field name                             data value   Description
-#define     rx_eo_converged_count                             0x0000     //RX eye optimization Convergence counter current value
-#define     rx_eo_converged_count_clear                       0x0FFF     // Clear mask
-#define     rx_eo_converged_end_count                         0x0000     //RX eye optimization Covergence counter end value
-#define     rx_eo_converged_end_count_clear                   0xF0FF     // Clear mask
-
-// rx_sls_rcvy_pg Register field name                                   data value   Description
-#define     rx_sls_rcvy_disable                               0x8000     //Disable SLS Recovery
-#define     rx_sls_rcvy_disable_clear                         0x7FFF     // Clear mask
-#define     rx_sls_rcvy_state_clear                           0xE0FF     // Clear mask
-
-// rx_sls_rcvy_gcrmsg_pg Register field name                            data value   Description
-#define     rx_sls_rcvy_req_gcrmsg                            0x8000     //GCR Message: SLS Rcvy; RX Lane Repair Req
-#define     rx_sls_rcvy_req_gcrmsg_clear                      0x7FFF     // Clear mask
-#define     rx_sls_rcvy_ip_gcrmsg                             0x4000     //GCR Message: SLS Rcvy; RX Lane Repair IP
-#define     rx_sls_rcvy_ip_gcrmsg_clear                       0xBFFF     // Clear mask
-#define     rx_sls_rcvy_done_gcrmsg                           0x2000     //GCR Message: SLS Rcvy; RX Lane Repair Done
-#define     rx_sls_rcvy_done_gcrmsg_clear                     0xDFFF     // Clear mask
-
-// rx_tx_lane_info_gcrmsg_pg Register field name                        data value   Description
-#define     rx_tx_bad_lane_cntr_gcrmsg                        0x0000     //GCR Message: RX Side TX Bad Lane Counter
-#define     rx_tx_bad_lane_cntr_gcrmsg_clear                  0x3FFF     // Clear mask
-
-// rx_err_tallying_gcrmsg_pg Register field name                        data value   Description
-#define     rx_dis_synd_tallying_gcrmsg                       0x8000     //GCR Message: Disable Syndrome Tallying
-#define     rx_dis_synd_tallying_gcrmsg_clear                 0x7FFF     // Clear mask
-
-// rx_trace_pg Register field name                                      data value   Description
-#define     rx_trc_mode_tap1                                  0x1000     //RX Trace Mode  Dynamic Repair State Machines
-#define     rx_trc_mode_tap2                                  0x2000     //RX Trace Mode  SLS Handshake State Machines with Recovery
-#define     rx_trc_mode_tap3                                  0x3000     //RX Trace Mode  Dynamic Recal State Machines
-#define     rx_trc_mode_tap4                                  0x4000     //RX Trace Mode  Recal Handshake State Machine with Recovery
-#define     rx_trc_mode_tap5                                  0x5000     //RX Trace Mode  CRC or ECC Tallying Logic
-#define     rx_trc_mode_tap6                                  0x6000     //RX Trace Mode  RX SLS Commands
-#define     rx_trc_mode_tap7                                  0x7000     //RX Trace Mode  RX Bad Lanes
-#define     rx_trc_mode_tap8                                  0x8000     //RX Trace Mode  RX SLS Lanes
-#define     rx_trc_mode_tap9                                  0x9000     //RX Trace Mode  GCR
-#define     rx_trc_mode_tap10                                 0xA000     //RX Trace Mode  Per Lane / Per Pack Trace (see rx_pp_trc_mode for details
-#define     rx_trc_mode_tap11                                 0xB000     //RX Trace Mode  TBD
-#define     rx_trc_mode_tap12                                 0xC000     //RX Trace Mode  TBD
-#define     rx_trc_mode_tap13                                 0xD000     //RX Trace Mode  TBD
-#define     rx_trc_mode_tap14                                 0xE000     //RX Trace Mode  TBD
-#define     rx_trc_mode_tap15                                 0xF000     //RX Trace Mode  TBD
-#define     rx_trc_mode_clear                                 0x0FFF     // Clear mask
-#define     rx_trc_grp_clear                                  0xFC0F     // Clear mask
-
-// rx_rc_step_cntl_pg Register field name                               data value   Description
-#define     rx_rc_enable_latch_offset_cal                     0x8000     //RX recalibration    latch offset adjustment enable
-#define     rx_rc_enable_latch_offset_cal_clear               0x7FFF     // Clear mask
-#define     rx_rc_enable_ctle_cal                             0x4000     //RX recalibration    CTLE/Peaking enable
-#define     rx_rc_enable_ctle_cal_clear                       0xBFFF     // Clear mask
-#define     rx_rc_enable_vga_cal                              0x2000     //RX recalibration    VGA gainand offset adjust enable
-#define     rx_rc_enable_vga_cal_clear                        0xDFFF     // Clear mask
-#define     rx_rc_enable_dfe_h1_cal                           0x0800     //RX recalibration    DFE H1  adjust enable
-#define     rx_rc_enable_dfe_h1_cal_clear                     0xF7FF     // Clear mask
-#define     rx_rc_enable_h1ap_tweak                           0x0400     //RX recalibration    H1/AN PR adjust enable
-#define     rx_rc_enable_h1ap_tweak_clear                     0xFBFF     // Clear mask
-#define     rx_rc_enable_ddc                                  0x0200     //RX recalibration    Dynamic data centering enable
-#define     rx_rc_enable_ddc_clear                            0xFDFF     // Clear mask
-#define     rx_rc_enable_ber_test                             0x0080     //RX recalibration    Bit error rate test enable
-#define     rx_rc_enable_ber_test_clear                       0xFF7F     // Clear mask
-#define     rx_rc_enable_result_check                         0x0040     //RX recalibration    Final results check enable
-#define     rx_rc_enable_result_check_clear                   0xFFBF     // Clear mask
-#define     rx_rc_enable_ctle_edge_track_only                 0x0010     //RX recalibration    CTLE/Peaking enable with edge tracking only
-#define     rx_rc_enable_ctle_edge_track_only_clear           0xFFEF     // Clear mask
-
-// rx_eo_recal_pg Register field name                                   data value   Description
-#define     rx_eye_opt_state                                  0x0000     //Common EDI/EI4 Eye optimizaton State Machine
-#define     rx_eye_opt_state_clear                            0x00FF     // Clear mask
-#define     rx_recal_state                                    0x0000     //Common EDI/EI4 recalibration State Machine
-#define     rx_recal_state_clear                              0xFF00     // Clear mask
-
-// rx_servo_ber_count_pg Register field name                            data value   Description
-#define     rx_servo_ber_count_work                           0x0000     //Rx servo-based bit error rate count working register
-#define     rx_servo_ber_count_work_clear                     0x000F     // Clear mask
-
-// rx_func_state_pg Register field name                                 data value   Description
-#define     rx_func_mode_state                                0x0000     //Functional Mode State Machine(RJR):
-#define     rx_func_mode_state_clear                          0x0FFF     // Clear mask
-
-// rx_dyn_rpr_debug_pg Register field name                              data value   Description
-#define     rx_dyn_rpr_enc_bad_data_lane_debug                0x0000     //For testfloor/debug purposes, specify the encoded bad data lane to report to the dynamic repair tally logic
-#define     rx_dyn_rpr_enc_bad_data_lane_debug_clear          0x01FF     // Clear mask
-#define     rx_dyn_rpr_bad_lane_valid_debug                   0x0080     //For testfloor/debug purposes, the specified encoded bad data lane will be tallied as having one cycle of a valid CRC/ECC error (this is a write-only pulse register)
-#define     rx_dyn_rpr_bad_lane_valid_debug_clear             0xFF7F     // Clear mask
-
-// rx_dyn_rpr_err_tallying2_pg Register field name                      data value   Description
-#define     rx_dyn_rpr_bad_bus_max                            0x0000     //CRC/ECC Dynamic Repair: Max number of times CRC or ECC errors can be found on the bus (not included in the bad lane cntr1 tally) before setting a FIR error
-#define     rx_dyn_rpr_bad_bus_max_clear                      0x01FF     // Clear mask
-#define     rx_dyn_rpr_err_cntr2_duration_tap1                0x0020     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  853.0ns & 1.3uS
-#define     rx_dyn_rpr_err_cntr2_duration_tap2                0x0040     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  27.3uS & 41.0uS
-#define     rx_dyn_rpr_err_cntr2_duration_tap3                0x0060     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  873.5uS & 1.3mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap4                0x0080     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  1.7mS & 2.6mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap5                0x00A0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  3.5mS & 5.1mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap6                0x00C0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  7.0mS & 10.5mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap7                0x00E0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  14.0mS & 21.0mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap8                0x0100     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  28.0mS & 41.9mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap9                0x0120     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  55.9mS & 83.9mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap10               0x0140     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  111.8mS & 167.8mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap11               0x0160     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  223.6mS & 335.5mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap12               0x0180     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  447.2mS & 671.1mS
-#define     rx_dyn_rpr_err_cntr2_duration_tap13               0x01A0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  894.4mS & 1.3 S
-#define     rx_dyn_rpr_err_cntr2_duration_tap14               0x01C0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  1.8 S & 2.7 S
-#define     rx_dyn_rpr_err_cntr2_duration_tap15               0x01E0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  infinite
-#define     rx_dyn_rpr_err_cntr2_duration_clear               0x3E1F     // Clear mask
-#define     rx_dyn_rpr_clr_err_cntr2                          0x0010     //CRC/ECC Dynamic Repair: Firmware-based clear of bus error counter2 register
-#define     rx_dyn_rpr_clr_err_cntr2_clear                    0xFFEF     // Clear mask
-
-// rx_result_chk_pg Register field name                                 data value   Description
-#define     rx_min_eye_width                                  0x0000     //Minimum acceptable eye width used during init or recal results checking--EDI or EI4
-#define     rx_min_eye_width_clear                            0xC0FF     // Clear mask
-#define     rx_min_eye_height                                 0x0000     //Minimum acceptable eye height used during init or recal results checking--EDI only
-#define     rx_min_eye_height_clear                           0xFF00     // Clear mask
-
-// rx_ber_chk_pg Register field name                                    data value   Description
-#define     rx_max_ber_check_count                            0x0000     //Maximum acceptable number of bit errors allowable after recal--EDI only
-#define     rx_max_ber_check_count_clear                      0x0000     // Clear mask
-
-// rx_sls_rcvy_fin_gcrmsg_pg Register field name                        data value   Description
-#define     rx_slv_shdw_done_fin_gcrmsg                       0x8000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done
-#define     rx_slv_shdw_done_fin_gcrmsg_clear                 0x7FFF     // Clear mask
-#define     rx_slv_shdw_nop_fin_gcrmsg                        0x4000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     rx_slv_shdw_nop_fin_gcrmsg_clear                  0xBFFF     // Clear mask
-#define     rx_slv_shdw_rpr_done_fin_gcrmsg                   0x2000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done
-#define     rx_slv_shdw_rpr_done_fin_gcrmsg_clear             0xDFFF     // Clear mask
-#define     rx_slv_shdw_rpr_nop_fin_gcrmsg                    0x1000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     rx_slv_shdw_rpr_nop_fin_gcrmsg_clear              0xEFFF     // Clear mask
-#define     rx_slv_unshdw_done_fin_gcrmsg                     0x0800     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done
-#define     rx_slv_unshdw_done_fin_gcrmsg_clear               0xF7FF     // Clear mask
-#define     rx_slv_unshdw_nop_fin_gcrmsg                      0x0400     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     rx_slv_unshdw_nop_fin_gcrmsg_clear                0xFBFF     // Clear mask
-#define     rx_slv_unshdw_rpr_done_fin_gcrmsg                 0x0200     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done
-#define     rx_slv_unshdw_rpr_done_fin_gcrmsg_clear           0xFDFF     // Clear mask
-#define     rx_slv_unshdw_rpr_nop_fin_gcrmsg                  0x0100     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear            0xFEFF     // Clear mask
-#define     rx_slv_recal_done_nop_fin_gcrmsg                  0x0080     //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop
-#define     rx_slv_recal_done_nop_fin_gcrmsg_clear            0xFF7F     // Clear mask
-#define     rx_slv_recal_fail_nop_fin_gcrmsg                  0x0040     //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop
-#define     rx_slv_recal_fail_nop_fin_gcrmsg_clear            0xFFBF     // Clear mask
-#define     rx_slv_recal_presults_fin_gcrmsg                  0x0020     //GCR Message: Slave Recal Pass Results; Need to finish slave recal handshake starting with waiting for results
-#define     rx_slv_recal_presults_fin_gcrmsg_clear            0xFFDF     // Clear mask
-#define     rx_slv_recal_fresults_fin_gcrmsg                  0x0010     //GCR Message: Slave Recal Fail Results; Need to finish slave recal handshake starting with waiting for results
-#define     rx_slv_recal_fresults_fin_gcrmsg_clear            0xFFEF     // Clear mask
-#define     rx_slv_recal_abort_ack_fin_gcrmsg                 0x0008     //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop
-#define     rx_slv_recal_abort_ack_fin_gcrmsg_clear           0xFFF7     // Clear mask
-#define     rx_slv_recal_abort_mnop_fin_gcrmsg                0x0004     //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop
-#define     rx_slv_recal_abort_mnop_fin_gcrmsg_clear          0xFFFB     // Clear mask
-#define     rx_slv_recal_abort_snop_fin_gcrmsg                0x0002     //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop
-#define     rx_slv_recal_abort_snop_fin_gcrmsg_clear          0xFFFD     // Clear mask
-
-// rx_wiretest_pp Register field name                                   data value   Description
-#define     rx_wt_pattern_length_256                          0x4000     //RX Wiretest Pattern Length  256
-#define     rx_wt_pattern_length_512                          0x8000     //RX Wiretest Pattern Length  512
-#define     rx_wt_pattern_length_1024                         0xC000     //RX Wiretest Pattern Length  1024
-#define     rx_wt_pattern_length_clear                        0x3FFF     // Clear mask
-
-// rx_mode1_pp Register field name                                      data value   Description
-#define     rx_reduced_scramble_mode_disable_1                0x4000     //Sets reduced density of scramble pattern.   Disable reduced density 
-#define     rx_reduced_scramble_mode_enable_div2              0x8000     //Sets reduced density of scramble pattern.   Enable Div2 Reduced Density 
-#define     rx_reduced_scramble_mode_enable_div4              0xC000     //Sets reduced density of scramble pattern.   Enable Div4 Reduced Density
-#define     rx_reduced_scramble_mode_clear                    0x3FFF     // Clear mask
-#define     rx_act_check_timeout_sel_128ui                    0x0800     //Sets Activity check timeout value.   128 UI 
-#define     rx_act_check_timeout_sel_256ui                    0x1000     //Sets Activity check timeout value.   256 UI 
-#define     rx_act_check_timeout_sel_512ui                    0x1800     //Sets Activity check timeout value.   512 UI 
-#define     rx_act_check_timeout_sel_1024ui                   0x2000     //Sets Activity check timeout value.   1024 UI 
-#define     rx_act_check_timeout_sel_2048ui                   0x2800     //Sets Activity check timeout value.   2048 UI 
-#define     rx_act_check_timeout_sel_4096ui                   0x3000     //Sets Activity check timeout value.   4096 UI 
-#define     rx_act_check_timeout_sel_infinite                 0x3800     //Sets Activity check timeout value.   Infinite
-#define     rx_act_check_timeout_sel_clear                    0xC7FF     // Clear mask
-#define     rx_block_lock_timeout_sel_1024ui                  0x0100     //Sets block lock timeout value.   1024 UI 
-#define     rx_block_lock_timeout_sel_2048ui                  0x0200     //Sets block lock timeout value.   2048 UI 
-#define     rx_block_lock_timeout_sel_4096ui                  0x0300     //Sets block lock timeout value.   4096 UI 
-#define     rx_block_lock_timeout_sel_8192ui                  0x0400     //Sets block lock timeout value.   8192 UI 
-#define     rx_block_lock_timeout_sel_16384ui                 0x0500     //Sets block lock timeout value.   16384 UI 
-#define     rx_block_lock_timeout_sel_32768ui                 0x0600     //Sets block lock timeout value.   32768 UI 
-#define     rx_block_lock_timeout_sel_infinite                0x0700     //Sets block lock timeout value.   Infinite
-#define     rx_block_lock_timeout_sel_clear                   0xF8FF     // Clear mask
-#define     rx_bit_lock_timeout_sel_512ui                     0x0020     //Sets bit lock/edge detect timeout value.   512 UI 
-#define     rx_bit_lock_timeout_sel_1024ui                    0x0040     //Sets bit lock/edge detect timeout value.   1024 UI 
-#define     rx_bit_lock_timeout_sel_2048ui                    0x0060     //Sets bit lock/edge detect timeout value.   2048 UI 
-#define     rx_bit_lock_timeout_sel_4096ui                    0x0080     //Sets bit lock/edge detect timeout value.   4096 UI 
-#define     rx_bit_lock_timeout_sel_8192ui                    0x00A0     //Sets bit lock/edge detect timeout value.   8192 UI 
-#define     rx_bit_lock_timeout_sel_16384ui                   0x00C0     //Sets bit lock/edge detect timeout value.   16384 UI 
-#define     rx_bit_lock_timeout_sel_infinite                  0x00E0     //Sets bit lock/edge detect timeout value.   Infinite
-#define     rx_bit_lock_timeout_sel_clear                     0x1F1F     // Clear mask
-
-// rx_cntl_pp Register field name                                       data value   Description
-#define     rx_prbs_check_sync                                0x4000     //Enables checking for the 12 ui scramble sync pattern. 
-#define     rx_prbs_check_sync_clear                          0xBFFF     // Clear mask
-#define     rx_enable_reduced_scramble                        0x2000     //Enables reduced density of scramble pattern. 
-#define     rx_enable_reduced_scramble_clear                  0xDFFF     // Clear mask
-#define     rx_prbs_inc                                       0x1000     //Shift the PRBS pattern forward in time by one extra local cycle (4ui for EDI, 2ui for EI4).
-#define     rx_prbs_inc_clear                                 0xEFFF     // Clear mask
-#define     rx_prbs_dec                                       0x0800     //Shift the PRBS pattern back in time by holding it one local cycle (4ui for EDI, 2ui for EI4).
-#define     rx_prbs_dec_clear                                 0xF7FF     // Clear mask
-
-// rx_dyn_recal_timeouts_pp Register field name                         data value   Description
-#define     rx_dyn_recal_interval_timeout_sel_tap1            0x1000     //RX Dynamic Recalibration Interval Timeout Selects  16kUI or 1.7us
-#define     rx_dyn_recal_interval_timeout_sel_tap2            0x2000     //RX Dynamic Recalibration Interval Timeout Selects  32kUI or 3.4us
-#define     rx_dyn_recal_interval_timeout_sel_tap3            0x3000     //RX Dynamic Recalibration Interval Timeout Selects  64kUI or 6.8us
-#define     rx_dyn_recal_interval_timeout_sel_tap4            0x4000     //RX Dynamic Recalibration Interval Timeout Selects  128kUI or 106.5ns
-#define     rx_dyn_recal_interval_timeout_sel_tap5            0x5000     //RX Dynamic Recalibration Interval Timeout Selects  256kUI or 1.7us
-#define     rx_dyn_recal_interval_timeout_sel_tap6            0x6000     //RX Dynamic Recalibration Interval Timeout Selects  8192kUI or 872.4us
-#define     rx_dyn_recal_interval_timeout_sel_tap7            0x7000     //RX Dynamic Recalibration Interval Timeout Selects  infinite
-#define     rx_dyn_recal_interval_timeout_sel_clear           0x8FFF     // Clear mask
-#define     rx_dyn_recal_status_rpt_timeout_sel_tap1          0x0400     //RX Dynamic Recalibration Status Reporting Timeout Selects  1024UI or 106.5ns
-#define     rx_dyn_recal_status_rpt_timeout_sel_tap2          0x0800     //RX Dynamic Recalibration Status Reporting Timeout Selects  2048UI or 212.9ns
-#define     rx_dyn_recal_status_rpt_timeout_sel_tap3          0x0C00     //RX Dynamic Recalibration Status Reporting Timeout Selects  4096UI or 426.0ns
-#define     rx_dyn_recal_status_rpt_timeout_sel_clear         0xF3FF     // Clear mask
-
-// rx_mode2_pp Register field name                                      data value   Description
-#define     rx_bist_jitter_pulse_ctl_0                        0x4000     //Jitter Select  (steps8
-#define     rx_bist_jitter_pulse_ctl_1                        0x8000     //Jitter Select  (steps2
-#define     rx_bist_jitter_pulse_ctl_2                        0xC000     //Jitter Select  (steps0
-#define     rx_bist_jitter_pulse_ctl_clear                    0x3FFF     // Clear mask
-#define     rx_bist_min_eye_width                             0x0000     //Sets the minimum eye width value considered acceptable by PHYBIST.
-#define     rx_bist_min_eye_width_clear                       0xE07F     // Clear mask
-
-// rx_ber_cntl_pp Register field name                                   data value   Description
-#define     rx_ber_en                                         0x8000     //Per-Pack (PP) Diagnostic Bit Error Rate (BER) error checking enable control. When 1 enables error checking. When 0 the error checking is disabled. This control enables the BER timer as well as enables the error checker and BER counters. The assumption is that the driver(s) are currently driving PRBS23 and the link has been trained before enabling BER checking.
-#define     rx_ber_en_clear                                   0x7FFF     // Clear mask
-#define     rx_ber_count_clr                                  0x4000     //PP Diag BER error counter clear pulse. When written to a 1 the per-lane error counters are cleared to all zeroes. Writing both this bit and the timer clear bit to a 1 will clear both and allow a new set of measurements to be run.
-#define     rx_ber_count_clr_clear                            0xBFFF     // Clear mask
-#define     rx_ber_timer_clr                                  0x2000     //PP Diag BER timer clear pulse. When written to a 1 the per-pack timers are cleared to all zeroes. Writing both this bit and the error counter clear bit to a 1 will clear both and allow a new set of measurements to be run.
-#define     rx_ber_timer_clr_clear                            0xDFFF     // Clear mask
-
-// rx_ber_mode_pp Register field name                                   data value   Description
-#define     rx_ber_timer_freeze_en                            0x8000     //Per-Pack (PP) Diagnostic Bit Error Rate (BER) Timer freeze enable. When set to a 1 the per-pack timer is frozen when any lane error count saturates in that pack.
-#define     rx_ber_timer_freeze_en_clear                      0x7FFF     // Clear mask
-#define     rx_ber_count_freeze_en                            0x4000     //PP Diag BER Lane Error Counter freeze enable. When set to a 1 the per-lane error counters are frozen when the timer saturates in that pack.
-#define     rx_ber_count_freeze_en_clear                      0xBFFF     // Clear mask
-#define     rx_ber_count_sel_2                                0x0400     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   2
-#define     rx_ber_count_sel_4                                0x0800     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   4
-#define     rx_ber_count_sel_8                                0x0C00     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   8
-#define     rx_ber_count_sel_16                               0x1000     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   16
-#define     rx_ber_count_sel_32                               0x1400     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   32
-#define     rx_ber_count_sel_64                               0x1800     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   64
-#define     rx_ber_count_sel_128                              0x1C00     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   128
-#define     rx_ber_count_sel_clear                            0xE3FF     // Clear mask
-#define     rx_ber_timer_sel_2tothe36th                       0x0080     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^36
-#define     rx_ber_timer_sel_2tothe32nd                       0x0100     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^32
-#define     rx_ber_timer_sel_2tothe28th                       0x0180     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^28
-#define     rx_ber_timer_sel_2tothe24th                       0x0200     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^24
-#define     rx_ber_timer_sel_2tothe20th                       0x0280     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^20
-#define     rx_ber_timer_sel_2tothe16th                       0x0300     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^16
-#define     rx_ber_timer_sel_2tothe12th                       0x0380     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^12
-#define     rx_ber_timer_sel_clear                            0xFC7F     // Clear mask
-#define     rx_ber_clr_count_on_read_en                       0x0040     //PP Diag BER Lane Error Counter clear on read. When set to a 1 this enables the clearing of a lanes error counter when it is read.
-#define     rx_ber_clr_count_on_read_en_clear                 0xFFBF     // Clear mask
-#define     rx_ber_clr_timer_on_read_en                       0x0020     //PP Diag BER Timer clear on read. When set to a 1 this enables the clearing of a lanes per-pack timer when it is read from any lane in the pack.
-#define     rx_ber_clr_timer_on_read_en_clear                 0xFFDF     // Clear mask
-
-// rx_servo_to1_pp Register field name                                  data value   Description
-#define     rx_servo_timeout_sel_A_512ui                      0x1000     //RX servo operation timeout A.  512 UI 
-#define     rx_servo_timeout_sel_A_1Kui                       0x2000     //RX servo operation timeout A.  1K UI 
-#define     rx_servo_timeout_sel_A_2Kui                       0x3000     //RX servo operation timeout A.  2K UI 
-#define     rx_servo_timeout_sel_A_4Kui                       0x4000     //RX servo operation timeout A.  4096 UI 
-#define     rx_servo_timeout_sel_A_8Kui                       0x5000     //RX servo operation timeout A.  8K UI 
-#define     rx_servo_timeout_sel_A_16Kui                      0x6000     //RX servo operation timeout A.  16K UI 
-#define     rx_servo_timeout_sel_A_32Kui                      0x7000     //RX servo operation timeout A.  32K UI 
-#define     rx_servo_timeout_sel_A_64Kui                      0x8000     //RX servo operation timeout A.  64K UI 
-#define     rx_servo_timeout_sel_A_128Kui                     0x9000     //RX servo operation timeout A.  128K UI 
-#define     rx_servo_timeout_sel_A_256Kui                     0xA000     //RX servo operation timeout A.  256K UI 
-#define     rx_servo_timeout_sel_A_512Kui                     0xB000     //RX servo operation timeout A.  512K UI 
-#define     rx_servo_timeout_sel_A_1Mui                       0xC000     //RX servo operation timeout A.  1M UI 
-#define     rx_servo_timeout_sel_A_2Mui                       0xD000     //RX servo operation timeout A.  2M UI 
-#define     rx_servo_timeout_sel_A_4Mui                       0xE000     //RX servo operation timeout A.  4M UI
-#define     rx_servo_timeout_sel_A_Infinite                   0xF000     //RX servo operation timeout A.  Infinite
-#define     rx_servo_timeout_sel_A_clear                      0x0FFF     // Clear mask
-#define     rx_servo_timeout_sel_B_512ui                      0x0100     //RX servo operation timeout B.  512 UI 
-#define     rx_servo_timeout_sel_B_1Kui                       0x0200     //RX servo operation timeout B.  1K UI 
-#define     rx_servo_timeout_sel_B_2Kui                       0x0300     //RX servo operation timeout B.  2K UI 
-#define     rx_servo_timeout_sel_B_4Kui                       0x0400     //RX servo operation timeout B.  4096 UI 
-#define     rx_servo_timeout_sel_B_8Kui                       0x0500     //RX servo operation timeout B.  8K UI 
-#define     rx_servo_timeout_sel_B_16Kui                      0x0600     //RX servo operation timeout B.  16K UI 
-#define     rx_servo_timeout_sel_B_32Kui                      0x0700     //RX servo operation timeout B.  32K UI 
-#define     rx_servo_timeout_sel_B_64Kui                      0x0800     //RX servo operation timeout B.  64K UI 
-#define     rx_servo_timeout_sel_B_128Kui                     0x0900     //RX servo operation timeout B.  128K UI 
-#define     rx_servo_timeout_sel_B_256Kui                     0x0A00     //RX servo operation timeout B.  256K UI 
-#define     rx_servo_timeout_sel_B_512Kui                     0x0B00     //RX servo operation timeout B.  512K UI 
-#define     rx_servo_timeout_sel_B_1Mui                       0x0C00     //RX servo operation timeout B.  1M UI 
-#define     rx_servo_timeout_sel_B_2Mui                       0x0D00     //RX servo operation timeout B.  2M UI 
-#define     rx_servo_timeout_sel_B_4Mui                       0x0E00     //RX servo operation timeout B.  4M UI
-#define     rx_servo_timeout_sel_B_Infinite                   0x0F00     //RX servo operation timeout B.  Infinite
-#define     rx_servo_timeout_sel_B_clear                      0xF0FF     // Clear mask
-#define     rx_servo_timeout_sel_C_512ui                      0x0010     //RX servo operation timeout C.  512 UI 
-#define     rx_servo_timeout_sel_C_1Kui                       0x0020     //RX servo operation timeout C.  1K UI 
-#define     rx_servo_timeout_sel_C_2Kui                       0x0030     //RX servo operation timeout C.  2K UI 
-#define     rx_servo_timeout_sel_C_4Kui                       0x0040     //RX servo operation timeout C.  4096 UI 
-#define     rx_servo_timeout_sel_C_8Kui                       0x0050     //RX servo operation timeout C.  8K UI 
-#define     rx_servo_timeout_sel_C_16Kui                      0x0060     //RX servo operation timeout C.  16K UI 
-#define     rx_servo_timeout_sel_C_32Kui                      0x0070     //RX servo operation timeout C.  32K UI 
-#define     rx_servo_timeout_sel_C_64Kui                      0x0080     //RX servo operation timeout C.  64K UI 
-#define     rx_servo_timeout_sel_C_128Kui                     0x0090     //RX servo operation timeout C.  128K UI 
-#define     rx_servo_timeout_sel_C_256Kui                     0x00A0     //RX servo operation timeout C.  256K UI 
-#define     rx_servo_timeout_sel_C_512Kui                     0x00B0     //RX servo operation timeout C.  512K UI 
-#define     rx_servo_timeout_sel_C_1Mui                       0x00C0     //RX servo operation timeout C.  1M UI 
-#define     rx_servo_timeout_sel_C_2Mui                       0x00D0     //RX servo operation timeout C.  2M UI 
-#define     rx_servo_timeout_sel_C_4Mui                       0x00E0     //RX servo operation timeout C.  4M UI
-#define     rx_servo_timeout_sel_C_Infinite                   0x00F0     //RX servo operation timeout C.  Infinite
-#define     rx_servo_timeout_sel_C_clear                      0x0F0F     // Clear mask
-#define     rx_servo_timeout_sel_D_512ui                      0x0001     //RX servo operation timeout D.  512 UI 
-#define     rx_servo_timeout_sel_D_1Kui                       0x0002     //RX servo operation timeout D.  1K UI 
-#define     rx_servo_timeout_sel_D_2Kui                       0x0003     //RX servo operation timeout D.  2K UI 
-#define     rx_servo_timeout_sel_D_4Kui                       0x0004     //RX servo operation timeout D.  4096 UI 
-#define     rx_servo_timeout_sel_D_8Kui                       0x0005     //RX servo operation timeout D.  8K UI 
-#define     rx_servo_timeout_sel_D_16Kui                      0x0006     //RX servo operation timeout D.  16K UI 
-#define     rx_servo_timeout_sel_D_32Kui                      0x0007     //RX servo operation timeout D.  32K UI 
-#define     rx_servo_timeout_sel_D_64Kui                      0x0008     //RX servo operation timeout D.  64K UI 
-#define     rx_servo_timeout_sel_D_128Kui                     0x0009     //RX servo operation timeout D.  128K UI 
-#define     rx_servo_timeout_sel_D_256Kui                     0x000A     //RX servo operation timeout D.  256K UI 
-#define     rx_servo_timeout_sel_D_512Kui                     0x000B     //RX servo operation timeout D.  512K UI 
-#define     rx_servo_timeout_sel_D_1Mui                       0x000C     //RX servo operation timeout D.  1M UI 
-#define     rx_servo_timeout_sel_D_2Mui                       0x000D     //RX servo operation timeout D.  2M UI 
-#define     rx_servo_timeout_sel_D_4Mui                       0x000E     //RX servo operation timeout D.  4M UI
-#define     rx_servo_timeout_sel_D_Infinite                   0x000F     //RX servo operation timeout D.  Infinite
-#define     rx_servo_timeout_sel_D_clear                      0xFF00     // Clear mask
-
-// rx_servo_to2_pp Register field name                                  data value   Description
-#define     rx_servo_timeout_sel_E_512ui                      0x1000     //RX servo operation timeout E.  512 UI 
-#define     rx_servo_timeout_sel_E_1Kui                       0x2000     //RX servo operation timeout E.  1K UI 
-#define     rx_servo_timeout_sel_E_2Kui                       0x3000     //RX servo operation timeout E.  2K UI 
-#define     rx_servo_timeout_sel_E_4Kui                       0x4000     //RX servo operation timeout E.  4096 UI 
-#define     rx_servo_timeout_sel_E_8Kui                       0x5000     //RX servo operation timeout E.  8K UI 
-#define     rx_servo_timeout_sel_E_16Kui                      0x6000     //RX servo operation timeout E.  16K UI 
-#define     rx_servo_timeout_sel_E_32Kui                      0x7000     //RX servo operation timeout E.  32K UI 
-#define     rx_servo_timeout_sel_E_64Kui                      0x8000     //RX servo operation timeout E.  64K UI 
-#define     rx_servo_timeout_sel_E_128Kui                     0x9000     //RX servo operation timeout E.  128K UI 
-#define     rx_servo_timeout_sel_E_256Kui                     0xA000     //RX servo operation timeout E.  256K UI 
-#define     rx_servo_timeout_sel_E_512Kui                     0xB000     //RX servo operation timeout E.  512K UI 
-#define     rx_servo_timeout_sel_E_1Mui                       0xC000     //RX servo operation timeout E.  1M UI 
-#define     rx_servo_timeout_sel_E_2Mui                       0xD000     //RX servo operation timeout E.  2M UI 
-#define     rx_servo_timeout_sel_E_4Mui                       0xE000     //RX servo operation timeout E.  4M UI
-#define     rx_servo_timeout_sel_E_Infinite                   0xF000     //RX servo operation timeout E.  Infinite
-#define     rx_servo_timeout_sel_E_clear                      0x0FFF     // Clear mask
-#define     rx_servo_timeout_sel_F_512ui                      0x0100     //RX servo operation timeout F.  512 UI 
-#define     rx_servo_timeout_sel_F_1Kui                       0x0200     //RX servo operation timeout F.  1K UI 
-#define     rx_servo_timeout_sel_F_2Kui                       0x0300     //RX servo operation timeout F.  2K UI 
-#define     rx_servo_timeout_sel_F_4Kui                       0x0400     //RX servo operation timeout F.  4096 UI 
-#define     rx_servo_timeout_sel_F_8Kui                       0x0500     //RX servo operation timeout F.  8K UI 
-#define     rx_servo_timeout_sel_F_16Kui                      0x0600     //RX servo operation timeout F.  16K UI 
-#define     rx_servo_timeout_sel_F_32Kui                      0x0700     //RX servo operation timeout F.  32K UI 
-#define     rx_servo_timeout_sel_F_64Kui                      0x0800     //RX servo operation timeout F.  64K UI 
-#define     rx_servo_timeout_sel_F_128Kui                     0x0900     //RX servo operation timeout F.  128K UI 
-#define     rx_servo_timeout_sel_F_256Kui                     0x0A00     //RX servo operation timeout F.  256K UI 
-#define     rx_servo_timeout_sel_F_512Kui                     0x0B00     //RX servo operation timeout F.  512K UI 
-#define     rx_servo_timeout_sel_F_1Mui                       0x0C00     //RX servo operation timeout F.  1M UI 
-#define     rx_servo_timeout_sel_F_2Mui                       0x0D00     //RX servo operation timeout F.  2M UI 
-#define     rx_servo_timeout_sel_F_4Mui                       0x0E00     //RX servo operation timeout F.  4M UI
-#define     rx_servo_timeout_sel_F_Infinite                   0x0F00     //RX servo operation timeout F.  Infinite
-#define     rx_servo_timeout_sel_F_clear                      0xF0FF     // Clear mask
-#define     rx_servo_timeout_sel_G_512ui                      0x0010     //RX servo operation timeout G.  512 UI 
-#define     rx_servo_timeout_sel_G_1Kui                       0x0020     //RX servo operation timeout G.  1K UI 
-#define     rx_servo_timeout_sel_G_2Kui                       0x0030     //RX servo operation timeout G.  2K UI 
-#define     rx_servo_timeout_sel_G_4Kui                       0x0040     //RX servo operation timeout G.  4096 UI 
-#define     rx_servo_timeout_sel_G_8Kui                       0x0050     //RX servo operation timeout G.  8K UI 
-#define     rx_servo_timeout_sel_G_16Kui                      0x0060     //RX servo operation timeout G.  16K UI 
-#define     rx_servo_timeout_sel_G_32Kui                      0x0070     //RX servo operation timeout G.  32K UI 
-#define     rx_servo_timeout_sel_G_64Kui                      0x0080     //RX servo operation timeout G.  64K UI 
-#define     rx_servo_timeout_sel_G_128Kui                     0x0090     //RX servo operation timeout G.  128K UI 
-#define     rx_servo_timeout_sel_G_256Kui                     0x00A0     //RX servo operation timeout G.  256K UI 
-#define     rx_servo_timeout_sel_G_512Kui                     0x00B0     //RX servo operation timeout G.  512K UI 
-#define     rx_servo_timeout_sel_G_1Mui                       0x00C0     //RX servo operation timeout G.  1M UI 
-#define     rx_servo_timeout_sel_G_2Mui                       0x00D0     //RX servo operation timeout G.  2M UI 
-#define     rx_servo_timeout_sel_G_4Mui                       0x00E0     //RX servo operation timeout G.  4M UI
-#define     rx_servo_timeout_sel_G_Infinite                   0x00F0     //RX servo operation timeout G.  Infinite
-#define     rx_servo_timeout_sel_G_clear                      0x0F0F     // Clear mask
-#define     rx_servo_timeout_sel_H_512ui                      0x0001     //RX servo operation timeout H.  512 UI 
-#define     rx_servo_timeout_sel_H_1Kui                       0x0002     //RX servo operation timeout H.  1K UI 
-#define     rx_servo_timeout_sel_H_2Kui                       0x0003     //RX servo operation timeout H.  2K UI 
-#define     rx_servo_timeout_sel_H_4Kui                       0x0004     //RX servo operation timeout H.  4096 UI 
-#define     rx_servo_timeout_sel_H_8Kui                       0x0005     //RX servo operation timeout H.  8K UI 
-#define     rx_servo_timeout_sel_H_16Kui                      0x0006     //RX servo operation timeout H.  16K UI 
-#define     rx_servo_timeout_sel_H_32Kui                      0x0007     //RX servo operation timeout H.  32K UI 
-#define     rx_servo_timeout_sel_H_64Kui                      0x0008     //RX servo operation timeout H.  64K UI 
-#define     rx_servo_timeout_sel_H_128Kui                     0x0009     //RX servo operation timeout H.  128K UI 
-#define     rx_servo_timeout_sel_H_256Kui                     0x000A     //RX servo operation timeout H.  256K UI 
-#define     rx_servo_timeout_sel_H_512Kui                     0x000B     //RX servo operation timeout H.  512K UI 
-#define     rx_servo_timeout_sel_H_1Mui                       0x000C     //RX servo operation timeout H.  1M UI 
-#define     rx_servo_timeout_sel_H_2Mui                       0x000D     //RX servo operation timeout H.  2M UI 
-#define     rx_servo_timeout_sel_H_4Mui                       0x000E     //RX servo operation timeout H.  4M UI
-#define     rx_servo_timeout_sel_H_Infinite                   0x000F     //RX servo operation timeout H.  Infinite
-#define     rx_servo_timeout_sel_H_clear                      0xFF00     // Clear mask
-
-// rx_servo_to3_pp Register field name                                  data value   Description
-#define     rx_servo_timeout_sel_I_512ui                      0x1000     //RX servo operation timeout I.  512 UI 
-#define     rx_servo_timeout_sel_I_1Kui                       0x2000     //RX servo operation timeout I.  1K UI 
-#define     rx_servo_timeout_sel_I_2Kui                       0x3000     //RX servo operation timeout I.  2K UI 
-#define     rx_servo_timeout_sel_I_4Kui                       0x4000     //RX servo operation timeout I.  4096 UI 
-#define     rx_servo_timeout_sel_I_8Kui                       0x5000     //RX servo operation timeout I.  8K UI 
-#define     rx_servo_timeout_sel_I_16Kui                      0x6000     //RX servo operation timeout I.  16K UI 
-#define     rx_servo_timeout_sel_I_32Kui                      0x7000     //RX servo operation timeout I.  32K UI 
-#define     rx_servo_timeout_sel_I_64Kui                      0x8000     //RX servo operation timeout I.  64K UI 
-#define     rx_servo_timeout_sel_I_128Kui                     0x9000     //RX servo operation timeout I.  128K UI 
-#define     rx_servo_timeout_sel_I_256Kui                     0xA000     //RX servo operation timeout I.  256K UI 
-#define     rx_servo_timeout_sel_I_512Kui                     0xB000     //RX servo operation timeout I.  512K UI 
-#define     rx_servo_timeout_sel_I_1Mui                       0xC000     //RX servo operation timeout I.  1M UI 
-#define     rx_servo_timeout_sel_I_2Mui                       0xD000     //RX servo operation timeout I.  2M UI 
-#define     rx_servo_timeout_sel_I_4Mui                       0xE000     //RX servo operation timeout I.  4M UI
-#define     rx_servo_timeout_sel_I_Infinite                   0xF000     //RX servo operation timeout I.  Infinite
-#define     rx_servo_timeout_sel_I_clear                      0x0FFF     // Clear mask
-#define     rx_servo_timeout_sel_J_512ui                      0x0100     //RX servo operation timeout J.  512 UI 
-#define     rx_servo_timeout_sel_J_1Kui                       0x0200     //RX servo operation timeout J.  1K UI 
-#define     rx_servo_timeout_sel_J_2Kui                       0x0300     //RX servo operation timeout J.  2K UI 
-#define     rx_servo_timeout_sel_J_4Kui                       0x0400     //RX servo operation timeout J.  4096 UI 
-#define     rx_servo_timeout_sel_J_8Kui                       0x0500     //RX servo operation timeout J.  8K UI 
-#define     rx_servo_timeout_sel_J_16Kui                      0x0600     //RX servo operation timeout J.  16K UI 
-#define     rx_servo_timeout_sel_J_32Kui                      0x0700     //RX servo operation timeout J.  32K UI 
-#define     rx_servo_timeout_sel_J_64Kui                      0x0800     //RX servo operation timeout J.  64K UI 
-#define     rx_servo_timeout_sel_J_128Kui                     0x0900     //RX servo operation timeout J.  128K UI 
-#define     rx_servo_timeout_sel_J_256Kui                     0x0A00     //RX servo operation timeout J.  256K UI 
-#define     rx_servo_timeout_sel_J_512Kui                     0x0B00     //RX servo operation timeout J.  512K UI 
-#define     rx_servo_timeout_sel_J_1Mui                       0x0C00     //RX servo operation timeout J.  1M UI 
-#define     rx_servo_timeout_sel_J_2Mui                       0x0D00     //RX servo operation timeout J.  2M UI 
-#define     rx_servo_timeout_sel_J_4Mui                       0x0E00     //RX servo operation timeout J.  4M UI
-#define     rx_servo_timeout_sel_J_Infinite                   0x0F00     //RX servo operation timeout J.  Infinite
-#define     rx_servo_timeout_sel_J_clear                      0xF0FF     // Clear mask
-#define     rx_servo_timeout_sel_K_512ui                      0x0010     //RX servo operation timeout K.  512 UI 
-#define     rx_servo_timeout_sel_K_1Kui                       0x0020     //RX servo operation timeout K.  1K UI 
-#define     rx_servo_timeout_sel_K_2Kui                       0x0030     //RX servo operation timeout K.  2K UI 
-#define     rx_servo_timeout_sel_K_4Kui                       0x0040     //RX servo operation timeout K.  4096 UI 
-#define     rx_servo_timeout_sel_K_8Kui                       0x0050     //RX servo operation timeout K.  8K UI 
-#define     rx_servo_timeout_sel_K_16Kui                      0x0060     //RX servo operation timeout K.  16K UI 
-#define     rx_servo_timeout_sel_K_32Kui                      0x0070     //RX servo operation timeout K.  32K UI 
-#define     rx_servo_timeout_sel_K_64Kui                      0x0080     //RX servo operation timeout K.  64K UI 
-#define     rx_servo_timeout_sel_K_128Kui                     0x0090     //RX servo operation timeout K.  128K UI 
-#define     rx_servo_timeout_sel_K_256Kui                     0x00A0     //RX servo operation timeout K.  256K UI 
-#define     rx_servo_timeout_sel_K_512Kui                     0x00B0     //RX servo operation timeout K.  512K UI 
-#define     rx_servo_timeout_sel_K_1Mui                       0x00C0     //RX servo operation timeout K.  1M UI 
-#define     rx_servo_timeout_sel_K_2Mui                       0x00D0     //RX servo operation timeout K.  2M UI 
-#define     rx_servo_timeout_sel_K_4Mui                       0x00E0     //RX servo operation timeout K.  4M UI
-#define     rx_servo_timeout_sel_K_Infinite                   0x00F0     //RX servo operation timeout K.  Infinite
-#define     rx_servo_timeout_sel_K_clear                      0x0F0F     // Clear mask
-#define     rx_servo_timeout_sel_L_512ui                      0x0001     //RX servo operation timeout L.  512 UI 
-#define     rx_servo_timeout_sel_L_1Kui                       0x0002     //RX servo operation timeout L.  1K UI 
-#define     rx_servo_timeout_sel_L_2Kui                       0x0003     //RX servo operation timeout L.  2K UI 
-#define     rx_servo_timeout_sel_L_4Kui                       0x0004     //RX servo operation timeout L.  4096 UI 
-#define     rx_servo_timeout_sel_L_8Kui                       0x0005     //RX servo operation timeout L.  8K UI 
-#define     rx_servo_timeout_sel_L_16Kui                      0x0006     //RX servo operation timeout L.  16K UI 
-#define     rx_servo_timeout_sel_L_32Kui                      0x0007     //RX servo operation timeout L.  32K UI 
-#define     rx_servo_timeout_sel_L_64Kui                      0x0008     //RX servo operation timeout L.  64K UI 
-#define     rx_servo_timeout_sel_L_128Kui                     0x0009     //RX servo operation timeout L.  128K UI 
-#define     rx_servo_timeout_sel_L_256Kui                     0x000A     //RX servo operation timeout L.  256K UI 
-#define     rx_servo_timeout_sel_L_512Kui                     0x000B     //RX servo operation timeout L.  512K UI 
-#define     rx_servo_timeout_sel_L_1Mui                       0x000C     //RX servo operation timeout L.  1M UI 
-#define     rx_servo_timeout_sel_L_2Mui                       0x000D     //RX servo operation timeout L.  2M UI 
-#define     rx_servo_timeout_sel_L_4Mui                       0x000E     //RX servo operation timeout L.  4M UI
-#define     rx_servo_timeout_sel_L_Infinite                   0x000F     //RX servo operation timeout L.  Infinite
-#define     rx_servo_timeout_sel_L_clear                      0xFF00     // Clear mask
-
-// rx_dfe_config_pp Register field name                                 data value   Description
-#define     rx_peak_cfg                                       0x0000     //RX DFE Peaking settings
-#define     rx_peak_cfg_clear                                 0x3FFF     // Clear mask
-#define     rx_amin_cfg                                       0x0000     //RX DFE Amin settings
-#define     rx_amin_cfg_clear                                 0xC7FF     // Clear mask
-#define     rx_anap_cfg                                       0x0000     //RX DFE An-Ap settings
-#define     rx_anap_cfg_clear                                 0xF9FF     // Clear mask
-#define     rx_h1_cfg                                         0x0000     //RX DFE H1 settings
-#define     rx_h1_cfg_clear                                   0xFE7F     // Clear mask
-#define     rx_h1ap_cfg                                       0x0000     //RX DFE H1 over Ap settings
-#define     rx_h1ap_cfg_clear                                 0x3F8F     // Clear mask
-#define     rx_dfe_ca_cfg                                     0x0000     //RX DFE clock adjust settings
-#define     rx_dfe_ca_cfg_clear                               0xF8F3     // Clear mask
-#define     rx_spmux_cfg                                      0x0000     //RX DFE speculation mux toggle settings
-#define     rx_spmux_cfg_clear                                0xE3CC     // Clear mask
-
-// rx_dfe_timers_pp Register field name                                 data value   Description
-#define     rx_init_tmr_cfg                                   0x0000     //RX clock init timer settings
-#define     rx_init_tmr_cfg_clear                             0x1FFF     // Clear mask
-#define     rx_ber_cfg                                        0x0000     //RX DDC Bit error rate timer settings
-#define     rx_ber_cfg_clear                                  0xE3FF     // Clear mask
-#define     rx_fifo_dly_cfg                                   0x0000     //RX Fifo Delay Blackout settings
-#define     rx_fifo_dly_cfg_clear                             0xFCFF     // Clear mask
-#define     rx_ddc_cfg                                        0x0000     //RX DDC config settings
-#define     rx_ddc_cfg_clear                                  0xFF3F     // Clear mask
-#define     rx_dac_bo_cfg                                     0x0000     //RX DAC black out period settings
-#define     rx_dac_bo_cfg_clear                               0xCFC7     // Clear mask
-#define     rx_prot_cfg                                       0x0000     //RX phase rotator filter settings
-#define     rx_prot_cfg_clear                                 0x7E39     // Clear mask
-
-// rx_reset_cfg_pp Register field name                                  data value   Description
-#define     rx_reset_cfg_hld_clear                            0x0000     // Clear mask
-
-// rx_recal_to1_pp Register field name                                  data value   Description
-#define     rx_recal_timeout_sel_A_512ui                      0x1000     //RX recal servo operation timeout A.  512 UI 
-#define     rx_recal_timeout_sel_A_1Kui                       0x2000     //RX recal servo operation timeout A.  1K UI 
-#define     rx_recal_timeout_sel_A_2Kui                       0x3000     //RX recal servo operation timeout A.  2K UI 
-#define     rx_recal_timeout_sel_A_4Kui                       0x4000     //RX recal servo operation timeout A.  4096 UI 
-#define     rx_recal_timeout_sel_A_8Kui                       0x5000     //RX recal servo operation timeout A.  8K UI 
-#define     rx_recal_timeout_sel_A_16Kui                      0x6000     //RX recal servo operation timeout A.  16K UI 
-#define     rx_recal_timeout_sel_A_32Kui                      0x7000     //RX recal servo operation timeout A.  32K UI 
-#define     rx_recal_timeout_sel_A_64Kui                      0x8000     //RX recal servo operation timeout A.  64K UI 
-#define     rx_recal_timeout_sel_A_128Kui                     0x9000     //RX recal servo operation timeout A.  128K UI 
-#define     rx_recal_timeout_sel_A_256Kui                     0xA000     //RX recal servo operation timeout A.  256K UI 
-#define     rx_recal_timeout_sel_A_512Kui                     0xB000     //RX recal servo operation timeout A.  512K UI 
-#define     rx_recal_timeout_sel_A_1Mui                       0xC000     //RX recal servo operation timeout A.  1M UI 
-#define     rx_recal_timeout_sel_A_2Mui                       0xD000     //RX recal servo operation timeout A.  2M UI 
-#define     rx_recal_timeout_sel_A_4Mui                       0xE000     //RX recal servo operation timeout A.  4M UI
-#define     rx_recal_timeout_sel_A_Infinite                   0xF000     //RX recal servo operation timeout A.  Infinite
-#define     rx_recal_timeout_sel_A_clear                      0x0FFF     // Clear mask
-#define     rx_recal_timeout_sel_B_512ui                      0x0100     //RX recal servo operation timeout B.  512 UI 
-#define     rx_recal_timeout_sel_B_1Kui                       0x0200     //RX recal servo operation timeout B.  1K UI 
-#define     rx_recal_timeout_sel_B_2Kui                       0x0300     //RX recal servo operation timeout B.  2K UI 
-#define     rx_recal_timeout_sel_B_4Kui                       0x0400     //RX recal servo operation timeout B.  4096 UI 
-#define     rx_recal_timeout_sel_B_8Kui                       0x0500     //RX recal servo operation timeout B.  8K UI 
-#define     rx_recal_timeout_sel_B_16Kui                      0x0600     //RX recal servo operation timeout B.  16K UI 
-#define     rx_recal_timeout_sel_B_32Kui                      0x0700     //RX recal servo operation timeout B.  32K UI 
-#define     rx_recal_timeout_sel_B_64Kui                      0x0800     //RX recal servo operation timeout B.  64K UI 
-#define     rx_recal_timeout_sel_B_128Kui                     0x0900     //RX recal servo operation timeout B.  128K UI 
-#define     rx_recal_timeout_sel_B_256Kui                     0x0A00     //RX recal servo operation timeout B.  256K UI 
-#define     rx_recal_timeout_sel_B_512Kui                     0x0B00     //RX recal servo operation timeout B.  512K UI 
-#define     rx_recal_timeout_sel_B_1Mui                       0x0C00     //RX recal servo operation timeout B.  1M UI 
-#define     rx_recal_timeout_sel_B_2Mui                       0x0D00     //RX recal servo operation timeout B.  2M UI 
-#define     rx_recal_timeout_sel_B_4Mui                       0x0E00     //RX recal servo operation timeout B.  4M UI
-#define     rx_recal_timeout_sel_B_Infinite                   0x0F00     //RX recal servo operation timeout B.  Infinite
-#define     rx_recal_timeout_sel_B_clear                      0xF0FF     // Clear mask
-
-// rx_recal_to2_pp Register field name                                  data value   Description
-#define     rx_recal_timeout_sel_G_512ui                      0x0010     //RX recal servo operation timeout G.  512 UI 
-#define     rx_recal_timeout_sel_G_1Kui                       0x0020     //RX recal servo operation timeout G.  1K UI 
-#define     rx_recal_timeout_sel_G_2Kui                       0x0030     //RX recal servo operation timeout G.  2K UI 
-#define     rx_recal_timeout_sel_G_4Kui                       0x0040     //RX recal servo operation timeout G.  4096 UI 
-#define     rx_recal_timeout_sel_G_8Kui                       0x0050     //RX recal servo operation timeout G.  8K UI 
-#define     rx_recal_timeout_sel_G_16Kui                      0x0060     //RX recal servo operation timeout G.  16K UI 
-#define     rx_recal_timeout_sel_G_32Kui                      0x0070     //RX recal servo operation timeout G.  32K UI 
-#define     rx_recal_timeout_sel_G_64Kui                      0x0080     //RX recal servo operation timeout G.  64K UI 
-#define     rx_recal_timeout_sel_G_128Kui                     0x0090     //RX recal servo operation timeout G.  128K UI 
-#define     rx_recal_timeout_sel_G_256Kui                     0x00A0     //RX recal servo operation timeout G.  256K UI 
-#define     rx_recal_timeout_sel_G_512Kui                     0x00B0     //RX recal servo operation timeout G.  512K UI 
-#define     rx_recal_timeout_sel_G_1Mui                       0x00C0     //RX recal servo operation timeout G.  1M UI 
-#define     rx_recal_timeout_sel_G_2Mui                       0x00D0     //RX recal servo operation timeout G.  2M UI 
-#define     rx_recal_timeout_sel_G_4Mui                       0x00E0     //RX recal servo operation timeout G.  4M UI
-#define     rx_recal_timeout_sel_G_Infinite                   0x00F0     //RX recal servo operation timeout G.  Infinite
-#define     rx_recal_timeout_sel_G_clear                      0x0F0F     // Clear mask
-#define     rx_recal_timeout_sel_H_512ui                      0x0001     //RX recal servo operation timeout H.  512 UI 
-#define     rx_recal_timeout_sel_H_1Kui                       0x0002     //RX recal servo operation timeout H.  1K UI 
-#define     rx_recal_timeout_sel_H_2Kui                       0x0003     //RX recal servo operation timeout H.  2K UI 
-#define     rx_recal_timeout_sel_H_4Kui                       0x0004     //RX recal servo operation timeout H.  4096 UI 
-#define     rx_recal_timeout_sel_H_8Kui                       0x0005     //RX recal servo operation timeout H.  8K UI 
-#define     rx_recal_timeout_sel_H_16Kui                      0x0006     //RX recal servo operation timeout H.  16K UI 
-#define     rx_recal_timeout_sel_H_32Kui                      0x0007     //RX recal servo operation timeout H.  32K UI 
-#define     rx_recal_timeout_sel_H_64Kui                      0x0008     //RX recal servo operation timeout H.  64K UI 
-#define     rx_recal_timeout_sel_H_128Kui                     0x0009     //RX recal servo operation timeout H.  128K UI 
-#define     rx_recal_timeout_sel_H_256Kui                     0x000A     //RX recal servo operation timeout H.  256K UI 
-#define     rx_recal_timeout_sel_H_512Kui                     0x000B     //RX recal servo operation timeout H.  512K UI 
-#define     rx_recal_timeout_sel_H_1Mui                       0x000C     //RX recal servo operation timeout H.  1M UI 
-#define     rx_recal_timeout_sel_H_2Mui                       0x000D     //RX recal servo operation timeout H.  2M UI 
-#define     rx_recal_timeout_sel_H_4Mui                       0x000E     //RX recal servo operation timeout H.  4M UI
-#define     rx_recal_timeout_sel_H_Infinite                   0x000F     //RX recal servo operation timeout H.  Infinite
-#define     rx_recal_timeout_sel_H_clear                      0xFF00     // Clear mask
-
-// rx_recal_to3_pp Register field name                                  data value   Description
-#define     rx_recal_timeout_sel_I_512ui                      0x1000     //RX recal servo operation timeout I.  512 UI 
-#define     rx_recal_timeout_sel_I_1Kui                       0x2000     //RX recal servo operation timeout I.  1K UI 
-#define     rx_recal_timeout_sel_I_2Kui                       0x3000     //RX recal servo operation timeout I.  2K UI 
-#define     rx_recal_timeout_sel_I_4Kui                       0x4000     //RX recal servo operation timeout I.  4096 UI 
-#define     rx_recal_timeout_sel_I_8Kui                       0x5000     //RX recal servo operation timeout I.  8K UI 
-#define     rx_recal_timeout_sel_I_16Kui                      0x6000     //RX recal servo operation timeout I.  16K UI 
-#define     rx_recal_timeout_sel_I_32Kui                      0x7000     //RX recal servo operation timeout I.  32K UI 
-#define     rx_recal_timeout_sel_I_64Kui                      0x8000     //RX recal servo operation timeout I.  64K UI 
-#define     rx_recal_timeout_sel_I_128Kui                     0x9000     //RX recal servo operation timeout I.  128K UI 
-#define     rx_recal_timeout_sel_I_256Kui                     0xA000     //RX recal servo operation timeout I.  256K UI 
-#define     rx_recal_timeout_sel_I_512Kui                     0xB000     //RX recal servo operation timeout I.  512K UI 
-#define     rx_recal_timeout_sel_I_1Mui                       0xC000     //RX recal servo operation timeout I.  1M UI 
-#define     rx_recal_timeout_sel_I_2Mui                       0xD000     //RX recal servo operation timeout I.  2M UI 
-#define     rx_recal_timeout_sel_I_4Mui                       0xE000     //RX recal servo operation timeout I.  4M UI
-#define     rx_recal_timeout_sel_I_Infinite                   0xF000     //RX recal servo operation timeout I.  Infinite
-#define     rx_recal_timeout_sel_I_clear                      0x0FFF     // Clear mask
-#define     rx_recal_timeout_sel_J_512ui                      0x0100     //RX recal servo operation timeout J.  512 UI 
-#define     rx_recal_timeout_sel_J_1Kui                       0x0200     //RX recal servo operation timeout J.  1K UI 
-#define     rx_recal_timeout_sel_J_2Kui                       0x0300     //RX recal servo operation timeout J.  2K UI 
-#define     rx_recal_timeout_sel_J_4Kui                       0x0400     //RX recal servo operation timeout J.  4096 UI 
-#define     rx_recal_timeout_sel_J_8Kui                       0x0500     //RX recal servo operation timeout J.  8K UI 
-#define     rx_recal_timeout_sel_J_16Kui                      0x0600     //RX recal servo operation timeout J.  16K UI 
-#define     rx_recal_timeout_sel_J_32Kui                      0x0700     //RX recal servo operation timeout J.  32K UI 
-#define     rx_recal_timeout_sel_J_64Kui                      0x0800     //RX recal servo operation timeout J.  64K UI 
-#define     rx_recal_timeout_sel_J_128Kui                     0x0900     //RX recal servo operation timeout J.  128K UI 
-#define     rx_recal_timeout_sel_J_256Kui                     0x0A00     //RX recal servo operation timeout J.  256K UI 
-#define     rx_recal_timeout_sel_J_512Kui                     0x0B00     //RX recal servo operation timeout J.  512K UI 
-#define     rx_recal_timeout_sel_J_1Mui                       0x0C00     //RX recal servo operation timeout J.  1M UI 
-#define     rx_recal_timeout_sel_J_2Mui                       0x0D00     //RX recal servo operation timeout J.  2M UI 
-#define     rx_recal_timeout_sel_J_4Mui                       0x0E00     //RX recal servo operation timeout J.  4M UI
-#define     rx_recal_timeout_sel_J_Infinite                   0x0F00     //RX recal servo operation timeout J.  Infinite
-#define     rx_recal_timeout_sel_J_clear                      0xF0FF     // Clear mask
-#define     rx_recal_timeout_sel_K_512ui                      0x0010     //RX recal servo operation timeout K.  512 UI 
-#define     rx_recal_timeout_sel_K_1Kui                       0x0020     //RX recal servo operation timeout K.  1K UI 
-#define     rx_recal_timeout_sel_K_2Kui                       0x0030     //RX recal servo operation timeout K.  2K UI 
-#define     rx_recal_timeout_sel_K_4Kui                       0x0040     //RX recal servo operation timeout K.  4096 UI 
-#define     rx_recal_timeout_sel_K_8Kui                       0x0050     //RX recal servo operation timeout K.  8K UI 
-#define     rx_recal_timeout_sel_K_16Kui                      0x0060     //RX recal servo operation timeout K.  16K UI 
-#define     rx_recal_timeout_sel_K_32Kui                      0x0070     //RX recal servo operation timeout K.  32K UI 
-#define     rx_recal_timeout_sel_K_64Kui                      0x0080     //RX recal servo operation timeout K.  64K UI 
-#define     rx_recal_timeout_sel_K_128Kui                     0x0090     //RX recal servo operation timeout K.  128K UI 
-#define     rx_recal_timeout_sel_K_256Kui                     0x00A0     //RX recal servo operation timeout K.  256K UI 
-#define     rx_recal_timeout_sel_K_512Kui                     0x00B0     //RX recal servo operation timeout K.  512K UI 
-#define     rx_recal_timeout_sel_K_1Mui                       0x00C0     //RX recal servo operation timeout K.  1M UI 
-#define     rx_recal_timeout_sel_K_2Mui                       0x00D0     //RX recal servo operation timeout K.  2M UI 
-#define     rx_recal_timeout_sel_K_4Mui                       0x00E0     //RX recal servo operation timeout K.  4M UI
-#define     rx_recal_timeout_sel_K_Infinite                   0x00F0     //RX recal servo operation timeout K.  Infinite
-#define     rx_recal_timeout_sel_K_clear                      0x0F0F     // Clear mask
-#define     rx_recal_timeout_sel_L_512ui                      0x0001     //RX recal servo operation timeout L.  512 UI 
-#define     rx_recal_timeout_sel_L_1Kui                       0x0002     //RX recal servo operation timeout L.  1K UI 
-#define     rx_recal_timeout_sel_L_2Kui                       0x0003     //RX recal servo operation timeout L.  2K UI 
-#define     rx_recal_timeout_sel_L_4Kui                       0x0004     //RX recal servo operation timeout L.  4096 UI 
-#define     rx_recal_timeout_sel_L_8Kui                       0x0005     //RX recal servo operation timeout L.  8K UI 
-#define     rx_recal_timeout_sel_L_16Kui                      0x0006     //RX recal servo operation timeout L.  16K UI 
-#define     rx_recal_timeout_sel_L_32Kui                      0x0007     //RX recal servo operation timeout L.  32K UI 
-#define     rx_recal_timeout_sel_L_64Kui                      0x0008     //RX recal servo operation timeout L.  64K UI 
-#define     rx_recal_timeout_sel_L_128Kui                     0x0009     //RX recal servo operation timeout L.  128K UI 
-#define     rx_recal_timeout_sel_L_256Kui                     0x000A     //RX recal servo operation timeout L.  256K UI 
-#define     rx_recal_timeout_sel_L_512Kui                     0x000B     //RX recal servo operation timeout L.  512K UI 
-#define     rx_recal_timeout_sel_L_1Mui                       0x000C     //RX recal servo operation timeout L.  1M UI 
-#define     rx_recal_timeout_sel_L_2Mui                       0x000D     //RX recal servo operation timeout L.  2M UI 
-#define     rx_recal_timeout_sel_L_4Mui                       0x000E     //RX recal servo operation timeout L.  4M UI
-#define     rx_recal_timeout_sel_L_Infinite                   0x000F     //RX recal servo operation timeout L.  Infinite
-#define     rx_recal_timeout_sel_L_clear                      0xFF00     // Clear mask
-
-// rx_recal_cntl_pp Register field name                                 data value   Description
-#define     rx_recal_in_progress                              0x8000     //Selects which servo timeouts are used. 
-#define     rx_recal_in_progress_clear                        0x7FFF     // Clear mask
-
-// rx_trace_pp Register field name                                      data value   Description
-#define     rx_pp_trc_mode_tap1                               0x2000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_tap2                               0x4000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_tap3                               0x6000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_tap4                               0x8000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_tap5                               0xA000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_tap6                               0xC000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_tap7                               0xE000     //Per Pack RX Trace Mode  TBD
-#define     rx_pp_trc_mode_clear                              0x1FFF     // Clear mask
-
-// rx_bist_gcrmsg_pp Register field name                                data value   Description
-#define     rx_bist_en                                        0x8000     //TBD
-#define     rx_bist_en_clear                                  0x7FFF     // Clear mask
-
-// rx_scope_cntl_pp Register field name                                 data value   Description
-#define     rx_scope_control                                  0x0000     //Bit 0 odd/even (1 is odd) Bit 1 speculation latch 0=0 1=1.
-#define     rx_scope_control_clear                            0x3FFF     // Clear mask
-#define     rx_bump_scope                                     0x2000     //This is a write only pulse which must stay on for 1 slow cycle. When pulsed it will bump the scope sync counter one notch.
-#define     rx_bump_scope_clear                               0xDFFF     // Clear mask
-
-// rx_fir_reset_pb Register field name                                  data value   Description
-#define     rx_pb_clr_par_errs                                0x0002     //Clear All RX Parity Error Latches
-#define     rx_pb_clr_par_errs_clear                          0xFFFD     // Clear mask
-#define     rx_pb_fir_reset                                   0x0001     //FIR Reset
-#define     rx_pb_fir_reset_clear                             0xFFFE     // Clear mask
-
-// rx_fir_pb Register field name                                        data value   Description
-#define     rx_pb_fir_errs_err_busctl_gcrs_ld_sm              0x0400     //A Per-Bus BUSCTL Register or State Machine Parity Error has occurred.  BUSCTL GCR Load SM Parity Error.
-#define     rx_pb_fir_errs_clear                              0x003F     // Clear mask
-
-// rx_fir_mask_pb Register field name                                   data value   Description
-#define     rx_pb_fir_errs_mask_err_busctl_gcrs_ld_sm         0x0400     //FIR mask for register or state machine parity checkers in per-bus BUSCTL logic. A value of 1 masks the error from generating a FIR error.  BUSCTL GCR Load SM Parity Error.
-#define     rx_pb_fir_errs_mask_clear                         0x003F     // Clear mask
-
-// rx_fir_error_inject_pb Register field name                           data value   Description
-#define     rx_pb_fir_errs_inj_1                              0x4000     //RX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     rx_pb_fir_errs_inj_err_inj_busctl_gcrs_ld_sm      0x0400     //RX Per-Group Parity Error Injection  BUSCTL GCR Load SM Parity Error Inject.
-#define     rx_pb_fir_errs_inj_clear                          0x003F     // Clear mask
-
-
-
-// ei4_tx_mode_pl Register field name                                       data value   Description
-#define     ei4_tx_lane_pdwn                                      0x8000     //Used to drive inhibit (tristate) and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (ei4_tx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance.  Also note that per-group registers ei4_tx_lane_disabled_vec_0_15 and ei4_tx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. 
-#define     ei4_tx_lane_pdwn_clear                                0x7FFF     // Clear mask
-#define     ei4_tx_lane_invert                                    0x4000     //Used to invert the polarity of a lane.
-#define     ei4_tx_lane_invert_clear                              0xBFFF     // Clear mask
-#define     ei4_tx_lane_quiesce_quiesce_to_0                      0x1000     //Used to force the output of a lane to a particular value.  Quiesce Lane to a Static 0 value
-#define     ei4_tx_lane_quiesce_quiesce_to_1                      0x2000     //Used to force the output of a lane to a particular value.  Quiesce Lane to a Static 1 value
-#define     ei4_tx_lane_quiesce_quiesce_to_z                      0x3000     //Used to force the output of a lane to a particular value.  Tri-State Lane Output
-#define     ei4_tx_lane_quiesce_clear                             0xCFFF     // Clear mask
-#define     ei4_tx_lane_scramble_disable                          0x0200     //Used to disable the TX scrambler on a specific lane or all lanes by using a per-lane/per-group global write.
-#define     ei4_tx_lane_scramble_disable_clear                    0xFDFF     // Clear mask
-
-// ei4_tx_cntl_stat_pl Register field name                                  data value   Description
-#define     ei4_tx_fifo_err                                       0x8000     //Indicates an error condition in the TX FIFO.
-#define     ei4_tx_fifo_err_clear                                 0x7FFF     // Clear mask
-
-// ei4_tx_spare_mode_pl Register field name                                 data value   Description
-#define     ei4_tx_pl_spare_mode_0                                0x8000     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     ei4_tx_pl_spare_mode_1                                0x4000     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     ei4_tx_pl_spare_mode_2                                0x2000     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     ei4_tx_pl_spare_mode_3                                0x1000     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     ei4_tx_pl_spare_mode_4                                0x0800     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     ei4_tx_pl_spare_mode_5                                0x0400     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     ei4_tx_pl_spare_mode_6                                0x0200     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     ei4_tx_pl_spare_mode_7                                0x0100     //Per-lane spare mode latch
-#define     ei4_tx_pl_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// ei4_tx_bist_stat_pl Register field name                                  data value   Description
-#define     ei4_tx_lane_bist_err                                  0x8000     //Indicates a TXBIST error occurred.
-#define     ei4_tx_lane_bist_err_clear                            0x7FFF     // Clear mask
-#define     ei4_tx_lane_bist_done                                 0x4000     //Indicates TXBIST has completed. 
-#define     ei4_tx_lane_bist_done_clear                           0xBFFF     // Clear mask
-
-// ei4_tx_prbs_mode_pl Register field name                                  data value   Description
-#define     ei4_tx_prbs_tap_id_pattern_b                          0x2000     //TX Per-Lane PRBS Tap Selector  PRBS tap point B
-#define     ei4_tx_prbs_tap_id_pattern_c                          0x4000     //TX Per-Lane PRBS Tap Selector  PRBS tap point C
-#define     ei4_tx_prbs_tap_id_pattern_d                          0x6000     //TX Per-Lane PRBS Tap Selector  PRBS tap point D
-#define     ei4_tx_prbs_tap_id_pattern_e                          0x8000     //TX Per-Lane PRBS Tap Selector  PRBS tap point E
-#define     ei4_tx_prbs_tap_id_pattern_f                          0xA000     //TX Per-Lane PRBS Tap Selector  PRBS tap point F
-#define     ei4_tx_prbs_tap_id_pattern_g                          0xC000     //TX Per-Lane PRBS Tap Selector  PRBS tap point G
-#define     ei4_tx_prbs_tap_id_pattern_h                          0xE000     //TX Per-Lane PRBS Tap Selector  PRBS tap point H
-#define     ei4_tx_prbs_tap_id_clear                              0x1FFF     // Clear mask
-
-// ei4_tx_data_cntl_gcrmsg_pl Register field name                           data value   Description
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_wt                 0x1000     //GCR Message: TX Per Data Lane Drive Patterns  Drive Wiretest Pattern
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_1s                 0x2000     //GCR Message: TX Per Data Lane Drive Patterns  Drive All 1s Pattern
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_simple_A           0x3000     //GCR Message: TX Per Data Lane Drive Patterns  Drive Simple Pattern A
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_simple_B           0x4000     //GCR Message: TX Per Data Lane Drive Patterns  Drive Simple Pattern B
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_full_prbs23        0x5000     //GCR Message: TX Per Data Lane Drive Patterns  PRBS-23 Full Speed Scramble Pattern A thru H
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_red_prbs23         0x6000     //GCR Message: TX Per Data Lane Drive Patterns  PRBS-23 Reduced Density Scramble Pattern A thru H
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_9th_prbs23         0x7000     //GCR Message: TX Per Data Lane Drive Patterns  PRBS-23 9th pattern
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_ei3_iap            0x8000     //GCR Message: TX Per Data Lane Drive Patterns  EI-3 Busy IAP Pattern (EI4 only
-#define     ei4_tx_drv_data_pattern_gcrmsg_drv_ei3_prbs12         0x9000     //GCR Message: TX Per Data Lane Drive Patterns  Drive EI-3 PRBS-12 Shifted RDT Pattern (EI4 only
-#define     ei4_tx_drv_data_pattern_gcrmsg_TDR_square_wave        0xA000     //GCR Message: TX Per Data Lane Drive Patterns  Drives TDR Pulse-Square waves
-#define     ei4_tx_drv_data_pattern_gcrmsg_k28_5                  0xB000     //GCR Message: TX Per Data Lane Drive Patterns  Drives 20-bit K28.5 pattern - padded to 32 bits
-#define     ei4_tx_drv_data_pattern_gcrmsg_unused_A               0xC000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     ei4_tx_drv_data_pattern_gcrmsg_unused_B               0xD000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     ei4_tx_drv_data_pattern_gcrmsg_unused_C               0xE000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     ei4_tx_drv_data_pattern_gcrmsg_unused_D               0xF000     //GCR Message: TX Per Data Lane Drive Patterns  Unused
-#define     ei4_tx_drv_data_pattern_gcrmsg_clear                  0x0FFF     // Clear mask
-#define     ei4_tx_drv_func_data_gcrmsg                           0x0800     //GCR Message: Functional Data
-#define     ei4_tx_drv_func_data_gcrmsg_clear                     0xF7FF     // Clear mask
-#define     ei4_tx_sls_lane_sel_gcrmsg                            0x0400     //GCR Message: SLS Commands & Recalibration
-#define     ei4_tx_sls_lane_sel_gcrmsg_clear                      0xFBFF     // Clear mask
-
-// ei4_tx_sync_pattern_gcrmsg_pl Register field name                        data value   Description
-#define     ei4_tx_drv_sync_patt_gcrmsg                           0x4000     //Sync Pattern
-#define     ei4_tx_drv_sync_patt_gcrmsg_clear                     0xBFFF     // Clear mask
-
-// ei4_tx_fir_pl Register field name                                        data value   Description
-#define     ei4_tx_pl_fir_errs                                    0x8000     //A 1 in this field indicates that a register or state machine parity error has occurred in per-lane logic.
-#define     ei4_tx_pl_fir_errs_clear                              0x7FFF     // Clear mask
-
-// ei4_tx_fir_mask_pl Register field name                                   data value   Description
-#define     ei4_tx_pl_fir_errs_mask                               0x8000     //FIR mask for all per-lane register or per-lane state machine parity errors.
-#define     ei4_tx_pl_fir_errs_mask_clear                         0x7FFF     // Clear mask
-
-// ei4_tx_fir_error_inject_pl Register field name                           data value   Description
-#define     ei4_tx_pl_fir_err_inj                                 0x8000     //TX Per-Lane Parity Error Injection
-#define     ei4_tx_pl_fir_err_inj_clear                           0x7FFF     // Clear mask
-
-// ei4_tx_mode_fast_pl Register field name                                  data value   Description
-#define     ei4_tx_err_inject                                     0x0000     //Software-only controlled register to inject one or more errors for one deserialized clock pulse on one or more specified beats on this lane.  Set bit position X to inject on beat X of a cycle.  Bits 0:3 are used in EDI and 0:1 are used in EI4. 
-#define     ei4_tx_err_inject_clear                               0x0FFF     // Clear mask
-#define     ei4_tx_err_inj_A_enable                               0x0800     //Control to enable the random bit error injection pattern A for this lane.(default)
-#define     ei4_tx_err_inj_A_enable_clear                         0xF7FF     // Clear mask
-#define     ei4_tx_err_inj_B_enable                               0x0400     //Control to enable the random bit error injection pattern B for this lane.(default)
-#define     ei4_tx_err_inj_B_enable_clear                         0xFBFF     // Clear mask
-
-// ei4_tx_clk_mode_pg Register field name                                   data value   Description
-#define     ei4_tx_clk_pdwn                                       0x8000     //Used to disable the TX clock and put it into a low power state.
-#define     ei4_tx_clk_pdwn_clear                                 0x7FFF     // Clear mask
-#define     ei4_tx_clk_invert                                     0x4000     //Used to invert the polarity of the clock.
-#define     ei4_tx_clk_invert_clear                               0xBFFF     // Clear mask
-#define     ei4_tx_clk_quiesce_p_quiesce_to_0                     0x1000     //Used to force the output of the positive differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 0 value
-#define     ei4_tx_clk_quiesce_p_quiesce_to_1                     0x2000     //Used to force the output of the positive differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 1 value
-#define     ei4_tx_clk_quiesce_p_quiesce_to_z                     0x3000     //Used to force the output of the positive differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Tri-State Clock Lane Output
-#define     ei4_tx_clk_quiesce_p_clear                            0xCFFF     // Clear mask
-#define     ei4_tx_clk_quiesce_n_quiesce_to_0                     0x0400     //Used to force the output of the negative differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 0 value
-#define     ei4_tx_clk_quiesce_n_quiesce_to_1                     0x0800     //Used to force the output of the negative differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Quiesce Clock Lane to a Static 1 value
-#define     ei4_tx_clk_quiesce_n_quiesce_to_z                     0x0C00     //Used to force the output of the negative differential leg of the clock lane to a particular value.  Note that the 0 and 1 settings for EDI are for lab characterization only, and the circuits are not deemed to have the proper drive strength in those modes to meet production level quality.  Tri-State Clock Lane Output
-#define     ei4_tx_clk_quiesce_n_clear                            0xF3FF     // Clear mask
-
-// ei4_tx_spare_mode_pg Register field name                                 data value   Description
-#define     ei4_tx_pg_spare_mode_0                                0x8000     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     ei4_tx_pg_spare_mode_1                                0x4000     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     ei4_tx_pg_spare_mode_2                                0x2000     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     ei4_tx_pg_spare_mode_3                                0x1000     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     ei4_tx_pg_spare_mode_4                                0x0800     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     ei4_tx_pg_spare_mode_5                                0x0400     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     ei4_tx_pg_spare_mode_6                                0x0200     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     ei4_tx_pg_spare_mode_7                                0x0100     //Per-group spare mode latch
-#define     ei4_tx_pg_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// ei4_tx_cntl_stat_pg Register field name                                  data value   Description
-#define     ei4_tx_fifo_init                                      0x4000     //Used to initialize the TX FIFO and put it into a known reset state. This will cause the load to unload delay of the FIFO to be set to the value in the ei4_tx_FIFO_L2U_DLY field of the ei4_tx_FIFO_Mode register.
-#define     ei4_tx_fifo_init_clear                                0xBFFF     // Clear mask
-
-// ei4_tx_mode_pg Register field name                                       data value   Description
-#define     ei4_tx_max_bad_lanes                                  0x0000     //Static Repair, Dynamic Repair & Recal max number of bad lanes per TX bus (NOTE: should match RX side)
-#define     ei4_tx_max_bad_lanes_clear                            0x07FF     // Clear mask
-#define     ei4_tx_msbswap                                        0x0400     //Used to enable end-for-end or msb swap of TX lanes.  For example, lanes 0 and N-1 swap, lanes 1 and N-2 swap, etc. 
-#define     ei4_tx_msbswap_clear                                  0xFBFF     // Clear mask
-
-// ei4_tx_bus_repair_pg Register field name                                 data value   Description
-#define     ei4_tx_bus_repair_count                               0x0000     //This field is used to TBD.
-#define     ei4_tx_bus_repair_count_clear                         0x3FFF     // Clear mask
-#define     ei4_tx_bus_repair_pos_0                               0x0000     //This field is used to TBD.
-#define     ei4_tx_bus_repair_pos_0_clear                         0xC07F     // Clear mask
-#define     ei4_tx_bus_repair_pos_1                               0x0000     //This field is used to TBD.
-#define     ei4_tx_bus_repair_pos_1_clear                         0x3F80     // Clear mask
-
-// ei4_tx_grp_repair_vec_0_15_pg Register field name                        data value   Description
-#define     ei4_tx_grp_repair_vec_0_15                            0x0000     //This field is used to TBD.
-#define     ei4_tx_grp_repair_vec_0_15_clear                      0x0000     // Clear mask
-
-// ei4_tx_grp_repair_vec_16_31_pg Register field name                       data value   Description
-#define     ei4_tx_grp_repair_vec_16_31                           0x0000     //This field is used to TBD.
-#define     ei4_tx_grp_repair_vec_16_31_clear                     0x0000     // Clear mask
-
-// ei4_tx_reset_act_pg Register field name                                  data value   Description
-#define     ei4_tx_reset_cfg_ena                                  0x8000     //Enable Configurable Group Reset
-#define     ei4_tx_reset_cfg_ena_clear                            0x7FFF     // Clear mask
-#define     ei4_tx_clr_par_errs                                   0x0002     //Clear All TX Parity Error Latches
-#define     ei4_tx_clr_par_errs_clear                             0xFFFD     // Clear mask
-#define     ei4_tx_fir_reset                                      0x0001     //FIR Reset
-#define     ei4_tx_fir_reset_clear                                0xFFFE     // Clear mask
-
-// ei4_tx_bist_stat_pg Register field name                                  data value   Description
-#define     ei4_tx_clk_bist_err                                   0x0000     //TBD
-#define     ei4_tx_clk_bist_err_clear                             0x3FFF     // Clear mask
-#define     ei4_tx_clk_bist_done                                  0x0000     //TBD
-#define     ei4_tx_clk_bist_done_clear                            0xCFFF     // Clear mask
-
-// ei4_tx_fir_pg Register field name                                        data value   Description
-#define     ei4_tx_pg_fir_errs_clear                              0x00FF     // Clear mask
-#define     ei4_tx_pl_fir_err                                     0x0001     //Summary bit indicating a TX per-lane register or state machine parity error has occurred in one or more lanes. The ei4_tx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane.
-#define     ei4_tx_pl_fir_err_clear                               0xFFFE     // Clear mask
-
-// ei4_tx_fir_mask_pg Register field name                                   data value   Description
-#define     ei4_tx_pg_fir_errs_mask_clear                         0x00FF     // Clear mask
-#define     ei4_tx_pl_fir_err_mask                                0x0001     //FIR mask for the summary bit that indicates a per-lane TX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane TX parity errors from causing a FIR error.\pmt
-#define     ei4_tx_pl_fir_err_mask_clear                          0xFFFE     // Clear mask
-
-// ei4_tx_fir_error_inject_pg Register field name                           data value   Description
-#define     ei4_tx_pg_fir_err_inj_inj_par_err                     0x1000     //TX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     ei4_tx_pg_fir_err_inj_clear                           0x00FF     // Clear mask
-
-// ei4_tx_id1_pg Register field name                                        data value   Description
-#define     ei4_tx_bus_id                                         0x0000     //This field is used to programmably set the bus number that a clkgrp belongs to.
-#define     ei4_tx_bus_id_clear                                   0x03FF     // Clear mask
-#define     ei4_tx_group_id                                       0x0000     //This field is used to programmably set the clock group number within a bus.
-#define     ei4_tx_group_id_clear                                 0xFE07     // Clear mask
-
-// ei4_tx_id2_pg Register field name                                        data value   Description
-#define     ei4_tx_last_group_id                                  0x0000     //This field is used to programmably set the last clock group number within a bus.
-#define     ei4_tx_last_group_id_clear                            0x03FF     // Clear mask
-
-// ei4_tx_id3_pg Register field name                                        data value   Description
-#define     ei4_tx_start_lane_id                                  0x0000     //This field is used to programmably set the first lane position in the group but relative to the bus.
-#define     ei4_tx_start_lane_id_clear                            0x80FF     // Clear mask
-#define     ei4_tx_end_lane_id                                    0x0000     //This field is used to programmably set the last lane position in the group but relative to the bus.
-#define     ei4_tx_end_lane_id_clear                              0x7F80     // Clear mask
-
-// ei4_tx_clk_cntl_gcrmsg_pg Register field name                            data value   Description
-#define     ei4_tx_drv_clk_pattern_gcrmsg_drv_wt                  0x4000     //TX Clock Drive Patterns  Drive Wiretest Pattern
-#define     ei4_tx_drv_clk_pattern_gcrmsg_drv_c4                  0x8000     //TX Clock Drive Patterns  Drive Clock Pattern
-#define     ei4_tx_drv_clk_pattern_gcrmsg_unused                  0xC000     //TX Clock Drive Patterns  Unused
-#define     ei4_tx_drv_clk_pattern_gcrmsg_clear                   0x3FFF     // Clear mask
-
-// ei4_tx_bad_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_tx_bad_lane1_gcrmsg                               0x0000     //GCR Message: Encoded bad lane one in relation to the entire TX bus
-#define     ei4_tx_bad_lane1_gcrmsg_clear                         0x01FF     // Clear mask
-#define     ei4_tx_bad_lane2_gcrmsg                               0x0000     //GCR Message: Encoded bad lane two in relation to the entire TX bus
-#define     ei4_tx_bad_lane2_gcrmsg_clear                         0xFE03     // Clear mask
-#define     ei4_tx_bad_lane_code_gcrmsg_bad_ln1_val               0x0001     //GCR Message: TX Bad Lane Code  Bad Lane 1 Valid
-#define     ei4_tx_bad_lane_code_gcrmsg_bad_lns12_val             0x0002     //GCR Message: TX Bad Lane Code  Bad Lanes 1 and 2 Valid
-#define     ei4_tx_bad_lane_code_gcrmsg_3plus_bad_lns             0x0003     //GCR Message: TX Bad Lane Code  3+ bad lanes
-#define     ei4_tx_bad_lane_code_gcrmsg_clear                     0xFFF0     // Clear mask
-
-// ei4_tx_sls_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_tx_sls_lane_gcrmsg                                0x0000     //GCR Message: Encoded SLS lane in relation to the entire TX bus
-#define     ei4_tx_sls_lane_gcrmsg_clear                          0x01FF     // Clear mask
-#define     ei4_tx_sls_lane_val_gcrmsg                            0x0100     //GCR Message: TX SLS Lane Valid
-#define     ei4_tx_sls_lane_val_gcrmsg_clear                      0xFEFF     // Clear mask
-
-// ei4_tx_wt_seg_enable_pg Register field name                              data value   Description
-#define     ei4_tx_wt_en_all_clk_segs_gcrmsg                      0x8000     //TX Clock Wiretest driver segnments enable
-#define     ei4_tx_wt_en_all_clk_segs_gcrmsg_clear                0x7FFF     // Clear mask
-#define     ei4_tx_wt_en_all_data_segs_gcrmsg                     0x4000     //TX Data  Wiretest driver segnments enable
-#define     ei4_tx_wt_en_all_data_segs_gcrmsg_clear               0xBFFF     // Clear mask
-
-// ei4_tx_pc_ffe_pg Register field name                                     data value   Description
-#define     ei4_tx_pc_test_mode                                   0x8000     //Driver Segment Test mode
-#define     ei4_tx_pc_test_mode_clear                             0x7FFF     // Clear mask
-#define     ei4_tx_main_slice_en_enc                              0x0000     //240ohm main slice enable (binary code - 0000 is zero slices and 0110 is maximum slices)
-#define     ei4_tx_main_slice_en_enc_clear                        0xF0FF     // Clear mask
-#define     ei4_tx_pc_slice_en_enc                                0x0000     //240ohm precompensation slice enable (binary code - 0000 is zero slices and 1110 is maximum slices)
-#define     ei4_tx_pc_slice_en_enc_clear                          0x0FF0     // Clear mask
-
-// ei4_tx_misc_analog_pg Register field name                                data value   Description
-#define     ei4_tx_slewctl_slew110ps                              0x4000     //Driver Slew Control (bits 2:3 are reserved)  110ps nominal rate 
-#define     ei4_tx_slewctl_slew140ps                              0x8000     //Driver Slew Control (bits 2:3 are reserved)  140ps nominal rate 
-#define     ei4_tx_slewctl_slew170ps                              0xC000     //Driver Slew Control (bits 2:3 are reserved)  170ps nominal rate 
-#define     ei4_tx_slewctl_clear                                  0x0FFF     // Clear mask
-#define     ei4_tx_pvtnl_enc_2400ohms                             0x0010     //PVT pfet enables for all driver slices  min pvt pfet enabled in parallel 
-#define     ei4_tx_pvtnl_enc_1200ohms                             0x0020     //PVT pfet enables for all driver slices  max pvt pfet enabled in parallel 
-#define     ei4_tx_pvtnl_enc_800ohms                              0x0030     //PVT pfet enables for all driver slices  both pvt pfets enabled in parallel
-#define     ei4_tx_pvtnl_enc_clear                                0xF3CF     // Clear mask
-#define     ei4_tx_pvtpl_enc_2400ohms                             0x0001     //PVT nfet enables for all driver slices  Min pvt nfet enabled in parallel 
-#define     ei4_tx_pvtpl_enc_1200ohms                             0x0002     //PVT nfet enables for all driver slices  Max pvt nfet enabled in parallel 
-#define     ei4_tx_pvtpl_enc_800ohms                              0x0003     //PVT nfet enables for all driver slices  Both pvt nfets enabled in parallel
-#define     ei4_tx_pvtpl_enc_clear                                0xFFF0     // Clear mask
-
-// ei4_tx_lane_disabled_vec_0_15_pg Register field name                     data value   Description
-#define     ei4_tx_lane_disabled_vec_0_15                         0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     ei4_tx_lane_disabled_vec_0_15_clear                   0x0000     // Clear mask
-
-// ei4_tx_lane_disabled_vec_16_31_pg Register field name                    data value   Description
-#define     ei4_tx_lane_disabled_vec_16_31                        0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     ei4_tx_lane_disabled_vec_16_31_clear                  0x0000     // Clear mask
-
-// ei4_tx_sls_lane_mux_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_tx_sls_lane_shdw_gcrmsg                           0x8000     //GCR Message: SLS lane shadowing or unshadowing functional data (used to set up TX mux controls)
-#define     ei4_tx_sls_lane_shdw_gcrmsg_clear                     0x7FFF     // Clear mask
-
-// ei4_tx_dyn_rpr_pg Register field name                                    data value   Description
-#define     ei4_tx_sls_hndshk_state_clear                         0x07FF     // Clear mask
-
-// ei4_tx_slv_mv_sls_ln_req_gcrmsg_pg Register field name                   data value   Description
-#define     ei4_tx_slv_mv_sls_shdw_req_gcrmsg                     0x8000     //GCR Message: Request to TX Slave to Move SLS Lane
-#define     ei4_tx_slv_mv_sls_shdw_req_gcrmsg_clear               0x7FFF     // Clear mask
-#define     ei4_tx_slv_mv_sls_shdw_rpr_req_gcrmsg                 0x4000     //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register
-#define     ei4_tx_slv_mv_sls_shdw_rpr_req_gcrmsg_clear           0xBFFF     // Clear mask
-#define     ei4_tx_slv_mv_sls_unshdw_req_gcrmsg                   0x2000     //GCR Message: Request to TX Slave to Move SLS Lane
-#define     ei4_tx_slv_mv_sls_unshdw_req_gcrmsg_clear             0xDFFF     // Clear mask
-#define     ei4_tx_slv_mv_sls_unshdw_rpr_req_gcrmsg               0x1000     //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register
-#define     ei4_tx_slv_mv_sls_unshdw_rpr_req_gcrmsg_clear         0xEFFF     // Clear mask
-#define     ei4_tx_bus_width                                      0x0000     //GCR Message: TX Bus Width
-#define     ei4_tx_bus_width_clear                                0xF01F     // Clear mask
-#define     ei4_tx_slv_mv_sls_rpr_req_gcrmsg                      0x0010     //GCR Message: Request to TX Slave to Move SLS Lane & Set Bad Lane Register
-#define     ei4_tx_slv_mv_sls_rpr_req_gcrmsg_clear                0xFFEF     // Clear mask
-#define     ei4_tx_sls_lane_sel_lg_gcrmsg                         0x0008     //GCR Message: Sets the ei4_tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios
-#define     ei4_tx_sls_lane_sel_lg_gcrmsg_clear                   0xFFF7     // Clear mask
-#define     ei4_tx_sls_lane_unsel_lg_gcrmsg                       0x0004     //GCR Message: Clears the ei4_tx_sls_lane_sel_gcrmsg for the last good lane per bus during recal bad lane scenarios
-#define     ei4_tx_sls_lane_unsel_lg_gcrmsg_clear                 0xFFFB     // Clear mask
-
-// ei4_tx_rdt_cntl_pg Register field name                                   data value   Description
-#define     ei4_tx_rdt_mode                                       0x8000     //Sets RDT mode
-#define     ei4_tx_rdt_mode_clear                                 0x7FFF     // Clear mask
-#define     ei4_tx_run_rdt                                        0x4000     //Drives RDT pattern
-#define     ei4_tx_run_rdt_clear                                  0xBFFF     // Clear mask
-
-// ei4_rx_dll_cal_cntl_pg Register field name                               data value   Description
-#define     ei4_rx_dll1_cal_good                                  0x8000     //RX DLL 1 Calibration has completed successfully and clock is properly aligned. This remains static (not dynamically updated) unless the initialization process requests either a new calibration or a fine update.
-#define     ei4_rx_dll1_cal_good_clear                            0x7FFF     // Clear mask
-#define     ei4_rx_dll1_cal_error                                 0x4000     //RX DLL 1 Calibration has failed to pass coarse delay or coarse vreg calibration and clock is not aligned.
-#define     ei4_rx_dll1_cal_error_clear                           0xBFFF     // Clear mask
-#define     ei4_rx_dll1_cal_error_fine                            0x2000     //RX DLL 1 Calibration has failed to pass fine vreg calibration on either reset or on update and clock is not aligned.
-#define     ei4_rx_dll1_cal_error_fine_clear                      0xDFFF     // Clear mask
-#define     ei4_rx_dll1_cal_skip_skip_delay                       0x0800     //RX DLL 1 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped.  Skip coarse delay cal only
-#define     ei4_rx_dll1_cal_skip_skip_vreg                        0x1000     //RX DLL 1 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped.  Skip coarse vreg cal only
-#define     ei4_rx_dll1_cal_skip_skip_both                        0x1800     //RX DLL 1 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped.  Skip both coarse vreg and coarse delay cal
-#define     ei4_rx_dll1_cal_skip_clear                            0xE7FF     // Clear mask
-#define     ei4_rx_dll1_coarse_adj_by2                            0x0400     //RX DLL 1 Calibration Coarse Delay Backoff TweakWhen coarse delay is calibrated normally 1 delay step is removed to assist finding the edge for fine delay. This allows for 2 steps adjustment.
-#define     ei4_rx_dll1_coarse_adj_by2_clear                      0xFBFF     // Clear mask
-#define     ei4_rx_dll2_cal_good                                  0x0080     //RX DLL 2 Calibration has completed successfully and clock is properly aligned. This remains static (not dynamically updated) unless the initialization process requests either a new calibration or a fine update.
-#define     ei4_rx_dll2_cal_good_clear                            0xFF7F     // Clear mask
-#define     ei4_rx_dll2_cal_error                                 0x0040     //RX DLL 2 Calibration has failed to pass coarse delay or coarse vreg calibration and clock is not aligned.
-#define     ei4_rx_dll2_cal_error_clear                           0xFFBF     // Clear mask
-#define     ei4_rx_dll2_cal_error_fine                            0x0020     //RX DLL 2 Calibration has failed to pass fine vreg calibration on either reset or on update and clock is not aligned.
-#define     ei4_rx_dll2_cal_error_fine_clear                      0xFFDF     // Clear mask
-#define     ei4_rx_dll2_cal_skip_skip_delay                       0x0008     //RX DLL 2 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped.  Skip coarse delay cal only
-#define     ei4_rx_dll2_cal_skip_skip_vreg                        0x0010     //RX DLL 2 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped.  Skip coarse vreg cal only
-#define     ei4_rx_dll2_cal_skip_skip_both                        0x0018     //RX DLL 2 Calibration Skip StepsIf any steps are skipped respective manual settings must be supplied. Fine cal cannot be skipped.  Skip both coarse vreg and coarse delay cal
-#define     ei4_rx_dll2_cal_skip_clear                            0xFCE7     // Clear mask
-#define     ei4_rx_dll2_coarse_adj_by2                            0x0004     //RX DLL 2 Calibration Coarse Delay Backoff TweakWhen coarse delay is calibrated normally 1 delay step is removed to assist finding the edge for fine delay. This allows for 2 steps adjustment.
-#define     ei4_rx_dll2_coarse_adj_by2_clear                      0xFFFB     // Clear mask
-
-// ei4_rx_dll1_setpoint1_pg Register field name                             data value   Description
-#define     ei4_rx_dll1_coarse_en                                 0x0000     //RX DLL 1 Calibration Result/Setting for Coarse Delay Adjust
-#define     ei4_rx_dll1_coarse_en_clear                           0x03FF     // Clear mask
-#define     ei4_rx_dll1_vreg_dac_coarse                           0x0000     //RX DLL 1 Calibration Result/Setting for Coarse VREG DAC
-#define     ei4_rx_dll1_vreg_dac_coarse_clear                     0xFE03     // Clear mask
-
-// ei4_rx_dll1_setpoint2_pg Register field name                             data value   Description
-#define     ei4_rx_dll1_vreg_dac_lower                            0x0000     //RX DLL 1 Calibration Result/Setting for Fine VREG DAC Lower
-#define     ei4_rx_dll1_vreg_dac_lower_clear                      0x0001     // Clear mask
-
-// ei4_rx_dll1_setpoint3_pg Register field name                             data value   Description
-#define     ei4_rx_dll1_vreg_dac_upper                            0x0000     //RX DLL 1 Calibration Result/Setting for Fine VREG DAC Upper
-#define     ei4_rx_dll1_vreg_dac_upper_clear                      0x0001     // Clear mask
-
-// ei4_rx_dll2_setpoint1_pg Register field name                             data value   Description
-#define     ei4_rx_dll2_coarse_en                                 0x0000     //RX DLL 2 Calibration Result/Setting for Coarse Delay Adjust
-#define     ei4_rx_dll2_coarse_en_clear                           0x03FF     // Clear mask
-#define     ei4_rx_dll2_vreg_dac_coarse                           0x0000     //RX DLL 2 Calibration Result/Setting for Coarse VREG DAC
-#define     ei4_rx_dll2_vreg_dac_coarse_clear                     0xFE03     // Clear mask
-
-// ei4_rx_dll2_setpoint2_pg Register field name                             data value   Description
-#define     ei4_rx_dll2_vreg_dac_lower                            0x0000     //RX DLL 2 Calibration Result/Setting for Fine VREG DAC Lower
-#define     ei4_rx_dll2_vreg_dac_lower_clear                      0x0001     // Clear mask
-
-// ei4_rx_dll2_setpoint3_pg Register field name                             data value   Description
-#define     ei4_rx_dll2_vreg_dac_upper                            0x0000     //RX DLL 2 Calibration Result/Setting for Fine VREG DAC Upper
-#define     ei4_rx_dll2_vreg_dac_upper_clear                      0x0001     // Clear mask
-
-// ei4_rx_dll_filter_mode_pg Register field name                            data value   Description
-#define     ei4_rx_dll_dll_filter_length_two                      0x2000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  2 samples
-#define     ei4_rx_dll_dll_filter_length_four                     0x4000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  4 samples
-#define     ei4_rx_dll_dll_filter_length_eight                    0x6000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  8 samples
-#define     ei4_rx_dll_dll_filter_length_sixteen                  0x8000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  16 samples
-#define     ei4_rx_dll_dll_filter_length_thirtytwo                0xA000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  32 samples
-#define     ei4_rx_dll_dll_filter_length_sixtyfour                0xC000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  64 samples
-#define     ei4_rx_dll_dll_filter_length_one28                    0xE000     //\bRX DLL Phase Detector Digital Filter Select\b. The DLL delay calibration digitally samples a Lead/Lag clock edge detector. This filter specifies the samples to take for different levels of filtering in 8 increments of 2*N. More filtering means longer detect time.  128 samples
-#define     ei4_rx_dll_dll_filter_length_clear                    0x1FFF     // Clear mask
-#define     ei4_rx_dll_dll_lead_lag_separation                    0x0000     //\bRX DLL Phase Detector Hysteresis Select\b. The DLL phase detector filters the clock Lead/Lag indicator. This specifies hysteresis separation between a valid lead and valid lag filter sample count in total number of samples. Do not set this higher than the ei4_rx_dll_dll_filter_length
-#define     ei4_rx_dll_dll_lead_lag_separation_clear              0xF1FF     // Clear mask
-
-// ei4_rx_dll_analog_tweaks_pg Register field name                          data value   Description
-#define     ei4_rx_dll_vreg_con                                   0x8000     //RX DLL Vreg KPrime Voltage Level Adjust.
-#define     ei4_rx_dll_vreg_con_clear                             0x7FFF     // Clear mask
-#define     ei4_rx_dll_vreg_compcon_clear                         0x8FFF     // Clear mask
-#define     ei4_rx_dll_vreg_ref_sel                               0x0000     //RX DLL Vreg Active Voltage Range Adjust. This is primarily for experimentation.000 is default. Others TBD.
-#define     ei4_rx_dll_vreg_ref_sel_clear                         0xF1FF     // Clear mask
-#define     ei4_rx_dll1_vreg_drvcon_clear                         0xFE3F     // Clear mask
-#define     ei4_rx_dll2_vreg_drvcon_clear                         0x8FC7     // Clear mask
-#define     ei4_rx_dll_vreg_dac_pullup                            0x0004     //RX DLL Vreg DAC Pullup Chickenswitchadjust dac range for bad hardware.
-#define     ei4_rx_dll_vreg_dac_pullup_clear                      0xFFFB     // Clear mask
-
-// ei4_tx_wiretest_pp Register field name                                   data value   Description
-#define     ei4_tx_wt_pattern_length_256                          0x4000     //TX Wiretest Pattern Length  256
-#define     ei4_tx_wt_pattern_length_512                          0x8000     //TX Wiretest Pattern Length  512
-#define     ei4_tx_wt_pattern_length_1024                         0xC000     //TX Wiretest Pattern Length  1024
-#define     ei4_tx_wt_pattern_length_clear                        0x3FFF     // Clear mask
-
-// ei4_tx_mode_pp Register field name                                       data value   Description
-#define     ei4_tx_reduced_scramble_mode_full_1                   0x4000     //Enables/Disables and sets reduced density of scramble pattern.   Full density 
-#define     ei4_tx_reduced_scramble_mode_div2                     0x8000     //Enables/Disables and sets reduced density of scramble pattern.   Enable Div2 Reduced Density 
-#define     ei4_tx_reduced_scramble_mode_div4                     0xC000     //Enables/Disables and sets reduced density of scramble pattern.   Enable Div4 Reduced Density.
-#define     ei4_tx_reduced_scramble_mode_clear                    0x3FFF     // Clear mask
-#define     ei4_tx_ei3_mode                                       0x0001     //EI3 mode - See also ei4_rx_ei3_mode 
-#define     ei4_tx_ei3_mode_clear                                 0xFFFE     // Clear mask
-
-// ei4_tx_sls_gcrmsg_pp Register field name                                 data value   Description
-#define     ei4_tx_snd_sls_cmd_gcrmsg                             0x8000     //GCR Message: Send SLS Command or Recalibration Data
-#define     ei4_tx_snd_sls_cmd_gcrmsg_clear                       0x7FFF     // Clear mask
-#define     ei4_tx_dyn_recal_tsr_ignore_gcrmsg                    0x4000     //GCR Message: Send Dynamic Recal SLS Commands all the time (not just during the Status Reporting interval)
-#define     ei4_tx_dyn_recal_tsr_ignore_gcrmsg_clear              0xBFFF     // Clear mask
-#define     ei4_tx_sls_cmd_gcrmsg                                 0x0000     //GCR Message: TX SLS Command
-#define     ei4_tx_sls_cmd_gcrmsg_clear                           0xC0FF     // Clear mask
-#define     ei4_tx_snd_sls_cmd_prev_gcrmsg                        0x0080     //GCR Message: Revert to sending previous SLS Command or Recalibration Data after recovery repair made
-#define     ei4_tx_snd_sls_cmd_prev_gcrmsg_clear                  0xFF7F     // Clear mask
-#define     ei4_tx_snd_sls_using_reg_scramble                     0x0040     //GCR Message: Send SLS command using normal scramble pattern instead of 9th pattern
-#define     ei4_tx_snd_sls_using_reg_scramble_clear               0xFFBF     // Clear mask
-
-// ei4_tx_ber_cntl_a_pp Register field name                                 data value   Description
-#define     ei4_tx_err_inj_a_rand_beat_dis                        0x8000     //Used to disable randomization of error inject on different beats of data for pattern A.
-#define     ei4_tx_err_inj_a_rand_beat_dis_clear                  0x7FFF     // Clear mask
-#define     ei4_tx_err_inj_a_fine_sel_1_16                        0x1000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-16 cycles
-#define     ei4_tx_err_inj_a_fine_sel_1_8                         0x2000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-8 cycles
-#define     ei4_tx_err_inj_a_fine_sel_1_4                         0x3000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-4 cycles
-#define     ei4_tx_err_inj_a_fine_sel_1_2                         0x4000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-2 cycles
-#define     ei4_tx_err_inj_a_fine_sel_fixed1                      0x5000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 1 cycle
-#define     ei4_tx_err_inj_a_fine_sel_fixed3                      0x6000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 3 cycles 
-#define     ei4_tx_err_inj_a_fine_sel_fixed7                      0x7000     //Random LSB/fine-grained cycle offset variation control for pattern A, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 7 cycles.
-#define     ei4_tx_err_inj_a_fine_sel_clear                       0x8FFF     // Clear mask
-#define     ei4_tx_err_inj_a_coarse_sel_9_24                      0x0100     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 9-24, mean of 16.5
-#define     ei4_tx_err_inj_a_coarse_sel_13_20                     0x0200     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 13-20, mean of 16.5
-#define     ei4_tx_err_inj_a_coarse_sel_16_19                     0x0300     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-19, mean of 16.5
-#define     ei4_tx_err_inj_a_coarse_sel_17_18                     0x0400     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-17, mean of 16.5
-#define     ei4_tx_err_inj_a_coarse_sel_1_8                       0x0500     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 1-8, mean of 4.5
-#define     ei4_tx_err_inj_a_coarse_sel_3_6                       0x0600     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 3-6, mean of 4.5
-#define     ei4_tx_err_inj_a_coarse_sel_4_5                       0x0700     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 4-5, mean of 4.5
-#define     ei4_tx_err_inj_a_coarse_sel_fixed1                    0x0800     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 1
-#define     ei4_tx_err_inj_a_coarse_sel_fixed3                    0x0900     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 3
-#define     ei4_tx_err_inj_a_coarse_sel_fixed5                    0x0A00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 5
-#define     ei4_tx_err_inj_a_coarse_sel_fixed6                    0x0B00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 6
-#define     ei4_tx_err_inj_a_coarse_sel_fixed7                    0x0C00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 7
-#define     ei4_tx_err_inj_a_coarse_sel_fixed17                   0x0D00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 17
-#define     ei4_tx_err_inj_a_coarse_sel_fixed21                   0x0E00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 21
-#define     ei4_tx_err_inj_a_coarse_sel_fixed25                   0x0F00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern A.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 25
-#define     ei4_tx_err_inj_a_coarse_sel_clear                     0xF0FF     // Clear mask
-#define     ei4_tx_err_inj_a_ber_sel                              0x0000     //Used to set the random bit error injection rate for pattern A.  When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). 
-#define     ei4_tx_err_inj_a_ber_sel_clear                        0x3FC0     // Clear mask
-
-// ei4_tx_ber_cntl_b_pp Register field name                                 data value   Description
-#define     ei4_tx_err_inj_b_rand_beat_dis                        0x8000     //Used to disable randomization of error inject on different beats of data for pattern B.
-#define     ei4_tx_err_inj_b_rand_beat_dis_clear                  0x7FFF     // Clear mask
-#define     ei4_tx_err_inj_b_fine_sel_1_16                        0x1000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-16 cycles
-#define     ei4_tx_err_inj_b_fine_sel_1_8                         0x2000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-8 cycles
-#define     ei4_tx_err_inj_b_fine_sel_1_4                         0x3000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-4 cycles
-#define     ei4_tx_err_inj_b_fine_sel_1_2                         0x4000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Random offset in range of 1-2 cycles
-#define     ei4_tx_err_inj_b_fine_sel_fixed1                      0x5000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 1 cycle
-#define     ei4_tx_err_inj_b_fine_sel_fixed3                      0x6000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 3 cycles 
-#define     ei4_tx_err_inj_b_fine_sel_fixed7                      0x7000     //Random LSB/fine-grained cycle offset variation control for pattern B, where cycles are deserialized domain cycles (2 UI for EI4, 4 UI for EDI).   Fixed offset of 7 cycles.
-#define     ei4_tx_err_inj_b_fine_sel_clear                       0x8FFF     // Clear mask
-#define     ei4_tx_err_inj_b_coarse_sel_9_24                      0x0100     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 9-24, mean of 16.5
-#define     ei4_tx_err_inj_b_coarse_sel_13_20                     0x0200     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 13-20, mean of 16.5
-#define     ei4_tx_err_inj_b_coarse_sel_16_19                     0x0300     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-19, mean of 16.5
-#define     ei4_tx_err_inj_b_coarse_sel_17_18                     0x0400     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 16-17, mean of 16.5
-#define     ei4_tx_err_inj_b_coarse_sel_1_8                       0x0500     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Range of 1-8, mean of 4.5
-#define     ei4_tx_err_inj_b_coarse_sel_3_6                       0x0600     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 3-6, mean of 4.5
-#define     ei4_tx_err_inj_b_coarse_sel_4_5                       0x0700     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.     Range of 4-5, mean of 4.5
-#define     ei4_tx_err_inj_b_coarse_sel_fixed1                    0x0800     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 1
-#define     ei4_tx_err_inj_b_coarse_sel_fixed3                    0x0900     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 3
-#define     ei4_tx_err_inj_b_coarse_sel_fixed5                    0x0A00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 5
-#define     ei4_tx_err_inj_b_coarse_sel_fixed6                    0x0B00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 6
-#define     ei4_tx_err_inj_b_coarse_sel_fixed7                    0x0C00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 7
-#define     ei4_tx_err_inj_b_coarse_sel_fixed17                   0x0D00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 17
-#define     ei4_tx_err_inj_b_coarse_sel_fixed21                   0x0E00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 21
-#define     ei4_tx_err_inj_b_coarse_sel_fixed25                   0x0F00     //Random MSB/coarse-grained multiplier for the base error rate counter, which controls bit error rate variation for pattern B.  There are also a number of nonrandom settings which are specifically chosen to avoid powers of two.    Fixed 25
-#define     ei4_tx_err_inj_b_coarse_sel_clear                     0xF0FF     // Clear mask
-#define     ei4_tx_err_inj_b_ber_sel                              0x0000     //Used to set the random bit error injection rate for pattern B.  When set to a binary value of N, the average bit error rate is 1/(2^N*beats*mean(msb)). 
-#define     ei4_tx_err_inj_b_ber_sel_clear                        0x3FC0     // Clear mask
-
-// ei4_tx_bist_cntl_pp Register field name                                  data value   Description
-#define     ei4_tx_bist_en                                        0x8000     //TBD. jgr
-#define     ei4_tx_bist_en_clear                                  0x7FFF     // Clear mask
-#define     ei4_tx_bist_clr                                       0x4000     //TBD. jgr
-#define     ei4_tx_bist_clr_clear                                 0xBFFF     // Clear mask
-#define     ei4_tx_bist_prbs7_en                                  0x2000     //TBD. This field is updated by the TX BIST logic when BIST is running. jgr
-#define     ei4_tx_bist_prbs7_en_clear                            0xDFFF     // Clear mask
-
-// ei4_tx_ber_cntl_sls_pp Register field name                               data value   Description
-#define     ei4_tx_err_inj_sls_mode                               0x8000     //Used to set the random bit error injection for pattern A to work during SLS transmission only. 
-#define     ei4_tx_err_inj_sls_mode_clear                         0x7FFF     // Clear mask
-#define     ei4_tx_err_inj_sls_all_cmd                            0x4000     //Used to qualify the SLS mode error injection for pattern A, to inject on all SLS command transmissions. 
-#define     ei4_tx_err_inj_sls_all_cmd_clear                      0xBFFF     // Clear mask
-#define     ei4_tx_err_inj_sls_recal                              0x2000     //Used to qualify the SLS mode error injection for pattern A, to inject on the calibration lane only when not sending an SLS command. See workbook for details.
-#define     ei4_tx_err_inj_sls_recal_clear                        0xDFFF     // Clear mask
-#define     ei4_tx_err_inj_sls_cmd                                0x0000     //Used to qualify the SLS mode error injection for pattern A, to inject on only this SLS command transmission. See workbook for SLS command codes.
-#define     ei4_tx_err_inj_sls_cmd_clear                          0xFFC0     // Clear mask
-
-// ei4_tx_cntl_pp Register field name                                       data value   Description
-#define     ei4_tx_enable_reduced_scramble                        0x8000     //Enables reduced density of scramble pattern. 
-#define     ei4_tx_enable_reduced_scramble_clear                  0x7FFF     // Clear mask
-
-// ei4_tx_reset_cfg_pp Register field name                                  data value   Description
-#define     ei4_tx_reset_cfg_hld_clear                            0x0000     // Clear mask
-
-// ei4_tx_tdr_cntl2_pp Register field name                                  data value   Description
-#define     ei4_tx_tdr_pulse_offset                               0x0000     //Offset value for TDR pulse.
-#define     ei4_tx_tdr_pulse_offset_clear                         0x000F     // Clear mask
-
-// ei4_tx_tdr_cntl3_pp Register field name                                  data value   Description
-#define     ei4_tx_tdr_pulse_width                                0x0000     //With of TDR pulse.
-#define     ei4_tx_tdr_pulse_width_clear                          0x000F     // Clear mask
-
-// ei4_rx_mode_pl Register field name                                       data value   Description
-#define     ei4_rx_lane_pdwn                                      0x8000     //Used to receive inhibit and fully power down a lane independent of the logical lane disable. This control is independent from the per-group logical lane disable settings (ei4_rx_lane_disable_vec*) in order to allow for flexibility. Note that this control routes through the boundary scan logic, which has dominance.  Also note that per-group registers ei4_rx_lane_disabled_vec_0_15 and ei4_rx_lane_disabled_vec_16_31 are used to logically disable a lane with respect to the training, recalibration, and repair machines so both this per-lane and the per-group registers need to be set in order to logically disable and powerdown a lane. Note that this per-lane register is adjusted for lane swizzling automatically in HW but it is NOT adjusted automatically in HW when in the MSB-LSB swap mode so the eRepair procedure needs to take care to power down the correct lane when in this mode. 
-#define     ei4_rx_lane_pdwn_clear                                0x7FFF     // Clear mask
-#define     ei4_rx_lane_scramble_disable                          0x0200     //Used to disable the RX descrambler on a specific lane or all lanes by using a per-lane/per-group global write.
-#define     ei4_rx_lane_scramble_disable_clear                    0xFDFF     // Clear mask
-
-// ei4_rx_cntl_pl Register field name                                       data value   Description
-#define     ei4_rx_block_lock_lane                                0x8000     //Enables rotation and checking for block lock. 
-#define     ei4_rx_block_lock_lane_clear                          0x7FFF     // Clear mask
-#define     ei4_rx_check_skew_lane                                0x4000     //Per-Lane Initialization controls. Checks skew request
-#define     ei4_rx_check_skew_lane_clear                          0xBFFF     // Clear mask
-
-// ei4_rx_spare_mode_pl Register field name                                 data value   Description
-#define     ei4_rx_pl_spare_mode_0                                0x8000     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     ei4_rx_pl_spare_mode_1                                0x4000     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     ei4_rx_pl_spare_mode_2                                0x2000     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     ei4_rx_pl_spare_mode_3                                0x1000     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     ei4_rx_pl_spare_mode_4                                0x0800     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     ei4_rx_pl_spare_mode_5                                0x0400     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     ei4_rx_pl_spare_mode_6                                0x0200     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     ei4_rx_pl_spare_mode_7                                0x0100     //Per-lane spare mode latch
-#define     ei4_rx_pl_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// ei4_rx_bist_stat_pl Register field name                                  data value   Description
-#define     ei4_rx_bist_err                                       0x8000     //Indicates a RXBIST error occurred.
-#define     ei4_rx_bist_err_clear                                 0x7FFF     // Clear mask
-#define     ei4_rx_bist_done                                      0x4000     //Indicates a RXBIST has completed. 
-#define     ei4_rx_bist_done_clear                                0xBFFF     // Clear mask
-
-// ei4_rx_offset_even_pl Register field name                                data value   Description
-#define     ei4_rx_offset_even_samp1                              0x0000     //This is the vertical offset of the even sampling latch.
-#define     ei4_rx_offset_even_samp1_clear                        0x80FF     // Clear mask
-#define     ei4_rx_offset_even_samp0                              0x0000     //This is the vertical offset of the even sampling latch.
-#define     ei4_rx_offset_even_samp0_clear                        0x7F80     // Clear mask
-
-// ei4_rx_offset_odd_pl Register field name                                 data value   Description
-#define     ei4_rx_offset_odd_samp1                               0x0000     //This is the vertical offset of the odd sampling latch.
-#define     ei4_rx_offset_odd_samp1_clear                         0x00FF     // Clear mask
-#define     ei4_rx_offset_odd_samp0                               0x0000     //This is the vertical offset of the odd sampling latch.
-#define     ei4_rx_offset_odd_samp0_clear                         0x7F80     // Clear mask
-
-// ei4_rx_amp_val_pl Register field name                                    data value   Description
-#define     ei4_rx_amp_peak                                       0x0000     //This is the vertical offset of the pre-amp.
-#define     ei4_rx_amp_peak_clear                                 0x0FFF     // Clear mask
-
-// ei4_rx_prot_status_pl Register field name                                data value   Description
-#define     ei4_rx_phaserot_val                                   0x0000     //RX Phase Rotator current value.
-#define     ei4_rx_phaserot_val_clear                             0x80FF     // Clear mask
-
-// ei4_rx_prot_mode_pl Register field name                                  data value   Description
-#define     ei4_rx_phaserot_offset                                0x0000     //RX Phase Rotator fixed offset from learned value.
-#define     ei4_rx_phaserot_offset_clear                          0x80FF     // Clear mask
-
-// ei4_rx_prot_cntl_pl Register field name                                  data value   Description
-#define     ei4_rx_prot_cntl_pl_dummy                             0x8000     //Per-Lane phase rotator control r/w register to make tools happy
-#define     ei4_rx_prot_cntl_pl_dummy_clear                       0x7FFF     // Clear mask
-#define     ei4_rx_ext_sr                                         0x0800     //RX Manual Phase Rotator Shift Right Pulse
-#define     ei4_rx_ext_sr_clear                                   0xF7FF     // Clear mask
-#define     ei4_rx_ext_sl                                         0x0400     //RX Manual Phase Rotator Shift Left Pulse
-#define     ei4_rx_ext_sl_clear                                   0xFBFF     // Clear mask
-
-// ei4_rx_fifo_stat_pl Register field name                                  data value   Description
-#define     ei4_rx_fifo_l2u_dly                                   0x0000     //RX FIFO load-to-unload delay, initailed during FIFO init and modified thereafter by the deskew machine.  For setting X, the latency is 2*X to 2*X+2 UI.  Default is 8-10 UI.
-#define     ei4_rx_fifo_l2u_dly_clear                             0x0FFF     // Clear mask
-#define     ei4_rx_fifo_init                                      0x0800     //Initializes the fifo unload counter with the load counter and initializes the fifo load to unload delay
-#define     ei4_rx_fifo_init_clear                                0xF7FF     // Clear mask
-
-// ei4_rx_prbs_mode_pl Register field name                                  data value   Description
-#define     ei4_rx_prbs_tap_id_pattern_b                          0x2000     //Per-Lane PRBS Tap Selector  PRBS tap point B
-#define     ei4_rx_prbs_tap_id_pattern_c                          0x4000     //Per-Lane PRBS Tap Selector  PRBS tap point C
-#define     ei4_rx_prbs_tap_id_pattern_d                          0x6000     //Per-Lane PRBS Tap Selector  PRBS tap point D
-#define     ei4_rx_prbs_tap_id_pattern_e                          0x8000     //Per-Lane PRBS Tap Selector  PRBS tap point E
-#define     ei4_rx_prbs_tap_id_pattern_F                          0xA000     //Per-Lane PRBS Tap Selector  PRBS tap point F
-#define     ei4_rx_prbs_tap_id_pattern_g                          0xC000     //Per-Lane PRBS Tap Selector  PRBS tap point G
-#define     ei4_rx_prbs_tap_id_pattern_h                          0xE000     //Per-Lane PRBS Tap Selector  PRBS tap point H
-#define     ei4_rx_prbs_tap_id_clear                              0x1FFF     // Clear mask
-
-// ei4_rx_vref_pl Register field name                                       data value   Description
-#define     ei4_rx_vref                                           0x0000     //This is the voltage reference setting of the pre-amp.
-#define     ei4_rx_vref_clear                                     0x00FF     // Clear mask
-
-// ei4_rx_stat_pl Register field name                                       data value   Description
-#define     ei4_rx_some_block_locked                              0x8000     //Per-Lane Block Lock Indicator
-#define     ei4_rx_some_block_locked_clear                        0x7FFF     // Clear mask
-#define     ei4_rx_all_block_locked_b                             0x4000     //Per-Lane Block Lock Indicator
-#define     ei4_rx_all_block_locked_b_clear                       0xBFFF     // Clear mask
-#define     ei4_rx_some_skew_valid                                0x2000     //Per-Lane Deskew Pattern B Detect Indicator
-#define     ei4_rx_some_skew_valid_clear                          0xDFFF     // Clear mask
-#define     ei4_rx_all_skew_valid_b                               0x1000     //Per-Lane Deskew Pattern B Detect Indicato (Active Low)r
-#define     ei4_rx_all_skew_valid_b_clear                         0xEFFF     // Clear mask
-#define     ei4_rx_some_prbs_synced                               0x0800     //Per-Lane PRBS Synchronization Indicator
-#define     ei4_rx_some_prbs_synced_clear                         0xF7FF     // Clear mask
-#define     ei4_rx_prbs_synced_b                                  0x0400     //Per-Lane PRBS Synchronization Indicator (Active Low)
-#define     ei4_rx_prbs_synced_b_clear                            0xFBFF     // Clear mask
-#define     ei4_rx_skew_value                                     0x0000     //Per-Lane PRBS Synchronization Count
-#define     ei4_rx_skew_value_clear                               0xFC0F     // Clear mask
-
-// ei4_rx_deskew_stat_pl Register field name                                data value   Description
-#define     ei4_rx_bad_block_lock                                 0x8000     //Deskew Step block lock not established--lane marked bad
-#define     ei4_rx_bad_block_lock_clear                           0x7FFF     // Clear mask
-#define     ei4_rx_bad_skew                                       0x4000     //Deskew Step skew value not detected--lane marked bad
-#define     ei4_rx_bad_skew_clear                                 0xBFFF     // Clear mask
-#define     ei4_rx_bad_deskew                                     0x2000     //Deskew Step deskew value
-#define     ei4_rx_bad_deskew_clear                               0xDFFF     // Clear mask
-
-// ei4_rx_fir_pl Register field name                                        data value   Description
-#define     ei4_rx_pl_fir_errs                                    0x8000     //A Per-Lane Register or State Machine Parity Error has occurred.
-#define     ei4_rx_pl_fir_errs_clear                              0x7FFF     // Clear mask
-
-// ei4_rx_fir_mask_pl Register field name                                   data value   Description
-#define     ei4_rx_pl_fir_errs_mask                               0x8000     //FIR mask for register or state machine parity checkers in per-lane logic. A value of 1 masks the error from generating a FIR error.
-#define     ei4_rx_pl_fir_errs_mask_clear                         0x7FFF     // Clear mask
-
-// ei4_rx_fir_error_inject_pl Register field name                           data value   Description
-#define     ei4_rx_pl_fir_err_inj                                 0x8000     //RX Per-Lane Parity Error Injection
-#define     ei4_rx_pl_fir_err_inj_clear                           0x7FFF     // Clear mask
-
-// ei4_rx_sls_pl Register field name                                        data value   Description
-#define     ei4_rx_sls_lane_sel                                   0x8000     //Selects which lane to receive SLS Commands and Recalibration Data on
-#define     ei4_rx_sls_lane_sel_clear                             0x7FFF     // Clear mask
-#define     ei4_rx_9th_pattern_en                                 0x4000     //Sets RX Descrabmler to use 9th Scramble Pattern
-#define     ei4_rx_9th_pattern_en_clear                           0xBFFF     // Clear mask
-
-// ei4_rx_wt_status_pl Register field name                                  data value   Description
-#define     ei4_rx_wt_lane_disabled                               0x8000     //Per-Lane Wiretest lane disabled status
-#define     ei4_rx_wt_lane_disabled_clear                         0x7FFF     // Clear mask
-#define     ei4_rx_wt_lane_inverted                               0x4000     //Per-Lane Wiretest lane inverted/swapped status
-#define     ei4_rx_wt_lane_inverted_clear                         0xBFFF     // Clear mask
-#define     ei4_rx_wt_lane_bad_code_n_stuck_1                     0x0800     //Per-Lane Wiretest Lane Bad code  N-leg stuck at 1.
-#define     ei4_rx_wt_lane_bad_code_n_stuck_0                     0x1000     //Per-Lane Wiretest Lane Bad code  N-leg stuck at 0.
-#define     ei4_rx_wt_lane_bad_code_p_stuck_1                     0x1800     //Per-Lane Wiretest Lane Bad code  P-leg stuck at 1.
-#define     ei4_rx_wt_lane_bad_code_p_stuck_0                     0x2000     //Per-Lane Wiretest Lane Bad code  P-leg stuck at 0.
-#define     ei4_rx_wt_lane_bad_code_n_or_p_floating               0x2800     //Per-Lane Wiretest Lane Bad code  N- or P- leg floating-swapping undetermined.
-#define     ei4_rx_wt_lane_bad_code_p_or_n_floating               0x3000     //Per-Lane Wiretest Lane Bad code  P or N leg floating--swapping undetermined.
-#define     ei4_rx_wt_lane_bad_code_unknown                       0x3800     //Per-Lane Wiretest Lane Bad code  Unknown failure.
-#define     ei4_rx_wt_lane_bad_code_clear                         0xC7FF     // Clear mask
-
-// ei4_rx_fifo_cntl_pl Register field name                                  data value   Description
-#define     ei4_rx_fifo_inc_l2u_dly                               0x8000     //Increment existing FIFO load-to-unload delay register.
-#define     ei4_rx_fifo_inc_l2u_dly_clear                         0x7FFF     // Clear mask
-#define     ei4_rx_fifo_dec_l2u_dly                               0x4000     //Decrement existing FIFO load-to-unload delay register.
-#define     ei4_rx_fifo_dec_l2u_dly_clear                         0xBFFF     // Clear mask
-#define     ei4_rx_clr_skew_valid                                 0x2000     //Clear skew valid registers                            
-#define     ei4_rx_clr_skew_valid_clear                           0xDFFF     // Clear mask
-
-// ei4_rx_ber_status_pl Register field name                                 data value   Description
-#define     ei4_rx_ber_count                                      0x0000     //Per-Lane (PL) Diagnostic Bit Error Rate (BER) error counter. Increments when in diagnostic BER mode AND the output of the descrambler is non-zero. This counter counts errors on every UI so it is a true BER counter.
-#define     ei4_rx_ber_count_clear                                0x00FF     // Clear mask
-#define     ei4_rx_ber_count_saturated                            0x0080     //PL Diag BER Error Counter saturation indicator. When '1' indicates that the error counter has saturated to the selected max value. A global per-lane read of this field will indicate if any lane error counters in the group are saturated.
-#define     ei4_rx_ber_count_saturated_clear                      0xFF7F     // Clear mask
-#define     ei4_rx_ber_count_frozen_by_lane                       0x0040     //PL Diag BER Error Counter and or PP Timer has been frozen by another lane's error counter being saturated.
-#define     ei4_rx_ber_count_frozen_by_lane_clear                 0xFFBF     // Clear mask
-#define     ei4_rx_ber_count_frozen_by_timer                      0x0020     //PL Diag BER Error Counter has been frozen by a diag BER timer becoming saturated.
-#define     ei4_rx_ber_count_frozen_by_timer_clear                0xFFDF     // Clear mask
-#define     ei4_rx_ber_timer_saturated                            0x0010     //PL Diag BER Timer saturation indicator. When '1' indicates that the pack BER timer has saturated to the max value. A global per-lane read of this field will indicate if any timer in the group has saturated.
-#define     ei4_rx_ber_timer_saturated_clear                      0xFFEF     // Clear mask
-
-// ei4_rx_ber_timer_0_15_pl Register field name                             data value   Description
-#define     ei4_rx_ber_timer_value_0_15                           0x0000     //PL Diag BER Timer value for this lane, bits 0-15. All lanes in a pack share a timer and will have the same timer value. The value can either be read on one lane in a pack to save data collection time or all lanes can be read.
-#define     ei4_rx_ber_timer_value_0_15_clear                     0x0000     // Clear mask
-
-// ei4_rx_ber_timer_16_31_pl Register field name                            data value   Description
-#define     ei4_rx_ber_timer_value_16_31                          0x0000     //PL Diag BER Timer value, bits 16-31.
-#define     ei4_rx_ber_timer_value_16_31_clear                    0x0000     // Clear mask
-
-// ei4_rx_ber_timer_32_39_pl Register field name                            data value   Description
-#define     ei4_rx_ber_timer_value_32_39                          0x0000     //PL Diag BER Timer value, bits 32-39.
-#define     ei4_rx_ber_timer_value_32_39_clear                    0x00FF     // Clear mask
-
-// ei4_rx_servo_cntl_pl Register field name                                 data value   Description
-#define     ei4_rx_servo_op_done                                  0x8000     //Servo Op completed
-#define     ei4_rx_servo_op_done_clear                            0x7FFF     // Clear mask
-#define     ei4_rx_servo_op_all_done_b                            0x4000     //All Servo Op (asserted low for global dot-Or reading)
-#define     ei4_rx_servo_op_all_done_b_clear                      0xBFFF     // Clear mask
-#define     ei4_rx_servo_op                                       0x0000     //Servo Operation code
-#define     ei4_rx_servo_op_clear                                 0xC1FF     // Clear mask
-
-// ei4_rx_fifo_diag_0_15_pl Register field name                             data value   Description
-#define     ei4_rx_fifo_out_0_15                                  0x0000     //Diag Capture: fifo entries 0 to 15
-#define     ei4_rx_fifo_out_0_15_clear                            0x0000     // Clear mask
-
-// ei4_rx_fifo_diag_16_31_pl Register field name                            data value   Description
-#define     ei4_rx_fifo_out_16_31                                 0x0000     //Diag Capture: fifo entries 16 to 31
-#define     ei4_rx_fifo_out_16_31_clear                           0x0000     // Clear mask
-
-// ei4_rx_fifo_diag_32_47_pl Register field name                            data value   Description
-#define     ei4_rx_fifo_out_32_47                                 0x0000     //Diag Capture: fifo entries 32 to 47
-#define     ei4_rx_fifo_out_32_47_clear                           0x0000     // Clear mask
-
-// ei4_rx_eye_width_status_pl Register field name                           data value   Description
-#define     ei4_rx_eye_width                                      0x0000     //RX Current Eye Width (in PR steps).
-#define     ei4_rx_eye_width_clear                                0x00FF     // Clear mask
-#define     ei4_rx_hist_min_eye_width_valid                       0x0080     //RX Historic Eye Minimum is valid for this lane.
-#define     ei4_rx_hist_min_eye_width_valid_clear                 0xFF7F     // Clear mask
-#define     ei4_rx_hist_min_eye_width                             0x0000     //RX Historic Eye Minimum--per-pack register valid for this lane if ei4_rx_hist_eye_min_valid is asserted for this lane.
-#define     ei4_rx_hist_min_eye_width_clear                       0xDFC0     // Clear mask
-
-// ei4_rx_eye_width_cntl_pl Register field name                             data value   Description
-#define     ei4_rx_reset_hist_eye_width_min                       0x8000     //RX Historic Eye Minimum Reset--reset historic min to maximum value and clears valid bits.
-#define     ei4_rx_reset_hist_eye_width_min_clear                 0x7FFF     // Clear mask
-
-// ei4_rx_trace_pl Register field name                                      data value   Description
-#define     ei4_rx_ln_trc_en                                      0x8000     //Enable tracing of this lane
-#define     ei4_rx_ln_trc_en_clear                                0x7FFF     // Clear mask
-
-// ei4_rx_servo_ber_count_pl Register field name                            data value   Description
-#define     ei4_rx_servo_ber_count                                0x0000     //Servo-based bit error count.
-#define     ei4_rx_servo_ber_count_clear                          0x000F     // Clear mask
-
-// ei4_rx_eye_opt_stat_pl Register field name                               data value   Description
-#define     ei4_rx_bad_eye_opt_ber                                0x8000     //Eye opt Step failed BER test--lane marked bad
-#define     ei4_rx_bad_eye_opt_ber_clear                          0x7FFF     // Clear mask
-#define     ei4_rx_bad_eye_opt_width                              0x4000     //Eye opt Step failed width test--lane marked bad
-#define     ei4_rx_bad_eye_opt_width_clear                        0xBFFF     // Clear mask
-
-// ei4_rx_clk_mode_pg Register field name                                   data value   Description
-#define     ei4_rx_clk_pdwn                                       0x8000     //Used to disable the rx clock and put it into a low power state.
-#define     ei4_rx_clk_pdwn_clear                                 0x7FFF     // Clear mask
-#define     ei4_rx_clk_invert                                     0x4000     //Used to invert the polarity of the clock.
-#define     ei4_rx_clk_invert_clear                               0xBFFF     // Clear mask
-
-// ei4_rx_spare_mode_pg Register field name                                 data value   Description
-#define     ei4_rx_pg_spare_mode_0                                0x8000     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_0_clear                          0x7FFF     // Clear mask
-#define     ei4_rx_pg_spare_mode_1                                0x4000     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_1_clear                          0xBFFF     // Clear mask
-#define     ei4_rx_pg_spare_mode_2                                0x2000     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_2_clear                          0xDFFF     // Clear mask
-#define     ei4_rx_pg_spare_mode_3                                0x1000     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_3_clear                          0xEFFF     // Clear mask
-#define     ei4_rx_pg_spare_mode_4                                0x0800     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_4_clear                          0xF7FF     // Clear mask
-#define     ei4_rx_pg_spare_mode_5                                0x0400     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_5_clear                          0xFBFF     // Clear mask
-#define     ei4_rx_pg_spare_mode_6                                0x0200     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_6_clear                          0xFDFF     // Clear mask
-#define     ei4_rx_pg_spare_mode_7                                0x0100     //Per-group spare mode latch
-#define     ei4_rx_pg_spare_mode_7_clear                          0xFEFF     // Clear mask
-
-// ei4_rx_stop_cntl_stat_pg Register field name                             data value   Description
-#define     ei4_rx_stop_state_enable                              0x8000     //Enable State machine stop of address
-#define     ei4_rx_stop_state_enable_clear                        0x7FFF     // Clear mask
-#define     ei4_rx_state_stopped                                  0x4000     //State Machines stopped
-#define     ei4_rx_state_stopped_clear                            0xBFFF     // Clear mask
-#define     ei4_rx_resume_from_stop                               0x2000     //Resume stopped state machines and /or counters
-#define     ei4_rx_resume_from_stop_clear                         0xDFFF     // Clear mask
-#define     ei4_rx_stop_addr_msb                                  0x0000     //Stop address Most-significant four bits 0 to 3
-#define     ei4_rx_stop_addr_msb_clear                            0xFF0F     // Clear mask
-#define     ei4_rx_stop_mask_msb                                  0x0000     //Stop mask    Most-significant four bits 0 to 3
-#define     ei4_rx_stop_mask_msb_clear                            0xF0F0     // Clear mask
-
-// ei4_rx_mode_pg Register field name                                       data value   Description
-#define     ei4_rx_master_mode                                    0x8000     //Master Mode
-#define     ei4_rx_master_mode_clear                              0x7FFF     // Clear mask
-#define     ei4_rx_disable_fence_reset                            0x4000     //Set to disable clearing of the RX and TX fence controls at the end of training. 
-#define     ei4_rx_disable_fence_reset_clear                      0xBFFF     // Clear mask
-
-// ei4_rx_bus_repair_pg Register field name                                 data value   Description
-#define     ei4_rx_bus_repair_count                               0x0000     //TBD
-#define     ei4_rx_bus_repair_count_clear                         0x3FFF     // Clear mask
-#define     ei4_rx_bus_repair_pos_0                               0x0000     //TBD
-#define     ei4_rx_bus_repair_pos_0_clear                         0xC07F     // Clear mask
-#define     ei4_rx_bus_repair_pos_1                               0x0000     //TBD
-#define     ei4_rx_bus_repair_pos_1_clear                         0x3F80     // Clear mask
-
-// ei4_rx_grp_repair_vec_0_15_pg Register field name                        data value   Description
-#define     ei4_rx_grp_repair_vec_0_15                            0x0000     //TBD
-#define     ei4_rx_grp_repair_vec_0_15_clear                      0x0000     // Clear mask
-
-// ei4_rx_grp_repair_vec_16_31_pg Register field name                       data value   Description
-#define     ei4_rx_grp_repair_vec_16_31                           0x0000     //TBD
-#define     ei4_rx_grp_repair_vec_16_31_clear                     0x0000     // Clear mask
-
-// ei4_rx_stop_addr_lsb_pg Register field name                              data value   Description
-#define     ei4_rx_stop_addr_lsb                                  0x0000     //Stop address least-significant 16 bits 4 to 19 
-#define     ei4_rx_stop_addr_lsb_clear                            0x0000     // Clear mask
-
-// ei4_rx_stop_mask_lsb_pg Register field name                              data value   Description
-#define     ei4_rx_stop_mask_lsb                                  0x0000     //Stop mask    least-significant 16 bits 4 to 19
-#define     ei4_rx_stop_mask_lsb_clear                            0x0000     // Clear mask
-
-// ei4_rx_reset_act_pg Register field name                                  data value   Description
-#define     ei4_rx_reset_cfg_ena                                  0x8000     //Enable Configurable Group Reset
-#define     ei4_rx_reset_cfg_ena_clear                            0x7FFF     // Clear mask
-#define     ei4_rx_clr_par_errs                                   0x0002     //Clear All RX Parity Error Latches
-#define     ei4_rx_clr_par_errs_clear                             0xFFFD     // Clear mask
-#define     ei4_rx_fir_reset                                      0x0001     //FIR Reset
-#define     ei4_rx_fir_reset_clear                                0xFFFE     // Clear mask
-
-// ei4_rx_id1_pg Register field name                                        data value   Description
-#define     ei4_rx_bus_id                                         0x0000     //This field is used to programmably set the bus number that a clkgrp belongs to.
-#define     ei4_rx_bus_id_clear                                   0x03FF     // Clear mask
-#define     ei4_rx_group_id                                       0x0000     //This field is used to programmably set the clock group number within a bus.
-#define     ei4_rx_group_id_clear                                 0xFE07     // Clear mask
-
-// ei4_rx_id2_pg Register field name                                        data value   Description
-#define     ei4_rx_last_group_id                                  0x0000     //This field is used to programmably set the last clock group number within a bus.
-#define     ei4_rx_last_group_id_clear                            0x03FF     // Clear mask
-
-// ei4_rx_id3_pg Register field name                                        data value   Description
-#define     ei4_rx_start_lane_id                                  0x0000     //This field is used to programmably set the first lane position in the group but relative to the bus.
-#define     ei4_rx_start_lane_id_clear                            0x80FF     // Clear mask
-#define     ei4_rx_end_lane_id                                    0x0000     //This field is used to programmably set the last lane position in the group but relative to the bus.
-#define     ei4_rx_end_lane_id_clear                              0x7F80     // Clear mask
-
-// ei4_rx_sls_mode_pg Register field name                                   data value   Description
-#define     ei4_rx_sls_disable                                    0x8000     //Disables receiving & decoding of SLS commands
-#define     ei4_rx_sls_disable_clear                              0x7FFF     // Clear mask
-#define     ei4_tx_sls_disable                                    0x4000     //Disables the sending of SLS commands
-#define     ei4_tx_sls_disable_clear                              0xBFFF     // Clear mask
-#define     ei4_rx_sls_cntr_tap_pts_tap2                          0x1000     //How Long the SLS RX Command Needs to be Stable for.  EDI - 32 c8 clks; EI4 - 64 c4 clks
-#define     ei4_rx_sls_cntr_tap_pts_tap3                          0x2000     //How Long the SLS RX Command Needs to be Stable for.  EDI - 64 c8 clks; EI4 - 128 c4 clks
-#define     ei4_rx_sls_cntr_tap_pts_tap4                          0x3000     //How Long the SLS RX Command Needs to be Stable for.  EDI - 128 c8 clks; EI4 - 256 c4 clks
-#define     ei4_rx_sls_cntr_tap_pts_clear                         0xCFFF     // Clear mask
-#define     ei4_rx_nonsls_cntr_tap_pts_tap2                       0x0400     //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data).  EDI - 64 c8 clks; EI4 - 128 c4 clks
-#define     ei4_rx_nonsls_cntr_tap_pts_tap3                       0x0800     //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data).  EDI - 128 c8 clks; EI4 - 256 c4 clks
-#define     ei4_rx_nonsls_cntr_tap_pts_tap4                       0x0C00     //How Long a Non-SLS RX Command Needs to be Stable for (to know we have switched from an SLS command to data).  EDI - 256 c8 clks; EI4 - 512 c4 clks
-#define     ei4_rx_nonsls_cntr_tap_pts_clear                      0xF3FF     // Clear mask
-#define     ei4_rx_sls_err_chk_run                                0x0200     //Run SLS error check counter
-#define     ei4_rx_sls_err_chk_run_clear                          0xFDFF     // Clear mask
-
-// ei4_rx_training_start_pg Register field name                             data value   Description
-#define     ei4_rx_start_wiretest                                 0x8000     //When this register is written to a 1 the training state machine will run the wiretest portion of the training states.
-#define     ei4_rx_start_wiretest_clear                           0x7FFF     // Clear mask
-#define     ei4_rx_start_deskew                                   0x4000     //When this register is written to a 1 the training state machine will run the deskew portion of the training states.
-#define     ei4_rx_start_deskew_clear                             0xBFFF     // Clear mask
-#define     ei4_rx_start_eye_opt                                  0x2000     //When this register is written to a 1 the training state machine will run the data eye optimization portion of the training states.
-#define     ei4_rx_start_eye_opt_clear                            0xDFFF     // Clear mask
-#define     ei4_rx_start_repair                                   0x1000     //When this register is written to a 1 the training state machine will run the static lane repair portion of the training states.
-#define     ei4_rx_start_repair_clear                             0xEFFF     // Clear mask
-#define     ei4_rx_start_func_mode                                0x0800     //When this register is written to a 1 the training state machine will run the transition to functional data portion of the training states.
-#define     ei4_rx_start_func_mode_clear                          0xF7FF     // Clear mask
-#define     ei4_rx_start_bist                                     0x0400     //Run initializations for BIST before enabling the BIST state machine. 
-#define     ei4_rx_start_bist_clear                               0xFBFF     // Clear mask
-#define     ei4_rx_start_offset_cal                               0x0200     //Run offset cal. 
-#define     ei4_rx_start_offset_cal_clear                         0xFDFF     // Clear mask
-#define     ei4_rx_start_wt_bypass                                0x0100     //Run wiretest bypass. 
-#define     ei4_rx_start_wt_bypass_clear                          0xFEFF     // Clear mask
-
-// ei4_rx_training_status_pg Register field name                            data value   Description
-#define     ei4_rx_wiretest_done                                  0x8000     //When this bit is read as a 1, the wiretest training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     ei4_rx_wiretest_done_clear                            0x7FFF     // Clear mask
-#define     ei4_rx_deskew_done                                    0x4000     //When this bit is read as a 1, the deskew training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     ei4_rx_deskew_done_clear                              0xBFFF     // Clear mask
-#define     ei4_rx_eye_opt_done                                   0x2000     //When this bit is read as a 1, the eye optimization training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     ei4_rx_eye_opt_done_clear                             0xDFFF     // Clear mask
-#define     ei4_rx_repair_done                                    0x1000     //When this bit is read as a 1, the static lane repair training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     ei4_rx_repair_done_clear                              0xEFFF     // Clear mask
-#define     ei4_rx_func_mode_done                                 0x0800     //When this bit is read as a 1, the transition to functional data training state has completed. Check the corresponding ei4_rx_ts_*_failed register field for the pass/fail status of this training state.
-#define     ei4_rx_func_mode_done_clear                           0xF7FF     // Clear mask
-#define     ei4_rx_bist_started                                   0x0400     //When this bit is read as a 1, the RX BIST initialization has finished and RX BIST has started running. 
-#define     ei4_rx_bist_started_clear                             0xFBFF     // Clear mask
-#define     ei4_rx_offset_cal_done                                0x0200     //When this bit is read as a 1, offset cal has completed. 
-#define     ei4_rx_offset_cal_done_clear                          0xFDFF     // Clear mask
-#define     ei4_rx_wt_bypass_done                                 0x0100     //When this bit is read as a 1, wiretest bypass has completed. 
-#define     ei4_rx_wt_bypass_done_clear                           0xFEFF     // Clear mask
-#define     ei4_rx_wiretest_failed                                0x0080     //When this bit is read as a 1, the wiretest training state encountered an error.
-#define     ei4_rx_wiretest_failed_clear                          0xFF7F     // Clear mask
-#define     ei4_rx_deskew_failed                                  0x0040     //When this bit is read as a 1, the deskew training state encountered an error.
-#define     ei4_rx_deskew_failed_clear                            0xFFBF     // Clear mask
-#define     ei4_rx_eye_opt_failed                                 0x0020     //When this bit is read as a 1, the eye optimization training state encountered an error.
-#define     ei4_rx_eye_opt_failed_clear                           0xFFDF     // Clear mask
-#define     ei4_rx_repair_failed                                  0x0010     //When this bit is read as a 1, the static lane repair training state encountered an error.
-#define     ei4_rx_repair_failed_clear                            0xFFEF     // Clear mask
-#define     ei4_rx_func_mode_failed                               0x0008     //When this bit is read as a 1, the transition to functional data training state encountered an error.
-#define     ei4_rx_func_mode_failed_clear                         0xFFF7     // Clear mask
-#define     ei4_rx_start_bist_failed                              0x0004     //When this bit is read as a 1, the RX BIST initialization has encountered and error. 
-#define     ei4_rx_start_bist_failed_clear                        0xFFFB     // Clear mask
-#define     ei4_rx_offset_cal_failed                              0x0002     //When this bit is read as a 1, offset cal has encountered an error. 
-#define     ei4_rx_offset_cal_failed_clear                        0xFFFD     // Clear mask
-#define     ei4_rx_wt_bypass_failed                               0x0001     //When this bit is read as a 1, wiretest bypass has encountered an error. 
-#define     ei4_rx_wt_bypass_failed_clear                         0xFFFE     // Clear mask
-
-// ei4_rx_recal_status_pg Register field name                               data value   Description
-#define     ei4_rx_recal_status                                   0x0000     //RX Recalibration Status
-#define     ei4_rx_recal_status_clear                             0x0000     // Clear mask
-
-// ei4_rx_timeout_sel_pg Register field name                                data value   Description
-#define     ei4_rx_sls_timeout_sel_tap1                           0x2000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  54.6us 
-#define     ei4_rx_sls_timeout_sel_tap2                           0x4000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  109.2us 
-#define     ei4_rx_sls_timeout_sel_tap3                           0x6000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  218.4us 
-#define     ei4_rx_sls_timeout_sel_tap4                           0x8000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  436.7us 
-#define     ei4_rx_sls_timeout_sel_tap5                           0xA000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  873.5us 
-#define     ei4_rx_sls_timeout_sel_tap6                           0xC000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  28.0ms 
-#define     ei4_rx_sls_timeout_sel_tap7                           0xE000     //Selects Spare Lane Signalling Timeout value (how long to wait for a SLS handshake command)  infinite
-#define     ei4_rx_sls_timeout_sel_clear                          0x1FFF     // Clear mask
-#define     ei4_rx_ds_bl_timeout_sel_tap1                         0x0400     //Selects Deskew Block Lock Timeout value.   128k UI or 13.6us 
-#define     ei4_rx_ds_bl_timeout_sel_tap2                         0x0800     //Selects Deskew Block Lock Timeout value.   256k UI or 27.3us 
-#define     ei4_rx_ds_bl_timeout_sel_tap3                         0x0C00     //Selects Deskew Block Lock Timeout value.   1M UI or 109.2us 
-#define     ei4_rx_ds_bl_timeout_sel_tap4                         0x1000     //Selects Deskew Block Lock Timeout value.   2M UI or 218.5us 
-#define     ei4_rx_ds_bl_timeout_sel_tap5                         0x1400     //Selects Deskew Block Lock Timeout value.   4M UI or 436.9us 
-#define     ei4_rx_ds_bl_timeout_sel_tap6                         0x1800     //Selects Deskew Block Lock Timeout value.   8M UI or 873.8us 
-#define     ei4_rx_ds_bl_timeout_sel_tap7                         0x1C00     //Selects Deskew Block Lock Timeout value.   infinite
-#define     ei4_rx_ds_bl_timeout_sel_clear                        0xE3FF     // Clear mask
-#define     ei4_rx_cl_timeout_sel_tap1                            0x0080     //Selects Clock Lock Timeout value.   128k UI or 13.6us 
-#define     ei4_rx_cl_timeout_sel_tap2                            0x0100     //Selects Clock Lock Timeout value.   256k UI or 27.3us 
-#define     ei4_rx_cl_timeout_sel_tap3                            0x0180     //Selects Clock Lock Timeout value.   1M UI or 109.2us 
-#define     ei4_rx_cl_timeout_sel_tap4                            0x0200     //Selects Clock Lock Timeout value.   2M UI or 218.5us 
-#define     ei4_rx_cl_timeout_sel_tap5                            0x0280     //Selects Clock Lock Timeout value.   4M UI or 436.9us 
-#define     ei4_rx_cl_timeout_sel_tap6                            0x0300     //Selects Clock Lock Timeout value.   8M UI or 873.8us 
-#define     ei4_rx_cl_timeout_sel_tap7                            0x0380     //Selects Clock Lock Timeout value.   infinite
-#define     ei4_rx_cl_timeout_sel_clear                           0xFC7F     // Clear mask
-#define     ei4_rx_wt_timeout_sel_tap1                            0x0010     //Selects Wiretest Timeout value.   128k UI or 13.6us 
-#define     ei4_rx_wt_timeout_sel_tap2                            0x0020     //Selects Wiretest Timeout value.   256k UI or 27.3us 
-#define     ei4_rx_wt_timeout_sel_tap3                            0x0030     //Selects Wiretest Timeout value.   1M UI or 109.2us 
-#define     ei4_rx_wt_timeout_sel_tap4                            0x0040     //Selects Wiretest Timeout value.   2M UI or 218.5us 
-#define     ei4_rx_wt_timeout_sel_tap5                            0x0050     //Selects Wiretest Timeout value.   4M UI or 436.9us 
-#define     ei4_rx_wt_timeout_sel_tap6                            0x0060     //Selects Wiretest Timeout value.   8M UI or 873.8us 
-#define     ei4_rx_wt_timeout_sel_tap7                            0x0070     //Selects Wiretest Timeout value.   infinite
-#define     ei4_rx_wt_timeout_sel_clear                           0xC78F     // Clear mask
-#define     ei4_rx_ds_timeout_sel_tap1                            0x0002     //Selects Deskew  Timeout value.   128k UI or 13.6us 
-#define     ei4_rx_ds_timeout_sel_tap2                            0x0004     //Selects Deskew  Timeout value.   256k UI or 27.3us 
-#define     ei4_rx_ds_timeout_sel_tap3                            0x0006     //Selects Deskew  Timeout value.   1M UI or 109.2us 
-#define     ei4_rx_ds_timeout_sel_tap4                            0x0008     //Selects Deskew  Timeout value.   2M UI or 218.5us 
-#define     ei4_rx_ds_timeout_sel_tap5                            0x000A     //Selects Deskew  Timeout value.   4M UI or 436.9us 
-#define     ei4_rx_ds_timeout_sel_tap6                            0x000C     //Selects Deskew  Timeout value.   8M UI or 873.8us 
-#define     ei4_rx_ds_timeout_sel_tap7                            0x000E     //Selects Deskew  Timeout value.   infinite
-#define     ei4_rx_ds_timeout_sel_clear                           0xFF11     // Clear mask
-
-// ei4_rx_fifo_mode_pg Register field name                                  data value   Description
-#define     ei4_rx_fifo_initial_l2u_dly                           0x0000     //RX FIFO Initial Load to Unload Delay. For setting X, the latency is 4*X to 4*X+4 UI.  Default is 16-20 UI.
-#define     ei4_rx_fifo_initial_l2u_dly_clear                     0x0FFF     // Clear mask
-#define     ei4_rx_fifo_final_l2u_dly                             0x0000     //RX FIFO Final Load to Unload Delay. For setting X, the latency is 4*X to 4*X+4 UI.  Default is 8-12 UI.
-#define     ei4_rx_fifo_final_l2u_dly_clear                       0xF0FF     // Clear mask
-#define     ei4_rx_fifo_max_deskew                                0x0000     //RX FIFO Max Deskew Control Value. TBD
-#define     ei4_rx_fifo_max_deskew_clear                          0xFF0F     // Clear mask
-#define     ei4_rx_fifo_final_l2u_min_err_thresh_tap1             0x0004     //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by ei4_rx_eo_final_l2u_timeout_sel.   16 errors 
-#define     ei4_rx_fifo_final_l2u_min_err_thresh_tap2             0x0008     //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by ei4_rx_eo_final_l2u_timeout_sel.   128 errors 
-#define     ei4_rx_fifo_final_l2u_min_err_thresh_tap3             0x000C     //RX FIFO error threshold used to qualify the minimum load to unload delay as bad, which is used as the point of reference for adjusting to the final load to unload delay. Note that the errors are accumulated across the entire clock group for a length of time selected by ei4_rx_eo_final_l2u_timeout_sel.   255 errors
-#define     ei4_rx_fifo_final_l2u_min_err_thresh_clear            0xFF33     // Clear mask
-
-// ei4_rx_sls_status_pg Register field name                                 data value   Description
-#define     ei4_rx_sls_cmd_val                                    0x8000     //Current SLS Command Valid
-#define     ei4_rx_sls_cmd_val_clear                              0x7FFF     // Clear mask
-#define     ei4_rx_sls_cmd_encode_shadow_request                  0x0100     //Current SLS Command  Driven by the RX side to request shadowing of its receive lane from lane n-1 to lane n
-#define     ei4_rx_sls_cmd_encode_shadow_done                     0x0200     //Current SLS Command  Driven by the RX side to signal now receiving lane n-1s data on lane n
-#define     ei4_rx_sls_cmd_encode_shadow_repair_request           0x0300     //Current SLS Command  Driven by the RX side to request shadowing and repair of its receive lane from lane n-1 to n.
-#define     ei4_rx_sls_cmd_encode_shadow_repair_done              0x0400     //Current SLS Command  Driven by the RX side to signal lane n-1 is repaired.
-#define     ei4_rx_sls_cmd_encode_unshadow_request                0x0500     //Current SLS Command  Driven by the RX side to request shadowing of receive lane from lane n+1 to lane n.
-#define     ei4_rx_sls_cmd_encode_unshadow_done                   0x0600     //Current SLS Command  Driven by the RX side to signal now receiving lane n+1 data on lane n
-#define     ei4_rx_sls_cmd_encode_unshadow_repair_request         0x0700     //Current SLS Command  Driven by the RX side to request unshadowing and repair of its receive lane from lane n+1 to lane n.
-#define     ei4_rx_sls_cmd_encode_unshadow_repair_done            0x0800     //Current SLS Command  Driven by the RX side to signal lane n+1 is repaired.
-#define     ei4_rx_sls_cmd_encode_sls_exception                   0x0900     //Current SLS Command  Driven by the RX side to indicate to the other side of the bus its RX SLS lane is broken.
-#define     ei4_rx_sls_cmd_encode_init_done                       0x0A00     //Current SLS Command  Driven to signal the CTLE/DFE/offset (re-
-#define     ei4_rx_sls_cmd_encode_recal_request                   0x0B00     //Current SLS Command  Driven on recalibration lane x to request a recalibration of its receive recalibration lane y.
-#define     ei4_rx_sls_cmd_encode_recal_running                   0x0C00     //Current SLS Command  Driven during the status reporting interval of recalibration to indicate recalibration has not completed
-#define     ei4_rx_sls_cmd_encode_recal_done                      0x0D00     //Current SLS Command  Driven to indicate its recalibration is complete.
-#define     ei4_rx_sls_cmd_encode_recal_failed                    0x0E00     //Current SLS Command  Driven to indicate recalibration has failed on its receive recalibration lane
-#define     ei4_rx_sls_cmd_encode_recal_abort                     0x0F00     //Current SLS Command  Abort recalibration.
-#define     ei4_rx_sls_cmd_encode_reserved2                       0x1000     //Current SLS Command  Reserved.010001
-#define     ei4_rx_sls_cmd_encode_reserved4                       0x1200     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved5                       0x1300     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved6                       0x1400     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved7                       0x1500     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved8                       0x1600     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved9                       0x1700     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved10                      0x1800     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_init_ack_done                   0x1900     //Current SLS Command  Driven in response to an init_done (not currently used
-#define     ei4_rx_sls_cmd_encode_reserved11                      0x1A00     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_recal_ack                       0x1B00     //Current SLS Command  Driven on recalibration lane y in response to a recal_request on its receive recalibration lane x
-#define     ei4_rx_sls_cmd_encode_reserved12                      0x1C00     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved13                      0x1D00     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_reserved14                      0x1E00     //Current SLS Command  Reserved.
-#define     ei4_rx_sls_cmd_encode_recal_abort_ack                 0x1F00     //Current SLS Command  Abort recalibration acknowledge.
-#define     ei4_rx_sls_cmd_encode_clear                           0xC0FF     // Clear mask
-#define     ei4_rx_sls_err_chk_cnt                                0x0000     //Error count result for SLS error checking mode
-#define     ei4_rx_sls_err_chk_cnt_clear                          0xFF00     // Clear mask
-
-// ei4_rx_fir1_pg Register field name                                       data value   Description
-#define     ei4_rx_pg_fir1_errs_par_err_ei4_rx_rpr_state              0x0800     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     ei4_rx_pg_fir1_errs_par_err_ei4_rx_eyeopt_state           0x0C00     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     ei4_rx_pg_fir1_errs_par_err_dsm_state                 0x0400     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     ei4_rx_pg_fir1_errs_par_err_rxdsm_state               0x0400     //A Per-Group RXCTL Register or State Machine Parity Error has occurred. 
-#define     ei4_rx_pg_fir1_errs_clear                             0x0003     // Clear mask
-#define     ei4_rx_pl_fir_err                                     0x0001     //Summary bit indicating an RX per-lane register or state machine parity error has occurred in one or more lanes. The ei4_rx_fir_pl register from each lane should be read to isolate to a particular piece of logic. There is no mechanism to determine which lane had the fault without reading FIR status from each lane.
-#define     ei4_rx_pl_fir_err_clear                               0xFFFE     // Clear mask
-
-// ei4_rx_fir2_pg Register field name                                       data value   Description
-#define     ei4_rx_pg_fir2_errs_err_sls_hndshk_sm                 0x0200     //A Per-Group Register or State Machine Parity Error has occurred.  RXCTL SLS Handshake SM Parity Error.
-#define     ei4_rx_pg_fir2_errs_clear                             0x01FF     // Clear mask
-
-// ei4_rx_fir1_mask_pg Register field name                                  data value   Description
-#define     ei4_rx_pg_fir1_errs_mask_clear                        0x0003     // Clear mask
-#define     ei4_rx_pl_fir_err_mask                                0x0001     //FIR mask for the summary bit that indicates an RX register or state machine parity error has occurred. This mask bit is used to block ALL per-lane parity errors from causing a FIR error.
-#define     ei4_rx_pl_fir_err_mask_clear                          0xFFFE     // Clear mask
-
-// ei4_rx_fir2_mask_pg Register field name                                  data value   Description
-#define     ei4_rx_pg_fir2_errs_mask_mask_sls_hndshk_sm           0x0200     //FIR mask for register or state machine parity checkers in per-group RX logic. A value of 1 masks the error from generating a FIR error.  RXCTL SLS Handshake SM Parity Error Mask.
-#define     ei4_rx_pg_fir2_errs_mask_clear                        0x01FF     // Clear mask
-
-// ei4_rx_fir1_error_inject_pg Register field name                          data value   Description
-#define     ei4_rx_pg_fir1_err_inj_1                              0x4000     //RX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     ei4_rx_pg_fir1_err_inj_inj_rpr_sm                     0x0800     //RX Per-Group Parity Error Injection  RXCTL Repair SM Parity Error Inject.
-#define     ei4_rx_pg_fir1_err_inj_inj_eyeopt_sm                  0x0C00     //RX Per-Group Parity Error Injection  RXCTL Eyeopt SM Parity Error Inject.
-#define     ei4_rx_pg_fir1_err_inj_inj_dsm_sm                     0x0400     //RX Per-Group Parity Error Injection  RXCTL Deskew SM Parity Error Inject.
-#define     ei4_rx_pg_fir1_err_inj_inj_rxdsm_sm                   0x0400     //RX Per-Group Parity Error Injection  RXCTL RX Deskew SM Parity Error Inject.
-#define     ei4_rx_pg_fir1_err_inj_clear                          0x0003     // Clear mask
-
-// ei4_rx_fir2_error_inject_pg Register field name                          data value   Description
-#define     ei4_rx_pg_fir2_err_inj_1                              0x2000     //RX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     ei4_rx_pg_fir2_err_inj_inj_sls_hndshk_sm              0x0200     //RX Per-Group Parity Error Injection  RXCTL SLS Handshake SM Parity Error Inject.
-#define     ei4_rx_pg_fir2_err_inj_clear                          0x01FF     // Clear mask
-
-// ei4_rx_fir_training_pg Register field name                               data value   Description
-#define     ei4_rx_pg_fir_training_error                          0x8000     //This field is now defunct and is permanently masked in the ei4_rx_fir_training_mask_pg FIR isolation register.
-#define     ei4_rx_pg_fir_training_error_clear                    0x7FFF     // Clear mask
-#define     ei4_rx_pg_fir_static_spare_deployed                   0x4000     //A spare lane has been deployed during training to heal a lane that was detected as bad. ei4_rx_Static_Spare_Deployed (SSD) will be set after the repair training step if during training either wiretest, deskew, eyeopt or repair has detected one or more bad lanes have been detected. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed and the ei4_rx_bad_lane.
-#define     ei4_rx_pg_fir_static_spare_deployed_clear             0xBFFF     // Clear mask
-#define     ei4_rx_pg_fir_static_max_spares_exceeded              0x2000     //A lane has been detected as bad during training but there are no spare lanes available to heal it. THIS FIR WILL NOT BE SET UNTIL THE REPAIR TRAINING STEP HAS BEEN RUN. THIS IS A CATASTROPHIC FAILURE FOR THE BUS WHEN IN MISSION MODE BUT ALL TRAINING STEPS WILL STILL BE RUN ON WHATEVER GOOD LANES THERE ARE. ei4_rx_static_max_spares_exceeded will be set if wiretest, deskew, eyeopt or repair find the excessive number of bad lanes.
-#define     ei4_rx_pg_fir_static_max_spares_exceeded_clear        0xDFFF     // Clear mask
-#define     ei4_rx_pg_fir_dynamic_repair_error                    0x1000     //A Dynamic Repair error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic.
-#define     ei4_rx_pg_fir_dynamic_repair_error_clear              0xEFFF     // Clear mask
-#define     ei4_rx_pg_fir_dynamic_spare_deployed                  0x0800     //A spare lane has been deployed by ECC/CRC logic to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed.
-#define     ei4_rx_pg_fir_dynamic_spare_deployed_clear            0xF7FF     // Clear mask
-#define     ei4_rx_pg_fir_dynamic_max_spares_exceeded             0x0400     //A lane has been detected as bad by ECC/CRC logic but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS.
-#define     ei4_rx_pg_fir_dynamic_max_spares_exceeded_clear       0xFBFF     // Clear mask
-#define     ei4_rx_pg_fir_recal_error                             0x0200     //A Recalibration Error has occurred. The Recal Error FFDC registers should be read to help isolate to a particular piece of logic.
-#define     ei4_rx_pg_fir_recal_error_clear                       0xFDFF     // Clear mask
-#define     ei4_rx_pg_fir_recal_spare_deployed                    0x0100     //A spare lane has been deployed during Recal to heal a lane that was detected as bad. The ei4_rx_bad_lane_enc_gcrmsg_pg register can be read to isolate which lane(s) were healed.
-#define     ei4_rx_pg_fir_recal_spare_deployed_clear              0xFEFF     // Clear mask
-#define     ei4_rx_pg_fir_recal_max_spares_exceeded               0x0080     //A lane has been detected as bad during Recal but there are no spare lanes to heal it. THIS IS A CATASTROPHIC FAILURE FOR THE BUS.
-#define     ei4_rx_pg_fir_recal_max_spares_exceeded_clear         0xFF7F     // Clear mask
-#define     ei4_rx_pg_fir_too_many_bus_errors                     0x0040     //More than one lane has been detected as having too many errors during functional operation. THIS IS A CATASTROPHIC FAILURE FOR THE BUS.
-#define     ei4_rx_pg_fir_too_many_bus_errors_clear               0xFFBF     // Clear mask
-
-// ei4_rx_fir_training_mask_pg Register field name                          data value   Description
-#define     ei4_rx_pg_fir_training_error_mask                     0x8000     //FIR mask for ei4_rx_pg_fir_training_error.
-#define     ei4_rx_pg_fir_training_error_mask_clear               0x7FFF     // Clear mask
-#define     ei4_rx_pg_fir_static_spare_deployed_mask              0x4000     //FIR mask for ei4_rx_pg_fir_static_spare_deployed.
-#define     ei4_rx_pg_fir_static_spare_deployed_mask_clear        0xBFFF     // Clear mask
-#define     ei4_rx_pg_fir_static_max_spares_exceeded_mask         0x2000     //FIR mask for ei4_rx_pg_fir_static_max_spares_exceeded
-#define     ei4_rx_pg_fir_static_max_spares_exceeded_mask_clear   0xDFFF     // Clear mask
-#define     ei4_rx_pg_fir_dynamic_repair_error_mask               0x1000     //FIR mask for ei4_rx_pg_fir_dynamic_repair_error
-#define     ei4_rx_pg_fir_dynamic_repair_error_mask_clear         0xEFFF     // Clear mask
-#define     ei4_rx_pg_fir_dynamic_spare_deployed_mask             0x0800     //FIR mask for ei4_rx_pg_fir_dynamic_spare_deployed.
-#define     ei4_rx_pg_fir_dynamic_spare_deployed_mask_clear       0xF7FF     // Clear mask
-#define     ei4_rx_pg_fir_dynamic_max_spares_exceeded_mask        0x0400     //FIR mask for ei4_rx_pg_fir_dynamic_max_spares_exceeded.
-#define     ei4_rx_pg_fir_dynamic_max_spares_exceeded_mask_clear  0xFBFF     // Clear mask
-#define     ei4_rx_pg_fir_recal_error_mask                        0x0200     //FIR mask for ei4_rx_pg_fir_recal_error.
-#define     ei4_rx_pg_fir_recal_error_mask_clear                  0xFDFF     // Clear mask
-#define     ei4_rx_pg_fir_recal_spare_deployed_mask               0x0100     //FIR mask for ei4_rx_pg_fir_recal_spare_deployed.
-#define     ei4_rx_pg_fir_recal_spare_deployed_mask_clear         0xFEFF     // Clear mask
-#define     ei4_rx_pg_fir_recal_max_spares_exceeded_mask          0x0080     //FIR mask for ei4_rx_pg_fir_recal_max_spares_exceeded.
-#define     ei4_rx_pg_fir_recal_max_spares_exceeded_mask_clear    0xFF7F     // Clear mask
-#define     ei4_rx_pg_fir_too_many_bus_errors_mask                0x0040     //FIR mask for ei4_rx_pg_fir_too_many_bus_errors.
-#define     ei4_rx_pg_fir_too_many_bus_errors_mask_clear          0xFFBF     // Clear mask
-
-// ei4_rx_timeout_sel1_pg Register field name                               data value   Description
-#define     ei4_rx_eo_offset_timeout_sel_tap1                     0x2000     //Selects Latch offset timeout.   128k UI or 13.6us 
-#define     ei4_rx_eo_offset_timeout_sel_tap2                     0x4000     //Selects Latch offset timeout.   256k UI or 27.3us 
-#define     ei4_rx_eo_offset_timeout_sel_tap3                     0x6000     //Selects Latch offset timeout.   1M UI or 109.2us 
-#define     ei4_rx_eo_offset_timeout_sel_tap4                     0x8000     //Selects Latch offset timeout.   2M UI or 218.5us 
-#define     ei4_rx_eo_offset_timeout_sel_tap5                     0xA000     //Selects Latch offset timeout.   4M UI or 436.9us 
-#define     ei4_rx_eo_offset_timeout_sel_tap6                     0xC000     //Selects Latch offset timeout.   8M UI or 873.8us 
-#define     ei4_rx_eo_offset_timeout_sel_tap7                     0xE000     //Selects Latch offset timeout.   infinite
-#define     ei4_rx_eo_offset_timeout_sel_clear                    0x1FFF     // Clear mask
-#define     ei4_rx_eo_vref_timeout_sel_tap1                       0x0400     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   128k UI or 13.6us 
-#define     ei4_rx_eo_vref_timeout_sel_tap2                       0x0800     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   256k UI or 27.3us 
-#define     ei4_rx_eo_vref_timeout_sel_tap3                       0x0C00     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   1M UI or 109.2us 
-#define     ei4_rx_eo_vref_timeout_sel_tap4                       0x1000     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   2M UI or 218.5us 
-#define     ei4_rx_eo_vref_timeout_sel_tap5                       0x1400     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   4M UI or 436.9us 
-#define     ei4_rx_eo_vref_timeout_sel_tap6                       0x1800     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   8M UI or 873.8us 
-#define     ei4_rx_eo_vref_timeout_sel_tap7                       0x1C00     //Selects  Vref adjust watchdog timeout (EI-4 ONLY).   infinite
-#define     ei4_rx_eo_vref_timeout_sel_clear                      0xE3FF     // Clear mask
-#define     ei4_rx_eo_ctle_timeout_sel_tap1                       0x0080     //Selects  CTLE ajdust watchdog timeout.   128k UI or 13.6us 
-#define     ei4_rx_eo_ctle_timeout_sel_tap2                       0x0100     //Selects  CTLE ajdust watchdog timeout.   256k UI or 27.3us 
-#define     ei4_rx_eo_ctle_timeout_sel_tap3                       0x0180     //Selects  CTLE ajdust watchdog timeout.   1M UI or 109.2us 
-#define     ei4_rx_eo_ctle_timeout_sel_tap4                       0x0200     //Selects  CTLE ajdust watchdog timeout.   2M UI or 218.5us 
-#define     ei4_rx_eo_ctle_timeout_sel_tap5                       0x0280     //Selects  CTLE ajdust watchdog timeout.   4M UI or 436.9us 
-#define     ei4_rx_eo_ctle_timeout_sel_tap6                       0x0300     //Selects  CTLE ajdust watchdog timeout.   8M UI or 873.8us 
-#define     ei4_rx_eo_ctle_timeout_sel_tap7                       0x0380     //Selects  CTLE ajdust watchdog timeout.   infinite
-#define     ei4_rx_eo_ctle_timeout_sel_clear                      0xFC7F     // Clear mask
-#define     ei4_rx_eo_et_timeout_sel_tap1                         0x0002     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   128k UI or 13.6us 
-#define     ei4_rx_eo_et_timeout_sel_tap2                         0x0004     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   256k UI or 27.3us 
-#define     ei4_rx_eo_et_timeout_sel_tap3                         0x0006     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   1M UI or 109.2us 
-#define     ei4_rx_eo_et_timeout_sel_tap4                         0x0008     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   2M UI or 218.5us 
-#define     ei4_rx_eo_et_timeout_sel_tap5                         0x000A     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   4M UI or 436.9us 
-#define     ei4_rx_eo_et_timeout_sel_tap6                         0x000C     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   8M UI or 873.8us 
-#define     ei4_rx_eo_et_timeout_sel_tap7                         0x000E     //Selects  Measure eye watchdog timeout (EI-4 ONLY).   infinite
-#define     ei4_rx_eo_et_timeout_sel_clear                        0xFF11     // Clear mask
-#define     ei4_rx_eo_final_l2u_timeout_sel                       0x0001     //Selects Final Load to Unload Delay qualification time per step. 
-#define     ei4_rx_eo_final_l2u_timeout_sel_clear                 0xFFFE     // Clear mask
-
-// ei4_rx_lane_bad_vec_0_15_pg Register field name                          data value   Description
-#define     ei4_rx_lane_bad_vec_0_15_clear                        0x0000     // Clear mask
-
-// ei4_rx_lane_bad_vec_16_31_pg Register field name                         data value   Description
-#define     ei4_rx_lane_bad_vec_16_31                             0x0000     //Lanes found bad by HW (status) or method to force lane bad from software (control).
-#define     ei4_rx_lane_bad_vec_16_31_clear                       0x0000     // Clear mask
-
-// ei4_rx_lane_disabled_vec_0_15_pg Register field name                     data value   Description
-#define     ei4_rx_lane_disabled_vec_0_15                         0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     ei4_rx_lane_disabled_vec_0_15_clear                   0x0000     // Clear mask
-
-// ei4_rx_lane_disabled_vec_16_31_pg Register field name                    data value   Description
-#define     ei4_rx_lane_disabled_vec_16_31                        0x0000     //Lanes disabled by HW (status) or method to force lane to be disabled (save power) from software (control).
-#define     ei4_rx_lane_disabled_vec_16_31_clear                  0x0000     // Clear mask
-
-// ei4_rx_lane_swapped_vec_0_15_pg Register field name                      data value   Description
-#define     ei4_rx_lane_swapped_vec_0_15                          0x0000     //Wiretest found that the P & N wire legs have been swapped on the lane indicated. Has the effect of basically inverting the signal.  Note that this status is invalid if the lane is marked bad.
-#define     ei4_rx_lane_swapped_vec_0_15_clear                    0x0000     // Clear mask
-
-// ei4_rx_lane_swapped_vec_16_31_pg Register field name                     data value   Description
-#define     ei4_rx_lane_swapped_vec_16_31                         0x0000     //Wiretest found that the P & N wire legs have been swapped on the lane indicated. Has the effect of basically inverting the signal.  Note that this status is invalid if the lane is marked bad.
-#define     ei4_rx_lane_swapped_vec_16_31_clear                   0x0000     // Clear mask
-
-// ei4_rx_init_state_pg Register field name                                 data value   Description
-#define     ei4_rx_main_init_state_1                              0x1000     //Main Initialization State Machine(RJR):  Wiretest Running
-#define     ei4_rx_main_init_state_2                              0x2000     //Main Initialization State Machine(RJR):  Deskew Running
-#define     ei4_rx_main_init_state_3                              0x3000     //Main Initialization State Machine(RJR):  Eye Optimization Running
-#define     ei4_rx_main_init_state_4                              0x4000     //Main Initialization State Machine(RJR):  Repair Running
-#define     ei4_rx_main_init_state_5                              0x5000     //Main Initialization State Machine(RJR):  Go Functional Running
-#define     ei4_rx_main_init_state_6                              0x9000     //Main Initialization State Machine(RJR):  Wiretest Failed
-#define     ei4_rx_main_init_state_7                              0x5000     //Main Initialization State Machine(RJR):  Deskew Failed
-#define     ei4_rx_main_init_state_8                              0xB000     //Main Initialization State Machine(RJR):  Eye Optimization Failed
-#define     ei4_rx_main_init_state_9                              0xC000     //Main Initialization State Machine(RJR):  Repair Failed
-#define     ei4_rx_main_init_state_10                             0xD000     //Main Initialization State Machine(RJR):  Go Functional Failed
-#define     ei4_rx_main_init_state_clear                          0x0FFF     // Clear mask
-
-// ei4_rx_wiretest_state_pg Register field name                             data value   Description
-#define     ei4_rx_wtm_state_clear                                0x07FF     // Clear mask
-#define     ei4_rx_wtr_state_clear                                0xF87F     // Clear mask
-#define     ei4_rx_wtl_state_clear                                0x0FE0     // Clear mask
-
-// ei4_rx_wiretest_laneinfo_pg Register field name                          data value   Description
-#define     ei4_rx_wtr_cur_lane                                   0x0000     //Wiretest Current Lane Under Test(RJR)
-#define     ei4_rx_wtr_cur_lane_clear                             0x07FF     // Clear mask
-#define     ei4_rx_wtr_max_bad_lanes_clear                        0xF83F     // Clear mask
-#define     ei4_rx_wtr_bad_lane_count                             0x0000     //Wiretest Current Number Of Bad Lanes in This Clk Group(RJR)
-#define     ei4_rx_wtr_bad_lane_count_clear                       0x07E0     // Clear mask
-
-// ei4_rx_wiretest_gcrmsgs_pg Register field name                           data value   Description
-#define     ei4_rx_wt_prev_done_gcrmsg                            0x8000     //GCR Message: Previous Clk Group Has Completed Wiretest
-#define     ei4_rx_wt_prev_done_gcrmsg_clear                      0x7FFF     // Clear mask
-#define     ei4_rx_wt_all_done_gcrmsg                             0x4000     //GCR Message: All Clk Groups Have Completed Wiretest
-#define     ei4_rx_wt_all_done_gcrmsg_clear                       0xBFFF     // Clear mask
-
-// ei4_rx_deskew_gcrmsgs_pg Register field name                             data value   Description
-#define     ei4_rx_deskew_seq_gcrmsg_dsalldeskewed                0x2000     //GCR Message: RX Deskew Sequencer GCR messages  Indicate all groups deskewed.
-#define     ei4_rx_deskew_seq_gcrmsg_dsprevdone                   0x4000     //GCR Message: RX Deskew Sequencer GCR messages  Indicate prior group completed deskew.
-#define     ei4_rx_deskew_seq_gcrmsg_dsalldone                    0x6000     //GCR Message: RX Deskew Sequencer GCR messages  Indicate all groups completed deskew.
-#define     ei4_rx_deskew_seq_gcrmsg_dsprevskew                   0x8000     //GCR Message: RX Deskew Sequencer GCR messages  Transmit skew values from prior group.
-#define     ei4_rx_deskew_seq_gcrmsg_dsmaxskew                    0xA000     //GCR Message: RX Deskew Sequencer GCR messages  Transmit max skew values to all groups.
-#define     ei4_rx_deskew_seq_gcrmsg_unused                       0xC000     //GCR Message: RX Deskew Sequencer GCR messages  Unused.
-#define     ei4_rx_deskew_seq_gcrmsg_dsnomsg                      0xE000     //GCR Message: RX Deskew Sequencer GCR messages  No message.
-#define     ei4_rx_deskew_seq_gcrmsg_clear                        0x1FFF     // Clear mask
-#define     ei4_rx_deskew_skmin_gcrmsg                            0x0000     //GCR Message: Min Skew Value for deskew sequence.
-#define     ei4_rx_deskew_skmin_gcrmsg_clear                      0xF03F     // Clear mask
-#define     ei4_rx_deskew_skmax_gcrmsg                            0x0000     //GCR Message: Max Skew Value for deskew sequence.
-#define     ei4_rx_deskew_skmax_gcrmsg_clear                      0x0FC0     // Clear mask
-
-// ei4_rx_deskew_state_pg Register field name                               data value   Description
-#define     ei4_rx_dsm_state_clear                                0x00FF     // Clear mask
-#define     ei4_rx_rxdsm_state_clear                              0x7F80     // Clear mask
-
-// ei4_rx_deskew_mode_pg Register field name                                data value   Description
-#define     ei4_rx_deskew_max_limit                               0x0000     //Maximum Deskewable Skew Fail Threshold
-#define     ei4_rx_deskew_max_limit_clear                         0x03FF     // Clear mask
-
-// ei4_rx_deskew_status_pg Register field name                              data value   Description
-#define     ei4_rx_deskew_minskew_grp                             0x0000     //Deskew Per-Group Raw Skew Min
-#define     ei4_rx_deskew_minskew_grp_clear                       0x03FF     // Clear mask
-#define     ei4_rx_deskew_maxskew_grp                             0x0000     //Deskew Per-Group Raw Skew Max
-#define     ei4_rx_deskew_maxskew_grp_clear                       0xFC0F     // Clear mask
-
-// ei4_rx_bad_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_rx_bad_lane1_gcrmsg                               0x0000     //GCR Message: Encoded bad lane one in relation to the entire RX bus
-#define     ei4_rx_bad_lane1_gcrmsg_clear                         0x01FF     // Clear mask
-#define     ei4_rx_bad_lane2_gcrmsg                               0x0000     //GCR Message: Encoded bad lane two in relation to the entire RX bus
-#define     ei4_rx_bad_lane2_gcrmsg_clear                         0xFE03     // Clear mask
-#define     ei4_rx_bad_lane_code_gcrmsg_bad_ln1_val               0x0001     //GCR Message: RX Bad Lane Code  Bad Lane 1 Valid
-#define     ei4_rx_bad_lane_code_gcrmsg_bad_lns12_val             0x0002     //GCR Message: RX Bad Lane Code  Bad Lanes 1 and 2 Valid
-#define     ei4_rx_bad_lane_code_gcrmsg_3plus_bad_lns             0x0003     //GCR Message: RX Bad Lane Code  3+ bad lanes
-#define     ei4_rx_bad_lane_code_gcrmsg_clear                     0xFFF0     // Clear mask
-
-// ei4_rx_static_repair_state_pg Register field name                        data value   Description
-#define     ei4_rx_rpr_state_clear                                0x03FF     // Clear mask
-
-// ei4_rx_ei4_tx_bus_info_pg Register field name                                data value   Description
-#define     ei4_rx_ei4_tx_bus_width                                   0x0000     //TX Bus Width
-#define     ei4_rx_ei4_tx_bus_width_clear                             0x01FF     // Clear mask
-#define     ei4_rx_ei4_rx_bus_width                                   0x0000     //RX Bus Width
-#define     ei4_rx_ei4_rx_bus_width_clear                             0xFE03     // Clear mask
-
-// ei4_rx_sls_lane_enc_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_rx_sls_lane_gcrmsg                                0x0000     //GCR Message: Encoded SLS lane in relation to the entire RX bus
-#define     ei4_rx_sls_lane_gcrmsg_clear                          0x01FF     // Clear mask
-#define     ei4_rx_sls_lane_val_gcrmsg                            0x0100     //GCR Message: RX SLS Lane Valid
-#define     ei4_rx_sls_lane_val_gcrmsg_clear                      0xFEFF     // Clear mask
-
-// ei4_rx_fence_pg Register field name                                      data value   Description
-#define     ei4_rx_fence                                          0x8000     //RX fence bit
-#define     ei4_rx_fence_clear                                    0x7FFF     // Clear mask
-
-// ei4_rx_term_pg Register field name                                       data value   Description
-#define     ei4_rx_term_test_mode                                 0x8000     //Termination Segment Test mode
-#define     ei4_rx_term_test_mode_clear                           0x7FFF     // Clear mask
-#define     ei4_rx_term_mode_enc                                  0x0000     //Slice enable for pfet/nfet pairs for termination mode.  Bits 0:3 determine how many 240ohm pairs to enable, out of 14.  Bit 4 enables a half-strength 480ohm pfet/nfet pair, and also controls whether that pair is enabled in test mode.
-#define     ei4_rx_term_mode_enc_clear                            0xE0FF     // Clear mask
-
-// ei4_rx_timeout_sel2_pg Register field name                               data value   Description
-#define     ei4_rx_func_mode_timeout_sel_tap1                     0x2000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   128k UI or 13.7us 
-#define     ei4_rx_func_mode_timeout_sel_tap2                     0x4000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   256k UI or 27.3us 
-#define     ei4_rx_func_mode_timeout_sel_tap3                     0x6000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   512k UI or 54.6us 
-#define     ei4_rx_func_mode_timeout_sel_tap4                     0x8000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   1M UI or 109.2us 
-#define     ei4_rx_func_mode_timeout_sel_tap5                     0xA000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   2M UI or 218.5us 
-#define     ei4_rx_func_mode_timeout_sel_tap6                     0xC000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   64M UI or 7ms
-#define     ei4_rx_func_mode_timeout_sel_tap7                     0xE000     //Selects Functional Mode wait timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   infinite
-#define     ei4_rx_func_mode_timeout_sel_clear                    0x1FFF     // Clear mask
-#define     ei4_rx_rc_slowdown_timeout_sel_tap1                   0x0400     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   128k UI or 13.7us 
-#define     ei4_rx_rc_slowdown_timeout_sel_tap2                   0x0800     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   256k UI or 27.3us 
-#define     ei4_rx_rc_slowdown_timeout_sel_tap3                   0x0C00     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   512k UI or 54.6us 
-#define     ei4_rx_rc_slowdown_timeout_sel_tap4                   0x1000     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   1M UI or 109.2us 
-#define     ei4_rx_rc_slowdown_timeout_sel_tap5                   0x1400     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   2M UI or 218.5us 
-#define     ei4_rx_rc_slowdown_timeout_sel_tap6                   0x1800     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   64M UI or 7ms
-#define     ei4_rx_rc_slowdown_timeout_sel_tap7                   0x1C00     //Selects Recal  Slowdown      timeout. Note that his should be longer than ei4_rx_sls_timeout_sel.   infinite
-#define     ei4_rx_rc_slowdown_timeout_sel_clear                  0xE3FF     // Clear mask
-#define     ei4_rx_pup_lite_wait_sel_tap1                         0x0100     //How long to wait for analog logic to power up an unused spare lane for recal/repair  107ns (default value
-#define     ei4_rx_pup_lite_wait_sel_tap2                         0x0200     //How long to wait for analog logic to power up an unused spare lane for recal/repair  213ns
-#define     ei4_rx_pup_lite_wait_sel_tap3                         0x0300     //How long to wait for analog logic to power up an unused spare lane for recal/repair  427ns
-#define     ei4_rx_pup_lite_wait_sel_clear                        0xFCFF     // Clear mask
-
-// ei4_rx_dyn_rpr_pg Register field name                                    data value   Description
-#define     ei4_rx_dyn_rpr_state_clear                            0xC0FF     // Clear mask
-#define     ei4_rx_sls_hndshk_state_clear                         0xFF00     // Clear mask
-
-// ei4_rx_dyn_rpr_gcrmsg_pg Register field name                             data value   Description
-#define     ei4_rx_dyn_rpr_req_gcrmsg                             0x8000     //GCR Message: CRC/ECC Tallying logic has a Dynamic Repair Request
-#define     ei4_rx_dyn_rpr_req_gcrmsg_clear                       0x7FFF     // Clear mask
-#define     ei4_rx_dyn_rpr_lane2rpr_gcrmsg                        0x0000     //GCR Message: CRC/ECC Tallying logic bad lane to repair
-#define     ei4_rx_dyn_rpr_lane2rpr_gcrmsg_clear                  0x80FF     // Clear mask
-#define     ei4_rx_dyn_rpr_ip_gcrmsg                              0x0080     //GCR Message: CRC/ECC Bad Lane Repair In Progress
-#define     ei4_rx_dyn_rpr_ip_gcrmsg_clear                        0xFF7F     // Clear mask
-#define     ei4_rx_dyn_rpr_complete_gcrmsg                        0x0040     //GCR Message: CRC/ECC Bad Lane Repaired
-#define     ei4_rx_dyn_rpr_complete_gcrmsg_clear                  0xFFBF     // Clear mask
-
-// ei4_rx_dyn_rpr_err_tallying1_pg Register field name                      data value   Description
-#define     ei4_rx_dyn_rpr_bad_lane_max                           0x0000     //CRC/ECC Dynamic Repair: Max number of times a lane can be found bad before repaired
-#define     ei4_rx_dyn_rpr_bad_lane_max_clear                     0x01FF     // Clear mask
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap1                0x0020     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  853.0ns & 1.3uS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap2                0x0040     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  27.3uS & 41.0uS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap3                0x0060     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  873.5uS & 1.3mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap4                0x0080     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  1.7mS & 2.6mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap5                0x00A0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  3.5mS & 5.1mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap6                0x00C0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  7.0mS & 10.5mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap7                0x00E0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  14.0mS & 21.0mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap8                0x0100     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  28.0mS & 41.9mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap9                0x0120     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  55.9mS & 83.9mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap10               0x0140     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  111.8mS & 167.8mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap11               0x0160     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  223.6mS & 335.5mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap12               0x0180     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  447.2mS & 671.1mS
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap13               0x01A0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  894.4mS & 1.3 S
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap14               0x01C0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  1.8 S & 2.7 S
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_tap15               0x01E0     //CRC/ECC Dynamic Repair: Duration the lane error counter1 can run before being cleared (determines the allowed error frequency)  infinite
-#define     ei4_rx_dyn_rpr_err_cntr1_duration_clear               0x3E1F     // Clear mask
-#define     ei4_rx_dyn_rpr_clr_err_cntr1                          0x0010     //CRC/ECC Dynamic Repair: Firmware-based clear of lane error counter1 register
-#define     ei4_rx_dyn_rpr_clr_err_cntr1_clear                    0xFFEF     // Clear mask
-#define     ei4_rx_dyn_rpr_disable                                0x0008     //CRC/ECC Dynamic Repair: When set, disables dynamic repair error tallying (both per lane and per bus error counters...cntr1 & cntr2)
-#define     ei4_rx_dyn_rpr_disable_clear                          0xFFF7     // Clear mask
-#define     ei4_rx_dyn_rpr_enc_bad_data_lane_width                0x0000     //CRC/ECC Dynamic Repair: Width of the enc_bad_data_lane vector used to determine number of 1s in clear code
-#define     ei4_rx_dyn_rpr_enc_bad_data_lane_width_clear          0xFFB8     // Clear mask
-
-// ei4_rx_eo_final_l2u_gcrmsgs_pg Register field name                       data value   Description
-#define     ei4_rx_eo_final_l2u_dly_seq_gcrmsg_fl2uallchg         0x4000     //GCR Message: RX Final Load to Unload Delay GCR messages  Indicate all groups have calculated max load to unload change.
-#define     ei4_rx_eo_final_l2u_dly_seq_gcrmsg_unused             0x8000     //GCR Message: RX Final Load to Unload Delay GCR messages  Unused.
-#define     ei4_rx_eo_final_l2u_dly_seq_gcrmsg_fl2unomsg          0xC000     //GCR Message: RX Final Load to Unload Delay GCR messages  No message.
-#define     ei4_rx_eo_final_l2u_dly_seq_gcrmsg_clear              0x3FFF     // Clear mask
-#define     ei4_rx_eo_final_l2u_dly_maxchg_gcrmsg                 0x0000     //GCR Message: Max change in miniumum load to unload delay.
-#define     ei4_rx_eo_final_l2u_dly_maxchg_gcrmsg_clear           0xC0FF     // Clear mask
-#define     ei4_rx_eo_final_l2u_dly_chg                           0x0000     //GCR Message: Local change in miniumum load to unload delay.
-#define     ei4_rx_eo_final_l2u_dly_chg_clear                     0x3FC0     // Clear mask
-
-// ei4_rx_gcr_msg_debug_dest_ids_pg Register field name                     data value   Description
-#define     ei4_rx_gcr_msg_debug_dest_bus_id_clear                0x03FF     // Clear mask
-#define     ei4_rx_gcr_msg_debug_dest_group_id_clear              0xFC0F     // Clear mask
-
-// ei4_rx_gcr_msg_debug_src_ids_pg Register field name                      data value   Description
-#define     ei4_rx_gcr_msg_debug_src_bus_id_clear                 0x03FF     // Clear mask
-#define     ei4_rx_gcr_msg_debug_src_group_id_clear               0xFC0F     // Clear mask
-
-// ei4_rx_gcr_msg_debug_dest_addr_pg Register field name                    data value   Description
-#define     ei4_rx_gcr_msg_debug_dest_addr_clear                  0x007F     // Clear mask
-#define     ei4_rx_gcr_msg_debug_send_msg                         0x0001     //GCR Messaging Debug: Send GCR Message on rising edge of this bit.
-#define     ei4_rx_gcr_msg_debug_send_msg_clear                   0xFFFE     // Clear mask
-
-// ei4_rx_gcr_msg_debug_write_data_pg Register field name                   data value   Description
-#define     ei4_rx_gcr_msg_debug_write_data_clear                 0x0000     // Clear mask
-
-// ei4_rx_wt_clk_status_pg Register field name                              data value   Description
-#define     ei4_rx_wt_clk_lane_inverted                           0x4000     //Clock Wiretest lane inverted/swapped status 
-#define     ei4_rx_wt_clk_lane_inverted_clear                     0xBFFF     // Clear mask
-#define     ei4_rx_wt_clk_lane_bad_code_n_stuck_1                 0x0800     //Clock Wiretest Lane Bad code  N leg stuck at 1 
-#define     ei4_rx_wt_clk_lane_bad_code_n_stuck_0                 0x1000     //Clock Wiretest Lane Bad code  N leg stuck at 0 
-#define     ei4_rx_wt_clk_lane_bad_code_p_stuck_1                 0x1800     //Clock Wiretest Lane Bad code  P leg stuck at 1 
-#define     ei4_rx_wt_clk_lane_bad_code_p_stuck_0                 0x2000     //Clock Wiretest Lane Bad code  P leg stuck at 0 
-#define     ei4_rx_wt_clk_lane_bad_code_n_or_p_floating           0x2800     //Clock Wiretest Lane Bad code  N  or P leg floating or swapping undetermined 
-#define     ei4_rx_wt_clk_lane_bad_code_NOT_USED_110              0x3000     //Clock Wiretest Lane Bad code Unused.
-#define     ei4_rx_wt_clk_lane_bad_code_NOT_USED_111              0x3800     //Clock Wiretest Lane Bad code Unused.
-#define     ei4_rx_wt_clk_lane_bad_code_clear                     0xC7FF     // Clear mask
-
-// ei4_rx_wiretest_pll_cntl_pg Register field name                          data value   Description
-#define     ei4_rx_wt_cu_pll_pgood                                0x8000     //RX PLL/DLL Enable
-#define     ei4_rx_wt_cu_pll_pgood_clear                          0x7FFF     // Clear mask
-#define     ei4_rx_wt_cu_pll_reset                                0x4000     //RX PLL/DLL Enable Request
-#define     ei4_rx_wt_cu_pll_reset_clear                          0xBFFF     // Clear mask
-#define     ei4_rx_wt_cu_pll_pgooddly_50ns                        0x0800     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   Nominal 50ns Reset per PLL Spec 
-#define     ei4_rx_wt_cu_pll_pgooddly_100ns                       0x1000     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   Double Nominal 50ns Reset per PLL Spec 
-#define     ei4_rx_wt_cu_pll_pgooddly_960ui                       0x1800     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   Typical simulation delay exceeding TX PLL 40-refclk locking period 
-#define     ei4_rx_wt_cu_pll_pgooddly_unused_100                  0x2000     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   Reserved 
-#define     ei4_rx_wt_cu_pll_pgooddly_unused_101                  0x2800     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   Reserved 
-#define     ei4_rx_wt_cu_pll_pgooddly_MAX                         0x3000     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   1024 UI  
-#define     ei4_rx_wt_cu_pll_pgooddly_disable                     0x3800     //RX PLL/DLL PGOOD Delay Selects length of reset period after ei4_rx_wt_cu_pll_reset is set.   Disable ei4_rx_wt_cu_pll_reset
-#define     ei4_rx_wt_cu_pll_pgooddly_clear                       0xC7FF     // Clear mask
-#define     ei4_rx_wt_cu_pll_lock                                 0x0400     //RX PLL/DLL Locked
-#define     ei4_rx_wt_cu_pll_lock_clear                           0xFBFF     // Clear mask
-#define     ei4_rx_wt_pll_refclksel                               0x0200     //Select between IO clock and BIST/Refclock
-#define     ei4_rx_wt_pll_refclksel_clear                         0xFDFF     // Clear mask
-
-// ei4_rx_eo_step_cntl_pg Register field name                               data value   Description
-#define     ei4_rx_eo_enable_latch_offset_cal                     0x8000     //RX eye optimization latch offset adjustment enable
-#define     ei4_rx_eo_enable_latch_offset_cal_clear               0x7FFF     // Clear mask
-#define     ei4_rx_eo_enable_ctle_cal                             0x4000     //RX eye optimization CTLE/Peakin enable
-#define     ei4_rx_eo_enable_ctle_cal_clear                       0xBFFF     // Clear mask
-#define     ei4_rx_eo_enable_vref_cal                             0x1000     //RX eye optimization VRef adjust enable
-#define     ei4_rx_eo_enable_vref_cal_clear                       0xEFFF     // Clear mask
-#define     ei4_rx_eo_enable_measure_eye_width                    0x0100     //RX eye optimization Eye width check enable
-#define     ei4_rx_eo_enable_measure_eye_width_clear              0xFEFF     // Clear mask
-#define     ei4_rx_eo_enable_final_l2u_adj                        0x0080     //RX eye optimization Final RX FIFO load-to-unload delay adjustment enable
-#define     ei4_rx_eo_enable_final_l2u_adj_clear                  0xFF7F     // Clear mask
-#define     ei4_rx_eo_enable_ber_test                             0x0040     //RX eye optimization Bit error rate test enable
-#define     ei4_rx_eo_enable_ber_test_clear                       0xFFBF     // Clear mask
-#define     ei4_rx_eo_enable_result_check                         0x0020     //RX eye optimization Final results check enable
-#define     ei4_rx_eo_enable_result_check_clear                   0xFFDF     // Clear mask
-
-// ei4_rx_eo_step_stat_pg Register field name                               data value   Description
-#define     ei4_rx_eo_latch_offset_done                           0x8000     //RX eye optimization latch offset adjustment done
-#define     ei4_rx_eo_latch_offset_done_clear                     0x7FFF     // Clear mask
-#define     ei4_rx_eo_ctle_done                                   0x4000     //RX eye optimization CTLE/Peaking done
-#define     ei4_rx_eo_ctle_done_clear                             0xBFFF     // Clear mask
-#define     ei4_rx_eo_vref_done                                   0x1000     //RX eye optimization VRef adjust done
-#define     ei4_rx_eo_vref_done_clear                             0xEFFF     // Clear mask
-#define     ei4_rx_eo_measure_eye_width_done                      0x0100     //RX eye optimization Eye width check done
-#define     ei4_rx_eo_measure_eye_width_done_clear                0xFEFF     // Clear mask
-#define     ei4_rx_eo_final_l2u_adj_done                          0x0080     //RX eye optimization Final RX FIFO load-to-unload adjust done
-#define     ei4_rx_eo_final_l2u_adj_done_clear                    0xFF7F     // Clear mask
-#define     ei4_rx_eo_result_check_done                           0x0010     //RX eye optimization Eye width/heightER check done 
-#define     ei4_rx_eo_result_check_done_clear                     0xFFEF     // Clear mask
-
-// ei4_rx_eo_step_fail_pg Register field name                               data value   Description
-#define     ei4_rx_eo_latch_offset_failed                         0x8000     //RX eye optimization latch offset adjustment  failed
-#define     ei4_rx_eo_latch_offset_failed_clear                   0x7FFF     // Clear mask
-#define     ei4_rx_eo_ctle_failed                                 0x4000     //RX eye optimization CTLE/Peaking  failed
-#define     ei4_rx_eo_ctle_failed_clear                           0xBFFF     // Clear mask
-#define     ei4_rx_eo_vref_failed                                 0x1000     //RX eye optimization VRef adjust  failed
-#define     ei4_rx_eo_vref_failed_clear                           0xEFFF     // Clear mask
-#define     ei4_rx_eo_measure_eye_width_failed                    0x0100     //RX eye optimization Measure eye width failed
-#define     ei4_rx_eo_measure_eye_width_failed_clear              0xFEFF     // Clear mask
-#define     ei4_rx_eo_final_l2u_adj_failed                        0x0080     //RX eye optimization Final RX FIFO load-to-unload adjust  failed
-#define     ei4_rx_eo_final_l2u_adj_failed_clear                  0xFF7F     // Clear mask
-#define     ei4_rx_eo_result_check_failed                         0x0040     //RX eye optimization Final Result checking failed
-#define     ei4_rx_eo_result_check_failed_clear                   0xFFBF     // Clear mask
-
-// ei4_rx_amp_val_pg Register field name                                    data value   Description
-#define     ei4_rx_amp_peak_work                                  0x0000     //Rx amp peak working register
-#define     ei4_rx_amp_peak_work_clear                            0x0FFF     // Clear mask
-
-// ei4_rx_sls_rcvy_pg Register field name                                   data value   Description
-#define     ei4_rx_sls_rcvy_disable                               0x8000     //Disable SLS Recovery
-#define     ei4_rx_sls_rcvy_disable_clear                         0x7FFF     // Clear mask
-#define     ei4_rx_sls_rcvy_state_clear                           0xE0FF     // Clear mask
-
-// ei4_rx_sls_rcvy_gcrmsg_pg Register field name                            data value   Description
-#define     ei4_rx_sls_rcvy_req_gcrmsg                            0x8000     //GCR Message: SLS Rcvy; RX Lane Repair Req
-#define     ei4_rx_sls_rcvy_req_gcrmsg_clear                      0x7FFF     // Clear mask
-#define     ei4_rx_sls_rcvy_ip_gcrmsg                             0x4000     //GCR Message: SLS Rcvy; RX Lane Repair IP
-#define     ei4_rx_sls_rcvy_ip_gcrmsg_clear                       0xBFFF     // Clear mask
-#define     ei4_rx_sls_rcvy_done_gcrmsg                           0x2000     //GCR Message: SLS Rcvy; RX Lane Repair Done
-#define     ei4_rx_sls_rcvy_done_gcrmsg_clear                     0xDFFF     // Clear mask
-
-// ei4_rx_ei4_tx_lane_info_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_rx_ei4_tx_bad_lane_cntr_gcrmsg                        0x0000     //GCR Message: RX Side TX Bad Lane Counter
-#define     ei4_rx_ei4_tx_bad_lane_cntr_gcrmsg_clear                  0x3FFF     // Clear mask
-
-// ei4_rx_err_tallying_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_rx_dis_synd_tallying_gcrmsg                       0x8000     //GCR Message: Disable Syndrome Tallying
-#define     ei4_rx_dis_synd_tallying_gcrmsg_clear                 0x7FFF     // Clear mask
-
-// ei4_rx_trace_pg Register field name                                      data value   Description
-#define     ei4_rx_trc_mode_tap1                                  0x1000     //RX Trace Mode  Dynamic Repair State Machines
-#define     ei4_rx_trc_mode_tap2                                  0x2000     //RX Trace Mode  SLS Handshake State Machines with Recovery
-#define     ei4_rx_trc_mode_tap3                                  0x3000     //RX Trace Mode  Dynamic Recal State Machines
-#define     ei4_rx_trc_mode_tap4                                  0x4000     //RX Trace Mode  Recal Handshake State Machine with Recovery
-#define     ei4_rx_trc_mode_tap5                                  0x5000     //RX Trace Mode  CRC or ECC Tallying Logic
-#define     ei4_rx_trc_mode_tap6                                  0x6000     //RX Trace Mode  RX SLS Commands
-#define     ei4_rx_trc_mode_tap7                                  0x7000     //RX Trace Mode  RX Bad Lanes
-#define     ei4_rx_trc_mode_tap8                                  0x8000     //RX Trace Mode  RX SLS Lanes
-#define     ei4_rx_trc_mode_tap9                                  0x9000     //RX Trace Mode  GCR
-#define     ei4_rx_trc_mode_tap10                                 0xA000     //RX Trace Mode  Per Lane / Per Pack Trace (see ei4_rx_pp_trc_mode for details
-#define     ei4_rx_trc_mode_tap11                                 0xB000     //RX Trace Mode  TBD
-#define     ei4_rx_trc_mode_tap12                                 0xC000     //RX Trace Mode  TBD
-#define     ei4_rx_trc_mode_tap13                                 0xD000     //RX Trace Mode  TBD
-#define     ei4_rx_trc_mode_tap14                                 0xE000     //RX Trace Mode  TBD
-#define     ei4_rx_trc_mode_tap15                                 0xF000     //RX Trace Mode  TBD
-#define     ei4_rx_trc_mode_clear                                 0x0FFF     // Clear mask
-#define     ei4_rx_trc_grp_clear                                  0xFC0F     // Clear mask
-
-// ei4_rx_rdt_cntl_pg Register field name                                   data value   Description
-#define     ei4_rx_run_rdt                                        0x8000     //RCV RDT pattern 0:(0) RDT off 
-#define     ei4_rx_run_rdt_clear                                  0x7FFF     // Clear mask
-#define     ei4_rx_rdt_check_mask                                 0x0000     //RCV RDT bit mask:  11111 checks all bits, otherwise only check the bit specified
-#define     ei4_rx_rdt_check_mask_clear                           0xC1FF     // Clear mask
-#define     ei4_rx_rdt_failed                                     0x0100     //RCV RDT FAILED
-#define     ei4_rx_rdt_failed_clear                               0xFEFF     // Clear mask
-
-// ei4_rx_rc_step_cntl_pg Register field name                               data value   Description
-#define     ei4_rx_rc_enable_edge_track                           0x1000     //RX recalibration    Eye tracking
-#define     ei4_rx_rc_enable_edge_track_clear                     0xEFFF     // Clear mask
-#define     ei4_rx_rc_enable_measure_eye_width                    0x0100     //RX recalibration    Eye width check enable
-#define     ei4_rx_rc_enable_measure_eye_width_clear              0xFEFF     // Clear mask
-#define     ei4_rx_rc_enable_result_check                         0x0040     //RX recalibration    Final results check enable
-#define     ei4_rx_rc_enable_result_check_clear                   0xFFBF     // Clear mask
-#define     ei4_rx_rc_enable_dll_update                           0x0020     //RX recalibration    DLL update enable
-#define     ei4_rx_rc_enable_dll_update_clear                     0xFFDF     // Clear mask
-
-// ei4_rx_eo_recal_pg Register field name                                   data value   Description
-#define     ei4_rx_eye_opt_state                                  0x0000     //Common EDI/EI4 Eye optimizaton State Machine
-#define     ei4_rx_eye_opt_state_clear                            0x00FF     // Clear mask
-#define     ei4_rx_recal_state                                    0x0000     //Common EDI/EI4 recalibration State Machine
-#define     ei4_rx_recal_state_clear                              0xFF00     // Clear mask
-
-// ei4_rx_servo_ber_count_pg Register field name                            data value   Description
-#define     ei4_rx_servo_ber_count_work                           0x0000     //Rx servo-based bit error rate count working register
-#define     ei4_rx_servo_ber_count_work_clear                     0x000F     // Clear mask
-
-// ei4_rx_func_state_pg Register field name                                 data value   Description
-#define     ei4_rx_func_mode_state                                0x0000     //Functional Mode State Machine(RJR):
-#define     ei4_rx_func_mode_state_clear                          0x0FFF     // Clear mask
-
-// ei4_rx_dyn_rpr_debug_pg Register field name                              data value   Description
-#define     ei4_rx_dyn_rpr_enc_bad_data_lane_debug                0x0000     //For testfloor/debug purposes, specify the encoded bad data lane to report to the dynamic repair tally logic
-#define     ei4_rx_dyn_rpr_enc_bad_data_lane_debug_clear          0x01FF     // Clear mask
-#define     ei4_rx_dyn_rpr_bad_lane_valid_debug                   0x0080     //For testfloor/debug purposes, the specified encoded bad data lane will be tallied as having one cycle of a valid CRC/ECC error (this is a write-only pulse register)
-#define     ei4_rx_dyn_rpr_bad_lane_valid_debug_clear             0xFF7F     // Clear mask
-
-// ei4_rx_dyn_rpr_err_tallying2_pg Register field name                      data value   Description
-#define     ei4_rx_dyn_rpr_bad_bus_max                            0x0000     //CRC/ECC Dynamic Repair: Max number of times CRC or ECC errors can be found on the bus (not included in the bad lane cntr1 tally) before setting a FIR error
-#define     ei4_rx_dyn_rpr_bad_bus_max_clear                      0x01FF     // Clear mask
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap1                0x0020     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  853.0ns & 1.3uS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap2                0x0040     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  27.3uS & 41.0uS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap3                0x0060     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  873.5uS & 1.3mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap4                0x0080     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  1.7mS & 2.6mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap5                0x00A0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  3.5mS & 5.1mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap6                0x00C0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  7.0mS & 10.5mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap7                0x00E0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  14.0mS & 21.0mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap8                0x0100     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  28.0mS & 41.9mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap9                0x0120     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  55.9mS & 83.9mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap10               0x0140     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  111.8mS & 167.8mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap11               0x0160     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  223.6mS & 335.5mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap12               0x0180     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  447.2mS & 671.1mS
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap13               0x01A0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  894.4mS & 1.3 S
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap14               0x01C0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  1.8 S & 2.7 S
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_tap15               0x01E0     //CRC/ECC Dynamic Repair: Duration the bad bus cntr2 error counter can run before being cleared (determines the allowed error frequency)  infinite
-#define     ei4_rx_dyn_rpr_err_cntr2_duration_clear               0x3E1F     // Clear mask
-#define     ei4_rx_dyn_rpr_clr_err_cntr2                          0x0010     //CRC/ECC Dynamic Repair: Firmware-based clear of bus error counter2 register
-#define     ei4_rx_dyn_rpr_clr_err_cntr2_clear                    0xFFEF     // Clear mask
-
-// ei4_rx_result_chk_pg Register field name                                 data value   Description
-#define     ei4_rx_min_eye_width                                  0x0000     //Minimum acceptable eye width used during init or recal results checking--EDI or EI4
-#define     ei4_rx_min_eye_width_clear                            0xC0FF     // Clear mask
-
-// ei4_rx_sls_rcvy_fin_gcrmsg_pg Register field name                        data value   Description
-#define     ei4_rx_slv_shdw_done_fin_gcrmsg                       0x8000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_done
-#define     ei4_rx_slv_shdw_done_fin_gcrmsg_clear                 0x7FFF     // Clear mask
-#define     ei4_rx_slv_shdw_nop_fin_gcrmsg                        0x4000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     ei4_rx_slv_shdw_nop_fin_gcrmsg_clear                  0xBFFF     // Clear mask
-#define     ei4_rx_slv_shdw_rpr_done_fin_gcrmsg                   0x2000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for shdw_rpr_done
-#define     ei4_rx_slv_shdw_rpr_done_fin_gcrmsg_clear             0xDFFF     // Clear mask
-#define     ei4_rx_slv_shdw_rpr_nop_fin_gcrmsg                    0x1000     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     ei4_rx_slv_shdw_rpr_nop_fin_gcrmsg_clear              0xEFFF     // Clear mask
-#define     ei4_rx_slv_unshdw_done_fin_gcrmsg                     0x0800     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_done
-#define     ei4_rx_slv_unshdw_done_fin_gcrmsg_clear               0xF7FF     // Clear mask
-#define     ei4_rx_slv_unshdw_nop_fin_gcrmsg                      0x0400     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     ei4_rx_slv_unshdw_nop_fin_gcrmsg_clear                0xFBFF     // Clear mask
-#define     ei4_rx_slv_unshdw_rpr_done_fin_gcrmsg                 0x0200     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for unshdw_rpr_done
-#define     ei4_rx_slv_unshdw_rpr_done_fin_gcrmsg_clear           0xFDFF     // Clear mask
-#define     ei4_rx_slv_unshdw_rpr_nop_fin_gcrmsg                  0x0100     //GCR Message: Slave RX SLS Lane Repaired; Need to finish slave shadow handshake starting with waiting for nop
-#define     ei4_rx_slv_unshdw_rpr_nop_fin_gcrmsg_clear            0xFEFF     // Clear mask
-#define     ei4_rx_slv_recal_done_nop_fin_gcrmsg                  0x0080     //GCR Message: Slave Recal Done; Need to finish slave recal handshake starting with waiting for nop
-#define     ei4_rx_slv_recal_done_nop_fin_gcrmsg_clear            0xFF7F     // Clear mask
-#define     ei4_rx_slv_recal_fail_nop_fin_gcrmsg                  0x0040     //GCR Message: Slave Recal Fail; Need to finish slave recal handshake starting with waiting for nop
-#define     ei4_rx_slv_recal_fail_nop_fin_gcrmsg_clear            0xFFBF     // Clear mask
-#define     ei4_rx_slv_recal_presults_fin_gcrmsg                  0x0020     //GCR Message: Slave Recal Pass Results; Need to finish slave recal handshake starting with waiting for results
-#define     ei4_rx_slv_recal_presults_fin_gcrmsg_clear            0xFFDF     // Clear mask
-#define     ei4_rx_slv_recal_fresults_fin_gcrmsg                  0x0010     //GCR Message: Slave Recal Fail Results; Need to finish slave recal handshake starting with waiting for results
-#define     ei4_rx_slv_recal_fresults_fin_gcrmsg_clear            0xFFEF     // Clear mask
-#define     ei4_rx_slv_recal_abort_ack_fin_gcrmsg                 0x0008     //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop
-#define     ei4_rx_slv_recal_abort_ack_fin_gcrmsg_clear           0xFFF7     // Clear mask
-#define     ei4_rx_slv_recal_abort_mnop_fin_gcrmsg                0x0004     //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop
-#define     ei4_rx_slv_recal_abort_mnop_fin_gcrmsg_clear          0xFFFB     // Clear mask
-#define     ei4_rx_slv_recal_abort_snop_fin_gcrmsg                0x0002     //GCR Message: Slave Recal Abort; Need to finish slave recal handshake starting with waiting for nop
-#define     ei4_rx_slv_recal_abort_snop_fin_gcrmsg_clear          0xFFFD     // Clear mask
-
-// ei4_rx_wiretest_pp Register field name                                   data value   Description
-#define     ei4_rx_wt_pattern_length_256                          0x4000     //RX Wiretest Pattern Length  256
-#define     ei4_rx_wt_pattern_length_512                          0x8000     //RX Wiretest Pattern Length  512
-#define     ei4_rx_wt_pattern_length_1024                         0xC000     //RX Wiretest Pattern Length  1024
-#define     ei4_rx_wt_pattern_length_clear                        0x3FFF     // Clear mask
-
-// ei4_rx_mode1_pp Register field name                                      data value   Description
-#define     ei4_rx_reduced_scramble_mode_disable_1                0x4000     //Sets reduced density of scramble pattern.   Disable reduced density 
-#define     ei4_rx_reduced_scramble_mode_enable_div2              0x8000     //Sets reduced density of scramble pattern.   Enable Div2 Reduced Density 
-#define     ei4_rx_reduced_scramble_mode_enable_div4              0xC000     //Sets reduced density of scramble pattern.   Enable Div4 Reduced Density
-#define     ei4_rx_reduced_scramble_mode_clear                    0x3FFF     // Clear mask
-#define     ei4_rx_act_check_timeout_sel_128ui                    0x0800     //Sets Activity check timeout value.   128 UI 
-#define     ei4_rx_act_check_timeout_sel_256ui                    0x1000     //Sets Activity check timeout value.   256 UI 
-#define     ei4_rx_act_check_timeout_sel_512ui                    0x1800     //Sets Activity check timeout value.   512 UI 
-#define     ei4_rx_act_check_timeout_sel_1024ui                   0x2000     //Sets Activity check timeout value.   1024 UI 
-#define     ei4_rx_act_check_timeout_sel_2048ui                   0x2800     //Sets Activity check timeout value.   2048 UI 
-#define     ei4_rx_act_check_timeout_sel_4096ui                   0x3000     //Sets Activity check timeout value.   4096 UI 
-#define     ei4_rx_act_check_timeout_sel_infinite                 0x3800     //Sets Activity check timeout value.   Infinite
-#define     ei4_rx_act_check_timeout_sel_clear                    0xC7FF     // Clear mask
-#define     ei4_rx_block_lock_timeout_sel_1024ui                  0x0100     //Sets block lock timeout value.   1024 UI 
-#define     ei4_rx_block_lock_timeout_sel_2048ui                  0x0200     //Sets block lock timeout value.   2048 UI 
-#define     ei4_rx_block_lock_timeout_sel_4096ui                  0x0300     //Sets block lock timeout value.   4096 UI 
-#define     ei4_rx_block_lock_timeout_sel_8192ui                  0x0400     //Sets block lock timeout value.   8192 UI 
-#define     ei4_rx_block_lock_timeout_sel_16384ui                 0x0500     //Sets block lock timeout value.   16384 UI 
-#define     ei4_rx_block_lock_timeout_sel_32768ui                 0x0600     //Sets block lock timeout value.   32768 UI 
-#define     ei4_rx_block_lock_timeout_sel_infinite                0x0700     //Sets block lock timeout value.   Infinite
-#define     ei4_rx_block_lock_timeout_sel_clear                   0xF8FF     // Clear mask
-#define     ei4_rx_bit_lock_timeout_sel_512ui                     0x0020     //Sets bit lock/edge detect timeout value.   512 UI 
-#define     ei4_rx_bit_lock_timeout_sel_1024ui                    0x0040     //Sets bit lock/edge detect timeout value.   1024 UI 
-#define     ei4_rx_bit_lock_timeout_sel_2048ui                    0x0060     //Sets bit lock/edge detect timeout value.   2048 UI 
-#define     ei4_rx_bit_lock_timeout_sel_4096ui                    0x0080     //Sets bit lock/edge detect timeout value.   4096 UI 
-#define     ei4_rx_bit_lock_timeout_sel_8192ui                    0x00A0     //Sets bit lock/edge detect timeout value.   8192 UI 
-#define     ei4_rx_bit_lock_timeout_sel_16384ui                   0x00C0     //Sets bit lock/edge detect timeout value.   16384 UI 
-#define     ei4_rx_bit_lock_timeout_sel_infinite                  0x00E0     //Sets bit lock/edge detect timeout value.   Infinite
-#define     ei4_rx_bit_lock_timeout_sel_clear                     0x1F1F     // Clear mask
-#define     ei4_rx_reverse_shift                                  0x0002     //RX Phase Rotator Direction
-#define     ei4_rx_reverse_shift_clear                            0xFFFD     // Clear mask
-#define     ei4_rx_ei3_mode                                       0x0001     //EI3 mode - See also ei4_tx_ei3_mode 
-#define     ei4_rx_ei3_mode_clear                                 0xFFFE     // Clear mask
-
-// ei4_rx_cntl_pp Register field name                                       data value   Description
-#define     ei4_rx_prbs_check_sync                                0x4000     //Enables checking for the 12 ui scramble sync pattern. 
-#define     ei4_rx_prbs_check_sync_clear                          0xBFFF     // Clear mask
-#define     ei4_rx_enable_reduced_scramble                        0x2000     //Enables reduced density of scramble pattern. 
-#define     ei4_rx_enable_reduced_scramble_clear                  0xDFFF     // Clear mask
-#define     ei4_rx_prbs_inc                                       0x1000     //Shift the PRBS pattern forward in time by one extra local cycle (4ui for EDI, 2ui for EI4).
-#define     ei4_rx_prbs_inc_clear                                 0xEFFF     // Clear mask
-#define     ei4_rx_prbs_dec                                       0x0800     //Shift the PRBS pattern back in time by holding it one local cycle (4ui for EDI, 2ui for EI4).
-#define     ei4_rx_prbs_dec_clear                                 0xF7FF     // Clear mask
-
-// ei4_rx_ei4_cal_cntl_pp Register field name                               data value   Description
-#define     ei4_rx_ddc_use_cyc_block_lock                         0x8000     //0 - use phase rot, 1 - use cycle sim block lock
-#define     ei4_rx_ddc_use_cyc_block_lock_clear                   0x7FFF     // Clear mask
-
-// ei4_rx_ei4_cal_inc_a_d_pp Register field name                            data value   Description
-#define     ei4_rx_cal_inc_val_A                                  0x0000     //RX Servo Accum Inc Value A
-#define     ei4_rx_cal_inc_val_A_clear                            0x0FFF     // Clear mask
-#define     ei4_rx_cal_inc_val_B                                  0x0000     //RX Servo Accum Inc Value B
-#define     ei4_rx_cal_inc_val_B_clear                            0xF0FF     // Clear mask
-#define     ei4_rx_cal_inc_val_C                                  0x0000     //RX Servo Accum Inc Value C
-#define     ei4_rx_cal_inc_val_C_clear                            0xFF0F     // Clear mask
-#define     ei4_rx_cal_inc_val_D                                  0x0000     //RX Servo Accum Inc Value D
-#define     ei4_rx_cal_inc_val_D_clear                            0xF0F0     // Clear mask
-
-// ei4_rx_ei4_cal_inc_e_h_pp Register field name                            data value   Description
-#define     ei4_rx_cal_inc_val_E                                  0x0000     //RX Servo Accum Inc Value E
-#define     ei4_rx_cal_inc_val_E_clear                            0x0FFF     // Clear mask
-#define     ei4_rx_cal_inc_val_F                                  0x0000     //RX Servo Accum Inc Value F
-#define     ei4_rx_cal_inc_val_F_clear                            0xF0FF     // Clear mask
-#define     ei4_rx_cal_inc_val_G                                  0x0000     //RX Servo Accum Inc Value G
-#define     ei4_rx_cal_inc_val_G_clear                            0xFF0F     // Clear mask
-#define     ei4_rx_cal_inc_val_H                                  0x0000     //RX Servo Accum Inc Value H
-#define     ei4_rx_cal_inc_val_H_clear                            0xF0F0     // Clear mask
-
-// ei4_rx_ei4_cal_dec_a_d_pp Register field name                            data value   Description
-#define     ei4_rx_cal_dec_val_A                                  0x0000     //RX Servo Accum Dec Value A
-#define     ei4_rx_cal_dec_val_A_clear                            0x0FFF     // Clear mask
-#define     ei4_rx_cal_dec_val_B                                  0x0000     //RX Servo Accum Dec Value B
-#define     ei4_rx_cal_dec_val_B_clear                            0xF0FF     // Clear mask
-#define     ei4_rx_cal_dec_val_C                                  0x0000     //RX Servo Accum Dec Value C
-#define     ei4_rx_cal_dec_val_C_clear                            0xFF0F     // Clear mask
-#define     ei4_rx_cal_dec_val_D                                  0x0000     //RX Servo Accum Dec Value D
-#define     ei4_rx_cal_dec_val_D_clear                            0xF0F0     // Clear mask
-
-// ei4_rx_ei4_cal_dec_e_h_pp Register field name                            data value   Description
-#define     ei4_rx_cal_dec_val_E                                  0x0000     //RX Servo Accum Dec Value E
-#define     ei4_rx_cal_dec_val_E_clear                            0x0FFF     // Clear mask
-#define     ei4_rx_cal_dec_val_F                                  0x0000     //RX Servo Accum Dec Value F
-#define     ei4_rx_cal_dec_val_F_clear                            0xF0FF     // Clear mask
-#define     ei4_rx_cal_dec_val_G                                  0x0000     //RX Servo Accum Dec Value G
-#define     ei4_rx_cal_dec_val_G_clear                            0xFF0F     // Clear mask
-#define     ei4_rx_cal_dec_val_H                                  0x0000     //RX Servo Accum Dec Value H
-#define     ei4_rx_cal_dec_val_H_clear                            0xF0F0     // Clear mask
-
-// ei4_rx_mode2_pp Register field name                                      data value   Description
-#define     ei4_rx_bist_jitter_pulse_ctl_0                        0x4000     //Jitter Select  (steps8
-#define     ei4_rx_bist_jitter_pulse_ctl_1                        0x8000     //Jitter Select  (steps2
-#define     ei4_rx_bist_jitter_pulse_ctl_2                        0xC000     //Jitter Select  (steps0
-#define     ei4_rx_bist_jitter_pulse_ctl_clear                    0x3FFF     // Clear mask
-#define     ei4_rx_bist_min_eye_width                             0x0000     //Sets the minimum eye width value considered acceptable by PHYBIST.
-#define     ei4_rx_bist_min_eye_width_clear                       0xC07F     // Clear mask
-
-// ei4_rx_ber_cntl_pp Register field name                                   data value   Description
-#define     ei4_rx_ber_en                                         0x8000     //Per-Pack (PP) Diagnostic Bit Error Rate (BER) error checking enable control. When 1 enables error checking. When 0 the error checking is disabled. This control enables the BER timer as well as enables the error checker and BER counters. The assumption is that the driver(s) are currently driving PRBS23 and the link has been trained before enabling BER checking.
-#define     ei4_rx_ber_en_clear                                   0x7FFF     // Clear mask
-#define     ei4_rx_ber_count_clr                                  0x4000     //PP Diag BER error counter clear pulse. When written to a 1 the per-lane error counters are cleared to all zeroes. Writing both this bit and the timer clear bit to a 1 will clear both and allow a new set of measurements to be run.
-#define     ei4_rx_ber_count_clr_clear                            0xBFFF     // Clear mask
-#define     ei4_rx_ber_timer_clr                                  0x2000     //PP Diag BER timer clear pulse. When written to a 1 the per-pack timers are cleared to all zeroes. Writing both this bit and the error counter clear bit to a 1 will clear both and allow a new set of measurements to be run.
-#define     ei4_rx_ber_timer_clr_clear                            0xDFFF     // Clear mask
-
-// ei4_rx_ber_mode_pp Register field name                                   data value   Description
-#define     ei4_rx_ber_timer_freeze_en                            0x8000     //Per-Pack (PP) Diagnostic Bit Error Rate (BER) Timer freeze enable. When set to a 1 the per-pack timer is frozen when any lane error count saturates in that pack.
-#define     ei4_rx_ber_timer_freeze_en_clear                      0x7FFF     // Clear mask
-#define     ei4_rx_ber_count_freeze_en                            0x4000     //PP Diag BER Lane Error Counter freeze enable. When set to a 1 the per-lane error counters are frozen when the timer saturates in that pack.
-#define     ei4_rx_ber_count_freeze_en_clear                      0xBFFF     // Clear mask
-#define     ei4_rx_ber_count_sel_2                                0x0400     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   2
-#define     ei4_rx_ber_count_sel_4                                0x0800     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   4
-#define     ei4_rx_ber_count_sel_8                                0x0C00     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   8
-#define     ei4_rx_ber_count_sel_16                               0x1000     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   16
-#define     ei4_rx_ber_count_sel_32                               0x1400     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   32
-#define     ei4_rx_ber_count_sel_64                               0x1800     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   64
-#define     ei4_rx_ber_count_sel_128                              0x1C00     //PP Diag BER Lane Error Counter saturation select. Selects the number of errors that will saturate the counter and cause a freeze event.   128
-#define     ei4_rx_ber_count_sel_clear                            0xE3FF     // Clear mask
-#define     ei4_rx_ber_timer_sel_2tothe36th                       0x0080     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^36
-#define     ei4_rx_ber_timer_sel_2tothe32nd                       0x0100     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^32
-#define     ei4_rx_ber_timer_sel_2tothe28th                       0x0180     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^28
-#define     ei4_rx_ber_timer_sel_2tothe24th                       0x0200     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^24
-#define     ei4_rx_ber_timer_sel_2tothe20th                       0x0280     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^20
-#define     ei4_rx_ber_timer_sel_2tothe16th                       0x0300     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^16
-#define     ei4_rx_ber_timer_sel_2tothe12th                       0x0380     //PP Diag BER Timer saturation select. Selects the timer value that will saturate the timer and cause a freeze event.   2^12
-#define     ei4_rx_ber_timer_sel_clear                            0xFC7F     // Clear mask
-#define     ei4_rx_ber_clr_count_on_read_en                       0x0040     //PP Diag BER Lane Error Counter clear on read. When set to a 1 this enables the clearing of a lanes error counter when it is read.
-#define     ei4_rx_ber_clr_count_on_read_en_clear                 0xFFBF     // Clear mask
-#define     ei4_rx_ber_clr_timer_on_read_en                       0x0020     //PP Diag BER Timer clear on read. When set to a 1 this enables the clearing of a lanes per-pack timer when it is read from any lane in the pack.
-#define     ei4_rx_ber_clr_timer_on_read_en_clear                 0xFFDF     // Clear mask
-
-// ei4_rx_servo_to1_pp Register field name                                  data value   Description
-#define     ei4_rx_servo_timeout_sel_A_512ui                      0x1000     //RX servo operation timeout A.  512 UI 
-#define     ei4_rx_servo_timeout_sel_A_1Kui                       0x2000     //RX servo operation timeout A.  1K UI 
-#define     ei4_rx_servo_timeout_sel_A_2Kui                       0x3000     //RX servo operation timeout A.  2K UI 
-#define     ei4_rx_servo_timeout_sel_A_4Kui                       0x4000     //RX servo operation timeout A.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_A_8Kui                       0x5000     //RX servo operation timeout A.  8K UI 
-#define     ei4_rx_servo_timeout_sel_A_16Kui                      0x6000     //RX servo operation timeout A.  16K UI 
-#define     ei4_rx_servo_timeout_sel_A_32Kui                      0x7000     //RX servo operation timeout A.  32K UI 
-#define     ei4_rx_servo_timeout_sel_A_64Kui                      0x8000     //RX servo operation timeout A.  64K UI 
-#define     ei4_rx_servo_timeout_sel_A_128Kui                     0x9000     //RX servo operation timeout A.  128K UI 
-#define     ei4_rx_servo_timeout_sel_A_256Kui                     0xA000     //RX servo operation timeout A.  256K UI 
-#define     ei4_rx_servo_timeout_sel_A_512Kui                     0xB000     //RX servo operation timeout A.  512K UI 
-#define     ei4_rx_servo_timeout_sel_A_1Mui                       0xC000     //RX servo operation timeout A.  1M UI 
-#define     ei4_rx_servo_timeout_sel_A_2Mui                       0xD000     //RX servo operation timeout A.  2M UI 
-#define     ei4_rx_servo_timeout_sel_A_4Mui                       0xE000     //RX servo operation timeout A.  4M UI
-#define     ei4_rx_servo_timeout_sel_A_Infinite                   0xF000     //RX servo operation timeout A.  Infinite
-#define     ei4_rx_servo_timeout_sel_A_clear                      0x0FFF     // Clear mask
-#define     ei4_rx_servo_timeout_sel_B_512ui                      0x0100     //RX servo operation timeout B.  512 UI 
-#define     ei4_rx_servo_timeout_sel_B_1Kui                       0x0200     //RX servo operation timeout B.  1K UI 
-#define     ei4_rx_servo_timeout_sel_B_2Kui                       0x0300     //RX servo operation timeout B.  2K UI 
-#define     ei4_rx_servo_timeout_sel_B_4Kui                       0x0400     //RX servo operation timeout B.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_B_8Kui                       0x0500     //RX servo operation timeout B.  8K UI 
-#define     ei4_rx_servo_timeout_sel_B_16Kui                      0x0600     //RX servo operation timeout B.  16K UI 
-#define     ei4_rx_servo_timeout_sel_B_32Kui                      0x0700     //RX servo operation timeout B.  32K UI 
-#define     ei4_rx_servo_timeout_sel_B_64Kui                      0x0800     //RX servo operation timeout B.  64K UI 
-#define     ei4_rx_servo_timeout_sel_B_128Kui                     0x0900     //RX servo operation timeout B.  128K UI 
-#define     ei4_rx_servo_timeout_sel_B_256Kui                     0x0A00     //RX servo operation timeout B.  256K UI 
-#define     ei4_rx_servo_timeout_sel_B_512Kui                     0x0B00     //RX servo operation timeout B.  512K UI 
-#define     ei4_rx_servo_timeout_sel_B_1Mui                       0x0C00     //RX servo operation timeout B.  1M UI 
-#define     ei4_rx_servo_timeout_sel_B_2Mui                       0x0D00     //RX servo operation timeout B.  2M UI 
-#define     ei4_rx_servo_timeout_sel_B_4Mui                       0x0E00     //RX servo operation timeout B.  4M UI
-#define     ei4_rx_servo_timeout_sel_B_Infinite                   0x0F00     //RX servo operation timeout B.  Infinite
-#define     ei4_rx_servo_timeout_sel_B_clear                      0xF0FF     // Clear mask
-#define     ei4_rx_servo_timeout_sel_C_512ui                      0x0010     //RX servo operation timeout C.  512 UI 
-#define     ei4_rx_servo_timeout_sel_C_1Kui                       0x0020     //RX servo operation timeout C.  1K UI 
-#define     ei4_rx_servo_timeout_sel_C_2Kui                       0x0030     //RX servo operation timeout C.  2K UI 
-#define     ei4_rx_servo_timeout_sel_C_4Kui                       0x0040     //RX servo operation timeout C.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_C_8Kui                       0x0050     //RX servo operation timeout C.  8K UI 
-#define     ei4_rx_servo_timeout_sel_C_16Kui                      0x0060     //RX servo operation timeout C.  16K UI 
-#define     ei4_rx_servo_timeout_sel_C_32Kui                      0x0070     //RX servo operation timeout C.  32K UI 
-#define     ei4_rx_servo_timeout_sel_C_64Kui                      0x0080     //RX servo operation timeout C.  64K UI 
-#define     ei4_rx_servo_timeout_sel_C_128Kui                     0x0090     //RX servo operation timeout C.  128K UI 
-#define     ei4_rx_servo_timeout_sel_C_256Kui                     0x00A0     //RX servo operation timeout C.  256K UI 
-#define     ei4_rx_servo_timeout_sel_C_512Kui                     0x00B0     //RX servo operation timeout C.  512K UI 
-#define     ei4_rx_servo_timeout_sel_C_1Mui                       0x00C0     //RX servo operation timeout C.  1M UI 
-#define     ei4_rx_servo_timeout_sel_C_2Mui                       0x00D0     //RX servo operation timeout C.  2M UI 
-#define     ei4_rx_servo_timeout_sel_C_4Mui                       0x00E0     //RX servo operation timeout C.  4M UI
-#define     ei4_rx_servo_timeout_sel_C_Infinite                   0x00F0     //RX servo operation timeout C.  Infinite
-#define     ei4_rx_servo_timeout_sel_C_clear                      0x0F0F     // Clear mask
-#define     ei4_rx_servo_timeout_sel_D_512ui                      0x0001     //RX servo operation timeout D.  512 UI 
-#define     ei4_rx_servo_timeout_sel_D_1Kui                       0x0002     //RX servo operation timeout D.  1K UI 
-#define     ei4_rx_servo_timeout_sel_D_2Kui                       0x0003     //RX servo operation timeout D.  2K UI 
-#define     ei4_rx_servo_timeout_sel_D_4Kui                       0x0004     //RX servo operation timeout D.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_D_8Kui                       0x0005     //RX servo operation timeout D.  8K UI 
-#define     ei4_rx_servo_timeout_sel_D_16Kui                      0x0006     //RX servo operation timeout D.  16K UI 
-#define     ei4_rx_servo_timeout_sel_D_32Kui                      0x0007     //RX servo operation timeout D.  32K UI 
-#define     ei4_rx_servo_timeout_sel_D_64Kui                      0x0008     //RX servo operation timeout D.  64K UI 
-#define     ei4_rx_servo_timeout_sel_D_128Kui                     0x0009     //RX servo operation timeout D.  128K UI 
-#define     ei4_rx_servo_timeout_sel_D_256Kui                     0x000A     //RX servo operation timeout D.  256K UI 
-#define     ei4_rx_servo_timeout_sel_D_512Kui                     0x000B     //RX servo operation timeout D.  512K UI 
-#define     ei4_rx_servo_timeout_sel_D_1Mui                       0x000C     //RX servo operation timeout D.  1M UI 
-#define     ei4_rx_servo_timeout_sel_D_2Mui                       0x000D     //RX servo operation timeout D.  2M UI 
-#define     ei4_rx_servo_timeout_sel_D_4Mui                       0x000E     //RX servo operation timeout D.  4M UI
-#define     ei4_rx_servo_timeout_sel_D_Infinite                   0x000F     //RX servo operation timeout D.  Infinite
-#define     ei4_rx_servo_timeout_sel_D_clear                      0xFF00     // Clear mask
-
-// ei4_rx_servo_to2_pp Register field name                                  data value   Description
-#define     ei4_rx_servo_timeout_sel_E_512ui                      0x1000     //RX servo operation timeout E.  512 UI 
-#define     ei4_rx_servo_timeout_sel_E_1Kui                       0x2000     //RX servo operation timeout E.  1K UI 
-#define     ei4_rx_servo_timeout_sel_E_2Kui                       0x3000     //RX servo operation timeout E.  2K UI 
-#define     ei4_rx_servo_timeout_sel_E_4Kui                       0x4000     //RX servo operation timeout E.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_E_8Kui                       0x5000     //RX servo operation timeout E.  8K UI 
-#define     ei4_rx_servo_timeout_sel_E_16Kui                      0x6000     //RX servo operation timeout E.  16K UI 
-#define     ei4_rx_servo_timeout_sel_E_32Kui                      0x7000     //RX servo operation timeout E.  32K UI 
-#define     ei4_rx_servo_timeout_sel_E_64Kui                      0x8000     //RX servo operation timeout E.  64K UI 
-#define     ei4_rx_servo_timeout_sel_E_128Kui                     0x9000     //RX servo operation timeout E.  128K UI 
-#define     ei4_rx_servo_timeout_sel_E_256Kui                     0xA000     //RX servo operation timeout E.  256K UI 
-#define     ei4_rx_servo_timeout_sel_E_512Kui                     0xB000     //RX servo operation timeout E.  512K UI 
-#define     ei4_rx_servo_timeout_sel_E_1Mui                       0xC000     //RX servo operation timeout E.  1M UI 
-#define     ei4_rx_servo_timeout_sel_E_2Mui                       0xD000     //RX servo operation timeout E.  2M UI 
-#define     ei4_rx_servo_timeout_sel_E_4Mui                       0xE000     //RX servo operation timeout E.  4M UI
-#define     ei4_rx_servo_timeout_sel_E_Infinite                   0xF000     //RX servo operation timeout E.  Infinite
-#define     ei4_rx_servo_timeout_sel_E_clear                      0x0FFF     // Clear mask
-#define     ei4_rx_servo_timeout_sel_F_512ui                      0x0100     //RX servo operation timeout F.  512 UI 
-#define     ei4_rx_servo_timeout_sel_F_1Kui                       0x0200     //RX servo operation timeout F.  1K UI 
-#define     ei4_rx_servo_timeout_sel_F_2Kui                       0x0300     //RX servo operation timeout F.  2K UI 
-#define     ei4_rx_servo_timeout_sel_F_4Kui                       0x0400     //RX servo operation timeout F.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_F_8Kui                       0x0500     //RX servo operation timeout F.  8K UI 
-#define     ei4_rx_servo_timeout_sel_F_16Kui                      0x0600     //RX servo operation timeout F.  16K UI 
-#define     ei4_rx_servo_timeout_sel_F_32Kui                      0x0700     //RX servo operation timeout F.  32K UI 
-#define     ei4_rx_servo_timeout_sel_F_64Kui                      0x0800     //RX servo operation timeout F.  64K UI 
-#define     ei4_rx_servo_timeout_sel_F_128Kui                     0x0900     //RX servo operation timeout F.  128K UI 
-#define     ei4_rx_servo_timeout_sel_F_256Kui                     0x0A00     //RX servo operation timeout F.  256K UI 
-#define     ei4_rx_servo_timeout_sel_F_512Kui                     0x0B00     //RX servo operation timeout F.  512K UI 
-#define     ei4_rx_servo_timeout_sel_F_1Mui                       0x0C00     //RX servo operation timeout F.  1M UI 
-#define     ei4_rx_servo_timeout_sel_F_2Mui                       0x0D00     //RX servo operation timeout F.  2M UI 
-#define     ei4_rx_servo_timeout_sel_F_4Mui                       0x0E00     //RX servo operation timeout F.  4M UI
-#define     ei4_rx_servo_timeout_sel_F_Infinite                   0x0F00     //RX servo operation timeout F.  Infinite
-#define     ei4_rx_servo_timeout_sel_F_clear                      0xF0FF     // Clear mask
-#define     ei4_rx_servo_timeout_sel_G_512ui                      0x0010     //RX servo operation timeout G.  512 UI 
-#define     ei4_rx_servo_timeout_sel_G_1Kui                       0x0020     //RX servo operation timeout G.  1K UI 
-#define     ei4_rx_servo_timeout_sel_G_2Kui                       0x0030     //RX servo operation timeout G.  2K UI 
-#define     ei4_rx_servo_timeout_sel_G_4Kui                       0x0040     //RX servo operation timeout G.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_G_8Kui                       0x0050     //RX servo operation timeout G.  8K UI 
-#define     ei4_rx_servo_timeout_sel_G_16Kui                      0x0060     //RX servo operation timeout G.  16K UI 
-#define     ei4_rx_servo_timeout_sel_G_32Kui                      0x0070     //RX servo operation timeout G.  32K UI 
-#define     ei4_rx_servo_timeout_sel_G_64Kui                      0x0080     //RX servo operation timeout G.  64K UI 
-#define     ei4_rx_servo_timeout_sel_G_128Kui                     0x0090     //RX servo operation timeout G.  128K UI 
-#define     ei4_rx_servo_timeout_sel_G_256Kui                     0x00A0     //RX servo operation timeout G.  256K UI 
-#define     ei4_rx_servo_timeout_sel_G_512Kui                     0x00B0     //RX servo operation timeout G.  512K UI 
-#define     ei4_rx_servo_timeout_sel_G_1Mui                       0x00C0     //RX servo operation timeout G.  1M UI 
-#define     ei4_rx_servo_timeout_sel_G_2Mui                       0x00D0     //RX servo operation timeout G.  2M UI 
-#define     ei4_rx_servo_timeout_sel_G_4Mui                       0x00E0     //RX servo operation timeout G.  4M UI
-#define     ei4_rx_servo_timeout_sel_G_Infinite                   0x00F0     //RX servo operation timeout G.  Infinite
-#define     ei4_rx_servo_timeout_sel_G_clear                      0x0F0F     // Clear mask
-#define     ei4_rx_servo_timeout_sel_H_512ui                      0x0001     //RX servo operation timeout H.  512 UI 
-#define     ei4_rx_servo_timeout_sel_H_1Kui                       0x0002     //RX servo operation timeout H.  1K UI 
-#define     ei4_rx_servo_timeout_sel_H_2Kui                       0x0003     //RX servo operation timeout H.  2K UI 
-#define     ei4_rx_servo_timeout_sel_H_4Kui                       0x0004     //RX servo operation timeout H.  4096 UI 
-#define     ei4_rx_servo_timeout_sel_H_8Kui                       0x0005     //RX servo operation timeout H.  8K UI 
-#define     ei4_rx_servo_timeout_sel_H_16Kui                      0x0006     //RX servo operation timeout H.  16K UI 
-#define     ei4_rx_servo_timeout_sel_H_32Kui                      0x0007     //RX servo operation timeout H.  32K UI 
-#define     ei4_rx_servo_timeout_sel_H_64Kui                      0x0008     //RX servo operation timeout H.  64K UI 
-#define     ei4_rx_servo_timeout_sel_H_128Kui                     0x0009     //RX servo operation timeout H.  128K UI 
-#define     ei4_rx_servo_timeout_sel_H_256Kui                     0x000A     //RX servo operation timeout H.  256K UI 
-#define     ei4_rx_servo_timeout_sel_H_512Kui                     0x000B     //RX servo operation timeout H.  512K UI 
-#define     ei4_rx_servo_timeout_sel_H_1Mui                       0x000C     //RX servo operation timeout H.  1M UI 
-#define     ei4_rx_servo_timeout_sel_H_2Mui                       0x000D     //RX servo operation timeout H.  2M UI 
-#define     ei4_rx_servo_timeout_sel_H_4Mui                       0x000E     //RX servo operation timeout H.  4M UI
-#define     ei4_rx_servo_timeout_sel_H_Infinite                   0x000F     //RX servo operation timeout H.  Infinite
-#define     ei4_rx_servo_timeout_sel_H_clear                      0xFF00     // Clear mask
-
-// ei4_rx_reset_cfg_pp Register field name                                  data value   Description
-#define     ei4_rx_reset_cfg_hld_clear                            0x0000     // Clear mask
-
-// ei4_rx_recal_to1_pp Register field name                                  data value   Description
-#define     ei4_rx_recal_timeout_sel_A_512ui                      0x1000     //RX recal servo operation timeout A.  512 UI 
-#define     ei4_rx_recal_timeout_sel_A_1Kui                       0x2000     //RX recal servo operation timeout A.  1K UI 
-#define     ei4_rx_recal_timeout_sel_A_2Kui                       0x3000     //RX recal servo operation timeout A.  2K UI 
-#define     ei4_rx_recal_timeout_sel_A_4Kui                       0x4000     //RX recal servo operation timeout A.  4096 UI 
-#define     ei4_rx_recal_timeout_sel_A_8Kui                       0x5000     //RX recal servo operation timeout A.  8K UI 
-#define     ei4_rx_recal_timeout_sel_A_16Kui                      0x6000     //RX recal servo operation timeout A.  16K UI 
-#define     ei4_rx_recal_timeout_sel_A_32Kui                      0x7000     //RX recal servo operation timeout A.  32K UI 
-#define     ei4_rx_recal_timeout_sel_A_64Kui                      0x8000     //RX recal servo operation timeout A.  64K UI 
-#define     ei4_rx_recal_timeout_sel_A_128Kui                     0x9000     //RX recal servo operation timeout A.  128K UI 
-#define     ei4_rx_recal_timeout_sel_A_256Kui                     0xA000     //RX recal servo operation timeout A.  256K UI 
-#define     ei4_rx_recal_timeout_sel_A_512Kui                     0xB000     //RX recal servo operation timeout A.  512K UI 
-#define     ei4_rx_recal_timeout_sel_A_1Mui                       0xC000     //RX recal servo operation timeout A.  1M UI 
-#define     ei4_rx_recal_timeout_sel_A_2Mui                       0xD000     //RX recal servo operation timeout A.  2M UI 
-#define     ei4_rx_recal_timeout_sel_A_4Mui                       0xE000     //RX recal servo operation timeout A.  4M UI
-#define     ei4_rx_recal_timeout_sel_A_Infinite                   0xF000     //RX recal servo operation timeout A.  Infinite
-#define     ei4_rx_recal_timeout_sel_A_clear                      0x0FFF     // Clear mask
-
-// ei4_rx_recal_to2_pp Register field name                                  data value   Description
-#define     ei4_rx_recal_timeout_sel_E_512ui                      0x1000     //RX recal servo operation timeout E.  512 UI 
-#define     ei4_rx_recal_timeout_sel_E_1Kui                       0x2000     //RX recal servo operation timeout E.  1K UI 
-#define     ei4_rx_recal_timeout_sel_E_2Kui                       0x3000     //RX recal servo operation timeout E.  2K UI 
-#define     ei4_rx_recal_timeout_sel_E_4Kui                       0x4000     //RX recal servo operation timeout E.  4096 UI 
-#define     ei4_rx_recal_timeout_sel_E_8Kui                       0x5000     //RX recal servo operation timeout E.  8K UI 
-#define     ei4_rx_recal_timeout_sel_E_16Kui                      0x6000     //RX recal servo operation timeout E.  16K UI 
-#define     ei4_rx_recal_timeout_sel_E_32Kui                      0x7000     //RX recal servo operation timeout E.  32K UI 
-#define     ei4_rx_recal_timeout_sel_E_64Kui                      0x8000     //RX recal servo operation timeout E.  64K UI 
-#define     ei4_rx_recal_timeout_sel_E_128Kui                     0x9000     //RX recal servo operation timeout E.  128K UI 
-#define     ei4_rx_recal_timeout_sel_E_256Kui                     0xA000     //RX recal servo operation timeout E.  256K UI 
-#define     ei4_rx_recal_timeout_sel_E_512Kui                     0xB000     //RX recal servo operation timeout E.  512K UI 
-#define     ei4_rx_recal_timeout_sel_E_1Mui                       0xC000     //RX recal servo operation timeout E.  1M UI 
-#define     ei4_rx_recal_timeout_sel_E_2Mui                       0xD000     //RX recal servo operation timeout E.  2M UI 
-#define     ei4_rx_recal_timeout_sel_E_4Mui                       0xE000     //RX recal servo operation timeout E.  4M UI
-#define     ei4_rx_recal_timeout_sel_E_Infinite                   0xF000     //RX recal servo operation timeout E.  Infinite
-#define     ei4_rx_recal_timeout_sel_E_clear                      0x0FFF     // Clear mask
-#define     ei4_rx_recal_timeout_sel_F_512ui                      0x0100     //RX recal servo operation timeout F.  512 UI 
-#define     ei4_rx_recal_timeout_sel_F_1Kui                       0x0200     //RX recal servo operation timeout F.  1K UI 
-#define     ei4_rx_recal_timeout_sel_F_2Kui                       0x0300     //RX recal servo operation timeout F.  2K UI 
-#define     ei4_rx_recal_timeout_sel_F_4Kui                       0x0400     //RX recal servo operation timeout F.  4096 UI 
-#define     ei4_rx_recal_timeout_sel_F_8Kui                       0x0500     //RX recal servo operation timeout F.  8K UI 
-#define     ei4_rx_recal_timeout_sel_F_16Kui                      0x0600     //RX recal servo operation timeout F.  16K UI 
-#define     ei4_rx_recal_timeout_sel_F_32Kui                      0x0700     //RX recal servo operation timeout F.  32K UI 
-#define     ei4_rx_recal_timeout_sel_F_64Kui                      0x0800     //RX recal servo operation timeout F.  64K UI 
-#define     ei4_rx_recal_timeout_sel_F_128Kui                     0x0900     //RX recal servo operation timeout F.  128K UI 
-#define     ei4_rx_recal_timeout_sel_F_256Kui                     0x0A00     //RX recal servo operation timeout F.  256K UI 
-#define     ei4_rx_recal_timeout_sel_F_512Kui                     0x0B00     //RX recal servo operation timeout F.  512K UI 
-#define     ei4_rx_recal_timeout_sel_F_1Mui                       0x0C00     //RX recal servo operation timeout F.  1M UI 
-#define     ei4_rx_recal_timeout_sel_F_2Mui                       0x0D00     //RX recal servo operation timeout F.  2M UI 
-#define     ei4_rx_recal_timeout_sel_F_4Mui                       0x0E00     //RX recal servo operation timeout F.  4M UI
-#define     ei4_rx_recal_timeout_sel_F_Infinite                   0x0F00     //RX recal servo operation timeout F.  Infinite
-#define     ei4_rx_recal_timeout_sel_F_clear                      0xF0FF     // Clear mask
-
-// ei4_rx_recal_cntl_pp Register field name                                 data value   Description
-#define     ei4_rx_recal_in_progress                              0x8000     //Selects which servo timeouts are used. 
-#define     ei4_rx_recal_in_progress_clear                        0x7FFF     // Clear mask
-
-// ei4_rx_trace_pp Register field name                                      data value   Description
-#define     ei4_rx_pp_trc_mode_tap1                               0x2000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_tap2                               0x4000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_tap3                               0x6000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_tap4                               0x8000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_tap5                               0xA000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_tap6                               0xC000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_tap7                               0xE000     //Per Pack RX Trace Mode  TBD
-#define     ei4_rx_pp_trc_mode_clear                              0x1FFF     // Clear mask
-
-// ei4_rx_bist_gcrmsg_pp Register field name                                data value   Description
-#define     ei4_rx_bist_en                                        0x8000     //TBD
-#define     ei4_rx_bist_en_clear                                  0x7FFF     // Clear mask
-
-// ei4_rx_fir_reset_pb Register field name                                  data value   Description
-#define     ei4_rx_pb_clr_par_errs                                0x0002     //Clear All RX Parity Error Latches
-#define     ei4_rx_pb_clr_par_errs_clear                          0xFFFD     // Clear mask
-#define     ei4_rx_pb_fir_reset                                   0x0001     //FIR Reset
-#define     ei4_rx_pb_fir_reset_clear                             0xFFFE     // Clear mask
-
-// ei4_rx_fir_pb Register field name                                        data value   Description
-#define     ei4_rx_pb_fir_errs_err_busctl_gcrs_ld_sm              0x0400     //A Per-Bus BUSCTL Register or State Machine Parity Error has occurred.  BUSCTL GCR Load SM Parity Error.
-#define     ei4_rx_pb_fir_errs_clear                              0x003F     // Clear mask
-
-// ei4_rx_fir_mask_pb Register field name                                   data value   Description
-#define     ei4_rx_pb_fir_errs_mask_err_busctl_gcrs_ld_sm         0x0400     //FIR mask for register or state machine parity checkers in per-bus BUSCTL logic. A value of 1 masks the error from generating a FIR error.  BUSCTL GCR Load SM Parity Error.
-#define     ei4_rx_pb_fir_errs_mask_clear                         0x003F     // Clear mask
-
-// ei4_rx_fir_error_inject_pb Register field name                           data value   Description
-#define     ei4_rx_pb_fir_errs_inj_1                              0x4000     //RX Per-Group Parity Error Injection  Causes a parity flip in the specific parity checker.
-#define     ei4_rx_pb_fir_errs_inj_err_inj_busctl_gcrs_ld_sm      0x0400     //RX Per-Group Parity Error Injection  BUSCTL GCR Load SM Parity Error Inject.
-#define     ei4_rx_pb_fir_errs_inj_clear                          0x003F     // Clear mask
-
-
-
-
-
-#endif
-
diff --git a/src/usr/hwpf/hwp/bus_training/erepairAccessorHwpFuncs.C b/src/usr/hwpf/hwp/bus_training/erepairAccessorHwpFuncs.C
deleted file mode 100644
index 349d9817e..000000000
--- a/src/usr/hwpf/hwp/bus_training/erepairAccessorHwpFuncs.C
+++ /dev/null
@@ -1,1523 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/erepairAccessorHwpFuncs.C $     */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: erepairAccessorHwpFuncs.C,v 1.2 2014/04/29 11:58:49 bilicon Exp $
-/**
- *  @file erepairAccessorHwpFuncs.C
- *
- *  @brief FW Team Utility functions that accesses fabric and memory eRepair
- *         data.
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          bilicon     10/24/2012  Created.
- */
-
-#include <erepairAccessorHwpFuncs.H>
-#include <string.h>
-#include <erepairConsts.H>
-
-using namespace EREPAIR;
-
-/** Forward Declarations **/
-
-/**
- * @brief: This function reads the field VPD data to check if there is any
- *         eRepair data. This function will be called during Mnfg mode IPL
- *         during which we need to make sure that the Field VPD is clear.
- *         The Field VPD needs to be clear to enable customers to have
- *         eRepair capability.
- *
- * @param [in]   i_endp1_target  Target of one end the connecting bus
- * @param [in]   i_endp2_target  Target of the other end of the connecting bus
- *                               The VPD of the passed targets are read for
- *                               checking the VPD contents
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mnfgCheckFieldVPD(const fapi::Target &i_endp1_target,
-                                   const fapi::Target &i_endp2_target);
-
-
-/**
- * @brief: This Function reads the specified VPD (Mnfg or Field) of the passed
- *         targets and verifies whether there are matching eRepair records.
- *         The matching eRepair lanes are returned in the passed references
- *         for vectors.
- *
- * @param [in]  i_endp1_target       Target of one end the connecting bus
- * @param [out] o_endp1_txFaillanes  Reference to vector which will have fail
- *                                   lane numbers on Tx side of target passed
- *                                   as first param
- * @param [out] o_endp1_rxFaillanes  Reference to vector which will have fail
- *                                   lane numbers on Rx side of target passed
- *                                   as first param
- * @param [in]  i_endp2_target       Target of the other end of the connecting
- *                                   bus
- * @param [out] o_endp2_txFaillanes  Reference to vector which will have fail
- *                                   lane numbers on Tx side of target passed
- *                                   as fourth param
- * @param [out] o_endp2_rxFaillanes  Reference to vector which will have fail
- *                                   lane numbers on Rx side of target passed
- *                                   as fourth param
- * @param [in]  i_charmModeIPL       If TRUE, indicates that the drawer is under
- *                                   CHARM operation, FALSE otherwise
- * @param [in]  i_vpdType            Indicates whether to read Mnfg VPD or
- *                                   Field VPD
- *
- * @return ReturnCode
- */
-fapi::ReturnCode getVerifiedRepairLanes(
-                                  const fapi::Target   &i_endp1_target,
-                                  std::vector<uint8_t> &o_endp1_txFaillanes,
-                                  std::vector<uint8_t> &o_endp1_rxFaillanes,
-                                  const fapi::Target   &i_endp2_target,
-                                  std::vector<uint8_t> &o_endp2_txFaillanes,
-                                  std::vector<uint8_t> &o_endp2_rxFaillanes,
-                                  const bool           i_charmModeIPL,
-                                  const erepairVpdType i_vpdType);
-
-/**
- * @brief This function checks to see if the passed vectors have matching
- *        fail lane numbers. If no matching lane number is found, such lane
- *        value will be invalidated in the vector
- *
- * @param [in]  io_endp1_txFaillanes        Reference to vector which has fail
- *                                          lane numbers of Tx side
- * @param [in]  io_endp2_rxFaillanes        Reference to vector which has fail
- *                                          lane numbers of Rx side
- * @param [out] o_invalidFails_inTx_Ofendp1 If TRUE, indicates that Tx has fail
- *                                          lane numbers for which there is no
- *                                          matching entry on Rx side
- * @param [out] o_invalidFails_inRx_Ofendp2 If TRUE, indicates that Tx has fail
- *                                          lane numbers for which there is no
- *                                          matching entry on Tx side
- *
- * @return void
- */
-void invalidateNonMatchingFailLanes(std::vector<uint8_t> &io_endp1_txFaillanes,
-                                    std::vector<uint8_t> &io_endp2_rxFaillanes,
-                                    bool &o_invalidFails_inTx_Ofendp1,
-                                    bool &o_invalidFails_inRx_Ofendp2);
-
-/**
- * @brief This function gets the eRepair threshold value of the passed target
- *        for the particular IPL type.
- *
- * @param [in]   i_endp_target The target for whose type the threshold value
- *                             is needed
- * @param [in]   i_mfgModeIPL  If TRUE, indicates that this is a MnfgMode IPL
- *                             If FALSE, indicates that this is a Normal IPL
- * @param [out]  o_threshold   The threshold return value
- *
- * @return ReturnCode
- */
-fapi::ReturnCode geteRepairThreshold(const fapi::Target &i_endp_target,
-                                     const bool         i_mfgModeIPL,
-                                     uint8_t            &o_threshold);
-
-/**
- * @brief This function determines the lane numbers that needs to be spared
- *        to support Corner testing.
- *
- * @param [in]  i_tgtType            The target type(XBus or ABus or DMIBus) for
- *                                   which the lanes that need to be spared are
- *                                   determined
- * @param [out] o_endp1_txFailLanes  The reference to the vector which will
- *                                   have the Tx side of lanes that need to be
- *                                   spared for endp1
- * @param [out] o_endp1_rxFailLanes  The reference to the vector which will
- *                                   have the Rx side of lanes that need to be
- *                                   spared for endp1
- * @param [out] o_endp2_txFailLanes  The reference to the vector which will
- *                                   have the Tx side of lanes that need to be
- *                                   spared for endp2
- * @param [out] o_endp2_rxFailLanes  The reference to the vector which will
- *                                   have the Rx side of lanes that need to be
- *                                   spared for endp2
- *
- * @return void
- */
-void getCornerTestingLanes(const fapi::TargetType i_tgtType,
-                           std::vector<uint8_t> &o_endp1_txFailLanes,
-                           std::vector<uint8_t> &o_endp1_rxFailLanes,
-                           std::vector<uint8_t> &o_endp2_txFailLanes,
-                           std::vector<uint8_t> &o_endp2_rxFailLanes);
-
-/**
- * @brief This function combines the eRepair lane numbers read from
- *        Manufacturing VPD and Field VPD
- *
- * @param [in]  i_mnfgFaillanes  The eRepair lane numbers read from the
- *                               Manufacturing VPD
- * @param [in]  i_fieldFaillanes The eRepair lane numbers read from the
- *                               Field VPD
- * @param [out] o_allFaillanes   The eRepair lane numbers which is the union
- *                               of the Field and Manufacturing eRepair lanes
- *                               passed as first iand second params
- *
- * @return void
- */
-void combineFieldandMnfgLanes(std::vector<uint8_t> &i_mnfgFaillanes,
-                              std::vector<uint8_t> &i_fieldFaillanes,
-                              std::vector<uint8_t> &o_allFailLanes);
-
-#ifndef __HOSTBOOT_MODULE
-/**
- * @brief: This function checks to see if the no.of fail lanes exceed the
- *         threshold on the sub-interfaces(Tx, Rx),in the scenario where
- *         a new drawer is being added through CHARM.
- *         The Tx lanes of endp1 will be combined with the Rx lanes of endp2
- *         and verified whether the combined value exceeds the threshold.
- *         Same verificatiion is done with Tx of endp2 and Rx of endp1
- *
- * @param [in] i_endp1_txFaillanes  Reference to vector which will have fail
- *                                  lane numbers of Tx of endp1
- * @param [in] i_endp1_rxFaillanes  Reference to vector which will have fail
- *                                  lane numbers of Rx of endp1
- * @param [in] i_endp2_txFaillanes  Reference to vector which will have fail
- *                                  lane numbers of Tx of endp2
- * @param [in] i_endp2_rxFaillanes  Reference to vector which will have fail
- *                                  lane numbers of Rx of endp2
- * @param [in] i_threshold          The eRepair threshold limit
- *
- * @return bool If TRUE, indicates that the threshold has been crossed,
- *               FALSE, otherwise.
- */
-bool charmModeThresholdExceed(std::vector<uint8_t> &o_endp1_txFaillanes,
-                              std::vector<uint8_t> &o_endp1_rxFaillanes,
-                              std::vector<uint8_t> &o_endp2_txFaillanes,
-                              std::vector<uint8_t> &o_endp2_rxFaillanes,
-                              const uint8_t        i_threshold);
-#endif
-
-
-/***** Function definitions *****/
-
-fapi::ReturnCode erepairGetRestoreLanes(const fapi::Target &i_endp1_target,
-                                      std::vector<uint8_t> &o_endp1_txFaillanes,
-                                      std::vector<uint8_t> &o_endp1_rxFaillanes,
-                                      const fapi::Target   &i_endp2_target,
-                                      std::vector<uint8_t> &o_endp2_txFaillanes,
-                                      std::vector<uint8_t> &o_endp2_rxFaillanes)
-{
-    fapi::ReturnCode l_rc;
-
-    std::vector<uint8_t>    l_endp1_txFieldFaillanes;
-    std::vector<uint8_t>    l_endp1_rxFieldFaillanes;
-    std::vector<uint8_t>    l_endp1_txMnfgFaillanes;
-    std::vector<uint8_t>    l_endp1_rxMnfgFaillanes;
-
-    std::vector<uint8_t>    l_endp2_txFieldFaillanes;
-    std::vector<uint8_t>    l_endp2_rxFieldFaillanes;
-    std::vector<uint8_t>    l_endp2_txMnfgFaillanes;
-    std::vector<uint8_t>    l_endp2_rxMnfgFaillanes;
-
-    bool                    l_mnfgModeIPL          = false;
-    bool                    l_charmModeIPL         = false;
-    bool                    l_enableDmiSpares      = false;
-    bool                    l_enableFabricSpares   = false;
-    bool                    l_disableFabricERepair = false;
-    bool                    l_disableMemoryERepair = false;
-    bool                    l_thresholdExceed      = false;
-    uint8_t                 l_threshold            = 0;
-    uint64_t                l_allMnfgFlags         = 0;
-    uint32_t                l_numTxFailLanes       = 0;
-    uint32_t                l_numRxFailLanes       = 0;
-    fapi::TargetType        l_endp1_tgtType = fapi::TARGET_TYPE_NONE;
-    fapi::TargetType        l_endp2_tgtType = fapi::TARGET_TYPE_NONE;
-
-    FAPI_INF(">>erepairGetRestoreLanes: endp1 = %s, endp2 = %s",
-             i_endp1_target.toEcmdString(), i_endp2_target.toEcmdString());
-
-    do
-    {
-        l_rc = FAPI_ATTR_GET(ATTR_MNFG_FLAGS, NULL, l_allMnfgFlags);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairGetRestoreLanes: Unable to read attribute"
-                     " - ATTR_MNFG_FLAGS");
-            break;
-        }
-
-        // Check if MNFG_DISABLE_FABRIC_EREPAIR is enabled
-        l_disableFabricERepair = false;
-        if(l_allMnfgFlags &
-           fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_DISABLE_FABRIC_eREPAIR)
-        {
-            l_disableFabricERepair = true;
-        }
-
-        // Check if MNFG_DISABLE_MEMORY_EREPAIR is enabled
-        l_disableMemoryERepair = false;
-        if(l_allMnfgFlags &
-           fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_DISABLE_MEMORY_eREPAIR)
-        {
-            l_disableMemoryERepair = true;
-        }
-
-        // Check if this is Manufacturing mode IPL.
-        l_mnfgModeIPL = false;
-        if(l_allMnfgFlags & fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS)
-        {
-            l_mnfgModeIPL = true;
-        }
-
-        // Get the type of passed targets
-        l_endp1_tgtType = i_endp1_target.getType();
-        l_endp2_tgtType = i_endp2_target.getType();
-
-        // Check if the correct target types are passed
-        if(l_endp1_tgtType == fapi::TARGET_TYPE_XBUS_ENDPOINT ||
-           l_endp1_tgtType == fapi::TARGET_TYPE_ABUS_ENDPOINT)
-        {
-            if(l_endp1_tgtType != l_endp2_tgtType)
-            {
-                FAPI_ERR("erepairGetRestoreLanes: Invalid endpoint target"
-                         " type %d-%d", l_endp1_tgtType, l_endp2_tgtType);
-
-                FAPI_SET_HWP_ERROR(l_rc,RC_EREPAIR_RESTORE_INVALID_TARGET_PAIR);
-                break;
-            }
-
-            if(l_mnfgModeIPL && l_disableFabricERepair)
-            {
-                // Fabric eRepair has been disabled using the
-                // Manufacturing policy flags
-                FAPI_INF("erepairGetRestoreLanes: Fabric eRepair is disabled");
-                break;
-            }
-        }
-        else if((l_endp1_tgtType    == fapi::TARGET_TYPE_MCS_CHIPLET
-                 && l_endp2_tgtType != fapi::TARGET_TYPE_MEMBUF_CHIP) ||
-                (l_endp1_tgtType    == fapi::TARGET_TYPE_MEMBUF_CHIP
-                 && l_endp2_tgtType != fapi::TARGET_TYPE_MCS_CHIPLET))
-        {
-            FAPI_ERR("erepairGetRestoreLanes: Invalid endpoint target"
-                     " type %d-%d", l_endp1_tgtType, l_endp2_tgtType);
-
-            FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_RESTORE_INVALID_TARGET_PAIR);
-            break;
-        }
-        else if(l_mnfgModeIPL && l_disableMemoryERepair)
-        {
-            // Memory eRepair has been disabled using the
-            // Manufacturing policy flags
-            FAPI_INF("erepairGetRestoreLanes: Memory eRepair is disabled");
-            break;
-        }
-
-#ifndef __HOSTBOOT_MODULE
-        // TODO: Check if this is CHARM mode IPL. RTC: 59493
-        // l_charmModeIPL = <read_TBD>
-
-        if(l_mnfgModeIPL && l_charmModeIPL)
-        {
-            // TODO: Review this policy during CHARM  supportcode review.
-            // RTC: 59493
-            FAPI_ERR("erepairGetRestoreLanes: Manufactuing flags should not"
-                     " be enabled during CHARM operation. Ignoring the"
-                     " Manufacturing flags for eRepair");
-        }
-#endif
-
-        if(l_mnfgModeIPL)
-        {
-            /***** Check Field VPD *****/
-
-            // Do not allow eRepair data in Field VPD during Mfg Mode IPL
-            l_rc = mnfgCheckFieldVPD(i_endp1_target,
-                                     i_endp2_target);
-            if(l_rc)
-            {
-                FAPI_ERR("erepairGetRestoreLanes:Error from mnfgCheckFieldVPD");
-                break;
-            }
-
-            /***** Read Manufacturing VPD *****/
-            l_rc = getVerifiedRepairLanes(i_endp1_target,
-                                          o_endp1_txFaillanes,
-                                          o_endp1_rxFaillanes,
-                                          i_endp2_target,
-                                          o_endp2_txFaillanes,
-                                          o_endp2_rxFaillanes,
-                                          l_charmModeIPL,
-                                          EREPAIR_VPD_MNFG);
-            if(l_rc)
-            {
-                FAPI_ERR("erepairGetRestoreLanes: Error from"
-                         " getVerifiedRepairLanes(Mnfg)");
-                break;
-            }
-        }
-        else
-        {   /***** Normal Mode IPL *****/
-
-            // During Normal mode IPL we read both Mnfg and Field VPD
-            // for restoring eRepair lanes
-
-            /***** Read Manufacturing VPD *****/
-
-            l_rc = getVerifiedRepairLanes(i_endp1_target,
-                                          l_endp1_txMnfgFaillanes,
-                                          l_endp1_rxMnfgFaillanes,
-                                          i_endp2_target,
-                                          l_endp2_txMnfgFaillanes,
-                                          l_endp2_rxMnfgFaillanes,
-                                          l_charmModeIPL,
-                                          EREPAIR_VPD_MNFG);
-            if(l_rc)
-            {
-                FAPI_ERR("erepairGetRestoreLanes: Error from"
-                         " getVerifiedRepairLanes(Mnfg)");
-                break;
-            }
-
-            /***** Read Field VPD *****/
-
-            l_rc = getVerifiedRepairLanes(i_endp1_target,
-                                          l_endp1_txFieldFaillanes,
-                                          l_endp1_rxFieldFaillanes,
-                                          i_endp2_target,
-                                          l_endp2_txFieldFaillanes,
-                                          l_endp2_rxFieldFaillanes,
-                                          l_charmModeIPL,
-                                          EREPAIR_VPD_FIELD);
-            if(l_rc)
-            {
-                FAPI_ERR("erepairGetRestoreLanes: Error from"
-                         " getVerifiedRepairLanes(Field)");
-                break;
-            }
-
-            /***** Combine the Mnfg and Field eRepair lanes *****/
-
-            // Combine the Tx side fail lanes of endp1
-            combineFieldandMnfgLanes(l_endp1_txMnfgFaillanes,
-                                     l_endp1_txFieldFaillanes,
-                                     o_endp1_txFaillanes);
-
-            // Combine the Rx side fail lanes of endp1
-            combineFieldandMnfgLanes(l_endp1_rxMnfgFaillanes,
-                                     l_endp1_rxFieldFaillanes,
-                                     o_endp1_rxFaillanes);
-
-            // Combine the Tx side fail lanes of endp2
-            combineFieldandMnfgLanes(l_endp2_txMnfgFaillanes,
-                                     l_endp2_txFieldFaillanes,
-                                     o_endp2_txFaillanes);
-
-            // Combine the Rx side fail lanes of endp1
-            combineFieldandMnfgLanes(l_endp2_rxMnfgFaillanes,
-                                     l_endp2_rxFieldFaillanes,
-                                     o_endp2_rxFaillanes);
-
-        } // end of else block of "if(l_mnfgModeIPL)"
-
-
-        /***** Remove invalid lane numbers *****/
-
-        // Check if there are invalid lanes in Tx side of endp1.
-        // If found, erase them from the vector
-        o_endp1_txFaillanes.erase(std::remove(o_endp1_txFaillanes.begin(),
-                                              o_endp1_txFaillanes.end(),
-                                              INVALID_FAIL_LANE_NUMBER),
-                                  o_endp1_txFaillanes.end());
-
-        // Check if there are invalid lanes in Rx side of endp1.
-        // If found, erase them from the vector
-        o_endp1_rxFaillanes.erase(std::remove(o_endp1_rxFaillanes.begin(),
-                                              o_endp1_rxFaillanes.end(),
-                                              INVALID_FAIL_LANE_NUMBER),
-                                  o_endp1_rxFaillanes.end());
-
-        // Check if there are invalid lanes in Tx side of endp2.
-        // If found, erase them from the vector
-        o_endp2_txFaillanes.erase(std::remove(o_endp2_txFaillanes.begin(),
-                                              o_endp2_txFaillanes.end(),
-                                              INVALID_FAIL_LANE_NUMBER),
-                                  o_endp2_txFaillanes.end());
-
-        // Check if there are invalid lanes in Rx side of endp2.
-        // If found, erase them from the vector
-        o_endp2_rxFaillanes.erase(std::remove(o_endp2_rxFaillanes.begin(),
-                                              o_endp2_rxFaillanes.end(),
-                                              INVALID_FAIL_LANE_NUMBER),
-                                  o_endp2_rxFaillanes.end());
-
-        /***** Check for threshold exceed conditions *****/
-
-        // Get the eRepair threshold limit
-        l_threshold = 0;
-        l_rc = geteRepairThreshold(i_endp1_target, l_mnfgModeIPL, l_threshold);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairGetRestoreLanes: Error from geteRepairThreshold");
-            break;
-        }
-
-        // Check if the eRepair threshold has exceeded for Tx side of endp1
-        if(o_endp1_txFaillanes.size() > l_threshold)
-        {
-            l_thresholdExceed = true;
-            l_numTxFailLanes = o_endp1_txFaillanes.size();
-
-            FAPI_ERR("erepairGetRestoreLanes: eRepair threshold exceed error"
-                     " seen in Tx of endp1 target. No.of lanes: %d",
-                     l_numTxFailLanes);
-        }
-
-        // Check if the eRepair threshold has exceeded for Rx side of endp1
-        if(o_endp1_rxFaillanes.size() > l_threshold)
-        {
-            l_thresholdExceed = true;
-            l_numRxFailLanes = o_endp1_rxFaillanes.size();
-
-            FAPI_ERR("erepairGetRestoreLanes: eRepair threshold exceed error"
-                     " seen in Rx of endp1 target. No.of lanes: %d",
-                     l_numRxFailLanes);
-        }
-
-        // Check if the eRepair threshold has exceeded for Tx side of endp2
-        if(o_endp2_txFaillanes.size() > l_threshold)
-        {
-            l_thresholdExceed = true;
-            l_numTxFailLanes = o_endp2_txFaillanes.size();
-
-            FAPI_ERR("erepairGetRestoreLanes: eRepair threshold exceed error"
-                     " seen in Tx of endp2 target. No.of lanes: %d",
-                     l_numTxFailLanes);
-        }
-
-        // Check if the eRepair threshold has exceeded for Rx side of endp2
-        if(o_endp2_rxFaillanes.size() > l_threshold)
-        {
-            l_thresholdExceed = true;
-            l_numRxFailLanes = o_endp2_rxFaillanes.size();
-
-            FAPI_ERR("erepairGetRestoreLanes: eRepair threshold exceed error"
-                     " seen in Rx of endp2 target. No.of lanes: %d",
-                     l_numRxFailLanes);
-        }
-
-        if(l_thresholdExceed)
-        {
-            FAPI_ERR("erepairGetRestoreLanes: Threshold has Exceeded");
-
-            const uint32_t &FFDC_TX_NUM_LANES = l_numTxFailLanes;
-            const uint32_t &FFDC_RX_NUM_LANES = l_numRxFailLanes;
-            const uint32_t &FFDC_THRESHOLD    = l_threshold;
-            FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_THRESHOLD_EXCEED);
-            break;
-        }
-
-#ifndef __HOSTBOOT_MODULE
-        // Check threshold exceed scenario during CHARM mode IPL
-        bool l_charmThresholdExceed = false;
-
-        if(l_charmModeIPL)
-        {
-            l_charmThresholdExceed = false;
-            l_charmThresholdExceed = charmModeThresholdExceed(
-                                                         o_endp1_txFaillanes,
-                                                         o_endp1_rxFaillanes,
-                                                         o_endp2_txFaillanes,
-                                                         o_endp2_rxFaillanes,
-                                                         l_threshold);
-
-            if(l_charmThresholdExceed)
-            {
-                FAPI_ERR("erepairGetRestoreLanes: CHARM IPL, Threshold Exceed");
-
-                FAPI_SET_HWP_ERROR(l_rc,
-                                   RC_EREPAIR_RESTORE_CHARM_THRESHOLD_EXCEED);
-                break;
-            }
-        }
-#endif
-        if(l_mnfgModeIPL)
-        {
-            // Check if MNFG_DMI_DEPLOY_LANE_SPARES is enabled
-            l_enableDmiSpares = false;
-            if(l_allMnfgFlags &
-               fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_DMI_DEPLOY_LANE_SPARES)
-            {
-                l_enableDmiSpares = true;
-            }
-
-            // Check if MNFG_FABRIC_DEPLOY_LANE_SPARES is enabled
-            l_enableFabricSpares = false;
-            if(l_allMnfgFlags &
-               fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_FABRIC_DEPLOY_LANE_SPARES)
-            {
-                l_enableFabricSpares = true;
-            }
-
-            if(l_enableDmiSpares || l_enableFabricSpares)
-            {
-                // This is a Corner testing IPL.
-                // eRepair Restore the pre-determined memory lanes
-                getCornerTestingLanes(l_endp1_tgtType,
-                                      o_endp1_txFaillanes,
-                                      o_endp1_rxFaillanes,
-                                      o_endp2_txFaillanes,
-                                      o_endp2_rxFaillanes);
-            }
-        } // end of if(l_mnfgModeIPL)
-    }while(0);
-
-    return l_rc;
-}
-
-void combineFieldandMnfgLanes(std::vector<uint8_t> &i_mnfgFaillanes,
-                              std::vector<uint8_t> &i_fieldFaillanes,
-                              std::vector<uint8_t> &o_allFaillanes)
-{
-    std::vector<uint8_t>::iterator l_it;
-
-    // Merge the Field and Mnfg fail lanes
-    l_it = o_allFaillanes.begin();
-    o_allFaillanes.insert(l_it,
-                          i_mnfgFaillanes.begin(),
-                          i_mnfgFaillanes.end());
-
-    l_it = o_allFaillanes.end();
-    o_allFaillanes.insert(l_it,
-                          i_fieldFaillanes.begin(),
-                          i_fieldFaillanes.end());
-
-    // Check if Mfg VPD and Field VPD have same fail lanes.
-    // If found, erase them
-    std::sort(o_allFaillanes.begin(), o_allFaillanes.end());
-
-    o_allFaillanes.erase(std::unique(o_allFaillanes.begin(),
-                                     o_allFaillanes.end()),
-                         o_allFaillanes.end());
-
-}
-
-void getCornerTestingLanes(const fapi::TargetType i_tgtType,
-                           std::vector<uint8_t> &o_endp1_txFaillanes,
-                           std::vector<uint8_t> &o_endp1_rxFaillanes,
-                           std::vector<uint8_t> &o_endp2_txFaillanes,
-                           std::vector<uint8_t> &o_endp2_rxFaillanes)
-{
-    std::vector<uint8_t>::iterator l_it;
-    uint8_t l_deployIndx = 0;
-    uint8_t l_maxDeploys = 0;
-    uint8_t *l_deployPtr = NULL;
-
-    uint8_t l_xDeployLanes[XBUS_MAXSPARES_IN_HW] = {XBUS_SPARE_DEPLOY_LANE_1,
-                                                    XBUS_SPARE_DEPLOY_LANE_2};
-
-    uint8_t l_aDeployLanes[ABUS_MAXSPARES_IN_HW] = {ABUS_SPARE_DEPLOY_LANE_1};
-
-    uint8_t l_dmiDeployLanes[DMIBUS_MAXSPARES_IN_HW] = {
-                                                 DMIBUS_SPARE_DEPLOY_LANE_1,
-                                                 DMIBUS_SPARE_DEPLOY_LANE_2};
-
-    // Idea is to push_back the pre-determined lanes into the Tx and Rx
-    // vectors of endpoint1 and endpoint2
-    do
-    {
-        switch(i_tgtType)
-        {
-            case fapi::TARGET_TYPE_XBUS_ENDPOINT:
-                l_maxDeploys = XBUS_MAXSPARES_IN_HW;
-                l_deployPtr = l_xDeployLanes;
-                break;
-
-            case fapi::TARGET_TYPE_ABUS_ENDPOINT:
-                l_maxDeploys = ABUS_MAXSPARES_IN_HW;
-                l_deployPtr = l_aDeployLanes;
-                break;
-
-            case fapi::TARGET_TYPE_MCS_CHIPLET:
-            case fapi::TARGET_TYPE_MEMBUF_CHIP:
-                l_maxDeploys = DMIBUS_MAXSPARES_IN_HW;
-                l_deployPtr = l_dmiDeployLanes;
-                break;
-
-            default:
-                FAPI_ERR("getCornerTestingLanes: Invalid target type");
-                break;
-        };
-
-        std::sort(o_endp1_txFaillanes.begin(), o_endp1_txFaillanes.end());
-        std::sort(o_endp1_rxFaillanes.begin(), o_endp1_rxFaillanes.end());
-
-        for(l_deployIndx = 0;
-            ((l_deployIndx < l_maxDeploys) &&
-             (o_endp1_txFaillanes.size() < l_maxDeploys));
-            l_deployIndx++)
-        {
-            l_it = std::find(o_endp1_txFaillanes.begin(),
-                             o_endp1_txFaillanes.end(),
-                             l_deployPtr[l_deployIndx]);
-
-            if(l_it == o_endp1_txFaillanes.end())
-            {
-                o_endp1_txFaillanes.push_back(l_deployPtr[l_deployIndx]);
-            }
-        }
-
-        for(l_deployIndx = 0;
-            ((o_endp1_rxFaillanes.size() < l_maxDeploys) &&
-             (l_deployIndx < l_maxDeploys));
-            l_deployIndx++)
-        {
-            l_it = std::find(o_endp1_rxFaillanes.begin(),
-                             o_endp1_rxFaillanes.end(),
-                             l_deployPtr[l_deployIndx]);
-
-            if(l_it == o_endp1_rxFaillanes.end())
-            {
-                o_endp1_rxFaillanes.push_back(l_deployPtr[l_deployIndx]);
-            }
-        }
-
-        // We can cassign the lanes of endpoint1 to endpoint2 because any
-        // existing faillanes in endpoint2 have already been matched with
-        // endpoint1. This means that there cannot be any faillanes in
-        // endpoint2 that do not have equivalent lanes in endpoint1.
-        o_endp2_txFaillanes = o_endp1_txFaillanes;
-        o_endp2_rxFaillanes = o_endp1_rxFaillanes;
-
-    }while(0);
-}
-
-fapi::ReturnCode geteRepairThreshold(const fapi::Target &i_endp_target,
-                                     const bool         i_mfgModeIPL,
-                                     uint8_t            &o_threshold)
-{
-    fapi::ReturnCode l_rc;
-    fapi::TargetType l_tgtType = fapi::TARGET_TYPE_NONE;
-
-    do
-    {
-        o_threshold = 0;
-        l_tgtType = i_endp_target.getType();
-
-        if(i_mfgModeIPL)
-        {
-            switch(l_tgtType)
-            {
-                case fapi::TARGET_TYPE_XBUS_ENDPOINT:
-                     l_rc = FAPI_ATTR_GET(ATTR_X_EREPAIR_THRESHOLD_MNFG,
-                                          NULL,
-                                          o_threshold);
-                    break;
-
-                case fapi::TARGET_TYPE_ABUS_ENDPOINT:
-                     l_rc = FAPI_ATTR_GET(ATTR_A_EREPAIR_THRESHOLD_MNFG,
-                                          NULL,
-                                          o_threshold);
-                    break;
-
-                case fapi::TARGET_TYPE_MCS_CHIPLET:
-                case fapi::TARGET_TYPE_MEMBUF_CHIP:
-                     l_rc = FAPI_ATTR_GET(ATTR_DMI_EREPAIR_THRESHOLD_MNFG,
-                                          NULL,
-                                          o_threshold);
-                    break;
-
-                default:
-                    FAPI_ERR("geteRepairThreshold: Invalid target type %d",
-                             l_tgtType);
-                    FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_RESTORE_INVALID_TARGET);
-                    break;
-            };
-        }
-        else
-        {
-            switch(l_tgtType)
-            {
-                case fapi::TARGET_TYPE_XBUS_ENDPOINT:
-                     l_rc = FAPI_ATTR_GET(ATTR_X_EREPAIR_THRESHOLD_FIELD,
-                                          NULL,
-                                          o_threshold);
-                    break;
-
-                case fapi::TARGET_TYPE_ABUS_ENDPOINT:
-                     l_rc = FAPI_ATTR_GET(ATTR_A_EREPAIR_THRESHOLD_FIELD,
-                                          NULL,
-                                          o_threshold);
-                    break;
-
-                case fapi::TARGET_TYPE_MCS_CHIPLET:
-                case fapi::TARGET_TYPE_MEMBUF_CHIP:
-                     l_rc = FAPI_ATTR_GET(ATTR_DMI_EREPAIR_THRESHOLD_FIELD,
-                                          NULL,
-                                          o_threshold);
-                    break;
-
-                default:
-                    FAPI_ERR("geteRepairThreshold: Invalid target type %d",
-                             l_tgtType);
-                    FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_RESTORE_INVALID_TARGET);
-                    break;
-            };
-        }
-    }while(0);
-
-    FAPI_INF("geteRepairThreshold: o_threshold = %d", o_threshold);
-    return l_rc;
-}
-
-fapi::ReturnCode mnfgCheckFieldVPD(const fapi::Target &i_endp1_target,
-                                   const fapi::Target &i_endp2_target)
-{
-    fapi::ReturnCode l_rc;
-    std::vector<uint8_t> l_endp1_txFaillanes;
-    std::vector<uint8_t> l_endp1_rxFaillanes;
-    std::vector<uint8_t> l_endp2_txFaillanes;
-    std::vector<uint8_t> l_endp2_rxFaillanes;
-    bool l_fieldVPDClear = true;
-
-    do
-    {
-        l_fieldVPDClear = true;
-
-        /***** Read Field VPD *****/
-
-        // During Mfg mode IPL, field VPD need to be clear.
-
-        // Get failed lanes for endp1
-        l_rc = erepairGetFieldFailedLanes(i_endp1_target,
-                                          l_endp1_txFaillanes,
-                                          l_endp1_rxFaillanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("mnfgCheckFieldVPD: Error from erepairGetFieldFailedLanes"
-                    " for %s",i_endp1_target.toEcmdString());
-            break;
-        }
-
-        // If there are fail lanes in Field VPD on endpoint1, create an
-        // error log and return
-        if(l_endp1_txFaillanes.size() ||
-           l_endp1_rxFaillanes.size())
-        {
-            l_fieldVPDClear = false;
-
-            FAPI_ERR("mnfgCheckFieldVPD: eRepair records found in"
-                     " Field VPD, in Tx of %s during Manufacturing mode IPL",
-                     i_endp1_target.toEcmdString());
-        }
-
-        // Get failed lanes for endp2
-        l_rc = erepairGetFieldFailedLanes(i_endp2_target,
-                                          l_endp2_txFaillanes,
-                                          l_endp2_rxFaillanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("mnfgCheckFieldVPD: Error from erepairGetFieldFailedLanes"
-                     " for %s",i_endp2_target.toEcmdString());
-            break;
-        }
-
-        // If there are fail lanes in Field VPD on endpoint2, create an
-        // error log and return
-        if(l_endp2_txFaillanes.size() ||
-           l_endp2_rxFaillanes.size())
-        {
-            l_fieldVPDClear = false;
-
-            FAPI_ERR("mnfgCheckFieldVPD: eRepair records found in"
-                     " Field VPD, in Rx of %s during Manufacturing mode IPL",
-                     i_endp2_target.toEcmdString());
-        }
-
-        if(l_fieldVPDClear != true)
-        {
-            FAPI_ERR("mnfgCheckFieldVPD: Field VPD need to be clear"
-                     " during Mnfg mode IPL");
-
-            FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_RESTORE_FIELD_VPD_NOT_CLEAR);
-        }
-    }while(0);
-
-    return (l_rc);
-}
-
-fapi::ReturnCode getVerifiedRepairLanes(
-                                  const fapi::Target   &i_endp1_target,
-                                  std::vector<uint8_t> &o_endp1_txFaillanes,
-                                  std::vector<uint8_t> &o_endp1_rxFaillanes,
-                                  const fapi::Target   &i_endp2_target,
-                                  std::vector<uint8_t> &o_endp2_txFaillanes,
-                                  std::vector<uint8_t> &o_endp2_rxFaillanes,
-                                  const bool           i_charmModeIPL,
-                                  const erepairVpdType i_vpdType)
-{
-    fapi::ReturnCode l_rc;
-
-    getLanes_t l_getLanes = NULL;
-    setLanes_t l_setLanes = NULL;
-
-    fapi::Target l_target[2] = {i_endp1_target, i_endp2_target};
-    bool         l_invalidFails_inTx_OfTgt[2] = {false, false};
-    bool         l_invalidFails_inRx_OfTgt[2] = {false, false};
-    uint8_t      l_tgtIndx = 0;
-
-    std::vector<uint8_t> l_emptyVector;
-    std::vector<uint8_t> l_txFaillanes;
-    std::vector<uint8_t> l_rxFaillanes;
-
-    FAPI_INF(">> getVerifiedRepairLanes: charm: %d, vpdType: %s",
-             i_charmModeIPL, i_vpdType == EREPAIR_VPD_FIELD ? "Field":"Mnfg");
-
-    do
-    {
-        /***** Read VPD *****/
-
-        if(i_vpdType == EREPAIR_VPD_FIELD)
-        {
-            l_getLanes = &erepairGetFieldFailedLanes;
-            l_setLanes = &erepairSetFieldFailedLanes;
-        }
-        else if(i_vpdType == EREPAIR_VPD_MNFG)
-        {
-            l_getLanes = &erepairGetMnfgFailedLanes;
-            l_setLanes = &erepairSetMnfgFailedLanes;
-        }
-
-        for(l_tgtIndx = 0; l_tgtIndx < 2; l_tgtIndx++)
-        {
-            // Get failed lanes for endp1 and endp2
-            l_rc = l_getLanes(l_target[l_tgtIndx],
-                              l_txFaillanes,
-                              l_rxFaillanes);
-
-            if(l_rc)
-            {
-                FAPI_ERR("getVerifiedRepairLanes: Error while getting failed"
-                         " lanes for %s",
-                         l_target[l_tgtIndx].toEcmdString());
-                break;
-            }
-
-            if(l_tgtIndx == 0)
-            {
-                o_endp1_txFaillanes = l_txFaillanes;
-                o_endp1_rxFaillanes = l_rxFaillanes;
-            }
-            else
-            {
-                o_endp2_txFaillanes = l_txFaillanes;
-                o_endp2_rxFaillanes = l_rxFaillanes;
-            }
-
-            l_txFaillanes.clear();
-            l_rxFaillanes.clear();
-        } // end of for(l_tgtIndx)
-
-        if(l_rc)
-        {
-            // break out of do-while(0) loop
-            break;
-        }
-
-        /***** Verify eRepair data *****/
-
-        // Do not check for matching fail lanes on the other end
-        // if this is a CHARM mode IPL
-        if(i_charmModeIPL == true)
-        {
-            break;
-        }
-
-        // Check if matching fail lanes exists on the sub-interfaces
-        // connecting the two end points
-        if(o_endp1_txFaillanes.size() || o_endp2_rxFaillanes.size())
-        {
-            invalidateNonMatchingFailLanes(o_endp1_txFaillanes,
-                                           o_endp2_rxFaillanes,
-                                           l_invalidFails_inTx_OfTgt[0],
-                                           l_invalidFails_inRx_OfTgt[1]);
-        }
-
-        if(o_endp2_txFaillanes.size() || o_endp1_rxFaillanes.size())
-        {
-            invalidateNonMatchingFailLanes(o_endp2_txFaillanes,
-                                           o_endp1_rxFaillanes,
-                                           l_invalidFails_inTx_OfTgt[1],
-                                           l_invalidFails_inRx_OfTgt[0]);
-        }
-
-        /***** Correct eRepair data of endp1 in VPD *****/
-
-        for(l_tgtIndx = 0; l_tgtIndx < 2; l_tgtIndx++)
-        {
-            if(l_tgtIndx == 0)
-            {
-                l_txFaillanes = o_endp1_txFaillanes;
-                l_rxFaillanes = o_endp1_rxFaillanes;
-            }
-            else
-            {
-                l_txFaillanes = o_endp2_txFaillanes;
-                l_rxFaillanes = o_endp2_rxFaillanes;
-            }
-
-            // Update endp1 and endp2 VPD to invalidate fail lanes that do
-            // not have matching fail lanes on the other end
-            if(l_invalidFails_inTx_OfTgt[l_tgtIndx] &&
-               l_invalidFails_inRx_OfTgt[l_tgtIndx])
-            {
-                l_rc = l_setLanes(l_target[l_tgtIndx],
-                                  l_txFaillanes,
-                                  l_rxFaillanes);
-                if(l_rc)
-                {
-                    FAPI_ERR("getVerifiedRepairLanes: Error while setting"
-                             " lanes for Tx and Rx on %s",
-                             l_target[l_tgtIndx].toEcmdString());
-                    break;
-                }
-            }
-            else if(l_invalidFails_inTx_OfTgt[l_tgtIndx])
-            {
-                l_rc = l_setLanes(l_target[l_tgtIndx],
-                                  l_txFaillanes,
-                                  l_emptyVector);
-                if(l_rc)
-                {
-                    FAPI_ERR("getVerifiedRepairLanes: Error while setting"
-                             " lanes for Tx on %s",
-                             l_target[l_tgtIndx].toEcmdString());
-                    break;
-                }
-            }
-            else if(l_invalidFails_inRx_OfTgt[l_tgtIndx])
-            {
-                l_rc = l_setLanes(l_target[l_tgtIndx],
-                                  l_emptyVector,
-                                  l_rxFaillanes);
-                if(l_rc)
-                {
-                    FAPI_ERR("getVerifiedRepairLanes: Error while setting"
-                              " lanes Rx on %s",
-                              l_target[l_tgtIndx].toEcmdString());
-                    break;
-                }
-            }
-        } // end of for loop
-    }while(0);
-
-    return l_rc;
-}
-
-void invalidateNonMatchingFailLanes(std::vector<uint8_t> &io_endp1_txFaillanes,
-                                    std::vector<uint8_t> &io_endp2_rxFaillanes,
-                                    bool &o_invalidFails_inTx_Ofendp1,
-                                    bool &o_invalidFails_inRx_Ofendp2)
-{
-    std::vector<uint8_t>::iterator l_it;
-    std::vector<uint8_t>::iterator l_itTmp;
-    std::vector<uint8_t>::iterator l_itDrv;
-    std::vector<uint8_t>::iterator l_itRcv;
-
-    o_invalidFails_inTx_Ofendp1 = false;
-    o_invalidFails_inRx_Ofendp2 = false;
-
-    std::sort(io_endp1_txFaillanes.begin(), io_endp1_txFaillanes.end());
-    std::sort(io_endp2_rxFaillanes.begin(), io_endp2_rxFaillanes.end());
-
-    // Start with drive side fail lanes and check for matching lanes
-    // on the recieve side
-    l_itTmp = io_endp2_rxFaillanes.begin();
-    for(l_itDrv = io_endp1_txFaillanes.begin();
-        l_itDrv != io_endp1_txFaillanes.end();
-        l_itDrv++)
-    {
-        l_it = std::lower_bound(io_endp2_rxFaillanes.begin(),
-                                io_endp2_rxFaillanes.end(),
-                                *l_itDrv);
-
-        // If matching fail lane is not found on the receive side,
-        // invalidate the drive side fail lane number
-        if((l_it == io_endp2_rxFaillanes.end()) || (*l_it > *l_itDrv))
-        {
-            *l_itDrv = INVALID_FAIL_LANE_NUMBER;
-            o_invalidFails_inTx_Ofendp1 = true;
-        }
-        else
-        {
-            // save the iterator for the next search
-            l_itTmp = l_it;
-        }
-    }
-
-    // Sort again as we might have invalidated some lanes
-    std::sort(io_endp1_txFaillanes.begin(),io_endp1_txFaillanes.end());
-
-    // Now, traverse through the receive side fail lanes and
-    // check for matching lanes on the drive side
-    for(l_itRcv = io_endp2_rxFaillanes.begin();
-        ((l_itRcv <= l_itTmp) && (l_itRcv != io_endp2_rxFaillanes.end()));
-        l_itRcv++)
-    {
-        l_it = std::lower_bound(io_endp1_txFaillanes.begin(),
-                                io_endp1_txFaillanes.end(),
-                                *l_itRcv);
-
-        // If matching lane is not found on the driver side,
-        // invalidate the receive side fail lane number
-        if((l_it == io_endp1_txFaillanes.end()) || (*l_it > *l_itRcv))
-        {
-            *l_itRcv = INVALID_FAIL_LANE_NUMBER;
-            o_invalidFails_inRx_Ofendp2 = true;
-        }
-    }
-
-    // Need to invalidate all the entries beyond the last
-    // lower bound of first search
-    if(l_itTmp != io_endp2_rxFaillanes.end())
-    {
-        for(l_itTmp++; l_itTmp != io_endp2_rxFaillanes.end(); l_itTmp++)
-        {
-            *l_itTmp = INVALID_FAIL_LANE_NUMBER;
-        }
-    }
-}
-
-fapi::ReturnCode erepairGetFailedLanes(const fapi::Target &i_endp_target,
-                                       std::vector<uint8_t> &o_txFailLanes,
-                                       std::vector<uint8_t> &o_rxFailLanes)
-{
-    fapi::ReturnCode               l_rc;
-    std::vector<uint8_t>           l_txFailLanes;
-    std::vector<uint8_t>           l_rxFailLanes;
-    std::vector<uint8_t>::iterator l_it;
-
-    FAPI_INF(">> erepairGetFailedLanes for %s", i_endp_target.toEcmdString());
-
-    do
-    {
-        // Get the erepair lanes from Field VPD
-        l_rc = erepairGetFieldFailedLanes(i_endp_target,
-                                          l_txFailLanes,
-                                          l_rxFailLanes);
-        if(l_rc)
-        {
-            FAPI_ERR("erepairGetFailedLanes: Error from"
-                     " erepairGetFieldFailedLanes");
-            break;
-        }
-
-        o_txFailLanes = l_txFailLanes;
-        o_rxFailLanes = l_rxFailLanes;
-
-        // Get the erepair lanes from Manufacturing VPD
-        l_txFailLanes.clear();
-        l_rxFailLanes.clear();
-        l_rc = erepairGetMnfgFailedLanes(i_endp_target,
-                                         l_txFailLanes,
-                                         l_rxFailLanes);
-        if(l_rc)
-        {
-            FAPI_ERR("erepairGetFailedLanes: Error from"
-                     " erepairGetMnfgFailedLanes");
-            break;
-        }
-
-        // Merge the Mnfg lanes with the Field lanes
-        l_it = o_txFailLanes.end();
-        o_txFailLanes.insert(l_it, l_txFailLanes.begin(), l_txFailLanes.end());
-
-        l_it = o_rxFailLanes.end();
-        o_rxFailLanes.insert(l_it, l_rxFailLanes.begin(), l_rxFailLanes.end());
-
-    }while(0);
-
-    return l_rc;
-}
-
-fapi::ReturnCode erepairGetFieldFailedLanes(const fapi::Target &i_endp_target,
-                                            std::vector<uint8_t> &o_txFailLanes,
-                                            std::vector<uint8_t> &o_rxFailLanes)
-{
-    fapi::ReturnCode l_rc;
-
-    FAPI_DBG(">> erepairGetFieldFailedLanes for %s", i_endp_target.toEcmdString());
-
-    do
-    {
-        // Execute the Accessor HWP to retrieve the failed lanes from the VPD
-        FAPI_EXEC_HWP(l_rc,
-                      erepairGetFailedLanesHwp,
-                      i_endp_target,
-                      EREPAIR_VPD_FIELD,
-                      o_txFailLanes,
-                      o_rxFailLanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairGetFieldFailedLanes: Error from Accessor HWP:"
-                     " erepairGetFailedLanesHwp");
-            break;
-        }
-
-        // Check if the VPD has any invalid fail lanes on Tx side.
-        // If found, remove them from the list.
-        o_txFailLanes.erase(std::remove(o_txFailLanes.begin(),
-                                        o_txFailLanes.end(),
-                                        INVALID_FAIL_LANE_NUMBER),
-                            o_txFailLanes.end());
-
-        // Check if the VPD has any invalid fail lanes on Rx side.
-        // If found, remove them from the list.
-        o_rxFailLanes.erase(std::remove(o_rxFailLanes.begin(),
-                                        o_rxFailLanes.end(),
-                                        INVALID_FAIL_LANE_NUMBER),
-                            o_rxFailLanes.end());
-    }while(0);
-
-    return l_rc;
-}
-
-
-fapi::ReturnCode erepairGetMnfgFailedLanes(const fapi::Target &i_endp_target,
-                                           std::vector<uint8_t> &o_txFailLanes,
-                                           std::vector<uint8_t> &o_rxFailLanes)
-{
-    fapi::ReturnCode l_rc;
-
-    FAPI_DBG(">> erepairGetMnfgFailedLanes for %s",
-             i_endp_target.toEcmdString());
-    do
-    {
-        // Execute the Accessor HWP to retrieve the failed lanes from the VPD
-        FAPI_EXEC_HWP(l_rc,
-                      erepairGetFailedLanesHwp,
-                      i_endp_target,
-                      EREPAIR_VPD_MNFG,
-                      o_txFailLanes,
-                      o_rxFailLanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairGetMnfgFailedLanes: Error from Accessor HWP:"
-                     " erepairGetFailedLanesHwp");
-            break;
-        }
-
-        // Check if the VPD has any invalid fail lanes on Tx side.
-        // If found, remove them from the list.
-        o_txFailLanes.erase(std::remove(o_txFailLanes.begin(),
-                                        o_txFailLanes.end(),
-                                        INVALID_FAIL_LANE_NUMBER),
-                           o_txFailLanes.end());
-
-        // Check if the VPD has any invalid fail lanes on Rx side.
-        // If found, remove them from the list.
-        o_rxFailLanes.erase(std::remove(o_rxFailLanes.begin(),
-                                        o_rxFailLanes.end(),
-                                        INVALID_FAIL_LANE_NUMBER),
-                            o_rxFailLanes.end());
-    }while(0);
-
-    return l_rc;
-}
-
-fapi::ReturnCode erepairSetFailedLanes(
-                                  const fapi::Target         &i_txEndp_target,
-                                  const fapi::Target         &i_rxEndp_target,
-                                  const std::vector<uint8_t> &i_rxFailLanes,
-                                  bool                       &o_thresholdExceed)
-{
-    fapi::ReturnCode l_rc;
-    uint64_t         l_allMnfgFlags    = 0;
-    bool             l_mnfgModeIPL     = false;
-    uint8_t          l_threshold       = 0;
-    setLanes_t       l_setLanes        = NULL;
-    getLanes_t       l_getLanes        = NULL;
-    std::vector<uint8_t> l_txFaillanes;
-    std::vector<uint8_t> l_rxFaillanes;
-    std::vector<uint8_t> l_emptyVector;
-    std::vector<uint8_t> l_throwAway;
-
-    FAPI_INF(">> erepairSetFailedLanes: %s-%s",
-              i_rxEndp_target.toEcmdString(), i_txEndp_target.toEcmdString());
-
-    do
-    {
-        o_thresholdExceed = false;
-
-        // Get the Manufacturing Policy flags
-        l_rc = FAPI_ATTR_GET(ATTR_MNFG_FLAGS, NULL, l_allMnfgFlags);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairSetFailedLanes: Unable to read attribute"
-                     "ATTR_MNFG_FLAGS");
-            break;
-        }
-
-        // Check if this is a Mnfg mode IPL
-        if(l_allMnfgFlags & fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_THRESHOLDS)
-        {
-            l_mnfgModeIPL = true;
-        }
-
-        if(l_mnfgModeIPL)
-        {
-            l_setLanes = &erepairSetMnfgFailedLanes;
-            l_getLanes = &erepairGetMnfgFailedLanes;
-        }
-        else
-        {
-            l_setLanes = &erepairSetFieldFailedLanes;
-            l_getLanes = &erepairGetFieldFailedLanes;
-        }
-
-        /*** Check if we have crossed the repair threshold ***/
-        // Get the eRepair threshold limit
-        l_threshold = 0;
-        l_rc = geteRepairThreshold(i_rxEndp_target, l_mnfgModeIPL, l_threshold);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairSetFailedLanes: Error (0x%x) from"
-                     " geteRepairThreshold", static_cast<uint32_t> (l_rc));
-            break;
-        }
-
-        // Check if the new fails have crossed the threshold
-        if(i_rxFailLanes.size() > l_threshold)
-        {
-            o_thresholdExceed = true;
-            break;
-        }
-
-        // Get existing fail lanes that are in the VPD of rx endpoint
-        l_rc = l_getLanes(i_rxEndp_target, l_throwAway, l_rxFaillanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairSetFailedLanes: Error (0x%x) from"
-                     " l_getLanes for %s", static_cast<uint32_t> (l_rc),
-                     i_rxEndp_target.toEcmdString());
-            break;
-        }
-
-        // Get existing fail lanes that are in the VPD of tx endpoint
-        l_rc = l_getLanes(i_txEndp_target, l_txFaillanes, l_throwAway);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairSetFailedLanes: Error (0x%x) from"
-                     " l_getLanes for %s", static_cast<uint32_t> (l_rc),
-                     i_txEndp_target.toEcmdString());
-            break;
-        }
-
-        // Lets combine the new and old fail lanes of Rx side
-        l_rxFaillanes.insert(l_rxFaillanes.end(),
-                             i_rxFailLanes.begin(),
-                             i_rxFailLanes.end());
-        // Remove duplicate lanes if any on the Rx side
-        std::sort(l_rxFaillanes.begin(), l_rxFaillanes.end());
-
-        l_rxFaillanes.erase(std::unique(l_rxFaillanes.begin(),
-                                        l_rxFaillanes.end()),
-                            l_rxFaillanes.end());
-
-        // Lets combine the new and old fail lanes of Tx side
-        l_txFaillanes.insert(l_txFaillanes.end(),
-                             i_rxFailLanes.begin(),
-                             i_rxFailLanes.end());
-        // Remove duplicate lanes if any on the Tx side
-        std::sort(l_txFaillanes.begin(), l_txFaillanes.end());
-
-        l_txFaillanes.erase(std::unique(l_txFaillanes.begin(),
-                                        l_txFaillanes.end()),
-                            l_txFaillanes.end());
-
-        // Check if the sum of old and new fail lanes have crossed the threshold
-        if((l_txFaillanes.size() > l_threshold) ||
-           (l_rxFaillanes.size() > l_threshold))
-        {
-            o_thresholdExceed = true;
-            break;
-        }
-
-        /*** Update the VPD ***/
-
-        // Lets write the VPD of endpoint1 with faillanes on Rx side
-        l_rc = l_setLanes(i_rxEndp_target, l_emptyVector, l_rxFaillanes);
-        if(l_rc)
-        {
-            FAPI_ERR("Error from l_setLanes for %s",
-                    i_rxEndp_target.toEcmdString());
-            break;
-        }
-
-        // Lets write the VPD of endpoint2 with faillanes on Tx side
-        l_rc = l_setLanes(i_txEndp_target, l_txFaillanes, l_emptyVector);
-        if(l_rc)
-        {
-            FAPI_ERR("Error from l_setLanes for %s",
-                      i_txEndp_target.toEcmdString());
-            break;
-        }
-    }while(0);
-
-    FAPI_INF("<< erepairSetFailedLanes");
-    return l_rc;
-}
-
-fapi::ReturnCode erepairSetFieldFailedLanes(
-                                      const fapi::Target         &i_endp_target,
-                                      const std::vector<uint8_t> &i_txFailLanes,
-                                      const std::vector<uint8_t> &i_rxFailLanes)
-{
-    fapi::ReturnCode l_rc;
-
-    do
-    {
-        // Execute the Accessor HWP to write the fail lanes to Field VPD
-        FAPI_EXEC_HWP(l_rc,
-                      erepairSetFailedLanesHwp,
-                      i_endp_target,
-                      EREPAIR_VPD_FIELD,
-                      i_txFailLanes,
-                      i_rxFailLanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairSetFieldFailedLanes: Error from Accessor HWP:"
-                     "erepairSetFailedLanesHwp");
-            break;
-        }
-    }while(0);
-
-    return l_rc;
-}
-
-fapi::ReturnCode erepairSetMnfgFailedLanes(
-                                     const fapi::Target   &i_endp_target,
-                                     const std::vector<uint8_t> &i_txFailLanes,
-                                     const std::vector<uint8_t> &i_rxFailLanes)
-{
-    fapi::ReturnCode l_rc;
-
-    do
-    {
-        // Execute the Accessor HWP to write the fail lanes to Mnfg VPD
-        FAPI_EXEC_HWP(l_rc,
-                      erepairSetFailedLanesHwp,
-                      i_endp_target,
-                      EREPAIR_VPD_MNFG,
-                      i_txFailLanes,
-                      i_rxFailLanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("erepairSetMnfgFailedLanes: Error from Accessor HWP:"
-                     "erepairSetMnfgFailedLanesHwp");
-            break;
-        }
-    }while(0);
-
-    return l_rc;
-}
-
-#ifndef __HOSTBOOT_MODULE
-bool charmModeThresholdExceed(std::vector<uint8_t> &i_endp1_txFaillanes,
-                              std::vector<uint8_t> &i_endp1_rxFaillanes,
-                              std::vector<uint8_t> &i_endp2_txFaillanes,
-                              std::vector<uint8_t> &i_endp2_rxFaillanes,
-                              const uint8_t        i_threshold)
-{
-    bool l_thresholdExceed = false;
-    std::vector<uint8_t> l_tmpFaillanes;
-    std::vector<uint8_t>::iterator l_it;
-    std::vector<uint8_t>::iterator l_it2;
-
-    FAPI_INF(">> charmModeThresholdExceed");
-
-    do
-    {
-        // Check for threshold exceed on Tx lanes of endp1 and Rx lanes of endp2
-        l_tmpFaillanes.clear();
-        l_tmpFaillanes = i_endp1_txFaillanes;
-
-        for(l_it = i_endp2_rxFaillanes.begin();
-            l_it != i_endp2_rxFaillanes.end(); l_it++)
-        {
-            // Check for duplicates
-            l_it2 = std::find(l_tmpFaillanes.begin(), l_tmpFaillanes.end(),
-                              *l_it);
-
-            if(l_it2 == l_tmpFaillanes.end())
-            {
-                l_tmpFaillanes.push_back(*l_it);
-            }
-        }
-
-        if(l_tmpFaillanes.size() > i_threshold)
-        {
-            FAPI_ERR("charmModeThresholdExceed: eRepair threshold exceed error"
-                     " seen in Tx side. Threshold: %d", i_threshold);
-
-            l_thresholdExceed = true;
-            break;
-        }
-
-        // Check for threshold exceed on Tx lanes of endp2 and Rx lanes of endp1
-        l_tmpFaillanes.clear();
-        l_tmpFaillanes = i_endp2_txFaillanes;
-        for(l_it = i_endp1_rxFaillanes.begin();
-            l_it != i_endp1_rxFaillanes.end(); l_it++)
-        {
-            // Check for duplicates
-            l_it2 = std::find(l_tmpFaillanes.begin(), l_tmpFaillanes.end(),
-                              *l_it);
-
-            if(l_it2 == l_tmpFaillanes.end())
-            {
-                l_tmpFaillanes.push_back(*l_it);
-            }
-        }
-
-        if(l_tmpFaillanes.size() > i_threshold)
-        {
-            FAPI_ERR("charmModeThresholdExceed: eRepair threshold exceed error"
-                     " seen in Rx side. Threshold: %d", i_threshold);
-
-            l_thresholdExceed = true;
-            break;
-        }
-    }while(0);
-
-    return l_thresholdExceed;
-}
-#endif
diff --git a/src/usr/hwpf/hwp/bus_training/erepairGetFailedLanesHwp.C b/src/usr/hwpf/hwp/bus_training/erepairGetFailedLanesHwp.C
deleted file mode 100644
index 8fc24cc61..000000000
--- a/src/usr/hwpf/hwp/bus_training/erepairGetFailedLanesHwp.C
+++ /dev/null
@@ -1,665 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/erepairGetFailedLanesHwp.C $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: erepairGetFailedLanesHwp.C,v 1.10 2015/03/13 05:14:40 bilicon Exp $
-/**
- *  @file erepairGetFailedLanesHwp.C
- *
- *  @brief FW Team HWP that accesses the fail lanes of Fabric and Memory buses.
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          bilicon     09/14/2012  Created.
- */
-
-#include <erepairGetFailedLanesHwp.H>
-
-using namespace EREPAIR;
-
-extern "C"
-{
-
-/******************************************************************************
- * Forward Declarations
- *****************************************************************************/
-
-/**
- * @brief Function called by the FW Team HWP that reads the data from Field VPD.
- *        This function makes the actual calls to read the VPD
- *        It determines the size of the buffer to be read, allocates memory
- *        of the determined size, calls fapiGetMvpdField to read the eRepair
- *        records. This buffer is further passed to another routine for
- *        parsing.
- *
- * @param[in] i_tgtHandle   Reference to X-Bus or A-Bus or MCS target
- * @param[in] i_vpdType     Specifies which VPD (MNFG or Field) to access.
- * @param[o]  o_txFailLanes Reference to a vector that will hold eRepair fail
- *                          lane numbers of the Tx sub-interface.
- * @param[o]  o_rxFailLanes Reference to a vector that will hold eRepair fail
- *                          lane numbers of the Rx sub-interface.
- *
- * @return ReturnCode
- */
-fapi::ReturnCode retrieveRepairData(const fapi::Target    &i_tgtHandle,
-                                    erepairVpdType        i_vpdType,
-                                    std::vector<uint8_t>  &o_txFailLanes,
-                                    std::vector<uint8_t>  &o_rxFailLanes);
-
-/**
- * @brief Function called by the FW Team HWP that parses the data read from
- *        Field VPD. This function matches each eRepair record read from the VPD
- *        and matches it against the attributes of the passed target.
- *        If a match is found, the corresponding eRepair record is copied into
- *        the respective failLane vectors to be returned to the caller.
- *
- * @param[in] i_tgtHandle   Reference to X-Bus or A-Bus or MCS target
- * @param[in] i_buf         This is the buffer that has the eRepair records
- *                          read from the VPD
- * @param[in] i_bufSz       This is the size of passed buffer in terms of bytes
- * @param[o]  o_txFailLanes Reference to a vector that will hold eRepair fail
- *                          lane numbers of the Tx sub-interface.
- * @param[o]  o_rxFailLanes Reference to a vector that will hold eRepair fail
- *                          lane numbers of the Rx sub-interface.
- *
- * @return ReturnCode
- */
-fapi::ReturnCode determineRepairLanes(const fapi::Target   &i_tgtHandle,
-                                      uint8_t              *i_buf,
-                                      uint32_t             i_bufSz,
-                                      std::vector<uint8_t> &o_txFailLanes,
-                                      std::vector<uint8_t> &o_rxFailLanes);
-
-
-/**
- * @brief Function to check if the system has Custom DIMM type (CDIMM).
- *        Attribute ATTR_EFF_CUSTOM_DIMM is read to determine the type.
- * @param[in] i_tgtHandle   Reference to X-Bus or A-Bus or MCS target
- * @param[o]  o_customDimm  Return value - ENUM_ATTR_EFF_CUSTOM_DIMM_NO
- *                                      or ENUM_ATTR_EFF_CUSTOM_DIMM_YES
- * @return ReturnCode
- */
-fapi::ReturnCode getDimmType(const fapi::Target &i_tgtHandle,
-                             uint8_t &o_customDimm);
-
-/******************************************************************************
- * Accessor HWP
- *****************************************************************************/
-
-fapi::ReturnCode erepairGetFailedLanesHwp(const fapi::Target  &i_tgtHandle,
-                                          erepairVpdType       i_vpdType,
-                                          std::vector<uint8_t> &o_txFailLanes,
-                                          std::vector<uint8_t> &o_rxFailLanes)
-{
-    fapi::ReturnCode l_rc;
-    fapi::Target     l_processorTgt;
-    fapi::TargetType l_tgtType = fapi::TARGET_TYPE_NONE;
-    std::vector<fapi::Target> l_mcsChiplets;
-
-    FAPI_INF(">> erepairGetFailedLanesHwp: i_tgtHandle: %s",
-             i_tgtHandle.toEcmdString());
-
-    do
-    {
-        o_txFailLanes.clear();
-        o_rxFailLanes.clear();
-
-        // Determine the type of target
-        l_tgtType = i_tgtHandle.getType();
-
-        // Verify if the correct target type is passed
-        if((l_tgtType != fapi::TARGET_TYPE_MCS_CHIPLET)    &&
-           (l_tgtType != fapi::TARGET_TYPE_MEMBUF_CHIP)    &&
-           (l_tgtType != fapi::TARGET_TYPE_XBUS_ENDPOINT)  &&
-           (l_tgtType != fapi::TARGET_TYPE_ABUS_ENDPOINT))
-        {
-            FAPI_ERR("erepairGetFailedLanesHwp: Invalid Target type %d",
-                    l_tgtType);
-            FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_INVALID_TARGET_TYPE);
-            break;
-        }
-
-        // Retrieve the Field eRepair lane numbers from the VPD
-        l_rc = retrieveRepairData(i_tgtHandle,
-                                  i_vpdType,
-                                  o_txFailLanes,
-                                  o_rxFailLanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("Error (0x%x) during retrieval of Field records",
-                    static_cast<uint32_t>(l_rc));
-            break;
-        }
-    }while(0);
-
-    return l_rc;
-}
-
-fapi::ReturnCode retrieveRepairData(const fapi::Target   &i_tgtHandle,
-                                    erepairVpdType       i_vpdType,
-                                    std::vector<uint8_t> &o_txFailLanes,
-                                    std::vector<uint8_t> &o_rxFailLanes)
-{
-    fapi::ReturnCode l_rc;
-    uint8_t          *l_retBuf = NULL;
-    uint32_t         l_bufSize = 0;
-    fapi::Target     l_procTarget;
-    uint8_t          l_customDimm;
-
-    FAPI_DBG(">> retrieveRepairData");
-
-    do
-    {
-        if(i_tgtHandle.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)
-        {
-            fapi::MBvpdRecord l_vpdRecord = fapi::MBVPD_RECORD_VEIR;
-
-            if(i_vpdType == EREPAIR_VPD_MNFG)
-            {
-                l_vpdRecord = fapi::MBVPD_RECORD_MER0;
-            }
-
-            // Determine the size of the eRepair data in the VPD
-            l_rc = fapiGetMBvpdField(l_vpdRecord,
-                                     fapi::MBVPD_KEYWORD_PDI,
-                                     i_tgtHandle,
-                                     NULL,
-                                     l_bufSize);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) during VPD size read",
-                        static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            // Check whether we have Memory on a CDIMM
-            l_rc = getDimmType(i_tgtHandle, l_customDimm);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) during DIMM type check",
-                        static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            if(l_customDimm == fapi::ENUM_ATTR_SPD_CUSTOM_YES)
-            {
-                if((l_bufSize == 0) ||
-                   ((i_vpdType == EREPAIR_VPD_FIELD) &&
-                    (l_bufSize > EREPAIR_MEM_FIELD_VPD_SIZE_PER_CENTAUR)) ||
-                   ((i_vpdType == EREPAIR_VPD_MNFG) &&
-                    (l_bufSize > EREPAIR_MEM_MNFG_VPD_SIZE_PER_CENTAUR)))
-                {
-                    FAPI_SET_HWP_ERROR(l_rc,
-                                       RC_ACCESSOR_HWP_INVALID_MEM_VPD_SIZE);
-                    break;
-                }
-            }
-            else if(l_bufSize == 0)
-            {
-                // TODO RTC: 119531. Add upper bound checking for l_bufSize
-                // This size check will depend on whether the Lane eRepair data
-                // is stored on the Planar VPD or on the Riser card VPD.
-                FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_INVALID_MEM_VPD_SIZE);
-                break;
-            }
-
-            // Allocate memory for buffer
-            l_retBuf = new uint8_t[l_bufSize];
-            if(l_retBuf == NULL)
-            {
-                FAPI_ERR("Failed to allocate memory size of %d", l_bufSize);
-                FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_MEMORY_ALLOC_FAIL);
-                break;
-            }
-
-            // Retrieve the Field eRepair data from the PNOR
-            l_rc = fapiGetMBvpdField(l_vpdRecord,
-                                     fapi::MBVPD_KEYWORD_PDI,
-                                     i_tgtHandle,
-                                     l_retBuf,
-                                     l_bufSize);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) during VPD read",
-                        static_cast<uint32_t> (l_rc));
-                break;
-            }
-        }
-        else
-        {
-            // Determine the Processor target
-            l_rc = fapiGetParentChip(i_tgtHandle, l_procTarget);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetParentChip",
-                        static_cast<uint32_t>(l_rc));
-                break;
-            }
-
-            fapi::MvpdRecord l_vpdRecord = fapi::MVPD_RECORD_VWML;
-
-            if(i_vpdType == EREPAIR_VPD_MNFG)
-            {
-                l_vpdRecord = fapi::MVPD_RECORD_MER0;
-            }
-
-            // Determine the size of the eRepair data in the VPD
-            l_rc = fapiGetMvpdField(l_vpdRecord,
-                                    fapi::MVPD_KEYWORD_PDI,
-                                    l_procTarget,
-                                    NULL,
-                                    l_bufSize);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) during VPD size read",
-                        static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            if((l_bufSize == 0) ||
-               ((i_vpdType == EREPAIR_VPD_FIELD) &&
-                (l_bufSize > EREPAIR_P8_MODULE_VPD_FIELD_SIZE)) ||
-               ((i_vpdType == EREPAIR_VPD_MNFG) &&
-                (l_bufSize > EREPAIR_P8_MODULE_VPD_MNFG_SIZE)))
-            {
-                FAPI_SET_HWP_ERROR(l_rc,
-                                   RC_ACCESSOR_HWP_INVALID_FABRIC_VPD_SIZE);
-                break;
-            }
-
-            // Allocate memory for buffer
-            l_retBuf = new uint8_t[l_bufSize];
-            if(l_retBuf == NULL)
-            {
-                FAPI_ERR("Failed to allocate memory size of %d", l_bufSize);
-                FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_MEMORY_ALLOC_FAIL);
-                break;
-            }
-
-            // Retrieve the Field eRepair data from the PNOR
-            l_rc = fapiGetMvpdField(l_vpdRecord,
-                                    fapi::MVPD_KEYWORD_PDI,
-                                    l_procTarget,
-                                    l_retBuf,
-                                    l_bufSize);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) during VPD read",
-                        static_cast<uint32_t> (l_rc));
-                break;
-            }
-        }
-
-        // Parse the buffer to determine eRepair lanes and copy the
-        // fail lane numbers to the return vector
-        l_rc = determineRepairLanes(i_tgtHandle,
-                                    l_retBuf,
-                                    l_bufSize,
-                                    o_txFailLanes,
-                                    o_rxFailLanes);
-        if(l_rc)
-        {
-            FAPI_ERR("determineRepairLanes failed");
-            break;
-        }
-    }while(0);
-
-    // Delete the buffer which has Field eRepair data
-    delete[] l_retBuf;
-
-    FAPI_DBG("<< retrieveRepairData");
-
-    return (l_rc);
-}
-
-fapi::ReturnCode determineRepairLanes(const fapi::Target   &i_tgtHandle,
-                                      uint8_t              *i_buf,
-                                      uint32_t             i_bufSz,
-                                      std::vector<uint8_t> &o_txFailLanes,
-                                      std::vector<uint8_t> &o_rxFailLanes)
-{
-    uint32_t         l_numRepairs         = 0;
-    uint8_t          *l_vpdPtr            = NULL;
-    eRepairHeader    *l_vpdHeadPtr        = NULL;
-    uint32_t         l_loop               = 0;
-    uint32_t         l_bytesParsed        = 0;
-    const uint32_t   l_memRepairDataSz    = sizeof(eRepairMemBus);
-    const uint32_t   l_fabricRepairDataSz = sizeof(eRepairPowerBus);
-    fapi::TargetType l_tgtType            = fapi::TARGET_TYPE_NONE;
-    fapi::Target     l_mcsTarget;
-    fapi::Target     l_tgtHandle;
-    fapi::ReturnCode l_rc;
-    uint8_t          l_customDimm;
-    fapi::ATTR_CHIP_UNIT_POS_Type l_busNum;
-
-    FAPI_DBG(">> determineRepairLanes");
-
-    do
-    {
-        l_tgtType = i_tgtHandle.getType();
-
-        // Get the parent chip target
-        fapi::Target l_chipTarget = i_tgtHandle;
-        if((l_tgtType == fapi::TARGET_TYPE_XBUS_ENDPOINT) ||
-           (l_tgtType == fapi::TARGET_TYPE_ABUS_ENDPOINT) ||
-           (l_tgtType == fapi::TARGET_TYPE_MCS_CHIPLET))
-        {
-            l_rc = fapiGetParentChip(i_tgtHandle, l_chipTarget);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetParentChip",
-                         static_cast<uint32_t>(l_rc));
-                break;
-            }
-        }
-
-        // Get the chip position
-        uint32_t l_chipPosition;
-        l_rc = FAPI_ATTR_GET(ATTR_POS, &l_chipTarget, l_chipPosition);
-        if(l_rc)
-        {
-            FAPI_ERR("Error (0x%x), from FAPI_ATTR_GET",
-                    static_cast<uint32_t>(l_rc));
-            break;
-        }
-
-        // Read the header and count information
-        l_vpdPtr = i_buf; // point to the start of header data
-        l_vpdHeadPtr = reinterpret_cast<eRepairHeader *> (l_vpdPtr);
-
-        l_numRepairs = l_vpdHeadPtr->numRecords;
-
-        l_bytesParsed = sizeof(eRepairHeader); // we've read the header data
-        l_vpdPtr += sizeof(eRepairHeader); // point to the start of repair data
-
-        // Parse for Power bus data
-        if((l_tgtType == fapi::TARGET_TYPE_XBUS_ENDPOINT) ||
-           (l_tgtType == fapi::TARGET_TYPE_ABUS_ENDPOINT))
-        {
-            eRepairPowerBus *l_fabricBus;
-
-            // Read Power bus eRepair data and get the failed lane numbers
-            for(l_loop = 0;
-                l_loop < l_numRepairs;
-                l_loop++, (l_vpdPtr += l_fabricRepairDataSz))
-            {
-                // Make sure we are not parsing more data than the passed size
-                l_bytesParsed += l_fabricRepairDataSz;
-                if(l_bytesParsed > i_bufSz)
-                {
-                    break;
-                }
-
-                l_fabricBus = reinterpret_cast<eRepairPowerBus *>(l_vpdPtr);
-
-#ifndef _BIG_ENDIAN
-                // We are on a Little Endian system.
-                // Need to swap the nibbles of the structure - eRepairPowerBus
-
-                uint8_t l_temp = l_vpdPtr[2];
-                l_fabricBus->type = (l_temp >> 4);
-                l_fabricBus->interface = (l_temp & 0x0F);
-#endif
-
-                // We do not need the check of processor ID because
-                // a MVPD read is specific to a Processor
-
-                // Check if we have the matching the Fabric Bus types
-                if((l_tgtType == fapi::TARGET_TYPE_ABUS_ENDPOINT) &&
-                   (l_fabricBus->type != PROCESSOR_EDI))
-                {
-                    continue;
-                }
-
-                if((l_tgtType == fapi::TARGET_TYPE_XBUS_ENDPOINT) &&
-                   (l_fabricBus->type != PROCESSOR_EI4))
-                {
-                    continue;
-                }
-
-                // Check if we have the matching fabric bus interface
-                l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,&i_tgtHandle,l_busNum);
-                if(l_rc)
-                {
-                    FAPI_ERR("Error (0x%x), from FAPI_ATTR_GET",
-                            static_cast<uint32_t>(l_rc));
-                    break;
-                }
-
-                if(l_fabricBus->device.fabricBus != l_busNum)
-                {
-                    continue;
-                }
-
-                // Check if we have valid fail lane numbers
-                if(l_fabricBus->failBit == INVALID_FAIL_LANE_NUMBER)
-                {
-                    continue;
-                }
-
-                // Copy the fail lane numbers in the vectors
-                if(l_fabricBus->interface == PBUS_DRIVER)
-                {
-                    o_txFailLanes.push_back(l_fabricBus->failBit);
-                }
-                else if(l_fabricBus->interface == PBUS_RECEIVER)
-                {
-                    o_rxFailLanes.push_back(l_fabricBus->failBit);
-                }
-            } // end of for loop
-        } // end of if(l_tgtType is XBus or ABus)
-        else if((l_tgtType == fapi::TARGET_TYPE_MCS_CHIPLET) ||
-                (l_tgtType == fapi::TARGET_TYPE_MEMBUF_CHIP))
-        {
-            // Parse for Memory bus data
-            eRepairMemBus *l_memBus;
-            l_tgtHandle = i_tgtHandle;
-
-            if(l_tgtType == fapi::TARGET_TYPE_MEMBUF_CHIP)
-            {
-                l_rc = fapiGetOtherSideOfMemChannel(
-                                                i_tgtHandle,
-                                                l_mcsTarget,
-                                                fapi::TARGET_STATE_FUNCTIONAL);
-                if(l_rc)
-                {
-                    FAPI_ERR("determineRepairLanes: Unable to get the connected"
-                             " MCS target");
-                    break;
-                }
-                l_tgtHandle = l_mcsTarget;
-
-                // Check whether we have Memory on a CDIMM
-                l_rc = getDimmType(i_tgtHandle, l_customDimm);
-
-                if(l_rc)
-                {
-                    FAPI_ERR("Error (0x%x) during DIMM type check",
-                            static_cast<uint32_t> (l_rc));
-                    break;
-                }
-            }
-
-            // Read Power bus eRepair data and get the failed lane numbers
-            for(l_loop = 0;
-                l_loop < l_numRepairs;
-                l_loop++, (l_vpdPtr += l_memRepairDataSz))
-            {
-                // Make sure we are not parsing more data than the passed size
-                l_bytesParsed += l_memRepairDataSz;
-                if(l_bytesParsed > i_bufSz)
-                {
-                    break;
-                }
-
-                l_memBus = reinterpret_cast<eRepairMemBus *>(l_vpdPtr);
-
-#ifndef _BIG_ENDIAN
-                // We are on a Little Endian system.
-                // Need to swap the nibbles of the structure - eRepairMemBus
-
-                uint8_t l_temp = l_vpdPtr[2];
-                l_memBus->type = (l_temp >> 4);
-                l_memBus->interface = (l_temp & 0x0F);
-#endif
-
-                // Check if we have the correct Centaur ID
-                // NOTE: We do not prefer to make the check of Centaur ID if the
-                // system is known to have CDIMMs. This check is applicable
-                // only for systems with ISDIMM because in the ISDIMM systems
-                // the Lane eRepair data for multiple Centaurs is maintained in
-                // a common VPD.
-                if((l_tgtType == fapi::TARGET_TYPE_MEMBUF_CHIP)     &&
-                   (l_customDimm != fapi::ENUM_ATTR_SPD_CUSTOM_YES) &&
-                   (l_chipPosition != l_memBus->device.proc_centaur_id))
-                {
-                    continue;
-                }
-
-                // Check if we have the matching the Memory Bus types
-                if(l_memBus->type != MEMORY_EDI)
-                {
-                    continue;
-                }
-
-                // Check if we have the matching memory bus interface
-                l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,&l_tgtHandle,l_busNum);
-                if(l_rc)
-                {
-                    FAPI_ERR("Error (0x%x), from ATTR_CHIP_UNIT_POS",
-                            static_cast<uint32_t>(l_rc));
-                    break;
-                }
-
-                if(l_memBus->device.memChannel != l_busNum)
-                {
-                    continue;
-                }
-
-                // Check if we have valid fail lane numbers
-                if(l_memBus->failBit == INVALID_FAIL_LANE_NUMBER)
-                {
-                    continue;
-                }
-
-                // Copy the fail lane numbers in the vectors
-                if(l_tgtType == fapi::TARGET_TYPE_MCS_CHIPLET)
-                {
-                   if(l_memBus->interface == DMI_MCS_DRIVE)
-                   {
-                       o_txFailLanes.push_back(l_memBus->failBit);
-                   }
-                   else if(l_memBus->interface == DMI_MCS_RECEIVE)
-                   {
-                       o_rxFailLanes.push_back(l_memBus->failBit);
-                   }
-                }
-                else if(l_tgtType == fapi::TARGET_TYPE_MEMBUF_CHIP)
-                {
-                   if(l_memBus->interface == DMI_MEMBUF_DRIVE)
-                   {
-                       o_txFailLanes.push_back(l_memBus->failBit);
-                   }
-                   else if(l_memBus->interface == DMI_MEMBUF_RECEIVE)
-                   {
-                       o_rxFailLanes.push_back(l_memBus->failBit);
-                   }
-                }
-            } // end of for loop
-        } // end of if(l_tgtType is MCS)
-
-    }while(0);
-
-    FAPI_INF("<< No.of Fail Lanes: tx: %zd, rx: %zd",
-              o_txFailLanes.size(), o_rxFailLanes.size());
-
-    return(l_rc);
-}
-
-fapi::ReturnCode getDimmType(const fapi::Target &i_tgtHandle,
-                             uint8_t &o_customDimm)
-{
-    fapi::ReturnCode          l_rc;
-    std::vector<fapi::Target> l_mbaChiplets;
-    fapi::Target              l_mbaTarget;
-
-    do
-    {
-        o_customDimm = fapi::ENUM_ATTR_SPD_CUSTOM_NO;
-
-        // Get the connected MBA chiplet and determine whether we have CDIMM
-        l_rc = fapiGetChildChiplets(i_tgtHandle,
-                                    fapi::TARGET_TYPE_MBA_CHIPLET,
-                                    l_mbaChiplets,
-                                    fapi::TARGET_STATE_FUNCTIONAL);
-
-        if(l_rc || (0 == l_mbaChiplets.size()))
-        {
-            FAPI_ERR("Error (0x%x) during get child MBA targets",
-                    static_cast<uint32_t> (l_rc));
-            break;
-        }
-
-        l_mbaTarget = l_mbaChiplets[0];
-        std::vector<fapi::Target> l_target_dimm_array;
-
-        l_rc =  fapiGetAssociatedDimms(l_mbaTarget, l_target_dimm_array);
-
-        if(l_rc)
-        {
-            FAPI_ERR("Error (0x%x), from fapiGetAssociatedDimms",
-                    static_cast<uint32_t>(l_rc));
-            break;
-        }
-
-        if(0 != l_target_dimm_array.size())
-        {
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM,
-                    &l_target_dimm_array[0],
-                    o_customDimm);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x), from FAPI_ATTR_GET",
-                        static_cast<uint32_t>(l_rc));
-                break;
-            }
-        }
-        else
-        {
-            o_customDimm = fapi::ENUM_ATTR_SPD_CUSTOM_NO;
-        }
-    }while(0);
-
-    return l_rc;
-}
-
-}// endof extern "C"
diff --git a/src/usr/hwpf/hwp/bus_training/erepairSetFailedLanesHwp.C b/src/usr/hwpf/hwp/bus_training/erepairSetFailedLanesHwp.C
deleted file mode 100755
index ad5af4beb..000000000
--- a/src/usr/hwpf/hwp/bus_training/erepairSetFailedLanesHwp.C
+++ /dev/null
@@ -1,942 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/erepairSetFailedLanesHwp.C $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: erepairSetFailedLanesHwp.C,v 1.5 2015/02/23 16:46:15 bilicon Exp $
-/**
- *  @file erepairSetFailedLanesHwp.C
- *
- *  @brief FW Team HWP that accesses the fail lanes of Fabric and Memory buses.
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          bilicon     13-JAN-2013 Created.
- */
-
-#include <erepairSetFailedLanesHwp.H>
-
-using namespace EREPAIR;
-using namespace fapi;
-
-extern "C"
-{
-
-/******************************************************************************
- * Forward Declarations
- *****************************************************************************/
-
-/**
- * @brief Function called by the FW Team HWP that writes the data to Field VPD.
- *        This function calls fapiSetMvpdField to write the VPD.
- *
- * @param[in] i_tgtHandle   Reference to X-Bus or A-Bus or MCS target
- * @param[in] i_vpdType     Specifies which VPD (MNFG or Field) to access.
- * @param[in] i_txFailLanes Reference to a vector that has eRepair fail
- *                          lane numbers of the Tx sub-interface.
- * @param[in] i_rxFailLanes Reference to a vector that has eRepair fail
- *                          lane numbers of the Rx sub-interface.
- *
- * @return ReturnCode
- */
-ReturnCode writeRepairDataToVPD(const Target               &i_tgtHandle,
-                                erepairVpdType             i_vpdType,
-                                const std::vector<uint8_t> &i_txFailLanes,
-                                const std::vector<uint8_t> &i_rxFailLanes);
-
-/**
- * @brief Function called by the FW Team HWP that updates the passed buffer
- *        with the eRepair faillane numbers.
- *
- * @param[in] i_tgtHandle   Reference to X-Bus or A-Bus or MCS target
- * @param[in] i_txFailLanes Reference to a vector that has the Tx side faillane
- *                          numbers that need to be updated to the o_buf buffer
- * @param[in] i_rxFailLanes Reference to a vector that has the Rx side faillane
- *                          numbers that need to be updated to the o_buf buffer
- * @param[in] i_bufSz       This is the size of passed buffer in terms of bytes
- * @param[o]  o_buf         This is the buffer that has the eRepair records
- *                          that needs to be written to the VPD
- *
- * @return ReturnCode
- */
-ReturnCode writeRepairLanesToBuf(const Target               &i_tgtHandle,
-                                 const std::vector<uint8_t> &i_txFailLanes,
-                                 const std::vector<uint8_t> &i_rxFailLanes,
-                                 const uint32_t             i_bufSz,
-                                 uint8_t                    *o_buf);
-
-/**
- * @brief Function called by the FW Team HWP that updates the passed buffer
- *        with the eRepair faillane numbers of a specified interface.
- *
- * @param[in] i_tgtHandle   Reference to X-Bus or A-Bus or MCS target
- * @param[in] i_interface   This indicates the sub-interface type the passed
- *                          faillane vector represents
- * @param[in] i_bufSz       This is the size of passed buffer in terms of bytes
- * @param[in] i_failLanes   Reference to a vector that has the faillane numbers
- *                          that need to be updated to the o_buf buffer
- * @param[o]  o_buf         This is the buffer that has the eRepair records
- *                          that needs to be written to the VPD
- *
- * @return ReturnCode
- */
-ReturnCode updateRepairLanesToBuf(const Target               &i_tgtHandle,
-                                  const interfaceType        i_interface,
-                                  const uint32_t             i_bufSz,
-                                  const std::vector<uint8_t> &i_failLanes,
-                                  uint8_t                    *o_buf);
-
-/******************************************************************************
- * Accessor HWP
- *****************************************************************************/
-
-ReturnCode erepairSetFailedLanesHwp(const Target               &i_tgtHandle,
-                                    erepairVpdType             i_vpdType,
-                                    const std::vector<uint8_t> &i_txFailLanes,
-                                    const std::vector<uint8_t> &i_rxFailLanes)
-{
-    ReturnCode l_rc;
-    Target     l_mcsTgt;
-    TargetType l_tgtType = TARGET_TYPE_NONE;
-
-    FAPI_INF(">> erepairSetFailedLanesHwp: i_tgtHandle: %s",
-             i_tgtHandle.toEcmdString());
-
-    do
-    {
-        if((i_txFailLanes.size() == 0) && (i_rxFailLanes.size() == 0))
-        {
-            FAPI_INF("erepairSetFailedLanesHwp: No fail lanes were provided");
-            break;
-        }
-
-        // Determine the type of target
-        l_tgtType = i_tgtHandle.getType();
-
-        // Verify if the correct target type is passed
-        if((l_tgtType != TARGET_TYPE_MCS_CHIPLET)    &&
-           (l_tgtType != TARGET_TYPE_MEMBUF_CHIP)    &&
-           (l_tgtType != TARGET_TYPE_XBUS_ENDPOINT)  &&
-           (l_tgtType != TARGET_TYPE_ABUS_ENDPOINT))
-        {
-            FAPI_ERR("erepairSetFailedLanesHwp: Invalid Target type %d",
-                     l_tgtType);
-            FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_INVALID_TARGET_TYPE);
-            break;
-        }
-
-        l_rc = writeRepairDataToVPD(i_tgtHandle,
-                                    i_vpdType,
-                                    i_txFailLanes,
-                                    i_rxFailLanes);
-
-        if(l_rc)
-        {
-            FAPI_ERR("Error (0x%x) during write of Field records",
-                     static_cast<uint32_t>(l_rc));
-            break;
-        }
-    }while(0);
-
-    return l_rc;
-}
-
-
-ReturnCode writeRepairDataToVPD(const Target               &i_tgtHandle,
-                                erepairVpdType             i_vpdType,
-                                const std::vector<uint8_t> &i_txFailLanes,
-                                const std::vector<uint8_t> &i_rxFailLanes)
-{
-    ReturnCode l_rc;
-    uint8_t    *l_retBuf = NULL;
-    uint32_t   l_bufSize = 0;
-    Target     l_procTarget;
-    uint8_t    l_customDimm;
-    std::vector<fapi::Target> l_mbaChiplets;
-    fapi::Target              l_mbaTarget;
-
-    FAPI_DBG(">> writeRepairDataToVPD");
-
-    do
-    {
-        if(i_tgtHandle.getType() == TARGET_TYPE_MEMBUF_CHIP)
-        {
-            fapi::MBvpdRecord l_vpdRecord = MBVPD_RECORD_VEIR;
-
-            if(i_vpdType == EREPAIR_VPD_MNFG)
-            {
-                l_vpdRecord = MBVPD_RECORD_MER0;
-            }
-
-            /*** Read the data from the FRU VPD ***/
-
-            // Determine the size of the eRepair data in the Centaur VPD
-            l_rc = fapiGetMBvpdField(l_vpdRecord,
-                                     MBVPD_KEYWORD_PDI,
-                                     i_tgtHandle,
-                                     NULL,
-                                     l_bufSize);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetMBvpdField",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            // Get the connected MBA chiplet and determine whether we have CDIMM
-            l_rc = fapiGetChildChiplets(i_tgtHandle,
-                                        fapi::TARGET_TYPE_MBA_CHIPLET,
-                                        l_mbaChiplets,
-                                        fapi::TARGET_STATE_FUNCTIONAL);
-
-            if(l_rc || (0 == l_mbaChiplets.size()))
-            {
-                FAPI_ERR("Error (0x%x) during get child MBA targets",
-                         static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            l_mbaTarget = l_mbaChiplets[0];
-            std::vector<fapi::Target> l_target_dimm_array;
-
-            l_rc =  fapiGetAssociatedDimms(l_mbaTarget, l_target_dimm_array);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x), from fapiGetAssociatedDimms",
-                          static_cast<uint32_t>(l_rc));
-                break;
-            }
-
-            if(0 != l_target_dimm_array.size())
-            {
-                l_rc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM,
-                                     &l_target_dimm_array[0],
-                                     l_customDimm);
-                if(l_rc)
-                {
-                    FAPI_ERR("Error (0x%x), from FAPI_ATTR_GET",
-                             static_cast<uint32_t>(l_rc));
-                    break;
-                }
-            }
-            else
-            {
-                l_customDimm = fapi::ENUM_ATTR_SPD_CUSTOM_NO;
-            }
-
-            if(l_customDimm == fapi::ENUM_ATTR_SPD_CUSTOM_YES)
-            {
-                if((l_bufSize == 0) ||
-                       ((i_vpdType == EREPAIR_VPD_FIELD) &&
-                        (l_bufSize > EREPAIR_MEM_FIELD_VPD_SIZE_PER_CENTAUR)) ||
-                       ((i_vpdType == EREPAIR_VPD_MNFG) &&
-                        (l_bufSize > EREPAIR_MEM_MNFG_VPD_SIZE_PER_CENTAUR)))
-                {
-                    FAPI_SET_HWP_ERROR(l_rc,
-                                       RC_ACCESSOR_HWP_INVALID_MEM_VPD_SIZE);
-                    break;
-                }
-            }
-            else if(l_bufSize == 0)
-            {
-                // TODO RTC: 119531. Add upper bound checking for l_bufSize
-                // This size check will depend on whether the Lane eRepair data
-                // is stored on the Planar VPD or on the Riser card VPD.
-                FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_INVALID_MEM_VPD_SIZE);
-                break;
-            }
-
-            // Allocate memory for buffer
-            l_retBuf = new uint8_t[l_bufSize];
-            if(l_retBuf == NULL)
-            {
-                FAPI_ERR("Failed to allocate memory size of %d", l_bufSize);
-                FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_MEMORY_ALLOC_FAIL);
-                break;
-            }
-
-            // Retrieve the Field eRepair data from the Centaur FRU VPD
-            l_rc = fapiGetMBvpdField(l_vpdRecord,
-                                     MBVPD_KEYWORD_PDI,
-                                     i_tgtHandle,
-                                     l_retBuf,
-                                     l_bufSize);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetMBvpdField",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            /*** Update the new eRepair data to the buffer ***/
-            l_rc = writeRepairLanesToBuf(i_tgtHandle,
-                                         i_txFailLanes,
-                                         i_rxFailLanes,
-                                         l_bufSize,
-                                         l_retBuf);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from writeRepairLanesToBuf",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            /*** Write the updated eRepair buffer back to Centaur FRU VPD ***/
-            l_rc = fapiSetMBvpdField(l_vpdRecord,
-                                     MBVPD_KEYWORD_PDI,
-                                     i_tgtHandle,
-                                     l_retBuf,
-                                     l_bufSize);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiSetMBvpdField",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-        } // end of(targetType == MEMBUF)
-        else
-        {
-            // Determine the Processor target
-            l_rc = fapiGetParentChip(i_tgtHandle, l_procTarget);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetParentChip",
-                        static_cast<uint32_t>(l_rc));
-                break;
-            }
-
-            fapi::MvpdRecord l_vpdRecord = MVPD_RECORD_VWML;
-
-            if(i_vpdType == EREPAIR_VPD_MNFG)
-            {
-                l_vpdRecord = MVPD_RECORD_MER0;
-            }
-
-            /*** Read the data from the Module VPD ***/
-
-            // Determine the size of the eRepair data in the VPD
-            l_rc = fapiGetMvpdField(l_vpdRecord,
-                                    MVPD_KEYWORD_PDI,
-                                    l_procTarget,
-                                    NULL,
-                                    l_bufSize);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetMvpdField",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            if((l_bufSize == 0) ||
-               ((i_vpdType == EREPAIR_VPD_FIELD) &&
-                (l_bufSize > EREPAIR_P8_MODULE_VPD_FIELD_SIZE)) ||
-               ((i_vpdType == EREPAIR_VPD_MNFG) &&
-                (l_bufSize > EREPAIR_P8_MODULE_VPD_MNFG_SIZE)))
-            {
-                FAPI_SET_HWP_ERROR(l_rc,
-                                   RC_ACCESSOR_HWP_INVALID_FABRIC_VPD_SIZE);
-                break;
-            }
-
-            // Allocate memory for buffer
-            l_retBuf = new uint8_t[l_bufSize];
-            if(l_retBuf == NULL)
-            {
-                FAPI_ERR("Failed to allocate memory size of %d", l_bufSize);
-                FAPI_SET_HWP_ERROR(l_rc, RC_ACCESSOR_HWP_MEMORY_ALLOC_FAIL);
-                break;
-            }
-
-            // Retrieve the Field eRepair data from the MVPD
-            l_rc = fapiGetMvpdField(l_vpdRecord,
-                                    MVPD_KEYWORD_PDI,
-                                    l_procTarget,
-                                    l_retBuf,
-                                    l_bufSize);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetMvpdField",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            /*** Update the new eRepair data to the buffer ***/
-            l_rc = writeRepairLanesToBuf(i_tgtHandle,
-                                         i_txFailLanes,
-                                         i_rxFailLanes,
-                                         l_bufSize,
-                                         l_retBuf);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from writeRepairLanesToBuf",
-                          static_cast<uint32_t> (l_rc));
-                break;
-            }
-
-            /*** Write the updated eRepair buffer back to MVPD ***/
-            l_rc = fapiSetMvpdField(l_vpdRecord,
-                                    MVPD_KEYWORD_PDI,
-                                    l_procTarget,
-                                    l_retBuf,
-                                    l_bufSize);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiSetMvpdField",
-                        static_cast<uint32_t> (l_rc));
-                break;
-            }
-        }
-    }while(0);
-
-    // Delete the buffer which has Field eRepair data
-    delete[] l_retBuf;
-
-    return (l_rc);
-}
-
-ReturnCode writeRepairLanesToBuf(const Target               &i_tgtHandle,
-                                 const std::vector<uint8_t> &i_txFailLanes,
-                                 const std::vector<uint8_t> &i_rxFailLanes,
-                                 const uint32_t             i_bufSz,
-                                 uint8_t                    *o_buf)
-{
-    ReturnCode l_rc;
-
-    FAPI_DBG(">> writeRepairLanesToBuf");
-
-    do
-    {
-        if(i_txFailLanes.size())
-        {
-            /*** Lets update the tx side fail lane vector to the VPD ***/
-            l_rc = updateRepairLanesToBuf(i_tgtHandle,
-                                          DRIVE,
-                                          i_bufSz,
-                                          i_txFailLanes,
-                                          o_buf);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x), from updateRepairLanesToBuf(DRIVE)",
-                          static_cast<uint32_t>(l_rc));
-                break;
-            }
-        }
-
-        if(i_rxFailLanes.size())
-        {
-            /*** Lets update the rx side fail lane vector to the VPD ***/
-            l_rc = updateRepairLanesToBuf(i_tgtHandle,
-                                          RECEIVE,
-                                          i_bufSz,
-                                          i_rxFailLanes,
-                                          o_buf);
-
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x), from updateRepairLanesToBuf(RECEIVE)",
-                          static_cast<uint32_t>(l_rc));
-                break;
-            }
-        }
-    }while(0);
-
-    return (l_rc);
-}
-
-ReturnCode updateRepairLanesToBuf(const Target               &i_tgtHandle,
-                                  const interfaceType        i_interface,
-                                  const uint32_t             i_bufSz,
-                                  const std::vector<uint8_t> &i_failLanes,
-                                  uint8_t                    *o_buf)
-{
-    ReturnCode       l_rc;
-    uint32_t         l_numRepairs           = 0;
-    uint32_t         l_newNumRepairs        = 0;
-    uint32_t         l_repairCnt            = 0;
-    uint32_t         l_bytesParsed          = 0;
-    uint8_t          l_repairLane           = 0;
-    uint32_t         l_repairDataSz         = 0;
-    uint8_t          *l_vpdPtr              = NULL;
-    uint8_t          *l_vpdDataPtr          = NULL;
-    uint8_t          *l_vpdWritePtr         = NULL;
-    eRepairHeader    *l_vpdHeadPtr          = NULL;
-    eRepairPowerBus  *l_overWritePtr        = NULL;
-    bool             l_overWrite            = false;
-    TargetType       l_tgtType              = TARGET_TYPE_NONE;
-    Target           l_mcsTarget;
-    Target           l_tgtHandle;
-    std::vector<uint8_t>::const_iterator l_it;
-    ATTR_CHIP_UNIT_POS_Type l_busNum;
-
-    FAPI_DBG(">> updateRepairLanesToBuf, interface: %s",
-              i_interface == DRIVE ? "Drive" : "Recevie");
-
-    do
-    {
-        l_repairDataSz = sizeof(eRepairPowerBus); // Size of memory Bus and
-                                                  // fabric Bus eRepair data
-                                                  // is same.
-        // Read the header and count information
-        l_vpdPtr = o_buf; // point to the start of header data
-        l_vpdHeadPtr = reinterpret_cast<eRepairHeader *> (l_vpdPtr);
-
-        l_numRepairs = l_newNumRepairs = l_vpdHeadPtr->numRecords;
-
-        // We've read the header data, increment bytes parsed
-        l_bytesParsed = sizeof(eRepairHeader);
-
-        // Get a pointer to the start of repair data
-        l_vpdPtr += sizeof(eRepairHeader);
-
-        l_tgtType = i_tgtHandle.getType();
-
-        l_tgtHandle = i_tgtHandle;
-        if(l_tgtType == TARGET_TYPE_MEMBUF_CHIP)
-        {
-            l_rc = fapiGetOtherSideOfMemChannel(i_tgtHandle,
-                                                l_mcsTarget,
-                                                TARGET_STATE_FUNCTIONAL);
-
-            if(l_rc)
-            {
-                FAPI_ERR("updateRepairLanesToBuf: unable to get the connected"
-                         " MCS target");
-                break;
-            }
-
-            l_tgtHandle = l_mcsTarget;
-        }
-
-        // Get the bus number
-        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_tgtHandle, l_busNum);
-        if(l_rc)
-        {
-            FAPI_ERR("Error (0x%x), from FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS)",
-                     static_cast<uint32_t>(l_rc));
-            break;
-        }
-
-        // Get the chip target
-        Target l_chipTarget = i_tgtHandle;
-        if((l_tgtType == TARGET_TYPE_XBUS_ENDPOINT) ||
-           (l_tgtType == TARGET_TYPE_ABUS_ENDPOINT) ||
-           (l_tgtType == TARGET_TYPE_MCS_CHIPLET))
-        {
-            l_rc = fapiGetParentChip(i_tgtHandle, l_chipTarget);
-            if(l_rc)
-            {
-                FAPI_ERR("Error (0x%x) from fapiGetParentChip",
-                        static_cast<uint32_t>(l_rc));
-                break;
-            }
-        }
-
-        // Get the chip number
-        uint32_t l_chipPosition;
-        l_rc = FAPI_ATTR_GET(ATTR_POS, &l_chipTarget, l_chipPosition);
-        if(l_rc)
-        {
-            FAPI_ERR("Error (0x%x), from FAPI_ATTR_GET(ATTR_POS)",
-                     static_cast<uint32_t>(l_rc));
-            break;
-        }
-
-        // This is needed because we can only store and compare a uint8_t
-        // value. For our purpose the value in l_chipPosition (Proc Position and
-        // Centaur Position) will always be within the range of uint8_t
-        uint8_t l_chipNum = l_chipPosition;
-
-        /*** Lets update the fail lane vector to the Buffer ***/
-
-        // Create a structure of eRepair data that we will be matching
-        // in the buffer.
-        struct erepairDataMatch
-        {
-            interfaceType   intType;
-            TargetType      tgtType;
-            union repairData
-            {
-                eRepairPowerBus fabBus;
-                eRepairMemBus   memBus;
-            }bus;
-        };
-
-        // Create an array of the above match structure to have all the
-        // combinations of Fabric and Memory repair data
-        erepairDataMatch l_repairMatch[8] =
-        {
-            { // index 0
-                DRIVE,
-                TARGET_TYPE_XBUS_ENDPOINT,
-                { // repairData
-                    { // fabBus
-                        { // device
-                            l_chipNum,// processor_id
-                            l_busNum, // fabricBus
-                        },
-                        PROCESSOR_EI4, // type
-                        PBUS_DRIVER,   // interface
-                    },
-                },
-            },
-            { // index 1
-                DRIVE,
-                TARGET_TYPE_ABUS_ENDPOINT,
-                { // repairData
-                    { // fabBus
-                        { // device
-                            l_chipNum,// processor_id
-                            l_busNum, // fabricBus
-                        },
-                        PROCESSOR_EDI, // type
-                        PBUS_DRIVER,   // interface
-                    },
-                },
-            },
-            { // index 2
-                RECEIVE,
-                TARGET_TYPE_XBUS_ENDPOINT,
-                { // repairData
-                    { // fabBus
-                        { // device
-                            l_chipNum,// processor_id
-                            l_busNum, // fabricBus
-                        },
-                        PROCESSOR_EI4, // type
-                        PBUS_RECEIVER, // interface
-                    },
-                },
-            },
-            { // index 3
-                RECEIVE,
-                TARGET_TYPE_ABUS_ENDPOINT,
-                { // repairData
-                    { // fabBus
-                        { // device
-                            l_chipNum,// processor_id
-                            l_busNum, // fabricBus
-                        },
-                        PROCESSOR_EDI, // type
-                        PBUS_RECEIVER, // interface
-                    },
-                },
-            },
-            { // index 4
-                DRIVE,
-                TARGET_TYPE_MCS_CHIPLET,
-                { // repairData
-                    { // fabBus
-                        { // device
-                            l_chipNum,// proc_centaur_id
-                            l_busNum, // memChannel
-                        },
-                        MEMORY_EDI,   // type
-                        DMI_MCS_DRIVE,// interface
-                    },
-                },
-            },
-            { // index 5
-                DRIVE,
-                TARGET_TYPE_MEMBUF_CHIP,
-                { // repairData
-                    { // memBus
-                        { // device
-                            l_chipNum,// proc_centaur_id
-                            l_busNum, // memChannel
-                        },
-                        MEMORY_EDI,      // type
-                        DMI_MEMBUF_DRIVE,// interface
-                    },
-                },
-            },
-            { // index 6
-                RECEIVE,
-                TARGET_TYPE_MCS_CHIPLET,
-                { // repairData
-                    { // memBus
-                        { // device
-                            l_chipNum,// proc_centaur_id
-                            l_busNum, // memChannel
-                        },
-                        MEMORY_EDI,      // type
-                        DMI_MCS_RECEIVE, // interface
-                    },
-                },
-            },
-            { // index 7
-                RECEIVE,
-                TARGET_TYPE_MEMBUF_CHIP,
-                { // repairData
-                    { // memBus
-                        { // device
-                            l_chipNum,// proc_centaur_id
-                            l_busNum, // memChannel
-                        },
-                        MEMORY_EDI,         // type
-                        DMI_MEMBUF_RECEIVE, // interface
-                    },
-                },
-            }
-        };
-
-        l_vpdDataPtr  = l_vpdPtr;
-        l_repairCnt   = 0;
-
-        // Pick each faillane for copying into buffer
-        for(l_it  = i_failLanes.begin();
-            l_it != i_failLanes.end();
-            l_it++, (l_vpdDataPtr += l_repairDataSz))
-        {
-            l_repairLane  = *l_it;
-            l_overWrite   = false;
-            l_vpdWritePtr = NULL;
-
-            // Parse the VPD for fabric and memory eRepair records
-            for(;
-                (l_repairCnt < l_numRepairs) && (l_bytesParsed <= i_bufSz);
-                l_repairCnt++, (l_vpdDataPtr += l_repairDataSz))
-            {
-                l_overWritePtr =
-                            reinterpret_cast<eRepairPowerBus *> (l_vpdDataPtr);
-
-                // Lets find the matching fabric
-                for(uint8_t l_loop = 0; l_loop < 8; l_loop++)
-                {
-                    if((l_tgtType == TARGET_TYPE_XBUS_ENDPOINT) ||
-                       (l_tgtType == TARGET_TYPE_ABUS_ENDPOINT))
-                    {
-                        if((i_interface == l_repairMatch[l_loop].intType)    &&
-                           (l_tgtType   == l_repairMatch[l_loop].tgtType)    &&
-                           ((l_overWritePtr->device).processor_id ==
-                        l_repairMatch[l_loop].bus.fabBus.device.processor_id)&&
-                           (l_overWritePtr->type ==
-                                l_repairMatch[l_loop].bus.fabBus.type)       &&
-                           (l_overWritePtr->interface ==
-                                l_repairMatch[l_loop].bus.fabBus.interface)  &&
-                           (l_overWritePtr->device.fabricBus ==
-                            l_repairMatch[l_loop].bus.fabBus.device.fabricBus))
-                        {
-                            // update the failBit number
-                            l_overWritePtr->failBit = l_repairLane;
-
-                            // Increment the count of parsed bytes
-                            l_bytesParsed += l_repairDataSz;
-
-                            l_repairCnt++;
-                            l_overWrite = true;
-
-                            break;
-                        }
-                    }
-                    else if((l_tgtType == TARGET_TYPE_MCS_CHIPLET) ||
-                            (l_tgtType == TARGET_TYPE_MEMBUF_CHIP) )
-                    {
-                        if((i_interface == l_repairMatch[l_loop].intType)    &&
-                           (l_tgtType   == l_repairMatch[l_loop].tgtType)    &&
-                           ((l_overWritePtr->device).processor_id ==
-                     l_repairMatch[l_loop].bus.memBus.device.proc_centaur_id)&&
-                           (l_overWritePtr->type ==
-                                l_repairMatch[l_loop].bus.memBus.type)       &&
-                           (l_overWritePtr->interface ==
-                                l_repairMatch[l_loop].bus.memBus.interface)  &&
-                           (l_overWritePtr->device.fabricBus ==
-                            l_repairMatch[l_loop].bus.memBus.device.memChannel))
-                        {
-                            // update the failBit number
-                            l_overWritePtr->failBit = l_repairLane;
-
-                            // Increment the count of parsed bytes
-                            l_bytesParsed += l_repairDataSz;
-
-                            l_repairCnt++;
-                            l_overWrite = true;
-
-                            break;
-                        }
-                    }
-
-                    // Check if we have a eRepair record that is invalidated
-                    // If yes, save the pointer so that we can overwrite it
-                    // if no matching record is found
-                    if(l_overWritePtr->failBit == INVALID_FAIL_LANE_NUMBER)
-                    {
-                        l_vpdWritePtr = l_vpdDataPtr;
-                    }
-                } // end of for(l_loop < 8)
-
-                if(l_overWrite == true)
-                {
-                    // Go for the next repairLane
-                    break;
-                }
-            } // end of for(vpd Parsing)
-
-            // Check if we have parsed more bytes than the passed size
-            if((l_vpdWritePtr == NULL)       &&
-               (l_bytesParsed > i_bufSz)     &&
-               (l_repairCnt < l_numRepairs))
-            {
-                if((l_tgtType == TARGET_TYPE_XBUS_ENDPOINT) ||
-                   (l_tgtType == TARGET_TYPE_ABUS_ENDPOINT))
-                {
-                    FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_MVPD_FULL);
-                }
-                else if((l_tgtType == TARGET_TYPE_MCS_CHIPLET) ||
-                        (l_tgtType == TARGET_TYPE_MEMBUF_CHIP) )
-                {
-                    FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_MBVPD_FULL);
-                }
-                break;
-            }
-
-            // Add at the end
-            if(l_overWrite == false)
-            {
-                if(l_vpdWritePtr == NULL)
-                {
-                    // We are writing at the end
-                    l_vpdWritePtr = l_vpdDataPtr;
-                }
-
-                if((l_tgtType == TARGET_TYPE_XBUS_ENDPOINT) ||
-                   (l_tgtType == TARGET_TYPE_ABUS_ENDPOINT))
-                {
-                    // Make sure we are not writing more records than the size
-                    // allocated in the VPD
-                    if(l_bytesParsed == i_bufSz)
-                    {
-                        FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_MVPD_FULL);
-                        break;
-                    }
-
-                    eRepairPowerBus *l_fabricBus =
-                             reinterpret_cast<eRepairPowerBus *>(l_vpdWritePtr);
-
-                    l_fabricBus->device.processor_id = l_chipNum;
-                    l_fabricBus->device.fabricBus    = l_busNum;
-                    l_fabricBus->failBit             = l_repairLane;
-
-                    if(i_interface == DRIVE)
-                    {
-                        l_fabricBus->interface = PBUS_DRIVER;
-                    }
-                    else if(i_interface == RECEIVE)
-                    {
-                        l_fabricBus->interface = PBUS_RECEIVER;
-                    }
-
-                    if(l_tgtType == TARGET_TYPE_XBUS_ENDPOINT)
-                    {
-                        l_fabricBus->type = PROCESSOR_EI4;
-                    }
-                    else if(l_tgtType == TARGET_TYPE_ABUS_ENDPOINT)
-                    {
-                        l_fabricBus->type = PROCESSOR_EDI;
-                    }
-
-                    l_newNumRepairs++;
-
-                    // Increment the count of parsed bytes
-                    l_bytesParsed += l_repairDataSz;
-#ifndef _BIG_ENDIAN
-                    // We are on a Little Endian system.
-                    // Need to swap the nibbles of structure - eRepairPowerBus
-
-                    l_vpdWritePtr[2] = ((l_vpdWritePtr[2] >> 4) |
-                                       (l_vpdWritePtr[2] << 4));
-#endif
-                }
-                else if((l_tgtType == TARGET_TYPE_MCS_CHIPLET) ||
-                        (l_tgtType == TARGET_TYPE_MEMBUF_CHIP) )
-                {
-                    // Make sure we are not writing more records than the size
-                    // allocated in the VPD
-                    if(l_bytesParsed == i_bufSz)
-                    {
-                        FAPI_SET_HWP_ERROR(l_rc, RC_EREPAIR_MBVPD_FULL);
-                        break;
-                    }
-
-                    eRepairMemBus *l_memBus =
-                               reinterpret_cast<eRepairMemBus *>(l_vpdWritePtr);
-
-                    l_memBus->device.proc_centaur_id = l_chipNum;
-                    l_memBus->device.memChannel      = l_busNum;
-                    l_memBus->type                   = MEMORY_EDI;
-                    l_memBus->failBit                = l_repairLane;
-
-                    if(i_interface == DRIVE)
-                    {
-                        if(l_tgtType == TARGET_TYPE_MCS_CHIPLET)
-                        {
-                            l_memBus->interface = DMI_MCS_DRIVE;
-                        }
-                        else if(l_tgtType == TARGET_TYPE_MEMBUF_CHIP)
-                        {
-                            l_memBus->interface = DMI_MEMBUF_DRIVE;
-                        }
-                    }
-                    else if(i_interface == RECEIVE)
-                    {
-                        if(l_tgtType == TARGET_TYPE_MCS_CHIPLET)
-                        {
-                            l_memBus->interface = DMI_MCS_RECEIVE;
-                        }
-                        else if(l_tgtType == TARGET_TYPE_MEMBUF_CHIP)
-                        {
-                            l_memBus->interface = DMI_MEMBUF_RECEIVE;
-                        }
-                    }
-
-                    l_newNumRepairs++;
-
-                    // Increment the count of parsed bytes
-                    l_bytesParsed += l_repairDataSz;
-#ifndef _BIG_ENDIAN
-                    // We are on a Little Endian system.
-                    // Need to swap the nibbles of structure - eRepairMemBus
-
-                    l_vpdWritePtr[2] = ((l_vpdWritePtr[2] >> 4) |
-                                       (l_vpdWritePtr[2] << 4));
-#endif
-                }
-            } // end of if(l_overWrite == false)
-        } // end of for(failLanes)
-
-        // Update the eRepair count
-        l_vpdHeadPtr->numRecords = l_newNumRepairs;
-
-    }while(0);
-
-    return(l_rc);
-}
-
-}// endof extern "C"
diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
deleted file mode 100644
index a990c0c09..000000000
--- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
+++ /dev/null
@@ -1,280 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs.C $                   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: gcr_funcs.C,v 1.12 2014/03/10 16:29:43 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : gcr_funcs.C
-// *! TITLE                : 
-// *! DESCRIPTION          : 
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkeykv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY: 
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |varkeykv|01/19/12| Initial check in to solve hostboot linker 
-//------------------------------------------------------------------------------
-#include <gcr_funcs.H>
-
-using namespace fapi;
-ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address, ecmdDataBufferBase &databuf_16bit)
-{
-	ReturnCode rc;
-	uint32_t rc_ecmd=0;
-	ecmdDataBufferBase set_bits(16), clear_bits(16);
-	rc_ecmd|=set_bits.flushTo0();
-	rc_ecmd|=clear_bits.flushTo1();
-   
-	if(rc_ecmd)
-	{
-      FAPI_ERR("Unexpected error in buffer manipulation\n");
-      rc.setEcmdError(rc_ecmd);
-	}
-	else
-	{
-		rc=doGCRop(chip_target, interface, gcr_op_read, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit);
-        if(!rc.ok())
-        {
-          FAPI_ERR("Unexpected error while performing GCR OP \n");
-        }
-	}
-
-	return  rc;
-}
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM WRITE  - main api for write - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, int skipCheck,int bypass_rmw)
-{
-	ReturnCode rc;
-	uint32_t rc_ecmd=0;
-	ecmdDataBufferBase databuf_16bit(16);
-	rc_ecmd|=databuf_16bit.flushTo0();
-        skipCheck=1; // This is redundant -- forcing to 1 
-	if(rc_ecmd)
-	{
-      FAPI_ERR("Unexpected error in buffer manipulation\n");
-      rc.setEcmdError(rc_ecmd);
-	}
-	else
-	{
-		rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck,bypass_rmw);
-        if(!rc.ok())
-        {
-          FAPI_ERR("Unexpected error while performing GCR OP \n");
-        }
-	}
-	return rc;
-}
-
-// UPPER LAYER FUNCTIONS
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// generate the 64 bit scom address for the GCR
-//------------------------------------------------------------------------------------------------------------------------------------
-uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) 
-{
-	uint32_t rc_ecmd=0;
-	ecmdDataBufferBase reg_scom_address(64), temp(64);
-	temp.flushTo0();
-	temp.setDoubleWord(0,gcr_data);
-
-	// 64 bit address
-	rc_ecmd|= reg_scom_address.setWord(0,temp.getWord(0));
-	rc_ecmd |= reg_scom_address.setWord(1,gcr_addr);
-	rc_ecmd |= reg_scom_address.setBit(0);
-
-	if(rc_ecmd)
-	{
-		FAPI_ERR("io_run_training: Unexpected failure in scom_address_64bit helper func");
-	}
-	return(reg_scom_address.getDoubleWord(0));
-}
-
-
-// use GCR_read and GCR_write for reg access - not this function!!!!
-/*************************************************************************************************************************/
-/* gcr2 is pgp mailbox format                                                                                            */
-/* gcr2        0         0         64      # total length                                                                */
-/* gcr2        wr        0         1       # gcr register read/write bit (read=1, write=0, opposite of gcr0)             */
-/* gcr2        reg_addr  12        9       # gcr ring (register) address (ext_addr)                                      */
-/* gcr2        rxtx      21        1       # =1 for a tx group                                                           */
-/* gcr2        group     22        5       # does NOT include tx/rx as leading bit                                       */
-/* gcr2        lane      27        5       # lane address                                                                */
-/* gcr2        data      48        16      # data                                                                        */
-/* gcr2        readvalid 39        1       # read data valid bit                                                         */
-/*************************************************************************************************************************/
-
-ReturnCode  doGCRop(const Target& chip_target, 
-					io_interface_t interface, 
-					gcr_op read_or_write, 
-					GCR_sub_registers target_io_reg, 
-					uint32_t group_address,  
-					uint32_t lane_address,  
-					ecmdDataBufferBase set_bits,  
-					ecmdDataBufferBase clear_bits, 
-					ecmdDataBufferBase &databuf_16bit, 
-					int skipCheck,
-					int bypass_rmw) 
-{
-    ReturnCode rc;
-    uint32_t rc_ecmd=0;
-    uint64_t  scom_address64=0;
-    ecmdDataBufferBase getscom_data64(64), putscom_data64(64), local_data16(16);
-
-	do
-	{
-		rc_ecmd |=getscom_data64.flushTo0();
-		rc_ecmd |=putscom_data64.flushTo0();
-		rc_ecmd |=local_data16.flushTo0();
-    
-		// Generate the  gcr2_register_data  putscom data
-		/* gcr2        reg_addr  12        9       # gcr ring (register) address (ext_addr)                                      */
-		// align the extended address to bit (12:20)
-		rc_ecmd |= getscom_data64.insert( GCR_sub_reg_ext_addr[target_io_reg], 12, 9, 23 );
-		FAPI_DBG("Register Extended address = %x\n",GCR_sub_reg_ext_addr[target_io_reg]);
-  
-		const char *temp;
-		temp=GCR_sub_reg_names[target_io_reg];
-		if(temp[0] == 'T' )
-		{
-			// This is a TX register/field need to set the TX bit
-			rc_ecmd |= getscom_data64.setBit( 21 ); // does not include leading TX bit now since we are using only RX
-		}
-		/* gcr2        group     22        5       # does NOT include tx/rx as leading bit                                       */
-		// align the group address to bit (22:26)
-		rc_ecmd |= getscom_data64.insert( group_address, 22, 5, 27); // does not include leading TX bit now since we are using only RX
-    
-		/* gcr2        lane      27        5       # lane address                                                                */
-		// align the lane address to bit (27:31)
-		rc_ecmd |=  getscom_data64.insert( lane_address, 27, 5, 27 );
-		if(rc_ecmd)
-		{
-			FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
-			rc.setEcmdError(rc_ecmd);
-			break;
-		}
-
-        FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]);
-        scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0));
-        if(!bypass_rmw)
-		{
-           rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );
-        }
-        else
-		{
-			getscom_data64.flushTo0();
-        }
-
-        if(!rc.ok())
-        {
-            FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n");
-		    FAPI_ERR( "IO GCR FUNCS \tRead GCR %s, @ = %llX, Data = %08X%08X  Failed  group_address=%d\n",
-            GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1),group_address);
-			break;
-        }
-		FAPI_DBG( "\tRead GCR2 %s:  GETSCOM 0x%llX %08X%08X \n",
-        GCR_sub_reg_names[target_io_reg], scom_address64, getscom_data64.getWord(0), getscom_data64.getWord(1) );
-		rc_ecmd|=getscom_data64.extract( local_data16,   48, 16 ); // return data on read ops -- for 54/52 onwards
-          
-		if(rc_ecmd)
-		{
-			FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
-			rc.setEcmdError(rc_ecmd);
-			break;
-		}
-		// register write operation
-		if (read_or_write == gcr_op_read) 
-		{
-			databuf_16bit = local_data16;
-			break;
-		}
-		// write operation
-		putscom_data64 = getscom_data64;
-            
-		// clear the desired bits first
-		databuf_16bit = databuf_16bit & clear_bits;
-                
-		// now set desired bits
-		databuf_16bit = databuf_16bit | set_bits;
-              
-		// data is now 64 bits and only last 16 bits are used  48:63 = 16bits  # data  
-		rc_ecmd|=putscom_data64.insert( databuf_16bit, 48, 16); //-- for model 54/52 onwards
-           
-		if(rc_ecmd)
-		{
-			FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred");
-			rc.setEcmdError(rc_ecmd);
-			break;
-		}
-		FAPI_DBG( "\tWrite GCR2 %s: PUTSCOM 0x%llX  0x%08X%08X",
-		GCR_sub_reg_names[target_io_reg], scom_address64, putscom_data64.getWord(0), putscom_data64.getWord(1) );
-		rc = fapiPutScom( chip_target, scom_address64, putscom_data64);
-		if(!rc.ok())
-		{
-			FAPI_ERR("IO gcr_funcs: PUTSCOM error occurred\n");
-			break;
-		}
-		// check the write
-		if(!skipCheck)
-		{
-			rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );
-		}
-		if(!rc.ok())
-		{
-			FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n");
-			break;
-		}
-		rc_ecmd=local_data16.insert(getscom_data64,0,16,48);  //-- for 54/52 onwards
-		if(rc_ecmd)
-		{
-			FAPI_ERR("IO gcr_funcs: DataBuffer operation error occurred\n");
-			rc.setEcmdError(rc_ecmd);
-			break;
-		}
-		if ( !skipCheck )
-		{ 
-			//add skipCheck for tx_err_inj since self resetting -- djd 2/11/11
-			if ( local_data16 != databuf_16bit )
-			{
-				FAPI_ERR( "\t %s VALIDATE write failed: read=0x%04X  write=%04X\n",
-				GCR_sub_reg_names[target_io_reg], local_data16.getHalfWord(0), databuf_16bit.getHalfWord(0) );
-				ecmdDataBufferBase &READ_BUF=local_data16;
-				ecmdDataBufferBase &WRITE_BUF=databuf_16bit;
-				FAPI_SET_HWP_ERROR(rc, IO_GCR_WRITE_MISMATCH_RC);
-			}
-		}
-                           
-	}while(0); 
-    return(rc);
-}
-
diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
deleted file mode 100644
index bf792defc..000000000
--- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
+++ /dev/null
@@ -1,151 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/gcr_funcs.H $                   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: gcr_funcs.H,v 1.22 2014/03/07 13:13:29 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : gcr_funcs.H
-// *! TITLE                : 
-// *! DESCRIPTION          : 
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkeykv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY: 
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |jaswamin|09/13/11|
-//   2.0   |varkeykv|01/12/12| Post GFW review changes
-//------------------------------------------------------------------------------
-
-#ifndef GCR_FUNCS
-#define GCR_FUNCS
-
-/* Include some system headers */
-#include <list>
-#include <stdint.h>
-#include <fapi.H>
-using namespace fapi;
-
-#include "edi_regs.h"
-
-
-enum io_interface_t {     CP_PSI,
-           CP_FABRIC_X0,
-           CP_FABRIC_A0, 
-           CP_IOMC0_P0,  
-           CP_IOMC1_P0,  
-           S1_FABRIC_SX0,
-           S1_FABRIC_SA0,
-           CEN_DMI,
-           };
-
-// P8 chip interfaces
-const uint32_t NUM_INTERFACES=21;
-const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",
-                                            "CP_FABRIC_X0", 
-                                            "CP_FABRIC_A0",
-                                            "CP_IOMC0_P0",  
-                                            "CP_IOMC1_P0",  
-                                            "S1_FABRIC_SX0",
-                                            "S1_FABRIC_SA0", 
-                                            "CEN_DMI" };
-// EDI register addresses for CP
-const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,
-                                                  0x0401103F,
-                                                  0x08010c3f, 
-                                                  0x02011a3F, 
-                                                  0x02011e3F,
-                                                  0x03010c3f,
-                                                  0x08010c3f, 
-                                                  0x0201043F  };
-const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,
-                                                  0x04011020, 
-                                                  0x08010c20, 
-                                                  0x02011a20, 
-                                                  0x02011e20,
-                                                  0x03010c20,
-                                                  0x08010c20, 
-                                                  0x02010420  };
-
-
-// Register type
-typedef enum { tx_per_lane,  tx_per_group,  tx_per_pack, tx_per_bus,  rx_per_lane,  rx_per_group,  rx_per_pack, rx_per_bus, num_register_type } register_type;
-
-typedef enum { gcr_op_read,  gcr_op_write }  gcr_op;
-
-     const uint32_t num_rxlanes_per_group[NUM_INTERFACES] ={1,20,24,24,24,20,24,18 };
-const uint32_t num_txlanes_per_group[NUM_INTERFACES] ={1,20,24,17,17,20,24,24 };
-const uint32_t num_groups_per_bus[NUM_INTERFACES] = { 1,4,1,1,1,4,1,1};
-
-// Lane Bit Defintions
-// 0x00  (lane 0),   0x01  (lane 1) , etc
-const uint8_t SELECT_ALL_LANES=0x1F;          // The lane address is a 5 bit value  0b 11111  selects all lanes
-
-// Group Bit Definitions 0x00 group 0 ,  0x01 group1 , etc
-const uint8_t  RX_GROUP_BROADCAST =0x0F ;       // (Write Only) The group address is a 6 bit value to select all groups ,
-const uint8_t  TX_GROUP_BROADCAST =0x2F  ;      // (Write Only) The group address is a 6 bit value to select all groups ,
-
-// ROUTINES
-//------------------------------------------------------------------------------------------------------------------------------------
-// generate the 64 bit scom address for the GCR
-//------------------------------------------------------------------------------------------------------------------------------------
-uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// handle GCR operations - do not use directly!
-// use GCR_read and GCR_write for reg access - not this function!!!!
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,
-                   gcr_op read_or_write, GCR_sub_registers target_io_reg,
-                   uint32_t group_address,  uint32_t lane_address,
-                   ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits,
-                   ecmdDataBufferBase &databuf_16bit, int skipCheck=0,int bypass_rmw=0);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM READ  - main api for read - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,
-                     GCR_sub_registers target_io_reg, uint32_t group_address,
-                     uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM WRITE  - main api for write - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface,
-                      GCR_sub_registers target_io_reg, uint32_t group_address,
-                      uint32_t lane_address,  ecmdDataBufferBase set_bits,
-                      ecmdDataBufferBase clear_bits, int skipCheck=0,int bypass_rmw=0);
-
-
-
-
-#endif
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
deleted file mode 100644
index 785338b4b..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
+++ /dev/null
@@ -1,200 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_clear_firs.C $               */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_clear_firs.C,v 1.16 2014/03/20 16:15:49 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 2012, 2013
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_clear_firs.C
-// *! TITLE                : 
-// *! DESCRIPTION          : To clear summary fir registers
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com
-// *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.10  |mjjones |04/30/13|  Removed unused 'interface' variable
-//   1.9   |jaswmain|03/26/13|  Removed DOS line endings
-//   1.8   |jaswamin|03/25/13|  Removed 64 bit fir clearing function.
-//   1.7   |varkeykv|03/20/13|  Additional moved FIR functions from clear firs to training files
-//   1.6   |jaswamin|03/05/13|  Modifications as per review comments
-//   1.5   |jaswamin|02/20/13|  Changes as per review comment
-//   1.4   |varkeykv|02/18/13|  Missing function check in
-//   1.3   |jaswamin|02/14/13|  function for reading the fir scom register contents, enums and arrays for doing fir isolation
-//   1.2   |jaswamin|02/14/13|  Additions for reading the fir register.
-//   1.1   |jaswamin|01/30/13|  Initial check in .
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "io_clear_firs.H"
-//#include "gcr_funcs.H"
-//#include "ei4_regs.h"
-
-extern "C" {
-
-
-using namespace fapi;
-
-
-// for toggling the rx and tx fir reset.
-ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_interface,uint32_t i_group){
-    
-    ReturnCode rc;
-    uint32_t rc_ecmd=0;
-    uint16_t bits = 0;
-    ecmdDataBufferBase data_buffer;
- 
-    ecmdDataBufferBase set_bits(16);
-    ecmdDataBufferBase clear_bits(16);
-    
-    //set the rx_fir_reset bit
-    bits=rx_fir_reset;
-    rc_ecmd|=set_bits.insert(bits,0,16);
-    bits=rx_fir_reset_clear;
-    rc_ecmd|=clear_bits.insert(bits,0,16);
-    if(rc_ecmd)
-    {
-        rc.setEcmdError(rc_ecmd);
-        return(rc);
-    }
-    rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
-    //clear the rx_fir_reset bit
-    bits=0x0000;
-    rc_ecmd|=set_bits.insert(bits,0,16);
-    bits=rx_fir_reset_clear;
-    rc_ecmd|=clear_bits.insert(bits,0,16);
-    if(rc_ecmd)
-    {
-        rc.setEcmdError(rc_ecmd);
-        return(rc);
-    }
-    rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
-    //set the tx_fir_reset bit
-    bits=tx_fir_reset;
-    rc_ecmd|=set_bits.insert(bits,0,16);
-    bits=tx_fir_reset_clear;
-    rc_ecmd|=clear_bits.insert(bits,0,16);
-    if(rc_ecmd)
-    {
-        rc.setEcmdError(rc_ecmd);
-        return(rc);
-    }
-    rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
-    //clear the tx_fir_reset
-    bits=0x0000;
-    rc_ecmd|=set_bits.insert(bits,0,16);
-    bits=tx_fir_reset_clear;
-    rc_ecmd|=clear_bits.insert(bits,0,16);
-    if(rc_ecmd)
-    {
-        rc.setEcmdError(rc_ecmd);
-        return(rc);
-    }
-    rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
-    return(rc);
-
-    
-}
-
-
-ReturnCode read_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface,ecmdDataBufferBase &o_databuf_64bit){
-    
-    ReturnCode rc;
-    uint32_t rc_ecmd=0;
-    uint64_t scom_address64=0;
-    ecmdDataBufferBase temp(64);
-    rc_ecmd |=o_databuf_64bit.flushTo0();
-    
-    //get the 64 bit scom address.
-    temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]);
-    scom_address64=temp.getDoubleWord(0);
-    
-    //read the 64 bit fir register
-    rc=fapiGetScom(i_target,scom_address64,o_databuf_64bit);
-    
-    return(rc);
-}
-
-ReturnCode io_clear_firs(const fapi::Target &i_target){
-    
-    ReturnCode rc;
-    io_interface_t gcr_interface; // requires different base address for gcr scoms
-    uint32_t group=0;
-    uint32_t max_group=1;
-    const fapi::Target &ENDPOINT=i_target;

-    
-    //on dmi
-    if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
-          FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
-          gcr_interface=CP_IOMC0_P0;
-          group=3; // design requires us to swap
-          
-     }
-     else if((i_target.getType() ==  fapi::TARGET_TYPE_MEMBUF_CHIP)){
-            FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
-            gcr_interface=CEN_DMI;
-            group=0;
-           
-     }
-     else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){
-            FAPI_DBG("This is a X Bus invocation");
-            gcr_interface=CP_FABRIC_X0;
-            group=0;
-            max_group=4;
-     }
-     
-     else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
-            FAPI_DBG("This is an A Bus invocation");
-            gcr_interface=CP_FABRIC_A0;
-            group=0;
-     }
-     else{
-        FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances");
-        FAPI_SET_HWP_ERROR(rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC);
-        return(rc);
-     }
-     if(gcr_interface==CP_FABRIC_X0){
-        // For X bus we need to clear all clock group FIRs ourselves
-        for (uint32_t current_group = 0 ; current_group < max_group; current_group++){
-            rc=clear_fir_err_regs(i_target,gcr_interface,current_group);
-        }
-     }
-     else{
-            rc=clear_fir_err_regs(i_target,gcr_interface,group);
-     }
-    return(rc);
-}
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
deleted file mode 100644
index 1c8811e3e..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
+++ /dev/null
@@ -1,215 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_clear_firs.H $               */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_clear_firs.H,v 1.11 2014/07/22 12:35:23 jaswamin Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 2012, 2013
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_clear_firs.H
-// *! TITLE                : 
-// *! DESCRIPTION          : To clear summary fir registers
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com
-// *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.11  |jaswamin|07/22/14|  Fixed the address
-//   1.7   |jaswmain|03/26/13|  Removed DOS line endings
-//   1.6   |jaswamin|03/25/13|  Removed 64 bit fir clearing function.
-//   1.5   |varkeykv|03/20/13|  Additional moved FIR functions from clear firs to training files
-//   1.4   |jaswamin|02/20/13|  Changes as per review comment
-//   1.3   |varkeykv|02/18/13|  Added func decl for clear mask fir function
-//   1.2   |jaswamin|02/14/13|  function for reading the fir scom register contents,enums and arrays for doing fir isolation
-//   1.1   |jaswamin|01/30/13|  Initial check in .
-//------------------------------------------------------------------------------
-#ifndef IO_CLEAR_FIRS_H
-#define IO_CLEAR_FIRS_H
-
-#include <fapi.H>
-#include "gcr_funcs.H"
-
-using namespace fapi;
-
-/**
- * io_clear_firs HWP func pointer typedef
- *
- */
-typedef fapi::ReturnCode (*io_clear_firs_FP_t)(const fapi::Target &target);
-
-// P8 chip interfaces
-const uint32_t FIR_INTERFACES=8;
-const uint32_t FIR_ISOLATION_REGS=42;
-
-enum fir_io_interface_t {FIR_CP_FABRIC_X0,
-                FIR_CP_FABRIC_X1,
-                FIR_CP_FABRIC_X2,
-                FIR_CP_FABRIC_X3,
-                FIR_CP_FABRIC_A0,
-                FIR_CP_IOMC0_P0,  
-                FIR_CP_IOMC1_P0,  
-                FIR_CEN_DMI };
-           
-const char * const fir_interface_name[FIR_INTERFACES] = {"CP_FABRIC_X0",
-                                            "CP_FABRIC_X1",
-                                            "CP_FABRIC_X2",
-                                            "CP_FABRIC_X3",
-                                            "CP_FABRIC_A0",
-                                            "CP_IOMC0_P0",  
-                                            "CP_IOMC1_P0",  
-                                            "CEN_DMI" };
-                                            
-// FIR register addresses for interfaces
-const uint32_t fir_clear_reg_addr[FIR_INTERFACES] = {   0x04011001,
-                                                  0x04011401,
-                                                  0x04011c01,
-                                                  0x04011801,
-                                                  0x08010c01, 
-                                                  0x02011a01, 
-                                                  0x02011e01, 
-                                                  0x02010401  };
-                                                  
-const uint32_t fir_rw_reg_addr[FIR_INTERFACES]={0x04011000,
-                                                  0x04011400,
-                                                  0x04011c00,
-                                                  0x04011800,
-                                                  0x08010c00, 
-                                                  0x02011a00, 
-                                                  0x02011e00, 
-                                                  0x02010400  };
-                                                  
-const uint32_t fir_clear_mask_reg_addr[FIR_INTERFACES]={0x04011004,
-                                                  0x04011404,
-                                                  0x04011c04,
-                                                  0x04011804,
-                                                  0x08010c04, 
-                                                  0x02011a04, 
-                                                  0x02011e04, 
-                                                  0x02010404  };
-// This is for Centaur Reconfig loop IO_CLEANUP  procedure
-const uint32_t scom_mode_pb_reg_addr[FIR_INTERFACES] ={ 0x04011020,
-                                                       0x04011420,
-                                                       0x04011C20,
-                                                       0x04011820,
-                                                       0x08010C20,
-                                                       0x02011A20,
-                                                       0x02011E20,
-                                                       0x02010420};
-    
-    
-    
-                                                  
-
-enum fir_error_type{
-    RX_PARITY,
-    TX_PARITY,
-    GCR_HANG_ERROR,
-    BUS0_SPARE_DEPLOYED=9,
-    BUS0_MAX_SPARES_EXCEEDED=10,
-    BUS0_RECALIBRATION_ERROR=11,
-    BUS0_TOO_MANY_BUS_ERRORS=12,
-    BUS1_SPARE_DEPLOYED=17,
-    BUS1_MAX_SPARES_EXCEEDED=18,
-    BUS1_RECALIBRATION_ERROR=19,
-    BUS1_TOO_MANY_BUS_ERRORS=20,
-    BUS2_SPARE_DEPLOYED=25,
-    BUS2_MAX_SPARES_EXCEEDED=26,
-    BUS2_RECALIBRATION_ERROR=27,
-    BUS2_TOO_MANY_BUS_ERRORS=28,
-    BUS3_SPARE_DEPLOYED=33,
-    BUS3_MAX_SPARES_EXCEEDED=34,
-    BUS3_RECALIBRATION_ERROR=35,
-    BUS3_TOO_MANY_BUS_ERRORS=36,
-    BUS4_SPARE_DEPLOYED=41,
-    BUS4_MAX_SPARES_EXCEEDED=42,
-    BUS4_RECALIBRATION_ERROR=43,
-    BUS4_TOO_MANY_BUS_ERRORS=44,                                              
-};
-const char * const fir1_reg[16] = {"RX_PG_FIR_ERR_PG_REGS",
-                                            "RX_PG_FIR_ERR_GCR_BUFF",
-                                            "RESERVED_FIR",
-                                            "RX_PG_FIR_ERR_GCRS_LD_SM",
-                                            "RX_PG_FIR_ERR_GCRS_UNLD_SM",
-                                            "RX_PG_FIR_ERR_GLB_INIT_SND_MSG_SM",  
-                                            "RX_PG_FIR_ERR_MAIN_INIT_SM",  
-                                            "RX_PG_FIR_ERR_WTM_SM",
-                                            "RX_PG_FIR_ERR_WTR_SM",
-                                            "RX_PG_FIR_ERR_WTL_SM",
-                                            "RX_PG_FIR_ERR_RPR_SM",
-                                            "RX_PG_FIR_ERR_EYEOPT_SM",
-                                            "RX_PG_FIR_ERR_DSM_SM",
-                                            "RX_PG_FIR_ERR_RXDSM_SM",
-                                            "RX_PG_CHAN_FAIL_RSVD",
-                                            "RX_PL_FIR_ERR"};
-                                            
-
-const char * const fir2_reg[16] = {"RX_PG_FIR_ERR_DYN_RPR_SM",
-                                            "RX_PG_FIR_ERR_SLS_HNDSHK_SM",
-                                            "RX_PG_FIR_ERR_DYN_RPR_SND_MSG_SM",
-                                            "RX_PG_FIR_ERR_RECAL_SM",
-                                            "RX_PG_FIR_ERR_SLS_ENC_SND_MSG_SM",
-                                            "RX_PG_FIR_ERR_GLB_CAL_SND_MSG_SM",
-                                            "RX_PG_FIR_ERR_STAT_RPR_SND_MSG_SM",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR",
-                                            "RESERVED_FIR"};
-
-extern "C"
-{
-
-/**
- * io_clear_firs HWP 
- *
- * target is any IO target P8 MCS,XBUS,Abus or centaur
- * 
- * 
- *
- * 
- */
-
-fapi::ReturnCode io_clear_firs(const fapi::Target &target);
-
-fapi::ReturnCode clear_fir_err_regs(const Target &target,io_interface_t chip_interface,uint32_t group);
-
-fapi::ReturnCode read_fir_reg(const Target &target,fir_io_interface_t chip_interface,ecmdDataBufferBase &databuf_64bit);
-
-
-
-
-    
-} // extern "C"
-#endif // CLEAR_IO_FIRS_H_
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.C b/src/usr/hwpf/hwp/bus_training/io_dccal.C
deleted file mode 100644
index 217774888..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_dccal.C
+++ /dev/null
@@ -1,961 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_dccal.C $                    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_dccal.C,v 1.40 2015/05/14 21:03:34 jmcgill Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_dccal.C
-// *! TITLE                : 
-// *! DESCRIPTION          : Impedance & offset calibration
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com      
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.31  |jaswamin|02/17/14| Fixed the order of scoms for the pll workaround
-//   1.22  |jaswamin|09/19/13| Removed unused variables 
-//   1.19  |thomsen |04/12/12| Added delay after starting zcal and offset cancellation to work around a GCR parity error bug (HW242564)
-//   1.18  |jaswamin|01/26/12| Commented out offset cal for X and A bus
-//   1.0   |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK
-//   1.1   |varkeykv |17/11/11|Code cleanup . Fixed header files. Changed fAPI API
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "proc_a_x_pci_dmi_pll_utils.H"
-#include "io_dccal.H"
-#include "gcr_funcs.H"
-#include <p8_scom_addresses.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-extern "C" {
-
-
-using namespace fapi;
-
-int binStrToInt(char *str,uint32_t length) {
-  int i = 0;
-  for ( uint32_t j = 0; j <length; j++ ) {
-    char c = str[j];
-    if ( c == '0' ) {
-      i = (i << 1);
-    } else {
-      i = (i << 1) | 0x1;
-    }
-  }
-  return i;
-}
-
-uint32_t  BinaryRound(uint32_t val, uint32_t numTruncBits, uint32_t center) {
-  // Round val by removing numTruncBits
-  // If the truncated fraction is exactly 0.5, round
-  // toward center
-  uint32_t newVal = 0x0;
-
-  uint32_t mask = 0x0;
-  for (uint32_t i = 0; i < numTruncBits; i++) {
-    mask = (mask << 1) + 0x1;
-  }
-
-  uint32_t half = 0x1 << (numTruncBits-1);
-
-  if ( (val & mask) > half  ) {
-    newVal = (val >> numTruncBits) + 1; // round up
-  } else if ( (val & mask) < half  ) {
-    newVal = (val >> numTruncBits); // round down
-  } else {
-    // On the boundary!  Round towards the nominal value
-    if ( val < (center << numTruncBits) ) {
-      newVal = (val >> numTruncBits) + 1; // round up
-    } else {
-      newVal = (val >> numTruncBits); // round down
-    }
-  }
-
-  return newVal;
-}
-
-// Offset cal doesnt do anything in VBU/sim ...
-ReturnCode run_offset_cal(const Target &target,io_interface_t master_interface,uint32_t master_group){
-// Assuming I will receive a target and slave_target from the Invoker. 
-    ReturnCode rc;
-    uint32_t rc_ecmd=0;
-    uint16_t bits = 0;
-    ecmdDataBufferBase data_buffer;
-	ecmdDataBufferBase rx_wt_timeout_sel_buf(16),rx_pdwn_lite_value_buf(16),rx_eo_latch_offset_done_buf(16),rx_wt_cu_pll_pgooddly_buf(16),rx_wt_cu_pll_pgooddly_buf_copy(16);
-    ecmdDataBufferBase set_bits(16);
-    ecmdDataBufferBase clear_bits(16);
-       const fapi::Target &TARGET=target;
-    //char printStr[200];
-    FAPI_DBG("In the Dccal procedure");
-    uint8_t ddlevel;
-    
-     rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_MCD_HANG_RECOVERY_BUG, &target,ddlevel);
-     if(rc)
-     {
-      FAPI_ERR("IO_DCCAL :Error Reading DDLEVEL using MCD_HANG_RECOVERY attribute");
-      return rc;
-     }
-     
-     
-     
-     FAPI_DBG("DDLevel FLAG is read as %d",ddlevel);
-     
-    io_interface_t chip_interface=master_interface;//first we run on master chip
-    uint32_t group=master_group;
-    const Target *target_ptr=&target; // Assuming I am allowed to do this . 
-		rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer);
-		if (rc) 
-		{
-			// have to add support for field parsing
-			FAPI_ERR("IO_DCCAL : GCR_read error for rx_training_status_pg");
-			return rc;
-		}
-        FAPI_DBG("IO_DCCAL : Starting Offset Calibration on interface %d group %d",chip_interface,group);
-        // read and save rx_pdwn_lite_disable
-        //int read_bit=rx_pdwn_lite_disable;
-        rc= GCR_read(*target_ptr,master_interface,rx_mode_pg ,group,0,rx_pdwn_lite_value_buf);if (rc) {return(rc);}
-        //int rx_pdwn_lite_value=rx_wt_timeout_sel_buf.getHalfWord(0) & read_bit;
-        	if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : GCR_read error for rx_mode_pg");
-			return rc;
-		}
-        // read and save rx_wt_timeout_sel
-        //read_bit=rx_wt_timeout_sel_tap7; //find the 3 bit value of the field. need it to be all 1's to do an &
-	// -- REVIEW , think this read is safe 
-        rc= GCR_read(*target_ptr,master_interface,rx_timeout_sel_pg ,group,0,rx_wt_timeout_sel_buf);
-			if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : GCR_read error for rx_timeout_sel_pg");
-			return rc;
-		}
-	
-        //int rx_wt_timeout_value=rx_wt_timeout_sel_buf.getHalfWord(0) & read_bit;
-        
-		//read and save rx_wt_cu_pll_pgooddly
-		//read_bit=rx_wt_cu_pll_pgooddly_disable; // selects 111 for the 3 bit field.need it to be all 1's to do an &
-		rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf);
-				if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : GCR_read error for rx_wiretest_pll_cntl_pgrx_wiretest_pll_cntl_pg");
-			return rc;
-		}
-
-
-		//int rx_wt_cu_pll_pgooddly_value=rx_wt_cu_pll_pgooddly_buf.getHalfWord(0) & read_bit;
-		
-		//read and save rx_wt_cu_pll_reset
-		//read_bit=rx_wt_cu_pll_reset;
-		//int rx_wt_cu_pll_reset_value=rx_wt_cu_pll_pgooddly_buf.getHalfWord(0) & read_bit;
-		
-		//read and save rx_wt_cu_pll_pgood
-		//read_bit=rx_wt_cu_pll_pgood;
-		//int rx_wt_cu_pll_pgood_value=rx_wt_cu_pll_pgooddly_buf.getHalfWord(0) & read_bit;
-		
-        // set power down lite disable, rx_pdwn_lite_disable
-        bits=rx_pdwn_lite_disable;
-		//bits=1;
-		rc_ecmd|=set_bits.insert(rx_pdwn_lite_value_buf,0,16);
-		//rc_ecmd|=set_bits.insert(bits,0,16);
-        //rc_ecmd|=set_bits.insert(bits,2,1);
-		//rc_ecmd|=set_bits.setOr(bits,0,16);
-		rc_ecmd|=set_bits.setBit(2);
-        bits=rx_pdwn_lite_disable_clear;
-        //rc_ecmd|=clear_bits.insert(bits,0,16);
-		rc_ecmd|=clear_bits.flushTo0();
-        if(rc_ecmd)
-        {
-	  FAPI_ERR("IO_DCCAL : error power down lite disable");
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,rx_mode_pg,group,0,set_bits ,clear_bits);
-	  if (rc)
-	  {
-		  FAPI_ERR("IO_DCCAL : GCR_write error for rx_mode_pg");
-		  return rc;
-	  }
-		//write rx_wt_cu_pll_pgooddly to  '111'
-		rc_ecmd|=set_bits.insert(rx_wt_cu_pll_pgooddly_buf,0,16);
-		rc_ecmd|=set_bits.setBit(2);
-		rc_ecmd|=set_bits.setBit(3);
-		rc_ecmd|=set_bits.setBit(4);
-		bits=rx_wt_cu_pll_pgooddly_clear;
-		rc_ecmd|=clear_bits.flushTo0();
-		if(rc_ecmd)
-		{
-			rc.setEcmdError(rc_ecmd);
-            return(rc);
-		}
-		rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits);
-				if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : GCR_write error for rx_wiretest_pll_cntl_pg");
-			return rc;
-		}
-        
-		// write rx_wt_timeout_sel to '111'
-		bits=rx_wt_timeout_sel_tap7;
-		rc_ecmd|=set_bits.insert(rx_wt_timeout_sel_buf,0,16);
-		//Update for DDLEVEL - as per Garys find 
-		if(ddlevel==1){
-		rc_ecmd|=  set_bits.setBit(9);
-		rc_ecmd|=  set_bits.setBit(10);
-		rc_ecmd|=  set_bits.setBit(11);
-		}else{
-		rc_ecmd|=    set_bits.setBit(10);
-		rc_ecmd|=  set_bits.setBit(11);
-		rc_ecmd|=  set_bits.setBit(12);
-		}
-        bits=rx_wt_timeout_sel_clear;
-        //rc_ecmd|=clear_bits.insert(bits,0,16);
-		rc_ecmd|=clear_bits.flushTo0();
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-	    FAPI_ERR("IO_DCCAL : error clearing bits for GCR_write rx_timeout_sel_pgrx_timeout_sel_pg");
-            return(rc);
-        }
-	// -- REVIEW , here bits are not used , only set_bits which are now conditioanlized 
-        rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);
-	if (rc)
-	{
-	  FAPI_ERR("IO_DCCAL : GCR_write error for rx_timeout_sel_pg");
-	  return rc;
-	}
-	    
-       
-		//writw rx_start_offset_cal to '1'
-    	bits=rx_start_offset_cal;
-        rc_ecmd|=set_bits.insert(bits,0,16);
-        bits=rx_start_offset_cal_clear;
-        rc_ecmd|=clear_bits.insert(bits,0,16); 
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-	    FAPI_ERR("IO_DCCAL : error setting up clear bits for GCR_write rx_training_start_pg");
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,rx_training_start_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-	
-	if (rc)
-	{
-		FAPI_ERR("IO_DCCAL : GCR_write error for rx_training_start_pg");
-		return rc;
-	}	
-		//write rx_wt_cu_pll_reset to '1'
-		rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf_copy);if (rc) {return(rc);}
-		rc_ecmd|=set_bits.insert(rx_wt_cu_pll_pgooddly_buf_copy,0,16);
-		//set_bits.setBit(0);
-		rc_ecmd|=set_bits.setBit(1);
-		//set_bits.setBit(2);
-		//set_bits.setBit(3);
-		//set_bits.setBit(4);
-		bits=rx_wt_cu_pll_pgooddly_clear;
-		rc_ecmd|=clear_bits.flushTo0();
-		if(rc_ecmd)
-		{
-		  FAPI_ERR("IO_DCCAL : error setting up set_bits and clear_bits for GCR_write rx_wiretest_pll_cntl_pg");
-			rc.setEcmdError(rc_ecmd);
-            return(rc);
-		}
-		rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits);
-		if(rc)
-				{
-			FAPI_ERR("IO_DCCAL : GCR_write error for rx_wiretest_pll_cntl_pg");
-			return rc;
-		}
-		
-		//write rx_wt_cu_pll_pgood to '1'
-		rc= GCR_read(*target_ptr,master_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf_copy);
-		if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : GCR_read error for rx_wiretest_pll_cntl_pg");
-			return rc;
-		}
-		rc_ecmd|=set_bits.insert(rx_wt_cu_pll_pgooddly_buf_copy,0,16);
-		rc_ecmd|=set_bits.setBit(0);
-		//set_bits.setBit(1);
-		//set_bits.setBit(2);
-		//set_bits.setBit(3);
-		//set_bits.setBit(4);
-		bits=rx_wt_cu_pll_pgooddly_clear;
-		rc_ecmd|=clear_bits.flushTo0();
-		if(rc_ecmd)
-		{
-		  FAPI_ERR("IO_DCCAL : error setting up set_bits and clear_bits for GCR_write rx_wiretest_pll_cntl_pg");
-			rc.setEcmdError(rc_ecmd);
-            return(rc);
-		}
-		rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,set_bits ,clear_bits);
-		if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : GCR_write error for rx_wiretest_pll_cntl_pg");
-			return rc;
-		}
-		
-	    fapiDelay(100000000,10000000); //Wait 100ms for zcal to complete before polling the status register
-      
-	    //write rx_wt_timeout_sel to '000'
-      rc_ecmd|=  set_bits.insert(rx_wt_timeout_sel_buf,0,16);
-		if(ddlevel==1){
-		rc_ecmd|=  set_bits.clearBit(9);
-		rc_ecmd|=  set_bits.clearBit(10);
-		rc_ecmd|=  set_bits.clearBit(11);
-		}else{
-		rc_ecmd|=    set_bits.clearBit(10);
-		rc_ecmd|=  set_bits.clearBit(11);
-		rc_ecmd|=  set_bits.clearBit(12);
-		}
-        bits=rx_wt_timeout_sel_clear;
-        //rc_ecmd|=clear_bits.insert(bits,0,16);
-		rc_ecmd|=clear_bits.flushTo0();
-        if(rc_ecmd)
-        {
-	  FAPI_ERR("IO_DCCAL : error setting up set_bits and clear_bits for GCR_write rx_timeout_sel_pg");
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-	//-- REVIEW here also bits var is not used but above dlevel conditions take care
-        rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);
-			if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : error GCR_write rx_timeout_sel_pg");
-			return rc;
-		}
-        // Poll for the done bit
-	
-        rc=GCR_read(*target_ptr,master_interface,rx_training_status_pg ,group,0,data_buffer);
-		if (rc)
-		{
-			FAPI_ERR("IO_DCCAL : error GCR_read rx_training_status_pg");
-			return rc;
-		}
-        
-        int done_bit=rx_offset_cal_done;
-        int fail_bit=rx_offset_cal_failed;
-        bool fail= data_buffer.getHalfWord(0) & fail_bit;
-        bool done = data_buffer.getHalfWord(0)& done_bit;
-        int timeoutCnt = 0;
-	//Updating timeout as per Gary/Joe's defect SW251251 to be ~1s than the 50s earlier count
-	// This needs to be regressed in lab 
-        while ( ( !done ) && ( timeoutCnt < 100 ) && !fail )
-        {
-                // wait for 80000 time units
-                // Time units may be something for simulation, and something else (or nothing) for hardware
-                // At any rate, this is intended to be approximately 100 us.
-                rc=GCR_read(*target_ptr,chip_interface,rx_training_status_pg,group,0,data_buffer);
-					if (rc)
-			{
-				// have to add support for field parsing
-				FAPI_ERR("IO_DCCAL : error GCR_read rx_training_status_pg in polling for done bit loop");
-				return rc;
-			}
-                fail= data_buffer.getHalfWord(0) & fail_bit;
-                done = data_buffer.getHalfWord(0)& done_bit;
-                fapiDelay(10000000,10000000);
-                timeoutCnt++;
-        }
-        
-        if ( fail)
-        {
-                FAPI_ERR("IO Offset cal error on interface %d",chip_interface);
-                //Set HWP error
-		io_interface_t& CHIP_INTERFACE = chip_interface;
-		ecmdDataBufferBase& DATA_BUFFER = data_buffer;
-		int& FAIL_BIT = fail_bit;
-		const Target &TARGET = target;
-
-                FAPI_SET_HWP_ERROR(rc,IO_DCCAL_OFFCAL_ERROR_RC);
-                return rc;
-        }
-        // Check for errors
-        else if ( timeoutCnt >=100 && !done && !fail )
-        {
-                FAPI_ERR("Timed out waiting for Done bit to be set");
-                //Set HWP error
-				int &TIMEOUTCNT=timeoutCnt;
-                FAPI_SET_HWP_ERROR(rc,IO_DCCAL_OFFCAL_TIMEOUT_RC);
-                return rc;
-        }
-        else
-        {
-             FAPI_DBG("IO Offset cal Completed on interface %d with timeoutcount %d",chip_interface,timeoutCnt);
-        }
-        
-        // clear eye opt offset cal done bit, rx_eo_latch_offset_done
-		rc=GCR_read(*target_ptr,chip_interface,rx_eo_step_stat_pg,group,0,set_bits);
-				if (rc)
-		{
-			// have to add support for field parsing
-			FAPI_ERR("IO_DCCAL : error GCR_read rx_eo_step_stat_pg");
-			return rc;
-		}
-        rc_ecmd|=set_bits.clearBit(0);
-        bits=rx_eo_latch_offset_done_clear;
-        rc_ecmd|=clear_bits.insert(bits,0,16);
-        if(rc_ecmd)
-        {
-	  FAPI_ERR("IO_DCCAL : error in set and clear bits for GCR_write rx_eo_step_stat_pg");
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,rx_eo_step_stat_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-        FAPI_DBG("Reading back 4.\n");
-		rc= GCR_read(*target_ptr,master_interface,rx_eo_step_stat_pg ,group,0,data_buffer);if (rc) {return(rc);}
-        // //restore rx_pdwn_lite_disable to saved value
-        
-        // bits=rx_pdwn_lite_value;
-        // rc_ecmd|=set_bits.insert(bits,0,16);
-        bits=rx_pdwn_lite_disable_clear;
-        rc_ecmd|=clear_bits.insert(bits,0,16);
-        // if(rc_ecmd)
-        // {
-            // rc.setEcmdError(rc_ecmd);
-            // return(rc);
-        // }
-        rc=GCR_write(*target_ptr,chip_interface,rx_mode_pg,group,0,rx_pdwn_lite_value_buf ,clear_bits);if (rc) {return(rc);}
-        
-		
-		
-        // restore rx_wt_timeout_sel to saved value
-        
-        //bits=rx_wt_timeout_value;
-		bits=rx_wt_timeout_sel_tap3;
-        rc_ecmd|=set_bits.insert(rx_wt_timeout_sel_buf,0,16);
-		//rc_ecmd |= set_bits.setAnd(bits,9,3);
-		// if(target.getType() !=  fapi::TARGET_TYPE_MEMBUF_CHIP){
-			// rc_ecmd|=set_bits.insert(bits,9,3);
-		// }
-		// else
-		//rc_ecmd |= set_bits.clearBit(9);
-        // --  bits=rx_wt_timeout_sel_clear;
-        rc_ecmd|=clear_bits.flushTo0();
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,rx_timeout_sel_pg,group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-        
-		FAPI_DBG("Reading back 5.\n");
-		rc= GCR_read(*target_ptr,master_interface,rx_timeout_sel_pg ,group,0,data_buffer);if (rc) {return(rc);}
-		
-        
-		//restore rx_wt_cu_pll_pgooddly
-		//restore rx_wt_cu_pll_reset
-		//restore rx_wt_cu_pll_pgood. Since they all belong to the same register field.
-		bits=rx_wt_cu_pll_pgooddly_clear;
-		rc_ecmd|=clear_bits.flushTo0();
-		if(rc_ecmd)
-		{
-			rc.setEcmdError(rc_ecmd);
-            return(rc);
-		}
-		rc=GCR_write(*target_ptr,chip_interface,rx_wiretest_pll_cntl_pg,group,0,rx_wt_cu_pll_pgooddly_buf ,clear_bits);if (rc) {return(rc);}
-    
-    
-    return(rc);
-}
-
-ReturnCode run_zcal_debug(const Target& target,io_interface_t interface,uint32_t group)
-{
-    ReturnCode rc;
-    ecmdDataBufferBase data_buffer(16);
-    rc=GCR_read(target,interface,tx_impcal_nval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
-    rc=GCR_read(target,interface,tx_impcal_pval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
-    rc=GCR_read(target,interface,tx_impcal_p_4x_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
-    return rc;
-}
-
-ReturnCode run_zcal(const Target& target,io_interface_t master_interface,uint32_t master_group){
-    ReturnCode rc;
-    const Target *target_ptr=&target; // Assuming I am allowed to do this . 
-    uint32_t m=128; // MARGIN RATIO
-    uint32_t k2=0; // POST CURSOR DRIVE RATIO
-    bool swOverride=false;// IS SW_OVERRIDE requested
-    uint16_t bits = 0;
-    uint32_t rc_ecmd=0;
-    ecmdDataBufferBase set_bits(16);
-    ecmdDataBufferBase clear_bits(16);
-    ecmdDataBufferBase data_buffer(16);
-    rc_ecmd=set_bits.flushTo0();
-    rc_ecmd|=clear_bits.flushTo1(); // I dont want to clear anything by default
-    const fapi::Target &TARGET=target;
-    const uint32_t& K2 = k2;
-    const uint32_t& M = m;
-    if(rc_ecmd)
-    {
-        rc.setEcmdError(rc_ecmd);
-        return(rc);
-    }
-    io_interface_t chip_interface=master_interface;//first we run on master chip
-    uint32_t group=master_group;
-    
-        const uint32_t min        = (10<<3);   // impcntl min -  - p8 - 10<<3
-        const uint32_t max        = (40<<3);   // impcntl max -  - p8 - 40<<3
-    
-        uint32_t zcal_p = 0;
-        uint32_t zcal_n = 0;
-            
-        uint32_t  zcal_override = 0; 
-    
-        if ((zcal_n>0) && (zcal_p>0) )
-        {
-                zcal_override = 1;
-        }
-    
-        if ( k2 > 0x20 ) {
-                    FAPI_DBG("POST CURSOR DRIVER RATIO k2 has exceeded 0.25");
-                    FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_K2_EXCEEDED_RC);
-                    return rc;
-        }
-    
-        if ( m > 0x80 ) {
-                    FAPI_DBG("MARGIN RATIO m has exceeded 100 percent");
-                    FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_M_EXCEEDED_RC);
-                    return rc;
-        }
-
-          if ( ( ! zcal_override ) && ( ! swOverride ) )
-        {
-
-                                FAPI_DBG("IO_DCCAL : Starting Impedance Calibration ");
-                                //Get initial settings for debug purpose
-                                run_zcal_debug(*target_ptr,chip_interface,group);
-                                // Clear zcal_start. Need to first set start bit to 0 to enable rise to 1 transition.
-                                rc=GCR_write(*target_ptr,chip_interface,tx_impcal_pb,group,0,set_bits,clear_bits,true);if (rc) {return(rc);}
-                                bits=tx_zcal_req;
-                                rc_ecmd|=set_bits.insert(bits,0,16);
-                                bits=tx_zcal_req_clear;
-                                rc_ecmd|=clear_bits.insert(bits,0,16);                                
-                                if(rc_ecmd)
-                                {
-                                    rc.setEcmdError(rc_ecmd);
-                                    return(rc);
-                                }
-                                // Skip a readback and verify 
-                                rc=GCR_write(*target_ptr,chip_interface,tx_impcal_pb,group,0,set_bits,clear_bits,true);if (rc) {return(rc);}
-                                fapiDelay(20000000,10000000); //Wait 20ms for zcal to complete before polling the status register
-                                // Poll for the done bit
-                                rc=GCR_read(*target_ptr,chip_interface,tx_impcal_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
-                                int done_bit=tx_zcal_done;
-                                int fail_bit=tx_zcal_error;
-                                bool fail= data_buffer.getHalfWord(0) & fail_bit;
-                                bool done = data_buffer.getHalfWord(0)& done_bit;
-                                int timeoutCnt = 0;
-                                while ( ( !done ) && ( timeoutCnt <150 ) ) {
-                                            // wait for 80000 time units
-                                            // Time units may be something for simulation, and something else (or nothing) for hardware
-                                            // At any rate, this is intended to be approximately 100 us.                                                  
-                                            rc=GCR_read(*target_ptr,chip_interface,tx_impcal_pb,group,0,data_buffer); if (rc) {return(rc);}// have to add support for field parsing
-                                            done = data_buffer.getHalfWord(0)& done_bit;
-                                            fail= data_buffer.getHalfWord(0) & fail_bit;
-                                            fapiDelay(10000,10000000); //Wait around for HW 
-                                            timeoutCnt++;
-                                }
-                                if(fail)
-                                {
-                                    FAPI_DBG("IO Impedance cal error on interface %d ",chip_interface);
-                                     run_zcal_debug(*target_ptr,chip_interface,group);
-                                    //set HWP error
-				    ecmdDataBufferBase& DATA_BUFFER=data_buffer;
-				    bool &FAIL=fail;
-                                    FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_ERROR_RC);
-                                    return(rc);
-                                    
-                                }
-                                // Check for errors
-                                else if ( timeoutCnt >= 100 &&!done && !fail )
-                                {
-                                            FAPI_DBG("Timed out waiting for Done bit to be set");
-                                            //set HWP error
-					    int &TIMEOUTCNT=timeoutCnt;
-                                            FAPI_SET_HWP_ERROR(rc,IO_DCCAL_ZCAL_TIMEOUT_RC);
-                                            return rc;
-                                }
-                                else
-                                {
-                                    FAPI_DBG("IO Impedance cal DONE successfully on interface %d",chip_interface);
-                                }                
-    
-    
-                    // Read the calculated values
-                    // (Values are: xxxxxx yy zz, where yy are 2R and 4R values, and zz is a binary fraction)
-                    rc=GCR_read(*target_ptr,chip_interface,tx_impcal_nval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
-                    data_buffer.extractToRight(&zcal_n,0,9); 
-                    rc=GCR_read(*target_ptr,chip_interface,tx_impcal_pval_pb,group,0,data_buffer);if (rc) {return(rc);} // have to add support for field parsing
-                    data_buffer.extractToRight(&zcal_p,0,9); 
-    
-        }
-        else if ( swOverride )
-        {
-            /*
-                   Software override might be required in case of workarounds to HW
-            */
-        }
-    
-        if ( ( (uint32_t)zcal_n < min )|| ( (uint32_t)zcal_n > max ) )
-        {
-                    FAPI_ERR("zcal_n value is out of impcntl range");
-		    uint32_t &ZCAL_N=zcal_n;
-		    const uint32_t &MIN=min;
-		    const uint32_t &MAX=max;
-		    
-                    FAPI_SET_HWP_ERROR(rc, IO_DCCAL_ZCALN_VALUE_OUT_OF_RANGE_RC);
-                    return rc;
-        }
-        if (   ( (uint32_t)zcal_p < min )|| ( (uint32_t)zcal_p > max ) )
-        {
-                    FAPI_ERR("zcal_p value is out of impcntl range");
-		    uint32_t &ZCAL_P=zcal_p;
-		    const uint32_t &MIN=min;
-		    const uint32_t &MAX=max;
-                    FAPI_SET_HWP_ERROR(rc, IO_DCCAL_ZCALP_VALUE_OUT_OF_RANGE_RC); 
-                    return rc;
-        }
-    
-        // margin = (1 -m)*zcal/2
-        //  bits:                       7    10
-        uint32_t margin_p = (0x80 - m) * zcal_p / 2;  // 7+2 = 9 binary decimal places // when it is 1 - something should it not be 0x01 - m?
-        uint32_t margin_n = (0x80 - m) * zcal_n / 2;  // 7+2 = 9 binary decimal places
-    
-        // postcursor = (zcal - 2*margin)*k2
-        //  bits:             7    7   10
-        uint32_t post_p = (zcal_p - (margin_p<<1))*k2;  // 7+7+2 = 16 binary decimal places
-        uint32_t post_n = (zcal_n - (margin_n<<1))*k2;  // 7+7+2 = 16 binary decimal places
-    
-        uint32_t main_p = (zcal_p - (margin_p<<1))- post_p;  // 2 binary decimal places
-        uint32_t main_n = (zcal_n - (margin_n<<1))- post_n;  // 2 binary decimal places
-    
-    
-        // Rounding
-        post_p = BinaryRound(post_p, 16, 999); // round up
-        post_n = BinaryRound(post_n, 16, 999); // round up
-        margin_p = BinaryRound(margin_p, 9, 999); // round up
-        margin_n = BinaryRound(margin_n, 9, 999); // round up
-        main_p = BinaryRound(main_p, 2, 999); // round up
-        main_n = BinaryRound(main_n, 2, 999); // round up
-             
-        FAPI_DBG("main_p value %d",main_p);
-        FAPI_DBG("post_p value %d",post_p);
-        FAPI_DBG("margin_p value %d",margin_p);
-        FAPI_DBG("main_n value %d",main_n);
-        FAPI_DBG("post_n value %d",post_n);
-        FAPI_DBG("margin_n value %d",margin_n);
-        
-              
-        rc_ecmd|=set_bits.flushTo0();
-        rc_ecmd|=clear_bits.flushTo0(); // I dont want to clear anything by default
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        //N segments
-        rc_ecmd|=set_bits.insert(main_p,1,7,25);
-        rc_ecmd|=set_bits.insert(main_n,9,7,25);
-
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_main_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
-        
-        rc_ecmd|=set_bits.flushTo0();
-        rc_ecmd|=clear_bits.flushTo0(); // I dont want to clear anything by default
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc_ecmd|=set_bits.insert(post_p,3,5,27);
-        rc_ecmd|=set_bits.insert(post_n,11,5,27);
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_post_pg ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
-        
-        rc_ecmd|=set_bits.flushTo0();
-        rc_ecmd|=clear_bits.flushTo0(); // I dont want to clear anything by default
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc_ecmd|=set_bits.insert(margin_p,3,5,27);
-        rc_ecmd|=set_bits.insert(margin_n,11,5,27);
-        if(rc_ecmd)
-        {
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-        rc=GCR_write(*target_ptr,chip_interface,tx_ffe_margin_pg  ,group,0,set_bits,clear_bits);if (rc) {return(rc);}
-        
-
-    return rc;
-}
-
-// Determines if target is a master ..I had assumed that PLAT wrapper code will know which side is master and which is slave 
-ReturnCode isChipMaster(const Target&  chip_target, io_interface_t chip_interface,uint32_t current_group, bool   & masterchip_found ) {
-    ReturnCode rc;
-    ecmdDataBufferBase    mode_data(16);
-    masterchip_found=false;
-
-    // Check if rx_master_mode bit is set for chip
-    // Read  rx_master_mode  for chip
-    if(chip_interface==CP_FABRIC_X0)
-    {
-	rc=GCR_read(chip_target ,  chip_interface, ei4_rx_mode_pg,  current_group,0, mode_data);
-    }
-    else
-    {
-	rc=GCR_read(chip_target ,  chip_interface, rx_mode_pg,  current_group,0, mode_data);
-    }
-    if (rc) {
-         FAPI_DBG("io_run_training: Error reading master mode bit\n");
-    }
-    // Check if  chip is master
-    if (mode_data.isBitSet(0)) {
-	 FAPI_DBG("This chip is a master\n");
-        masterchip_found  =true;
-    }
-    return(rc);
-}
-
-// These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave
-// In EI4 both sides have pu targets
-ReturnCode io_dccal(const Target& target){
-    ReturnCode rc;
-    io_interface_t master_interface=CP_IOMC0_P0;
-    uint32_t master_group=0;
-
-    fapi::Target parent_target;
-    const fapi::Target& TARGET = target;
-    FAPI_DBG("Running IO DCCAL PROCEDURE");
-
-    // This is a DMI/MC bus
-    if (target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
-    {
-        FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
-        master_interface=CP_IOMC0_P0; // base scom for MC bus
-        master_group=3; // Design requires us to do this as per scom map and layout
-
-        // determine chip unit position
-        uint8_t mcs_pos;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &target, mcs_pos);
-        if (rc)
-        {
-            FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
-            return(rc);
-        }
-
-        // obtain parent chip target needed for ring manipulation
-	    rc = fapiGetParentChip(target, parent_target);
-        if (rc)
-        {
-            FAPI_ERR("Error from fapiGetParentChip");
-            return(rc);
-        }
-
-        // update PLL for dccal operation
-        rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
-                                            RING_ADDRESS_PROC_PB_BNDY_DMIPLL,
-                                            RING_OP_MOD_REFCLK_SEL,
-                                            static_cast<p8_pll_utils_bus_id>(mcs_pos),
-                                            true);
-        if (rc)
-        {
-            FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-            return(rc);
-        }
-
-        // EDI/DMI needs both impedance cal and offset cal
-        // Z cal doesnt require group since its a per bus feature , but to satisfy PLAT swapped translation requirements we pass group=3 on master
-        rc = run_zcal(target,master_interface,master_group);
-        if (rc)
-        {
-            FAPI_ERR("Error from run_zcal");
-            return(rc);
-        }
-        // Offset cal requires group address
-        rc = run_offset_cal(target,master_interface,master_group);
-        if (rc)
-        {
-            FAPI_ERR("Error from run_offset_cal");
-            return(rc);
-        }
-
-        // restore PLL config for functional operation
-        rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
-                                            RING_ADDRESS_PROC_PB_BNDY_DMIPLL,
-                                            RING_OP_MOD_REFCLK_SEL,
-                                            static_cast<p8_pll_utils_bus_id>(mcs_pos),
-                                            true);
-        if (rc)
-        {
-            FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-            return(rc);
-        }
-    }
-    else if (target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)
-    {
-        FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
-        master_interface=CEN_DMI; // base scom for CEN
-        master_group=0;
-
-        // install PLL config for dccal operation
-        rc = proc_a_x_pci_dmi_pll_scan_bndy(target,
-                                            RING_ADDRESS_MEMB_TP_BNDY_PLL,
-                                            RING_OP_MOD_REFCLK_SEL,
-                                            RING_BUS_ID_0,
-                                            true);
-        if (rc)
-        {
-            FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-            return(rc);
-        }
-
-        // EDI/DMI needs both impedance cal and offset cal
-        // Z cal doesnt require group since its a per bus feature , but to satisfy PLAT swapped translation requirements we pass group=3 on master
-        // Offset cal requires group address
-        rc = run_zcal(target,master_interface,master_group);
-        if (rc)
-        {
-            FAPI_ERR("Error from run_zcal");
-            return(rc);
-        }
-        rc = run_offset_cal(target,master_interface,master_group);
-        if (rc)
-        {
-            FAPI_ERR("Error from run_offset_cal");
-            return(rc);
-        }
-
-        // restore PLL config for functional operation
-        rc = proc_a_x_pci_dmi_pll_scan_bndy(target,
-                                            RING_ADDRESS_MEMB_TP_BNDY_PLL,
-                                            RING_OP_MOD_REFCLK_SEL,
-                                            RING_BUS_ID_0,
-                                            true);
-        if (rc)
-        {
-            FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-            return(rc);
-        }
-	}
-    //This is an X Bus
-    else if (target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)
-    {
-        FAPI_DBG("This is a X Bus training invocation");
-    }
-    //This is an A Bus
-    else if (target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)
-    {
-        FAPI_DBG("This is an A Bus training invocation");
-        master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
-        master_group=0; // Design requires us to do this as per scom map and layout
-
-        uint8_t abus;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &target, abus);
-        if (rc)
-        {
-            FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS)");
-            return(rc);
-        }
-
-        // obtain parent chip target needed for ring manipulation
-	    rc = fapiGetParentChip(target, parent_target);
-        if (rc)
-        {
-            FAPI_ERR("Error from fapiGetParentChip");
-            return(rc);
-        }
-
-        // install PLL config for dccal operation
-        rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
-                                            RING_ADDRESS_PROC_AB_BNDY_PLL,
-                                            RING_OP_MOD_REFCLK_SEL,
-                                            static_cast<p8_pll_utils_bus_id>(abus),
-                                            true);
-        if (rc)
-        {
-            FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-            return(rc);
-        }
-
-        // EDI-A bus needs both impedance cal and offset cal
-	    rc = run_zcal(target,master_interface,master_group);
-        if (rc)
-        {
-            FAPI_ERR("Error from run_zcal");
-            return(rc);
-        }
-	    rc = run_offset_cal(target,master_interface,master_group);
-        if (rc)
-        {
-            FAPI_ERR("Error from run_offset_cal");
-            return(rc);
-        }
-
-        // restore PLL config for functional operation
-        rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
-                                            RING_ADDRESS_PROC_AB_BNDY_PLL,
-                                            RING_OP_MOD_REFCLK_SEL,
-                                            static_cast<p8_pll_utils_bus_id>(abus),
-                                            true);
-        if (rc)
-        {
-            FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-            return(rc);
-        }
-    }
-    else
-    {
-        FAPI_ERR("Invalid io_dccal HWP invocation . Target doesnt belong to DMI/X/A instances");
-        FAPI_SET_HWP_ERROR(rc, IO_DCCAL_INVALID_INVOCATION_RC);
-    }
-    return rc;
-}
-
-
-
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/bus_training/io_dccal.H b/src/usr/hwpf/hwp/bus_training/io_dccal.H
deleted file mode 100644
index 868410c87..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_dccal.H
+++ /dev/null
@@ -1,55 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_dccal.H $                    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_dccal.H,v 1.9 2013/12/04 10:35:50 jaswamin Exp $
-#ifndef IO_DCCAL_H_
-#define IO_DCCAL_H_
-
-#include <fapi.H>
-
-using namespace fapi;
-
-/**
- * io_dccal HWP func pointer typedef
- *
- */
-typedef fapi::ReturnCode (*io_dccal_FP_t)(const fapi::Target &target);
-
-extern "C"
-{
-
-/**
- * io_dccal HWP 
- *
- * master_target is any IO target P8 MCS,XBUS,Abus or centaur
- * 
- * 
- *
- * 
- */
-
-fapi::ReturnCode io_dccal(const fapi::Target &target);
-
-    
-} // extern "C"
-#endif // IO_DCCAL_H_
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C b/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C
deleted file mode 100644
index c27888dc0..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_fir_isolation.C
+++ /dev/null
@@ -1,554 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_fir_isolation.C $            */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_fir_isolation.C,v 1.14 2014/03/20 14:06:08 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 2012  , 2013
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_fir_isolation.C
-// *! TITLE                :
-// *! DESCRIPTION          : To isolate the error causing the firs to flag
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com
-// *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.9   |jaswamin|04/19/13| Fixes for firmware compile issues.
-//   1.8   |jaswamin|03/22/13| Added comments
-//   1.7   |jaswamin|03/18/13| Changed indentation
-//   1.6   |jaswamin|03/13/13| Returncode logging
-//   1.5   |jaswamin|03/12/13| Return in case of a gcr operation error.
-//   1.4   |jaswamin|03/06/13| Removed commented out portion.
-//   1.3   |jaswamin|03/04/13| Changes as per review comment.
-//   1.2   |jaswamin|02/20/13| Changes as per review comment
-//   1.1   |jaswamin|02/14/13| Initial check in .
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "io_fir_isolation.H"
-#include "gcr_funcs.H"
-
-
-extern "C" {
-
-
-using namespace fapi;
-
- //! Function    : io_fir_too_many_bus_err_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //! Returns     : o_rc => FFDC data for too many bus error. This includes the target
- //!                                              details and the source of the error.
- //! Description : This function provides the target details including the clock group
- //!               which had this error. This is sent as FFDC data along with the training
- //!               register contents.
-ReturnCode io_fir_too_many_bus_err_isolation(const fapi::Target &i_target,
-                                             io_interface_t i_chip_interface,
-                                             uint32_t i_current_group){
-
-        ReturnCode o_rc;
-        ecmdDataBufferBase    error_data(16);
-
-        o_rc=GCR_read(i_target ,  i_chip_interface, rx_fir_training_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        if(error_data.isBitSet(8,1)){
-            ecmdDataBufferBase & BUS_ERROR_REG = error_data; //bit1 of the register represnts the spare deployed bit.
-            const fapi::Target & ENDPOINT = i_target;
-            FAPI_SET_HWP_ERROR(o_rc,IO_FIR_TOO_MANY_BUS_ERROR_RC);
-			fapiLogError(o_rc,FAPI_ERRL_SEV_UNRECOVERABLE);
-        }
-        return(FAPI_RC_SUCCESS);
-}
-
- //! Function    : io_fir_recal_error_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //! Returns     : o_rc => FFDC data for recal error. This includes the target details
- //!               and the source of the error.
- //! Description : This function collects the register contents of the training register
- //!               that would help root cause the error which could be due to
- //!               dynamic repair fail or dynamic recal fail. This is given
- //!               as FFDC data.
-ReturnCode io_fir_recal_error_isolation(const fapi::Target &i_target,
-                                        io_interface_t i_chip_interface,
-                                        uint32_t i_current_group){
-
-        ReturnCode o_rc;
-        ecmdDataBufferBase    error_data(16);
-
-        o_rc=GCR_read(i_target ,  i_chip_interface, rx_fir_training_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        if(error_data.isBitSet(3,1) || error_data.isBitSet(6,1)){       //can be caused by dynamic repair or recal error (bits 3 and 6 respectively)
-            ecmdDataBufferBase & RECAL_ERROR_REG = error_data ; //bit1 of the register represnts the spare deployed bit.
-            const fapi::Target & ENDPOINT = i_target;
-            FAPI_SET_HWP_ERROR(o_rc,IO_FIR_RECALIBRATION_ERROR_RC);
-			fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-        }
-        return(FAPI_RC_SUCCESS); // bilicon: This needs to be changed to "return(o_rc)"
-}
-
- //! Function    : io_fir_max_spares_exceeded_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //! Returns     : o_rc => FFDC data for maximum deployable spares exceeded error.
- //!               This includes the target details and the source of the error.
- //! Description : This function collects the register contents of the training register
- //!               that would help root cause the error as being from pre/during training,
- //!               post training or during recal that caused the spares to exceed.
- //!               This is provided as FFDC dump.
-ReturnCode io_fir_max_spares_exceeded_isolation(const fapi::Target &i_target,
-                                                io_interface_t i_chip_interface,
-                                                uint32_t i_current_group){
-
-        ReturnCode o_rc;
-        ecmdDataBufferBase    error_data(16);
-
-        o_rc=GCR_read(i_target ,  i_chip_interface, rx_fir_training_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        if(error_data.isBitSet(2,1) || error_data.isBitSet(5,1)|| error_data.isBitSet(8,1)){    // can be caused by a static (pre training - bit 2) or dynamic (post training - bit 5) or recal(bit 8)
-            ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit2 /bit 5 /bit 8of the register represents the max spare exceeded bit.To determine what caused the max spares exceeded error
-            const fapi::Target & ENDPOINT = i_target;
-            FAPI_SET_HWP_ERROR(o_rc,IO_FIR_MAX_SPARES_EXCEEDED_FIR_RC);
-			fapiLogError(o_rc,FAPI_ERRL_SEV_UNRECOVERABLE);
-        }
-        return(FAPI_RC_SUCCESS); // bilicon: This needs to be changed to "return(o_rc)"
-}
-
- //! Function    : io_fir_spare_deployed_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //! Returns     : o_rc => FFDC data for spare deployed error. This includes the
- //!               target details and the source of the error.
- //! Description : This function collects the register contents of the training register
- //!               that would help root cause the error as being from pre/during training,
- //!               post training or during recal that caused the spares to be deployed.
- //!               This is provided as FFDC dump.
-ReturnCode io_fir_spare_deployed_isolation(const fapi::Target &i_target,
-                                           io_interface_t i_chip_interface,
-                                           uint32_t i_current_group){
-
-        ReturnCode o_rc;
-        ecmdDataBufferBase    error_data(16);
-
-        o_rc=GCR_read(i_target ,  i_chip_interface, rx_fir_training_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        if(error_data.isBitSet(1,1) || error_data.isBitSet(4,1) || error_data.isBitSet(7,1)){ // can be caused by a spare deployment prior to training , post training or during recal
-            ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit1 /bit4 / bit 7 of the register represnts the spare deployed bit. To determine which type of error caused the spare to be deployed
-            const fapi::Target & ENDPOINT = i_target;
-            FAPI_SET_HWP_ERROR(o_rc,IO_FIR_SPARES_DEPLOYED_FIR_RC);
-			fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-        }
-        return(FAPI_RC_SUCCESS);// bilicon: This needs to be changed to "return(o_rc)"
-}
-
- //! Function    : io_fir_tx_parity_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //! Returns     : o_rc => FFDC data for the tx fir parity error. This includes
- //!               the target details, the parity error that caused this bit to be set
- //!               and the lane id if it is a lane level error.
- //! Description : This function collects the register contents that would help
- //!               determine the source of the parity error and provides it as a FFDC data dump.
-
-ReturnCode io_fir_tx_parity_isolation(const fapi::Target &i_target,
-                                      io_interface_t i_chip_interface,
-                                      uint32_t i_current_group){
-
-        ReturnCode o_rc;
-        ecmdDataBufferBase    error_data(16);
-        uint32_t loop_val=0;
-        uint32_t lane,group;
-
-        if(i_chip_interface==CP_FABRIC_X0){
-                lane=77;
-        }
-        else if(i_chip_interface==CP_FABRIC_A0){
-                lane=23;
-        }
-        else if(i_chip_interface==CP_IOMC0_P0){
-                lane=17;
-        }
-        else{
-                lane=24;
-        }
-
-        for(loop_val=0;loop_val<lane;loop_val++){
-
-                if(i_chip_interface==CP_FABRIC_X0){
-                        group=loop_val%20;
-                }
-                else{
-                        group=i_current_group;
-                }
-
-                o_rc=GCR_read(i_target ,  i_chip_interface, tx_fir_pl,  group,loop_val, error_data);
-                if(o_rc){
-                    FAPI_ERR("io_fir_isolation: Error reading rx fir per lane register\n");
-                    return(o_rc);
-                }
-                //bit 0 for rx_fir_pl in case of X and bit 0 and 1 for A and DMI
-                if(error_data.isBitSet(0,1)){
-
-                    // find the current lane and group to send information
-
-                    uint32_t & LANE_ID = loop_val;
-                    ecmdDataBufferBase & TX_ERROR_REG = error_data;
-                    const fapi::Target & ENDPOINT = i_target;
-                    FAPI_DBG("io_fir_rx_parity_isolation:A per lane register or state machine error has occured. Lane is %d\n",loop_val);
-                    FAPI_SET_HWP_ERROR(o_rc,IO_FIR_LANE_TX_PARITY_ERROR_RC);
-					fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-                    break;
-                }
-        }
-
-
-        o_rc=GCR_read(i_target ,i_chip_interface, tx_fir_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        for(loop_val=0;loop_val<16;loop_val++){
-
-                if(error_data.isBitSet(loop_val,1)){
-
-                    ecmdDataBufferBase & TX_ERROR_REG = error_data;
-                    const fapi::Target & ENDPOINT = i_target;
-                    FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GROUP_TX_PARITY_ERROR_RC);
-					fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-                    break;
-                }
-        }
-
-        return(FAPI_RC_SUCCESS);
-
-}
-
- //! Function    : io_fir_rx_parity_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //! Returns     : o_rc => FFDC data for the rx fir parity error. This includes
- //!               the target details, the parity error that caused this bit to be set
- //!               and the lane id if it is a lane level error.
- //! Description : This function collects the register contents that would help determine
- //!               the source of the parity error and provides it as a FFDC data dump.
-ReturnCode io_fir_rx_parity_isolation(const fapi::Target &i_target,
-                                      io_interface_t i_chip_interface,
-                                      uint32_t i_current_group){
-
-
-        ReturnCode o_rc;
-        ecmdDataBufferBase    error_data(16);
-        uint32_t loop_val=0;
-        uint32_t lane,group;
-
-        //in case its bit 0 it is the rx_parity error. To find which bit is set read the registers that contribute to it. This is a per lane register. Hence we need to loop through each
-        //lane to determine which is erroring out.
-        if(i_chip_interface==CP_FABRIC_X0){
-                lane=77;
-        }
-        else if(i_chip_interface==CP_FABRIC_A0){
-                lane=23;
-        }
-        else if(i_chip_interface==CP_IOMC0_P0){
-                lane=24;
-        }
-        else{
-                lane=17;
-        }
-
-        for(loop_val=0;loop_val<lane;loop_val++){
-
-                if(i_chip_interface==CP_FABRIC_X0){
-                        group=loop_val%20;
-                }
-                else{
-                        group=i_current_group;
-                }
-
-                o_rc=GCR_read(i_target ,  i_chip_interface, rx_fir_pl,  group,loop_val, error_data);
-
-                if(o_rc){
-                    FAPI_DBG("io_fir_isolation: Error reading rx fir per lane register\n");
-                    return(o_rc);
-                }
-                //bit 0 for rx_fir_pl in case of X and bit 0 and 1 for A and DMI
-                if(error_data.isBitSet(0,1) || error_data.isBitSet(1,1)){
-
-
-                    // find the current lane and group to send information
-                    uint32_t & LANE_ID = loop_val;
-                    ecmdDataBufferBase & RX_ERROR_REG = error_data;
-                    const fapi::Target & ENDPOINT = i_target;
-                    FAPI_DBG("io_fir_rx_parity_isolation:A per lane register or state machine error has occured. Lane is %d\n",loop_val);
-                    FAPI_SET_HWP_ERROR(o_rc,IO_FIR_LANE_RX_PARITY_ERROR_RC);
-					fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-                    break;
-                }
-        }
-
-        //for fir1_reg and fir2_reg it is group wise hence do not need lane information
-
-        o_rc=GCR_read(i_target ,i_chip_interface, rx_fir1_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        for(loop_val=0;loop_val<16;loop_val++){
-
-                if(error_data.isBitSet(loop_val,1)){
-                    ecmdDataBufferBase & RX_ERROR_REG = error_data;
-                    const fapi::Target & ENDPOINT = i_target;
-                    FAPI_DBG("io_fir_isolation: %s\n",fir1_reg[loop_val]);
-                    FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GROUP_RX_PARITY_ERROR_RC);
-					fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-                    break;
-                }
-        }
-
-
-        o_rc=GCR_read(i_target ,  i_chip_interface, rx_fir2_pg,  i_current_group,0, error_data);
-        if(o_rc)
-                return o_rc;
-        for(loop_val=0;loop_val<16;loop_val++){
-
-                if(error_data.isBitSet(loop_val,1)){
-                    ecmdDataBufferBase & RX_ERROR_REG = error_data;
-                    const fapi::Target & ENDPOINT = i_target;
-                    FAPI_DBG("io_fir_isolation: %s\n",fir2_reg[loop_val]);
-                    FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GROUP_RX_PARITY_ERROR_RC);
-					fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-                    break;
-                }
-        }
-
-
-        o_rc=GCR_read(i_target,i_chip_interface,rx_fir_pb,i_current_group,0,error_data);
-        if(o_rc)
-                return o_rc;
-        for(loop_val=0;loop_val<16;loop_val++){
-
-                if(error_data.isBitSet(loop_val,1)){
-                    ecmdDataBufferBase & RX_ERROR_REG = error_data;
-                    const fapi::Target & ENDPOINT = i_target;
-                    FAPI_SET_HWP_ERROR(o_rc,IO_FIR_BUS_RX_PARITY_ERROR_RC);
-					fapiLogError(o_rc,FAPI_ERRL_SEV_RECOVERED);
-                    break;
-                }
-        }
-        return(FAPI_RC_SUCCESS);
-}
-
- //! Function    : io_error_isolation
- //! Parameters  : i_target => FAPI target,
- //!               chip_interface => io_chip_interface viz., A, X, DMI, CEN
- //!               current_group  => current clock group under test in the interface
- //!               fir_data       => data in the 64 bit flat scom fir register
- //! Returns     : o_rc => FFDC data for the FIR error if any (determined using the bit
- //!               set in the 64 bit fir register)
- //! Description : This function determines the type of error based on the fir bit that
- //!               is set and calls the appropriate isolation function for that error.
-ReturnCode io_error_isolation(const fapi::Target &i_target,
-                              io_interface_t i_chip_interface,
-                              uint32_t i_current_group,
-                              ecmdDataBufferBase &i_fir_data){
-
-        ReturnCode o_rc;
-        //ecmdDataBufferBase    error_data(16),id_data(16);
-
-
-        //need to determine what error it represents.
-
-        //if it is a rx_parity error
-        if(i_fir_data.isBitSet(RX_PARITY,1)){
-                o_rc=io_fir_rx_parity_isolation(i_target,i_chip_interface,i_current_group);
-				if(o_rc)
-                        return(o_rc);
-        }
-
-        //check for tx_parity error
-        if(i_fir_data.isBitSet(TX_PARITY,1)){
-
-                o_rc=io_fir_tx_parity_isolation(i_target,i_chip_interface,i_current_group);
-				if(o_rc)
-                        return(o_rc);
-        }
-
-        //GCR hang error
-        if(i_fir_data.isBitSet(GCR_HANG_ERROR,1)){
-            //check whether the gcr hang error bit is set
-
-
-                const fapi::Target & ENDPOINT = i_target;
-                FAPI_SET_HWP_ERROR(o_rc,IO_FIR_GCR_HANG_ERROR_RC);
-                fapiLogError(o_rc,FAPI_ERRL_SEV_UNRECOVERABLE); //since the logging of error needs to happen here for this error.
-
-
-        }
-
-        //spare deploy?
-        if(i_fir_data.isBitSet(BUS0_SPARE_DEPLOYED,1) ||
-           i_fir_data.isBitSet(BUS1_SPARE_DEPLOYED,1) ||
-           i_fir_data.isBitSet(BUS2_SPARE_DEPLOYED,1) ||
-           i_fir_data.isBitSet(BUS3_SPARE_DEPLOYED,1) ||
-           i_fir_data.isBitSet(BUS4_SPARE_DEPLOYED,1) ){
-
-           o_rc=io_fir_spare_deployed_isolation(i_target,i_chip_interface,i_current_group);
-		   if(o_rc)
-                        return(o_rc);
-
-
-        }
-
-        //maximum spares deployed and exceeded?
-        if(i_fir_data.isBitSet(BUS0_MAX_SPARES_EXCEEDED,1) ||
-           i_fir_data.isBitSet(BUS1_MAX_SPARES_EXCEEDED,1) ||
-           i_fir_data.isBitSet(BUS2_MAX_SPARES_EXCEEDED,1) ||
-           i_fir_data.isBitSet(BUS3_MAX_SPARES_EXCEEDED,1) ||
-           i_fir_data.isBitSet(BUS4_MAX_SPARES_EXCEEDED,1)){
-
-           o_rc=io_fir_max_spares_exceeded_isolation(i_target,i_chip_interface,i_current_group);
-           if(o_rc)
-                return(o_rc);
-
-        }
-
-        //recalibration error
-        if(i_fir_data.isBitSet(BUS0_RECALIBRATION_ERROR,1) ||
-           i_fir_data.isBitSet(BUS1_RECALIBRATION_ERROR,1) ||
-           i_fir_data.isBitSet(BUS2_RECALIBRATION_ERROR,1) ||
-           i_fir_data.isBitSet(BUS3_RECALIBRATION_ERROR,1) ||
-           i_fir_data.isBitSet(BUS4_RECALIBRATION_ERROR,1)){
-
-
-           o_rc=io_fir_recal_error_isolation(i_target,i_chip_interface,i_current_group);
-		   if(o_rc)
-				return(o_rc);
-
-        }
-
-       //too many bus errors
-        if(i_fir_data.isBitSet(BUS0_TOO_MANY_BUS_ERRORS,1) ||
-           i_fir_data.isBitSet(BUS1_TOO_MANY_BUS_ERRORS,1) ||
-           i_fir_data.isBitSet(BUS2_TOO_MANY_BUS_ERRORS,1) ||
-           i_fir_data.isBitSet(BUS3_TOO_MANY_BUS_ERRORS,1) ||
-           i_fir_data.isBitSet(BUS4_TOO_MANY_BUS_ERRORS,1)){
-
-           o_rc=io_fir_too_many_bus_err_isolation(i_target,i_chip_interface,i_current_group);
-		   if(o_rc)
-				return(o_rc);
-
-        }
-
-        return(FAPI_RC_SUCCESS); // Currently this does not cause any harm as you are returning all the errors in the middle of the function, but it is good to change this to  "return(o_r)".
-}
-
-ReturnCode io_fir_isolation(const fapi::Target &i_target){
-
-    ReturnCode o_rc;
-    uint32_t rc_ecmd=0;
-    fir_io_interface_t interface;
-    io_interface_t gcr_interface; // requires different base address for gcr scoms
-    uint32_t group;
-    ecmdDataBufferBase    fir_data(64);
-    rc_ecmd|=fir_data.flushTo0();
-    if(rc_ecmd)
-    {
-        o_rc.setEcmdError(rc_ecmd);
-        return(o_rc);
-    }
-
-    //on dmi
-    if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
-          FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
-          interface=FIR_CP_IOMC0_P0; // base scom for MC bus
-          gcr_interface=CP_IOMC0_P0;
-          o_rc=read_fir_reg(i_target,interface,fir_data);
-          group=3;
-          if(o_rc)
-                        return(o_rc);
-          o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
-
-     }
-     //on cen side
-     else if((i_target.getType() ==  fapi::TARGET_TYPE_MEMBUF_CHIP)){
-            FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
-            interface=FIR_CEN_DMI;
-            gcr_interface=CEN_DMI;
-            o_rc=read_fir_reg(i_target,interface,fir_data);
-            group=0;
-            if(o_rc)
-                        return(o_rc);
-            o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
-
-     }
-     // on x bus
-     else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){
-            FAPI_DBG("This is a X Bus invocation");
-            interface=FIR_CP_FABRIC_X0;
-            gcr_interface=CP_FABRIC_X0;
-            o_rc=read_fir_reg(i_target,interface,fir_data);
-            group=0;
-            if(o_rc)
-                        return(o_rc);
-            o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
-
-     }
-     //on a bus
-     else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
-            FAPI_DBG("This is an A Bus invocation");
-            interface=FIR_CP_FABRIC_A0;
-            gcr_interface=CP_FABRIC_A0;
-            o_rc=read_fir_reg(i_target,interface,fir_data);
-            group=0;
-            if(o_rc)
-                        return(o_rc);
-            o_rc=io_error_isolation(i_target,gcr_interface,group,fir_data);
-
-     }
-     else{
-        FAPI_ERR("Invalid io_fir HWP invocation . Target doesnt belong to DMI/X/A instances");
-        const fapi::Target & ENDPOINT = i_target;
-        FAPI_SET_HWP_ERROR(o_rc, IO_FIR_INVALID_INVOCATION_RC);
-     }
-
-     return(o_rc);
-
-
-}
-
-
-}
diff --git a/src/usr/hwpf/hwp/bus_training/io_fir_isolation.H b/src/usr/hwpf/hwp/bus_training/io_fir_isolation.H
deleted file mode 100644
index 0a57dc7f5..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_fir_isolation.H
+++ /dev/null
@@ -1,85 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_fir_isolation.H $            */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_fir_isolation.H,v 1.5 2013/04/15 10:30:45 jaswamin Exp $

-// *!***************************************************************************

-// *! (C) Copyright International Business Machines Corp. 2012, 2013

-// *!           All Rights Reserved -- Property of IBM

-// *!                   ***  ***

-// *!***************************************************************************

-// *! FILENAME             : IO_fir_isolation.H

-// *! TITLE                : 

-// *! DESCRIPTION          : This procedure provides FFDC data obtained by isolating the errors based on the bit set in the 64 bit register. This can be used to root cause the issue.

-// *! CONTEXT              : 

-// *!

-// *! OWNER  NAME          : Janani Swaminathan         Email: jaswamin@in.ibm.com

-// *! BACKUP NAME          : Varkey Varghese            Email: varkey.kv@in.ibm.com      

-// *!

-// *!***************************************************************************

-// CHANGE HISTORY:

-//------------------------------------------------------------------------------

-// Version:|Author: | Date:  | Comment:

-// --------|--------|--------|--------------------------------------------------

-//   1.5   |jaswamin|13/04/15| Fixed the parameter description in comment.

-//   1.4   |jaswamin|13/03/22| Changed it to conform with the FW specifications

-//   1.3   |jaswamin|13/03/18| Made it more readable.

-//   1.2   |jaswamin|13/03/06| Added cvs tag

-//   1.1   |jaswamin|13/02/14| Initial check in

-//------------------------------------------------------------------------------

-

-/****************************************************************************************/

-/* IO_FIR_ISOLATION.H                                                                           */

-/****************************************************************************************/

-#ifndef IO_FIR_ISOLATION_H

-#define IO_FIR_ISOLATION_H

-

-#include "io_clear_firs.H"

-

-using namespace fapi;

-typedef fapi::ReturnCode (*io_fir_isolation_FP_t)(const fapi::Target &target);

-

-extern "C"

-{

-

-/**

- * io_fir_isoaltion HWP 

- *

- * target is any IO target P8 MCS,XBUS,Abus or centaur

- * 

- * 

- *

- * 

- */

-

- //! Function    : io_fir_isolation

- //! Paramteres  : i_target => FAPI target

- //! Returns     : o_rc => return code for function.

- //! Description : Wrapper code that calls the underlying error isolation procedures - to be used by the firmware for sending in target information.

- //!               This function gets target information and the 64 bit flat scom fir register value necessary for gathering FFDC data. 

-fapi::ReturnCode io_fir_isolation(const fapi::Target &i_target);

-

-

-} // extern "C"

-#endif

-

diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
deleted file mode 100644
index f76549cd9..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ /dev/null
@@ -1,1130 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_funcs.C $                    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.C,v 1.25 2014/03/20 08:36:49 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : IO_funcs.C
-// *! TITLE                : 
-// *! DESCRIPTION          : IO training common functions
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com     
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//  1.14   |jaswamin|01/28/12| Changed fatal errors to warning prints to allow training to continue
-//   1.0   |varkeykv|01/19/12| Initial check in to solve linker problems in host
-//			       boot..moved in from io_run_training
-//------------------------------------------------------------------------------
-#include "io_funcs.H"
-
-
-extern "C"
-{
-    using namespace fapi;
-    
-
-/****************************************************************************************/
-/* edi_training.C   - functions of edi_training class                                */
-/****************************************************************************************/
-
-//! Wrapper to Run W,D,E,R , F based on bus_status (selected on);
-ReturnCode  edi_training::run_training(const Target& master_target,  io_interface_t master_interface,uint32_t master_group, const Target&  slave_target,  io_interface_t  slave_interface,uint32_t slave_group) {
-    ReturnCode rc;
-    // bool master_chip_found=false; -- maybe for fabric ...need to test later
-	
-	FAPI_DBG("io_run_training: Starting training on SLAVE side");
-
-	// Set the slave rx_start_wderf
-        rc=run_training_functions(slave_target,slave_interface,slave_group);
-	if (!rc.ok())  {
-		 FAPI_ERR("io_run_training: Failed starting slave side training");
-	}
-        else{
-            FAPI_DBG("io_run_training: Starting training on MASTER side\n");
-            // Set the master  rx_start_wderf
-            rc=run_training_functions(master_target,  master_interface,master_group);
-            if (!rc.ok())  {
-                    FAPI_ERR("io_run_training: Failed starting master side training");
-            }
-            else{
-                 // Get training function  status for Master Chip  (poll on the master chip's rx_wderf_done)
-		 if(master_interface==CP_FABRIC_X0){
-		    for (int current_group = 0 ; current_group < 4; current_group++)
-		    {
-		    rc=training_function_status(master_target  ,  master_interface,current_group,   slave_target  ,  slave_interface,current_group);
-			if(!rc.ok()){
-			    FAPI_ERR("io_run_training : Failed Training");
-			    return rc;
-			}
-		    }
-		 }
-		 else{
-		     rc=training_function_status(master_target  ,  master_interface,master_group,   slave_target  ,  slave_interface,slave_group);
-			if(!rc.ok()){
-			    FAPI_ERR("io_run_training : Failed Training");
-			    return rc;
-			}
-		    }
-		 }
-        }
-    return(rc);
-}
-
-
-//  Run selected training function(s)
-ReturnCode  edi_training::run_training_functions(const Target& target, io_interface_t interface,uint32_t current_group) {
-    ReturnCode rc;
-	uint32_t rc_ecmd=0;
-	uint16_t bits=0;
-	ecmdDataBufferBase set_bits, clear_bits,status_data;
-	rc_ecmd|=set_bits.setBitLength(16);
-	rc_ecmd|=clear_bits.setBitLength(16);
-	rc_ecmd|=set_bits.flushTo0();
-	rc_ecmd|=clear_bits.flushTo0();
-	
-	if(rc_ecmd)
-	{
-		FAPI_ERR("io_run_training:Data Buffer initiatlization failed !!\n");
-		rc.setEcmdError(rc_ecmd); 
-	}
-	else
-	{// Successful databuffer initialization ..we can proceed 
-		if (wire_test_status==SELECTED)
-                {
-			bits=rx_start_wiretest;
-			if(endpoints_set==1)
-			{
-				wire_test_status = RUNNING;
-			}
-			rx_wderf_start[WIRE_TEST]=1;
-		}
-		if (desckew_status==SELECTED)
-                {
-			bits|=rx_start_deskew;
-			rx_wderf_start[DESKEW]=1;
-			if(endpoints_set==1)
-			{
-				desckew_status = RUNNING;
-			}
-		}
-		if (eye_opt_status==SELECTED)
-                {
-			bits|=rx_start_eye_opt;
-			rx_wderf_start[EYE_OPT]=1;
-			if(endpoints_set==1)
-			{
-				eye_opt_status= RUNNING;
-			}
-		}
-		if (repair_status==SELECTED)
-                {
-			bits|=rx_start_repair;
-			rx_wderf_start[REPAIR]=1;
-			if(endpoints_set==1)
-			{
-				repair_status = RUNNING;
-			}
-		}
-		if (functional_status==SELECTED)
-                {
-			bits|=rx_start_func_mode;
-			rx_wderf_start[FUNCTIONAL]=1;
-			if(endpoints_set==1)
-			{
-				functional_status = RUNNING;
-			}
-		}
-		endpoints_set++; // Count number of endpoints we have set for training... when its 2 then we set the status to RUNNING
-	
-		// No need to do group wise loops , since for every end point there will be a separate thread of training code run 
-		// Set Start Bits for group
-		// Group address is set to 0 , since according to Discussion with Dean ,this code will run once per group.
-		rc_ecmd|=set_bits.insert(bits,0,16);
-
-		if(rc_ecmd)
-		{
-			FAPI_ERR("io_run_training:Data Buffer insertion failed !!\n");
-                        rc.setEcmdError(rc_ecmd);
-		}
-		else
-		{
-
-			if(interface==CP_FABRIC_X0)
-			{
-	      		       FAPI_DBG("io_run_training:Setting Training start bit via broadcast on interface %d group=%d\n",interface,current_group);
-   			       rc=GCR_write(target ,  interface,  ei4_rx_training_start_pg, 15,0,   set_bits, clear_bits,1,1);
-			}
-			else
-			{
-  	           FAPI_DBG("io_run_training:Setting Training start bit on interface %d group=%d\n",interface,current_group);
-			   rc=GCR_write(target ,  interface,  rx_training_start_pg, current_group,0,   set_bits, clear_bits);
-			}
-			if (rc) {
-				 FAPI_ERR("io_run_training: Failed to write training start bits \n");
-			}
-		}
-	}
-    return(rc);
- }
-
-
-// Checks Status of Training Functions on Master Chip and also captures failure data on failure
-ReturnCode  edi_training::training_function_status(const Target&  master_chip_target, io_interface_t  master_chip_interface ,uint32_t master_group,  const Target& slave_chip_target ,
-												   io_interface_t slave_chip_interface,uint32_t slave_group)
-{
-    ReturnCode rc;
-    uint32_t rc_ecmd=0;
-    ecmdDataBufferBase    status_data;
-    rc_ecmd|=status_data.setBitLength(16);
-    rc_ecmd|=status_data.flushTo0();
-    
-    	//Reference variables matching error XML
-	const fapi::Target& MASTER_TARGET = master_chip_target;
-	const fapi::Target& SLAVE_TARGET = slave_chip_target;
-	const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface;
-	const uint32_t& MASTER_GROUP = master_group;
-	const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface;
-	const uint32_t& SLAVE_GROUP = slave_group;
-    
-    if(rc_ecmd)
-    {
-          FAPI_ERR("io_run_training: Failed buffer intialization in training_function_status\n");
-          rc.setEcmdError(rc_ecmd);
-    }
-    else
-    {
-        uint64_t  curr_cyc = 0;         // start time
-        uint64_t end_cycle=max_poll_cycles ;
-	
-	uint64_t &FFDC_NUM_CYCLES=curr_cyc;
-        int state,fail_bit;
-    
-        while ( curr_cyc < end_cycle )
-            {
-                    // Reads Status Register for interface
-		    if(master_chip_interface==CP_FABRIC_X0)
-			{
-			  rc=GCR_read(master_chip_target , master_chip_interface,  ei4_rx_training_status_pg,  master_group,0,  status_data);
-			}
-		    else
-		    {
-			rc=GCR_read(master_chip_target , master_chip_interface,  rx_training_status_pg,  master_group,0,  status_data);
-		    }
-                    if (rc) {
-                      FAPI_DBG("io_run_training:Failed reading training status on master chip\n");
-                      return(rc);
-                    }
-    
-                    if (wire_test_status== RUNNING )
-                    {
-                            state=WIRE_TEST;
-                            fail_bit=rx_wiretest_failed;
-			    //Done bit does not get set on FAIL ..Update as per Mike Spears/Pete
-                            if( status_data.isBitSet(state) || (status_data.getHalfWord(0) & fail_bit) )
-                            {
-                                    rx_wderf_done[WIRE_TEST]=true;
-                                    if (status_data.getHalfWord(0) & fail_bit)
-                                    {
-                                       FAPI_ERR("io_run_training: the wiretest training state reported a fail  \n");
-				      // FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_WIRETEST_RC);
-                                       wire_test_status =  FAILED ;
-                                       rx_wderf_failed[WIRE_TEST]=true;
-                                      // Run First FAILED Data Capture for Wire Test for FAILED bus
-                                       rc=dump_ffdc_wiretest(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
-				       break;
-				    
-                                    }
-                                    else
-                                    {
-                                       FAPI_DBG("io_run_training:   the wiretest training function completed successfully  \n") ;
-                                       wire_test_status =  SUCCESSFULL ;
-                                    }
-                            }
-                     }
-                    
-                    if (desckew_status == RUNNING )
-                    {
-                            state=DESKEW;
-                            fail_bit=rx_deskew_failed;
-			    //Done bit does not get set on FAIL ..Update as per Mike Spears/Pete
-                            if( status_data.isBitSet(state)|| (status_data.getHalfWord(0) & fail_bit))
-                            {
-                                    rx_wderf_done[DESKEW]=1;
-                                    if (status_data.getHalfWord(0) & fail_bit || (status_data.getHalfWord(0) & fail_bit) )
-                                    {
-                                            rx_wderf_failed[DESKEW]=true;
-                                            FAPI_ERR("io_run_training : deskew training state reported a fail  \n");
-                                            //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_DESKEW_RC);
-                                            desckew_status =  FAILED ;
-					    rc=dump_ffdc_deskew(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
-					    break;
-                                    }
-                                    else
-                                    {
-                                            FAPI_DBG("io_run_training:    deskew  training function completed successfully  \n") ;
-                                            desckew_status =   SUCCESSFULL ;
-                                    }
-                            }
-                    }
-                    
-                    if (eye_opt_status == RUNNING )
-                    {
-                            state=EYE_OPT;
-                            fail_bit=rx_eye_opt_failed;
-			     //Done bit does not get set on FAIL ..Update as per Mike Spears/Pete
-                            if( status_data.isBitSet(state) || (status_data.getHalfWord(0) & fail_bit) )
-                            {
-                                    rx_wderf_done[EYE_OPT]=1;
-                                    if (status_data.getHalfWord(0) & fail_bit)
-                                    {
-                                             FAPI_ERR("io_run_training : eye_opt_ training state reported a fail\n");
-                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_EYE_OPT_RC);
-                                             rx_wderf_failed[EYE_OPT]=true;
-                                             eye_opt_status =  FAILED ;
-					    rc=dump_ffdc_eyeopt(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
-					     break;
-                                    }
-                                    else
-                                    {
-                                             FAPI_DBG("io_run_training:    eye_opt_ training function completed successfully  \n") ;
-                                             eye_opt_status =   SUCCESSFULL ;
-                                    }
-                            }
-                    }
-                    
-                    if (repair_status == RUNNING )
-                    {
-                            state=REPAIR;
-                            fail_bit=rx_repair_failed;
-			     //Done bit does not get set on FAIL ..Update as per Mike Spears/Pete
-                            if( status_data.isBitSet(state) || (status_data.getHalfWord(0) & fail_bit) )
-                            {
-                                    rx_wderf_done[REPAIR]=1;
-                                    if (status_data.getHalfWord(0) & fail_bit)
-                                    {
-                                             FAPI_DBG("io_run_training: static repair encountered an error    \n");
-					      //FAPI_SET_HWP_ERROR(rc,   IO_RUN_TRAINING_FAIL_REPAIR_RC);
-					     rc=dump_ffdc_repair(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
-                                             rx_wderf_failed[REPAIR]=true;
-                                             repair_status =  FAILED ;
-					     break;
-                                    }
-                                    else
-                                    {
-                                             FAPI_DBG("io_run_training:   the rx_repair function completed successfully  \n") ;
-                                             repair_status =  SUCCESSFULL ;
-                                    }
-                            }
-                    }
-                    
-                    
-                    if (functional_status == RUNNING)
-                    {
-			FAPI_DBG("functional status is Running!!");
-                            state=FUNCTIONAL;
-                            fail_bit=rx_func_mode_failed;
-			     //Done bit does not get set on FAIL ..Update as per Mike Spears/Pete
-                            if( status_data.isBitSet(state ) || (status_data.getHalfWord(0) & fail_bit))
-                            {
-                                    rx_wderf_done[FUNCTIONAL]=1;
-                                    if (status_data.getHalfWord(0) & fail_bit)
-                                    {
-                                             FAPI_DBG("io_run_training:   rx_func_mode_failed    \n");
-                                             rx_wderf_failed[FUNCTIONAL]=true;
-                                             //FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_FAIL_FUNC_MODE_RC);
-					      rc=dump_ffdc_func(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
-                                             functional_status =   FAILED ;
-					     break;
-                                    }
-                                    else
-                                    {
-                                             FAPI_DBG("io_run_training:   rx_func_mode_function completed successfully  \n") ;
-                                             functional_status =  SUCCESSFULL  ;
-                                    }
-                       }
-                    }
-                    
-                    
-                    if ((wire_test_selected && wire_test_status== RUNNING)  ||  (desckew_selected && desckew_status == RUNNING)   ||
-                       (repair_selected &&  repair_status == RUNNING )     ||  (eye_opt_selected && eye_opt_status == RUNNING)   ||
-                       (functional_selected &&  functional_status ==   RUNNING ) )
-                    {
-                        // Training still running  ,  continue checking status
-                        curr_cyc++;
-                        FAPI_DBG("\n\t io_run_training: Cycles into polling = %lld\n", curr_cyc);
-                        FAPI_DBG("\n\t io_run_training: Cycles remaining in polling = %lld\n", end_cycle - curr_cyc );
-			// Updated Loop count and per delay call count to acheive max of 100ms theoretical delay as per Mike Spear
-			// This is 1ms poll call..Loop counter =100 .. a total of ~100ms
-                        rc=fapiDelay(1000000,increment_poll_cycles);
-                        if(!rc.ok())
-                        {
-                               FAPI_ERR("io_run_training : Unexpected error in fapiDelay routine\n");
-                               return(rc);
-                        }
-                    }
-                    else
-                    {
-                     // Training Completed Exit cuurent  Loop
-                     break;
-                    }
-                    
-                    if ( curr_cyc >= end_cycle )
-                    {
-                            dump_ffdc_wiretest(master_chip_target, master_chip_interface ,master_group,  slave_chip_target ,  slave_chip_interface,slave_group);
-			     
-			    if (wire_test_selected && wire_test_status== RUNNING)
-			    {
-			    FAPI_ERR("io_run_training: wiretest timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_FUNCS_WIRETEST_TIMEOUT_RC);
-			    }
-			    else if (desckew_selected && desckew_status == RUNNING)
-			    {
-			    FAPI_ERR("io_run_training: deskew timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_FUNCS_DESKEW_TIMEOUT_RC);
-			    }
-			    else if (repair_selected && repair_status == RUNNING)
-			    {
-			    FAPI_ERR("io_run_training: repair timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_FUNCS_REPAIR_TIMEOUT_RC);
-			    }
-			    else if (eye_opt_selected && eye_opt_status == RUNNING)
-			    {
-			    FAPI_ERR("io_run_training: eyeopt timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_FUNCS_EYEOPT_TIMEOUT_RC);
-			    }
-			    else
-			    {
-			    FAPI_ERR("io_run_training: func timeout");
-			    FAPI_SET_HWP_ERROR(rc, IO_FUNCS_FUNC_MODE_TIMEOUT_RC);
-			    }
-			    break;
-                    }
-            }   // polling loop
-    }
-    return(rc);
-}
-
-// Determines if target is a master...currently not used , but could be used in Fabric(EI4) but i assume PLAT code will know which side is master and which is slave 
-ReturnCode edi_training::isChipMaster(const Target&  chip_target, io_interface_t chip_interface,uint32_t current_group, bool   & masterchip_found ) {
-    ReturnCode rc;
-    ecmdDataBufferBase    mode_data(16);
-    masterchip_found=false;
-
-    // Check if rx_master_mode bit is set for chip
-    // Read  rx_master_mode  for chip
-    if(chip_interface==CP_FABRIC_X0)
-    {
-	rc=GCR_read(chip_target ,  chip_interface, ei4_rx_mode_pg,  current_group,0, mode_data);
-    }
-    else
-    {
-	rc=GCR_read(chip_target ,  chip_interface, rx_mode_pg,  current_group,0, mode_data);
-    }
-    if (rc) {
-         FAPI_DBG("io_run_training: Error reading master mode bit\n");
-    }
-    // Check if  chip is master
-    if (mode_data.isBitSet(0)) {
-	 FAPI_DBG("This chip is a master\n");
-        masterchip_found  =true;
-    }
-    return(rc);
-}
-
-
-
-// First Fail Data Capture (wire_test)
-// FFDC functions have not been tested in detail ..
-// Will need to tie this into the eRepair/PRD conversation that we are having with Zane
-  // DUMP ALL THESE
-  //      rx_lane_disabled_vec_0_15_pg,
-  //      rx_lane_disabled_vec_16_31_pg,
-  //      rx_lane_swapped_vec_0_15_pg,
-  //      rx_lane_swapped_vec_16_31_pg,
-  //      rx_init_state_pg,
-  //      rx_wiretest_state_pg,
-  //      rx_wiretest_laneinfo_pg,
-  //	rx_wt_status_pl
-          //rx_main_init_state
-          //rx_wtl_state
-          //rx_wtm_state
-          //rx_wtr_state
-          //rx_wtr_bad_lane_count
-          //rx_wt_lane_bad_code ( per lane - can we?)
-          //rx_wtr_bad_lane_count
-          //rx_wiretest_failed
-          //rx_wt_clk_bad_lane_code?
-          //rx_wt_clk_lane_inverted?
-	  //rx_wt_clk_status_pg
-ReturnCode  edi_training::dump_ffdc_wiretest(const Target&  master_chip_target, io_interface_t  master_chip_interface ,uint32_t master_group, const Target& slave_chip_target ,
-											 io_interface_t slave_chip_interface,uint32_t slave_group)
-{
-    ReturnCode rc;
-    ReturnCode lane_rc; // for logging per lane FFDC
-    
-	const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface;
-	const uint32_t& MASTER_GROUP = master_group;
-	const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface;
-	const uint32_t& SLAVE_GROUP = slave_group;
-    
-    const fapi::Target &MASTER_TARGET=master_chip_target;
-    const fapi::Target &SLAVE_TARGET=slave_chip_target;
-    
-    
-    //FFDC Buffers
-    ecmdDataBufferBase MASTER_RX_LANE_BAD_0_15_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_BAD_16_31_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_DISABLED_VEC_0_15_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_DISABLED_VEC_16_31_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_SWAPPED_VEC_0_15_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_SWAPPED_VEC_16_31_PG(16);
-    ecmdDataBufferBase MASTER_RX_INIT_STATE_PG(16);
-    ecmdDataBufferBase MASTER_RX_WIRETEST_STATE_PG(16);
-    ecmdDataBufferBase MASTER_RX_WIRETEST_LANEINFO_PG(16);
-    ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase MASTER_RX_WT_CLK_STATUS_PG(16);
-    
-     ecmdDataBufferBase SLAVE_RX_LANE_BAD_0_15_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_BAD_16_31_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_DISABLED_VEC_0_15_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_DISABLED_VEC_16_31_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_SWAPPED_VEC_0_15_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_SWAPPED_VEC_16_31_PG(16);
-    ecmdDataBufferBase SLAVE_RX_INIT_STATE_PG(16);
-    ecmdDataBufferBase SLAVE_RX_WIRETEST_STATE_PG(16);
-    ecmdDataBufferBase SLAVE_RX_WIRETEST_LANEINFO_PG(16);
-    ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase SLAVE_RX_WT_CLK_STATUS_PG(16);
-    
-    //These are for per-lane FFDC captures
-    ecmdDataBufferBase RX_WT_STATUS_PL(16);
-    
-    const uint32_t NUM_PG_REGS=11;
-  //  const uint32_t NUM_PL_REGS=0;
-    
-    const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_lane_bad_vec_0_15_pg,rx_lane_bad_vec_16_31_pg,rx_lane_disabled_vec_0_15_pg, rx_lane_disabled_vec_16_31_pg,rx_lane_swapped_vec_0_15_pg,
-    rx_lane_swapped_vec_16_31_pg,rx_init_state_pg,rx_wiretest_state_pg,rx_wiretest_laneinfo_pg,rx_training_status_pg,rx_wt_clk_status_pg};
-    
-   // const GCR_sub_registers pl_reg_list[NUM_PL_REGS]={};
-    
-    ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS]= { &MASTER_RX_LANE_BAD_0_15_PG,
-					    &MASTER_RX_LANE_BAD_16_31_PG,
-					    &MASTER_RX_LANE_DISABLED_VEC_0_15_PG,
-					    &MASTER_RX_LANE_DISABLED_VEC_16_31_PG,
-					    &MASTER_RX_LANE_SWAPPED_VEC_0_15_PG,
-					    &MASTER_RX_LANE_SWAPPED_VEC_16_31_PG,
-					    &MASTER_RX_INIT_STATE_PG,
-					    &MASTER_RX_WIRETEST_STATE_PG,
-					    &MASTER_RX_WIRETEST_LANEINFO_PG,
-					    &MASTER_RX_TRAINING_STATUS_PG,
-					    &MASTER_RX_WT_CLK_STATUS_PG
-					};
-     
-  ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS]= { &SLAVE_RX_LANE_BAD_0_15_PG,
-					    &SLAVE_RX_LANE_BAD_16_31_PG,
-					    &SLAVE_RX_LANE_DISABLED_VEC_0_15_PG,
-					    &SLAVE_RX_LANE_DISABLED_VEC_16_31_PG,
-					    &SLAVE_RX_LANE_SWAPPED_VEC_0_15_PG,
-					    &SLAVE_RX_LANE_SWAPPED_VEC_16_31_PG,
-					    &SLAVE_RX_INIT_STATE_PG,
-					    &SLAVE_RX_WIRETEST_STATE_PG,
-					    &SLAVE_RX_WIRETEST_LANEINFO_PG,
-					    &SLAVE_RX_TRAINING_STATUS_PG,
-					    &SLAVE_RX_WT_CLK_STATUS_PG
-					};
-    FAPI_DBG("dump_ffdc_wiretest function entered \n");
-    
-    
-
-    // Capture MASTER Side registers 
-
-    uint32_t rx_lane_end=num_rxlanes_per_group[master_chip_interface];
-    
-	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(master_chip_target ,  master_chip_interface, pg_reg_list[reg_num],  master_group,0,  *MASTER_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	    
-	}
-	
-	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(slave_chip_target ,  slave_chip_interface, pg_reg_list[reg_num],  slave_group,0,  *SLAVE_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-	
-        FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_WIRETEST_FAIL_RC);
-	
-	//Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex
-	for(uint32_t lane=0;lane<rx_lane_end;++lane){
-	    FAPI_DBG("Reading per lane register RX_WT_STATUS_PL on lane %d",lane);
-	    rc=GCR_read(master_chip_target ,  master_chip_interface, rx_wt_status_pl,  master_group,lane, RX_WT_STATUS_PL);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading RX_WT_STATUS_PL"); 
-	    }
-	    else{
-	    // we will continue to try other lanes data
-	    const fapi::Target & CHIP_TARGET= master_chip_target;
-	     uint32_t &LANEID=lane;
-		//as per Andrea to save log space 
-		FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_WIRETEST_FAIL_LANE_MASTER_DATA_RC);
-	    }
-	}
-	
-
-    // Capture SLAVE Side registers 
-     rx_lane_end=num_rxlanes_per_group[slave_chip_interface];
-    
-
-	
-		//Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex
-	for(uint32_t lane=0;lane<rx_lane_end;++lane){
-	    FAPI_DBG("Reading per lane register RX_WT_STATUS_PL on lane %d",lane);
-	     rc=GCR_read(slave_chip_target ,  slave_chip_interface, rx_wt_status_pl,  slave_group,lane,  RX_WT_STATUS_PL);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading RX_WT_STATUS_PL"); 
-	    }
-	    else{
-	     const fapi::Target & CHIP_TARGET= slave_chip_target;
-	     uint32_t &LANEID=lane;
-		//as per Andrea to save log space 
-		FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_WIRETEST_FAIL_LANE_SLAVE_DATA_RC);
-	    }
-	}
-
-    return(lane_rc);
-}
-
-
-   //rx_rxdsm_state
-   //   rx_deskew_failed --> rx_training_status_pg 
-   //    rx_bad_block_lock --> rx_deskew_stat_pl
-   //     rx_bad_skew  --> rx_deskew_stat_pl
-   //     rx_bad_deskew --> rx_deskew_stat_pl
-   //     rx_some_skew_valid --> rx_stat_pl
-   //     rx_some_block_locked --> rx_stat_pl
-   //     rx_skew_value  --> rx_stat_pl
-   //     rx_vref --> rx_vref_pl 
-   //     rx_fifo_l2u_dly --> rx_fifo_stat_pl 
-   //     rx_phaserot_val -->  rx_prot_status_pl
-
-ReturnCode  edi_training::dump_ffdc_deskew(const Target&  master_chip_target, io_interface_t  master_chip_interface ,uint32_t master_group, const Target& slave_chip_target ,
-											 io_interface_t slave_chip_interface,uint32_t slave_group)
-{
-    ReturnCode rc;
-    ReturnCode lane_rc; // for logging per lane FFDC
-    
-    const fapi::Target &MASTER_TARGET=master_chip_target;
-    const fapi::Target &SLAVE_TARGET=slave_chip_target;
-    	const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface;
-	const uint32_t& MASTER_GROUP = master_group;
-	const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface;
-	const uint32_t& SLAVE_GROUP = slave_group;
-    
-    
-    //FFDC Buffers;
-    ecmdDataBufferBase MASTER_RX_INIT_STATE_PG(16);
-    ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase MASTER_RX_DESKEW_STATE_PG(16);
-      ecmdDataBufferBase MASTER_RX_LANE_BAD_0_15_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_BAD_16_31_PG(16);
-    
-    ecmdDataBufferBase SLAVE_RX_INIT_STATE_PG(16);
-    ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase SLAVE_RX_DESKEW_STATE_PG(16);
-      ecmdDataBufferBase SLAVE_RX_LANE_BAD_0_15_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_BAD_16_31_PG(16);
-
-    
-    //These are for per-lane FFDC captures
-    ecmdDataBufferBase RX_DESKEW_STAT_PL(16);
-    ecmdDataBufferBase RX_STAT_PL(16);
-    ecmdDataBufferBase RX_FIFO_STAT_PL(16);
-    ecmdDataBufferBase RX_PROT_STATUS_PL(16);
-    
-    //EI4 only
-        ecmdDataBufferBase RX_VREF_PL(16);
-    
-    const uint32_t NUM_PG_REGS=5;
-    const uint32_t NUM_PL_REGS=5;
-    
-    const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_init_state_pg,rx_training_status_pg,rx_deskew_state_pg,rx_lane_bad_vec_0_15_pg,rx_lane_bad_vec_16_31_pg};
-    
-    const GCR_sub_registers pl_reg_list[NUM_PL_REGS]={rx_deskew_stat_pl,rx_stat_pl,rx_fifo_stat_pl,rx_prot_status_pl,ei4_rx_vref_pl};
-    
-    ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= {  &MASTER_RX_INIT_STATE_PG,
-					    &MASTER_RX_TRAINING_STATUS_PG,
-					    &MASTER_RX_DESKEW_STATE_PG,&MASTER_RX_LANE_BAD_0_15_PG,&MASTER_RX_LANE_BAD_16_31_PG,
-					    &RX_DESKEW_STAT_PL,
-					    &RX_STAT_PL,
-					    &RX_FIFO_STAT_PL,
-					    &RX_PROT_STATUS_PL,
-					        &RX_VREF_PL
-					};
-     
-    ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= {  &SLAVE_RX_INIT_STATE_PG,
-				       &SLAVE_RX_TRAINING_STATUS_PG,
-				       & SLAVE_RX_DESKEW_STATE_PG,&SLAVE_RX_LANE_BAD_0_15_PG,&SLAVE_RX_LANE_BAD_16_31_PG,
-					    &RX_DESKEW_STAT_PL,
-					    &RX_STAT_PL,
-					    &RX_FIFO_STAT_PL,
-					    &RX_PROT_STATUS_PL,
-					     &RX_VREF_PL
-				   };
-
-
-    FAPI_DBG("dump_ffdc_deskew function entered \n");
-
-    // Capture MASTER Side registers 
-
-    uint32_t rx_lane_end=num_rxlanes_per_group[master_chip_interface];
-    
-	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(master_chip_target ,  master_chip_interface, pg_reg_list[reg_num],  master_group,0,  *MASTER_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-	
-	    
-  	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(slave_chip_target ,  slave_chip_interface, pg_reg_list[reg_num],  slave_group,0,  *SLAVE_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-	
-        FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_RC);
-	//Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex
-	for(uint32_t lane=0;lane<rx_lane_end;++lane){
-	    for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){
-		if(master_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_vref_pl ){
-		    continue; // VREF PL valid only for X bus 
-		}
-		FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane);
-		rc=GCR_read(master_chip_target ,  master_chip_interface, pl_reg_list[lane_reg_num],  master_group,lane, *MASTER_BUFFERS[NUM_PG_REGS+lane_reg_num]);
-		if (rc)
-		{
-		     FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); 
-		}
-		else{
-	    	// we will continue to try other lanes data
-		const fapi::Target & CHIP_TARGET= master_chip_target;
-		 uint32_t &LANEID=lane;
-		 FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_LANE_MASTER_DATA_RC);
-		   //as per Andrea to save log space 
-		   FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_LANE_MASTER_DATA_RC);
-		}
-	     }
-	}
-	
-
-    // Capture SLAVE Side registers 
-     rx_lane_end=num_rxlanes_per_group[slave_chip_interface];
-
-	//Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex
-	for(uint32_t lane=0;lane<rx_lane_end;++lane){
-	    for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){
-		 if(slave_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_vref_pl ){
-		    continue; // VREF PL valid only for X bus 
-		}
-		FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane);
-		rc=GCR_read(slave_chip_target ,  slave_chip_interface, pl_reg_list[lane_reg_num],  slave_group,lane, *SLAVE_BUFFERS[NUM_PG_REGS+lane_reg_num]);
-		if (rc)
-		{
-		     FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); 
-		}
-		else{
-		    		// we will continue to try other lanes data
-		const fapi::Target & CHIP_TARGET= slave_chip_target;
-		 uint32_t &LANEID=lane;
-		   //as per Andrea to save log space 
-		   FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_DESKEW_FAIL_LANE_SLAVE_DATA_RC);
-		}
-	     }
-	}
-
-
-
-    return(lane_rc);
-}
-
-
-// FFDC AS per Rob
-//
-//rx_eye_opt_failed -->  rx_training_status_pg 
-//rx_eye_opt_state  rx_eo_recal_pg 
-//rx_ap_even_samp rx_ap_pl
-//rx_ap_odd_samp rx_ap_pl
-//rx_an_even_samp rx_an_pl
-//rx_an_odd_samp rx_an_pl
-//rx_amin_even  rx_amin_pl 
-//rx_amin_odd  rx_amin_pl 
-//rx_h1_even_samp1  rx_h1_even_pl
-//rx_h1_even_samp0  rx_h1_even_pl
-//rx_h1_odd_samp1  rx_h1_odd_pl
-//rx_h1_odd_samp0 rx_h1_odd_pl
-//rx_bad_eye_opt_ber rx_eye_opt_stat_pl
-//rx_bad_eye_opt_width rx_eye_opt_stat_pl
-//rx_bad_eye_opt_height rx_eye_opt_stat_pl
-//rx_bad_eye_opt_ddc rx_eye_opt_stat_pl
-//rx_eye_width rx_eye_width_status_pl 
-//rx_hist_min_eye_width_valid rx_eye_width_status_pl 
-//rx_hist_min_eye_width rx_eye_width_status_pl 
-//rx_dcd_adjust rx_dcd_adj_pl
-
-ReturnCode  edi_training::dump_ffdc_eyeopt(const Target&  master_chip_target, io_interface_t  master_chip_interface ,uint32_t master_group, const Target& slave_chip_target ,
-											 io_interface_t slave_chip_interface,uint32_t slave_group)
-{
-    ReturnCode rc;
-    ReturnCode lane_rc; // for logging per lane FFDC
-    
-    const fapi::Target &MASTER_TARGET=master_chip_target;
-    const fapi::Target &SLAVE_TARGET=slave_chip_target;
-    
-    	const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface;
-	const uint32_t& MASTER_GROUP = master_group;
-	const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface;
-	const uint32_t& SLAVE_GROUP = slave_group;
-    
-    //FFDC Buffers;
-    ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase MASTER_RX_EO_RECAL_PG(16);
-      ecmdDataBufferBase MASTER_RX_LANE_BAD_0_15_PG(16);
-    ecmdDataBufferBase MASTER_RX_LANE_BAD_16_31_PG(16);
-    
-    ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase SLAVE_RX_EO_RECAL_PG(16);
-      ecmdDataBufferBase SLAVE_RX_LANE_BAD_0_15_PG(16);
-    ecmdDataBufferBase SLAVE_RX_LANE_BAD_16_31_PG(16);
-
-    
-    //These are for per-lane FFDC captures
-    ecmdDataBufferBase RX_AP_PL(16);// EDI only
-    ecmdDataBufferBase RX_AN_PL(16);// EDI only
-    ecmdDataBufferBase RX_AMIN_PL(16);// EDI only
-    ecmdDataBufferBase RX_H1_EVEN_PL(16);// EDI only
-    ecmdDataBufferBase RX_H1_ODD_PL(16);// EDI only
-    ecmdDataBufferBase RX_EYE_OPT_STATE_PL(16); // both
-    ecmdDataBufferBase RX_EYE_WIDTH_STATUS_PL(16); //both 
-    ecmdDataBufferBase RX_DCD_ADJ_PL(16); // ei4 only
-    
-    const uint32_t NUM_PG_REGS=4;
-    const uint32_t NUM_PL_REGS=8;
-    
-    const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_training_status_pg,rx_eo_recal_pg,rx_lane_bad_vec_0_15_pg,rx_lane_bad_vec_16_31_pg};
-    
-    const GCR_sub_registers pl_reg_list[NUM_PL_REGS]={rx_ap_pl,rx_an_pl,rx_amin_pl,rx_h1_even_pl,rx_h1_odd_pl,rx_eye_opt_stat_pl,rx_eye_width_status_pl,ei4_rx_dcd_adj_pl};
-    
-    ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= {  &MASTER_RX_TRAINING_STATUS_PG,
-					    &MASTER_RX_EO_RECAL_PG,&MASTER_RX_LANE_BAD_0_15_PG,&MASTER_RX_LANE_BAD_16_31_PG,
-					    &RX_AP_PL,
-					    &RX_AN_PL,
-					    &RX_AMIN_PL,
-					    &RX_H1_EVEN_PL,
-					    &RX_H1_ODD_PL,
-					    &RX_EYE_OPT_STATE_PL, 
-					    &RX_EYE_WIDTH_STATUS_PL, 
-					    &RX_DCD_ADJ_PL
-					};
-     
-       
-    ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS+NUM_PL_REGS]= {  &SLAVE_RX_TRAINING_STATUS_PG,
-					    &SLAVE_RX_EO_RECAL_PG,&SLAVE_RX_LANE_BAD_0_15_PG,&SLAVE_RX_LANE_BAD_16_31_PG,
-					    &RX_AP_PL,
-					    &RX_AN_PL,
-					    &RX_AMIN_PL,
-					    &RX_H1_EVEN_PL,
-					    &RX_H1_ODD_PL,
-					    &RX_EYE_OPT_STATE_PL, 
-					    &RX_EYE_WIDTH_STATUS_PL, 
-					    &RX_DCD_ADJ_PL
-					};
-     
-
-
-    FAPI_DBG("dump_ffdc_eyeopt function entered \n");
-
-    // Capture MASTER Side registers 
-
-    uint32_t rx_lane_end=num_rxlanes_per_group[master_chip_interface];
-    
-	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(master_chip_target ,  master_chip_interface, pg_reg_list[reg_num],  master_group,0,  *MASTER_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-	
-	    
-  	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(slave_chip_target ,  slave_chip_interface, pg_reg_list[reg_num],  slave_group,0,  *SLAVE_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-	
-        FAPI_SET_HWP_ERROR(lane_rc,IO_FUNCS_EYEOPT_FAIL_RC);
-	//Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex
-	for(uint32_t lane=0;lane<rx_lane_end;++lane){
-	    for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){
-		if(master_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_dcd_adj_pl ){
-		    continue; // DCD ADJ PL valid only for X bus 
-		}
-		if(master_chip_interface==CP_FABRIC_X0 && lane_reg_num<5 ){
-		    continue; // Only 7,8,9 regs valid on X bus 
-		}
-		FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane);
-		rc=GCR_read(master_chip_target ,  master_chip_interface, pl_reg_list[lane_reg_num],  master_group,lane, *MASTER_BUFFERS[NUM_PG_REGS+lane_reg_num]);
-		if (rc)
-		{
-		     FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); 
-		}
-		else{
-		// we will continue to try other lanes data
-		const fapi::Target & CHIP_TARGET= master_chip_target;
-		 uint32_t &LANEID=lane;
-		   //as per Andrea to save log space 
-		   FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_EYEOPT_FAIL_LANE_MASTER_DATA_RC);
-		}
-	     }
-	}
-	
-
-    // Capture SLAVE Side registers 
-     rx_lane_end=num_rxlanes_per_group[slave_chip_interface];
-
-	//Lets do per-lane registers now , will Log and continue instead of wasting buffers and making it complex
-	for(uint32_t lane=0;lane<rx_lane_end;++lane){
-	    for(uint32_t lane_reg_num=0;lane_reg_num<NUM_PL_REGS;++lane_reg_num){
-		if(slave_chip_interface!=CP_FABRIC_X0 && pl_reg_list[lane_reg_num] ==ei4_rx_dcd_adj_pl ){
-		    continue; // DCD ADJ PL valid only for X bus 
-		}
-		if(slave_chip_interface==CP_FABRIC_X0 && lane_reg_num<5 ){
-		    continue; // Only 7,8,9 regs valid on X bus 
-		}
-		FAPI_DBG("Reading per lane register %s on lane %d",GCR_sub_reg_names[pl_reg_list[lane_reg_num]],lane);
-		rc=GCR_read(slave_chip_target ,  slave_chip_interface, pl_reg_list[lane_reg_num],  slave_group,lane, *SLAVE_BUFFERS[NUM_PG_REGS+lane_reg_num]);
-		if (rc)
-		{
-		     FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pl_reg_list[lane_reg_num]]); 
-		}
-		else{
-		    		// we will continue to try other lanes data
-		const fapi::Target & CHIP_TARGET= slave_chip_target;
-		 uint32_t &LANEID=lane;
-		   //as per Andrea to save log space 
-		   FAPI_ADD_INFO_TO_HWP_ERROR(lane_rc,IO_FUNCS_EYEOPT_FAIL_LANE_SLAVE_DATA_RC);
-		}
-	     }
-	}
-
-
-
-    return(lane_rc);
-}
-
-//FFDC for repair  
-//rx_rpr_state rx_static_repair_state_pg
-//rx_repair_failed  rx_training_status_pg 
-//rx_bad_lane1_gcrmsg rx_bad_lane_enc_gcrmsg_pg
-//rx_bad_lane2_gcrmsgrx_bad_lane_enc_gcrmsg_pg
-
-ReturnCode  edi_training::dump_ffdc_repair(const Target&  master_chip_target, io_interface_t  master_chip_interface ,uint32_t master_group, const Target& slave_chip_target ,
-											 io_interface_t slave_chip_interface,uint32_t slave_group)
-{
-    ReturnCode rc;
-    ReturnCode lane_rc; // for logging per lane FFDC
-    
-    const fapi::Target &MASTER_TARGET=master_chip_target;
-    const fapi::Target &SLAVE_TARGET=slave_chip_target;
-    	const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface;
-	const uint32_t& MASTER_GROUP = master_group;
-	const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface;
-	const uint32_t& SLAVE_GROUP = slave_group;
-    
-    //FFDC Buffers;
-    ecmdDataBufferBase MASTER_RX_STATIC_REPAIR_STATE_PG(16);
-    ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase MASTER_RX_BAD_LANE_ENC_GCRMSG_PG(16);
-    
-    ecmdDataBufferBase SLAVE_RX_STATIC_REPAIR_STATE_PG(16);
-    ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16);
-    ecmdDataBufferBase SLAVE_RX_BAD_LANE_ENC_GCRMSG_PG(16);
-
-
-    
-    const uint32_t NUM_PG_REGS=3;
-    
-    const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_static_repair_state_pg,rx_training_status_pg,rx_bad_lane_enc_gcrmsg_pg};
-    
-    
-    ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS]= {
-						    &MASTER_RX_STATIC_REPAIR_STATE_PG,
-						    &MASTER_RX_TRAINING_STATUS_PG,
-						    &MASTER_RX_BAD_LANE_ENC_GCRMSG_PG,
-					};
-     
-       
-     ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS]= {
-						    &SLAVE_RX_STATIC_REPAIR_STATE_PG,
-						    &SLAVE_RX_TRAINING_STATUS_PG,
-						    &SLAVE_RX_BAD_LANE_ENC_GCRMSG_PG,
-					};
-     
-     
-
-
-    FAPI_DBG("dump_ffdc_repair function entered \n");
-
-    // Capture MASTER Side registers 
-
-
-	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(master_chip_target ,  master_chip_interface, pg_reg_list[reg_num],  master_group,0,  *MASTER_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	} 
-
-  	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(slave_chip_target ,  slave_chip_interface, pg_reg_list[reg_num],  slave_group,0,  *SLAVE_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-
-       FAPI_SET_HWP_ERROR(rc,IO_FUNCS_REPAIR_FAIL_RC);
-    return(rc);
-}
-
-
-ReturnCode  edi_training::dump_ffdc_func(const Target&  master_chip_target, io_interface_t  master_chip_interface ,uint32_t master_group, const Target& slave_chip_target ,
-											 io_interface_t slave_chip_interface,uint32_t slave_group)
-{
-    ReturnCode rc;
-    ReturnCode lane_rc; // for logging per lane FFDC
-    
-    const fapi::Target &MASTER_TARGET=master_chip_target;
-    const fapi::Target &SLAVE_TARGET=slave_chip_target;
-    	const io_interface_t& MASTER_CHIP_INTERFACE = master_chip_interface;
-	const uint32_t& MASTER_GROUP = master_group;
-	const io_interface_t& SLAVE_CHIP_INTERFACE = slave_chip_interface;
-	const uint32_t& SLAVE_GROUP = slave_group;
-    
-    //FFDC Buffers;
-    ecmdDataBufferBase MASTER_RX_FUNC_STATE_PG(16);
-    ecmdDataBufferBase MASTER_RX_TRAINING_STATUS_PG(16);
-    
-    ecmdDataBufferBase SLAVE_RX_FUNC_STATE_PG(16);
-    ecmdDataBufferBase SLAVE_RX_TRAINING_STATUS_PG(16);
-
-
-    
-    const uint32_t NUM_PG_REGS=2;
-    
-    const GCR_sub_registers pg_reg_list[NUM_PG_REGS]={rx_func_state_pg,rx_training_status_pg};
-    
-    
-    ecmdDataBufferBase *MASTER_BUFFERS[NUM_PG_REGS]= {
-						    &MASTER_RX_FUNC_STATE_PG,
-						    &MASTER_RX_TRAINING_STATUS_PG,
-					};
-     
-       
-     ecmdDataBufferBase *SLAVE_BUFFERS[NUM_PG_REGS]= {
-						    &SLAVE_RX_FUNC_STATE_PG,
-						    &SLAVE_RX_TRAINING_STATUS_PG,
-					};
-     
-     
-
-
-    FAPI_DBG("dump_ffdc_func function entered \n");
-
-    // Capture MASTER Side registers 
-
-
-	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on MASTER side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(master_chip_target ,  master_chip_interface, pg_reg_list[reg_num],  master_group,0,  *MASTER_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	} 
-
-  	for(uint32_t reg_num=0;reg_num<NUM_PG_REGS;++reg_num){
-	    FAPI_DBG("Reading register name %s on SLAVE side",GCR_sub_reg_names[pg_reg_list[reg_num]]);
-	    rc=GCR_read(slave_chip_target ,  slave_chip_interface, pg_reg_list[reg_num],  slave_group,0,  *SLAVE_BUFFERS[reg_num]);
-	    if (rc)
-	    {
-		 FAPI_ERR("io_run_training : Error Reading %s",GCR_sub_reg_names[pg_reg_list[reg_num]]); 
-	    }
-	    // Not doing the else here on purpose.. if read on one reg fails , we want to try next and maybe the slave side if all fails
-	}
-
-       FAPI_SET_HWP_ERROR(rc,IO_FUNCS_FUNC_FAIL_RC);
-    return(rc);
-}
-
-}
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H
deleted file mode 100644
index a563e4de5..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.H
+++ /dev/null
@@ -1,195 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_funcs.H $                    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_funcs.H,v 1.17 2014/02/20 13:27:29 varkeykv Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : IO_funcs.H
-// *! TITLE                : 
-// *! DESCRIPTION          : IO training comomon functions
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Vijay S Kantanavar      Email: vijaysk@in.ibm.com      
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |varkeykv|11/17/11| Combined other header files into one common file
-//------------------------------------------------------------------------------
-
-/****************************************************************************************/
-/* IO_funcs.H                                                                           */
-/****************************************************************************************/
-#ifndef IO_funcs
-#define IO_funcs
-#include <fapi.H>
-#include "gcr_funcs.H"
-#include "io_clear_firs.H"
-
-using namespace fapi;
-	// Bus Status State
-	typedef enum {  NOT_RUNNING, SELECTED,  RUNNING,   SUCCESSFULL  ,
-        FAILED} bus_status;
-
-class edi_training {
-public:
-	
-	// Training enums for Wire test , Deskew , Eye Opt ,Repair , Functional   ---
-	typedef   enum {  WIRE_TEST ,  DESKEW ,  EYE_OPT ,  REPAIR , FUNCTIONAL
-                                           , TRAINING_TYPES} training_function;
-
-    // Selection
-	bus_status    wire_test_selected;
-	bus_status    desckew_selected;
-	bus_status    eye_opt_selected;
-	bus_status    repair_selected;
-	bus_status    functional_selected;
-
-    // Current Training States
-	bus_status    wire_test_status;
-	bus_status    desckew_status;
-	bus_status    eye_opt_status;
-	bus_status    repair_status;
-	bus_status    functional_status;
-        //Updating max cycles to suit 280ms theoretical max timeout as per Mike Spear
-	static const uint32_t      max_poll_cycles=1000;
-	static const uint32_t      increment_poll_cycles=1;
-	uint32_t endpoints_set; // How many end points have we accessed so far
-
-	bool		          rx_wderf_timeout[6];   // Summary 5 bit timout  status
-	bool		          rx_wderf_start[6];     // Summary 5 bit status
-	bool		          rx_wderf_done[6];      // Summary 5 bit done
-	bool		          rx_wderf_failed[6];    // Summary 5 bit failed
-
-	// Constructor Initializes default states for status variables
-    edi_training( bus_status wire_test=SELECTED,bus_status deskew=SELECTED,bus_status eye_opt=SELECTED,bus_status repair=SELECTED,bus_status functional=SELECTED)
-    {
-        wire_test_selected     =       wire_test;
-        desckew_selected       =       deskew;
-        eye_opt_selected       =       eye_opt;
-        repair_selected        =       repair;
-        functional_selected    =       functional;
-
-        wire_test_status        =     wire_test;
-        desckew_status          =     deskew;
-        eye_opt_status          =     eye_opt;
-        repair_status           =     repair;
-        functional_status       =     functional;
-        
-        for(int i=0;i<6;++i)
-        {
-                rx_wderf_timeout[i]=false;
-                rx_wderf_start[i]=false;
-                rx_wderf_done[i]=false;
-                rx_wderf_failed[i]=false;
-        }
-        endpoints_set=0; // reset this for multi endpoint pair runs
-    } 
-	
-	//! Destructor
-	~edi_training() {
-        } 
-
-    //  Training Functions
-    // Run Wirtest,Deskew,Repair and Functional mode on selected target(endpoint) pair
-    ReturnCode  run_training(const Target& master_target,  io_interface_t
-                             master_interface,uint32_t master_group,const Target&  slave_target,
-			     io_interface_t slave_interface,uint32_t slave_group);
-    // Runs the selected training function(s)
-    ReturnCode  run_training_functions(const Target&  target,
-                                       io_interface_t interface,uint32_t current_group);
-   // Checks the status of the training selected function(s)
-    ReturnCode  training_function_status(const Target& master_target,
-                                         io_interface_t master_interface,uint32_t master_group,
-                                         const Target& slave_target,
-                                         io_interface_t slave_interface,uint32_t slave_group
-                                          );
-
-    // First Fail Data Capture Routines
-    // Wire Test First Fail Data Capture
-    ReturnCode dump_ffdc_wiretest(const Target&  master_chip_target,
-                                  io_interface_t  master_chip_interface ,
-				  uint32_t master_group,
-                                  const Target& slave_chip_target ,
-                                  io_interface_t slave_chip_interface,
-				  uint32_t slave_group
-                                  );
-    
-      // First Fail Data Capture Routines
-    // Deskew First Fail Data Capture
-    ReturnCode dump_ffdc_deskew(const Target&  master_chip_target,
-                                  io_interface_t  master_chip_interface ,
-				  uint32_t master_group,
-                                  const Target& slave_chip_target ,
-                                  io_interface_t slave_chip_interface,
-				  uint32_t slave_group
-                                  );
-    
-    // Eye opt First Fail Data Capture
-    ReturnCode dump_ffdc_eyeopt(const Target&  master_chip_target,
-                                  io_interface_t  master_chip_interface ,
-				  uint32_t master_group,
-                                  const Target& slave_chip_target ,
-                                  io_interface_t slave_chip_interface,
-				  uint32_t slave_group
-                                  );
-    
-        // Repair First Fail Data Capture
-    ReturnCode dump_ffdc_repair(const Target&  master_chip_target,
-                                  io_interface_t  master_chip_interface ,
-				  uint32_t master_group,
-                                  const Target& slave_chip_target ,
-                                  io_interface_t slave_chip_interface,
-				  uint32_t slave_group
-                                  );
-     // FUnc mode First Fail Data Capture
-    ReturnCode dump_ffdc_func(const Target&  master_chip_target,
-                                  io_interface_t  master_chip_interface ,
-				  uint32_t master_group,
-                                  const Target& slave_chip_target ,
-                                  io_interface_t slave_chip_interface,
-				  uint32_t slave_group
-                                  );
-
-    // Utility functions
-    // Determines if target chip is a Master (reads rx_master_mode bit)
-    ReturnCode isChipMaster(const Target& target, io_interface_t interface,uint32_t current_group,
-                            bool& master_chip_found
-                            );
-        
-};
-
-
-
-
-
-
-/* functions */
-#endif
diff --git a/src/usr/hwpf/hwp/bus_training/io_hwp_common_ipl_and_rt.mk b/src/usr/hwpf/hwp/bus_training/io_hwp_common_ipl_and_rt.mk
deleted file mode 100644
index d54f4f551..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_hwp_common_ipl_and_rt.mk
+++ /dev/null
@@ -1,41 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/bus_training/io_hwp_common_ipl_and_rt.mk $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2014
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-# ROOTPATH must be defined before including this file.
-
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-
-OBJS += gcr_funcs.o
-OBJS += io_power_down_lanes.o
-OBJS += io_read_erepair.o
-OBJS += io_clear_firs.o
-OBJS += io_fir_isolation.o
-OBJS += erepairAccessorHwpFuncs.o
-OBJS += erepairGetFailedLanesHwp.o
-OBJS += erepairSetFailedLanesHwp.o
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_post_trainadv.C b/src/usr/hwpf/hwp/bus_training/io_post_trainadv.C
deleted file mode 100644
index bf4ce15b5..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_post_trainadv.C
+++ /dev/null
@@ -1,60 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_post_trainadv.C $            */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_post_trainadv.C,v 1.2 2013/11/08 14:23:07 mjjones Exp $
-//*!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-//*!***************************************************************************
-// *! FILENAME             : io_post_trainadv.C
-// *! TITLE                :
-// *! DESCRIPTION          : The purpose of this code is to allow for future post-training activity such as Host-based characterization
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-//*!***************************************************************************
-// CHANGE HISTORY:
-//-----------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|-------------------------------------------------
-//   1.1   |thomsen |05/10/13| Initial empty shell
-//   1.2   |mjjones |11/07/13| Cleanup
-//-----------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "io_post_trainadv.H"
-
-extern "C"
-{
-
-fapi::ReturnCode io_post_trainadv(const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    return rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/bus_training/io_post_trainadv.H b/src/usr/hwpf/hwp/bus_training/io_post_trainadv.H
deleted file mode 100644
index 10d4fdf0a..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_post_trainadv.H
+++ /dev/null
@@ -1,49 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_post_trainadv.H $            */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_post_trainadv.H,v 1.2 2013/11/08 14:22:27 mjjones Exp $
-#ifndef IO_POST_TRAINADV_H_
-#define IO_POST_TRAINADV_H_
-
-#include <fapi.H>
-
-/**
- * io_post_trainadv HWP func pointer typedef
- */
-typedef fapi::ReturnCode (*io_post_trainadv_FP_t)(const fapi::Target &);
-
-extern "C"
-{
-
-/**
- * @brief Debug routine for IO Characterization
- *
- * @param[in]  i_target  Reference to bus endpoint target. Type is one of:
- *                       XBUS_ENDPOINT, ABUS_ENDPOINT,
- *                       MCS_CHIPLET, MEMBUF_CHIP
- * @return ReturnCode
- */
-fapi::ReturnCode io_post_trainadv(const fapi::Target & i_target);
-
-} // extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
deleted file mode 100644
index 1650e326c..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
+++ /dev/null
@@ -1,222 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C $         */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_power_down_lanes.C,v 1.14 2014/09/29 23:22:56 garyp Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_power_down_lanes.C
-// *! TITLE                : 
-// *! DESCRIPTION          : Power down bad lanes
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Steffen, Chris           Email: cwsteffen@us.ibm.com
-// *! BACKUP NAME          : Peterson, Gary           Email: garyp@us.ibm.com      
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY: 
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |varkeykv||Initial check in 
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "io_power_down_lanes.H"
-#include "gcr_funcs.H"
-
-extern "C" {
-
-    using namespace fapi;
-
-    /*
-    This function will perform power down of lanes on any IO target: MEMBUF, MCS ,XBUS, or ABUS
-    For rx_lanes, it will also set rx_wt_lane_disabled
-    For a bad lane, it will be called twice:
-          once with target set to the rx target, rx_lanes populated, and tx_lanes empty
-          once with target set to the tx target, tx_lanes populated, and rx_lanes empty
-    */
-
-    ReturnCode io_power_down_lanes(const Target& target, const std::vector<uint8_t> &tx_lanes, const std::vector<uint8_t> &rx_lanes) {
-	ReturnCode rc;
-	ecmdDataBufferBase data(16);
-	ecmdDataBufferBase mask(16);
-	ecmdDataBufferBase mode_reg(16);
-	uint8_t lane=0;
-	bool msbswap=false;
-	const uint8_t xbus_lanes_per_group=20;
-	uint8_t end_lane=0;
-
-	io_interface_t interface=CP_IOMC0_P0; // Since G
-	uint32_t rc_ecmd=0;
-	uint8_t clock_group=0;
-	uint8_t start_group=0;
-
-	do {
-	    // rx_lane_pdwn, tx_lane_pdwn, and  rx_wt_lane_disabled are all bit 0; and this routine is setting all 3, so we set up data and mask once
-	    rc_ecmd=mask.flushTo1();
-	    if(rc_ecmd) {
-		FAPI_ERR("io_power_down_lanes error occured while flushing bits for mask");
-		rc.setEcmdError(rc_ecmd);
-		break;
-	    }
-
-	    rc_ecmd=data.flushTo0();
-	    if(rc_ecmd) {
-		FAPI_ERR("io_power_down_lanes error occured while flushing bits for data");
-		rc.setEcmdError(rc_ecmd);
-		break;
-	    }
-
-	    rc_ecmd=data.setBit(0);
-	    if(rc_ecmd) {
-		FAPI_ERR("io_power_down_lanes error occured while clearing bits for data");
-		rc.setEcmdError(rc_ecmd);
-		break;
-	    }
-
-	    // Check which type of bus this is and do setup needed
-	    fapi::TargetType l_type= target.getType();
-	    switch (l_type) {
-		case fapi::TARGET_TYPE_ABUS_ENDPOINT:
-		    start_group=0;
-		    interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
-		    break;
-		case fapi::TARGET_TYPE_XBUS_ENDPOINT:
-		    start_group=0;
-		    interface=CP_FABRIC_X0; // base scom for X bus
-		    break;
-		case fapi::TARGET_TYPE_MCS_CHIPLET:
-		    start_group=3;
-		    interface=CP_IOMC0_P0; // base scom for MC bus
-		    break;
-		case fapi::TARGET_TYPE_MEMBUF_CHIP:
-		    start_group=0;
-		    interface=CEN_DMI; // base scom Centaur chip
-		    break;
-		default:
-		    FAPI_ERR("Invalid io_power_down_lanes HWP invocation");
-  		    const fapi::Target& TARGET = target;
-		    FAPI_SET_HWP_ERROR(rc, IO_POWER_DOWN_LANES_INVALID_INVOCATION_RC);
-		    break;
-	    }
-	    if (rc) {
-		break;
-	    }
-
-	    FAPI_INF("Power down IO lanes\n");
-
-	    rc = GCR_read( target, interface, tx_mode_pg, start_group, 0, mode_reg);
-	    if(rc) {
-		FAPI_ERR("GCR_read returned an error while reading tx_mode_pg");
-		break;
-	    }
-
-	    if(mode_reg.isBitSet(5)) {
-		FAPI_DBG("TX MSB-LSB SWAP MODE ON on this target %d \n",tx_end_lane_id);
-		msbswap=true;
-	    }
-
-	    //TX Lanes power down; target must be the tx
-	    for(uint8_t i=0;i<tx_lanes.size();++i) {
-		lane=tx_lanes[i];
-		//For X bus, adjust the lane and clock group
-		if(interface==CP_FABRIC_X0) {
-		    clock_group=start_group;
-		    while(lane>(xbus_lanes_per_group-1)) {
-			lane=lane-xbus_lanes_per_group;
-			clock_group++;
-		    }
-		}
-		else {
-		    clock_group=start_group;
-		    // MSBLSB SWAP condition can be there in MC or A
-		    if(msbswap) {
-			// We can read out tx_end_lane_id now for swap correction
-			rc = GCR_read( target, interface, tx_id3_pg, clock_group, 0, mode_reg);
-			if(rc) {
-			    FAPI_ERR("GCR_read returned an error during call to read tx_id3_pg");
-			    break;
-			}
-
-			rc_ecmd=mode_reg.extract(&end_lane,9,7);
-			if(rc_ecmd) {
-			    rc.setEcmdError(rc_ecmd);
-			    break;
-			}
-			end_lane=end_lane>>1;// move left aligned extract by 1
-			FAPI_DBG("END lane id is %d\n",end_lane);
-			lane=end_lane-tx_lanes[i]; // GFW VPD does not know about MSBSWAP , this adjusts for swapping
-		    }
-		}
-
-		//Power down this lane
-		rc = GCR_write( target, interface, tx_mode_pl, clock_group, lane, data, mask );
-		if(rc) {
-		    FAPI_ERR("GCR_write returned an error  while writing tx_mode_pl");
-		    break;
-		}
-	    }
-
-	    if (rc) { //break out of larger while loop
-		break;
-	    }
-
-	    // Process RX lane powerdown; target must be the rx
-            for(uint8_t i=0;i<rx_lanes.size();++i) {
-		lane=rx_lanes[i];
-
-		//For X bus, adjust the lane and clock group
-		if(interface==CP_FABRIC_X0) {
-		    clock_group=start_group;
-		    while(lane>(xbus_lanes_per_group-1)) {
-			lane=lane-xbus_lanes_per_group;
-			clock_group++;
-		    }
-		}
-		else {
-		    clock_group=start_group;
-		}
-
-		//Power down this lane
-		rc = GCR_write( target, interface, rx_mode_pl, clock_group, lane, data, mask );
-		if(rc) {
-		    FAPI_ERR("GCR_write returned an error while writing rx_mode_pl");
-		    break;
-		}
-
-		// Set rx_wt_lane_disabled for this lane; see SW244284, SW280992
-		rc = GCR_write( target, interface,  rx_wt_status_pl, clock_group, lane, data, mask );
-		if(rc) {
-		    FAPI_ERR("GCR_write returned an error while writing rx_wt_status_pl");
-		    break;
-		}
-	    }
-	} while(0); // run loop only once
-	return rc;
-    } //end io_power_down_lanes
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H
deleted file mode 100644
index 36953fe8c..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H
+++ /dev/null
@@ -1,54 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_power_down_lanes.H $         */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_power_down_lanes.H,v 1.5 2014/03/06 11:12:24 varkeykv Exp $
-#ifndef IO_POWER_DOWN_LANES_H_
-#define IO_POWER_DOWN_LANES_H_
-
-
-#include <fapi.H> 
-
-/**
- * @brief IO Power down lanes
- * The user needs to pass in Lane numbers that needs to be powered down
- **/
-typedef fapi::ReturnCode (*io_power_down_lanes_FP_t)(const fapi::Target &target,const std::vector<uint8_t> &tx_lanes,const std::vector<uint8_t> &rx_lanes);
-
-extern "C"
-{
-
-/**
- * @brief IO read erepair function 
- *
- * @param[in] target could P8 MCS ,Centaur ( MEMBUF )  , p8 XBUS or p8 ABUS
- *
- * rx lanes and tx lanes -- user needs to pass in lanes that should be powered down 
- * 
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode io_power_down_lanes(const fapi::Target &target,const std::vector<uint8_t> &tx_lanes,const std::vector<uint8_t> &rx_lanes);
-
-} // extern "C"
-
-#endif // IO_POWER_DOWN_LANES_H_
diff --git a/src/usr/hwpf/hwp/bus_training/io_pre_trainadv.C b/src/usr/hwpf/hwp/bus_training/io_pre_trainadv.C
deleted file mode 100644
index 711d221c6..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_pre_trainadv.C
+++ /dev/null
@@ -1,60 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_pre_trainadv.C $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_pre_trainadv.C,v 1.2 2013/11/08 13:45:41 mjjones Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_pre_trainadv.C
-// *! TITLE                :
-// *! DESCRIPTION          : The purpose of this code is to allow for future pre-training activity such as Host-based characterization
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.1   |thomsen |05/10/13| Initial empty shell
-//   1.2   |mjjones |11/07/13| Cleanup
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "io_pre_trainadv.H"
-
-extern "C"
-{
-
-fapi::ReturnCode io_pre_trainadv(const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    return rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/bus_training/io_pre_trainadv.H b/src/usr/hwpf/hwp/bus_training/io_pre_trainadv.H
deleted file mode 100644
index 508162800..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_pre_trainadv.H
+++ /dev/null
@@ -1,49 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_pre_trainadv.H $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_pre_trainadv.H,v 1.2 2013/11/08 14:22:11 mjjones Exp $
-#ifndef IO_PRE_TRAINADV_H_
-#define IO_PRE_TRAINADV_H_
-
-#include <fapi.H>
-
-/**
- * io_pre_trainadv HWP func pointer typedef
- */
-typedef fapi::ReturnCode (*io_pre_trainadv_FP_t)(const fapi::Target &);
-
-extern "C"
-{
-
-/**
- * @brief Debug routine for IO Characterization
- * 
- * @param[in]  i_target  Reference to bus endpoint target. Type is one of:
- *                       XBUS_ENDPOINT, ABUS_ENDPOINT,
- *                       MCS_CHIPLET, MEMBUF_CHIP
- * @return ReturnCode
- */
-fapi::ReturnCode io_pre_trainadv(const fapi::Target & i_target);
-
-} // extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/bus_training/io_read_erepair.C b/src/usr/hwpf/hwp/bus_training/io_read_erepair.C
deleted file mode 100644
index 4889426e0..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_read_erepair.C
+++ /dev/null
@@ -1,194 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_read_erepair.C $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_read_erepair.C,v 1.12 2014/04/17 15:58:23 steffen Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_read_erepair.C
-// *! TITLE                :
-// *! DESCRIPTION          : Read e-repair data
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:   | Comment:
-// --------|--------|---------|--------------------------------------------------
-//   1.0   |varkeykv|21-Jan-13|Initial check in
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "io_read_erepair.H"
-#include "gcr_funcs.H"
-
-extern "C" {
-
-
-using namespace fapi;
-
-
-//! Read repair values from VPD into the HW
-/*
- This function will perform erepair for one IO type target  -- eithe MCS or XBUS or ABUS
-* Tx and Rx lanes vector is filled in by the HWP with bad lane numbers
-*/
-ReturnCode io_read_erepair(const Target& target,std::vector<uint8_t> &rx_lanes)
-{
-	ReturnCode rc;
-	ecmdDataBufferBase data_one(16);
-	ecmdDataBufferBase mask(16);
-	uint8_t lane=0;
-
-	io_interface_t interface=CP_IOMC0_P0; // Since G
-	uint32_t rc_ecmd=0;
-	uint8_t start_group=0;
-	uint8_t end_group=0;
-        const fapi::Target &TARGET=target;
-		rc_ecmd=mask.flushTo1();
-		if(rc_ecmd)
-		{
-			rc.setEcmdError(rc_ecmd);
-			return(rc);
-		}
-
-		// Check which type of bus this is and do setup needed
-		fapi::TargetType l_type = target.getType();
-        switch (l_type)
-        {
-            case fapi::TARGET_TYPE_ABUS_ENDPOINT:
-				start_group=0;
-				end_group=0;
-				interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
-				break;
-			case fapi::TARGET_TYPE_XBUS_ENDPOINT:
-				start_group=0;
-				end_group=0;
-				interface=CP_FABRIC_X0; // base scom for X bus
-				break;
-			case fapi::TARGET_TYPE_MCS_CHIPLET:
-				start_group=3;
-				end_group=3;
-				interface=CP_IOMC0_P0; // base scom for MC bus
-				break;
-			case fapi::TARGET_TYPE_MEMBUF_CHIP:
-				start_group=0;
-				end_group=0;
-				interface=CEN_DMI; // base scom Centaur chip
-				break;
-			default:
-				FAPI_ERR("Invalid io_read_erepair HWP invocation");
-		        FAPI_SET_HWP_ERROR(rc,IO_READ_EREPAIR_INVALID_INVOCATION_RC);
-				break;
-		}
-		if (rc)
-		{
-			return(rc);
-		}
-
-		FAPI_INF("Reading erepair data \n");
-
-		for(uint8_t clock_group=start_group;clock_group<=end_group;++clock_group)
-		{
-			// This is only for X bus ..where multi groups are translated to consecutive lane numbers
-			if(interface==CP_FABRIC_X0)
-			{
-				switch (clock_group)
-				{
-					case 0:
-						lane=0;
-						break;
-					case 1:
-						lane=20;
-						break;
-					case 2:
-						lane=40;
-						break;
-					case 3:
-						lane=60;
-						break;
-					default:
-						//don't need to do anything?
-						FAPI_ERR("io_read_erepair has a non-known clock groupd");
-						break;
-				}
-			}
-
-			//Collect the RX bad lanes
-			rc_ecmd|=data_one.flushTo0();
-
-			if(rc_ecmd)
-			{
-				FAPI_ERR("io_read_erepair hit an error while flushing data");
-				rc.setEcmdError(rc_ecmd);
-				return(rc);
-			}
-
-			rc = GCR_read( target, interface,  rx_bad_lane_enc_gcrmsg_pg, clock_group,  0,  data_one);
-			if(rc)
-			{
-				FAPI_ERR("io_read_erepair hit an error while writing rx_bad_lane_enc_gcrmsg_pg");
-				return(rc);
-			}
-
-			// RX lane records
-			// Set the RX bad lanes in the RX vector
-			uint8_t status=0;
-			
-			// Get first bad lane
-			data_one.extract(&status,14,2);
-			status=status>>6;
-			FAPI_DBG("Bad lane status is %d",status);
-			
-			if(status!=0){
-			  if(status>=1){
-			      data_one.extract(&lane,0,7);
-			      lane=lane>>1;
-			      FAPI_DBG("First bad lane is %d",lane);
-			      rx_lanes.push_back(lane); // 0 to 15 bad lanes
-			  }
-			  // Get second bad lane if any
-			  if(status>=2){
-			      data_one.extract(&lane,7,7);
-			      lane=lane>>1;
-			      FAPI_DBG("Second bad lane is %d",lane);
-			      rx_lanes.push_back(lane); // 16 to 31 bad lanes
-			  }
-			}
-			else{
-			  // No bad lanes to report
-			   FAPI_DBG("No bad lane to report!!");
-			}
-
-		}
-	return rc;
-}
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_read_erepair.H b/src/usr/hwpf/hwp/bus_training/io_read_erepair.H
deleted file mode 100644
index dd763ae59..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_read_erepair.H
+++ /dev/null
@@ -1,54 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_read_erepair.H $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_read_erepair.H,v 1.4 2013/02/05 06:06:06 varkeykv Exp $
-#ifndef IO_READ_EREPAIR_H_
-#define IO_READ_EREPAIR_H_
-
-#include <fapi.H>
-
-/**
- * @brief IO read e repair function
- * the  rx vectors will return to the caller(PRD or e-repair)the bad lane numbers on this endpoint 
- */
-typedef fapi::ReturnCode (*io_read_erepair_FP_t)(const fapi::Target &target,std::vector<uint8_t> &rx_lanes);
-
-extern "C"
-{
-
-/**
- * @brief IO read erepair function 
- *
- * @param[in] target could P8 MCS ,Centaur ( MEMBUF )  , p8 XBUS or p8 ABUS
- *
- * rx lanes will return bad lane data to the caller on this particular bus/endpoint
- * e-repair will duplicate this to TX vpd records as well on the other connected side 
- * 
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode io_read_erepair(const fapi::Target &target,std::vector<uint8_t> &rx_lanes);
-
-} // extern "C"
-
-#endif // IO_READ_EREPAIR_H_
diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
deleted file mode 100644
index 9407d912e..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
+++ /dev/null
@@ -1,218 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_restore_erepair.C $          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_restore_erepair.C,v 1.19 2014/04/18 21:25:49 steffen Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_restore_erepair.C
-// *! TITLE                :
-// *! DESCRIPTION          : Restore e-repair data
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK
-//------------------------------------------------------------------------------
-
-
-#include <fapi.H>
-#include "io_restore_erepair.H"
-#include "gcr_funcs.H"
-#include "io_power_down_lanes.H"
-#include <erepairAccessorHwpFuncs.H>
-
-extern "C" {
-
-
-using namespace fapi;
-
-
-//! Read repair values from VPD into the HW
-/*
- This function will perform erepair for one IO type target  -- eithe MCS or XBUS or ABUS
- * In Cronus the tx_lanes and rx_lanes vectors should be passed empty so we will use the accessor provided data instead
- * This is due to a MFG FW requirement that needed to pass in bad lanes as args instead of via VPD
- * Note that power down of lanes is done by a seperate HWP called io_power_down_lanes
- * Its up to the caller to call that separately to power down a lane
-*/
-ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lanes,std::vector<uint8_t> &rx_lanes)
-{
-  ReturnCode rc;
-  ecmdDataBufferBase data_one(16);
-  ecmdDataBufferBase data_two(16);
-  ecmdDataBufferBase mode_reg(16);
-  ecmdDataBufferBase mask(16);
-  uint8_t lane=0;
-  bool lane_valid=false;
-
-  io_interface_t interface=CP_IOMC0_P0; // Since G
-  uint32_t rc_ecmd=0;
-  uint8_t start_group=0;
-  uint8_t end_group=0;
-
-    rc_ecmd=mask.flushTo1();
-    if(rc_ecmd)
-    {
-        rc.setEcmdError(rc_ecmd);
-        return(rc);
-    }
-
-  // Check which type of bus this is and do setup needed
-  if(target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) {
-    start_group=0;
-    end_group=0;
-    interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
-  }
-  else if(target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT ) {
-    start_group=0;
-    end_group=3;
-    interface=CP_FABRIC_X0; // base scom for X bus
-  }
-  else if(target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET){
-    start_group=3;
-    end_group=3;
-    interface=CP_IOMC0_P0; // base scom for MC bus
-  }
-  else if(target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP){
-    start_group=0;
-    end_group=0;
-    interface=CEN_DMI; // base scom Centaur chip
-  }
-  else{
-      FAPI_ERR("Invalid io_restore_erepair HWP invocation");
-      const fapi::Target &TARGET = target;
-      FAPI_SET_HWP_ERROR(rc, IO_RESTORE_EREPAIR_INVALID_INVOCATION_RC);
-      return(rc);
-  }
-  // Use the accessor to fetch VPD data for this particular target instance
-  // -- New MFG requirement .. GFW Will pass in lanes as args
-  // And we still need to run this in Cronus
-  // Since the hack was not made in the accessor to detect this,
-  // Provision was made to detect if arguments passed in are empty.
-  // If so then the accessor is called to determine from VPD data directly .
-
-  // This is specially for Cronus/Lab
-  if(tx_lanes.size()==0 && rx_lanes.size()==0){
-   // rc=erepairGetFailedLanes(target,tx_lanes,rx_lanes);
-    //FAPI_EXEC_HWP(rc,erepairGetFailedLanesHwp,target,tx_lanes,rx_lanes);
-    if(!rc.ok()){
-      FAPI_ERR("Accessor HWP has returned a fail");
-      return rc;
-    }
-  }
-
-   FAPI_INF("Restoring erepair data \n");
-
-    for(uint8_t clock_group=start_group;clock_group<=end_group;++clock_group){
-      rc_ecmd|=data_one.flushTo0();
-      rc_ecmd|=data_two.flushTo0();
-
-      if(rc_ecmd)
-      {
-          rc.setEcmdError(rc_ecmd);
-          return(rc);
-      }
-
-      // Read in original data
-
-      // Read in values for RMW
-      rc = GCR_read( target,interface,rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one);
-      if(rc){return rc;}
-      rc = GCR_read( target,interface,rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two);
-      if(rc){return rc;}
-
-      // RX lane records
-      // Set the RX bad lanes in the buffer
-      for(uint8_t i=0;i<rx_lanes.size();++i){
-
-            if(interface==CP_FABRIC_X0){
-                  if(clock_group==0 && rx_lanes[i]<20){
-                    lane=rx_lanes[i];
-                    lane_valid=true;
-                  }
-                  else if(clock_group==1 && (rx_lanes[i]>19 && rx_lanes[i]<40)){
-                    lane=rx_lanes[i]-20;
-                    lane_valid=true;
-                  }
-                  else if(clock_group==2 && (rx_lanes[i]>39 && rx_lanes[i]<60)){
-                    lane=rx_lanes[i]-40;
-                    lane_valid=true;
-                  }
-                  else if(clock_group==3 && (rx_lanes[i]>59 && rx_lanes[i]<80) ){
-                    lane=rx_lanes[i]-60;
-                    lane_valid=true;
-                  }
-                  else{
-                    lane_valid=false;
-                  }
-            }
-            else{
-              lane=rx_lanes[i];
-              lane_valid=true;
-            }
-          if (lane < 16 && lane_valid) {
-             rc_ecmd = data_one.setBit(lane);
-             if(rc_ecmd)
-             {
-                 rc.setEcmdError(rc_ecmd);
-                 return(rc);
-             }
-          }
-          else if(lane>=16 && lane_valid) {
-             rc_ecmd = data_two.setBit(lane-16);
-             if(rc_ecmd)
-             {
-                 rc.setEcmdError(rc_ecmd);
-                 return(rc);
-             }
-          }
-      }
-       FAPI_DBG("#2 Corrected RX lane is  %d\n",lane);
-      //Now write the bad lanes in one shot on the slave side RX
-      if(!data_one.isBitClear(0,16)){
-        rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one,mask );
-        if(rc){return rc;}
-      }
-       if(!data_two.isBitClear(0,16)){
-        //Now write the bad lanes in one shot on the slave side RX
-        rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two,mask);
-        if(rc){return rc;}
-       }
-    }
-    FAPI_EXEC_HWP(rc, io_power_down_lanes,target,tx_lanes,rx_lanes);
-  return rc;
-}
-
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H
deleted file mode 100644
index 9c501dab1..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.H
+++ /dev/null
@@ -1,58 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_restore_erepair.H $          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_restore_erepair.H,v 1.9 2014/03/05 12:01:04 varkeykv Exp $
-#ifndef IO_RESTORE_EREPAIR_H_
-#define IO_RESTORE_EREPAIR_H_
-
-
-#include <fapi.H>
-
-/**
- * @brief IO restore e repair function
- * In Cronus the tx_lanes and rx_lanes vectors should be passed empty so we will use the accessor provided data instead 
- * This is due to a MFG FW requirement that needed to pass in bad lanes as args instead of via VPD
- * Note that power down of lanes is done by a seperate HWP called io_power_down_lanes
- * Its up to the caller to call that separately to power down a lane if required
- *
- */
-typedef fapi::ReturnCode (*io_restore_erepair_FP_t)(const fapi::Target &target,std::vector<uint8_t> &tx_lanes,std::vector<uint8_t> &rx_lanes);
-
-extern "C"
-{
-
-/**
- * @brief IO restore erepair function 
- *
- * @param[in] target could P8 MCS ,Centaur ( MEMBUF )  , p8 XBUS or p8 ABUS
- *
- * rx lanes and tx lanes should be passed in by the caller based on VPD data for bad lanes on this target endpoint.
- * Invalidation and other checks should be done prior to passing in these parms
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode io_restore_erepair(const fapi::Target &target,std::vector<uint8_t> &tx_lanes,std::vector<uint8_t> &rx_lanes);
-
-} // extern "C"
-
-#endif // IO_RESTORE_EREPAIR_H_
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C
deleted file mode 100644
index 8366c1bc4..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.C
+++ /dev/null
@@ -1,1282 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_run_training.C $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_run_training.C,v 1.66 2015/05/14 21:03:37 jmcgill Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : io_run_training.C
-// *! TITLE                : 
-// *! DESCRIPTION          : IO Wiretest,Deskew ,Eye Opt training procedure
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Janani Swaminathan      Email:  jaswamin@in.ibm.com     
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//  1.27   |jaswamin|01/28/13|Changed fatal errors to warning prints to allow training to continue
-//   1.0   |varkeykv|09/27/11|Initial check in . Have to modify targets once bus target is defined and available.Not tested in any way other than in unit SIM IOTK
-//   1.1   |varkeykv|11/16/11|Fixed header files & dependencies
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include "io_run_training.H"
-#include "io_funcs.H"
-#include <p8_scom_addresses.H>
-#include "proc_a_x_pci_dmi_pll_utils.H"
-
-
-
-extern "C" {
-    using namespace fapi;
-
-
-
-    ReturnCode io_training_set_pll_post_wiretest(const Target& target){
-        ReturnCode rc;
-        fapi::Target parent_target;
-        uint8_t chip_unit = 0;
-
-        FAPI_DBG("Running PLL updation code");
-
-
-
-        // This is a DMI/MC bus
-        if (target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
-        {
-            FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
-
-            // Lets get chip unit pos , used for PLL table lookup
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,
-                    &target,
-                    chip_unit);
-
-            if (rc)
-            {
-                FAPI_ERR("Error retreiving MCS chiplet number!");
-                return rc;
-            }
-
-            // obtain parent chip target needed for ring manipulation
-            rc = fapiGetParentChip(target, parent_target);
-            if (rc)
-            {
-                FAPI_ERR("Error from fapiGetParentChip");
-                return(rc);
-            }
-
-            // install PLL config (adjust PFD360)
-            rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
-                                                RING_ADDRESS_PROC_PB_BNDY_DMIPLL,
-                                                RING_OP_MOD_PFD360,
-                                                static_cast<p8_pll_utils_bus_id>(chip_unit),
-                                                true);
-            if (rc)
-            {
-                FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                return(rc);
-            }
-
-
-        }
-        else if (target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)
-        {
-            FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
-
-            // install PLL config (adjust PFD360)
-            rc = proc_a_x_pci_dmi_pll_scan_bndy(target,
-                                                RING_ADDRESS_MEMB_TP_BNDY_PLL,
-                                                RING_OP_MOD_PFD360,
-                                                RING_BUS_ID_0,
-                                                true);
-            if (rc)
-            {
-                FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                return(rc);
-            }
-
-
-        }
-        //This is an X Bus
-        else if (target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)
-        {
-            FAPI_DBG("This is a X Bus training invocation");
-        }
-        //This is an A Bus
-        else if (target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)
-        {
-            FAPI_DBG("This is an A Bus training invocation");
-
-            // Lets get chip unit pos , used for PLL table lookup 
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,
-                    &target,
-                    chip_unit);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error retreiving Abus chiplet number!");
-                return rc;
-            }
-
-            // obtain parent chip target needed for ring manipulation
-            rc = fapiGetParentChip(target, parent_target);
-            if (rc)
-            {
-                FAPI_ERR("Error from fapiGetParentChip");
-                return(rc);
-            }
-
-            // install PLL config (adjust PFD360)
-            rc = proc_a_x_pci_dmi_pll_scan_bndy(parent_target,
-                                                RING_ADDRESS_PROC_AB_BNDY_PLL,
-                                                RING_OP_MOD_PFD360,
-                                                static_cast<p8_pll_utils_bus_id>(chip_unit),
-                                                true);
-            if (rc)
-            {
-                FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                return(rc);
-            }
-
-        }
-        else
-        {
-            FAPI_ERR("Invalid target passed to PLL Update code.. target does not belong to DMI/X/A instances");
-            const fapi::Target &TARGET = target;
-            FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_SET_PLL_INVALID_INVOCATION_RC);
-        }
-        return rc;
-    }
-
-    // For clearing the FIR mask , used by io run training 
-    ReturnCode clear_fir_mask_reg(const Target &i_target,fir_io_interface_t i_chip_interface){
-
-        ReturnCode rc;
-        uint32_t rc_ecmd = 0;
-        uint8_t chip_unit = 0;
-        uint8_t link_fir_unmask_data = 0xFF;
-        ecmdDataBufferBase data(64);
-        FAPI_INF("io_run_training:In the Clear FIR MASK register function ");
-
-        do
-        {
-            // initialize mask to all 1s
-            rc_ecmd |= data.invert();
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%X setting up FIR mask data buffer",
-                        rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            // set FIR mask appropriately based on interface type / link being trained
-            if ((i_chip_interface == FIR_CP_FABRIC_A0) ||
-                    (i_chip_interface == FIR_CP_IOMC0_P0))
-            {
-                rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,
-                        &i_target,
-                        chip_unit);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error retreiving chiplet number!");
-                    break;
-                }
-
-                // adjust for DMI number
-                if (i_chip_interface == FIR_CP_IOMC0_P0)
-                {
-                    chip_unit = chip_unit % 4;
-                    // BUS ID Remapped to linear by John Rell so commenting this out 
-                    link_fir_unmask_data = 0x87; // as per Gary via SW245014
-                }
-                // adjust for ABUS number
-                else
-                {
-                    chip_unit = chip_unit + 1;
-                    link_fir_unmask_data = 0x87;// as per Gary via SW245014, leave at this value 
-                }
-            }
-
-            // SW228820 , for Xbus all data goes into BUS0 fields regardless of instance
-            else if ((i_chip_interface == FIR_CEN_DMI) ||
-                    (i_chip_interface == FIR_CP_FABRIC_X0))
-            {
-                chip_unit = 0;
-                if (i_chip_interface == FIR_CEN_DMI)
-                {
-                    //link_fir_unmask_data = 0x8F;
-                    link_fir_unmask_data = 0x87; // as per Gary via SW245014
-                }
-                else
-                {
-                    //link_fir_unmask_data = 0x87;
-                    link_fir_unmask_data = 0x97; // as per Gary via SW245014
-                }
-            }
-
-            rc_ecmd |= data.insert(link_fir_unmask_data,
-                    8+(8*chip_unit),
-                    8);
-
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%X setting up FIR mask data buffer",
-                        rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            // use FIR AND mask register to un-mask selected bits
-            rc = fapiPutScom(i_target, fir_clear_mask_reg_addr[i_chip_interface], data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing FIR mask register (=%08X)!",
-                        fir_clear_mask_reg_addr[i_chip_interface]);
-                break;
-            }
-
-        } while(0);
-
-        return(rc);
-    }
-
-    // For clearing out spare deployed summary bit , in case of false HW triggers on known bad lanes
-    // io_clear_firs only clear out lower level regs, not the summary FIR 
-    ReturnCode clear_fir_summary_reg(const Target &i_target,fir_io_interface_t i_chip_interface){
-
-        ReturnCode rc;
-        uint32_t rc_ecmd = 0;
-        uint8_t chip_unit = 0;
-        ecmdDataBufferBase data(64);
-        uint64_t scom_address64=0;
-        ecmdDataBufferBase temp(64);
-
-        FAPI_INF("io_run_training:In the Clear FIR MASK register function ");
-
-        do
-        {
-
-            // set FIR mask appropriately based on interface type / link being trained
-            if ((i_chip_interface == FIR_CP_FABRIC_A0) ||
-                    (i_chip_interface == FIR_CP_IOMC0_P0))
-            {
-                rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,
-                        &i_target,
-                        chip_unit);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error retreiving chiplet number!");
-                    break;
-                }
-
-                // adjust for DMI number
-                if (i_chip_interface == FIR_CP_IOMC0_P0)
-                {
-                    chip_unit = chip_unit % 4;
-                    // BUS ID Remapped to linear by John Rell/Joe so removed remap logic 
-                }
-                // adjust for ABUS number
-                else
-                {
-                    chip_unit = chip_unit + 1;
-                }
-            }
-
-            // SW228820 , for Xbus all data goes into BUS0 fields regardless of instance
-            else if ((i_chip_interface == FIR_CEN_DMI) ||
-                    (i_chip_interface == FIR_CP_FABRIC_X0))
-            {
-                chip_unit = 0;
-            }
-
-
-
-
-            rc_ecmd=temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]);
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%X setting up FIR mask data buffer",
-                        rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            scom_address64=temp.getDoubleWord(0);
-
-            //read the 64 bit fir register
-            rc=fapiGetScom(i_target,scom_address64,data);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("Problem in fapi get scom ");
-                break;
-            }
-
-            FAPI_DBG("Clearing spare deployed bit at %d",(8*(chip_unit+1)+1));
-            rc_ecmd |= data.clearBit(8*(chip_unit+1)+1);
-
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("ECMD Error 0x%X setting up FIR data Buffer",
-                        rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            // Clear spare deployed bit on appropriate bits 
-            rc = fapiPutScom(i_target, scom_address64, data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Problem in put scom ");
-                break;
-            }
-
-        } while(0);
-
-        return(rc);
-    }
-
-    // FIR Workaround Code -- Pre Training Section - HW205368 - procedure from Rob /Pete
-    ReturnCode fir_workaround_pre_training(const Target& master_target,  io_interface_t master_interface,uint32_t master_group, const Target&  slave_target,  io_interface_t  slave_interface,uint32_t slave_group,
-            ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old)
-    {
-        ReturnCode rc;
-        //Start - Workaround Pre Training Section - HW205368 - procedure from Rob /Pete
-
-        uint8_t max_group=1;
-
-        if(master_interface==CP_FABRIC_X0){
-            max_group=4;
-        }
-
-        // Take backup of slave bad lane data restored by FW prior to training
-        FAPI_DBG("io_run_training: Saving Bad lane information for HW workaround ");
-        if(master_interface==CP_FABRIC_X0){
-            for (int current_group = 0 ; current_group < max_group; current_group++){
-                rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group,  0,   slave_data_one_old[current_group]);
-                if(rc){return rc;}
-                rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group,  0,  slave_data_two_old[current_group]);
-                if(rc){return rc;}
-            }
-            //Take backup of master bad lane data restored by FW prior to training 
-            for (int current_group = 0 ; current_group < max_group; current_group++){
-                rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group,  0,   master_data_one_old[current_group]);
-                if(rc){return rc;}
-                rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group,  0,  master_data_two_old[current_group]);
-                if(rc){return rc;}
-            }
-        }else{
-            rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group,  0,   slave_data_one_old[0]);
-            if(rc){return rc;}
-            rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group,  0,  slave_data_two_old[0]);
-            if(rc){return rc;}
-            //Take backup of master bad lane data restored by FW prior to training 
-            rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group,  0,   master_data_one_old[0]);
-            if(rc){return rc;}
-            rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group,  0,  master_data_two_old[0]);
-            if(rc){return rc;}
-        }
-        // End - Workaround HW205368
-        return(rc);
-    }
-
-    ReturnCode fir_workaround_post_training(const Target& master_target,  io_interface_t master_interface,uint32_t master_group, const Target&  slave_target,  io_interface_t  slave_interface,uint32_t slave_group,
-            ecmdDataBufferBase *slave_data_one_old,ecmdDataBufferBase *slave_data_two_old,ecmdDataBufferBase *master_data_one_old,ecmdDataBufferBase *master_data_two_old)
-    {
-        ReturnCode rc;
-        //These buffers will store new bad lane info after training 
-        ecmdDataBufferBase slave_data_one_new[4];
-        ecmdDataBufferBase slave_data_two_new[4];
-        ecmdDataBufferBase master_data_one_new[4];
-        ecmdDataBufferBase master_data_two_new[4];
-        fir_io_interface_t fir_master_interface=FIR_CP_IOMC0_P0;
-        fir_io_interface_t fir_slave_interface=FIR_CEN_DMI;
-
-        uint8_t max_group=1;
-
-        //Translate some enums in training header to fir enums 
-        if(master_interface==CP_FABRIC_X0){
-            fir_master_interface=FIR_CP_FABRIC_X0;
-        }
-        else if(master_interface==CP_IOMC0_P0){
-            fir_master_interface= FIR_CP_IOMC0_P0;
-        }
-        else if(master_interface== CEN_DMI){
-            fir_master_interface=FIR_CEN_DMI;
-        }
-        else if(master_interface== CP_FABRIC_A0){
-            fir_master_interface=FIR_CP_FABRIC_A0;
-        }
-        if(slave_interface==CP_FABRIC_X0){
-            fir_slave_interface=FIR_CP_FABRIC_X0;
-        }
-        else if(slave_interface==CP_IOMC0_P0){
-            fir_slave_interface= FIR_CP_IOMC0_P0;
-        }
-        else if(slave_interface== CEN_DMI){
-            fir_slave_interface=FIR_CEN_DMI;
-        }
-        else if(slave_interface== CP_FABRIC_A0){
-            fir_slave_interface=FIR_CP_FABRIC_A0;
-        }
-        else{
-            FAPI_DBG("This is not a possible state since checking of these parms is done in top layer and error code returned ");
-            const fapi::Target &TARGET = master_target;
-            FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_POST_TRAINING_INVALID_INVOCATION_RC);
-            return(rc);          
-        }
-
-
-        if(master_interface==CP_FABRIC_X0){
-            max_group=4;
-        }
-
-        FAPI_DBG("io_run_training : Starting post training HW workaround ");
-        // Start post training part of Workaround - HW205368 - procedure from Rob /Pete
-        // Read slave side bad lane data after training
-        if(master_interface==CP_FABRIC_X0){
-            for (int current_group = 0 ; current_group < max_group; current_group++){
-                rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, current_group,  0,   slave_data_one_new[current_group]);
-                if(rc){return rc;}
-                rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, current_group,  0,  slave_data_two_new[current_group]);
-                if(rc){return rc;}
-            }
-            //Take backup of master bad lane data restored by FW prior to training 
-            for (int current_group = 0 ; current_group < max_group; current_group++){
-                rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, current_group,  0,   master_data_one_new[current_group]);
-                if(rc){return rc;}
-                rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, current_group,  0,  master_data_two_new[current_group]);
-                if(rc){return rc;}
-            }
-        }else{
-            rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_0_15_pg, slave_group,  0,   slave_data_one_new[0]);
-            if(rc){return rc;}
-            rc = GCR_read( slave_target, slave_interface, rx_lane_bad_vec_16_31_pg, slave_group,  0,  slave_data_two_new[0]);
-            if(rc){return rc;}
-            //Take backup of master bad lane data restored by FW prior to training 
-            rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_0_15_pg, master_group,  0,   master_data_one_new[0]);
-            if(rc){return rc;}
-            rc = GCR_read( master_target, master_interface, rx_lane_bad_vec_16_31_pg, master_group,  0,  master_data_two_new[0]);
-            if(rc){return rc;}
-        }
-        // Now we will compare the old and new bad lane data and take appropriate action
-        if(master_interface==CP_FABRIC_X0)
-        {
-            for (int current_group = 0 ; current_group < max_group; current_group++){
-                if(slave_data_one_new[current_group]==slave_data_one_old[current_group] && slave_data_two_new[current_group]==slave_data_two_old[current_group]  ){
-                    // If old and new data is same , no need to present FIRs to PRD
-                    if( !( slave_data_one_new[current_group].isBitClear(0,16) && slave_data_two_new[current_group].isBitClear(0,16) )){
-                        FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side ");
-                        // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors
-                        rc = io_clear_firs(slave_target);
-                        if(rc) return rc;
-                        rc = clear_fir_summary_reg(slave_target,fir_slave_interface);
-                        if(rc) return rc;
-                        rc = clear_fir_summary_reg(master_target,fir_master_interface);
-                        if(rc) return rc;
-                    }
-                }
-                if(master_data_one_new[current_group]==master_data_one_old[current_group] && master_data_two_new[current_group]==master_data_two_old[current_group]  ){
-                    // If old and new data is same , no need to present FIRs to PRD
-                    if( !( master_data_one_new[current_group].isBitClear(0,16) && master_data_two_new[current_group].isBitClear(0,16) )){
-                        FAPI_DBG("io_run_training : Clear invalid FIRs on the master side ");
-                        // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors
-                        rc = io_clear_firs(master_target);
-                        if(rc) return rc;
-                        rc = clear_fir_summary_reg(slave_target,fir_slave_interface);
-                        if(rc) return rc;
-                        rc = clear_fir_summary_reg(master_target,fir_master_interface);
-                        if(rc) return rc;
-                    }
-                }
-            }
-        }
-        else
-        {
-            if(slave_data_one_new[0]==slave_data_one_old[0] && slave_data_two_new[0]==slave_data_two_old[0]  ){
-                // If old and new data is same , no need to present FIRs to PRD
-                if( !( slave_data_one_new[0].isBitClear(0,16) && slave_data_two_new[0].isBitClear(0,16) )){
-                    FAPI_DBG("io_run_training : Clear invalid FIRs on the slave side ");
-                    // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors
-                    rc = io_clear_firs(slave_target);
-                    if(rc) return rc;
-                    rc = clear_fir_summary_reg(slave_target,fir_slave_interface);
-                    if(rc) return rc;
-                    rc = clear_fir_summary_reg(master_target,fir_master_interface);
-                    if(rc) return rc;
-                }
-            }
-            if(master_data_one_new[0]==master_data_one_old[0] && master_data_two_new[0]==master_data_two_old[0]  ){
-                // If old and new data is same , no need to present FIRs to PRD
-                if( !( master_data_one_new[0].isBitClear(0,16) && master_data_two_new[0].isBitClear(0,16) )){
-                    FAPI_DBG("io_run_training : Clear invalid FIRs on the master side ");
-                    // If all bad lane info is clear in new data then no need to clear ,this is a 0==0 case of both old and new empty vectors
-                    rc = io_clear_firs(master_target);
-                    if(rc) return rc;
-                    rc = clear_fir_summary_reg(slave_target,fir_slave_interface);
-                    if(rc) return rc;
-                    rc = clear_fir_summary_reg(master_target,fir_master_interface);
-                    if(rc) return rc;
-                }
-            }
-        }
-
-
-        FAPI_DBG("io_run_training : Clearing FIR masks now-- REORDER");
-        //Finally Unmask the LFIR to let PRD take action post training
-        rc=clear_fir_mask_reg(slave_target,fir_slave_interface);
-        if(rc) return rc;
-        rc=clear_fir_mask_reg(master_target,fir_master_interface);
-        // END post training part of Workaround - HW205368 - procedure from Rob /Pete
-
-
-        return rc;
-
-    }
-
-    // //HW249235 --For DLL workaround
-    // This function will check DLL status on slave and slave side . If any DLL has failed it will update to the next valid
-    // DLL value . 3,4,5,6 are valid values that we are given to select.
-    // This will continue until we run out of valid DLL reg selects or when the DLL cal passes
-
-    ReturnCode check_dll_status_and_modify(const Target &master_target, io_interface_t master_interface,const Target &slave_target,
-            io_interface_t slave_interface,bool dll_master_array[],
-            bool dll_slave_array[],bool &dll_workaround_done,bool &dll_workaround_fail)
-    {
-        ReturnCode rc;
-        uint32_t rc_ecmd=0;
-        ecmdDataBufferBase dll_reg(16),set_bits(16),clear_bits(16),temp_bits(16);
-        const uint16_t dll_vals[]={2,3,4,5,6,7};
-        uint16_t bits=0;
-        uint16_t dll_value=0;
-        bool found_dll_master=false;
-        bool found_dll_slave=false;
-        bool found_dll_master_groups=false;
-        bool found_dll_slave_groups=false;
-        //bool dump_ffdc=false;
-
-        bits=ei4_rx_dll_vreg_ref_sel_clear;
-        rc_ecmd=clear_bits.insert(bits,0,16);
-
-        if(rc_ecmd)
-        {
-            FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-            rc.setEcmdError(rc_ecmd);
-            return(rc);
-        }
-
-        FAPI_INF("DLL WORKAROUND CODE executing");
-        // First we will populate current DLL values into std::vector
-        for (int current_group = 0 ; current_group < 4; current_group++){
-            // slave side operations
-            rc = GCR_read( slave_target, slave_interface,  ei4_rx_dll_analog_tweaks_pg, current_group,  0,   dll_reg);
-            if(rc){return rc;}
-            rc_ecmd|=dll_reg.extract( &dll_value,   4, 3 );
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-                rc.setEcmdError(rc_ecmd);
-                return(rc);
-            }
-
-            FAPI_DBG("Extracted DLL value is %d",dll_value);
-            dll_value=dll_value>>13;
-            FAPI_DBG("DLL value for %d clock group is %d on slave side",current_group,dll_value);
-            if(rc){return rc;}
-
-            if(dll_value>=dll_vals[0] && dll_value<=dll_vals[5]){
-                dll_slave_array[current_group*6+(dll_value-dll_vals[0])]=true;
-            }
-            else{
-                FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!");
-                const fapi::Target &TARGET = slave_target;
-                ecmdDataBufferBase &DLL_REG=dll_reg;
-                FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_CHECK_DLL_VAL_OUT_OF_BOUND_RC);
-                return rc;
-            }
-
-            rc = GCR_read( slave_target, slave_interface, ei4_rx_dll_cal_cntl_pg, current_group,  0,   dll_reg);
-            if(rc){return rc;}
-            if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){
-                // Some DLL error is present , lets push this Clock group ref cal value to the next untried value
-                FAPI_DBG("DLL error detected on clock group %d on slave target",current_group);
-
-                rc=GCR_write(slave_target, slave_interface,  ei4_rx_dll_cal_cntl_pg, current_group,0,   temp_bits, temp_bits,1,1);
-                if(rc){return rc;}
-                rc=GCR_write(master_target, master_interface,  ei4_rx_dll_cal_cntl_pg, current_group,0,   temp_bits, temp_bits,1,1);
-                if(rc){return rc;}
-                for(int dll_valid=0;dll_valid<6;++dll_valid){
-                    if(dll_slave_array[current_group*6 + dll_valid]==false){
-                        // Now set the DLL vref cal sel reg value to the next valid untried value
-                        dll_value=dll_vals[dll_valid];
-                        FAPI_DBG("DLL value to be written is %d dll_valid=%d current_group=%d",dll_value,dll_valid,current_group);
-                        rc=GCR_read(slave_target , slave_interface,  ei4_rx_dll_analog_tweaks_pg,  current_group,0, set_bits);
-                        if(rc){return rc;}
-                        rc_ecmd=set_bits.insert(dll_value,4,3,13);
-                        if(rc_ecmd)
-                        {
-                            FAPI_ERR("Failed buffer insertion in DLL workaround function \n");
-                            rc.setEcmdError(rc_ecmd);
-                            return rc;
-                        }
-                        rc=GCR_write(slave_target, slave_interface,  ei4_rx_dll_analog_tweaks_pg, current_group,0,   set_bits, clear_bits);
-                        if(rc){return rc;}
-                        found_dll_slave=true;
-                        dll_slave_array[current_group*6 + dll_valid]=true;
-                        break;
-                    }
-                }
-                if(found_dll_slave==false){
-                    FAPI_ERR("No valid DLL reg value left to search.. DLL cal on slave of this channel has failed ");
-                    // Now do FFDC call outs
-                    //dump_ffdc=true;
-                    dll_workaround_fail=true;
-                    const fapi::Target &TARGET = slave_target;
-                    ecmdDataBufferBase &DLL_REG=dll_reg;
-                    FAPI_SET_HWP_ERROR(rc,IO_RUN_TRAINING_CHECK_DLL_WORKAROUND_FAIL);
-                    return rc;
-                }
-            }
-            else{
-                FAPI_DBG("NO DLL error detected on clock group %d on slave target",current_group);
-            }
-
-            if(!found_dll_slave){  // If slave has DLL failure , Master status is invalid - John G 
-                // master SIDE operations 
-                // Push current DLL value into the std::vector
-                rc_ecmd |= dll_reg.flushTo0();
-                if(rc_ecmd)
-                {
-                    FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-                    rc.setEcmdError(rc_ecmd);
-                    return rc;
-                }
-                rc = GCR_read( master_target, master_interface,  ei4_rx_dll_analog_tweaks_pg, current_group,  0,   dll_reg);
-                if(rc){return rc;}
-                rc_ecmd|=dll_reg.extract( &dll_value,   4, 3 );
-                if(rc_ecmd)
-                {
-                    FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-                    rc.setEcmdError(rc_ecmd);
-                    return rc;
-                }
-
-                FAPI_DBG("Extracted DLL value is %d",dll_value);
-                dll_value=dll_value>>13;
-                FAPI_DBG("DLL value for %d clock group is %d on master side",current_group,dll_value);
-                if(rc){return rc;}
-                if(dll_value>=dll_vals[0] && dll_value<=dll_vals[5]){
-                    dll_master_array[current_group*6+(dll_value-dll_vals[0])]=true;
-                }
-                else{
-                    FAPI_ERR("DLL Vreg Cal sel value out of bounds for workaround !!");
-                    const fapi::Target &TARGET = slave_target;
-                    ecmdDataBufferBase &DLL_REG=dll_reg;
-                    FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_CHECK_DLL_VAL_OUT_OF_BOUND_RC);
-                    return rc;
-                }
-                rc = GCR_read( master_target, master_interface, ei4_rx_dll_cal_cntl_pg, current_group,  0,   dll_reg);
-                if(rc){return rc;}
-                if(dll_reg.isBitSet(1) || dll_reg.isBitSet(2) || dll_reg.isBitSet(9) || dll_reg.isBitSet(10)){
-                    // Some DLL error is present , lets push this Clock group to the next untried value
-                    FAPI_DBG("DLL error detected on clock group %d on master target",current_group);
-                    rc=GCR_write(slave_target, slave_interface,  ei4_rx_dll_cal_cntl_pg, current_group,0,   temp_bits, temp_bits,1,1);
-                    if(rc){return rc;}
-                    rc=GCR_write(master_target, master_interface,  ei4_rx_dll_cal_cntl_pg, current_group,0,   temp_bits, temp_bits,1,1);
-                    if(rc){return rc;}
-
-                    for(int dll_valid=0;dll_valid<6;++dll_valid){
-                        if(dll_master_array[current_group*6 + dll_valid]==false){
-                            // Now set the DLL vref cal sel reg value to the next valid untried value
-                            dll_value=dll_vals[dll_valid];
-                            FAPI_DBG("DLL value to be written is %d",dll_value);
-                            rc=GCR_read(master_target , master_interface,  ei4_rx_dll_analog_tweaks_pg,  current_group,0, set_bits);
-                            if(rc){return rc;}
-                            rc_ecmd=set_bits.insert(dll_value,4,3,13);
-                            if(rc_ecmd)
-                            {
-                                FAPI_ERR("Failed buffer insertion in DLL workaround function \n");
-                                rc.setEcmdError(rc_ecmd);
-                                return rc;
-                            }
-                            rc=GCR_write(master_target, master_interface,  ei4_rx_dll_analog_tweaks_pg, current_group,0,   set_bits, clear_bits);
-                            if(rc){return rc;}
-                            found_dll_master=true;
-                            dll_master_array[current_group*6 + dll_valid]=true;
-                            break;
-                        }
-                    }
-                    if(found_dll_master==false){
-                        FAPI_ERR("No valid DLL reg value left to search.. DLL cal on master of this channel has failed ");
-                        //dump_ffdc=true;
-                    }
-                }
-                else{
-                    FAPI_DBG("NO DLL error detected on clock group %d on master target",current_group);
-                }
-
-            }
-            if(found_dll_master){
-                found_dll_master_groups=true;
-            }
-            if(found_dll_slave){
-                found_dll_slave_groups=true;
-            }
-        }
-
-        if(found_dll_master_groups || found_dll_slave_groups ) {
-            // at least one clock group on a slave or slave had a DLL fail and valid values to try so we will ask wrapper to continue the
-            // workaround invocations
-            FAPI_DBG("One setting failed on master or slave ");
-            dll_workaround_done=false;
-        }
-        else{
-            // No DLL fail or no Vreg sel values left to try out so we are done 
-            dll_workaround_done=true;
-            FAPI_DBG("DLL Workaround done in checker function");
-            //if(dump_ffdc){
-            //     rc=edi_training::dump_dll_ffdc(master_target,master_interface,slave_target,slave_interface);
-            //}
-        }
-
-
-        return rc;
-    }
-
-    ReturnCode set_tx_drv_pattern(const Target &master_target, io_interface_t master_interface,uint32_t master_group,const Target &slave_target,
-            io_interface_t slave_interface,uint32_t slave_group)
-    {
-        ReturnCode rc;
-        uint32_t rc_ecmd=0;
-        // For DLL shmoo workaround 
-        ecmdDataBufferBase set_bits(16),clear_bits(16),clear_train_bits(16);
-        uint16_t bits=0;
-
-        FAPI_DBG("DLL workaround : Setting TX DRV pattern back to 0000 before restarting training on X bus ");
-        // Clear Clk pattern
-        bits=ei4_tx_drv_data_pattern_gcrmsg_clear;
-        rc_ecmd=clear_bits.insert(bits,0,16);
-        if(rc_ecmd)
-        {
-            FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-            rc.setEcmdError(rc_ecmd);
-            return rc;
-        }
-        rc=GCR_write(slave_target, slave_interface,ei4_tx_data_cntl_gcrmsg_pl  , 15,31,   set_bits, clear_bits,1,1);
-        if(rc){return rc;}
-        rc=GCR_write(master_target, master_interface,ei4_tx_data_cntl_gcrmsg_pl , 15,31,   set_bits, clear_bits,1,1);
-        if(rc){return rc;}
-        //Clear Data pattern 
-        bits=ei4_tx_drv_clk_pattern_gcrmsg_clear;
-        rc_ecmd=clear_bits.insert(bits,0,16);
-        if(rc_ecmd)
-        {
-            FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-            rc.setEcmdError(rc_ecmd);
-            return rc;
-        }
-        rc=GCR_write(slave_target, slave_interface, ei4_tx_clk_cntl_gcrmsg_pg  , 15,0,   set_bits, clear_bits,1,1);
-        if(rc){return rc;}
-        rc=GCR_write(master_target, master_interface, ei4_tx_clk_cntl_gcrmsg_pg , 15,0,   set_bits, clear_bits,1,1);
-        if(rc){return rc;}
-
-        // According to John G , This reset is required as well 
-        bits= ei4_rx_wt_cu_pll_reset_clear  ;
-        rc_ecmd = clear_bits.insert(bits,0,16);
-        rc_ecmd |= set_bits.flushTo0();
-        if(rc_ecmd)
-        {
-            FAPI_ERR("Failed buffer intialization in DLL workaround function \n");
-            rc.setEcmdError(rc_ecmd);
-            return rc;
-        }
-        //Reset wt_cu_pll & Wiretest status & Start bits 
-        for (int current_group = 0 ; current_group < 4; current_group++){
-            //Reset training start and status bits - as per Rob 
-            rc=GCR_write(slave_target ,  slave_interface,  ei4_rx_training_start_pg,current_group,0,   set_bits, clear_train_bits,1,1);
-            if(rc){return rc;}
-            rc=GCR_write(slave_target , slave_interface,  ei4_rx_training_status_pg,  current_group,0, set_bits,clear_train_bits,1,1);
-            if(rc){return rc;}
-            //Reset Wt PLL as per John G 
-            rc=GCR_write(slave_target, slave_interface, ei4_rx_wiretest_pll_cntl_pg  , current_group,0,   set_bits, clear_bits,1,1);
-            if(rc){return rc;}
-
-            //Reset training start and status bits - as per Rob 
-            rc=GCR_write(master_target ,  master_interface,  ei4_rx_training_start_pg,current_group,0,   set_bits, clear_train_bits,1,1);
-            if(rc){return rc;}
-            rc=GCR_write(master_target , master_interface,  ei4_rx_training_status_pg,  current_group,0,  set_bits,clear_train_bits,1,1);
-            if(rc){return rc;}
-            // Reset Wt PLL as per John G
-            rc=GCR_write(master_target, master_interface, ei4_rx_wiretest_pll_cntl_pg  , current_group,0,   set_bits, clear_bits,1,1);
-            if(rc){return rc;}
-        }
-
-
-        FAPI_DBG("Done Setting TX Drv pattern to 0000 and wt_cu_pll_reset to 0 for DLL workaround ");
-        return rc;
-    }
-
-    //HW Defect HW220449 , HW HW247831
-    // Set rx_sls_extend_sel=001 on slave side of X bus post training
-    ReturnCode do_sls_fix(const Target &slave_target, io_interface_t slave_interface)
-    {
-        ReturnCode rc;
-        uint32_t rc_ecmd=0;
-        ecmdDataBufferBase set_bits(16),clear_bits(16);
-        uint16_t bits=1;
-
-        FAPI_DBG("Setting rx_extend_sel to 001 for all Xbus slaves for HW220449");
-        for (int current_group = 0 ; current_group < 4; current_group++){
-            rc = GCR_read( slave_target, slave_interface,ei4_rx_spare_mode_pg, current_group,  0,  set_bits);
-            if(rc){return rc;}
-            rc_ecmd = set_bits.insert(bits,5,3,13); // insert rx_sls_extend_sel
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Failed buffer manipulation in do_sls_fix \n");
-                rc.setEcmdError(rc_ecmd);
-                return rc;
-            }
-            rc=GCR_write(slave_target, slave_interface, ei4_rx_spare_mode_pg , current_group,0,   set_bits, clear_bits);
-            if(rc){return rc;}
-        }
-        return rc;
-    }
-
-    // To handle the MAX_SPARE_EXCEEDED FIR case which we have to handle here in our HWP instead of waiting for PRD.
-    ReturnCode handle_max_spare(const Target &target,io_interface_t interface,uint8_t current_group){
-        ReturnCode o_rc;
-        uint32_t rc_ecmd=0;
-        ecmdDataBufferBase error_data(16);
-        uint32_t bitPos=0x2680;
-
-        if(interface==CP_FABRIC_X0){
-            o_rc=GCR_read(target ,  interface, ei4_rx_fir_training_pg,  current_group,0, error_data);
-        }
-        else{
-            o_rc=GCR_read(target ,  interface, rx_fir_training_pg,  current_group,0, error_data);
-        }
-        if(o_rc)
-            return o_rc;
-        if(error_data.isBitSet(2,1)){    // can be caused by a static (pre training - bit 2) or dynamic (post training - bit 5) or recal(bit 8)
-            FAPI_ERR("MAX_SPARE_EXCEEDED ON THIS BUS clock group %d",current_group);
-            rc_ecmd = error_data.setAnd(bitPos,0,16);
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Failed buffer manipulation in handle_max_spare \n");
-                o_rc.setEcmdError(rc_ecmd);
-                return o_rc;
-            }
-            ecmdDataBufferBase & SPARE_ERROR_REG = error_data; //bit2 /bit 5 /bit 8of the register represents the max spare exceeded bit.To determine what caused the max spares exceeded error
-            const fapi::Target & CHIP_TARGET= target;
-            FAPI_SET_HWP_ERROR(o_rc,IO_RUN_TRAINING_FIR_MAX_SPARES_EXCEEDED_RC);
-        }
-        return(o_rc);
-    }
-
-    // These functions work on a pair of targets. One is the master side of the bus interface, the other the slave side. For eg; in EDI(DMI2)PU is the master and Centaur is the slave
-    // In EI4 both sides have pu targets . After the talk with Dean , my understanding is that targets are configured down upto the endpoints of a particular bus. eg; pu 0 A0 --> pu 1 A3 could be a combination on EI4
-    // In a EDI(DMI) bus the targets are considered to be one pu and one centaur pair . The overall code is same for EDI and EI4 and the run_training function handles both bus types ( X ,A or MC ) . 
-    ReturnCode io_run_training(const Target &master_target,const Target &slave_target){
-        ReturnCode rc;
-        io_interface_t master_interface,slave_interface;
-        uint32_t master_group=0;
-        uint32_t slave_group=0;
-        const uint32_t max_group=4; // Num of X bus groups in one bus
-        edi_training init;
-
-        // Workaround - HW 220654 -- Need to split WDERF into WDE + RF
-        edi_training init1(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run WDE first
-
-        // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF 
-
-        // For Xbus DLL Workaround , we need Wiretest alone , then DE and RF 
-        edi_training init_w(SELECTED,NOT_RUNNING, NOT_RUNNING, NOT_RUNNING, NOT_RUNNING); // Run W for Xbus
-        edi_training init_wde(SELECTED,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING); // Run DE next for X bus
-
-        // For the PLL workaround we need a DE Object since DE + RF should be separate as per original guidelines
-        edi_training init_de(NOT_RUNNING,SELECTED,SELECTED, NOT_RUNNING, NOT_RUNNING);
-
-        // Need an object to restore object state after one wiretest run. 
-        edi_training copy_w=init_w;
-        // DE & RF needs to be split due to HW 220654 
-        edi_training init2( NOT_RUNNING, NOT_RUNNING, NOT_RUNNING,SELECTED,SELECTED); // Run RF next
-        bool is_master=false;
-        //FIR workaround buffers
-        //These buffers will store old bad lane info that was restored prior to training 
-        ecmdDataBufferBase slave_data_one_old[4];
-        ecmdDataBufferBase slave_data_two_old[4];
-        ecmdDataBufferBase master_data_one_old[4];
-        ecmdDataBufferBase master_data_two_old[4];
-
-
-        // This is a DMI/MC bus 
-        if( (master_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )&&
-                (slave_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP))
-        {
-            FAPI_DBG("This is a DMI bus using base DMI scom address");
-            master_interface=CP_IOMC0_P0; // base scom for MC bus
-            slave_interface=CEN_DMI; // Centaur scom base
-            master_group=3; // Design requires us to do this as per scom map and layout
-            slave_group=0;
-            rc=fir_workaround_pre_training(master_target,master_interface,master_group,
-                    slave_target,slave_interface,slave_group,
-                    slave_data_one_old,slave_data_two_old,
-                    master_data_one_old,master_data_two_old);
-            if(rc) return rc;
-            // Workaround - HW 220654 -- Need to split WDERF into WDE + RF due to sync problem
-            // For PLL workaround now we run W alone , followed by DE then RF 
-            rc=init_w.run_training(master_target,master_interface,master_group,
-                    slave_target,slave_interface,slave_group);
-            if(!rc.ok()){
-                return rc;
-            }
-
-            // Now Set PLL to runtime setting and continue with training
-            // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs
-
-            rc=io_training_set_pll_post_wiretest(slave_target);
-            //FAPI_DBG("Waiting for 1s after PLL Update on slave");
-            //rc=fapiDelay(1000000,1000);
-
-            if(!rc.ok()){
-                FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); 
-                return rc;
-            }
-            rc=io_training_set_pll_post_wiretest(master_target);
-            if(!rc.ok()){
-                FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE "); 
-                return rc;
-            }
-
-            // FAPI_DBG("Waiting for 1s after PLL Update on master");
-            //  rc=fapiDelay(1000000,1000); 
-            // Run DE Now - as per Gary 
-            rc=init_de.run_training(master_target,master_interface,master_group,
-                    slave_target,slave_interface,slave_group);
-            if(!rc.ok()){
-                return rc;
-            }
-            //Now Run RF 
-            rc=init2.run_training(master_target,master_interface,master_group,
-                    slave_target,slave_interface,slave_group);
-            if(rc) return rc;
-            rc=fir_workaround_post_training(master_target,master_interface,
-                    master_group,slave_target,
-                    slave_interface,slave_group,
-                    slave_data_one_old,slave_data_two_old,
-                    master_data_one_old,master_data_two_old);
-            if(rc) return rc;
-            rc=handle_max_spare(master_target,master_interface,master_group);
-            if(rc) return rc;
-            rc=handle_max_spare(slave_target,slave_interface,slave_group);
-            if(rc) return rc;
-
-
-        }
-        //This is an X Bus
-        else if( (master_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT  )&&
-                (slave_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT ))
-        {
-            FAPI_DBG("This is a X Bus training invocation");
-            master_interface=CP_FABRIC_X0; // base scom for X bus
-            slave_interface=CP_FABRIC_X0; // base scom for X bus
-            slave_group=0; // Design requires us to do this as per scom map and layout
-            master_group=0;
-            uint8_t trial_count=0;
-            //HW249235 --For DLL workaround 
-            bool dll_master_array[24],dll_slave_array[24]; // DLL array for each clock group
-            bool dll_workaround_done=false;
-            bool dll_workaround_fail=false;
-
-            //init Bool array
-            for(int i=0;i<24;++i){
-                dll_master_array[i]=false;
-                dll_slave_array[i]=false;
-            }
-
-            rc=init.isChipMaster(master_target,master_interface,master_group,is_master);
-            if(rc.ok()){
-                if(!is_master)
-                {
-                    //Swap slave and slave targets !!
-                    FAPI_DBG("X Bus ..target swap performed");
-                    rc=fir_workaround_pre_training(slave_target,slave_interface,
-                            slave_group,slave_target,
-                            slave_interface,slave_group,
-                            slave_data_one_old,slave_data_two_old,
-                            master_data_one_old,master_data_two_old);
-                    if(rc) return rc;
-                    do
-                    {
-                        trial_count++;
-                        FAPI_DBG("TRAINING TRIAL count=%d",trial_count);
-                        rc=init_w.run_training(slave_target,slave_interface,
-                                slave_group,master_target,
-                                master_interface,master_group);
-                        if(rc) {
-                            //HW249235 --For DLL workaround
-                            FAPI_DBG("Starting DLL Workaround");
-                            rc=check_dll_status_and_modify(slave_target,
-                                    slave_interface,
-                                    master_target,
-                                    master_interface,
-                                    dll_slave_array,
-                                    dll_master_array,
-                                    dll_workaround_done,
-                                    dll_workaround_fail);
-                            if(rc) return rc;
-                            // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete
-                            //Prep the targets for next round of WDE training -- Steps by Rob & Pete
-                            if(!dll_workaround_done)
-                            {
-                                rc=set_tx_drv_pattern(slave_target,
-                                        slave_interface,
-                                        slave_group,
-                                        master_target,
-                                        master_interface,
-                                        master_group);
-                                if(rc) return rc;
-                            }
-                            
-                        }
-                        else{
-                            if(trial_count>1){
-                                FAPI_DBG("DLL workaround was successfull");
-                            }
-                            dll_workaround_done=true;
-                        }
-                        init_w=copy_w;
-                    }while(!dll_workaround_done);
-                    if(!dll_workaround_fail){
-                        // We need to reset Wirtest machine so that we can do WDE again
-                        rc=set_tx_drv_pattern(slave_target,slave_interface,
-                                slave_group,master_target,
-                                master_interface,master_group);
-                        if(rc) return rc;
-                        rc=init_wde.run_training(slave_target,slave_interface,
-                                slave_group,master_target,
-                                master_interface,master_group);
-                        if(rc) return rc;
-                        rc=init2.run_training(slave_target,slave_interface,
-                                slave_group,master_target,
-                                master_interface,master_group);
-                        if(rc) return rc;
-                        rc=fir_workaround_post_training(slave_target,
-                                slave_interface,
-                                slave_group,
-                                slave_target,
-                                slave_interface,
-                                slave_group,
-                                slave_data_one_old,
-                                slave_data_two_old,
-                                master_data_one_old,
-                                master_data_two_old);
-                        if(rc) return rc;
-                        //HW Defect HW220449 , HW HW247831
-                        // Set rx_sls_extend_sel=001 on slave side of X bus post training
-                        rc=do_sls_fix(master_target,master_interface);
-                        if(rc) return rc;
-                    }
-                }
-                else{
-                    rc=fir_workaround_pre_training(master_target,
-                            master_interface,
-                            master_group,
-                            slave_target,
-                            slave_interface,
-                            slave_group,
-                            master_data_one_old,
-                            master_data_two_old,
-                            slave_data_one_old,
-                            slave_data_two_old);
-                    if(rc) return rc;
-                    do{
-                        trial_count++;
-                        FAPI_DBG("TRAINING TRIAL count=%d",trial_count);
-                        rc=init_w.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
-                        if(rc) {
-                            //HW249235 --For DLL workaround
-                            FAPI_DBG("Starting DLL Workaround");
-                            rc=check_dll_status_and_modify(master_target,master_interface,slave_target,slave_interface,
-                                    dll_master_array,dll_slave_array,dll_workaround_done,dll_workaround_fail);
-                            if(rc) return rc;
-                            // Reset tx drive pattern to 0000 before starting Wiretest again -- As per Rob /Pete
-                            //Prep the targets for next round of WDE training -- Steps by Rob & Pete
-                            if(!dll_workaround_done){
-                                rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface,
-                                        slave_group);
-                                if(rc) return rc;
-                            }
-                        }
-                        else{
-                            if(trial_count>1){
-                                FAPI_DBG("DLL workaround was successfull");
-                            }
-                            dll_workaround_done=true;
-                        }
-                        init_w=copy_w;// Reset training object state to default
-                    }while(!dll_workaround_done);
-                    if(!dll_workaround_fail){
-                        // We need to reset Wirtest machine so that we can do WDE again
-                        rc=set_tx_drv_pattern(master_target,master_interface,master_group,slave_target,slave_interface,
-                                slave_group);
-                        if(rc) return rc;
-                        rc=init_wde.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
-                        if(rc) return rc;
-                        rc=init2.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
-                        if(rc) return rc;
-                        rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group,
-                                master_data_one_old,master_data_two_old,slave_data_one_old,slave_data_two_old);
-                        if(rc) return rc;
-
-                        //HW Defect HW220449 , HW HW247831
-                        // Set rx_sls_extend_sel=001 on slave side of X bus post training
-                        rc=do_sls_fix(slave_target,slave_interface);
-                        if(rc) return rc;
-                    }
-                }
-                for(uint32_t current_group=0;current_group<max_group;++current_group){
-                    rc=handle_max_spare(master_target,master_interface,current_group);
-                    if(rc) return rc;
-                    rc=handle_max_spare(slave_target,slave_interface,current_group);
-                    if(rc) return rc;
-                }
-            }
-        }
-        //This is an A Bus
-        else if( (master_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT )&& (slave_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
-            FAPI_DBG("This is an A Bus training invocation");
-            master_interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT 
-            slave_interface=CP_FABRIC_A0; //base scom for A bus
-            master_group=0; // Design requires us to do this as per scom map and layout
-            slave_group=0;
-            rc=init.isChipMaster(master_target,master_interface,master_group,is_master);
-            if(rc.ok()){
-                if(!is_master)
-                {
-                    FAPI_DBG("A Bus ..target swap performed");
-
-                    rc=fir_workaround_pre_training(slave_target,slave_interface,
-                            slave_group,slave_target,
-                            slave_interface,slave_group,
-                            slave_data_one_old,slave_data_two_old,
-                            master_data_one_old,master_data_two_old);
-
-                    if(rc) return rc;
-                    rc=init_w.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
-
-                    if(!rc.ok()){
-                        return rc;
-                    }
-
-                    // Now Set PLL to runtime setting and continue with training
-                    // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs
-
-                    rc=io_training_set_pll_post_wiretest(slave_target);
-
-                    if(!rc.ok()){
-                        FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); 
-                        return rc;
-                    }
-                    rc=io_training_set_pll_post_wiretest(master_target);
-                    if(!rc.ok()){
-                        FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE ");
-                        return rc;
-                    }
-                    rc=init_de.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
-                    if(rc) return rc;
-
-                    // Now do RF
-                    rc=init2.run_training(slave_target,slave_interface,slave_group,
-                            master_target,master_interface,master_group);
-                    if(rc) return rc;
-                    rc=fir_workaround_post_training(slave_target,
-                            slave_interface,
-                            slave_group,
-                            slave_target,
-                            slave_interface,
-                            slave_group,
-                            slave_data_one_old,
-                            slave_data_two_old,
-                            master_data_one_old,
-                            master_data_two_old);
-                    if(rc) return rc;
-                }
-                else
-                {
-
-                    rc=fir_workaround_pre_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group,
-                            slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old);
-                    if(rc) return rc;
-                    rc=init_w.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
-
-                    if(!rc.ok()){
-                        return rc;
-                    }
-
-                    // Now Set PLL to runtime setting and continue with training
-                    // Call Janani's PLL ring set function from DCCAL module. It in turn uses Joe's funcs
-
-                    rc=io_training_set_pll_post_wiretest(slave_target);
-
-                    if(!rc.ok()){
-                        FAPI_DBG("PLL SETTING FAILED ON SLAVE SIDE "); 
-                        return rc;
-                    }
-                    rc=io_training_set_pll_post_wiretest(master_target);
-                    if(!rc.ok()){
-                        FAPI_DBG("PLL SETTING FAILED ON MASTER SIDE ");
-                        return(rc);
-                    }
-                    rc=init_de.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
-                    if(rc) return rc;
-
-                    // Now do RF
-                    rc=init2.run_training(master_target,master_interface,master_group,
-                            slave_target,slave_interface,slave_group);
-                    if(rc) return rc;
-                    rc=fir_workaround_post_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group,
-                            slave_data_one_old,slave_data_two_old,master_data_one_old,master_data_two_old);
-                    if(rc) return rc;
-                }
-            }
-        }
-        else{
-            FAPI_ERR("Invalid io_run_training HWP invocation . Pair of targets dont belong to DMI/X/A instances");
-            const fapi::Target &MASTER_TARGET = master_target;
-            const fapi::Target &SLAVE_TARGET = slave_target;
-            FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_TARGET_PAIR_RC);
-        }
-        return rc;
-    }
-
-
-} // extern 
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.H b/src/usr/hwpf/hwp/bus_training/io_run_training.H
deleted file mode 100644
index 116d2c0c6..000000000
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.H
+++ /dev/null
@@ -1,55 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/bus_training/io_run_training.H $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_run_training.H,v 1.9 2014/03/05 11:56:29 varkeykv Exp $
-#ifndef IO_RUN_TRAINING_H_
-#define IO_RUN_TRAINING_H_
-
-
-#include <fapi.H>
-
-using namespace fapi;
-
-/**
- * io_run_training func pointer Typedef for hostboot 
- *
- */
-typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &);
-
-extern "C"
-{
-
-/**
- * io_run_training 
- *
- * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric 
- * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric
- * while these are called master or slave... I actually do a check in the code to see 
- * whether these are actually master chips by reading a GCR master_mode bit
- * and accordingly will perform a target swap if required 
- * @return ReturnCode
- */
-fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);
-
-} // extern "C"
-
-#endif // IO_RUN_TRAINING_H
diff --git a/src/usr/hwpf/hwp/bus_training/makefile b/src/usr/hwpf/hwp/bus_training/makefile
deleted file mode 100644
index dfd36e634..000000000
--- a/src/usr/hwpf/hwp/bus_training/makefile
+++ /dev/null
@@ -1,54 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/bus_training/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2014
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = bus_training
-
-SUBDIRS += runtime.d
-
-# ROOTPATH must be defined before including this file.
-include io_hwp_common_ipl_and_rt.mk
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-OBJS += io_funcs.o
-OBJS += io_run_training.o
-OBJS += pbusLinkSvc.o
-OBJS += io_dccal.o
-OBJS += io_restore_erepair.o
-OBJS += io_post_trainadv.o
-OBJS += io_pre_trainadv.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-## vpath   %.C proc_cen_framelock:io_run_training
-## vpath   %.H proc_cen_framelock:io_run_training
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/bus_training/runtime/makefile b/src/usr/hwpf/hwp/bus_training/runtime/makefile
deleted file mode 100644
index 82ea1db91..000000000
--- a/src/usr/hwpf/hwp/bus_training/runtime/makefile
+++ /dev/null
@@ -1,36 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/bus_training/runtime/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2014
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-HOSTBOOT_RUNTIME = 1
-ROOTPATH = ../../../../../..
-MODULE = bus_training_rt
-
-VPATH += ..
-EXTRAINCDIR += ..
-
-# ROOTPATH must be defined before including this file.
-include ../io_hwp_common_ipl_and_rt.mk
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/core_activate/core_activate.H b/src/usr/hwpf/hwp/core_activate/core_activate.H
deleted file mode 100644
index c8198e841..000000000
--- a/src/usr/hwpf/hwp/core_activate/core_activate.H
+++ /dev/null
@@ -1,140 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/core_activate.H $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef  __CORE_ACTIVATE_CORE_ACTIVATE_H
-#define  __CORE_ACTIVATE_CORE_ACTIVATE_H
-
-/**
- *  @file core_activate.H
- *
- *  Core Activate
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  *****************************************************************
- *  THIS FILE WAS GENERATED ON 2012-04-11:1609
- *  *****************************************************************
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
- /*  @tag isteplist
- *  @docversion     v1.28 (12/03/12)
- *  @istepname      core_activate
- *  @istepnum       16
- *  @istepdesc      Core Activate
- *
- *  @{
- *      @substepnum     1
- *      @substepname    host_activate_master
- *      @substepdesc    : Activate master core
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    host_activate_slave_cores
- *      @substepdesc    : Activate slave cores
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     3
- *      @substepname    mss_scrub
- *      @substepdesc    : Start background scrub
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     4
- *      @substepname    host_ipl_complete
- *      @substepdesc    : Notify FSP drawer ipl complete
- *       *          @target_sched   serial
- *  @}
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-namespace   CORE_ACTIVATE
-{
-
-
-
-/**
- *  @brief   host_activate_master
- *
- *           Activate master core
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*    call_host_activate_master( void    *io_pArgs );
-
-
-
-/**
- *  @brief   host_activate_slave_cores
- *
- *           Activate slave cores
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*    call_host_activate_slave_cores( void    *io_pArgs );
-
-
-/**
- *  @brief   mss_scrub
- *
- *           Start background scrub
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_mss_scrub( void    *io_pArgs );
-
-
-/**
- *  @brief   host_ipl_complete
- *
- *           Notify FSP drawer ipl complete
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*    call_host_ipl_complete( void    *io_pArgs );
-
-};   // end namespace
-
-#endif
-
diff --git a/src/usr/hwpf/hwp/core_activate/makefile b/src/usr/hwpf/hwp/core_activate/makefile
deleted file mode 100644
index c365a32e9..000000000
--- a/src/usr/hwpf/hwp/core_activate/makefile
+++ /dev/null
@@ -1,83 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/core_activate/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-MODULE = core_activate
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  NOTE: add the base istep dir here.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_post_winkle
-##  @todo   RTC Story 51709 and Story 51711 : revisit this later -
-##  proc_set_pore_bar is used by multiple isteps, so it should be in its own
-##  "utility" library
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/switch_rec_attn
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_check_slw_done
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_block_wakeup_intr
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures
-
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += proc_prep_master_winkle.o
-OBJS += proc_stop_deadman_timer.o
-OBJS += proc_sbe_utils.o
-OBJS += proc_switch_cfsim.o
-OBJS += proc_switch_rec_attn.o
-OBJS += cen_switch_rec_attn.o
-OBJS += proc_post_winkle.o
-OBJS += proc_check_slw_done.o
-
-
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/<HWP_dir>
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/switch_rec_attn
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_post_winkle
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_check_slw_done
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.C b/src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.C
deleted file mode 100755
index b00715e41..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.C
+++ /dev/null
@@ -1,404 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_check_slw_done.C,v 1.10 2015/09/17 16:10:02 cmolsen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_slw_done.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Michael Olsen Email: cmolsen@us.ibm.com
-/// \file proc_check_slw_done.C
-/// \brief  Check the SLW complex for proper state
-///
-/// \verbatim
-///
-///     Dependency: ATTR_PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR has the 
-///                 XIP offset of the good value for Deep Winkle
-///                 For P8, this is set in p8_set_pore_bar.C
-///
-///     parms:  i_ex_target
-///     {
-///
-///         Check that passed chiplet number is in the ETR chiplet vector
-///         if not,
-///             - call collect_ex_ffdc()
-///             - return FAIL code
-///
-///         Check SLW is in clean state
-///             - Control/Status register indicates stopped condition
-///             - read ATTR_PM_SLW_DEEP_SLEEP_EXIT_GOOD_HALT_ADDR to get the 
-///                 the value of the good halt address
-///             - if good_halt_address is not NULL,
-///                 - Compare PC (from Control/Status register) to the "good" address
-///                 if miscompare,
-///                     - put "good" address in FFDC data
-///                     - collect PBA BAR2 and MASK2
-///                     - collect_slw_ffdc()
-///                     - collect_ex_ffdc()
-///                     - image_meta_data()
-///                     - return FAIL code
-///
-///             - For the passed chiplet
-///                 - Read PMHistory
-///                 - Compare PMHistory value with ETR transition value
-///                 - if miscompare,
-///                     - collect_slw_ffdc()
-///                     - collect_ex_ffdc()
-///                     - return FAIL code
-///
-///         Check PMC LFIR for SLW related bits
-///         (Fatal err (11); Status RC (12); Status Value(13); Write while active (14);
-///         Timeout (15))
-///             if errors non-zero,
-///                 - collect_slw_ffdc()
-///                 - collect_ex_ffdc()
-///                 - return FAIL code
-///
-///         exit
-///      }
-///
-///      collect_slw_ffdc()
-///      {
-///          - EX number
-///          - SLW Regs (including ETR which indicates the chiplets being hit)
-///          - PMC LFIR
-///          - PBA LFIR
-///      }
-///
-///      collect_ex_ffdc()
-///      {
-///          - PMGP0
-///          - GP3
-///          - PMHistory
-///          - PMErr
-///      }
-///
-///
-/// Background:
-/// If a non-Success return occurs, it could be two possibilities
-///     1) SLW engine never saw the IPI ---> in this case, the passed chiplet
-///         number will not be in the ETR vector;
-///             - gather FFDC for missing IPI due to HB bug OR HW settings
-///         Dump IPC state AND a HB dump
-///     2) SLW engine is in error --> gather FFDC for a SLW engine fail
-///         Need to be able to callout the right thing -- VPD, memory UE, is it SLW engine itself
-///
-///  Procedure Prereq:
-///     - System clocks are running
-/// \endverbatim
-///
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-#include "proc_check_slw_done.H"
-#include "p8_pm.H"
-
-extern "C" {
-
-using namespace fapi;
-
-// ----------------------------------------------------------------------
-// Constant definitions
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Global variables
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Function prototypes
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Function definitions
-// ----------------------------------------------------------------------
-
-
-/**
- * proc_check_slw_done
- *
- * @param[in] i_target EX target
- *
- * @retval ECMD_SUCCESS
- * @retval ERROR
- */
-fapi::ReturnCode
-proc_check_slw_done(const fapi::Target& i_ex_target)
-{
-    fapi::ReturnCode    rc;
-    uint32_t            e_rc = 0;
-
-    ecmdDataBufferBase  data(64);
-    ecmdDataBufferBase  etr(64);
-    ecmdDataBufferBase  gp3(64);
-    ecmdDataBufferBase  pmgp0(64);
-    ecmdDataBufferBase  pmgp1(64);
-    ecmdDataBufferBase  pmhist(64);
-    ecmdDataBufferBase  pmerr(64);
-
-    uint8_t             l_ex_number = 0;
-    fapi::Target        l_parentTarget;
-    uint64_t            address;
-    uint64_t            ex_offset;
-    
-    uint32_t            good_halt_address = 0;
-
-    uint32_t            idle_transition = 0;
-    uint32_t            ex_vector = 0;
-    uint32_t            ex_test_bit = 0;
-    uint32_t            slw_fsm_state = 0;
-    uint32_t            slw_stack_state = 0;
-    uint64_t            slw_address = 0;
-    uint32_t            pm_hist_state = 0;
-    uint32_t            pmc_lfir_slw = 0;
-
-    // 24 bit mask
-    const uint64_t      SLW_ADDRESS_MASK = 0x0000000000FFFFFF;
-
-    bool                b_state_error = false;
-
-    do
-    {
-
-        FAPI_INF("Beginnning proc_check_slw_done...");
-
-        // Get the parent chip to target the PCBS registers
-        rc = fapiGetParentChip(i_ex_target, l_parentTarget);
-        if (rc)
-        {
-            FAPI_ERR("fapiGetParentChip access");
-            break;
-        }
-
-        // Get the core number
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_ex_target, l_ex_number);
-        if (rc)
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc);
-            break;
-        }
-
-        FAPI_INF("Checking EX %d on %s", l_ex_number, l_parentTarget.toEcmdString());
-
-        ex_offset = l_ex_number * 0x01000000;
-
-        // Read the pertinent registers
-
-        address = EX_GP3_0x100F0012 + ex_offset;
-        GETSCOM(rc, l_parentTarget, address, gp3);
-
-        address = EX_PMGP0_0x100F0100 + ex_offset;
-        GETSCOM(rc, l_parentTarget, address, pmgp0);
-
-        address = EX_PMGP1_0x100F0103 + ex_offset;
-        GETSCOM(rc, l_parentTarget, address, pmgp1);
-
-        address = EX_PMErr_REG_0x100F0109 + ex_offset;
-        GETSCOM(rc, l_parentTarget, address, pmerr);
-
-        address = EX_PMSTATEHISTPHYP_REG_0x100F0110 + ex_offset;
-        GETSCOM(rc, l_parentTarget, address, pmhist);
-
-        // Check that passed chiplet number is in the ETR chiplet vector
-        GETSCOM(rc, l_parentTarget, PORE_SLW_EXE_TRIGGER_0x00068009, etr);
-
-        e_rc |= etr.extractToRight( &idle_transition, 8, 4 );
-        e_rc |= etr.extractToRight( &ex_vector, 32, 16 );
-        E_RC_CHECK(e_rc, rc);
-
-        ex_test_bit = (ex_vector>>(16-l_ex_number-1) & 0x0001);
-        FAPI_DBG("\tex_vector: 0x%04X;  ex_test_bit: %1X", ex_vector, ex_test_bit);
-
-        // If chiplet not in ETR, collected FFDC and return
-        if (!ex_test_bit)
-        {
-            FAPI_ERR("EX %d is not in current SLW EXE Trigger 0x%016llX", l_ex_number, etr.getDoubleWord(0));
-            const uint64_t& GP3     = gp3.getDoubleWord(0);
-            const uint64_t& PMGP0   = pmgp0.getDoubleWord(0);
-            const uint64_t& PMGP1   = pmgp1.getDoubleWord(0);
-            const uint64_t& PMERR   = pmerr.getDoubleWord(0);
-            const uint64_t& PMHIST  = pmhist.getDoubleWord(0);
-            const uint64_t& EX      = l_ex_number;
-            const fapi::Target& EX_IN_ERROR = i_ex_target;
-            const fapi::Target& CHIP_IN_ERROR = l_parentTarget;
-            FAPI_SET_HWP_ERROR(rc, RC_PMPROC_CHKSLW_NOT_IN_ETR);
-            break;
-
-        }
-
-        // Check SLW is in clean state
-        address = PORE_SLW_STATUS_0x00068000;
-        GETSCOM(rc, l_parentTarget, address, data);
-
-        e_rc |= data.extractToRight( &slw_fsm_state,    3, 4 );
-        e_rc |= data.extractToRight( &slw_stack_state, 12, 4 );
-        E_RC_CHECK(e_rc, rc);
-
-        slw_address = data.getDoubleWord(0);
-        slw_address &= SLW_ADDRESS_MASK;
-
-        if ((slw_fsm_state & 0x000F) != 0x1)
-        {
-            FAPI_ERR("SLW FSM not in Wait state");
-            b_state_error = true;
-        }
-        if ((slw_stack_state & 0x000F) != 0x1)
-        {
-            FAPI_ERR("SLW FSM stack is not empty");
-            b_state_error = true;
-        }
-
-        address = PORE_SLW_CONTROL_0x00068001;
-        GETSCOM(rc, l_parentTarget, address, data);
-
-        if (data.isBitClear(0))
-        {
-            FAPI_ERR("SLW engine is not stopped");
-            b_state_error = true;
-        }
-
-        if (b_state_error)
-        {
-            const uint64_t& EX = l_ex_number;
-            const fapi::Target& CHIP_IN_ERROR = l_parentTarget;
-
-            // XML will dump the SLW registers
-
-            FAPI_SET_HWP_ERROR(rc, RC_PMPROC_CHKSLW_INVALID_STATE);
-            break;
-        }
-        
-        // Get the good_halt_address
-        GETATTR(rc,
-                ATTR_PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR,
-                "ATTR_PM_SLW_DEEP_WINKLE_EXIT_GOOD_HALT_ADDR",
-                NULL,
-                good_halt_address);
-
-        // if good_halt_address is not NULL, compare PC to the "good" address
-        if (good_halt_address)
-        {
-            FAPI_INF("Checking for good halt address: 0x%08llX", (uint64_t)good_halt_address );
-            uint64_t good_halt_address_masked = good_halt_address & SLW_ADDRESS_MASK;
-            uint64_t slw_address_masked = slw_address & SLW_ADDRESS_MASK;
-            if ((good_halt_address_masked) != slw_address_masked)
-            {
-                FAPI_ERR("SLW engine address does not match the expected address: actual = 0x%016llX; expected =  0x%016llX",
-                                slw_address_masked, good_halt_address_masked);
-                const uint64_t& GP3     = gp3.getDoubleWord(0);
-                const uint64_t& PMGP0   = pmgp0.getDoubleWord(0);
-                const uint64_t& PMGP1   = pmgp1.getDoubleWord(0);
-                const uint64_t& PMERR   = pmerr.getDoubleWord(0);
-                const uint64_t& PMHIST  = pmhist.getDoubleWord(0);
-                const uint64_t& GOODHALTADDR = (uint64_t)good_halt_address;
-                const uint64_t& EX      = l_ex_number;
-                const fapi::Target& EX_IN_ERROR = i_ex_target;
-                const fapi::Target& CHIP_IN_ERROR = l_parentTarget;
-                FAPI_SET_HWP_ERROR(rc, RC_PMPROC_CHKSLW_ADDRESS_MISMATCH);
-                break;
-            }
-            else
-            {
-                FAPI_INF("Good halt address checking passed");
-
-            }
-        }
-        else
-        {
-            FAPI_INF("No good halt address is available;  bypassing address check");
-        }
-
-        // For the passed chiplet, check for running
-        FAPI_INF("Checking EX %d for RUNNING state", l_ex_number);
-        e_rc |= pmhist.extractToRight( &pm_hist_state, 0, 2 );
-        E_RC_CHECK(e_rc, rc);
-
-        FAPI_DBG("\tPMHist = 0x%016llX; pm_hist_state = 0x%08X", pmhist.getDoubleWord(0), pm_hist_state);
-
-        // History = 0 means running;  something other than that is not good
-        if (pm_hist_state)
-        {
-            FAPI_ERR("EX %d is not in expected RUNNING state: PMHist = 0x%016llX", l_ex_number, pmhist.getDoubleWord(0));
-            const uint64_t& PMHIST  = pmhist.getDoubleWord(0);
-            const uint64_t& GP3     = gp3.getDoubleWord(0);
-            const uint64_t& PMGP0   = pmgp0.getDoubleWord(0);
-            const uint64_t& PMGP1   = pmgp1.getDoubleWord(0);
-            const uint64_t& PMERR   = pmerr.getDoubleWord(0);
-            const uint64_t& EX      = l_ex_number;
-            const fapi::Target& CHIP_IN_ERROR = l_parentTarget;
-
-             // XML will dump the SLW registers
-
-            FAPI_SET_HWP_ERROR(rc, RC_PMPROC_CHKSLW_EX_NOT_RUNNING);
-            break;
-        }
-
-        // Check PMC LFIR for SLW related bits
-        //      Fatal err (11)
-        //      Status RC (12)
-        //      Status Value(13)
-        //      Write while active (14)
-        //      Timeout (15)
-        FAPI_INF("Checking PMC Local FIR for SLW errors");
-        address = PMC_LFIR_0x01010840;
-        GETSCOM(rc, l_parentTarget, address, data);
-
-        e_rc |= data.extractToRight( &pmc_lfir_slw, 11, 5 );
-        E_RC_CHECK(e_rc, rc);
-
-        FAPI_DBG("\tPMC LFIR = 0x%016llX; pmc_lfir_slw = 0x%08X", data.getDoubleWord(0), pmc_lfir_slw);
-
-        // Non-zero is not good
-        if (pmc_lfir_slw)
-        {
-            FAPI_ERR("PMC LFIR has unexpeced SLW bits on: PMC LFIR = 0x%016llX", data.getDoubleWord(0));
-            const uint64_t& PMCLFIR = data.getDoubleWord(0);
-
-            const uint64_t& GP3     = gp3.getDoubleWord(0);
-            const uint64_t& PMGP0   = pmgp0.getDoubleWord(0);
-            const uint64_t& PMGP1   = pmgp1.getDoubleWord(0);
-            const uint64_t& PMERR   = pmerr.getDoubleWord(0);
-            const uint64_t& EX      = l_ex_number;
-            const fapi::Target& CHIP_IN_ERROR = l_parentTarget;
-
-
-             // XML will dump the SLW registers
-
-            FAPI_SET_HWP_ERROR(rc, RC_PMPROC_CHKSLW_PMC_FIR_ERRORS);
-            break;
-        }
-
-    } while(0);
-    
-    FAPI_INF("Exiting proc_check_slw_done...");
-    return rc;
-}
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.H b/src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.H
deleted file mode 100755
index 73587af88..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.H
+++ /dev/null
@@ -1,82 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_check_slw_done/proc_check_slw_done.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_check_slw_done.H,v 1.3 2014/01/24 19:41:18 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_slw_done.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_check_slw_done.H
-// *! DESCRIPTION :
-// *!
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Michael Olsen Email: cmolsen@us.ibm.coms
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_CHECKSLWDONE_H_
-#define _PROC_CHECKSLWDONE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "p8_pm.H"
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_check_slw_done_FP_t) (  const fapi::Target&);
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Parameter structure definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-/**
- * proc_check_slw_done
- *
- * @param[in] i_target EX target
- *
- * @retval ECMD_SUCCESS
- * @retval ERROR 
- */
-fapi::ReturnCode
-proc_check_slw_done(const fapi::Target& i_ex_target);
-
-
-} // extern "C"
-
-#endif // _PROC_CHECKSLWDONE_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.C b/src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.C
deleted file mode 100644
index ab4651aa6..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.C
+++ /dev/null
@@ -1,172 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_post_winkle.C,v 1.2 2013/07/18 00:45:00 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_post_winkle.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Michael Olsen Email: cmolsen@us.ibm.com
-/// \file proc_post_winkle.C
-/// \brief  Re-enables the standard product idle mode configuration after
-///         an IPL Winkle action
-///
-/// \verbatim
-///
-///     For the passed EX target,
-///         - Remove disable of DISABLE_FORCE_DEEP_TO_FAST_WINKLE that was
-///             set on the master core.  Removing on the non_master cores
-///             is not harmful
-///
-///  Procedure Prereq:
-///     - System clocks are running
-/// \endverbatim
-///
-//------------------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Includes
-// ----------------------------------------------------------------------
-#include "proc_post_winkle.H"
-
-extern "C" {
-
-using namespace fapi;
-
-// ----------------------------------------------------------------------
-// Constant definitions
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Global variables
-// ----------------------------------------------------------------------
-
-// ----------------------------------------------------------------------
-// Function prototypes
-// ----------------------------------------------------------------------
-
-
-// ----------------------------------------------------------------------
-// Function definitions
-// ----------------------------------------------------------------------
-
-
-/**
- * proc_post_winkle
- *
- * @param[in] i_target EX target
- *
- * @retval ECMD_SUCCESS
- * @retval ERROR only those from called functions or MACROs
- */
-fapi::ReturnCode
-proc_post_winkle(const Target& i_ex_target)
-{
-    fapi::ReturnCode    l_rc;
-    uint32_t            rc = 0;
-
-    ecmdDataBufferBase  data(64);
-    uint64_t            address = 0;
-    uint64_t            ex_offset = 0;    
-
-    uint8_t             l_ex_number = 0;
-    fapi::Target        l_parentTarget;
-
-    do
-    {
-
-        FAPI_INF("Beginnning proc_post_winkle...");
-
-        // Get the parent chip to target the PCBS registers
-        l_rc = fapiGetParentChip(i_ex_target, l_parentTarget);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetParentChip access");
-            break;
-        }
-
-        // Get the core number
-        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_ex_target, l_ex_number);
-        if (l_rc)
-        {
-            FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)l_rc);
-            break;
-        }
-
-        FAPI_INF("Processing core %d on %s", l_ex_number, l_parentTarget.toEcmdString());
-        
-        ex_offset = l_ex_number * 0x01000000;
-        
-        // Debug
-        address = EX_PMGP1_0x100F0103 + ex_offset;
-        l_rc = fapiGetScom(l_parentTarget, address, data);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("Scom error reading PMGP1\n");
-            break;
-        }
-        FAPI_DBG("\tBefore PMGP1: 0x%016llX", data.getDoubleWord(0));
-
-        // Enable movement to Fast Winkle if errors are present.  This is
-        // turned off in the during the IPL process
-        rc |= data.flushTo1();
-        rc |= data.clearBit(20);
-        if(rc)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc);
-            l_rc.setEcmdError(rc);
-            break;
-        }
-
-        address = EX_PMGP1_AND_0x100F0104 + ex_offset;
-        l_rc = fapiPutScom(l_parentTarget, address, data);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("Scom error updating PMGP1\n");
-            break;
-        }
-        FAPI_INF("Enabled the conversion of Deep Winkle operations to Fast Winkle if errors are present upon Winkle entry");
-        
-        // Debug
-        address = EX_PMGP1_0x100F0103 + ex_offset;
-        l_rc = fapiGetScom(l_parentTarget, address, data);
-        if(!l_rc.ok())
-        {
-            FAPI_ERR("Scom error reading PMGP1\n");
-            break;
-        }
-        FAPI_DBG("\tAfter  PMGP1: 0x%016llX", data.getDoubleWord(0));
-
-    } while(0);
-
-    FAPI_INF("Exiting proc_post_winkle...");
-    return l_rc;
-}
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.H
deleted file mode 100644
index 15803edeb..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.H
+++ /dev/null
@@ -1,79 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_post_winkle/proc_post_winkle.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_post_winkle.H,v 1.1 2013/06/28 19:47:32 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_post_winkle.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_post_winkle.H
-// *! DESCRIPTION : Re-enables the standard product idle mode configuration after
-// *!               an IPL Winkle action
-// *!
-// *! OWNER NAME  : Greg Still    Email: stillgs@us.ibm.com
-// *! BACKUP NAME : Michael Olsen Email: cmolsen@us.ibm.coms
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_POSTWINKLE_H_
-#define _PROC_POSTWINKLE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "p8_pm.H"
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_post_winkle_FP_t) (const fapi::Target&);
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Parameter structure definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-/// \param[in] i_target EX target
-
-/// \retval ECMD_SUCCESS if something good happens,
-/// \retval BAD_RETURN_CODE otherwise
-fapi::ReturnCode 
-proc_post_winkle(const fapi::Target& i_ex_target);
-
-
-} // extern "C"
-
-#endif // _PROC_POSTWINKLE_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
deleted file mode 100644
index 90895484e..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C
+++ /dev/null
@@ -1,245 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_prep_master_winkle.C,v 1.15 2014/02/10 04:51:31 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_prep_master_winkle.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_prep_master_winkle.C
-// *! DESCRIPTION : Prepares for the master core to winkle
-// *!
-// *! OWNER NAME  : Greg Still              Email: stillgs@us.ibm.com
-// *!
-// *! Overview:
-// *!    Wait for SBE ready
-// *!    Start SBE deadman timer
-// *!    *Enter winkle*
-// *!
-// *!    Note: Hostboot should always run with i_useRealSBE = true
-// *!
-// *!    Here's the flow of SBE_VITAL substeps:
-// *!    SBE (automatic on procedure entry): substep_proc_entry
-// *!    SBE                               : substep_sbe_ready
-// *!    HB (proc_prep_master_winkle)      : substep_deadman_start
-// *!    SBE                               : substep_deadman_waiting_for_winkle
-// *!    SBE                               : substep_deadman_waiting_for_wakeup
-// *!    HB (proc_stop_deadman_timer)      : substep_hostboot_alive_again
-// *!    SBE                   : (stops with error code 0xF to indicate success)
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_prep_master_winkle.H>
-#include <p8_scom_addresses.H>
-#include <p8_istep_num.H>
-#include <proc_sbe_trigger_winkle.H>
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-
-//------------------------------------------------------------------------------
-// function: proc_prep_master_winkle
-//     Wait for SBE ready
-//     Start SBE deadman timer
-//     *Enter winkle*
-//
-// parameters: i_ex_target     => Reference to master chiplet target
-//             i_useRealSBE => True if proc_sbe_trigger_winkle is supposed to be
-//                             running on the real SBE (usually true), else
-//                             false if proc_sbe_trigger_winkle is running on
-//                             the FSP (via poreve).
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-    fapi::ReturnCode proc_prep_master_winkle(const fapi::Target & i_ex_target, 
-                                             const bool & i_useRealSBE)
-    {
-        // data buffer to hold register values
-        ecmdDataBufferBase data(64);
-        ecmdDataBufferBase pmgp1(64);
-
-        // return codes
-        uint32_t                    rc_ecmd = 0;
-        fapi::ReturnCode            rc;
-        
-        // istep/substep umbers
-        uint32_t                    istep_num = 0;
-        uint8_t                     substep_num = 0;
-        
-        // addressing variables
-        uint64_t                    address;
-        uint8_t                     l_ex_number = 0;
-        fapi::Target                l_parentTarget;
-
-        // mark function entry
-        FAPI_INF("Entry, useRealSBE is %s\n", i_useRealSBE? "true":"false");
-
-        do
-        {
-            
-            // Get the parent chip to target the PCBS registers
-            rc = fapiGetParentChip(i_ex_target, l_parentTarget);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetParentChip access");
-                break;
-            }
-                                  
-            // Wait for SBE ready
-            // ie. SBE running, and istep num and substep num correct
-            if( i_useRealSBE )
-            {            
-                rc = fapiGetScom(l_parentTarget, PORE_SBE_CONTROL_0x000E0001, data);
-                if(!rc.ok())
-                {
-                    FAPI_ERR("Scom error reading SBE STATUS\n");
-                    break;
-                }
-                if( data.isBitSet( 0 ) )
-                {
-                    FAPI_ERR("SBE isn't running when it should be\n");
-                    const fapi::Target & CHIP_IN_ERROR = l_parentTarget;
-                    ecmdDataBufferBase & SBE_STATUS = data;
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_PREP_MASTER_WINKLE_SBE_NOT_RUNNING);
-                    break;
-                }
-            }
-
-            rc = fapiGetScom(l_parentTarget, MBOX_SBEVITAL_0x0005001C, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error reading SBE VITAL\n");
-                break;
-            }
-
-            rc_ecmd |= data.extractToRight(&istep_num,
-                                           ISTEP_NUM_BIT_POSITION,
-                                           ISTEP_NUM_BIT_LENGTH);
-            rc_ecmd |= data.extractToRight(&substep_num,
-                                           SUBSTEP_NUM_BIT_POSITION,
-                                           SUBSTEP_NUM_BIT_LENGTH);
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            if( istep_num != PROC_SBE_TRIGGER_WINKLE_ISTEP_NUM )
-            {
-                FAPI_ERR("Expected istep num %llX but found %X\n",
-                         PROC_SBE_TRIGGER_WINKLE_ISTEP_NUM,
-                         istep_num );
-                const fapi::Target & CHIP_IN_ERROR = l_parentTarget;
-                ecmdDataBufferBase & SBE_VITAL = data;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_PREP_MASTER_WINKLE_BAD_ISTEP_NUM);
-                break;
-            }
-            if( substep_num != SUBSTEP_SBE_READY )
-            {
-                FAPI_ERR("Expected substep num %X but found %X\n",
-                         SUBSTEP_SBE_READY,
-                         substep_num );
-                const fapi::Target & CHIP_IN_ERROR = l_parentTarget;
-                ecmdDataBufferBase & SBE_VITAL = data;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_PREP_MASTER_WINKLE_BAD_SUBSTEP_NUM);
-                break;
-            }
-            FAPI_INF("SBE is ready for master to enter winkle\n");
-
-            // Get the core number
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_ex_target, l_ex_number);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetAttribute of ATTR_CHIP_UNIT_POS with rc = 0x%x", (uint32_t)rc);
-                break;
-            }
-
-            FAPI_INF("Processing core %d on %s", l_ex_number, l_parentTarget.toEcmdString());           
-                
-            // Disable movement to Fast Winkle if errors are present
-            rc_ecmd |= pmgp1.flushTo0();
-            rc_ecmd |= pmgp1.setBit(20);
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            address = EX_PMGP1_OR_0x100F0105 + (l_ex_number*0x01000000);
-            rc = fapiPutScom(l_parentTarget, address, pmgp1);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error updating PMGP1\n");
-                break;
-            }
-            FAPI_INF("Disabled the ability to have Deep Winkle turned to Fast Winkle if errors are present\n");  
-          
-
-            //Start the deadman timer
-            substep_num = SUBSTEP_DEADMAN_START;
-            rc_ecmd |= data.insertFromRight(&substep_num,
-                                            SUBSTEP_NUM_BIT_POSITION,
-                                            SUBSTEP_NUM_BIT_LENGTH);
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(l_parentTarget, MBOX_SBEVITAL_0x0005001C, data);
-            if(!rc.ok())
-            {
-                FAPI_ERR("Scom error updating SBE VITAL\n");
-                break;
-            }
-            
-            //Enter winkle
-            FAPI_INF("HB should enter winkle now, FSP should execute proc_force_winkle now\n");
-
-        } while (0);
-
-        // mark function exit
-        FAPI_INF("Exit");
-        return rc;
-    }
-
-} // extern "C"
-/* Local Variables: */
-/* c-basic-offset: 4 */
-/* End: */
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
deleted file mode 100644
index 711c651ae..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H
+++ /dev/null
@@ -1,85 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_prep_master_winkle.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_prep_master_winkle.H,v 1.9 2014/02/10 04:51:32 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_prep_master_winkle.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_prep_master_winkle.H
-// *! DESCRIPTION : Prepares for the master core to winkle
-// *!
-// *! OWNER NAME  : Greg Still              Email: stillgs@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_PREP_MASTER_WINKLE_H_
-#define _PROC_PREP_MASTER_WINKLE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_prep_master_winkle_FP_t)(const fapi::Target &,
-                                                         const bool &);
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * @brief Start the auto-POR engine and the SBE
- *
- * @param[in] i_ex_target  Reference to master chiplet target
- * @param[in] i_useRealSBE True if proc_sbe_trigger_winkle is supposed to be
- *                         running on the real SBE (usually true), else
- *                         false if proc_sbe_trigger_winkle is running on
- *                         the FSP (via poreve).
- *
- * @return ReturnCode
- */
-  fapi::ReturnCode proc_prep_master_winkle(const fapi::Target & i_ex_target,
-                                           const bool & i_useRealSBE);
-
-} // extern "C"
-
-#endif // _PROC_PREP_MASTER_WINKLE_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H b/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H
deleted file mode 100644
index b3b6729b7..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H
+++ /dev/null
@@ -1,51 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_prep_master_winkle/proc_sbe_trigger_winkle.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_trigger_winkle.H,v 1.8 2013/10/18 17:23:48 jeshua Exp $
-
-/// Substep numbers for the proc_sbe_trigger_winkle procedure
-
-#ifndef __PROC_SBE_TRIGGER_WINKLE_H
-#define __PROC_SBE_TRIGGER_WINKLE_H
-
-#include "fapi_sbe_common.H"
-#include "sbe_vital.H"
-
-//NOTE: The following values must stay constant as HB looks for them
-CONST_UINT8_T(SUBSTEP_PROC_ENTRY,                   ULL(0x0));
-CONST_UINT8_T(SUBSTEP_SBE_READY,                    ULL(0x1));
-CONST_UINT8_T(SUBSTEP_DEADMAN_START,                ULL(0x2));
-CONST_UINT8_T(SUBSTEP_DEADMAN_WAITING_FOR_WINKLE,   ULL(0x3));
-CONST_UINT8_T(SUBSTEP_DEADMAN_WAITING_FOR_WAKEUP,   ULL(0x4));
-CONST_UINT8_T(SUBSTEP_DEADMAN_WAITING_FOR_HOSTBOOT, ULL(0x5));
-CONST_UINT8_T(SUBSTEP_HOSTBOOT_ALIVE_AGAIN,         ULL(0x6));
-
-#ifdef __ASSEMBLER__
-// The location in the proc_sbe_trigger_winkle_control
-// containing the mask of threads to start
-//WARNING: if thread_start_vector_start is changed from 16,
-//then the code needs to be updated to shift it to bit 16
-.set THREAD_START_VECTOR_START, 16
-.set THREAD_START_VECTOR_LENGTH, 8
-#endif
-
-#endif  // __PROC_SBE_TRIGGER_WINKLE_H
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_intr_service.H b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_intr_service.H
deleted file mode 100644
index feae59ddb..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_intr_service.H
+++ /dev/null
@@ -1,39 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_intr_service.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_intr_service.H,v 1.2 2015/07/27 00:28:05 jmcgill Exp $
-
-/// Substep numbers for the proc_sbe_intr_service procedure
-
-#ifndef __PROC_SBE_INTR_SERVICE_H
-#define __PROC_SBE_INTR_SERVICE_H
-
-#include "fapi_sbe_common.H"
-#include "sbe_vital.H"
-
-//NOTE: The following values must stay constant as HB looks for them
-CONST_UINT8_T(PROC_SBE_INTR_SERVICE_SUBSTEP_SBE_READY,                    ULL(0x1));
-CONST_UINT8_T(PROC_SBE_INTR_SERVICE_SUBSTEP_HALT_SUCCESS,                 ULL(0xF));
-
-#endif  // __PROC_SBE_INTR_SERVICE_H
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.C b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.C
deleted file mode 100644
index 8bfebd193..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.C
+++ /dev/null
@@ -1,237 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_utils.C,v 1.1 2015/07/27 00:39:15 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_sbe_utils.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_sbe_utils.C
-// *! DESCRIPTION : SBE utility functions
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_sbe_utils.H>
-#include <p8_scom_addresses.H>
-#include <p8_istep_num.H>
-#include <sbe_vital.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-const uint8_t SBE_STOPPED_AT_BREAKPOINT_0xB = 0xB;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-extern "C"
-{
-
-
-fapi::ReturnCode proc_sbe_utils_reset_sbe(
-    const fapi::Target & i_target)
-{
-    ecmdDataBufferBase sbe_reset_data(64);
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    do
-    {
-        rc_ecmd |= sbe_reset_data.flushTo0();
-        rc_ecmd |= sbe_reset_data.setBit(0);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, PORE_SBE_RESET_0x000E0002, sbe_reset_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Scom error resetting SBE");
-            break;
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-fapi::ReturnCode proc_sbe_utils_update_substep(
-    const fapi::Target & i_target,
-    uint8_t i_substep_num)
-{
-    // data buffer to hold register values
-    ecmdDataBufferBase sbe_vital_data(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    do
-    {
-        // read SBE Vital register
-        FAPI_DBG("Checking SBE Vital register");
-        rc = fapiGetScom(i_target, MBOX_SBEVITAL_0x0005001C, sbe_vital_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading SBE Vital register");
-            break;
-        }
-
-        rc_ecmd |= sbe_vital_data.insertFromRight(&i_substep_num,
-                                                  SUBSTEP_NUM_BIT_POSITION,
-                                                  SUBSTEP_NUM_BIT_LENGTH);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, MBOX_SBEVITAL_0x0005001C, sbe_vital_data);
-        if(!rc.ok())
-        {
-            FAPI_ERR("Error updating SBE Vital register");
-            break;
-        }
-    } while(0);
-
-    return(rc);
-}
-
-
-
-fapi::ReturnCode proc_sbe_utils_check_status(
-    const fapi::Target & i_target,
-    bool & o_running,
-    uint8_t & o_halt_code,
-    uint16_t & o_istep_num,
-    uint8_t & o_substep_num)
-{
-    // data buffer to hold register values
-    ecmdDataBufferBase sbe_vital_data(64);
-    ecmdDataBufferBase sbe_control_data(64);
-    ecmdDataBufferBase sbe_status_data(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    do
-    {
-        // read SBE Control register
-        FAPI_DBG("Checking SBE Control register");
-        rc = fapiGetScom(i_target, PORE_SBE_CONTROL_0x000E0001, sbe_control_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading SBE Control register");
-            break;
-        }
-
-        // Bit 0 : 1=stopped, 0=running (or stopped at breakpoint)
-        if (sbe_control_data.isBitClear(0))
-        {
-            o_running = true;
-
-            // if running, check for stopped at breakpoint
-            FAPI_DBG("Checking SBE Status register");
-            rc = fapiGetScom(i_target, PORE_SBE_STATUS_0x000E0000, sbe_status_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error reading SBE Status register");
-                break;
-            }
-
-            uint8_t state = 0;
-            uint64_t address = sbe_status_data.getDoubleWord(0) & 0x0000FFFFFFFFFFFFULL;
-            rc_ecmd |= sbe_status_data.extractToRight(&state, 3, 4);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) extracting data from SBE Status data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            if (state == SBE_STOPPED_AT_BREAKPOINT_0xB)
-            {
-                FAPI_INF("SBE stopped at breakpoint (address 0x%012llX)",
-                         address);
-                o_running = false;
-                break;
-            }
-        }
-        else
-        {
-            o_running = false;
-        }
-
-        // read SBE Vital register
-        FAPI_DBG("Checking SBE Vital register");
-        rc = fapiGetScom(i_target, MBOX_SBEVITAL_0x0005001C, sbe_vital_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading SBE Vital register");
-            break;
-        }
-
-        // parse out halt code & istep progress information
-        o_halt_code = 0;
-        o_istep_num = 0;
-        o_substep_num = 0;
-        rc_ecmd |= sbe_vital_data.extractToRight(&o_halt_code,
-                                                 HALT_CODE_BIT_POSITION,
-                                                 HALT_CODE_BIT_LENGTH);
-        rc_ecmd |= sbe_vital_data.extractToRight(&o_istep_num,
-                                                 ISTEP_NUM_BIT_POSITION,
-                                                 ISTEP_NUM_BIT_LENGTH);
-        rc_ecmd |= sbe_vital_data.extractToRight(&o_substep_num,
-                                                 SUBSTEP_NUM_BIT_POSITION,
-                                                 SUBSTEP_NUM_BIT_LENGTH);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error (0x%x) extracting data from SBE Vital data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-    } while(0);
-
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.H b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.H
deleted file mode 100644
index 4a45dc95a..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.H
+++ /dev/null
@@ -1,96 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_sbe_utils.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_utils.H,v 1.1 2015/07/27 00:39:15 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_sbe_utils.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_sbe_utils.H
-// *! DESCRIPTION : SBE utility functions
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_SBE_UTILS_H_
-#define _PROC_SBE_UTILS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-/**
- * @brief Reset SBE engine
- *
- * @param[in] i_target Reference to chip target
- * @return ReturnCode
- */
-fapi::ReturnCode proc_sbe_utils_reset_sbe(
-    const fapi::Target & i_target);
-
-/**
- * @brief Update SBE Vital register with substep progress code
- *
- * @param[in] i_target Reference to chip target
- * @param[in] i_substep_num Substep progress code to write
- * @return ReturnCode
- */
-fapi::ReturnCode proc_sbe_utils_update_substep(
-    const fapi::Target & i_target,
-    uint8_t i_substep_num);
-
-/**
- * @brief Determine SBE run state and istep progress
- *
- * @param[in] i_target Reference to chip target
- * @param[out] o_running Is SBE running or stopped?
- * @param[out] o_halt_code SBE halt code (only valid if SBE stopped)
- * @param[out] o_istep_num Current istep number (0xMmm)
- * @param[out] o_substep_num Current substep within istep
- * @return ReturnCode
- */
-fapi::ReturnCode proc_sbe_utils_check_status(
-    const fapi::Target & i_target,
-    bool & o_running,
-    uint8_t & o_halt_code,
-    uint16_t & o_istep_num,
-    uint8_t & o_substep_num);
-
-
-} // extern "C"
-
-#endif // _PROC_SBE_UTILS_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
deleted file mode 100644
index 32f38f971..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C
+++ /dev/null
@@ -1,307 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_stop_deadman_timer.C,v 1.14 2015/08/04 19:56:09 thi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_deadman_timer.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_stop_deadman_timer.C
-// *! DESCRIPTION : Stops deadman timer
-// *!
-// *! OWNER NAME  : Greg Still              Email: stillgs@us.ibm.com
-// *!
-// *! Overview:
-// *!    Notify SBE that HB is alive again
-// *!    Conditionally stop the SBE
-// *!
-// *!    Here's the flow of SBE_VITAL substeps:
-// *!    SBE (automatic on procedure entry): substep_proc_entry
-// *!    SBE                               : substep_sbe_ready
-// *!    HB (proc_prep_master_winkle)      : substep_deadman_start
-// *!    SBE                               : substep_deadman_waiting_for_winkle
-// *!    SBE                               : substep_deadman_waiting_for_wakeup
-// *!    HB (proc_stop_deadman_timer)      : substep_hostboot_alive_again
-// *!    SBE                   : (stops with error code 0xF to indicate success)
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_stop_deadman_timer.H>
-#include <p8_scom_addresses.H>
-#include <p8_istep_num.H>
-#include <proc_sbe_trigger_winkle.H>
-#include <proc_sbe_intr_service.H>
-#include <proc_sbe_utils.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-const uint64_t NS_TO_FINISH = 10000000; //(10 ms)
-const uint64_t MS_TO_FINISH = NS_TO_FINISH/1000000;
-const uint64_t SIM_CYCLES_TO_FINISH = 10000000;
-
-const uint64_t MAX_WAIT_TIME_MS = 1000;
-
-const uint8_t  SBE_EXIT_SUCCESS_0xF = 0xF;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-fapi::ReturnCode proc_stop_deadman_timer(const fapi::Target & i_target,
-                                         bool & o_intr_service_running)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_INF("Start");
-
-    do
-    {
-        //
-        // check SBE progress
-        //
-
-        // given this procedure is running, the SBE deadman function should have worked
-        // check that the SBE VITAL reached the correct spot
-        bool sbe_running;
-        size_t loop_time = 0;
-        uint8_t halt_code;
-        uint16_t istep_num;
-        uint8_t substep_num;
-        bool intr_service_loop_reached = false;
-        rc = proc_sbe_utils_check_status(
-            i_target,
-            sbe_running,
-            halt_code,
-            istep_num,
-            substep_num);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from proc_check_sbe_state_check_status");
-            break;
-        }
-
-        if (!(sbe_running &&
-              !halt_code &&
-              (istep_num == proc_sbe_trigger_winkle_istep_num) &&
-              (substep_num == SUBSTEP_DEADMAN_WAITING_FOR_HOSTBOOT)))
-        {
-            FAPI_ERR("Expected istep/substep num %llX/%X but found %X/%X",
-                     proc_sbe_trigger_winkle_istep_num,
-                     SUBSTEP_DEADMAN_WAITING_FOR_HOSTBOOT,
-                     istep_num,
-                     substep_num);
-            const fapi::Target & CHIP_IN_ERROR = i_target;
-            const bool & SBE_RUNNING = sbe_running;
-            const uint8_t & HALT_CODE = halt_code;
-            const uint16_t & ISTEP_NUM = istep_num;
-            const uint8_t & SUBSTEP_NUM = substep_num;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_DEADMAN_TIMER_UNEXPECTED_INITIAL_STATE);
-            fapiLogError(rc);
-        }
-
-        //
-        // send SBE message -- HOSTBOOT_ALIVE_AGAIN
-        //
-
-        rc = proc_sbe_utils_update_substep(
-            i_target,
-            SUBSTEP_HOSTBOOT_ALIVE_AGAIN);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from proc_sbe_utils_update_substep");
-            break;
-        }
-
-        //
-        // Loop until:
-        //   SBE stopped OR
-        //   interrupt serivce ready loop is reached OR
-        //   loop time is exceeded
-        //
-
-        while (sbe_running &&
-               !intr_service_loop_reached &&
-               (loop_time < MAX_WAIT_TIME_MS))
-        {
-            // sleep 10ms, then check again
-            loop_time += MS_TO_FINISH;
-            rc = fapiDelay(NS_TO_FINISH, SIM_CYCLES_TO_FINISH);
-            if (rc)
-            {
-                FAPI_ERR("Error from fapiDelay");
-                break;
-            }
-
-            // retrieve status
-            rc = proc_sbe_utils_check_status(
-                i_target,
-                sbe_running,
-                halt_code,
-                istep_num,
-                substep_num);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_check_sbe_state_check_status");
-                break;
-            }
-
-            intr_service_loop_reached =
-                sbe_running &&
-                !halt_code &&
-                (istep_num == PROC_SBE_INTR_SERVICE_ISTEP_NUM) &&
-                (substep_num == SUBSTEP_SBE_READY);
-        }
-
-        // break if we took an error in the while loop
-        if (rc)
-        {
-            break;
-        }
-
-        FAPI_INF("SBE is running [%d], loop time [%zd], interrupt service loop reached [%d]",
-                 sbe_running, loop_time, intr_service_loop_reached);
-
-        // ensure correct halt code is captured
-        if (!sbe_running)
-        {
-            rc = proc_sbe_utils_check_status(
-                i_target,
-                sbe_running,
-                halt_code,
-                istep_num,
-                substep_num);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_check_sbe_state_check_status");
-                break;
-            }
-        }
-
-        // handle three valid possibilities:
-        // 1) SBE stopped at end of deadman timer routine (SBE code supports interrupt service, but the service is not enabled)
-        // 2) SBE is running interrupt service routine (SBE code supports interrupt service, and the service is enabled)
-        // 3) SBE is still running deadman timer routine (SBE code does not support interrupt service)
-        // If not in one of those 3 expected states, error out
-        if (!sbe_running &&
-            (halt_code == SBE_EXIT_SUCCESS_0xF) &&
-            (istep_num == proc_sbe_trigger_winkle_istep_num) &&
-            (substep_num == SUBSTEP_HOSTBOOT_ALIVE_AGAIN))
-        {
-            FAPI_INF("SBE halted at end of deadman timer routine, interrupt service is NOT running!");
-            o_intr_service_running = false;
-
-            // reset the SBE so it can be used for MPIPL if needed
-            rc = proc_sbe_utils_reset_sbe(i_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_sbe_utils_reset_sbe");
-                break;
-            }
-        }
-        else if (intr_service_loop_reached)
-        {
-            FAPI_INF("SBE finished deadman timer routine, interrupt service is running!");
-            o_intr_service_running = true;
-        }
-        else if ( (sbe_running) &&
-                  (istep_num == proc_sbe_trigger_winkle_istep_num) &&
-                  (substep_num == SUBSTEP_HOSTBOOT_ALIVE_AGAIN) )
-         
-        {
-            FAPI_INF("SBE is still running but not SBE interrupt.  Stop and "
-                     "reset the SBE!");
-
-            // Stop the SBE
-            ecmdDataBufferBase data(64);
-            rc = fapiGetScom(i_target, PORE_SBE_CONTROL_0x000E0001, data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error returned from fapiGetScom, addr 0x%.16llX ",
-                         PORE_SBE_CONTROL_0x000E0001);
-                break;
-            }
-            rc_ecmd |= data.setBit( 0 );
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            rc = fapiPutScom(i_target, PORE_SBE_CONTROL_0x000E0001, data);
-            if ( !rc.ok() )
-            {
-                FAPI_ERR("Error returned from fapiPutScom to stop "
-                         "SBE, addr 0x%.16llX", PORE_SBE_CONTROL_0x000E0001);
-                break;
-            }
-
-            // Reset the SBE
-            rc = proc_sbe_utils_reset_sbe(i_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_sbe_utils_reset_sbe");
-                break;
-            }
-
-            // Set flag to indicate SBE interrupt is not running
-            o_intr_service_running = false;
-        }
-        // error
-        else
-        {
-            FAPI_ERR("SBE did not reach acceptable final state!");
-            const fapi::Target & CHIP_IN_ERROR = i_target;
-            const bool & SBE_RUNNING = sbe_running;
-            const uint8_t & HALT_CODE = halt_code;
-            const uint16_t & ISTEP_NUM = istep_num;
-            const uint8_t & SUBSTEP_NUM = substep_num;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_DEADMAN_TIMER_UNEXPECTED_FINAL_STATE);
-            break;
-        }
-
-    } while (0);
-
-    // mark function exit
-    FAPI_INF("Exit");
-    return rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H b/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H
deleted file mode 100644
index 2db6de18b..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer/proc_stop_deadman_timer.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_stop_deadman_timer.H,v 1.4 2015/07/27 00:44:20 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_deadman_timer.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_stop_deadman_timer.H
-// *! DESCRIPTION : Stops deadman timer
-// *!
-// *! OWNER NAME  : Greg Still              Email: stillgs@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_STOP_DEADMAN_TIMER_H_
-#define _PROC_STOP_DEADMAN_TIMER_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_stop_deadman_timer_FP_t)(const fapi::Target &,
-                                                         bool &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * @brief Stop the deadman timer
- *
- * @param[in] i_target  Reference to chip target
- * @param[out] o_intr_service_running Indicates state of interrupt service
- *
- * @return ReturnCode
- */
-fapi::ReturnCode proc_stop_deadman_timer(const fapi::Target & i_target,
-                                         bool & o_intr_service_running);
-
-} // extern "C"
-
-#endif // _PROC_STOP_DEADMAN_TIMER_H_
diff --git a/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.C b/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.C
deleted file mode 100755
index 05a9e5cc1..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.C
+++ /dev/null
@@ -1,480 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_switch_cfsim.C,v 1.7 2012/05/03 10:41:46 rkoester Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_cfsim.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_switch_cfsim.C
-// *! DESCRIPTION : Configure the PLLs
-// *!
-// *! OWNER NAME  : Ralph C. Koester         Email: rkoester@de.ibm.com
-// *! Backup      : Todd A. Venton           Email: venton@us.ibm.com
-// *!
-// *!
-// *! General Description:
-// *!
-// *!   The purpose of this procedure is to reset fences in CFAM
-// *!
-// *!   via the mailbox register of the PIB
-// *!
-// *!   set the sbetrigger reg via SCOM write
-// *|
-// *! Procedure Prereq : none
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_switch_cfsim.H"
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// parameters: io_data       => Input data buffer
-//             i_reset       => Input parameter (RESET)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_reset_fence(ecmdDataBufferBase & io_data, bool i_RESET)
-{
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_reset_fence: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, RESET=%s\n\n" ,
-             i_RESET? "true":"false");
-
-    do
-    {
-
-       if(i_RESET==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.clearBit(3,3);
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_reset_fence: Error 0x%x setting up data buffer to RESET all fences",
-                 rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-       }
-
-    } while(0);
-
-    FAPI_DBG("proc_reset_fence: End");
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// parameters: io_data            => Input data buffer
-//             i_reset_opb_switch => Input parameter (RESET_OPB_SWITCH)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_reset_opb( ecmdDataBufferBase & io_data,
-                                 bool i_RESET_OPB_SWITCH)
-{
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_reset_opb: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, RESET_OPB_SWITCH=%s\n\n" ,
-             i_RESET_OPB_SWITCH? "true":"false");
-
-
-    do
-    {
-
-       if(i_RESET_OPB_SWITCH==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.setBit(1);
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_reset_opb: Error 0x%x setting up data buffer to RESET both  OPB switches",
-                    rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-       }
-
-    } while(0);
-
-    FAPI_DBG("proc_reset_opb: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// // parameters: io_data       => Input data buffer
-//                i_fence_fsi0  => Input parameter (FENCE_FSI0)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fence_fsi0( ecmdDataBufferBase & io_data,
-                                  bool i_FENCE_FSI0)
-{
-
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_fence_fsi0: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, FENCE_FSI0=%s\n\n" ,
-             i_FENCE_FSI0? "true":"false");
-
-
-    do
-    {
-
-       if(i_FENCE_FSI0==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.setBit(3);
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_fence_fsi0: Error 0x%x setting up data buffer to bring-up the fence for FSI0 port",
-                    rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-    }
-
-    } while(0);
-
-    FAPI_DBG("proc_fence_fsi0: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// parameters: io_data         => Input data buffer
-//             i_fence_pib_nh  => Input parameter (FENCE_PIB_NH)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_pib_nh( ecmdDataBufferBase & io_data,
-                              bool i_FENCE_PIB_NH)
-{
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_pib_nh: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, FENCE_PIB_NH=%s\n\n" ,
-             i_FENCE_PIB_NH? "true":"false");
-
-
-    do
-    {
-
-       if(i_FENCE_PIB_NH==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.setBit(4);
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_pib_nh: Error 0x%x setting up data buffer to bring-up the fence for the none HOST PIB port",
-                    rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-    }
-
-    } while(0);
-
-    FAPI_DBG("proc_pib_nh: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// parameters: io_data        => Input data buffer
-//             i_fence_pib_h  => Input parameter (FENCE_PIB_H)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_pib_h( ecmdDataBufferBase & io_data,
-                             bool i_FENCE_PIB_H)
-{
-
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_pib_h: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, FENCE_PIB_H=%s\n\n" ,
-             i_FENCE_PIB_H? "true":"false");
-
-
-    do
-    {
-
-       if(i_FENCE_PIB_H==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.setBit(5);
-         FAPI_DBG("data set bit done");
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_pib_h: Error 0x%x setting up data buffer to bring-up the fence for the HOST PIB port",
-                    rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-       }
-
-    } while(0);
-
-    FAPI_DBG("proc_pib_h: End");
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// parameters: io_data       => Input data buffer
-//             i_fence_fsi1  => Input parameter (FENCE_FSI1)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fence_fsi1( ecmdDataBufferBase & io_data,
-                                  bool i_FENCE_FSI1)
-{
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-
-    FAPI_DBG("proc_fence_fsi1: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, FENCE_FSI1=%s\n\n" ,
-             i_FENCE_FSI1? "true":"false");
-
-    do
-    {
-
-       if(i_FENCE_FSI1==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.setBit(6);
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_fence_fsi1: Error 0x%x setting up data buffer to bring-up the fence for the FSI-1 port",
-                    rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-       }
-
-    } while(0);
-
-    FAPI_DBG("proc_fence_fsi1: End");
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manipulate GP4 of CFAM via MBOX
-// parameters: io_data          => Input data buffer
-//             i_fence_pib_sw1  => Input parameter (FENCE_PIB_SW1)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_pib_sw1( ecmdDataBufferBase & io_data ,
-                               bool i_FENCE_PIB_SW1)
-{
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_pib_sw1: Start");
-
-    // mark function entry
-    FAPI_INF("Entry, FENCE_PIB_SW1=%s\n\n" ,
-             i_FENCE_PIB_SW1? "true":"false");
-
-//  // temporary for debug only
-//  if (i_FENCE_PIB_SW1==true) { FAPI_DBG(" Debug only, print: FENCE_PIB_SW1==true ");}
-//  else { FAPI_DBG(" Debug only, print: FENCE_PIB_SW1==false ") ; }
-
-
-    do
-    {
-
-       if(i_FENCE_PIB_SW1==true){
-         // manipulate external buffer
-         rc_ecmd |= io_data.setBit(7);
-       }
-       if (rc_ecmd)
-       {
-           FAPI_ERR("proc_pib_sw1: Error 0x%x setting up data buffer to bring-up the PIB_SW1 fence",
-                    rc_ecmd);
-           rc.setEcmdError(rc_ecmd);
-           break;
-       }
-
-    } while(0);
-
-    FAPI_DBG("proc_pib_sw1: End");
-
-    return rc;
-}
-//------------------------------------------------------------------------------
-// Hardware Procedure
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_switch_cfsim(const fapi::Target& i_target,
-                                   bool RESET,
-                                   bool RESET_OPB_SWITCH,
-                                   bool FENCE_FSI0,
-                                   bool FENCE_PIB_NH,
-                                   bool FENCE_PIB_H,
-                                   bool FENCE_FSI1,
-                                   bool FENCE_PIB_SW1)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase manipulate(64);
-
-    // mark HWP entry
-    FAPI_INF("proc_switch_cfsim: Entering ...");
-
-    do
-    {
-       rc = fapiGetScom(i_target, MBOX_FSIGP4_0x00050013, manipulate);
-       if (rc)
-       {
-            FAPI_ERR("proc_switch_cfsim: fapiGetScom error (MBOX_FSIGP4_0x00050013)");
-            break;
-       }
-
-        // start manipulation based on parsed inputs
-
-        FAPI_DBG("Starting manipulating the fences ...");
-
-        rc = proc_reset_fence(
-             manipulate,
-             RESET);
-             if (rc)
-             {
-                break;
-             }
-
-        rc = proc_reset_opb(
-             manipulate,
-             RESET_OPB_SWITCH);
-             if (rc)
-             {
-                break;
-             }
-
-        rc = proc_fence_fsi0(
-             manipulate,
-             FENCE_FSI0);
-             if (rc)
-             {
-                break;
-             }
-
-        rc = proc_pib_nh(
-             manipulate,
-             FENCE_PIB_NH);
-             if (rc)
-             {
-                break;
-             }
-
-        rc = proc_pib_h(
-             manipulate,
-             FENCE_PIB_H);
-             if (rc)
-             {
-                break;
-             }
-
-        rc = proc_fence_fsi1(
-             manipulate,
-             FENCE_FSI1);
-             if (rc)
-             {
-                break;
-             }
-
-        rc = proc_pib_sw1(
-             manipulate,
-             FENCE_PIB_SW1);
-             if (rc)
-             {
-                break;
-             }
-
-        FAPI_DBG("proc_switch_cfsim: manipulating the fences done.");
-
-
-       rc = fapiPutScom(i_target, MBOX_FSIGP4_0x00050013, manipulate);
-       if (rc)
-       {
-            FAPI_ERR("proc_switch_cfsim: fapiPutScom error (MBOX_FSIGP4_0x00050013)");
-            break;
-       }
-
-
-
-    } while (0); // end do
-
-        // mark function exit
-        FAPI_INF("proc_switch_cfsim: Exiting ...");
-        return rc;
-}  // end FAPI procedure proc_switch_cfsim
-
-} // extern "C"
-/* Local Variables: */
-/* c-basic-offset: 4 */
-/* End: */
diff --git a/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H b/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H
deleted file mode 100755
index 828b6af91..000000000
--- a/src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H
+++ /dev/null
@@ -1,112 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/proc_switch_cfsim/proc_switch_cfsim.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_switch_cfsim.H,v 1.4 2014/03/18 12:37:57 bgeukes Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_cfsim.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : p8_switch_cfsim.H
-// *! DESCRIPTION : (FAPI)
-// *!
-// *! OWNER NAME  : Ralph Koester Email: rkoester@de.ibm.com
-// *! BACKUP NAME : Gebhard Weber Email: gweber@de.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-// *!               this is a function pointer of p8_switch_cfsim.C
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _P8_SWITCH_CFSIM_H_
-#define _P8_SWITCH_CFSIM_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-
-typedef fapi::ReturnCode
-(*proc_switch_cfsim_FP_t)(const fapi::Target&, bool, bool, bool, bool, bool,
-                          bool, bool);
-
-
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-
-/**
- * @brief access GP4 of CFAM via MBOX
- *
- * @param[in] i_target     Processor Chip Target (Murano, Venice)
- * @param[in] RESET        True if all fences should be reset
- * @param[in] RESETOPB     Reset both OPB switches
- * @param[in] FENCEFSI0    Fence port FSI-0
- * @param[in] FENCEPIBnh   Fence PIB none HOST PIB port
- * @param[in] FENCEPIBh    Fence HOST PIB port
- * @param[in] FENCEFSI1    Fence Port FSI-1
- * @param[in] FENCEPIBSW1  fence PIB por
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode proc_switch_cfsim(const fapi::Target& i_target,
-                                   bool i_RESET,
-                                   bool i_RESET_OPB_SWITCH,
-                                   bool i_FENCE_FSI0,
-                                   bool i_FENCE_PIB_NH,
-                                   bool i_FENCE_PIB_H,
-                                   bool i_FENCE_FSI1,
-                                   bool i_FENCE_PIB_SW1);
-
-} // extern "C"
-
-
-#endif // _PROC_SWITCH_CFSIM_H_
-
-
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C
deleted file mode 100644
index a81d58c36..000000000
--- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C
+++ /dev/null
@@ -1,126 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_switch_rec_attn.C,v 1.4 2013/03/04 17:56:36 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_switch_rec_attn.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_switch_rec_attn
-// *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attns and special attns to the FSP.
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! SCREEN      : pervasive_screen
-// #! ADDITIONAL COMMENTS : See inline comments below.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <cen_switch_rec_attn.H>
-
-//  Constants
-const uint8_t RECOV_ERR_IPOLL_MASK_BIT = 5;
-const uint8_t SPEC_ATTN_IPOLL_MASK_BIT = 6;
-
-extern "C" {
-
-using namespace fapi;
-
-fapi::ReturnCode cen_switch_rec_attn(const fapi::Target & i_target)
-{
-    // Target is centaur
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase scom_data(64);
-
-
-    FAPI_INF("********* cen_switch_rec_attn start *********");
-    do
-    {
-
-        // Clear bit 5 in the IPOLL Mask Register 0x01020013 to unmask the recoverable errors going to FSI and DMI.
-        // Clear bit 6 in the IPOLL Mask Register 0x01020013 to unmask the special attn interrupts going to FSI and DMI.
-        // Note: In Centaur the outputs of the ITR Macro go to both the FSI and to the DMI.
-        //       The "HostBridge" mentioned in the P8 Pervasive Workbook is NOT the DMI path.
-        //       In Centaur the IPOLL Mask bits 0-3 to not do anything.
-        //       In Centaur the IPOLL Mask bits 4-7 controll signals going to BOTH FSI and DMI.
-        FAPI_DBG("Writing IPOLL Mask Register 0x01020013 to clear bit 5 and 6 (to unmask recov errs and spc attns) ...");
-        rc = fapiGetScom( i_target, TP_IPOLL_MSK_0x01020013, scom_data);
-        if ( rc )
-        {
-            FAPI_ERR("Error reading Interrupt IPOLL Mask Reg 0x01020013.");
-            break;
-        }
-        rc_ecmd |= scom_data.clearBit(RECOV_ERR_IPOLL_MASK_BIT);
-        rc_ecmd |= scom_data.clearBit(SPEC_ATTN_IPOLL_MASK_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write Interrupt IPOLL Mask Register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_IPOLL_MSK_0x01020013, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing Interrupt IPOLL Mask Reg 0x01020013.");
-            break;
-        }
-
-
-    } while(0);
-
-
-    FAPI_INF("********* cen_switch_rec_attn complete *********");
-    return rc;
-}
-
-} //end extern C
-
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: cen_switch_rec_attn.C,v $
-Revision 1.4  2013/03/04 17:56:36  mfred
-Add some header comments for BACKUP and SCREEN.
-
-Revision 1.3  2013/01/18 17:18:31  mfred
-Clear mask to allow special attentions to go to FSP, along with recoverables.
-
-Revision 1.2  2012/12/13 22:54:32  mfred
-Update to remove unneeded commands and unmask recoverable path to FSI.
-
-Revision 1.1  2012/12/10 22:39:02  mfred
-Adding new procedure cen_switch_rec_attn.
-
-
-*/
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H
deleted file mode 100644
index 676e39eac..000000000
--- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H
+++ /dev/null
@@ -1,71 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/cen_switch_rec_attn.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_switch_rec_attn.H,v 1.1 2012/12/10 22:39:06 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_switch_rec_attn.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_switch_rec_attn.H
-// *! DESCRIPTION : The purpose of this procedure is to route Centaur recoverable attentions to the FSP instead of to the P8 host.
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-//
-// Header file for cen_switch_rec_attn.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.0    | mfred    | 05/30/12| Initial creation
-
-#ifndef CEN_SWITCH_REC_ATTNHWPB_H_
-#define CEN_SWITCH_REC_ATTNHWPB_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*cen_switch_rec_attn_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-    // Target is centaur
-
-/**
- * @brief cen_switch_rec_attn procedure.  The purpose of this procedure is to route Centaur recoverable attentions to the FSP instead of to the P8 host.
- *
- * @param[in]  i_target  Reference to centaur target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode cen_switch_rec_attn(const fapi::Target& i_target);
-    // Target is centaur
-
-} // extern "C"
-
-#endif // CEN_SWITCH_REC_ATTNHWPB_H_
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
deleted file mode 100644
index 738e0118d..000000000
--- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C
+++ /dev/null
@@ -1,201 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_switch_rec_attn.C,v 1.3 2013/11/25 17:13:06 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_rec_attn.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_switch_rec_attn.C
-// *! DESCRIPTION : The purpose of this procedure is to mask Centaur recoverable attentions from the host
-// *!               (At this point in the IPL process those attentions should be routed to the FSP.)
-// *!
-// *! OWNER NAME  : Mark Fredrickson     Email: mfred@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_switch_rec_attn.H>
-#include <fapi.H>
-
-
-using namespace fapi;
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// MCS MCI FIR bit/field definitions
-const uint8_t MCI_CENTAUR_CHECKSTOP_BIT  = 12;
-const uint8_t MCI_CENTAUR_RECOV_ERR_BIT  = 15;
-const uint8_t MCI_CENTAUR_SPEC_ATTN_BIT  = 16;
-const uint8_t MCI_CENTAUR_MAINT_COMP_BIT = 17;
-
-
-//------------------------------------------------------------------------------
-// Function definition
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-    //------------------------------------------------------------------------------
-    // function:  mask Centaur recoverable attentions from the host
-    //
-    // parameters: i_target       =>   MCS chiplet of processor chip
-    // returns: FAPI_RC_SUCCESS if operation was successful, else error
-    //------------------------------------------------------------------------------
-    fapi::ReturnCode proc_switch_rec_attn(const fapi::Target & i_target)
-    {
-        // data buffer to hold register values
-        ecmdDataBufferBase scom_data(64);
-
-        // return codes
-        uint32_t rc_ecmd = 0;
-        fapi::ReturnCode rc;
-
-
-
-        // mark function entry
-        FAPI_INF("********* Starting proc_switch_rec_attn *********");
-        do
-        {
-
-            // Mask the following FIR bits that came over from Centaur
-            // MCS_MCIFIR(12,15,16,17)
-            // The FIR bits are in the MCS MCIFIR register (02011840 is the first instance)
-            // The FIR masks are in the MCS MCIFIRMASK reg (02011843 is the first instance)
-            FAPI_INF("Mask OFF the MCI FIR bits 12,15,16,17 coming from Centaur.\n");
-            rc = fapiGetScom(i_target, MCS_MCIFIRMASK_0x02011843, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (MCS_MCIFIRMASK_0x02011843)");
-                break;
-            }
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_CHECKSTOP_BIT);
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_RECOV_ERR_BIT);
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_SPEC_ATTN_BIT);
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_MAINT_COMP_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to mask the MCI FIR bits", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, MCS_MCIFIRMASK_0x02011843, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiPutScom error (MCS_MCIFIRMASK_0x02011843)");
-                break;
-            }
-
-
-            // Marc Gollub also suggested that the action bits for these signals should be set to recoverable attention (A0=0, A1=1)
-            // The action0 bits are in the MCS MCIFIRACT0 reg (02011846 is the first instance)
-            // The action1 bits are in the MCS MCIFIRACT1 reg (02011847 is the first instance)
-            FAPI_INF("Set MCS MCI ACTION0 bits 12,15,16,17 to zero in MCS_MCIFIRACT0_0x02011846.\n");
-            rc = fapiGetScom(i_target, MCS_MCIFIRACT0_0x02011846, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (MCS_MCIFIRACT0_0x02011846)");
-                break;
-            }
-            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_CHECKSTOP_BIT);
-            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_RECOV_ERR_BIT);
-            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_SPEC_ATTN_BIT);
-            rc_ecmd |= scom_data.clearBit(MCI_CENTAUR_MAINT_COMP_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to clear action bits in MCS_MCIFIRACT0_0x02011846", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, MCS_MCIFIRACT0_0x02011846, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiPutScom error (MCS_MCIFIRACT0_0x02011846)");
-                break;
-            }
-
-            FAPI_INF("Set MCS MCI ACTION1 bits 12,15,16,17 to one in MCS_MCIFIRACT1_0x02011847.\n");
-            rc = fapiGetScom(i_target, MCS_MCIFIRACT1_0x02011847, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (MCS_MCIFIRACT1_0x02011847)");
-                break;
-            }
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_CHECKSTOP_BIT);
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_RECOV_ERR_BIT);
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_SPEC_ATTN_BIT);
-            rc_ecmd |= scom_data.setBit(MCI_CENTAUR_MAINT_COMP_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to set action bits in MCS_MCIFIRACT1_0x02011847", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, MCS_MCIFIRACT1_0x02011847, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiPutScom error (MCS_MCIFIRACT1_0x02011847)");
-                break;
-            }
-
-
-        } while (0); // end do
-
-        // mark function exit
-        FAPI_INF("********* proc_switch_rec_attn complete *********");
-        return rc;
-    }  // end FAPI procedure proc_switch_rec_attn
-
-} // extern "C"
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: proc_switch_rec_attn.C,v $
-Revision 1.3  2013/11/25 17:13:06  mfred
-Change include statements to avoid problems.  (From Gerrit review.)
-
-Revision 1.2  2013/04/12 19:23:36  mfred
-Avoid clearing bit 18 of the MCIFIRMASK by reading the reg first. (Fix for SW197032).
-
-Revision 1.1  2012/12/10 20:38:04  mfred
-Committing new procedure proc_switch_rec_attn.
-
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H b/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H
deleted file mode 100644
index 918ef67c3..000000000
--- a/src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H
+++ /dev/null
@@ -1,77 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/core_activate/switch_rec_attn/proc_switch_rec_attn.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_switch_rec_attn.H,v 1.1 2012/12/10 20:38:07 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_switch_rec_attn.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_switch_rec_attn.H
-// *! DESCRIPTION : The purpose of this procedure is to mask Centaur recoverable attentions from the host
-// *!               (At this point in the IPL process those attentions should be routed to the FSP.)
-// *!
-// *! OWNER NAME  : Mark Fredrickson     Email: mfred@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_SWITCH_REC_ATTN_H_
-#define _PROC_SWITCH_REC_ATTN_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_switch_rec_attn_FP_t)(const fapi::Target &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-/**
- * @brief proc_switch_rec_attn procedure.  The purpose of this procedure is to mask Centaur recoverable attentions from the host.
- *
- * @param[in]  i_target  Reference to pu.mcs target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode proc_switch_rec_attn(const fapi::Target & i_target);
-    // Target is pu.mcs
-
-} // extern "C"
-
-#endif // _PROC_SWITCH_REC_ATTN_H_
diff --git a/src/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.C b/src/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.C
deleted file mode 100644
index 98f9bf92e..000000000
--- a/src/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.C
+++ /dev/null
@@ -1,842 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dimmBadDqBitmapAccessHwp.C $                 */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: dimmBadDqBitmapAccessHwp.C,v 1.16 2015/04/22 20:09:16 cswenson Exp $
-/**
- *  @file dimmBadDqBitmapAccessHwp.C
- *
- *  @brief FW Team HWP that accesses the Bad DQ Bitmap.
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     02/17/2012  Created.
- *                          mjjones     01/30/2013  Cope with platform endian
- *                                                  differences
- *                          dedahle     06/22/2013  Show unconnected DQ lines
- *                          dedahle     09/20/2013  Temporarily use
- *                                                  ATTR_EFF_DIMM_SPARE
- *                          dedahle     09/20/2013  Support manufacturing mode
- *                          dedahle     10/11/2013  Add memset for gcc version
- *                                                  constructor syntax issue
- *                          dedahle     12/01/2013  Fix
- *                                                  dimmUpdateDqBitmapSpareByte
- *                                                  to not set bits for
- *                                                  connected DQs
- *                          dedahle     01/08/2014  Switch back to reading
- *                                                  ATTR_VPD_DIMM_SPARE
- *                          smcprek     01/14/2014  Perform Reconfig Loop on
- *                                                  Bad DQ set
- *                          whs         02/24/2014  Capture bad DQs as FFDC
- *                                                  in mnfg error logs
- *                          whs         03/27/2014  fix current FFDC bit map
- *                          cswenson    04/22/2014  fix spare byte translate
- */
-
-#include <dimmBadDqBitmapAccessHwp.H>
-#include <config.h>
-
-// DQ Data format in DIMM SPD
-const uint32_t DIMM_BAD_DQ_MAGIC_NUMBER = 0xbadd4471;
-const uint8_t DIMM_BAD_DQ_VERSION = 1;
-const uint8_t ECC_DQ_BYTE_NUMBER_INDEX = 8;
-const uint8_t SPARE_DRAM_DQ_BYTE_NUMBER_INDEX = 9;
-
-struct dimmBadDqDataFormat
-{
-    uint32_t iv_magicNumber;
-    uint8_t  iv_version;
-    uint8_t  iv_reserved1;
-    uint8_t  iv_reserved2;
-    uint8_t  iv_reserved3;
-    uint8_t  iv_bitmaps[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE];
-};
-
-extern "C"
-{
-
-/**
- * @brief Returns bits for unconnected spare DRAM.
- *
- *
- * @param[in] i_mba       Reference to MBA Target.
- * @param[in] i_dimm      Reference to DIMM Target.
- * @param[o]  o_spareByte Reference to the spare byte returned to caller.
- *
- * @return ReturnCode
- */
-fapi::ReturnCode dimmGetDqBitmapSpareByte(
-    const fapi::Target & i_mba,
-    const fapi::Target & i_dimm,
-    uint8_t (&o_spareByte)[DIMM_DQ_MAX_DIMM_RANKS])
-{
-    fapi::ReturnCode l_rc;
-
-    do
-    {
-        // Spare DRAM Attribute: Returns spare DRAM availability for
-        // all DIMMs associated with the target MBA.
-        uint8_t l_mbaSpare[DIMM_DQ_MAX_MBA_PORTS][DIMM_DQ_MAX_MBAPORT_DIMMS]
-                                                 [DIMM_DQ_MAX_DIMM_RANKS] = {};
-
-        l_rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_mba, l_mbaSpare);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmGetDqBitmapSpareByte: "
-                     "Error getting DRAM Spare data");
-            break;
-        }
-        // Find the mba port this dimm is connected to
-        uint8_t l_mbaPort = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &i_dimm, l_mbaPort);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmGetDqBitmapSpareByte: "
-                     "Error getting MBA port number");
-            break;
-        }
-        // Find the dimm number associated with this dimm
-        uint8_t l_dimm = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &i_dimm, l_dimm);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmGetDqBitmapSpareByte: "
-                     "Error getting dimm number");
-            break;
-        }
-        // Iterate through each rank of this DIMM
-        for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-        {
-            // Handle spare DRAM configuration cases
-            switch (l_mbaSpare[l_mbaPort][l_dimm][i])
-            {
-                case fapi::ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE:
-                    // Set DQ bits reflecting unconnected
-                    // spare DRAM in caller's data
-                    o_spareByte[i] = 0xFF;
-                    break;
-
-                case fapi::ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE:
-                    o_spareByte[i] = 0x0F;
-                    break;
-
-                case fapi::ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE:
-                    o_spareByte[i] = 0xF0;
-                    break;
-
-                // As erroneous value will not be encountered.
-                case fapi::ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE:
-                default:
-                    o_spareByte[i] = 0x0;
-                    break;
-            }
-        }
-    }while(0);
-    return l_rc;
-}
-
-/**
- * @brief Called by dimmBadDqBitmapAccessHwp() to query ATTR_EFF_DIMM_SPARE
- * and set bits for unconnected spare DRAM in caller's data.
- *
- *
- * @param[in] i_mba       Reference to MBA Target.
- * @param[in] i_dimm      Reference to DIMM Target.
- * @param[o]  o_data      Reference to Bad DQ Bitmap set by
- *                        the caller.  Only the SPARE_DRAM_DQ_BYTE_NUMBER_INDEX
- *                        byte is modified by this function.
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode dimmUpdateDqBitmapSpareByte(
-    const fapi::Target & i_mba,
-    const fapi::Target & i_dimm,
-    uint8_t (&o_data)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE])
-{
-    fapi::ReturnCode l_rc;
-
-    uint8_t spareByte[DIMM_DQ_MAX_DIMM_RANKS];
-    memset(spareByte, 0, sizeof(spareByte));
-
-    l_rc = dimmGetDqBitmapSpareByte(i_mba,i_dimm,spareByte);
-    if (l_rc)
-    {
-        FAPI_ERR("dimmUpdateDqBitmapSpareByte: "
-                 "Error getting spare byte");
-        return l_rc;
-    }
-
-    for (uint32_t i=0; i<DIMM_DQ_MAX_DIMM_RANKS; i++)
-    {
-        o_data[i][SPARE_DRAM_DQ_BYTE_NUMBER_INDEX] |= spareByte[i];
-    }
-    return l_rc;
-}
-
-/**
- * @brief Called by dimmBadDqBitmapAccessHwp() to query
- * ATTR_SPD_MODULE_MEMORY_BUS_WIDTH in order to determine
- * ECC support for this DIMM.  This function will set
- * bits in the caller's data if ECC lines are not present.
- *
- *
- * @param[in] i_dimm      Reference to DIMM Target.
- * @param[o]  o_data      Reference to Bad DQ Bitmap set by
- *                        the caller.  Only the ECC_DQ_BYTE_NUMBER_INDEX
- *                        byte is modified by this function.
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode dimmUpdateDqBitmapEccByte(
-    const fapi::Target & i_dimm,
-    uint8_t (&o_data)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE])
-{
-    fapi::ReturnCode l_rc;
-
-    do
-    {
-        // Memory Bus Width Attribute
-        uint8_t l_eccBits = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_MEMORY_BUS_WIDTH,
-                                         &i_dimm, l_eccBits);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmUpdateDqBitmapEccByte: "
-                     "Error getting ECC data");
-            break;
-        }
-        // The ATTR_SPD_MODULE_MEMORY_BUS_WIDTH contains ENUM values
-        // for bus widths of 8, 16, 32, and 64 bits both with ECC
-        // and without ECC.  WExx ENUMS deonote the ECC extension
-        // is present, and all have bit 3 set.  Therefore,
-        // it is only required to check against the WE8 = 0x08 ENUM
-        // value in order to determine if ECC lines are present.
-
-        // If ECCs are disconnected
-        if (!(fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_WE8 &
-              l_eccBits))
-        {
-            // Iterate through each rank and set DQ bits in
-            // caller's data.
-            for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-            {
-                // Set DQ bits in caller's data
-                o_data[i][ECC_DQ_BYTE_NUMBER_INDEX] = 0xFF;
-            }
-        }
-
-    }while(0);
-    return l_rc;
-}
-
-/**
- * @brief Called by dimmBadDqBitmapAccessHwp() to query ATTR_SPD_BAD_DQ_DATA
- *
- *
- * @param[in] i_mba             Reference to MBA Target.
- * @param[in] i_dimm            Reference to DIMM Target.
- * @param[o]  o_data            Reference to Bad DQ Bitmap set by this function
- * @param[in] i_wiringData      Reference to Centaur DQ to DIMM Connector
- *                              DQ Wiring attribute.
- * @param[in] i_allMnfgFlags    Manufacturing flags bitmap
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode dimmBadDqBitmapGet(
-    const fapi::Target & i_mba,
-    const fapi::Target & i_dimm,
-    uint8_t (&o_data)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE],
-    const uint8_t (&i_wiringData)[DIMM_DQ_NUM_DQS],
-    uint64_t i_allMnfgFlags)
-{
-    fapi::ReturnCode l_rc;
-
-    // DQ SPD Attribute
-    uint8_t (&l_spdData)[DIMM_DQ_SPD_DATA_SIZE] =
-        *(reinterpret_cast<uint8_t(*)[DIMM_DQ_SPD_DATA_SIZE]>
-            (new uint8_t[DIMM_DQ_SPD_DATA_SIZE]()));
-
-    // memset to avoid known syntax issue with previous compiler versions
-    // and ensure zero initialized array.
-    memset(l_spdData, 0, sizeof(l_spdData));
-
-    dimmBadDqDataFormat * l_pSpdData =
-        reinterpret_cast<dimmBadDqDataFormat *>(l_spdData);
-
-    // Pointer which will be used to initialize a clean bitmap during
-    // manufacturing mode
-    uint8_t (*l_pBuf)[DIMM_DQ_RANK_BITMAP_SIZE] = NULL;
-
-    do
-    {
-        // Get the SPD DQ attribute
-        l_rc = FAPI_ATTR_GET(ATTR_SPD_BAD_DQ_DATA, &i_dimm, l_spdData);
-
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: Error getting SPD data");
-            break;
-        }
-        // Zero caller's data
-        memset(o_data, 0, sizeof(o_data));
-        // Check the magic number and version number. Note that the
-        // magic number is stored in SPD in big endian format and
-        // platforms of any endianness can access it
-        if ((FAPI_BE32TOH(l_pSpdData->iv_magicNumber) !=
-               DIMM_BAD_DQ_MAGIC_NUMBER) ||
-            (l_pSpdData->iv_version != DIMM_BAD_DQ_VERSION))
-        {
-            FAPI_INF("dimmBadDqBitmapAccessHwp: SPD DQ not initialized");
-        }
-        else
-        {
-            // Translate bitmap from DIMM DQ to Centaur DQ point of view
-            // for each rank
-            for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-            {
-                // Iterate through all the DQ bits in the rank
-                for (uint8_t j = 0; j < DIMM_DQ_NUM_DQS; j++)
-                {
-                    // There is a byte for each 8 DQs, j/8 gives the
-                    // byte number. The MSB in each byte is the lowest
-                    // DQ, (0x80 >> (j % 8)) gives the bit mask
-                    // corresponding to the DQ within the byte
-                    if ((l_pSpdData->iv_bitmaps[i][j/8]) &
-                        (0x80 >> (j % 8)))
-                    {
-                        // DIMM DQ bit is set in SPD data.
-                        // Set Centaur DQ bit in caller's data.
-                        // The wiring data maps Centaur DQ to DIMM DQ
-                        // Find the Centaur DQ that maps to this DIMM DQ
-                        uint8_t k = 0;
-                        for (; k < DIMM_DQ_NUM_DQS; k++)
-                        {
-                            if (i_wiringData[k] == j)
-                            {
-                                o_data[i][k/8] |= (0x80 >> (k % 8));
-                                break;
-                            }
-                        }
-
-                        if (k == DIMM_DQ_NUM_DQS)
-                        {
-                            FAPI_INF("dimmBadDqBitmapAccessHwp: "
-                                     "Centaur DQ not found for %d!",j);
-                        }
-                    }
-                }
-            }
-        }
-        // Set bits for any unconnected DQs.
-        // First, check ECC.
-        l_rc = dimmUpdateDqBitmapEccByte(i_dimm, o_data);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                     "Error getting ECC data");
-            break;
-        }
-        // Check spare DRAM
-        l_rc = dimmUpdateDqBitmapSpareByte(i_mba, i_dimm, o_data);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                     "Error getting spare DRAM data");
-            break;
-        }
-        // If system is in DISABLE_DRAM_REPAIRS mode
-        if (i_allMnfgFlags &
-            fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_DISABLE_DRAM_REPAIRS)
-        {
-
-            // Flag to set if the discrepancies (described below)
-            // are found
-            bool mfgModeBadBitsPresent = false;
-            // Create a local zero-initialized bad dq bitmap
-            l_pBuf = new uint8_t[DIMM_DQ_MAX_DIMM_RANKS]
-                                         [DIMM_DQ_RANK_BITMAP_SIZE]();
-            uint8_t (&l_data)[DIMM_DQ_MAX_DIMM_RANKS]
-                                 [DIMM_DQ_RANK_BITMAP_SIZE] =
-            *(reinterpret_cast<uint8_t(*)[DIMM_DQ_MAX_DIMM_RANKS]
-                                 [DIMM_DQ_RANK_BITMAP_SIZE]>(l_pBuf));
-            // memset to avoid known syntax issue with previous
-            // compiler versions and ensure zero initialized array.
-            memset(l_data, 0, sizeof(l_data));
-
-            // Check ECC.
-            l_rc = dimmUpdateDqBitmapEccByte(i_dimm, l_data);
-            if (l_rc)
-            {
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                         "Error getting ECC data (Mfg mode)");
-                break;
-            }
-            // Check spare DRAM
-            l_rc = dimmUpdateDqBitmapSpareByte(i_mba, i_dimm, l_data);
-            if (l_rc)
-            {
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                         "Error getting spare DRAM data (Mfg mode)");
-                break;
-            }
-            // Compare l_data, which represents a bad dq bitmap with the
-            // appropriate spare/ECC bits set (if any) and all other DQ
-            // lines functional, to caller's o_data.
-            // If discrepancies are found, we know this is the result of
-            // a manufacturing mode process and these bits should not be
-            // recorded.
-            for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-            {
-                for (uint8_t j = 0; j < (DIMM_DQ_RANK_BITMAP_SIZE); j++)
-                {
-                    if (o_data[i][j] != l_data[i][j])
-                    {
-                        mfgModeBadBitsPresent = true;
-                        break ;
-                    }
-                }
-                if (mfgModeBadBitsPresent)
-                {
-                    break;
-                }
-            }
-            // Create and log fapi error if discrepancies were found
-            if (mfgModeBadBitsPresent)
-            {
-                // Get this DIMM's position
-                uint32_t l_dimmPos = 0;
-                l_rc = FAPI_ATTR_GET(ATTR_POS, &i_dimm, l_dimmPos);
-                if (l_rc)
-                {
-                    FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                             "Error getting DIMM position,"
-                             " reporting as 0xFFFFFFFF");
-                    l_dimmPos = 0xFFFFFFFF;
-                }
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: Read requested while"
-                         " in DISABLE_DRAM_REPAIRS mode found"
-                         " extra bad bits set for DIMM: %d",
-                         l_dimmPos);
-                const fapi::Target & DIMM = i_dimm;
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK0)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[0];
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK1)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[1];
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK2)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[2];
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK3)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[3];
-                uint8_t (&CURRENT_BAD_DQ_BITMAP_RANK0)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = o_data[0];
-                uint8_t (&CURRENT_BAD_DQ_BITMAP_RANK1)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = o_data[1];
-                uint8_t (&CURRENT_BAD_DQ_BITMAP_RANK2)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = o_data[2];
-                uint8_t (&CURRENT_BAD_DQ_BITMAP_RANK3)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = o_data[3];
-                FAPI_SET_HWP_ERROR(l_rc,
-                    RC_BAD_DQ_MFG_MODE_BITS_FOUND_DURING_GET);
-                fapiLogError(l_rc);
-
-                // correct the output bit map
-                for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-                {
-                    for (uint8_t j = 0; j < (DIMM_DQ_RANK_BITMAP_SIZE); j++)
-                    {
-                        o_data[i][j] = l_data[i][j];
-                    }
-                }
-            }
-        }
-    } while(0);
-    delete [] &l_spdData;
-    delete [] l_pBuf;
-    return l_rc;
-}
-
-/**
- * @brief Called by dimmBadDqBitmapAccessHwp() to set ATTR_SPD_BAD_DQ_DATA
- * Also checks if a bad Dq bit is set by first calling dimmBadDqBitmapGet()
- * and sets ATTR_RECONFIGURE_LOOP with the 'OR' of the current value and
- * the fapi enum BAD_DQ_BIT_SET if appropriate
- *
- * @param[in] i_mba             Reference to MBA Target.
- * @param[in] i_dimm            Reference to DIMM Target.
- * @param[in] i_data            Reference to Bad DQ Bitmap set by the caller
- * @param[in] i_wiringData      Reference to Centaur DQ to DIMM Connector
- *                              DQ Wiring attribute.
- * @param[in] i_allMnfgFlags    Manufacturing flags bitmap
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode dimmBadDqBitmapSet(
-    const fapi::Target & i_mba,
-    const fapi::Target & i_dimm,
-    const uint8_t (&i_data)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE],
-    const uint8_t (&i_wiringData)[DIMM_DQ_NUM_DQS],
-    uint64_t i_allMnfgFlags)
-{
-    fapi::ReturnCode l_rc;
-
-    // Read current BadDqBitmap into l_prev_data
-    uint8_t (l_prev_data)[DIMM_DQ_MAX_DIMM_RANKS]
-                         [DIMM_DQ_RANK_BITMAP_SIZE];
-    bool badDQSet = false;
-    l_rc = dimmBadDqBitmapGet(i_mba, i_dimm, l_prev_data, i_wiringData,
-                              i_allMnfgFlags);
-    if (l_rc)
-    {
-        FAPI_ERR("dimmBadDqBitmapAccessHwp: Error getting DQ bitmap");
-        return l_rc;
-    }
-
-    // Check if Bad DQ bit set
-    for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-    {
-        for (uint8_t j = 0; j < (DIMM_DQ_RANK_BITMAP_SIZE); j++)
-        {
-            if (i_data[i][j] != l_prev_data[i][j])
-            {
-                badDQSet = true;
-                break;
-            }
-        }
-        if (badDQSet)
-        {
-            break;
-        }
-    }
-
-    // Set ATTR_RECONFIGURE_LOOP to indicate a bad DqBitMap was set
-    if (badDQSet)
-    {
-        FAPI_INF("dimmBadDqBitmapAccessHwp: Reconfigure needed, Bad DQ set");
-
-        fapi::ATTR_RECONFIGURE_LOOP_Type l_reconfigAttr = 0;
-        l_rc = FAPI_ATTR_GET(ATTR_RECONFIGURE_LOOP, NULL, l_reconfigAttr);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: Error getting "
-                     "ATTR_RECONFIGURE_LOOP");
-            return l_rc;
-        }
-
-        // 'OR' values in case of multiple reasons for reconfigure
-        l_reconfigAttr |= fapi::ENUM_ATTR_RECONFIGURE_LOOP_BAD_DQ_BIT_SET;
-
-#ifndef CONFIG_VPD_GETMACRO_USE_EFF_ATTR
-        l_rc = FAPI_ATTR_SET(ATTR_RECONFIGURE_LOOP, NULL, l_reconfigAttr);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: Error setting "
-                     "ATTR_RECONFIGURE_LOOP");
-            return l_rc;
-        }
-#endif
-    }
-
-    // DQ SPD Attribute
-    uint8_t (&l_spdData)[DIMM_DQ_SPD_DATA_SIZE] =
-        *(reinterpret_cast<uint8_t(*)[DIMM_DQ_SPD_DATA_SIZE]>
-            (new uint8_t[DIMM_DQ_SPD_DATA_SIZE]()));
-
-    // memset to avoid known syntax issue with previous compiler versions
-    // and ensure zero initialized array.
-    memset(l_spdData, 0, sizeof(l_spdData));
-
-    dimmBadDqDataFormat * l_pSpdData =
-        reinterpret_cast<dimmBadDqDataFormat *>(l_spdData);
-
-    // Pointer which will be used to initialize a clean bitmap during
-    // manufacturing mode
-    uint8_t (*l_pBuf)[DIMM_DQ_RANK_BITMAP_SIZE] = NULL;
-
-    do
-    {
-        // If system is in DISABLE_DRAM_REPAIRS mode
-        if (i_allMnfgFlags &
-            fapi::ENUM_ATTR_MNFG_FLAGS_MNFG_DISABLE_DRAM_REPAIRS)
-        {
-            // Flag to set if the discrepancies (described below)
-            // are found
-            bool mfgModeBadBitsPresent = false;
-            // Create a local zero-initialized bad dq bitmap
-            l_pBuf = new uint8_t[DIMM_DQ_MAX_DIMM_RANKS]
-                                         [DIMM_DQ_RANK_BITMAP_SIZE]();
-            uint8_t (&l_data)[DIMM_DQ_MAX_DIMM_RANKS]
-                                 [DIMM_DQ_RANK_BITMAP_SIZE] =
-            *(reinterpret_cast<uint8_t(*)[DIMM_DQ_MAX_DIMM_RANKS]
-                                 [DIMM_DQ_RANK_BITMAP_SIZE]>(l_pBuf));
-            // memset to avoid known syntax issue with previous
-            // compiler versions and ensure zero initialized array.
-            memset(l_data, 0, sizeof(l_data));
-
-            // Check ECC.
-            l_rc = dimmUpdateDqBitmapEccByte(i_dimm, l_data);
-            if (l_rc)
-            {
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                         "Error getting ECC data (Mfg mode)");
-                break;
-            }
-            // Check spare DRAM
-            l_rc = dimmUpdateDqBitmapSpareByte(i_mba, i_dimm, l_data);
-            if (l_rc)
-            {
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                         "Error getting spare DRAM data (Mfg mode)");
-                break;
-            }
-            // Compare l_data, which represents a bad dq bitmap with the
-            // appropriate spare/ECC bits set (if any) and all other DQ
-            // lines functional, to caller's i_data.
-            // If discrepancies are found, we know this is the result of
-            // a manufacturing mode process and these bits should not be
-            // recorded.
-            for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-            {
-                for (uint8_t j = 0; j < (DIMM_DQ_RANK_BITMAP_SIZE); j++)
-                {
-                    if (i_data[i][j] != l_data[i][j])
-                    {
-                        mfgModeBadBitsPresent = true;
-                        break;
-                    }
-                }
-                // Break out of this section when first
-                // discrepancy is noticed
-                if (mfgModeBadBitsPresent)
-                {
-                    break;
-                }
-            }
-            // Create and log fapi error if discrepancies were found
-            if (mfgModeBadBitsPresent)
-            {
-                // Get this DIMM's position
-                uint32_t l_dimmPos = 0;
-                l_rc = FAPI_ATTR_GET(ATTR_POS, &i_dimm, l_dimmPos);
-                if (l_rc)
-                {
-                    FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                             "Error getting DIMM position,"
-                             " reporting as 0xFFFFFFFF");
-                    l_dimmPos = 0xFFFFFFFF;
-                }
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: Write requested while"
-                         " in DISABLE_DRAM_REPAIRS mode found"
-                         " extra bad bits set for DIMM: %d",
-                         l_dimmPos);
-                const fapi::Target & DIMM = i_dimm;
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK0)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[0];
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK1)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[1];
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK2)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[2];
-                uint8_t (&CLEAN_BAD_DQ_BITMAP_RANK3)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] = l_data[3];
-                uint8_t (&UPDATE_BAD_DQ_BITMAP_RANK0)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] =
-                       const_cast< uint8_t (&)
-                    [DIMM_DQ_RANK_BITMAP_SIZE]>(i_data[0]);
-                uint8_t (&UPDATE_BAD_DQ_BITMAP_RANK1)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] =
-                       const_cast< uint8_t (&)
-                    [DIMM_DQ_RANK_BITMAP_SIZE]>(i_data[1]);
-                uint8_t (&UPDATE_BAD_DQ_BITMAP_RANK2)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] =
-                       const_cast< uint8_t (&)
-                    [DIMM_DQ_RANK_BITMAP_SIZE]>(i_data[2]);
-                uint8_t (&UPDATE_BAD_DQ_BITMAP_RANK3)
-                    [DIMM_DQ_RANK_BITMAP_SIZE] =
-                       const_cast< uint8_t (&)
-                    [DIMM_DQ_RANK_BITMAP_SIZE]>(i_data[3]);
-                FAPI_SET_HWP_ERROR(l_rc,
-                    RC_BAD_DQ_MFG_MODE_BITS_FOUND_DURING_SET);
-                fapiLogError(l_rc);
-            }
-            // Don't write bad dq bitmap,
-            // Break out of do {...} while(0)
-            break;
-        }
-
-        // Set up the data to write to SPD
-        l_pSpdData->iv_magicNumber = FAPI_HTOBE32(DIMM_BAD_DQ_MAGIC_NUMBER);
-        l_pSpdData->iv_version = DIMM_BAD_DQ_VERSION;
-        l_pSpdData->iv_reserved1 = 0;
-        l_pSpdData->iv_reserved2 = 0;
-        l_pSpdData->iv_reserved3 = 0;
-        memset(l_pSpdData->iv_bitmaps, 0, sizeof(l_pSpdData->iv_bitmaps));
-
-        // Get the spare byte
-        uint8_t spareByte[DIMM_DQ_MAX_DIMM_RANKS];
-        memset(spareByte, 0, sizeof(spareByte));
-
-        l_rc = dimmGetDqBitmapSpareByte(i_mba,i_dimm,spareByte);
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                    "Error getting spare byte");
-            break;
-        }
-
-        // Translate bitmap from Centaur DQ to DIMM DQ point of view for
-        // each rank
-        for (uint8_t i = 0; i < DIMM_DQ_MAX_DIMM_RANKS; i++)
-        {
-            // Iterate through all the DQ bits in the rank
-            for (uint8_t j = 0; j < DIMM_DQ_NUM_DQS; j++)
-            {
-                if ((j/8) == SPARE_DRAM_DQ_BYTE_NUMBER_INDEX)
-                {
-                    // The spareByte can be one of: 0x00 0x0F 0xF0 0xFF
-                    // If a bit is set, then that spare is unconnected
-                    // so continue to the next num_dqs, do not translate
-                    if (spareByte[i] & (0x80 >> (j % 8)))
-                    {
-                        continue;
-                    }
-                }
-                if ((i_data[i][j/8]) & (0x80 >> (j % 8)))
-                {
-                    // Centaur DQ bit set in callers data.
-                    // Set DIMM DQ bit in SPD data.
-                    // The wiring data maps Centaur DQ to DIMM DQ
-                    uint8_t dBit = i_wiringData[j];
-                    l_pSpdData->iv_bitmaps[i][dBit/8] |=
-                        (0x80 >> (dBit % 8));
-                }
-            }
-        }
-
-        // Set the SPD DQ attribute
-        l_rc = FAPI_ATTR_SET(ATTR_SPD_BAD_DQ_DATA, &i_dimm, l_spdData);
-
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: Error setting SPD data");
-            break;
-        }
-    } while(0);
-    delete [] &l_spdData;
-    delete [] l_pBuf;
-    return l_rc;
-}
-
-}
-
-extern "C"
-{
-
-fapi::ReturnCode dimmBadDqBitmapAccessHwp(
-    const fapi::Target & i_mba,
-    const fapi::Target & i_dimm,
-    uint8_t (&io_data)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE],
-    const bool i_get)
-{
-    if (i_get)
-    {
-        FAPI_INF(">>dimmBadDqBitmapAccessHwp: Getting bitmap");
-    }
-    else
-    {
-        FAPI_INF(">>dimmBadDqBitmapAccessHwp: Setting bitmap");
-    }
-
-    fapi::ReturnCode l_rc;
-
-    // Note the use of heap based arrays to avoid large stack allocations
-
-    // Centaur DQ to DIMM Connector DQ Wiring attribute.
-    uint8_t (&l_wiringData)[DIMM_DQ_NUM_DQS] =
-        *(reinterpret_cast<uint8_t(*)[DIMM_DQ_NUM_DQS]>
-            (new uint8_t[DIMM_DQ_NUM_DQS]()));
-
-    // memset to avoid known syntax issue with previous compiler versions
-    // and ensure zero initialized array.
-    memset(l_wiringData, 0, sizeof(l_wiringData));
-
-    do
-    {
-        // Manufacturing flags attribute
-        uint64_t l_allMnfgFlags = 0;
-        // Get the manufacturing flags bitmap to be used in both get and set
-        l_rc = FAPI_ATTR_GET(ATTR_MNFG_FLAGS, NULL, l_allMnfgFlags);
-        if(l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: Unable to read attribute"
-                     " - ATTR_MNFG_FLAGS");
-            break;
-        }
-        // Get the Centaur DQ to DIMM Connector DQ Wiring attribute.
-        // Note that for C-DIMMs, this will return a simple 1:1 mapping.
-        // This code cannot tell the difference between C-DIMMs and IS-DIMMs.
-        l_rc = FAPI_ATTR_GET(ATTR_CEN_DQ_TO_DIMM_CONN_DQ,
-                             &i_dimm, l_wiringData);
-
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                     "Error getting wiring attribute");
-            break;
-        }
-
-        if (i_get)
-        {
-            l_rc = dimmBadDqBitmapGet(i_mba, i_dimm, io_data, l_wiringData,
-                                      l_allMnfgFlags);
-            if (l_rc)
-            {
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                        "Error getting DQ bitmap");
-                break;
-            }
-        }
-        else
-        {
-            l_rc = dimmBadDqBitmapSet(i_mba, i_dimm, io_data, l_wiringData,
-                                      l_allMnfgFlags);
-            if (l_rc)
-            {
-                FAPI_ERR("dimmBadDqBitmapAccessHwp: "
-                        "Error setting DQ bitmap");
-                break;
-            }
-        }
-
-    }while(0);
-
-    delete [] &l_wiringData;
-    FAPI_INF("<<dimmBadDqBitmapAccessHwp");
-    return l_rc;
-}
-
-}
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/dimmBadDqBitmapFuncs.C b/src/usr/hwpf/hwp/dimmBadDqBitmapFuncs.C
deleted file mode 100644
index 8f0efa171..000000000
--- a/src/usr/hwpf/hwp/dimmBadDqBitmapFuncs.C
+++ /dev/null
@@ -1,236 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dimmBadDqBitmapFuncs.C $                     */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: dimmBadDqBitmapFuncs.C,v 1.4 2013/08/13 20:32:55 mjjones Exp $
-/**
- *  @file dimmBadDqBitmapFuncs.C
- *
- *  @brief FW Team Utility functions that accesses the Bad DQ Bitmap.
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     02/17/2012  Created.
- *                          farrugia    07/09/2012  Added dimmBadDqBitmapAccessHwp.H
- *                                                  since FAPI_HWP_EXEC may need the
- *                                      typedefs function pointer when
- *                                                  running with some PLATs (ie Cronus)
- *                          dedahle     06/20/2013  dimmGetBadDqBitmap/
- *                                                  dimmSetBadDqBitmap funcs
- *                                                  get/set ATTR_BAD_DQ_BITMAP
- */
-
-#include <dimmBadDqBitmapFuncs.H>
-#include <dimmBadDqBitmapAccessHwp.H>
-#include <string.h>
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// Utility function to check parameters and find a DIMM target
-//------------------------------------------------------------------------------
-fapi::ReturnCode dimmBadDqCheckParamFindDimm(const fapi::Target & i_mba,
-                                             const uint8_t i_port,
-                                             const uint8_t i_dimm,
-                                             const uint8_t i_rank,
-                                             fapi::Target & o_dimm)
-{
-    fapi::ReturnCode l_rc;
-
-    if ((i_port >= DIMM_DQ_MAX_MBA_PORTS) ||
-        (i_dimm >= DIMM_DQ_MAX_MBAPORT_DIMMS) ||
-        (i_rank >= DIMM_DQ_MAX_DIMM_RANKS))
-    {
-        FAPI_ERR("dimmBadDqCheckParamFindDimm: Bad parameter. %d:%d:%d",
-                i_port, i_dimm, i_rank);
-        const uint8_t & FFDC_PORT = i_port;
-        const uint8_t & FFDC_DIMM = i_dimm;
-        const uint8_t & FFDC_RANK = i_rank;
-        FAPI_SET_HWP_ERROR(l_rc, RC_BAD_DQ_DIMM_BAD_PARAM);
-    }
-    else
-    {
-        std::vector<fapi::Target> l_dimms;
-
-        // Get the functional DIMMs associated with the MBA chiplet
-        l_rc = fapiGetAssociatedDimms(i_mba, l_dimms);
-
-        if (l_rc)
-        {
-            FAPI_ERR("dimmBadDqCheckParamFindDimm: "
-                        "Error from fapiGetAssociatedDimms");
-        }
-        else
-        {
-            // Find the DIMM with the correct MBA port/dimm
-            uint8_t l_port = 0;
-            uint8_t l_dimm = 0;
-            std::vector<fapi::Target>::const_iterator dimmIter;
-
-            for (dimmIter = l_dimms.begin();
-                    dimmIter != l_dimms.end();
-                    ++dimmIter)
-            {
-                l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &(*dimmIter), l_port);
-
-                if (l_rc)
-                {
-                    FAPI_ERR("dimmBadDqCheckParamFindDimm: "
-                                "Error getting ATTR_MBA_PORT for dimm");
-                    break;
-                }
-                else if (l_port == i_port)
-                {
-                    l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &(*dimmIter), l_dimm);
-
-                    if (l_rc)
-                    {
-                        FAPI_ERR("dimmBadDqCheckParamFindDimm: "
-                                    "Error getting ATTR_MBA_DIMM for dimm");
-                        break;
-                    }
-                    else if (l_dimm == i_dimm)
-                    {
-                        o_dimm = *dimmIter;
-                        break;
-                    }
-                }            
-            }
-
-            if (!l_rc)
-            {
-                if (dimmIter == l_dimms.end())
-                {
-                    FAPI_ERR("dimmBadDqCheckParamFindDimm: "
-                             "Did not find DIMM for %s:%d:%d",
-                             i_mba.toEcmdString(), i_port, i_dimm);
-                    const fapi::Target & FFDC_MBA_TARGET = i_mba;
-                    const uint8_t & FFDC_PORT = i_port;
-                    const uint8_t & FFDC_DIMM = i_dimm;
-                    FAPI_SET_HWP_ERROR(l_rc, RC_BAD_DQ_DIMM_NOT_FOUND);
-                }
-            }
-        }
-    }
-
-    return l_rc;
-}
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode dimmGetBadDqBitmap(const fapi::Target & i_mba,
-                                    const uint8_t i_port,
-                                    const uint8_t i_dimm,
-                                    const uint8_t i_rank,
-                                    uint8_t (&o_data)[DIMM_DQ_RANK_BITMAP_SIZE])
-{
-    FAPI_INF(">>dimmGetBadDqBitmap. %s:%d:%d:%d", i_mba.toEcmdString(), i_port,
-             i_dimm, i_rank);
-
-    fapi::ReturnCode l_rc;
-
-    // Check parameters and find the DIMM Target
-    fapi::Target l_dimm;
-    l_rc = dimmBadDqCheckParamFindDimm(i_mba, i_port, i_dimm, i_rank, l_dimm);
-
-    if (!l_rc)
-    {
-        // Get the Bad DQ bitmap by querying ATTR_BAD_DQ_BITMAP.
-        // Use a heap based array to avoid large stack alloc
-        uint8_t (&l_dqBitmap)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE] =
-            *(reinterpret_cast<uint8_t(*)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE]>
-                (new uint8_t[DIMM_DQ_MAX_DIMM_RANKS*DIMM_DQ_RANK_BITMAP_SIZE]));
-       
-        l_rc = FAPI_ATTR_GET(ATTR_BAD_DQ_BITMAP, &l_dimm, l_dqBitmap);
-
-        if (l_rc)
-        {
-            FAPI_ERR("dimmGetBadDqBitmap: Error getting ATTR_BAD_DQ_BITMAP for dimm");
-        }
-        else
-        {
-            //Write contents of DQ bitmap for specific rank to o_data.
-            memcpy(o_data, l_dqBitmap[i_rank], DIMM_DQ_RANK_BITMAP_SIZE);
-        }
-
-        delete [] &l_dqBitmap;
-    }
-
-    FAPI_INF("<<dimmGetBadDqBitmap");
-    return l_rc;
-}
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode dimmSetBadDqBitmap(
-    const fapi::Target & i_mba,
-    const uint8_t i_port,
-    const uint8_t i_dimm,
-    const uint8_t i_rank,
-    const uint8_t (&i_data)[DIMM_DQ_RANK_BITMAP_SIZE])
-{
-    FAPI_INF(">>dimmSetBadDqBitmap. %s:%d:%d:%d", i_mba.toEcmdString(), i_port, i_dimm, i_rank);
-
-    fapi::ReturnCode l_rc;
-
-    // Check parameters and find the DIMM Target
-    fapi::Target l_dimm;
-    l_rc = dimmBadDqCheckParamFindDimm(i_mba, i_port, i_dimm, i_rank, l_dimm);
-
-    if (!l_rc)
-    {
-        // Get the Bad DQ bitmap by querying ATTR_BAD_DQ_BITMAP.
-        // Use a heap based array to avoid large stack alloc
-        uint8_t (&l_dqBitmap)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE] =
-            *(reinterpret_cast<uint8_t(*)[DIMM_DQ_MAX_DIMM_RANKS][DIMM_DQ_RANK_BITMAP_SIZE]>
-                (new uint8_t[DIMM_DQ_MAX_DIMM_RANKS*DIMM_DQ_RANK_BITMAP_SIZE]));
-
-        l_rc = FAPI_ATTR_GET(ATTR_BAD_DQ_BITMAP, &l_dimm, l_dqBitmap);
-
-        if (l_rc)
-        {
-            FAPI_ERR("dimmSetBadDqBitmap: Error getting ATTR_BAD_DQ_BITMAP for dimm");
-        }
-        else
-        {
-            // Add the rank bitmap to the DIMM bitmap and write the bitmap
-            memcpy(l_dqBitmap[i_rank], i_data, DIMM_DQ_RANK_BITMAP_SIZE);
-
-            l_rc = FAPI_ATTR_SET(ATTR_BAD_DQ_BITMAP, &l_dimm, l_dqBitmap);
-
-            if (l_rc)
-            {
-                FAPI_ERR("dimmSetBadDqBitmap: Error setting ATTR_BAD_DQ_BITMAP for dimm");
-            }
-        }
-
-        delete [] &l_dqBitmap;
-    }
-
-
-    FAPI_INF("<<dimmSetBadDqBitmap");
-    return l_rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/HBconfig b/src/usr/hwpf/hwp/dmi_training/HBconfig
deleted file mode 100644
index f3bf34d2b..000000000
--- a/src/usr/hwpf/hwp/dmi_training/HBconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-config NO_DMI_EREPAIR
-    default y if(!MEMVPD_WRITE || !MEMVPD_READ)
-    help
-        Do not apply erepair information on the DMI bus during boot
diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C
deleted file mode 100644
index a0f36e402..000000000
--- a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C
+++ /dev/null
@@ -1,127 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_dmi_scominit.C,v 1.5 2013/10/28 23:07:05 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_dmi_scominit.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_dmi_scominit.C
-// *! DESCRIPTION : Invoke DMI initfiles (FAPI)
-// *!
-// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
-// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-//  Version     Date        Owner       Description
-//------------------------------------------------------------------------------
-//    1.5       10/28/13    jmcgill     Updates for RAS review
-//    1.4       02/05/13    thomsen     Fixed typo that caused the procedure
-//                                      to not compile
-//    1.3       01/31/13    thomsen     Added separate calls to base & custom
-//                                      scominit files. Removed separate calls
-//                                      to SIM vs. HW scominit files. Fixed
-//                                      informational print to not say Error
-//    1.2       01/09/13    thomsen     Added separate calls to SIM vs. HW
-//                                      scominit files
-//                                      Added commented-out call to OVERRIDE
-//                                      initfile for system/bus/lane specific
-//                                      inits
-//    1.1       8/11/12     jmcgill     Initial release
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapiHwpExecInitFile.H>
-#include <cen_dmi_scominit.H>
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-// HWP entry point, comments in header
-fapi::ReturnCode cen_dmi_scominit(const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    fapi::TargetType target_type;
-    std::vector<fapi::Target> targets;
-
-    // mark HWP entry
-    FAPI_INF("cen_dmi_scominit: Start");
-
-    do
-    {
-        // obtain target type to determine which initfile(s) to execute
-        target_type = i_target.getType();
-        targets.push_back(i_target);
-
-        // Centaur chip target
-        if (target_type == fapi::TARGET_TYPE_MEMBUF_CHIP)
-        {
-            // Call BASE DMI SCOMINIT
-            FAPI_INF("cen_dmi_scominit: fapiHwpExecInitfile executing %s on %s",
-                     CEN_DMI_BASE_IF, i_target.toEcmdString());
-            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, CEN_DMI_BASE_IF);
-            if (!rc.ok())
-            {
-                FAPI_ERR("cen_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s",
-                         CEN_DMI_BASE_IF, i_target.toEcmdString());
-                break;
-            }
-            // Call CUSTOMIZED DMI SCOMINIT
-            FAPI_INF("cen_dmi_scominit: fapiHwpExecInitfile executing %s on %s",
-                     CEN_DMI_CUSTOM_IF, i_target.toEcmdString());
-            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, CEN_DMI_CUSTOM_IF);
-            if (!rc.ok())
-            {
-                FAPI_ERR("cen_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s",
-                         CEN_DMI_CUSTOM_IF, i_target.toEcmdString());
-                break;
-            }
-        }
-        // unsupported target type
-        else
-        {
-            FAPI_ERR("cen_dmi_scominit: Unsupported target type");
-            const fapi::Target & TARGET = i_target;
-            FAPI_SET_HWP_ERROR(rc, RC_CEN_DMI_SCOMINIT_INVALID_TARGET);
-            break;
-        }
-    } while (0);
-
-    // mark HWP exit
-    FAPI_INF("cen_dmi_scominit: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H b/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H
deleted file mode 100644
index 55ceec454..000000000
--- a/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H
+++ /dev/null
@@ -1,97 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit/cen_dmi_scominit.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_dmi_scominit.H,v 1.3 2013/10/28 23:07:08 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_dmi_scominit.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_dmi_scominit.H
-// *! DESCRIPTION : Invoke DMI initfiles (FAPI)
-// *!
-// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
-// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-//  Version     Date        Owner       Description
-//------------------------------------------------------------------------------
-//    1.4       10/28/13    jmcgill     Updates for RAS review
-//    1.3       01/23/13    thomsen     Added separate calls to base & custom
-//                                      scominit files. Removed separate calls
-//                                      to SIM vs. HW scominit files
-//    1.1       08/11/12    jmcgill     Initial release
-//------------------------------------------------------------------------------
-
-
-#ifndef CEN_DMI_SCOMINIT_H_
-#define CEN_DMI_SCOMINIT_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-const char * const CEN_DMI_BASE_IF   = "cen.dmi.scom.if";
-const char * const CEN_DMI_CUSTOM_IF = "cen.dmi.custom.scom.if";
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*cen_dmi_scominit_FP_t)(const fapi::Target & i_target);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-/**
- * @brief HWP that calls the DMI SCOM initfiles
- *
- * Should be called with all functional Centaur chips
- *
- *
- * @param[in] i_target Reference to target
- *                     If TARGET_TYPE_MEMBUF_CHIP, calls:
- *                     - cen.dmi.scom.initfile
- *
- * @return ReturnCode
- */
-fapi::ReturnCode cen_dmi_scominit(const fapi::Target & i_target);
-
-
-} // extern "C"
-
-#endif // CEN_DMI_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C b/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C
deleted file mode 100644
index 1ed672dd6..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C
+++ /dev/null
@@ -1,32 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.C $   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#include <fapi.H>
-#include "io_dccal.H"
-
-extern "C" {
-
-ReturnCode dmi_io_dccal(const Target &master_target){
-     return io_dccal(master_target);
-}
-
-} // extern 
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H b/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H
deleted file mode 100644
index 2408782d9..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H
+++ /dev/null
@@ -1,35 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_io_dccal/dmi_io_dccal.H $   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef DMI_IO_DCCAL_H_
-#define DMI_IO_DCCAL_H_
-
-using namespace fapi;
-
-extern "C"
-{
-
-fapi::ReturnCode dmi_io_dccal(const fapi::Target &master_target);
-
-} // extern "C"
-
-#endif // DMI_IO_DCCAL_H
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.C
deleted file mode 100644
index 009b0a1a2..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.C
+++ /dev/null
@@ -1,32 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#include <fapi.H>
-#include "io_run_training.H"
-
-extern "C" {
-
-ReturnCode dmi_io_run_training(const Target &master_target,const Target &slave_target){
-     return io_run_training(master_target,slave_target);
-}
-
-} // extern 
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.H b/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.H
deleted file mode 100644
index 39da014d6..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.H
+++ /dev/null
@@ -1,35 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_io_run_training/dmi_io_run_training.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef DMI_IO_RUN_TRAINING_H_
-#define DMI_IO_RUN_TRAINING_H_
-
-using namespace fapi;
-
-extern "C"
-{
-
-fapi::ReturnCode dmi_io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);
-
-} // extern "C"
-
-#endif // DMI_IO_RUN_TRAINING_H
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.C b/src/usr/hwpf/hwp/dmi_training/dmi_training.C
deleted file mode 100644
index 7fff52cef..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.C
+++ /dev/null
@@ -1,614 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_training.C $                */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-/**
- *  @file dmi_training.C
- *
- *  Support file for hardware procedure:
- *      DMI Training
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/**
- * @note    "" comments denote lines that should be built from the HWP
- *          tag block.  See the preliminary design in dmi_training.H
- *          Please save.
- */
-
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-#include    <trace/interface.H>
-#include    <initservice/taskargs.H>
-#include    <errl/errlentry.H>
-
-#include    <initservice/isteps_trace.H>
-
-#include    <isteps/hwpisteperror.H>
-#include    <errl/errludtarget.H>
-#include    <hwas/common/deconfigGard.H>
-
-//  targeting support.
-#include    <targeting/common/commontargeting.H>
-#include    <targeting/common/utilFilter.H>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-
-//  --  prototype   includes    --
-#include    "dmi_training.H"
-#include    "proc_cen_framelock.H"
-#include    "dmi_io_run_training.H"
-#include    "proc_dmi_scominit.H"
-#include    "cen_dmi_scominit.H"
-#include    "io_post_trainadv.H"
-#include    "io_pre_trainadv.H"
-#include    "proc_cen_set_inband_addr.H"
-#include    "mss_get_cen_ecid.H"
-#include    "io_restore_erepair.H"
-#include <erepairAccessorHwpFuncs.H>
-#include    "dmi_io_dccal/dmi_io_dccal.H"
-#include    <pbusLinkSvc.H>
-#include    <ibscom/ibscomif.H>
-#include    <config.h>
-#include <ipmi/ipmifruinv.H>
-
-namespace   DMI_TRAINING
-{
-
-using   namespace   ISTEP;
-using   namespace   ISTEP_ERROR;
-using   namespace   ERRORLOG;
-using   namespace   TARGETING;
-using   namespace   fapi;
-using   namespace   EDI_EI_INITIALIZATION;
-
-//*****************************************************************
-// Function prototypes
-//*****************************************************************
-void get_dmi_io_targets(TargetPairs_t& o_dmi_io_targets);
-
-
-//
-//  Wrapper function to call dmi_pre_trainadv
-//
-void*    call_dmi_pre_trainadv( void *io_pArgs )
-{
-    errlHndl_t l_errl = NULL;
-    ISTEP_ERROR::IStepError l_StepError;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_pre_trainadv entry" );
-
-    TargetPairs_t l_dmi_pre_trainadv_targets;
-    get_dmi_io_targets(l_dmi_pre_trainadv_targets);
-
-    TARGETING::TargetHandleList l_cpuTargetList;
-    getAllChips(l_cpuTargetList, TYPE_PROC);
-
-
-    // Note:
-    // Due to lab tester board environment, HW procedure writer (Varkey) has
-    // requested to send in one target of a time (we used to send in
-    // the MCS and MEMBUF pair in one call). Even though they don't have to be
-    // in order, we should keep the pair concept here in case we need to send
-    // in a pair in the future again.
-    for (TargetPairs_t::const_iterator
-         l_itr = l_dmi_pre_trainadv_targets.begin();
-         l_itr != l_dmi_pre_trainadv_targets.end();
-         ++l_itr)
-    {
-        const fapi::Target l_fapi_mcs_target( TARGET_TYPE_MCS_CHIPLET,
-                (const_cast<TARGETING::Target*>(l_itr->first)));
-
-        const fapi::Target l_fapi_membuf_target( TARGET_TYPE_MEMBUF_CHIP,
-                (const_cast<TARGETING::Target*>(l_itr->second)));
-
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "===== Call dmi_pre_trainadv HWP( mcs 0x%.8X, mem 0x%.8X) : ",
-                TARGETING::get_huid(l_itr->first),
-                TARGETING::get_huid(l_itr->second));
-
-        // Call on the MCS
-        FAPI_INVOKE_HWP(l_errl, io_pre_trainadv, l_fapi_mcs_target);
-
-        if (l_errl)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR 0x%.8X :  dmi_pre_trainadv HWP Target MCS 0x%.8X",
-                      l_errl->reasonCode(), TARGETING::get_huid(l_itr->first));
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_errl );
-
-            // Commit Error
-            errlCommit( l_errl, HWPF_COMP_ID );
-            // We want to continue the training despite the error, so
-            // no break
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  call_dmi_pre_trainadv HWP - Target 0x%.8X",
-                    TARGETING::get_huid(l_itr->first));
-        }
-
-        // Call on the MEMBUF
-        FAPI_INVOKE_HWP(l_errl, io_pre_trainadv, l_fapi_membuf_target);
-        if (l_errl)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                    "ERROR 0x%.8X :  dmi_pre_trainadv HWP Target Membuf 0x%.8X",
-                    l_errl->reasonCode(), TARGETING::get_huid(l_itr->second));
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_errl );
-
-            // Commit Error
-            errlCommit( l_errl, HWPF_COMP_ID );
-            // We want to continue the training despite the error, so
-            // no break
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  call_dmi_pre_trainadv HWP - Target 0x%.8X",
-                    TARGETING::get_huid(l_itr->second));
-        }
-
-    }
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_dmi_pre_trainadv exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_StepError.getErrorHandle();
-}
-
-
-//
-//  Wrapper function to call dmi_io_run_training
-//
-void*    call_dmi_io_run_training( void *io_pArgs )
-{
-    errlHndl_t l_err = NULL;
-
-    ISTEP_ERROR::IStepError l_StepError;
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "call_dmi_io_run_training entry" );
-
-    TargetPairs_t l_dmi_io_dccal_targets;
-    get_dmi_io_targets(l_dmi_io_dccal_targets);
-
-    TARGETING::TargetHandleList l_cpuTargetList;
-    getAllChips(l_cpuTargetList, TYPE_PROC);
-
-    for (TargetPairs_t::const_iterator
-         l_itr = l_dmi_io_dccal_targets.begin();
-         (!l_err) && (l_itr != l_dmi_io_dccal_targets.end());
-         ++l_itr)
-    {
-        const fapi::Target l_fapi_master_target( TARGET_TYPE_MCS_CHIPLET,
-                (const_cast<TARGETING::Target*>(l_itr->first)));
-
-        const fapi::Target l_fapi_slave_target( TARGET_TYPE_MEMBUF_CHIP,
-                (const_cast<TARGETING::Target*>(l_itr->second)));
-
-       TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "===== Call dmi_io_run_training HWP(mcs 0x%x, mem 0x%x ) : ",
-               TARGETING::get_huid(l_itr->first),
-               TARGETING::get_huid(l_itr->second));
-
-        // dmi_io_run_training reads ATTR_MEMB_TP_BNDY_PLL_LENGTH, the Attribute
-        // Accessor (getPllRingAttr) needs to read ATTR_MSS_FREQ to find the
-        // ring data to get its length, but ATTR_MSS_FREQ is not yet setup, this
-        // is done by mss_freq. However, the ring length is the same for a
-        // particular EC level, the frequency only selects the data. Ideally the
-        // Accessor would be able to return the ring length without a frequency,
-        // a workaround is to set ATTR_MSS_FREQ to a default value here
-        TARGETING::Target* l_membuf_target =
-            (const_cast<TARGETING::Target*>(l_itr->second));
-        l_membuf_target->setAttr<TARGETING::ATTR_MSS_FREQ>(1600);
-
-        FAPI_INVOKE_HWP(l_err, dmi_io_run_training,
-                        l_fapi_master_target, l_fapi_slave_target);
-
-        // Clear ATTR_MSS_FREQ.
-        l_membuf_target->setAttr<TARGETING::ATTR_MSS_FREQ>(0);
-
-        if (l_err)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR 0x%.8X :  dmi_io_run_training HWP",
-                      l_err->reasonCode());
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_err);
-
-            // Commit Error
-            errlCommit( l_err, HWPF_COMP_ID );
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  dmi_io_run_training HWP");
-        }
-
-    }   // end target pair list
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "call_dmi_io_run_training exit" );
-
-    return l_StepError.getErrorHandle();
-}
-
-//
-//  Wrapper function to call dmi_post_trainadv
-//
-void*    call_dmi_post_trainadv( void *io_pArgs )
-{
-    errlHndl_t l_errl = NULL;
-    ISTEP_ERROR::IStepError l_StepError;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_dmi_post_trainadv entry" );
-
-    TargetPairs_t l_dmi_post_trainadv_targets;
-    get_dmi_io_targets(l_dmi_post_trainadv_targets);
-
-    TARGETING::TargetHandleList l_cpuTargetList;
-    getAllChips(l_cpuTargetList, TYPE_PROC);
-
-
-    // Note:
-    // Due to lab tester board environment, HW procedure writer (Varkey) has
-    // requested to send in one target of a time (we used to send in
-    // the MCS and MEMBUF pair in one call). Even though they don't have to be
-    // in order, we should keep the pair concept here in case we need to send
-    // in a pair in the future again.
-    for (TargetPairs_t::const_iterator
-         l_itr = l_dmi_post_trainadv_targets.begin();
-         l_itr != l_dmi_post_trainadv_targets.end();
-         ++l_itr)
-    {
-        const fapi::Target l_fapi_mcs_target( TARGET_TYPE_MCS_CHIPLET,
-                (const_cast<TARGETING::Target*>(l_itr->first)));
-
-        const fapi::Target l_fapi_membuf_target( TARGET_TYPE_MEMBUF_CHIP,
-                (const_cast<TARGETING::Target*>(l_itr->second)));
-
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "===== Call dmi_post_trainadv HWP( mcs 0x%.8X, mem 0x%.8X) : ",
-                TARGETING::get_huid(l_itr->first),
-                TARGETING::get_huid(l_itr->second));
-
-        // Call on the MCS
-        FAPI_INVOKE_HWP(l_errl, io_post_trainadv, l_fapi_mcs_target);
-
-        if (l_errl)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR 0x%.8X :  dmi_post_trainadv HWP Target MCS 0x%.8X",
-                      l_errl->reasonCode(), TARGETING::get_huid(l_itr->first));
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_errl );
-
-            // Commit Error
-            errlCommit( l_errl, HWPF_COMP_ID );
-            // We want to continue the training despite the error, so
-            // no break
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  call_dmi_post_trainadv HWP - Target 0x%.8X",
-                    TARGETING::get_huid(l_itr->first));
-        }
-
-        // Call on the MEMBUF
-        FAPI_INVOKE_HWP(l_errl, io_post_trainadv, l_fapi_membuf_target);
-        if (l_errl)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                   "ERROR 0x%.8X :  dmi_post_trainadv HWP Target Membuf 0x%.8X",
-                   l_errl->reasonCode(), TARGETING::get_huid(l_itr->second));
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_errl );
-
-            // Commit Error
-            errlCommit( l_errl, HWPF_COMP_ID );
-            // We want to continue the training despite the error, so
-            // no break
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "SUCCESS :  call_dmi_post_trainadv HWP - Target 0x%.8X",
-                    TARGETING::get_huid(l_itr->second));
-        }
-
-    }
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_dmi_post_trainadv exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_StepError.getErrorHandle();
-}
-
-
-//
-//  Wrapper function to call  proc_cen_framelock
-//
-void*    call_proc_cen_framelock( void *io_pArgs )
-{
-    errlHndl_t l_err = NULL;
-    proc_cen_framelock_args     l_args;
-
-    IStepError l_StepError;
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "call_proc_cen_framework entry" );
-
-    //  get the mcs chiplets
-    TARGETING::TargetHandleList l_mcsTargetList;
-    getAllChiplets(l_mcsTargetList, TYPE_MCS);
-
-    for (TargetHandleList::const_iterator
-            l_mcs_iter = l_mcsTargetList.begin();
-            l_mcs_iter != l_mcsTargetList.end();
-            ++l_mcs_iter)
-    {
-        //  make a local copy of the MCS target
-        TARGETING::Target*  l_mcs_target = *l_mcs_iter;
-
-        //  find all the Centaurs that are associated with this MCS
-        TARGETING::TargetHandleList l_memTargetList;
-        getChildAffinityTargets(l_memTargetList, l_mcs_target,
-                 CLASS_CHIP, TYPE_MEMBUF);
-
-        for (TargetHandleList::const_iterator
-                l_mem_iter = l_memTargetList.begin();
-                l_mem_iter != l_memTargetList.end();
-                ++l_mem_iter)
-        {
-            //  make a local copy of the MEMBUF target
-            TARGETING::Target*  l_mem_target = *l_mem_iter;
-
-            uint8_t l_memNum = l_mem_target->getAttr<ATTR_POSITION>();
-
-            // fill out the args struct.
-            l_args.channel_init_timeout =   CHANNEL_INIT_TIMEOUT_NO_TIMEOUT;
-            l_args.frtl_auto_not_manual =   true;
-            l_args.frtl_manual_pu       =   0;
-            l_args.frtl_manual_mem      =   0;
-
-            fapi::Target l_fapiMcsTarget( TARGET_TYPE_MCS_CHIPLET,
-                        (const_cast<TARGETING::Target*>(l_mcs_target)));
-            fapi::Target l_fapiMemTarget( TARGET_TYPE_MEMBUF_CHIP,
-                        (const_cast<TARGETING::Target*>(l_mem_target)));
-
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "mcs HUID %.8X mem HUID %.8X",
-                TARGETING::get_huid(l_mcs_target),
-                TARGETING::get_huid(l_mem_target));
-
-            FAPI_INVOKE_HWP( l_err,
-                             proc_cen_framelock,
-                             l_fapiMcsTarget,
-                             l_fapiMemTarget,
-                             l_args  );
-            if ( l_err )
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                 "ERROR 0x%.8X : proc_cen_framelock HWP( mem %d )",
-                l_err->reasonCode(), l_memNum );
-
-                // Create IStep error log and cross ref error that occurred
-                l_StepError.addErrorDetails( l_err);
-
-                // Commit Error
-                errlCommit( l_err, HWPF_COMP_ID );
-
-            }
-            else
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                        "SUCCESS :  proc_cen_framelock HWP( mem %d ) ",
-                        l_memNum );
-            }
-
-        }   // end mem
-
-    }   // end mcs
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_proc_cen_framework exit" );
-
-    return l_StepError.getErrorHandle();
-}
-
-//
-//  Wrapper function to call host_startprd_dmi
-//
-void*    call_host_startprd_dmi( void *io_pArgs )
-{
-    errlHndl_t l_err = NULL;
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_startPRD_dmi entry" );
-
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_startPRD_dmi exit" );
-
-    return l_err;
-}
-
-//
-//  Wrapper function to call host_attnlisten_cen
-//
-void*    call_host_attnlisten_cen( void *io_pArgs )
-{
-
-    errlHndl_t l_err = NULL;
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_attnlisten_cen entry" );
-
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "call_host_attnlisten_cen exit" );
-
-    return l_err;
-}
-
-//
-//  Wrapper function to call cen_set_inband_addr
-//
-void*    call_cen_set_inband_addr( void *io_pArgs )
-{
-    IStepError l_StepError;
-    errlHndl_t l_err = NULL;;
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_cen_set_inband_addr entry" );
-
-    do{
-        //  get the mcs chiplets
-        TARGETING::TargetHandleList l_mcsTargetList;
-        getAllChiplets(l_mcsTargetList, TYPE_MCS);
-
-        for (TargetHandleList::const_iterator
-             l_mcs_iter = l_mcsTargetList.begin();
-             l_mcs_iter != l_mcsTargetList.end();
-             ++l_mcs_iter)
-        {
-            TARGETING::Target* l_pTarget = *l_mcs_iter;
-            const fapi::Target
-              l_fapi_target( TARGET_TYPE_MCS_CHIPLET,
-                             (const_cast<TARGETING::Target*>(l_pTarget)));
-
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "Running cen_set_inband_addr HWP on "
-                      "target HUID %.8X", TARGETING::get_huid(l_pTarget));
-
-            FAPI_INVOKE_HWP(l_err, proc_cen_set_inband_addr, l_fapi_target);
-            if ( l_err )
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "ERROR 0x%.8X : proc_cen_set_inband_addr HWP",
-                           l_err->reasonCode());
-
-                // capture the target data in the elog
-                ErrlUserDetailsTarget(l_pTarget).addToLog( l_err );
-
-                // Create IStep error log and cross ref error that occurred
-                l_StepError.addErrorDetails( l_err);
-
-                // Commit Error
-                errlCommit( l_err, HWPF_COMP_ID );
-
-            }
-            else
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "SUCCESS :  proc_cen_set_inband_addr HWP");
-            }
-        }   // end for mcs
-
-        l_err = l_StepError.getErrorHandle();
-
-        //Now enable Inband SCOM for all membuf chips.
-        IBSCOM::enableInbandScoms();
-    }while(0);
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_cen_set_inband_addr exit" );
-
-    return l_err;
-}
-
-//
-//  Utility function to get DMI IO target list
-//  First is MCS target, Second is MEMBUF target
-//
-void get_dmi_io_targets(TargetPairs_t& o_dmi_io_targets)
-{
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "get_dmi_io_targets" );
-
-    o_dmi_io_targets.clear();
-    TARGETING::TargetHandleList l_cpuTargetList;
-    getAllChips(l_cpuTargetList, TYPE_PROC);
-
-    for ( TargetHandleList::const_iterator
-          l_iter = l_cpuTargetList.begin();
-          l_iter != l_cpuTargetList.end();
-          ++l_iter )
-    {
-        //  make a local copy of the CPU target
-        const TARGETING::Target*  l_cpu_target = *l_iter;
-
-        // find all MCS chiplets of the proc
-        TARGETING::TargetHandleList l_mcsTargetList;
-        getChildChiplets( l_mcsTargetList, l_cpu_target, TYPE_MCS );
-
-        for ( TargetHandleList::const_iterator
-              l_iterMCS = l_mcsTargetList.begin();
-              l_iterMCS != l_mcsTargetList.end();
-              ++l_iterMCS )
-        {
-            //  make a local copy of the MCS target
-            const TARGETING::Target*  l_mcs_target = *l_iterMCS;
-
-            //  find all the Centaurs that are associated with this MCS
-            TARGETING::TargetHandleList l_memTargetList;
-            getChildAffinityTargets(l_memTargetList, l_mcs_target,
-                     CLASS_CHIP, TYPE_MEMBUF);
-
-            for ( TargetHandleList::const_iterator
-                    l_iterMemBuf = l_memTargetList.begin();
-                    l_iterMemBuf != l_memTargetList.end();
-                    ++l_iterMemBuf )
-            {
-                //  make a local copy of the MEMBUF target
-                const TARGETING::Target*  l_mem_target = *l_iterMemBuf;
-                o_dmi_io_targets.insert(std::pair<const TARGETING::Target*,
-                  const TARGETING::Target*>(l_mcs_target, l_mem_target));
-
-            }  //end for l_mem_target
-
-        }   // end for l_mcs_target
-
-    }   // end for l_cpu_target
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, "get_dmi_io_targets exit" );
-
-    return;
-}
-
-};   // end namespace
-
diff --git a/src/usr/hwpf/hwp/dmi_training/dmi_training.H b/src/usr/hwpf/hwp/dmi_training/dmi_training.H
deleted file mode 100644
index 0d6042428..000000000
--- a/src/usr/hwpf/hwp/dmi_training/dmi_training.H
+++ /dev/null
@@ -1,297 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/dmi_training.H $                */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef  __DMI_TRAINING_DMI_TRAINING_H
-#define __DMI_TRAINING_DMI_TRAINING_H
-/**
- *  @file dmi_training.H
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/*  @tag isteplist
- *  @docversion     v1.18 (12/03/12)
- *  @istepname      dmi_training
- *  @istepnum       11
- *  @istepdesc      DMI Training
- *
- *  @{
- *      @substepnum     1
- *      @substepname    mss_getecid
- *      @substepdesc    : Read out ECID from all centaur chips
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    proc_dmi_scominit
- *      @substepdesc    : DMI Scom setup on P8 MCS
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     3
- *      @substepname    dmi_scominit
- *      @substepdesc    : Scom setup on centaur
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     4
- *      @substepname    dmi_erepair
- *      @substepdesc    : Restore EDI Bus eRepair data
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     5
- *      @substepname    dmi_io_dccal
- *      @substepdesc    : Calibrate DMI interfaces
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     6
- *      @substepname    dmi_pre_trainadv
- *      @substepdesc    : Advanced pre DMI training
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     7
- *      @substepname    dmi_io_run_training
- *      @substepdesc    : Run training on MC buses
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     8
- *      @substepname    dmi_post_trainadv
- *      @substepdesc    : Advanced post DMI training
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     9
- *      @substepname    proc_cen_framelock
- *      @substepdesc    : Initialize EDI Frame
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     10
- *      @substepname    host_startprd_dmi
- *      @substepdesc    : Load PRD for DMI domain
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     11
- *      @substepname    host_attnlisten_cen
- *      @substepdesc    : Start listening for attentions
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum    12
- *      @substepname    cen_set_inband_addr
- *      @substepdesc    : Set the Inband base addresses
- *          @target_sched   serial
- *  @}
- *
- */
-
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-
-namespace   DMI_TRAINING
-{
-
-/**
- * @brief   mss_getecid
- *
- *          Read out ECID of all centaur chips
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_mss_getecid( void * io_pArgs );
-
-/**
- * @brief   dmi_attr_update
- *
- *  Stub HWP to allow FW to override attributes programmatically
- *
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-
-void * call_dmi_attr_update( void * io_pArgs );
-
-/**
- * @brief   proc_dmi_scominit
- *
- *          DMI Scom setup on P8 MCS
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_proc_dmi_scominit( void * io_pArgs );
-
-
-/**
- * @brief   dmi_scominit
- *
- *          Scom setup on centaur
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_dmi_scominit( void * io_pArgs );
-
-
-/**
- *  @brief   dmi_erepair
- *
- *           Restore EDI Bus eRepair data
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_dmi_erepair( void * io_pArgs );
-
-
-/**
- *  @brief   dmi_io_dccal
- *
- *           Calibrate DMI interfaces
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_dmi_io_dccal( void * io_pArgs );
-
-
-/**
- *  @brief   dmi_pre_trainadv
- *
- *           Advanced pre DMI training
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_dmi_pre_trainadv( void * io_pArgs );
-
-
-/**
- *  @brief   dmi_io_run_training
- *
- *           Run training on MC buses
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_dmi_io_run_training( void * io_pArgs );
-
-
-/**
- *  @brief   dmi_post_trainadv
- *
- *           Advanced post DMI training
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_dmi_post_trainadv( void * io_pArgs );
-
-
-/**
- *  @brief  proc_cen_framelock
- *
- *          Initialize EDI Frame
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_proc_cen_framelock( void *io_pArgs );
-
-
-/**
- *  @brief   host_startprd_dmi
- *
- *           Load PRD for DMI domain
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_host_startprd_dmi( void * io_pArgs );
-
-
-/**
- *  @brief   host_attnlisten_cen
- *
- *           Start listening for attentions
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_host_attnlisten_cen( void * io_pArgs );
-
-
-/**
- *  @brief   cen_set_inband_addr
- *
- *           Set the Inband base addresses
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                               or NULL.
- *  return  any error logs to istep
- *
- */
-void*    call_cen_set_inband_addr( void * io_pArgs );
-
-
-};   // end namespace
-
-#endif
diff --git a/src/usr/hwpf/hwp/dmi_training/makefile b/src/usr/hwpf/hwp/dmi_training/makefile
deleted file mode 100644
index 7eeca2800..000000000
--- a/src/usr/hwpf/hwp/dmi_training/makefile
+++ /dev/null
@@ -1,71 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/dmi_training/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2012,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = dmi_training
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/mss_getecid
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_pre_trainadv
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_post_trainadv
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit
-
-OBJS += dmi_training.o
-OBJS += proc_cen_framelock.o
-OBJS += dmi_io_run_training.o
-OBJS += proc_cen_set_inband_addr.o
-OBJS += mss_get_cen_ecid.o
-OBJS += dmi_io_dccal.o
-OBJS += proc_dmi_scominit.o
-OBJS += cen_dmi_scominit.o
-OBJS += mss_get_cen_ecid_decode.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_run_training
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/mss_getecid
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/dmi_io_dccal
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_pre_trainadv
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_post_trainadv
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dmi_training/cen_dmi_scominit
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
deleted file mode 100644
index 3b32a46a5..000000000
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C
+++ /dev/null
@@ -1,456 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid.C,v 1.41 2015/02/11 15:26:08 janssens Exp $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : mss_get_cen_ecid.C
-// *! DESCRIPTION : Get ECID string from target using SCOM's
-// *!
-// *! OWNER NAME  : Mark Bellows Email: bellows@us.ibm.com
-// *! Copied From : Joe McGill's proc_cleanup code
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.41  | janssens |11-FEB-15| Fixed compile bug
-//   1.40  | sglancy  |11-FEB-15| Fixed Firmware compile bug
-//   1.39  | sglancy  |10-FEB-15| Removed hardcoding of centaur version and removed erroneous FAPI_ERR statement
-//   1.38  | sglancy  |03-FEB-15| Fixed bugs surrounding the ATTR_CENTAUR_BLUEWATERFALL_NWELL_BROKEN_CHECK_FLAG update
-//   1.37  | jprispol |03-NOV-14| Moved bluewaterfall/nwell variable declarations
-//   1.36  | jprispol |28-OCT-14| Updated bluewaterfall/nwell broken attribute name
-//   1.34  | jprispol |24-OCT-14| Replaced privileged fapi attribute call
-//   1.32  | sglancy  |08-MAY-14| Changed location of the setting ATTR_MSS_INIT_STATE to track IPL states
-//   1.31  | sglancy  |25-MAR-14| RAS review updates
-//   1.30  | bellows  |11-NOV-13| Gerrit review updates
-//   1.29  | bellows  |08-NOV-13| Added ATTR_MSS_INIT_STATE to track IPL states
-//   1.28  | bellows  |02-OCT-13| Minor Review Comments addressed
-//   1.27  | bellows  |26-SEP-13| Fixed Minor firware comment
-//   1.26  | bellows  |19-SEP-13| Fixed the bug in 1.24
-//   1.25  | bellows  |18-SEP-13| Back to 1.23 because of some issue
-//   1.24  | bellows  |17-SEP-13| Support for external wrappers and decode
-//   1.23  | bellows  |10-SEP-13| For DD2, no partial logic hardware bits
-//   1.22  | jones    |18-JUN-13| <attr ec use>
-//   1.21  | bellows  |14-JUN-13| ECBIT added for case when we can trust the cache enable
-//   1.20  | bellows  |22-MAY-13| Bluewaterfall matching actual ECID definition
-//   1.19  | bellows  |15-MAY-13| Added Bluewaterfall handling
-//   1.18  | bellows  |27-MAR-13| Fixes to rc handling from reviewer comments
-//   1.17  | bellows  |26-MAR-13| Additional reviewer comments
-//   1.16  | bellows  |26-MAR-13| Cleanup because of Firmware Gerrit Review Comments
-//   1.15  | bellows  |22-MAR-13| Changed name of ECID Attribute per Firmware request
-//   1.14  | bellows  |29-JAN-13| Getting sub version, setting NWELL Attribute
-//   1.13  | bellows  |24-JAN-13| Cache Disable Valid bit is ecid_128, made bit
-//         |          |         | number consistent
-//   1.12  | bellows  |23-JAN-13| PSRO attriubute is available in cronus dev
-//   1.11  | bellows  |21-JAN-13| fixed log comment
-//   1.10  | bellows  |21-JAN-13| chip sub id read, psro shell added
-//   1.9   | bellows  |15-JAN-13| moved Cache Enable Information to the caller
-//   1.8   | sglancy  |10-DEC-12| Corrected typo
-//   1.7   | sglancy  | 6-DEC-12| Updated to coincide with firmware updates to ECID attribute
-//   1.6   | sglancy  | 5-DEC-12| Updated to coincide with firmware change requests
-//   1.5-1 | sglancy  | 5-DEC-12| Lost due to no update log
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <mss_get_cen_ecid.H>
-
-extern "C" {
-
-using namespace fapi;
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-  fapi::ReturnCode  user_ecid(    uint8_t & o_ddr_port_status,
-                                  uint8_t & o_cache_enable,
-                                  uint8_t & o_centaur_sub_revision,
-                                  ecid_user_struct & ecid_struct
-                                  );
-
-// HWP entry point
-  fapi::ReturnCode mss_get_cen_ecid(
-                                    const fapi::Target& i_target,
-                                    uint8_t & o_ddr_port_status,
-                                    uint8_t & o_cache_enable,
-                                    uint8_t & o_centaur_sub_revision,
-                                    ecid_user_struct & ecid_struct
-                                    )
-  {
-    // return code
-    fapi::ReturnCode rc;
-
-
-    // set the init state attribute to CLOCKS_ON
-    uint8_t l_attr_mss_init_state;
-    l_attr_mss_init_state=ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON;
-    rc = FAPI_ATTR_SET(ATTR_MSS_INIT_STATE, &i_target, l_attr_mss_init_state);
-    if(rc) return rc;
-
-    uint8_t l_bluewaterfall_nwell_broken;
-    rc = FAPI_ATTR_GET(ATTR_CENTAUR_BLUEWATERFALL_NWELL_BROKEN_CHECK_FLAG,
-                    &i_target, l_bluewaterfall_nwell_broken);
-    // For certain Centaur DD1.0* subversions, adjustments need to be made to
-    // the bluewaterfall and the transistor misplaced in the nwell.
-    // l_bluewaterfall_nwell_broken will be 1 if needing changes and 0 if not
-    if (!rc.ok()) {
-        FAPI_ERR("mss_get_cen_ecid: could not GET ATTR_CENTAUR_BLUEWATERFALL_NWELL_BROKEN_CHECK_FLAG" );
-        return rc;
-    }
-
-    if(l_bluewaterfall_nwell_broken) ecid_struct.io_ec = 0x10;
-    else ecid_struct.io_ec = 0x20;
-    FAPI_INF("Centaur EC version 0x%02x",ecid_struct.io_ec);
-    
-    if(ecid_struct.valid) {
-
-      rc = mss_parse_ecid(ecid_struct.io_ecid,
-                          ecid_struct.i_checkL4CacheEnableUnknown,
-                          ecid_struct.i_ecidContainsPortLogicBadIndication,
-                          l_bluewaterfall_nwell_broken,
-                          o_ddr_port_status,
-                          o_cache_enable,
-                          o_centaur_sub_revision,
-                          ecid_struct.o_psro,
-                          ecid_struct.o_bluewaterfall_broken,
-                          ecid_struct.o_nwell_misplacement );
-
-      // procedure is done.
-      return rc;
-    }
-
-    uint8_t l_psro;
-
-    // mark HWP entry
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase scom(64);
-    FAPI_IMP("Entering mss_get_cen_ecid....");
-    rc = fapiGetScom( i_target, ECID_PART_0_0x00010000, scom );
-    if (rc)
-    {
-      FAPI_ERR("mss_get_cen_ecid: could not read scom address 0x00010000" );
-      return rc;
-    }
-    rc_ecmd = scom.reverse();
-    if(rc_ecmd)
-    {
-      FAPI_ERR("mss_get_cen_ecid: error manipulating ecmdDataBufferBase");
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    ecid_struct.io_ecid[0] = scom.getDoubleWord(0);
-
-    //gets the second part of the ecid and sets the attribute
-    rc = fapiGetScom( i_target, ECID_PART_1_0x00010001, scom );
-    if (rc)
-    {
-      FAPI_ERR("mss_get_cen_ecid: could not read scom address 0x00010001" );
-      return rc;
-    }
-    rc_ecmd |= scom.reverse();
-    if(rc_ecmd)
-    {
-      FAPI_ERR("mss_get_cen_ecid: error manipulating ecmdDataBufferBase");
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    ecid_struct.io_ecid[1] = scom.getDoubleWord(0);
-
-    uint64_t ecid[2];
-    ecid[0]=ecid_struct.io_ecid[0];
-    ecid[1]=ecid_struct.io_ecid[1];
-
-    rc = FAPI_ATTR_SET(ATTR_ECID, &i_target, ecid);
-    if (rc)
-    {
-      FAPI_ERR("mss_get_cen_ecid: Could not set ATTR_ECID" );
-      return rc;
-    }
-
-    uint8_t l_checkL4CacheEnableUnknown = 0;
-    rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_CHECK_L4_CACHE_ENABLE_UNKNOWN,
-                       &i_target, l_checkL4CacheEnableUnknown);
-    if (!rc.ok()) {
-      FAPI_ERR("mss_get_cen_ecid: could not get ATTR_CENTAUR_EC_CHECK_L4_CACHE_ENABLE_UNKNOWN" );
-      return rc;
-    }
-
-    uint8_t l_ecidContainsPortLogicBadIndication = 0;
-    rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ECID_CONTAINS_PORT_LOGIC_BAD_INDICATION,
-                       &i_target, l_ecidContainsPortLogicBadIndication);
-    if (!rc.ok()) {
-      FAPI_ERR("mss_get_cen_ecid: could not get ATTR_CENTAUR_EC_ECID_CONTAINS_PORT_LOGIC_BAD_INDICATION" );
-      return rc;
-    }
-
-    uint8_t l_bluewaterfall_broken;
-    uint8_t l_nwell_misplacement;
-    rc = mss_parse_ecid(ecid,
-                        l_checkL4CacheEnableUnknown,
-                        l_ecidContainsPortLogicBadIndication,
-                        l_bluewaterfall_nwell_broken,
-                        o_ddr_port_status,
-                        o_cache_enable,
-                        o_centaur_sub_revision,
-                        l_psro,
-                        l_bluewaterfall_broken,
-                        l_nwell_misplacement );
-
-    ecid_struct.o_psro=l_psro;
-    ecid_struct.o_bluewaterfall_broken=l_bluewaterfall_broken;
-    ecid_struct.o_nwell_misplacement=l_nwell_misplacement;
-
-    if (rc)
-    {
-      FAPI_ERR("mss_get_cen_ecid: mss_parse_ecid" );
-      return rc;
-    }
-
-    rc = FAPI_ATTR_SET(ATTR_MSS_PSRO, &i_target, l_psro);
-    if (!rc.ok()) {
-      FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_PSRO" );
-      return rc;
-    }
-
-    rc = FAPI_ATTR_SET(ATTR_MSS_BLUEWATERFALL_BROKEN, &i_target, l_bluewaterfall_broken);
-    if (!rc.ok()) {
-      FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_BLUEWATERFALL_BROKEN" );
-      return rc;
-    }
-
-    rc = FAPI_ATTR_SET(ATTR_MSS_NWELL_MISPLACEMENT, &i_target, l_nwell_misplacement);
-    if (!rc.ok()) {
-      FAPI_ERR("mss_get_cen_ecid: could not set ATTR_MSS_NWELL_MISPLACEMENT" );
-      return rc;
-    }
-    
-   // mark HWP exit
-    FAPI_IMP("Exiting mss_get_cen_ecid....");
-    return rc;
-  }
-
-// Decoder function which allows us to pass in just the raw ECID data and get it decoded for in the lab
-// or we can just use it to set up all the needed attributes
-
-  fapi::ReturnCode  mss_parse_ecid(uint64_t ecid[2],
-                                   const uint8_t i_checkL4CacheEnableUnknown,
-                                   const uint8_t i_ecidContainsPortLogicBadIndication,
-                                   const uint8_t i_bluewaterfall_nwell_broken,
-                                   uint8_t & o_ddr_port_status,
-                                   uint8_t & o_cache_enable,
-                                   uint8_t & o_centaur_sub_revision,
-                                   uint8_t & o_psro,
-                                   uint8_t & o_bluewaterfall_broken,
-                                   uint8_t & o_nwell_misplacement ){
-//get bit128
-    uint8_t bit128 = 0;
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase scom(64);
-
-    o_nwell_misplacement = 0;
-    o_bluewaterfall_broken = 0;
-
-
-    rc_ecmd = scom.setDoubleWord(0, ecid[1]);
-    if(rc_ecmd) {
-      FAPI_ERR("mss_get_cen_ecid: error manipulating ecmdDataBufferBase" );
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd |= scom.extract(&bit128,63,1);
-    bit128 = bit128 >> 7;
-    if(rc_ecmd) {
-      FAPI_ERR("mss_get_cen_ecid: could not extract cache data_valid bit" );
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-
-    if(bit128 == 1) { // Cache enable bit is valid
-
-    //gets bits 113 and 114 to determine the state of the cache
-      uint8_t bit113_114=0;
-      rc_ecmd |= scom.extract(&bit113_114,48,2);
-      bit113_114 = bit113_114 >> 6;
-      uint8_t t;
-      if(rc_ecmd) {
-        FAPI_ERR("mss_get_cen_ecid: could not extract cache data" );
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-      }
-    //determines the state of the cache
-      if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON;
-      else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A;
-      else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B;
-      else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
-
-    // Centaur DD1.X chips have an ECBIT in bit127, if this is zero then the
-    // cache enable bits are in an unknown state. DD2.X chips and higher do not
-    // have an ECBIT. The decision to look at the ECBIT is done with a Chip EC
-    // Feature Attribute - the attribute XML can be easily tweaked if it is
-    // found that other DD levels also have an ECBIT.
-    // Centaur | DataValid | ECBIT  | Return Value   | Firmware Action | Cronus Action**|
-    // 1.*     | 0         | 0 or 1 | DIS            | DIS             | DIS            |
-    // 1.*     | 1         | 0      | Unk ENA/DIS/A/B| DIS             | ENA/DIS/A/B    |
-    // 1.*     | 1         | 1      | ENA/DIS/A/B    | ENA/DIS*        | ENA/DIS/A/B    |
-    // != 1.*  | 0         | N/A    | DIS            | DIS             | DIS            |
-    // != 1.*  | 1         | N/A    | ENA/DIS/A/B    | ENA/DIS         | ENA/DIS/A/B    |
-    // 
-    // * firmware can suport paritial cache if it wants to for DD1.* (e.g. DD1.0 DD1.01, DD1.1 etc)
-    //    However, if it chooses to, it should still make all Unk ones disabled
-    // ** Cronus Action - cronus and all fapi procedures only support the original defintion of ENA/DIS/A/B
-    //    Cronus actually uses its config file for the 4 values and checks the hardware via the get_cen_ecid
-    //    procedure during step 11 to make sure the end user does not enable a disable cache
-    //    Under cronus, the Unk information is only printed to the screen
-
-      if (i_checkL4CacheEnableUnknown)
-      {
-        uint8_t bit127 = 0;
-        rc_ecmd |= scom.extract(&bit127,62,1);
-        bit127 = bit127 >> 7;
-        if(rc_ecmd) {
-          FAPI_ERR("mss_get_cen_ecid: could not extract ECBIT bit" );
-          rc.setEcmdError(rc_ecmd);
-          return rc;
-        }
-        if(bit127 == 0) {
-          FAPI_INF("mss_get_cen_ecid: Cache Enable Bits are in Unknown State");
-          if(bit113_114 == 0) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_ON;
-          else if(bit113_114 == 1) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_A;
-          else if(bit113_114 == 2) t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_B;
-          else t = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_OFF;
-        }
-        else
-        {
-          FAPI_INF("mss_get_cen_ecid: Cache Enable Bits are in Known State");
-        }
-      }
-
-      o_cache_enable = t;
-    }
-    else {
-      FAPI_INF("Cache Disbled because eDRAM data bits are assumed to be bad");
-      o_cache_enable = fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF;
-    }
-
-    //reads in the ECID info for whether a DDR port side is good or bad
-    //This is only defined for DD1.x parts
-    if(i_ecidContainsPortLogicBadIndication ) {
-      rc_ecmd |= scom.extract(&o_ddr_port_status,50,2);
-      if(rc_ecmd) {
-        FAPI_ERR("mss_get_cen_ecid: could not extract DDR status data" );
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-      }
-      o_ddr_port_status = o_ddr_port_status >> 6;
-    }
-    else {
-      o_ddr_port_status = 0x0; // logic in both ports are good
-    }
-
-
-     //116..123         average PSRO from 85C wafer test
-    uint8_t bit117_124=0;
-    rc_ecmd |= scom.extract(&bit117_124,52,8);
-    if(rc_ecmd) {
-      FAPI_ERR("mss_get_cen_ecid: could not extract PSRO" );
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    o_psro=bit117_124;
-
-    // read the bit in the ecid to see if we are a DD1.01
-   // Bit 124 DD1.01  Indicator Bit. Set to '1' for DD1.01 devices
-    uint8_t bit125 =0;
-    rc_ecmd = scom.extract(&bit125,60,1);
-    bit125 = bit125 >> 7;
-    if(rc_ecmd) {
-      FAPI_ERR("mss_get_cen_ecid: could not extract dd1.01 indicator bit" );
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    o_centaur_sub_revision=bit125;
-    // The ecid contains the chip's subrevision, changes in the subrevision should not
-    // change firmware behavior but for the exceptions, update attributes to indicate
-    // those behaviors
-    if (i_bluewaterfall_nwell_broken && (o_centaur_sub_revision < 1))
-    {
-  // For DD1.00, the transistor misplaced in the nwell needs some setting adjustments to get it to function
-  // after DD1.00, we no longer need to make that adjustment
-      o_nwell_misplacement = 1;
-    }
-
-    uint8_t bit126 =0;
-    rc_ecmd = scom.extract(&bit126,61,1);
-    bit126 = bit126 >> 7;
-    if(rc_ecmd) {
-      FAPI_ERR("mss_get_cen_ecid: could not extract dd1.03 indicator bit" );
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-
-  // we have to look at both the bluewaterfall and the n-well misplacement to determine the proper values of the n-well
-    if (i_bluewaterfall_nwell_broken) {
-      if(bit126 == 0)
-      {
-  // on and after DD1.03, we no longer need to make adjustments due to the bluewaterfall - this is before
-        o_bluewaterfall_broken = 1;
-      }
-      else {
-        o_nwell_misplacement = 0; // Assume if the bluewaterfall is fixed, then the nwell is also fixed
-      }
-    }
-
-    return rc;
-  }
-
-  fapi::ReturnCode  user_ecid(    uint8_t & o_ddr_port_status,
-                                  uint8_t & o_cache_enable,
-                                  uint8_t & o_centaur_sub_revision,
-                                  ecid_user_struct & ecid_struct
-                                  ){
-
-    return mss_parse_ecid(ecid_struct.io_ecid,
-                          ecid_struct.i_checkL4CacheEnableUnknown,
-                          ecid_struct.i_ecidContainsPortLogicBadIndication,
-                          ecid_struct.i_bluewaterfall_nwell_broken,
-                          o_ddr_port_status,
-                          o_cache_enable,
-                          o_centaur_sub_revision,
-                          ecid_struct.o_psro,
-                          ecid_struct.o_bluewaterfall_broken,
-                          ecid_struct.o_nwell_misplacement );
-
-  }
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H
deleted file mode 100644
index b6e9ef23d..000000000
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H
+++ /dev/null
@@ -1,148 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid.H,v 1.14 2014/10/24 16:44:40 jprispol Exp $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : mss_get_cen_ecid.H
-// *! DESCRIPTION : Get ECID string from target using SCOM's
-// *!
-// *! OWNER NAME  : Mark Bellows Email: bellows@us.ibm.com
-// *! Copied From : Joe McGill's proc_cleanup code 
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.14  | jprispol |24-OCT-14| Replaced privileged fapi attr call in mss_get_cen_ecid.c
-//   1.11  | sglancy  |25-MAR-14| Minor Review Comments addressed
-//   1.10  | bellows  |02-OCT-13| Minor Review Comments addressed
-//   1.9   | bellows  |17-SEP-13| Allow for external wrapper parsing
-//   1.8   | bellows  |26-MAR-13| Reviewer found updates
-//   1.7   | bellows  |22-MAR-13| Changed commented name of ECID Attribute per Firmware request
-//   1.6   | bellows  |21-JAN-13| added in sub revision reader
-//   1.5   | bellows  |15-JAN-13| moved Cache Enable Information to the caller
-// 1.1-1.4 | various  |07-DEC-12| Original Program
-
-#ifndef _MSS_GET_CEN_ECID_H_
-#define _MSS_GET_CEN_ECID_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-
-//defines enumerators
-enum mss_get_cen_ecid_ddr_status
-{
-  MSS_GET_CEN_ECID_DDR_STATUS_ALL_GOOD = 0,
-  MSS_GET_CEN_ECID_DDR_STATUS_MBA1_BAD = 1,
-  MSS_GET_CEN_ECID_DDR_STATUS_MBA0_BAD = 2,
-  MSS_GET_CEN_ECID_DDR_STATUS_ALL_BAD = 3,
-};
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-class  ecid_user_struct {
-public:
-  uint8_t  valid;
-  uint8_t  i_checkL4CacheEnableUnknown;
-  uint8_t  i_ecidContainsPortLogicBadIndication;
-  uint8_t  i_bluewaterfall_nwell_broken;
-  uint8_t  i_user_defined;
-  uint8_t  io_ec;
-  uint64_t io_ecid[2];
-  uint8_t  o_psro;
-  uint8_t  o_bluewaterfall_broken;
-  uint8_t  o_nwell_misplacement;
-
-  ecid_user_struct();
-};
-
-inline   ecid_user_struct::ecid_user_struct() { valid=0; i_checkL4CacheEnableUnknown=0; i_ecidContainsPortLogicBadIndication=0; i_user_defined=0; io_ec=0; io_ecid[0]=0; io_ecid[1]=0;  }
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*mss_get_cen_ecid_FP_t)(const fapi::Target& i_target, uint8_t & o_ddr_port_status, uint8_t & o_cache_enable,      uint8_t & o_centaur_sub_revision, ecid_user_struct & user_data
-
-                         );
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-// function: FAPI mss_get_cen_ecid HWP entry point
-// parameters: i_target => cen chip target
-//             &o_ddr_port_status => indicates if the MBA's are bad, with MBA 1 being the rightmost bit and MBA 0 being the next to right most bit
-//             &o_cache_enable => what it would have set the cache enable attribute to if it sets attributes
-//             &o_centaur_sub_revision => the sub revision indicator between DD1.0 and DD1.01
-// returns: FAPI_RC_SUCCESS if FBC stop is deasserted at end of execution
-//          else FAPI return code for failing operation
-// Updates attributes: ATTR_ECID[2] -> bits 1-64 and 65-128 of the ECID
-//                     ATTR_MSS_PSRO -> average PSRO from 85C wafer test
-//                     ATTR_MSS_NWELL_MISPLACEMENT -> indicates if nwell defect in hardware
-  fapi::ReturnCode mss_get_cen_ecid(
-                                    const fapi::Target& i_target,
-                                    uint8_t & o_ddr_port_status,
-                                    uint8_t & o_cache_enable,
-                                    uint8_t & o_centaur_sub_revision,
-                                    ecid_user_struct & user_data
-
-                                    );
-
-  fapi::ReturnCode mss_parse_ecid(
-                                  uint64_t ecid[2], // input ECID in bit order
-                                  const uint8_t l_checkL4CacheEnableUnknown, // input L4CacheEnableUnknown is possible
-                                  const uint8_t l_ecidContainsPortLogicBadIndication, // input logic can be bad
-                                  const uint8_t l_bluewaterfall_nwell_broken, // adjustments possibly needed for bluewaterfall and transistor misplaced in the nwell
-                                  uint8_t & ddr_port, //output ddr ports are non functional
-                                  uint8_t & cache_enable_o, // output cache is functional or not
-                                  uint8_t & centaur_sub_revision_o, // output sub revsion number
-                                  uint8_t & o_psro, // output psro
-                                  uint8_t & o_bluewaterfall_broken, // output blue waterfall broken
-                                  uint8_t & o_nwell_misplacement   // output nwell misplacement
-                                  );
-
-
-
-} // extern "C"
-
-#endif // _MSS_GET_CEN_ECID_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C
deleted file mode 100644
index 8b34a8e1e..000000000
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C
+++ /dev/null
@@ -1,258 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid_decode.C,v 1.10 2015/02/03 15:08:48 sglancy Exp $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : mss_get_cen_ecid_decode.C
-// *! DESCRIPTION : Get ECID string from target using SCOM's
-// *!
-// *! OWNER NAME  : Mark Bellows Email: bellows@us.ibm.com
-// *! Copied From : Joe McGill's proc_cleanup code
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.10  | sglancy  |03-FEB-15| Fixed bugs surrounding the ATTR_CENTAUR_BLUEWATERFALL_NWELL_BROKEN_CHECK_FLAG update
-//   1.9   | bellows  |17-FEB-14| RAS Review Comments
-//   1.8   | bellows  |14-OCT-13| One more sprintf update to make this hostboot/cronus agnostic
-//   1.7   | bellows  |08-OCT-13| Made update so it compiles with cronus + hostboot
-//   1.6   | thi      |05-OCT-13| Fix compiler error
-//   1.5   | bellows  |02-OCT-13| Minor Review Comments addressed
-//   1.4   | bellows  |27-SEP-13| Removed std::string
-//   1.3   | bellows  |26-SEP-13| Firware comments and error checking added
-//   1.2   | bellows  |25-SEP-13| Changed the format so that the ECID bits are
-//         |          |         | broken into two lines.
-//   1.1   | bellows  |17-SEP-13| Initial version
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <mss_get_cen_ecid_decode.H>
-
-using namespace fapi;
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-// HWP entry point
-  fapi::ReturnCode mss_get_cen_ecid_decode(
-                                           uint8_t & i_ddr_port_status,
-                                           uint8_t & i_cache_enable,
-                                           uint8_t & i_centaur_sub_revision,
-                                           ecid_user_struct & i_user_info,
-                                           char * o_display_string
-                                           )
-  {
-    // return code
-    fapi::ReturnCode rc;
-
-
-//void decode_base_code(uint64_t ecid[2], uint8_t ddr_port, uint8_t cache_enable_o, uint8_t centaur_sub_revision_o, uint8_t nwell, uint8_t waterfall_broken, uint8_t user_input, uint8_t psro, uint8_t i_ec) {
-    //checks the DDR ports and outputs the results
-    //prints out all of the information
-    uint32_t t = i_user_info.io_ecid[0];
-    ecmdDataBufferBase temp(64);
-    uint64_t data[2];
-    data[0]=i_user_info.io_ecid[0];
-    data[1]=i_user_info.io_ecid[1];
-    char ecid_char;
-    uint8_t c;
-    float chip_version;
-    char  ECID[13];
-    for(int i=0;i<13;i++) ECID[i]='\0';
-    uint8_t x;
-    uint8_t y;
-    char temp_string[200];
-    uint32_t rc_num = 0;
-
-    o_display_string[0]='\0';
-
-
-    rc_num |= temp.insert(&t,32,32,0);
-    t = data[0] >> 32;
-    rc_num |= temp.insert(&t,0,32,0);
-    for(uint8_t i=0;i<10;i++)
-    {
-      rc_num |= temp.extract(&c,4+i*6,6);
-      c = c >> 2;
-      rc = get_ecid_char( c, &ecid_char);
-      if(rc)
-      {
-        FAPI_ERR("get_ecid_char returned with an error");
-        return rc;
-      }
-      ECID[i]=ecid_char;
-    }
-    get_ecid_checksum(ECID);
-
-    //generates the x and y location from the ecid
-    t = data[1];
-    rc_num |= temp.insert(&t,32,32,0);
-    t = data[1] >> 32;
-    rc_num |= temp.insert(&t,0,32,0);
-    rc_num |= temp.extract(&x,0,8);
-    rc_num |= temp.extract(&y,8,8);
-
-    chip_version=i_user_info.io_ec/0x10;
-
-    if(i_user_info.io_ec < 0x20)
-    {
-      if(!i_user_info.o_nwell_misplacement) chip_version = 1.01;
-      if(!i_user_info.o_bluewaterfall_broken) chip_version=1.10;
-    }
-    else {
-       chip_version=2.00;
-    }
-
-    if(!(i_user_info.i_user_defined & CSV))
-    {
-      sprintf(temp_string, "ECID(1:64)   0x%016llx\n", static_cast<unsigned long long int>(i_user_info.io_ecid[0]));
-      strcat(o_display_string, temp_string);
-      sprintf(temp_string, "ECID(65:128) 0x%016llx\n", static_cast<unsigned long long int>(i_user_info.io_ecid[1]));
-      strcat(o_display_string, temp_string);
-      sprintf(temp_string, "  Wafer ID: %s\n", ECID);
-      strcat(o_display_string, temp_string);
-      sprintf(temp_string, "  Chip X/Y loc: x:%d y:%d\n",x,y);
-      strcat(o_display_string, temp_string);
-      sprintf(temp_string, "  Chip version: DD%.02f\n",chip_version);
-      strcat(o_display_string, temp_string);
-
-      switch(i_cache_enable)
-      {
-          case  fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON:
-              sprintf(temp_string, "  All eDRAMs Halves are good\n"); // Note A is Even, B is Odd
-              break;
-          case fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A:
-              sprintf(temp_string, "  eDRAM Half A is good.  eDRAM Half B is bad\n");
-              break;
-          case ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B:
-              sprintf(temp_string, "  eDRAM Half A is bad.  eDRAM Half B is good\n");
-              break;
-          case ENUM_ATTR_MSS_CACHE_ENABLE_OFF:
-              sprintf(temp_string, "  All eDRAMs Halves are bad\n");
-              break;
-          case ENUM_ATTR_MSS_CACHE_ENABLE_UNK_ON:
-              sprintf(temp_string, "  All eDRAMs Halves are full unk good\n");
-              break;
-          case ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_A:
-              sprintf(temp_string, "  All eDRAMs A or Even unk good\n");
-              break;
-          case ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_B:
-              sprintf(temp_string, "  All eDRAMs B or odd  unk good\n");
-              break;
-          default:
-              sprintf(temp_string, "  All eDRAMs Halves are full unk bad\n");
-              break;
-      }
-      strcat(o_display_string, temp_string);
-
-      if(i_ddr_port_status == 0)   sprintf(temp_string, "  All DDR Ports are good\n"); 	
-      else if(i_ddr_port_status == 1) sprintf(temp_string, "  DDR Port 0/1 is good.  DDR Port 2/3 is bad\n");
-      else if(i_ddr_port_status == 2)   sprintf(temp_string, "  DDR Port 0/1 is bad.  DDR Port 2/3 is good\n");
-      else sprintf(temp_string, "  All DDR Ports are bad\n"); // this is informational, so no callouts are made
-      strcat(o_display_string, temp_string);
-
-      sprintf(temp_string, "  PSRO: 0x%02x %f ps\n",i_user_info.o_psro, i_user_info.o_psro*0.025+7.5);
-      strcat(o_display_string, temp_string);
-    }
-    //prints out a CSV
-    else 
-    {
-      uint8_t repair,bad_edram_a,bad_edram_b;
-      uint8_t bad_ddr_port01,bad_ddr_port23;
-      if(i_cache_enable == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_ON)  {repair=1;bad_edram_a=0;bad_edram_b=0; } 
-      else if(i_cache_enable == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_A) {repair=1;bad_edram_a=0;bad_edram_b=1; }
-      else if(i_cache_enable == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_HALF_B) {repair=1;bad_edram_a=1;bad_edram_b=0; }
-      else if(i_cache_enable == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_OFF) {repair=1;bad_edram_a=1;bad_edram_b=1; }
-//    else if(cache_enable_o == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_ON) {repair=0;bad_edram_a=0;bad_edram_b=0; } 
-//    else if(cache_enable_o == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_A) {repair=0;bad_edram_a=0;bad_edram_b=1; }
-//    else if(cache_enable_o == fapi::ENUM_ATTR_MSS_CACHE_ENABLE_UNK_HALF_B) {repair=0;bad_edram_a=1;bad_edram_b=0; }
-      else {repair=0;bad_edram_a=1;bad_edram_b=1; }
-
-      if(i_ddr_port_status == 0)   { bad_ddr_port01 = 0 ; bad_ddr_port23 = 0; }
-      else if(i_ddr_port_status == 1)   { bad_ddr_port01 = 0 ; bad_ddr_port23 = 1; }
-      else if(i_ddr_port_status == 2)   { bad_ddr_port01 = 1 ; bad_ddr_port23 = 0; }
-      else    { bad_ddr_port01 = 1 ; bad_ddr_port23 = 1; }
-      sprintf(o_display_string, "%s,%d,%d,%0.2f,%d,%d,%d,%d,%d,%f ps\n",ECID,x,y,chip_version,repair,bad_edram_a,bad_edram_b,bad_ddr_port01,bad_ddr_port23,((float)i_user_info.o_psro*0.025+7.5));
-    }
-
-    if(rc_num)
-    {
-      FAPI_ERR("Error occured during databuffer manipulations");
-      rc.setEcmdError(rc);
-    }
-
-    return rc;
-  }
-
-//gets the character for the ECID
-  fapi::ReturnCode get_ecid_char(uint8_t c, char *creturn)
-  {
-   //c is a number, so use the offset for a number
-    if(c < 10) {*creturn = (char)(c+48);}
-    else {*creturn = (char)(c+55);}
-    return fapi::FAPI_RC_SUCCESS;
-  }
-
-//gets the checksum, the last two characters, in the ecid string
-  void get_ecid_checksum(char ECID[13])
-  {
-    char rtn[13];
-    for(uint32_t i = 0; i < 10; i++) rtn[i] = ECID[i];
-    rtn[10]='A';
-    rtn[11]='0';
-    rtn[12]='\0';
-    int sum=0;
-    for (uint32_t i = 0; i < 12; i++)
-    {
-      sum = ((sum * 8) + (rtn[i] - 32)) % 59;
-    }
-    if (sum != 0)
-    {
-      int adjust = 59 - sum;
-      rtn[11] += adjust & 7;
-      adjust >>= 3;
-      rtn[10] += adjust & 7;
-    }
-    for (uint32_t i = 0; i < 13; i++)
-    {
-      ECID[i] = rtn[i];
-    }
-  }
-
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.H b/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.H
deleted file mode 100644
index 86edee48f..000000000
--- a/src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.H
+++ /dev/null
@@ -1,109 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/mss_getecid/mss_get_cen_ecid_decode.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_get_cen_ecid_decode.H,v 1.4 2014/02/19 13:41:32 bellows Exp $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : mss_get_cen_ecid_decode.H
-// *! DESCRIPTION : Decode the ECID into a string
-// *!
-// *! OWNER NAME  : Mark Bellows Email: bellows@us.ibm.com
-// *! Copied From : Joe McGill's proc_cleanup code 
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.4   | bellows  |19-FEB-14| RAS Review Updates
-//   1.3   | bellows  |02-OCT-13| Minor Review Comments addressed
-//   1.2   | bellows  |24-SEP-13| Fixed typo
-//   1.1   | bellows  |17-SEP-13| Original Program
-
-#ifndef _MSS_GET_CEN_ECID_DECODE_H_
-#define _MSS_GET_CEN_ECID_DECODE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <mss_get_cen_ecid.H>
-
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*mss_get_cen_ecid_decode_FP_t)(uint8_t & i_ddr_port_status, uint8_t & i_cache_enable,      uint8_t & i_centaur_sub_revision, ecid_user_struct & i_user_data, char *o_display_string
-                         );
-
-const int MSS_GET_CEN_ECID_DECODE_STRING_LENGTH=1000;
-
-//void decode_base_code(uint64_t ecid[2], uint8_t ddr_port, uint8_t cache_enable_o, uint8_t centaur_sub_revision_o, uint8_t o_nwell_misplacement, uint8_t o_bluewaterfall_broken, uint8_t user_defined, uint8_t psro, uint8_t i_ec );
-//ReturnCode get_ecid_char(uint8_t c, char *creturn);
-//void get_ecid_checksum(char ECID[12]);
-
-enum user_flags {
-  USER_INPUT_ECID = 1,
-  CSV = 2,
-  COMMENT = 4,
-};
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-// function: FAPI mss_get_cen_ecid_decode HWP entry point
-// parameters:
-//             &o_ddr_port_status => indicates if the MBA's are bad, with MBA 1 being the rightmost bit and MBA 0 being the next to right most bit
-//             &o_cache_enable => what it would have set the cache enable attribute to if it sets attributes
-//             &o_centaur_sub_revision => the sub revision indicator between DD1.0 and DD1.01
-//             &o_user_data => holder for additional information for printing
-//             &o_display_string -> output string- max of MSS_GET_CEN_ECID_DECODE_STRING_LENGTH length  
-// returns: FAPI_RC_SUCCESS if FBC stop is deasserted at end of execution
-//          else FAPI return code for failing operation
-  fapi::ReturnCode mss_get_cen_ecid_decode(
-                                    uint8_t & i_ddr_port_status,
-                                    uint8_t & i_cache_enable,
-                                    uint8_t & i_centaur_sub_revision,
-                                    ecid_user_struct & i_user_data,
-                                    char * o_display_string
-
-                                    );
-  fapi::ReturnCode get_ecid_char(uint8_t c, char *creturn); // print helping function
-  void get_ecid_checksum(char ECID[13]);
-
-} // extern "C"
-
-#endif // _MSS_GET_CEN_ECID_DECODE_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
deleted file mode 100644
index c128825a3..000000000
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ /dev/null
@@ -1,2246 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_cen_framelock.C,v 1.31 2015/03/31 20:53:36 baysah Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_cen_framelock.C
-// *! DESCRIPTION : Run framelock and FRTL (FAPI)
-// *!
-// *! OWNER NAME  : Irving Baysah           Email: baysah@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-// Change Log
-// Version | who      |Date     | Comment
-// -----------------------------------------------------------------------------
-//         |          |         |
-//   1.31  | baysah   |31-MAR-15| Defect SW298496 was rejected by mustfix board due to assumed risk with no real benefits of the function to customers.
-//         |          |         |
-//   1.30  | baysah   |24-MAR-15| Defect SW298496 required MCIFIR(32) to be unmasked and set as recoverable to allow PRD
-//         |          |         | to threshold on Mirror channel before shutting down a channel.
-//         |          |         |
-//   1.29  | bwieman  |08-jan-14| revert of 1.28
-//   1.28  | baysah   |12-DEC-14| Masked MCIFIR(26) MCIFIRQ_POWERBUS_PROTOCOL_ERROR due to CAPI defect HW281374
-//         |          |         |
-//   1.27  | baysah   |09-MAY-14| Added Delay in status register polling routine
-//         |          |         |
-//   1.25  | baysah   |11-APR-14| Changed MBI internal scom FIRs from masked to recoverable error per Marc Gollub
-//         |          |         |
-//   1.24  | baysah   |07-APR-14| Changed seqid_ooo, MBIFIR(4) and MCIFIR(4), to masked per RAS request since it gets trigger by 1 crc error.
-//         |          |         | Made MCIFIR(46,48,49) as checkstop in Vendd1(bit 46 only) and Vendd2 and Murdd2 for all 3 fir bits .
-//         |          |         | Made MCIFIR(40) recoverable for MurDD2 and VenDD2, its a xstop for DD1 processors.
-//         |          |         |
-//   1.23  | gollub   |07-APR-14| Added call to mss_unmask_inband_errors (used to be called in mss_draminit_mc)
-//   1.22  | baysah   |05-MAR-14| Fix for Defect SW248451 is to change replay buffer overrun to checkstop in MCI
-//   1.20  | bellows  |25-NOV-13| Changed include to use <> instead of "" for hostboot
-//   1.19  | bellows  |08-NOV-13| Added ATTR_MSS_INIT_STATE to track IPL states
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_cen_framelock.H>
-#include <mss_unmask_errors.H>
-
-extern "C"
-{
-using namespace fapi;
-
-fapi::ReturnCode proc_cen_framelock_cloned(const fapi::Target& i_pu_target,
-                                    const fapi::Target& i_mem_target,
-                                    const proc_cen_framelock_args& i_args);
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear the Centaur MBI Status Register
-// parameters: i_mem_target  => Centaur target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_stat_reg(
-    const fapi::Target& i_mem_target )
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase zero_data(64);
-
-    //FAPI_DBG("proc_cen_framelock_clear_cen_mbi_stat_reg: Start");
-
-    rc = fapiPutScom(i_mem_target, MBI_STAT_0x0201080B, zero_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_clear_cen_mbi_stat_reg: fapiPutScom error (MBI_STAT_0x0201080B)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to get the Centaur MBI Status Register
-// parameters: i_mem_target  => Centaur target
-//             o_data        => Output data
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_get_cen_mbi_stat_reg(
-    const fapi::Target& i_mem_target,
-    ecmdDataBufferBase& o_data)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_get_cen_mbi_stat_reg: Start");
-
-    rc = fapiGetScom(i_mem_target, MBI_STAT_0x0201080B, o_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_get_cen_mbi_stat_reg: fapiGetScom error (MBI_STAT_0x0201080B)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear the Centaur MBI FIR Register
-// parameters: i_mem_target  => Centaur target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_clear_cen_mbi_fir_reg(
-    const fapi::Target& i_mem_target)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase zero_data(64);
-
-    //FAPI_DBG("proc_cen_framelock_clear_cen_mbi_fir_reg: Start");
-
-    rc = fapiPutScom(i_mem_target, MBI_FIR_0x02010800, zero_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_clear_cen_mbi_fir_reg: fapiPutScom error (MBI_FIR_0x02010800)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to get the Centaur MBI FIR Register
-// parameters: i_mem_target  => Centaur target
-//             o_data        => Output data
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_get_cen_mbi_fir_reg(
-    const fapi::Target& i_mem_target,
-    ecmdDataBufferBase& o_data)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_get_cen_mbi_fir_reg: Start");
-
-    rc = fapiGetScom(i_mem_target, MBI_FIR_0x02010800, o_data);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_get_cen_mbi_fir_reg: fapiGetScom error (MBI_FIR_0x02010800)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear the P8 MCI Status Register
-// parameters: i_pu_target  => P8 MCS chip unit target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_clear_pu_mci_stat_reg(
-    const fapi::Target& i_pu_target)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase zero_data(64);
-
-    //FAPI_DBG("proc_cen_framelock_clear_pu_mci_stat_reg: Start");
-
-    rc = fapiPutScom(i_pu_target, MCS_MCISTAT_0x0201184B, zero_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_clear_pu_mci_stat_reg: fapiPutScom error (MCS_MCISTAT_0x0201184B)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to get the P8 MCI Status Register
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             o_data       => Output data
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_get_pu_mci_stat_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& o_data)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_get_pu_mci_stat_reg: Start");
-
-    rc = fapiGetScom(i_pu_target, MCS_MCISTAT_0x0201184B, o_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_get_pu_mci_stat_reg: fapiGetScom error (MCS_MCISTAT_0x0201184B)");
-    }
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear the P8 MCI FIR Register
-// parameters: i_pu_target  => P8 MCS chip unit target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_clear_pu_mci_fir_reg(
-    const fapi::Target& i_pu_target)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase zero_data(64);
-
-    //FAPI_DBG("proc_cen_framelock_clear_pu_mci_fir_reg: Start");
-
-    rc = fapiPutScom(i_pu_target, MCS_MCIFIR_0x02011840, zero_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_clear_pu_mci_fir_reg: fapiPutScom error (MCS_MCIFIR_0x02011840)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to get the P8 MCI FIR Register
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             o_data       => output data
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_get_pu_mci_fir_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& o_data)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_get_pu_mci_fir_reg: Start");
-
-    rc = fapiGetScom(i_pu_target, MCS_MCIFIR_0x02011840, o_data);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_get_pu_mci_fir_reg: fapiGetScom error (MCS_MCIFIR_0x02011840)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the Centaur MBI Config Register
-// parameters: i_mem_target => Centaur target
-//             i_data       => Input data
-//             i_mask       => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_cen_mbi_cfg_reg(
-    const fapi::Target& i_mem_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_cfg_reg: Start");
-    rc = fapiPutScomUnderMask(i_mem_target, MBI_CFG_0x0201080A, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_cen_mbi_cfg_reg: fapiPutScomUnderMask error (MBI_CFG_0x0201080A)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the P8 MCI Config Register
-// parameters: i_pu_target => P8 MCS chip unit target
-//             i_data      => Input data
-//             i_mask      => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_pu_mci_cfg_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_pu_mci_cfg_reg: Start");
-
-    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCICFG_0x0201184A, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_pu_mci_cfg_reg: fapiPutScomUnderMask error (MCS_MCICFG_0x0201184A)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the Centaur MBI FIR Mask Register
-// parameters: i_mem_target => Centaur target
-//             i_data       => Input data
-//             i_mask       => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_cen_mbi_firmask_reg(
-    const fapi::Target& i_mem_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_firmsk_reg: Start");
-    rc = fapiPutScomUnderMask(i_mem_target, MBI_FIRMASK_0x02010803, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_cen_mbi_firmask_reg: fapiPutScomUnderMask error (MBI_FIRMASK_0x02010803)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the Centaur MBI FIR Action0 Register
-// parameters: i_mem_target => Centaur target
-//             i_data       => Input data
-//             i_mask       => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_cen_mbi_firact0_reg(
-    const fapi::Target& i_mem_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_firact0_reg: Start");
-    rc = fapiPutScomUnderMask(i_mem_target, MBI_FIRACT0_0x02010806, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_cen_mbi_firact0_reg: fapiPutScomUnderMask error (MBI_FIRACT0_0x02010806)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the Centaur MBI FIR Action1 Register
-// parameters: i_mem_target => Centaur target
-//             i_data       => Input data
-//             i_mask       => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_cen_mbi_firact1_reg(
-    const fapi::Target& i_mem_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_cen_mbi_firact1_reg: Start");
-    rc = fapiPutScomUnderMask(i_mem_target, MBI_FIRACT1_0x02010807, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_cen_mbi_firact1_reg: fapiPutScomUnderMask error (MBI_FIRACT1_0x02010807)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the P8 MCI FIR Mask Register
-// parameters: i_pu_target => P8 MCS chip unit target
-//             i_data      => Input data
-//             i_mask      => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_pu_mci_firmask_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_pu_mci_firmask_reg: Start");
-
-    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCIFIRMASK_0x02011843, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_pu_mci_firmask_reg: fapiPutScomUnderMask error (MCS_MCIFIRMASK_0x02011843)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the P8 MCI FIR Action0 Register
-// parameters: i_pu_target => P8 MCS chip unit target
-//             i_data      => Input data
-//             i_mask      => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_pu_mci_firact0_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_pu_mci_firact0_reg: Start");
-
-    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCIFIRACT0_0x02011846, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_pu_mci_firact0_reg: fapiPutScomUnderMask error (MCS_MCIFIRACT0_0x02011846)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the P8 MCI FIR Action1 Register
-// parameters: i_pu_target => P8 MCS chip unit target
-//             i_data      => Input data
-//             i_mask      => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_pu_mci_firact1_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_pu_mci_firact1_reg: Start");
-
-    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCIFIRACT1_0x02011847, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_pu_mci_firact1_reg: fapiPutScomUnderMask error (MCS_MCIFIRACT1_0x02011847)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set the P8 MCS Mode4 Register
-// parameters: i_pu_target => P8 MCS chip unit target
-//             i_data      => Input data
-//             i_mask      => Input mask
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_set_pu_mcs_mode4_reg(
-    const fapi::Target& i_pu_target,
-    ecmdDataBufferBase& i_data,
-    ecmdDataBufferBase& i_mask)
-{
-    fapi::ReturnCode rc;
-
-    //FAPI_DBG("proc_cen_framelock_set_pu_mcs_mode4_reg: Start");
-
-    rc = fapiPutScomUnderMask(i_pu_target, MCS_MCSMODE4_0x0201181A, i_data, i_mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_set_pu_mcs_mode4_reg: fapiPutScomUnderMask error (MCS_MCSMODE4_0x0201181A)");
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to initiate P8/Centaur framelock operation and
-//           poll for completion
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur chip target
-//             i_args       => proc_cen_framelock HWP argumemt structure
-// returns: FAPI_RC_SUCCESS if framelock sequence completes successfully,
-//          RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR_MCS
-//          RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR_MEMBUF
-//              if MCI FIR is set during framelock operation,
-//          RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR
-//              if MCI indicates framelock operation failure
-//          RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR
-//              if MCI does not post pass/fail indication after framelock
-//              operation is started,
-//          else FAPI getscom/putscom return code for failing SCOM operation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_framelock(
-    const fapi::Target& i_pu_target,
-    const fapi::Target& i_mem_target,
-    const proc_cen_framelock_args& i_args)
-{
-    // data buffers
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase mask(64);
-    ecmdDataBufferBase mci_stat(64);
-    ecmdDataBufferBase mci_fir(64);
-    ecmdDataBufferBase errstate(8);
-
-    // Reference variables matching error XML
-    const ecmdDataBufferBase & MCI_STAT = mci_stat;
-    const ecmdDataBufferBase & MCI_FIR = mci_fir;
-    const fapi::Target & MCS_CHIPLET = i_pu_target;
-    const fapi::Target & MEMBUF_CHIP = i_mem_target;
-
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-
-    FAPI_DBG("proc_cen_framelock_run_framelock: Starting framelock sequence ...");
-
-    // Clear P8 MCI FIR registers
-    rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing P8 MCI FIR regs");
-        return rc;
-    }
-
-
-    // Clear P8 Status registers
-    rc = proc_cen_framelock_clear_pu_mci_stat_reg(i_pu_target);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_framelock: Error clearing P8 MCI Status regs");
-        return rc;
-    }
-
-
-    // set channel init timeout value in P8 MCI Configuration Register
-    // FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to set channel init timeout value ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= mask.flushTo0();
-    rc_ecmd |= data.insertFromRight(
-        (uint32_t) (i_args.channel_init_timeout &
-                    MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    rc_ecmd |= mask.setBit(
-        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to set init timeout",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to set init timeout");
-        return rc;
-    }
-
-    // start framelock
-    // FAPI_DBG("proc_cen_framelock_run_framelock: Writing P8 MCI Configuration Register to initiate framelock ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_START_FRAMELOCK_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_framelock: Error 0x%x setting up data buffers to initiate framelock",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_framelock: Error writing P8 MCI Configuration register to initiate framelock");
-        return rc;
-    }
-
-    // poll until framelock operation is finished, a timeout is deemed to
-    // have occurred, or an error is detected
-    uint8_t polls = 0;
-
-    while (polls < PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
-    {
-        // Read P8 MCI Status Register
-        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI Status Register");
-            return rc;
-        }
-
-        // Read P8 MCI FIR Register
-        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Error reading P8 MCI FIR Register");
-            return rc;
-        }
-
-        // Fail if P8 MCI Frame Lock FAIL
-        if (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI STAT");
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if MCI FIR bits are set
-        if (mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI FIR errors set (MCS)");
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR_MCS);
-            return rc;
-        }
-
-        if (mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_framelock: Framelock fail. P8 MCI FIR errors set (MEMBUF)");
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_P8_FIR_ERR_MEMBUF);
-            return rc;
-        }
-
-        // Success if P8 PASS bits set
-        if ((mci_stat.isBitSet(MCI_STAT_FRAMELOCK_PASS_BIT)) )
-        {
-            FAPI_INF("proc_cen_framelock_run_framelock: Framelock completed successfully!");
-            break;
-        }
-        else
-        {
-            polls++;
-            FAPI_INF("proc_cen_framelock_run_framelock: Framelock not done, loop %d of %d...",
-                     polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
-
-
-            // 1ms/100simcycles delay
-            fapiDelay(1000000, 100); //fapiDelay(nanoseconds, simcycles)
-
-        }
-    }
-
-    if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
-    {
-        // Loop count has expired, timeout
-        FAPI_ERR("proc_cen_framelock_run_framelock:!!!! NO FRAME LOCK STATUS DETECTED !!!!");
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FL_TIMEOUT_ERR);
-        return rc;
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to initiate P8/Centaur FRTL (frame round trip
-//           latency) determination and check for completion
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur chip target
-// returns: FAPI_RC_SUCCESS if FRTL sequence completes successfully,
-//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR_MCS
-//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR_MEMBUF
-//              if MCI FIR is set during FRTL operation,
-//          RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR
-//              if MCI indicates FRTL operation failure,
-//          RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR
-//              if MCI does not post pass/fail indication after FRTL
-//              operation is started,
-//          else FAPI getscom/putscom return code for failing SCOM operation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_frtl(
-    const fapi::Target& i_pu_target,
-    const fapi::Target& i_mem_target)
-{
-    // data buffers for putscom/getscom calls
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase mask(64);
-    ecmdDataBufferBase mci_stat(64);
-    ecmdDataBufferBase mci_fir(64);
-
-    // Reference variables matching error XML
-    const ecmdDataBufferBase & MCI_STAT = mci_stat;
-    const ecmdDataBufferBase & MCI_FIR = mci_fir;
-    const fapi::Target & MCS_CHIPLET = i_pu_target;
-    const fapi::Target & MEMBUF_CHIP = i_mem_target;
-
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_DBG("proc_cen_framelock_run_frtl: Starting FRTL sequence ...");
-
-    // start FRTL
-    // FAPI_DBG("proc_cen_framelock_run_frtl: Writing P8 MCI Configuration Register to initiate FRTL ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_START_FRTL_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_frtl: Error 0x%x setting up data buffers to initiate FRTL",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
-        return rc;
-    }
-
-    // Poll until FRTL operation is finished, a timeout is deemed to
-    // have occurred, or an error is detected
-    uint8_t polls = 0;
-
-    while (polls < PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
-    {
-        // Read P8 MCI Status Register
-        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI Status Register");
-            return rc;
-        }
-
-        // Read P8 MCI FIR Register
-        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_frtl: Error reading P8 MCI FIR Register");
-            return rc;
-        }
-
-        // Fail if P8 MCI FRTL FAIL or Channel Interlock Fail
-        if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)  ||
-            mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail. P8 MCI STAT");
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if MCI FIR bits are set
-        if (mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail. P8 FIR errors set (MCS)");
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR_MCS);
-            return rc;
-        }
-
-        if (mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_FRTL_COUNTER_OVERFLOW_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_frtl: FRTL fail. P8 FIR errors set (MEMBUF)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_FRTL_P8_FIR_ERR_MEMBUF);
-            return rc;
-        }
-
-        // Success if P8 FRTL and InterLock PASS bits are set
-        if ((mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)) &&
-            (mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT)))
-        {
-            FAPI_INF("proc_cen_framelock_run_frtl: FRTL (auto) completed successfully!");
-            break;
-        }
-        else
-        {
-            polls++;
-            FAPI_INF("proc_cen_framelock_run_frtl: FRTL not done, loop %d of %d...",
-                     polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
-
-
-            // 1ms/100simcycles delay
-            fapiDelay(1000000, 100); //fapiDelay(nanoseconds, simcycles)
-        }
-    }
-
-    if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
-    {
-        // Loop count has expired, timeout
-        FAPI_ERR("proc_cen_framelock_run_frtl:!!!! NO FRAME LOCK STATUS DETECTED !!!!");
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_FRTL_TIMEOUT_ERR);
-        return rc;
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to initiate P8/Centaur framelock operation and
-//           poll for completion after the first operation fails.
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur chip target
-//             i_args       => proc_cen_framelock HWP argumemt structure
-// returns: FAPI_RC_SUCCESS if framelock sequence completes successfully,
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_CEN_FIR_ERR
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_P8_FIR_ERR_MCS
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_P8_FIR_ERR_MEMBUF
-//              if MCI/MBI FIR is set during framelock operation,
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_CEN_FAIL_ERR
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_P8_FAIL_ERR
-//              if MCI/MBI indicates framelock operation failure
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_TIMEOUT_ERR
-//              if MCI/MBI does not post pass/fail indication after framelock
-//              operation is started,
-//          else FAPI getscom/putscom return code for failing SCOM operation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_errstate_framelock(
-    const fapi::Target& i_pu_target,
-    const fapi::Target& i_mem_target,
-    const proc_cen_framelock_args& i_args)
-{
-    // data buffers
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase mask(64);
-    ecmdDataBufferBase mbi_stat(64);
-    ecmdDataBufferBase mbi_fir(64);
-    ecmdDataBufferBase mci_stat(64);
-    ecmdDataBufferBase mci_fir(64);
-
-    // Reference variables matching error XML
-    const ecmdDataBufferBase & MCI_STAT = mci_stat;
-    const ecmdDataBufferBase & MCI_FIR = mci_fir;
-    const ecmdDataBufferBase & MBI_STAT = mbi_stat;
-    const ecmdDataBufferBase & MBI_FIR = mbi_fir;
-    const fapi::Target & MCS_CHIPLET = i_pu_target;
-    const fapi::Target & MEMBUF_CHIP = i_mem_target;
-
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Starting framelock Error State sequence ...");
-
-
-    // Clear MBI Channel Fail Configuration Bit
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MBI_CFG_FORCE_CHANNEL_FAIL_BIT);
-    rc_ecmd |= data.copy(mask);
-    rc_ecmd |= data.clearBit(MBI_CFG_FORCE_CHANNEL_FAIL_BIT);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x clearing MBI force channel fail bit",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data,  mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing Centaur MBI Configuration Register to clear the force channel fail bit");
-        return rc;
-    }
-
-
-    //Clear MCI Force Channel Fail Configuration Bit
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_FORCE_CHANNEL_FAIL_BIT);
-    rc_ecmd |= data.copy(mask);
-    rc_ecmd |= data.clearBit(MCI_CFG_FORCE_CHANNEL_FAIL_BIT);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x clearing MCI force channel fail bit",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to clear the force channel fail bit");
-        return rc;
-    }
-
-
-    // Clear Centaur MBI FIR registers
-    rc = proc_cen_framelock_clear_cen_mbi_fir_reg(i_mem_target);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing Centaur MBI FIR regs");
-        return rc;
-    }
-
-
-    // Clear Centaur MBI Status registers
-    rc = proc_cen_framelock_clear_cen_mbi_stat_reg(i_mem_target);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing Centaur MBI Status regs");
-        return rc;
-    }
-
-
-    // Clear P8 MCI FIR registers
-    rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing P8 MCI FIR regs");
-        return rc;
-    }
-
-
-    // Clear P8 Status registers
-    rc = proc_cen_framelock_clear_pu_mci_stat_reg(i_pu_target);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error clearing P8 MCI Status regs");
-        return rc;
-    }
-
-
-
-    // set channel init timeout value in P8 MCI Configuration Register
-    //FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Writing P8 MCI Configuration Register to set channel init timeout value ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= mask.flushTo0();
-    rc_ecmd |= data.insertFromRight(
-        (uint32_t) (i_args.channel_init_timeout &
-                    MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    rc_ecmd |= mask.setBit(
-        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to set init timeout",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to set init timeout");
-        return rc;
-    }
-
-
-    // start framelock on Centaur MBI
-    //FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Writing Centaur MBI Configuration Register to force framelock ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRAMELOCK_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to force framelock",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing Centaur MBI Configuration Register to force framelock");
-        return rc;
-    }
-
-
-    // start framelock on P8 MCI
-    //FAPI_DBG("proc_cen_framelock_run_errstate_framelock: Writing P8 MCI Configuration Register to initiate framelock ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_START_FRAMELOCK_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error 0x%x setting up data buffers to initiate framelock",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error writing P8 MCI Configuration register to initiate framelock");
-        return rc;
-    }
-
-    // poll until framelock operation is finished, a timeout is deemed to
-    // have occurred, or an error is detected
-    uint8_t polls = 0;
-
-    while (polls < PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
-    {
-        // Read CEN MBI Status Register
-        rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, mbi_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading Centaur MBI status Register");
-            return rc;
-        }
-
-        // Read CEN MBI FIR Register
-        rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading Centaur MBI FIR Register");
-            return rc;
-        }
-
-        // Read P8 MCI Status Register
-        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading P8 MCI Status Register");
-            return rc;
-        }
-
-        // Read P8 MCI FIR Register
-        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Error reading P8 MCI FIR Register");
-            return rc;
-        }
-
-        // Fail if Centaur MBI Frame Lock FAIL
-        if (mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. Centaur MBI STAT");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_CEN_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if Centaur MBI FIR bits are set
-        if (mbi_fir.isBitSet(MBI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_MBICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. Centaur MBI FIR errors set");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_CEN_FIR_ERR);
-            return rc;
-        }
-
-        // Fail if P8 MCI Frame Lock FAIL
-        if (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. P8 MCI STAT");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_P8_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if P8 MCI FIR bits are set
-        if (mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. P8 MCI FIR errors set (MCS)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_P8_FIR_ERR_MCS);
-            return rc;
-        }
-
-        // Fail if P8 MCI FIR bits are set
-        if (mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_framelock: Framelock fail. P8 MCI FIR errors set (MEMBUF)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_P8_FIR_ERR_MEMBUF);
-            return rc;
-        }
-
-        // Success if P8 and Centaur PASS bits set
-        if ((mbi_stat.isBitSet(MBI_STAT_FRAMELOCK_PASS_BIT)) &&
-            (mci_stat.isBitSet(MCI_STAT_FRAMELOCK_PASS_BIT)))
-        {
-            FAPI_INF("proc_cen_framelock_run_errstate_framelock: Framelock completed successfully!");
-            break;
-        }
-        else
-        {
-            polls++;
-            FAPI_INF("proc_cen_framelock_run_errstate_framelock: Framelock not done, loop %d of %d...",
-                     polls, PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS);
-
-
-            // 1ms/100simcycles delay
-            fapiDelay(1000000, 100); //fapiDelay(nanoseconds, simcycles)
-
-        }
-    }
-
-    if (polls >= PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_framelock:!!!! NO FRAME LOCK STATUS DETECTED !!!!");
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_ERRSTATE_FL_TIMEOUT_ERR);
-        return rc;
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to initiate P8/Centaur FRTL (frame round trip
-//           latency) determination and check for completion
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur chip target
-// returns: FAPI_RC_SUCCESS if FRTL sequence completes successfully,
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_CEN_FIR_ERR
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_P8_FIR_ERR_MCS
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_P8_FIR_ERR_MEMBUF
-//              if MCI/MBI FIR is set during FRTL operation,
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_CEN_FAIL_ERR
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_P8_FAIL_ERR
-//              if MCI/MBI indicates FRTL operation failure,
-//          RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_TIMEOUT_ERR
-//              if MCI/MBI does not post pass/fail indication after FRTL
-//              operation is started,
-//          else FAPI getscom/putscom return code for failing SCOM operation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_errstate_frtl(
-    const fapi::Target& i_pu_target,
-    const fapi::Target& i_mem_target)
-{
-    // data buffers for putscom/getscom calls
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase mask(64);
-    ecmdDataBufferBase mbi_stat(64);
-    ecmdDataBufferBase mbi_fir(64);
-    ecmdDataBufferBase mci_stat(64);
-    ecmdDataBufferBase mci_fir(64);
-
-    // Reference variables matching error XML
-    const ecmdDataBufferBase & MCI_STAT = mci_stat;
-    const ecmdDataBufferBase & MCI_FIR = mci_fir;
-    const ecmdDataBufferBase & MBI_STAT = mbi_stat;
-    const ecmdDataBufferBase & MBI_FIR = mbi_fir;
-    const fapi::Target & MCS_CHIPLET = i_pu_target;
-    const fapi::Target & MEMBUF_CHIP = i_mem_target;
-
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Starting FRTL Error State sequence ...");
-
-
-
-
-    // if error state is set, force FRTL bit in Centaur MBI
-    //FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Writing Centaur MBI Configuration register to force FRTL ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MBI_CFG_FORCE_FRTL_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error 0x%x setting up data buffers to force FRTL",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error writing Centaur MBI Configuration Register to force FRTL");
-        return rc;
-    }
-
-
-    // start FRTL
-    //FAPI_DBG("proc_cen_framelock_run_errstate_frtl: Writing P8 MCI Configuration Register to initiate FRTL ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_START_FRTL_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error 0x%x setting up data buffers to initiate FRTL",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error writing P8 MCI Configuration register to initiate FRTL");
-        rc.setEcmdError(rc);
-        return rc;
-    }
-
-    // Poll until FRTL operation is finished, a timeout is deemed to
-    // have occurred, or an error is detected
-    uint8_t polls = 0;
-
-    while (polls < PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
-    {
-        // Read Centaur MBI Status Register
-        rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, mbi_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading Centaur MBI Status Register");
-            return rc;
-        }
-
-        // Read Centaur MBI FIR Register
-        rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading Centaur MBI FIR Register");
-            return rc;
-        }
-
-        // Read P8 MCI Status Register
-        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading P8 MCI Status Register");
-            return rc;
-        }
-
-        // Read P8 MCI FIR Register
-        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: Error reading P8 MCI FIR Register");
-            return rc;
-        }
-
-        // Fail if Centaur MBI FRTL FAIL or Channel Interlock Fail
-        if (mbi_stat.isBitSet(MBI_STAT_FRTL_FAIL_BIT)  ||
-            mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. Centaur MBI STAT");
-            FAPI_SET_HWP_ERROR(rc,
-                              RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_CEN_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if Centaur MBI FIR bits are set
-        if (mbi_fir.isBitSet(MBI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_FRTL_COUNTER_OVERFLOW_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_MBICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. Centaur MBI FIR errors set");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_CEN_FIR_ERR);
-            return rc;
-        }
-
-        // Fail if P8 MCI FRTL FAIL or Channel Interlock Fail
-        if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)  ||
-            mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. P8 MCI STAT");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_P8_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if MCI FIR bits are set
-        if (mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. P8 MCI FIR errors set (MCS)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_P8_FIR_ERR_MCS);
-            return rc;
-        }
-
-        if (mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_FRTL_COUNTER_OVERFLOW_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_errstate_frtl: FRTL fail. P8 MCI FIR errors set (MEMBUF)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_P8_FIR_ERR_MEMBUF);
-            return rc;
-        }
-
-        // Success if Centaur and P8 PASS bits set
-        if ((mbi_stat.isBitSet(MBI_STAT_FRTL_PASS_BIT)) &&
-            (mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
-            (mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
-            (mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)))
-        {
-            FAPI_INF("proc_cen_framelock_run_errstate_frtl: FRTL (auto) completed successfully!");
-            break;
-        }
-        else
-        {
-            polls++;
-            FAPI_INF("proc_cen_framelock_run_errstate_frtl: FRTL not done, loop %d of %d ...\n",
-                     polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
-
-            // 1ms/100simcycles delay
-            fapiDelay(1000000, 100); //fapiDelay(nanoseconds, simcycles)
-
-        }
-    }
-
-    if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
-    {
-        // Loop count has expired, timeout
-        FAPI_ERR("proc_cen_framelock_run_errstate_frtl:!!!! NO FRAME LOCK STATUS DETECTED !!!!");
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_ERRSTATE_FRTL_TIMEOUT_ERR);
-        return rc;
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to initiate P8/Centaur FRTL (frame round trip
-//           latency) determination and check for completion
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur chip target
-//             i_args       => proc_cen_framelock HWP argumemt structure
-// returns: FAPI_RC_SUCCESS if FRTL sequence completes successfully,
-//          RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_CEN_FIR_ERR
-//          RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_P8_FIR_ERR_MCS
-//          RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_P8_FIR_ERR_MEMBUF
-//              if MCI/MBI FIR is set during FRTL operation,
-//          RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_CEN_FAIL_ERR
-//          RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_P8_FAIL_ERR
-//              if MCI/MBI indicates FRTL operation failure,
-//          RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_TIMEOUT_ERR
-//              if MCI/MBI does not post pass/fail indication after FRTL
-//              operation is started,
-//          else FAPI getscom/putscom return code for failing SCOM operation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_run_manual_frtl(
-    const fapi::Target& i_pu_target,
-    const fapi::Target& i_mem_target,
-    const proc_cen_framelock_args& i_args)
-{
-    // data buffers for putscom/getscom calls
-    ecmdDataBufferBase data(64);
-    ecmdDataBufferBase mask(64);
-    ecmdDataBufferBase mbi_stat(64);
-    ecmdDataBufferBase mbi_fir(64);
-    ecmdDataBufferBase mci_stat(64);
-    ecmdDataBufferBase mci_fir(64);
-
-    // Reference variables matching error XML
-    const ecmdDataBufferBase & MCI_STAT = mci_stat;
-    const ecmdDataBufferBase & MCI_FIR = mci_fir;
-    const ecmdDataBufferBase & MBI_STAT = mbi_stat;
-    const ecmdDataBufferBase & MBI_FIR = mbi_fir;
-    const fapi::Target & MCS_CHIPLET = i_pu_target;
-    const fapi::Target & MEMBUF_CHIP = i_mem_target;
-
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_DBG("proc_cen_framelock_run_manual_frtl: Starting FRTL manual sequence ...");
-
-
-
-
-    // Manual mode
-
-    // Disable auto FRTL mode & channel init timeout in Centaur MBI
-    // Configuration Register
-    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing Centaur MBI Configuration register to disable auto FRTL mode & channel init timeout ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MBI_CFG_AUTO_FRTL_DISABLE_BIT);
-    rc_ecmd |= data.copy(mask);
-    rc_ecmd |= data.insertFromRight(
-        (uint32_t) (CHANNEL_INIT_TIMEOUT_NO_TIMEOUT &
-                    MBI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-        MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    rc_ecmd |= mask.setBit(
-        MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to disable Centaur auto FRTL mode",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to disable auto FRTL mode");
-        return rc;
-    }
-
-    // write specified FRTL value into Centaur MBI Configuration
-    // Register
-    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing Centaur MBI Configuration register to set manual FRTL value ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= mask.flushTo0();
-    rc_ecmd |= data.insertFromRight(
-        (uint32_t) (i_args.frtl_manual_mem &
-                    MBI_CFG_MANUAL_FRTL_FIELD_MASK),
-        MBI_CFG_MANUAL_FRTL_START_BIT,
-        (MBI_CFG_MANUAL_FRTL_END_BIT -
-         MBI_CFG_MANUAL_FRTL_START_BIT + 1));
-    rc_ecmd |= mask.setBit(
-        MBI_CFG_MANUAL_FRTL_START_BIT,
-        (MBI_CFG_MANUAL_FRTL_END_BIT -
-         MBI_CFG_MANUAL_FRTL_START_BIT + 1));
-
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL value",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to set manual FRTL value");
-        return rc;
-    }
-
-
-    // disable auto FRTL mode & channel init timeout in P8 MCI
-    // Configuration Register
-    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing P8 MCI Configuration register to disable auto FRTL mode & channel init timeout ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_AUTO_FRTL_DISABLE_BIT);
-    rc_ecmd |= data.copy(mask);
-    rc_ecmd |= data.insertFromRight(
-        (uint32_t)(CHANNEL_INIT_TIMEOUT_NO_TIMEOUT &
-                   MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK),
-        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    rc_ecmd |= mask.setBit(
-        MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT,
-        (MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT -
-         MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT + 1));
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to disable P8 auto FRTL mode",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to disable auto FRTL mode");
-        return rc;
-    }
-
-    // write specified FRTL value into P8 MCI Configuration Register
-    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing P8 MCI Configuration register to set manual FRTL value ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= mask.flushTo0();
-    rc_ecmd |= data.insertFromRight(
-        (uint32_t)(i_args.frtl_manual_pu &
-                   MCI_CFG_MANUAL_FRTL_FIELD_MASK),
-        MCI_CFG_MANUAL_FRTL_START_BIT,
-        (MCI_CFG_MANUAL_FRTL_END_BIT -
-         MCI_CFG_MANUAL_FRTL_START_BIT + 1));
-    rc_ecmd |= mask.setBit(
-        MCI_CFG_MANUAL_FRTL_START_BIT,
-        (MCI_CFG_MANUAL_FRTL_END_BIT -
-         MCI_CFG_MANUAL_FRTL_START_BIT + 1));
-
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set P8 manual FRTL value",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to set manual FRTL value");
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-
-    // write FRTL manual done bit into Centaur MBI Configuration
-    // Register
-    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing Centaur MBI Configuration register to set manual FRTL done bit ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MBI_CFG_MANUAL_FRTL_DONE_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR( "proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to set Centaur manual FRTL done",
-                  rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing Centaur MBI Configuration register to set manual FRTL done");
-        return rc;
-    }
-
-    // write FRTL manual done bit into P8 MCI Configuration Register
-    //FAPI_DBG("proc_cen_framelock_run_manual_frtl: Writing P8 MCI Configuration register to set manual FRTL done bit ...");
-    rc_ecmd |= data.flushTo0();
-    rc_ecmd |= data.setBit(MCI_CFG_MANUAL_FRTL_DONE_BIT);
-    rc_ecmd |= data.copy(mask);
-    if (rc_ecmd)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error 0x%x setting up data buffers to write P8 manual FRTL done",
-                 rc_ecmd);
-        rc.setEcmdError(rc_ecmd);
-        return rc;
-    }
-
-    rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, data, mask);
-    if (rc)
-    {
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error writing P8 MCI Configuration register to set manual FRTL done");
-        return rc;
-    }
-
-
-
-
-    // Poll until FRTL operation is finished, a timeout is deemed to
-    // have occurred, or an error is detected
-    uint8_t polls = 0;
-
-    while (polls < PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
-    {
-        // Read Centaur MBI Status Register
-        rc = proc_cen_framelock_get_cen_mbi_stat_reg(i_mem_target, mbi_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading Centaur MBI Status Register");
-            return rc;
-        }
-
-        // Read Centaur MBI FIR Register
-        rc = proc_cen_framelock_get_cen_mbi_fir_reg(i_mem_target, mbi_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading Centaur MBI FIR Register");
-            return rc;
-        }
-
-        // Read P8 MCI Status Register
-        rc = proc_cen_framelock_get_pu_mci_stat_reg(i_pu_target, mci_stat);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading P8 MCI Status Register");
-            return rc;
-        }
-
-        // Read P8 MCI FIR Register
-        rc = proc_cen_framelock_get_pu_mci_fir_reg(i_pu_target, mci_fir);
-        if (rc)
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: Error reading P8 MCI FIR Register");
-            return rc;
-        }
-
-        // Fail if Centaur MBI FRTL FAIL or Channel Interlock Fail
-        if (mbi_stat.isBitSet(MBI_STAT_FRTL_FAIL_BIT)  ||
-            mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. Centaur MBI STAT");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_CEN_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if Centaur MBI FIR bits are set
-        if (mbi_fir.isBitSet(MBI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_FRTL_COUNTER_OVERFLOW_BIT) ||
-            mbi_fir.isBitSet(MBI_FIR_MBICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. Centaur MBI FIR errors set");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_CEN_FIR_ERR);
-            return rc;
-        }
-
-        // Fail if P8 MCI FRTL FAIL or Channel Interlock Fail
-        if (mci_stat.isBitSet(MCI_STAT_FRTL_FAIL_BIT)  ||
-            mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. P8 MCI STAT");
-            FAPI_SET_HWP_ERROR(rc,
-                               RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_P8_FAIL_ERR);
-            return rc;
-        }
-
-        // Fail if MCI FIR bits are set
-        if (mci_fir.isBitSet(MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_MCICFGQ_PARITY_ERROR_BIT))
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. P8 MCI FIR errors set (MCS)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_P8_FIR_ERR_MCS);
-            return rc;
-        }
-
-        if (mci_fir.isBitSet(MCI_FIR_DMI_CHANNEL_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_FRTL_COUNTER_OVERFLOW_BIT) ||
-            mci_fir.isBitSet(MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT)                )
-        {
-            FAPI_ERR("proc_cen_framelock_run_manual_frtl: FRTL fail. P8 MCI FIR errors set (MEMBUF)");
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_P8_FIR_ERR_MEMBUF);
-            return rc;
-        }
-
-        // Success if Centaur and P8 PASS bits set
-        if ((mbi_stat.isBitSet(MBI_STAT_FRTL_PASS_BIT)) &&
-            (mbi_stat.isBitSet(MBI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
-            (mci_stat.isBitSet(MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT)) &&
-            (mci_stat.isBitSet(MCI_STAT_FRTL_PASS_BIT)))
-        {
-            FAPI_INF("proc_cen_framelock_run_manual_frtl: FRTL (manual) completed successfully!");
-            break;
-        }
-        else
-        {
-            polls++;
-            FAPI_INF("proc_cen_framelock_run_manual_frtl: FRTL not done, loop %d of %d...\n",
-                     polls, PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS);
-
-            // 1ms/100simcycles delay
-            fapiDelay(1000000, 100); //fapiDelay(nanoseconds, simcycles)
-
-        }
-    }
-
-    if (polls >= PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS)
-    {
-        // Loop count has expired, timeout
-        FAPI_ERR("proc_cen_framelock_run_manual_frtl:!!!! NO FRAME LOCK STATUS DETECTED !!!!");
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_CEN_FRAMELOCK_MANUAL_FRTL_TIMEOUT_ERR);
-        return rc;
-    }
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// The Main Hardware Procedure
-// ##################################################
-// The frame lock procedure initializes the Centaur DMI memory channel.  In the
-// event of errors, it will attempt to rerun the procedure.  There will be up to 3 attempts
-// at initialization before giving up.  This procedure assumes the DMI/EDI channel training
-// states completed successfully and that the DMI fence was lowered.
-//
-// When the procedure is first run, NO SCOM will be performed on Centaur.  All the scom accesses
-// are limited to Murano/Venice.  This allows for very fast initialization of the channels.  However,
-// if the initialization does encounter a fail event, the procedure will make a second (if necessary,
-// a third attempt) at intializing the channel.  The second and third attempts require scoms to both
-// P8 and Centaur chips.
-//
-//
-
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
-                                    const fapi::Target& i_mem_target,
-                                    const proc_cen_framelock_args& i_args)
-{
-    fapi::ReturnCode l_rc;
-
-    l_rc = proc_cen_framelock_cloned(i_pu_target, i_mem_target, i_args);
-
-	// If mss_unmask_inband_errors gets it's own bad rc,
-	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
-	// Else if mss_unmask_inband_errors runs clean,
-	// it will just return the passed in rc.
-	l_rc = mss_unmask_inband_errors(i_mem_target, l_rc);
-
-	return l_rc;
-}
-
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_cen_framelock_cloned(const fapi::Target& i_pu_target,
-                                    const fapi::Target& i_mem_target,
-                                    const proc_cen_framelock_args& i_args)
-{
-
- // data buffers for putscom/getscom calls
-    ecmdDataBufferBase mci_data(64);
-    ecmdDataBufferBase mbi_data(64);
-    ecmdDataBufferBase mci_mask(64);
-    ecmdDataBufferBase mbi_mask(64);
-
-    fapi::ReturnCode l_rc;
-    uint32_t l_ecmdRc = 0;
-    uint8_t  l_murdd1_new_mcs_fir = 0;
-    uint8_t  l_vendd1_new_mcs_fir = 0;
-    uint8_t  l_procdd2_new_mcs_fir = 0;
-
-    // mark HWP entry
-    FAPI_IMP("proc_cen_framelock: Entering ...");
-
-    // validate arguments
-    if (i_args.frtl_manual_mem > MBI_CFG_MANUAL_FRTL_FIELD_MASK)
-    {
-        FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL mem argument value!",
-                 i_args.frtl_manual_mem);
-        const proc_cen_framelock_args & ARGS = i_args;
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-        return l_rc;
-    }
-
-    if (i_args.frtl_manual_pu > MCI_CFG_MANUAL_FRTL_FIELD_MASK)
-    {
-        FAPI_ERR("proc_cen_framelock: Out of range value %d presented for manual FRTL pu argument value!",
-                 i_args.frtl_manual_pu);
-        const proc_cen_framelock_args & ARGS = i_args;
-        FAPI_SET_HWP_ERROR(l_rc, RC_PROC_CEN_FRAMELOCK_INVALID_ARGS);
-        return l_rc;
-    }
-
-
-
-    // Get attribute to determine If Murano DD1 processor
-    l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL, &i_pu_target, l_murdd1_new_mcs_fir);
-    if(l_rc)
-    {
-        FAPI_ERR("Error getting ATTR_CHIP_EC_FEATURE_MCS_MURDD1_FIR_CONTROL");
-        return l_rc;
-    }
-
-
-    // Get attribute to determine If Venice DD1 processor
-    l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_MCS_VENDD1_FIR_CONTROL, &i_pu_target, l_vendd1_new_mcs_fir);
-    if(l_rc)
-    {
-        FAPI_ERR("Error getting ATTR_CHIP_EC_FEATURE_MCS_VENDD1_FIR_CONTROL");
-        return l_rc;
-    }
-
-
-
-    // Get attribute to determine If Murano or Venice DD2 processor
-    l_rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_MCS_P8_DD2_FIR_CONTROL, &i_pu_target, l_procdd2_new_mcs_fir);
-    if(l_rc)
-    {
-        FAPI_ERR("Error getting ATTR_CHIP_EC_FEATURE_MCS_P8_DD2_FIR_CONTROL");
-        return l_rc;
-    }
-
-
-
-    // Execute Framelock
-    l_rc = proc_cen_framelock_run_framelock(i_pu_target, i_mem_target, i_args);
-
-    if (!l_rc)
-    {
-        // Execute FRTL
-        if (i_args.frtl_auto_not_manual)
-        {
-            l_rc = proc_cen_framelock_run_frtl(i_pu_target, i_mem_target);
-        }
-        else
-        {
-            l_rc = proc_cen_framelock_run_manual_frtl(i_pu_target, i_mem_target,
-                                                      i_args);
-        }
-    }
-
-    if (l_rc)
-    {
-        // The regular framelock/frtl failed, retry up to twice using the
-        // errorstate functions
-        const uint8_t NUM_FRAMELOCK_ERR_RETRIES = 2;
-        for (uint8_t i=0; i<NUM_FRAMELOCK_ERR_RETRIES; i++)
-        {
-            // Force MBI in Channel Fail State
-            l_ecmdRc |= mbi_data.flushTo0();
-            l_ecmdRc |= mbi_data.setBit(MBI_CFG_FORCE_CHANNEL_FAIL_BIT);
-            l_ecmdRc |= mbi_data.copy(mbi_mask);
-            if (l_ecmdRc)
-            {
-                FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to force MBI in channel fail state",
-                         l_ecmdRc);
-                l_rc.setEcmdError(l_ecmdRc);
-                return l_rc;
-            }
-
-            l_rc = proc_cen_framelock_set_cen_mbi_cfg_reg(i_mem_target, mbi_data,  mbi_mask);
-            if (l_rc)
-            {
-                FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Configuration Register to force framelock");
-                return l_rc;
-            }
-
-            //Force MCI in Channel Fail State
-            l_ecmdRc |= mci_data.flushTo0();
-            l_ecmdRc |= mci_data.setBit(MCI_CFG_FORCE_CHANNEL_FAIL_BIT);
-            l_ecmdRc |= mci_data.copy(mci_mask);
-            if (l_ecmdRc)
-            {
-                FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to force MCI in channel fail state",
-                         l_ecmdRc);
-                l_rc.setEcmdError(l_ecmdRc);
-                return l_rc;
-            }
-
-            l_rc = proc_cen_framelock_set_pu_mci_cfg_reg(i_pu_target, mci_data, mci_mask);
-            if (l_rc)
-            {
-                 FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Configuration register to force MCI in channel fail state");
-                 return l_rc;
-            }
-
-            // 1ms/100simcycles delay
-            fapiDelay(1000000, 100); //fapiDelay(nanoseconds, simcycles)
-
-            // Execute errorstate Framelock
-            l_rc = proc_cen_framelock_run_errstate_framelock(i_pu_target,
-                                                             i_mem_target,
-                                                             i_args);
-
-            // In error state attempt FRTL although FL might have failed
-            fapi::ReturnCode l_rc2;
-            if (i_args.frtl_auto_not_manual)
-            {
-                l_rc2 = proc_cen_framelock_run_errstate_frtl(i_pu_target,
-                                                             i_mem_target);
-            }
-            else
-            {
-                l_rc2 = proc_cen_framelock_run_manual_frtl(i_pu_target,
-                                                           i_mem_target,
-                                                           i_args);
-            }
-
-            if (!l_rc)
-            {
-                // Framelock successful, use FRTL result
-                l_rc = l_rc2;
-            }
-
-            if (!l_rc)
-            {
-                // Success, break out of retry loop
-                break;
-            }
-        }
-    }
-
-    if (l_rc)
-    {
-        return l_rc;
-    }
-
-    // Clear FIR register before exiting procedure
-    // Clear P8 MCI FIR registers
-    l_rc = proc_cen_framelock_clear_pu_mci_fir_reg(i_pu_target);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error clearing P8 MCI FIR regs");
-        return l_rc;
-    }
-
-    // Clear Centaur MBI FIR registers
-    l_rc = proc_cen_framelock_clear_cen_mbi_fir_reg(i_mem_target);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error clearing Centaur MBI FIR regs");
-        return l_rc;
-    }
-
-    // EXIT Procedure
-    // by setting the MCI and MBI fir action and mask registers according to PRD requirements.
-
-    // (Action0, Action1, Mask)
-    // ------------------------
-    // (0,0,0) = Checkstop
-    // (0,1,0) = Recoverable Error
-    // (1,0,x) = Recoverable Interrupt
-    // (1,1,0) = Machine Check
-    // (x,x,1) = MASKED
-    // (1,0,0) = Use this setting for non-implemented bits
-
-    // Set P8 MCI FIR ACT0
-    //     Set action regs to recoverable interrupt (action0=1, action1=0) for MCIFIR's 12,15,16 and 17
-    //     On 4/25/2013, PRD asked to change bit 12 action from recov intr to recover error
-    //     On 12/10/2013, PRD asked to change bit 12 action back from recov error to recover interrupt
-    l_ecmdRc |= mci_data.flushTo0();
-    l_ecmdRc |= mci_data.setBit(12);    //Centaur Checkstop
-    l_ecmdRc |= mci_data.setBit(15);    //Centaur Recoverable Attention
-    l_ecmdRc |= mci_data.setBit(16);    //Centaur Special Attention
-    l_ecmdRc |= mci_data.setBit(17);    //Centaur Maintenance Complete
-    l_ecmdRc |= mci_data.copy(mci_mask);
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
-                 l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-    l_rc = proc_cen_framelock_set_pu_mci_firact0_reg(i_pu_target, mci_data, mci_mask);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action0 Register");
-        return l_rc;
-    }
-
-    // Set P8 MCI FIR ACT1
-    //     Set action regs to recoverable error (action0=0, action1=1) for the following MCIFIR's
-    l_ecmdRc |= mci_data.flushTo0();
-    l_ecmdRc |= mci_data.setBit(0);     //Replay Timeout
-    l_ecmdRc |= mci_data.setBit(4);     //Seqid OOO
-    l_ecmdRc |= mci_data.setBit(5);     //Replay Buffer CE
-    l_ecmdRc |= mci_data.setBit(6);     //Replay Buffer UE
-    l_ecmdRc |= mci_data.setBit(8);     //MCI Internal Control Parity Error
-    l_ecmdRc |= mci_data.setBit(9);     //MCI Data Flow Parity Error
-    l_ecmdRc |= mci_data.setBit(10);    //CRC Performance Degradation
-    //l_ecmdRc |= mci_data.setBit(12);    //Centaur Checkstop
-    l_ecmdRc |= mci_data.setBit(20);    //Scom Register parity error
-    l_ecmdRc |= mci_data.setBit(22);    //mcicfgq parity error
-   // l_ecmdRc |= mci_data.setBit(23);    //Replay Buffer Overrun
-    l_ecmdRc |= mci_data.setBit(24);    //MCIFIRQ_MCS_RECOVERABLE_ERROR
-    l_ecmdRc |= mci_data.setBit(27);    //MCS Command List Timeout due to PowerBus
-    //l_ecmdRc |= mci_data.setBit(32);    //MCIFIRQ_MIRROR_ACTION_OCCURRED
-    l_ecmdRc |= mci_data.setBit(35);    //PowerBus Write Data Buffer CE
-    l_ecmdRc |= mci_data.setBit(36);    //PowerBus Write Data Buffer UE
-
-    if (l_procdd2_new_mcs_fir)
-    {
-    l_ecmdRc |= mci_data.setBit(40);     //MCS Channel Timeout Error is recoverable for DD2 processors, since channel timeout will force channel fail
-    }
-    //l_ecmdRc |= mci_data.setBit(40);   //MCS Channel Timeout Error (On 5/06/2013 changed this fir to xstop, have to re-eval for Murano dd2)
-
-
-    l_ecmdRc |= mci_data.copy(mci_mask);
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCI FIR actions",
-                 l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-    l_rc = proc_cen_framelock_set_pu_mci_firact1_reg(i_pu_target, mci_data, mci_mask);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Action1 Register");
-        return l_rc;
-    }
-
-    // Set P8 MCS Mode4 Register
-    //     Enable recoverable interrupt output of MCS_MCIFIR to drive host attention
-    //        MCMODE4Q[12]=0 (disable special attention output)
-    //        MCMODE4Q[13]=1 (enable host attention output)
-
-    l_ecmdRc |= mci_data.flushTo0();
-    l_ecmdRc |= mci_data.setBit(12);    //MCS FIR recov_int output drives MCS spec_attn_output
-    l_ecmdRc |= mci_data.setBit(13);    //MCS FIR recov_int output drives MCS host_attn_output
-    l_ecmdRc |= mci_data.copy(mci_mask);
-    l_ecmdRc |= mci_data.clearBit(12);  //MCS FIR recov_int output drives MCS spec_attn_output
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MCS Mode4 Register",
-                 l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-    l_rc = proc_cen_framelock_set_pu_mcs_mode4_reg(i_pu_target, mci_data, mci_mask);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error writing P8 MCS Mode4 Register");
-        return l_rc;
-    }
-
-    // Set P8 MCI FIR Mask
-    l_ecmdRc |= mci_data.flushTo0();
-    l_ecmdRc |= mci_data.setBit(0);     //Replay Timeout
-    //l_ecmdRc |= mci_data.setBit(4);     //Seqid OOO                        //Mask since it can be trigger by a crc error and will overflow the prd logs
-    l_ecmdRc |= mci_data.setBit(5);     //Replay Buffer CE
-    l_ecmdRc |= mci_data.setBit(6);     //Replay Buffer UE
-    l_ecmdRc |= mci_data.setBit(8);     //MCI Internal Control Parity Error
-    l_ecmdRc |= mci_data.setBit(9);     //MCI Data Flow Parity Error
-    l_ecmdRc |= mci_data.setBit(10);    //CRC Performance Degradation
-    l_ecmdRc |= mci_data.setBit(12);    //Centaur Checkstop
-    l_ecmdRc |= mci_data.setBit(15);    //Centaur Recoverable Attention
-    l_ecmdRc |= mci_data.setBit(16);    //Centaur Special Attention
-    l_ecmdRc |= mci_data.setBit(17);    //Centaur Maintenance Complete
-    l_ecmdRc |= mci_data.setBit(20);    //SCOM Register Parity Error
-    l_ecmdRc |= mci_data.setBit(22);    //MCICFGQ Parity Error
-    l_ecmdRc |= mci_data.setBit(23);    //Replay Buffer Overrun
-    l_ecmdRc |= mci_data.setBit(24);    //Recoverable MC Internal Error
-    l_ecmdRc |= mci_data.setBit(25);    //Non-Recoverable MC Internal Error (xstop)
-    l_ecmdRc |= mci_data.setBit(26);    //PowerBus Protocol Error (xstop)                //1.29 UNDONE Mask for CAPI defect HW281374
-    l_ecmdRc |= mci_data.setBit(27);    //MCS Command List Timeout due to PB
-    l_ecmdRc |= mci_data.setBit(28);    //Multiple RCMD or CRESP active
-    l_ecmdRc |= mci_data.setBit(29);    //Inband Bar Hit with Incorrect TTYPE (xstop)
-    l_ecmdRc |= mci_data.setBit(30);    //Multiple Bar Hit (xstop)
-    //l_ecmdRc |= mci_data.setBit(32);    //MCIFIRQ_MIRROR_ACTION_OCCURRED
-    l_ecmdRc |= mci_data.setBit(33);    //Invalid Foreign Bar Access (xstop)
-    l_ecmdRc |= mci_data.setBit(35);    //PowerBus Write Data Buffer CE
-    l_ecmdRc |= mci_data.setBit(36);    //PowerBus Write Data Buffer UE
-    l_ecmdRc |= mci_data.setBit(38);    //HA Illegal Consumer Access Error (xstop)
-    l_ecmdRc |= mci_data.setBit(39);    //HA Illegal Producer Access Error (xstop)
-    l_ecmdRc |= mci_data.setBit(40);    //MCS Channel Timeout Error
-
-    if (!l_murdd1_new_mcs_fir)
-    {
-    l_ecmdRc |= mci_data.setBit(46);    //Non-bypassable data marked as bypass new fir in VenDD1, VenDD2 and MurDD2
-    }
-
-    if (l_procdd2_new_mcs_fir)
-    {
-    l_ecmdRc |= mci_data.setBit(48);    //Processor asked for Centaur to set MDI bit to 1, but Centaur set it to 0.
-    l_ecmdRc |= mci_data.setBit(49);    //SFTAT bit is not the same across an octoword, for non-error cases
-    }
-
-    l_ecmdRc |= mci_data.copy(mci_mask);
-    l_ecmdRc |= mci_data.clearBit(0);     //Replay Timeout
-    //l_ecmdRc |= mci_data.clearBit(4);     //Seqid OOO                       //Mask since it can be trigger by a crc error and will overflow the prd logs
-    l_ecmdRc |= mci_data.clearBit(5);     //Replay Buffer CE
-    l_ecmdRc |= mci_data.clearBit(6);     //Replay Buffer UE
-    l_ecmdRc |= mci_data.clearBit(8);     //MCI Internal Control Parity Error
-    l_ecmdRc |= mci_data.clearBit(9);     //MCI Data Flow Parity Error
-    l_ecmdRc |= mci_data.clearBit(10);    //CRC Performance Degradation
-    l_ecmdRc |= mci_data.clearBit(12);    //Centaur Checkstop
-    l_ecmdRc |= mci_data.clearBit(15);    //Centaur Recoverable Attention
-    l_ecmdRc |= mci_data.clearBit(16);    //Centaur Special Attention
-    l_ecmdRc |= mci_data.clearBit(17);    //Centaur Maintenance Complete
-    l_ecmdRc |= mci_data.clearBit(20);    //SCOM Register Parity Error
-    l_ecmdRc |= mci_data.clearBit(22);    //MCICFGQ Parity Error
-    l_ecmdRc |= mci_data.clearBit(23);    //Replay Buffer Overrun
-    l_ecmdRc |= mci_data.clearBit(24);    //Recoverable MC Internal Error
-    l_ecmdRc |= mci_data.clearBit(25);    //Non-Recoverable MC Internal Error (xstop)
-    l_ecmdRc |= mci_data.clearBit(26);    //PowerBus Protocol Error (xstop)            //1.29 UNDONE Mask for CAPI defect HW281374
-    l_ecmdRc |= mci_data.clearBit(27);    //MCS Command List Timeout due to PB
-    l_ecmdRc |= mci_data.clearBit(28);    //Multiple RCMD or CRESP active
-    l_ecmdRc |= mci_data.clearBit(29);    //Inband Bar Hit with Incorrect TTYPE (xstop)
-    l_ecmdRc |= mci_data.clearBit(30);    //Multiple Bar Hit (xstop)
-    //l_ecmdRc |= mci_data.clearBit(32);    //MCIFIRQ_MIRROR_ACTION_OCCURRED
-    l_ecmdRc |= mci_data.clearBit(33);    //Invalid Foreign Bar Access (xstop)
-    l_ecmdRc |= mci_data.clearBit(35);    //PowerBus Write Data Buffer CE
-    l_ecmdRc |= mci_data.clearBit(36);    //PowerBus Write Data Buffer UE
-    l_ecmdRc |= mci_data.clearBit(38);    //HA Illegal Consumer Access Error (xstop)
-    l_ecmdRc |= mci_data.clearBit(39);    //HA Illegal Producer Access Error (xstop)
-    l_ecmdRc |= mci_data.clearBit(40);    //MCS Channel Timeout Error
-
-    if (!l_murdd1_new_mcs_fir)
-    {
-    l_ecmdRc |= mci_data.clearBit(46);    //Non-bypassable data marked as bypass new fir in VenDD1, VenDD2 and MurDD2
-    }
-
-    if (l_procdd2_new_mcs_fir)
-    {
-    l_ecmdRc |= mci_data.clearBit(48);    //Processor asked for Centaur to set MDI bit to 1, but Centaur set it to 0.
-    l_ecmdRc |= mci_data.clearBit(49);    //SFTAT bit is not the same across an octoword, for non-error cases
-    }
-
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MCI FIRs",
-                 l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-
-
-    l_rc = proc_cen_framelock_set_pu_mci_firmask_reg(i_pu_target, mci_data, mci_mask);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error writing P8 MCI Fir Mask Register");
-        return l_rc;
-    }
-
-    // No Bits are set in FIR ACT0
-
-    // Set CEN MBI FIR ACT1
-    l_ecmdRc |= mbi_data.flushTo0();
-    l_ecmdRc |= mbi_data.clearBit(4);   //Seqid OOO
-    l_ecmdRc |= mbi_data.setBit(5);     //Replay Buffer CE
-    l_ecmdRc |= mbi_data.setBit(10);    //CRC Performance Degradation
-    l_ecmdRc |= mbi_data.setBit(16);    //Scom Register parity error
-    l_ecmdRc |= mbi_data.setBit(25);    //MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE: Internal SCOM Error Clone
-    l_ecmdRc |= mbi_data.setBit(26);    //MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY: Internal SCOM Error Clone copy
-    l_ecmdRc |= mbi_data.copy(mbi_mask);
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to set MBI FIR actions",
-                 l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-    l_rc = proc_cen_framelock_set_cen_mbi_firact1_reg(i_mem_target, mbi_data, mbi_mask);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Action1 Register");
-        return l_rc;
-    }
-
-    // Set Centaur MBI FIR Mask
-    l_ecmdRc |= mbi_data.flushTo0();
-    l_ecmdRc |= mbi_data.setBit(0);     //Replay Timeout
-    //l_ecmdRc |= mbi_data.setBit(4);     //Seqid ooo                       //Mask since it can be trigger by a crc error and will overflow the prd logs
-    l_ecmdRc |= mbi_data.setBit(5);     //Replay Buffer CE
-    l_ecmdRc |= mbi_data.setBit(6);     //Replay Buffer UE
-    l_ecmdRc |= mbi_data.setBit(8);     //MBI Internal Control Parity Error
-    l_ecmdRc |= mbi_data.setBit(9);     //MBI Data Flow Parity Error
-    l_ecmdRc |= mbi_data.setBit(10);    //CRC Performance Degradation
-    l_ecmdRc |= mbi_data.setBit(16);    //SCOM Register parity
-    l_ecmdRc |= mbi_data.setBit(19);    //MBICFGQ Parity Error
-    l_ecmdRc |= mbi_data.setBit(20);    //Replay Buffer Overrun Error
-    l_ecmdRc |= mbi_data.setBit(25);    //MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE: Internal SCOM Error Clone
-    l_ecmdRc |= mbi_data.setBit(26);    //MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY: Internal SCOM Error Clone copy
-    l_ecmdRc |= mbi_data.copy(mbi_mask);
-    l_ecmdRc |= mbi_data.clearBit(0);     //Replay Timeout
-    //l_ecmdRc |= mbi_data.clearBit(4);     //Seqid ooo                       //Mask since it can be trigger by a crc error and will overflow the prd logs
-    l_ecmdRc |= mbi_data.clearBit(5);     //Replay Buffer CE
-    l_ecmdRc |= mbi_data.clearBit(6);     //Replay Buffer UE
-    l_ecmdRc |= mbi_data.clearBit(8);     //MBI Internal Control Parity Error
-    l_ecmdRc |= mbi_data.clearBit(9);     //MBI Data Flow Parity Error
-    l_ecmdRc |= mbi_data.clearBit(10);    //CRC Performance Degradation
-    l_ecmdRc |= mbi_data.clearBit(16);    //SCOM Register parity
-    l_ecmdRc |= mbi_data.clearBit(19);    //MBICFGQ Parity Error
-    l_ecmdRc |= mbi_data.clearBit(20);    //Replay Buffer Overrun Error
-    l_ecmdRc |= mbi_data.clearBit(25);    //MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE: Internal SCOM Error Clone
-    l_ecmdRc |= mbi_data.clearBit(26);    //MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY: Internal SCOM Error Clone copy
-    if (l_ecmdRc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error 0x%x setting up data buffers to mask MBI FIRs",
-                 l_ecmdRc);
-        l_rc.setEcmdError(l_ecmdRc);
-        return l_rc;
-    }
-
-    l_rc = proc_cen_framelock_set_cen_mbi_firmask_reg(i_mem_target, mbi_data, mbi_mask);
-    if (l_rc)
-    {
-        FAPI_ERR("proc_cen_framelock: Error writing Centaur MBI Fir Mask Register");
-        return l_rc;
-    }
-
-    // mark HWP exit
-    FAPI_IMP("proc_cen_framelock: Exiting ...");
-    return l_rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
deleted file mode 100644
index b2b849de0..000000000
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
+++ /dev/null
@@ -1,189 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_cen_framelock.H,v 1.8 2013/10/30 03:48:12 baysah Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_cen_framelock.H
-// *! DESCRIPTION : Run framelock and FRTL (FAPI)
-// *!
-// *! OWNER NAME  : Irving Baysah           Email: baysah@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-// *! Runs EDI frame lock procedure and FRTL (frame round trip latency)
-// *! calculation.  Once frame lock is achieved, CRC checking is enabled,
-// *! idle frames will be transmitted in both directions, and host can issue
-// *! inband configuration accesses.
-// *!
-// *! Prerequisites: DMI training is complete & EDI fence bit has been lowered.
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_CEN_FRAMELOCK_H_
-#define _PROC_CEN_FRAMELOCK_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <fapiUtil.H>
-#include <p8_scom_addresses.H>
-#include <cen_scom_addresses.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// enum to represent supported channel init timeout values
-enum proc_cen_framelock_channel_init_timeout
-{
-    CHANNEL_INIT_TIMEOUT_NO_TIMEOUT = 0,
-    CHANNEL_INIT_TIMEOUT_3US = 1,
-    CHANNEL_INIT_TIMEOUT_7US = 2,
-    CHANNEL_INIT_TIMEOUT_14US = 3
-};
-
-// structure to represent HWP arguments
-struct proc_cen_framelock_args
-{
-    proc_cen_framelock_channel_init_timeout channel_init_timeout;
-                         // channel init timeout value to program for framelock/
-                         // auto/FRTL
-    bool frtl_auto_not_manual; // set FRTL mode (true = auto-calculation via HW,
-                               // false = manually-programmed via SW)
-    uint8_t frtl_manual_pu; // in manual FRTL mode, P8 MCI FRTL value to be
-                            // programmed
-    uint8_t frtl_manual_mem; // in manual FRTL mode, Centaur MBI FRTL value to
-                             // be programmed
-};
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_cen_framelock_FP_t)(const fapi::Target&,
-                           const fapi::Target&,
-                           const proc_cen_framelock_args&);
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// framelock/FRTL polling constants
-const uint8_t PROC_CEN_FRAMELOCK_MAX_FRAMELOCK_POLLS = 5;
-const uint8_t PROC_CEN_FRAMELOCK_MAX_FRTL_POLLS = 5;
-
-// P8 MCI Configuration Register field/bit definitions
-const uint32_t MCI_CFG_FORCE_CHANNEL_FAIL_BIT = 0;
-const uint32_t MCI_CFG_START_FRAMELOCK_BIT = 7;
-const uint32_t MCI_CFG_START_FRTL_BIT = 8;
-const uint32_t MCI_CFG_AUTO_FRTL_DISABLE_BIT = 9;
-const uint32_t MCI_CFG_MANUAL_FRTL_START_BIT = 10;
-const uint32_t MCI_CFG_MANUAL_FRTL_END_BIT = 16;
-const uint32_t MCI_CFG_MANUAL_FRTL_DONE_BIT = 17;
-const uint32_t MCI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT = 35;
-const uint32_t MCI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT   = 36;
-
-const uint8_t MCI_CFG_MANUAL_FRTL_FIELD_MASK = 0x7F;
-const uint32_t MCI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK = 0x3;
-
-// P8 MCI Status Register field/bit definitions
-const uint32_t MCI_STAT_FRAMELOCK_PASS_BIT = 0;
-const uint32_t MCI_STAT_FRAMELOCK_FAIL_BIT = 1;
-const uint32_t MCI_STAT_FRTL_PASS_BIT = 2;
-const uint32_t MCI_STAT_FRTL_FAIL_BIT = 3;
-const uint32_t MCI_STAT_CHANNEL_INTERLOCK_PASS_BIT = 12;
-const uint32_t MCI_STAT_CHANNEL_INTERLOCK_FAIL_BIT = 13;
-
-// P8 MCI FIR Register field/bit definitions
-const uint32_t MCI_FIR_DMI_CHANNEL_FAIL_BIT = 1;
-const uint32_t MCI_FIR_CHANNEL_INIT_TIMEOUT_BIT = 7;
-const uint32_t MCI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT = 8;
-const uint32_t MCI_FIR_DATA_FLOW_PARITY_ERROR_BIT = 9;
-const uint32_t MCI_FIR_CHANNEL_INTERLOCK_FAIL_BIT = 11;
-const uint32_t MCI_FIR_CENTAUR_CHECKSTOP_FAIL_BIT = 12;
-const uint32_t MCI_FIR_FRTL_COUNTER_OVERFLOW_BIT = 19;
-const uint32_t MCI_FIR_MCICFGQ_PARITY_ERROR_BIT = 22;
-const uint32_t MCI_FIR_CHANNEL_FAIL_ACTIVE_BIT = 31;
-
-// Centaur MBI Configuration Register field/bit defintions
-const uint32_t MBI_CFG_FORCE_CHANNEL_FAIL_BIT = 0;
-const uint32_t MBI_CFG_FORCE_FRAMELOCK_BIT = 7;
-const uint32_t MBI_CFG_FORCE_FRTL_BIT = 8;
-const uint32_t MBI_CFG_AUTO_FRTL_DISABLE_BIT = 9;
-const uint32_t MBI_CFG_MANUAL_FRTL_START_BIT = 10;
-const uint32_t MBI_CFG_MANUAL_FRTL_END_BIT = 16;
-const uint32_t MBI_CFG_MANUAL_FRTL_DONE_BIT = 17;
-const uint32_t MBI_CFG_CHANNEL_INIT_TIMEOUT_START_BIT = 35;
-const uint32_t MBI_CFG_CHANNEL_INIT_TIMEOUT_END_BIT = 36;
-
-const uint8_t MBI_CFG_MANUAL_FRTL_FIELD_MASK = 0x7F;
-const uint32_t MBI_CFG_CHANNEL_INIT_TIMEOUT_FIELD_MASK = 0x3;
-
-// Centaur MBI Status Register field/bit definitions
-const uint32_t MBI_STAT_FRAMELOCK_PASS_BIT = 0;
-const uint32_t MBI_STAT_FRAMELOCK_FAIL_BIT = 1;
-const uint32_t MBI_STAT_FRTL_PASS_BIT = 2;
-const uint32_t MBI_STAT_FRTL_FAIL_BIT = 3;
-const uint32_t MBI_STAT_CHANNEL_INTERLOCK_PASS_BIT = 13;
-const uint32_t MBI_STAT_CHANNEL_INTERLOCK_FAIL_BIT = 14;
-
-// Centaur MBI FIR Register field/bit definitions
-const uint32_t MBI_FIR_DMI_CHANNEL_FAIL_BIT = 1;
-const uint32_t MBI_FIR_CHANNEL_INIT_TIMEOUT_BIT = 7;
-const uint32_t MBI_FIR_INTERNAL_CONTROL_PARITY_ERROR_BIT = 8;
-const uint32_t MBI_FIR_DATA_FLOW_PARITY_ERROR_BIT = 9;
-const uint32_t MBI_FIR_GLOBAL_HOST_CHECKSTOP_BIT = 11;
-const uint32_t MBI_FIR_CHANNEL_INTERLOCK_FAIL_BIT = 13;
-const uint32_t MBI_FIR_LOCAL_HOST_CHECKSTOP_BIT = 14;
-const uint32_t MBI_FIR_FRTL_COUNTER_OVERFLOW_BIT = 15;
-const uint32_t MBI_FIR_MBICFGQ_PARITY_ERROR_BIT = 19;
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// function: FAPI proc_cen_framelock HWP entry point, execute P8/Centaur
-//           framelock and FRTL operations
-// parameters: i_pu_target  => P8 MCS chip unit target
-//             i_mem_target => Centaur chip target
-//             i_args       => proc_cen_framelock HWP argumemt structure
-// returns: FAPI_RC_SUCCESS if framelock/FRTL sequence completes successfully,
-//          or error from proc_cen_framelock_errors.xml
-//          else FAPI getscom/putscom return code for failing operation
-fapi::ReturnCode proc_cen_framelock(const fapi::Target& i_pu_target,
-                                    const fapi::Target& i_mem_target,
-                                    const proc_cen_framelock_args& i_args);
-
-} // extern "C"
-
-#endif // _PROC_CEN_FRAMELOCK_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C
deleted file mode 100644
index 5afa101c4..000000000
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C
+++ /dev/null
@@ -1,179 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_cen_set_inband_addr.C,v 1.8 2014/02/05 17:34:30 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_set_inband_addr.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_cen_set_inband_addr.C
-// *! DESCRIPTION : Set the inband base address in the MCS MDFGPR register
-// *!
-// *! OWNER NAME  : Mark Fredrickson     Email: mfred@us.ibm.com
-// *!
-// *! The purpose of this procedure is to set the inband base address in the MCS MDFGPR register
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_cen_set_inband_addr.H>
-
-
-using namespace fapi;
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-
-
-//------------------------------------------------------------------------------
-// Function definition
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-    //------------------------------------------------------------------------------
-    // function:  Set the inband base address in the MCS MDFGPR register
-    //
-    // parameters: i_target       =>   MCS chiplet of processor chip
-    // returns: FAPI_RC_SUCCESS if operation was successful, else error
-    //------------------------------------------------------------------------------
-    fapi::ReturnCode proc_cen_set_inband_addr(const fapi::Target & i_target)
-    {
-        // data buffer to hold register values
-        ecmdDataBufferBase scom_data(64);
-        ecmdDataBufferBase attr_data(64);
-
-        // return codes
-        uint32_t rc_ecmd = 0;
-        fapi::ReturnCode rc;
-
-        // locals
-        uint64_t        inband_base_addr = 0;
-
-
-        // mark function entry
-        FAPI_INF("********* Starting proc_cen_set_inband_addr *********");
-        do
-        {
-
-            // Read the ATTR_MCS_INBAND_BASE_ADDRESS attribute
-            rc = FAPI_ATTR_GET( ATTR_MCS_INBAND_BASE_ADDRESS, &i_target, inband_base_addr);
-            if (rc)
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_MCS_INBAND_BASE_ADDRESS.");
-                break;
-            }
-            FAPI_DBG("The inband base address is specified to be set to: %#llX.", inband_base_addr);
-
-
-
-            // Munge the bits:
-            // Extract bits 14:27 from the attribute value, pass them into bits 6:19 of the register
-            // In the target register:
-            // Bit 0 is MCFGPRQ_VALID.   Needs to be set to '1'.
-            // Bits 6:19 are MCFGPRQ_BASE_ADDRESS.  Needs to be set to base address for inband SCOM operations.
-            rc_ecmd |= attr_data.setDoubleWord(0, inband_base_addr);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x filling ecmd data buffer with value from an attribute.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc_ecmd |= scom_data.flushTo0();
-            // Insert bits 17:27 from the attribute data into the scom data buffer bits 6:19
-            rc_ecmd |= scom_data.insert( attr_data, 6, 14, 14);
-            // Set bit 0 to be a '1'
-            rc_ecmd |= scom_data.setBit(0);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to write MCS MCFGPR Register.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-
-
-            // Write the MCS MCFGPR register.
-            // Write SCOM  address=MCS_MCFGPR_0x02011802 using data from attibute.
-            FAPI_DBG("Writing MCS MCFGPR Register to set base address for inband SCOM operations.");
-            rc = fapiPutScom( i_target, MCS_MCFGPR_0x02011802, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing MCS MCFGPR Register to set base address for inband SCOM operations.");
-                break;
-            }
-
-
-
-        } while (0); // end do
-
-        // mark function exit
-        FAPI_INF("********* proc_cen_set_inband_addr complete *********");
-        return rc;
-    }  // end FAPI procedure proc_cen_set_inband_addr
-
-} // extern "C"
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: proc_cen_set_inband_addr.C,v $
-Revision 1.8  2014/02/05 17:34:30  mfred
-Changed include statements to use <> instead of double-quotes.
-
-Revision 1.7  2012/11/30 15:33:50  mfred
-Several updates suggested by gerrit code review.  Get rid of unused attribute reference.  Change name of inband bar attribute.
-
-Revision 1.6  2012/11/15 20:15:01  mfred
-Update the hwp to take real address from attribute and modify value for BAR register.
-
-Revision 1.5  2012/11/06 17:11:36  mfred
-Procedure now gets the BAR value from the attribute.
-
-Revision 1.4  2012/10/24 15:32:27  mfred
-Temporarilly hardcode the BAR value until the attribute is ready.
-
-Revision 1.3  2012/10/11 14:36:24  mfred
-Updated code to write to MCS MCFGPR Regsiter.
-
-Revision 1.2  2012/10/10 21:11:15  mfred
-Check in some updates to two new procedures.
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H
deleted file mode 100644
index 30b5b836d..000000000
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H
+++ /dev/null
@@ -1,76 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_set_inband_addr/proc_cen_set_inband_addr.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_cen_set_inband_addr.H,v 1.2 2012/11/30 15:33:55 mfred Exp $
-// $Source: /afs/awd.austin.ibm.com/proj/p9/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_set_inband_addr.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_cen_set_inband_addr.H
-// *! DESCRIPTION : Set the inband base address in the MCS unit MCFGPR registers
-// *!
-// *! OWNER NAME  : Mark Fredrickson     Email: mfred@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_CEN_SET_INBAND_ADDR_H_
-#define _PROC_CEN_SET_INBAND_ADDR_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_cen_set_inband_addr_FP_t)(const fapi::Target &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-/**
- * @brief proc_cen_set_inband_addr procedure.  The purpose of this procedure is to set the inband base address in the MCS unit MCFGPR registers
- *
- * @param[in]  i_target  Reference to pu.mcs target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode proc_cen_set_inband_addr(const fapi::Target & i_target);
-    // Target is pu.mcs
-
-} // extern "C"
-
-#endif // _PROC_CEN_SET_INBAND_ADDR_H_
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
deleted file mode 100644
index 9665ff610..000000000
--- a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C
+++ /dev/null
@@ -1,235 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_dmi_scominit.C,v 1.10 2014/05/08 20:46:32 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_dmi_scominit.C
-// *! DESCRIPTION : Invoke DMI initfiles (FAPI)
-// *!
-// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
-// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-//  Version     Date        Owner       Description
-//------------------------------------------------------------------------------
-//    1.9       03/10/14    jmcgill     Add endpoint power up
-//    1.8       10/08/13    jmcgill     Updates for RAS review
-//    1.7       05/14/13    jmcgill     Address review comments
-//    1.6       05/01/13    jgrell      Added proc chip target
-//    1.5       02/06/13    jmcgill     Change passed targets in order to match
-//                                      scominit file updates.
-//    1.4       02/04/13    thomsen     Fixed informational print to not say
-//                                      Error
-//    1.3       01/23/13    thomsen     Added separate calls to base &
-//                                      customized scominit files. Removed
-//                                      separate calls to SIM vs. HW scominit
-//                                      files
-//    1.2       01/10/13    thomsen     Added separate calls to SIM vs. HW
-//                                      scominit files
-//                                      Added commented-out call to OVERRIDE
-//                                      initfile for system/bus/lane specific
-//                                      inits
-//                                      Changed passed targets in order to match
-//                                      scominit file updates.
-//                                      CO-REQs required:
-//                                        p8.dmi.vbu.scom.initfile v1.1 and
-//                                        p8.dmi.hw.scom.initfile v1.1
-//    1.1       8/11/12     jmcgill     Initial release
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapiHwpExecInitFile.H>
-#include <proc_dmi_scominit.H>
-#include <p8_scom_addresses.H>
-
-
-//------------------------------------------------------------------------------
-//  Constant definitions
-//------------------------------------------------------------------------------
-
-// map MCS chiplet ID -> associated bus IORESET bit in IOMC SCOM_MODE_PB
-// register
-const uint8_t IOMC_SCOM_MODE_PB_IORESET_BIT[8] = { 5,4,2,3,5,4,2,3 };
-
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-// HWP entry point, comments in header
-fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-
-    fapi::Target this_pu_target;
-    std::vector<fapi::Target> targets;
-    fapi::Target cen_target;
-
-    uint8_t mcs_pos;
-    ecmdDataBufferBase data(64);
-
-    // mark HWP entry
-    FAPI_INF("proc_dmi_scominit: Start");
-
-    do
-    {
-        // test target type to confirm correct before calling initfile(s)
-        // to execute
-        if (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET)
-        {
-
-            rc = fapiGetOtherSideOfMemChannel(i_target,
-                                              cen_target,
-                                              fapi::TARGET_STATE_FUNCTIONAL);
-            // use return code only to indicate presence of connected Centaur,
-            // do not propogate/emit error if not connected
-            if (rc.ok())
-            {
-                // set the init state attribute to DMI_ACTIVE
-                uint8_t attr_mss_init_state = fapi::ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE;
-                rc = FAPI_ATTR_SET(ATTR_MSS_INIT_STATE,
-                                   &cen_target,
-                                   attr_mss_init_state);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_dmi_scominit: Error from FAPI_ATTR_SET (ATTR_MSS_INIT_STATE) on %s",
-                             cen_target.toEcmdString());
-                    break;
-                }
-            }
-            else
-            {
-                rc = fapi::FAPI_RC_SUCCESS;
-            }
-
-
-            // assert IO reset to power-up bus endpoint logic
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mcs_pos);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_dmi_scominit: Error from FAPI_ATTR_GET (ATTR_CHIP_UNIT_POS) on %s",
-                         i_target.toEcmdString());
-                break;
-            }
-
-            // read-modify-write, set single reset bit (HW auto-clears)
-            // on writeback
-            rc = fapiGetScom(i_target, IOMC_SCOM_MODE_PB_0x02011A20, data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_dmi_scominit: Error from fapiGetScom (IOMC_SCOM_MODE_PB_0x02011A20) on %s",
-                         i_target.toEcmdString());
-                break;
-            }
-
-            rc_ecmd |= data.setBit(IOMC_SCOM_MODE_PB_IORESET_BIT[mcs_pos]);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_dmi_scominit: Error 0x%x forming IOMC SCOM Mode PB register data buffer on %s",
-                         rc_ecmd, i_target.toEcmdString());
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            rc = fapiPutScom(i_target, IOMC_SCOM_MODE_PB_0x02011A20, data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_dmi_scominit: Error from fapiPutScom (IOMC_SCOM_MODE_PB_0x02011A20) on %s",
-                         i_target.toEcmdString());
-                break;
-            }
-
-            // get parent chip target
-            rc = fapiGetParentChip(i_target, this_pu_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_dmi_scominit: Error from fapiGetParentChip (%s)",
-                         i_target.toEcmdString());
-                break;
-            }
-
-            // populate targets vector
-            targets.push_back(i_target);       // chiplet target
-            targets.push_back(this_pu_target); // chip target
-
-            // Call BASE DMI SCOMINIT
-            FAPI_INF("proc_dmi_scominit: fapiHwpExecInitfile executing %s on %s, %s",
-                     MCS_DMI_BASE_IF,
-                     i_target.toEcmdString(),
-                     this_pu_target.toEcmdString());
-            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_BASE_IF);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s, %s",
-                         MCS_DMI_BASE_IF,
-                         i_target.toEcmdString(),
-                         this_pu_target.toEcmdString());
-                break;
-            }
-
-            // Call CUSTOMIZED DMI SCOMINIT
-            FAPI_INF("proc_dmi_scominit: fapiHwpExecInitfile executing %s on %s, %s",
-                     MCS_DMI_CUSTOM_IF,
-                     i_target.toEcmdString(),
-                     this_pu_target.toEcmdString());
-            FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, targets, MCS_DMI_CUSTOM_IF);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_dmi_scominit: Error from fapiHwpExecInitfile executing %s on %s, %s",
-                         MCS_DMI_CUSTOM_IF,
-                         i_target.toEcmdString(),
-                         this_pu_target.toEcmdString());
-                break;
-            }
-        }
-        // unsupported target type
-        else
-        {
-            FAPI_ERR("proc_dmi_scominit: Unsupported target type");
-            const fapi::Target & MCS_TARGET = i_target;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_DMI_SCOMINIT_INVALID_TARGET);
-            break;
-        }
-    } while (0);
-
-    // mark HWP exit
-    FAPI_INF("proc_dmi_scominit: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H b/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H
deleted file mode 100644
index f3f6a304e..000000000
--- a/src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H
+++ /dev/null
@@ -1,87 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dmi_training/proc_dmi_scominit/proc_dmi_scominit.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_dmi_scominit.H,v 1.4 2013/11/09 18:37:40 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_dmi_scominit.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_dmi_scominit.H
-// *! DESCRIPTION : Invoke DMI initfile (FAPI)
-// *!
-// *! OWNER NAME  : Mike Jones        Email: mjjones@us.ibm.com
-// *! BACKUP NAME : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef PROC_DMI_SCOMINIT_H_
-#define PROC_DMI_SCOMINIT_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-const char * const MCS_DMI_BASE_IF   = "p8.dmi.scom.if";
-const char * const MCS_DMI_CUSTOM_IF = "p8.dmi.custom.scom.if";
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_dmi_scominit_FP_t)(const fapi::Target & i_target);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-/**
- * @brief HWP that calls the DMI SCOM initfiles
- *
- * Should be called with all functional MCS chiplets
- *
- * @param[in] i_target Reference to MCS chiplet target
- *                     If TARGET_TYPE_MCS_CHIPLET, calls:
- *                     - p8.dmi.scom.initfile
- *                     - p8.dmi.custom.scom.initfile
- *
- * @return ReturnCode
- */
-fapi::ReturnCode proc_dmi_scominit(const fapi::Target & i_target);
-
-
-} // extern "C"
-
-#endif // PROC_DMI_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C
deleted file mode 100644
index d7fbcd0af..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.C
+++ /dev/null
@@ -1,140 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/dram_initialization.C $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file dram_initialization.C
- *
- *  Support file for IStep: dram_initialization
- *   Dram Initialization
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-#include    <trace/interface.H>
-#include    <initservice/taskargs.H>
-#include    <errl/errlentry.H>
-#include    <errl/errludtarget.H>
-#include    <diag/mdia/mdia.H>
-#include    <diag/attn/attn.H>
-#include    <initservice/isteps_trace.H>
-#include    <isteps/hwpisteperror.H>
-#include    <errl/errludtarget.H>
-#include    <intr/interrupt.H>    // for PIR_t structure
-
-//  targeting support
-#include    <targeting/common/commontargeting.H>
-#include    <targeting/common/util.H>
-#include    <targeting/common/utilFilter.H>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-#include    <isteps/hwpf_reasoncodes.H>
-
-#include    "dram_initialization.H"
-#include    <pbusLinkSvc.H>
-
-//  Uncomment these files as they become available:
-// #include    "host_startPRD_dram/host_startPRD_dram.H"
-#include    "host_mpipl_service/proc_mpipl_ex_cleanup.H"
-#include    "host_mpipl_service/proc_mpipl_chip_cleanup.H"
-#include    "mss_extent_setup/mss_extent_setup.H"
-// #include    "mss_memdiag/mss_memdiag.H"
-// #include    "mss_scrub/mss_scrub.H"
-#include    "mss_thermal_init/mss_thermal_init.H"
-#include    "proc_setup_bars/mss_setup_bars.H"
-#include    "proc_setup_bars/proc_setup_bars.H"
-#include    "proc_pcie_config/proc_pcie_config.H"
-#include    "proc_exit_cache_contained/proc_exit_cache_contained.H"
-#include    "mss_power_cleanup/mss_power_cleanup.H"
-#include    "proc_throttle_sync/proc_throttle_sync.H"
-//remove these once memory setup workaround is removed
-#include <devicefw/driverif.H>
-#include <vpd/spdenums.H>
-#include <sys/time.h>
-#include <sys/mm.h>
-#include <dump/dumpif.H>
-#include <vfs/vfs.H>
-
-#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS
-    #include    <occ/occ_common.H>
-#endif
-
-namespace   DRAM_INITIALIZATION
-{
-
-using   namespace   ISTEP;
-using   namespace   ISTEP_ERROR;
-using   namespace   ERRORLOG;
-using   namespace   TARGETING;
-using   namespace   EDI_EI_INITIALIZATION;
-using   namespace   fapi;
-using   namespace   ERRORLOG;
-
-//
-//  Wrapper function to call mss_extent_setup
-//
-void*    call_mss_extent_setup( void    *io_pArgs )
-{
-    errlHndl_t  l_errl  =   NULL;
-
-    IStepError  l_stepError;
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "call_mss_extent_setup entry" );
-
-    //  call the HWP
-    FAPI_INVOKE_HWP( l_errl, mss_extent_setup );
-
-    if ( l_errl )
-    {
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "ERROR : failed executing mss_extent_setup returning error" );
-
-        // Create IStep error log and cross reference to error that occurred
-        l_stepError.addErrorDetails( l_errl );
-
-        // Commit Error
-        errlCommit( l_errl, HWPF_COMP_ID );
-    }
-    else
-    {
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "SUCCESS : mss_extent_setup completed ok" );
-    }
-
-
-    TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "call_mss_extent_setup exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_stepError.getErrorHandle();
-}
-
-};   // end namespace
diff --git a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H b/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H
deleted file mode 100644
index c6f5ae633..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/dram_initialization.H
+++ /dev/null
@@ -1,230 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/dram_initialization.H $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef  __DRAM_INITIALIZATION_DRAM_INITIALIZATION_H
-#define  __DRAM_INITIALIZATION_DRAM_INITIALIZATION_H
-
-#include <errl/errlentry.H>
-
-/**
- *  @file dram_initialization.H
- *
- *  Dram Initialization
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  *****************************************************************
- *  THIS FILE WAS GENERATED ON 2012-04-11:1608
- *  *****************************************************************
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
- /*  @tag isteplist
- *  @docversion     v1.28 (12/03/12)
- *  @istepname      dram_initialization
- *  @istepnum       14
- *  @istepdesc      Dram Initialization
- *
- *  @{
- *      @substepnum     1
- *      @substepname    host_startprd_dram
- *      @substepdesc    : Load PRD for DRAM domain
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    mss_extent_setup
- *      @substepdesc    MSS Extent Setup
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     3
- *      @substepname    mss_memdiag
- *      @substepdesc     Mainstore Pattern Testing
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     4
- *      @substepname    mss_thermal_init
- *      @substepdesc    : Initialize the thermal sensor
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     5
- *      @substepname    proc_pcie_config
- *      @substepdesc    : Configure the PHBs
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     6
- *      @substepname    mss_power_cleanup
- *      @substepdesc    : Clean up any MCS/Centuars
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     7
- *      @substepname    proc_setup_bars
- *      @substepdesc    : Setup Memory BARs
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     8
- *      @substepname    proc_exit_cache_contained
- *      @substepdesc    : Allow execution from memory
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     9
- *      @substepname    host_mpipl_service
- *      @substepdesc    : host_mpipl_service
- *          @target_sched   serial
- *  @}
-
- */
-
-namespace   DRAM_INITIALIZATION
-{
-
-
-/**
- *  @brief   host_startprd_dram
- *
- *           Load PRD for DRAM domain
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_host_startprd_dram( void    *io_pArgs );
-
-
-/**
- *  @brief   mss_extent_setup
- *
- *           MSS Extent Setup
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_mss_extent_setup( void    *io_pArgs );
-
-/**
- *  @brief   mss_memdiag
- *
- *  Mainstore Pattern Testing
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*   call_mss_memdiag( void    *io_pArgs );
-
-
-/**
- *  @brief   mss_thermal_init
- *
- *           Initialize the thermal sensor
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_mss_thermal_init( void    *io_pArgs );
-
-/**
- *  @brief   proc_pcie_config
- *
- *           Configure the PHBs
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_proc_pcie_config( void    *io_pArgs );
-
-/**
- *  @brief   mss_power_cleanup
- *
- *           Clean up any MCS/Centaurs
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_mss_power_cleanup( void    *io_pArgs );
-
-
-/**
- *  @brief   proc_setup_bars
- *
- *           Setup Memory BARs
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_proc_setup_bars( void    *io_pArgs );
-
-
-/**
- *  @brief   proc_exit_cache_contained
- *
- *           Allow execution from memory
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- */
-void*    call_proc_exit_cache_contained( void    *io_pArgs );
-
-
-/**
- *  @brief   host_mpipl_service
- *
- *           Perform MPIPL tasks
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  pointer to any errlogs
- *
- *  NOTE: this step will only run as part of an mpipl,
- *        the istep dispatcher will not call this step for
- *        the normal ipl flow
- *
- */
-void*   call_host_mpipl_service( void   *io_pArgs);
-
-};   // end namespace
-
-#endif
diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C
deleted file mode 100644
index 2d4c9b01a..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C
+++ /dev/null
@@ -1,346 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_mpipl_chip_cleanup.C,v 1.11 2015/05/01 18:04:36 belldi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_chip_cleanup.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_mpipl_chip_cleanup.C
-// *! DESCRIPTION : To enable MCD recovery
-// *!
-// *! OWNER  NAME : Dion Bell                Email: belldi@us.ibm.com
-// *! BACKUP NAME : Dion Bell                Email: belldi@us.ibm.com
-// *!
-// *! 
-// *! 
-// *! 
-// *! 
-// *! Additional Note(s):
-// *! 
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_mpipl_chip_cleanup.H"
-#include "p8_scom_addresses.H"
-
-extern "C"
-{
-  //------------------------------------------------------------------------------
-  // Function definitions
-  //------------------------------------------------------------------------------
-
-  //------------------------------------------------------------------------------
-  // name: proc_mpipl_chip_cleanup
-  //------------------------------------------------------------------------------
-  // purpose: 
-  // To enable MCD recovery
-  // To remove PCIe Express Controllers (PECs) from CAPP mode
-  //
-  // Note: PHBs are left in ETU reset state after executing proc_mpipl_nest_cleanup, which runs before this procedure.  PHYP releases PHBs from ETU reset post HostBoot IPL.
-  //
-  // SCOM regs
-  //
-  // 1) MCD even recovery control register
-  // 0000000002013410 (SCOM)
-  // bit 0 (MCD_REC_EVEN_ENABLE): 0 to 1 transition needed to start, reset to 0 at end of request.
-  // bit 5 (MCD_REC_EVEN_REQ_PEND)
-  //
-  //
-  // 2) MCD odd recovery control register
-  // 0000000002013411 (SCOM)
-  // bit 0 (MCD_REC_ODD_ENABLE): 0 to 1 transition needed to start, reset to 0 at end of request.
-  // bit 5 (MCD_REC_ODD_REQ_PEND)
-  //
-  // 3) Clear PCI Nest FIR registers
-  // 02012X00 (SCOM) 
-  //
-  // 4) PB AIB CAPP Enable registers
-  // 09013CX3 (SCOM) 
-  // bit 0 (PE_CAPP_EN): Enable CAPP mode of operation 
-  //
-  //
-  // parameters: 
-  // 'i_target' is reference to chip target
-  //
-  // returns:
-  // FAPI_RC_SUCCESS (success, MCD recovery enabled for odd and even slices)
-  //
-  // RC_MCD_RECOVERY_NOT_DISABLED_RC (MCD recovery for even or odd slice is not disabled; therefore can't re-enable MCD recovery)
-  // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_mpipl_chip_cleanup_errors.xml)
-  // 
-  // getscom/putscom fapi errors
-  // fapi error assigned from eCMD function failure
-  // 
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode proc_mpipl_chip_cleanup(const fapi::Target &i_target){
-    const char *procedureName = "proc_mpipl_chip_cleanup"; //Name of this procedure
-    fapi::ReturnCode rc; //fapi return code value
-    uint32_t rc_ecmd = 0;    //ecmd return code value
-    const uint32_t data_size = 64; //Size of data buffer
-    const int MAX_MCD_DIRS = 2; //Max of 2 MCD Directories (even and odd)
-    ecmdDataBufferBase fsi_data[MAX_MCD_DIRS];
-    const uint64_t ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[MAX_MCD_DIRS] = {
-      0x0000000002013410, //MCD even recovery control register address
-      0x0000000002013411  //MCD odd recovery control register address
-    };     
-    const uint32_t MCD_RECOVERY_CTRL_REG_BIT_POS0 = 0; //Bit 0 of MCD even and odd recovery control regs
-    const char *ARY_MCD_DIR_STRS[MAX_MCD_DIRS] = {
-      "Even", //Ptr to char string "Even" for even MCD
-      "Odd"   //Ptr to char string "Odd" for odd MCD
-    }; 
-    uint8_t num_phb;
-    const int MAX_PHBS = 4;
-    const uint64_t PCI_NEST_FIR_REG_ADDRS[MAX_PHBS] = {
-      0x02012000,
-      0x02012400,
-      0x02012800,
-      0x02012C00
-    };     
-    
-    const uint64_t PE_SECURE_CAPP_ENABLE_REG_ADDRS[MAX_PHBS] = {
-      0x09013C03,
-      0x09013C43,
-      0x09013C83,
-      0x09013CC3
-    };
-   
-
-    do {
-      //Set bit length for 64-bit buffers
-      rc_ecmd = fsi_data[0].setBitLength(data_size);
-      rc_ecmd |= fsi_data[1].setBitLength(data_size);
-      if(rc_ecmd) {
-        rc.setEcmdError(rc_ecmd);
-        break;
-      }
-  
-      //Verify MCD recovery was previously disabled for even and odd slices
-      //If not, this is an error condition
-      for (int counter = 0; counter < MAX_MCD_DIRS; counter++) {
-        FAPI_DBG("Verifying MCD %s Recovery is disabled, target=%s", ARY_MCD_DIR_STRS[counter], i_target.toEcmdString());
-        
-        //Get data from MCD Even or Odd Recovery Ctrl reg
-        rc = fapiGetScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data[counter]);
-        if (!rc.ok()) {
-          FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], i_target.toEcmdString());
-          break;
-        }
-        
-  
-        //Check whether bit 0 is 0, meaning MCD recovery is disabled as expected
-        if( fsi_data[counter].getBit(MCD_RECOVERY_CTRL_REG_BIT_POS0) ) {
-          FAPI_ERR("%s: MCD %s Recovery not disabled as expected, target=%s", procedureName, ARY_MCD_DIR_STRS[counter], i_target.toEcmdString());
-          const fapi::Target & CHIP_TARGET = i_target;
-  	  const uint64_t & MCD_RECOV_CTRL_REG_ADDR = ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter];
-          ecmdDataBufferBase & MCD_RECOV_CTRL_REG_DATA = fsi_data[counter];
-          FAPI_SET_HWP_ERROR(rc, RC_MPIPL_MCD_RECOVERY_NOT_DISABLED_RC);
-          break;
-        }
-      }
-      if(!rc.ok()) {
-        break;
-      }
-  
-      //Assert bit 0 of MCD Recovery Ctrl regs to enable MCD recovery
-      for (int counter = 0; counter < MAX_MCD_DIRS; counter++) {
-        FAPI_DBG("Enabling MCD %s Recovery, target=%s", ARY_MCD_DIR_STRS[counter], i_target.toEcmdString());
-        
-        //Assert bit 0 of MCD Even or Odd Recovery Control reg to enable recovery
-        rc_ecmd = fsi_data[counter].setBit(MCD_RECOVERY_CTRL_REG_BIT_POS0 );
-        if(rc_ecmd) {
-          FAPI_ERR("%s: Error (%u) asserting bit pos %u in ecmdDataBufferBase that stores value of MCD %s Recovery Control reg (addr: 0x%08llX), target=%s", procedureName, rc_ecmd, MCD_RECOVERY_CTRL_REG_BIT_POS0, ARY_MCD_DIR_STRS[counter], ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], i_target.toEcmdString());
-          rc.setEcmdError(rc_ecmd);
-          break;
-        }
-        
-        //Write data to MCD Even or Odd Recovery Control reg
-        rc = fapiPutScom(i_target, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], fsi_data[counter]);
-        if (!rc.ok()) {
-          FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, ARY_MCD_RECOVERY_CTRL_REGS_ADDRS[counter], i_target.toEcmdString());
-          break;
-        }
-      }
-      if(!rc.ok()) {
-        break;
-      }
-  
-      // SW227429: clear PCI Nest FIR registers
-      // hostboot is blindly sending EOIs in order to ensure no interrupts are pending when  PHYP starts up again
-      // with ETU held in reset, these get trapped in PCI and force a freeze to occur (PCI Nest FIR(14))
-      // clearing the FIR should remove the freeze condition
-      rc_ecmd = fsi_data[0].flushTo0();
-      if (rc_ecmd) {
-        FAPI_ERR("%s: Error (%u) forming PCI Nest FIR clear data buffer, target=%s", procedureName, rc_ecmd, i_target.toEcmdString());
-        rc.setEcmdError(rc_ecmd);
-        break;
-      }
-      
-      rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB, &i_target, num_phb);
-      if (!rc.ok())
-      {
-          FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)");
-          break;
-      }
-
-      for (int counter = 0; counter < num_phb; counter++) {
-        FAPI_DBG("Clearing PCI%d Nest FIR, target=%s", counter, i_target.toEcmdString());
-        rc = fapiPutScom(i_target, PCI_NEST_FIR_REG_ADDRS[counter], fsi_data[0]);
-        if (!rc.ok()) {
-          FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, PCI_NEST_FIR_REG_ADDRS[counter], i_target.toEcmdString());
-          break;
-        }
-      }
-      if(!rc.ok()) {
-        break;
-      }
-      
-      //SW295661: Clear bit 0 of the Snoop CAPI Configuration register to disable snoop pipelines so Ttype aren't decoded for CAPI
-      FAPI_DBG("Reading Snoop CAPI Configuration register, addr=0x%08llX, target=%s", CAPP_CXA_SNOOP_CFG_0x0201301A, i_target.toEcmdString());
-      rc = fapiGetScom(i_target, CAPP_CXA_SNOOP_CFG_0x0201301A, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_CXA_SNOOP_CFG_0x0201301A, i_target.toEcmdString());
-        break;
-      }
-      rc_ecmd = fsi_data[0].clearBit(0);
-      if (rc_ecmd) {
-        FAPI_ERR("%s: Error (%u) Couldn't clear bit 0 in data buffer for Snoop CAPI Configuration register, target=%s", procedureName, rc_ecmd, i_target.toEcmdString());
-        rc.setEcmdError(rc_ecmd);
-        break;
-      }
-      FAPI_DBG("Snoop CAPI configuration register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", CAPP_CXA_SNOOP_CFG_0x0201301A, fsi_data[0].getDoubleWord(0), i_target.toEcmdString());
-        
-      FAPI_DBG("Writing Snoop CAPI Configuration register, target=%s", i_target.toEcmdString());
-      rc = fapiPutScom(i_target, CAPP_CXA_SNOOP_CFG_0x0201301A, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_CXA_SNOOP_CFG_0x0201301A, i_target.toEcmdString());
-        break;
-      }
-      
-      //SW295661: Clear bit 3 of the APC Master PowerBus Control register to turn off examing cresps when PHBs taken out of CAPP mode
-      FAPI_DBG("Reading APC Master PowerBus Control register, addr=0x%08llX, target=%s", CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString());
-      rc = fapiGetScom(i_target, CAPP_APC_MASTER_PB_CTL_0x02013018, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString());
-        break;
-      }
-      rc_ecmd = fsi_data[0].clearBit(3);
-      if (rc_ecmd) {
-        FAPI_ERR("%s: Error (%u) Couldn't clear bit 3 in data buffer for APC Master PowerBus Control register (addr: 0x%08llX), target=%s", procedureName, rc_ecmd, CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString());
-        rc.setEcmdError(rc_ecmd);
-        break;
-      }
-      FAPI_DBG("APC Master PowerBus Control register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", CAPP_APC_MASTER_PB_CTL_0x02013018, fsi_data[0].getDoubleWord(0), i_target.toEcmdString());
-        
-      FAPI_DBG("Writing APC Master PowerBus Control register (addr: 0x%08llX), target=%s", CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString());
-      rc = fapiPutScom(i_target, CAPP_APC_MASTER_PB_CTL_0x02013018, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_PB_CTL_0x02013018, i_target.toEcmdString());
-        break;
-      }
-      
-      //SW295661: Clear bits 1-3 of the APC Master CAPI Control register to disable PHBs in ES chiplet attached to CAPP PHB port 0 and port 1 interfaces (will get reset to correct vals when code walks PCI buses and configures CAPI)
-      FAPI_DBG("Reading APC Master CAPI Control register, addr=0x%08llX, target=%s", CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString());
-      rc = fapiGetScom(i_target, CAPP_APC_MASTER_CAPI_CTL_0x02013019, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString());
-        break;
-      }
-      rc_ecmd = fsi_data[0].clearBit(1,3);
-      if (rc_ecmd) {
-        FAPI_ERR("%s: Error (%u) Couldn't clear bits 1-3 in data buffer for APC Master CAPI Control register (addr: 0x%08llX) , target=%s", procedureName, rc_ecmd, CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString());
-        rc.setEcmdError(rc_ecmd);
-        break;
-      }
-      FAPI_DBG("APC Master CAPI Control register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", CAPP_APC_MASTER_CAPI_CTL_0x02013019, fsi_data[0].getDoubleWord(0), i_target.toEcmdString());
-        
-      FAPI_DBG("Writing APC Master CAPI Control register (addr: 0x%08llX), target=%s", CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString());
-      rc = fapiPutScom(i_target, CAPP_APC_MASTER_CAPI_CTL_0x02013019, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, CAPP_APC_MASTER_CAPI_CTL_0x02013019, i_target.toEcmdString());
-        break;
-      }
-
-      //SW295661: Clear bits 0 and 1 of CAPP Error Status and Control reg (scom addr: 0x0201300E).
-      FAPI_DBG("Reading CAPP Error Status and Control register, addr=0x%08llX, target=%s", NX_CAPP_ERR_STAT_CTRL_0x0201300E, i_target.toEcmdString());
-      rc = fapiGetScom(i_target, NX_CAPP_ERR_STAT_CTRL_0x0201300E, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, NX_CAPP_ERR_STAT_CTRL_0x0201300E, i_target.toEcmdString());
-        break;
-      }
-      rc_ecmd |= fsi_data[0].clearBit(0); //Clear bit 0 (Error Recovery Initiated)
-      rc_ecmd |= fsi_data[0].clearBit(1); //Clear bit 1 (Error Recovery Complete)
-      if (rc_ecmd) {
-        FAPI_ERR("%s: Error (%u) Couldn't clear bit(s) in data buffer for CAPP Error Status and Control register, target=%s", procedureName, rc_ecmd, i_target.toEcmdString());
-        rc.setEcmdError(rc_ecmd);
-        break;
-      }
-      FAPI_DBG("CAPP Error Status and Control register, addr: 0x%08llX, buffer value to write: 0x%016llX, chip: %s", NX_CAPP_ERR_STAT_CTRL_0x0201300E, fsi_data[0].getDoubleWord(0), i_target.toEcmdString());
-        
-      FAPI_DBG("Writing CAPP Error Status and Control register, target=%s", i_target.toEcmdString());
-      rc = fapiPutScom(i_target, NX_CAPP_ERR_STAT_CTRL_0x0201300E, fsi_data[0]);
-      if (!rc.ok()) {
-        FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, NX_CAPP_ERR_STAT_CTRL_0x0201300E, i_target.toEcmdString());
-        break;
-      }
-
-      //SW295661: Disable CAPP mode of operation by clearing bit 0 of PE Secure CAPP Enable register
-      for (int counter = 0; counter < num_phb; counter++) {
-        FAPI_DBG("Reading PE%d Secure CAPP Enable register (addr: 0x%08llX), target=%s", counter, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString());
-        rc = fapiGetScom(i_target, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], fsi_data[0]);
-        if (!rc.ok()) {
-          FAPI_ERR("%s: fapiGetScom error (addr: 0x%08llX), target=%s", procedureName, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString());
-          break;
-        }
-
-        rc_ecmd = fsi_data[0].clearBit(0);
-        if (rc_ecmd) {
-          FAPI_ERR("%s: Error (%u) Couldn't clear bit 0 in data buffer for PE%d Secure CAPP Enable register (addr: 0x%08llX), target=%s", procedureName, rc_ecmd, counter, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString());
-          rc.setEcmdError(rc_ecmd);
-          break;
-        }
-
-        FAPI_DBG("Writing PE%d Secure CAPP Enable register (addr: 0x%08llX), target=%s", counter, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString());
-        rc = fapiPutScom(i_target, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], fsi_data[0]);
-        if (!rc.ok()) {
-          FAPI_ERR("%s: fapiPutScom error (addr: 0x%08llX), target=%s", procedureName, PE_SECURE_CAPP_ENABLE_REG_ADDRS[counter], i_target.toEcmdString());
-          break;
-        }
-      }
-    } while(0);
-
-    FAPI_IMP("Exiting %s", procedureName);
-
-    return rc;
-  }
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H
deleted file mode 100644
index 0d12def30..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H
+++ /dev/null
@@ -1,73 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_chip_cleanup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_mpipl_chip_cleanup.H,v 1.3 2014/03/02 23:16:17 belldi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_chip_cleanup.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_mpipl_chip_cleanup.H
-// *! DESCRIPTION : To enable MCD recovery
-// *!
-// *! OWNER  NAME  : Dion Bell                Email: belldi@us.ibm.com
-// *! BACKUP NAME  : Dion Bell                Email: belldi@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_MPIPL_CHIP_CLEANUP_H_
-#define _PROC_MPIPL_CHIP_CLEANUP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure Definition(s)
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_mpipl_chip_cleanup_FP_t) (const fapi::Target &);
-
-extern "C"
-{
-  /**
-  * @brief To enable MCD recovery
-  *
-  * @param[in] (1) 'i_target' Reference to processor chip target
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode proc_mpipl_chip_cleanup(const fapi::Target & i_target);
-
-
-
-} //extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C
deleted file mode 100644
index d90305dc3..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C
+++ /dev/null
@@ -1,277 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_mpipl_ex_cleanup.C,v 1.6 2013/08/20 17:31:41 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_mpipl_ex_cleanup.C
-// *! DESCRIPTION : Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode
-// *!
-// *! OWNER  NAME : Dion Bell                Email: belldi@us.ibm.com
-// *! BACKUP NAME : Dion Bell                Email: belldi@us.ibm.com
-// *!
-// *!
-// *!
-// *!
-// *! Additional Note(s):
-// *!
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_mpipl_ex_cleanup.H"
-#include "p8_scom_addresses.H"
-
-extern "C"
-{
-
-  //------------------------------------------------------------------------------
-  // name: proc_mpipl_ex_cleanup
-  //------------------------------------------------------------------------------
-  // purpose:
-  // Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode
-  // SCOM regs:
-  // 1) GP3 Register (NA in PERV CPLT)
-  //
-  // bit 27 (TP_LVLTRANS_FENCE): Electrical winkel fence. Mainly used by power management.
-  //
-  // 2) PowerManagement GP0 reg
-  //
-  // bit 22 (TP_TC_PERVASIVE_ECO_FENCE): Pervasive ECO fence
-  //
-  // bit 39 (PM_SLV_WINKLE_FENCE): Fence off the powered off chiplet in winkle. - Logical fence/hold for pcb_slave and pcb_slave_pm. For electrical fence see bit 23.
-  //
-  // 3) PowerManagement GP1
-  //
-  // Bit 5: WINKLE_POWER_OFF_SEL: Winkle Power Off Select:
-  // Selects which voltage level to place the Core and ECO domain PFETs upon Winkle entry. 0 = Vret (Fast Winkle Mode), 1 = Voff (Deep Winkle Mode). Depending on the setting of pmicr_latency_en, this bit is controlled with a PCB-write (0) or by the PMICR in the core (1).
-  //
-  // Bit 15: PMICR_LATENCY_EN: Selects how the sleep/winkle latency (which is deep/fast) is controlled. If asserted the PMICR controls the winkle/sleep_power_off_sel in PMGP1, otherwise those bits are controlled via SCOM by OCC.
-
-  // parameters:
-  // 'i_target' is chip target
-  //
-  // returns:
-  // FAPI_RC_SUCCESS (success, EX chiplets entered fast winkle)
-  //
-  // getscom/putscom/getattribute fapi errors
-  // fapi error assigned from eCMD function failure
-  //
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode proc_mpipl_ex_cleanup(const fapi::Target & i_target) {
-    const char          *procedureName = "proc_mpipl_ex_cleanup";
-    fapi::ReturnCode    rc; //fapi return code
-    uint32_t            rc_ecmd = 0;    //ecmd return code value
-    ecmdDataBufferBase  fsi_data(64); //64-bit data buffer
-    uint8_t             attr_chip_unit_pos; //EX chiplet's unit offset within chip with respect to similar EX units
-    const uint64_t      EX_OFFSET_MULT = 0x01000000; //Multiplier used to calculate offset for respective EX chiplet
-
-    uint64_t            address;   // Varible for computed addresses
-    uint64_t            offset;
-    char                reg_name[32];  // Character array for register names
-
-
-    // Relevant PMGP0 bits
-//    const uint32_t      PM_DISABLE = 0;
-    const uint32_t      BLOCK_REG_WKUP_SOURCE = 53;
-
-
-    // Relevant PMGP1 bits  
-    const uint32_t      WINKLE_POWER_OFF_SEL = 5;
-
-    std::vector<fapi::Target> v_ex_chiplets; //Vector of EX chiplets
-
-
-    do
-    {
-        //Entering fapi function
-        FAPI_INF("Entering %s", procedureName);
-
-        //Get vector of EX chiplets
-        rc = fapiGetChildChiplets(  i_target, 
-                                    fapi::TARGET_TYPE_EX_CHIPLET, 
-                                    v_ex_chiplets, 
-                                    fapi::TARGET_STATE_FUNCTIONAL); 
-        if (rc) 
-        {
-             FAPI_ERR("%s: fapiGetChildChiplets error", procedureName);
-             break;
-        }
-
-        FAPI_INF("Processing target %s", i_target.toEcmdString());
-        
-        //Parse thru EX chiplets and prepare fast-winkled cores for deep operations
-        //Loop thru EX chiplets in vector
-        for (uint32_t counter = 0; counter < v_ex_chiplets.size(); counter++)
-        {
-
-            // Get EX chiplet number
-            rc = FAPI_ATTR_GET( ATTR_CHIP_UNIT_POS,
-                                &(v_ex_chiplets[counter]),
-                                attr_chip_unit_pos);
-            if (rc)
-            {
-                FAPI_ERR("%s: fapiGetAttribute error (ATTR_CHIP_UNIT_POS)", procedureName);
-                break;
-            }
-            FAPI_INF("EX chiplet pos = 0x%02X", attr_chip_unit_pos);
-
-
-            // Calculate the address offset based on chiplet number
-            offset = EX_OFFSET_MULT * attr_chip_unit_pos;
-                        
-            // -----------------------------------------------------------------
-            FAPI_DBG("\tOriginal register contents");
-            address = EX_GP3_0x100F0012 + offset;
-            strcpy(reg_name, "GP3");
-            rc = fapiGetScom( i_target, address, fsi_data );
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0));
-            
-            address = EX_PMGP0_0x100F0100 + offset;
-            strcpy(reg_name, "PMGP0");
-            rc = fapiGetScom( i_target, address, fsi_data );
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0));
-
-            address = EX_PMGP1_0x100F0103 + offset;
-            strcpy(reg_name, "PMGP1");
-            rc = fapiGetScom( i_target, address, fsi_data );
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0));
-            // -----------------------------------------------------------------
-
-            // Clean up configuration remnants of the fast-winkle configuration
-            // that  was used to flush the chiplets after checkstop.  EX chiplets
-            // will have been through SBE EX Init with certain step skippled due 
-            // to MPIPL.
-            
-            FAPI_INF("Re-establish Deep Winkle mode default");
-            address = EX_PMGP1_OR_0x100F0105 + offset;
-            strcpy(reg_name, "PMGP1 OR");
-
-            rc_ecmd |= fsi_data.flushTo0();
-            rc_ecmd |= fsi_data.setBit(WINKLE_POWER_OFF_SEL);
-            if(rc_ecmd)
-            {
-                FAPI_ERR("ecmdDatatBuffer error preparing %s reg (addr: 0x%08llX) with rc %x", reg_name, address, rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, address, fsi_data);
-            if (rc)
-            {
-                FAPI_ERR("fapiPutScom error (addr: 0x%08llX)", address);
-                break;
-            }
-
-            FAPI_INF("Clear block wakeup sources to PM logic.  PM is NOT re-enabled");
-            // (eg clear Block Interrrupt Sources)
-            address = EX_PMGP0_AND_0x100F0101 + offset;
-            strcpy(reg_name, "PMGP0 AND");
-
-            rc_ecmd |= fsi_data.flushTo1();
-//            rc_ecmd |= fsi_data.clearBit(PM_DISABLE);
-            rc_ecmd |= fsi_data.clearBit(BLOCK_REG_WKUP_SOURCE);
-            if(rc_ecmd)
-            {
-                FAPI_ERR("ecmdDatatBuffer error preparing %s reg (addr: 0x%08llX)", reg_name, address);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, address, fsi_data);
-            if (rc)
-            {
-                 FAPI_ERR("fapiPutScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            
-            // -----------------------------------------------------------------
-            FAPI_DBG("\tUpdated register contents");
-            address = EX_GP3_0x100F0012 + offset;
-            strcpy(reg_name, "GP3");
-            rc = fapiGetScom( i_target, address, fsi_data );
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0));
-            
-            address = EX_PMGP0_0x100F0100 + offset;
-            strcpy(reg_name, "PMGP0");
-            rc = fapiGetScom( i_target, address, fsi_data );
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0));
-
-            address = EX_PMGP1_0x100F0103 + offset;
-            strcpy(reg_name, "PMGP1");
-            rc = fapiGetScom( i_target, address, fsi_data );
-            if (rc)
-            {
-                FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", address);
-                break;
-            }
-            FAPI_DBG("\t%s (addr: 0x%08llX), val=0x%016llX", reg_name, address, fsi_data.getDoubleWord(0));
-            // -----------------------------------------------------------------
-        } // chiplet loop
-
-        // Error exit from above loop
-        // Not really needed as outer while(0) is next but here for consistent structure
-        if (!rc.ok())
-        {
-            break;
-        }
-    } while (0);
-
-    //Exiting fapi function
-    FAPI_INF("Exiting %s", procedureName);
-
-    return rc;
-  }
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H
deleted file mode 100644
index 9b2f6e694..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H
+++ /dev/null
@@ -1,71 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/host_mpipl_service/proc_mpipl_ex_cleanup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_mpipl_ex_cleanup.H,v 1.4 2014/03/03 00:42:49 belldi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_mpipl_ex_cleanup.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_mpipl_ex_cleanup.H
-// *! DESCRIPTION : Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode
-// *!
-// *! OWNER  NAME  : Dion Bell                Email: belldi@us.ibm.com
-// *! BACKUP NAME  : Dion Bell                Email: belldi@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_MPIPL_EX_CLEANUP_H_
-#define _PROC_MPIPL_EX_CLEANUP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <vector>
-
-//------------------------------------------------------------------------------
-// Structure Definition(s)
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_mpipl_ex_cleanup_FP_t) (const fapi::Target &);
-
-extern "C"
-{
-  /**
-  * @brief Undo step that prepared fast-winkled cores for scanning and set up deep winkle mode
-  *
-  * @param[in] (1) 'i_target' Reference to processor chip target
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode proc_mpipl_ex_cleanup(const fapi::Target &i_target);
-}
-
-#endif
diff --git a/src/usr/hwpf/hwp/dram_initialization/makefile b/src/usr/hwpf/hwp/dram_initialization/makefile
deleted file mode 100644
index b5bf93cf2..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/makefile
+++ /dev/null
@@ -1,90 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/dram_initialization/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2014
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-MODULE = dram_initialization
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
-
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/cen_stopclocks
-
-##  NOTE: add the base istep dir here.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/dram_initialization/mss_memdiag
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config/
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += dram_initialization.o
-OBJS += proc_exit_cache_contained.o
-OBJS += mss_extent_setup.o
-OBJS += mss_setup_bars.o
-OBJS += proc_fab_smp.o
-OBJS += proc_setup_bars.o
-OBJS += proc_pcie_config.o
-OBJS += proc_mpipl_ex_cleanup.o
-OBJS += proc_mpipl_chip_cleanup.o
-OBJS += mss_thermal_init.o
-OBJS += mss_power_cleanup.o
-OBJS += proc_throttle_sync.o
-
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/<HWP_dir>
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_memdiag
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/host_mpipl_service
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
deleted file mode 100644
index 465862227..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_extent_setup.C,v 1.8 2012/07/17 13:24:10 bellows Exp $
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-//Owner :- Girisankar paulraj
-//Back-up owner :- Mark bellows
-//
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.8    | bellows  |16-Jul-12| added in Id tag
-//  1.7    | bellows  |15-Jun-12| Updated for Firmware
-//  1.3    | gpaulraj |11-Nov-11| modified according HWPF format
-//  1.2    | gpaulraj |02-oct-11| supported for MCS loop - SIM model. compiled in the ecmd & FAPI calls included.
-//  1.1    | gpaulraj |31-jul-11| First drop for centaur
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-//#include <prcdUtils.H>
-//#include <verifUtils.H>
-//#include <cen_maintcmds.H>
-#include <mss_extent_setup.H>
-//----------------------------------------------------------------------
-//  eCMD Includes
-//----------------------------------------------------------------------
-//#include <ecmdClientCapi.H>
-//#include <ecmdDataBuffer.H>
-//#include <ecmdUtils.H>
-//#include <ecmdSharedUtils.H>
-//#include <fapiClientCapi.H>
-//#include <croClientCapi.H>
-//#include <fapi.H>
-//#include <fapiSystemConfig.H> 
-//#include <fapiSharedUtils.H>
-// attributes listing
-// FAPI procedure calling
-//
-extern "C" {
-
-using namespace fapi;
-
-
-ReturnCode mss_extent_setup(){
-
-    ReturnCode rc;
-	    if(rc){
-		FAPI_ERR(" Calling Extent function Error ");
-		return rc;
-	    }
-    return rc;
-}
-
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
deleted file mode 100755
index 9fa840606..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
+++ /dev/null
@@ -1,72 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_extent_setup.H,v 1.8 2012/07/17 13:22:51 bellows Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_extent_setup.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : girisankar paulraj     Email: gpaulraj@in.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_extent_setup.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.8    | bellows  |16-Jul-12| added in Id tag
-//  1.7    | bellows  |15-Jun-12| Updated for Firmware
-//   1.2   |          |         |
-//   1.1   | gpaulraj |11-NOV-11| First Draft.
-
-#ifndef MSS_EXTENT_SETUP_H_
-#define MSS_EXTENT_SETUP_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_extent_setup_FP_t)();
-
-extern "C"
-{
-
-/**
- * @brief extent setup  procedure -- currently an open shell until extent functions are found t obe needed 
- *
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode mss_extent_setup();
-
-} // extern "C"
-
-#endif // MSS_EXTENT_SETUP_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C b/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C
deleted file mode 100644
index 9165bcf7e..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C
+++ /dev/null
@@ -1,541 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_power_cleanup.C,v 1.7 2014/02/19 13:41:33 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_power_cleanup.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_power_cleanup
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Bellows      Email: bellows@us.ibm.com
-// *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com
-
-// *! ADDITIONAL COMMENTS :
-//
-// power clean up
-// needs to deconfig centaurs and mba - (needs three targets)
-//    Two reasons:  centaur is bad and no DIMMs
-//    Needed to set up fences and turn off power / clock drivers
-//
-// There is a sub function that cleans up an mba that needs to be called if we deconfigure an mba
-// this procedure does not write attributes just shuts down hardware
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.7   | bellows  |19-FEB-14| RAS Review Updates Pass 2
-//   1.6   |bellows   |17-FEB-14| RAS review updates
-//   1.5   |bellows   |05-FEB-14| Making this procedure work on really non-functional centaurs
-//   1.4   |bellows   |21-Nov-13| Gerrit Review Updates - unused variable removed
-//   1.3   |bellows   |11-Nov-13| Gerrit Review Updates
-//   1.2   |bellows   |11-Nov-13| Update due to new istep location
-//   1.1   |bellows   |07-Nov-13| copied from mss_cnfg_cleanup version 1.3
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// My Includes
-//------------------------------------------------------------------------------
-#include <cen_stopclocks.H>
-#include <mss_power_cleanup.H>
-#include <cen_scom_addresses.H>
-#include <mss_eff_config.H>
-#include <common_scom_addresses.H>
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Constants
-//------------------------------------------------------------------------------
-
-const uint8_t PORT_SIZE = 2;
-const uint8_t DIMM_SIZE = 2;
-
-
-//------------------------------------------------------------------------------
-// extern encapsulation
-//------------------------------------------------------------------------------
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// @brief mss_power_cleanup(): This function will disable a centaur - fencing it and powering it down
-//
-// @param const fapi::Target i_target_centaur: the fapi target of the centaur
-// @param const fapi::Target i_target_mba0: the mba0 target
-// @param const fapi::Target i_target_mba1: the mba1 target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-  fapi::ReturnCode mss_power_cleanup(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1)
-  {
-    fapi::ReturnCode rc,rc0,rc1,rcf,rcc;
-    uint8_t centaur_functional=1, mba0_functional=1, mba1_functional=1;
-
-    FAPI_INF("Running mss_power_cleanupon %s\n", i_target_centaur.toEcmdString());
-
-    do
-    {
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_centaur, centaur_functional);
-      if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; }
-
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba0, mba0_functional);
-      if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; }
-
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba1, mba1_functional);
-      if(rc) { FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL"); break; }
-
-      rc0 = mss_power_cleanup_mba_part1(i_target_centaur, i_target_mba0);
-      rc1 = mss_power_cleanup_mba_part1(i_target_centaur, i_target_mba1);
-
-      rcf = mss_power_cleanup_mba_fence(i_target_centaur, i_target_mba0, i_target_mba1);
-
-      rcc = mss_power_cleanup_centaur(i_target_centaur);
-
-
-
-      if(rc0) {
-        if(mba0_functional) {
-          FAPI_ERR("mba0 was functional yet it got a bad return code");
-          const fapi::Target & MBA_CHIPLET = i_target_mba0;
-          FAPI_SET_HWP_ERROR(rc0, RC_MSS_POWER_CLEANUP_MBA0_UNEXPECTED_BAD_RC);
-          rc=rc0;
-          break;
-        }
-        else {
-          FAPI_INF("mba0 was not functional and it got a bad return code");
-        }
-      }
-
-      if(rc1) {
-        if(mba1_functional) {
-          FAPI_ERR("mba1 was functional yet it got a bad return code");
-          const fapi::Target & MBA_CHIPLET = i_target_mba1;
-          FAPI_SET_HWP_ERROR(rc1, RC_MSS_POWER_CLEANUP_MBA1_UNEXPECTED_BAD_RC);
-          rc=rc1;
-          break;
-        }
-        else {
-          FAPI_INF("mba1 was not functional and it got a bad return code");
-        }
-      }
-
-      if(rcf) {
-        if(centaur_functional) {
-          FAPI_ERR("centaur was functional yet it got a bad return code during fencing");
-          const fapi::Target & CENTAUR = i_target_centaur;
-          FAPI_SET_HWP_ERROR(rcf, RC_MSS_POWER_CLEANUP_FENCING_UNEXPECTED_BAD_RC);
-          rc=rcf;
-          break;
-        }
-        else {
-          FAPI_INF("centaur was not functional and it got a bad return code");
-        }
-      }
-
-      if(rcc) {
-        if(centaur_functional) {
-          FAPI_ERR("centaur was functional yet it got a bad return code during cleanup");
-          const fapi::Target & CENTAUR = i_target_centaur;
-          FAPI_SET_HWP_ERROR(rcc, RC_MSS_POWER_CLEANUP_CENTAUR_UNEXPECTED_BAD_RC);
-          rc=rcc;
-          break;
-        }
-        else {
-          FAPI_INF("centaur was not functional and it got a bad return code");
-        }
-      }
-
-    } while(0); 
-
-    return rc;
-  } // end mss_power_cleanup()
-
-  fapi::ReturnCode set_powerdown_bits(int mba_functional,  ecmdDataBufferBase &data_buffer_64)
-  {
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-
-    if(mba_functional == 0)
-    {
-      FAPI_INF("set_powerdown_bits MBA not Functional");
-      rc_num |= data_buffer_64.setBit(0  +48);    // MASTER_PD_CNTL (48)
-      rc_num |= data_buffer_64.setBit(1  +48);    // ANALOG_INPUT_STAB2 (49)
-      rc_num |= data_buffer_64.setBit(7  +48);    // ANALOG_INPUT_STAB1 (55)
-      rc_num |= data_buffer_64.setBit(8  +48,2);  // SYSCLK_CLK_GATE (56:57)
-      rc_num |= data_buffer_64.setBit(10 +48);    // DP18_RX_PD(0) (58)
-      rc_num |= data_buffer_64.setBit(11 +48);    // DP18_RX_PD(1) (59)
-      rc_num |= data_buffer_64.setBit(14 +48);    // TX_TRISTATE_CNTL (62)
-      rc_num |= data_buffer_64.setBit(15 +48);    // VCC_REG_PD (63)
-    }
-    else
-    {
-      rc_num |= data_buffer_64.clearBit(0  +48);    // MASTER_PD_CNTL (48)
-      rc_num |= data_buffer_64.clearBit(1  +48);    // ANALOG_INPUT_STAB2 (49)
-      rc_num |= data_buffer_64.clearBit(7  +48);    // ANALOG_INPUT_STAB1 (55)
-      rc_num |= data_buffer_64.clearBit(8  +48,2);  // SYSCLK_CLK_GATE (56:57)
-      rc_num |= data_buffer_64.clearBit(10 +48);    // DP18_RX_PD(0) (58)
-      rc_num |= data_buffer_64.clearBit(11 +48);    // DP18_RX_PD(1) (59)
-      rc_num |= data_buffer_64.clearBit(14 +48);    // TX_TRISTATE_CNTL (62)
-      rc_num |= data_buffer_64.clearBit(15 +48);    // VCC_REG_PD (63)
-    }
-
-    if (rc_num)
-    {
-      FAPI_ERR( "Error setting up buffers");
-      rc.setEcmdError(rc_num);
-    }
-
-    return rc;
-  }
-
-  fapi::ReturnCode mss_power_cleanup_mba_part1(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba)
-  {
-  // turn off functional vector
-    fapi::ReturnCode rc;
-    uint8_t centaur_functional;
-    uint8_t mba_functional;
-    ecmdDataBufferBase data_buffer_64(64);
-    uint32_t rc_num = 0;
-    uint8_t unit_pos = 0;
-    ecmdDataBufferBase cfam_data(32);
-    int memon=0;
-
-    do
-    {
-      FAPI_INF("Starting mss_power_cleanup_mba_part1");
-
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_centaur, centaur_functional);
-      if(rc)
-      {
-        FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL");
-        break;
-      }
-      FAPI_INF("working on a centaur whose functional is %d", centaur_functional);
-
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba, mba_functional);
-      if(rc) {
-        FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL");
-        break;
-      }
-      FAPI_INF("working on an mba whose functional is %d", mba_functional);
-
-// But to clarify so there's no misconception, you can only turn off the clocks to the MEMS grid (Ports 2/3).  If you want to deconfigure Ports 0/1, there is no way to turn those clocks off. The best you can do there is shut down the PHY inside DDR (I think they have an ultra low power mode where you can turn off virtually everything including their PLLs, phase rotators, analogs , FIFOs, etc) plus of course you can disable their I/O. I think those steps should be done no matter which port you're deconfiguring, but in terms of the chip clock grid, you only get that additional power savings in the bad Port 2/3 case.
-      if(centaur_functional == 1 && mba_functional == 0)
-      {
-        FAPI_INF("cleanup_part1 MBA not functional");
-      // check that clocks are up to the DDR partition before turning it off
-      // this case will only happen if we get memory up and later come back and want to
-      // deconfigure it.  The first time, it may not even be up yet.
-        rc = fapiGetScom(i_target_centaur, TP_CLK_STATUS_0x01030008, data_buffer_64);
-        if(rc) {
-          FAPI_ERR("ERROR: Cannot getScom 0x1030008");
-          break;
-        }
-        if(data_buffer_64.getDoubleWord(0) == 0x000007FFFFFFFFFFull)
-        { // pervasive clocks are on
-          rc = fapiGetScom(i_target_centaur, MEM_CLK_STATUS_0x03030008, data_buffer_64);
-          if(rc)
-          {
-            FAPI_ERR("ERROR: Cannot getScom 0x3030008");
-            break;
-          }
-          if(data_buffer_64.getDoubleWord(0) == 0x0000001FFFFFFFFFull)
-          {
-            memon=1;
-          }
-        }
-
-
-        if(memon)
-        {
-          FAPI_INF("Mem Clocks On");
-
-          if(mba_functional == 0)
-          {
-
-            FAPI_INF("This mba is not functional, doing more transactions");
-
-      // Do Port 0
-            rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, data_buffer_64);
-            if(rc)
-            {
-              FAPI_ERR("ERROR: Cannot getScom DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F");
-              break;
-            }
-
-            rc = set_powerdown_bits(mba_functional, data_buffer_64);
-            if(rc) break;
-
-            rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, data_buffer_64);
-            if(rc)
-            {
-              FAPI_ERR("ERROR: Cannot putScom DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F");
-              break;
-            }
-
-      // Do Port 1
-            rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, data_buffer_64);
-            if(rc)
-            {
-              FAPI_ERR("ERROR: Cannot getScom DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F");
-              break;
-            }
-
-            rc = set_powerdown_bits(mba_functional, data_buffer_64);
-            if(rc) break;
-
-            rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, data_buffer_64);
-            if(rc)
-            {
-              FAPI_ERR("ERROR: Cannot putScom DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F");
-              break;
-            }
-// From Section 10.4
-          } // mba functional
-        }
-//12. Grid Clock off , South Port Pair. This is done by asserting the GP bit controlling
-//TP_CHIP_DPHY23_GRID_DISABLE (Table 57 ). This must be decided during CFAMINIT . it may not be
-//dynamically updated
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, unit_pos); // 0 = MBA01 and 1 = MBA23
-        if(rc)
-        {
-          FAPI_ERR("ERROR: Cannot get ATTR_CHIP_UNIT_POS");
-          break;
-        }
-
-        if(unit_pos == 1)
-        {
-          rc = fapiGetCfamRegister( i_target_centaur, CFAM_FSI_GP4_0x00001013, cfam_data);
-          if(rc)
-          {
-            FAPI_ERR("ERROR: Cannot getCfamRegister CFAM_FSI_GP4_0x00001013");
-            break;
-          }
-
-          if(mba_functional == 0)
-          {
-            rc_num |= cfam_data.setBit(1);
-          }
-          else
-          {
-            rc_num |= cfam_data.clearBit(1);
-          }
-
-          if (rc_num)
-          {
-            FAPI_ERR( "Error setting up buffers");
-            rc.setEcmdError(rc_num);
-            break;
-          }
-
-          rc = fapiPutCfamRegister( i_target_centaur, CFAM_FSI_GP4_0x00001013, cfam_data);
-          if(rc)
-          {
-            FAPI_ERR("ERROR: Cannot putCfamRegister CFAM_FSI_GP4_0x00001013");
-            break;
-          }
-        } // mba 1 only code
-
-      }
-    }
-    while(0);
-
-    if(rc) {
-      FAPI_ERR("ERROR: Bad RC in mss_power_cleanup_mba_part1");
-    }
-    return rc;
-  } // end of mss_power_cleanup_mba_part1
-
-  fapi::ReturnCode mss_power_cleanup_mba_fence(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1) {
-  // turn off functional vector
-    fapi::ReturnCode rc;
-    uint8_t mba_functional0, mba_functional1;
-    ecmdDataBufferBase data_buffer_64(64);
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase cfam_data(32);
-    int memon=0;
-
-    do
-    {
-      FAPI_INF("Starting mss_power_cleanup_mba_fence");
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba0, mba_functional0);
-      if(rc) break;
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_mba1, mba_functional1);
-      if(rc) break;
-      FAPI_INF("mba0 functional is %d", mba_functional0);
-      FAPI_INF("mba1 functional is %d", mba_functional1);
-
-
-//enable_partial_good_dc memn_fence_dc mems_fence_dc Fencing Behavior
-//0 0 0 Normal operation, no fencing enabled
-//0 1 1 Chiplet boundary (inter chiplet nets) fencing enabled. Both
-//      bits set for full fencing. Both MBAs fenced from MBS but
-//      not from each other
-//0 0 1 Not a valid setting. Fencing enabled for MEMS chiplet boundary only.
-//0 1 0 Not a valid setting. Fencing enabled for MEMS chiplet boundary only.
-//1 0 0 No Fencing enabled .
-//1 0 1 MEMS (Ports 2/3) bad, fencing enabled to MEMN and at chiplet boundary of MEMS
-//1 1 0 MEMN (Ports 0/1) bad, fencing enabled to MEMS and at chiplet boundary of MEMN
-//1 1 1 Fencing enabled between MEMN and MEMS and at chiplet boundary.
-      rc = fapiGetScom(i_target_centaur, TP_CLK_STATUS_0x01030008, data_buffer_64);
-      if(rc) break;
-      if(data_buffer_64.getDoubleWord(0) == 0x000007FFFFFFFFFFull)
-      { // pervasive clocks are on
-        rc = fapiGetScom(i_target_centaur, MEM_CLK_STATUS_0x03030008, data_buffer_64);
-        if(rc) break;
-        if(data_buffer_64.getDoubleWord(0) == 0x0000001FFFFFFFFFull)
-        {
-          memon=1;
-        }
-      }
-
-      if(memon) {
-        FAPI_INF("Mem Clocks On");
-        rc = fapiGetScom( i_target_centaur, MEM_GP3_0x030F0012, data_buffer_64);
-        if (rc) break;
-
-        if(mba_functional0 == 0 || mba_functional1 == 0)
-        { // one of the two are non-functional
-          rc_num |= data_buffer_64.setBit(31); // enable_partial_good_dc
-        }
-        else
-        {
-          rc_num |= data_buffer_64.clearBit(31); 
-        }
-
-        if(mba_functional0 == 0)
-        {
-          rc_num |= data_buffer_64.setBit(18); // memn_fence_dc
-        }
-        else
-        {
-          rc_num |= data_buffer_64.clearBit(18); // memn_fence_dc
-        }
-        if(mba_functional1 == 0)
-        {
-          rc_num |= data_buffer_64.setBit(17); // mems_fence_dc
-        }
-        else {
-          rc_num |= data_buffer_64.clearBit(17); // mems_fence_dc
-        }
-
-        if (rc_num)
-        {
-          FAPI_ERR( "Error setting up buffers");
-          rc.setEcmdError(rc_num);
-          break;
-        }
-
-        rc = fapiPutScom( i_target_centaur, MEM_GP3_0x030F0012, data_buffer_64);
-        if (rc) break;
-      }
-
-
-    } while(0);
-
-    if(rc)
-    {
-      FAPI_ERR("ERROR: during mss_power_cleanup_mba_fence");
-    }
-    return rc;
-  } // end of mss_power_cleanup_mba_fense
-
-  fapi::ReturnCode mss_power_cleanup_centaur(const fapi::Target & i_target_centaur) {
-  // turn off functional vector
-    fapi::ReturnCode rc;
-    uint8_t centaur_functional;
-
-    do
-    {
-      FAPI_INF("Starting mss_power_cleanup_centaur");
-      rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &i_target_centaur, centaur_functional);
-      if(rc) {
-        FAPI_ERR("ERROR: Cannot get ATTR_FUNCTIONAL");
-        break;
-      }
-
-      int memon=0;
-      int pervon=0;
-      ecmdDataBufferBase data_buffer_64(64);
-
-      if(centaur_functional == 0) { 
-      // check that clocks are up to the DDR partition before turning it off
-      // this case will only happen if we get memory up and later come back and want to
-      // deconfigure it.  The first time, it may not even be up yet.
-        rc = fapiGetScom(i_target_centaur, TP_CLK_STATUS_0x01030008, data_buffer_64);
-        if(rc)
-        {
-          FAPI_ERR("ERROR: Cannot getScom 0x1030008");
-          break;
-        }
-        if(data_buffer_64.getDoubleWord(0) == 0x000007FFFFFFFFFFull)
-        { // pervasive clocks are on
-          pervon=1;
-          rc = fapiGetScom(i_target_centaur, MEM_CLK_STATUS_0x03030008, data_buffer_64);
-          if(rc)
-          {
-            FAPI_ERR("ERROR: Cannot getScom 0x3030008");
-            break;
-          }
-          if(data_buffer_64.getDoubleWord(0) == 0x0000001FFFFFFFFFull)
-          {
-            memon=1;
-          }
-        }
-
-
-        if(pervon || memon)
-        {
-          bool l_stop_mem_clks=true;
-          bool l_stop_nest_clks=true;
-          bool l_stop_dram_rfrsh_clks=true;
-          bool l_stop_tp_clks=false;
-          bool l_stop_vitl_clks=false;
-          FAPI_INF("Calling cen_stopclocks");
-          rc = cen_stopclocks(i_target_centaur, l_stop_mem_clks, l_stop_nest_clks, l_stop_dram_rfrsh_clks, l_stop_tp_clks, l_stop_vitl_clks );
-
-        } // clocks are on, so kill them
-      } // non functional centaurs
-      FAPI_INF("Ending mss_power_cleanup_centaur");
-    }
-    while(0);
-
-    if(rc) { FAPI_ERR("ERROR: Bad RC in mss_power_cleanup_centaur"); }
-    return rc;
-  } // end of mss_power_cleanup_centaur
-
-
-} // extern "C"
-
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H b/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H
deleted file mode 100644
index d93584ec2..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H
+++ /dev/null
@@ -1,100 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_power_cleanup/mss_power_cleanup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_power_cleanup.H,v 1.3 2014/02/19 13:41:35 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_power_cleanup.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_power_cleanup.H
-// *! DESCRIPTION : Header file for mss_eff_config.
-// *! OWNER NAME  : Mark Bellows      Email: bellows@us.ibm.com
-// *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.3   | bellows  |19-FEB-14| RAS Review Updates
-//   1.2   |bellows   |11-Nov-13| Gerrit Review Comments
-//   1.1   |bellows   |07-Nov-13| copied from mss_cnfg_cleanup.H version 1.2
-//------------------------------------------------------------------------------
-
-
-#ifndef mss_power_cleanup_H_
-#define mss_power_cleanup_H_
-
-//------------------------------------------------------------------------------
-// My Includes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_power_cleanup_FP_t)(const fapi::Target & i_target_centaur,
-                                                  const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1);
-typedef fapi::ReturnCode (*mss_power_cleanup_mba_FP_t)( const fapi::Target & i_target_mba);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// @brief mss_power_cleanup(): Clean up a centaur and also MBAs, also calls the mba cleanup under the covers
-//
-// @param const fapi::Target i_target_centaur: the centaur
-// @param const fapi::Target i_target_mba0: the mba0 
-// @param const fapi::Target i_target_mba1: the mba1
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_power_cleanup(const fapi::Target & i_target_centaur,
-                                                  const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1);
-//------------------------------------------------------------------------------
-// @brief mss_power_cleanup_mba(): Clean up a centaur and also MBAs
-//
-// @param const fapi::Target i_target_mba0: the mba0 
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_power_cleanup_mba(const fapi::Target & i_target_mba); // clean up an mba
-
-fapi::ReturnCode mss_power_cleanup_centaur(const fapi::Target & i_target_centaur);
-fapi::ReturnCode mss_power_cleanup_mba_part1(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba);
-fapi::ReturnCode mss_power_cleanup_mba_fence(const fapi::Target & i_target_centaur, const fapi::Target & i_target_mba0, const fapi::Target & i_target_mba1 );
-
-
-
-} // extern "C"
-
-#endif // mss_power_cleanup_H
-
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
deleted file mode 100644
index a98b58ddf..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
+++ /dev/null
@@ -1,662 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_thermal_init.C,v 1.20 2015/03/02 20:43:37 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_thermal_init
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Jacob Sloat       Email: jdsloat@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// applicable CQ component memory_screen
-//
-// DESCRIPTION:
-// The purpose of this procedure is to configure and start the OCC cache and Centaur thermal cache
-//
-// TODO:
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.20  | pardeik  |02-MAR-15| initialize l_dimm_ranks_array to zero
-//                              | use const variables in for loops instead of numbers
-//   1.18  | pardeik  |12-FEB-15| change ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP to
-//                              | a centaur target (was system)
-//   1.17  | pardeik  |19-NOV-14| Use MRW attribute for SC address map for ISDIMMs
-//   1.16  | pardeik  |06-FEB-14| removed string in trace statement
-//   1.15  | pardeik  |24-FEB-14| added support for ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE
-//   1.14  | pardeik  |12-FEB-14| changed CONFIG_INTERVAL_TIMER from 5 to 15 to 
-//   1.13  | pardeik  |30-JAN-14| workaround for SW243504 (enable sensors on master
-//                              |   i2c bus if ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE=ON)
-//   1.12  | pardeik  |06-JAN-14| enable writing of safemode IPL throttles
-//   1.11  | pardeik  |20-DEC-13| Only get sensor map attributes if a custom dimm
-//   1.10  | pardeik  |21-NOV-13| added support for dimm temperature sensor attributes
-//   1.9   | pardeik  |11-OCT-13| gerrit review updates to remove uneeded items
-//   1.8   | pardeik  |04-OCT-13| changes done from gerrit review
-//   1.7   | pardeik  |01-AUG-13| Functional corrections to procedure
-//                              | Updates for defect HW257484
-//                              | Use custom DIMM instead of dimm type attribute
-//                              | Added commented out throttle section at end to enable later
-//   1.6   | joabhend |28-NOV-12| Corrected procedure_name from char* to const char*
-//   1.5   | joabhend |16-NOV-12| Updated code to reflect review output
-//   1.4   | joabhend |02-NOV-12| Corrected scom call from SCAC_FIRMASK to SCAC_ADDRMAP
-//   1.3   | joabhend |10-OCT-12| Added section for emergency throttle disable, removed FIR bit 33 handling
-//   1.2   | gollub   |05-SEP-12| Calling mss_unmask_fetch_errors after mss_thermal_init_cloned
-//   1.1   | joabhend |30-APR-12| First Draft
-
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <mss_thermal_init.H>
-#include <fapi.H>
-#include <mss_unmask_errors.H>
-#include <cen_scom_addresses.H>
-
-extern "C" {
-
-   using namespace fapi;
-
-
-   // Procedures in this file
-   fapi::ReturnCode mss_thermal_init_cloned(const fapi::Target & i_target);
-   
-   
-//******************************************************************************
-//
-//******************************************************************************
-   
-fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
-{
-    // Target is centaur
-    
-    fapi::ReturnCode l_rc;
-    
-    l_rc = mss_thermal_init_cloned(i_target);
-    
-	// If mss_unmask_fetch_errors gets it's own bad rc,
-	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
-	// Else if mss_unmask_fetch_errors runs clean, 
-	// it will just return the passed in rc.
-	l_rc = mss_unmask_fetch_errors(i_target, l_rc);
-
-	return l_rc;
-}
-   
-
-//******************************************************************************
-//
-//******************************************************************************
-
-   fapi::ReturnCode mss_thermal_init_cloned(const fapi::Target & i_target)
-   {
-
-      fapi::ReturnCode l_rc;
-      uint32_t l_ecmd_rc = 0;
-
-      FAPI_INF("*** Running mss_thermal_init ***");
-
-      // Constant declaration
-      const uint8_t l_NUM_MBAS = 2;                                     // Number of MBAs per Centaur
-      const uint8_t l_NUM_PORTS = 2;					// Number of ports per MBA
-      const uint8_t l_NUM_DIMMS = 2;					// Number of dimms per MBA port
-
-      const uint64_t HANG_PULSE_0_REG = 0x00000000020f0020ULL;
-      const uint64_t THERM_MODE_REG = 0x000000000205000fULL;
-      const uint64_t CONTROL_REG = 0x0000000002050012ULL;
-
-      const uint64_t SCAC_FIRMASK = 0x00000000020115c3ULL;
-      const uint64_t SCAC_ACTMASK = 0x00000000020115d3ULL;
-      const uint64_t SCAC_ADDRMAP = 0x00000000020115cdULL;
-      const uint64_t SCAC_CONFIG = 0x00000000020115ceULL;
-      const uint64_t SCAC_ENABLE = 0x00000000020115ccULL;
-      const uint64_t SCAC_I2CMCTRL = 0x00000000020115d1ULL;
-      const uint64_t SCAC_PIBTARGET = 0x00000000020115d2ULL;
-      const uint64_t I2CM_RESET = 0x00000000000A0001ULL;
-
-      const uint64_t MBS_EMER_THROT = 0x000000000201142dULL;
-      const uint64_t MBS_FIR_REG = 0x0000000002011400ULL;
-
-      const uint32_t PRIMARY_I2C_BASE_ADDR = 0x000A0000;
-      const uint32_t SPARE_I2C_BASE_ADDR = 0x000A0000;
-      const uint32_t I2C_SETUP_UPPER_HALF = 0xD2314049;
-      const uint32_t I2C_SETUP_LOWER_HALF = 0x05000000;
-      const uint32_t ACT_MASK_UPPER_HALF = 0x00018000;
-      const uint32_t ACT_MASK_LOWER_HALF = 0x00000000;
-// OCC polls cacheline every 2 ms (could vary from this, as seen on scope)
-// For I2C bus at 50kHz (9.6 ms max to read 8 sensors), use interval of 15 for margin and to prevent stall errors when 8 sensors are enabled to be read
-      const uint32_t CONFIG_INTERVAL_TIMER = 15;
-      const uint32_t CONFIG_STALL_TIMER = 128;
-      const uint8_t I2C_BUS_ENCODE_PRIMARY = 0;
-      const uint8_t I2C_BUS_ENCODE_SECONDARY = 8;
-      const uint8_t MAX_NUM_DIMM_SENSORS = 8;
-      const uint8_t MAX_I2C_BUSSES = 2;
-
-      // Variable declaration
-      uint8_t l_dimm_ranks_array[l_NUM_MBAS][l_NUM_PORTS][l_NUM_DIMMS];	// Number of ranks for each configured DIMM in each MBA
-      uint8_t l_custom_dimm[l_NUM_MBAS];				// Custom DIMM
-      uint8_t l_mba_pos = 0;						// Current MBA for populating rank array
-      ecmdDataBufferBase l_data(64);
-      ecmdDataBufferBase l_data_scac_enable(64);
-      ecmdDataBufferBase l_data_scac_addrmap(64);
-      uint8_t l_cdimm_sensor_map;
-      uint8_t l_cdimm_sensor_map_primary;
-      uint8_t l_cdimm_sensor_map_secondary;
-      uint8_t l_cdimm_number_dimm_temp_sensors;
-      uint8_t l_i2c_address_map;
-      uint8_t l_data_scac_addrmap_offset;
-      uint8_t l_i2c_bus_encode;
-      uint8_t l_sensor_map_mask;
-      uint8_t l_master_i2c_temp_sensor_enable;
-      uint8_t l_spare_i2c_temp_sensor_enable;
-      uint32_t l_dimm_sensor_cache_addr_map = 0;
-
-//********************************************
-// Centaur internal temperature polling setup 
-//********************************************
-// setup hang pulse
-      l_rc = fapiGetScom(i_target, HANG_PULSE_0_REG, l_data);
-      if (l_rc) return l_rc;
-      l_ecmd_rc |= l_data.setBit(1);
-      l_ecmd_rc |= l_data.setBit(2);
-      if(l_ecmd_rc) {
-	  l_rc.setEcmdError(l_ecmd_rc);
-	  return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, HANG_PULSE_0_REG, l_data);
-      if (l_rc) return l_rc;
-// setup DTS enables
-      l_rc = fapiGetScom(i_target, THERM_MODE_REG, l_data);
-      if (l_rc) return l_rc;
-      l_ecmd_rc |= l_data.setBit(20);
-      l_ecmd_rc |= l_data.setBit(21);
-      if(l_ecmd_rc) {
-	  l_rc.setEcmdError(l_ecmd_rc);
-	  return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, THERM_MODE_REG, l_data);
-      if (l_rc) return l_rc;
-// setup pulse count and enable DTS sampling
-      l_rc = fapiGetScom(i_target, THERM_MODE_REG, l_data);
-      if (l_rc) return l_rc;
-      l_ecmd_rc |= l_data.setBit(5);
-      l_ecmd_rc |= l_data.setBit(6);
-      l_ecmd_rc |= l_data.setBit(7);
-      l_ecmd_rc |= l_data.setBit(8);
-      l_ecmd_rc |= l_data.setBit(9);
-      if(l_ecmd_rc) {
-	  l_rc.setEcmdError(l_ecmd_rc);
-	  return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, THERM_MODE_REG, l_data);
-      if (l_rc) return l_rc;
-// issue a reset
-      l_ecmd_rc |= l_data.flushTo0();
-      l_ecmd_rc |= l_data.setBit(0);
-      l_ecmd_rc |= l_data.setBit(1);
-      l_ecmd_rc |= l_data.setBit(2);
-      l_ecmd_rc |= l_data.setBit(3);
-      l_ecmd_rc |= l_data.setBit(4);
-      if(l_ecmd_rc) {
-	  l_rc.setEcmdError(l_ecmd_rc);
-	  return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, CONTROL_REG, l_data);
-      if (l_rc) return l_rc;
-// Centaur internal temperature polling setup complete
-
-
-      // Get input attributes from MBAs
-      std::vector<fapi::Target> l_target_mba_array;
-      l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_target_mba_array);
-      if (l_rc) return l_rc;
-
-      // need to clear out the array since it could be sparsely filled
-      //  in the ISDIMM case
-      for( size_t i = 0;
-           i < (sizeof(l_custom_dimm)/sizeof(l_custom_dimm[0]));
-           i++ )
-      {
-          l_custom_dimm[i] = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO;
-      }
-
-      // zero out the l_dimm_ranks_array so it is initialized for later use if there is a deconfigured MBA
-      for (uint8_t i = 0; i < l_NUM_MBAS; i++)
-      {
-	  for (uint8_t j = 0; j < l_NUM_PORTS; j++)
-	  {
-	      for (uint8_t k = 0; k < l_NUM_DIMMS; k++)
-	      {
-		  l_dimm_ranks_array[i][j][k]=0;
-	      }
-	  }
-
-      }
-
-      for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){
-         l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_target_mba_array[mba_index], l_mba_pos);
-	 if (l_rc) return l_rc;
-	 FAPI_INF("MBA_POS: %d", l_mba_pos);
-
-	 l_rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &l_target_mba_array[mba_index], l_dimm_ranks_array[l_mba_pos]);
-	 if (l_rc) return l_rc;
-	 FAPI_INF("EFF_NUM_RANKS: %d:%d:%d:%d", l_dimm_ranks_array[l_mba_pos][0][0], l_dimm_ranks_array[l_mba_pos][0][1], l_dimm_ranks_array[l_mba_pos][1][0], l_dimm_ranks_array[l_mba_pos][1][1]);
-
-	 l_rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &l_target_mba_array[mba_index], l_custom_dimm[l_mba_pos]);
-	 if (l_rc) return l_rc;
-	 FAPI_INF("ATTR_EFF_CUSTOM_DIMM: %d", l_custom_dimm[l_mba_pos]);
-      }
-
-      // Get attributes for dimm temperature sensor mapping for only a custom dimm so we don't get an error
-      // Get attritute for custom dimms for enablement on the master i2c bus
-      if ((l_custom_dimm[0] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_custom_dimm[1] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES))
-      {
-	  l_rc = FAPI_ATTR_GET(ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY, &i_target, l_cdimm_sensor_map_primary);
-	  if (l_rc) return l_rc;
-	  l_rc = FAPI_ATTR_GET(ATTR_VPD_CDIMM_SENSOR_MAP_SECONDARY, &i_target, l_cdimm_sensor_map_secondary);
-	  if (l_rc) return l_rc;
-	  l_rc = FAPI_ATTR_GET(ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE, NULL, l_master_i2c_temp_sensor_enable);
-	  if (l_rc) return l_rc;
-	  l_rc = FAPI_ATTR_GET(ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE, NULL, l_spare_i2c_temp_sensor_enable);
-	  if (l_rc) return l_rc;
-      }
-      else
-      {
-	  // sensor cache address map for non custom dimm temperature sensors (which i2c bus and i2c address they are)
-	  l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, &i_target, l_dimm_sensor_cache_addr_map);
-	  if (l_rc) return l_rc;
-      }
-
-      // Configure Centaur Thermal Cache
-
-      // ---------------------------------
-      // Clear the master enable bit
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_CONFIG, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.clearBit(0); //Master enable is bit 0
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-         return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, SCAC_CONFIG, l_data);
-      if (l_rc) return l_rc;
-
-      // ---------------------------------
-      // Mask FIR bit 33 
-      // Sets if any sensor cache addresses are written while the master enable is set
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_FIRMASK, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.setBit(33);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-         return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, SCAC_FIRMASK, l_data);
-      if (l_rc) return l_rc;
-
-      // ---------------------------------
-      // Program PibTarget Register
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_PIBTARGET, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.insert(PRIMARY_I2C_BASE_ADDR, 0, 32, 0);
-      l_ecmd_rc |= l_data.insert(SPARE_I2C_BASE_ADDR, 32, 32, 0);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, SCAC_PIBTARGET, l_data);
-      if (l_rc) return l_rc;
-
-      // ---------------------------------
-      // Program I2CMCtrl Register
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_I2CMCTRL, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.insert(I2C_SETUP_UPPER_HALF, 0, 32, 0);
-      l_ecmd_rc |= l_data.insert(I2C_SETUP_LOWER_HALF, 32, 32, 0);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, SCAC_I2CMCTRL, l_data);
-      if (l_rc) return l_rc;
-
-
-      // ---------------------------------
-      // Program Action Mask Register
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_ACTMASK, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.insert(ACT_MASK_UPPER_HALF, 0, 32, 0);
-      l_ecmd_rc |= l_data.insert(ACT_MASK_LOWER_HALF, 32, 32, 0);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-         return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, SCAC_ACTMASK, l_data);
-      if (l_rc) return l_rc;
-
-
-      // ---------------------------------
-      // Program SensorCacheConfiguration Register
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_CONFIG, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.setBit(1);   //Sync to OCC_Read signal
-      l_ecmd_rc |= l_data.insert(CONFIG_INTERVAL_TIMER, 11, 5, 32-5);
-      l_ecmd_rc |= l_data.insert(CONFIG_STALL_TIMER, 16, 8, 32-8);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-      l_rc = fapiPutScom(i_target, SCAC_CONFIG, l_data);
-      if (l_rc) return l_rc;
-
-      // --------------------------------------------------------
-      // Program SensorCacheEnable and SensorAddressMap Registers
-      // --------------------------------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_ENABLE, l_data_scac_enable);
-      if (l_rc) return l_rc;
-
-      l_rc = fapiGetScom(i_target, SCAC_ADDRMAP, l_data_scac_addrmap);
-      if (l_rc) return l_rc;
-
-      if ((l_custom_dimm[0] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) || (l_custom_dimm[1] == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){
-
-	  l_cdimm_number_dimm_temp_sensors = 0;
-	  // cycle through both primary and secondary i2c busses, determine i2c address and enable bits
-	  for (uint8_t k = 0; k < MAX_I2C_BUSSES; k++)
-	  {
-	      for (uint8_t i = 0; i < MAX_NUM_DIMM_SENSORS; i++)
-	      {
-		  if (k == 0)
-		  {
-		      l_i2c_bus_encode = I2C_BUS_ENCODE_PRIMARY;
-		      l_cdimm_sensor_map = l_cdimm_sensor_map_primary;
-		  }
-		  else
-		  {
-		      l_i2c_bus_encode = I2C_BUS_ENCODE_SECONDARY;
-		      l_cdimm_sensor_map = l_cdimm_sensor_map_secondary;
-		  }
-		  switch (i)
-		  {
-		      case 0:
-			  l_sensor_map_mask = 0x01;
-			  break;
-		      case 1:
-			  l_sensor_map_mask = 0x02;
-			  break;
-		      case 2:
-			  l_sensor_map_mask = 0x04;
-			  break;
-		      case 3:
-			  l_sensor_map_mask = 0x08;
-			  break;
-		      case 4:
-			  l_sensor_map_mask = 0x10;
-			  break;
-		      case 5:
-			  l_sensor_map_mask = 0x20;
-			  break;
-		      case 6:
-			  l_sensor_map_mask = 0x40;
-			  break;
-		      case 7:
-			  l_sensor_map_mask = 0x80;
-			  break;
-		      default:
-			  l_sensor_map_mask = 0x00;		
-		  }
-		  if ((l_cdimm_sensor_map & l_sensor_map_mask) != 0)
-		  {
-		      // Only enable the sensor for custom dimms based on the attributes
-		      if (
-			  (
-			   (k==0)
-			   &&
-			   (l_master_i2c_temp_sensor_enable ==
-			    ENUM_ATTR_MRW_CDIMM_MASTER_I2C_TEMP_SENSOR_ENABLE_OFF)
-			   )
-			  ||
-			  (
-			   (k==1)
-			   &&
-			   (l_spare_i2c_temp_sensor_enable ==
-			    ENUM_ATTR_MRW_CDIMM_SPARE_I2C_TEMP_SENSOR_ENABLE_OFF)
-			   )
-			  )
-		      {
-			  // do nothing here - do not enable the sensor
-		      }
-		      else	
-		      {	
-			  l_ecmd_rc |= l_data_scac_enable.setBit(l_cdimm_number_dimm_temp_sensors);
-		      }
-		      l_i2c_address_map = i + l_i2c_bus_encode;
-		      l_data_scac_addrmap_offset = l_cdimm_number_dimm_temp_sensors * 4;
-		      l_ecmd_rc |= l_data_scac_addrmap.insert(l_i2c_address_map, l_data_scac_addrmap_offset , 4, 4);
-		      l_cdimm_number_dimm_temp_sensors++;
-		      if(l_ecmd_rc) {
-			  l_rc.setEcmdError(l_ecmd_rc);
-			  return l_rc;
-		      }
-		      if (l_cdimm_number_dimm_temp_sensors > MAX_NUM_DIMM_SENSORS)
-		      {
-			  FAPI_ERR("Invalid number of dimm temperature sensors specified in the CDIMM VPD MW keyword");
-			  const fapi::Target & MEM_CHIP = i_target;
-			  uint8_t FFDC_DATA_1 = l_cdimm_sensor_map_primary;
-			  uint8_t FFDC_DATA_2 = l_cdimm_sensor_map_secondary;
-			  FAPI_SET_HWP_ERROR(l_rc, RC_MSS_CDIMM_INVALID_NUMBER_SENSORS);
-			  return l_rc;
-		      }
-		  }
-	      }
-	  }
-      }
-      else{
-         // Iterate through the num_ranks array to determine what DIMMs are plugged
-	 // Enable sensor monitoring for each plugged DIMM
-         uint32_t l_iterator = 0;
-         for (uint32_t i = 0; i < l_NUM_MBAS; i++){
-	    if (l_dimm_ranks_array[i][0][0] != 0){
-	       l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator);
-	    }
-	    l_iterator++;
-	    if (l_dimm_ranks_array[i][0][1] != 0){
-	       l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator);
-	    }
-	    l_iterator++;
-	    if (l_dimm_ranks_array[i][1][0] != 0){
-	       l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator);
-	    }
-	    l_iterator++;
-	    if (l_dimm_ranks_array[i][1][1] != 0){
-	       l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator);
-	    }
-	    l_iterator++;
-	 }
-	 l_ecmd_rc |= l_data_scac_addrmap.insert(l_dimm_sensor_cache_addr_map, 0, 32, 0);
-	 if(l_ecmd_rc) {
-	     l_rc.setEcmdError(l_ecmd_rc);
-	     return l_rc;
-	 }
-
-      }
-
-
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, SCAC_ENABLE, l_data_scac_enable);
-      if (l_rc) return l_rc;
-
-      l_rc = fapiPutScom(i_target, SCAC_ADDRMAP, l_data_scac_addrmap);
-      if (l_rc) return l_rc;
-
-      //---------------------------------
-      // Reset the I2CM
-      //---------------------------------
-
-      ecmdDataBufferBase l_reset(64);
-      l_ecmd_rc |= l_reset.setBit(0);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-         return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, I2CM_RESET, l_reset);
-      if (l_rc) return l_rc;
-
-      // ---------------------------------
-      // Set the master enable bit
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, SCAC_CONFIG, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.setBit(0);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, SCAC_CONFIG, l_data);
-      if (l_rc) return l_rc;
-
-      // Configure Centaur Thermal Cache COMPLETED
-
-
-
-      // Disable Emergency Throttles
-
-      // ---------------------------------
-      // Clear the emergency throttle FIR bit (MBS FIR 21)
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, MBS_FIR_REG, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.clearBit(21);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, MBS_FIR_REG, l_data);
-      if (l_rc) return l_rc;
-
-
-      // ---------------------------------
-      // Reset emergency throttle in progress bit (EMER THROT 0)
-      // ---------------------------------
-
-      l_rc = fapiGetScom(i_target, MBS_EMER_THROT, l_data);
-      if (l_rc) return l_rc;
-
-      l_ecmd_rc |= l_data.clearBit(0);
-      if(l_ecmd_rc) {
-         l_rc.setEcmdError(l_ecmd_rc);
-	 return l_rc;
-      }
-
-      l_rc = fapiPutScom(i_target, MBS_EMER_THROT, l_data);
-      if (l_rc) return l_rc;
-
-      // Disable Emergency Throttles COMPLETED
-
-
-// Write the IPL Safe Mode Throttles
-// For centaur DD2 and above since OCC only writes runtime throttles for this
-
-      uint8_t l_enable_safemode_throttle = 0;
-      l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_SAFEMODE_THROTTLE, &i_target, l_enable_safemode_throttle);
-      if (l_rc) return l_rc;
-
-      if (l_enable_safemode_throttle)
-      {
-	  uint32_t l_safemode_throttle_n_per_mba;
-	  uint32_t l_safemode_throttle_n_per_chip;
-	  uint32_t l_throttle_d;
-
-	  l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_MBA, NULL, l_safemode_throttle_n_per_mba);
-	  if (l_rc) return l_rc;
-	  l_rc = FAPI_ATTR_GET(ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, NULL, l_safemode_throttle_n_per_chip);
-	  if (l_rc) return l_rc;
-	  l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_THROTTLE_DENOMINATOR, NULL, l_throttle_d);
-	  if (l_rc) return l_rc;
-// write the N/M throttle control register
-	  for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){
-	      l_rc = fapiGetScom(l_target_mba_array[mba_index], MBA01_MBA_FARB3Q_0x03010416, l_data);
-	      if (l_rc) return l_rc;
-	      l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_n_per_mba, 0, 15);
-	      l_ecmd_rc |= l_data.insertFromRight(l_safemode_throttle_n_per_chip, 15, 16);
-	      l_ecmd_rc |= l_data.insertFromRight(l_throttle_d, 31, 14);
-	      if(l_ecmd_rc) {
-		  l_rc.setEcmdError(l_ecmd_rc);
-		  return l_rc;
-	      }
-	      l_rc = fapiPutScom(l_target_mba_array[mba_index], MBA01_MBA_FARB3Q_0x03010416, l_data);
-	      if (l_rc) return l_rc;
-	  }
-      }
-
-      FAPI_INF("*** mss_thermal_init COMPLETE ***");
-      return l_rc;
-
-   } //end mss_thermal_init
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H
deleted file mode 100644
index 191fe47af..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H
+++ /dev/null
@@ -1,88 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_thermal_init.H,v 1.1 2012/09/05 18:11:58 joabhend Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_throttle_to_power.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
-// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_thermal_init.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.1   | joabhend |30-APR-12| First Draft.
-
-
-
-#ifndef MSS_THERMAL_INIT_H_
-#define MSS_THERMAL_INIT_H_
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-//----------------------------------------------------------------------
-//  Defines
-//----------------------------------------------------------------------
-
-//----------------------------------------------------------------------
-//  ENUMs
-//----------------------------------------------------------------------
-
-//----------------------------------------------------------------------
-//  Data Types
-//----------------------------------------------------------------------
-
-typedef fapi::ReturnCode (*mss_thermal_init_FP_t)(const fapi::Target & i_target);
-
-extern "C"
-{
-
-/**
- * @brief mss_thermal_init procedure. Configure and start the OCC cache and Centaur thermal cache
- *
- * @param[in]  i_target  Reference to centaur target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target);
-
-} // extern "C"
-
-#endif // MSS_THERMAL_INIT_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C b/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C
deleted file mode 100644
index 786d21a76..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C
+++ /dev/null
@@ -1,71 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_exit_cache_contained.C,v 1.3 2014/02/10 04:49:54 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_exit_cache_contained.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_exit_cache_contained.C
-// *! DESCRIPTION : 
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_exit_cache_contained.H>
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// HWP entry point
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_exit_cache_contained()
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    // mark HWP entry
-    FAPI_IMP("proc_exit_cache_contained : Entering ...");
-
-
-    // log function exit
-    FAPI_IMP("proc_exit_cache_contained : Exiting ...");
-    return rc;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H b/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H
deleted file mode 100644
index 614c8a7b3..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H
+++ /dev/null
@@ -1,70 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_exit_cache_contained/proc_exit_cache_contained.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_exit_cache_contained.H,v 1.2 2014/02/10 04:49:53 stillgs Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_exit_cache_contained.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_exit_cache_contained.H
-// *! DESCRIPTION : 
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_EXIT_CACHE_CONTAINED_H_
-#define _PROC_EXIT_CACHE_CONTAINED_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_exit_cache_contained_FP_t)();
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-fapi::ReturnCode proc_exit_cache_contained();
-
-} // extern "C"
-
-#endif // _PROC_EXIT_CACHE_CONTAINED_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
deleted file mode 100644
index f189f668e..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C
+++ /dev/null
@@ -1,329 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_config.C,v 1.11 2015/06/29 01:47:49 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_pcie_config.C
-// *! DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapiHwpExecInitFile.H>
-#include <proc_pcie_config.H>
-#include <proc_a_x_pci_dmi_pll_setup.H>
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: apply PBCQ/AIB customization via SCOM initfile
-// parameters: i_target => processor chip target
-// returns: FAPI_RC_SUCCESS if initfile evaluation is successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_pcie_config_pbcq(
-    const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    std::vector<fapi::Target> targets;
-
-    // mark function entry
-    FAPI_INF("proc_pcie_config_pbcq: Start");
-
-    do
-    {
-        // execute Phase2 SCOM initfile
-        targets.push_back(i_target);
-        FAPI_INF("proc_pcie_config_pbcq: Executing %s on %s",
-                 PROC_PCIE_CONFIG_PHASE2_IF, i_target.toEcmdString());
-        FAPI_EXEC_HWP(
-            rc,
-            fapiHwpExecInitFile,
-            targets,
-            PROC_PCIE_CONFIG_PHASE2_IF);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq: Error from fapiHwpExecInitfile executing %s on %s",
-                     PROC_PCIE_CONFIG_PHASE2_IF,
-                     i_target.toEcmdString());
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_INF("proc_pcie_config_pbcq: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: initialize PBCQ FIRs
-//             clear FIR/WOF
-//             initialize FIR action settings
-//             reset FIR masks
-// parameters: i_target  => processor chip target
-//             i_num_phb => number of PHB units
-// returns: FAPI_RC_SUCCESS if all actions are successful,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_pcie_config_pbcq_fir(
-    const fapi::Target & i_target,
-    uint8_t i_num_phb)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    ecmdDataBufferBase data(64);
-
-    // mark function entry
-    FAPI_INF("proc_pcie_config_pbcq_fir: Start");
-
-    // loop over all PHBs
-    for (size_t i = 0; i < i_num_phb; i++)
-    {
-        // clear FIR
-        rc_ecmd |= data.flushTo0();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR clear data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target,
-                         PROC_PCIE_CONFIG_PCIE_NEST_FIR[i],
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_0x%08X)",
-                     i, PROC_PCIE_CONFIG_PCIE_NEST_FIR[i]);
-            break;
-        }
-
-        // clear FIR WOF
-        rc = fapiPutScom(i_target,
-                         PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i],
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_WOF_0x%08X)",
-                     i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[i]);
-            break;
-        }
-
-        // set action0
-        rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action0 register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutScom(i_target,
-                         PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i],
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION0_0x%08X)",
-                     i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[i]);
-            break;
-        }
-
-        // set action1
-        rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action1 register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutScom(i_target,
-                         PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i],
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION1_0x%08X)",
-                     i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[i]);
-            break;
-        }
-
-        // set action2
-        fapi::ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT_Type action2_present = 0;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT, &i_target, action2_present);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: fapiGetAttribute of ATTR_CHIP_EC_FEATURE_PCI_NEST_FIR_ACTION2_PRESENT failed");
-            break;
-        }
-        if (action2_present)
-        {
-            rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2_VAL);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Action2 register data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            rc = fapiPutScom(i_target,
-                             PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[i],
-                             data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_ACTION2_0x%08X)",
-                         i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[i]);
-                break;
-            }
-        }
-
-        // set mask
-        rc_ecmd |= data.setDoubleWord(0, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error 0x%x setting up PCIE Nest FIR Mask register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutScom(i_target,
-                         PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i],
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config_pbcq_fir: Error from fapiPutScom (PCIE%zd_FIR_MASK_0x%08X)",
-                     i, PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[i]);
-            break;
-        }
-    }
-
-    // mark function exit
-    FAPI_INF("proc_pcie_config_pbcq_fir: End");
-    return rc;
-}
-
-
-// HWP entry point, comments in header
-fapi::ReturnCode proc_pcie_config(
-    const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    uint8_t pcie_enabled;
-    uint8_t num_phb;
-
-    // mark HWP entry
-    FAPI_INF("proc_pcie_config: Start");
-
-    do
-    {
-        // check for supported target type
-        if (i_target.getType() != fapi::TARGET_TYPE_PROC_CHIP)
-        {
-            FAPI_ERR("proc_pcie_config: Unsupported target type");
-            const fapi::Target & TARGET = i_target;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_PCIE_CONFIG_INVALID_TARGET);
-            break;
-        }
-
-        // query PCIE partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
-                           &i_target,
-                           pcie_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_pcie_config: Error querying ATTR_PROC_PCIE_ENABLE");
-            break;
-        }
-
-        // initialize PBCQ/AIB, configure PBCQ FIRs (only if partial good
-        // atttribute is set)
-        if (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
-        {
-            // determine PHB configuration
-            rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
-                               &i_target,
-                               num_phb);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_pcie_config: Error from FAPI_ATTR_GET (ATTR_PROC_PCIE_NUM_PHB)");
-                break;
-            }
-
-            rc = proc_pcie_config_pbcq(i_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq");
-                break;
-            }
-
-            rc = proc_pcie_config_pbcq_fir(i_target, num_phb);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_pcie_config: Error from proc_pcie_config_pbcq_fir");
-                break;
-            }
-
-            rc = proc_a_x_pci_dmi_pll_setup_unmask_lock(
-                i_target,
-                PCIE_CHIPLET_0x09000000);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_pcie_config: Error from proc_a_x_pci_dmi_pll_setup_unmask_lock");
-                break;
-            }
-        }
-        else
-        {
-            FAPI_DBG("proc_pcie_config: Skipping initialization (partial good)");
-        }
-
-    } while(0);
-
-    // mark HWP exit
-    FAPI_INF("proc_pcie_config: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H b/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
deleted file mode 100644
index 63339f41d..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H
+++ /dev/null
@@ -1,142 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_pcie_config/proc_pcie_config.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_config.H,v 1.7 2015/07/01 21:15:04 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_config.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_pcie_config.H
-// *! DESCRIPTION : Perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22) (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!   Configure PBCQ/AIB registers
-// *!   Clear PBCQ FIRs, setup for runtime
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef PROC_PCIE_CONFIG_H_
-#define PROC_PCIE_CONFIG_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// SCOM initfile to execute
-const char * const PROC_PCIE_CONFIG_PHASE2_IF = "p8.pe.phase2.scom.if";
-
-// PCIe physical constants
-const uint8_t PROC_PCIE_CONFIG_NUM_PHB = 4;
-
-const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR[PROC_PCIE_CONFIG_NUM_PHB] =
-{
-    PCIE0_FIR_0x02012000,
-    PCIE1_FIR_0x02012400,
-    PCIE2_FIR_0x02012800,
-    PCIE3_FIR_0x02012C00
-};
-
-const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_WOF[PROC_PCIE_CONFIG_NUM_PHB] =
-{
-    PCIE0_FIR_WOF_0x02012008,
-    PCIE1_FIR_WOF_0x02012408,
-    PCIE2_FIR_WOF_0x02012808,
-    PCIE3_FIR_WOF_0x02012C08
-};
-
-const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0[PROC_PCIE_CONFIG_NUM_PHB] =
-{
-    PCIE0_FIR_ACTION0_0x02012006,
-    PCIE1_FIR_ACTION0_0x02012406,
-    PCIE2_FIR_ACTION0_0x02012806,
-    PCIE3_FIR_ACTION0_0x02012C06
-};
-
-const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1[PROC_PCIE_CONFIG_NUM_PHB] =
-{
-    PCIE0_FIR_ACTION1_0x02012007,
-    PCIE1_FIR_ACTION1_0x02012407,
-    PCIE2_FIR_ACTION1_0x02012807,
-    PCIE3_FIR_ACTION1_0x02012C07
-};
-
-const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2[PROC_PCIE_CONFIG_NUM_PHB] =
-{
-    PCIE0_FIR_ACTION2_0x02012020,
-    PCIE1_FIR_ACTION2_0x02012420,
-    PCIE2_FIR_ACTION2_0x02012820,
-    PCIE3_FIR_ACTION2_0x02012C20
-};
-
-const uint32_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK[PROC_PCIE_CONFIG_NUM_PHB] =
-{
-    PCIE0_FIR_MASK_0x02012003,
-    PCIE1_FIR_MASK_0x02012403,
-    PCIE2_FIR_MASK_0x02012803,
-    PCIE3_FIR_MASK_0x02012C03
-};
-
-const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION0_VAL = 0x5B0F819000000000ULL;
-const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION1_VAL = 0x7F0F819000000000ULL;
-const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_ACTION2_VAL = 0xEFF07E0800000000ULL;
-const uint64_t PROC_PCIE_CONFIG_PCIE_NEST_FIR_MASK_VAL = 0x0030006E00000000ULL;
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_pcie_config_FP_t)(const fapi::Target & i_target);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: perform PCIe PBCQ/AIB Inits (Phase 2, Steps 9-22)
-// parameters: i_target => processor chip target
-// returns: FAPI_RC_SUCCESS if all programming is successful,
-//          RC_PROC_PCIE_CONFIG_INVALID_TARGET if invalid target is supplied,
-//          else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_pcie_config(const fapi::Target & i_target);
-
-
-} // extern "C"
-
-#endif // PROC_PCIE_CONFIG_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
deleted file mode 100644
index ecf7279fe..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C
+++ /dev/null
@@ -1,788 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_setup_bars.C,v 1.45 2015/04/24 06:25:04 gpaulraj Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *!
-// *! TITLE       : mss_setup_bars.C
-// *! DESCRIPTION : Program MCS base address registers (BARs) (FAPI)
-// *!
-// *! OWNER NAME  : Girisankar Paulraj      Email: gpaulraj@in.ibm.com
-// *! OWNER NAME  : Mark Bellows            Email: bellows@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.45   | gpaulraj | 04/24/15| fix for SW304630
-//  1.43   | gpaulraj | 03/19/15| fix SW296125 - modified k as k = 0
-//  1.42   | gpaulraj | 05/21/14| fixed on 1 MCS mirror BAR EN  issue -SW261358
-//  1.40   | gpaulraj | 05/06/14| fixed on mirror configuration issue
-//  1.39   | gpaulraj | 04/08/14| 5/5 FW review feedback - gerrit process - SW251227
-//  1.33   |          | 03/09/14| RAS review
-//  1.32   | gpaulraj | 08/16/13| fixed code
-//  1.31   | gpaulraj | 08/13/13| fix HW259884 Mirror BAR Scom Parity Error
-//  1.30   | gpaulraj | 08/13/13| added fix HW259884 Mirror BAR Scom Parity Error
-//  1.29   | gpaulraj | 08/12/13| fixed mirror BAR issues
-//  1.27   | jmcgill  | 05/21/13| address FW review issues
-//  1.26   | jmcgill  | 04/22/13| rewrite to line up with attribute changes
-//  1.23   | bellows  | 12/04/12| more updates
-//  1.22   | gpaulraj | 10/03/12| review updates
-//  1.21   | gpaulraj | 10/02/12| review updates
-//  1.19   | bellows  | 09/25/12| review updates
-//  1.18   | bellows  | 09/06/12| updates suggested by Van
-//  1.17   | bellows  | 08/31/12| use the final 32bit attribute
-//  1.16   | bellows  | 08/29/12| remove compile error, use 32bit group info
-//         |          |         | as a temporary fix
-//  1.10   | bellows  | 07/16/12| added in Id tag
-//  1.4    | bellows  | 06-05-12| Updates to Match First Configuration, work for
-//         |          |         | P8 and Murano
-//  1.3    | gpaulraj | 05-22-12| 2MCS/group supported for 128GB CDIMM
-//  1.2    | gpaulraj | 05-07-12| 256 group configuration in
-//  1.1    | gpaulraj | 03-19-12| First drop for centaur
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-
-#include <mss_setup_bars.H>
-
-
-//------------------------------------------------------------------------------
-//  Function definitions
-//------------------------------------------------------------------------------
-
-extern "C" {
-
-
-const int SETUP_BARS_MBA_SIZE_MCS=8;
-const int SETUP_BARS_MBA_SIZE_PORT=2;
-struct MssSetupBarsSizeInfo{
-   uint8_t MBA_size[SETUP_BARS_MBA_SIZE_MCS][SETUP_BARS_MBA_SIZE_PORT]; // mcs, mba pairs, port, dimm
-   uint32_t MCS_size[SETUP_BARS_MBA_SIZE_MCS];
-};
-
-//------------------------------------------------------------------------------
-// function: write non-mirrored BAR registers (MCFGP/MCFGPA) for a single MCS
-// parameters: i_mcs_target      => MCS chiplet target
-//             i_pri_valid       => true if MCS primary non-mirrored BAR
-//                                  should be marked valid
-//             i_group_member_id => group member ID (only valid if
-//                                  i_pri_valid=true)
-//             i_group_data      => MSS_MCS_GROUP_32 attribute data
-//                                  for member group (only valid if
-//                                  i_pri_valid=true)
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_setup_bars_init_nm_bars(
-    const fapi::Target& i_mcs_target,
-    bool i_pri_valid,
-    uint32_t i_group_member_id,
-    uint32_t i_group_data[])
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    ecmdDataBufferBase MCFGP(64);
-    ecmdDataBufferBase MCFGPA(64);
-
-    // Defect HW259884 (AddNote by retter) P8 Lab Brazos: Mirror BAR Scom Parity Error - workaround
-    ecmdDataBufferBase MCIFIR(64);
-    ecmdDataBufferBase MCIFIRMASK(64);
-    ecmdDataBufferBase MCSMODE4(64);
-
-    do
-    {
-        rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-        // Mask MCIFIR bit 25
-        rc_ecmd |= MCIFIRMASK.setBit(25);
-        if (rc_ecmd)
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCIFIRMASK data buffer",
-                         rc_ecmd);
-             rc.setEcmdError(rc_ecmd);
-             break;
-        }
-        rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-
-        // establish base content for MCFGP register
-        rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_RCMD0_BIT);
-        rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_RCMD1_BIT);
-        rc_ecmd |= MCFGP.setBit(MCFGP_RSVD_1_BIT);
-        rc_ecmd |= MCFGP.setBit(MCFGP_ENABLE_FASTPATH_BIT);
-
-        // check buffer manipulation return codes
-        if (rc_ecmd)
-        {
-            FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGP base data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        if (i_pri_valid)
-        {
-            // MCFGPQ_VALID
-            rc_ecmd |= MCFGP.setBit(MCFGP_VALID_BIT);
-            // MCFGPQ_MCS_UNITS_PER_GROUP
-            rc_ecmd |= MCFGP.insertFromRight(
-                i_group_data[MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX] / 2,
-                MCFGP_MCS_UNITS_PER_GROUP_START_BIT,
-                (MCFGP_MCS_UNITS_PER_GROUP_END_BIT-
-                 MCFGP_MCS_UNITS_PER_GROUP_START_BIT)+1);
-            // MCFGPQ_GROUP_MEMBER_IDENTIFICATION
-            rc_ecmd |= MCFGP.insertFromRight(
-                i_group_member_id,
-                MCFGP_GROUP_MEMBER_ID_START_BIT,
-                (MCFGP_GROUP_MEMBER_ID_END_BIT-
-                 MCFGP_GROUP_MEMBER_ID_START_BIT)+1);
-            // MCFGPQ_GROUP_SIZE
-            rc_ecmd |= MCFGP.insertFromRight(
-                (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/4)-1,
-                MCFGP_GROUP_SIZE_START_BIT,
-                (MCFGP_GROUP_SIZE_END_BIT-
-                 MCFGP_GROUP_SIZE_START_BIT)+1);
-
-            // MCFGPQ_BASE_ADDRESS_OF_GROUP
-            rc_ecmd |= MCFGP.insertFromRight(
-                i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] >> 2,
-                MCFGP_BASE_ADDRESS_START_BIT,
-                (MCFGP_BASE_ADDRESS_END_BIT-
-                 MCFGP_BASE_ADDRESS_START_BIT)+1);
-
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGP data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            bool alt_valid = i_group_data[MSS_MCS_GROUP_32_ALT_VALID_INDEX];
-            if (alt_valid)
-            {
-                if (i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] !=
-                    (i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] +
-                     (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/2)))
-                {
-                    FAPI_ERR("mss_setup_bars_init_nm_bars: Invalid non-mirrored alternate BAR configuration");
-                    const uint32_t & ALT_BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX];
-                    const uint32_t & BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_BASE_INDEX];
-	            const uint32_t & SIZE_INDEX= i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX];
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_MSS_SETUP_BARS_NM_ALT_BAR_ERR);
-                    break;
-                }
-
-                // MCFGPAQ_VALID
-                rc_ecmd |= MCFGPA.setBit(MCFGPA_VALID_BIT);
-
-                // MCFGPAQ_GROUP_SIZE
-                rc_ecmd |= MCFGPA.insertFromRight(
-                    (i_group_data[MSS_MCS_GROUP_32_ALT_SIZE_INDEX]/4)-1,
-                    MCFGPA_GROUP_SIZE_START_BIT,
-                    (MCFGPA_GROUP_SIZE_END_BIT-
-                     MCFGPA_GROUP_SIZE_START_BIT)+1);
-
-                // MCFGPAQ_BASE_ADDRESS_OF_GROUP
-                rc_ecmd |= MCFGPA.insertFromRight(
-                    i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] >> 2,
-                    MCFGPA_BASE_ADDRESS_START_BIT,
-                    (MCFGPA_BASE_ADDRESS_END_BIT-
-                     MCFGPA_BASE_ADDRESS_START_BIT)+1);
-
-                // check buffer manipulation return codes
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("mss_setup_bars_init_nm_bars: Error 0x%X setting up MCFGPA data buffer",
-                             rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-            }
-        }
-
-        // write registers
-        rc = fapiPutScom(i_mcs_target, MCS_MCFGP_0x02011800, MCFGP);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCFGP_0x02011800)");
-            break;
-        }
-
-        rc = fapiPutScom(i_mcs_target, MCS_MCFGPA_0x02011814, MCFGPA);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCFGPA_0x02011814)");
-            break;
-        }
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCSMODE4_0x0201181A");
-             break;
-        }
-        // set MCSMODE4 bit 0
-        rc_ecmd |= MCSMODE4.setBit(0);
-        rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A");
-             break;
-        }
-        // Clear MCSMODE4 bit 0
-        rc_ecmd |= MCSMODE4.clearBit(0);
-        rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A");
-             break;
-        }
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCIFIR_0x02011840");
-             break;
-        }
-        // Reset MCIFIR bit 25
-        rc_ecmd |= MCIFIR.clearBit(25);
-        rc = fapiPutScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCIFIR_0x02011840");
-             break;
-        }
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-        // Unmask MCIFIR bit 25
-        rc_ecmd |= MCIFIRMASK.clearBit(25);
-        rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_nm_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: write mirrored BAR registers (MCFGPM/MCFGPMA) for a single MCS
-// parameters: i_mcs_target => MCS chiplet target
-//             i_pri_valid  => true if MCS primary mirrored BAR
-//                             should be marked valid
-//             i_group_data => MSS_MCS_GROUP_32 attribute data
-//                             for member group (only valid if
-//                             i_pri_valid=true)
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_setup_bars_init_m_bars(
-    const fapi::Target& i_mcs_target,
-    bool i_pri_valid,
-    uint32_t i_group_data[])
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    ecmdDataBufferBase MCFGPM(64);
-    ecmdDataBufferBase MCFGPMA(64);
-
-    // Defect HW259884 (AddNote by retter) P8 Lab Brazos: Mirror BAR Scom Parity Error - workaround
-    ecmdDataBufferBase MCIFIR(64);
-    ecmdDataBufferBase MCIFIRMASK(64);
-    ecmdDataBufferBase MCSMODE4(64);
-    do
-    {
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-        // Mask MCIFIR bit 25
-        rc_ecmd |= MCIFIRMASK.setBit(25);
-        if (rc_ecmd)
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCIFIRMASK data buffer",
-                         rc_ecmd);
-             rc.setEcmdError(rc_ecmd);
-             break;
-        }
-        rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-        if (i_pri_valid)
-        {
-
-            // MCFGPMQ_VALID
-            rc_ecmd |= MCFGPM.setBit(MCFGPM_VALID_BIT);
-            // MCFGPMQ_GROUP_SIZE
-            rc_ecmd |= MCFGPM.insertFromRight(
-                (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/4)-1,
-                MCFGPM_GROUP_SIZE_START_BIT,
-                (MCFGPM_GROUP_SIZE_END_BIT-
-                 MCFGPM_GROUP_SIZE_START_BIT)+1);
-
-            // MCFGPMQ_BASE_ADDRESS_OF_GROUP
-            rc_ecmd |= MCFGPM.insertFromRight(
-                i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] >> 2,
-                MCFGPM_BASE_ADDRESS_START_BIT,
-                (MCFGPM_BASE_ADDRESS_END_BIT-
-                 MCFGPM_BASE_ADDRESS_START_BIT)+1);
-
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCFGPM data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            bool alt_valid = i_group_data[MSS_MCS_GROUP_32_ALT_VALID_INDEX];
-            if (alt_valid)
-            {
-                // MCFGPMAQ_VALID
-                rc_ecmd |= MCFGPMA.setBit(MCFGPMA_VALID_BIT);
-
-                // MCFGPMAQ_GROUP_SIZE
-                rc_ecmd |= MCFGPMA.insertFromRight(
-                    (i_group_data[MSS_MCS_GROUP_32_ALT_SIZE_INDEX]/4)-1,
-                    MCFGPMA_GROUP_SIZE_START_BIT,
-                    (MCFGPMA_GROUP_SIZE_END_BIT-
-                     MCFGPMA_GROUP_SIZE_START_BIT)+1);
-
-                // MCFGPMAQ_BASE_ADDRESS_OF_GROUP
-                rc_ecmd |= MCFGPMA.insertFromRight(
-                    i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] >> 2,
-                    MCFGPMA_BASE_ADDRESS_START_BIT,
-                    (MCFGPMA_BASE_ADDRESS_END_BIT-
-                     MCFGPMA_BASE_ADDRESS_START_BIT)+1);
-
-                if (i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX] !=
-                    (i_group_data[MSS_MCS_GROUP_32_BASE_INDEX] +
-                     (i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX]/2)))
-                {
-                    FAPI_ERR("mss_setup_bars_init_m_bars: Invalid mirrored alternate BAR configuration");
-                    const uint32_t & ALT_BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_ALT_BASE_INDEX];
-		    const uint32_t & BASE_INDEX = i_group_data[MSS_MCS_GROUP_32_BASE_INDEX];
-		    const uint32_t & SIZE_INDEX= i_group_data[MSS_MCS_GROUP_32_SIZE_INDEX];
-                    FAPI_SET_HWP_ERROR(rc,
-                                       RC_MSS_SETUP_BARS_M_ALT_BAR_ERR);
-                    break;
-                }
-            }
-
-            // check buffer manipulation return codes
-            if (rc_ecmd)
-            {
-                FAPI_ERR("mss_setup_bars_init_m_bars: Error 0x%X setting up MCFGPMA data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-
-        // write registers
-        rc = fapiPutScom(i_mcs_target, MCS_MCFGPM_0x02011801, MCFGPM);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCFGPM_0x02011801)");
-            break;
-        }
-        rc = fapiPutScom(i_mcs_target, MCS_MCFGPMA_0x02011815, MCFGPMA);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCFGPMA_0x02011815");
-            break;
-        }
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCSMODE4_0x0201181A");
-             break;
-        }
-        // set MCSMODE4 bit 0
-        rc_ecmd |= MCSMODE4.setBit(0);
-        rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A");
-             break;
-        }
-        // Clear MCSMODE4 bit 0
-        rc_ecmd |= MCSMODE4.clearBit(0);
-        rc = fapiPutScom(i_mcs_target, MCS_MCSMODE4_0x0201181A, MCSMODE4);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCSMODE4_0x0201181A");
-             break;
-        }
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIR_0x02011840");
-             break;
-        }
-        // Reset MCIFIR bit 25
-        rc_ecmd |= MCIFIR.clearBit(25);
-        rc = fapiPutScom(i_mcs_target, MCS_MCIFIR_0x02011840, MCIFIR);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIR_0x02011840");
-             break;
-        }
-
-        rc = fapiGetScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiGetScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-        // Unmask MCIFIR bit 25
-        rc_ecmd |= MCIFIRMASK.clearBit(25);
-        rc = fapiPutScom(i_mcs_target, MCS_MCIFIRMASK_0x02011843, MCIFIRMASK);
-        if (!rc.ok())
-        {
-             FAPI_ERR("mss_setup_bars_init_m_bars: Error from fapiPutScom (MCS_MCIFIRMASK_0x02011843");
-             break;
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: mss_setup_bars_mcs_size
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_setup_bars_mcs_size(  const fapi::Target & i_target,std::vector<fapi::Target> & i_associated_centaurs, MssSetupBarsSizeInfo & io_sizeInfo)
-{
-      fapi::ReturnCode rc;
-      uint8_t centaur;
-      uint8_t mba_i;
-      uint8_t mba=0;
-      uint8_t dimm=0;
-      uint32_t cenpos;
-      uint32_t procpos;
-      uint8_t port;
-       uint32_t l_unit_pos =0;
-       uint8_t min_group = 1;
-      uint8_t mba_pos[2][2] = { {0, 0},{0,0}};
-      std::vector<fapi::Target> l_mba_chiplets;
-      uint8_t cen_count=0;
-      rc = FAPI_ATTR_GET(ATTR_POS,&i_target, procpos);
-      if(rc) return rc;
-      for(centaur= 0; centaur < i_associated_centaurs.size(); centaur++) {
-        mba=0;port=0;dimm=0;
-        fapi::Target & centaur_t = i_associated_centaurs[centaur];
-        rc = FAPI_ATTR_GET(ATTR_POS,&centaur_t, cenpos);
-        if(rc) return rc;
-        if(cenpos>=procpos*8 && cenpos<(procpos*8+8)){
-                FAPI_INF("... working on centaur %d", cenpos);
-                io_sizeInfo.MCS_size[cenpos - procpos * 8]=0;
-                rc = fapiGetChildChiplets(i_associated_centaurs[centaur], fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets);
-                if(rc) return rc;
-                for(mba_i=0; mba_i<l_mba_chiplets.size(); mba_i++) {
-
-                  rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[mba_i], mba);
-                  if(rc) return rc;
-                  FAPI_INF("... working on mba %d", mba);
-                  rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[mba_i],mba_pos);
-                  if(rc) return rc;
-                  for(port = 0; port<2; port++)
-                  {	
-                    for(dimm=0; dimm<2; dimm++) {
-                       io_sizeInfo.MCS_size[cenpos - procpos * 8]+=mba_pos[port][dimm];
-                       io_sizeInfo.MBA_size[cenpos - procpos * 8][mba] += mba_pos[port][dimm];
-                    }
-                  }
-
-                  FAPI_INF(" Cen Pos %d mba %d DIMM SIZE %d \n",cenpos,mba, io_sizeInfo.MBA_size[cenpos - procpos * 8][mba]);
-                  FAPI_INF(" Cen Pos %d MBA SIZE %d %d  %d %d \n",cenpos, mba_pos[0][0],mba_pos[0][1],mba_pos[1][0],mba_pos[1][1]);
-                  FAPI_INF(" MCS SIZE %d\n",io_sizeInfo.MCS_size[cenpos - procpos * 8]);
-            }
-            cen_count++;l_unit_pos++;
-        }
-      }
-      FAPI_INF("attr_mss_setting %d and  no  of MBAs   %d \n",min_group,l_unit_pos);
-     return rc;
-}
-
-//------------------------------------------------------------------------------
-// function: mss_setup_bars HWP entry point
-//           NOTE: see comments above function prototype in header
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target,   std::vector<fapi::Target> & i_associated_centaurs)
-{
-    fapi::ReturnCode rc;
-    std::vector<fapi::Target> l_mcs_chiplets;
-    uint32_t group_data[16][16];
-    uint8_t M_valid;
-    MssSetupBarsSizeInfo sizeInfo;
-    do
-    {
-
-        rc= mss_setup_bars_mcs_size(i_pu_target,i_associated_centaurs, sizeInfo);
-        // obtain group configuration attribute for this chip
-        rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32, &i_pu_target, group_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars: Error reading ATTR_MSS_MCS_GROUP_32");
-            break;
-        }
-        rc = FAPI_ATTR_GET(ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING, NULL, M_valid);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars: Error reading ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING");
-            break;
-        }
-
-
-         //check if all the grouped mcs are valid
-         for (size_t i = MSS_MCS_GROUP_32_NM_START_INDEX;
-                (i <= MSS_MCS_GROUP_32_NM_END_INDEX);
-                i++)
-           {
-               // only process valid groups
-               if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0)
-               {
-                   continue;
-               }
-
-               uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX];
-
-               uint32_t mcs_sz = group_data[i][0];
-               for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
-                    (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group);
-                    j++)
-               {
-                    if(mcs_sz !=  sizeInfo.MCS_size[group_data[i][j]])
-                    {
-                          FAPI_INF(" Group %zd will not be configured as MCS %d is not valid grouped size is %d , present MCS size is %d \n",i,group_data[i][j],mcs_sz, sizeInfo.MCS_size[group_data[i][j]]);
-                          for(uint8_t k = 0; k<16;k++) { group_data[i][k]=0; }
-                     }
-               }
-           }
-        // get child MCS chiplets
-        rc = fapiGetChildChiplets(i_pu_target,
-                                  fapi::TARGET_TYPE_MCS_CHIPLET,
-                                  l_mcs_chiplets,
-                                  fapi::TARGET_STATE_FUNCTIONAL);
-        if (!rc.ok())
-        {
-            FAPI_ERR("mss_setup_bars: Error from fapiGetChildChiplets");
-            break;
-        }
-
-        // loop through & set configuration of each MCS chiplet
-        for (std::vector<fapi::Target>::iterator iter = l_mcs_chiplets.begin();
-             iter != l_mcs_chiplets.end();
-             iter++)
-        {
-            // obtain MCS chip unit number
-            uint8_t mcs_pos = 0x0;
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*iter), mcs_pos);
-            if (!rc.ok())
-            {
-                FAPI_ERR("mss_setup_bars: Error reading ATTR_CHIP_UNIT_POS");
-                break;
-            }
-
-            // determine non-mirrored member group
-            bool nm_bar_valid = false;
-            uint8_t nm_bar_group_index = 0x0;
-            uint8_t nm_bar_group_member_id = 0x0;
-            for (size_t i = MSS_MCS_GROUP_32_NM_START_INDEX;
-                 (i <= MSS_MCS_GROUP_32_NM_END_INDEX);
-                 i++)
-            {
-                // only process valid groups
-                if (group_data[i][MSS_MCS_GROUP_32_SIZE_INDEX] == 0)
-                {
-                    continue;
-                }
-
-                uint32_t mcs_in_group = group_data[i][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX];
-
-
-                for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
-                     (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group);
-                     j++)
-                {
-                    if (mcs_pos == group_data[i][j])
-                    {
-                        if (nm_bar_valid)
-                        {
-                            const uint8_t& MCS_POS = mcs_pos;
-                            const uint8_t& GROUP_INDEX_A = nm_bar_group_index;
-                            const uint8_t& GROUP_INDEX_B = i;
-                            FAPI_ERR("mss_setup_bars: MCS %d is listed as a member in multiple non-mirrored groups",
-                                     mcs_pos);
-                            FAPI_SET_HWP_ERROR(
-                                rc,
-                                RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR);
-                            break;
-                        }
-                        nm_bar_valid = true;
-                        nm_bar_group_index = i;
-                        nm_bar_group_member_id =
-                            j-MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
-                    }
-                }
-                if (!rc.ok())
-                {
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-
-            // write non-mirrored BARs based on group configuration
-            rc = mss_setup_bars_init_nm_bars(
-                *iter,
-                nm_bar_valid,
-                nm_bar_group_member_id,
-                group_data[nm_bar_group_index]);
-            if (!rc.ok())
-            {
-                FAPI_ERR("mss_setup_bars: Error from mss_setup_bars_init_nm_bars");
-                break;
-            }
-
-            // determine mirrored member group
-            if(!M_valid)
-	    {
-            	bool m_bar_valid = false;
-            	uint8_t m_bar_group_index = 0x0;
-            	for (size_t i = MSS_MCS_GROUP_32_M_START_INDEX;
-                 (i <= MSS_MCS_GROUP_32_M_END_INDEX);
-                 i++)
-            	{
-                	// only process valid groups
-                 if (group_data[i-8][MSS_MCS_GROUP_32_SIZE_INDEX] == 0)
-                    {
-                    	continue;
-                    }
-
-                 uint32_t mcs_in_group = group_data[i-8][MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX];
-                 if( mcs_in_group > 1)
-                 {
-                	for (size_t j = MSS_MCS_GROUP_32_MEMBERS_START_INDEX;
-                    	 (j < MSS_MCS_GROUP_32_MEMBERS_START_INDEX+mcs_in_group);
-                    	 j++)
-                	{
-                    	   if (mcs_pos == group_data[i-8][j])
-                    	   {
-                        	if (m_bar_valid)
-                        	{
-                            	const uint8_t& MCS_POS = mcs_pos;
-                            	const uint8_t& GROUP_INDEX_A = m_bar_group_index;
-                            	const uint8_t& GROUP_INDEX_B = i;
-                            	FAPI_ERR("mss_setup_bars: MCS %d is listed as a member in multiple mirrored groups",
-                                     mcs_pos);
-                            	FAPI_SET_HWP_ERROR(
-                                	rc,
-                                 RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR);
-                            	break;
-                       	        }
-                        	m_bar_valid = true;
-                        	m_bar_group_index = i;
-                           }
-                	}
-            	    if (!rc.ok())
-            	    {
-                	    break;
-            	    }
-                  }
-            	}
-            	if (!rc.ok())
-            	{
-                	break;
-            	}
-            	// write mirrored BARs based on group configuration
-            	rc = mss_setup_bars_init_m_bars(
-                	*iter,
-                	m_bar_valid,
-                	group_data[m_bar_group_index]);
-            	if (!rc.ok())
-            	{
-                	FAPI_ERR("mss_setup_bars: Error from mss_setup_bars_init_m_bars");
-               		 break;
-            	}
-            }
-            // write attribute signifying BARs are valid & MSS inits are finished
-            uint8_t final = 1;
-            rc = FAPI_ATTR_SET(ATTR_MSS_MEM_IPL_COMPLETE, &i_pu_target, final);
-            if (!rc.ok())
-            {
-               	FAPI_ERR("mss_setup_bars: Error from FAPI_ATTR_SET (ATTR_MSS_MEM_IPL_COMPLETE)");
-               	break;
-            }
-
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
deleted file mode 100644
index ed59991f5..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H
+++ /dev/null
@@ -1,149 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/mss_setup_bars.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_setup_bars.H,v 1.9 2014/04/08 16:04:12 gpaulraj Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *!
-// *! TITLE       : mss_setup_bars.C
-// *! DESCRIPTION : Program MCS base address registers (BARs) (FAPI)
-// *!
-// *! OWNER NAME  : Girisankar Paulraj      Email: gpaulraj@in.ibm.com
-// *! OWNER NAME  : Mark Bellows            Email: bellows@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.9    | gpaulraj | 04/08/14|  5/5 FW review feedback - gerrit process - SW251227
-//  1.4    | jdsloat  | 03/13/14| changed const names to stop interfering with eff_grouping
-//  1.3    | bellows  | 07/16/12| added in ID tag
-//  1.1    | gpaulraj | 03/19/12| Updated
-//------------------------------------------------------------------------------
-
-#ifndef MSS_SETUP_BARS_H_
-#define MSS_SETUP_BARS_H_
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-
-
-//------------------------------------------------------------------------------
-//  Constant definitions
-//------------------------------------------------------------------------------
-
-// MCFGP bit/field definitions
-const uint32_t MCFGP_VALID_BIT = 0;
-const uint32_t MCFGP_MCS_UNITS_PER_GROUP_START_BIT = 1;
-const uint32_t MCFGP_MCS_UNITS_PER_GROUP_END_BIT = 3;
-const uint32_t MCFGP_GROUP_MEMBER_ID_START_BIT = 4;
-const uint32_t MCFGP_GROUP_MEMBER_ID_END_BIT = 8;
-const uint32_t MCFGP_ENABLE_RCMD0_BIT = 9;
-const uint32_t MCFGP_ENABLE_RCMD1_BIT = 10;
-const uint32_t MCFGP_GROUP_SIZE_START_BIT = 11;
-const uint32_t MCFGP_GROUP_SIZE_END_BIT = 23;
-const uint32_t MCFGP_RSVD_1_BIT = 24;
-const uint32_t MCFGP_ENABLE_FASTPATH_BIT = 25;
-const uint32_t MCFGP_BASE_ADDRESS_START_BIT = 26;
-const uint32_t MCFGP_BASE_ADDRESS_END_BIT = 43;
-
-// MCFGPA bit/field defintions
-const uint32_t MCFGPA_VALID_BIT = 0;
-const uint32_t MCFGPA_GROUP_SIZE_START_BIT = 11;
-const uint32_t MCFGPA_GROUP_SIZE_END_BIT = 23;
-const uint32_t MCFGPA_BASE_ADDRESS_START_BIT = 26;
-const uint32_t MCFGPA_BASE_ADDRESS_END_BIT = 43;
-
-// MCFGPM bit/field definitions
-const uint32_t MCFGPM_VALID_BIT = 0;
-const uint32_t MCFGPM_GROUP_SIZE_START_BIT = 11;
-const uint32_t MCFGPM_GROUP_SIZE_END_BIT = 23;
-const uint32_t MCFGPM_BASE_ADDRESS_START_BIT = 26;
-const uint32_t MCFGPM_BASE_ADDRESS_END_BIT = 43;
-
-// MCFGPMA bit/field definitions
-const uint32_t MCFGPMA_VALID_BIT = 0;
-const uint32_t MCFGPMA_GROUP_SIZE_START_BIT = 11;
-const uint32_t MCFGPMA_GROUP_SIZE_END_BIT = 23;
-const uint32_t MCFGPMA_BASE_ADDRESS_START_BIT = 26;
-const uint32_t MCFGPMA_BASE_ADDRESS_END_BIT = 43;
-
-// attribute index constants
-// first array dimension (group ID)
-const uint8_t MSS_MCS_GROUP_32_NM_START_INDEX = 0;
-const uint8_t MSS_MCS_GROUP_32_NM_END_INDEX   = 7;
-const uint8_t MSS_MCS_GROUP_32_M_START_INDEX  = 8;
-const uint8_t MSS_MCS_GROUP_32_M_END_INDEX    = 15;
-
-// second array dimension (group definition)
-const uint8_t MSS_MCS_GROUP_32_MCS_IN_GROUP_INDEX  = 1;
-const uint8_t MSS_MCS_GROUP_32_SIZE_INDEX          = 2;
-const uint8_t MSS_MCS_GROUP_32_BASE_INDEX          = 3;
-const uint8_t MSS_MCS_GROUP_32_MEMBERS_START_INDEX = 4;
-const uint8_t MSS_MCS_GROUP_32_ALT_VALID_INDEX     = 12;
-const uint8_t MSS_MCS_GROUP_32_ALT_SIZE_INDEX      = 13;
-const uint8_t MSS_MCS_GROUP_32_ALT_BASE_INDEX      = 14;
-
-
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*mss_setup_bars_FP_t)(const fapi::Target& i_pu_target, std::vector<fapi::Target> & i_associated_centaurs);
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function: program MCS base address registers (BARs)
-//           writes non-mirrored (MCFGP/MCFGPA) &
-//           mirrored BAR registers (MCFGPM/MCFGPMA)
-// parameters: i_pu_target  => chip level target
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          RC_MSS_SETUP_BARS_MULTIPLE_GROUP_ERR if a child MCS is listed
-//            as a member in multiple groups
-//          else failing return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_setup_bars(const fapi::Target& i_pu_target, std::vector<fapi::Target> & i_associated_centaurs);
-
-
-} // extern "C"
-
-#endif // MSS_SETUP_BARS_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C
deleted file mode 100644
index 487def4a2..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C
+++ /dev/null
@@ -1,329 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_fab_smp.C,v 1.9 2014/01/27 05:22:07 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_fab_smp.C
-// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_fab_smp.H>
-
-extern "C" {
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility function to read & return fabric node ID attribute
-// parameters: i_target  => pointer to chip/chiplet target
-//             o_node_id => node ID value
-// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_smp_get_node_id_attr(
-    const fapi::Target* i_target,
-    proc_fab_smp_node_id& o_node_id)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // chiplet->chip target conversion
-    bool use_parent = false;
-    fapi::Target parent_target;
-    // temporary attribute storage used to build procedure data structures
-    uint8_t node_id_attr;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_smp_get_node_id_attr: Start");
-
-    do
-    {
-        if (i_target->getType() != fapi::TARGET_TYPE_PROC_CHIP)
-        {
-            use_parent = true;
-            // retrieve parent target if input target is a chiplet
-            rc = fapiGetParentChip(*i_target,
-                                   parent_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_fab_smp_get_node_id_attr: Error from fapiGetParentChip");
-                break;
-            }
-        }
-
-        // retrieve node ID attribute
-        rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID,
-                           ((use_parent)?
-                            (&parent_target):
-                            (i_target)),
-                           node_id_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_smp_get_node_id_attr: Error querying ATTR_FABRIC_NODE_ID");
-            break;
-        }
-
-        // print attribute value
-        FAPI_DBG("proc_fab_smp_get_node_id_attr: ATTR_FABRIC_NODE_ID = 0x%X",
-                 node_id_attr);
-
-        // translate to output value
-        switch (node_id_attr)
-        {
-            case 0:
-                o_node_id = FBC_NODE_ID_0;
-                break;
-            case 1:
-                o_node_id = FBC_NODE_ID_1;
-                break;
-            case 2:
-                o_node_id = FBC_NODE_ID_2;
-                break;
-            case 3:
-                o_node_id = FBC_NODE_ID_3;
-                break;
-            case 4:
-                o_node_id = FBC_NODE_ID_4;
-                break;
-            case 5:
-                o_node_id = FBC_NODE_ID_5;
-                break;
-            case 6:
-                o_node_id = FBC_NODE_ID_6;
-                break;
-            case 7:
-                o_node_id = FBC_NODE_ID_7;
-                break;
-            default:
-                FAPI_ERR("proc_fab_smp_get_node_id_attr: Invalid fabric node ID attribute value 0x%02X",
-                         node_id_attr);
-                const fapi::Target & TARGET = *i_target;
-                const uint8_t& ATTR_DATA = node_id_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR);
-                break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_smp_get_node_id_attr: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to read & return fabric chip ID attribute
-// parameters: i_target  => pointer to chip/chiplet target
-//             o_chip_id => chip ID value
-// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_smp_get_chip_id_attr(
-    const fapi::Target* i_target,
-    proc_fab_smp_chip_id& o_chip_id)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // chiplet->chip target conversion
-    bool use_parent = false;
-    fapi::Target parent_target;
-    // temporary attribute storage used to build procedure data structures
-    uint8_t chip_id_attr;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_smp_get_chip_id_attr: Start");
-
-    do
-    {
-        if (i_target->getType() != fapi::TARGET_TYPE_PROC_CHIP)
-        {
-            use_parent = true;
-            // retrieve parent target if input target is a chiplet
-            rc = fapiGetParentChip(*i_target,
-                                   parent_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_fab_smp_get_chip_id_attr: Error from fapiGetParentChip");
-                break;
-            }
-        }
-
-        // retrieve chip ID attribute
-        rc = FAPI_ATTR_GET(ATTR_FABRIC_CHIP_ID,
-                           ((use_parent)?
-                            (&parent_target):
-                            (i_target)),
-                           chip_id_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_smp_get_chip_id_attr: Error querying ATTR_FABRIC_CHIP_ID");
-            break;
-        }
-
-        // print attribute value
-        FAPI_DBG("proc_fab_smp_get_chip_id_attr: ATTR_FABRIC_CHIP_ID = 0x%X",
-                 chip_id_attr);
-
-        // translate to output value
-        switch (chip_id_attr)
-        {
-            case 0:
-                o_chip_id = FBC_CHIP_ID_0;
-                break;
-            case 1:
-                o_chip_id = FBC_CHIP_ID_1;
-                break;
-            case 2:
-                o_chip_id = FBC_CHIP_ID_2;
-                break;
-            case 3:
-                o_chip_id = FBC_CHIP_ID_3;
-                break;
-            case 4:
-                o_chip_id = FBC_CHIP_ID_4;
-                break;
-            case 5:
-                o_chip_id = FBC_CHIP_ID_5;
-                break;
-            case 6:
-                o_chip_id = FBC_CHIP_ID_6;
-                break;
-            case 7:
-                o_chip_id = FBC_CHIP_ID_7;
-                break;
-            default:
-                FAPI_ERR("proc_fab_smp_get_chip_id_attr: Invalid fabric chip ID attribute value 0x%02X",
-                         chip_id_attr);
-                const fapi::Target & TARGET = *i_target;
-                const uint8_t& ATTR_DATA = chip_id_attr;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR);
-                break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_smp_get_chip_id_attr: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to read & return PCIe/DSMP mux attribute values
-// parameters: i_target          => pointer to chip target
-//             o_pcie_not_f_link => vector of boolean values representing state
-//                                  of PCIe/DSMP mux settings (one value per
-//                                  foreign link, true=PCIe function, false=
-//                                  DSMP function)
-// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
-//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
-//              invalid,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs(
-    const fapi::Target* i_target,
-    bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS])
-{
-    // return code
-    fapi::ReturnCode rc;
-    // temporary attribute storage used to build procedure data structures
-    uint8_t pcie_not_f_link_attr[PROC_FAB_SMP_NUM_F_LINKS];
-
-    // mark function entry
-    FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: Start");
-
-    do
-    {
-        // retrieve PCIe/DSMP mux attributes
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NOT_F_LINK,
-                           i_target,
-                           pcie_not_f_link_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Error querying ATTR_PROC_PCIE_NOT_F_LINK");
-            break;
-        }
-
-        // loop over all links
-        for (uint8_t l = 0;
-             l < PROC_FAB_SMP_NUM_F_LINKS;
-             l++)
-        {
-            // print attribute value
-            FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: ATTR_PROC_PCIE_NOT_F_LINK[%d] = 0x%X",
-                     l, pcie_not_f_link_attr[l]);
-
-            // validate attribute value
-            switch (pcie_not_f_link_attr[l])
-            {
-                case 0:
-                    o_pcie_not_f_link[l] = false;
-                    break;
-                case 1:
-                    o_pcie_not_f_link[l] = true;
-                    break;
-                default:
-                    FAPI_ERR("proc_fab_smp_get_pcie_dsmp_mux_attrs: Invalid PCIe/DSMP mux attribute value 0x%02X",
-                             pcie_not_f_link_attr[l]);
-                    const fapi::Target & TARGET = *i_target;
-                    const uint8_t& ATTR_DATA = pcie_not_f_link_attr[l];
-                    FAPI_SET_HWP_ERROR(rc,
-                        RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR);
-                    break;
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_smp_get_pcie_dsmp_mux_attrs: End");
-    return rc;
-}
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H
deleted file mode 100644
index 7f26f083c..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H
+++ /dev/null
@@ -1,163 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_fab_smp.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_fab_smp.H,v 1.9 2014/01/27 05:22:15 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_smp.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_fab_smp.H
-// *! DESCRIPTION : Common fabric structure defintions/utility functions (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_FAB_SMP_H_
-#define _PROC_FAB_SMP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// define set of supported fabric node ID values
-enum proc_fab_smp_node_id
-{
-    FBC_NODE_ID_0 = 0,
-    FBC_NODE_ID_1 = 1,
-    FBC_NODE_ID_2 = 2,
-    FBC_NODE_ID_3 = 3,
-    FBC_NODE_ID_4 = 4,
-    FBC_NODE_ID_5 = 5,
-    FBC_NODE_ID_6 = 6,
-    FBC_NODE_ID_7 = 7
-};
-
-// define set of supported fabric chip ID values
-enum proc_fab_smp_chip_id
-{
-    FBC_CHIP_ID_0 = 0,
-    FBC_CHIP_ID_1 = 1,
-    FBC_CHIP_ID_2 = 2,
-    FBC_CHIP_ID_3 = 3,
-    FBC_CHIP_ID_4 = 4,
-    FBC_CHIP_ID_5 = 5,
-    FBC_CHIP_ID_6 = 6,
-    FBC_CHIP_ID_7 = 7
-};
-
-// define set of supported epsilon table types
-enum proc_fab_smp_eps_table_type
-{
-    PROC_FAB_SMP_EPSILON_TABLE_TYPE_LE = 1,
-    PROC_FAB_SMP_EPSILON_TABLE_TYPE_HE = 2,
-    PROC_FAB_SMP_EPSILON_TABLE_TYPE_1S = 3
-};
-
-// define set of supported broadcast/pump modes
-enum proc_fab_smp_pump_mode
-{
-    PROC_FAB_SMP_PUMP_MODE1 = 1,
-    PROC_FAB_SMP_PUMP_MODE2 = 2
-};
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// largest representable fabric real address given HW implementation
-const uint64_t PROC_FAB_SMP_MAX_ADDRESS = ((1ULL << 50)-1ULL);
-
-// number of links supported per chip
-const uint8_t PROC_FAB_SMP_NUM_A_LINKS = 3;
-const uint8_t PROC_FAB_SMP_NUM_X_LINKS = 4;
-const uint8_t PROC_FAB_SMP_NUM_F_LINKS = 2;
-
-// range of fabric node/chip ID fields
-const uint8_t PROC_FAB_SMP_NUM_CHIP_IDS = 8;
-const uint8_t PROC_FAB_SMP_NUM_NODE_IDS = 8;
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: utility function to read & return fabric node ID attribute
-// parameters: i_target  => pointer to chip/chiplet target
-//             o_node_id => node ID value
-// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
-//          RC_PROC_FAB_SMP_FABRIC_NODE_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_smp_get_node_id_attr(
-    const fapi::Target* i_target,
-    proc_fab_smp_node_id& o_node_id);
-
-//------------------------------------------------------------------------------
-// function: utility function to read & return fabric chip ID attribute
-// parameters: i_target  => pointer to chip/chiplet target
-//             o_chip_id => chip ID value
-// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
-//          RC_PROC_FAB_SMP_FABRIC_CHIP_ID_ATTR_ERR if attribute value is
-//              invalid,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_smp_get_chip_id_attr(
-    const fapi::Target* i_target,
-    proc_fab_smp_chip_id& o_chip_id);
-
-//------------------------------------------------------------------------------
-// function: utility function to read & return PCIe/DSMP mux attribute values
-// parameters: i_target          => pointer to chip target
-//             o_pcie_not_f_link => vector of boolean values representing state
-//                                  of PCIe/DSMP mux settings (one value per
-//                                  foreign link, true=PCIe function, false=
-//                                  DSMP function)
-// returns: FAPI_RC_SUCCESS if attribute read is successful & value is valid,
-//          RC_PROC_FAB_SMP_PCIE_NOT_F_LINK_ATTR_ERR if attribute value is
-//              invalid,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_smp_get_pcie_dsmp_mux_attrs(
-    const fapi::Target* i_target,
-    bool o_pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS]);
-
-
-} // extern "C"
-
-#endif // _PROC_FAB_SMP_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
deleted file mode 100644
index 2315b73cd..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ /dev/null
@@ -1,3887 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.C,v 1.29 2015/11/10 19:39:58 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_setup_bars.C
-// *! DESCRIPTION : Program nest base address registers (BARs) (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_setup_bars.H>
-#include <proc_setup_bars_defs.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// logical size->physical encoding translation maps
-const std::map<uint64_t, uint64_t> proc_setup_bars_nf_bar_size::xlate_map =
-    proc_setup_bars_nf_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_f_bar_size::xlate_map =
-    proc_setup_bars_f_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_bar_size::xlate_map =
-    proc_setup_bars_fsp_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_fsp_mmio_mask_size::xlate_map =
-    proc_setup_bars_fsp_mmio_mask_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_nx_mmio_bar_size::xlate_map =
-    proc_setup_bars_nx_mmio_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_npu_mmio_bar_size::xlate_map =
-    proc_setup_bars_npu_mmio_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_hca_nm_bar_size::xlate_map =
-    proc_setup_bars_hca_nm_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_as_mmio_bar_size::xlate_map =
-    proc_setup_bars_as_mmio_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_mcd_bar_size::xlate_map =
-    proc_setup_bars_mcd_bar_size::create_map();
-
-const std::map<uint64_t, uint64_t> proc_setup_bars_pcie_bar_size::xlate_map =
-    proc_setup_bars_pcie_bar_size::create_map();
-
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility function to display address range/BAR information and
-//           check properties
-// parameters: i_bar_def        => structure encapsulating address range/BAR
-//                                 properties
-//             i_bar_addr_range => structure encapsulating address range
-// returns: true if any properties specified by i_bar_def are violated,
-//          false otherwise
-//------------------------------------------------------------------------------
-bool proc_setup_bars_common_check_bar(
-    const proc_setup_bars_bar_def& i_bar_def,
-    const proc_setup_bars_addr_range& i_bar_addr_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // set if error should be logged at end of function
-    bool error = false;
-
-    do
-    {
-        // print range information
-        i_bar_addr_range.print();
-
-        // only check if BAR enable attribute is set
-        if (i_bar_addr_range.enabled)
-        {
-            // ensure that address range lies in fabric real address space
-            if (!i_bar_addr_range.is_in_fbc_range())
-            {
-                FAPI_ERR("proc_setup_bars_common_check_bar: BAR range is not wholly contained in FBC real address space");
-                error = true;
-                break;
-            }
-            // ensure that base address value lies in implemented address space
-            if (i_bar_addr_range.base_addr &
-                i_bar_def.base_addr_mask)
-            {
-                FAPI_ERR("proc_setup_bars_common_check_bar: BAR base address attribute value is out-of-range");
-                error = true;
-                break;
-            }
-            // ensure that address range size is in range
-            if ((i_bar_addr_range.size < i_bar_def.size_min) ||
-                (i_bar_addr_range.size > i_bar_def.size_max))
-            {
-                FAPI_ERR("proc_setup_bars_common_check_bar: BAR size attribute value is out-of-range");
-                error = true;
-                break;
-            }
-            // check that base address range and mask are aligned
-            if (i_bar_def.check_aligned &&
-                !i_bar_addr_range.is_aligned())
-            {
-                FAPI_ERR("proc_setup_bars_common_check_bar: BAR base address/size range values are not aligned");
-                error = true;
-                break;
-            }
-        }
-    } while(0);
-
-    return error;
-}
-
-
-//------------------------------------------------------------------------------
-// function: retrieve attribute (with optional indices) using FAPI AttributeId
-// parameters: i_attr           => attribute ID to query
-//             i_attr_id        => enum identifying attribute function
-//             i_target         => pointer to chip target
-//             i_attr_idx1      => attribute array index1
-//             i_attr_idx2      => attribute array index1
-//             o_val            => output value
-// returns: FAPI_RC_SUCCESS if attribute read is successful & output value
-//              is valid,
-//          RC_PROC_SETUP_BARS_ATTR_QUERY_ERR if FAPI attribute ID is
-//              unsupported,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_query_attr(
-    const fapi::AttributeId i_attr,
-    const proc_setup_bars_attr_id i_attr_id,
-    const fapi::Target* i_target,
-    const uint32_t i_attr_idx1,
-    const uint32_t i_attr_idx2,
-    uint64_t& o_val)
-{
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_query_attr: Start");
-
-    // ATTR_PROC_MEM_BASES_ACK
-    if (i_attr == fapi::ATTR_PROC_MEM_BASES_ACK)
-    {
-        fapi::ATTR_PROC_MEM_BASES_ACK_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES_ACK, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_MEM_SIZES_ACK
-    else if (i_attr == fapi::ATTR_PROC_MEM_SIZES_ACK)
-    {
-        fapi::ATTR_PROC_MEM_SIZES_ACK_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES_ACK, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_MIRROR_BASES_ACK
-    else if (i_attr == fapi::ATTR_PROC_MIRROR_BASES_ACK)
-    {
-        fapi::ATTR_PROC_MIRROR_BASES_ACK_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES_ACK, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_MIRROR_SIZES_ACK
-    else if (i_attr == fapi::ATTR_PROC_MIRROR_SIZES_ACK)
-    {
-        fapi::ATTR_PROC_MIRROR_SIZES_ACK_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES_ACK, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_FOREIGN_NEAR_BASE
-    else if (i_attr == fapi::ATTR_PROC_FOREIGN_NEAR_BASE)
-    {
-        fapi::ATTR_PROC_FOREIGN_NEAR_BASE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_NEAR_BASE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_FOREIGN_NEAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_FOREIGN_NEAR_SIZE)
-    {
-        fapi::ATTR_PROC_FOREIGN_NEAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_NEAR_SIZE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_FOREIGN_FAR_BASE
-    else if (i_attr == fapi::ATTR_PROC_FOREIGN_FAR_BASE)
-    {
-        fapi::ATTR_PROC_FOREIGN_FAR_BASE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_FAR_BASE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_FOREIGN_FAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_FOREIGN_FAR_SIZE)
-    {
-        fapi::ATTR_PROC_FOREIGN_FAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FOREIGN_FAR_SIZE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1];
-    }
-    // ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_PSI_BRIDGE_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_PSI_BRIDGE_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_PSI_BRIDGE_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PSI_BRIDGE_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_FSP_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_FSP_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_FSP_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_FSP_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_FSP_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_FSP_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_FSP_BAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_FSP_BAR_SIZE)
-    {
-        fapi::ATTR_PROC_FSP_BAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FSP_BAR_SIZE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_FSP_MMIO_MASK_SIZE
-    else if (i_attr == fapi::ATTR_PROC_FSP_MMIO_MASK_SIZE)
-    {
-        fapi::ATTR_PROC_FSP_MMIO_MASK_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_FSP_MMIO_MASK_SIZE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_INTP_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_INTP_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_INTP_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_INTP_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_INTP_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_INTP_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_INTP_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_INTP_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_NX_MMIO_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_NX_MMIO_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_NX_MMIO_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_NX_MMIO_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_NX_MMIO_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_NX_MMIO_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_NX_MMIO_BAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_NX_MMIO_BAR_SIZE)
-    {
-        fapi::ATTR_PROC_NX_MMIO_BAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_NX_MMIO_BAR_SIZE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_AS_MMIO_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_AS_MMIO_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_AS_MMIO_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_AS_MMIO_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_AS_MMIO_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_AS_MMIO_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_AS_MMIO_BAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_AS_MMIO_BAR_SIZE)
-    {
-        fapi::ATTR_PROC_AS_MMIO_BAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_AS_MMIO_BAR_SIZE, i_target, attr_data);
-        o_val = attr_data;
-    }
-    // ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1][i_attr_idx2];
-    }
-    // ATTR_PROC_NPU_MMIO_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_NPU_MMIO_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_NPU_MMIO_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_NPU_MMIO_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1][i_attr_idx2];
-    }
-    // ATTR_PROC_NPU_MMIO_BAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_NPU_MMIO_BAR_SIZE)
-    {
-        fapi::ATTR_PROC_NPU_MMIO_BAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_NPU_MMIO_BAR_SIZE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1][i_attr_idx2];
-    }
-    // ATTR_PROC_PCIE_BAR_BASE_ADDR
-    else if (i_attr == fapi::ATTR_PROC_PCIE_BAR_BASE_ADDR)
-    {
-        fapi::ATTR_PROC_PCIE_BAR_BASE_ADDR_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_BASE_ADDR, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1][i_attr_idx2];
-    }
-    // ATTR_PROC_PCIE_BAR_ENABLE
-    else if (i_attr == fapi::ATTR_PROC_PCIE_BAR_ENABLE)
-    {
-        fapi::ATTR_PROC_PCIE_BAR_ENABLE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_ENABLE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1][i_attr_idx2];
-    }
-    // ATTR_PROC_PCIE_BAR_SIZE
-    else if (i_attr == fapi::ATTR_PROC_PCIE_BAR_SIZE)
-    {
-        fapi::ATTR_PROC_PCIE_BAR_SIZE_Type attr_data;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_BAR_SIZE, i_target, attr_data);
-        o_val = attr_data[i_attr_idx1][i_attr_idx2];
-    }
-    else
-    {
-        FAPI_ERR("proc_setup_bars_query_attr: Unsupported FAPI Attribute ID");
-        const fapi::Target & TARGET = *i_target;
-        const fapi::AttributeId & FAPI_ATTR_ID = i_attr;
-        const proc_setup_bars_attr_id & ATTR_ID = i_attr_id;
-        const uint32_t & ATTR_IDX1 = i_attr_idx1;
-        const uint32_t & ATTR_IDX2 = i_attr_idx2;
-        FAPI_SET_HWP_ERROR(rc,
-            RC_PROC_SETUP_BARS_ATTR_QUERY_ERR);
-    }
-
-    FAPI_DBG("proc_setup_bars_query_attr: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: retrieve attributes defining unit BAR/range programming
-// parameters: i_target         => pointer to chip target
-//             i_attr_id        => enum identifying BAR/range function
-//             i_base_addr_attr => pointer to attribute ID associated with
-//                                 BAR/range base address
-//             i_enable_attr    => pointer to attribute ID associated with
-//                                 BAR/range enable
-//             i_size_attr      => pointer to attribute ID associated with
-//                                 BAR/range size
-//             i_attr_idx1      => attribute array index1
-//             i_attr_idx2      => attribute array index2
-//             i_bar_def        => structure encapsulating BAR/range
-//                                 properties
-//             io_addr_range    => address range structure encapsulating
-//                                 attribute values
-// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
-//              are valid,
-//          RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR if no rule is
-//              provided to set BAR/range address/enable/size,
-//          RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR if BAR/range
-//              attribute content violates expected behavior,
-//          else FAPI_ATTR_GET return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_get_range_attrs(
-    const fapi::Target* i_target,
-    const proc_setup_bars_attr_id i_attr_id,
-    const fapi::AttributeId* i_base_addr_attr,
-    const fapi::AttributeId* i_enable_attr,
-    const fapi::AttributeId* i_size_attr,
-    const uint32_t i_attr_idx1,
-    const uint32_t i_attr_idx2,
-    const proc_setup_bars_bar_def& i_bar_def,
-    proc_setup_bars_addr_range& io_addr_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint64_t bar_enabled;
-
-    FAPI_DBG("proc_setup_bars_get_range_attrs: Start");
-    do
-    {
-        // BAR base address
-        if ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FSP_MMIO) && !i_attr_idx1 && !i_attr_idx2)
-        {
-            io_addr_range.base_addr = 0x0;
-        }
-        else if (i_base_addr_attr)
-        {
-    	    rc = proc_setup_bars_query_attr(
-                *i_base_addr_attr,
-                i_attr_id,
-                i_target,
-                i_attr_idx1, i_attr_idx2,
-                io_addr_range.base_addr);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_get_range_attrs: Error querying BAR base address attribute (Unit/Range ID = 0x%X, FAPI Attribute ID = %08X)",
-                         i_attr_id, *i_base_addr_attr);
-                break;
-            }
-        }
-        else
-        {
-            FAPI_ERR("proc_setup_bars_get_range_attrs: No rule to set range base address");
-            const fapi::Target & TARGET = *i_target;
-            const proc_setup_bars_attr_id & ATTR_ID = i_attr_id;
-            const uint32_t & ATTR_IDX1 = i_attr_idx1;
-            const uint32_t & ATTR_IDX2 = i_attr_idx2;
-            const proc_setup_bars_attr_lookup_err_type & ERR_TYPE = PROC_SETUP_BARS_BASE_ADDR_ATTR_LOOKUP_ERR;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR);
-            break;
-        }
-
-        // BAR size
-        if (((i_attr_id == PROC_SETUP_BARS_ATTR_ID_PSI) ||
-             (i_attr_id == PROC_SETUP_BARS_ATTR_ID_INTP)) &&
-            !i_attr_idx1 && !i_attr_idx2)
-        {
-            io_addr_range.size = PROC_SETUP_BARS_SIZE_1_MB;
-        }
-        else if (i_size_attr)
-        {
-            rc = proc_setup_bars_query_attr(
-                *i_size_attr,
-                i_attr_id,
-                i_target,
-                i_attr_idx1, i_attr_idx2,
-                io_addr_range.size);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_get_range_attrs: Error querying BAR size attribute (Unit/Range ID = 0x%X, FAPI Attribute ID = 0x%08X)",
-                         i_attr_id, *i_size_attr);
-                break;
-            }
-        }
-        else
-        {
-            FAPI_ERR("proc_setup_bars_get_range_attrs: No rule to set range size");
-            const fapi::Target & TARGET = *i_target;
-            const proc_setup_bars_attr_id & ATTR_ID = i_attr_id;
-            const uint32_t & ATTR_IDX1 = i_attr_idx1;
-            const uint32_t & ATTR_IDX2 = i_attr_idx2;
-            const proc_setup_bars_attr_lookup_err_type & ERR_TYPE = PROC_SETUP_BARS_SIZE_ATTR_LOOKUP_ERR;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR);
-            break;
-        }
-
-        // BAR enable
-        if ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FSP_MMIO) && !i_attr_idx1 && !i_attr_idx2)
-        {
-            io_addr_range.enabled = true;
-        }
-
-        else if (((i_attr_id == PROC_SETUP_BARS_ATTR_ID_NM) && (i_attr_idx1 < PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES) && !i_attr_idx2) ||
-                 ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_M)  && (i_attr_idx1 < PROC_SETUP_BARS_NUM_MIRRORED_RANGES) && !i_attr_idx2) ||
-                 ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FN) && (i_attr_idx1 < PROC_FAB_SMP_NUM_F_LINKS) && !i_attr_idx2) ||
-                 ((i_attr_id == PROC_SETUP_BARS_ATTR_ID_FF) && (i_attr_idx1 < PROC_FAB_SMP_NUM_F_LINKS) && !i_attr_idx2))
-        {
-            io_addr_range.enabled = (io_addr_range.size != 0);
-        }
-        else if (i_enable_attr)
-        {
-    	    rc = proc_setup_bars_query_attr(
-                *i_enable_attr,
-                i_attr_id,
-                i_target,
-                i_attr_idx1, i_attr_idx2,
-                bar_enabled);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_get_range_attrs: Error querying BAR enable attribute (Unit/Range ID = 0x%X, FAPI Attribute ID = 0x%08X)",
-                         i_attr_id, *i_enable_attr);
-                break;
-            }
-            io_addr_range.enabled = (bar_enabled == 0x1ULL);
-        }
-        else
-        {
-            FAPI_ERR("proc_setup_bars_get_range_attrs: No rule to set range enable");
-            const fapi::Target & TARGET = *i_target;
-            const proc_setup_bars_attr_id & ATTR_ID = i_attr_id;
-            const uint32_t & ATTR_IDX1 = i_attr_idx1;
-            const uint32_t & ATTR_IDX2 = i_attr_idx2;
-            const proc_setup_bars_attr_lookup_err_type & ERR_TYPE = PROC_SETUP_BARS_ENABLE_ATTR_LOOKUP_ERR;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR);
-            break;
-        }
-
-        // check BAR attribute content
-        if (proc_setup_bars_common_check_bar(
-                i_bar_def,
-                io_addr_range) != false)
-        {
-            FAPI_ERR("proc_setup_bars_get_range_attrs: Error from proc_setup_bars_common_check_bar");
-            const fapi::Target & TARGET = *i_target;
-            const proc_setup_bars_attr_id & ATTR_ID = i_attr_id;
-            const uint32_t & ATTR_IDX1 = i_attr_idx1;
-            const uint32_t & ATTR_IDX2 = i_attr_idx2;
-            const uint64_t & BASE_ADDR = io_addr_range.base_addr;
-            const bool & ENABLED = io_addr_range.enabled;
-            const uint64_t & SIZE = io_addr_range.size;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR);
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_get_range_attrs: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: retrieve attributes defining non-mirrored/mirrored memory ranges
-// parameters: i_target         => pointer to chip target
-//             i_range_id       => enum identifying range function
-//             i_base_addr_attr => pointer to attribute ID associated with
-//                                 ange base addresses
-//             i_size_attr      => pointer to attribute ID associated with
-//                                 range sizes
-//             i_num_ranges     => number of ranges (attribute dimension)
-//             i_range_def      => structure encapsulating range
-//                                 properties
-//             io_addr_range    => address range structure encapsulating
-//                                 attribute
-//                                 values (size will be rounded up to nearest
-//                                 power of two)
-// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
-//              are valid,
-//          RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ATTR_OVERLAP_ERR if chip
-//              memory range attributes specify overlapping address ranges,
-//          RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ERR if merged chip 
-//              memory address range is invalid,
-//          RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR if BAR/range
-//              attribute content violates expected behavior,
-//          else proc_setup_bars_get_range_attrs failing return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_get_memory_range_attrs(
-    const fapi::Target* i_target,
-    const proc_setup_bars_attr_id i_range_id,
-    const fapi::AttributeId i_base_addr_attr,
-    const fapi::AttributeId i_size_attr,
-    const uint8_t i_num_ranges,
-    const proc_setup_bars_bar_def& i_range_def,
-    proc_setup_bars_addr_range& io_addr_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // set of ranges, to be checked/merged into single range
-    std::vector<proc_setup_bars_addr_range> ranges(i_num_ranges);
-
-    // mark function entry
-    FAPI_DBG("proc_setup_bars_get_memory_range_attrs: Start");
-
-    do
-    {
-        // build individual ranges
-        for (uint8_t r = 0; r < i_num_ranges; r++)
-        {
-            rc = proc_setup_bars_get_range_attrs(
-                i_target,
-                i_range_id,
-                &i_base_addr_attr,
-                NULL,
-                &i_size_attr,
-                r, 0,
-                i_range_def,
-                ranges[r]);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_get_memory_range_attrs: Error from proc_setup_bars_get_range_attrs (Range ID = 0x%X, Range index = %d)",
-                         i_range_id, r);
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // check that ranges are non-overlapping
-        if (i_num_ranges > 1)
-        {
-            for (uint8_t r = 0; (r < i_num_ranges-1) && rc.ok(); r++)
-            {
-                for (uint8_t x = r+1; x < i_num_ranges; x++)
-                {
-                    if (ranges[r].overlaps(ranges[x]))
-                    {
-                        FAPI_ERR("proc_setup_bars_get_memory_range_attrs: Memory range attributes specify overlapping address regions (Range ID = 0x%X, Range index1 = %d, Range index2 = %d)",
-                                 i_range_id, r, x);
-                        const fapi::Target & TARGET = *i_target;
-                        const proc_setup_bars_attr_id & RANGE_ID = i_range_id;
-                        const uint32_t & ATTR_IDX1 = r;
-                        const uint64_t & BASE_ADDR1 = ranges[r].base_addr;
-                        const uint64_t & END_ADDR1 = ranges[r].end_addr();
-                        const bool & ENABLED1 = ranges[r].enabled;
-                        const uint32_t & ATTR_IDX2 = x;
-                        const uint64_t & BASE_ADDR2 = ranges[x].base_addr;
-                        const uint64_t & END_ADDR2 = ranges[x].end_addr();
-                        const bool & ENABLED2 = ranges[x].enabled;
-                        FAPI_SET_HWP_ERROR(rc,
-                            RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ATTR_OVERLAP_ERR);
-                        break;
-                    }
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-
-        // ranges are non-overlapping, merge to single range
-        for (uint8_t r = 0; r < i_num_ranges; r++)
-        {
-            // merge to build single range
-            io_addr_range.merge(ranges[r]);
-        }
-
-        // ensure range is power of 2 aligned
-        if (io_addr_range.enabled && !io_addr_range.is_power_of_2())
-        {
-            io_addr_range.round_next_power_of_2();
-        }
-
-        // check final range content
-        if (proc_setup_bars_common_check_bar(
-                i_range_def,
-                io_addr_range) != false)
-        {
-            FAPI_ERR("proc_setup_bars_get_memory_range_attrs: Error from proc_setup_bars_common_check_bar");
-            const fapi::Target & TARGET = *i_target;
-            const proc_setup_bars_attr_id & RANGE_ID = i_range_id;
-            const uint64_t & BASE_ADDR = io_addr_range.base_addr;
-            const uint64_t & END_ADDR = io_addr_range.end_addr();
-            const bool & ENABLED = io_addr_range.enabled;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ERR);
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_setup_bars_get_memory_range_attrs: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to call all BAR attribute query functions
-// parameters: io_smp_chip => structure encapsulating single chip in SMP
-//                            topology (containing target for attribute
-//                            query and storage for all address ranges)
-// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
-//              are valid,
-//          else failing return code from attribute query function
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_get_bar_attrs(
-    proc_setup_bars_smp_chip& io_smp_chip)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_setup_bars_get_bar_attrs: Start");
-
-    do
-    {
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for non-mirrored memory range");
-        rc = proc_setup_bars_get_memory_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_NM,
-            fapi::ATTR_PROC_MEM_BASES_ACK,
-            fapi::ATTR_PROC_MEM_SIZES_ACK,
-            PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES,
-            non_mirrored_range_def,
-            io_smp_chip.non_mirrored_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_memory_range_attrs (non-mirrored)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for mirrored memory range");
-        rc = proc_setup_bars_get_memory_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_M,
-            fapi::ATTR_PROC_MIRROR_BASES_ACK,
-            fapi::ATTR_PROC_MIRROR_SIZES_ACK,
-            PROC_SETUP_BARS_NUM_MIRRORED_RANGES,
-            mirrored_range_def,
-            io_smp_chip.mirrored_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_memory_range_attrs (mirrored)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for foreign near memory ranges");
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
-        {
-            rc = proc_setup_bars_get_range_attrs(
-                &(io_smp_chip.chip->this_chip),
-                PROC_SETUP_BARS_ATTR_ID_FN,
-                &f_near_range_base_addr_attr,
-                NULL,
-                &f_near_range_size_attr,
-                l, 0,
-                common_f_scope_bar_def,
-                io_smp_chip.foreign_near_ranges[l]);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (foreign near, link = %d)",
-                         l);
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for foreign far memory ranges");
-        for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
-        {
-            rc = proc_setup_bars_get_range_attrs(
-                &(io_smp_chip.chip->this_chip),
-                PROC_SETUP_BARS_ATTR_ID_FF,
-                &f_far_range_base_addr_attr,
-                NULL,
-                &f_far_range_size_attr,
-                l, 0,
-                common_f_scope_bar_def,
-                io_smp_chip.foreign_far_ranges[l]);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (foreign far, link = %d)",
-                         l);
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PSI address range");
-        rc = proc_setup_bars_get_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_PSI,
-            &psi_bridge_bar_base_addr_attr,
-            &psi_bridge_bar_en_attr,
-            NULL,
-            0, 0,
-            psi_bridge_bar_def,
-            io_smp_chip.psi_range);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (PSI)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for FSP address range");
-        rc = proc_setup_bars_get_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_FSP,
-            &fsp_bar_base_addr_attr,
-            &fsp_bar_en_attr,
-            &fsp_bar_size_attr,
-            0, 0,
-            fsp_bar_def,
-            io_smp_chip.fsp_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (FSP)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for FSP MMIO mask");
-        rc = proc_setup_bars_get_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_FSP_MMIO,
-            NULL,
-            NULL,
-            &fsp_mmio_mask_size_attr,
-            0, 0,
-            fsp_mmio_mask_def,
-            io_smp_chip.fsp_mmio_mask_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_addrs (FSP MMIO)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for INTP address range");
-        rc = proc_setup_bars_get_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_INTP,
-            &intp_bar_base_addr_attr,
-            &intp_bar_en_attr,
-            NULL,
-            0, 0,
-            intp_bar_def,
-            io_smp_chip.intp_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (INTP)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for NX MMIO address range");
-        rc = proc_setup_bars_get_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_NX,
-            &nx_mmio_bar_base_addr_attr,
-            &nx_mmio_bar_en_attr,
-            &nx_mmio_bar_size_attr,
-            0, 0,
-            nx_mmio_bar_def,
-            io_smp_chip.nx_mmio_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (NX)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for AS MMIO address range");
-        rc = proc_setup_bars_get_range_attrs(
-            &(io_smp_chip.chip->this_chip),
-            PROC_SETUP_BARS_ATTR_ID_AS,
-            &as_mmio_bar_base_addr_attr,
-            &as_mmio_bar_en_attr,
-            &as_mmio_bar_size_attr,
-            0, 0,
-            as_mmio_bar_def,
-            io_smp_chip.as_mmio_range);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (AS)");
-            break;
-        }
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for NPU MMIO address ranges");
-        for (uint8_t u = 0;
-             (u < PROC_SETUP_BARS_NPU_NUM_UNITS) && (rc.ok());
-             u++)
-        {
-            for (uint8_t r = 0;
-                 r < PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT;
-                 r++)
-            {
-                rc = proc_setup_bars_get_range_attrs(
-                    &(io_smp_chip.chip->this_chip),
-                    PROC_SETUP_BARS_ATTR_ID_NPU,
-                    &npu_mmio_bar_base_addr_attr,
-                    &npu_mmio_bar_en_attr,
-                    &npu_mmio_bar_size_attr,
-                    u, r,
-                    npu_mmio_bar_def,
-                    io_smp_chip.npu_mmio_ranges[u][r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (NPU MMIO, unit = %d, range=%d)",
-                             u, r);
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-
-        FAPI_DBG("proc_setup_bars_get_bar_attrs: Querying base address/size attributes for PCIe address ranges");
-        for (uint8_t u = 0;
-             (u < PROC_SETUP_BARS_PCIE_NUM_UNITS) && (rc.ok());
-             u++)
-        {
-            for (uint8_t r = 0;
-                 r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT;
-                 r++)
-            {
-                rc = proc_setup_bars_get_range_attrs(
-                    &(io_smp_chip.chip->this_chip),
-                    PROC_SETUP_BARS_ATTR_ID_PCIE,
-                    &pcie_mmio_bar_base_addr_attr,
-                    &pcie_mmio_bar_en_attr,
-                    &pcie_mmio_bar_size_attr,
-                    u, r,
-                    ((PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[r])?
-                     (pcie_mmio_bar_def):
-                     (pcie_phb_bar_def)),
-                    io_smp_chip.pcie_ranges[u][r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_get_bar_attrs: Error from proc_setup_bars_get_range_attrs (PCIE, unit = %d, range=%d)",
-                             u, r);
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_setup_bars_get_bar_attrs: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to call all chip attribute query functions
-//           (fabric configuration/node/position/BARs)
-// parameters: i_proc_chip => pointer to HWP input structure for this chip
-//             io_smp_chip => fully specified structure encapsulating
-//                            single chip in SMP topology
-// returns: FAPI_RC_SUCCESS if all attribute reads are successful & values
-//              are valid,
-//          else failing return code from attribute query function
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_process_chip(
-    proc_setup_bars_proc_chip* i_proc_chip,
-    proc_setup_bars_smp_chip& io_smp_chip)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint8_t pcie_enabled;
-    uint8_t nx_enabled;
-    uint8_t nv_present;
-    uint8_t init_group_as_chip;
-    uint8_t dual_capp_present;
-
-    // mark function entry
-    FAPI_DBG("proc_setup_bars_process_chip: Start");
-
-    do
-    {
-        // set HWP input pointer
-        io_smp_chip.chip = i_proc_chip;
-
-        // display target information for this chip
-        FAPI_DBG("proc_setup_bars_process_chip: Target: %s",
-                 io_smp_chip.chip->this_chip.toEcmdString());
-
-        // determine number of PHBs
-        FAPI_DBG("proc_setup_bars_process_chip: Querying PHB configuration");
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_NUM_PHB,
-                           &(io_smp_chip.chip->this_chip),
-                           io_smp_chip.num_phb);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_NUM_PHB");
-            break;
-        }
-
-        // get PCIe/DSMP mux attributes
-        FAPI_DBG("proc_setup_bars_process_chip: Querying PCIe/DSMP mux attribute");
-        rc = proc_fab_smp_get_pcie_dsmp_mux_attrs(&(io_smp_chip.chip->this_chip),
-                                                  io_smp_chip.pcie_not_f_link);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_pcie_dsmp_mux_attrs");
-            break;
-        }
-
-        // get node ID attribute
-        FAPI_DBG("proc_setup_bars_process_chip: Querying node ID attribute");
-        rc = proc_fab_smp_get_node_id_attr(&(io_smp_chip.chip->this_chip),
-                                           io_smp_chip.node_id);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_node_id_attr");
-            break;
-        }
-
-        // get chip ID attribute
-        FAPI_DBG("proc_setup_bars_process_chip: Querying chip ID attribute");
-        rc = proc_fab_smp_get_chip_id_attr(&(io_smp_chip.chip->this_chip),
-                                           io_smp_chip.chip_id);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error from proc_fab_smp_get_chip_id_attr");
-            break;
-        }
-
-        // query NX partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_NX_ENABLE,
-                           &(io_smp_chip.chip->this_chip),
-                           nx_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_NX_ENABLE");
-            break;
-        }
-
-        // query PCIE partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
-                           &(io_smp_chip.chip->this_chip),
-                           pcie_enabled);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_PROC_PCIE_ENABLE");
-            break;
-        }
-
-        io_smp_chip.nx_enabled =
-            (nx_enabled == fapi::ENUM_ATTR_PROC_NX_ENABLE_ENABLE);
-
-        io_smp_chip.pcie_enabled =
-            (pcie_enabled == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE);
-
-        // configure group BARs to cover chip ranges?
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS,
-                           &(io_smp_chip.chip->this_chip),
-                           init_group_as_chip);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_INIT_GROUP_BARS_AS_CHIP_BARS");
-            break;
-        }
-        io_smp_chip.init_group_as_chip = (init_group_as_chip != 0);
-
-        // get NV link presence attribute
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_NV_PRESENT,
-                           &(io_smp_chip.chip->this_chip),
-                           nv_present);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_NV_PRESENT");
-            break;
-        }
-        io_smp_chip.nv_present = (nv_present != 0);
-
-        // get dual CAPP presence attribute
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT,
-                           &(io_smp_chip.chip->this_chip),
-                           dual_capp_present);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error querying ATTR_CHIP_EC_FEATURE_DUAL_CAPP_PRESENT");
-            break;
-        }
-        io_smp_chip.dual_capp_present = (dual_capp_present != 0);
-
-        // get BAR attributes
-        rc = proc_setup_bars_get_bar_attrs(io_smp_chip);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_process_chip: Error from proc_setup_bars_get_bar_attrs");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_setup_bars_process_chip: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: insert chip structure into proper position within SMP model based
-//           on its fabric node/chip ID
-//           chip non-mirrored/mirrored range information will be merged
-//           with those of its enclosing node
-// parameters: i_smp_chip => structure encapsulating single chip in SMP topology
-//             io_smp     => structure encapsulating full SMP
-// returns: FAPI_RC_SUCCESS if insertion is successful and merged node ranges
-//              are valid,
-//          RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails,
-//          RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
-//              fabric node/chip IDs are detected
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_insert_chip(
-    proc_setup_bars_smp_chip& i_smp_chip,
-    proc_setup_bars_smp_system& io_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // node/chip ID
-    proc_fab_smp_node_id node_id = i_smp_chip.node_id;
-    proc_fab_smp_chip_id chip_id = i_smp_chip.chip_id;
-
-    // mark function entry
-    FAPI_DBG("proc_setup_bars_insert_chip: Start");
-
-    do
-    {
-        FAPI_DBG("proc_setup_bars_insert_chip: Inserting n%d p%d",
-                 node_id, chip_id);
-
-        // search to see if node structure already exists for the node ID
-        // associated with this chip
-        std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator
-            n_iter;
-        n_iter = io_smp.nodes.find(node_id);
-        // no matching node found, create one
-        if (n_iter == io_smp.nodes.end())
-        {
-            FAPI_DBG("proc_setup_bars_insert_chip: No matching node found, inserting new node structure");
-            proc_setup_bars_smp_node n;
-            std::pair<
-                std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator,
-                bool> ret;
-            ret = io_smp.nodes.insert(
-                std::pair<proc_fab_smp_node_id, proc_setup_bars_smp_node>
-                (node_id, n));
-            n_iter = ret.first;
-            if (!ret.second)
-            {
-                FAPI_ERR("proc_setup_bars_insert_chip: Error encountered adding node to SMP map");
-                const fapi::Target & TARGET = i_smp_chip.chip->this_chip;
-                const proc_fab_smp_node_id & NODE_ID = node_id;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR);
-                break;
-            }
-        }
-
-        // search to see if match exists in this node for the chip ID associated
-        // with this chip
-        std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator
-            p_iter;
-        p_iter = io_smp.nodes[node_id].chips.find(chip_id);
-        // matching chip ID & node ID already found, flag an error
-        if (p_iter != io_smp.nodes[node_id].chips.end())
-        {
-            FAPI_ERR("proc_setup_bars_insert_chip: Duplicate fabric node ID / chip ID found");
-            const fapi::Target & TARGET1 = i_smp_chip.chip->this_chip;
-            const fapi::Target & TARGET2 = p_iter->second.chip->this_chip;
-            const proc_fab_smp_node_id & NODE_ID = node_id;
-            const proc_fab_smp_chip_id & CHIP_ID = chip_id;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR);
-            break;
-        }
-        // insert chip into SMP
-        io_smp.nodes[node_id].chips[chip_id] = i_smp_chip;
-
-        // update node address regions
-        i_smp_chip.non_mirrored_range.print();
-        io_smp.nodes[node_id].non_mirrored_range.print();
-        io_smp.nodes[node_id].non_mirrored_range.merge(io_smp.nodes[node_id].chips[chip_id].non_mirrored_range);
-        io_smp.nodes[node_id].non_mirrored_range.print();
-
-        i_smp_chip.mirrored_range.print();
-        io_smp.nodes[node_id].mirrored_range.print();
-        io_smp.nodes[node_id].mirrored_range.merge(io_smp.nodes[node_id].chips[chip_id].mirrored_range);
-        io_smp.nodes[node_id].mirrored_range.print();
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_setup_bars_insert_chip: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to process all HWP input structures and build
-//           SMP data structure
-// parameters: i_proc_chips => vector of HWP input structures (one entry per
-//                             chip in SMP)
-//             io_smp       => fully specified structure encapsulating full SMP
-// returns: FAPI_RC_SUCCESS if all processing is successful,
-//          else failing return code from chip processing/insertion wrapper
-//              functions
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_process_chips(
-    std::vector<proc_setup_bars_proc_chip>& i_proc_chips,
-    proc_setup_bars_smp_system& io_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_setup_bars_process_chips: Start");
-
-    do
-    {
-        // loop over all chips passed from platform to HWP
-        std::vector<proc_setup_bars_proc_chip>::iterator c_iter;
-        for (c_iter = i_proc_chips.begin();
-             c_iter != i_proc_chips.end();
-             c_iter++)
-        {
-            // process platform provided data in chip argument,
-            // query chip specific attributes
-            proc_setup_bars_smp_chip smp_chip;
-            rc = proc_setup_bars_process_chip(&(*c_iter),
-                                              smp_chip);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_process_chips: Error from proc_setup_bars_process_chip");
-                break;
-            }
-
-            // insert chip into SMP data structure given node & chip ID
-            rc = proc_setup_bars_insert_chip(smp_chip,
-                                             io_smp);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_process_chips: Error from proc_setup_bars_insert_chip");
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // perform final adjustment on node specific resources once
-        // all chips have been processed
-        std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter;
-        for (n_iter = io_smp.nodes.begin();
-             n_iter != io_smp.nodes.end();
-             n_iter++)
-        {
-            FAPI_DBG("Performing final adjustment on n%d", n_iter->first);
-
-            // update node address ranges (non-mirrored & mirrored)
-            FAPI_DBG("proc_setup_bars_process_chips: Ranges after merging:");
-            n_iter->second.non_mirrored_range.print();
-            n_iter->second.mirrored_range.print();
-
-            // update node address ranges (non-mirrored & mirrored) to
-            // ensure ranges are power of 2 aligned
-            FAPI_DBG("proc_setup_bars_process_chips: Node %d ranges after power of two alignment:",
-                     n_iter->first);
-            if (n_iter->second.non_mirrored_range.enabled &&
-                !n_iter->second.non_mirrored_range.is_power_of_2())
-            {
-                n_iter->second.non_mirrored_range.round_next_power_of_2();
-            }
-            n_iter->second.non_mirrored_range.print();
-
-            if (n_iter->second.mirrored_range.enabled &&
-                !n_iter->second.mirrored_range.is_power_of_2())
-            {
-                n_iter->second.mirrored_range.round_next_power_of_2();
-            }
-            n_iter->second.mirrored_range.print();
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_setup_bars_process_chips: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to write HW BAR register given address range
-//           structure and register definition structure
-// parameters: i_target      => chip target
-//             i_scom_addr   => BAR SCOM address
-//             i_bar_reg_def => structure defining rules to format address
-//                              range content into register layout
-//             i_addr_range  => structure defining BAR address range
-//                              (enable/base/size)
-// returns: FAPI_RC_SUCCESS if register write is successful,
-//          RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF if BAR register definition
-//              structure is invalid,
-//          RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size
-//              translation is unsuccessful,
-//          else failing return code from SCOM/data buffer manipulation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_common_write_bar_reg(
-    const fapi::Target& i_target,
-    const uint32_t& i_scom_addr,
-    const proc_setup_bars_bar_reg_def& i_bar_reg_def,
-    const proc_setup_bars_addr_range& i_addr_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    // BAR register data buffer
-    ecmdDataBufferBase bar_data(64);
-    ecmdDataBufferBase bar_data_mask(64);
-    ecmdDataBufferBase size_data(64);
-    ecmdDataBufferBase static_data(64);
-    ecmdDataBufferBase static_data_mask(64);
-
-    FAPI_DBG("proc_setup_bars_common_write_bar_reg: Start");
-    do
-    {
-        // write base address
-        if (i_bar_reg_def.has_base)
-        {
-            // previous checking ensures zeroes for all non-implemented bits
-            rc_ecmd |= bar_data.setDoubleWord(0, i_addr_range.base_addr);
-            // shift position to proper location in register
-            if (i_bar_reg_def.base_shift == PROC_SETUP_BARS_SHIFT_LEFT)
-            {
-                rc_ecmd |= bar_data.shiftLeft(i_bar_reg_def.base_shift_amount);
-            }
-            else if (i_bar_reg_def.base_shift == PROC_SETUP_BARS_SHIFT_RIGHT)
-            {
-                rc_ecmd |= bar_data.shiftRight(i_bar_reg_def.base_shift_amount);
-            }
-            else if (i_bar_reg_def.base_shift != PROC_SETUP_BARS_SHIFT_NONE)
-            {
-                FAPI_ERR("proc_setup_bars_common_write_bar_reg: Invalid base shift value in register definition");
-                const fapi::Target & TARGET = i_target;
-                const uint32_t & SCOM_ADDR = i_scom_addr;
-                const uint64_t & BASE_ADDR = i_addr_range.base_addr;
-                const bool & ENABLED = i_addr_range.enabled;
-                const uint64_t & SIZE = i_addr_range.size;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF);
-                break;
-            }
-            // set mask
-            rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.base_start_bit,
-                                            (i_bar_reg_def.base_end_bit -
-                                             i_bar_reg_def.base_start_bit + 1));
-        }
-
-        // write enable bit
-        if (i_bar_reg_def.has_enable)
-        {
-            rc_ecmd |= bar_data.writeBit(i_bar_reg_def.enable_bit,
-                                         i_addr_range.enabled ? 1 : 0);
-            rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.enable_bit);
-        }
-
-        // write size field
-        if (i_bar_reg_def.has_size)
-        {
-            // encoded size value for register programming
-            std::map<uint64_t, uint64_t>::const_iterator s;
-            uint64_t size_xlate;
-            // translate size into register encoding
-            s = i_bar_reg_def.xlate_map->find(i_addr_range.size);
-            if (s == i_bar_reg_def.xlate_map->end())
-            {
-                FAPI_ERR("proc_setup_bars_common_write_bar_reg: Unsupported BAR size 0x%016llX",
-                         i_addr_range.size);
-                const fapi::Target & TARGET = i_target;
-                const uint32_t & SCOM_ADDR = i_scom_addr;
-                const uint64_t & BASE_ADDR = i_addr_range.base_addr;
-                const bool & ENABLED = i_addr_range.enabled;
-                const uint64_t & SIZE = i_addr_range.size;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_SIZE_XLATE_ERR);
-                break;
-            }
-            size_xlate = s->second;
-
-            rc_ecmd |= size_data.setDoubleWord(0, size_xlate);
-            rc_ecmd |= size_data.shiftLeft(63 - i_bar_reg_def.size_end_bit);
-            rc_ecmd |= bar_data.merge(size_data);
-            rc_ecmd |= bar_data_mask.setBit(i_bar_reg_def.size_start_bit,
-                                            (i_bar_reg_def.size_end_bit -
-                                             i_bar_reg_def.size_start_bit + 1));
-        }
-
-        // merge static data & mask
-        rc_ecmd |= static_data.setDoubleWord(
-            0,
-            i_bar_reg_def.static_data);
-        rc_ecmd |= static_data_mask.setDoubleWord(
-            0,
-            i_bar_reg_def.static_data_mask);
-
-        rc_ecmd |= bar_data.merge(static_data);
-        rc_ecmd |= bar_data_mask.merge(static_data_mask);
-
-        // check buffer manipulation return codes
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_setup_bars_common_write_bar_reg: Error 0x%X setting up BAR data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write BAR register with updated content
-        rc = fapiPutScomUnderMask(i_target,
-                                  i_scom_addr,
-                                  bar_data,
-                                  bar_data_mask);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_common_write_bar_reg: fapiPutScomUnderMask error (%08X)",
-                     i_scom_addr);
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_common_write_bar_reg: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: write L3 BAR attributes (consumed by winkle image creation
-//           procedures) specific to enabled local chip
-//           non-mirrored/mirrored memory ranges
-// parameters: i_target                => chip target
-//             i_is_non_mirrored_range => boolean idenitfying range type
-//                                        (true=non-mirrored, false=mirrored)
-//             i_addr_range            => structure representing chip
-//                                        non-mirrored/mirrored range
-// returns: FAPI_RC_SUCCESS if attribute writes are successful,
-//          RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if logical->physical size
-//              translation is unsuccessful,
-//          else failing return code from attribute/data buffer manipulation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_l3_write_local_chip_memory_bar_attr(
-    const fapi::Target* i_target,
-    const bool i_is_non_mirrored_range,
-    const proc_setup_bars_addr_range& i_addr_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    // BAR1 register data buffer
-    ecmdDataBufferBase bar_data(64);
-    ecmdDataBufferBase bar_size_data(64);
-    uint64_t bar_attr_data;
-
-    FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Start");
-    do
-    {
-        // previous checking ensures zeroes for all non-implemented bits
-        rc_ecmd |= bar_data.setDoubleWord(0, i_addr_range.base_addr);
-        rc_ecmd |= bar_data.shiftLeft(L3_BAR12_BASE_ADDR_LEFT_SHIFT_AMOUNT);
-
-        // encoded size value for register programming
-        std::map<uint64_t, uint64_t>::const_iterator s;
-        uint64_t size_xlate;
-        // translate size into register encoding
-        s = proc_setup_bars_nf_bar_size::xlate_map.find(i_addr_range.size);
-        if (s == proc_setup_bars_nf_bar_size::xlate_map.end())
-        {
-            FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Unsupported BAR size 0x%016llX",
-                     i_addr_range.size);
-            const fapi::Target & TARGET = *i_target;
-            const uint32_t & SCOM_ADDR = EX_L3_BAR1_REG_0x1001080B;
-            const uint64_t & BASE_ADDR = i_addr_range.base_addr;
-            const bool & ENABLED = i_addr_range.enabled;
-            const uint64_t & SIZE = i_addr_range.size;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_SETUP_BARS_SIZE_XLATE_ERR);
-            break;
-        }
-        size_xlate = s->second;
-        rc_ecmd |= bar_size_data.setDoubleWord(0, size_xlate);
-        rc_ecmd |= bar_size_data.shiftLeft(63 - L3_BAR12_SIZE_END_BIT);
-        rc_ecmd |= bar_data.merge(bar_size_data);
-
-        // enable bit only in BAR2
-        if (!i_is_non_mirrored_range)
-        {
-            rc_ecmd |= bar_data.writeBit(L3_BAR2_ENABLE_BIT,
-                                         i_addr_range.enabled ? 1 : 0);
-        }
-
-        // check buffer manipulation return codes
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error 0x%X setting up BAR data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // set data for attribute push
-        bar_attr_data = bar_data.getDoubleWord(0);
-
-        if (i_is_non_mirrored_range)
-        {
-            // L3 BAR1 (non-mirrored)
-            FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Setting ATTR_PROC_L3_BAR1_REG = %016llX",
-                     bar_attr_data);
-            rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR1_REG,
-                               i_target,
-                               bar_attr_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error setting ATTR_PROC_L3_BAR1_REG");
-                break;
-            }
-        }
-        else
-        {
-            // L3 BAR2 (mirrored)
-            FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Setting ATTR_PROC_L3_BAR2_REG = %016llX",
-                     bar_attr_data);
-            rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR2_REG,
-                               i_target,
-                               bar_attr_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_l3_write_local_chip_memory_bar_attr: Error setting ATTR_PROC_L3_BAR2_REG");
-                break;
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_l3_write_local_chip_memory_bar_attr: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write PCIe BARs specific to enabled local
-//           chip non-mirrored/mirrored memory ranges
-// parameters: i_target             => chip target
-//             i_num_phb            => number of PHBs
-//             i_non_mirrored_range => structure representing chip non-mirrored
-//                                     address range
-//             i_mirrored_range     => structure representing chip mirrored
-//                                     address range
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_pcie_write_local_chip_memory_bars(
-    const fapi::Target& i_target,
-    const uint8_t i_num_phb,
-    const proc_setup_bars_addr_range& i_non_mirrored_range,
-    const proc_setup_bars_addr_range& i_mirrored_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Start");
-    // loop over all units
-    for (uint8_t u = 0;
-         u < i_num_phb;
-         u++)
-    {
-        if (i_non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Writing PCIe %d Nodal Non-Mirrored BAR register",
-                     u);
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_target,
-                PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[u],
-                common_nf_scope_bar_reg_def,
-                i_non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_pcie_write_local_chip_memory_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-        if (i_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: Writing PCIe %d Nodal Mirrored BAR register",
-                     u);
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_target,
-                PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[u],
-                common_nf_scope_bar_reg_def,
-                i_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_pcie_write_local_chip_memory_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-    }
-
-    FAPI_DBG("proc_setup_bars_pcie_write_local_chip_memory_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: write L3 BAR attributes (consumed by winkle image creation
-//           procedures) specific to enabled local node
-//           non-mirrored/mirrored memory ranges
-// parameters: i_target                => chip target
-//             i_is_non_mirrored_range => boolean idenitfying range type
-//                                        (true=non-mirrored, false=mirrored)
-//             i_node_addr_range       => structure representing node
-//                                        non-mirrored/mirrored range
-//             i_chip_addr_range       => structure representing chip
-//                                        non-mirrored/mirrored range
-// returns: FAPI_RC_SUCCESS if attribute writes are successful,
-//          else failing return code from attribute/data buffer manipulation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_l3_write_local_node_memory_bar_attr(
-    const fapi::Target* i_target,
-    const bool i_is_non_mirrored_range,
-    const proc_setup_bars_addr_range& i_node_addr_range,
-    const proc_setup_bars_addr_range& i_chip_addr_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase base(64);
-    ecmdDataBufferBase diff(64);
-    ecmdDataBufferBase mask(64);
-    uint64_t mask_attr = 0x0;
-
-    FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Start");
-
-    do
-    {
-        // retrieve mask register attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_L3_BAR_GROUP_MASK_REG,
-                           i_target,
-                           mask_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error querying ATTR_PROC_L3_BAR_GROUP_MASK_REG");
-            break;
-        }
-        FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Read ATTR_PROC_L3_BAR_GROUP_MASK_REG = %016llX",
-                 mask_attr);
-        // push current value into data buffer
-        rc_ecmd |= mask.setDoubleWord(0, mask_attr);
-
-        // set group mask based on first difference between
-        // node start/end addresses
-        uint32_t first_diff_bit = 0;
-        // load base address
-        rc_ecmd |= base.setDoubleWord(0, i_node_addr_range.base_addr);
-        // load end address
-        rc_ecmd |= diff.setDoubleWord(0, i_node_addr_range.end_addr());
-        // XOR base/end address
-        rc_ecmd |= diff.setXor(base, 0, 64);
-
-        // walk range of XOR result over group mask, stop at first 1 found
-        bool match_found = false;
-        for (first_diff_bit = L3_BAR_GROUP_MASK_RA_DIFF_START_BIT;
-             first_diff_bit <= L3_BAR_GROUP_MASK_RA_DIFF_END_BIT;
-             first_diff_bit++)
-        {
-            if (diff.getBit(first_diff_bit))
-            {
-                match_found = true;
-                break;
-            }
-        }
-
-        if (match_found)
-        {
-            // set all group mask bits to a 1, starting from first bit which
-            // was found to be different, to the end of the mask range
-            uint32_t mask_set_start_bit = (i_is_non_mirrored_range)?
-                L3_BAR_GROUP_MASK_NON_MIRROR_MASK_START_BIT:
-                L3_BAR_GROUP_MASK_MIRROR_MASK_START_BIT;
-
-            mask_set_start_bit += (first_diff_bit-
-                                   L3_BAR_GROUP_MASK_RA_DIFF_START_BIT);
-
-            uint32_t mask_set_num_bits = (i_is_non_mirrored_range)?
-                L3_BAR_GROUP_MASK_NON_MIRROR_MASK_END_BIT:
-                L3_BAR_GROUP_MASK_MIRROR_MASK_END_BIT;
-
-            mask_set_num_bits -= (mask_set_start_bit-1);
-
-            rc_ecmd |= mask.setBit(mask_set_start_bit,
-                                   mask_set_num_bits);
-        }
-
-        // enable bit only for mirorred region
-        if (!i_is_non_mirrored_range)
-        {
-            rc_ecmd |= mask.writeBit(L3_BAR_GROUP_MASK_MIRROR_ENABLE_BIT,
-                                     i_node_addr_range.enabled ? 1 : 0);
-        }
-
-        // check buffer manipulation return codes
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error 0x%X setting up BAR mask data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // push current data buffer state back into attribute
-        mask_attr = mask.getDoubleWord(0);
-        FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: Setting ATTR_PROC_L3_BAR_GROUP_MASK_REG = %016llX",
-                 mask_attr);
-        rc = FAPI_ATTR_SET(ATTR_PROC_L3_BAR_GROUP_MASK_REG,
-                           i_target,
-                           mask_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error setting ATTR_PROC_L3_BAR_GROUP_MASK_REG");
-            break;
-        }
-
-        // if no memory is installed on the local chip, fill the shared
-        // BAR address with the node base
-        if (!i_chip_addr_range.enabled)
-        {
-            // clear size mask
-            proc_setup_bars_addr_range base_addr_range = i_node_addr_range;
-            base_addr_range.size = PROC_SETUP_BARS_SIZE_4_GB;
-
-            rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr(
-                i_target,
-                i_is_non_mirrored_range,
-                base_addr_range);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_l3_write_local_node_memory_bar_attr: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr");
-                break;
-            }
-        }
-    } while(0);
-
-
-    FAPI_DBG("proc_setup_bars_l3_write_local_node_memory_bar_attr: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write PCIe BARs specific to enabled local
-//           node non-mirrored/mirrored memory ranges
-// parameters: i_target             => chip target
-//             i_num_phb            => number of PHBs
-//             i_non_mirrored_range => structure representing node non-mirrored
-//                                     address range
-//             i_mirrored_range     => structure representing node mirrored
-//                                     address range
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_pcie_write_local_node_memory_bars(
-    const fapi::Target& i_target,
-    const uint8_t i_num_phb,
-    const proc_setup_bars_addr_range& i_non_mirrored_range,
-    const proc_setup_bars_addr_range& i_mirrored_range)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Start");
-    // loop over all units
-    for (uint8_t u = 0;
-         u < i_num_phb;
-         u++)
-    {
-        if (i_non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Writing PCIe %d Group Non-Mirrored BAR register",
-                     u);
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_target,
-                PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[u],
-                common_nf_scope_bar_reg_def,
-                i_non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_pcie_write_local_node_memory_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-        if (i_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: Writing PCIe %d Group Mirrored BAR register",
-                     u);
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_target,
-                PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[u],
-                common_nf_scope_bar_reg_def,
-                i_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_pcie_write_local_node_memory_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-    }
-
-    FAPI_DBG("proc_setup_bars_pcie_write_local_node_memory_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write PCIe BARs specific to enabled local
-//           chip near/far foreign memory ranges
-//           NOTE: only links which are marked for processing will be acted on
-// parameters: i_target              => chip target
-//             i_num_phb             => number of PHBs
-//             i_process_links       => array of boolean values dictating which
-//                                      links should be acted on (one per link)
-//             i_foreign_near_ranges => array of structures representing
-//                                      near foreign address range (one per link)
-//             i_foreign_far_ranges  => array of structures representing
-//                                      far foreign address range (one per link)
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_pcie_write_foreign_memory_bars(
-    const fapi::Target& i_target,
-    const uint8_t i_num_phb,
-    const bool i_process_links[PROC_FAB_SMP_NUM_F_LINKS],
-    const proc_setup_bars_addr_range i_foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS],
-    const proc_setup_bars_addr_range i_foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS])
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Start");
-
-    // loop over all units
-    for (uint8_t u = 0;
-         (u < i_num_phb) && (rc.ok());
-         u++)
-    {
-        // process ranges
-        for (uint8_t r = 0;
-             (r < PROC_FAB_SMP_NUM_F_LINKS) && (rc.ok());
-             r++)
-        {
-            if (i_foreign_near_ranges[r].enabled && i_process_links[r])
-            {
-                FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Writing PCIe %d Foreign F%d Near BAR register",
-                         u, r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_target,
-                    PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[u][r],
-                    common_f_scope_bar_reg_def,
-                    i_foreign_near_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_pcie_write_foreign_memory_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-            if (i_foreign_far_ranges[r].enabled && i_process_links[r])
-            {
-                FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: Writing PCIe %d Foreign F%d Far BAR register",
-                         u, r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_target,
-                    PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[u][r],
-                    common_f_scope_bar_reg_def,
-                    i_foreign_far_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_pcie_write_foreign_memory_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-        }
-    }
-
-    FAPI_DBG("proc_setup_bars_pcie_write_foreign_memory_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write enabled PCIe IO BARs
-// parameters: i_target       => chip target
-//             i_num_phb      => number of PHBs
-//             io_addr_ranges => 2D array of address range structures
-//                               encapsulating attribute values
-//                               (first dimension = unit, second dimension =
-//                                links per unit)
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function or
-//              data buffer manipulation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_pcie_write_io_bar_regs(
-    const fapi::Target& i_target,
-    const uint8_t i_num_phb,
-    const proc_setup_bars_addr_range addr_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT])
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Start");
-    // loop over all units
-    for (uint8_t u = 0;
-         u < i_num_phb;
-         u++)
-    {
-        // enable bit/mask bit per range
-        ecmdDataBufferBase enable_data(64);
-        ecmdDataBufferBase enable_mask(64);
-
-        // loop over all ranges
-        for (uint8_t r = 0;
-             r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT;
-             r++)
-        {
-            if (addr_ranges[u][r].enabled)
-            {
-                // MMIO range (BAR + mask)
-                if (PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[r])
-                {
-                    // write BAR register
-                    FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d MMIO BAR%d register",
-                             u, r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_target,
-                        PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[u][r],
-                        pcie_mmio_bar_reg_def,
-                        addr_ranges[u][r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-
-                    // write BAR mask register
-                    FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d MMIO BAR%d Mask register",
-                             u, r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_target,
-                        PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[u][r],
-                        pcie_mmio_bar_mask_reg_def,
-                        addr_ranges[u][r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-                }
-                // PHB range (only BAR, mask is implied)
-                else
-                {
-                    for (uint8_t i = 0;
-                         i < PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE;
-                         i++)
-                    {
-                        FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: Writing PCIe %d PHB BAR (%s) register",
-                                 u, (i == 0)?("Nest"):("PCIe"));
-                        rc = proc_setup_bars_common_write_bar_reg(
-                            i_target,
-                            PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[u][i],
-                            pcie_phb_bar_reg_def,
-                            addr_ranges[u][r]);
-                        if (!rc.ok())
-                        {
-                            FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg");
-                            break;
-                        }
-                    }
-                    if (!rc.ok())
-                    {
-                        break;
-                    }
-                }
-                // set enable bit data/mask
-                rc_ecmd |= enable_data.setBit(
-                    PROC_SETUP_BARS_PCIE_BAR_EN_BIT[r]);
-                rc_ecmd |= enable_mask.setBit(
-                    PROC_SETUP_BARS_PCIE_BAR_EN_BIT[r]);
-                // check buffer manipulation return codes
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error 0x%X setting up BAR Enable data buffer",
-                             rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        if (enable_data.getDoubleWord(0) != 0x0ULL)
-        {
-            // set static data field with BAR enable bits
-            proc_setup_bars_bar_reg_def pcie_bar_en_reg_def =
-            {
-                false,                         // base: other reg
-                PROC_SETUP_BARS_SHIFT_NONE,
-                0,
-                0,
-                0,
-                false,                         // enable: static data
-                0,
-                false,                         // size: other reg
-                0,
-                0,
-                NULL,
-                enable_data.getDoubleWord(0),
-                enable_mask.getDoubleWord(0)
-            };
-            proc_setup_bars_addr_range pcie_bar_en_dummy_range;
-
-            // write BAR enable register (do last, when all unit BAR content is set)
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_target,
-                PROC_SETUP_BARS_PCIE_BAR_EN_REGS[u],
-                pcie_bar_en_reg_def,
-                pcie_bar_en_dummy_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            // if enabling BARs, pull ETU out of reset
-            ecmdDataBufferBase etu_reset(64);
-            rc = fapiPutScom(i_target,
-                             PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[u],
-                             etu_reset);
-            if (!rc.ok())
-            {
-               FAPI_ERR("proc_setup_bars_pcie_write_io_bar_regs: Error from fapiPutScom (PCIE%d_ETU_RESET_0x%08X)",
-                        u, PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[u]);
-               break;
-            }
-        }
-    }
-
-    FAPI_DBG("proc_setup_bars_pcie_write_io_bar_regs: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write all BARs tied to local chip region
-//           (non-mirrored/mirrored/MMIO regions)
-// parameters: i_smp_chip => structure encapsulating single chip in SMP topology
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-//
-// Local chip region BARs:
-//
-// PSI/FSP
-//   PSI Bridge BAR                           (PSI_BRIDGE_BAR_0x0201090A)
-//   FSP BAR                                  (PSI_FSP_BAR_0x0201090B)
-//   FSP Memory Mask                          (PSI_FSP_MMR_0x0201090C)
-//   FSP MMIO Mask                            (PSI_BRIDGE_STATUS_CTL_0x0201090E)
-//
-// INTP
-//   INTP BAR                                 (ICP_BAR_0x020109CA)
-//
-// L3 (transmitted via attributes)
-//   L3 BAR1 (Non-Mirrored)                   (EX_L3_BAR1_0x1001080B)
-//   L3 BAR2 (Mirrored)                       (EX_L3_BAR2_0x10010813)
-//
-// NX
-//   NX MMIO BAR                              (NX_MMIO_BAR_0x0201308D)
-//   NX CXA0 Nodal Non-Mirrored BAR           (NX_APC_NODAL_BAR0_0x0201302D)
-//   NX CXA1 Nodal Non-Mirrored BAR           (NX_CXA1_APC_NODAL_BAR0_0x020131AD)
-//   NX Nodal Non-Mirrored BAR                (NX_NODAL_BAR0_0x02013095)
-//   NX CXA0 Nodal Mirrored BAR               (NX_APC_NODAL_BAR1_0x0201302E)
-//   NX CXA1 Nodal Mirrored BAR               (NX_CXA1_APC_NODAL_BAR1_0x020131AE)
-//   NX Nodal Mirrored BAR                    (NX_NODAL_BAR1_0x02013096)
-//
-// NPU
-//   NPU0 Nodal Non-Mirrored BAR              (NPU0_NODAL_BAR0_0x08013C04)
-//   NPU0 Nodal Mirrored BAR                  (NPU0_NODAL_BAR1_0x08013C05)
-//   NPU1 Nodal Non-Mirrored BAR              (NPU1_NODAL_BAR0_0x08013C44)
-//   NPU1 Nodal Mirrored BAR                  (NPU1_NODAL_BAR1_0x08013C45)
-//   NPU2 Nodal Non-Mirrored BAR              (NPU2_NODAL_BAR0_0x08013D04)
-//   NPU2 Nodal Mirrored BAR                  (NPU2_NODAL_BAR1_0x08013D05)
-//   NPU3 Nodal Non-Mirrored BAR              (NPU3_NODAL_BAR0_0x08013D44)
-//   NPU3 Nodal Mirrored BAR                  (NPU3_NODAL_BAR1_0x08013D45)
-//
-//   NPU0 MMIO BAR0                           (NPU0_MMIO_BAR0_0x08013C02)
-//   NPU0 MMIO BAR1                           (NPU0_MMIO_BAR1_0x08013C03)
-//   NPU1 MMIO BAR0                           (NPU1_MMIO_BAR0_0x08013C42)
-//   NPU1 MMIO BAR1                           (NPU1_MMIO_BAR1_0x08013C43)
-//   NPU2 MMIO BAR0                           (NPU2_MMIO_BAR0_0x08013D02)
-//   NPU2 MMIO BAR1                           (NPU2_MMIO_BAR1_0x08013D03)
-//   NPU3 MMIO BAR0                           (NPU3_MMIO_BAR0_0x08013D42)
-//   NPU3 MMIO BAR1                           (NPU3_MMIO_BAR1_0x08013D43)
-// 
-// HCA
-//   HCA EN BAR and Range Register            (HCA_EN_BAR_0x0201094A)
-//   HCA EN Mirror BAR and Range Register     (HCA_EN_MIRROR_BAR_0x02010953)
-//   HCA EH BAR and Range Register            (HCA_EH_BAR_0x0201098A)
-//   HCA EH Mirror BAR and Range Register     (HCA_EH_MIRROR_BAR_0x02010993)
-//
-// MCD
-//   MCD Configuration 0 (Non-Mirrored)       (MCD_CN00_0x0201340C)
-//   MCD Configuration 1 (Mirrored)           (MCD_CN01_0x0201340D)
-//
-// PCIe
-//   PCIE0 Nodal Non-Mirrored BAR             (PCIE0_NODAL_BAR0_0x02012010)
-//   PCIE0 Nodal Mirrored BAR                 (PCIE0_NODAL_BAR1_0x02012011)
-//   PCIE0 IO BAR0                            (PCIE0_IO_BAR0_0x02012040)
-//   PCIE0 IO BAR0 Mask                       (PCIE0_IO_MASK0_0x02012043)
-//   PCIE0 IO BAR1                            (PCIE0_IO_BAR1_0x02012041)
-//   PCIE0 IO BAR1 Mask                       (PCIE0_IO_MASK1_0x02012044)
-//   PCIE0 IO BAR2                            (PCIE0_IO_BAR2_0x02012042)
-//   PCIE0 IO BAR Enable                      (PCIE0_IO_BAR_EN_0x02012045)
-//
-//   PCIE1 Nodal Non-Mirrored BAR             (PCIE1_NODAL_BAR0_0x02012410)
-//   PCIE1 Nodal Mirrored BAR                 (PCIE1_NODAL_BAR1_0x02012411)
-//   PCIE1_IO BAR0                            (PCIE1_IO_BAR0_0x02012440)
-//   PCIE1_IO BAR0 Mask                       (PCIE1_IO_MASK0_0x02012443)
-//   PCIE1_IO BAR1                            (PCIE1_IO_BAR1_0x02012441)
-//   PCIE1_IO BAR1 Mask                       (PCIE1_IO_MASK1_0x02012444)
-//   PCIE1_IO BAR2                            (PCIE1_IO_BAR2_0x02012442)
-//   PCIE1_IO BAR Enable                      (PCIE1_IO_BAR_EN_0x02012445)
-//
-//   PCIE2 Nodal Non-Mirrored BAR             (PCIE2_NODAL_BAR0_0x02012810)
-//   PCIE2 Nodal Mirrored BAR                 (PCIE2_NODAL_BAR1_0x02012811)
-//   PCIE2 IO BAR0                            (PCIE2_IO_BAR0_0x02012840)
-//   PCIE2 IO BAR0 Mask                       (PCIE2_IO_MASK0_0x02012843)
-//   PCIE2 IO BAR1                            (PCIE2_IO_BAR1_0x02012841)
-//   PCIE2 IO BAR1 Mask                       (PCIE2_IO_MASK1_0x02012844)
-//   PCIE2 IO BAR2                            (PCIE2_IO_BAR2_0x02012842)
-//   PCIE2 IO BAR Enable                      (PCIE2_IO_BAR_EN_0x02012845)
-//
-//   PCIE3 Nodal Non-Mirrored BAR             (PCIE3_NODAL_BAR0_0x02012C10)
-//   PCIE3 Nodal Mirrored BAR                 (PCIE3_NODAL_BAR1_0x02012C11)
-//   PCIE3 IO BAR0                            (PCIE3_IO_BAR0_0x02012C40)
-//   PCIE3 IO BAR0 Mask                       (PCIE3_IO_MASK0_0x02012C43)
-//   PCIE3 IO BAR1                            (PCIE3_IO_BAR1_0x02012C41)
-//   PCIE3 IO BAR1 Mask                       (PCIE3_IO_MASK1_0x02012C44)
-//   PCIE3 IO BAR2                            (PCIE3_IO_BAR2_0x02012C42)
-//   PCIE3 IO BAR Enable                      (PCIE3_IO_BAR_EN_0x02012C45)
-//
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_write_local_chip_region_bars(
-    proc_setup_bars_smp_chip& i_smp_chip)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Start");
-
-    do
-    {
-        // PSI
-        if (i_smp_chip.psi_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PSI_BRIDGE_BAR_0x0201090A,
-                psi_bridge_bar_reg_def,
-                i_smp_chip.psi_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // FSP
-        if (i_smp_chip.fsp_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing FSP BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PSI_FSP_BAR_0x0201090B,
-                fsp_bar_reg_def,
-                i_smp_chip.fsp_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing FSP Memory Mask register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PSI_FSP_MMR_0x0201090C,
-                fsp_bar_mask_reg_def,
-                i_smp_chip.fsp_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge Status Control register (FSP BAR enable)");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PSI_BRIDGE_STATUS_CTL_0x0201090E,
-                fsp_bar_en_reg_def,
-                i_smp_chip.fsp_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            if (i_smp_chip.fsp_mmio_mask_range.enabled)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing PSI Bridge Status Control register (FSP MMIO mask)");
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    PSI_BRIDGE_STATUS_CTL_0x0201090E,
-                    fsp_mmio_mask_reg_def,
-                    i_smp_chip.fsp_mmio_mask_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-        }
-
-        // INTP
-        if (i_smp_chip.intp_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing INTP BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                ICP_BAR_0x020109CA,
-                intp_bar_reg_def,
-                i_smp_chip.intp_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // NX (MMIO)
-        if (i_smp_chip.nx_mmio_range.enabled && i_smp_chip.nx_enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX MMIO BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_MMIO_BAR_0x0201308D,
-                nx_mmio_bar_reg_def,
-                i_smp_chip.nx_mmio_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing AS MMIO BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_AS_MMIO_BAR_0x0201309E,
-                as_mmio_bar_reg_def,
-                i_smp_chip.as_mmio_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // NX (non-mirrored)
-        if (i_smp_chip.non_mirrored_range.enabled && i_smp_chip.nx_enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA0 APC Nodal Non-Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_APC_NODAL_BAR0_0x0201302D,
-                common_nf_scope_bar_reg_def,
-                i_smp_chip.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            if (i_smp_chip.dual_capp_present)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA1 APC Nodal Non-Mirrored BAR register");
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    NX_CXA1_APC_NODAL_BAR0_0x020131AD,
-                    common_nf_scope_bar_reg_def,
-                    i_smp_chip.non_mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX Nodal Non-Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_NODAL_BAR0_0x02013095,
-                common_nf_scope_bar_reg_def,
-                i_smp_chip.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // NX (mirrored)
-        if (i_smp_chip.mirrored_range.enabled && i_smp_chip.nx_enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA0 APC Nodal Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_APC_NODAL_BAR1_0x0201302E,
-                common_nf_scope_bar_reg_def,
-                i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            if (i_smp_chip.dual_capp_present)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX CXA1 APC Nodal Mirrored BAR register");
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    NX_CXA1_APC_NODAL_BAR1_0x020131AE,
-                    common_nf_scope_bar_reg_def,
-                    i_smp_chip.mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NX Nodal Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_NODAL_BAR1_0x02013096,
-                common_nf_scope_bar_reg_def,
-                i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // NPU (non-mirrored)
-        if (i_smp_chip.non_mirrored_range.enabled && i_smp_chip.nv_present)
-        {
-            for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NPU%d Nodal Non-Mirrored BAR register", u);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    PROC_SETUP_BARS_NPU_CHIP_NON_MIRRORED_BAR[u],
-                    common_nf_scope_bar_reg_def,
-                    i_smp_chip.non_mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-
-        // NPU (mirrored)
-        if (i_smp_chip.mirrored_range.enabled && i_smp_chip.nv_present)
-        {
-            for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NPU%d Nodal Mirrored BAR register", u);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    PROC_SETUP_BARS_NPU_CHIP_MIRRORED_BAR[u],
-                    common_nf_scope_bar_reg_def,
-                    i_smp_chip.mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-
-        // NPU (MMIO)
-        if (i_smp_chip.nv_present)
-        {
-            for (uint8_t u = 0; (u < PROC_SETUP_BARS_NPU_NUM_UNITS); u++)
-            {
-                for (uint8_t r = 0; (r < PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT); r++)
-                {
-                    FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing NPU%d MMIO BAR%d register", u, r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_smp_chip.chip->this_chip,
-                        PROC_SETUP_BARS_NPU_MMIO_BAR[u][r],
-                        npu_mmio_bar_reg_def,
-                        i_smp_chip.npu_mmio_ranges[u][r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-                }
-                if (!rc.ok())
-                {
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-
-        // HCA (non-mirrored)
-        if (i_smp_chip.non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EN BAR and Range (Non-Mirrored) register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                HCA_EN_BAR_0x0201094A,
-                hca_nm_bar_reg_def,
-                i_smp_chip.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EH BAR and Range (Non-Mirrored) register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                HCA_EH_BAR_0x0201098A,
-                hca_nm_bar_reg_def,
-                i_smp_chip.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // HCA (mirrored)
-        if (i_smp_chip.mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EN Mirror BAR and Range (Mirrored) register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                HCA_EN_MIRROR_BAR_0x02010953,
-                hca_m_bar_reg_def,
-                i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing HCA EH Mirror BAR and Range (Mirrored) register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                HCA_EH_MIRROR_BAR_0x02010993,
-                hca_m_bar_reg_def,
-                i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // MCD (non-mirrored)
-        if (i_smp_chip.non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 0 (Non-Mirrored) register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                MCD_CN00_0x0201340C,
-                mcd_nf_bar_reg_def,
-                i_smp_chip.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // MCD (mirrored)
-        if (i_smp_chip.mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing MCD Configuration 1 (Mirrored) register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                MCD_CN01_0x0201340D,
-                mcd_nf_bar_reg_def,
-                i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // L3 (non-mirrored)
-        if (i_smp_chip.non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing L3 BAR1 (Non-Mirrored) attribute");
-            rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr(
-                    &(i_smp_chip.chip->this_chip),
-                    true,
-                    i_smp_chip.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr");
-                break;
-            }
-        }
-
-        // L3 (mirrored)
-        if (i_smp_chip.mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: Writing L3 BAR2 (Mirrored) attribute");
-            rc = proc_setup_bars_l3_write_local_chip_memory_bar_attr(
-                    &(i_smp_chip.chip->this_chip),
-                    false,
-                    i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_l3_write_local_chip_memory_bar_attr");
-                break;
-            }
-        }
-
-        // PCIe (non-mirrored/mirrored)
-        if (i_smp_chip.pcie_enabled)
-        {
-            rc = proc_setup_bars_pcie_write_local_chip_memory_bars(
-                i_smp_chip.chip->this_chip,
-                i_smp_chip.num_phb,
-                i_smp_chip.non_mirrored_range,
-                i_smp_chip.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_local_chip_memory_bars");
-                break;
-            }
-        }
-
-        // PCIe (IO)
-        if (i_smp_chip.pcie_enabled)
-        {
-            rc = proc_setup_bars_pcie_write_io_bar_regs(
-                i_smp_chip.chip->this_chip,
-                i_smp_chip.num_phb,
-                i_smp_chip.pcie_ranges);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_chip_region_bars: Error from proc_setup_bars_pcie_write_io_bar_regs");
-                break;
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_write_local_chip_region_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write all BARs tied to local node region
-//           (non-mirrored/mirrored regions)
-// parameters: i_smp_chip => structure encapsulating single chip in SMP topology
-//             i_smp_node => structure encapsulating node which this chip
-//                           resides in
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-//
-// Local node region BARs:
-//
-// L3 (transmitted via attributes)
-//   L3 BAR Group Mask                        (EX_L3_BAR_GROUP_MASK_0x10010816)
-//
-// NX
-//   NX CXA0 Group Non-Mirorred BAR           (NX_APC_GROUP_BAR0_0x0201302F)
-//   NX CXA1 Group Non-Mirorred BAR           (NX_CXA1_APC_GROUP_BAR0_0x020131AF)
-//   NX Group Non-Mirorred BAR                (NX_GROUP_BAR0_0x02013097)
-//   NX CXA0 Group Mirrored BAR               (NX_APC_GROUP_BAR1_0x02013030)
-//   NX CXA1 Group Mirrored BAR               (NX_CXA1_APC_GROUP_BAR1_0x020131B0)
-//   NX Group Mirrored BAR                    (NX_GROUP_BAR1_0x02013098)
-//
-// NPU
-//   NPU0 Group Non-Mirrored BAR              (NPU0_GROUP_BAR0_0x08013C06)
-//   NPU0 Group Mirrored BAR                  (NPU0_GROUP_BAR1_0x08013C07)
-//   NPU1 Group Non-Mirrored BAR              (NPU1_GROUP_BAR0_0x08013C46)
-//   NPU1 Group Mirrored BAR                  (NPU1_GROUP_BAR1_0x08013C47)
-//   NPU2 Group Non-Mirrored BAR              (NPU2_GROUP_BAR0_0x08013D06)
-//   NPU2 Group Mirrored BAR                  (NPU2_GROUP_BAR1_0x08013D07)
-//   NPU3 Group Non-Mirrored BAR              (NPU3_GROUP_BAR0_0x08013D46)
-//   NPU3 Group Mirrored BAR                  (NPU3_GROUP_BAR1_0x08013D47)
-//
-// PCIe
-//   PCIE0 Group Non-Mirrored BAR             (PCIE0_GROUP_BAR0_0x02012012)
-//   PCIE0 Group Mirrored BAR                 (PCIE0_GROUP_BAR1_0x02012013)
-//
-//   PCIE1 Group Non-Mirrored BAR             (PCIE1_GROUP_BAR0_0x02012412)
-//   PCIE1 Group Mirrored BAR                 (PCIE1_GROUP_BAR1_0x02012413)
-//
-//   PCIE2 Group Non-Mirrored BAR             (PCIE2_GROUP_BAR0_0x02012812)
-//   PCIE2 Group Mirrored BAR                 (PCIE2_GROUP_BAR1_0x02012813)
-//
-//   PCIE3 Group Non-Mirrored BAR             (PCIE3_GROUP_BAR0_0x02012C12)
-//   PCIE3 Group Mirrored BAR                 (PCIE3_GROUP_BAR1_0x02012C13)
-//
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_write_local_node_region_bars(
-    proc_setup_bars_smp_chip& i_smp_chip,
-    proc_setup_bars_smp_node& i_smp_node)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Start");
-
-    // set non-mirrored/mirrored ranges based on group=chip EC feature attribute
-    proc_setup_bars_addr_range non_mirrored_range =
-        ((i_smp_chip.init_group_as_chip)?(i_smp_chip.non_mirrored_range):(i_smp_node.non_mirrored_range));
-    proc_setup_bars_addr_range mirrored_range =
-        ((i_smp_chip.init_group_as_chip)?(i_smp_chip.mirrored_range):(i_smp_node.mirrored_range));
-
-    do
-    {
-        // NX (non-mirrored)
-        if (non_mirrored_range.enabled && i_smp_chip.nx_enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA0 APC Group Non-Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_APC_GROUP_BAR0_0x0201302F,
-                common_nf_scope_bar_reg_def,
-                non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            if (i_smp_chip.dual_capp_present)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA1 APC Group Non-Mirrored BAR register");
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    NX_CXA1_APC_GROUP_BAR0_0x020131AF,
-                    common_nf_scope_bar_reg_def,
-                    non_mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX Group Non-Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_GROUP_BAR0_0x02013097,
-                common_nf_scope_bar_reg_def,
-                non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // NX (mirrored)
-        if (mirrored_range.enabled && i_smp_chip.nx_enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA0 APC Group Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_APC_GROUP_BAR1_0x02013030,
-                common_nf_scope_bar_reg_def,
-                mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-
-            if (i_smp_chip.dual_capp_present)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX CXA1 APC Group Mirrored BAR register");
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    NX_CXA1_APC_GROUP_BAR1_0x020131B0,
-                    common_nf_scope_bar_reg_def,
-                    mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-
-            FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NX Group Mirrored BAR register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                NX_GROUP_BAR1_0x02013098,
-                common_nf_scope_bar_reg_def,
-                mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-        // NPU (non-mirrored)
-        if (non_mirrored_range.enabled && i_smp_chip.nv_present)
-        {
-            for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NPU%d Group Non-Mirrored BAR register", u);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    PROC_SETUP_BARS_NPU_NODE_NON_MIRRORED_BAR[u],
-                    common_nf_scope_bar_reg_def,
-                    non_mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-
-        }
-
-        // NPU (mirrored)
-        if (mirrored_range.enabled && i_smp_chip.nv_present)
-        {
-            for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++)
-            {
-                FAPI_DBG("proc_setup_bars_write_local_node_region_bars: Writing NPU%d Group Mirrored BAR register", u);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    PROC_SETUP_BARS_NPU_NODE_MIRRORED_BAR[u],
-                    common_nf_scope_bar_reg_def,
-                    mirrored_range);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-
-        // L3 (non-mirrored)
-        if (non_mirrored_range.enabled)
-        {
-            rc = proc_setup_bars_l3_write_local_node_memory_bar_attr(
-                &(i_smp_chip.chip->this_chip),
-                true,
-                non_mirrored_range,
-                i_smp_chip.non_mirrored_range);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_l3_write_local_node_memory_bar_attr");
-                break;
-            }
-        }
-
-        // L3 (mirrored)
-        if (mirrored_range.enabled)
-        {
-            rc = proc_setup_bars_l3_write_local_node_memory_bar_attr(
-                &(i_smp_chip.chip->this_chip),
-                false,
-                mirrored_range,
-                i_smp_chip.mirrored_range);
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_l3_write_local_node_memory_bar_attr");
-                break;
-            }
-        }
-
-        // PCIe (non-mirrored/mirrored)
-        if (i_smp_chip.pcie_enabled)
-        {
-            rc = proc_setup_bars_pcie_write_local_node_memory_bars(
-                i_smp_chip.chip->this_chip,
-                i_smp_chip.num_phb,
-                non_mirrored_range,
-                mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_local_node_region_bars: Error from proc_setup_bars_pcie_write_local_node_memory_bars");
-                break;
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_write_local_node_region_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write all BARs tied to remote node regions
-//           (non-mirrored/mirrored regions)
-// parameters: i_smp_chip    => structure encapsulating single chip in SMP
-//                              topology
-//             i_smp_node_a0 => structure encapsulating node reachable from
-//                              A0 link on this chip
-//             i_smp_node_a1 => structure encapsulating node reachable from
-//                              A1 link on this chip
-//             i_smp_node_a2 => structure encapsulating node reachable from
-//                              A2 link on this chip
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-//
-// Remote node region BARs:
-//
-// PB
-//   PB Remote Group (A0) Non-Mirrored BAR    (PB_RGMCFG00_0x02010C58)
-//   PB Remote Group (A0) Mirrored BAR        (PB_RGMCFGM00_0x02010C5B)
-//   PB Remote Group (A1) Non-Mirrored BAR    (PB_RGMCFG01_0x02010C59)
-//   PB Remote Group (A1) Mirrored BAR        (PB_RGMCFGM01_0x02010C5C)
-//   PB Remote Group (A2) Non-Mirrored BAR    (PB_RGMCFG10_0x02010C5A)
-//   PB Remote Group (A2) Mirrored BAR        (PB_RGMCFGM10_0x02010C5D)
-//
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_write_remote_node_region_bars(
-    proc_setup_bars_smp_chip& i_smp_chip,
-    proc_setup_bars_smp_node& i_smp_node_a0,
-    proc_setup_bars_smp_node& i_smp_node_a1,
-    proc_setup_bars_smp_node& i_smp_node_a2)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Start");
-
-    do
-    {
-        // A0 (non-mirrored)
-        if (i_smp_node_a0.non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A0) Non-Mirrored Configuration register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PB_RGMCFG00_0x02010C58,
-                common_nf_scope_bar_reg_def,
-                i_smp_node_a0.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // A0 (mirrored)
-        if (i_smp_node_a0.mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A0) Mirrored Configuration register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PB_RGMCFGM00_0x02010C5B,
-                common_nf_scope_bar_reg_def,
-                i_smp_node_a0.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // A1 (non-mirrored)
-        if (i_smp_node_a1.non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A1) Non-Mirrored Configuration register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PB_RGMCFG01_0x02010C59,
-                common_nf_scope_bar_reg_def,
-                i_smp_node_a1.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // A1 (mirrored)
-        if (i_smp_node_a1.mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A1) Mirrored Configuration register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PB_RGMCFGM01_0x02010C5C,
-                common_nf_scope_bar_reg_def,
-                i_smp_node_a1.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // A2 (non-mirrored)
-        if (i_smp_node_a2.non_mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A2) Non-Mirrored Configuration register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PB_RGMCFG10_0x02010C5A,
-                common_nf_scope_bar_reg_def,
-                i_smp_node_a2.non_mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-
-        // A2 (mirrored)
-        if (i_smp_node_a2.mirrored_range.enabled)
-        {
-            FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: Writing PB Remote Group (A2) Mirrored Configuration register");
-            rc = proc_setup_bars_common_write_bar_reg(
-                i_smp_chip.chip->this_chip,
-                PB_RGMCFGM10_0x02010C5D,
-                common_nf_scope_bar_reg_def,
-                i_smp_node_a2.mirrored_range);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_remote_node_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                break;
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_write_remote_node_region_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write all BARs tied to local chip foreign
-//           regions (near/far)
-// parameters: i_smp_chip    => structure encapsulating single chip in SMP
-//                              topology
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from common BAR write function
-//------------------------------------------------------------------------------
-//
-// Foreign region BARs:
-//
-// PB
-//   PB F0 Near BAR (West)                    (PB_FLMCFG0_WEST_0x02010C12)
-//   PB F0 Near BAR (Center)                  (PB_FLMCFG0_CENT_0x02010C5E)
-//   PB F0 Near BAR (East)                    (PB_FLMCFG0_EAST_0x02010C92)
-//   PB F0 Far BAR (West)                     (PB_FRMCFG0_WEST_0x02010C14)
-//   PB F0 Far BAR (Center)                   (PB_FRMCFG0_CENT_0x02010C60)
-//   PB F0 Far BAR (East)                     (PB_FRMCFG0_EAST_0x02010C94)
-//   PB F1 Near BAR (West)                    (PB_FLMCFG1_WEST_0x02010C13)
-//   PB F1 Near BAR (Center)                  (PB_FLMCFG1_CENT_0x02010C5F)
-//   PB F1 Near BAR (East)                    (PB_FLMCFG1_EAST_0x02010C93)
-//   PB F1 Far BAR (West)                     (PB_FRMCFG1_WEST_0x02010C15)
-//   PB F1 Far BAR (Center)                   (PB_FRMCFG1_CENT_0x02010C61)
-//   PB F1 Far BAR (East)                     (PB_FRMCFG1_EAST_0x02010C95)
-//
-// NX
-//   NX CXA0 APC F0 Near BAR                  (NX_APC_NEAR_BAR_F0_0x02013031)
-//   NX CXA1 APC F0 Near BAR                  (NX_CXA1_APC_NEAR_BAR_F0_0x020131B1)
-//   NX CXA0 APC F0 Far BAR                   (NX_APC_FAR_BAR_F0_0x02013032)
-//   NX CXA1 APC F0 Far BAR                   (NX_CXA1_APC_FAR_BAR_F0_0x020131B2)
-//   NX CXA0 APC F1 Near BAR                  (NX_APC_NEAR_BAR_F1_0x02013033)
-//   NX CXA1 APC F1 Near BAR                  (NX_CXA1_APC_NEAR_BAR_F1_0x020131B3)
-//   NX CXA0 APC F1 Far BAR                   (NX_APC_FAR_BAR_F1_0x02013034)
-//   NX CXA1 APC F1 Far BAR                   (NX_CXA1_APC_FAR_BAR_F1_0x020131B4)
-//   NX F0 Near BAR                           (NX_NEAR_BAR_F0_0x02013099)
-//   NX F0 Far BAR                            (NX_FAR_BAR_F0_0x0201309A)
-//   NX F1 Near BAR                           (NX_NEAR_BAR_F1_0x0201309B)
-//   NX F1 Far BAR                            (NX_FAR_BAR_F1_0x0201309C)
-//
-// MCD
-//   MCD Configuration 2 (F0)                 (MCD_CN10_0x0201340E)
-//   MCD Configuration 3 (F1)                 (MCD_CN11_0x0201340F)
-//
-// PCIe
-//   PCIE0 F0 Near BAR                        (PCIE0_NEAR_BAR_F0_0x02012014)
-//   PCIE0 F0 Far BAR                         (PCIE0_FAR_BAR_F0_0x02012015)
-//   PCIE0 F1 Near BAR                        (PCIE0_NEAR_BAR_F1_0x02012016)
-//   PCIE0 F1 Far BAR                         (PCIE0_FAR_BAR_F1_0x02012017)
-//
-//   PCIE1 F0 Near BAR                        (PCIE1_NEAR_BAR_F0_0x02012414)
-//   PCIE1 F0 Far BAR                         (PCIE1_FAR_BAR_F0_0x02012415)
-//   PCIE1 F1 Near BAR                        (PCIE1_NEAR_BAR_F1_0x02012416)
-//   PCIE1 F1 Far BAR                         (PCIE1_FAR_BAR_F1_0x02012417)
-//
-//   PCIE2 F0 Near BAR                        (PCIE2_NEAR_BAR_F0_0x02012814)
-//   PCIE2 F0 Far BAR                         (PCIE2_FAR_BAR_F0_0x02012815)
-//   PCIE2 F1 Near BAR                        (PCIE2_NEAR_BAR_F1_0x02012816)
-//   PCIE2 F1 Far BAR                         (PCIE2_FAR_BAR_F1_0x02012817)
-//
-//   PCIE3 F0 Near BAR                        (PCIE3_NEAR_BAR_F0_0x02012C14)
-//   PCIE3 F0 Far BAR                         (PCIE3_FAR_BAR_F0_0x02012C15)
-//   PCIE3 F1 Near BAR                        (PCIE3_NEAR_BAR_F1_0x02012C16)
-//   PCIE3 F1 Far BAR                         (PCIE3_FAR_BAR_F1_0x02012C17)
-//
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_write_foreign_region_bars(
-    proc_setup_bars_smp_chip& i_smp_chip)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Start");
-
-    do
-    {
-        bool process_links[PROC_FAB_SMP_NUM_F_LINKS] =
-        {
-            i_smp_chip.chip->process_f0,
-            i_smp_chip.chip->process_f1
-        };
-
-        // PCIe (near/far)
-        if (i_smp_chip.pcie_enabled)
-        {
-            rc = proc_setup_bars_pcie_write_foreign_memory_bars(
-                i_smp_chip.chip->this_chip,
-                i_smp_chip.num_phb,
-                process_links,
-                i_smp_chip.foreign_near_ranges,
-                i_smp_chip.foreign_far_ranges);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_pcie_write_foreign_memory_bars");
-                break;
-            }
-        }
-
-        // process ranges
-        for (uint8_t r = 0;
-             (r < PROC_FAB_SMP_NUM_F_LINKS) && (rc.ok());
-             r++)
-        {
-            // near
-            if (process_links[r] &&
-                i_smp_chip.foreign_near_ranges[r].enabled)
-            {
-                // PB (near, west)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (West) register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    PB_FLMCFG0_WEST_0x02010C12:
-                    PB_FLMCFG1_WEST_0x02010C13,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_near_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-
-                // PB (near, cent)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (Center) register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    PB_FLMCFG0_CENT_0x02010C5E:
-                    PB_FLMCFG1_CENT_0x02010C5F,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_near_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-
-                // PB (near, east)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Near BAR (East) register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    PB_FLMCFG0_EAST_0x02010C92:
-                    PB_FLMCFG1_EAST_0x02010C93,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_near_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-
-                // NX APC (near)
-                if (i_smp_chip.nx_enabled)
-                {
-                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA0 APC F%d Near BAR register",
-                             r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_smp_chip.chip->this_chip,
-                        (r == 0)?
-                        NX_APC_NEAR_BAR_F0_0x02013031:
-                        NX_APC_NEAR_BAR_F1_0x02013033,
-                        common_f_scope_bar_reg_def,
-                        i_smp_chip.foreign_near_ranges[r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-
-                    if (i_smp_chip.dual_capp_present)
-                    {
-                        FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA1 APC F%d Near BAR register",
-                                 r);
-                        rc = proc_setup_bars_common_write_bar_reg(
-                            i_smp_chip.chip->this_chip,
-                            (r == 0)?
-                            NX_CXA1_APC_NEAR_BAR_F0_0x020131B1:
-                            NX_CXA1_APC_NEAR_BAR_F1_0x020131B3,
-                            common_f_scope_bar_reg_def,
-                            i_smp_chip.foreign_near_ranges[r]);
-                        if (!rc.ok())
-                        {
-                            FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                            break;
-                        }
-                    }
-                }
-
-                // NX (near)
-                if (i_smp_chip.nx_enabled)
-                {
-                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Near BAR register",
-                             r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_smp_chip.chip->this_chip,
-                        (r == 0)?
-                        NX_NEAR_BAR_F0_0x02013099:
-                        NX_NEAR_BAR_F1_0x0201309B,
-                        common_f_scope_bar_reg_def,
-                        i_smp_chip.foreign_near_ranges[r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-                }
-
-                // MCD (near only)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing MCD Configuration %d (F%d) register",
-                         r+1, r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    MCD_CN10_0x0201340E:
-                    MCD_CN11_0x0201340F,
-                    (r == 0)?
-                    mcd_f0_bar_reg_def:
-                    mcd_f1_bar_reg_def,
-                    i_smp_chip.foreign_near_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-            }
-
-            // far
-            if (process_links[r] &&
-                i_smp_chip.foreign_near_ranges[r].enabled)
-            {
-                // PB (far, west)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (West) register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    PB_FRMCFG0_WEST_0x02010C14:
-                    PB_FRMCFG1_WEST_0x02010C15,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_far_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-
-                // PB (far, center)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (Center) register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    PB_FRMCFG0_CENT_0x02010C60:
-                    PB_FRMCFG1_CENT_0x02010C61,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_far_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-
-                // PB (far, east)
-                FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing PB F%d Far BAR (East) register",
-                         r);
-                rc = proc_setup_bars_common_write_bar_reg(
-                    i_smp_chip.chip->this_chip,
-                    (r == 0)?
-                    PB_FRMCFG0_EAST_0x02010C94:
-                    PB_FRMCFG1_EAST_0x02010C95,
-                    common_f_scope_bar_reg_def,
-                    i_smp_chip.foreign_far_ranges[r]);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                    break;
-                }
-
-                // NX APC (far)
-                if (i_smp_chip.nx_enabled)
-                {
-                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA0 APC F%d Far BAR register",
-                             r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_smp_chip.chip->this_chip,
-                        (r == 0)?
-                        NX_APC_FAR_BAR_F0_0x02013032:
-                        NX_APC_FAR_BAR_F1_0x02013034,
-                        common_f_scope_bar_reg_def,
-                        i_smp_chip.foreign_far_ranges[r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-
-                    if (i_smp_chip.dual_capp_present)
-                    {
-                        FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX CXA1 APC F%d Far BAR register",
-                                 r);
-                        rc = proc_setup_bars_common_write_bar_reg(
-                            i_smp_chip.chip->this_chip,
-                            (r == 0)?
-                            NX_CXA1_APC_FAR_BAR_F0_0x020131B2:
-                            NX_CXA1_APC_FAR_BAR_F1_0x020131B4,
-                            common_f_scope_bar_reg_def,
-                            i_smp_chip.foreign_far_ranges[r]);
-                        if (!rc.ok())
-                        {
-                            FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                            break;
-                        }
-                    }
-                }
-
-                // NX (far)
-                if (i_smp_chip.nx_enabled)
-                {
-                    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: Writing NX F%d Far BAR register",
-                             r);
-                    rc = proc_setup_bars_common_write_bar_reg(
-                        i_smp_chip.chip->this_chip,
-                        (r == 0)?
-                        NX_FAR_BAR_F0_0x0201309A:
-                        NX_FAR_BAR_F1_0x0201309C,
-                        common_f_scope_bar_reg_def,
-                        i_smp_chip.foreign_far_ranges[r]);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_foreign_region_bars: Error from proc_setup_bars_common_write_bar_reg");
-                        break;
-                    }
-                }
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_write_foreign_region_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility function to find node structure associated with a given
-//           target
-// parameters: i_target => chip target
-//             i_smp    => structure encapsulating SMP topology
-//             o_node   => node structure associated with chip target input
-// returns: FAPI_RC_SUCCESS if matching node is found
-//          RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR if node map lookup is
-//              unsuccessful,
-//          else failing return code from node ID attribute query function
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_find_node(
-    const fapi::Target& i_target,
-    proc_setup_bars_smp_system& i_smp,
-    proc_setup_bars_smp_node& o_node)
-{
-    // return code
-    fapi::ReturnCode rc;
-    proc_fab_smp_node_id node_id;
-
-    FAPI_DBG("proc_setup_bars_find_node: Start");
-
-    do
-    {
-        // get node ID attribute
-        FAPI_DBG("proc_setup_find_node: Querying node ID attribute");
-        rc = proc_fab_smp_get_node_id_attr(&(i_target),
-                                           node_id);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars_find_node: Error from proc_fab_smp_get_node_id_attr");
-            break;
-        }
-
-        // search to see if node structure already exists for the node ID
-        // associated with this chip
-        std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator
-            n_iter;
-        n_iter = i_smp.nodes.find(node_id);
-        // no match node found, exit
-        if (n_iter == i_smp.nodes.end())
-        {
-            FAPI_ERR("proc_setup_bars_find_node: insert_chip: Error encountered finding node in SMP map");
-            const fapi::Target & TARGET = i_target;
-            const proc_fab_smp_node_id & NODE_ID = node_id;
-            FAPI_SET_HWP_ERROR(rc,
-                RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR);
-            break;
-        }
-        o_node = n_iter->second;
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_find_node: End");
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// function: check that all address ranges are non-overlapping
-// parameters: i_smp => structure encapsulating fully
-//                      specified SMP topology
-// returns: FAPI_RC_SUCCESS if all ranges are non-overlapping
-//          else RC_PROC_SETUP_BARS_SYSTEM_RANGE_OVERLAP_ERR
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_check_bars(
-    proc_setup_bars_smp_system& i_smp)
-{
-    // return code
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator p_iter;
-
-    std::vector<proc_setup_bars_addr_range*> sys_ranges;
-    std::vector<fapi::Target*> targets;
-
-    // fsp_mmio_mask_range specifically excluded, as this range by itself
-    // does not represent an active portion of real address space
-    const uint32_t ranges_per_chip = 7 +
-        (2* PROC_FAB_SMP_NUM_F_LINKS) +
-        (PROC_SETUP_BARS_NPU_NUM_UNITS * PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT) +
-        (PROC_SETUP_BARS_PCIE_NUM_UNITS * PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT);
-
-    FAPI_DBG("proc_setup_bars_check_bars: Start");
-
-    do
-    {
-        for (n_iter = i_smp.nodes.begin();
-             n_iter != i_smp.nodes.end();
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 p_iter != n_iter->second.chips.end();
-                 p_iter++)
-            {
-                targets.push_back(&(p_iter->second.chip->this_chip));
-
-                sys_ranges.push_back(&(p_iter->second.non_mirrored_range));
-                sys_ranges.push_back(&(p_iter->second.mirrored_range));
-                for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
-                {
-                    sys_ranges.push_back(&(p_iter->second.foreign_near_ranges[l]));
-                }
-                for (uint8_t l = 0; l < PROC_FAB_SMP_NUM_F_LINKS; l++)
-                {
-                    sys_ranges.push_back(&(p_iter->second.foreign_far_ranges[l]));
-                }
-                sys_ranges.push_back(&(p_iter->second.psi_range));
-                sys_ranges.push_back(&(p_iter->second.fsp_range));
-                sys_ranges.push_back(&(p_iter->second.intp_range));
-                sys_ranges.push_back(&(p_iter->second.nx_mmio_range));
-                sys_ranges.push_back(&(p_iter->second.as_mmio_range));
-                for (uint8_t u = 0; u < PROC_SETUP_BARS_PCIE_NUM_UNITS; u++)
-                {
-                    for (uint8_t r = 0; r < PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT; r++)
-                    {
-                        sys_ranges.push_back(&(p_iter->second.pcie_ranges[u][r]));
-                    }
-                }
-                for (uint8_t u = 0; u < PROC_SETUP_BARS_NPU_NUM_UNITS; u++)
-                {
-                    for (uint8_t r = 0; r < PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT; r++)
-                    {
-                        sys_ranges.push_back(&(p_iter->second.npu_mmio_ranges[u][r]));
-                    }
-                }
-            }
-        }
-
-        // check that ranges are non-overlapping
-        if (sys_ranges.size() > 1)
-        {
-            for (uint32_t r = 0; (r < sys_ranges.size()-1) && rc.ok(); r++)
-            {
-                for (uint32_t x = r+1; x < sys_ranges.size(); x++)
-                {
-                    if (sys_ranges[r]->overlaps(*(sys_ranges[x])))
-                    {
-                        uint32_t target_r = r / ranges_per_chip;
-                        uint32_t range_r = r % ranges_per_chip;
-                        uint32_t target_x = x / ranges_per_chip;
-                        uint32_t range_x = x % ranges_per_chip;
-
-                        FAPI_ERR("proc_setup_bars_check_bars: Overlapping address regions detected");
-                        FAPI_ERR("  target: %s, Range index = %d",
-                                 targets[target_r]->toEcmdString(), range_r);
-                        sys_ranges[r]->print();
-                        FAPI_ERR("  target: %s, Range index = %d",
-                                 targets[target_x]->toEcmdString(), range_x);
-                        sys_ranges[x]->print();
-
-                        const fapi::Target & TARGET1 = *(targets[target_r]);
-                        const uint32_t RANGE_ID1 = range_r;
-                        const uint64_t & BASE_ADDR1 = sys_ranges[r]->base_addr;
-                        const uint64_t & END_ADDR1 = sys_ranges[r]->end_addr();
-                        const bool & ENABLED1 = sys_ranges[r]->enabled;
-
-                        const fapi::Target & TARGET2 = *(targets[target_x]);
-                        const uint32_t RANGE_ID2 = range_x;
-                        const uint64_t & BASE_ADDR2 = sys_ranges[x]->base_addr;
-                        const uint64_t & END_ADDR2 = sys_ranges[x]->end_addr();
-                        const bool & ENABLED2 = sys_ranges[x]->enabled;
-
-                        FAPI_SET_HWP_ERROR(rc,
-                            RC_PROC_SETUP_BARS_SYSTEM_RANGE_OVERLAP_ERR);
-                        break;
-                    }
-                }
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_check_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: wrapper function to write all chip BARs
-// parameters: i_smp                        => structure encapsulating fully
-//                                             specified SMP topology
-//             i_init_local_chip_local_node => boolean qualifying application
-//                                             of local chip/local node range
-//                                             specific BAR resources
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from lower level BAR write/node search
-//              functions
-//------------------------------------------------------------------------------
-fapi::ReturnCode
-proc_setup_bars_write_bars(
-    proc_setup_bars_smp_system& i_smp,
-    const bool i_init_local_chip_local_node)
-{
-    // return code
-    fapi::ReturnCode rc;
-    std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::iterator p_iter;
-
-    FAPI_DBG("proc_setup_bars_write_bars: Start");
-
-    do
-    {
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                // init local chip/local node resources?
-                if (i_init_local_chip_local_node)
-                {
-                    rc = proc_setup_bars_write_local_chip_region_bars(
-                        p_iter->second);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_local_chip_region_bars");
-                        break;
-                    }
-
-                    rc = proc_setup_bars_write_local_node_region_bars(
-                        p_iter->second,
-                        n_iter->second);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_local_node_region_bars");
-                        break;
-                    }
-                }
-
-                // determine which remote node ranges should be initialized
-                proc_setup_bars_smp_node smp_node_a0;
-                proc_setup_bars_smp_node smp_node_a1;
-                proc_setup_bars_smp_node smp_node_a2;
-                if (p_iter->second.chip->a0_chip.getType() != fapi::TARGET_TYPE_NONE)
-                {
-                    rc = proc_setup_bars_find_node(
-                        p_iter->second.chip->a0_chip,
-                        i_smp,
-                        smp_node_a0);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node");
-                        break;
-                    }
-                }
-                if (p_iter->second.chip->a1_chip.getType() != fapi::TARGET_TYPE_NONE)
-                {
-                    rc = proc_setup_bars_find_node(
-                        p_iter->second.chip->a1_chip,
-                        i_smp,
-                        smp_node_a1);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node");
-                        break;
-                    }
-                }
-                if (p_iter->second.chip->a2_chip.getType() != fapi::TARGET_TYPE_NONE)
-                {
-                    rc = proc_setup_bars_find_node(
-                        p_iter->second.chip->a2_chip,
-                        i_smp,
-                        smp_node_a2);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_write_bars: Error from proc_setup_bars_find_node");
-                        break;
-                    }
-                }
-
-                // initialize remote node related ranges
-                rc = proc_setup_bars_write_remote_node_region_bars(
-                    p_iter->second,
-                    smp_node_a0,
-                    smp_node_a1,
-                    smp_node_a2);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_remote_node_region_bars");
-                    break;
-                }
-
-                // initialize foreign link related regions
-                rc = proc_setup_bars_write_foreign_region_bars(
-                    p_iter->second);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_setup_bars_write_bars: Error from proc_setup_bars_write_foreign_region_bars");
-                    break;
-                }
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_write_bars: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: enable MCD probes/unmask FIRs
-// parameters: i_smp                        => structure encapsulating fully
-//                                             specified SMP topology
-//             i_init_local_chip_local_node => boolean qualifying application
-//                                             of local chip/local node range
-//                                             specific BAR resources
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          else failing return code from failing SCOM access
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars_config_mcd(
-    proc_setup_bars_smp_system& i_smp,
-    const bool i_init_local_chip_local_node)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    ecmdDataBufferBase mcd_fir_mask_data(64);
-    ecmdDataBufferBase mcd_recov_data(64);
-    ecmdDataBufferBase mcd_recov_mask(64);
-    std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node>::const_iterator n_iter;
-    std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip>::const_iterator p_iter;
-
-    FAPI_DBG("proc_setup_bars_config_mcd: Start");
-
-    do
-    {
-        for (n_iter = i_smp.nodes.begin();
-             (n_iter != i_smp.nodes.end()) && (rc.ok());
-             n_iter++)
-        {
-            for (p_iter = n_iter->second.chips.begin();
-                 (p_iter != n_iter->second.chips.end()) && (rc.ok());
-                 p_iter++)
-            {
-                bool config_mcd = false;
-                bool cfg_enable[PROC_SETUP_BARS_NUM_MCD_CFG] =
-                    { false, false, false, false };
-
-                // ensure MCD probes are enabled and FIR is unmasked if:
-                //   initializing local chip resources and there is a
-                //     non-mirrored/mirrored range enabled OR
-                //   initializing foreign resources and there is a
-                //     near range enabled
-
-                if (i_init_local_chip_local_node &&
-                    (p_iter->second.non_mirrored_range.enabled ||
-                     p_iter->second.mirrored_range.enabled))
-                {
-                    config_mcd = true;
-                    cfg_enable[0] = p_iter->second.non_mirrored_range.enabled;
-                    cfg_enable[1] = p_iter->second.mirrored_range.enabled;
-                }
-
-                bool process_f_links[PROC_FAB_SMP_NUM_F_LINKS] =
-                {
-                    p_iter->second.chip->process_f0,
-                    p_iter->second.chip->process_f1
-                };
-
-                // process ranges
-                for (uint8_t r = 0;
-                     (r < PROC_FAB_SMP_NUM_F_LINKS);
-                     r++)
-                {
-                    if (process_f_links[r] &&
-                        p_iter->second.foreign_near_ranges[r].enabled)
-                    {
-                        config_mcd = true;
-                        cfg_enable[2+r] = true;
-                    }
-                }
-
-                if (config_mcd)
-                {
-                    uint64_t mcd_fir_mask = MCD_FIR_MASK_RUNTIME_VAL;
-
-                    // unmask MCD FIR
-                    rc_ecmd |= mcd_fir_mask_data.setDoubleWord(
-                        0,
-                        mcd_fir_mask);
-
-                    // check buffer manipulation return codes
-                    if (rc_ecmd)
-                    {
-                        FAPI_ERR("proc_setup_bars_config_mcd: Error 0x%X setting up FIR mask data buffer",
-                                 rc_ecmd);
-                        rc.setEcmdError(rc_ecmd);
-                        break;
-                    }
-
-                    rc = fapiPutScom(p_iter->second.chip->this_chip,
-                                     MCD_FIR_MASK_0x02013403,
-                                     mcd_fir_mask_data);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_FIR_MASK_0x02013403)");
-                        break;
-                    }
-
-                    // enable MCD probes for selected config registers
-                    rc_ecmd |= mcd_recov_data.setBit(MCD_RECOVERY_ENABLE_BIT);
-                    rc_ecmd |= mcd_recov_mask.setBit(MCD_RECOVERY_ENABLE_BIT);
-                    for (uint8_t i = 0;
-                         i < PROC_SETUP_BARS_NUM_MCD_CFG;
-                         i++)
-                    {
-                        rc_ecmd |= mcd_recov_data.writeBit(
-                            MCD_RECOVERY_CFG_EN_BIT[i],
-                            cfg_enable[i]);
-                        rc_ecmd |= mcd_recov_mask.writeBit(
-                            MCD_RECOVERY_CFG_EN_BIT[i],
-                            cfg_enable[i]);
-                    }
-
-                    // check buffer manipulation return codes
-                    if (rc_ecmd)
-                    {
-                        FAPI_ERR("proc_setup_bars_config_mcd: Error 0x%X setting up recovery data buffer",
-                                 rc_ecmd);
-                        rc.setEcmdError(rc_ecmd);
-                        break;
-                    }
-
-                    rc = fapiPutScomUnderMask(p_iter->second.chip->this_chip,
-                                              MCD_REC_EVEN_0x02013410,
-                                              mcd_recov_data,
-                                              mcd_recov_mask);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_REC_EVEN_0x02013410)");
-                        break;
-                    }
-
-                    rc = fapiPutScomUnderMask(p_iter->second.chip->this_chip,
-                                              MCD_REC_ODD_0x02013411,
-                                              mcd_recov_data,
-                                              mcd_recov_mask);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_setup_bars_config_mcd: fapiPutScomUnderMask error (MCD_REC_ODD_0x02013411)");
-                        break;
-                    }
-                }
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_setup_bars_config_mcd: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: proc_setup_bars HWP entry point
-//           NOTE: see comments above function prototype in header
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars(
-    std::vector<proc_setup_bars_proc_chip>& i_proc_chips,
-    const bool i_init_local_chip_local_node)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // SMP model
-    proc_setup_bars_smp_system smp;
-
-    // mark HWP entry
-    FAPI_IMP("proc_setup_bars: Entering ...");
-
-    do
-    {
-        // process all chips passed from platform to HWP, query chip
-        // specific attributes and insert into system SMP data structure
-        // given logical node & chip ID
-        rc = proc_setup_bars_process_chips(i_proc_chips,
-                                           smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_process_chips");
-            break;
-        }
-
-        // check that all ranges are non-overlapping
-        rc = proc_setup_bars_check_bars(smp);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_check_bars");
-            break;
-        }
-
-        // write BAR registers
-        rc = proc_setup_bars_write_bars(smp,
-                                        i_init_local_chip_local_node);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_write_bars");
-            break;
-        }
-
-        // configure MCD resources
-        rc = proc_setup_bars_config_mcd(smp,
-                                        i_init_local_chip_local_node);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_setup_bars: Error from proc_setup_bars_config_mcd");
-            break;
-        }
-
-    } while(0);
-
-    // log function exit
-    FAPI_IMP("proc_setup_bars: Exiting ...");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
deleted file mode 100644
index 5d64c74ed..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
+++ /dev/null
@@ -1,183 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars.H,v 1.17 2014/08/05 20:43:46 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_setup_bars.H
-// *! DESCRIPTION : Program nest base address registers (BARs) (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *! Program nest unit BAR registers, driven by attributes representing system
-// *! memory map (including MMIO).
-// *!
-// *! High level execution flow:
-// *!     proc_setup_bars()
-// *!         proc_setup_bars_process_chips()
-// *!             proc_setup_bars_process_chip()
-// *!                 proc_fab_smp_get_pcie_dsmp_mux_attrs()
-// *!                 proc_fab_smp_get_node_id_attr()
-// *!                 proc_fab_smp_get_chip_id_attr()
-// *!                 proc_setup_bars_get_bar_attrs()
-// *!                     proc_setup_bars_get_memory_range_attrs (non-mirrored)
-// *!                     proc_setup_bars_get_memory_range_attrs (mirrored)
-// *!                     proc_setup_bars_get_range_attrs (foreign, near)
-// *!                     proc_setup_bars_get_range_attrs (foreign, far)
-// *!                     proc_setup_bars_get_range_attrs (psi)
-// *!                     proc_setup_bars_get_range_attrs (fsp)
-// *!                     proc_setup_bars_get_range_attrs (fsp mmio mask)
-// *!                     proc_setup_bars_get_range_attrs (intp)
-// *!                     proc_setup_bars_get_range_attrs (nx)
-// *!                     proc_setup_bars_get_range_attrs (as)
-// *!                     proc_setup_bars_get_range_attrs (pcie)
-// *!             proc_setup_bars_insert_chip()
-// *!         proc_setup_bars_write_bars()
-// *!             proc_setup_bars_write_local_chip_region_bars()
-// *!             proc_setup_bars_write_local_node_region_bars()
-// *!             proc_setup_bars_find_remote_node()
-// *!             proc_setup_bars_write_remote_node_region_bars()
-// *!             proc_setup_bars_write_foreign_region_bars()
-// *!
-// *! Platform Notes:
-// *!     This HWP has multiple IPL use cases. In all cases the HWP input
-// *!     is expected to contain an entry for each chip in the SMP at the
-// *!     time/scope of the invocation:
-// *!
-// *!         1. HBI (drawer scope):
-// *!            All local chip/local node resources should be initialized
-// *!            at this time (HWP boolean flag controlling this function
-// *!            set to true).
-// *!
-// *!            All A links active in the scope of the drawer should be
-// *!            reflected in the per-chip HWP input structures.
-// *!
-// *!         2. FSP (drawer integration):
-// *!            All local chip/local node resources should already have
-// *!            been initialized in each drawer, so the HWP boolean flag
-// *!            controlling this function should be set to false.
-// *!
-// *!            Only 'new' A links which cross previously initialized
-// *!            drawers should be reflected in the per-chip HWP input
-// *!            structures.
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_SETUP_BARS_H_
-#define _PROC_SETUP_BARS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <vector>
-#include <map>
-#include <fapi.H>
-#include "proc_fab_smp.H"
-#include "p8_scom_addresses.H"
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// HWP argument structure defining properties of this chip
-// and links which should be considered in this invocation (A/F)
-struct proc_setup_bars_proc_chip
-{
-    // target for this chip
-    fapi::Target this_chip;
-
-    // targets defining A link connected chips
-    // qualify which remote node based BAR resources should be initalized on
-    // this chip
-    fapi::Target a0_chip;
-    fapi::Target a1_chip;
-    fapi::Target a2_chip;
-
-    // init F link related BARs for this chip?
-    bool process_f0;
-    bool process_f1;
-};
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_setup_bars_FP_t)(std::vector<proc_setup_bars_proc_chip>&,
-                        const bool);
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: program nest unit BAR registers, driven by attributes representing
-//           system memory map (including MMIO)
-// parameters: i_proc_chips => vector of structures defining properties of each
-//                             chip and links which should be considered in
-//                             this invocation to drive initialization of BARs
-//                             tied to remote node regions (A links) and
-//                             foreign regions (F links)
-//             i_init_local_chip_local_node => boolean qualifying initilization
-//                                             of BARs tied to local chip/local
-//                                             node regions
-// returns: FAPI_RC_SUCCESS if all register writes are successful,
-//          RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR if no rule is found to set
-//              BAR/range address, enable, or size,
-//          RC_PROC_SETUP_BARS_ATTR_CONTENT_ERR if BAR/range attribute content
-//              violates expected behavior,
-//          RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ATTR_OVERLAP_ERR if chip
-//              memory range attributes specify overlapping address ranges,
-//          RC_PROC_SETUP_BARS_CHIP_MEMORY_RANGE_ERR if merged
-//              chip memory address range is invalid,
-//          RC_PROC_SETUP_BARS_NODE_ADD_INTERNAL_ERR if node map insert fails,
-//          RC_PROC_SETUP_BARS_NODE_FIND_INTERNAL_ERR if node map lookup is
-//              unsuccessful,
-//          RC_PROC_SETUP_BARS_DUPLICATE_FABRIC_ID_ERR if chips with duplicate
-//              fabric node/chip IDs are detected,
-//          RC_PROC_SETUP_BARS_INVALID_BAR_REG_DEF if BAR register definition
-//              structure is invalid,
-//          RC_PROC_SETUP_BARS_SIZE_XLATE_ERR if BAR logical->physical size
-//              translation is unsuccessful,
-//          RC_PROC_SETUP_BARS_SYSTEM_RANGE_OVERLAP_ERR if any overapping
-//              ranges are detected, considering all ranges in system,
-//          else failing return code
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_setup_bars(
-    std::vector<proc_setup_bars_proc_chip>& i_proc_chips,
-    const bool i_init_local_chip_local_node);
-
-} // extern "C"
-
-
-#endif // _PROC_SETUP_BARS_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H
deleted file mode 100644
index 7e70a1e4d..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H
+++ /dev/null
@@ -1,1332 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars_defs.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_setup_bars_defs.H,v 1.6 2015/11/10 19:39:58 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars_defs.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_setup_bars_defs.H
-// *! DESCRIPTION : Structure/constant definitions for proc_setup_bars HWP (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_SETUP_BARS_DEFS_H_
-#define _PROC_SETUP_BARS_DEFS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_setup_bars.H"
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// address range size definition constants
-const uint64_t PROC_SETUP_BARS_SIZE_1_PB   = 0x0004000000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_512_TB = 0x0002000000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_256_TB = 0x0001000000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_128_TB = 0x0000800000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_64_TB  = 0x0000400000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_32_TB  = 0x0000200000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_16_TB  = 0x0000100000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_8_TB   = 0x0000080000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_4_TB   = 0x0000040000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_2_TB   = 0x0000020000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_1_TB   = 0x0000010000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_512_GB = 0x0000008000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_256_GB = 0x0000004000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_128_GB = 0x0000002000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_64_GB  = 0x0000001000000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_32_GB  = 0x0000000800000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_16_GB  = 0x0000000400000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_8_GB   = 0x0000000200000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_4_GB   = 0x0000000100000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_2_GB   = 0x0000000080000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_1_GB   = 0x0000000040000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_512_MB = 0x0000000020000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_256_MB = 0x0000000010000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_128_MB = 0x0000000008000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_64_MB  = 0x0000000004000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_32_MB  = 0x0000000002000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_16_MB  = 0x0000000001000000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_8_MB   = 0x0000000000800000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_4_MB   = 0x0000000000400000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_2_MB   = 0x0000000000200000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_1_MB   = 0x0000000000100000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_512_KB = 0x0000000000080000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_256_KB = 0x0000000000040000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_128_KB = 0x0000000000020000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_64_KB  = 0x0000000000010000ULL;
-const uint64_t PROC_SETUP_BARS_SIZE_4_KB   = 0x0000000000001000ULL;
-
-// memory (non-mirrored/mirrored) constants
-const uint8_t PROC_SETUP_BARS_NUM_NON_MIRRORED_RANGES = 8;
-const uint8_t PROC_SETUP_BARS_NUM_MIRRORED_RANGES = 4;
-
-// PCIe unit contstants
-const uint8_t PROC_SETUP_BARS_PCIE_NUM_UNITS = 4;
-const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT = 3;
-
-// NPU unit constants
-const uint8_t PROC_SETUP_BARS_NPU_NUM_UNITS = 4;
-const uint8_t PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT = 2;
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// structure to represent range of FBC real address space
-struct proc_setup_bars_addr_range
-{
-    // default constructor (mark range disabled)
-    proc_setup_bars_addr_range() :
-        enabled(false),
-        base_addr(0),
-        size(0)
-    {
-    }
-
-    // constructor
-    proc_setup_bars_addr_range(
-        const uint64_t& range_base_addr,
-        const uint64_t& range_size) :
-        enabled(range_size != 0),
-        base_addr(range_base_addr),
-        size(range_size)
-    {
-    }
-
-    // determine if region size is power of 2 aligned
-    bool is_power_of_2() const
-    {
-        return ((size != 0) && !(size & (size - 1)));
-    }
-
-    // round region size to next largest power of 2
-    void round_next_power_of_2()
-    {
-        size = size - 1;
-        size = size | (size >> 1);
-        size = size | (size >> 2);
-        size = size | (size >> 4);
-        size = size | (size >> 8);
-        size = size | (size >> 16);
-        size = size | (size >> 32);
-        size = size + 1;
-    }
-
-    // return ending address of range
-    uint64_t end_addr() const
-    {
-        return(base_addr + size - 1);
-    }
-
-    // check for overlapping ranges
-    bool overlaps(const proc_setup_bars_addr_range& range_compare) const
-    {
-        // if either range is disabled, consider them non-overlapping
-        return(enabled &&
-               range_compare.enabled &&
-               (base_addr <= range_compare.end_addr()) &&
-               (end_addr() >= range_compare.base_addr));
-    }
-
-    // merge two ranges (span breadth of both ranges)
-    void merge(const proc_setup_bars_addr_range& range_new)
-    {
-        // if range is disabled, set values to track those of new
-        // range (which may also be disabled)
-        if (!enabled)
-        {
-            enabled = range_new.enabled;
-            base_addr = range_new.base_addr;
-            size = range_new.size;
-        }
-        // if new range is disabled, leave as-is
-        // otherwise merge two valid ranges
-        else if (range_new.enabled)
-        {
-            uint64_t new_start_addr;
-            uint64_t new_end_addr;
-
-            // calculate new base address (smaller of the two start addresses)
-            if (base_addr < range_new.base_addr)
-            {
-                new_start_addr = base_addr;
-            }
-            else
-            {
-                new_start_addr = range_new.base_addr;
-            }
-            // calculate new end address (larger of the two end addresses)
-            if (end_addr() > range_new.end_addr())
-            {
-                new_end_addr = end_addr();
-            }
-            else
-            {
-                new_end_addr = range_new.end_addr();
-            }
-            // set new range values
-            base_addr = new_start_addr;
-            size = (new_end_addr - new_start_addr + 1);
-        }
-    }
-
-    // check that if region size aligns exactly to base address range
-    // (i.e., no overlap between BAR and size)
-    bool is_aligned() const
-    {
-        return ((base_addr & (size - 1)) == 0x0ULL);
-    }
-
-    // does range lie completely within FBC address range?
-    bool is_in_fbc_range() const
-    {
-        return ((base_addr < PROC_FAB_SMP_MAX_ADDRESS) &&
-                (end_addr() < PROC_FAB_SMP_MAX_ADDRESS));
-    }
-
-    // utility function to display address range information
-    void print() const
-    {
-        FAPI_DBG("proc_setup_bars_print_addr_range: %s :: [ %016llX-%016llX ]",
-                 (enabled)?("E"):("D"),
-                 base_addr,
-                 end_addr());
-    }
-
-    bool enabled;
-    uint64_t base_addr;
-    uint64_t size;
-};
-
-// structure to represent fabric connectivty & properites for a single chip
-// in the SMP topology
-struct proc_setup_bars_smp_chip
-{
-    // associated HWP input structure
-    proc_setup_bars_proc_chip* chip;
-
-    // chip properties/attributes:
-    // fabric chip/node ID
-    proc_fab_smp_chip_id chip_id;
-    proc_fab_smp_node_id node_id;
-    // partial good attributes
-    bool nx_enabled;
-    bool pcie_enabled;
-    bool nv_present;
-    bool init_group_as_chip;
-    bool dual_capp_present;
-    // number of valid PCIe PHBs
-    uint8_t num_phb;
-    // select for PCIe/DSMP mux (one per link)
-    bool pcie_not_f_link[PROC_FAB_SMP_NUM_F_LINKS];
-    // real address ranges covered by resources on this chip
-    proc_setup_bars_addr_range non_mirrored_range;
-    proc_setup_bars_addr_range mirrored_range;
-    proc_setup_bars_addr_range foreign_near_ranges[PROC_FAB_SMP_NUM_F_LINKS];
-    proc_setup_bars_addr_range foreign_far_ranges[PROC_FAB_SMP_NUM_F_LINKS];
-    proc_setup_bars_addr_range psi_range;
-    proc_setup_bars_addr_range fsp_range;
-    proc_setup_bars_addr_range fsp_mmio_mask_range;
-    proc_setup_bars_addr_range intp_range;
-    proc_setup_bars_addr_range nx_mmio_range;
-    proc_setup_bars_addr_range as_mmio_range;
-    proc_setup_bars_addr_range npu_mmio_ranges[PROC_SETUP_BARS_NPU_NUM_UNITS][PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT];
-    proc_setup_bars_addr_range pcie_ranges[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT];
-};
-
-// structure to represent properties for a single node in the SMP topology
-struct proc_setup_bars_smp_node
-{
-    // chips which reside in this node
-    std::map<proc_fab_smp_chip_id, proc_setup_bars_smp_chip> chips;
-
-    // node properties/attributes:
-    // fabric node ID
-    proc_fab_smp_node_id node_id;
-    // real address ranges covered for mirrored & non-mirrored regions
-    // (considering all chips in node)
-    proc_setup_bars_addr_range non_mirrored_range;
-    proc_setup_bars_addr_range mirrored_range;
-};
-
-// structure to represent collection of nodes in SMP topology
-struct proc_setup_bars_smp_system
-{
-    // nodes which reside in this SMP
-    std::map<proc_fab_smp_node_id, proc_setup_bars_smp_node> nodes;
-};
-
-// define set of shared design non-foreign BAR sizes
-struct proc_setup_bars_nf_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_64_TB]  = 0x3FFFULL;
-        m[PROC_SETUP_BARS_SIZE_32_TB]  = 0x1FFFULL;
-        m[PROC_SETUP_BARS_SIZE_16_TB]  = 0x0FFFULL;
-        m[PROC_SETUP_BARS_SIZE_8_TB]   = 0x07FFULL;
-        m[PROC_SETUP_BARS_SIZE_4_TB]   = 0x03FFULL;
-        m[PROC_SETUP_BARS_SIZE_2_TB]   = 0x01FFULL;
-        m[PROC_SETUP_BARS_SIZE_1_TB]   = 0x00FFULL;
-        m[PROC_SETUP_BARS_SIZE_512_GB] = 0x007FULL;
-        m[PROC_SETUP_BARS_SIZE_256_GB] = 0x003FULL;
-        m[PROC_SETUP_BARS_SIZE_128_GB] = 0x001FULL;
-        m[PROC_SETUP_BARS_SIZE_64_GB]  = 0x000FULL;
-        m[PROC_SETUP_BARS_SIZE_32_GB]  = 0x0007ULL;
-        m[PROC_SETUP_BARS_SIZE_16_GB]  = 0x0003ULL;
-        m[PROC_SETUP_BARS_SIZE_8_GB]   = 0x0001ULL;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0x0000ULL;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of shared design foreign BAR sizes
-struct proc_setup_bars_f_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_8_TB]   = 0x7FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_4_TB]   = 0x3FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_2_TB]   = 0x1FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_1_TB]   = 0x0FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_512_GB] = 0x07FFFULL;
-        m[PROC_SETUP_BARS_SIZE_256_GB] = 0x03FFFULL;
-        m[PROC_SETUP_BARS_SIZE_128_GB] = 0x01FFFULL;
-        m[PROC_SETUP_BARS_SIZE_64_GB]  = 0x00FFFULL;
-        m[PROC_SETUP_BARS_SIZE_32_GB]  = 0x007FFULL;
-        m[PROC_SETUP_BARS_SIZE_16_GB]  = 0x003FFULL;
-        m[PROC_SETUP_BARS_SIZE_8_GB]   = 0x001FFULL;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0x000FFULL;
-        m[PROC_SETUP_BARS_SIZE_2_GB]   = 0x0007FULL;
-        m[PROC_SETUP_BARS_SIZE_1_GB]   = 0x0003FULL;
-        m[PROC_SETUP_BARS_SIZE_512_MB] = 0x0001FULL;
-        m[PROC_SETUP_BARS_SIZE_256_MB] = 0x0000FULL;
-        m[PROC_SETUP_BARS_SIZE_128_MB] = 0x00007ULL;
-        m[PROC_SETUP_BARS_SIZE_64_MB]  = 0x00003ULL;
-        m[PROC_SETUP_BARS_SIZE_32_MB]  = 0x00001ULL;
-        m[PROC_SETUP_BARS_SIZE_16_MB]  = 0x00000ULL;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of FSP BAR sizes
-struct proc_setup_bars_fsp_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0x000ULL;
-        m[PROC_SETUP_BARS_SIZE_2_GB]   = 0x800ULL;
-        m[PROC_SETUP_BARS_SIZE_1_GB]   = 0xC00ULL;
-        m[PROC_SETUP_BARS_SIZE_512_MB] = 0xE00ULL;
-        m[PROC_SETUP_BARS_SIZE_256_MB] = 0xF00ULL;
-        m[PROC_SETUP_BARS_SIZE_128_MB] = 0xF80ULL;
-        m[PROC_SETUP_BARS_SIZE_64_MB]  = 0xFC0ULL;
-        m[PROC_SETUP_BARS_SIZE_32_MB]  = 0xFE0ULL;
-        m[PROC_SETUP_BARS_SIZE_16_MB]  = 0xFF0ULL;
-        m[PROC_SETUP_BARS_SIZE_8_MB]   = 0xFF8ULL;
-        m[PROC_SETUP_BARS_SIZE_4_MB]   = 0xFFCULL;
-        m[PROC_SETUP_BARS_SIZE_2_MB]   = 0xFFEULL;
-        m[PROC_SETUP_BARS_SIZE_1_MB]   = 0xFFFULL;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of FSP MMIO mask sizes
-struct proc_setup_bars_fsp_mmio_mask_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0xF;
-        m[PROC_SETUP_BARS_SIZE_2_GB]   = 0x7;
-        m[PROC_SETUP_BARS_SIZE_1_GB]   = 0x3;
-        m[PROC_SETUP_BARS_SIZE_512_MB] = 0x1;
-        m[PROC_SETUP_BARS_SIZE_256_MB] = 0x0;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of NX MMIO mask sizes
-struct proc_setup_bars_nx_mmio_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_16_GB] = 0x2;
-        m[PROC_SETUP_BARS_SIZE_16_MB] = 0x4;
-        m[PROC_SETUP_BARS_SIZE_1_MB]  = 0x3;
-        m[PROC_SETUP_BARS_SIZE_64_KB] = 0x1;
-        m[PROC_SETUP_BARS_SIZE_4_KB]  = 0x0;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of NPU MMIO mask sizes
-struct proc_setup_bars_npu_mmio_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_2_MB]   = 0x5;
-        m[PROC_SETUP_BARS_SIZE_1_MB]   = 0x4;
-        m[PROC_SETUP_BARS_SIZE_512_KB] = 0x3;
-        m[PROC_SETUP_BARS_SIZE_256_KB] = 0x2;
-        m[PROC_SETUP_BARS_SIZE_128_KB] = 0x1;
-        m[PROC_SETUP_BARS_SIZE_64_KB]  = 0x0;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of AS MMIO mask sizes
-struct proc_setup_bars_as_mmio_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_2_MB]   = 0x3;
-        m[PROC_SETUP_BARS_SIZE_1_MB]   = 0x2;
-        m[PROC_SETUP_BARS_SIZE_512_KB] = 0x1;
-        m[PROC_SETUP_BARS_SIZE_256_KB] = 0x0;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of HCA BAR sizes
-struct proc_setup_bars_hca_nm_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_2_TB]   = 0x1FFULL;
-        m[PROC_SETUP_BARS_SIZE_1_TB]   = 0x0FFULL;
-        m[PROC_SETUP_BARS_SIZE_512_GB] = 0x07FULL;
-        m[PROC_SETUP_BARS_SIZE_256_GB] = 0x03FULL;
-        m[PROC_SETUP_BARS_SIZE_128_GB] = 0x01FULL;
-        m[PROC_SETUP_BARS_SIZE_64_GB]  = 0x00FULL;
-        m[PROC_SETUP_BARS_SIZE_32_GB]  = 0x007ULL;
-        m[PROC_SETUP_BARS_SIZE_16_GB]  = 0x003ULL;
-        m[PROC_SETUP_BARS_SIZE_8_GB]   = 0x001ULL;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0x000ULL;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of MCD BAR sizes
-struct proc_setup_bars_mcd_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_32_TB]  = 0x1FFFFFULL;
-        m[PROC_SETUP_BARS_SIZE_16_TB]  = 0x0FFFFFULL;
-        m[PROC_SETUP_BARS_SIZE_8_TB]   = 0x07FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_4_TB]   = 0x03FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_2_TB]   = 0x01FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_1_TB]   = 0x00FFFFULL;
-        m[PROC_SETUP_BARS_SIZE_512_GB] = 0x007FFFULL;
-        m[PROC_SETUP_BARS_SIZE_256_GB] = 0x003FFFULL;
-        m[PROC_SETUP_BARS_SIZE_128_GB] = 0x001FFFULL;
-        m[PROC_SETUP_BARS_SIZE_64_GB]  = 0x000FFFULL;
-        m[PROC_SETUP_BARS_SIZE_32_GB]  = 0x0007FFULL;
-        m[PROC_SETUP_BARS_SIZE_16_GB]  = 0x0003FFULL;
-        m[PROC_SETUP_BARS_SIZE_8_GB]   = 0x0001FFULL;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0x0000FFULL;
-        m[PROC_SETUP_BARS_SIZE_2_GB]   = 0x00007FULL;
-        m[PROC_SETUP_BARS_SIZE_1_GB]   = 0x00003FULL;
-        m[PROC_SETUP_BARS_SIZE_512_MB] = 0x00001FULL;
-        m[PROC_SETUP_BARS_SIZE_256_MB] = 0x00000FULL;
-        m[PROC_SETUP_BARS_SIZE_128_MB] = 0x000007ULL;
-        m[PROC_SETUP_BARS_SIZE_64_MB]  = 0x000003ULL;
-        m[PROC_SETUP_BARS_SIZE_32_MB]  = 0x000001ULL;
-        m[PROC_SETUP_BARS_SIZE_16_MB]  = 0x000000ULL;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// define set of PCIe MMIO BAR (BAR0/1 only) sizes
-struct proc_setup_bars_pcie_bar_size
-{
-    static std::map<uint64_t, uint64_t> create_map()
-    {
-        std::map<uint64_t, uint64_t> m;
-        m[PROC_SETUP_BARS_SIZE_1_PB]   = 0x000000000ULL;
-        m[PROC_SETUP_BARS_SIZE_512_TB] = 0x200000000ULL;
-        m[PROC_SETUP_BARS_SIZE_256_TB] = 0x300000000ULL;
-        m[PROC_SETUP_BARS_SIZE_128_TB] = 0x380000000ULL;
-        m[PROC_SETUP_BARS_SIZE_64_TB]  = 0x3C0000000ULL;
-        m[PROC_SETUP_BARS_SIZE_32_TB]  = 0x3E0000000ULL;
-        m[PROC_SETUP_BARS_SIZE_16_TB]  = 0x3F0000000ULL;
-        m[PROC_SETUP_BARS_SIZE_8_TB]   = 0x3F8000000ULL;
-        m[PROC_SETUP_BARS_SIZE_4_TB]   = 0x3FC000000ULL;
-        m[PROC_SETUP_BARS_SIZE_2_TB]   = 0x3FE000000ULL;
-        m[PROC_SETUP_BARS_SIZE_1_TB]   = 0x3FF000000ULL;
-        m[PROC_SETUP_BARS_SIZE_512_GB] = 0x3FF800000ULL;
-        m[PROC_SETUP_BARS_SIZE_256_GB] = 0x3FFC00000ULL;
-        m[PROC_SETUP_BARS_SIZE_128_GB] = 0x3FFE00000ULL;
-        m[PROC_SETUP_BARS_SIZE_64_GB]  = 0x3FFF00000ULL;
-        m[PROC_SETUP_BARS_SIZE_32_GB]  = 0x3FFF80000ULL;
-        m[PROC_SETUP_BARS_SIZE_16_GB]  = 0x3FFFC0000ULL;
-        m[PROC_SETUP_BARS_SIZE_8_GB]   = 0x3FFFE0000ULL;
-        m[PROC_SETUP_BARS_SIZE_4_GB]   = 0x3FFFF0000ULL;
-        m[PROC_SETUP_BARS_SIZE_2_GB]   = 0x3FFFF8000ULL;
-        m[PROC_SETUP_BARS_SIZE_1_GB]   = 0x3FFFFC000ULL;
-        m[PROC_SETUP_BARS_SIZE_512_MB] = 0x3FFFFE000ULL;
-        m[PROC_SETUP_BARS_SIZE_256_MB] = 0x3FFFFF000ULL;
-        m[PROC_SETUP_BARS_SIZE_128_MB] = 0x3FFFFF800ULL;
-        m[PROC_SETUP_BARS_SIZE_64_MB]  = 0x3FFFFFC00ULL;
-        m[PROC_SETUP_BARS_SIZE_32_MB]  = 0x3FFFFFE00ULL;
-        m[PROC_SETUP_BARS_SIZE_16_MB]  = 0x3FFFFFF00ULL;
-        m[PROC_SETUP_BARS_SIZE_8_MB]   = 0x3FFFFFF80ULL;
-        m[PROC_SETUP_BARS_SIZE_4_MB]   = 0x3FFFFFFC0ULL;
-        m[PROC_SETUP_BARS_SIZE_2_MB]   = 0x3FFFFFFE0ULL;
-        m[PROC_SETUP_BARS_SIZE_1_MB]   = 0x3FFFFFFF0ULL;
-        m[PROC_SETUP_BARS_SIZE_512_KB] = 0x3FFFFFFF8ULL;
-        m[PROC_SETUP_BARS_SIZE_256_KB] = 0x3FFFFFFFCULL;
-        m[PROC_SETUP_BARS_SIZE_128_KB] = 0x3FFFFFFFEULL;
-        m[PROC_SETUP_BARS_SIZE_64_KB]  = 0x3FFFFFFFFULL;
-        return m;
-    }
-    static const std::map<uint64_t, uint64_t> xlate_map;
-};
-
-// structure to represent logical HW BAR properties
-struct proc_setup_bars_bar_def
-{
-    // mask for implemented base address bits (1 for all non implemented bits)
-    uint64_t base_addr_mask;
-    // minimum/maximum supported size values
-    uint64_t size_min;
-    uint64_t size_max;
-    // check that base address/size are aligned?
-    bool check_aligned;
-};
-
-// define set of supported shift operations for aligning logical
-// BAR base address to physical position in HW register
-enum proc_setup_bars_shift_base
-{
-    PROC_SETUP_BARS_SHIFT_LEFT,
-    PROC_SETUP_BARS_SHIFT_RIGHT,
-    PROC_SETUP_BARS_SHIFT_NONE
-};
-
-// set of BAR/range attribute identifiers
-enum proc_setup_bars_attr_id
-{
-    PROC_SETUP_BARS_ATTR_ID_NM = 0,
-    PROC_SETUP_BARS_ATTR_ID_M = 1,
-    PROC_SETUP_BARS_ATTR_ID_FN = 2,
-    PROC_SETUP_BARS_ATTR_ID_FF = 3,
-    PROC_SETUP_BARS_ATTR_ID_PSI = 4,
-    PROC_SETUP_BARS_ATTR_ID_FSP = 5,
-    PROC_SETUP_BARS_ATTR_ID_FSP_MMIO = 6,
-    PROC_SETUP_BARS_ATTR_ID_INTP = 7,
-    PROC_SETUP_BARS_ATTR_ID_NX = 8,
-    PROC_SETUP_BARS_ATTR_ID_AS = 9,
-    PROC_SETUP_BARS_ATTR_ID_PCIE = 10,
-    PROC_SETUP_BARS_ATTR_ID_NPU = 11
-};
-
-// encoding for RC_PROC_SETUP_BARS_ATTR_LOOKUP_ERR types
-enum proc_setup_bars_attr_lookup_err_type
-{
-    PROC_SETUP_BARS_BASE_ADDR_ATTR_LOOKUP_ERR = 0,
-    PROC_SETUP_BARS_ENABLE_ATTR_LOOKUP_ERR = 1,
-    PROC_SETUP_BARS_SIZE_ATTR_LOOKUP_ERR = 2
-};
-
-// structure to represent physical HW BAR register programming
-struct proc_setup_bars_bar_reg_def
-{
-    // base address programming information
-    bool has_base;
-    proc_setup_bars_shift_base base_shift;
-    uint8_t base_shift_amount;
-    uint8_t base_start_bit;
-    uint8_t base_end_bit;
-    // enable programming information
-    bool has_enable;
-    uint8_t enable_bit;
-    // size programming information
-    bool has_size;
-    uint8_t size_start_bit;
-    uint8_t size_end_bit;
-    // translate logical size to register programming
-    const std::map<uint64_t, uint64_t>* xlate_map;
-    // static value/mask to be written along with BAR content
-    uint64_t static_data;
-    uint64_t static_data_mask;
-};
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// non-mirrored range constants
-const proc_setup_bars_bar_def non_mirrored_range_def =
-{
-    0xFFFC0000FFFFFFFFULL,         // base: RA 14:63
-    PROC_SETUP_BARS_SIZE_4_GB,     // size (min): 4 GB
-    PROC_SETUP_BARS_SIZE_4_TB,     // size (max): 4 TB
-    false
-};
-
-// mirrored range constants
-const proc_setup_bars_bar_def mirrored_range_def =
-{
-    0xFFFC0000FFFFFFFFULL,         // base: RA 14:63
-    PROC_SETUP_BARS_SIZE_2_GB,     // size (min): 2 GB
-    PROC_SETUP_BARS_SIZE_2_TB,     // size (max): 2 TB
-    false
-};
-
-// shared non-foreign BAR design (mirrored/non-mirrored regions) constants
-const proc_setup_bars_bar_def common_nf_scope_bar_def =
-{
-    0xFFFC0000FFFFFFFFULL,         // base: RA 14:31
-    PROC_SETUP_BARS_SIZE_4_GB,     // size (min): 4 GB
-    PROC_SETUP_BARS_SIZE_64_TB,    // size (min): 64 TB
-    true
-};
-
-const proc_setup_bars_bar_reg_def common_nf_scope_bar_reg_def =
-{
-    true,                          // base: bits 15:32
-    PROC_SETUP_BARS_SHIFT_RIGHT,
-    1,
-    15,
-    32,
-    true,                          // enable: bit 0
-    0,
-    true,                          // size: bits 1:14
-    1,
-    14,
-    &proc_setup_bars_nf_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// shared foreign BAR design (near/far regions) constants
-const fapi::AttributeId f_near_range_base_addr_attr = fapi::ATTR_PROC_FOREIGN_NEAR_BASE;
-const fapi::AttributeId f_near_range_size_attr = fapi::ATTR_PROC_FOREIGN_NEAR_SIZE;
-
-const fapi::AttributeId f_far_range_base_addr_attr = fapi::ATTR_PROC_FOREIGN_FAR_BASE;
-const fapi::AttributeId f_far_range_size_attr = fapi::ATTR_PROC_FOREIGN_FAR_SIZE;
-
-const proc_setup_bars_bar_def common_f_scope_bar_def =
-{
-    0xFFFC000000FFFFFFULL,         // base: RA 14:39
-    PROC_SETUP_BARS_SIZE_16_MB,    // size (min): 16 MB
-    PROC_SETUP_BARS_SIZE_8_TB,     // size (min): 8 TB
-    true
-};
-
-const proc_setup_bars_bar_reg_def common_f_scope_bar_reg_def =
-{
-    true,                          // base: bits 20:45
-    PROC_SETUP_BARS_SHIFT_RIGHT,
-    6,
-    20,
-    45,
-    true,                          // enable: bit 0
-    0,
-    true,                          // size: bits 1:19
-    1,
-    19,
-    &proc_setup_bars_f_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// PSI BAR constants
-const fapi::AttributeId psi_bridge_bar_base_addr_attr = fapi::ATTR_PROC_PSI_BRIDGE_BAR_BASE_ADDR;
-const fapi::AttributeId psi_bridge_bar_en_attr = fapi::ATTR_PROC_PSI_BRIDGE_BAR_ENABLE;
-
-const proc_setup_bars_bar_def psi_bridge_bar_def =
-{
-    0xFFFC0000000FFFFFULL,         // base: RA 14:43
-    PROC_SETUP_BARS_SIZE_1_MB,     // size (min): 1 MB
-    PROC_SETUP_BARS_SIZE_1_MB,     // size (max): 1 MB
-    true
-};
-
-const proc_setup_bars_bar_reg_def psi_bridge_bar_reg_def =
-{
-    true,                          // base: bits 14:43
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    43,
-    true,                          // enable: bit 63
-    63,
-    false,                         // size: implied
-    0,
-    0,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-// FSP BAR constants
-const fapi::AttributeId fsp_bar_base_addr_attr = fapi::ATTR_PROC_FSP_BAR_BASE_ADDR;
-const fapi::AttributeId fsp_bar_en_attr = fapi::ATTR_PROC_FSP_BAR_ENABLE;
-const fapi::AttributeId fsp_bar_size_attr = fapi::ATTR_PROC_FSP_BAR_SIZE;
-
-const proc_setup_bars_bar_def fsp_bar_def =
-{
-    0xFFFC0000000FFFFFULL,         // base: RA 14:43
-    PROC_SETUP_BARS_SIZE_1_MB,     // size (min): 1 MB
-    PROC_SETUP_BARS_SIZE_4_GB,     // size (max): 4 GB
-    true
-};
-
-const proc_setup_bars_bar_reg_def fsp_bar_reg_def =
-{
-    true,                          // base: bits 14:43
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    43,
-    false,                         // enable: other reg
-    0,
-    false,                         // size: other reg
-    0,
-    0,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-const proc_setup_bars_bar_reg_def fsp_bar_mask_reg_def =
-{
-    false,                         // base: other reg
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    0,
-    0,
-    false,                         // enable: other reg
-    0,
-    true,                          // size: 32:43
-    32,
-    43,
-    &proc_setup_bars_fsp_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-const proc_setup_bars_bar_reg_def fsp_bar_en_reg_def =
-{
-    false,                         // base: other reg
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    0,
-    0,
-    true,                          // enable: bit 1
-    1,
-    false,                         // size: other reg
-    0,
-    0,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-// FSP MMIO mask constants
-const fapi::AttributeId fsp_mmio_mask_size_attr = fapi::ATTR_PROC_FSP_MMIO_MASK_SIZE;
-
-const proc_setup_bars_bar_def fsp_mmio_mask_def =
-{
-    0xFFFFFFFFFFFFFFFFULL,         // base: unused
-    PROC_SETUP_BARS_SIZE_256_MB,   // size (min): 256 MB
-    PROC_SETUP_BARS_SIZE_4_GB,     // size (max): 4 GB
-    true
-};
-
-const proc_setup_bars_bar_reg_def fsp_mmio_mask_reg_def =
-{
-    false,                         // base: unused
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    0,
-    0,
-    false,                         // enable: unused
-    0,
-    true,                          // size: bits 8:11
-    8,
-    11,
-    &proc_setup_bars_fsp_mmio_mask_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// INTP BAR constants
-const fapi::AttributeId intp_bar_base_addr_attr = fapi::ATTR_PROC_INTP_BAR_BASE_ADDR;
-const fapi::AttributeId intp_bar_en_attr = fapi::ATTR_PROC_INTP_BAR_ENABLE;
-
-const proc_setup_bars_bar_def intp_bar_def =
-{
-    0xFFFC0000000FFFFFULL,         // base: RA 14:43
-    PROC_SETUP_BARS_SIZE_1_MB,     // size (min): 1 MB
-    PROC_SETUP_BARS_SIZE_1_MB,     // size (max): 1 MB
-    true
-};
-
-const proc_setup_bars_bar_reg_def intp_bar_reg_def =
-{
-    true,                          // base: bits 0:29
-    PROC_SETUP_BARS_SHIFT_LEFT,
-    14,
-    0,
-    29,
-    true,                          // enable: bit 30
-    30,
-    false,                         // size: implied
-    0,
-    0,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-// L3 BAR constants
-const uint32_t L3_BAR12_BASE_ADDR_LEFT_SHIFT_AMOUNT = 14;
-const uint32_t L3_BAR12_SIZE_END_BIT = 34;
-const uint32_t L3_BAR2_ENABLE_BIT = 35;
-
-const uint32_t L3_BAR_GROUP_MASK_RA_DIFF_START_BIT = 18;
-const uint32_t L3_BAR_GROUP_MASK_RA_DIFF_END_BIT = 31;
-
-const uint32_t L3_BAR_GROUP_MASK_NON_MIRROR_MASK_START_BIT = 3;
-const uint32_t L3_BAR_GROUP_MASK_NON_MIRROR_MASK_END_BIT = 16;
-
-const uint32_t L3_BAR_GROUP_MASK_MIRROR_MASK_START_BIT = 20;
-const uint32_t L3_BAR_GROUP_MASK_MIRROR_MASK_END_BIT = 33;
-const uint32_t L3_BAR_GROUP_MASK_MIRROR_ENABLE_BIT = 34;
-
-// NX MMIO BAR constants
-const fapi::AttributeId nx_mmio_bar_base_addr_attr = fapi::ATTR_PROC_NX_MMIO_BAR_BASE_ADDR;
-const fapi::AttributeId nx_mmio_bar_en_attr = fapi::ATTR_PROC_NX_MMIO_BAR_ENABLE;
-const fapi::AttributeId nx_mmio_bar_size_attr = fapi::ATTR_PROC_NX_MMIO_BAR_SIZE;
-
-const proc_setup_bars_bar_def nx_mmio_bar_def =
-{
-    0xFFFC000000000FFFULL,         // base: RA 14:51
-    PROC_SETUP_BARS_SIZE_4_KB,     // size (min): 4 KB
-    PROC_SETUP_BARS_SIZE_16_GB,    // size (max): 16 GB
-    true
-};
-
-const proc_setup_bars_bar_reg_def nx_mmio_bar_reg_def =
-{
-    true,                          // base: bits 14:51
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    51,
-    true,                          // enable: bit 52
-    52,
-    true,                          // size: bits 53:55
-    53,
-    55,
-    &proc_setup_bars_nx_mmio_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// AS MMIO BAR constants
-const fapi::AttributeId as_mmio_bar_base_addr_attr = fapi::ATTR_PROC_AS_MMIO_BAR_BASE_ADDR;
-const fapi::AttributeId as_mmio_bar_en_attr = fapi::ATTR_PROC_AS_MMIO_BAR_ENABLE;
-const fapi::AttributeId as_mmio_bar_size_attr = fapi::ATTR_PROC_AS_MMIO_BAR_SIZE;
-
-const proc_setup_bars_bar_def as_mmio_bar_def =
-{
-    0xFFFC000000000FFFULL,         // base: RA 14:51
-    PROC_SETUP_BARS_SIZE_4_KB,     // size (min): 4 KB
-    PROC_SETUP_BARS_SIZE_16_GB,    // size (max): 16 GB
-    true
-};
-
-const proc_setup_bars_bar_reg_def as_mmio_bar_reg_def =
-{
-    true,                          // base: bits 14:51
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    51,
-    true,                          // enable: bit 52
-    52,
-    true,                          // size: bits 53:55
-    53,
-    55,
-    &proc_setup_bars_as_mmio_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// NPU BAR constants
-const uint32_t PROC_SETUP_BARS_NPU_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] =
-{
-    NPU0_NODAL_BAR0_0x08013C04,
-    NPU1_NODAL_BAR0_0x08013C44,
-    NPU2_NODAL_BAR0_0x08013D04,
-    NPU3_NODAL_BAR0_0x08013D44
-};
-
-const uint32_t PROC_SETUP_BARS_NPU_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] =
-{
-    NPU0_NODAL_BAR1_0x08013C05,
-    NPU1_NODAL_BAR1_0x08013C45,
-    NPU2_NODAL_BAR1_0x08013D05,
-    NPU3_NODAL_BAR1_0x08013D45
-};
-
-const uint32_t PROC_SETUP_BARS_NPU_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] =
-{
-    NPU0_GROUP_BAR0_0x08013C06,
-    NPU1_GROUP_BAR0_0x08013C46,
-    NPU2_GROUP_BAR0_0x08013D06,
-    NPU3_GROUP_BAR0_0x08013D46
-};
-
-const uint32_t PROC_SETUP_BARS_NPU_NODE_MIRRORED_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS] =
-{
-    NPU0_GROUP_BAR1_0x08013C07,
-    NPU1_GROUP_BAR1_0x08013C47,
-    NPU2_GROUP_BAR1_0x08013D07,
-    NPU3_GROUP_BAR1_0x08013D47
-};
-
-// NPU MMIO BAR constants
-const uint32_t PROC_SETUP_BARS_NPU_MMIO_BAR[PROC_SETUP_BARS_NPU_NUM_UNITS][PROC_SETUP_BARS_NPU_MMIO_RANGES_PER_UNIT] =
-{
-    {
-        NPU0_MMIO_BAR0_0x08013C02,
-        NPU0_MMIO_BAR1_0x08013C03
-    },
-    {
-        NPU1_MMIO_BAR0_0x08013C42,
-        NPU1_MMIO_BAR1_0x08013C43
-    },
-    {
-        NPU2_MMIO_BAR0_0x08013D02,
-        NPU2_MMIO_BAR1_0x08013D03
-    },
-    {
-        NPU3_MMIO_BAR0_0x08013D42,
-        NPU3_MMIO_BAR1_0x08013D43
-    }
-};
-
-const fapi::AttributeId npu_mmio_bar_base_addr_attr = fapi::ATTR_PROC_NPU_MMIO_BAR_BASE_ADDR;
-const fapi::AttributeId npu_mmio_bar_en_attr = fapi::ATTR_PROC_NPU_MMIO_BAR_ENABLE;
-const fapi::AttributeId npu_mmio_bar_size_attr = fapi::ATTR_PROC_NPU_MMIO_BAR_SIZE;
-
-const proc_setup_bars_bar_def npu_mmio_bar_def =
-{
-    0xFFFC000000000FFFULL,         // base: RA 14:51
-    PROC_SETUP_BARS_SIZE_64_KB,    // size (min): 64 KB
-    PROC_SETUP_BARS_SIZE_2_MB,     // size (max): 2 MB
-    true
-};
-
-const proc_setup_bars_bar_reg_def npu_mmio_bar_reg_def =
-{
-    true,                          // base: bits 14:51
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    51,
-    true,                          // enable: bit 52
-    52,
-    true,                          // size: bits 53:55
-    53,
-    55,
-    &proc_setup_bars_npu_mmio_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// HCA BAR and Range register constants
-const proc_setup_bars_bar_reg_def hca_nm_bar_reg_def =
-{
-    true,                          // base: bits 14:31
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    31,
-    false,                         // enable: bit 63 (off for SW258328)
-    63,
-    true,                          // size: bits 32:40
-    32,
-    40,
-    &proc_setup_bars_hca_nm_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL
-};
-
-// HCA Mirror BAR and Range register constants
-const proc_setup_bars_bar_reg_def hca_m_bar_reg_def =
-{
-    true,                          // base: bits 14:32
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    14,
-    32,
-    false,                         // enable: bit 63 (off for SW258328)
-    63,
-    false,                         // size: other reg
-    0,
-    0,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-// MCD Configuration Register constants
-const proc_setup_bars_bar_reg_def mcd_nf_bar_reg_def =
-{
-    true,                          // base: bits 30:55
-    PROC_SETUP_BARS_SHIFT_RIGHT,
-    16,
-    30,
-    55,
-    true,                          // enable: bit 0
-    0,
-    true,                          // size: bits 9:29
-    9,
-    29,
-    &proc_setup_bars_mcd_bar_size::xlate_map,
-    0x4000000000000000ULL,         // 1 config/group, system scope
-    0x780000000000001CULL
-};
-
-const proc_setup_bars_bar_reg_def mcd_f0_bar_reg_def =
-{
-    true,                          // base: bits 30:55
-    PROC_SETUP_BARS_SHIFT_RIGHT,
-    16,
-    30,
-    55,
-    true,                          // enable: bit 0
-    0,
-    true,                          // size: bits 9:29
-    9,
-    29,
-    &proc_setup_bars_mcd_bar_size::xlate_map,
-    0x4000000000000010ULL,         // 1 config/group, foreign scope, f0 link
-    0x780000000000001CULL
-};
-
-const proc_setup_bars_bar_reg_def mcd_f1_bar_reg_def =
-{
-    true,                          // base: bits 30:55
-    PROC_SETUP_BARS_SHIFT_RIGHT,
-    16,
-    30,
-    55,
-    true,                          // enable: bit 0
-    0,
-    true,                          // size: bits 9:29
-    9,
-    29,
-    &proc_setup_bars_mcd_bar_size::xlate_map,
-    0x4000000000000014ULL,         // 1 config/group, foreign scope, f1 link
-    0x780000000000001CULL
-};
-
-// MCD FIR Register constants
-const uint64_t MCD_FIR_MASK_RUNTIME_VAL = 0x2FC0000000000000ULL;
-
-// MCD Evn/Odd Recovery Control Register field/bit definitions
-const uint8_t PROC_SETUP_BARS_NUM_MCD_CFG = 4;
-
-const uint64_t MCD_RECOVERY_ENABLE_BIT = 0;
-const uint64_t MCD_RECOVERY_CFG_EN_BIT[PROC_SETUP_BARS_NUM_MCD_CFG] = {40,41,42,43};
-
-// PCIe BAR constants
-const uint32_t PROC_SETUP_BARS_PCIE_CHIP_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    PCIE0_NODAL_BAR0_0x02012010,
-    PCIE1_NODAL_BAR0_0x02012410,
-    PCIE2_NODAL_BAR0_0x02012810,
-    PCIE3_NODAL_BAR0_0x02012C10,
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_CHIP_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    PCIE0_NODAL_BAR1_0x02012011,
-    PCIE1_NODAL_BAR1_0x02012411,
-    PCIE2_NODAL_BAR1_0x02012811,
-    PCIE3_NODAL_BAR1_0x02012C11
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_NODE_NON_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    PCIE0_GROUP_BAR0_0x02012012,
-    PCIE1_GROUP_BAR0_0x02012412,
-    PCIE2_GROUP_BAR0_0x02012812,
-    PCIE3_GROUP_BAR0_0x02012C12
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_NODE_MIRRORED_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    PCIE0_GROUP_BAR1_0x02012013,
-    PCIE1_GROUP_BAR1_0x02012413,
-    PCIE2_GROUP_BAR1_0x02012813,
-    PCIE3_GROUP_BAR1_0x02012C13
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_NEAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] =
-{
-    {
-        PCIE0_NEAR_BAR_F0_0x02012014,
-        PCIE0_NEAR_BAR_F1_0x02012016
-    },
-    {
-        PCIE1_NEAR_BAR_F0_0x02012414,
-        PCIE1_NEAR_BAR_F1_0x02012416
-    },
-    {
-        PCIE2_NEAR_BAR_F0_0x02012814,
-        PCIE2_NEAR_BAR_F1_0x02012816
-    },
-    {
-        PCIE3_NEAR_BAR_F0_0x02012C14,
-        PCIE3_NEAR_BAR_F1_0x02012C16
-    }
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_FOREIGN_FAR_BAR[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_FAB_SMP_NUM_F_LINKS] =
-{
-    {
-        PCIE0_FAR_BAR_F0_0x02012015,
-        PCIE0_FAR_BAR_F1_0x02012017
-    },
-    {
-        PCIE1_FAR_BAR_F0_0x02012415,
-        PCIE1_FAR_BAR_F1_0x02012417
-    },
-    {
-        PCIE2_FAR_BAR_F0_0x02012815,
-        PCIE2_FAR_BAR_F1_0x02012817
-    },
-    {
-        PCIE3_FAR_BAR_F0_0x02012C15,
-        PCIE3_FAR_BAR_F1_0x02012C17
-    }
-};
-
-const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO = 2;
-const uint8_t PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_PHB  = 1;
-const uint8_t PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE   = 2;
-
-const uint8_t PROC_SETUP_BARS_PCIE_RANGE_TYPE_MMIO[PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT] =
-{
-    true,   // BAR 0 = MMIO (primary)
-    true,   // BAR 1 = MMIO (backup/failover)
-    false,  // BAR 2 = PHB
-};
-
-const fapi::AttributeId pcie_mmio_bar_base_addr_attr = fapi::ATTR_PROC_PCIE_BAR_BASE_ADDR;
-const fapi::AttributeId pcie_mmio_bar_en_attr = fapi::ATTR_PROC_PCIE_BAR_ENABLE;
-const fapi::AttributeId pcie_mmio_bar_size_attr = fapi::ATTR_PROC_PCIE_BAR_SIZE;
-
-const proc_setup_bars_bar_def pcie_mmio_bar_def =
-{
-    0xFFFC00000000FFFFULL,         // base: RA 14:47
-    PROC_SETUP_BARS_SIZE_64_KB,    // size (min): 64 KB
-    PROC_SETUP_BARS_SIZE_1_PB,     // size (min): 1 PB
-    true
-};
-
-const proc_setup_bars_bar_reg_def pcie_mmio_bar_reg_def =
-{
-    true,                          // base: bits 0:33
-    PROC_SETUP_BARS_SHIFT_LEFT,
-    14,
-    0,
-    33,
-    false,                         // enable: other reg
-    0,
-    false,                         // size: other reg
-    0,
-    0,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO] =
-{
-    {
-        PCIE0_IO_BAR0_0x02012040,
-        PCIE0_IO_BAR1_0x02012041
-    },
-    {
-        PCIE1_IO_BAR0_0x02012440,
-        PCIE1_IO_BAR1_0x02012441
-    },
-    {
-        PCIE2_IO_BAR0_0x02012840,
-        PCIE2_IO_BAR1_0x02012841
-    },
-    {
-        PCIE3_IO_BAR0_0x02012C40,
-        PCIE3_IO_BAR1_0x02012C41
-    }
-};
-
-const proc_setup_bars_bar_reg_def pcie_mmio_bar_mask_reg_def =
-{
-    false,                         // base: other reg
-    PROC_SETUP_BARS_SHIFT_NONE,
-    0,
-    0,
-    0,
-    false,                         // enable: other reg
-    0,
-    true,                          // size: bits 0:33
-    0,
-    33,
-    &proc_setup_bars_pcie_bar_size::xlate_map,
-    0x0ULL,
-    0x0ULL,
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_BAR_MASK_REGS_MMIO[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_RANGES_PER_UNIT_MMIO] =
-{
-    {
-        PCIE0_IO_MASK0_0x02012043,
-        PCIE0_IO_MASK1_0x02012044
-    },
-    {
-        PCIE1_IO_MASK0_0x02012443,
-        PCIE1_IO_MASK1_0x02012444
-    },
-    {
-        PCIE2_IO_MASK0_0x02012843,
-        PCIE2_IO_MASK1_0x02012844
-    },
-    {
-        PCIE3_IO_MASK0_0x02012C43,
-        PCIE3_IO_MASK1_0x02012C44
-    }
-};
-
-const proc_setup_bars_bar_def pcie_phb_bar_def =
-{
-    0xFFFC000000000FFFULL,         // base: RA 14:51
-    PROC_SETUP_BARS_SIZE_4_KB,     // size (min): 4 KB
-    PROC_SETUP_BARS_SIZE_4_KB,     // size (min): 4 KB
-    true
-};
-
-const proc_setup_bars_bar_reg_def pcie_phb_bar_reg_def =
-{
-    true,                          // base: bits 0:37
-    PROC_SETUP_BARS_SHIFT_LEFT,
-    14,
-    0,
-    37,
-    false,                         // enable: other reg
-    0,
-    false,                         // size: implied
-    0,
-    33,
-    NULL,
-    0x0ULL,
-    0x0ULL
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_BAR_REGS_PHB[PROC_SETUP_BARS_PCIE_NUM_UNITS][PROC_SETUP_BARS_PCIE_REGS_PER_PHB_RANGE] =
-{
-    {
-        PCIE0_IO_BAR2_0x02012042,
-        PCIE0_ASB_BAR_0x0901200B
-    },
-    {
-        PCIE1_IO_BAR2_0x02012442,
-        PCIE1_ASB_BAR_0x0901240B
-    },
-    {
-        PCIE2_IO_BAR2_0x02012842,
-        PCIE2_ASB_BAR_0x0901280B
-    },
-    {
-        PCIE3_IO_BAR2_0x02012C42,
-        PCIE3_ASB_BAR_0x09012C0B
-    }
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_BIT[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    0x0,
-    0x1,
-    0x2
-};
-
-const uint32_t PROC_SETUP_BARS_PCIE_BAR_EN_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    PCIE0_IO_BAR_EN_0x02012045,
-    PCIE1_IO_BAR_EN_0x02012445,
-    PCIE2_IO_BAR_EN_0x02012845,
-    PCIE3_IO_BAR_EN_0x02012C45
-};
-
-// ETU Reset register field/bit definitions
-const uint32_t PROC_SETUP_BARS_PCIE_ETU_RESET_REGS[PROC_SETUP_BARS_PCIE_NUM_UNITS] =
-{
-    PCIE0_ETU_RESET_0x0901200A,
-    PCIE1_ETU_RESET_0x0901240A,
-    PCIE2_ETU_RESET_0x0901280A,
-    PCIE3_ETU_RESET_0x09012C0A
-};
-
-
-#endif // _PROC_SETUP_BARS_DEFS_H_
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C b/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C
deleted file mode 100755
index 4f6f18953..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C
+++ /dev/null
@@ -1,261 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_throttle_sync.C,v 1.6 2013/12/19 22:22:03 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_throttle_sync.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *!  Licensed material - Program property of IBM
-// *!  Refer to copyright instructions form no. G120-2083
-// *! Created on Tue Nov 12 2013 at 13:42:15
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_throttle_sync
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  :  Bellows Mark D.Email: bellows@us.ibm.com
-// *! BACKUP NAME :                 Email: ______@us.ibm.com
-
-// *! ADDITIONAL COMMENTS :
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.6   | bellows  |19-DEC-13| Fixed the minor (not functional) setting of rc_ecmd = for next set of data buffer commands
-//   1.5   | bellows  |13-DEC-13| One missed firmware review comment
-//   1.4   | bellows  |13-DEC-13| Firmware review updates
-//   1.3   | bellows  |06-DEC-13| Handle the MCS functional but no centaur case
-//   1.2   | bellows  |25-NOV-13| Functional Debug Performed
-//   1.1   | bellows  |12-NOV-13| Created.
-#include <fapi.H>
-#include <proc_throttle_sync.H>
-#include <p8_scom_addresses.H>
-
-extern "C" {
-
-  using namespace fapi;
-
-  const uint32_t MAX_SYNC_RETRIES = 1000;
-// run on one processor
-  ReturnCode proc_throttle_sync(fapi::Target & i_target_proc) {
-
-    ReturnCode rc;
-    ecmdDataBufferBase mask_buffer_64(64);
-    ecmdDataBufferBase data_buffer_64(64);
-    uint8_t l_attr_cen_ec_throttle_sync_possible;
-    uint32_t rc_ecmd;
-    uint8_t l_proc_attached_centaurs=0;
-    uint8_t l_summary_sync_possible=true;
-    uint32_t i=0;
-    std::vector<fapi::Target> l_target_attached_mcs;
-    fapi::Target cen_target;
-
-    do {
-    // determine how far into the IPL we have gone
-      rc = fapiGetChildChiplets( i_target_proc, TARGET_TYPE_MCS_CHIPLET, l_target_attached_mcs );
-      if (rc)
-      {
-        FAPI_ERR("Failed to find attached mcs\n");
-        break;
-      }
-
-// find the one mcs
-// also form the centaur vector
-      uint8_t theonemcs=0xff; // index into the MCS vector for the one MCS
-      uint8_t l_functional;
-      uint8_t unit_num[8];
-      uint8_t pos_attr_data;
-
-      for(i=0; i<8; i++) unit_num[i]=0xff;
-      for(i=0; i < l_target_attached_mcs.size(); i++) {
-        FAPI_INF("working on mcs %s\n", l_target_attached_mcs[i].toEcmdString());
-
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_target_attached_mcs[i], pos_attr_data);
-        if(rc) {
-          FAPI_ERR("ERROR: Unable to get ATTR_CHIP_UNIT_POS\n");
-          break;
-        }
-
-
-        rc = fapiGetOtherSideOfMemChannel( l_target_attached_mcs[i], cen_target );
-        if (rc)
-        {
-          FAPI_INF("--> this mcs does not have an attached centaur!\n");
-          rc=fapi::FAPI_RC_SUCCESS;
-        }
-        else {
-          unit_num[pos_attr_data] = i; // save in index back into the uint_num array
-
-          cen_target.setType(TARGET_TYPE_MEMBUF_CHIP);
-
-          // find out if this centaur can do a sync.  They should all be the same.  Give up if any aren't
-          // capable
-          rc = FAPI_ATTR_GET(ATTR_CEN_EC_THROTTLE_SYNC_POSSIBLE, &cen_target, l_attr_cen_ec_throttle_sync_possible);
-          if(rc) break;
-
-          if( ! l_attr_cen_ec_throttle_sync_possible) { // one or more are not DD2
-            FAPI_INF("--> the attached centaur is not capable of this type of sync\n");
-            l_summary_sync_possible=false;
-          }
-
-          // all functional centaurs form a vector to do a sync on
-          rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL, &cen_target,   l_functional);
-          if(rc) {
-            FAPI_ERR("Could not get ATTR_FUNCTIONAL");
-            break;
-          }
-          if(l_functional) {
-            l_proc_attached_centaurs |= ( 0x80 >> pos_attr_data );
-          }
-        }
-
-      }
-
-
-
-      if(l_summary_sync_possible) {
-        FAPI_INF("--> Because sync possible, running procedure\n");
-
-// SYNC PROCEDURE:
-// 1.) Determined the MCS to be the master
-//      Choose MC2.MCS0, since its on both Murano and Venice.
-//      However, if its deconfigured then the code will have to determine the next master per processor chip.
-//  [ This is determined by the platform.  The suggestion is to use MC2.MCS0, but if that is not available, pick a different one ]
-      // select the one
-        if(unit_num[4] != 0xFF) theonemcs=unit_num[4];
-        else if(unit_num[5] != 0xFF) theonemcs=unit_num[5];
-        else if(unit_num[6] != 0xFF) theonemcs=unit_num[6];
-        else if(unit_num[7] != 0xFF) theonemcs=unit_num[7];
-        else if(unit_num[0] != 0xFF) theonemcs=unit_num[0];
-        else if(unit_num[1] != 0xFF) theonemcs=unit_num[1];
-        else if(unit_num[2] != 0xFF) theonemcs=unit_num[2];
-        else if(unit_num[3] != 0xFF) theonemcs=unit_num[3];
-        else {
-          FAPI_IMP("Did not find a valid MCS on this processor %s\n", i_target_proc.toEcmdString());
-          break;
-        }
-
-        FAPI_INF("--> the one mcs is %s\n", l_target_attached_mcs[theonemcs].toEcmdString() );
-// 2.) Select which MCS to be the targets per processor.  You'll want to select the configured MCS's with Centaur attached, but it might still work if you select all of them.
-//       Bits 0:7 of MCSYNC Register (Scom addr 201180B) are the select bits.  These bits should be set on the master only.  They tell the master, which targets to send the sync commands.
-//
-// 	Here's the mapping, if you wish to select the configured MCS's only.  The red MCS's below are only on Venice chips.
-// 	Bit 0: MC0.MCS0
-// 	Bit 1: MC0.MCS1
-// 	Bit 2: MC1.MCS0
-// 	Bit 3: MC1.MCS1
-// 	Bit 4: MC2.MCS0
-// 	Bit 5: MC2.MCS1
-// 	Bit 6: MC3.MCS0
-// 	Bit 7: MC3.MCS1
-        bool l_sync_complete=false;
-        uint32_t l_tries=0;
-        while ( l_sync_complete == false && l_tries < 1000 ) {
-          rc_ecmd = ECMD_DBUF_SUCCESS;
-          FAPI_INF("--> Doing the sync sequence try is %d\n", l_tries );
-          rc_ecmd |= data_buffer_64.clearBit(0,64);
-          rc_ecmd |= mask_buffer_64.clearBit(0,64);
-
-          FAPI_INF("--> the vector of attached centaurs is %02x\n", l_proc_attached_centaurs );
-          for(i=0; i<8; i++) {
-            if((l_proc_attached_centaurs>>(7-i)) & 0x1) {
-              rc_ecmd |= data_buffer_64.setBit(i);
-            }
-            rc_ecmd |= mask_buffer_64.setBit(i);
-          }
-
-// 3.) Setup the sync commands to issue to centaur on the master MCS
-//      Bit 12 of MCSYNC Register is N/M Sync (Scom addr 201180B)
-//      Bit 15 of MCSYNC Register is PC Sync (Scom addr 201180B)
-
-          rc_ecmd |= data_buffer_64.setBit(12);
-          rc_ecmd |= mask_buffer_64.setBit(12);
-          rc_ecmd |= data_buffer_64.setBit(15);
-          rc_ecmd |= mask_buffer_64.setBit(15);
-          if(rc_ecmd) {
-            rc.setEcmdError(rc_ecmd);
-            break;
-          }
-          rc = fapiPutScomUnderMask(l_target_attached_mcs[theonemcs], MCS_MCSYNC_0x0201180B, data_buffer_64, mask_buffer_64);
-          if(rc) break;
-
-// 4.) Generate the Sync Command to Centaur from the master MCS
-//      Bit 0 of MCS Mode3 Register (Scom addr 201180A)
-//      (This bit needs a reset before another set, it does not reset automatically)
-          rc_ecmd = data_buffer_64.clearBit(0,64);
-          rc_ecmd |= data_buffer_64.setBit(0);
-          rc_ecmd |= mask_buffer_64.clearBit(0,64);
-          rc_ecmd |= mask_buffer_64.setBit(0);
-          if(rc_ecmd) {
-            rc.setEcmdError(rc_ecmd);
-            break;
-          }
-
-          rc = fapiPutScomUnderMask(l_target_attached_mcs[theonemcs], MCS_MODE3_REGISTER_0x0201180A, data_buffer_64, mask_buffer_64);
-          if(rc) break;
-
-          // this resets the before mentioned bit
-          rc_ecmd = data_buffer_64.clearBit(0);
-          if(rc_ecmd) {
-            rc.setEcmdError(rc_ecmd);
-            break;
-          }
-          rc = fapiPutScomUnderMask(l_target_attached_mcs[theonemcs], MCS_MODE3_REGISTER_0x0201180A, data_buffer_64, mask_buffer_64);
-          if(rc) break;
-
-// 5.) Read the SYNC status register on the master MCS
-//      Bits 1:7 of MCS Mode3 Register (Scom addr 201180A)
-//     If any status bit is set, this indicates that a replay has occurred on the DMI channel, repeat steps 3 and 4 above.
-// (actually to build the register back up, we go to step 2 to pick up the centaurs again)
-          rc = fapiGetScom(l_target_attached_mcs[theonemcs], MCS_MODE3_REGISTER_0x0201180A, data_buffer_64);
-          if(rc) break;
-
-          if(data_buffer_64.isBitClear(1,7) == true) {
-            l_sync_complete=true;
-          }
-          else {
-            l_tries++;
-            FAPI_INF("--> Not all ready, reissue the sync,  tries are %d\n", l_tries );
-            l_sync_complete=false;
-          }
-        }
-        if(rc) break;
-        if (l_tries == MAX_SYNC_RETRIES) {
-          FAPI_ERR("This processor did not see a successful MCSYNC\n");
-          FAPI_SET_HWP_ERROR(rc, RC_PROC_MCSYNC_THERMAL_RETRY_EXCEEDED);
-          break;
-        }
-        FAPI_INF("--> Success in running the sync sequence tries were %d\n", l_tries );
-
-      }
-    } while(0);
-
-    return rc;
-  }
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H b/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H
deleted file mode 100755
index 825758003..000000000
--- a/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H
+++ /dev/null
@@ -1,74 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync/proc_throttle_sync.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_throttle_sync.H,v 1.2 2013/11/25 21:13:13 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_throttle_sync.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *!  Licensed material - Program property of IBM
-// *!  Refer to copyright instructions form no. G120-2083
-// *! Created on Tue Nov 12 2013 at 13:42:15
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_throttle_sync
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  :  Bellows Mark D.Email: bellows@us.ibm.com
-// *! BACKUP NAME :                 Email: ______@us.ibm.com
-
-// *! ADDITIONAL COMMENTS :
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.2   | bellows  |25-NOV-13| Updated call to procedure
-//   1.1   | bellows  |12-NOV-13| Created.
-#ifndef __PROC_THROTTLE_SYNC_H
-#define __PROC_THROTTLE_SYNC_H
-
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-
-typedef fapi::ReturnCode (*proc_throttle_sync_FP_t)(fapi::Target &  i_target_proc );
-
-extern "C"
-{
-  using namespace fapi;
-
-/**
- * @brief proc_throttle_sync procedure. Sync all MBA below this processor when changing thermal parameters
- *
- * @param[in]   fapi::Target i_target_proc,              // Platform runs this on each processor *
- * @return ReturnCode
- */
-
-  ReturnCode proc_throttle_sync(fapi::Target &  i_target_proc );
-
-} // extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/dram_training/HBconfig b/src/usr/hwpf/hwp/dram_training/HBconfig
deleted file mode 100644
index 56d064030..000000000
--- a/src/usr/hwpf/hwp/dram_training/HBconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-config PALMETTO_VDDR
-    default n
-    help
-        Enable the Hostboot DRAM VDDR function for Palmetto
-
-config PCA95X_8BIT
-    default n
-    depends on (!PCA95X_16BIT)
-    help
-        Set the PCA95X support to an 8 bit chip.
-
-config PCA95X_16BIT
-    default y if (!PCA95X_8BIT)
-    depends on (!PCA95X_8BIT)
-    help
-        Set the PCA95X support to a 16 bit chip.
diff --git a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C b/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C
deleted file mode 100644
index 4275e1e9e..000000000
--- a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C
+++ /dev/null
@@ -1,1190 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_stopclocks.C,v 1.16 2014/01/16 17:49:16 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_stopclocks.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_stopclocks
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! SCREEN      : pervasive_screen
-// *! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure is to stop the clocks in the Centaur chip
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <cen_scom_addresses.H>
-#include <cen_stopclocks.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-// CFAM FSI GP4 register bit/field definitions
-const uint8_t FSI_GP4_MEMRESET_STABILITY_BIT  = 2;
-const uint8_t FSI_GP4_DPHY_PLLRESET_BIT       = 4;
-
-// PERVGP3 register bit/field definitions
-const uint8_t PERVGP3_VITL_CLKOFF_BIT   = 16;
-
-// GP3 register bit/field definitions
-const uint8_t GP3_VITAL_THOLD_BIT       = 16;
-const uint8_t GP3_FENCE_EN_BIT          = 18;
-const uint8_t GP3_EDRAM_ENABLE_BIT      = 28;
-
-// GP0 register bit/field definitions
-const uint8_t GP0_SYNCCLK_MUXSEL_BIT    = 1;
-const uint8_t GP0_FLUSHMODE_INHIBIT_BIT = 2;
-const uint8_t GP0_FORCE_ALIGN_BIT       = 3;
-const uint8_t GP0_SCAN_DIS_DC_B_BIT     = 6;
-const uint8_t GP0_ABIST_MODE_BIT        = 11;
-const uint8_t GP0_PERV_FENCE_BIT        = 63;
-
-// FSIGP3 register bit/field definitions
-const uint8_t FSIGP3_PIB2PCB_BYPASS_BIT = 20;
-const uint8_t FSIGP3_FSI_FENCE4_BIT     = 25;
-const uint8_t FSIGP3_FSI_FENCE5_BIT     = 26;
-
-// Global bit definitions for all CLK_REGIONS
-const uint8_t CLK_REGION_CLOCK_CMD_BIT      = 0;
-const uint8_t CLK_REGION_CLOCK_CMD_LEN      = 2;
-const uint8_t CLK_REGION_CLOCK_CMD_STOP     = 2;
-
-const uint8_t TP_CLK_STAT_NET_SL            = 3;
-const uint8_t TP_CLK_STAT_NET_NSL           = 4;
-const uint8_t TP_CLK_STAT_NET_ARY           = 5;
-const uint8_t TP_CLK_STAT_PIB_SL            = 6;
-const uint8_t TP_CLK_STAT_PIB_NSL           = 7;
-const uint8_t TP_CLK_STAT_PIB_ARY           = 8;
-
-
-// Clock Region Register clock stop data patterns
-// const uint64_t CLK_REGION_REG_DATA_TO_STOP_NSL_ARY = 0x8FE0060000000000ull;
-const uint64_t CLK_REGION_REG_DATA_TO_STOP_ALL     = 0x8FE00E0000000000ull;
-// const uint64_t CLK_REGION_STOP_NSL_ARY_W_REFRESH   = 0x8FC0060000000000ull;
-const uint64_t CLK_REGION_STOP_ALL_BUT_REFRESH     = 0x8FC00E0000000000ull;
-const uint64_t EXPECTED_CLOCK_STATUS               = 0xFFFFFFFFFFFFFFFFull;
-const uint64_t EXPECTED_CLOCK_STATUS_W_REFRESH     = 0xFFFFFF1FFFFFFFFFull;   // Bits 24,25,26 should be OFF for refresh clocks to be active.
-
-// Expected CLK_STAT after execution of stopclocks
-const uint32_t FSI_SHIFT_SET_PULSE_LENGTH      = 0x0000000F;
-
-
-
-
-extern "C" {
-
-using namespace fapi;
-
-//------------------------------------------------------------------------------
-// Function definition:  cen_stopclocks
-// parameters: i_target                =>   chip target
-//             i_stop_mem_clks         =>   True to stop MEM chiplet clocks                             (should default TRUE)
-//             i_stop_nest_clks        =>   True to stop NEST chiplet clocks (except DRAM refresh clk)  (should default TRUE)
-//             i_stop_dram_rfrsh_clks  =>   True to stop NEST chiplet DRAM refresh clocks (cache)       (should default FALSE)
-//             i_stop_tp_clks          =>   True to stop PERVASIVE (TP) chiplet clocks                  (should default FALSE)
-//             i_stop_vitl_clks        =>   True to stop PERVASIVE VITL clocks                          (should default FALSE)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode cen_stopclocks(const fapi::Target & i_target,
-                                const bool i_stop_mem_clks,
-                                const bool i_stop_nest_clks,
-                                const bool i_stop_dram_rfrsh_clks,
-                                const bool i_stop_tp_clks,
-                                const bool i_stop_vitl_clks)
-{
-    // Target is centaur chip
-
-    bool i2_stop_mem_clks;
-    bool i2_stop_nest_clks;
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase scom_data(64);
-    ecmdDataBufferBase cfam_data(32);
-
-    FAPI_INF("********* cen_stopclocks start *********");
-    do
-    {
-        // The instructions for coding this procedure came from Tobias Webel's Common POR Spreadsheet step 30.1
-        // Start with instructions common to all eclipz chips
-
-        // Set flushmode_inhibit in Chiplet GP0
-        // Set force_align in Chiplet GP0
-        // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop
-        // Write ClockControl, Clock Region Register, Clock Stop command (arrays + nsl only, not refresh clock region) MEM chiplet
-        // Write ClockControl, Clock Region Register, Clock Stop command (sl + refresh clock region) MEM chiplet
-        // Read Clock Status Register (MEM chiplet)
-        // Write ClockControl, Clock Region Register, Clock Stop command (arrays + nsl only, not refresh clock region) NEST chiplet
-        // Write ClockControl, Clock Region Register, Clock Stop command (sl + refresh clock region) NEST chiplet
-        // Read Clock Status Register (NEST chiplet)
-        // Reset MemReset Stablilty Control
-        // Reset D3PHY PLL Control (Reset all PLLs)
-        // reset abist_mode_dc for core chiplets (core recovery)
-        // set synclk_muxsel (io_clk_sel)
-        // assert perv fence GP0.63
-        // GP3(28) disable EDRAM (just chiplets with EDRAM logic)(skip this step if refresh clock domain stays running)
-        // assert fence GP3.18
-
-        // The following instructions were added by Jeshua Smith to put each chiplet in a good state for scanning:
-        // Set tc_scan_dis_dc_b to a '1' in each chiplet to allow rings to be scanned.
-        // TODO - compare these instructions agains the P7+ procedure to see if we are missing anything.
-
-        // Note:  This procedure should not do multicast to do all non-perv chiplets at the same time because the user could
-        //        wish to skip some of the chiplets!
-
-
-
-
-        //-----------------
-        //   Check options, VITL clock and PCB fabric clocks.   @@@
-        //-----------------
-
-        i2_stop_mem_clks  = i_stop_mem_clks;
-        i2_stop_nest_clks = i_stop_nest_clks;
-
-        // Before attempting to stop the clocks in any chiplet, check to see that the pervasive VITL clocks are running.
-        // Do this by checking bit 16 of the PERV GP3 register.
-        FAPI_DBG("Checking PERV GPP3 Register bit 16 to see if the VITL clock is ON.");
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000101B, cfam_data);
-        if (rc)
-        {
-            FAPI_ERR("Error getting PERV GP3 via CFAM");
-            break;
-        }
-        if (cfam_data.isBitSet(PERVGP3_VITL_CLKOFF_BIT))
-        {
-            // The Pervasive VITL clock is OFF. So we cannot talk to the chiplets.  There is nothing left to do, so just return.
-            FAPI_INF("The Pervasive VITL clock is OFF.  The procedure cannot access the chiplets or check other clocks.");
-            break;
-        }
-
-        // If we have gotten this far the Pervasive VITL clock must be ON.
-        // Check to see if the PCB fabric clocks are running.
-        // Do this by checking the PIB and NET clock regions in the TP chiplet (chiplet 01).
-        // Read Clock Status Register (TP chiplet)   0x0100008  
-        // Bits 3-8 should be ZERO if the PIB and NET clocks are running.
-        FAPI_DBG("Reading Clock Status Register in the TP chiplet to see if PIB and NET clocks are running. Bits 3-8 should be zero.");
-        rc = fapiGetScom( i_target, TP_CLK_STATUS_0x01030008, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error reading TP chiplet Clock Status Register.");
-            break;
-        }
-        if ( scom_data.isBitSet(TP_CLK_STAT_NET_SL)  ||
-             scom_data.isBitSet(TP_CLK_STAT_NET_NSL) ||
-             scom_data.isBitSet(TP_CLK_STAT_NET_ARY) ||
-             scom_data.isBitSet(TP_CLK_STAT_PIB_SL)  ||
-             scom_data.isBitSet(TP_CLK_STAT_PIB_NSL) ||
-             scom_data.isBitSet(TP_CLK_STAT_PIB_ARY) )
-        {
-            // At least one of the NET or PIB clocks is NOT running.
-            FAPI_INF("At least one of the NET or PIB clocks is NOT running.  May not be able to use the PCB fabric to access chiplets.");
-            FAPI_INF("Procedure will not attempt to turn off clocks in the individual chiplets..");
-            i2_stop_mem_clks  = false;
-            i2_stop_nest_clks = false;
-        }
-
-        FAPI_INF("   Input parameters: ");
-        FAPI_INF("       stop_mem_clks        = %s", i2_stop_mem_clks       ? "true":"false");
-        FAPI_INF("       stop_nest_clks       = %s", i2_stop_nest_clks      ? "true":"false");
-        FAPI_INF("       stop_dram_rfrsh_clks = %s", i_stop_dram_rfrsh_clks ? "true":"false");
-        FAPI_INF("       stop_tp_clks         = %s", i_stop_tp_clks         ? "true":"false");
-        FAPI_INF("       stop_vitl_clks       = %s", i_stop_vitl_clks       ? "true":"false");
-
-        if ((!i2_stop_mem_clks)  &&
-            (!i2_stop_nest_clks) &&
-            (!i_stop_tp_clks)    &&
-            (!i_stop_vitl_clks))
-        {
-            FAPI_INF("Specified input options are set to skip both the NEST and MEM chiplets, so there is nothing to do.  Returning.");
-            break;
-        }
-
-        //-----------------
-        //   MEM Chiplet @@@ 03
-        //-----------------
-        if ( i2_stop_mem_clks )
-        {
-            // FW team requested that we check to see if the vital clock region is running before stopping the clocks.
-            // If the vital clocks are not running, then other clocks are not running either, so we are done.
-            // If the vital clocks are running, then we should be able to access the necessary registers to stop the other clocks.
-            FAPI_DBG("Reading GP3 Register, bit 16, to see if VITAL clocks are running.");
-            rc = fapiGetScom( i_target, MEM_GP3_0x030F0012, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading GP3 register in attempt to verify that VITAL clocks are running.");
-                break;
-            }
-            if (scom_data.isBitSet(GP3_VITAL_THOLD_BIT))
-            {
-                // The VITAL thold is asserted, so no clocks are running in this chiplet.   Nothing left to do, so just return.
-                FAPI_INF("The VITAL clocks are not running for this chiplet, so all other clocks should be already stopped.");
-            }
-            else
-            {
-
-                // Start with instructions common to eclipz chips
-        
-                // Set flushmode_inhibit in Chiplet GP0
-                // multicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(2) = 0b1  (0x2000 0000 0000 0000)
-                // MEM_GP0_OR_0x03000005
-                FAPI_DBG("Setting flushmode_inhibit in MEM chiplet GP0 Register (bit 2).");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_FLUSHMODE_INHIBIT_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set flushmode_inhibit in MEM chiplet GP0 Register.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP0 registers in MEM chiplet to set flushmode inhibit (bit 2).");
-                    break;
-                }
-        
-        
-                // Set force_align in Chiplet GP0
-                // multicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(3) = 0b1  (0x1000 0000 0000 0000)   Cannot combine with previous step.
-                // MEM_GP0_OR_0x03000005
-                FAPI_DBG("Setting force_align in MEM chiplet GP0 register (bit 3).");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_FORCE_ALIGN_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to Set force_align in MEM chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP0 registers in MEM chiplet to set force_align (bit 3).");
-                    break;
-                }
-        
-        
-                // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop
-                // multicast address 0x[xx]03 0007    Data:  0x0000 0000 0000 0000
-                // MEM_CLK_SCANSEL_0x03030007
-                FAPI_DBG("Writing Clock Control Scan Region Register to all zeros in MEM chiplet prior clock stop.");
-                rc_ecmd |= scom_data.flushTo0();
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to write CC Scan Region Register to all zeros..",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing CC Scan Region Registers in MEM chiplet.");
-                    break;
-                }
-        
-        
-                // Now do Centaur-specific instructions
-        
-        
-        
-                // Write ClockControl, Clock Region Register, Clock Stop command for MEM chiplet
-                // 0x0303 0006 Data: 0x8FE00E0000000000
-                // MEM_CLK_REGION_0x03030006
-                FAPI_DBG("Writing Clock Control Clock Region Register in MEM chiplet to stop the clocks.");
-                rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_STOP_ALL);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set general clock stop command in MEM chiplet CC Clock Region Register.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing MEM chiplet CC Clock Region Register to stop the clocks.");
-                    break;
-                }
-        
-        
-                // Read Clock Status Register (MEM chiplet)
-                // 0x0303 0008  Data: expected value: 0xFFFF FFFF FFFF FFFF
-                // MEM_CLK_STATUS_0x03030008
-                FAPI_DBG("Reading Clock Status Register in the MEM chiplet to see if clocks are stopped. Expected value = 0xFFFF FFFF FFFF FFFF.");
-                rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error reading MEM chiplet Clock Status Register.");
-                    break;
-                }
-                uint64_t clock_status = scom_data.getDoubleWord(0);
-                if ( clock_status != EXPECTED_CLOCK_STATUS )
-                {
-                    FAPI_ERR("MEM chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX",
-                             EXPECTED_CLOCK_STATUS, clock_status);
-                    const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS;
-                    const uint64_t & ACTUAL_STATUS = clock_status;
-                    const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target;
-                    FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_MEM_CLOCK_STATUS);
-                    break;
-                }
-                else
-                {
-                    FAPI_INF("Expected clock status was read in MEM chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS);
-                }
-        
-        
-        
-                // Reset MemReset Stablilty Control
-                // CFAM 0x13  bit(02) = 0
-                // CFAM_FSI_GP4_0x00001013
-                FAPI_DBG("Clearing CFAM FSI GP4 Register, bit 2 to reset MemReset Stablilty Control.");
-                rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error reading CFAM FSI GP4 Register.");
-                    break;
-                }
-                rc_ecmd |= cfam_data.clearBit(FSI_GP4_MEMRESET_STABILITY_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set MemReset Stability Control (FSI GP4 bit 2).",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing FSI GP4 Register to reset the MemReset Stability Control (bit2).");
-                    break;
-                }
-        
-        
-                // Reset D3PHY PLL Control (Reset all D3PHY PLLs)
-                // CFAM 0x13  bit(04) = 0
-                // CFAM_FSI_GP4_0x00001013
-                FAPI_DBG("Clearing CFAM FSI GP4 Register, bit 4 to reset D3PHY PLL Control (Reset all D3PHY PLLs).");
-                rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error reading CFAM FSI GP4 register.");
-                    break;
-                }
-                rc_ecmd |= cfam_data.clearBit(FSI_GP4_DPHY_PLLRESET_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to reset the D3PHY PLLs .",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing FSI GP4 register to reset the D3PHY PLLs (by clearing bit 4).");
-                    break;
-                }
-        
-        
-                // Resume instructions that are common to eclipz chips.
-        
-        
-                // reset abist_mode_dc for core chiplets (core recovery)
-                // Does this make sense for Centaur?   (Centaur has no cores.)
-                // Multicast address: "0x[xx]00 0004  WAND codepoint" Data: bit(11) = 0b0   0xFFEF FFFF FFFF FFFF
-                // MEM_GP0_AND_0x03000004
-                FAPI_DBG("Clearing GP0 Register bit 11 in MEM chiplet to reset abist_mode_dc.");
-                rc_ecmd |= scom_data.flushTo1();
-                rc_ecmd |= scom_data.clearBit(GP0_ABIST_MODE_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear bit 11 of the GP0 registers in the MEM chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing the GP0 registers in the MEM chiplet to reset abist mode..");
-                    break;
-                }
-        
-        
-                // set synclk_muxsel (io_clk_sel)
-                // Multicast address: "0x[xx]00 0005  WOR codepoint"  bit(1) = 0b1   0x4000 0000 0000 0000
-                // MEM_GP0_OR_0x03000005
-                // assert perv fence GP0.63
-                // Multicast address: "0x[xx]00 0005  WOR codepoint"  bit(63) = 0b1  0x4000 0000 0000 0001  (Can be combined with previous step)
-                // MEM_GP0_OR_0x03000005
-                FAPI_DBG("Setting GP0 Register bit 1 in MEM chiplet to set synclk_muxsel (io_clk_sel).");
-                FAPI_DBG("Setting GP0 Register bit 63 in MEM chiplet to assert the pervasive fence.");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_SYNCCLK_MUXSEL_BIT);
-                rc_ecmd |= scom_data.setBit(GP0_PERV_FENCE_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set syncclk_muxsel and pervasive fence in GP0 registers..",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP0 registers in MEM chiplet to set syncclk_muxsel and pervasive fence..");
-                    break;
-                }
-        
-        
-                // GP3(28) disable EDRAM (just chiplets with EDRAM logic)
-                // Note: This action is probably un-needed for the MEM chiplet since it does not contain any EDRAM.
-                // Multicast address: "0x[xx]0F 0013  WAND codepoint"   bit(28) = 0b0   0xFFFF FFF7 FFFF FFFF
-                // MEM_GP3_AND_0x030F0013
-                FAPI_DBG("Clearing GP3 Register bit 28 in MEM chiplet to disable any EDRAM.");
-                rc_ecmd |= scom_data.flushTo1();
-                rc_ecmd |= scom_data.clearBit(GP3_EDRAM_ENABLE_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear GP3(bit 28), to disable EDRAM in MEM chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP3 Registers in MEM chiplet to disable any EDRAM.");
-                    break;
-                }
-        
-        
-                // assert fence GP3.18
-                // Multicast address: "0x[xx]0F 0014  WOR codepoint"  bit(18) = 0b1   0x0000 2000 0000 0000
-                // MEM_GP3_OR_0x030F0014
-                FAPI_DBG("Setting GP3 Regsiter bit 18 in MEM chiplet to assert the fence.");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP3_FENCE_EN_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set GP3(bit18) to assert the fence in the MEM chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP3 registers in MEM chiplet to assert the fence.");
-                    break;
-                }
-     
-                // Set scan_dis_dc_b bit in Chiplet GP0
-                // unicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(6) = 0b1  (0x0200 0000 0000 0000)
-                // MEM_GP0_OR_0x03000005
-                FAPI_DBG("Setting MEM chiplet GP0 Register bit 6 to set scan_dis_dc_b to allow for scanning.");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_SCAN_DIS_DC_B_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set scan_dis_dc_b in MEM chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing MEM chiplet GP0 register to set scan_dis_dc_b for scanning.");
-                    break;
-                }
-            }  // End of stop clock operations that are done if the vital clock is running.
-        }  // End of MEM chiplet code
-
-
-        //-----------------
-        //   NEST Chiplet @@@ 02
-        //-----------------
-        if ( i2_stop_nest_clks )
-        {
-            // FW team requested that we check to see if the vital clock region is running before stopping the clocks.
-            // If the vital clocks are not running, then other clocks are not running either, so we are done.
-            // If the vital clocks are running, then we should be able to access the necessary registers to stop the other clocks.
-            FAPI_DBG("Reading GP3 Register, bit 16, to see if VITAL clocks are running.");
-            rc = fapiGetScom( i_target, NEST_GP3_0x020F0012, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading GP3 register in attempt to verify that VITAL clocks are running.");
-                break;
-            }
-            if (scom_data.isBitSet(GP3_VITAL_THOLD_BIT))
-            {
-                // The VITAL thold is asserted, so no clocks are running in this chiplet.   Nothing left to do, so just return.
-                FAPI_INF("The VITAL clocks are not running for this chiplet, so all other clocks should be already stopped.");
-            }
-            else
-            {
-
-                // Start with instructions common to eclipz chips
-       
-                // Set flushmode_inhibit in Chiplet GP0
-                // multicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(2) = 0b1  (0x2000 0000 0000 0000)
-                // NEST_GP0_OR_0x02000005
-                FAPI_DBG("Setting flushmode_inhibit in NEST chiplet GP0 Register (bit 2).");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_FLUSHMODE_INHIBIT_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set flushmode_inhibit in NEST chiplet GP0 Register.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP0 registers in NEST chiplet to set flushmode inhibit (bit 2).");
-                    break;
-                }
-       
-       
-                // Set force_align in Chiplet GP0
-                // multicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(3) = 0b1  (0x1000 0000 0000 0000)   Cannot combine with previous step.
-                // NEST_GP0_OR_0x02000005
-                FAPI_DBG("Setting force_align in NEST chiplet GP0 register (bit 3).");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_FORCE_ALIGN_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to Set force_align in NEST chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP0 registers in NEST chiplet to set force_align (bit 3).");
-                    break;
-                }
-       
-       
-                // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop
-                // multicast address 0x[xx]03 0007    Data:  0x0000 0000 0000 0000
-                // NEST_CLK_SCANSEL_0x02030007
-                FAPI_DBG("Writing Clock Control Scan Region Register to all zeros in NEST chiplet prior clock stop.");
-                rc_ecmd |= scom_data.flushTo0();
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to write CC Scan Region Register to all zeros..",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_CLK_SCANSEL_0x02030007, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing CC Scan Region Registers in NEST chiplet.");
-                    break;
-                }
-       
-       
-                // Now do Centaur-specific instructions
-       
-       
-       
-                // Write ClockControl, Clock Region Register, Clock Stop command for NEST chiplet
-                // 0x0203 0006  Data: 0x8FE00E0000000000
-                // NEST_CLK_REGION_0x02030006
-                FAPI_DBG("Writing Clock Control Clock Region Register in NEST chiplet to stop the clocks.");
-                if ( i_stop_dram_rfrsh_clks )
-                {
-                    rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_STOP_ALL);
-                }
-                else
-                {
-                    rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_STOP_ALL_BUT_REFRESH );
-                }
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set general clock stop command in NEST chiplet CC Clock Region Register.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_CLK_REGION_0x02030006, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing NEST chiplet CC Clock Region Register to stop the clocks.");
-                    break;
-                }
-       
-       
-                // Read Clock Status Register (NEST chiplet)
-                // 0x0203 0008  Data: expected value: 0xFFFF FFFF FFFF FFFF
-                // NEST_CLK_STATUS_0x02030008
-                if ( i_stop_dram_rfrsh_clks )
-                {
-                    FAPI_DBG("Reading Clock Status Register in the NEST chiplet to see if clocks are stopped. Expected value = 0xFFFF FFFF FFFF FFFF.");
-                    rc = fapiGetScom( i_target, NEST_CLK_STATUS_0x02030008, scom_data);
-                    if (rc)
-                    {
-                        FAPI_ERR("Error reading NEST chiplet Clock Status Register.");
-                        break;
-                    }
-                    uint64_t clock_status = scom_data.getDoubleWord(0);
-                    if ( clock_status != EXPECTED_CLOCK_STATUS )
-                    {
-                        FAPI_ERR("NEST chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX",
-                                 EXPECTED_CLOCK_STATUS, clock_status);
-                        const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS;
-                        const uint64_t & ACTUAL_STATUS = clock_status;
-                        const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target;
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_NEST_CLOCK_STATUS);
-                        break;
-                    }
-                    else
-                    {
-                        FAPI_INF("Expected clock status was read in NEST chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS);
-                    }
-                }
-                else
-                {
-                    FAPI_DBG("Reading Clock Status Register in the NEST chiplet to see if clocks are stopped. Expected value = 0xFFFF FF1F FFFF FFFF.");
-                    rc = fapiGetScom( i_target, NEST_CLK_STATUS_0x02030008, scom_data);
-                    if (rc)
-                    {
-                        FAPI_ERR("Error reading NEST chiplet Clock Status Register.");
-                        break;
-                    }
-                    uint64_t clock_status = scom_data.getDoubleWord(0);
-                    if ( clock_status != EXPECTED_CLOCK_STATUS_W_REFRESH )
-                    {
-                        FAPI_ERR("NEST chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX",
-                                 EXPECTED_CLOCK_STATUS_W_REFRESH, clock_status);
-                        const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS_W_REFRESH;
-                        const uint64_t & ACTUAL_STATUS = clock_status;
-                        const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target;
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_NEST_CLOCK_STATUS);
-                        break;
-                    }
-                    else
-                    {
-                        FAPI_INF("Expected clock status was read in NEST chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS_W_REFRESH);
-                    }
-                }
-       
-       
-                // Resume instructions that are common to eclipz chips.
-       
-       
-                // reset abist_mode_dc for core chiplets (core recovery)
-                // Does this make sense for Centaur?   (Centaur has no cores.)
-                // Multicast address: "0x[xx]00 0004  WAND codepoint" Data: bit(11) = 0b0   0xFFEF FFFF FFFF FFFF
-                // NEST_GP0_AND_0x02000004
-                FAPI_DBG("Clearing GP0 Register bit 11 in NEST chiplet to reset abist_mode_dc.");
-                rc_ecmd |= scom_data.flushTo1();
-                rc_ecmd |= scom_data.clearBit(GP0_ABIST_MODE_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear bit 11 of the GP0 registers in the NEST chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_GP0_AND_0x02000004, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing the GP0 registers in the NEST chiplet to reset abist mode..");
-                    break;
-                }
-       
-       
-                // set synclk_muxsel (io_clk_sel)
-                // Multicast address: "0x[xx]00 0005  WOR codepoint"  bit(1) = 0b1   0x4000 0000 0000 0000
-                // NEST_GP0_OR_0x02000005
-                // assert perv fence GP0.63
-                // Multicast address: "0x[xx]00 0005  WOR codepoint"  bit(63) = 0b1  0x4000 0000 0000 0001  (Can be combined with previous step)
-                // NEST_GP0_OR_0x02000005
-                FAPI_DBG("Setting GP0 Register bit 1 in NEST chiplet to set synclk_muxsel (io_clk_sel).");
-                FAPI_DBG("Setting GP0 Register bit 63 in NEST chiplet to assert the pervasive fence.");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_SYNCCLK_MUXSEL_BIT);
-                rc_ecmd |= scom_data.setBit(GP0_PERV_FENCE_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set syncclk_muxsel and pervasive fence in GP0 registers..",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP0 registers in NEST chiplet to set syncclk_muxsel and pervasive fence..");
-                    break;
-                }
-       
-       
-                // GP3(28) disable EDRAM (just chiplets with EDRAM logic)
-                // Note:  (skip this step if refresh clock domain stays running)
-                // Multicast address: "0x[xx]0F 0013  WAND codepoint"   bit(28) = 0b0   0xFFFF FFF7 FFFF FFFF
-                // NEST_GP3_AND_0x020F0013
-                if ( i_stop_dram_rfrsh_clks )
-                {
-                    FAPI_DBG("Clearing GP3 Register bit 28 in NEST chiplet to disable any EDRAM.");
-                    rc_ecmd |= scom_data.flushTo1();
-                    rc_ecmd |= scom_data.clearBit(GP3_EDRAM_ENABLE_BIT);
-                    if (rc_ecmd)
-                    {
-                        FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear GP3(bit 28), to disable EDRAM in NEST chiplet.",  rc_ecmd);
-                        rc.setEcmdError(rc_ecmd);
-                        break;
-                    }
-                    rc = fapiPutScom( i_target, NEST_GP3_AND_0x020F0013, scom_data);
-                    if (rc)
-                    {
-                        FAPI_ERR("Error writing GP3 Registers in NEST chiplet to disable any EDRAM.");
-                        break;
-                    }
-                }
-       
-       
-                // assert fence GP3.18
-                // Multicast address: "0x[xx]0F 0014  WOR codepoint"  bit(18) = 0b1   0x0000 2000 0000 0000
-                // NEST_GP3_OR_0x020F0014
-                FAPI_DBG("Setting GP3 Regsiter bit 18 in NEST chiplet to assert the fence.");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP3_FENCE_EN_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set GP3(bit18) to assert the fence in the NEST chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_GP3_OR_0x020F0014, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing GP3 registers in NEST chiplet to assert the fence.");
-                    break;
-                }
-     
-                // Set scan_dis_dc_b bit in Chiplet GP0
-                // unicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(6) = 0b1  (0x0200 0000 0000 0000)
-                // NEST_GP0_OR_0x02000005
-                FAPI_DBG("Setting NEST chiplet GP0 Register bit 6 to set scan_dis_dc_b to allow for scanning.");
-                rc_ecmd |= scom_data.flushTo0();
-                rc_ecmd |= scom_data.setBit(GP0_SCAN_DIS_DC_B_BIT);
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("Error 0x%x setting up ecmd data buffer to set scan_dis_dc_b in NEST chiplet.",  rc_ecmd);
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-                rc = fapiPutScom( i_target, NEST_GP0_OR_0x02000005, scom_data);
-                if (rc)
-                {
-                    FAPI_ERR("Error writing NEST chiplet GP0 register to set scan_dis_dc_b for scanning.");
-                    break;
-                }
-            }  // End of stop clock operations that are done if the vital clock is running.
-        }  // End of NEST chiplet code
-
-
-
-        //-----------------
-        //   TP Chiplet @@@ 01
-        //-----------------
-
-        if (i_stop_tp_clks)
-        {
-
-            // Set the length of the FSI shifter set pulse
-            // Do this in the CFAM FSI SHIFT_CONTROL_REGISTER_2.
-            FAPI_DBG("Setting length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2.");
-            rc_ecmd |= cfam_data.setWord(0,FSI_SHIFT_SET_PULSE_LENGTH); //Set cfam_data to 0x0000000F
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error attempting to set length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2.");
-                break;
-            }
-
-
-            // Go into PIB2PCB bypass path
-            // Set this in CFAM GP3 register.  Read the register first to preserve other contents.
-            FAPI_DBG("Setting FSI GP3 bit 20 to go into PIB2PCB bypass.");
-            rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error getting FSI_GP3 via CFAM");
-                break;
-            }
-            rc_ecmd |= cfam_data.setBit(FSIGP3_PIB2PCB_BYPASS_BIT); //Set bit 20 to go into PIB2PCB bypass
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error attempting to go into PIB2PCB bypass.");
-                break;
-            }
-
-
-            // Set flushmode_inhibit in Chiplet GP0
-            // unicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(2) = 0b1  (0x2000 0000 0000 0000)
-            // TP_GP0_OR_0x01000005
-            FAPI_DBG("Setting TP chiplet GP0 Register bit 2 to set flushmode_inhibit.");
-            rc_ecmd |= scom_data.flushTo0();
-            rc_ecmd |= scom_data.setBit(GP0_FLUSHMODE_INHIBIT_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set flushmode_inhibit in TP chiplet.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing TP chiplet GP0 register to set flushmode inhibit.");
-                break;
-            }
-
-            // Set force_align in Chiplet GP0
-            // unicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(3) = 0b1  (0x1000 0000 0000 0000)   Cannot combine with previous step.
-            // TP_GP0_OR_0x01000005
-            FAPI_DBG("Setting TP chiplet GP0 Register bit 3 to set force_align.");
-            rc_ecmd |= scom_data.flushTo0();
-            rc_ecmd |= scom_data.setBit(GP0_FORCE_ALIGN_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set force_align in TP chiplet.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing TP chiplet GP0 register to set force_align.");
-                break;
-            }
-
-            // Write ClockControl, Scan Region Register, set all bits to zero prior clock stop
-            // unicast address 0x[xx]03 0007    Data:  0x0000 0000 0000 0000
-            // TP_CLK_SCANSEL_0x01030007
-            FAPI_DBG("Writing TP chiplet Clock Control Scan Region Register to all zeros prior clock stop.");
-            rc_ecmd |= scom_data.flushTo0();
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to write CC Scan Region Register to all zeros in TP chiplet.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, TP_CLK_SCANSEL_0x01030007, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing TP chiplet CC Scan Region Register.");
-                break;
-            }
-
-            // Write ClockControl, Clock Region Register, Clock Stop command (arrays + nsl only, not refresh clock region) TP chiplet
-            // TP_CLK_REGION_0x01030006
-            FAPI_DBG("Writing Clock Control Clock Region Register in TP chiplet to stop the clocks.");
-            rc_ecmd |= scom_data.flushTo1();
-            rc_ecmd |= scom_data.insertFromRight(CLK_REGION_CLOCK_CMD_STOP,
-                                                 CLK_REGION_CLOCK_CMD_BIT,
-                                                 CLK_REGION_CLOCK_CMD_LEN);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set general clock stop command in TP chiplet CC Clock Region Register.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, TP_CLK_REGION_0x01030006, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing TP chiplet CC Clock Region Register to stop the clocks.");
-                break;
-            }
-
-            // Read Clock Status Register (TP chiplet)
-            // 0x0103 0008  Data: expected value: FFFFFFFFFFFFFFFF
-            // TP_CLK_STATUS_0x01030008
-            FAPI_DBG("Reading Clock Status Register in the TP chiplet to see if clocks are stopped. Expected value = 0x%016llX.", EXPECTED_CLOCK_STATUS);
-            rc = fapiGetScom( i_target, TP_CLK_STATUS_0x01030008, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading TP chiplet Clock Status Register.");
-                break;
-            }
-            uint64_t clock_status = scom_data.getDoubleWord(0);
-            if ( clock_status != EXPECTED_CLOCK_STATUS )
-            {
-                FAPI_ERR("TP chiplet clock status 0x%016llX was expected but read clock status = 0x%016llX.",
-                         EXPECTED_CLOCK_STATUS, clock_status);
-                const uint64_t & EXPECTED_STATUS = EXPECTED_CLOCK_STATUS;
-                const uint64_t & ACTUAL_STATUS = clock_status;
-                const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target;
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_UNEXPECTED_TP_CLOCK_STATUS);
-                break;
-            }
-            else
-            {
-                FAPI_INF("Expected clock status was read in TP chiplet after stopping the clocks: 0x%016llX ", EXPECTED_CLOCK_STATUS);
-            }
-
-
-            // Set L3 EDRAM fence in chiplet by setting bit(19) in chiplet GP0 registers  (Fence only exists in EX chiplets.)
-
-
-            // Resume instructions that are common to all eclipz chips.
-
-
-            // reset abist_mode_dc for core chiplets only (core recovery)
-
-
-            // set synclk_muxsel (io_clk_sel)
-            // Unicast address: "0x[xx]00 0005  WOR codepoint"  bit(1) = 0b1   0x4000 0000 0000 0000
-            // TP_GP0_OR_0x01000005
-            // assert perv fence GP0.63
-            // Unicast address: "0x[xx]00 0005  WOR codepoint"  bit(63) = 0b1  0x4000 0000 0000 0001  (Can be combined with previous step)
-            // TP_GP0_OR_0x01000005
-            FAPI_DBG("Setting TP chiplet GP0 Register bit 1 to set synclk_muxsel (io_clk_sel).");
-            FAPI_DBG("Setting TP chiplet GP0 Register bit 63 to assert the pervasive fence.");
-            rc_ecmd |= scom_data.flushTo0();
-            rc_ecmd |= scom_data.setBit(GP0_SYNCCLK_MUXSEL_BIT);
-            rc_ecmd |= scom_data.setBit(GP0_PERV_FENCE_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set syncclk_muxsel and pervasive fence in TP chiplet.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing TP chiplet GP0 register to set syncclk_muxsel and pervasive fence..");
-                break;
-            }
-
-
-            // GP3(28) disable EDRAM (just chiplets with EDRAM logic)
-
-
-            // Instruction from Johannes Koesters   12 Sept, 2013
-            // Leave this commented out for now.   Seems to cause problems if we set the fence on the TP chiplet.
-            // 
-            // Change this to use PERV GP3 Register  (CFAM 101B)  (Normal GP3 reg N/A in TP chiplet) ?
-            //// assert fence GP3.18
-            //// Unicast address: "0x[xx]0F 0014  WOR codepoint"  bit(18) = 0b1   0x0000 2000 0000 0000
-            //// TP_GP3_OR_0x010F0014
-            //FAPI_DBG("Setting TP chiplet GP3 Regsiter bit 18 to assert the fence.");
-            //rc_ecmd |= scom_data.flushTo0();
-            //rc_ecmd |= scom_data.setBit(GP3_FENCE_EN_BIT);
-            //if (rc_ecmd)
-            //{
-            //    FAPI_ERR("Error 0x%x setting up ecmd data buffer to assert the fence in TP chiplet.",  rc_ecmd);
-            //    rc.setEcmdError(rc_ecmd);
-            //    break;
-            //}
-            //rc = fapiPutScom( i_target, TP_GP3_OR_0x010F0014, scom_data);
-            //if (rc)
-            //{
-            //    FAPI_ERR("Error writing TP chiplet GP3 register to assert the fence.");
-            //    break;
-            //}
-
-
-            // Set scan_dis_dc_b bit in Chiplet GP0
-            // unicast address "0x[xx]00 0005 WOR codepoint"   Data: bit(6) = 0b1  (0x0200 0000 0000 0000)
-            // TP_GP0_OR_0x01000005
-            FAPI_DBG("Setting TP chiplet GP0 Register bit 6 to set scan_dis_dc_b to allow for scanning.");
-            rc_ecmd |= scom_data.flushTo0();
-            rc_ecmd |= scom_data.setBit(GP0_SCAN_DIS_DC_B_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set scan_dis_dc_b in TP chiplet.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, TP_GP0_OR_0x01000005, scom_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing TP chiplet GP0 register to set scan_dis_dc_b for scanning.");
-             break;
-            }
-        }  // End of TP Chiplet clock section
-
-
-
-        //-----------------
-        //   VITL Clocks @@@ 00
-        //-----------------
-
-        if (i_stop_vitl_clks)
-        {
-
-            // Set the length of the FSI shifter set pulse
-            // Do this in the CFAM FSI SHIFT_CONTROL_REGISTER_2.
-            FAPI_DBG("Setting length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2.");
-            rc_ecmd |= cfam_data.setWord(0,FSI_SHIFT_SET_PULSE_LENGTH); //Set cfam_data to 0x0000000F
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error attempting to set length of the set pulse in the FSI SHIFT_CONTROL_REGISTER_2.");
-                break;
-            }
-
-
-            // Disable the VITL clocks
-            // Set this in PERV GP3 register.  Read the register first to preserve other contents.
-            FAPI_DBG("Setting PERV GPP3 Register bit 16 to turn OFF the VITL clock.");
-            rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000101B, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error getting PERV GP3 via CFAM");
-                break;
-            }
-            rc_ecmd |= cfam_data.setBit(PERVGP3_VITL_CLKOFF_BIT); //Set bit 16 to turn OFF VITL clock
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000101B, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error attempting to set PERV GP3 Reg bit 16 to stop the VITL clocks.");
-                break;
-            }
-
-
-            // Set Some FSI fences
-            // Set this in CFAM GP3 register.  Read the register first to preserve other contents.
-            FAPI_DBG("Setting FSI GP3 bits 25 and,26 to set FSI fences 4 and 5.");
-            rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error getting FSI_GP3 via CFAM");
-                break;
-            }
-            rc_ecmd |= cfam_data.setBit(FSIGP3_FSI_FENCE4_BIT); //Set bits 25 to set FSI fence 4
-            rc_ecmd |= cfam_data.setBit(FSIGP3_FSI_FENCE5_BIT); //Set bits 26 to set FSI fence 5
-            if(rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase for CFAM operation", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_0x00001012, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error attempting to set FSI fences in FSI GP3 register.");
-                break;
-            }
-        }  // End of VITL clock section
-
-
-    } while(0);
-
-    FAPI_INF("********* cen_stopclocks complete *********");
-    return rc;
-}
-
-} //end extern C
-
-
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-
-$Log: cen_stopclocks.C,v $
-Revision 1.16  2014/01/16 17:49:16  mfred
-Updates for error msgs, error handling, and removing newline chars from msgs.  From Mike Jones.
-
-Revision 1.15  2013/10/16 14:39:32  mfred
-Set the FSI shifter pulse width before stopping the TP or VITL clocks.
-
-Revision 1.14  2013/10/10 14:23:32  mfred
-Updates from Gerrit review. Continue with other chiplet even if clocks are off in MEM chiplet.
-
-Revision 1.13  2013/09/27 16:44:50  mfred
-Separate option to stop the VITL clks, and checks to avoid calling options that will cause failures.
-
-Revision 1.12  2013/03/04 17:56:33  mfred
-Add some header comments for BACKUP and SCREEN.
-
-Revision 1.11  2013/02/27 21:16:30  mfred
-Make change to stop all clock regions simultaneously.
-
-Revision 1.10  2013/01/17 21:38:55  mfred
-Check vital clock before trying to stop clocks.  Assert scan_dis_dc_b after stopping clocks.
-
-Revision 1.9  2012/10/05 20:10:43  mfred
-Remove the use of multicast in case only one chiplet is selected.
-
-Revision 1.8  2012/08/30 12:09:29  mfred
-Only disable EDRAM if the refresh clock was turned OFF.
-
-Revision 1.7  2012/08/30 11:56:08  mfred
-Added input options to select chiplet and to stop refresh clock.
-
-Revision 1.6  2012/08/27 16:53:40  mfred
-Exit when unexpected clock status is seen.
-
-Revision 1.5  2012/07/10 14:29:36  mfred
-Removed some bad comments and some whitespace.
-
-Revision 1.4  2012/06/07 19:31:19  mfred
-Fixed calls to CFAM registers.  They are not scommable.
-
-Revision 1.3  2012/05/31 14:02:06  mfred
-Committing updates for cen_stopclocks.
-
-Revision 1.2  2012/03/14 19:26:34  mfred
-Replace prototype with functional code.
-
-Revision 1.1  2012/03/07 14:22:11  mfred
-Adding prototype for cen_stopclocks.
-
-*/
-
diff --git a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H b/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H
deleted file mode 100644
index 5d0bd5b7d..000000000
--- a/src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H
+++ /dev/null
@@ -1,91 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/cen_stopclocks/cen_stopclocks.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_stopclocks.H,v 1.5 2013/10/10 14:23:35 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_stopclocks.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_stopclocks.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// This is the header file for cen_stopclocks.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-#ifndef CEN_STOPCLOCKSHWPB_H_
-#define CEN_STOPCLOCKSHWPB_H_
-
-#include <fapi.H>
-
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*cen_stopclocks_FP_t)(const fapi::Target &,
-                                                const bool,
-                                                const bool,
-                                                const bool,
-                                                const bool,
-                                                const bool);
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-    // Target is centaur chip
-
-/**
- * @brief cen_stopclocks procedure:  The purpose of this procedure is to assert the tholds (stop the clocks) in the Centaur chip.
- *
- * @param[in] i_target                 Reference to centaur target
- * @param[in] i_stop_mem_clks          True if MEM chiplet clocks should be stopped, else false
- * @param[in] i_stop_nest_clks         True if NEST chiplet clocks (except for refresh clks) should be stopped, else false
- * @param[in] i_stop_dram_rfrsh_clks   If (i_stop_nest_clks==true) then true if NEST chiplet refresh clocks should be stopped, else false
- * @param[in] i_stop_tp_clks           True if PERV (TP) chiplet clocks should be stopped, else false
- * @param[in] i_stop_vitl_clks         True if PERV VITL clocks should be stopped, else false
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode cen_stopclocks(const fapi::Target& i_target,
-                                    const bool i_stop_mem_clks,
-                                    const bool i_stop_nest_clks,
-                                    const bool i_stop_dram_rfrsh_clks,
-                                    const bool i_stop_tp_clks,
-                                    const bool i_stop_vitl_clks);
-
-    // Target is centaur chip
-
-} // extern "C"
-
-#endif // CEN_STOPCLOCKSHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/dram_training.H b/src/usr/hwpf/hwp/dram_training/dram_training.H
deleted file mode 100644
index 11501cbfb..000000000
--- a/src/usr/hwpf/hwp/dram_training/dram_training.H
+++ /dev/null
@@ -1,286 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/dram_training.H $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef  __DRAM_TRAINING_DRAM_TRAINING_H
-#define  __DRAM_TRAINING_DRAM_TRAINING_H
-
-/**
- *  @file dram_training.H
- *
- *  Step 13 DRAM Training
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  *****************************************************************
- *  THIS FILE WAS GENERATED ON 2012-02-27:2142
- *  *****************************************************************
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/*  @tag isteplist
- *  @docversion     v1.28 (12/03/12)
- *  @istepname      dram_training
- *  @istepnum       13
- *  @istepdesc      Step 13 DRAM Training
- *
- *  @{
- *      @substepnum     1
- *      @substepname    host_disable_vddr
- *      @substepdesc    : Disable VDDR on CanContinue loops
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    mem_pll_initf
- *      @substepdesc    : PLL initfile for MBAs
- *      @target_sched   serial
- *  @}
-
- *  @{
- *      @substepnum     3
- *      @substepname    mem_pll_setup
- *      @substepdesc    : Setup PLL for MBAs
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     4
- *      @substepname    mem_startclocks
- *      @substepdesc    : Start clocks on MBAs
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     5
- *      @substepname    host_enable_vddr
- *      @substepdesc    : Enable the VDDR3 Voltage Rail
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     6
- *      @substepname    mss_scominit
- *      @substepdesc    : Perform scom inits to MC and PHY
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     7
- *      @substepname    mss_ddr_phy_reset
- *      @substepdesc    : Soft reset of DDR PHY macros
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     8
- *      @substepname    mss_draminit
- *      @substepdesc    : Dram initialize
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     9
- *      @substepname    mss_draminit_training
- *      @substepdesc    : Dram training
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     10
- *      @substepname     mss_draminit_trainadv
- *      @substepdesc     : Advanced dram training
- *      @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     11
- *      @substepname     mss_draminit_mc
- *      @substepdesc     : Hand off control to MC
- *      @target_sched   serial
- * @}
- */
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-namespace   DRAM_TRAINING
-{
-
-/**
- *  @brief   host_disable_vddr
- *
- *           Disable VDDR on CanContinue loops
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return any errlogs to istep 
- *
- */
-void*    call_host_disable_vddr( void * io_pArgs );
-
-/**
- *  @brief   mem_pll_initf
- *
- *           PLL init file for MBAs
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mem_pll_initf( void * io_pArgs );
-
-/**
- *  @brief   mem_pll_setup
- *
- *           Setup PLL for MBAs
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mem_pll_setup( void * io_pArgs );
-
-
-
-/**
- *  @brief   mem_startclocks
- *
- *           Start clocks on MBAs
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mem_startclocks( void * io_pArgs );
-
-
-
-/**
- *  @brief   host_enable_vddr
- *
- *           Enable the VDDR3 Voltage Rail
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
-
- *
- */
-void*    call_host_enable_vddr( void * io_pArgs );
-
-
-
-/**
- *  @brief   mss_scominit
- *
- *           Perform scom inits to MC and PHY
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mss_scominit( void * io_pArgs );
-
-
-
-/**
- *  @brief   mss_ddr_phy_reset
- *
- *           Soft reset of DDR PHY macros
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mss_ddr_phy_reset( void * io_pArgs );
-
-
-
-/**
- *  @brief   mss_draminit
- *
- *           Dram initialize
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mss_draminit( void * io_pArgs );
-
-
-/**
- *  @brief   mss_draminit_training
- *
- *           Dram training
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mss_draminit_training( void * io_pArgs );
-
-
-
-/**
- *  @brief   mss_draminit_trainadv
- *
- *           Advanced dram training
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mss_draminit_trainadv( void * io_pArgs );
-
-
-
-/**
- *  @brief   mss_draminit_mc
- *
- *           Hand off control to MC
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep 
- *
- */
-void*    call_mss_draminit_mc( void * io_pArgs );
-/**
- *  @brief   mss_dimm_power_test
- *
- *
- *  param[in,out] io_pArgs  -   (normally) a pointer to a TaskArgs struct,
- *                              or NULL.
- *  return  any errlogs to istep
- *
- */
-void*    call_mss_dimm_power_test( void * io_pArgs );
-
-
-};   // end namespace
-
-#endif
-
diff --git a/src/usr/hwpf/hwp/dram_training/makefile b/src/usr/hwpf/hwp/dram_training/makefile
deleted file mode 100644
index 11496a39b..000000000
--- a/src/usr/hwpf/hwp/dram_training/makefile
+++ /dev/null
@@ -1,99 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/dram_training/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-MODULE = dram_training
-
-CFLAGS += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), -D FAPI_MSSLABONLY -D FAPI_LRDIMM)
-CFLAGS += -DFAPI_DDR4
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  NOTE: add the base istep dir here. 
-##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/@istepname
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/???
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_pll_setup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/cen_stopclocks
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_initialization/proc_throttle_sync
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += mss_draminit.o
-OBJS += mss_funcs.o
-OBJS += mss_draminit_mc.o
-OBJS += mss_draminit_training.o
-OBJS += mss_ddr_phy_reset.o
-OBJS += mss_termination_control.o
-OBJS += cen_mem_startclocks.o
-OBJS += mss_scominit.o
-OBJS += cen_mem_pll_initf.o
-OBJS += cen_mem_pll_setup.o
-OBJS += mss_draminit_training_advanced.o
-OBJS += mss_access_delay_reg.o
-OBJS += mss_generic_shmoo.o
-OBJS += mss_mcbist.o
-OBJS += mss_mcbist_common.o
-OBJS += mss_mcbist_address.o
-OBJS += mss_lrdimm_funcs.o
-OBJS += cen_stopclocks.o
-OBJS += mss_ddr4_pda.o
-OBJS += mss_ddr4_funcs.o
-OBJS += mss_mrs6_DDR4.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_training
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_mc
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_startclocks
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_scominit
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mem_pll_setup
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/cen_stopclocks
-
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
deleted file mode 100644
index 1e4c9fb6f..000000000
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C
+++ /dev/null
@@ -1,598 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_initf.C,v 1.13 2014/09/23 21:53:45 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_mem_pll_initf
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! SCREEN      : pervasive_screen
-// #! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure is scan the correct values into the Centaur chip MEM PLL controller.
-//
-// The MEM PLL needs to be set to various frequency settings based on the value of some memory attributes.
-// Here is some specific information in a 4/4/2012 note from Jeff Sabrowski:
-//
-// Hi Mark F,
-// The valid values for Voltage are:  1350, 1250 and 1200.
-// In the future, we may have a 900-ish value for low voltage DDR4, but the actual value won't be known for a year or more.
-// One thing I am thinking about that will complicate things is how to run corners.
-// This attribute will contain the nominal voltage.
-// To margin the voltage, a second attribute (that is set before IPL) exists that indicates the percent offset (plus or minus) to the nominal.
-// Power code will need to figure out the correct value from both those attributes.
-// I suppose there's the possibility that the offset value will also be in millivolts, but we haven't talked to the firmware group about this recently,
-// so this may be a good time to ping them on the offset piece again.
-//
-// For Frequency, we only have a few specific values we plan to support, although I plan to have a few extra "buckets" coded for lab bringup work.
-// The supported frequencies are 1066, 1333 and 1600.  I plan to code in 800, 1866 as well, and maybe 2133.
-// These are all the nominal/standard DDR3 and DDR4 JEDEC speeds.
-// Mark B will need to correct me if I am wrong, but I believe we are doing the same as voltage
-// -- having an attribute for nominal frequency and a second attribute for margin (+/- percent of nominal).
-//
-// The reason for "nominal" attribute plus a "margin" attribute is due to our firmware procedures being designed to work with nominal voltage and frequency
-// -- when at any margin, we don't want our code to recalculate "actuals" in order to properly stress parts.
-//
-// -Jeff
-//
-// Jeff Sabrowski  (jsabrow@us.ibm.com)
-//
-//
-// The supported frequencies listed above are the DDR frequencies. They also match the MEM PLL output B frequencies and the MBA frequencies.
-// MEM PLL output A should be running at half of the output B frequency.
-// MEM PLL output A drives the DDR phys.  The DDR phys double the MEM PLL output A frequency to get back to the MEM PLL output B frequency.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <cen_mem_pll_initf.H>
-
-#include <p8_delta_scan_rw.h>
-#include <p8_ring_identification.H>
-
-
-//  Constants
-
-// Register values for using setpulse
-const uint64_t OPCG_REG0_FOR_SETPULSE  = 0x818C000000000000ull;
-const uint64_t OPCG_REG2_FOR_SETPULSE  = 0x0000000000002000ull;
-const uint64_t OPCG_REG3_FOR_SETPULSE  = 0x6000000000000000ull;
-const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull;
-
-const uint32_t MEMB_TP_BNDY_PLL_RING_ADDR  = 0x01030088;
-
-// Pervasive LFIR Register field/bit definitions
-const uint8_t PERV_LFIR_SCAN_COLLISION_BIT = 3;
-
-const bool MASK_SCAN_COLLISION  = true;
-
-extern "C" {
-
-using namespace fapi;
-
-
-
-//------------------------------------------------------------------------------
-// cen_load_pll_ring_from_buffer
-//------------------------------------------------------------------------------
-fapi::ReturnCode cen_load_pll_ring_from_buffer(const fapi::Target & i_target,
-                                               ecmdDataBufferBase i_scan_ring_data
-                                               )
-{
-    // Target is centaur
-
-    fapi::ReturnCode    rc;
-    uint32_t            rc_ecmd = 0;
-    ecmdDataBufferBase  scom_data(64);
-
-
-    FAPI_INF("Starting subroutine: cen_load_pll_ring_from_buffer...");
-    do
-    {
-        //-------------------------------------------
-        //  Mask Pervasive LFIR
-        //------------------------------------------
-
-        if (MASK_SCAN_COLLISION)
-        {
-            FAPI_DBG("Masking Pervasive LFIR scan collision bit ...");
-            rc_ecmd |= scom_data.flushTo0();
-            rc_ecmd |= scom_data.setBit(PERV_LFIR_SCAN_COLLISION_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set Pervasive LFIR Mask Register.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_OR_0x0104000F, scom_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing Pervasive LFIR Mask OR Register.");
-                break;
-            }
-        }
-
-        //-------------------------------------------
-        //  Set the OPCG to generate the setpulse
-        //------------------------------------------
-        //   Write SCOM   address=0x01030002  data=0x818C000000000000  unicast, write TP OPCG Reg0 to generate setpulse
-        FAPI_DBG("Writing TP OPCG Register 0 to 0x818C000000000000 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP OPCG Register 0.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_OPCG_CNTL0_0x01030002, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing TP OPCG Register0 0x01030002 to 0x818C000000000000 to generate setpulse.");
-            break;
-        }
-
-        //   Write SCOM   address=0x01030004  data=0x0000000000002000  unicast, write TP OPCG Reg2 to generate setpulse
-        FAPI_DBG("Writing TP OPCG Register 2 to 0x0000000000002000 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP OPCG Register 2.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_OPCG_CNTL2_0x01030004, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing TP OPCG Register2 0x01030004 to 0x0000000000002000 to generate setpulse.");
-            break;
-        }
-
-        //   Write SCOM   address=0x01030005  data=0x6000000000000000  unicast, write TP OPCG Reg3 to generate setpulse
-        FAPI_DBG("Writing TP OPCG Register 3 to 0x6000000000000000 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP OPCG Register 3.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_OPCG_CNTL3_0x01030005, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing TP OPCG Register3 0x01030005 to 0x6000000000000000 to generate setpulse.");
-            break;
-        }
-
-        //   Write SCOM   address=0x01030006  data=0x0010040000000000  unicast, write TP Clock Region Reg to generate setpulse
-        FAPI_DBG("Writing TP OPCG Clock Region Register to 0x0010040000000000 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write TP Clock Region Register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_CLK_REGION_0x01030006, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing TP Clock Region Register 0x01030006 to 0x0010040000000000 to generate setpulse.");
-            break;
-        }
-
-        //------------------------------------------------
-        //  Scan new ring data into tp_pll_bndy scan ring.
-        //------------------------------------------------
-        rc = fapiPutRing(i_target, MEMB_TP_BNDY_PLL_RING_ADDR, i_scan_ring_data, RING_MODE_SET_PULSE);
-        if (rc)
-        {
-            FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t)rc);
-            break;
-        }
-        FAPI_DBG("Loading of the scan ring data for ring tp_pll_bndy is done.\n");
-
-        //-------------------------------------------
-        //  Set the OPCG back to a good state
-        //------------------------------------------
-        //   Write SCOM   address=0x01030005  data=0x0000000000000000  unicast, clear TP OPCG Reg3
-        FAPI_DBG("Writing TP OPCG Register 3 to 0x0000000000000000 to clear setpulse ...");
-        rc_ecmd |= scom_data.flushTo0();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP OPCG Register 3.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_OPCG_CNTL3_0x01030005, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing TP OPCG Register3 0x01030005 to 0x0000000000000000 to clear setpulse.");
-            break;
-        }
-
-        //   Write SCOM   address=0x01030006  data=0x0000000000000000  unicast, clear TP Clock Region Reg
-        FAPI_DBG("Writing TP OPCG Clock Region Register to 0x0000000000000000 to clear setpulse ...");
-        rc_ecmd |= scom_data.flushTo0();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP Clock Region Register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, TP_CLK_REGION_0x01030006, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing TP Clock Region Register 0x01030006 to 0x0000000000000000 to clear setpulse.");
-            break;
-        }
-
-        //-------------------------------------------
-        //  Clear & Unmask Pervasive LFIR
-        //------------------------------------------
-        if (MASK_SCAN_COLLISION)
-        {
-            FAPI_DBG("Clearing Pervasive LFIR scan collision bit ...");
-            rc_ecmd |= scom_data.flushTo1();
-            rc_ecmd |= scom_data.clearBit(PERV_LFIR_SCAN_COLLISION_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Pervasive LFIR Register.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, TP_PERV_LFIR_AND_0x0104000B, scom_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing Pervasive LFIR AND Register.");
-                break;
-            }
-
-            // Change for SW245030. Leave this FIR masked.   Feb. 4 2014   M.Fredrickson
-            //FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ...");
-            //rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_AND_0x0104000E, scom_data);
-            //if (!rc.ok())
-            //{
-            //    FAPI_ERR("Error writing Pervasive LFIR Mask And Register.");
-            //    break;
-            //}
-        }
-
-    } while(0);
-
-    FAPI_INF("Finished executing subroutine: cen_load_pll_ring_from_buffer");
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// cen_mem_pll_initf
-//------------------------------------------------------------------------------
-fapi::ReturnCode cen_mem_pll_initf(const fapi::Target & i_target)
-{
-    // Target is centaur
-    fapi::ReturnCode    rc;
-    uint32_t            rc_ecmd         = 0;
-    uint8_t             is_simulation   = 0;
-    uint32_t            mss_freq        = 0;
-    uint32_t            nest_freq       = 0;
-    uint32_t            ring_length     = 0;
-    uint32_t            mem_pll_update_bit_offset = 0;
-    uint8_t             attrRingData[80]={0};   // Set to 80 bytes to match length in XML file, not actual scan ring length.
-    ecmdDataBufferBase  ring_data;
-
-    FAPI_INF("********* cen_mem_pll_initf start *********");
-    do
-    {
-        FAPI_DBG("Setting up the Centaur MEM PLL.");
-
-        //------------------------------------------
-        //  Read attributes for setting the PLL data
-        //------------------------------------------
-
-        // The code that loads the PLL scan ring data should choose the correct data to load based on
-        // the DDR frequency and voltage settings and a lab override value.
-        // The supported frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz
-        // (These are the DDR frequencies and the PLL output B frequencies.)
-        // The DDR frequency can be determined from attribute ATTR_MSS_FREQ  (in MHz)
-        // The DDR voltage can be determined from attribute ATTR_MSS_VOLT  (in millivolts)
-        // Get another attribute for selecting the "override" ring.    Use CQ to request an attribute.
-        // (The selection of rings should include an "override ring that can be used in the lab")
-
-        // Read the attributes
-        rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION.");
-            break;
-        }
-        rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &i_target, mss_freq);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_MSS_FREQ.");
-            break;
-        }
-        // ATTR_FREQ_PB_MHZ is a "system" attribute, so use NULL as the target.
-        rc = FAPI_ATTR_GET( ATTR_FREQ_PB_MHZ, NULL, nest_freq);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_FREQ_PB_MHZ.");
-            break;
-        }
-
-        FAPI_DBG("ATTR_IS_SIMULATION attribute is set to : %d.", is_simulation);
-        FAPI_DBG("DDR frequency is set to : %d.", mss_freq);
-        FAPI_DBG("NEST frequency is set to : %d.", nest_freq);
-
-        // Read in the PLL Ring LENGTH based on the frequency attributes.
-        if ( is_simulation )
-        {
-            rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_LENGTH, &i_target, ring_length);
-        }
-        else if ( nest_freq == 2000 )
-        {
-            switch (mss_freq) {
-                case 1066 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_LENGTH, &i_target, ring_length);
-                    break;
-                case 1333 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_LENGTH, &i_target, ring_length);
-                    break;
-                case 1600 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_LENGTH, &i_target, ring_length);
-                    break;
-                case 1866 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_LENGTH, &i_target, ring_length);
-                    break;
-                default   :
-                    FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq);
-                    FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected.");
-                    uint32_t & MSS_FREQ = mss_freq;
-                    FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ);
-            }
-        }
-        else if ( nest_freq == 2400 )
-        {
-            switch (mss_freq) {
-                case 1066 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_LENGTH, &i_target, ring_length);
-                    break;
-                case 1333 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_LENGTH, &i_target, ring_length);
-                    break;
-                case 1600 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_LENGTH, &i_target, ring_length);
-                    break;
-                case 1866 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_LENGTH, &i_target, ring_length);
-                    break;
-                default   :
-                    FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq);
-                    FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected.");
-                    uint32_t & MSS_FREQ = mss_freq;
-                    FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ);
-            }
-        }
-        else
-        {
-            FAPI_ERR("Un-Supported NEST frequency detected: %d.", nest_freq);
-            FAPI_ERR("NEST frequency of 2000 or 2400 expected.");
-            uint32_t & NEST_FREQ = nest_freq;
-            FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_NEST_FREQ);
-            break;
-        }
-        if (rc)
-        {
-            FAPI_ERR("Failed to get the PLL ring LENGTH attribute.");
-            break;
-        }
-        FAPI_DBG("PLL ring LENGTH attribute is set to : %d.", ring_length);
-
-        // Read in the PLL Ring DATA based on the frequency attributes.
-        if ( is_simulation )
-        {
-            rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_DATA, &i_target, attrRingData);
-        }
-        else if ( nest_freq == 2000 )
-        {
-            switch (mss_freq) {
-                case 1066 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1066_DATA, &i_target, attrRingData);
-                    break;
-                case 1333 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1333_DATA, &i_target, attrRingData);
-                    break;
-                case 1600 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1600_DATA, &i_target, attrRingData);
-                    break;
-                case 1866 :
-                    rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_NEST4000_MEM1866_DATA, &i_target, attrRingData);
-                    break;
-                default   :
-                    FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq);
-                    FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected.");
-                    uint32_t & MSS_FREQ = mss_freq;
-                    FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ);
-            }
-        }
-        else if ( nest_freq == 2400 )
-        {
-            switch (mss_freq) {
-                case 1066 :
-                    rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1066_DATA, &i_target, attrRingData);
-                    break;
-                case 1333 :
-                    rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1333_DATA, &i_target, attrRingData);
-                    break;
-                case 1600 :
-                    rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1600_DATA, &i_target, attrRingData);
-                    break;
-                case 1866 :
-                    rc = FAPI_ATTR_GET( ATTR_MEMB_TP_BNDY_PLL_NEST4800_MEM1866_DATA, &i_target, attrRingData);
-                    break;
-                default   :
-                    FAPI_ERR("Un-Supported DDR frequency detected: %d.", mss_freq);
-                    FAPI_ERR("DDR frequency of 1066, 1333, 1600, or 1866 expected.");
-                    uint32_t & MSS_FREQ = mss_freq;
-                    FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_MSS_FREQ);
-            }
-        }
-        else
-        {
-            FAPI_ERR("Un-Supported NEST frequency detected: %d.", nest_freq);
-            FAPI_ERR("NEST frequency of 2000 or 2400 expected.");
-            uint32_t & NEST_FREQ = nest_freq;
-            FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_INITF_UNSUPPORTED_NEST_FREQ);
-            break;
-        }
-        if (rc)
-        {
-            FAPI_ERR("Failed to get the PLL ring DATA attribute.");
-            break;
-        }
-
-        // set DMI PFD360 bit for runtime
-        uint32_t memb_dmi_cupll_pfd360_bit_offset;
-        rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET, &i_target, memb_dmi_cupll_pfd360_bit_offset);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get DMI PFD360 offset attribute");
-            break;
-        }
-        FAPI_DBG("DMI PLL PFD360 offset is set to : %d.", memb_dmi_cupll_pfd360_bit_offset);
-
-        rc = FAPI_ATTR_GET(ATTR_MEMB_MEM_PLL_CFG_UPDATE_OFFSET, &i_target, mem_pll_update_bit_offset);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get the MEM PLL PLLCTR1(44) offset attribute");
-            break;
-        }
-        FAPI_DBG("MEM PLL PLLCTR1(44) offset is set to : %d.", mem_pll_update_bit_offset);
-
-
-        // Set the ring_data buffer to the right length for the ring data
-        rc_ecmd |= ring_data.setBitLength(ring_length);   // This length needs to match the real scan length in the scandef file (Required for hostboot.)
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // in order to update its output frequency, the MEM PLL needs to see PLLCTRL1(44) toggle
-        // ensure output frequency changes by running three scans w/ setpulse (PLLCTRL1(44) = 0->1->0)
-        for (uint32_t scan_num = 0; scan_num < 3; scan_num++)
-        {
-            // Put the ring data from the attribute into the buffer
-            rc_ecmd |= ring_data.insert(attrRingData, 0, ring_length, 0);
-
-            // clamp PFD360 bit to 0 for runtime
-            rc_ecmd |= ring_data.clearBit(memb_dmi_cupll_pfd360_bit_offset);
-
-            // force desired value of MEM PLLCTR1(44)
-            if (scan_num % 2) {
-                rc_ecmd |= ring_data.setBit(mem_pll_update_bit_offset);
-            }
-            else {
-                rc_ecmd |= ring_data.clearBit(mem_pll_update_bit_offset);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer (scan=%d).",  rc_ecmd, scan_num);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            // Call the subroutine to load the data into the simulation or HW model
-            rc = cen_load_pll_ring_from_buffer ( i_target, ring_data );
-            if (rc)
-            {
-                FAPI_ERR("Subroutine: cen_load_pll_ring_from_buffer failed (scan=%d)!", scan_num);
-                break;
-            }
-        }
-        if (rc)
-        {
-            break;
-        }
-    } while(0);
-
-    FAPI_INF("********* cen_mem_pll_initf complete *********");
-    return rc;
-}
-
-} //end extern C
-
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: cen_mem_pll_initf.C,v $
-Revision 1.13  2014/09/23 21:53:45  jmcgill
-add explicit clear for DMI PFD360 bit, based on change in base attribute values (SW279708)
-
-Revision 1.12  2014/02/04 21:08:46  mfred
-Change to leave TP FIR bit 3 masked out.  SW245030.
-
-Revision 1.11  2014/01/15 03:34:28  jmcgill
-scan ring 3x to ensure toggle on MEM PLLCTR1(44), which will guarantee output frequency change
-
-Revision 1.10  2013/12/10 03:41:34  mfred
-Make changes to support TP_BNDY scan chain addresses changing to chiplet 1 for zSeries.
-
-Revision 1.9  2013/11/15 16:29:56  mfred
-Changes made by Mike Jones for gerrit review, mostly for improved error handling.
-
-Revision 1.8  2013/10/02 16:09:38  mfred
-Mask FIR bit during scanning to resolve HW255774.  Add code to load desired MEM PLL freq after determining DDR freq.
-
-Revision 1.7  2013/07/08 14:00:24  mfred
-Back out accidental change.
-
-Revision 1.5  2013/03/04 17:56:24  mfred
-Add some header comments for BACKUP and SCREEN.
-
-Revision 1.4  2013/01/29 21:50:52  mfred
-Use new PLL ring attributes.
-
-Revision 1.3  2012/11/07 23:22:44  mfred
-Updated MEM PLL settings for HW with values from Tim Diemoz.
-
-Revision 1.2  2012/08/27 16:05:20  mfred
-committing minor updates as suggested by FW review.
-
-Revision 1.1  2012/08/13 17:16:08  mfred
-Adding new hwp cen_mem_pll_initf.
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H
deleted file mode 100644
index a2c444d2e..000000000
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H
+++ /dev/null
@@ -1,73 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_initf.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_initf.H,v 1.3 2013/11/15 16:29:59 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_initf.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_mem_pll_initf.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for cen_mem_pll_initf.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.0    | mfred    | 08/09/12| Initial creation
-//  1.3    | mjjones  | 11/12/13| Deleted internal func prototype
-
-#ifndef CEN_MEM_PLL_INITF_H_
-#define CEN_MEM_PLL_INITF_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*cen_mem_pll_initf_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-
-/**
- * @brief cen_mem_pll_initf procedure.
- *
- * The purpose of this procedure is to scan the right values in to the Centaur
- * MEM PLL controller..
- *
- * @param[in]  i_target  Reference to centaur target
- * @return ReturnCode
- */
-fapi::ReturnCode cen_mem_pll_initf(const fapi::Target& i_target);
-
-} // extern "C"
-
-#endif // CEN_MEM_PLL_INITF_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C
deleted file mode 100644
index a65fbecb5..000000000
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C
+++ /dev/null
@@ -1,233 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_setup.C,v 1.26 2014/03/19 13:58:05 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_setup.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_mem_pll_setup
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! SCREEN      : pervasive_screen
-// #! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure is to make sure the Centaur MEM PLL locks.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <cen_mem_pll_setup.H>
-
-//  Constants
-const uint64_t  DELAY_100NS             = 100;     // General purpose 100 ns delay for HW mode   (2000 sim cycles if simclk - 20ghz)
-const uint64_t  DELAY_2000SIMCYCLES     = 2000;    // General purpose 2000 sim cycle delay for sim mode     (100 ns if simclk = 20Ghz)
-const uint16_t  POLL_COUNT_MAX          = 50;      // Number of times to poll for PLL lock before timing out.
-
-// CFAM FSI STATUS register bit/field definitions
-const uint8_t FSI_STATUS_MEM_PLL_LOCK_BIT = 25;
-
-// TP LFIR  bit/field definitions
-const uint8_t TP_LFIR_ERRORS_FROM_NEST_PLL_LOCK_BIT = 19;
-const uint8_t TP_LFIR_ERRORS_FROM_MEM_PLL_LOCK_BIT  = 20;
-
-extern "C" {
-
-using namespace fapi;
-
-fapi::ReturnCode cen_mem_pll_setup(const fapi::Target & i_target)
-{
-    // Target is centaur
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase cfam_data(32);
-    uint32_t            rc_ecmd = 0;
-    ecmdDataBufferBase  scom_data(64);
-
-    uint32_t  poll_count           = 0;
-    uint32_t  done_polling         = 0;
-
-    FAPI_INF("********* cen_mem_pll_setup start *********");
-    do
-    {
-        //---------------------------------------
-        // Poll for PLL lock bit
-        //---------------------------------------
-        // Check MEM PLL lock bit (25) in CFAM FSI status register to see if PLL is locked
-        // Check bit 25 only.  Bit 25 is for the MEM PLL. (Bit 24 is the PLL lock for NEST PLL)
-        FAPI_DBG("Polling on FSI STATUS register bit 25 to see if MEM PLL has locked....\n");
-        done_polling = 0;
-        poll_count = 0;
-        do
-        {
-            rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
-            if (rc)
-            {
-                FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles.");
-                break;
-            }
-
-            rc = fapiGetCfamRegister( i_target, CFAM_FSI_STATUS_0x00001007, cfam_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading FSI STATUS Regiter 0x00001007.");
-                break;
-            }
-            if ( cfam_data.isBitSet(FSI_STATUS_MEM_PLL_LOCK_BIT) ) done_polling = 1;
-            poll_count++;
-
-        } while ((done_polling == 0) && (poll_count < POLL_COUNT_MAX)); // Poll until PLL is locked or max count is reached.
-        if (rc) break;    // Go to end of proc if error found inside polling loop.
-
-        if ( (poll_count == POLL_COUNT_MAX) && ( done_polling != 1 ) )
-        {
-            FAPI_ERR("Centaur MEM PLL failed to lock!  Polling timed out after %d loops.",POLL_COUNT_MAX);
-            ecmdDataBufferBase & CFAM_FSI_STATUS = cfam_data;
-            const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target;
-            FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_PLL_SETUP_PLL_LOCK_TIMEOUT);
-            break;
-        }
-        else
-        {
-            FAPI_INF("Centaur MEM PLL is now locked.");
-        }
-
-
-        FAPI_DBG("Clearing the FIR PLL lock error bits and unmasking TP LFIR PLL lock error bits ...");
-        rc_ecmd |= scom_data.flushTo1();
-        rc_ecmd |= scom_data.clearBit(TP_LFIR_ERRORS_FROM_NEST_PLL_LOCK_BIT);
-        rc_ecmd |= scom_data.clearBit(TP_LFIR_ERRORS_FROM_MEM_PLL_LOCK_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear TP LFIR PLL Lock bits.", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, TP_PERV_LFIR_AND_0x0104000B, scom_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error writing Pervasive LFIR AND Register.");
-            break;
-        }
-        rc = fapiPutScom(i_target, TP_PERV_LFIR_MASK_AND_0x0104000E, scom_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error writing Pervasive LFIR Mask AND Register.");
-            break;
-        }
-
-
-    } while(0);
-
-    FAPI_INF("********* cen_mem_pll_setup complete *********");
-    return rc;
-}
-
-} //end extern C
-
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: cen_mem_pll_setup.C,v $
-Revision 1.26  2014/03/19 13:58:05  mfred
-Update to clear and unmask the PLL lock FIR bits after the PLL locks.  SW249390.
-
-Revision 1.25  2013/11/15 16:30:00  mfred
-Changes made by Mike Jones for gerrit review, mostly for improved error handling.
-
-Revision 1.24  2013/03/04 17:56:26  mfred
-Add some header comments for BACKUP and SCREEN.
-
-Revision 1.23  2012/08/13 17:16:16  mfred
-Adding new hwp cen_mem_pll_initf.
-
-Revision 1.22  2012/07/12 21:16:53  mfred
-Remove a lot of simulation-only code, use putspys to set the PLL control ring.
-
-Revision 1.21  2012/07/10 14:30:59  mfred
-Commented out some lines.
-
-Revision 1.20  2012/07/05 20:06:43  mfred
-But MEM PLL into bypass before scanning in new settings.
-
-Revision 1.19  2012/07/02 16:33:31  mfred
-Added MEM PLL settings for simulation.
-
-Revision 1.18  2012/06/27 20:34:39  mfred
-Updates to use real MEM PLL instead of var osc.
-
-Revision 1.17  2012/06/25 23:37:54  jeshua
-Attempt to fix up the mem pll variable oscillators
-
-Revision 1.16  2012/06/14 19:25:13  mfred
-Fixing spelling in comment.
-
-Revision 1.15  2012/06/14 19:07:51  mfred
-Added more code for setting real PLL control chain.  Values are still not final.
-
-Revision 1.14  2012/06/13 20:59:58  mfred
-Some updates for using real PLL.cen_mem_pll_setup.C
-
-Revision 1.13  2012/06/07 13:52:23  jmcgill
-use independent data buffers for cfam/scom accesses
-
-Revision 1.12  2012/06/06 20:05:03  jmcgill
-change FSI GP3/GP4/status register accesses from SCOM->CFAM
-
-Revision 1.11  2012/05/31 18:29:17  mfred
-Updates for RC checking and error messages, etc.
-
-Revision 1.10  2012/04/26 20:52:57  mfred
-add additional comment
-
-Revision 1.9  2012/04/26 14:35:29  mfred
-Some fixes.
-
-Revision 1.8  2012/04/06 15:58:20  mfred
-Plugged in real error msgs, removed some unneeded actions.
-
-Revision 1.5  2012/04/03 21:35:57  mfred
-Many updates for both sim and lab actions.
-
-Revision 1.4  2012/04/02 15:30:43  mfred
-removing prcdUtils.H from this dir.
-
-Revision 1.3  2012/03/30 19:11:06  mfred
-removing some obsolete files
-
-Revision 1.1  2012/03/23 20:36:03  mfred
-Checking in a shell prototype for cen_mem_pll_setup.
-
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H b/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H
deleted file mode 100644
index a0f4a7b90..000000000
--- a/src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H
+++ /dev/null
@@ -1,73 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mem_pll_setup/cen_mem_pll_setup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_pll_setup.H,v 1.2 2012/08/27 16:05:25 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_pll_setup.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_mem_pll_setup.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for cen_mem_pll_setup.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.0    | mfred    | 03/21/12| Initial creation
-
-#ifndef CEN_MEM_PLL_SETUPHWPB_H_
-#define CEN_MEM_PLL_SETUPHWPB_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*cen_mem_pll_setup_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-    // Target is centaur
-
-/**
- * @brief cen_mem_pll_setup procedure.  The purpose of this procedure is to make sure that the Centaur MEM PLL locks.
- *
- * @param[in]  i_target  Reference to centaur target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode cen_mem_pll_setup(const fapi::Target& i_target);
-    // Target is centaur
-
-} // extern "C"
-
-#endif // CEN_MEM_PLL_SETUPHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C
deleted file mode 100644
index a2394f6a4..000000000
--- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C
+++ /dev/null
@@ -1,465 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_startclocks.C,v 1.13 2014/04/07 19:01:06 gollub Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_mem_startclocks
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! SCREEN      : pervasive_screen
-// #! ADDITIONAL COMMENTS : See below
-//
-// The purpose of this procedure is to drop the fences and release the tholds associated with the Centaur chip MEM PLL.
-// to allow propagation of MEM Centaur clocks to internal logic, arrays, and PHYs.
-// See sepecific instructions below.
-//
-// Note: This procedure only starts the clocks in the MEM chiplet.
-//       Use the cen_sbe_tp_chiplet_init1.S procedure to start the clocks in the PERV chiplet.
-//       Use the cen_sbe_startclocks.S procedure to start the clocks in the NEST chiplet.
-//
-// The following details are from the Common POR spreadsheet sections 20.1 and 21.1 and from the Centaur Chip Spec.
-//
-// Common clock start actions:
-//   Write SCOM      address 0x6B0F0013  bit(18)=0b0                   multicast, drop fence in GP3
-//   Write SCOM      address 0x6B0F0014  bit(28)=0b1                   multicast, enable EDRAM, just chiplets with EDRAM logic
-//   ---not centaur---Write SCOM      address 0x6B0F0102  bit(40)=0b1                   enable EDRAM GP0
-//   Write SCOM      address 0x6B000004  bit(63)=0b0                   multicast, drop pervasive fence in GP0
-//   Write SCOM      address 0x6B000004  bit(0)=0b0, bit(1)=0b0        multicast, clear mux selects in GP0
-//   Write SCOM      address 0x6B000005  bit(11)=0b1                   abist_mode_dc for core chiplets (core recovery)
-//   Write SCOM      address 0x6B030007  0x0000000000000000            Write CC Scan Region Reg, set all bits='0' prior clk start
-//
-// Centaur-specific clock start actions:
-//   Write SCOM      address 0x03030006  data=0x4FE0 0600 0000 0000    unicast, write CC clock region reg in MEM chiplet. start clocks
-//   Write SCOM      address 0x03030006  data=0x4FE0 0E00 0000 0000    unicast, write CC clock region reg in MEM chiplet. start clocks
-//   Read SCOM       address 0x03030008  expect=0x0000 001F FFFF FFFF  unicast, read clock status reg in MEM chiplet
-//   Write SCOM      address 0x02030006  data=0x4FE0 0600 0000 0000    unicast, write CC clock region reg in NEST chiplet. start clocks
-//   Write SCOM      address 0x02030006  data=0x4FE0 0E00 0000 0000    unicast, write CC clock region reg in NEST chiplet. start clocks
-//   Read SCOM       address 0x02030008  expect=0x0000 001F FFFF FFFF  unicast, read clock status reg in NEST chiplet
-//   Write CFAM      address 0x13        bit(02)=0b1                   Set MemReset Stability Control
-//   Write CFAM      address 0x13        bit(04)=0b1                   Release D3PHY PLL Reset Control
-//
-// More common clock start actions:
-//   Write SCOM      address 0x6B000004  bit(3)=0b0                    multicast, clear force_align in all Chiplets in GP0
-//   Write SCOM      address 0x6B000004  bit(2)=0b0                    multicast, clear flushmode_inhibit in Chiplet in GP0
-//
-// Enable Drivers and Receivers
-//   Write CFAM      address 0x13        bit(22:23)=0b11,bit(28:30)=0b111   Enable drivers and receivers
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <cen_mem_startclocks.H>
-#include <mss_unmask_errors.H>
-
-//  Constants
-// CFAM FSI GP4 register bit/field definitions
-const uint8_t FSI_GP4_MEMRESET_STABILITY_BIT  = 2;
-const uint8_t FSI_GP4_DPHY_PLLRESET_BIT       = 4;
-
-// GP3 register bit/field definitions
-const uint8_t GP3_FENCE_EN_BIT     = 18;
-const uint8_t GP3_EDRAM_ENABLE_BIT = 28;
-
-// GP0 register bit/field definitions
-const uint8_t GP0_ABSTCLK_MUXSEL_BIT    = 0;
-const uint8_t GP0_SYNCCLK_MUXSEL_BIT    = 1;
-const uint8_t GP0_FLUSHMODE_INHIBIT_BIT = 2;
-const uint8_t GP0_FORCE_ALIGN_BIT       = 3;
-const uint8_t GP0_ABIST_MODE_BIT        = 11;
-const uint8_t GP0_PERV_FENCE_BIT        = 63;
-
-// Clock Region Register clock start data patterns
-const uint64_t CLK_REGION_REG_DATA_TO_START_NSL_ARY = 0x4FE0060000000000ull;
-const uint64_t CLK_REGION_REG_DATA_TO_START_ALL     = 0x4FE00E0000000000ull;
-
-// Clock Status Register expected pattern
-const uint64_t MEM_CLK_STATUS_REG_EXP_DATA = 0x0000001FFFFFFFFFull;
-
-// Chiplet FIR register expected pattern
-const uint64_t MEM_XSTOP_FIR_REG_EXP_DATA = 0x0000000000000000ull;
-
-
-extern "C" {
-
-
-using namespace fapi;
-
-// Procedures in this file
-fapi::ReturnCode cen_mem_startclocks_cloned(const fapi::Target & i_target);
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode cen_mem_startclocks(const fapi::Target & i_target)
-{
-    // Target is centaur
-    
-    fapi::ReturnCode l_rc;
-    
-    l_rc = cen_mem_startclocks_cloned(i_target);
-    
-	// If mss_unmask_pervasive_errors gets it's own bad rc,
-	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
-	// Else if mss_unmask_pervasive_errors runs clean, 
-	// it will just return the passed in rc.
-	l_rc = mss_unmask_pervasive_errors(i_target, l_rc);
-
-	return l_rc;
-}
-
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode cen_mem_startclocks_cloned(const fapi::Target & i_target)
-{
-    // Target is centaur
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase scom_data(64);
-    ecmdDataBufferBase cfam_data(32);
-
-
-
-    FAPI_INF("********* cen_mem_startclocks start *********");
-    do
-    {
-        //
-        // The following details are from the Common POR spreadsheet sections 20.1 and 21.1 and from the Centaur Chip Spec.
-        //
-        // Common clock start actions:
-        //
-
-
-        //   Write SCOM      address 0x030F0013  bit(18)=0b0    , drop fence in GP3
-        FAPI_DBG("Writing GP3 AND mask to clear chiplet fence (bit 18) ...");
-        rc_ecmd |= scom_data.flushTo1();
-        rc_ecmd |= scom_data.clearBit(GP3_FENCE_EN_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear chiplet fence.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_GP3_AND_0x030F0013, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP3 AND mask 0x030F0013 (bit 18) to clear chiplet fence.");
-            break;
-        }
-
-
-        //   Write SCOM      address 0x030F0014  bit(28)=0b1    , enable EDRAM, just chiplets with EDRAM logic
-        FAPI_DBG("Writing GP3 OR mask to enable EDRAM (bit 28) ...");
-        rc_ecmd |= scom_data.flushTo0();
-        rc_ecmd |= scom_data.setBit(GP3_EDRAM_ENABLE_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to enable EDRAM.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_GP3_OR_0x030F0014, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP3 OR mask 0x030F0014 (bit 28) to enable EDRAM.");
-            break;
-        }
-
-
-        //   ---not needed for centaur---Write SCOM      address 0x6B0F0102  bit(40)=0b1                   enable EDRAM GP0
-
-
-        //   Write SCOM      address 0x03000004  bit(63)=0b0               , drop pervasive fence in GP0
-        //   Write SCOM      address 0x03000004  bit(0)=0b0, bit(1)=0b0    , clear mux selects in GP0
-        FAPI_DBG("Writing GP0 AND mask to drop pervasive fence (bit 63) ...");
-        FAPI_DBG("Writing GP0 AND mask to clear mux selects (bits 0-1) ...");
-        rc_ecmd |= scom_data.flushTo1();
-        rc_ecmd |= scom_data.clearBit(GP0_ABSTCLK_MUXSEL_BIT);
-        rc_ecmd |= scom_data.clearBit(GP0_SYNCCLK_MUXSEL_BIT);
-        rc_ecmd |= scom_data.clearBit(GP0_PERV_FENCE_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to drop pervasive fence and clear mux selects.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bits 0,1,63) to drop pervasive fence and clear mux selects.");
-            break;
-        }
-
-
-        //   Write SCOM      address 0x03000005  bit(11)=0b1        abist_mode_dc for core chiplets (core recovery)
-        FAPI_DBG("Writing GP0 OR mask to set abist_mode_dc (bit 11) ...");
-        rc_ecmd |= scom_data.flushTo0();
-        rc_ecmd |= scom_data.setBit(GP0_ABIST_MODE_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to set abist_mode_dc.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_GP0_OR_0x03000005, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP0 OR mask 0x03000005 (bit 11) to set abist_mode_dc.");
-            break;
-        }
-
-
-        //   Write SCOM      address 0x03030007  0x0000000000000000     Write CC Scan Region Reg, set all bits='0' prior clk start
-        FAPI_DBG("Writing CC Scan Region Register to all zeros prior to clock start ...");
-        rc_ecmd |= scom_data.flushTo0();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to flush Scan Region Register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_CLK_SCANSEL_0x03030007, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing CC Scan Region Register 0x03030007 to all zeros prior to clock start.");
-            break;
-        }
-
-
-        //
-        // Centaur-specific clock start actions:
-
-
-        //   Write SCOM      address 0x03030006  data=0x4FE0 0600 0000 0000    unicast, write CC clock region reg in MEM chiplet. start clocks
-        FAPI_DBG("Writing CC Clock Region Register to 0x4FE0060000000000 to start array and nsl clocks ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_NSL_ARY);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to start array and nsl clocks.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE0060000000000 to start array and nsl clocks.");
-            break;
-        }
-
-
-        //   Write SCOM      address 0x03030006  data=0x4FE0 0E00 0000 0000    unicast, write CC clock region reg in MEM chiplet. start clocks
-        FAPI_DBG("Writing CC Clock Region Register to 0x4FE00E0000000000 to start sl clocks ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_REG_DATA_TO_START_ALL);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to start sl clocks.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_CLK_REGION_0x03030006, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing CC Clock Region Register 0x03030006 to 0x4FE00E0000000000 to start sl clocks.");
-            break;
-        }
-
-
-        //   Read SCOM       address 0x03030008  expect=0x0000 001F FFFF FFFF  unicast, read clock status reg in MEM chiplet
-        FAPI_DBG("Reading CC Clock Status Register to see if clocks are running ...");
-        rc = fapiGetScom( i_target, MEM_CLK_STATUS_0x03030008, scom_data);
-        if ( rc )
-        {
-            FAPI_ERR("Error reading CC Clock Status Register 0x03030008.");
-            break;
-        }
-        if ( scom_data.getDoubleWord(0) != MEM_CLK_STATUS_REG_EXP_DATA )
-        {
-            FAPI_ERR("Unexpected clock status! Clk Status Reg 0x03030008 = %16llX, but %16llX was expected.",scom_data.getDoubleWord(0),MEM_CLK_STATUS_REG_EXP_DATA);
-            uint64_t MEM_CLK_STATUS_REG = scom_data.getDoubleWord(0);
-            const fapi::Target & MEMBUF_CHIP_IN_ERROR = i_target;
-            FAPI_SET_HWP_ERROR(rc, RC_CEN_MEM_STARTCLOCKS_UNEXPECTED_CLOCK_STATUS);
-            break;
-        }
-
-
-        // The clocks for the NEST chiplet are started in the cen_sbe_startclocks.S procedure.    So don't do them here!
-        //   Write SCOM      address 0x02030006  data=0x4FE0 0600 0000 0000    unicast, write CC clock region reg in NEST chiplet. start clocks
-        //   Write SCOM      address 0x02030006  data=0x4FE0 0E00 0000 0000    unicast, write CC clock region reg in NEST chiplet. start clocks
-        //   Read SCOM       address 0x02030008  expect=0x0000 001F FFFF FFFF  unicast, read clock status reg in NEST chiplet
-
-
-        //   Write CFAM      address 0x13        bit(02)=0b1       Set MemReset Stability Control
-        FAPI_DBG("Writing FSI GP4 register (bit2) to set MemReset Stability control ...");
-        rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-        if (rc)
-        {
-            FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013.");
-            break;
-        }
-        rc_ecmd |= cfam_data.setBit(FSI_GP4_MEMRESET_STABILITY_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to set MemReset Stability control.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 2) to set MemReset Stability control.");
-            break;
-        }
-
-
-        //   Write CFAM      address 0x13        bit(04)=0b1     Release D3PHY PLL Reset Control
-        FAPI_DBG("Writing FSI GP4 register (bit4) to release D3PHY PLL Reset Control ...");
-        rc = fapiGetCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-        if (rc)
-        {
-            FAPI_ERR("Error reading FSI GP4 Regiter 0x00001013.");
-            break;
-        }
-        rc_ecmd |= cfam_data.setBit(FSI_GP4_DPHY_PLLRESET_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to release D3PHY PLL Reset Control.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutCfamRegister( i_target, CFAM_FSI_GP4_0x00001013, cfam_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing FSI GP4 0x00001013 (bit 4) to release D3PHY PLL Reset Control.");
-            break;
-        }
-
-
-        //
-        // More common clock start actions:
-
-
-        //   Write SCOM      address 0x03000004  bit(3)=0b0    clear force_align in all Chiplets in GP0
-        FAPI_DBG("Writing GP0 AND mask to clear force_align (bit 3) ...");
-        rc_ecmd |= scom_data.flushTo1();
-        rc_ecmd |= scom_data.clearBit(GP0_FORCE_ALIGN_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear force_align.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 3) to clear force_align.");
-            break;
-        }
-
-
-        //   Write SCOM      address 0x03000004  bit(2)=0b0    clear flushmode_inhibit in Chiplet in GP0
-        FAPI_DBG("Writing GP0 AND mask to clear flushmode_inhibit (bit 2) ...");
-        rc_ecmd |= scom_data.flushTo1();
-        rc_ecmd |= scom_data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear flushmode_inhibit.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_GP0_AND_0x03000004, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP0 AND mask 0x03000004 (bit 2) to clear flushmode_inhibit.");
-            break;
-        }
-
-
-        // The enablement of RI and DI is done in cen_sbe_startclocks.   It does not need to be done here.
-
-
-    } while(0);
-
-    FAPI_INF("********* cen_mem_startclocks complete *********");
-    return rc;
-}
-
-} //end extern C
-
-
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: cen_mem_startclocks.C,v $
-Revision 1.13  2014/04/07 19:01:06  gollub
-
-#|   1.55  | gollub   |07-APR-14| Added dependancy on mss_unmask_errors for cen_mem_startclocks.C
-
-Revision 1.12  2013/11/15 16:30:02  mfred
-Changes made by Mike Jones for gerrit review, mostly for improved error handling.
-
-Revision 1.11  2013/07/08 13:38:27  mfred
-Change one hwp_error usage from RC_MSS_UNEXPECTED_CLOCK_STATUS to RC_MSS_UNEXPECTED_MEM_CLK_STATUS.
-
-Revision 1.10  2013/03/04 17:56:29  mfred
-Add some header comments for BACKUP and SCREEN.
-
-Revision 1.9  2012/06/07 13:52:27  jmcgill
-use independent data buffers for cfam/scom accesses
-
-Revision 1.8  2012/06/06 20:04:59  jmcgill
-change FSI GP3/GP4/status register accesses from SCOM->CFAM
-
-Revision 1.7  2012/05/31 18:29:20  mfred
-Updates for RC checking and error messages, etc.
-
-Revision 1.6  2012/05/09 21:26:40  mfred
-Removed setting of RI, DI.  Added error checking to ecmdDataBuffer operations.  Removed unneeded statements.
-
-Revision 1.5  2012/05/02 15:32:30  mfred
-Take out some comments and unnecessary code
-
-Revision 1.4  2012/04/26 15:29:55  mfred
-fix some messages and comment out FIR error for now.
-
-Revision 1.3  2012/04/26 14:35:34  mfred
-Some fixes.
-
-Revision 1.2  2012/03/26 13:30:24  mfred
-Replace place_holder error msgs with real error msgs.
-
-Revision 1.1  2012/03/23 20:34:32  mfred
-Check in initial version of cen_mem_startclocks
-
-*/
-
diff --git a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H b/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H
deleted file mode 100644
index b0a532852..000000000
--- a/src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H
+++ /dev/null
@@ -1,73 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mem_startclocks/cen_mem_startclocks.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_mem_startclocks.H,v 1.1 2012/03/23 20:34:38 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/cen_mem_startclocks.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : cen_mem_startclocks.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for cen_mem_startclocks.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.0    | mfred    | 03/21/12| Initial creation
-
-#ifndef CEN_MEM_STARTCLOCKSHWPB_H_
-#define CEN_MEM_STARTCLOCKSHWPB_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*cen_mem_startclocks_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-    // Target is centaur
-
-/**
- * @brief cen_mem_startclocks procedure.  The purpose of this procedure is release the tholds associated with the Centaur MEM PLL..
- *
- * @param[in]  i_target  Reference to centaur target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode cen_mem_startclocks(const fapi::Target& i_target);
-    // Target is centaur
-
-} // extern "C"
-
-#endif // CEN_MEM_STARTCLOCKSHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
deleted file mode 100644
index 1716d7e7f..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
+++ /dev/null
@@ -1,1286 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-// $Id: mss_ddr_phy_reset.C,v 1.28 2014/01/31 15:09:03 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_ddr_phy_reset
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! SCREEN      : memory_screen
-// #! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure is to do a soft reset of the DDR PHY logic
-// and to get the Centaur chip ready for DRAM initializaion.
-// See sepecific instructions below.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <mss_ddr_phy_reset.H>
-#include <mss_termination_control.H>
-#include <mss_unmask_errors.H>
-#include <dimmBadDqBitmapFuncs.H>
-
-//  Constants
-const uint64_t  DELAY_100NS             = 100;      // general purpose 100 ns delay for HW mode   (2000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_1US               = 1000;     // general purpose 1 usec delay for HW mode   (20000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_100US             = 100000;   // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_2000SIMCYCLES     = 2000;     // general purpose 2000 sim cycle delay for sim mode     (100 ns if simclk = 20Ghz)
-const uint64_t  DELAY_20000SIMCYCLES    = 20000;    // general purpose 20000 sim cycle delay for sim mode    (1 usec if simclk = 20Ghz)
-const uint64_t  DELAY_2000000SIMCYCLES  = 2000000;  // general purpose 2000000 sim cycle delay for sim mode  (100 usec if simclk = 20Ghz)
-
-const uint16_t  DP18_PLL_EXP_LOCK_STATUS  = 0xF800; // DP18 PLL lock status that is expected at the conclusion of this procedure.
-const uint16_t  AD32S_PLL_EXP_LOCK_STATUS = 0xC000; // AD32S PLL lock status that is expected at the conclusion of this procedure.
-const uint16_t  MAX_POLL_LOOPS            = 10;     // Loop 10 times during PLL lock polling
-
-
-extern "C" {
-
-
-using namespace fapi;
-
-// prototypes of functions called in phy reset
-ReturnCode mss_deassert_force_mclk_low (const Target& i_target); 
-ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target);
-ReturnCode mss_ddr_phy_flush(const fapi::Target & i_target);
-
-fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
-{
-    // Target is centaur.mba
-
-    fapi::ReturnCode rc;
-
-    rc = mss_ddr_phy_reset_cloned(i_target);
-    if (rc) {
-        FAPI_ERR(" mss_ddr_phy_reset_cloned failed!  rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-    }
-    else	// reset successful
-    {
-        rc = mss_slew_cal(i_target);
-        if (rc) {
-            FAPI_ERR(" mss_slew_cal failed!  rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-        }
-        else	// slew cal successful
-        {
-            rc = mss_ddr_phy_flush(i_target);
-            if (rc) {
-                FAPI_ERR(" mss_ddr_phy_flush failed!  rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            }
-        }
-    }	// should exit early if any functions has a bad return code
-
-    // If mss_unmask_ddrphy_errors gets it's own bad rc,
-    // it will commit the passed in rc (if non-zero), and return it's own bad rc.
-    // Else if mss_unmask_ddrphy_errors runs clean,
-    // it will just return the passed in rc.
-    rc = mss_unmask_ddrphy_errors(i_target, rc);
-
-    return rc;
-}
-
-fapi::ReturnCode mss_ddr_phy_reset_cloned(const fapi::Target & i_target)
-{
-    // Target is centaur.mba
-
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    uint32_t poll_count = 0;
-    uint32_t done_polling = 0;
-    uint8_t is_simulation = 0;
-    ecmdDataBufferBase i_data(64);
-    ecmdDataBufferBase dp_p0_lock_data(64);
-    ecmdDataBufferBase dp_p1_lock_data(64);
-    ecmdDataBufferBase ad_p0_lock_data(64);
-    ecmdDataBufferBase ad_p1_lock_data(64);
-    uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; // 10 byte array of bad bits
-    uint8_t valid_dimms  = 0;
-    uint8_t valid_dimm[2][2];
-    uint8_t num_mranks_per_dimm[2][2];
-    uint8_t l_port       = 0;
-    uint8_t l_dimm       = 0;
-    uint8_t l_rank       = 0;
-    bool new_error        = false;
-    bool P0_DP0_reg_error = false;
-    bool P0_DP1_reg_error = false;
-    bool P0_DP2_reg_error = false;
-    bool P0_DP3_reg_error = false;
-    bool P0_DP4_reg_error = false;
-    bool P1_DP0_reg_error = false;
-    bool P1_DP1_reg_error = false;
-    bool P1_DP2_reg_error = false;
-    bool P1_DP3_reg_error = false;
-    bool P1_DP4_reg_error = false;
-    fapi::Target l_centaurTarget;
-    uint8_t      continue_on_dp18_pll_lock_failure = 0;
-
-
-    FAPI_INF("********* mss_ddr_phy_reset start *********");
-    do
-    { 
-
-        //
-        // Here are the specific instructions from section 14.7.3 of the Centaur Chip Specification:
-        //
-        // Run cen_ddr_phy_reset.C prepares the DDR PLLs. These PLLs were previously configured via scan init, but have
-        // been held in reset. At this point the PLL GP bit is deasserted to take the PLLs out of reset.
-        //
-        // The cen_ddr_phy_reset.C now resets the DDR PHY logic. This process will NOT destroy any configuration values
-        // previously loaded via the init file. The intent is for the initialized phase rotator configuration to remain valid after the
-        // soft reset completes. If this assumption fails to hold true, it will require replacing this step with a PHY hard reset,
-        // and then using inband configuration writes to restore all the DDR Configuration Registers.
-        //
-        // The following steps must be performed as part of the PHY reset procedure.
-  
-
-         // PLL Lock cannot happen if mclk low is asserted
-        // this procedure was moved from draminit to:
-        // Deassert Force_mclk_low signal
-        // see CQ 216395 (HW217109)
-        rc = mss_deassert_force_mclk_low(i_target);
-        if (rc)
-        {
-            FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            break;
-        }
-
-
-        //
-        // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value.
-        //    (Note: The chip should already be in this state.)
-        FAPI_DBG("Step 1: All control signals to the PHYs should already be set to their inactive state, idle state, or inactive values.\n");
-  
-  
-  
-        //
-        // 2. For DD0: Assert dfi_reset_all (GP4 bit 5 = "1") for at least 32 memory clock cycles. This signal DOES
-        //    erradicate all DDR configuration register initialization, thereby requiring the DDR registers to be reprogrammed
-        //    via SCOM after the PHY reset sequence completes.
-        //    For DD1: Set mcbist_ddr_dfi_reset_recover ="1" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 & 0x03010EA7)
-        //    for at least 32 memory clock cycles. This signal does NOT reset the configuration registers
-        //    within the PHY.
-        FAPI_DBG("Step 2: MBA CCS_MODEQ(25), Setting mcbist_ddr_dfi_reset_recover = 1 for DDR PHY soft reset.\n");
-        rc = fapiGetScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error reading CCS_MODEQ register.");
-            break;
-        }
-        rc_ecmd |= i_data.setBit(25);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to set bit 25 of CCS_MODEQ register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing CCS_MODEQ register .");
-            break;
-        }
-        rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
-        if (rc)
-        {
-            FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles.");
-            break;
-        }
-
-
-
-        //
-        // 3. For DD0: Deassert dfi_reset_all (GP4 bit 5 = "0")
-        //    For DD1: Deassert mcbist_ddr_dfi_reset_recover = "0" (CCS_MODEQ(25) SCOM Addr: 0x030106A7 0x03010EA7)
-        FAPI_DBG("Step 3: MBA CCS_MODEQ(25), Setting mcbist_ddr_dfi_reset_recover = 0 to release soft reset.\n");
-        rc = fapiGetScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error reading CCS_MODEQ register .");
-            break;
-        }
-        rc_ecmd |= i_data.clearBit(25);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear bit 25 of CCS_MODEQ register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing CCS_MODEQ register.");
-            break;
-        }
-  
-  
-  
-        //
-        // 4. Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset and enable the internal impedance controller.
-        //    (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 4: Write 0x0010 to PC IO PVT N/P FET driver control registers to assert ZCTL reset.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000010ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0010 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
-            break;
-        }
-
-
-
-        //
-        // 5. Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset while impedance controller is still enabled.
-        //    (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 5: Write 0x0018 to PC IO PVT N/P FET driver control registers to deassert ZCTL reset.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000018ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0018 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
-            break;
-        }
-
-
-
-        //
-        // 6. Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller.
-        //    (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 6: Write 0x0008 to PC IO PVT N/P FET driver control registers to deassert the impedance controller.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000008ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0008 into PC_IO_PVT_FET_CONTROL regs.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
-            break;
-        }
-
-
-
-        //
-        // 7. Write 0x4000 into the PC Resets Registers. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active
-        //                                                (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F)
-        FAPI_DBG("Step 7: Write 0x4000 into the PC Resets Regs. This deasserts the PLL_RESET and leaves the SYSCLK_RESET bit active.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000004000ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x4000 into PC_RESETS registers.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P1 register.");
-            break;
-        }
-
-
-
-        //
-        // 8. Wait at least 1 millisecond to allow the PLLs to lock. Otherwise, poll the PC DP18 PLL Lock Status
-        //    and the PC AD32S PLL Lock Status to determine if all PLLs have locked.
-        //    PC DP18 PLL Lock Status should be 0xF800:  (SCOM Addr: 0x8000C0000301143F, 0x8001C0000301143F, 0x8000C0000301183F, 0x8001C0000301183F)
-        //    PC AD32S PLL Lock Status should be 0xC000: (SCOM Addr: 0x8000C0010301143F, 0x8001C0010301143F, 0x8000C0010301183F, 0x8001C0010301183F)
-        //------------------------
-        // 8a - Poll for lock bits
-        FAPI_DBG("Step 8: Poll until DP18 and AD32S PLLs have locked....\n");
-        do
-        {
-            rc = fapiDelay(DELAY_1US, DELAY_20000SIMCYCLES); // wait 20000 simcycles (in sim mode) OR 1 usec (in hw mode)
-            if (rc)
-            {
-                FAPI_ERR("Error executing fapiDelay of 1us or 20000simcycles.");
-                break;
-            }
-            done_polling = 1;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0_0x8000C0000301143F, dp_p0_lock_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P0 register.");
-                break;
-            }
-            if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1_0x8001C0000301143F, dp_p1_lock_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading DPHY01_DDRPHY_PC_DP18_PLL_LOCK_STATUS_P1 register.");
-                break;
-            }
-            if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0_0x8000C0010301143F, ad_p0_lock_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P0 register.");
-                break;
-            }
-            if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            rc = fapiGetScom( i_target, DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1_0x8001C0010301143F, ad_p1_lock_data);
-            if (rc)
-            {
-                FAPI_ERR("Error reading DPHY01_DDRPHY_PC_AD32S_PLL_LOCK_STATUS_P1 register.");
-                break;
-            }
-            if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS ) done_polling = 0;
-            poll_count++;
-        } while ((done_polling == 0) && (poll_count < MAX_POLL_LOOPS)); // Poll until PLLs are locked.
-        if (rc) break;    // Go to end of proc if error found inside polling loop.
-  
-
-        if (poll_count == MAX_POLL_LOOPS)
-        {
-
-            //-------------------------------
-            // Check to see if we should continue even if the DP18 PLL lock fails
-            rc = fapiGetParentChip(i_target, l_centaurTarget);
-            if (rc)
-            {
-                FAPI_ERR("Error getting Centaur parent target from the input MBA");
-                break;
-            }
-            rc = FAPI_ATTR_GET( ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL, &l_centaurTarget, continue_on_dp18_pll_lock_failure);
-            if (rc)
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL.");
-                break;
-            }
-            FAPI_DBG("Got attribute ATTR_CENTAUR_EC_MSS_CONTINUE_ON_DP18_PLL_LOCK_FAIL:  value=%X.\n", continue_on_dp18_pll_lock_failure);
-
-            //-------------------------------
-            // 8b - Check Port 0 DP lock bits
-            if ( dp_p0_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS )
-            {
-                if ( dp_p0_lock_data.isBitClear(48) ) { FAPI_INF("Port 0 DP 0 PLL failed to lock!");}
-                if ( dp_p0_lock_data.isBitClear(49) ) { FAPI_INF("Port 0 DP 1 PLL failed to lock!");}
-                if ( dp_p0_lock_data.isBitClear(50) ) { FAPI_INF("Port 0 DP 2 PLL failed to lock!");}
-                if ( dp_p0_lock_data.isBitClear(51) ) { FAPI_INF("Port 0 DP 3 PLL failed to lock!");}
-                if ( dp_p0_lock_data.isBitClear(52) ) { FAPI_INF("Port 0 DP 4 PLL failed to lock!");}
-                if (!continue_on_dp18_pll_lock_failure)
-                {
-                    FAPI_ERR("One or more DP18 port 0 (0x0C000) PLL failed to lock!   Lock Status = %04X",dp_p0_lock_data.getHalfWord(3));
-                    FAPI_ERR("DP18 PLL lock failed and this chip does not have the known DP18 lock bug.");
-                    const uint16_t & EXPECTED_STATUS = DP18_PLL_EXP_LOCK_STATUS;
-                    const uint16_t ACTUAL_STATUS = dp_p0_lock_data.getHalfWord(3);
-                    const fapi::Target & MBA_IN_ERROR = i_target;
-                    const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget;
-                    FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_0_PLL_FAILED_TO_LOCK);
-                    break;
-                }
-                // for DD1 parts that have the DP18 lock bug - keep going to initialize any other channels that might be good.
-                FAPI_INF("One or more DP18 port 0 (0x0C000) PLL failed to lock!   Lock Status = %04X",dp_p0_lock_data.getHalfWord(3));
-                FAPI_INF("Continuing anyway to initialize any other channels that might be good...");
-            }
-            //-------------------------------
-            // 8c - Check Port 1 DP lock bits
-            if ( dp_p1_lock_data.getHalfWord(3) != DP18_PLL_EXP_LOCK_STATUS )
-            {
-                if ( dp_p1_lock_data.isBitClear(48) ) { FAPI_INF("Port 1 DP 0 PLL failed to lock!");}
-                if ( dp_p1_lock_data.isBitClear(49) ) { FAPI_INF("Port 1 DP 1 PLL failed to lock!");}
-                if ( dp_p1_lock_data.isBitClear(50) ) { FAPI_INF("Port 1 DP 2 PLL failed to lock!");}
-                if ( dp_p1_lock_data.isBitClear(51) ) { FAPI_INF("Port 1 DP 3 PLL failed to lock!");}
-                if ( dp_p1_lock_data.isBitClear(52) ) { FAPI_INF("Port 1 DP 4 PLL failed to lock!");}
-                if (!continue_on_dp18_pll_lock_failure)
-                {
-                    FAPI_ERR("One or more DP18 port 1 (0x1C000) PLL failed to lock!   Lock Status = %04X",dp_p1_lock_data.getHalfWord(3));
-                    FAPI_ERR("DP18 PLL lock failed and this chip does not have the known DP18 lock bug.");
-                    const uint16_t & EXPECTED_STATUS = DP18_PLL_EXP_LOCK_STATUS;
-                    const uint16_t ACTUAL_STATUS = dp_p1_lock_data.getHalfWord(3);
-                    const fapi::Target & MBA_IN_ERROR = i_target;
-                    const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget;
-                    FAPI_SET_HWP_ERROR(rc, RC_MSS_DP18_1_PLL_FAILED_TO_LOCK);
-                    break;
-                }
-                // for DD1 parts that have the DP18 lock bug - keep going to initialize any other channels that might be good.
-                FAPI_INF("One or more DP18 port 1 (0x1C000) PLL failed to lock!   Lock Status = %04X",dp_p1_lock_data.getHalfWord(3));
-                FAPI_INF("Continuing anyway to initialize any other channels that might be good...");
-            }
-            //-------------------------------
-            // 8d - Check Port 0 AD lock bits
-            if ( ad_p0_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS )
-            {
-                FAPI_ERR("One or more AD32S port 0 (0x0C001) PLL failed to lock!   Lock Status = %04X",ad_p0_lock_data.getHalfWord(3));
-                const uint16_t & EXPECTED_STATUS = AD32S_PLL_EXP_LOCK_STATUS;
-                const uint16_t ACTUAL_STATUS = ad_p0_lock_data.getHalfWord(3);
-                const fapi::Target & MBA_IN_ERROR = i_target;
-                const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget;
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_0_PLL_FAILED_TO_LOCK);
-                break;
-            }
-            //-------------------------------
-            // 8e - Check Port 1 AD lock bits
-            if ( ad_p1_lock_data.getHalfWord(3) != AD32S_PLL_EXP_LOCK_STATUS )
-            {
-                FAPI_ERR("One or more AD32S port 1 (0x1C001) PLL failed to lock!   Lock Status = %04X",ad_p1_lock_data.getHalfWord(3));
-                const uint16_t & EXPECTED_STATUS = AD32S_PLL_EXP_LOCK_STATUS;
-                const uint16_t ACTUAL_STATUS = ad_p1_lock_data.getHalfWord(3);
-                const fapi::Target & MBA_IN_ERROR = i_target;
-                const fapi::Target & MEMBUF_CHIP_IN_ERROR = l_centaurTarget;
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_AD32S_1_PLL_FAILED_TO_LOCK);
-                break;
-            }
-        }
-        else
-        {
-            FAPI_INF("AD32S PLLs are now locked.  DP18 PLLs should also be locked.");
-        }
-
-
-
-        //
-        // 9.Write '8024'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
-        //   This takes the dphy_nclk/SysClk alignment circuit out of reset and puts the dphy_nclk/SysClk alignment circuit into the Continuous Update Mode.
-        //           ADR SysClk PR Control Registers  :  (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F,
-        //                                                           0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F)
-        //          DP18 SysClk PR Control Registers  :  (SCOM Addr: 0x800000070301143F, 0x800004070301143F, 0x800008070301143F, 0x80000C070301143F, 0x800010070301143F,
-        //                                                           0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F,
-        //                                                           0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F,
-        //                                                           0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F)
-        FAPI_DBG("Step 9: Write '8024'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008024ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8024 into Phase Rotator Registers.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
-            break;
-        }
-
-
-
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-            P0_DP0_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-            P1_DP0_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-            P0_DP1_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-            P1_DP1_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-            P0_DP2_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-            P1_DP2_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-            P0_DP3_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-            P1_DP3_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-            P0_DP4_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-            P1_DP4_reg_error = true;
-        }
-
-
-
-        //
-        // 10.Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.
-        FAPI_DBG("Step 10: Wait at least 5932 memory clock cycles to allow the clock alignment circuit to perform initial alignment.\n");
-        rc = fapiDelay(DELAY_100US, DELAY_2000000SIMCYCLES); // wait 2000000 simcycles (in sim mode) OR 100 usec (in hw mode)
-        if (rc)
-        {
-            FAPI_ERR("Error executing fapiDelay of 100us or 2000000simcycles.");
-            break;
-        }
-
-
-
-        //
-        // 11.Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset
-        //                                                (SCOM Addr: 0x8000C00E0301143F, 0x8001C00E0301143F, 0x8000C00E0301183F, 0x8001C00E0301183F)
-        FAPI_DBG("Step 11: Write 0x0000 into the PC Resets Register. This deasserts the SysClk Reset.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000000ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0000 into the PC Resets registers.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P0_0x8000C00E0301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_RESETS_P1_0x8001C00E0301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_RESETS_P1 register.");
-            break;
-        }
-
-
-
-        //
-        // 12.Write '8020'x into the ADR SysClk Phase Rotator Control Registers and into the DP18 SysClk Phase Rotator Control Registers.
-        //    This takes the dphy_nclk/SysClk alignment circuit out of Continuous Update Mode.
-        //           ADR SysClk PR Control Registers  :  (SCOM Addr: 0x800080320301143F, 0x800084320301143F, 0x800180320301143F, 0x800184320301143F,
-        //                                                           0x800080320301183F, 0x800084320301183F, 0x800180320301183F, 0x800184320301183F)
-        //          DP18 SysClk PR Control Registers  :  (SCOM Addr: 0x800000070301143F, 0x800004070301143F, 0x800008070301143F, 0x80000C070301143F, 0x800010070301143F,
-        //                                                           0x800000070301183F, 0x800004070301183F, 0x800008070301183F, 0x80000C070301183F, 0x800010070301183F,
-        //                                                           0x800100070301143F, 0x800104070301143F, 0x800108070301143F, 0x80010C070301143F, 0x800110070301143F,
-        //                                                           0x800100070301183F, 0x800104070301183F, 0x800108070301183F, 0x80010C070301183F, 0x800110070301183F)
-        FAPI_DBG("Step 12: Write '8020'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008020ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
-            break;
-        }
-
-
-
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-            P0_DP0_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-            P1_DP0_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-            P0_DP1_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-            P1_DP1_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-            P0_DP2_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-            P1_DP2_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-            P0_DP3_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-            P1_DP3_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-            P0_DP4_reg_error = true;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-            P1_DP4_reg_error = true;
-        }
-
-
-
-        // Work-around required to get alignment in simulation
-        // Read the ATTR_IS_SIMULATION attribute
-        rc = FAPI_ATTR_GET( ATTR_IS_SIMULATION, NULL, is_simulation);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION.");
-            break;
-        }
-        if (is_simulation)
-        {
-            FAPI_DBG("Step 12.1 (SIM ONLY): Write '8000'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
-            rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008000ull);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register.");
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register.");
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register.");
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
-                break;
-            }
-
-
-
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-                P0_DP0_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-                P1_DP0_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-                P0_DP1_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-                P1_DP1_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-                P0_DP2_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-                P1_DP2_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-                P0_DP3_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-                P1_DP3_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-                P0_DP4_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-                P1_DP4_reg_error = true;
-            }
-
-
-            FAPI_DBG("Step 12.2 (SIM ONLY): Write '8080'x into the ADR SysClk Phase Rotator Control Regs and the DP18 SysClk Phase Rotator Control Regs.\n");
-            rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000008080ull);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x8020 into the Phase Rotator registers.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0_0x800080320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S0 register.");
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0_0x800180320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S0 register.");
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1_0x800084320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P0_ADR32S1 register.");
-                break;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1_0x800184320301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_ADR_SYSCLK_CNTL_PR_P1_ADR32S1 register.");
-                break;
-            }
-
-
-
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0_0x800000070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_0 register.");
-                P0_DP0_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0_0x800100070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_0 register.");
-                P1_DP0_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1_0x800004070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_1 register.");
-                P0_DP1_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1_0x800104070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_1 register.");
-                P1_DP1_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2_0x800008070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_2 register.");
-                P0_DP2_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2_0x800108070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_2 register.");
-                P1_DP2_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3_0x80000C070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_3 register.");
-                P0_DP3_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3_0x80010C070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_3 register.");
-                P1_DP3_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4_0x800010070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P0_4 register.");
-                P0_DP4_reg_error = true;
-            }
-            rc = fapiPutScom( i_target, DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4_0x800110070301143F, i_data);
-            if (rc)
-            {
-                FAPI_ERR("Error writing DPHY01_DDRPHY_DP18_SYSCLK_PR_P1_4 register.");
-                P1_DP4_reg_error = true;
-            }
-        }
-
-
-        //
-        // 13.Wait at least 32 memory clock cycles.
-        FAPI_DBG("Step 13: Wait at least 32 memory clock cycles.\n");
-        rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
-        if (rc)
-        {
-            FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles.");
-            break;
-        }
-
-
-
-        //
-        // 14.Write 0x0018 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.
-        //    This step takes approximately 2112 (64 * 33) memory clock cycles.
-        //                                                (SCOM Addr: 0x8000C0140301143F,  0x8000C0140301183F, 0x8001C0140301143F, 0x8001C0140301183F)
-        FAPI_DBG("Step 14: Write 0x0018 to PC IO PVT N/P FET driver control register to enable internal ZQ calibration.\n");
-        rc_ecmd |= i_data.setDoubleWord(0, 0x0000000000000018ull);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write 0x0018 into the PC_IO_PVT_FET_CONTROL registers.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0_0x8000C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P0 register.");
-            break;
-        }
-        rc = fapiPutScom( i_target, DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1_0x8001C0140301143F, i_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing DPHY01_DDRPHY_PC_IO_PVT_FET_CONTROL_P1 register.");
-            break;
-        }
-
-
-
-
-
-        //
-        // Now do some error checking and mark bad channels
-        // Check to see if there were any register access problems on DP registers, or corresponding PLLs that did not lock.
-        // If so, mark the DP pairs as bad.
-
-        // Loop through only valid (functional) dimms.
-        // For each valid dimm, loop through all the ranks belonging to that dimm.
-        // If there was either a register access error, or if the PLL did not lock, then mark the DP pair as bad.
-        // Do this by setting the dqBitmap attribute for all dimms and ranks associated with that PLL or register.
-        // Read the dqBitmap first, so that you do not clear values that may already be set.
-        // (Some DP channels may already be marked as bad.)
-
-	// Find out which dimms are functional
-        rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR,	&i_target, valid_dimms);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR");
-            break;
-        }
-        valid_dimm[0][0] = (valid_dimms & 0x80);
-        valid_dimm[0][1] = (valid_dimms & 0x40);
-        valid_dimm[1][0] = (valid_dimms & 0x08);
-        valid_dimm[1][1] = (valid_dimms & 0x04);
-
-        // Find out how many ranks are on each dimm
-        rc = FAPI_ATTR_GET( ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_mranks_per_dimm);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_EFF_NUM_RANKS_PER_DIMM.");
-            break;
-        }
-
-
-        // Loop through each PORT (0,1)
-        for(l_port=0; l_port<1; l_port++ )
-        {
-            // Loop through each DIMM:(0,1)
-            for(l_dimm=0; l_dimm<DIMM_DQ_MAX_MBAPORT_DIMMS; l_dimm++ )
-            {
-                if (valid_dimm[l_port][l_dimm])
-                {
-                    // Ok, this DIMM is functional. So loop through the RANKs of this dimm.
-                    for(l_rank=0; l_rank<num_mranks_per_dimm[l_port][l_dimm]; l_rank++ )
-                    {
-                        // Get the bad DQ Bitmap for l_port, l_dimm, l_rank
-                        rc = dimmGetBadDqBitmap(i_target,
-                                                l_port,
-                                                l_dimm,
-                                                l_rank,
-                                                l_dqBitmap);
-                        if (rc)
-                        {
-                            FAPI_ERR("Error from dimmGetBadDqBitmap");
-                            break;
-                        }
-            
-                        // Mark the bad bits for each register that had problems or PLL that did not lock
-                        new_error = false;
-                        if ( l_port == 0 )
-                        {
-                            if (( P0_DP0_reg_error ) || ( dp_p0_lock_data.isBitClear(48) )) { l_dqBitmap[0] = 0xff; l_dqBitmap[1] = 0xff; new_error = true; }
-                            if (( P0_DP1_reg_error ) || ( dp_p0_lock_data.isBitClear(49) )) { l_dqBitmap[2] = 0xff; l_dqBitmap[3] = 0xff; new_error = true; }
-                            if (( P0_DP2_reg_error ) || ( dp_p0_lock_data.isBitClear(50) )) { l_dqBitmap[4] = 0xff; l_dqBitmap[5] = 0xff; new_error = true; }
-                            if (( P0_DP3_reg_error ) || ( dp_p0_lock_data.isBitClear(51) )) { l_dqBitmap[6] = 0xff; l_dqBitmap[7] = 0xff; new_error = true; }
-                            if (( P0_DP4_reg_error ) || ( dp_p0_lock_data.isBitClear(52) )) { l_dqBitmap[8] = 0xff; l_dqBitmap[9] = 0xff; new_error = true; }
-                        } else {
-                            if (( P1_DP0_reg_error ) || ( dp_p1_lock_data.isBitClear(48) )) { l_dqBitmap[0] = 0xff; l_dqBitmap[1] = 0xff; new_error = true; }
-                            if (( P1_DP1_reg_error ) || ( dp_p1_lock_data.isBitClear(49) )) { l_dqBitmap[2] = 0xff; l_dqBitmap[3] = 0xff; new_error = true; }
-                            if (( P1_DP2_reg_error ) || ( dp_p1_lock_data.isBitClear(50) )) { l_dqBitmap[4] = 0xff; l_dqBitmap[5] = 0xff; new_error = true; }
-                            if (( P1_DP3_reg_error ) || ( dp_p1_lock_data.isBitClear(51) )) { l_dqBitmap[6] = 0xff; l_dqBitmap[7] = 0xff; new_error = true; }
-                            if (( P1_DP4_reg_error ) || ( dp_p1_lock_data.isBitClear(52) )) { l_dqBitmap[8] = 0xff; l_dqBitmap[9] = 0xff; new_error = true; }
-                        }
-            
-                        // If there are new errors, write back the bad DQ Bitmap for l_port, l_dimm, l_rank
-                        if ( new_error )
-                        {
-                            rc = dimmSetBadDqBitmap(i_target,
-                                                    l_port,
-                                                    l_dimm,
-                                                    l_rank,
-                                                    l_dqBitmap);
-                            if (rc)
-                            {
-                                FAPI_ERR("Error from dimmPutBadDqBitmap");
-                                break;
-                            }
-                        }
-                    }  // End of loop over RANKs
-                    if (rc) break;    // Go to end of proc if error found inside loop.
-                }
-            }  // End of loop over DIMMs
-            if (rc) break;    // Go to end of proc if error found inside loop.
-        }  // End of loop over PORTs
-
-
-    } while(0);
-
-    FAPI_INF("********* mss_ddr_phy_reset complete *********");
-
-    return rc;
-}
-
-
-// function moved from draminit because we need mclk low not asserted for pll locking
-ReturnCode mss_deassert_force_mclk_low (const Target& i_target)
-{ 
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer(64);
-
-    FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++");
-
-
-    rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
-    if(rc) return rc;
-    rc_num = data_buffer.setBit(63);
-    rc.setEcmdError( rc_num);
-    if(rc) return rc;
-    rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    return rc;
-}
-
-fapi::ReturnCode mss_ddr_phy_flush(const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase i_data(64);
-    ecmdDataBufferBase l_mask(64);
-	
-	FAPI_INF(" Performing mss_ddr_phy_flush routine");
-
-	FAPI_INF("ADR/DP18 FLUSH: 1) set PC_POWERDOWN_1 register, powerdown enable(48), flush bit(58)");
-	rc_ecmd = i_data.flushTo0();		// clear data buffer
-	rc_ecmd |= i_data.setBit(48);		// set MASTER_PD_CNTL bit
-	rc_ecmd |= i_data.setBit(58);		// set WR_FIFO_STAB bit
-
-	rc_ecmd |= l_mask.flushTo0();		// clear mask buffer
-	rc_ecmd |= l_mask.setBit(48);		// set MASTER_PD_CNTL bit
-	rc_ecmd |= l_mask.setBit(58);		// set WR_FIFO_STAB mask bit
-	if (rc_ecmd)
-	{
-		rc.setEcmdError(rc_ecmd);
-		return rc;
-	}
-
-	rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, i_data, l_mask);
-	if(rc) return rc;
-
-	rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, i_data, l_mask);
-	if(rc) return rc;
-
-	rc = fapiDelay(DELAY_100NS, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 nS (in hw mode)
-	if(rc) return rc;
-	
-	FAPI_INF("ADR/DP18 FLUSH: 2) clear PC_POWERDOWN_1 register, powerdown enable(48), flush bit(58)");
-	rc_ecmd = i_data.flushTo0();		// clear data buffer
-
-	rc_ecmd |= l_mask.flushTo0();		// clear mask buffer
-	rc_ecmd |= l_mask.setBit(48);		// set MASTER_PD_CNTL bit
-	rc_ecmd |= l_mask.setBit(58);		// set WR_FIFO_STAB mask bit
-	if (rc_ecmd)
-	{
-		rc.setEcmdError(rc_ecmd);
-		return rc;
-	}
-
-	rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P0_0x8000C0100301143F, i_data, l_mask);
-	if(rc) return rc;
-
-	rc = fapiPutScomUnderMask(i_target, DPHY01_DDRPHY_PC_POWERDOWN_1_P1_0x8001C0100301143F, i_data, l_mask);
-	if(rc) return rc;
-
-	return rc;
-}
-
-} //end extern C
-
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-
-$Log: mss_ddr_phy_reset.C,v $
-Revision 1.28  2014/01/31 15:09:03  mfred
-Mike Jones added statements to pass target into XML for callouts.
-
-Revision 1.27  2014/01/16 20:54:48  mfred
-Updates for passing more data to error handler.  From Mike Jones.
-
-Revision 1.26  2013/09/16 20:17:57  mwuu
-Cleanup of the calling functions so first fail will run unmask function.
-
-Revision 1.25  2013/06/26 17:40:56  mwuu
-Submitting Mark Fredrickson's clean up from FW review.
-
-Revision 1.24  2013/06/19 20:07:53  mwuu
-Implemented new ADR flush procedure via powerdown1 register.
-
-Revision 1.22  2013/06/14 17:44:49  mwuu
-Backed out the ADR flush workaround.
-
-Revision 1.21  2013/06/12 23:17:19  mwuu
-Removed DP18 flush section, fixed ADR toggle flush loop.
-
-Revision 1.20  2013/06/12 20:58:17  mwuu
-Fixed loop control structure for toggling the 0,1,0 in ADR block of flush FN.
-
-Revision 1.19  2013/06/11 19:05:27  mwuu
-Update to use master ranks for bad bitmap, and added flush function for ADR/DP18 workaround.
-
-Revision 1.18  2013/03/18 19:38:48  mfred
-Update to not continue if DP18 PLL fails to lock and EC is DD2.
-
-Revision 1.17  2012/12/03 15:49:27  mfred
-Fixed bug to allow exit from loops in case of error.
-
-Revision 1.16  2012/11/29 23:02:53  mfred
-Fix for ZQ_CAL workaround and support for partial set of dimms.
-
-Revision 1.15  2012/11/16 16:36:20  mfred
-Update code to return an error from mss_slew_cal, if any, unless there is an error from mss_ddr_phy_reset.
-
-Revision 1.14  2012/11/14 23:42:43  mfred
-Call mss_slew_cal after the ddr_phy_reset steps.
-
-Revision 1.13  2012/10/19 20:27:26  mfred
-Added support for sub-partial-good operation when only a subset of DPs are good.
-
-Revision 1.12  2012/09/06 15:01:46  gollub
-
-Calling mss_unmask_ddrphy_errors after mss_ddr_phy_reser_cloned.
-
-Revision 1.11  2012/07/27 16:43:25  bellows
-CQ216395 hardware needs force mclk low in phy reset procedure
-
-Revision 1.10  2012/07/24 17:11:02  mfred
-Removed confusing comment.
-
-Revision 1.9  2012/07/18 16:27:39  mfred
-Check for ATTR_IS_SIMULATION attribute instead of use compiler switch.
-
-Revision 1.8  2012/06/07 22:30:25  jmcgill
-add sim only inits for phase rotator alignment (wrapped in SIM_ONLY ifdef for now)
-
-Revision 1.7  2012/05/31 18:27:54  mfred
-Removing some config settings that are now done in config file.  See Gary Van Huben note May 3, 2012
-
-Revision 1.6  2012/03/21 18:16:25  mfred
-Remove some commented out lines.
-
-Revision 1.5  2012/03/21 18:12:24  mfred
-Made updates requested by GFW team during code review 1.
-
-Revision 1.4  2012/02/22 18:36:36  mfred
-update for PLL lock polling, and check for ddr3 vs ddr4
-
-Revision 1.3  2012/02/14 16:34:12  mfred
-Fixed code to use halfword(3) instead of halfword(0)
-
-Revision 1.2  2012/01/31 18:42:07  mfred
-Change proc to do a single MBA and DDRPHY.  Looping will be handled by the target.
-
-Revision 1.1  2011/11/18 14:20:10  mfred
-Changed name of cen_ddr_phy_reset to mss_ddr_phy_reset.
-
-Revision 1.1  2011/10/27 22:49:36  mfred
-New version of cen_ddr_phy_reset that support the extended scom addresses.
-
-Revision 1.5  2011/04/29 16:44:06  mfred
-Removed a couple of unused address variables.
-
-Revision 1.4  2011/04/18 20:12:49  mfred
-Update scom addresses in comments and fix steps 10 and 13 per info from Gary H.
-
-Revision 1.3  2011/04/18 18:54:58  mfred
-Fixed some output messages.
-
-Revision 1.2  2011/04/12 13:22:32  mfred
-Fixed some output messages.
-
-Revision 1.1  2011/04/07 16:15:03  mfred
-Initial release.
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H
deleted file mode 100644
index e03f9e4ab..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H
+++ /dev/null
@@ -1,73 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_ddr_phy_reset.H,v 1.2 2012/03/21 18:12:28 mfred Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_ddr_phy_reset.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Mark Fredrickson  Email: mfred@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_ddr_phy_reset.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.1    | mfred  | 11/19/11| Updated
-
-#ifndef MSS_DDR_PHY_RESETHWPB_H_
-#define MSS_DDR_PHY_RESETHWPB_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_ddr_phy_reset_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-    // Target is centaur.mba
-
-/**
- * @brief mss_ddr_phy_reset procedure.  The purpose of this procedure is to do a soft reset of the DDR PHY logic and cause the DDR PLLs to lock.
- *
- * @param[in]  i_target  Reference to centaur.mba target
- *
- * @return ReturnCode
- */
-
-    fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target& i_target);
-    // Target is centaur.mba
-
-} // extern "C"
-
-#endif // MSS_DDR_PHY_RESETHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H
deleted file mode 100644
index 327b8940e..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H
+++ /dev/null
@@ -1,110 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_ddr4_funcs.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_ddr4_funcs.H,v 1.5 2015/09/04 18:14:20 thi Exp $
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_ddr4_funcs.H
-// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures
-// *! OWNER NAME : jdsloat@us.ibm.com
-// *! BACKUP NAME : sglancy@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//         |          |         |
-//  1.5    | 09/04/15 | thi     | Fix Doxygen
-//  1.4    | 03/14/14 | kcook   | Added DDR4 Register function support.
-//  1.3    | 10/10/13 | bellows | Added required CVS Id comment
-//  1.2    | 10/09/13 | jdsloat | Fixed argument list in function call
-//  1.1    | 10/04/13 | jdsloat | First revision
-
-#ifndef _MSS_DDR4_FUNCS_H
-#define _MSS_DDR4_FUNCS_H
-
-
-//----------------------------------------------------------------------
-// DDR4 FUNCS
-//----------------------------------------------------------------------
-
-
-//--------------------------------------------------------------
-// @brief Set MRS1 settings for Rank 0 and Rank 1
-//
-// @param[in] i_target             Reference to MBA Target.
-// @param[in] i_port_number        MBA port number
-// @param[in/out] io_ccs_inst_cnt  CCS instruction count
-//
-// @return ReturnCode
-//--------------------------------------------------------------
-fapi::ReturnCode mss_mrs_load_ddr4( fapi::Target& i_target,
-                                      uint32_t i_port_number,
-                                      uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// @brief Writes MPR pattern for inverted address location for
-//        training with DDR4 RDIMMs.
-//
-// @param[in] i_target_mba          Reference to MBA Target.
-//
-// @return ReturnCode
-//--------------------------------------------------------------
-fapi::ReturnCode mss_ddr4_invert_mpr_write( fapi::Target& i_target_mba);
-
-//--------------------------------------------------------------
-// @brief Writes RCD control words for DDR4 register.
-//
-// @param[in] i_target             Reference to MBA Target.
-// @param[in] i_port_number        MBA port number
-// @param[in/out] io_ccs_inst_cnt  CCS instruction count
-//
-// @return ReturnCode
-//--------------------------------------------------------------
-fapi::ReturnCode mss_rcd_load_ddr4(
-            fapi::Target& i_target,
-            uint32_t i_port_number,
-            uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// @brief Creates RCD_CNTRL_WORD attribute for DDR4 register
-//
-// @param[in] i_target_mba          Reference to MBA Target.
-//
-// @return ReturnCode
-//--------------------------------------------------------------
-fapi::ReturnCode mss_create_rcd_ddr4( const fapi::Target& i_target_mba);
-
-#endif /* _MSS_DDR4_FUNCS_H */
-
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
deleted file mode 100755
index e95011aee..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ /dev/null
@@ -1,2532 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.C,v 1.70 2015/09/04 01:10:11 kmack Exp $
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.70   | kmack    |01-Sep-15| Fixed more RCs and removed extraneous comments
-//  1.69   | kmack    |28-Aug-15| Fixed an RC
-//  1.68   | kmack    |10-Aug-15| Moved the mss_lrdimm_ddr4_db_load call to the be included or not included based on def FAPI_LRDIMM
-//  1.67   | kmack    |05-Aug-15| Commented out FAPI_DDR4 code
-//  1.66   | jdsloat  |09-MAY-14| Added an explicit 500us delay before execution of MRS cmds.
-//  1.65   | jdsloat  |09-APL-14| Fixed ifdef around #include mss_lrdimm_ddr4_funcs.H
-//  1.64   | jdsloat  |01-APL-14| RAS review edits/changes
-//  1.63   | jdsloat  |01-APL-14| RAS review edits/changes
-//  1.62   | jdsloat  |28-MAR-14| RAS review edits/changes
-//  1.61   | kcook    | 03/18/13| Added include mss_lrdimm_ddr4_funcs.H
-//  1.60   | kcook    | 03/14/13| Added calls to DDR4 ISDIMM functions.
-//  1.59   | jdsloat  | 11/11/13| Changed EFF attributes to VPD named attributes
-//  1.58   | jdsloat  | 10/15/13| Added rc checks in ddr4 shadow regs check per review request
-//  1.57   | jdsloat  | 10/09/13| Added mrs_load_ddr4 with defines for ddr4 usage, added shadow regs, removed complicated flow
-//  1.56   | bellows  | 09/16/13| Hostboot compile fix
-//  1.55   | kcook    | 09/13/13| Updated define FAPI_LRDIMM token.
-//  1.54   | kcook    | 08/27/13| Removed LRDIMM support to mss_lrdimm_funcs.C.
-//         |          |         | Added check for valid rank when flagging address mirroring.
-//  1.53   | kcook    | 08/16/13| Added LRDIMM support. Use with mss_funcs.C v1.32.
-//  1.52   | jdsloat  | 08/07/13| Added a single rc_num check and edited a debug/error message to make firmware happy.
-//  1.51   | jdsloat  | 08/01/13| Fixed dimm/rank conversion in address mirroring phy setting for a 4 rank dimm scenario
-//  1.50   | mwuu     | 07/17/13| Fixed CS when accessing RCD words on 1 rank RDIMMs
-//         |          |         | Added checks for invalid RTT_NOM, RTT_WR
-//  1.49   | jdsloat  | 06/11/13| Added several rc checks
-//  1.48   | jdsloat  | 05/20/13| Updated Mirror mode for DDR4 and keyed off new mba mirror_mode attribute
-//  1.47   | jdsloat  | 04/09/13| Added position info to debug messages
-//         |          |         | Added setup cycle for 2N mode
-//         |          |         | Added CKE high for RCD
-//         |          |         | Moved address mirror mode into its own function in mss_funcs
-//  1.46   | jdsloat  | 02/12/13| Fixed RTT_WR in MR2
-//  1.45   | jdsloat  | 01/28/13| is_sim check for address mirror mode
-//  1.44   | jdsloat  | 01/25/13| Address Mirror Mode added for dual drop CDIMMs
-//  1.43   | bellows  | 12/06/12| Fixed Review Comment
-//  1.42   | jdsloat  | 12/02/12| SHADOW REG PRINT OUT FIX
-//  1.41   | jdsloat  | 11/19/12| RCD Bit order fix.
-//  1.40   | jdsloat  | 11/17/12| MPR operation bit (MRS3, ADDR2) fix
-//  1.39   | gollub   | 9/05/12 | Calling mss_unmask_draminit_errors after mss_draminit_cloned
-//  1.38   | jdsloat  | 8/29/12 | Fixed Shadow Regs with Regression
-//  1.37   | jdsloat  | 8/28/12 | Revert back to 1.35.
-//  1.36   | jdsloat  | 7/25/12 | Printing out contents of MRS shadow registers.
-//  1.35   | bellows  | 7/25/12 | CQ 216395 (move force mclk low deassert to phyreset, resetn toggle)
-//  1.34   | bellows  | 7/16/12 | added in Id tag
-//  1.33   | jdsloat  | 6/26/12 | Added rtt_nom rank by rank value.
-//  1.32   | jdsloat  | 6/11/12 | Fixed Attributes: RTT_NOM, CL, DRAM_WR within the MRS load.
-//  1.31   | bellows  | 5/24/12 | Removed GP Bit
-//  1.30   | bellows  | 5/03/12 | MODEQ reg writes (HW191966). Has GP Bit for backwards compatibility
-//  1.29   | bellows  | 5/03/12 | Workaround removed for (HW199042). Use new hardware or workaround.initfile after phyreset
-//  1.28   | bellows  | 4/11/12 | fixed missing fapi:: for targets and return codes
-//  1.27   | bellows  | 4/11/12 | Workaround for fixing up phy config reset (HW199042)
-//  1.26   | jdsloat  | 3/20/12 | MRS bank fixe to remove reverse in ccs_inst_arry0
-//  1.25   | jdsloat  | 3/09/12 | RCD address fix.  Cleaned up the RCD section.
-//  1.24   | jdsloat  | 3/08/12 | Added CDIMM to RCD Check, MRS cycles through only configured ranks
-//  1.23   | jdsloat  | 3/05/12 | Fixed dram_al enum typo
-//  1.22   | jdsloat  | 2/27/12 | Fixed hostboot parenthesis error
-//  1.21   | jdsloat  | 2/27/12 | Cycle through Ports local of MRS/RCD, CL shift fix, Initialization of address/CS, neg end bit bug fix
-//  1.20   | jdsloat  | 2/23/12 | Fixed CL typo in MRS load
-//  1.19   | jdsloat  | 2/23/12 | MRS per rank, Interpret MRS ENUM correctly, CSN initialized to 0xFF
-//  1.18   | jdsloat  | 2/16/12 | Initialize rc_num, add num_ranks ==1 to MRS, Fix BA position in MRS
-//  1.17   | jdsloat  | 2/14/12 | MBA target translation, if statement clarification, style fixes
-//  1.16   | jdsloat  | 2/08/12 | Target to Target&, Described target with comment
-//  1.15   | jdsloat  | 2/02/12 | Fixed attributes array sizes, added debug messagesTarget to Target&, Described target
-//  1.14   | jdsloat  | 1/19/12 | Tabs to 4 spaces - properly
-//  1.13   | jdsloat  | 1/16/12 | Tabs to 4 spaces
-//  1.12   | jdsloat  | 1/13/12 | Curly Brackets, capitalization, "mss_" prefix, argument prefixes, no include C's, RC checks
-//  1.11   | jdsloat  | 1/5/12  | Changed Attribute grab, cleaned up includes section, Got rid of Globals
-//  1.10   | jdsloat  | 12/08/11| Changed MRS load  RAS, CAS, WEN
-//  1.9    | jdsloat  | 12/07/11| CSN for 2 rank dimms 0x3 to 0xC
-//  1.8    | jdsloat  | 11/08/11| Cycling through Ports - fix
-//  1.7    | jdsloat  | 10/31/11| CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix
-//  1.6    | jdsloat  | 10/18/11| RCD execution fix, debug messages
-//  1.5    | jdsloat  | 10/13/11| MRS fix, CCS count fix, get attribute fix, ecmdbuffer lengths within name
-//  1.4    | jdsloat  | 10/11/11| Fix CS Lines, dataBuffer.insert functions, ASSERT_RESETN_DRIVE_MEM_CLKS fix, attribute names
-//  1.3    | jdsloat  | 10/05/11| Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE
-//  1.2    | jdsloat  |04-OCT-11| Changing cen_funcs.C, cen_funcs.H to mss_funcs.C, mss_funcs.H
-//  1.1    | jdsloat  |04-OCT-11| First drop
-//---------|----------|---------|-----------------------------------------------
-//  1.6    | jdsloat  |29-Sep-11|Functional Changes: port flow, CCS changes, only configed CS, etc.  Compiles.
-//  1.5    | jdsloat  |22-Sep-11|Converted to FAPI, functional changes to match documentation
-//  1.3    | jdsloat  |14-Jul-11|Change GP4 register address from 1013 to 0x1013
-//  1.2    | jdsloat  |22-Apr-11|Moved CCS operations to Cen_funcs.C, draminit_training to cen_draminit_training.C
-//  1.1    | jdsloat  |31-Mar-11|First drop for centaur
-
-//----------------------------------------------------------------------
-//  FAPI function Includes
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-
-//----------------------------------------------------------------------
-//  Centaur function Includes
-//----------------------------------------------------------------------
-#include <mss_funcs.H>
-#include "cen_scom_addresses.H"
-#include <mss_unmask_errors.H>
-#include <mss_lrdimm_funcs.H>
-#include <mss_ddr4_funcs.H>
-
-#ifdef FAPI_LRDIMM
-#include <mss_lrdimm_ddr4_funcs.H>
-#endif
-
-#ifndef FAPI_LRDIMM
-using namespace fapi;
-fapi::ReturnCode mss_lrdimm_rcd_load(Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of mss_lrdimm_rcd_load on %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-ReturnCode mss_lrdimm_mrs_load(Target& i_target, uint32_t i_port_number, uint32_t dimm_number, uint32_t& io_ccs_inst_cnt)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of mss_lrdimm_mrs_load function on %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-fapi::ReturnCode mss_lrdimm_ddr4_db_load(Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of lrdimm_ddr4_db_load  %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-#endif
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-//----------------------------------------------------------------------
-//  Constants
-//----------------------------------------------------------------------
-const uint8_t MAX_NUM_DIMMS = 2;
-const uint8_t MAX_NUM_PORTS = 2;
-const uint8_t MAX_NUM_RANK_PAIR = 4;
-const uint8_t MAX_NUM_LR_RANKS = 8;
-const uint8_t MRS0_BA = 0;
-const uint8_t MRS1_BA = 1;
-const uint8_t MRS2_BA = 2;
-const uint8_t MRS3_BA = 3;
-const uint8_t MRS4_BA = 4;
-const uint8_t MRS5_BA = 5;
-const uint8_t MRS6_BA = 6;
-const uint8_t INVALID = 255;
-
-
-extern "C" {
-
-using namespace fapi;
-
-ReturnCode mss_rcd_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt);
-ReturnCode mss_mrs_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt);
-ReturnCode mss_assert_resetn_drive_mem_clks( Target& i_target);
-ReturnCode mss_deassert_force_mclk_low( Target& i_target);
-ReturnCode mss_assert_resetn ( Target& i_target, uint8_t value);
-ReturnCode mss_draminit_cloned(Target& i_target);
-
-const uint64_t  DELAY_100NS             = 100;      // general purpose 100 ns delay for HW mode   (2000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_1US               = 1000;     // general purpose 1 usec delay for HW mode   (20000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_100US             = 100000;   // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_500US             = 500000;   // general purpose 500 usec delay for HW mode (10000000 sim cycles if simclk = 20ghz)
-const uint64_t  DELAY_2000SIMCYCLES     = 2000;     // general purpose 2000 sim cycle delay for sim mode     (100 ns if simclk = 20Ghz)
-const uint64_t  DELAY_20000SIMCYCLES    = 20000;    // general purpose 20000 sim cycle delay for sim mode    (1 usec if simclk = 20Ghz)
-const uint64_t  DELAY_2000000SIMCYCLES  = 2000000;  // general purpose 2000000 sim cycle delay for sim mode  (100 usec if simclk = 20Ghz)
-const uint64_t  DELAY_10000000SIMCYCLES  = 10000000;  // general purpose 10000000 sim cycle delay for sim mode  (500 usec if simclk = 20Ghz)
-
-ReturnCode mss_draminit(Target& i_target)
-{
-    // Target is centaur.mba
-
-    ReturnCode rc;
-
-    rc = mss_draminit_cloned(i_target);
-
-        // If mss_unmask_draminit_errors gets it's own bad rc,
-        // it will commit the passed in rc (if non-zero), and return it's own bad rc.
-        // Else if mss_unmask_draminit_errors runs clean,
-        // it will just return the passed in rc.
-        rc = mss_unmask_draminit_errors(i_target, rc);
-
-        return rc;
-}
-
-ReturnCode mss_draminit_cloned(Target& i_target)
-{
-    // Target is centaur.mba
-    //
-
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t port_number;
-    uint32_t ccs_inst_cnt = 0;
-    uint8_t dram_gen;
-    uint8_t dimm_type;
-    uint8_t rank_pair_group = 0;
-    uint8_t bit_position = 0;
-    ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase mrs0(16);
-    ecmdDataBufferBase mrs1(16);
-    ecmdDataBufferBase mrs2(16);
-    ecmdDataBufferBase mrs3(16);
-    ecmdDataBufferBase mrs4(16);
-    ecmdDataBufferBase mrs5(16);
-    ecmdDataBufferBase mrs6(16);
-    uint16_t MRS0 = 0;
-    uint16_t MRS1 = 0;
-    uint16_t MRS2 = 0;
-    uint16_t MRS3 = 0;
-    uint16_t MRS4 = 0;
-    uint16_t MRS5 = 0;
-    uint16_t MRS6 = 0;
-    uint8_t num_drops_per_port;
-    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
-    uint8_t secondary_ranks_array[4][2]; //secondary_ranks_array[group][port]
-    uint8_t tertiary_ranks_array[4][2]; //tertiary_ranks_array[group][port]
-    uint8_t quaternary_ranks_array[4][2]; //quaternary_ranks_array[group][port]
-    uint8_t is_sim = 0;
-    uint8_t pri_dimm = 0;
-    uint8_t pri_dimm_rank = 0;
-    uint8_t sec_dimm = 0;
-    uint8_t sec_dimm_rank = 0;
-    uint8_t ter_dimm = 0;
-    uint8_t ter_dimm_rank = 0;
-    uint8_t qua_dimm = 0;
-    uint8_t qua_dimm_rank = 0;
-
-
-    //populate primary_ranks_arrays_array
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, secondary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, secondary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, secondary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, secondary_ranks_array[3]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, tertiary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, tertiary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, tertiary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, tertiary_ranks_array[3]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, quaternary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, quaternary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, quaternary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, quaternary_ranks_array[3]);
-    if(rc) return rc;
-
-
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, num_drops_per_port);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-
-    // Check to see if any dimm needs address mirror mode.  Set the approriate flag.
-    if ( ( address_mirror_map[0][0] ||
-          address_mirror_map[0][1] ||
-          address_mirror_map[1][0] ||
-          address_mirror_map[1][1] )
-        && (is_sim == 0)   )
-    {
-
-        FAPI_INF( "Setting Address Mirroring in the PHY on %s ", i_target.toEcmdString());
-
-        //Set the Address and BA bits affected by mirroring
-        if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                if(rc) return rc;
-                rc_num = rc_num | data_buffer_64.setBit(58);
-                rc_num = rc_num | data_buffer_64.setBit(59);
-                rc_num = rc_num | data_buffer_64.setBit(60);
-                rc_num = rc_num | data_buffer_64.setBit(62);
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-                rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                if(rc) return rc;
-
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                if(rc) return rc;
-                rc_num = rc_num | data_buffer_64.setBit(58);
-                rc_num = rc_num | data_buffer_64.setBit(59);
-                rc_num = rc_num | data_buffer_64.setBit(60);
-                rc_num = rc_num | data_buffer_64.setBit(62);
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-                rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                if(rc) return rc;
-                rc_num = rc_num | data_buffer_64.setBit(58);
-                rc_num = rc_num | data_buffer_64.setBit(59);
-                rc_num = rc_num | data_buffer_64.setBit(60);
-                rc_num = rc_num | data_buffer_64.setBit(61);
-                rc_num = rc_num | data_buffer_64.setBit(62);
-                rc_num = rc_num | data_buffer_64.setBit(63);
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-                rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                if(rc) return rc;
-
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                if(rc) return rc;
-                rc_num = rc_num | data_buffer_64.setBit(58);
-                rc_num = rc_num | data_buffer_64.setBit(59);
-                rc_num = rc_num | data_buffer_64.setBit(60);
-                rc_num = rc_num | data_buffer_64.setBit(61);
-                rc_num = rc_num | data_buffer_64.setBit(62);
-                rc_num = rc_num | data_buffer_64.setBit(63);
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-                rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-
-        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
-        {
-            for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++)
-            {
-
-                // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7
-                pri_dimm = (primary_ranks_array[rank_pair_group][port_number]) / 4;
-                pri_dimm_rank = primary_ranks_array[rank_pair_group][port_number] - 4*pri_dimm;
-                sec_dimm = (secondary_ranks_array[rank_pair_group][port_number]) / 4;
-                sec_dimm_rank = secondary_ranks_array[rank_pair_group][port_number] - 4*sec_dimm;
-                ter_dimm = (tertiary_ranks_array[rank_pair_group][port_number]) / 4;
-                ter_dimm_rank = tertiary_ranks_array[rank_pair_group][port_number] - 4*ter_dimm;
-                qua_dimm = (quaternary_ranks_array[rank_pair_group][port_number]) / 4;
-                qua_dimm_rank = quaternary_ranks_array[rank_pair_group][port_number] - 4*qua_dimm;
-                // Set the rank pairs that will be affected.
-                if ( port_number == 0 )
-                {
-                    if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 48;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                    if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 49;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P0");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P0_0x8000C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                    if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 48;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                    if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 49;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P0_0x8000C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                }
-                if ( port_number == 1 )
-                {
-                    if ( ( ( address_mirror_map[port_number][pri_dimm] & (0x08 >> pri_dimm_rank) ) ) && (primary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 48;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                    if ( ( ( address_mirror_map[port_number][sec_dimm] & (0x08 >> sec_dimm_rank) ) ) && (secondary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 49;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_P1");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_P1_0x8001C0110301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                    if ( ( ( address_mirror_map[port_number][ter_dimm] & (0x08 >> ter_dimm_rank) ) ) && (tertiary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on %s PORT%d RANKPAIR%d RANK%d", i_target.toEcmdString(), port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 48;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                    if ( ( ( address_mirror_map[port_number][qua_dimm] & (0x08 >> qua_dimm_rank) ) ) && (quaternary_ranks_array[rank_pair_group][port_number] != 0xff ) )
-                    {
-                        FAPI_INF( "Address Mirroring on PORT%d RANKPAIR%d RANK%d", port_number, rank_pair_group, primary_ranks_array[rank_pair_group][port_number]);
-                        bit_position = 2 * rank_pair_group + 49;
-                        FAPI_INF( "Setting bit %d", bit_position);
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.setBit(bit_position);
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_draminit_cloned: Error setting up buffers for DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_RANK_GROUP_EXT_P1_0x8001C0350301143F, data_buffer_64);
-                        if(rc) return rc;
-                    }
-                }
-
-            }
-        }
-    }
-
-        //Commented because Master Attention Reg Check not written yet.
-        //Master Attntion Reg Check... Need to add appropriate call below.
-        //MASTER_ATTENTION_REG_CHECK();
-
-        // Step one: Deassert Force_mclk_low signal
-        // this action needs to be done in ddr_phy_reset so that the plls can actually lock
-
-        // Step two: Assert Resetn signal, Begin driving mem clks
-        rc = mss_assert_resetn_drive_mem_clks(i_target);
-        if(rc)
-        {
-            FAPI_ERR(" assert_resetn_drive_mem_clks Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            return rc;
-        }
-
-        rc = mss_assert_resetn(i_target, 0 ); // assert a reset
-        if(rc)
-        {
-            FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            return rc;
-        }
-
-        rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
-        if(rc) return rc;
-
-        rc = mss_assert_resetn(i_target, 1 ); // de-assert a reset
-        if(rc)
-        {
-            FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            return rc;
-        }
-        // Cycle through Ports...
-        // Ports 0-1
-        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
-        {
-            if (!((dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_UDIMM)||(dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_CDIMM)))
-            {
-                // Step three: Load RCD Control Words
-                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                {
-                   rc = mss_rcd_load_ddr4(i_target, port_number, ccs_inst_cnt);
-                   if(rc)
-                   {
-                       FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                       return rc;
-                   }
-                   if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
-                   {
-                      // Set Data Buffer Function  words
-                      rc = mss_lrdimm_ddr4_db_load(i_target, port_number, ccs_inst_cnt);
-                      if(rc)
-                      {
-                          FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                          return rc;
-                      }
-                   }
-
-                }
-                else
-                {
-                   rc = mss_rcd_load(i_target, port_number, ccs_inst_cnt);
-                   if(rc)
-                   {
-                       FAPI_ERR(" rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                       return rc;
-                   }
-
-                   if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
-                   {
-                      // Set Function 1-13 rcd words
-                      rc = mss_lrdimm_rcd_load(i_target, port_number, ccs_inst_cnt);
-                      if(rc)
-                      {
-                          FAPI_ERR(" LRDIMM rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                          return rc;
-                      }
-                   }
-                }
-            }
-        }
-
-        rc = fapiDelay(DELAY_500US, DELAY_10000000SIMCYCLES); // wait 10000 simcycles (in sim mode) OR 500 uS (in hw mode)
-
-        if(rc)
-        {
-            FAPI_ERR(" Delay Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            return rc;
-        }
-
-
-
-
-
-        // Cycle through Ports...
-        // Ports 0-1
-        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
-        {
-
-            // Step four: Load MRS Setting
-            if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)
-            {
-                    rc = mss_mrs_load(i_target, port_number, ccs_inst_cnt);
-                    if(rc)
-                    {
-                        FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                        return rc;
-                    }
-            }
-            else
-            {
-                    rc = mss_mrs_load_ddr4(i_target, port_number, ccs_inst_cnt);
-                    if(rc)
-                    {
-                        FAPI_ERR(" mrs_load_ddr4 Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                        return rc;
-                    }
-            }
-
-        }
-
-        // Execute the contents of CCS array
-        if (ccs_inst_cnt  > 0)
-        {
-            // Set the End bit on the last CCS Instruction
-            rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1);
-            if(rc)
-            {
-                FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                return rc;
-            }
-
-            rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-            if(rc)
-            {
-                FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                return rc;
-            }
-
-            ccs_inst_cnt = 0;
-        }
-        else
-        {
-            FAPI_INF("No Memory configured.");
-        }
-
-        // Cycle through Ports...
-        // Ports 0-1
-        for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
-        {
-
-        for ( rank_pair_group = 0; rank_pair_group < MAX_NUM_RANK_PAIR; rank_pair_group++)
-        {
-        //Check if rank group exists
-            if((primary_ranks_array[rank_pair_group][0] != INVALID) || (primary_ranks_array[rank_pair_group][1] != INVALID))
-            {
-
-                if (port_number == 0)
-                {
-                        // Get contents of MRS Shadow Regs and Print it to output
-                        if (rank_pair_group == 0)
-                        {
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P0_0x8000C01C0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0 );
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P0_0x8000C0200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(),  port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P0_0x8000C0210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(),  port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P0_0x8000C0220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(),  port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-                        else if (rank_pair_group == 1)
-                        {
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P0_0x8000C11C0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS0);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P0_0x8000C11F0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P0_0x8000C1200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P0_0x8000C1210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P0_0x8000C1220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-                        else if (rank_pair_group == 2)
-                        {
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P0_0x8000C21C0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS0);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P0_0x8000C21F0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P0_0x8000C2200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P0_0x8000C2210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P0_0x8000C2220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-                        else if (rank_pair_group == 3)
-                        {
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P0_0x8000C31C0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(),  port_number, rank_pair_group, MRS0);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P0_0x8000C31F0301143F, data_buffer_64);
-                               if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P0_0x8000C3200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P0_0x8000C3210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P0_0x8000C3220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-                }
-                else if (port_number == 1)
-                {
-                        if (rank_pair_group == 0)
-                        {
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP0_P1_0x8001C01C0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS0 );
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP0_P1_0x8001C0200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP0_P1_0x8001C0210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP0_P1_0x8001C0220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-                        else if (rank_pair_group == 1)
-                        {
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP1_P1_0x8001C11C0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS0);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP1_P1_0x8001C11F0301143F, data_buffer_64);
-                                if(rc) return rc;
-                                rc_num = rc_num | data_buffer_64.reverse();
-                                rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                                FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP1_P1_0x8001C1200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP1_P1_0x8001C1210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP1_P1_0x8001C1220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-
-                                }
-
-                        }
-                        else if (rank_pair_group == 2)
-                        {
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP2_P1_0x8001C21C0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP2_P1_0x8001C21F0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                                if (rc_num)
-                                {
-                                    FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                    rc_buff.setEcmdError(rc_num);
-                                    return rc_buff;
-                                }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP2_P1_0x8001C2200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP2_P1_0x8001C2210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP2_P1_0x8001C2220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-                        else if (rank_pair_group == 3)
-                        {
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_PRI_RP3_P1_0x8001C31C0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs0.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-                               if (rc_num)
-                               {
-                                   FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                   rc_buff.setEcmdError(rc_num);
-                                   return rc_buff;
-                               }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 0 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS0);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs1.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-                               if (rc_num)
-                               {
-                                   FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                   rc_buff.setEcmdError(rc_num);
-                                   return rc_buff;
-                               }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 1 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS1);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs2.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-                               if (rc_num)
-                               {
-                                   FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                   rc_buff.setEcmdError(rc_num);
-                                   return rc_buff;
-                               }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 2 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS2);
-
-                               rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR3_PRI_RP3_P1_0x8001C31F0301143F, data_buffer_64);
-                                if(rc) return rc;
-                               rc_num = rc_num | data_buffer_64.reverse();
-                               rc_num = rc_num | mrs3.insert(data_buffer_64, 0, 16);
-                               rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                               if (rc_num)
-                               {
-                                   FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                   rc_buff.setEcmdError(rc_num);
-                                   return rc_buff;
-                               }
-                               FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 3 RP %d VALUE: 0x%04X", i_target.toEcmdString(), port_number, rank_pair_group, MRS3);
-
-                                if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                {
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR0_SEC_RP3_P1_0x8001C3200301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs4.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 4 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS4);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_SEC_RP3_P1_0x8001C3210301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs5.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 5 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS5);
-
-                                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_SEC_RP3_P1_0x8001C3220301143F, data_buffer_64);
-                                        if(rc) return rc;
-                                        rc_num = rc_num | data_buffer_64.reverse();
-                                        rc_num = rc_num | mrs6.insert(data_buffer_64, 0, 16);
-                                        rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-                                        if (rc_num)
-                                        {
-                                            FAPI_ERR( "mss_draminit: Error setting up buffers");
-                                            rc_buff.setEcmdError(rc_num);
-                                            return rc_buff;
-                                        }
-                                        FAPI_INF( "%s PORT %d SHADOW REGISTER MRS 6 RP %d VALUE: 0x%04X",  i_target.toEcmdString(), port_number, rank_pair_group, MRS6);
-                                }
-
-                        }
-
-                }
-                }
-            }
-        }
-
-        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
-        {
-           FAPI_INF("Performing B-side address inversion MPR write pattern");
-
-           rc = mss_ddr4_invert_mpr_write(i_target);
-           if (rc) return rc;
-        }
-
-
-
-        // TODO:
-        // This is Commented out because RCD Parity Check has not been written yet.
-        // Check RCD Parity
-        //rc = RCD_PARITY_CHECK(i_target);
-        //if(rc){
-            //FAPI_ERR(" RCD_PARITY_CHECK FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-            //return rc;
-        //}
-
-        //Master Attntion Reg Check... Need to add appropriate call below.
-        //MASTER_ATTENTION_REG_CHECK();
-
-    return rc;
-}
-
-
-
-ReturnCode mss_assert_resetn_drive_mem_clks(
-            Target& i_target
-            )
-{
-    // mcbist_ddr_resetn = 1 -- to deassert DDR RESET#
-    //mcbist_ddr_dphy_nclk = 01, mcbist_ddr_dphy_pclk = 10 -- to drive the memory clks
-
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase stop_on_err_1(1);
-    ecmdDataBufferBase ue_disable_1(1);
-    ecmdDataBufferBase data_sel_2(2);
-    ecmdDataBufferBase pclk_2(2);
-    rc_num = rc_num | pclk_2.insertFromRight((uint32_t) 2, 0, 2);
-    ecmdDataBufferBase nclk_2(2);
-    rc_num = rc_num | nclk_2.insertFromRight((uint32_t) 1, 0, 2);
-    ecmdDataBufferBase cal_time_cnt_16(16);
-    ecmdDataBufferBase resetn_1(1);
-    rc_num = rc_num | resetn_1.setBit(0);
-    ecmdDataBufferBase reset_recover_1(1);
-    ecmdDataBufferBase copy_spare_cke_1(1);
-    rc_num = rc_num | copy_spare_cke_1.setBit(0); // mdb : clk enable on for spare
-
-    FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN, DRIVING MEM CLKS +++++++++++++++++++++");
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_assert_resetn_drive_mem_clks: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    // Setting CCS Mode
-    rc = mss_ccs_mode(i_target,
-                      stop_on_err_1,
-                      ue_disable_1,
-                      data_sel_2,
-                      pclk_2,
-                      nclk_2,
-                      cal_time_cnt_16,
-                      resetn_1,
-                      reset_recover_1,
-                      copy_spare_cke_1);
-
-    return rc;
-}
-
-ReturnCode mss_rcd_load(
-            Target& i_target,
-            uint32_t i_port_number,
-            uint32_t& io_ccs_inst_cnt
-            )    {
-
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t dimm_number;
-    uint32_t rcd_number;
-
-    ecmdDataBufferBase rcd_cntl_wrd_4(8);
-    ecmdDataBufferBase rcd_cntl_wrd_64(64);
-    uint16_t num_ranks;
-
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.setBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.setBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.setBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    uint64_t rcd_array[2][2]; //[port][dimm]
-    uint8_t dimm_type;
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array);
-    if(rc) return rc;
-
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-    io_ccs_inst_cnt ++;
-
-    FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number);
-
-    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-        num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-        if (num_ranks == 0)
-        {
-            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks);
-        }
-        else
-        {
-            FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number);
-            FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]);
-
-            if (rc_num)
-            {
-                FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                rc_buff.setEcmdError(rc_num);
-                return rc_buff;
-            }
-
-            // ALL active CS lines at a time.
-            rc_num = rc_num | csn_8.setBit(0,8);
-            if (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)
-            {
-                // for dimm0 use CS0,1 (active low); for dimm1 use CS4,5 (active low)
-                rc_num = rc_num | csn_8.clearBit((4*dimm_number), 2 );
-            }
-            else if ((num_ranks == 1) || (num_ranks == 2))
-            {
-                rc_num = rc_num | csn_8.clearBit(0+4*dimm_number);
-                rc_num = rc_num | csn_8.clearBit(1+4*dimm_number);
-            }
-            else if (num_ranks == 4)
-            {
-                rc_num = rc_num | csn_8.clearBit(0+4*dimm_number);
-                rc_num = rc_num | csn_8.clearBit(1+4*dimm_number);
-                rc_num = rc_num | csn_8.clearBit(2+4*dimm_number);
-                rc_num = rc_num | csn_8.clearBit(3+4*dimm_number);
-            }
-
-            // Propogate through the 16, 4-bit control words
-            for ( rcd_number = 0; rcd_number<= 15; rcd_number++)
-            {
-                rc_num = rc_num | bank_3.clearBit(0, 3);
-                rc_num = rc_num | address_16.clearBit(0, 16);
-
-                rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcd_array[i_port_number][dimm_number]);
-                rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*rcd_number, 4);
-
-                //control word number code bits A0, A1, A2, BA2
-                rc_num = rc_num | address_16.insert(rcd_number, 2, 1, 29);
-                rc_num = rc_num | address_16.insert(rcd_number, 1, 1, 30);
-                rc_num = rc_num | address_16.insert(rcd_number, 0, 1, 31);
-                rc_num = rc_num | bank_3.insert(rcd_number, 2, 1, 28);
-
-                //control word values RCD0 = A3, RCD1 = A4, RCD2 = BA0, RCD3 = BA1
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 3);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 4, 1, 2);
-                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 0, 1, 1);
-                rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 1, 1, 0);
-
-                // Send out to the CCS array
-                if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && (rcd_number == 2 || rcd_number == 10) )
-                {
-                   rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words
-                }
-                else
-                {
-                   rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
-                }
-
-
-                if (rc_num)
-                {
-                   FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                   rc_buff.setEcmdError(rc_num);
-                   return rc_buff;
-                }
-
-                rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                if(rc) return rc;
-                rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                if(rc) return rc;
-                io_ccs_inst_cnt ++;
-
-            }
-        }
-    }
-    return rc;
-}
-
-ReturnCode mss_mrs_load(
-            Target& i_target,
-            uint32_t i_port_number,
-            uint32_t& io_ccs_inst_cnt
-            )
-{
-
-    uint32_t dimm_number;
-    uint32_t rank_number;
-    uint32_t mrs_number;
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-
-    ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.clearBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.clearBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.clearBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase csn_setup_8(8);
-    rc_num = rc_num | csn_setup_8.setBit(0,8);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_idles_setup_16(16);
-    rc_num = rc_num | num_idles_setup_16.insertFromRight((uint32_t) 400, 0, 16);
-
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    ecmdDataBufferBase mrs0(16);
-    ecmdDataBufferBase mrs1(16);
-    ecmdDataBufferBase mrs2(16);
-    ecmdDataBufferBase mrs3(16);
-    uint16_t MRS0 = 0;
-    uint16_t MRS1 = 0;
-    uint16_t MRS2 = 0;
-    uint16_t MRS3 = 0;
-
-    uint16_t num_ranks = 0;
-    uint8_t lrdimm_rank_mult_mode = 0;
-
-
-    FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number);
-
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t dram_2n_mode = 0;
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-
-    //Lines commented out in the following section are waiting for xml attribute adds
-    //MRS0
-    uint8_t dram_bl;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl);
-    if(rc) return rc;
-    uint8_t read_bt; //Read Burst Type
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt);
-    if(rc) return rc;
-    uint8_t dram_cl;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl);
-    if(rc) return rc;
-    uint8_t test_mode; //TEST MODE
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode);
-    if(rc) return rc;
-    uint8_t dll_reset; //DLL Reset
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset);
-    if(rc) return rc;
-    uint8_t dram_wr;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr);
-    if(rc) return rc;
-    uint8_t dll_precharge; //DLL Control For Precharge
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge);
-    if(rc) return rc;
-
-    if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8)
-    {
-        dram_bl = 0x00;
-    }
-    else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF)
-    {
-        dram_bl = 0x80;
-    }
-    else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4)
-    {
-        dram_bl = 0x40;
-    }
-
-    if (dram_wr == 16)
-    {
-        dram_wr = 0x00;
-    }
-    else if (dram_wr == 5)
-    {
-        dram_wr = 0x80;
-    }
-    else if (dram_wr == 6)
-    {
-        dram_wr = 0x40;
-    }
-    else if (dram_wr == 7)
-    {
-        dram_wr = 0xC0;
-    }
-    else if (dram_wr == 8)
-    {
-        dram_wr = 0x20;
-    }
-    else if (dram_wr == 10)
-    {
-        dram_wr = 0xA0;
-    }
-    else if (dram_wr == 12)
-    {
-        dram_wr = 0x60;
-    }
-    else if (dram_wr == 14)
-    {
-        dram_wr = 0xE0;
-    }
-
-
-    if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL)
-    {
-        read_bt = 0x00;
-    }
-    else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE)
-    {
-        read_bt = 0xFF;
-    }
-
-    if ((dram_cl > 4)&&(dram_cl < 12))
-    {
-        dram_cl = (dram_cl - 4) << 1;
-    }
-    else if ((dram_cl > 11)&&(dram_cl < 17))
-    {
-        dram_cl = ((dram_cl - 12) << 1) + 1;
-    }
-    dram_cl = mss_reverse_8bits(dram_cl);
-
-    if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL)
-    {
-        test_mode = 0x00;
-    }
-    else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST)
-    {
-        test_mode = 0xFF;
-    }
-
-    if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_YES)
-    {
-        dll_reset = 0xFF;
-    }
-    else if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_NO)
-    {
-        dll_reset = 0x00;
-    }
-
-    if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
-    {
-        dll_precharge = 0x00;
-    }
-    else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT)
-    {
-        dll_precharge = 0xFF;
-    }
-
-    //MRS1
-    uint8_t dll_enable; //DLL Enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable);
-    if(rc) return rc;
-    uint8_t out_drv_imp_cntl[2][2];
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl);
-    if(rc) return rc;
-    uint8_t dram_rtt_nom[2][2][4];
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom);
-    if(rc) return rc;
-    uint8_t dram_al;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al);
-    if(rc) return rc;
-    uint8_t wr_lvl; //write leveling enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl);
-    if(rc) return rc;
-    uint8_t tdqs_enable; //TDQS Enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable);
-    if(rc) return rc;
-    uint8_t q_off; //Qoff - Output buffer Enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off);
-    if(rc) return rc;
-
-    if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE)
-    {
-        dll_enable = 0x00;
-    }
-    else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE)
-    {
-        dll_enable = 0xFF;
-    }
-
-    if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE)
-    {
-        dram_al = 0x00;
-    }
-    else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1)
-    {
-        dram_al = 0x80;
-    }
-    else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2)
-    {
-        dram_al = 0x40;
-    }
-
-    if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE)
-    {
-        wr_lvl = 0x00;
-    }
-    else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE)
-    {
-        wr_lvl = 0xFF;
-    }
-
-    if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE)
-    {
-        tdqs_enable = 0x00;
-    }
-    else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE)
-    {
-        tdqs_enable = 0xFF;
-    }
-
-    if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE)
-    {
-        q_off = 0xFF;
-    }
-    else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE)
-    {
-        q_off = 0x00;
-    }
-
-    //MRS2
-    uint8_t pt_arr_sr; //Partial Array Self Refresh
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_PASR, &i_target, pt_arr_sr);
-    if(rc) return rc;
-    uint8_t cwl; // CAS Write Latency
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl);
-    if(rc) return rc;
-    uint8_t auto_sr; // Auto Self-Refresh
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ASR, &i_target, auto_sr);
-    if(rc) return rc;
-    uint8_t sr_temp; // Self-Refresh Temp Range
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_SRT, &i_target, sr_temp);
-    if(rc) return rc;
-    uint8_t dram_rtt_wr[2][2][4];
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr);
-    if(rc) return rc;
-
-    if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FULL)
-    {
-        pt_arr_sr = 0x00;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_HALF)
-    {
-        pt_arr_sr = 0x80;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_QUARTER)
-    {
-        pt_arr_sr = 0x40;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_FIRST_EIGHTH)
-    {
-        pt_arr_sr = 0xC0;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_THREE_FOURTH)
-    {
-        pt_arr_sr = 0x20;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_HALF)
-    {
-        pt_arr_sr = 0xA0;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_QUARTER)
-    {
-        pt_arr_sr = 0x60;
-    }
-    else if (pt_arr_sr == ENUM_ATTR_EFF_DRAM_PASR_LAST_EIGHTH)
-    {
-        pt_arr_sr = 0xE0;
-    }
-
-    cwl = mss_reverse_8bits(cwl - 5);
-
-    if (auto_sr == ENUM_ATTR_EFF_DRAM_ASR_SRT)
-    {
-        auto_sr = 0x00;
-    }
-    else if (auto_sr == ENUM_ATTR_EFF_DRAM_ASR_ASR)
-    {
-        auto_sr = 0xFF;
-    }
-
-    if (sr_temp == ENUM_ATTR_EFF_DRAM_SRT_NORMAL)
-    {
-        sr_temp = 0x00;
-    }
-    else if (sr_temp == ENUM_ATTR_EFF_DRAM_SRT_EXTEND)
-    {
-        sr_temp = 0xFF;
-    }
-
-    //MRS3
-    uint8_t mpr_loc; // MPR Location
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_LOC, &i_target, mpr_loc);
-    if(rc) return rc;
-    uint8_t mpr_op; // MPR Operation Mode
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op);
-    if(rc) return rc;
-
-    mpr_loc = mss_reverse_8bits(mpr_loc);
-
-    if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE)
-    {
-        mpr_op = 0xFF;
-    }
-    else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE)
-    {
-        mpr_op = 0x00;
-    }
-
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-    io_ccs_inst_cnt ++;
-
-    // Dimm 0-1
-    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-        num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-        if (num_ranks == 0)
-        {
-            FAPI_INF( " %s PORT%d DIMM%d not configured. Num_ranks: %d ", i_target.toEcmdString(), i_port_number, dimm_number, num_ranks);
-        }
-        else
-        {
-
-            if (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)
-            {
-                rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode);
-                if(rc) return rc;
-
-                if ( (lrdimm_rank_mult_mode == 4) && (num_ranks == 8) )
-                {
-                   num_ranks = 2;
-                }
-            }
-
-            // Rank 0-3
-            for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-            {
-                    FAPI_INF( "MRS SETTINGS FOR %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port_number, dimm_number, rank_number);
-
-                    rc_num = rc_num | csn_8.setBit(0,8);
-                    rc_num = rc_num | address_16.clearBit(0, 16);
-
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_bl, 0, 2, 0);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 2, 1, 0);
-                    rc_num = rc_num | mrs0.insert((uint8_t) read_bt, 3, 1, 0);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 4, 3, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) test_mode, 7, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dll_reset, 8, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_wr, 9, 3);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dll_precharge, 12, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 13, 3);
-
-                    rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-
-                    if ( lrdimm_rank_mult_mode != 0 )
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40;
-                    }
-                    else
-                    {
-                        //DECONFIG and FFDC INFO
-                        const fapi::Target & TARGET_MBA_ERROR = i_target;
-                        const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number];
-                        const uint32_t & PORT = i_port_number;
-                        const uint32_t & DIMM = dimm_number;
-                        const uint32_t & RANK = rank_number;
-
-                        FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_NOM value: %d from attribute", dram_rtt_nom[i_port_number][dimm_number][rank_number]);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_RTT_NOM_IMP_INPUT_ERROR);
-                        return rc;
-                    }
-
-                    if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM40)
-                    {
-                        out_drv_imp_cntl[i_port_number][dimm_number] = 0x00;
-                    }
-                    else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34)
-                    {
-                        out_drv_imp_cntl[i_port_number][dimm_number] = 0x80;
-                    }
-
-                    rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 2, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 6, 1, 1);
-                    rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 9, 1, 2);
-                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1);
-                    rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3);
-
-                    rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-
-
-                    if ( (lrdimm_rank_mult_mode != 0) && (rank_number > 1) )
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = dram_rtt_wr[i_port_number][dimm_number][0];
-                    }
-                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80;
-                    }
-                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40;
-                    }
-                    else
-                    {
-
-                        //DECONFIG and FFDC INFO
-                        const fapi::Target & TARGET_MBA_ERROR = i_target;
-                        const uint8_t & IMP = dram_rtt_nom[i_port_number][dimm_number][rank_number];
-                        const uint32_t & PORT = i_port_number;
-                        const uint32_t & DIMM = dimm_number;
-                        const uint32_t & RANK = rank_number;
-
-                        FAPI_ERR( "mss_mrs_load: Error determining ATTR_VPD_DRAM_RTT_WR value: %d from attribute", dram_rtt_wr[i_port_number][dimm_number][rank_number]);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_RTT_WR_IMP_INPUT_ERROR);
-                        return rc;
-                    }
-
-                    rc_num = rc_num | mrs2.insert((uint8_t) pt_arr_sr, 0, 3);
-                    rc_num = rc_num | mrs2.insert((uint8_t) cwl, 3, 3);
-                    rc_num = rc_num | mrs2.insert((uint8_t) auto_sr, 6, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) sr_temp, 7, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2);
-                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 5);
-
-                    rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-
-                    rc_num = rc_num | mrs3.insert((uint8_t) mpr_loc, 0, 2);
-                    rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-                    rc_num = rc_num | mrs3.insert((uint16_t) 0x0000, 3, 13);
-
-                    rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                    FAPI_INF( "MRS 0: 0x%04X", MRS0);
-                    FAPI_INF( "MRS 1: 0x%04X", MRS1);
-                    FAPI_INF( "MRS 2: 0x%04X", MRS2);
-                    FAPI_INF( "MRS 3: 0x%04X", MRS3);
-
-                    if (rc_num)
-                    {
-                        FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-                        rc_buff.setEcmdError(rc_num);
-                        return rc_buff;
-                    }
-
-                    // Only corresponding CS to rank
-                    rc_num = rc_num | csn_8.setBit(0,8);
-                    rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-
-                    // Propogate through the 4 MRS cmds
-                    for ( mrs_number = 0; mrs_number < 4; mrs_number++)
-                    {
-
-                        // Copying the current MRS into address buffer matching the MRS_array order
-                        // Setting the bank address
-                        if (mrs_number == 0)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 1)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 2)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 3)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5);
-                        }
-
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-
-                        if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-                        {
-                            rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-                            if(rc) return rc;
-                        }
-
-
-                        if (dram_2n_mode  == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE)
-                        {
-
-                        // Send out to the CCS array a "setup" cycle
-                        rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_setup_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                        if(rc) return rc;
-                        rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_setup_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                        if(rc) return rc;
-
-                        io_ccs_inst_cnt ++;
-
-                        }
-
-                        // Send out to the CCS array
-                        rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                        if(rc) return rc;
-                        rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                        if(rc) return rc;
-                        io_ccs_inst_cnt ++;
-                    } // end mrs loop
-            } // end rank loop
-
-            // For LRDIMM  Set Rtt_nom, rtt_wr, driver impedance for R0 and R1
-            if ( (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && lrdimm_rank_mult_mode != 0 )
-            {
-                 rc = mss_lrdimm_mrs_load(i_target, i_port_number, dimm_number, io_ccs_inst_cnt);
-                 if(rc) return rc;
-            } // end LRDIMM 8R dir MRS 1
-
-        } // end if has ranks
-    } // end dimm loop
-
-    return rc;
-}
-
-ReturnCode mss_assert_resetn (
-            Target& i_target,
-            uint8_t value
-            )
-{
-// value of 1 deasserts reset
-
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer(64);
-
-    FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN to the value of %d +++++++++++++++++++++", value);
-
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.insert( value, 24, 1, 7); // use bit 7
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_assert_resetn: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    return rc;
-}
-
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H
deleted file mode 100644
index b11db8a7a..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H
+++ /dev/null
@@ -1,74 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.H $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.H,v 1.5 2012/02/10 21:59:20 jdsloat Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_draminit.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_draminit.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Jacob Sloat     Email: jdsloat@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_draminit.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.4    | jdsloat  |  2/10/12| & fix
-//  1.3    | jdsloat  |  2/08/12| added description to target
-//  1.2    | jdsloat  |  1/13/12| added "fapi::" and "const" in typedef to match the call in the extern
-//  1.1    | jdsloat  | 11/18/11| Updated
-
-#ifndef MSS_DRAMINITHWPB_H_
-#define MSS_DRAMINITHWPB_H_
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_draminit_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-
-/**
- * @brief Draminit procedure. Loading RCD and MRS into the drams.
- *
- * @param[in]  i_target  Reference to centaur.mba target
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode mss_draminit(const fapi::Target& i_target);
-
-} // extern "C"
-
-#endif // MSS_DRAMINITHWPB_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
deleted file mode 100644
index 23b656401..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ /dev/null
@@ -1,1281 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_mc.C,v 1.51 2015/03/19 16:48:09 dcadiga Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : cen_draminit_mc.C
-// *! DESCRIPTION : Procedure for handing over control to the MC
-// *! OWNER NAME :  David Cadigan   Email: dcadiga@us.ibm.com
-// *! BACKUP NAME : Jacob Sloat   Email: jdsloat@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-//
-//Run cen_draminit_mc.C to complete the initialization sequence. This performs the steps of
-//***Set the IML Complete bit MBSSQ(2) (SCOM Addr: 0x02011417) to indicate that IML has completed
-//***Start the refresh engines
-//***Enabling periodic calibration and power management.
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.51   | dcadiga  |18-MAR-15| Added function to enable address inversion on port 1
-//  1.50   | gollub   |12-FEB-15| Changed maint cmd delay from 100mSec to 1mSec
-//  1.49   | gollub   |12-FEB-15| Add check for RCD protect time on RDIMM and LRDIMM
-//  1.48   | dcadiga  |05-DEC-14| Powerdown control at initfile
-//  1.47   | dcadiga  |09-SEP-14| Removed SPARE cke disable step
-//  1.46   | gollub   |07-APR-14| Removed call to mss_unmask_inband_errors (moved it to proc_cen_framelock)
-//  1.45   | dcadiga  |14-FEB-14| Periodic Cal Fix for DD2
-//  1.44   | bellows  |12-FEB-14| Workaround for ENABLE_RCE_WITH_OTHER_ERRORS_HW246685
-//  1.43   | dcadiga  |28-OCT-13| Fixed code review comments for parent chip and typos
-//  1.42   | dcadiga  |16-OCT-13| Fixed Code Review Comments, added DD2.X EC check for parity on 32GB
-//  1.41   | dcadiga  |16-OCT-13| repeating Brent's test
-//  1.40   | bwieman  |21-JUN-13| just testing a commit
-//  1.39   | dcadiga  |21-JUN-13| Fixed Code Review Comments
-//  1.38   | dcadiga  |10-JUN-13| Removed Local Edit Info, added version comment
-//  1.37   | dcadiga  |10-JUN-13| Added Periodic Cal for 1.1
-//  1.36   | dcadiga  |03-APR-13| Fixed compile warning
-//  1.35   | dcadiga  |01-APR-13| Temp Fix For Parity Error on 32GB
-//  1.34   | dcadiga  |12-MAR-13| Added spare cke disable as step 0
-//  1.33   | dcadiga  |04-FEB-13| For some reason the main procedure call was commented out in the last commit... commenting it back in
-//  1.32   | gollub   |31-JAN-13| Uncommenting mss_unmask_maint_errors and mss_unmask_inband_errors
-//  1.31   | dcadiga  |21-JAN-13| Fixed variable name for memcal_interval (coded as memcal_iterval...)
-//  1.30   | dcadiga  |21-JAN-13| Hardcoded memcal interval to 0 (disabled) until attribute for EC is available
-//  1.29   | jdsloat  |14-JAN-13| Owner changed to Dave Cadigan.
-//  1.28   | bellows  |01-JAN-13| Added ECC Enable 64-byte data/checkbit inversion (from jdsloat)
-//  1.27   | gollub   |21-DEC-12| Calling mss_unmask_maint_errors and mss_unmask_inband_errors after mss_draminit_mc_cloned
-//  1.26   | jdsloat  |21-NOV-12| Changed Periodic Cal to Execute via MBA regs depending upon the ZQ Cal and MEM Cal timer values; 0 = disabled
-//  1.25   | jdsloat  |11-SEP-12| Calling mss_unmask_maint_errors and mss_unmask_inband_errors after mss_draminit_mc_cloned
-//  1.24   | bellows  |16-JUL-12| added in Id tag
-//  1.22   | bellows  |13-JUL-12| Fixed periodic cal bit 61 being set. HW214829
-//  1.20   | jdsloat  |21-MAY-12| Typo fix, addresses moved to cen_scom_addresses.H, moved per cal settings to initfile
-//  1.19   | jdsloat  |08-MAY-12| All Refresh controls moved to initfile, changed to just enable refresh
-//  1.18   | jdsloat  |07-MAY-12| Fixed refresh interval, trfc, ref check interval bit ordering
-//  1.16   | bellows  |04-MAY-12| Temporary remove of attr read of freq until method defined
-//  1.15   | jdsloat  |16-APR-12| TRFC fixed to insert the right aligned 8 bits
-//  1.15   | jdsloat  |12-Mar-12| Attribute upgrade for cronusflex 12.4 ... trfc to uint32
-//  1.14   | jdsloat  |07-Mar-12| Fixed iml_complete to match target
-//  1.13   | jdsloat  |07-Mar-12| Changed to target centaur with getChildchip, fixed buffer insert
-//  1.12   | jdsloat  |20-Feb-12| Built control_bit_ecc and power_management, added ccs_mode_reset
-//  1.11   | jdsloat  |20-Feb-12| removing #include <fapiClientCapi.H>
-//  1.10   | jdsloat  |20-Feb-12| Made Constants, Fixed RC_buff checking, Num_ranks check
-//  1.10   | jdsloat  |10-Feb-12| updated formatting/style, fixed some addresses, removed mba23 calls
-//  1.9    | M Bellows|19-Jan-12| temporarily added includes and getconfig functions
-//  1.8    | M Bellows|12-Jan-12| fixed refresh address, temporarly disabled periodic cal, 
-//         |          |         | fixed unsigned long constants, fixed variable declaration 
-//         |          |         | for calibration registers"
-//  1.7    | D Cadigan| 011012  | Changed periodic cal routine to reflect changes in registers for Centaur1
-//  1.6    | D Cadigan| 12222011| Fixed insert again
-//  1.5    | D Cadigan| 12212011| Fixed insert for buffers, modified dram_freq to temporarily calculate a value based on the method in mss_freq
-//  1.4    | D Cadigan| 12092011| Added header file
-//  1.3    | D Cadigan| 09302011| Moved to FAPI VBU directory
-//  1.2    | D Cadigan| 09282011| Converted to fapi, enhanced procedures to take in some variables.  Still need to debug those functions
-//  1.1    | D Cadigan| 04072011| Initial Copy
-
-//----------------------------------------------------------------------
-//  FAPI Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-//----------------------------------------------------------------------
-//  Centaur function Includes
-//----------------------------------------------------------------------
-#include <mss_funcs.H>
-#include <mss_unmask_errors.H>
-
-//----------------------------------------------------------------------
-//  Address Includes
-//----------------------------------------------------------------------
-#include <cen_scom_addresses.H>
-
-
-extern "C" {
-
-using namespace fapi;
-
-
-//----------------------------------------------------------------------
-//  Subroutine declarations 
-//----------------------------------------------------------------------
-ReturnCode mss_draminit_mc_cloned(Target& i_target);
-ReturnCode mss_start_refresh (Target& i_mbatarget, Target& i_centarget);
-ReturnCode mss_enable_periodic_cal(Target& i_target);
-ReturnCode mss_set_iml_complete(Target& i_target);
-ReturnCode mss_enable_power_management(Target& i_target);
-ReturnCode mss_enable_control_bit_ecc(Target& i_target);
-ReturnCode mss_ccs_mode_reset(Target& i_target);
-ReturnCode mss_check_RCD_protect_time(Target& i_target);
-ReturnCode mss_spare_cke_disable(Target& i_target);
-ReturnCode mss_enable_addr_inversion(Target& i_target);
-
-
-ReturnCode mss_draminit_mc(Target& i_target)
-{
-    // Target is centaur.mba
-    fapi::ReturnCode l_rc;
-   //Commented back in by dcadiga 
-    l_rc = mss_draminit_mc_cloned(i_target);
-    //FAPI_INF("DID NOT RUN DRAMINIT MC\n");
-	// If mss_unmask_maint_errors gets it's own bad rc,
-	// it will commit the passed in rc (if non-zero), and return it's own bad rc.
-	// Else if mss_unmask_maint_errors runs clean,
-	// it will just return the passed in rc.
-	l_rc = mss_unmask_maint_errors(i_target, l_rc);
-
-	return l_rc;
-}
-
-
-
-ReturnCode mss_draminit_mc_cloned(Target& i_target)
-{
-// Target is centaur
-//
-    ReturnCode rc;
-    std::vector<fapi::Target> l_mbaChiplets;
-    uint32_t rc_num  = 0;
-    uint8_t scom_parity_fixed_dd2 = 0;
-    rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_SCOM_PARITY_ERROR_HW244827_FIXED, &i_target, scom_parity_fixed_dd2);
-    if (rc) return rc;
-    // Get associated MBA's on this centaur
-    rc=fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mbaChiplets);
-    if (rc) return rc;
-
-
-
-
-
-    // Step Zero: Turn Off Spare CKE - This needs to be off before IML complete 
-    // STEP COMMENTED FOR SW275629
-    FAPI_INF("+++ Disabling Spare CKE FIX DISABLED +++");
-    //for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
-    //{
-    //   rc = mss_spare_cke_disable(l_mbaChiplets[i]);
-    //   if(rc)
-    //   {
-    //      FAPI_ERR("---Error During Spare CKE Disable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-    //      return rc;
-    //   }
-
-    //}
-
-
-    // Step One: Set IML COMPLETE
-    FAPI_INF( "+++ Setting IML Complete +++");
-    rc = mss_set_iml_complete(i_target);
-    if(rc)
-    {
-       FAPI_ERR("---Error During IML Complete Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-       return rc;
-    }
-    //DD1.X Scom Parity Fix HW244827
-    if(!scom_parity_fixed_dd2)
-    {
-       FAPI_INF("+++DD1.X Centaur, clearing MBS Parity FIR +++");
-       ecmdDataBufferBase parity_tmp_data_buffer_64(64);
-       rc = fapiGetScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64);
-       if(rc) return rc;
-       rc_num = rc_num | parity_tmp_data_buffer_64.clearBit(8);
-       if(rc_num)
-       {
-           rc.setEcmdError(rc_num);
-           return rc;
-       }
-       rc = fapiPutScom(i_target, MBS_FIR_REG_0x02011400, parity_tmp_data_buffer_64);
-       if(rc)
-       {
-          FAPI_ERR("---Error During Clear Parity Bit rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-          return rc;
-       }
-
-    }
-    // Loop through the 2 MBA's
-    for (uint32_t i=0; i < l_mbaChiplets.size(); i++)
-    {
-        
-
-        // Step Two: Disable CCS address lines
-        FAPI_INF( "+++ Disabling CCS Address Lines +++");
-        rc = mss_ccs_mode_reset(l_mbaChiplets[i]);
-        if(rc)
-        {
-           FAPI_ERR("---Error During CCS Mode Reset rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-
-        // Step Two.1: Check RCD protect time on RDIMM and LRDIMM
-        FAPI_INF( "+++ Check RCD protect time on RDIMM and LRDIMM +++");
-        rc = mss_check_RCD_protect_time(l_mbaChiplets[i]);
-        if(rc)
-        {
-           FAPI_ERR("---Error During Check RCD protect time rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-	
-	//Step Two.2: Enable address inversion on each MBA for ALL CARDS
-	FAPI_INF("+++ Setting up adr inversion for port 1 +++");
-	rc = mss_enable_addr_inversion(l_mbaChiplets[i]);
-        if(rc)
-        {
-           FAPI_ERR("---Error During ADR Inversion rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-	
-
-        // Step Three: Enable Refresh
-        FAPI_INF( "+++ Enabling Refresh +++");
-	ecmdDataBufferBase mba01_ref0q_data_buffer_64(64);
-	rc = fapiGetScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
-	if(rc) return rc;
-	//Bit 0 is enable		   
-	rc_num = rc_num | mba01_ref0q_data_buffer_64.setBit(0);
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	rc = fapiPutScom(l_mbaChiplets[i], MBA01_REF0Q_0x03010432, mba01_ref0q_data_buffer_64);
-        if(rc)
-        {
-           FAPI_ERR("---Error During Refresh Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-        // Step Four: Setup Periodic Cals
-        FAPI_INF( "+++ Setting Up Periodic Cals +++");
-        rc = mss_enable_periodic_cal(l_mbaChiplets[i]);
-        if(rc)
-        {
-           FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-        // Step Five: Setup Power Management
-        FAPI_INF( "+++ Setting Up Power Management +++");
-        FAPI_INF( "+++ POWER MANAGEMENT HANDLED AT INITFILE +++");
-        //Procedure commented out because domain reduction enablement now handled at the initfile
-        //rc = mss_enable_power_management(l_mbaChiplets[i]);
-        //if(rc)
-        //{
-        //   FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-        //   return rc;
-        //}
-  
-    }
-
-    // Step Six: Setup Control Bit ECC
-    FAPI_INF( "+++ Setting Up Control Bit ECC +++");
-    rc = mss_enable_control_bit_ecc(i_target);
-    if(rc)
-    {
-        FAPI_ERR("---Error During Control Bit ECC Setup rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-        return rc;
-    }
-
-    return rc;
-}
-
-ReturnCode mss_enable_periodic_cal (Target& i_target)
-{
-    //Target MBA
-
-    //Procedure to setup and enable periodic cals
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0;
-    uint8_t bluewaterfall_broken = 0;
-    uint8_t nwell_misplacement = 0;
-
-    //Find Parent chip for EC check
-    fapi::Target l_target_centaur;
-    rc = fapiGetParentChip(i_target, l_target_centaur);
-    if(rc) return rc;
-
-
- 
-
-    ecmdDataBufferBase data_buffer_64(64);
-
-    uint32_t memcal_iterval; //  00 = Disable
-    rc = FAPI_ATTR_GET(ATTR_EFF_MEMCAL_INTERVAL, &i_target, memcal_iterval);
-    if(rc) return rc;
-    //Determine what type of Centaur this is
-    rc = FAPI_ATTR_GET(ATTR_MSS_BLUEWATERFALL_BROKEN, &l_target_centaur, bluewaterfall_broken);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, nwell_misplacement);
-    if(rc) return rc;
-
-
-
-    if((bluewaterfall_broken == 0) && (nwell_misplacement == 0)){
-       FAPI_INF("+++ Centaur is DD1.1 or later, enabling MEMCAL +++");
-    }
-    else{
-       FAPI_INF("+++ RD Phase Select Workaround, DISABLING MEMCAL VIA HARDCODE +++");
-       memcal_iterval = 0;
-    }
-
-    uint32_t zq_cal_iterval; //  00 = Disable
-    rc = FAPI_ATTR_GET(ATTR_EFF_ZQCAL_INTERVAL, &i_target, zq_cal_iterval);
-    if(rc) return rc;
-
-    
-    rc = fapiGetScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
-    if(rc) return rc;
-
-    FAPI_INF("+++ Enabling Periodic Calibration +++");
-
-    if (zq_cal_iterval != 0)
-    {
-        //ZQ Cal Enabled
-	rc_num = rc_num | data_buffer_64.setBit(0);
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	FAPI_INF("+++ Periodic Calibration: ZQ Cal Enabled +++");
-    }
-    else
-    {
-        //ZQ Cal Disabled
-	rc_num = rc_num | data_buffer_64.clearBit(0);
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	FAPI_INF("+++ Periodic Calibration: ZQ Cal Disabled +++");
-    }
-
-    rc = fapiPutScom(i_target, MBA01_MBA_CAL0Q_0x0301040F, data_buffer_64);
-    if(rc) return rc;
-
-
-    if (memcal_iterval != 0)
-    {
-
-
-
-        uint8_t attr_centaur_ec_rdclk_pr_update_hw236658_fixed; 
-        rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_RDCLK_PR_UPDATE_HW236658_FIXED, &i_target, attr_centaur_ec_rdclk_pr_update_hw236658_fixed);
-        if(rc) return rc;
-
-        if(!attr_centaur_ec_rdclk_pr_update_hw236658_fixed){
-	
-           //Check EC, Disable Phase Select Update for DD2 HW
-           //Phase Select Fix for DD1.1
-           rc_num = rc_num | data_buffer_64.flushTo0();
-           rc_num = rc_num | data_buffer_64.setBit(52);
-           if(rc_num)
-           {
-              rc.setEcmdError(rc_num);
-              return rc;
-           }
-	
-	
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_0_0x800000120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_1_0x800004120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_2_0x800008120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_3_0x80000C120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P0_4_0x800010120301143F,data_buffer_64);
-           if(rc) return rc;
-
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_0_0x800100120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_1_0x800104120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_2_0x800108120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_3_0x80010C120301143F,data_buffer_64);
-           if(rc) return rc;
-           rc = fapiPutScom(i_target,DPHY01_DDRPHY_DP18_RD_DIA_CONFIG5_P1_4_0x800110120301143F,data_buffer_64);
-	
-	
-	}
-	
-	//Disable Periodic Read Centering for ALL HW
-        rc_num = rc_num | data_buffer_64.flushTo0();
-	if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	rc = fapiGetScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F,data_buffer_64);
-        rc_num = rc_num | data_buffer_64.clearBit(54);
-	rc = fapiPutScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F,data_buffer_64);
-
-
-
-        rc_num = rc_num | data_buffer_64.flushTo0();
-	if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	rc = fapiGetScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F,data_buffer_64);
-        rc_num = rc_num | data_buffer_64.clearBit(54);
-	rc = fapiPutScom(i_target,DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P1_0x8001C00B0301143F,data_buffer_64);
-
-        if(rc) return rc;
-
-
-        //Mem Cal Enabled
-        rc_num = rc_num | data_buffer_64.flushTo0();
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-        rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
-        if(rc) return rc;
-	rc_num = rc_num | data_buffer_64.setBit(0);
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	FAPI_INF("+++ Periodic Calibration: Mem Cal Enabled +++");
-    }
-    else
-    {
-        //Mem Cal Disabled
-        rc_num = rc_num | data_buffer_64.flushTo0();
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-        rc = fapiGetScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
-        if(rc) return rc;
-	rc_num = rc_num | data_buffer_64.clearBit(0);
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	FAPI_INF("+++ Periodic Calibration: Mem Cal Disabled +++");
-    }
-    rc = fapiPutScom(i_target, MBA01_MBA_CAL1Q_0x03010410, data_buffer_64);
-    if(rc) return rc;
-    return rc;
-
-}
-
-ReturnCode mss_set_iml_complete (Target& i_target)
-{
-    //Target centaur
-
-    //Set IML Complete
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0; 
-    ecmdDataBufferBase data_buffer_64(64);
-
-    rc = fapiGetScom(i_target, MBSSQ_0x02011417, data_buffer_64);
-    if(rc) return rc;
-
-    rc_num = rc_num | data_buffer_64.setBit(2);
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_set_iml_complete: Error setting up buffers");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, MBSSQ_0x02011417, data_buffer_64);
-    if(rc) return rc;
-
-    FAPI_INF("+++ IML Complete Enabled +++");
-    return rc;
-}
-
-ReturnCode mss_enable_control_bit_ecc (Target& i_target)
-{
-    //Target centaur
-
-    //Enable Control Bit ECC
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0;
-    ecmdDataBufferBase ecc0_data_buffer_64(64);
-    ecmdDataBufferBase ecc1_data_buffer_64(64);
-
-    rc = fapiGetScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64);
-    if(rc) return rc;
-
-    rc = fapiGetScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64);
-    if(rc) return rc;
-
-    // Enable Memory ECC Check/Correct for MBA01
-    // This assumes that all other settings of this register
-    // are set in previous precedures or initfile. 
-    rc_num = rc_num | ecc0_data_buffer_64.clearBit(0);
-    rc_num = rc_num | ecc0_data_buffer_64.clearBit(1);
-    rc_num = rc_num | ecc0_data_buffer_64.setBit(3);
-
-    // Enable Memory ECC Check/Correct for MBA23
-    // This assumes that all other settings of this register
-    // are set in previous precedures or initfile. 
-    rc_num = rc_num | ecc1_data_buffer_64.clearBit(0);
-    rc_num = rc_num | ecc1_data_buffer_64.clearBit(1);
-    rc_num = rc_num | ecc1_data_buffer_64.setBit(3);
-
-    uint8_t attr_centaur_ec_enable_rce_with_other_errors_hw246685; 
-    rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_RCE_WITH_OTHER_ERRORS_HW246685, &i_target, attr_centaur_ec_enable_rce_with_other_errors_hw246685);
-    if(rc) return rc;
-
-    if(attr_centaur_ec_enable_rce_with_other_errors_hw246685) {
-      rc_num = rc_num | ecc0_data_buffer_64.setBit(16);
-      rc_num = rc_num | ecc1_data_buffer_64.setBit(16);
-    }
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_enable_control_bit_ecc: Error setting up buffers");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, MBS_ECC0_MBSECCQ_0x0201144A, ecc0_data_buffer_64);
-    if(rc) return rc;
-
-    rc = fapiPutScom(i_target, MBS_ECC1_MBSECCQ_0x0201148A, ecc1_data_buffer_64);
-    if(rc) return rc;
-
-    FAPI_INF("+++ mss_enable_control_bit_ecc complete +++");
-    return rc;
-}
-
-ReturnCode mss_enable_power_management (Target& i_target)
-{
-    // Target MBA
-    //Enable Power Management
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0;
-    ecmdDataBufferBase pm_data_buffer_64(64);
-
-    rc = fapiGetScom(i_target, MBA01_PM0Q_0x03010434, pm_data_buffer_64);
-    if(rc) return rc;
-
-    // Enable power domain control
-    // This assumes that all other settings of this register
-    // are set in previous precedures or initfile. 
-    rc_num = rc_num | pm_data_buffer_64.setBit(2);
-
-    
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_enable_power_management: Error setting up buffers");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, MBA01_PM0Q_0x03010434, pm_data_buffer_64);
-    if(rc) return rc;
-
-    FAPI_INF("+++ mss_enable_power_management complete +++");
-    return rc;
-}
-
-ReturnCode mss_ccs_mode_reset (Target& i_target)
-{
-
-    //Target MBA
-    //Selects address data from the mainline
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0;
-    ecmdDataBufferBase ccs_mode_data_buffer_64(64);
-
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, ccs_mode_data_buffer_64);
-    if(rc) return rc;
-
-    rc_num = rc_num | ccs_mode_data_buffer_64.clearBit(29);
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_ccs_mode_reset: Error setting up buffers");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, ccs_mode_data_buffer_64);
-    if(rc) return rc;
-
-    FAPI_INF("+++ mss_ccs_mode_reset complete +++");
-    return rc;
-}
-
-
-ReturnCode mss_check_RCD_protect_time (Target& i_target)
-{
-
-    // Target MBA
-    
-    uint32_t l_ecmd_rc = 0; 
-    fapi::ReturnCode l_rc;
-    fapi::Target l_targetCentaur;
-    uint8_t l_mbaPosition = 0;    
-    uint8_t l_dimm_type = 0;
-    uint8_t l_cfg_wrdone_dly = 0;
-    uint8_t l_cfg_rdtag_dly = 0;
-    uint8_t l_cfg_rcd_protection_time = 0;
-    uint8_t l_highest_cfg_rcd_protection_time = 0;
-    uint8_t l_max_cfg_rcd_protection_time = 0;
-    uint8_t l_cmdType = 0x10; // DISPLAY, bit 0:5 = 10000b 
-    uint8_t l_valid_dimms  = 0;
-    uint8_t l_valid_dimm[2][2];
-    uint8_t l_port=0;
-    uint8_t l_dimm=0;
-    uint8_t l_dimm_index = 0;
-
-    std::vector<fapi::Target> l_target_dimm_array;
-    uint8_t l_target_port = 0;
-    uint8_t l_target_dimm = 0;
-
-    // 1 ms delay for HW mode
-    const uint64_t  HW_MODE_DELAY = 1000000;
-    
-    // 200000 sim cycle delay for SIM mode
-    const uint64_t  SIM_MODE_DELAY = 200000;
-
-    uint32_t l_mbeccfir_mask_or_address[2]={
-    // port0/1                            port2/3
-    MBS_ECC0_MBECCFIR_MASK_OR_0x02011445, MBS_ECC1_MBECCFIR_MASK_OR_0x02011485};
-
-    uint32_t l_mbeccfir_and_address[2]={
-    // port0/1                            port2/3
-    MBS_ECC0_MBECCFIR_AND_0x02011441,  MBS_ECC0_MBECCFIR_AND_0x02011481};
-    
-    uint32_t l_mbeccfir_address[2]={
-    // port0/1                            port2/3
-    MBS_ECC0_MBECCFIR_0x02011440, MBS_ECC1_MBECCFIR_0x02011480};
-      
-    ecmdDataBufferBase l_mbeccfir_mask_or(64);  
-    ecmdDataBufferBase l_mbeccfir_and(64);
-    ecmdDataBufferBase l_mbeccfir(64);
-    ecmdDataBufferBase l_mbacalfir_mask_or(64);
-    ecmdDataBufferBase l_mbacalfir_mask_and(64);
-    ecmdDataBufferBase l_mbacalfir_and(64);    
-    ecmdDataBufferBase l_mbacalfir(64);        
-    ecmdDataBufferBase l_mba_dsm0(64);    
-    ecmdDataBufferBase l_mba_farb0(64);    
-    ecmdDataBufferBase l_mbmct(64);    
-    ecmdDataBufferBase l_mbmaca(64);    
-    ecmdDataBufferBase l_mbasctl(64);
-    ecmdDataBufferBase l_mbmcc(64);
-    ecmdDataBufferBase l_mbafir(64);    
-    ecmdDataBufferBase l_mbmsr(64);
-
-    //------------------------------------------------------    
-    // Get DIMM type        
-    //------------------------------------------------------        
-    l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_dimm_type);
-    if(l_rc)
-    {
-        FAPI_ERR("Error getting ATTR_EFF_DIMM_TYPE on %s.",i_target.toEcmdString());
-        return l_rc;
-    }
-    
-    //------------------------------------------------------            
-    // Only run on RDIMM or LRDIMM
-    //------------------------------------------------------            
-    if ((l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM)||(l_dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM))
-    {
-        //------------------------------------------------------
-        // Exit if parity error reporting disabled
-        //------------------------------------------------------
-        // NOTE: This is just to be safe, so we don't create errors in case the initfile is out of sync.
-        // Read FARB0
-        l_rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0);
-        if(l_rc) return l_rc;
-        
-        if(l_mba_farb0.isBitSet(60))
-        {
-            FAPI_ERR("Exit mss_check_RCD_protect_time, since parity error reporting disabled on %s.",i_target.toEcmdString());
-            return l_rc;
-        }
-
-        //------------------------------------------------------    
-        // Get Centaur target for the given MBA
-        //------------------------------------------------------
-        l_rc = fapiGetParentChip(i_target, l_targetCentaur);
-        if(l_rc)
-        {
-            FAPI_ERR("Error getting Centaur parent target for the given MBA on %s.",i_target.toEcmdString());
-            return l_rc;
-        }        
-
-        //------------------------------------------------------
-        // Get MBA position: 0 = mba01, 1 = mba23
-        //------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbaPosition);
-        if(l_rc)
-        {
-            FAPI_ERR("Error getting MBA position on %s.",i_target.toEcmdString());
-            return l_rc;
-        } 
-
-        //------------------------------------------------------
-        // Find out which DIMMs are functional
-        //------------------------------------------------------
-        l_rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, l_valid_dimms);
-        if (l_rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR on %s.",i_target.toEcmdString());
-            return l_rc;
-        }
-        l_valid_dimm[0][0] = (l_valid_dimms & 0x80); // port0, dimm0
-        l_valid_dimm[0][1] = (l_valid_dimms & 0x40); // port0, dimm1
-        l_valid_dimm[1][0] = (l_valid_dimms & 0x08); // port1, dimm0
-        l_valid_dimm[1][1] = (l_valid_dimms & 0x04); // port1, dimm1
-
-
-        //------------------------------------------------------ 
-        // Mask MBECCFIR bit 45: maint RCD parity error
-        //------------------------------------------------------    
-        l_ecmd_rc |= l_mbeccfir_mask_or.flushTo0();
-        // Set bit 45 in the OR mask
-        l_ecmd_rc |= l_mbeccfir_mask_or.setBit(45);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        // Write OR mask
-        l_rc = fapiPutScom(l_targetCentaur, l_mbeccfir_mask_or_address[l_mbaPosition], l_mbeccfir_mask_or); 
-        if(l_rc) return l_rc;
-
-
-        //------------------------------------------------------ 
-        // Mask MBACALFIR bits 4,7: port0,1 RCD parity error
-        //------------------------------------------------------    
-        l_ecmd_rc |= l_mbacalfir_mask_or.flushTo0();
-        // Set bit 4,7 in the OR mask
-        l_ecmd_rc |= l_mbacalfir_mask_or.setBit(4);
-        l_ecmd_rc |= l_mbacalfir_mask_or.setBit(7);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        // Write OR mask
-        l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_MASK_OR_0x03010405, l_mbacalfir_mask_or); 
-        if(l_rc) return l_rc;
-
-
-        //------------------------------------------------------ 
-        // Find l_max_cfg_rcd_protection_time
-        //------------------------------------------------------    
-        l_rc = fapiGetScom(i_target, MBA01_MBA_DSM0_0x0301040a, l_mba_dsm0);
-        if(l_rc) return l_rc;
-        // Get 24:29 cfg_wrdone_dly
-        l_ecmd_rc |= l_mba_dsm0.extractPreserve(&l_cfg_wrdone_dly, 24, 6, 8-6);
-        // Get 36:41 cfg_rdtag_dly
-        l_ecmd_rc |= l_mba_dsm0.extractPreserve(&l_cfg_rdtag_dly, 36, 6, 8-6);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-
-        // Pick lower of the two: cfg_wrdone_dly and cfg_rdtag_dly, and use that for l_max_cfg_rcd_protection_time
-        if (l_cfg_wrdone_dly <= l_cfg_rdtag_dly)
-        {
-            l_max_cfg_rcd_protection_time = l_cfg_wrdone_dly;
-        }
-        else
-        {
-            l_max_cfg_rcd_protection_time = l_cfg_rdtag_dly;
-        }                       
-        
-        //------------------------------------------------------ 
-        // Maint cmd setup steps we can do once per MBA
-        //------------------------------------------------------    
-
-        // Load display cmd type: MBMCT, 0:5 = 10000b      
-        l_rc = fapiGetScom(i_target, MBA01_MBMCTQ_0x0301060A, l_mbmct);
-        if(l_rc) return l_rc;        
-        l_ecmd_rc |= l_mbmct.insert(l_cmdType, 0, 5, 8-5 );
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        l_rc = fapiPutScom(i_target, MBA01_MBMCTQ_0x0301060A, l_mbmct);
-        if(l_rc) return l_rc;
-
-        // Clear all stop conditions in MBASCTL        
-        l_rc = fapiGetScom(i_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctl);
-        if(l_rc) return l_rc;
-        l_ecmd_rc |= l_mbasctl.clearBit(0,13);
-        l_ecmd_rc |= l_mbasctl.clearBit(16);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        l_rc = fapiPutScom(i_target, MBA01_MBASCTLQ_0x0301060F, l_mbasctl);
-        if(l_rc) return l_rc;
-
-
-        //------------------------------------------------------
-        // For each port in the given MBA:0,1
-        //------------------------------------------------------
-        for(l_port=0; l_port<2; l_port++ )
-        {
-            //------------------------------------------------------
-            // For each DIMM select on the given port:0,1
-            //------------------------------------------------------            
-            for(l_dimm=0; l_dimm<2; l_dimm++ )
-            {
-                //------------------------------------------------------
-                // If DIMM valid
-                //------------------------------------------------------            
-                if (l_valid_dimm[l_port][l_dimm])
-                {
-                    //------------------------------------------------------ 
-                    // Start with cfg_rcd_protection_time of 8
-                    //------------------------------------------------------                     
-                    l_cfg_rcd_protection_time = 8;
-
-                    //------------------------------------------------------ 
-                    // Clear MBECCFIR bit 45: maint RCD parity error
-                    //------------------------------------------------------    
-                    l_ecmd_rc |= l_mbeccfir_and.flushTo1();
-                    // Clear bit 45 in the AND mask
-                    l_ecmd_rc |= l_mbeccfir_and.clearBit(45);
-                    if(l_ecmd_rc)
-                    {
-                        l_rc.setEcmdError(l_ecmd_rc);
-                        return l_rc;
-                    }
-                    // Write AND mask
-                    l_rc = fapiPutScom(l_targetCentaur, l_mbeccfir_and_address[l_mbaPosition], l_mbeccfir_and); 
-                    if(l_rc) return l_rc;
-
-                    //------------------------------------------------------ 
-                    // Loop until we find a passing cfg_rcd_protection_time
-                    //------------------------------------------------------    
-                    do
-                    {
-                        //------------------------------------------------------ 
-                        // Clear MBACALFIR bits 4,7: port0,1 RCD parity error
-                        //------------------------------------------------------
-                        // NOTE: Clearing these each time so they will be accrate for FFDC
-                        l_ecmd_rc |= l_mbacalfir_and.flushTo1();
-                        // Clear bit 4,7 in the AND mask
-                        l_ecmd_rc |= l_mbacalfir_and.clearBit(4);
-                        l_ecmd_rc |= l_mbacalfir_and.clearBit(7);
-                        if(l_ecmd_rc)
-                        {
-                            l_rc.setEcmdError(l_ecmd_rc);
-                            return l_rc;
-                        }
-                        // Write AND mask
-                        l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_AND_0x03010401, l_mbacalfir_and); 
-                        if(l_rc) return l_rc;
-
-
-                        //------------------------------------------------------ 
-                        // Set l_cfg_rcd_protection_time
-                        //------------------------------------------------------                            
-                        // Read FARB0
-                        l_rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0);
-                        if(l_rc) return l_rc;
-                        
-                        // Set cfg_rcd_protection_time
-                        l_ecmd_rc |= l_mba_farb0.insert( l_cfg_rcd_protection_time, 48, 6, 8-6 );
-                                
-
-                        //------------------------------------------------------ 
-                        // Arm single shot RCD parity error for the given port
-                        //------------------------------------------------------                            
-                        // Select single shot
-                        l_ecmd_rc |= l_mba_farb0.clearBit(59);                                
-                        if(l_port == 0)
-                        {
-                            // Select port0 CAS
-                            l_ecmd_rc |= l_mba_farb0.setBit(40);
-                        }
-                        else
-                        {
-                            // Select port1 CAS
-                            l_ecmd_rc |= l_mba_farb0.setBit(42);
-                        }                                
-                        if(l_ecmd_rc)
-                        {
-                            l_rc.setEcmdError(l_ecmd_rc);
-                            return l_rc;
-                        }
-                        // Write FARB0
-                        l_rc = fapiPutScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0);
-                        if(l_rc) return l_rc;
-
-
-                        //------------------------------------------------------ 
-                        // Do single address display cmd
-                        //------------------------------------------------------    
-
-                        // Load start address in MBMACA for the given DIMM
-                        l_ecmd_rc |= l_mbmaca.flushTo0();                      
-                        if(l_dimm == 1)
-                        {
-                            l_ecmd_rc |= l_mbmaca.setBit(1);
-                        }
-                        
-                        if(l_ecmd_rc)
-                        {
-                            l_rc.setEcmdError(l_ecmd_rc);
-                            return l_rc;
-                        }                        
-                        l_rc = fapiPutScom(i_target, MBA01_MBMACAQ_0x0301060D, l_mbmaca);
-                        if(l_rc) return l_rc;
-                        
-                        // Start the command: MBMCCQ
-                        l_ecmd_rc |= l_mbmcc.flushTo0();        
-                        l_ecmd_rc |= l_mbmcc.setBit(0);
-                        if(l_ecmd_rc)
-                        {
-                            l_rc.setEcmdError(l_ecmd_rc);
-                            return l_rc;
-                        }
-                        l_rc = fapiPutScom(i_target, MBA01_MBMCCQ_0x0301060B, l_mbmcc);
-                        if(l_rc) return l_rc;        
-
-                        // Check for MBAFIR[1], invalid maint address.
-                        l_rc = fapiGetScom(i_target, MBA01_MBAFIRQ_0x03010600, l_mbafir);
-                        if(l_rc) return l_rc;
-                        
-                        if (l_mbafir.isBitSet(1))
-                        {
-                            FAPI_ERR("Display invalid address = 0x%.8X 0x%.8X, on port%d, dimm%d, %s.",
-                            l_mbmaca.getWord(0), l_mbmaca.getWord(1), l_port, l_dimm, i_target.toEcmdString());
-
-                            // Calling out FW high
-                            // FFDC: MBA target
-                            const fapi::Target & MBA = i_target;
-                            // FFDC: Capture invalid address
-                            ecmdDataBufferBase & MBMACA = l_mbmaca;
-                            // FFDC: Capture FIR
-                            ecmdDataBufferBase & MBAFIR = l_mbafir;
-                            // Create new log
-                            FAPI_SET_HWP_ERROR(l_rc, RC_MSS_DRAMINIT_MC_DISPLAY_INVALID_ADDR);
-                            
-                            return l_rc;                            
-                        }
-
-                        // Delay 1 mSec
-                        fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY);
-
-                        // See if MBMSRQ[0] maint cmd in progress bit if off
-                        l_rc = fapiGetScom(i_target, MBA01_MBMSRQ_0x0301060C, l_mbmsr);
-                        if(l_rc) return l_rc;
-
-                        // If cmd still in progress
-                        if (l_mbmsr.isBitSet(1))
-                        {
-                            FAPI_ERR("Display timeout on %s.",i_target.toEcmdString());
-
-                            // Calling out FW high
-                            // Calling out MBA target low, deconfig, gard
-                            const fapi::Target & MBA = i_target;
-                            // FFDC: Capture cmd type
-                            ecmdDataBufferBase & MBMCT = l_mbmct;
-                            // FFDC: Capture address
-                            ecmdDataBufferBase & MBMACA = l_mbmaca;
-                            // FFDC: Capture stop conditions
-                            ecmdDataBufferBase & MBASCTL = l_mbasctl;
-                            // FFDC: Capture stop/start control reg
-                            ecmdDataBufferBase & MBMCC = l_mbmcc;
-                            // FFDC: Capture Capture cmd in progress reg
-                            ecmdDataBufferBase & MBMSR = l_mbmsr;
-                            // FFDC: Capture FIR
-                            ecmdDataBufferBase & MBAFIR = l_mbafir;
-                            // Create new log
-                            FAPI_SET_HWP_ERROR(l_rc, RC_MSS_DRAMINIT_MC_DISPLAY_TIMEOUT);
-                            
-                            return l_rc;
-                        }
-                    
-
-                        //------------------------------------------------------ 
-                        // Check for MBECCFIR bit 45: maint RCD parity error
-                        //------------------------------------------------------    
-
-                        l_rc = fapiGetScom(l_targetCentaur, l_mbeccfir_address[l_mbaPosition], l_mbeccfir); 
-                        if(l_rc) return l_rc;
-
-                        // If FIR bit set
-                        if (l_mbeccfir.isBitSet(45))
-                        {                            
-                            // Save highest value seen on this MBA
-                            if (l_cfg_rcd_protection_time > l_highest_cfg_rcd_protection_time)
-                            {
-                                l_highest_cfg_rcd_protection_time = l_cfg_rcd_protection_time;
-                            }
-                            
-                            break; // Exit do-while loop and move on to another DIMM
-                        }
-                        
-                        // Else FIR not set
-                        else
-                        {                        
-                            // Reached max_cfg_rcd_protection_time
-                            if (l_cfg_rcd_protection_time == l_max_cfg_rcd_protection_time)
-                            {
-                                FAPI_ERR("Injected RCD parity error detected too late for RCD retry to be effective, max_cfg_rcd_protection_time=%d, port%d, dimm%d, %s",
-                                 l_max_cfg_rcd_protection_time, l_port, l_dimm, i_target.toEcmdString());
-
-
-                                //Read mbacalfir for FFDC                               
-                                l_rc = fapiGetScom(i_target, MBA01_MBACALFIR_0x03010400, l_mbacalfir);
-                                if(l_rc) return l_rc;
-
-                                // Get DIMM targets for this MBA
-                                l_rc = fapiGetAssociatedDimms(i_target, l_target_dimm_array);
-                                if (l_rc)
-                                {
-                                    FAPI_ERR("Failed to get associated DIMMs on %s.",i_target.toEcmdString());
-                                    return l_rc;
-                                }
-                                
-                                // Find DIMM target for this l_port and l_dimm
-                                for (l_dimm_index = 0; l_dimm_index < l_target_dimm_array.size(); l_dimm_index ++)
-                                {
-                                    l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[l_dimm_index], l_target_port);
-                                    if (l_rc)
-                                    {
-                                        FAPI_ERR("Failed to get ATTR_MBA_PORT on %s.",i_target.toEcmdString());
-                                        return l_rc;
-                                    }
-
-                                    l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[l_dimm_index], l_target_dimm);
-                                    if (l_rc)
-                                    {
-                                        FAPI_ERR("Failed to get ATTR_MBA_DIMM on %s.",i_target.toEcmdString());
-                                        return l_rc;
-                                    }
-                                    
-                                    if ((l_target_port == l_port) && (l_target_dimm == l_dimm))
-                                    {
-                                        break; // Break out of for loop since we found the DIMM target for this l_port and l_dimm
-                                    }
-                                }
-
-
-                                // Calling out DIMM high, deconfig, gard                                
-                                const fapi::Target & DIMM = l_target_dimm_array[l_dimm_index];
-                                // Calling out MBA target low, deconfig, gard
-                                const fapi::Target & MBA = i_target;
-                                // FFDC: PORT select: 0,1
-                                uint8_t PORT_SELECT = l_port;
-                                // FFDC: DIMM select: 0,1
-                                uint8_t DIMM_SELECT = l_dimm;
-                                // FFDC: MBS has to be told about RCD parity error before cfg_wrdone_dly so it knows to retry writes
-                                uint8_t CFG_WRDONE_DLY = l_cfg_wrdone_dly;
-                                // FFDC: MBS has to be told about RCD parity error before cfg_rdtag_dly so it knows to retry reads                                
-                                uint8_t CFG_RDTAG_DLY = l_cfg_rdtag_dly;
-                                // FFDC: Injected RCD parity error not detected within detected max_cfg_rcd_protection_time, so RCD retry not effective
-                                uint8_t MAX_CFG_RCD_PROTECTION_TIME = l_max_cfg_rcd_protection_time;                                
-                                // FFDC: Capture register with the RCD retry settings
-                                ecmdDataBufferBase & MBA_FARB0 = l_mba_farb0;
-                                // FFDC: Capture MBACALFIR to see if at least the MBA detected the injected RCD parity error
-                                ecmdDataBufferBase & MBACALFIR = l_mbacalfir;
-                                // Create new log
-                                FAPI_SET_HWP_ERROR(l_rc, RC_MSS_DRAMINIT_MC_INSUF_RCD_PROTECT_TIME);
-                                // 'Commit' the log so we can keep running
-                                fapiLogError(l_rc);
-                                                                                                                               
-                                break; // Exit do-while loop and move on to another DIMM
-                            }
-                            
-                            // Else increment cfg_rcd_protection_time and try again
-                            else
-                            {                           
-                                l_cfg_rcd_protection_time++;                        
-                            }                        
-                        }
-                    }
-                    while (1);
-                    
-                }// End if valid DIMM
-            }// End for each DIMM select
-        }// End for each port                                                
-
-
-        //------------------------------------------------------ 
-        // Clear MBECCFIR bit 45
-        //------------------------------------------------------    
-        l_ecmd_rc |= l_mbeccfir_and.flushTo1();
-        // Clear bit 45 in the AND mask
-        l_ecmd_rc |= l_mbeccfir_and.clearBit(45);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        // Write AND mask
-        l_rc = fapiPutScom(l_targetCentaur, l_mbeccfir_and_address[l_mbaPosition], l_mbeccfir_and); 
-        if(l_rc) return l_rc;
-
-
-        //------------------------------------------------------ 
-        // Clear MBACALFIR bits 4,7: port0,1 RCD parity error
-        //------------------------------------------------------    
-        l_ecmd_rc |= l_mbacalfir_and.flushTo1();
-        // Clear bit 4,7 in the AND mask
-        l_ecmd_rc |= l_mbacalfir_and.clearBit(4);
-        l_ecmd_rc |= l_mbacalfir_and.clearBit(7);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        // Write AND mask
-        l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_AND_0x03010401, l_mbacalfir_and); 
-        if(l_rc) return l_rc;
-
-
-        //------------------------------------------------------ 
-        // Unmask MBACALFIR bits 4,7: port0,1 RCD parity error
-        //------------------------------------------------------    
-        l_ecmd_rc |= l_mbacalfir_mask_and.flushTo1();
-        // Set bit 4,7 in the AND mask
-        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(4);
-        l_ecmd_rc |= l_mbacalfir_mask_and.clearBit(7);
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        // Write AND mask
-        l_rc = fapiPutScom(i_target, MBA01_MBACALFIR_MASK_AND_0x03010404, l_mbacalfir_mask_and); 
-        if(l_rc) return l_rc;
-
-
-        //------------------------------------------------------ 
-        // Load l_highest_cfg_rcd_protection_time
-        //------------------------------------------------------    
-        // NOTE: We are loading highest_cfg_rcd_protection_time here just so we can stop after mss_draminit_mc and read out the values from the hw as a way to debug
-        // NOTE: The final value we want to load is max_cfg_rcd_protection_time, which we will do in mss_thermal_init, before we enable RCD recovery.
-        // NOTE: If no DIMM on this MBA passed, highest_cfg_rcd_protection_time will be 0
-        
-        // Read FARB0
-        l_rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0);
-        if(l_rc) return l_rc;        
-        // Set highest_cfg_rcd_protection_time
-        l_ecmd_rc |= l_mba_farb0.insert( l_highest_cfg_rcd_protection_time, 48, 6, 8-6 );
-        if(l_ecmd_rc)
-        {
-            l_rc.setEcmdError(l_ecmd_rc);
-            return l_rc;
-        }
-        // Write FARB0
-        l_rc = fapiPutScom(i_target, MBA01_MBA_FARB0Q_0x03010413, l_mba_farb0);
-        if(l_rc) return l_rc;
-
-        
-    } // End if RDIMM or LRDIMM
-
-
-
-    FAPI_INF("+++ mss_check_RCD_protect_time complete +++");
-    return l_rc;
-}
-
-
-ReturnCode mss_spare_cke_disable (Target& i_target)
-{
-
-    //Target MBA
-    //Selects address data from the mainline
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0;
-    ecmdDataBufferBase spare_cke_data_buffer_64(64);
-
-    //Setup SPARE CKE enable bit
-    rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, spare_cke_data_buffer_64);
-    if(rc) return rc;
-    rc_num = rc_num | spare_cke_data_buffer_64.clearBit(42);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, spare_cke_data_buffer_64);
-    if(rc) return rc;
-
-
-    FAPI_INF("+++ mss_spare_cke_disable complete +++");
-    return rc;
-}
-
-ReturnCode mss_enable_addr_inversion (Target& i_target)
-{
-
-    //Target MBA
-    //Sets address inversion on port 1 of an MBA
-    //Variables
-    ReturnCode rc;
-    uint32_t rc_num  = 0;
-    ecmdDataBufferBase MBA_FARB0_DB_64(64);
-
-    //Set bit 56 for adr inversion on port 1
-    rc = fapiGetScom(i_target, MBA01_MBA_FARB0Q_0x03010413, MBA_FARB0_DB_64);
-    if(rc) return rc;
-    rc_num = rc_num | MBA_FARB0_DB_64.setBit(56);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, MBA01_MBA_FARB0Q_0x03010413, MBA_FARB0_DB_64);
-    if(rc) return rc;
-
-
-    FAPI_INF("+++ mss_enable_addr_inversion complete +++");
-    return rc;
-}
-
-
-
-} //end extern C
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
deleted file mode 100644
index f772beb7d..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
+++ /dev/null
@@ -1,58 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_mc.H,v 1.5 2012/07/17 13:22:39 bellows Exp $
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|   Date:  | Author:  | Comment:
-//---------|----------|----------|-----------------------------------------------
-//  1.5    | 07/16/12 | bellows  | added in Id tag
-//  1.4    | 03/07/12 | jdsloat  | changed target to centaur
-//  1.3    | 02/17/12 | jdsloat  | Added the other &
-//  1.1    | 02/02/12 | jdsloat  | Added & and description of target type
-//  1.0    | 12/08/11 | dcadiga  | First draft.
-
-#ifndef mss_draminit_mc_H_
-#define mss_draminit_mc_H_
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_draminit_mc_FP_t)(const fapi::Target& target);
-
-extern "C"
-{
-
-/**
- * @brief Draminit MC procedure. Enable MC functions and set IML complete within centaur
- *
- * @param[in]  i_target  Reference to centaur target
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode mss_draminit_mc(const fapi::Target& target);
-
-} // extern "C"
-
-#endif // mss_draminit_mc_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
deleted file mode 100644
index d5c18550e..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C
+++ /dev/null
@@ -1,4430 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_access_delay_reg.C,v 1.25 2014/04/18 19:23:36 jdsloat Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_access_delay_reg
-// *! OWNER NAME  : Saurabh Chadha     Email: sauchadh@in.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure is to give different phase rototor values like RD_DQ, RD_DQS, WR_DQ, WR_DQS 
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.1   | sauchadh |15-Oct-12| First Draft.
-//   1.2   | sauchadh |29-Oct-12| Fixed Firmware comments
-//   1.3   | sauchadh |29-Oct-12| Fixed error due to rc_num
-//   1.4   | sauchadh |29-Oct-12| Fixed error due to rc
-//   1.5   | sauchadh |6-Nov-12 | Added RAW modes
-//   1.6   | sauchadh |20-Nov-12| Made index to follow ISDIMM net for DQS and added glacier 2 suppport
-//   1.7   | sauchadh |30-Nov-12| Glacier 1 and 2 selected based on init file settings
-//   1.8   | sauchadh |5-Dec-12 | Fixed firmware comments and added DQS align DQS gate
-//   1.9   | sauchadh |14-Dec-12| Fixed Firmware comments
-//   1.10  | sauchadh |14-Dec-12| Fixed Firmware comments
-//   1.11  | sauchadh |18-Dec-12| Fixed Frimware comments and removed print statements in between
-//   1.12  | sauchadh |18-Dec-12| Added support for unused DQS in x8 mode
-//   1.13  | sauchadh |7-Jan-12 | Added DQSCLK and RDCLK in phase select register
-//   1.14  | sauchadh |8-Jan-12 | Fixed Firmware comments
-//   1.15  | sauchadh |20-may-13| Fixed swizzle issue in DQSCLK phase rotators
-//   1.16  | sauchadh |12-jun-13| ADDED	 CAC registers for read dqs
-//   1.17  | sauchadh |18-Jul-13| Added data bit disable registers
-//   1.19  | abhijsau |9-Oct-13 | Added mss_c4_phy() function 
-//   1.21  | abhijsau |16-Dec-13| Added function for fw
-//   1.22  |sauchadh  |10-Jan-14| changed dimmtype attribute to ATTR_EFF_CUSTOM_DIMM
-//   1.23  | mjjones  |17-Jan-14| Fixed layout and error handling for RAS Review
-//   1.24  |sauchadh  |24-Jan-14| Added check for unused DQS 
-//   1.25  |sauchadh  |18-Apr-14| SW257010: mss_c4_phy: initialized dqs_lane array and verbose flag, used array indexes rather than counter
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-#include <mss_access_delay_reg.H>
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-extern "C" {
-
-//******************************************************************************
-//Function name: mss_access_delay_reg()
-//Description:This function Read and Write delay values for RD_DQ, WR_DQ, RD_DQS, WR_DQS
-//RD_DQ  - Read Delay (DQ) registers
-//WR_DQ  - Write delay (DQ) registers
-//RD_DQS - DQS_CLK_ALIGN
-//WR_DQS - Write delay (DQS)registers
-//Input  : Target MBA=i_target_mba, i_access_type_e = READ or WRITE, i_port_u8=0 or 1, i_rank_u8=valid ranks,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS or RAW_modes, i_input_index_u8=follow ISDIMMnet/C4 for non raw modes and supports raw modes, i_verbose-extra print statements   
-//Output : delay value=io_value_u32 if i_access_type_e = READ else if i_access_type_e = WRITE no return value
-//******************************************************************************
-fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba,
-                                      access_type_t i_access_type_e,
-                                      uint8_t i_port_u8,
-                                      uint8_t i_rank_u8,
-                                      input_type_t i_input_type_e,
-                                      uint8_t i_input_index_u8,
-                                      uint8_t i_verbose,
-                                      uint32_t &io_value_u32)
-{
-   // Reference variables for Error FFDC
-   const fapi::Target & MBA_TARGET = i_target_mba;
-   const access_type_t & ACCESS_TYPE_PARAM = i_access_type_e;
-   const uint8_t & PORT_PARAM = i_port_u8;
-   const uint8_t & RANK_PARAM = i_rank_u8;
-   const input_type_t & TYPE_PARAM = i_input_type_e;
-   const uint8_t & INDEX_PARAM = i_input_index_u8;
-
-   fapi::ReturnCode rc; 
-    
-   const uint8_t max_rp=8; 
-   uint8_t l_val=0;
-   uint8_t l_dram_width=0;
-   scom_location l_out;
-   uint64_t l_scom_add=0x0ull;
-   uint32_t l_sbit=0;
-   uint32_t l_len=0;
-   uint32_t rc_num=0;
-   ecmdDataBufferBase data_buffer_64(64);
-   ecmdDataBufferBase out(16);
-   uint32_t l_output=0;
-   uint32_t l_start=0;
-   uint8_t l_rank_pair=9;
-   uint8_t l_rankpair_table[max_rp]={255};
-   uint8_t l_dimmtype=0;
-   uint8_t l_block=0;
-   uint8_t l_lane=0;
-   uint8_t l_start_bit=0;
-   uint8_t l_len8=0;
-   input_type l_type;
-   uint8_t l_mbapos=0;
-   const uint8_t l_ISDIMM_dqmax=71;
-   const uint8_t l_CDIMM_dqmax=79;
-   uint8_t l_adr=0;
-    const uint8_t addr_max=19;
-   const uint8_t cmd_max=3;
-   const uint8_t cnt_max=20;
-   const uint8_t clk_max=8;
-   const uint8_t addr_lanep0[addr_max]={1,5,3,7,10,6,4,10,13,12,9,9,0,0,6,4,1,4,8};
-   const uint8_t addr_adrp0[addr_max]={2,1,1,3,1,3,1,3,3,3,2,3,2,3,1,0,3,3,3};
-   const uint8_t addr_lanep1[addr_max]={7,10,3,6,8,12,6,1,5,8,2,0,13,4,5,9,6,11,9};
-   const uint8_t addr_adrp1[addr_max]={2,1,2,2,1,3,1,1,1,3,1,3,2,3,3,0,0,1,3};
-   const uint8_t addr_lanep2[addr_max]={8,0,7,1,12,10,1,5,9,5,13,5,4,2,4,9,10,9,0};
-   const uint8_t addr_adrp2[addr_max]={2,2,3,0,3,1,2,0,1,3,2,1,0,2,3,3,3,2,1};
-   const uint8_t addr_lanep3[addr_max]={6,2,9,9,2,3,4,10,0,5,1,5,4,1,8,11,5,12,1};
-   const uint8_t addr_adrp3[addr_max]={3,0,2,3,2,0,3,3,1,2,2,1,0,1,3,3,0,3,0};
-   
-   const uint8_t cmd_lanep0[cmd_max]={2,11,5};
-   const uint8_t cmd_adrp0[cmd_max]={3,1,3};
-   const uint8_t cmd_lanep1[cmd_max]={2,10,10};
-   const uint8_t cmd_adrp1[cmd_max]={2,3,2};
-   const uint8_t cmd_lanep2[cmd_max]={3,11,3};
-   const uint8_t cmd_adrp2[cmd_max]={1,3,0};
-   const uint8_t cmd_lanep3[cmd_max]={7,10,7};
-   const uint8_t cmd_adrp3[cmd_max]={1,1,3};
-   
-   const uint8_t cnt_lanep0[cnt_max]={0,7,3,1,7,8,8,3,8,6,7,2,2,0,9,1,3,6,9,2};
-   const uint8_t cnt_adrp0[cnt_max]={1,0,3,0,2,2,1,2,0,0,1,2,0,0,1,1,0,2,0,1};
-   const uint8_t cnt_lanep1[cnt_max]={5,4,0,5,11,9,10,7,1,11,0,4,12,3,6,8,1,4,7,7};
-   const uint8_t cnt_adrp1[cnt_max]={2,1,2,0,2,1,0,1,3,0,1,0,2,1,3,0,2,2,3,0};
-   const uint8_t cnt_lanep2[cnt_max]={0,4,7,13,11,5,12,2,3,6,11,6,7,1,10,8,8,2,4,1};
-   const uint8_t cnt_adrp2[cnt_max]={0,1,1,3,1,2,2,0,2,2,0,1,2,1,0,3,1,1,2,3};
-   const uint8_t cnt_lanep3[cnt_max]={0,11,9,8,4,7,0,3,8,6,13,8,7,0,6,6,1,2,9,5};
-   const uint8_t cnt_adrp3[cnt_max]={2,1,0,2,1,0,3,2,0,1,3,1,2,0,0,2,3,1,1,3};
-   
-   const uint8_t clk_lanep0[clk_max]={10,11,11,10,4,5,13,12};
-   const uint8_t clk_adrp0[clk_max]={0,0,2,2,2,2,2,2};
-   const uint8_t clk_lanep1[clk_max]={3,2,8,9,1,0,3,2};
-   const uint8_t clk_adrp1[clk_max]={3,3,2,2,0,0,0,0};
-   const uint8_t clk_lanep2[clk_max]={11,10,6,7,2,3,8,9};
-   const uint8_t clk_adrp2[clk_max]={2,2,0,0,3,3,0,0};
-   const uint8_t clk_lanep3[clk_max]={3,2,13,12,10,11,11,10};
-   const uint8_t clk_adrp3[clk_max]={3,3,2,2,0,0,2,2};
-   
-   
-   rc = mss_getrankpair(i_target_mba,i_port_u8,i_rank_u8,&l_rank_pair,l_rankpair_table);   if(rc) return rc;
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc;
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos);  if(rc) return rc;
-   
-   if(i_verbose==1)
-   {
-      FAPI_INF("dimm type=%d",l_dimmtype);
-      FAPI_INF("rank pair=%d",l_rank_pair);       
-   }
-   if(i_port_u8 >1)
-   {
-      FAPI_ERR("Wrong port specified (%d)", i_port_u8);
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-      return rc;
-   }
-
-   if (l_mbapos>1)
-   {
-       FAPI_ERR("Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos);
-       const uint8_t & MBA_POS = l_mbapos;
-       FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_BAD_MBA_POS);
-       return rc;
-   }
-
-   if((l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) || (l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8))   // Checking for dram width here so that checking can be skipped in called function
-   {
-      if(i_verbose==1)
-      {
-         FAPI_INF("dram width=%d",l_dram_width);
-      }
-   }
-   else
-   {
-      FAPI_ERR("Bad dram width from ATTR_EFF_DRAM_WIDTH (%d)", l_dram_width);
-      const uint8_t & DRAM_WIDTH = l_dram_width;
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_BAD_DRAM_WIDTH);
-      return rc;
-   }
-   
-   if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ) 
-   {
-      if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-      {
-         l_type=CDIMM_DQ;
-         
-         if(i_input_index_u8>l_CDIMM_dqmax)    
-         {
-            FAPI_ERR("CDIMM_DQ: Wrong input index specified (%d, max %d)" ,
-                     i_input_index_u8, l_CDIMM_dqmax);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-            return rc;
-         }
-      }
-      else
-      {
-         l_type=ISDIMM_DQ;
-         if(i_input_index_u8>l_ISDIMM_dqmax)
-         {
-            FAPI_ERR("ISDIMM_DQ: Wrong input index specified (%d, max %d)",
-                     i_input_index_u8, l_ISDIMM_dqmax);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-            return rc;
-         }
-      }
-      
-      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc;
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("C4 value is=%d",l_val);
-      }   
-      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_out.scom_addr);
-         FAPI_INF("start bit=%d",l_out.start_bit);
-         FAPI_INF("length=%d",l_out.bit_length);
-      }   
-      l_scom_add=l_out.scom_addr;
-      l_sbit=l_out.start_bit;
-      l_len=l_out.bit_length;
-	 
-   }
-   
-   else if(i_input_type_e==ADDRESS)
-   {
-      if(i_input_index_u8<=18) // 19 delay values for Address
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=addr_lanep0[i_input_index_u8];
-            l_adr=addr_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=addr_lanep1[i_input_index_u8];
-            l_adr=addr_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=addr_lanep2[i_input_index_u8];
-            l_adr=addr_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=addr_lanep3[i_input_index_u8];
-            l_adr=addr_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      
-      ip_type_t l_input=ADDRESS_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==DATA_DISABLE)
-   {
-      if(i_input_index_u8<=4) // 5 delay values for data bits disable register
-      {
-         l_block=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      
-      ip_type_t l_input=DATA_DISABLE_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-      }
-      l_lane=0;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   
-   else if(i_input_type_e==COMMAND)
-   {
-      if(i_input_index_u8<=2) // 3 delay values for Command
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=cmd_lanep0[i_input_index_u8];
-            l_adr=cmd_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=cmd_lanep1[i_input_index_u8];
-            l_adr=cmd_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=cmd_lanep2[i_input_index_u8];
-            l_adr=cmd_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=cmd_lanep3[i_input_index_u8];
-            l_adr=cmd_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=COMMAND_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }   
-   
-    else if(i_input_type_e==CONTROL)
-   {
-      if(i_input_index_u8<=19) // 20 delay values for Control
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=cnt_lanep0[i_input_index_u8];
-            l_adr=cnt_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=cnt_lanep1[i_input_index_u8];
-            l_adr=cnt_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=cnt_lanep2[i_input_index_u8];
-            l_adr=cnt_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=cnt_lanep3[i_input_index_u8];
-            l_adr=cnt_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=CONTROL_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==CLOCK)
-   {
-      if(i_input_index_u8<=7) // 8 delay values for CLK
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=clk_lanep0[i_input_index_u8];
-            l_adr=clk_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=clk_lanep1[i_input_index_u8];
-            l_adr=clk_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=clk_lanep2[i_input_index_u8];
-            l_adr=clk_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=clk_lanep3[i_input_index_u8];
-            l_adr=clk_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=CLOCK_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }   
-   
-    
-   else if (i_input_type_e==RD_DQS || i_input_type_e==WR_DQS || i_input_type_e==DQS_ALIGN ||  i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK)	    
-   {
-     
-      if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-      {
-         l_type=CDIMM_DQS;
-      }
-      else
-      {
-         l_type=ISDIMM_DQS;
-      }
-      
-      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("C4 value is=%d",l_val);
-      }
-      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_out.scom_addr);
-         FAPI_INF("start bit=%d",l_out.start_bit);
-         FAPI_INF("length=%d",l_out.bit_length); 
-      }
-      l_scom_add=l_out.scom_addr;
-      l_sbit=l_out.start_bit;
-      l_len=l_out.bit_length;   
-         
-   }
-   
-   
-   else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4) 
-   {
-      if(i_input_type_e==RAW_RDCLK_0)
-      {
-         l_block=0;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_1)
-      {
-         l_block=1;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_2)
-      {
-         l_block=2;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_3)
-      {
-         l_block=3;
-      }
-      
-      else
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3) // 4 delay values for RDCLK 
-      {
-         l_lane=i_input_index_u8;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;      
-      }
-     
-      ip_type_t l_input=RAW_RDCLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4)
-   {
-      if(i_input_type_e==RAW_DQSCLK_0)
-      {
-         l_block=0;
-      }
-      
-      else if(i_input_type_e==RAW_DQSCLK_1)
-      {
-         l_block=1;
-      }
-      
-      else if(i_input_type_e==RAW_DQSCLK_2)
-      {
-         l_block=2;
-      }
-      
-      else if(i_input_type_e==RAW_DQSCLK_3)
-      {
-         l_block=3;
-      }
-      
-      else
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3) // 4 delay values for DQSCLK
-      {
-         l_lane=i_input_index_u8;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_DQSCLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-         
-   else if(i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4)
-   {
-      if(i_input_type_e==RAW_WR_DQ_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_WR_DQ_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_WR_DQ_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_WR_DQ_3)
-      {
-         l_block=3;
-      }
-      else
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=15) // 16 Write delay values for DQ bits
-      {
-         l_lane=i_input_index_u8;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-     
-      ip_type_t l_input=RAW_WR_DQ;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4)
-   {
-      if(i_input_type_e==RAW_RD_DQ_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_RD_DQ_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_RD_DQ_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_RD_DQ_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=15)   // 16 read delay values for DQ bits
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_RD_DQ;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4)
-   {
-      if(i_input_type_e==RAW_RD_DQS_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_RD_DQS_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_RD_DQS_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_RD_DQS_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3) // 4 Read DQS delay values 
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      
-      ip_type_t l_input=RAW_RD_DQS;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4)
-   {
-      if(i_input_type_e==RAW_DQS_ALIGN_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_DQS_ALIGN_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_DQS_ALIGN_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_DQS_ALIGN_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3)     // 4 DQS alignment delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_DQS_ALIGN;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   
-   else if(i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4)
-   {
-      if(i_input_type_e==RAW_WR_DQS_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_WR_DQS_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_WR_DQS_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_WR_DQS_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3)      // 4 Write DQS delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_WR_DQS;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   else if(i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4)
-   {
-      if(i_input_type_e==RAW_SYS_CLK_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_SYS_CLK_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_SYS_CLK_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_SYS_CLK_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      } 
-      if(i_input_index_u8==0) // 1 system clock delay value
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_SYS_CLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_SYS_ADDR_CLK)
-   {
-      if(i_input_index_u8<=1)   // 1 system address clock delay value
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_SYS_ADDR_CLKS0S1;
-      if(i_verbose==1)
-      {
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   
-   else if(i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4)
-   {
-      if(i_input_type_e==RAW_WR_CLK_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_WR_CLK_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_WR_CLK_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_WR_CLK_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      } 
-      if(i_input_index_u8==0)           //  1 Write clock delay value
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_WR_CLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3)
-   {
-      if(i_input_type_e==RAW_ADDR_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_ADDR_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_ADDR_2)
-      {
-         l_block=2;
-      }
-      else 
-      {
-         l_block=3;
-      }
-      if(i_input_index_u8<=15)      //  16 Addr delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_ADDR;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-  
-   else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4)
-   {
-      if(i_input_type_e==RAW_DQS_GATE_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_DQS_GATE_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_DQS_GATE_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_DQS_GATE_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-              
-      if(i_input_index_u8<=3)     // 4 Gate Delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_DQS_GATE;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   } 
-   
-   else
-   {
-      FAPI_ERR("Wrong input type specified (%d)", i_input_type_e);
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-      return rc;
-   } 
-     
-   if(i_access_type_e==READ)   
-   {
-      rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc;
-      rc_num= rc_num | data_buffer_64.extractToRight(&l_output,l_sbit,l_len);
-      if(rc_num)
-      {
-        FAPI_ERR( "ecmd error on l_scom_add extract");       
-	rc.setEcmdError(rc_num);
-        return rc;
-      }    
-      io_value_u32=l_output;
-     // FAPI_INF("Delay value=%d",io_value_u32);
-   }
-   
-   else if(i_access_type_e==WRITE)
-   {
-      
-      if(i_input_type_e==RD_DQ || i_input_type_e==RD_DQS || i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4 || i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4
-      || i_input_type_e==RAW_SYS_ADDR_CLK || i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4 || i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4
-      || i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3 || i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4
-      || i_input_type_e==DQS_ALIGN || i_input_type_e==COMMAND || i_input_type_e==ADDRESS || i_input_type_e==CONTROL || i_input_type_e==CLOCK )   
-      {
-         l_start=25;   // l_start is starting bit of delay value in the register. There are different registers and each register has a different field for delay
-      }
-      else if(i_input_type_e==WR_DQ || i_input_type_e==WR_DQS || i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4 || i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4 )
-      {
-         l_start=22;
-      }
-   
-      else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4 || i_input_type_e==DQS_GATE)
-      {
-         l_start=29;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4 || i_input_type_e==RDCLK || i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4 || i_input_type_e==DQSCLK)
-      {
-         l_start=30;  
-      }
-      
-      else if(i_input_type_e==DATA_DISABLE)
-      {
-         l_start=16;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input type specified (%d)", i_input_type_e);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_INVALID_INPUT);
-         return rc;
-      }
-      if(i_verbose==1)
-      {
-         FAPI_INF("value given=%d",io_value_u32);
-      }
-      
-      rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc;	  
-      rc_num=data_buffer_64.insert(io_value_u32,l_sbit,l_len,l_start);
-      if(rc_num)
-      {
-        FAPI_ERR( "ecmd error on l_scom_add extract");       
-	rc.setEcmdError(rc_num);
-        return rc;
-      }    
-      rc=fapiPutScom(i_target_mba,l_scom_add,data_buffer_64); if(rc) return rc;
-   }
-   return rc;
-}
-
-//******************************************************************************
-//Function name: cross_coupled()
-//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19 , i_verbose-extra print statements  
-//Output : out (address,start bit and bit length)
-//******************************************************************************    
-fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,
-                               uint8_t i_port,
-                               uint8_t i_rank_pair,
-                               input_type_t i_input_type_e,
-                               uint8_t i_input_index,
-                               uint8_t i_verbose,
-                               scom_location& out)
-{    
-   fapi::ReturnCode rc; 
-   const uint8_t l_dqmax=80;
-   const uint8_t l_dqsmax=20;
-   const uint8_t l_dqs=4;
-   const uint8_t lane_dq_p0[l_dqmax]={4,6,5,7,2,1,3,0,13,15,12,14,8,9,11,10,13,15,12,14,9,8,11,10,13,15,12,14,11,9,10,8,11,8,9,10,12,13,14,15,7,6,5,4,1,3,2,0,5,6,4,7,3,1,2,0,7,4,5,6,2,0,3,1,3,0,1,2,6,5,4,7,11,8,9,10,15,13,12,14}; 
-   const uint8_t lane_dq_p1[l_dqmax]={9,11,8,10,13,14,15,12,10,8,11,9,12,13,14,15,1,0,2,3,4,5,6,7,9,11,10,8,15,12,13,14,5,7,6,4,1,0,2,3,0,2,1,3,5,4,6,7,0,2,3,1,4,5,6,7,12,15,13,14,11,8,10,9,5,7,4,6,3,2,0,1,14,12,15,13,9,8,11,10}; 
-   const uint8_t lane_dq_p2[l_dqmax]={13,15,12,14,11,9,10,8,13,12,14,15,10,9,11,8,5,6,7,4,2,3,0,1,10,9,8,11,13,12,15,14,15,12,13,14,11,10,9,8,7,6,4,5,1,0,3,2,0,2,1,3,5,6,4,7,5,7,6,4,1,0,2,3,1,2,3,0,7,6,5,4,9,10,8,11,12,15,14,13};
-   const uint8_t lane_dq_p3[l_dqmax]={4,5,6,7,0,1,3,2,12,13,15,14,8,9,10,11,10,8,11,9,12,13,15,14,3,0,1,2,4,6,7,5,9,10,11,8,14,13,15,12,7,5,6,4,3,1,2,0,5,6,7,4,1,2,3,0,14,12,15,13,8,10,9,11,0,3,2,1,6,5,7,4,10,11,9,8,12,13,15,14};
-   const uint8_t dqs_dq_lane_p0[l_dqsmax]={4,0,12,8,12,8,12,8,8,12,4,0,4,0,4,0,0,4,8,12};
-   const uint8_t dqs_dq_lane_p1[l_dqsmax]={8,12,8,12,0,4,8,12,4,0,0,4,0,4,12,8,4,0,12,8};
-   const uint8_t dqs_dq_lane_p2[l_dqsmax]={12,8,12,8,4,0,8,12,12,8,4,0,0,4,4,0,0,4,8,12};
-   const uint8_t dqs_dq_lane_p3[l_dqsmax]={4,0,12,8,8,12,0,4,8,12,4,0,4,0,12,8,0,4,8,12};
-   const uint8_t block_p1[l_dqmax]={0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2};
-   const uint8_t block_p0[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1};
-   const uint8_t block_p2[l_dqmax]={1,1,1,1,1,1,1,1,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,4,4,4,4,4,4,4,4};
-   const uint8_t block_p3[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
-   const uint8_t block_dqs_p0[l_dqsmax]={2,2,2,2,0,0,3,3,4,4,3,3,4,4,1,1,0,0,1,1};
-   const uint8_t block_dqs_p1[l_dqsmax]={0,0,3,3,0,0,1,1,2,2,3,3,4,4,4,4,1,1,2,2};
-   const uint8_t block_dqs_p2[l_dqsmax]={1,1,3,3,0,0,0,0,2,2,2,2,3,3,4,4,1,1,4,4};
-   const uint8_t block_dqs_p3[l_dqsmax]={2,2,2,2,0,0,0,0,3,3,3,3,4,4,4,4,1,1,1,1};
-   const uint8_t dqslane[l_dqs]={16,18,20,22};
-   uint8_t l_j=0;
-   uint8_t l_flag=0; 
-   uint8_t l_mbapos = 0;
-   uint8_t l_dram_width=0;
-   uint8_t l_lane=0;
-   const uint8_t & INVALID_DQS =l_lane;
-   uint8_t l_block=0;
-   uint8_t lane_dqs[4];
-   uint8_t l_index=0;
-   uint8_t l_dq=0;
-   uint64_t l_scom_address_64=0x0ull;
-   uint8_t l_start_bit=0;
-   uint8_t l_len=0;
-   ip_type_t l_input_type;
-   ecmdDataBufferBase data_buffer_64(64);
-   uint8_t l_dimmtype=0;
-   uint8_t l_swizzle=0;
-      
-   rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc;
-      
-   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc;
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc;
-         
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
-   
-      
-   if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ)
-   {
-      if(i_port==0 && l_mbapos==0)
-      {
-         l_lane=lane_dq_p0[i_input_index];
-	 l_block=block_p0[i_input_index];	    
-      }
-      else if(i_port==1 && l_mbapos==0)
-      {
-         l_lane=lane_dq_p1[i_input_index];
-         l_block=block_p1[i_input_index];	    
-      } 
-      else if(i_port==0 && l_mbapos==1)
-      {
-         l_lane=lane_dq_p2[i_input_index];
-         l_block=block_p2[i_input_index];	
-      }
-      else
-      {
-	 l_lane=lane_dq_p3[i_input_index];
-	 l_block=block_p3[i_input_index];	
-      }
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      } 
-      if(i_input_type_e==RD_DQ)
-      {
-         l_input_type=RD_DQ_t;
-      }
-      else 	
-      {
-         l_input_type=WR_DQ_t;    
-      }
-      
-            
-      rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
-      out.scom_addr=l_scom_address_64;
-      out.start_bit=l_start_bit;
-      out.bit_length=l_len; 
-   }
-   
-   else if (i_input_type_e==WR_DQS ||  i_input_type_e==DQS_ALIGN)	    
-   {
-      if(i_port==0 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p0[i_input_index];
-         l_block=block_dqs_p0[i_input_index]; 
-      }
-             
-      else if(i_port==1 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p1[i_input_index];   
-         l_block=block_dqs_p1[i_input_index]; 
-      }   
-      else if(i_port==0 && l_mbapos==1)
-      {
-         l_dq=dqs_dq_lane_p2[i_input_index];   
-         l_block=block_dqs_p2[i_input_index]; 
-      }
-      else 
-      {
-         l_dq=dqs_dq_lane_p3[i_input_index];   
-         l_block=block_dqs_p3[i_input_index]; 
-      }
-       
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("dqs_dq_lane=%d",l_dq);
-      }
-      l_input_type=RD_CLK_t; 
-      rc=get_address(i_target_mba,i_port,i_rank_pair, l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("read clock address=%llx",l_scom_address_64);
-      }
-      rc=fapiGetScom(i_target_mba,l_scom_address_64,data_buffer_64);if(rc) return rc; 
-            
-      if(l_dram_width==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
-      {
-         
-         if (data_buffer_64.isBitSet(48))
-         {
-            lane_dqs[l_index]=16;
-            l_index++;
-         }
-         else if(data_buffer_64.isBitSet(52))
-         { 
-            lane_dqs[l_index]=18;
-            l_index++;
-         }
-        
-         if (data_buffer_64.isBitSet(49))
-         {
-            lane_dqs[l_index]=16;
-            l_index++;
-         }
-     
-         else if (data_buffer_64.isBitSet(53))
-         {
-            lane_dqs[l_index]=18;
-            l_index++;
-         }
-         
-         if (data_buffer_64.isBitSet(54))
-         {
-            lane_dqs[l_index]=20;
-            l_index++;
-         }
-         else if (data_buffer_64.isBitSet(56))
-         {
-            lane_dqs[l_index]=22;
-            l_index++;
-         }
-      
-         if (data_buffer_64.isBitSet(55))
-         {
-            lane_dqs[l_index]=20;
-            l_index++;
-         }
-         else if (data_buffer_64.isBitSet(57))   // else is not possible as one of them will definitely get set
-         {
-            lane_dqs[l_index]=22;
-            l_index++;
-         }
-         if(i_verbose==1)
-         {
-            FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]);
-         }   
-         if(l_dq==0)
-         {
-            l_lane=lane_dqs[0];
-         }
-         else if(l_dq==4)
-         {
-            l_lane=lane_dqs[1];
-         }  
-         else if(l_dq==8)
-         {
-            l_lane=lane_dqs[2];
-         }
-         else 
-         {
-            l_lane=lane_dqs[3];
-         }
-         
-         if(i_verbose==1)
-         {
-            FAPI_INF("lane is=%d",l_lane); 
-         }
-      }			  
-   
-     
-      else
-      {   
-         if (data_buffer_64.isBitSet(48)&& data_buffer_64.isBitSet(49))
-         {		  
-            lane_dqs[l_index]=16;
-            l_index++; 		    
-         }
-         else if (data_buffer_64.isBitSet(52)&& data_buffer_64.isBitSet(53))
-         {		  
-            lane_dqs[l_index]=18;
-            l_index++; 		    
-         }
-         if (data_buffer_64.isBitSet(54)&& data_buffer_64.isBitSet(55))
-         {		  
-            lane_dqs[l_index]=20;
-            l_index++; 		    
-         }
-         else if (data_buffer_64.isBitSet(56)&& data_buffer_64.isBitSet(57))   // else is not possible as one of them will definitely get set
-         {		  
-            lane_dqs[l_index]=22;
-            l_index++; 		    
-         }
-         if(i_verbose==1)
-         {
-            FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); 
-         } 
-         if((l_dq==0) || (l_dq==4))
-         {
-            l_lane=lane_dqs[0];
-         }
-         else 
-         {
-            l_lane=lane_dqs[1];
-         }
-         
-         if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-         {
-            if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7) || (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17) || (i_input_index==19))
-            {
-               if(l_lane==16)
-               {
-                  l_lane=18;
-               }
-               else if(l_lane==18)
-               {
-                  l_lane=16;
-               }
-               
-               else if(l_lane==20)
-               {
-                  l_lane=22;
-               }
-               
-               else
-               {
-                  l_lane=20;
-               }
-               
-            }
-         }
-         
-         else
-         {
-            if((i_port==0) && (l_mbapos==0))
-            {
-               if(l_swizzle==1)
-               {
-                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==6))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                     
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                     
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  
-                  }   
-               }
-                           
-               else
-               {
-                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                       
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                       
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  }   
-                          
-               }
-            }   
-            
-            else if((i_port==1) && (l_mbapos==0))
-            {
-               if(l_swizzle==1)
-               {
-                  if((i_input_index==2) || (i_input_index==0) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==7))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                     
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                  
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  }   
-               }
-               
-               else
-               {
-                  if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                     
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                  
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  }   
-               }
-            }
-                  
-                  
-            else
-            {
-               if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
-               {
-                  if(l_lane==16)
-                  {
-                     l_lane=18;
-                  }
-                  else if(l_lane==18)
-                  {
-                     l_lane=16;
-                  }
-                  
-                  else if(l_lane==20)
-                  {
-                     l_lane=22;
-                  }
-                  
-                  else
-                  {
-                     l_lane=20;
-                  }
-               
-               }   
-            }
-            
-            
-            
-         }
-         if(i_verbose==1)
-         {
-            FAPI_INF("lane is=%d",l_lane);
-         }   
-      }
-      
-      if(i_input_type_e==WR_DQS)	  		  
-      {
-         l_input_type=WR_DQS_t;  
-      }
-      else
-      {
-         l_input_type=DQS_ALIGN_t;
-      }
-      
-      
-      for(l_j=0;l_j<4;l_j++)
-      {
-         if(l_lane==dqslane[l_j])
-         {
-            l_flag=1;
-            break;
-         }
-         
-      }
-      if(l_flag==0)
-      {
-        FAPI_ERR("Invalid DQS and DQS lane=%d",l_lane);
-        FAPI_SET_HWP_ERROR(rc, RC_CROSS_COUPLED_INVALID_DQS);
-        return rc; 
-      }
-      
-      
-      rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
-      out.scom_addr=l_scom_address_64;
-      out.start_bit=l_start_bit;
-      out.bit_length=l_len; 
-   }   
-      
-    
-   else if (i_input_type_e==RD_DQS || i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK)	    
-   {
-      
-      
-      if(i_port==0 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p0[i_input_index];
-         l_block=block_dqs_p0[i_input_index]; 
-      }
-             
-      else if(i_port==1 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p1[i_input_index];   
-         l_block=block_dqs_p1[i_input_index]; 
-      }   
-      else if(i_port==0 && l_mbapos==1)
-      {
-         l_dq=dqs_dq_lane_p2[i_input_index];   
-         l_block=block_dqs_p2[i_input_index]; 
-      }
-      else
-      {
-         l_dq=dqs_dq_lane_p3[i_input_index];   
-         l_block=block_dqs_p3[i_input_index]; 
-      }
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("dqs_dq_lane=%d",l_dq);
-      }   
-      if(l_dq==0)
-      {
-         l_lane=16;
-      }
-         
-      else if(l_dq==4)
-      {
-         l_lane=18;
-      }
-         
-      else if (l_dq==8)
-      {
-         l_lane=20;
-      }
-         
-      else
-      {
-         l_lane=22;
-      }
-      //FAPI_INF("here");
-      
-      if (i_input_type_e==DQS_GATE)
-      {
-         l_input_type=DQS_GATE_t;
-      }
-      
-      else if(i_input_type_e==RDCLK)
-      {
-         l_input_type=RDCLK_t;
-      }
-      
-      else if(i_input_type_e==RD_DQS)
-      {
-         l_input_type=RD_DQS_t;
-      }
-      
-      else
-      {
-         l_input_type=DQSCLK_t;
-      }
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("lane is=%d",l_lane);
-      }
-      
-      rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
-      out.scom_addr=l_scom_address_64;
-      out.start_bit=l_start_bit;
-      out.bit_length=l_len; 
-   }
-   
-   else
-   {
-      FAPI_ERR("Wrong input type specified (%d)", i_input_type_e);
-      const input_type_t & TYPE_PARAM = i_input_type_e;
-      FAPI_SET_HWP_ERROR(rc, RC_CROSS_COUPLED_INVALID_INPUT);
-      return rc;
-   }  
-
-   return rc; 
-}
-
-
-//******************************************************************************
-//Function name: rosetta_map()
-//Description:This function returns C4 bit for the corresponding ISDIMM bit
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1,i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS, i_input_index_u8=0-79/0-71/0-8/0-19, i_verbose-extra print statements    
-//Output : C4 bit=o_value
-//****************************************************************************** 
-fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,
-                             uint8_t i_port,
-                             input_type i_input_type_e,
-                             uint8_t i_input_index,
-                             uint8_t i_verbose,
-                             uint8_t &o_value) //This function is used by some other procedures
-{  // Boundary check is done again
-    // Reference variables for Error FFDC
-    const fapi::Target & MBA_TARGET = i_target_mba;
-    const uint8_t & PORT_PARAM = i_port;
-    const input_type & TYPE_PARAM = i_input_type_e;
-    const uint8_t & INDEX_PARAM = i_input_index;
-
-    fapi::ReturnCode rc;
-   
-   const uint8_t l_ISDIMM_dqmax=71; 
-   const uint8_t l_CDIMM_dqmax=79;
-   uint8_t l_mbapos = 0;
-   uint8_t l_dimmtype=0;
-   const uint8_t l_maxdq=72;
-   const uint8_t l_maxdqs=18;
-   uint8_t l_swizzle=0;
-   const uint8_t GL_DQ_p0_g1[l_maxdq]={10,9,11,8,12,13,14,15,3,1,2,0,7,5,4,6,20,21,22,23,16,17,18,19,64,65,66,67,71,70,69,68,32,33,34,35,36,37,38,39,42,40,43,41,44,46,45,47,48,51,50,49,52,53,54,55,58,56,57,59,60,61,62,63,31,28,29,30,25,27,26,24};
-   const uint8_t GL_DQ_p0_g2[l_maxdq]={10,9,11,8,12,13,14,15,3,1,2,0,7,5,4,6,16,17,18,19,20,21,22,23,64,65,66,67,71,70,69,68,32,33,34,35,36,37,38,39,42,40,43,41,44,46,45,47,48,51,50,49,52,53,54,55,58,56,57,59,60,61,62,63,25,27,26,24,28,31,29,30};
-   const uint8_t GL_DQ_p1_g1[l_maxdq]={15,13,12,14,9,8,10,11,5,7,4,6,3,2,1,0,20,22,21,23,16,17,18,19,70,71,69,68,67,66,65,64,32,35,34,33,38,37,39,36,40,41,42,43,44,45,46,47,49,50,48,51,52,53,54,55,59,57,56,58,60,62,61,63,27,26,25,24,31,30,28,29};
-   const uint8_t GL_DQ_p1_g2[l_maxdq]={8,9,10,11,12,13,14,15,3,2,1,0,4,5,6,7,16,17,18,19,20,21,22,23,67,66,64,65,70,71,69,68,32,35,34,33,38,37,39,36,40,41,42,43,44,45,46,47,49,50,48,51,52,53,54,55,59,57,56,58,60,62,61,63,27,26,25,24,31,30,28,29};
-   const uint8_t GL_DQ_p2[l_maxdq]={9,11,10,8,12,15,13,14,0,1,3,2,5,4,7,6,19,17,16,18,20,22,21,23,66,67,65,64,71,70,69,68,32,33,34,35,36,37,38,39,41,40,43,42,45,44,47,46,48,49,50,51,52,53,54,55,58,56,57,59,60,61,62,63,25,27,24,26,28,31,29,30};
-   const uint8_t GL_DQ_p3[l_maxdq]={3,2,0,1,4,5,6,7,11,10,8,9,15,14,12,13,16,17,18,19,20,21,22,23,64,65,66,67,68,69,70,71,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,24,25,26,27,28,29,30,31};
-
-   const uint8_t GL_DQS_p0_g1[l_maxdqs]={2,0,5,16,8,10,12,14,7,3,1,4,17,9,11,13,15,6};
-   const uint8_t GL_DQS_p0_g2[l_maxdqs]={2,0,4,16,8,10,12,14,6,3,1,5,17,9,11,13,15,7};
-   const uint8_t GL_DQS_p1_g1[l_maxdqs]={3,1,5,16,8,10,12,14,6,2,0,4,17,9,11,13,15,7};
-   const uint8_t GL_DQS_p1_g2[l_maxdqs]={2,0,4,16,8,10,12,14,6,3,1,5,17,9,11,13,15,7};
-   const uint8_t GL_DQS_p2[l_maxdqs]={2,0,4,16,8,10,12,14,6,3,1,5,17,9,11,13,15,7};
-   const uint8_t GL_DQS_p3[l_maxdqs]={0,2,4,16,8,10,12,14,6,1,3,5,17,9,11,13,15,7};
-   
-   rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc;
-   
-   
-   if(l_swizzle ==0 || l_swizzle ==1)
-   {
-      if(i_verbose==1)
-      {
-         FAPI_INF("swizzle type=%d",l_swizzle);
-      }   
-   }
-   
-   else
-   {
-      FAPI_ERR("Wrong swizzle value (%d)", l_swizzle);
-      const uint8_t & SWIZZLE_TYPE = l_swizzle;
-      FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_BAD_SWIZZLE_VALUE);
-      return rc;
-   }
-   
-   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc;
-
-   if(i_port >1)
-   {
-      FAPI_ERR("Wrong port specified (%d)", i_port);
-      FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT);
-      return rc;
-   }
-
-   if (l_mbapos>1)
-   {
-       FAPI_ERR("Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos);
-       const uint8_t & MBA_POS = l_mbapos;
-       FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_BAD_MBA_POS);
-       return rc;
-   }
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc;
-   
-   if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-   {
-      if(i_input_index>l_CDIMM_dqmax)    
-      {
-         FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT);
-         FAPI_ERR("Wrong input index specified rc = 0x%08X" ,uint32_t(rc));
-         return rc;      
-      }
-   }
-   else
-   {
-      if(i_input_index>l_ISDIMM_dqmax)
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index);
-         FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT);
-         return rc;
-      }
-   }
-    	
-   if(i_input_type_e ==ISDIMM_DQ)
-   {
-      if(i_port==0 && l_mbapos==0)
-      {
-         if(l_swizzle==1)
-         {
-            o_value=GL_DQ_p0_g1[i_input_index];   
-         }
-         else
-         {
-            o_value=GL_DQ_p0_g2[i_input_index];    
-         }
-            
-      }
-	            
-      else if(i_port==1 && l_mbapos==0)
-      {
-         if(l_swizzle==1)
-         {
-            o_value=GL_DQ_p1_g1[i_input_index];
-         }
-         else
-         {
-            o_value=GL_DQ_p1_g2[i_input_index];    
-         }
-      }
-   
-      else if(i_port==0 && l_mbapos==1)
-      {
-         o_value=GL_DQ_p2[i_input_index];    
-      }
-      else 
-      {
-         o_value=GL_DQ_p3[i_input_index];    
-      }
-          
-   }
-      
-    
-   else if(i_input_type_e ==ISDIMM_DQS)
-   {
-        
-      if(i_port==0 && l_mbapos==0)
-      {
-         if(l_swizzle==1)
-         {
-            o_value=GL_DQS_p0_g1[i_input_index];
-         }
-         else 
-         {
-            o_value=GL_DQS_p0_g2[i_input_index];    
-         }
-            
-      }    
-      else if(i_port==1 && l_mbapos==0)
-      {
-         if(l_swizzle==1)
-         {
-            o_value=GL_DQS_p1_g1[i_input_index];
-         }
-         else 
-         {
-            o_value=GL_DQS_p1_g2[i_input_index];    
-         }
-            
-      }
-      else if(i_port==0 && l_mbapos==1)
-      {
-         o_value=GL_DQS_p2[i_input_index];
-      }
-      else 
-      {
-         o_value=GL_DQS_p3[i_input_index];
-      }
-                    
-   }      
-   else if(i_input_type_e==CDIMM_DQS)
-   {
-      o_value=i_input_index;   
-   }
-      
-   else if(i_input_type_e==CDIMM_DQ)
-   {
-      o_value=i_input_index;
-   }
-       
-   else
-   {
-      FAPI_ERR("Wrong input type specified (%d)", i_input_type_e);
-      FAPI_SET_HWP_ERROR(rc, RC_ROSETTA_MAP_INVALID_INPUT);
-      return rc;      
-   }
-   
-   return rc;
-}
-
-//******************************************************************************
-//Function name: get address()
-//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS, i_block=0 or 1 or 2 or 3 or 4, i_lane=0-15   
-//Output : scom address=o_scom_address_64, start bit=o_start_bit, bit length=o_len 
-//******************************************************************************    
-fapi::ReturnCode get_address(const fapi::Target & i_target_mba,
-                             uint8_t i_port,
-                             uint8_t i_rank_pair,
-                             ip_type_t i_input_type_e,
-                             uint8_t i_block,
-                             uint8_t i_lane,
-                             uint64_t &o_scom_address_64,
-                             uint8_t &o_start_bit,
-                             uint8_t &o_len)
-{
-   fapi::ReturnCode rc;
-   
-   uint64_t l_scom_address_64 = 0x0ull;
-   uint64_t l_temp=0x0ull;
-   uint8_t l_mbapos;
-   uint8_t l_lane=0;
-   const uint64_t l_port01_st=0x8000000000000000ull;
-   const uint64_t l_port23_st=0x8001000000000000ull;
-   const uint64_t l_port01_adr_st=0x8000400000000000ull;
-   const uint64_t l_port23_adr_st=0x8001400000000000ull;
-   const uint32_t l_port01_en=0x0301143f;
-   const uint64_t l_rd_port01_en=0x040301143full;
-   const uint64_t l_sys_clk_en=0x730301143full;
-   const uint64_t l_wr_clk_en =0x740301143full;
-   const uint64_t l_adr02_st=0x8000400000000000ull;
-   const uint64_t l_adr13_st=0x8001400000000000ull;
-   const uint64_t l_dqs_gate_en=0x000000130301143full;
-   const uint64_t l_dqsclk_en=0x090301143full;
-   const uint64_t l_data_ds_en=0x7c0301143full;
-   uint8_t l_tmp=0;
-   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc;
-   
-   if(i_input_type_e==WR_DQ_t || i_input_type_e==RAW_WR_DQ)
-   {
-      if(i_lane > 7)
-      {
-         l_scom_address_64 = 0x00000040;
-         l_scom_address_64=l_scom_address_64<<32;
-         l_temp|=(i_lane-8);
-      }
-		
-      else
-      {
-         l_scom_address_64|=0x00000038;
-         l_scom_address_64=l_scom_address_64<<32;
-         l_temp|=i_lane;
-      }
-      l_temp|=(i_block*4)<<8;
-      l_temp|=i_rank_pair<<8;
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_port01_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_port01_en;
-      }
-             
-      o_scom_address_64=l_scom_address_64;
-      o_start_bit=48; 
-      o_len=10;
-     
-   }
-   
-   else if(i_input_type_e==RD_DQ_t || i_input_type_e==RAW_RD_DQ)
-   {
-      l_scom_address_64|=0x00000050;       
-      l_scom_address_64=l_scom_address_64<<32;
-      l_lane=i_lane/2;           
-      l_temp|=l_lane;
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_port01_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_port01_en;
-      }
-            
-      if((i_lane % 2) == 0)
-      {
-         o_start_bit=48;
-         o_len=7;
-      }
-      else
-      {
-         o_start_bit=56;
-         o_len=7;
-      }
-   
-      
-      o_scom_address_64=l_scom_address_64; 
-     
-   }
-   
-   else if(i_input_type_e==COMMAND_t || i_input_type_e==CLOCK_t ||  i_input_type_e==CONTROL_t ||  i_input_type_e==ADDRESS_t )
-   {
-      l_tmp|=4;       
-      l_lane=i_lane/2;           
-      l_temp=l_lane+l_tmp;
-      l_temp|=(i_block*4)<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_adr_st | l_temp | l_port01_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_adr_st | l_temp | l_port01_en;
-      }
-            
-      if((i_lane % 2) == 0)
-      {
-         o_start_bit=49;
-         o_len=7;
-      }
-      else
-      {
-         o_start_bit=57;
-         o_len=7;
-      }
-   
-      
-      o_scom_address_64=l_scom_address_64; 
-     
-   }    
-        
-       
-   else if(i_input_type_e==WR_DQS_t  || i_input_type_e==RAW_WR_DQS)    
-   {
-      
-      if(i_input_type_e==RAW_WR_DQS)
-      {
-         if(i_lane==0)
-         {
-            i_lane=16;   
-         }
-         else if(i_lane==1)
-         {
-            i_lane=18;   
-         }
-         else if(i_lane==2)
-         {
-            i_lane=20;   
-         }
-         else 
-         {
-            i_lane=22;   
-         }
-      }
-      if(i_lane==16)
-      {
-         l_scom_address_64|=0x00000048;   	    
-      }
-      else if(i_lane==18)
-      {
-         l_scom_address_64|=0x0000004a;   	    
-      }
-      else if(i_lane==20)
-      {
-         l_scom_address_64|=0x0000004c;   	    
-      }
-      else
-      {
-         l_scom_address_64|=0x0000004e;   	    
-      }
-               
-      l_scom_address_64=l_scom_address_64<<32;             
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_port01_en;
-      }
-      else
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_port01_en;
-      }
-     
-      o_start_bit=48; 
-      o_len=10;  
-      o_scom_address_64=l_scom_address_64; 
-      
-   }
-   
-   else if(i_input_type_e==DATA_DISABLE_t)    
-   {
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_data_ds_en;
-      }
-      else
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_data_ds_en;
-      }
-     
-      o_start_bit=48; 
-      o_len=16;  
-      o_scom_address_64=l_scom_address_64; 
-   }
-   
-   else if(i_input_type_e==RD_CLK_t)
-   {  
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {   
-         l_scom_address_64|= l_port01_st | l_temp| l_rd_port01_en;
-      }
-      else 
-      {   
-         l_scom_address_64|= l_port23_st | l_temp| l_rd_port01_en;
-      }
-      
-         
-      o_start_bit=0;
-      o_len=0;
-      o_scom_address_64=l_scom_address_64;   
-      
-   } 
-            
-   else if(i_input_type_e==RD_DQS_t || i_input_type_e==RAW_RD_DQS) 
-   {
-      
-      if(i_input_type_e==RAW_RD_DQS)
-      {
-         if(i_lane==0)
-         {
-            i_lane=16;   
-         }
-         else if(i_lane==1)
-         {
-            i_lane=18;   
-         }
-         else if(i_lane==2)
-         {
-            i_lane=20;   
-         }
-         else
-         {
-            i_lane=22;   
-         }
-      }   
-      if(i_lane==16)
-      {
-         l_scom_address_64|=0x00000030;  
-         o_start_bit=49;  	    
-      }
-      else if(i_lane==18)
-      {
-	 l_scom_address_64|=0x00000030;   	
-	 o_start_bit=57;     
-      }
-      else if(i_lane==20)
-      {
-         l_scom_address_64|=0x00000031; 
-         o_start_bit=49;   	    
-      }
-      else 
-      {
-         l_scom_address_64|=0x00000031;  
-         o_start_bit=57;  	    
-      }
-   
-      l_scom_address_64=l_scom_address_64<<32;             
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_port01_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_port01_en;
-      }
-      
-        
-      o_len=7;  
-      o_scom_address_64=l_scom_address_64; 
-     
-   }
-   
-   else if(i_input_type_e==RDCLK_t || i_input_type_e==RAW_RDCLK) 
-   {
-      if(i_input_type_e==RAW_RDCLK) 
-      {
-         if(i_lane==0)
-         {
-            i_lane=16;   
-         }
-         else if(i_lane==1)
-         {
-            i_lane=18;   
-         }
-         else if(i_lane==2)
-         {
-            i_lane=20;   
-         }
-         else
-         {
-            i_lane=22;   
-         }
-      }   
-      if(i_lane==16)
-      {
-         o_start_bit=50;    
-      }
-      else if(i_lane==18)
-      {
-	 o_start_bit=54;     
-      }
-      else if(i_lane==20)
-      {
-         o_start_bit=58;   	    
-      }
-      else 
-      {
-         o_start_bit=62;  	    
-      }
-   
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_dqsclk_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_dqsclk_en;
-      }
-             
-      o_len=2;  
-      o_scom_address_64=l_scom_address_64; 
-     
-   }
-   
-    else if(i_input_type_e==DQSCLK_t || i_input_type_e==RAW_DQSCLK) 
-   {
-      if(i_input_type_e==RAW_DQSCLK) 
-      {
-         if(i_lane==0)
-         {
-            i_lane=16;   
-         }
-         else if(i_lane==1)
-         {
-            i_lane=18;   
-         }
-         else if(i_lane==2)
-         {
-            i_lane=20;   
-         }
-         else
-         {
-            i_lane=22;   
-         }
-      }
-           
-      if(i_lane==16)
-      {
-         o_start_bit=48;    
-      }
-      else if(i_lane==18)
-      {
-	 o_start_bit=52;     
-      }
-      else if(i_lane==20)
-      {
-         o_start_bit=56;   	    
-      }
-      else 
-      {
-         o_start_bit=60;  	    
-      }
-   
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_dqsclk_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_dqsclk_en;
-      }
-             
-      o_len=2;  
-      o_scom_address_64=l_scom_address_64; 
-     
-   }
-   
-     
-   else if(i_input_type_e==DQS_ALIGN_t || i_input_type_e==RAW_DQS_ALIGN) 
-   {
-      
-      if(i_input_type_e==RAW_DQS_ALIGN)
-      {
-         if(i_lane==0)
-         {
-            i_lane=16;   
-         }
-         else if(i_lane==1)
-         {
-            i_lane=18;   
-         }
-         else if(i_lane==2)
-         {
-            i_lane=20;   
-         }
-         else 
-         {
-            i_lane=22;   
-         }
-      }   
-      if(i_lane==16)
-      {
-         l_scom_address_64|=0x0000005c;  
-         o_start_bit=49;  	    
-      }
-      else if(i_lane==18)
-      {
-	 l_scom_address_64|=0x0000005c;   	
-	 o_start_bit=57;     
-      }
-      else if(i_lane==20)
-      {
-         l_scom_address_64|=0x0000005d; 
-         o_start_bit=49;   	    
-      }
-      else 
-      {
-         l_scom_address_64|=0x0000005d;  
-         o_start_bit=57;  	    
-      }
-   
-      l_scom_address_64=l_scom_address_64<<32;             
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_port01_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_port01_en;
-      }
-       
-          
-      o_len=7;  
-      o_scom_address_64=l_scom_address_64; 
-     
-   }
-   
-   
-   
-   else if(i_input_type_e==RAW_SYS_ADDR_CLKS0S1)
-   {  
-     
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         if(i_lane==0)
-         {
-            l_scom_address_64=0x800080340301143full;
-         }
-         else
-         {
-            l_scom_address_64=0x800084340301143full;   
-         }
-      }
-         
-      else 
-      {
-         if(i_lane==0)
-         {
-            l_scom_address_64=0x800180340301143full;
-         }
-         else
-         {
-            l_scom_address_64=0x800184340301143full;   
-         }
-      }   
-         
-      o_start_bit=49;
-      o_len=7;
-      o_scom_address_64=l_scom_address_64;   
-      
-   }
-   
-   else if(i_input_type_e==RAW_SYS_CLK)
-   {  
-      l_temp|=(i_block*4)<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {   
-         l_scom_address_64|= l_port01_st | l_temp| l_sys_clk_en;
-      }
-      else 
-      {   
-         l_scom_address_64|= l_port23_st | l_temp| l_sys_clk_en;
-      }
-               
-      o_start_bit=49;
-      o_len=7;
-      o_scom_address_64=l_scom_address_64;  
-      
-   }
-   
-    else if(i_input_type_e==RAW_WR_CLK)
-   {  
-      l_temp|=(i_block*4)<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {   
-         l_scom_address_64|= l_port01_st | l_temp| l_wr_clk_en;
-      }
-      else 
-      {   
-         l_scom_address_64|= l_port23_st | l_temp| l_wr_clk_en;
-      }
-               
-      o_start_bit=49;
-      o_len=7;
-      o_scom_address_64=l_scom_address_64;  
-      
-   } 
-   
-   else if(i_input_type_e==RAW_ADDR)
-   {
-      l_scom_address_64|=0x00000004;       
-      l_lane=i_lane;
-      if(i_lane<=7)
-      {
-         i_lane=i_lane/2;   
-      }
-      else if(i_lane==8 || i_lane==9)
-      {
-      l_scom_address_64=0x00000008;
-      i_lane=0;
-      }
-      else if(i_lane==10 || i_lane==11)
-      {
-      l_scom_address_64=0x00000009;
-      i_lane=0;
-      }
-      else if(i_lane==12 || i_lane==13)
-      {
-      l_scom_address_64=0x0000000a;
-      i_lane=0;
-      }
-      else 
-      {
-      l_scom_address_64=0x0000000b;
-      i_lane=0;
-      }
-      l_scom_address_64=l_scom_address_64<<32; 
-      l_temp|=i_lane;
-      l_temp|=(i_block*4)<<8;     
-      l_temp=l_temp<<32;
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_adr02_st | l_temp | l_port01_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_adr13_st | l_temp | l_port01_en;
-      }
-       
-      if((l_lane % 2) == 0)
-      {
-         o_start_bit=49;
-         o_len=7;
-      }
-      else
-      {
-         o_start_bit=57;
-         o_len=7;
-      }
-   
-      
-      o_scom_address_64=l_scom_address_64; 
-     
-   }    
-   
-   else if(i_input_type_e==RAW_DQS_GATE ||  i_input_type_e==DQS_GATE_t)
-   {
-      if(i_input_type_e==RAW_DQS_GATE)
-      {
-         l_lane=i_lane/4;    
-         l_temp|=l_lane;
-      }
-      if(i_input_type_e==DQS_GATE_t)
-      {
-         l_lane=i_lane;    
-      }
-      
-      l_temp|=(i_block*4)<<8;     
-      l_temp|=i_rank_pair<<8;     
-      l_temp=l_temp<<32;
-     
-      if(i_input_type_e==RAW_DQS_GATE)
-      {
-         if((i_lane % 4) == 0)
-         {
-            o_start_bit=49;
-            o_len=3;
-         }
-         else if((i_lane % 4) == 1)
-         {
-            o_start_bit=53;
-            o_len=3;
-         }
-      
-         else if((i_lane % 4) == 2)
-         {
-            o_start_bit=57;
-            o_len=3;
-         }
-      
-         else 
-         {
-            o_start_bit=61;
-            o_len=3;
-         }
-      }
-      
-      else
-      {
-         if(l_lane == 16)
-         {
-            o_start_bit=49;
-            o_len=3;
-         }
-         else if(l_lane ==18)
-         {
-            o_start_bit=53;
-            o_len=3;
-         }
-      
-         else if(l_lane ==20)
-         {
-            o_start_bit=57;
-            o_len=3;
-         }
-      
-         else 
-         {
-            o_start_bit=61;
-            o_len=3;
-         }
-         
-      }
-      
-      if((i_port==0 && l_mbapos==0) || (i_port==0 && l_mbapos==1))
-      {
-         l_scom_address_64|= l_port01_st | l_temp | l_dqs_gate_en;
-      }
-      else 
-      { 
-         l_scom_address_64|= l_port23_st | l_temp | l_dqs_gate_en;
-      }
-                 
-      o_scom_address_64=l_scom_address_64; 
-      
-   } 
-      
-   return rc;
-} 
- 
-//******************************************************************************
-//Function name: mss_getrankpair()
-//Description:This function returns rank pair and valid ranks from a given rank 
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank=valid ranks  
-//Output : rank pair=o_rank_pair, valid ranks=o_rankpair_table[] 
-//******************************************************************************
-fapi::ReturnCode mss_getrankpair(const fapi::Target & i_target_mba,
-                                 uint8_t i_port,
-                                 uint8_t i_rank,
-                                 uint8_t *o_rank_pair,
-                                 uint8_t o_rankpair_table[])
-{
-   fapi::ReturnCode rc;
-   uint8_t l_temp_rank[2]={0};
-   uint8_t l_temp_rankpair_table[16]={0};
-   uint8_t l_i= 0;
-   uint8_t l_rank_pair = 0;
-   uint8_t l_j= 0;
-   uint8_t l_temp_swap = 0;
- 
- 
-   for(l_i=0; l_i<8; l_i++)     	//populate Rank Pair Table as FF - invalid
-   {
-      //l_temp_rankpair_table[l_i]=255;
-      o_rankpair_table[l_i]=255;
-   }
- 
-   if(i_port==0 || i_port ==1)
-   {	
-	
-      rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[0]=l_temp_rank[i_port];
-	
-      rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[1]=l_temp_rank[i_port];
-	
-      rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[2]=l_temp_rank[i_port];
-      rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[3]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[4]=l_temp_rank[i_port];
-	
-      rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[5]=l_temp_rank[i_port];
-      rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[6]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[7]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[8]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[9]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[10]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[11]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[12]=l_temp_rank[i_port];
-	
-      rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[13]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[14]=l_temp_rank[i_port];
-   	
-      rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target_mba, l_temp_rank);if(rc) return rc;
-      l_temp_rankpair_table[15]=l_temp_rank[i_port];
-
-	
-   }
-
-   for(l_i=0; l_i<16; l_i++)
-   {
-      if(l_temp_rankpair_table[l_i]==i_rank)
-      {
-	 l_rank_pair=l_i;break;
-      }
-   }
-	
-   l_rank_pair = l_rank_pair%4; // if index l_i is greater than 4,8,12 Secondary, Tertiary, Quaternary.
-	
-	
-   for(l_i=0; l_i<15; l_i++)
-   {
-      for(l_j=l_i+1;l_j<16;l_j++)
-      {
-         if(l_temp_rankpair_table[l_i]>l_temp_rankpair_table[l_j])
-         {
-            l_temp_swap = l_temp_rankpair_table[l_j];
-            l_temp_rankpair_table[l_j]=l_temp_rankpair_table[l_i];
-            l_temp_rankpair_table[l_i]=l_temp_swap;
-         }
-      }
-   }
-	
-   for(l_i=0; l_i<8; l_i++)
-   {
-      if(l_temp_rankpair_table[l_i]!=255)
-         o_rankpair_table[l_i]=l_temp_rankpair_table[l_i];
-   }
-   *o_rank_pair = l_rank_pair;
-	
-	
-   return rc;
-} //end of mss_getrankpair
-
-//******************************************************************************
-//Function name: mss_c4_phy()
-//Description:This function returns address,start bit and bit length for RD_DQ, WR_DQ, RD_DQS, WR_DQS
-//Input  : Target MBA=i_target_mba, i_port_u8=0 or 1, i_rank_pair=0 or 1 or 2 or 3, i_input_type_e=RD_DQ or RD_DQS or WR_DQ or WR_DQS,i_input_index_u8=0-79/0-71/0-8/0-19 , i_verbose-extra print statements  
-//Output : out (address,start bit and bit length)
-//******************************************************************************
-fapi::ReturnCode mss_c4_phy(const fapi::Target & i_target_mba,
-                            uint8_t i_port,
-                            uint8_t i_rank_pair,
-                            input_type_t i_input_type_e,
-                            uint8_t &i_input_index,
-                            uint8_t i_verbose,
-                            uint8_t &phy_lane,
-                            uint8_t &phy_block,
-                            uint8_t flag)
-{
-   fapi::ReturnCode rc; 
-   const uint8_t l_dqmax=80;
-   const uint8_t l_dqsmax=20;
-   //const uint8_t l_blkmax=5;
-   const uint8_t lane_dq_p0[l_dqmax]={4,6,5,7,2,1,3,0,13,15,12,14,8,9,11,10,13,15,12,14,9,8,11,10,13,15,12,14,11,9,10,8,11,8,9,10,12,13,14,15,7,6,5,4,1,3,2,0,5,6,4,7,3,1,2,0,7,4,5,6,2,0,3,1,3,0,1,2,6,5,4,7,11,8,9,10,15,13,12,14}; 
-   const uint8_t lane_dq_p1[l_dqmax]={9,11,8,10,13,14,15,12,10,8,11,9,12,13,14,15,1,0,2,3,4,5,6,7,9,11,10,8,15,12,13,14,5,7,6,4,1,0,2,3,0,2,1,3,5,4,6,7,0,2,3,1,4,5,6,7,12,15,13,14,11,8,10,9,5,7,4,6,3,2,0,1,14,12,15,13,9,8,11,10}; 
-   const uint8_t lane_dq_p2[l_dqmax]={13,15,12,14,11,9,10,8,13,12,14,15,10,9,11,8,5,6,7,4,2,3,0,1,10,9,8,11,13,12,15,14,15,12,13,14,11,10,9,8,7,6,4,5,1,0,3,2,0,2,1,3,5,6,4,7,5,7,6,4,1,0,2,3,1,2,3,0,7,6,5,4,9,10,8,11,12,15,14,13};
-   const uint8_t lane_dq_p3[l_dqmax]={4,5,6,7,0,1,3,2,12,13,15,14,8,9,10,11,10,8,11,9,12,13,15,14,3,0,1,2,4,6,7,5,9,10,11,8,14,13,15,12,7,5,6,4,3,1,2,0,5,6,7,4,1,2,3,0,14,12,15,13,8,10,9,11,0,3,2,1,6,5,7,4,10,11,9,8,12,13,15,14};
-   const uint8_t dqs_dq_lane_p0[l_dqsmax]={4,0,12,8,12,8,12,8,8,12,4,0,4,0,4,0,0,4,8,12};
-   const uint8_t dqs_dq_lane_p1[l_dqsmax]={8,12,8,12,0,4,8,12,4,0,0,4,0,4,12,8,4,0,12,8};
-   const uint8_t dqs_dq_lane_p2[l_dqsmax]={12,8,12,8,4,0,8,12,12,8,4,0,0,4,4,0,0,4,8,12};
-   const uint8_t dqs_dq_lane_p3[l_dqsmax]={4,0,12,8,8,12,0,4,8,12,4,0,4,0,12,8,0,4,8,12};
-   const uint8_t block_p1[l_dqmax]={0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,2,2,2,2,2,2,2,2};
-   const uint8_t block_p0[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1};
-   const uint8_t block_p2[l_dqmax]={1,1,1,1,1,1,1,1,3,3,3,3,3,3,3,3,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,4,4,4,4,4,4,4,4};
-   const uint8_t block_p3[l_dqmax]={2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1};
-   const uint8_t block_dqs_p0[l_dqsmax]={2,2,2,2,0,0,3,3,4,4,3,3,4,4,1,1,0,0,1,1};
-   const uint8_t block_dqs_p1[l_dqsmax]={0,0,3,3,0,0,1,1,2,2,3,3,4,4,4,4,1,1,2,2};
-   const uint8_t block_dqs_p2[l_dqsmax]={1,1,3,3,0,0,0,0,2,2,2,2,3,3,4,4,1,1,4,4};
-   const uint8_t block_dqs_p3[l_dqsmax]={2,2,2,2,0,0,0,0,3,3,3,3,4,4,4,4,1,1,1,1};
-   uint8_t l_mbapos = 0;
-   uint8_t l_dram_width=0;
-   uint8_t l_lane=0;
-   uint8_t l_block=0;
-   uint8_t lane_dqs[4]={0}; //Initialize to 0.  This is a numerical ID of a false lane.  Another function catches this in mss_draminit_training.
-   uint8_t l_index=0;
-   uint8_t l_dq=0;
-   uint8_t l_phy_dq=0;
-   //uint8_t l_phy_block=0;
-   uint64_t l_scom_address_64=0x0ull;
-   uint8_t l_start_bit=0;
-   uint8_t l_len=0;
-   ip_type_t l_input_type;
-   ecmdDataBufferBase data_buffer_64(64);
-   uint8_t l_dimmtype=0;
-   uint8_t l_swizzle=0;
-   i_verbose=1; //Default the verbose flag high 
-      
-   rc = FAPI_ATTR_GET(ATTR_MSS_DQS_SWIZZLE_TYPE, &i_target_mba, l_swizzle); if(rc) return rc;
-      
-   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos); if(rc) return rc;
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc;
-         
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
-   
-      
-   if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ)
-   {
-   
-      if(i_port==0 && l_mbapos==0)
-      {
-	  
-	  if(flag==1){
-		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
-			if(phy_block==block_p0[l_phy_dq]){
-				if(phy_lane==lane_dq_p0[l_phy_dq]){
-				i_input_index=l_phy_dq;
-				}
-			}
-		}	
-	  }else{
-	  
-         l_lane=lane_dq_p0[i_input_index];
-		l_block=block_p0[i_input_index];	 
-		}
-      }
-      else if(i_port==1 && l_mbapos==0)
-      {
-	  
-	  if(flag==1){
-		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
-			if(phy_block==block_p1[l_phy_dq]){
-				if(phy_lane==lane_dq_p1[l_phy_dq]){
-				i_input_index=l_phy_dq;
-				}
-			}
-		}
-	}else{
-         l_lane=lane_dq_p1[i_input_index];
-         l_block=block_p1[i_input_index];	    
-		}
-	} 
-    else if(i_port==0 && l_mbapos==1)
-      {
-	  if(flag==1){
-		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
-			if(phy_block==block_p2[l_phy_dq]){
-				if(phy_lane==lane_dq_p2[l_phy_dq]){
-				i_input_index=l_phy_dq;
-				}
-			}
-		}
-	}else{
-	  
-         l_lane=lane_dq_p2[i_input_index];
-         l_block=block_p2[i_input_index];	
-		}
-    }
-    else
-      {
-	  if(flag==1){
-		for(l_phy_dq=0;l_phy_dq<l_dqmax;l_phy_dq++){
-			if(phy_block==block_p3[l_phy_dq]){
-				if(phy_lane==lane_dq_p3[l_phy_dq]){
-				i_input_index=l_phy_dq;
-				}
-			}
-		}
-	}else{
-		l_lane=lane_dq_p3[i_input_index];
-		l_block=block_p3[i_input_index];	
-	 }
-    }
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      } 
-      // if(i_input_type_e==RD_DQ)
-      // {
-         // l_input_type=RD_DQ_t;
-      // }
-      // else 	
-      // {
-         // l_input_type=WR_DQ_t;    
-      // }
-      
-            
-      // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
-      if(flag==0){
-	  phy_lane=l_lane;
-	  phy_block=l_block;
-	  }
-	  // out.scom_addr=l_scom_address_64;
-      // out.start_bit=l_start_bit;
-      // out.bit_length=l_len; 
-   }
-   
-   else if (i_input_type_e==WR_DQS ||  i_input_type_e==DQS_ALIGN)	    
-   {
-      if(i_port==0 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p0[i_input_index];
-         l_block=block_dqs_p0[i_input_index]; 
-      }
-             
-      else if(i_port==1 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p1[i_input_index];   
-         l_block=block_dqs_p1[i_input_index]; 
-      }   
-      else if(i_port==0 && l_mbapos==1)
-      {
-         l_dq=dqs_dq_lane_p2[i_input_index];   
-         l_block=block_dqs_p2[i_input_index]; 
-      }
-      else 
-      {
-         l_dq=dqs_dq_lane_p3[i_input_index];   
-         l_block=block_dqs_p3[i_input_index]; 
-      }
-       
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("dqs_dq_lane=%d",l_dq);
-      }
-      l_input_type=RD_CLK_t; 
-      rc=get_address(i_target_mba,i_port,i_rank_pair, l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("read clock address=%llx",l_scom_address_64);
-      }
-      rc=fapiGetScom(i_target_mba,l_scom_address_64,data_buffer_64);if(rc) return rc; 
-            
-      if(l_dram_width==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4)
-      {
-         
-         if (data_buffer_64.isBitSet(48))
-         {
-            lane_dqs[0]=16;
-            
-         }
-         else if(data_buffer_64.isBitSet(52))
-         { 
-            lane_dqs[0]=18;
-            
-         }
-        
-         if (data_buffer_64.isBitSet(49))
-         {
-            lane_dqs[1]=16;
-            
-         }
-     
-         else if (data_buffer_64.isBitSet(53))
-         {
-            lane_dqs[1]=18;
-            
-         }
-         
-         if (data_buffer_64.isBitSet(54))
-         {
-            lane_dqs[2]=20;
-            
-         }
-         else if (data_buffer_64.isBitSet(56))
-         {
-            lane_dqs[2]=22;
-           
-         }
-      
-         if (data_buffer_64.isBitSet(55))
-         {
-            lane_dqs[3]=20;
-         }
-         else if (data_buffer_64.isBitSet(57))   // else is not possible as one of them will definitely get set
-         {
-            lane_dqs[3]=22;
-          
-         }
-         if(i_verbose==1)
-         {
-            FAPI_INF("array is=%d and %d and %d and %d",lane_dqs[0],lane_dqs[1],lane_dqs[2],lane_dqs[3]);
-         }   
-         if(l_dq==0)
-         {
-            l_lane=lane_dqs[0];
-         }
-         else if(l_dq==4)
-         {
-            l_lane=lane_dqs[1];
-         }  
-         else if(l_dq==8)
-         {
-            l_lane=lane_dqs[2];
-         }
-         else 
-         {
-            l_lane=lane_dqs[3];
-         }
-         
-         if(i_verbose==1)
-         {
-            FAPI_INF("lane is=%d",l_lane); 
-         }
-      }			  
-   
-     
-      else
-      {   
-         if (data_buffer_64.isBitSet(48)&& data_buffer_64.isBitSet(49))
-         {		  
-            lane_dqs[l_index]=16;
-            l_index++; 		    
-         }
-         else if (data_buffer_64.isBitSet(52)&& data_buffer_64.isBitSet(53))
-         {		  
-            lane_dqs[l_index]=18;
-            l_index++; 		    
-         }
-         if (data_buffer_64.isBitSet(54)&& data_buffer_64.isBitSet(55))
-         {		  
-            lane_dqs[l_index]=20;
-            l_index++; 		    
-         }
-         else if (data_buffer_64.isBitSet(56)&& data_buffer_64.isBitSet(57))   // else is not possible as one of them will definitely get set
-         {		  
-            lane_dqs[l_index]=22;
-            l_index++; 		    
-         }
-         if(i_verbose==1)
-         {
-            FAPI_INF("array is=%d and %d",lane_dqs[0],lane_dqs[1]); 
-         } 
-         if((l_dq==0) || (l_dq==4))
-         {
-            l_lane=lane_dqs[0];
-         }
-         else 
-         {
-            l_lane=lane_dqs[1];
-         }
-         
-         if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-         {
-            if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7) || (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) || (i_input_index==17) || (i_input_index==19))
-            {
-               if(l_lane==16)
-               {
-                  l_lane=18;
-               }
-               else if(l_lane==18)
-               {
-                  l_lane=16;
-               }
-               
-               else if(l_lane==20)
-               {
-                  l_lane=22;
-               }
-               
-               else
-               {
-                  l_lane=20;
-               }
-               
-            }
-         }
-         
-         else
-         {
-            if((i_port==0) && (l_mbapos==0))
-            {
-               if(l_swizzle==1)
-               {
-                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==6))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                     
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                     
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  
-                  }   
-               }
-                           
-               else
-               {
-                  if((i_input_index==3) || (i_input_index==1) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                       
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                       
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  }   
-                          
-               }
-            }   
-            
-            else if((i_port==1) && (l_mbapos==0))
-            {
-               if(l_swizzle==1)
-               {
-                  if((i_input_index==2) || (i_input_index==0) || (i_input_index==4) || (i_input_index==17)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==7))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                     
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                  
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  }   
-               }
-               
-               else
-               {
-                  if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
-                  {
-                     if(l_lane==16)
-                     {
-                        l_lane=18;
-                     }
-                     else if(l_lane==18)
-                     {
-                        l_lane=16;
-                     }
-                     
-                     else if(l_lane==20)
-                     {
-                        l_lane=22;
-                     }
-                  
-                     else
-                     {
-                        l_lane=20;
-                     }
-                  }   
-               }
-            }
-                  
-                  
-            else
-            {
-               if((i_input_index==1) || (i_input_index==3) || (i_input_index==5) || (i_input_index==7)|| (i_input_index==9) || (i_input_index==11) || (i_input_index==13) || (i_input_index==15) ||  (i_input_index==17))
-               {
-                  if(l_lane==16)
-                  {
-                     l_lane=18;
-                  }
-                  else if(l_lane==18)
-                  {
-                     l_lane=16;
-                  }
-                  
-                  else if(l_lane==20)
-                  {
-                     l_lane=22;
-                  }
-                  
-                  else
-                  {
-                     l_lane=20;
-                  }
-               
-               }   
-            }
-            
-            
-            
-         }
-         if(i_verbose==1)
-         {
-            FAPI_INF("lane is=%d",l_lane);
-         }   
-      }  
-      
-      // if(i_input_type_e==WR_DQS)	  		  
-      // {
-         // l_input_type=WR_DQS_t;  
-      // }
-      // else
-      // {
-         // l_input_type=DQS_ALIGN_t;
-      // }
-      
-      // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
-	 if(flag==0){
-	 phy_lane=l_lane;
-	  phy_block=l_block;
-	  }
-	  // out.scom_addr=l_scom_address_64;
-      // out.start_bit=l_start_bit;
-      // out.bit_length=l_len; 
-   } else if (i_input_type_e==RD_DQS || i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK)	    
-   {
-      
-      
-      if(i_port==0 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p0[i_input_index];
-         l_block=block_dqs_p0[i_input_index]; 
-      }
-             
-      else if(i_port==1 && l_mbapos==0)
-      {
-         l_dq=dqs_dq_lane_p1[i_input_index];   
-         l_block=block_dqs_p1[i_input_index]; 
-      }   
-      else if(i_port==0 && l_mbapos==1)
-      {
-         l_dq=dqs_dq_lane_p2[i_input_index];   
-         l_block=block_dqs_p2[i_input_index]; 
-      }
-      else
-      {
-         l_dq=dqs_dq_lane_p3[i_input_index];   
-         l_block=block_dqs_p3[i_input_index]; 
-      }
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("dqs_dq_lane=%d",l_dq);
-      }   
-      if(l_dq==0)
-      {
-         l_lane=16;
-      }
-         
-      else if(l_dq==4)
-      {
-         l_lane=18;
-      }
-         
-      else if (l_dq==8)
-      {
-         l_lane=20;
-      }
-         
-      else
-      {
-         l_lane=22;
-      }
-      //FAPI_INF("here");
-      
-      if (i_input_type_e==DQS_GATE)
-      {
-         l_input_type=DQS_GATE_t;
-      }
-      
-      else if(i_input_type_e==RDCLK)
-      {
-         l_input_type=RDCLK_t;
-      }
-      
-      else if(i_input_type_e==RD_DQS)
-      {
-         l_input_type=RD_DQS_t;
-      }
-      
-      else
-      {
-         l_input_type=DQSCLK_t;
-      }
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("lane is=%d",l_lane);
-      }
-	  
-	  if(flag==0){
-	 phy_lane=l_lane;
-	  phy_block=l_block;
-	  }
-      
-      // rc=get_address(i_target_mba,i_port,i_rank_pair,l_input_type,l_block,l_lane,l_scom_address_64,l_start_bit,l_len); if(rc) return rc; 		 
-      // out.scom_addr=l_scom_address_64;
-      // out.start_bit=l_start_bit;
-      // out.bit_length=l_len; 
-   }   
-      
-   else
-   {
-      FAPI_ERR("Wrong input type specified (%d)", i_input_type_e);
-      const input_type_t & TYPE_PARAM = i_input_type_e;
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_C4_PHY_INVALID_INPUT);
-      return rc;
-   }  
-
-   return rc;
-}
- 
-fapi::ReturnCode mss_access_delay_reg_schmoo(const fapi::Target & i_target_mba,
-                                             access_type_t i_access_type_e,
-                                             uint8_t i_port_u8,
-                                             uint8_t i_rank_u8,
-                                             input_type_t i_input_type_e,
-                                             uint8_t i_input_index_u8,
-                                             uint8_t i_verbose,
-                                             uint16_t &io_value_u16)
-{
-   // Reference variables for Error FFDC
-   const fapi::Target & MBA_TARGET = i_target_mba;
-   const access_type_t & ACCESS_TYPE_PARAM = i_access_type_e;
-   const uint8_t & PORT_PARAM = i_port_u8;
-   const uint8_t & RANK_PARAM = i_rank_u8;
-   const input_type_t & TYPE_PARAM = i_input_type_e;
-   const uint8_t & INDEX_PARAM = i_input_index_u8;
-
-   fapi::ReturnCode rc; 
-    
-   const uint8_t max_rp=8; 
-   uint8_t l_val=0;
-   uint8_t l_dram_width=0;
-   scom_location l_out;
-   uint64_t l_scom_add=0x0ull;
-   uint32_t l_sbit=0;
-   uint32_t l_len=0;
-   uint32_t l_value_u32=0;
-   uint32_t rc_num=0;
-   ecmdDataBufferBase data_buffer_64(64);
-   ecmdDataBufferBase data_buffer_32(32);
-   ecmdDataBufferBase out(16);
-   uint32_t l_output=0;
-   uint32_t l_start=0;
-   uint8_t l_rank_pair=9;
-   uint8_t l_rankpair_table[max_rp]={255};
-   uint8_t l_dimmtype=0;
-   uint8_t l_block=0;
-   uint8_t l_lane=0;
-   uint8_t l_start_bit=0;
-   uint8_t l_len8=0;
-   input_type l_type;
-   uint8_t l_mbapos=0;
-   const uint8_t l_ISDIMM_dqmax=71;
-   const uint8_t l_CDIMM_dqmax=79;
-   uint8_t l_adr=0;
-    const uint8_t addr_max=19;
-   const uint8_t cmd_max=3;
-   const uint8_t cnt_max=20;
-   const uint8_t clk_max=8;
-   const uint8_t addr_lanep0[addr_max]={1,5,3,7,10,6,4,10,13,12,9,9,0,0,6,4,1,4,8};
-   const uint8_t addr_adrp0[addr_max]={2,1,1,3,1,3,1,3,3,3,2,3,2,3,1,0,3,3,3};
-   const uint8_t addr_lanep1[addr_max]={7,10,3,6,8,12,6,1,5,8,2,0,13,4,5,9,6,11,9};
-   const uint8_t addr_adrp1[addr_max]={2,1,2,2,1,3,1,1,1,3,1,3,2,3,3,0,0,1,3};
-   const uint8_t addr_lanep2[addr_max]={8,0,7,1,12,10,1,5,9,5,13,5,4,2,4,9,10,9,0};
-   const uint8_t addr_adrp2[addr_max]={2,2,3,0,3,1,2,0,1,3,2,1,0,2,3,3,3,2,1};
-   const uint8_t addr_lanep3[addr_max]={6,2,9,9,2,3,4,10,0,5,1,5,4,1,8,11,5,12,1};
-   const uint8_t addr_adrp3[addr_max]={3,0,2,3,2,0,3,3,1,2,2,1,0,1,3,3,0,3,0};
-   
-   const uint8_t cmd_lanep0[cmd_max]={2,11,5};
-   const uint8_t cmd_adrp0[cmd_max]={3,1,3};
-   const uint8_t cmd_lanep1[cmd_max]={2,10,10};
-   const uint8_t cmd_adrp1[cmd_max]={2,3,2};
-   const uint8_t cmd_lanep2[cmd_max]={3,11,3};
-   const uint8_t cmd_adrp2[cmd_max]={1,3,0};
-   const uint8_t cmd_lanep3[cmd_max]={7,10,7};
-   const uint8_t cmd_adrp3[cmd_max]={1,1,3};
-   
-   const uint8_t cnt_lanep0[cnt_max]={0,7,3,1,7,8,8,3,8,6,7,2,2,0,9,1,3,6,9,2};
-   const uint8_t cnt_adrp0[cnt_max]={1,0,3,0,2,2,1,2,0,0,1,2,0,0,1,1,0,2,0,1};
-   const uint8_t cnt_lanep1[cnt_max]={5,4,0,5,11,9,10,7,1,11,0,4,12,3,6,8,1,4,7,7};
-   const uint8_t cnt_adrp1[cnt_max]={2,1,2,0,2,1,0,1,3,0,1,0,2,1,3,0,2,2,3,0};
-   const uint8_t cnt_lanep2[cnt_max]={0,4,7,13,11,5,12,2,3,6,11,6,7,1,10,8,8,2,4,1};
-   const uint8_t cnt_adrp2[cnt_max]={0,1,1,3,1,2,2,0,2,2,0,1,2,1,0,3,1,1,2,3};
-   const uint8_t cnt_lanep3[cnt_max]={0,11,9,8,4,7,0,3,8,6,13,8,7,0,6,6,1,2,9,5};
-   const uint8_t cnt_adrp3[cnt_max]={2,1,0,2,1,0,3,2,0,1,3,1,2,0,0,2,3,1,1,3};
-   
-   const uint8_t clk_lanep0[clk_max]={10,11,11,10,4,5,13,12};
-   const uint8_t clk_adrp0[clk_max]={0,0,2,2,2,2,2,2};
-   const uint8_t clk_lanep1[clk_max]={3,2,8,9,1,0,3,2};
-   const uint8_t clk_adrp1[clk_max]={3,3,2,2,0,0,0,0};
-   const uint8_t clk_lanep2[clk_max]={11,10,6,7,2,3,8,9};
-   const uint8_t clk_adrp2[clk_max]={2,2,0,0,3,3,0,0};
-   const uint8_t clk_lanep3[clk_max]={3,2,13,12,10,11,11,10};
-   const uint8_t clk_adrp3[clk_max]={3,3,2,2,0,0,2,2};
-   
-   
-   rc = mss_getrankpair(i_target_mba,i_port_u8,i_rank_u8,&l_rank_pair,l_rankpair_table);   if(rc) return rc;
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimmtype); if(rc) return rc;
-   
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbapos);  if(rc) return rc;
-   
-   if(i_verbose==1)
-   {
-      FAPI_INF("dimm type=%d",l_dimmtype);
-      FAPI_INF("rank pair=%d",l_rank_pair);       
-   }
-   if(i_port_u8 >1)
-   {
-      FAPI_ERR("Wrong port specified (%d)", i_port_u8);
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-      return rc;
-   }
-   
-   if (l_mbapos>1)
-   {
-      FAPI_ERR("Bad position from ATTR_CHIP_UNIT_POS (%d)", l_mbapos);
-      const uint8_t & MBA_POS = l_mbapos;
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_BAD_MBA_POS);
-   }
-
-   if((l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4) || (l_dram_width ==fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8))   // Checking for dram width here so that checking can be skipped in called function
-   {
-      if(i_verbose==1)
-      {
-         FAPI_INF("dram width=%d",l_dram_width);
-      }
-   }
-   
-   else
-   {
-      FAPI_ERR("Bad dram width from ATTR_EFF_DRAM_WIDTH (%d)", l_dram_width);
-      const uint8_t & DRAM_WIDTH = l_dram_width;
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_BAD_DRAM_WIDTH);
-      return rc;
-   }
-   
-   if(i_input_type_e==RD_DQ || i_input_type_e==WR_DQ) 
-   {
-      
-      if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-      {
-         l_type=CDIMM_DQ;
-         
-         if(i_input_index_u8>l_CDIMM_dqmax)    
-         {
-            FAPI_ERR("CDIMM_DQ: Wrong input index specified (%d, max %d)" ,
-                     i_input_index_u8, l_CDIMM_dqmax);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-            return rc;
-         }
-            
-      }
-      else
-      {
-         l_type=ISDIMM_DQ;
-         if(i_input_index_u8>l_ISDIMM_dqmax)
-         {
-            FAPI_ERR("ISDIMM_DQ: Wrong input index specified (%d, max %d)",
-                     i_input_index_u8, l_ISDIMM_dqmax);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-            return rc;
-         }
-      }
-         
-      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc;
-      
-      if(i_verbose==1)
-      {
-         FAPI_INF("C4 value is=%d",l_val);
-      }   
-      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_out.scom_addr);
-         FAPI_INF("start bit=%d",l_out.start_bit);
-         FAPI_INF("length=%d",l_out.bit_length);
-      }   
-      l_scom_add=l_out.scom_addr;
-      l_sbit=l_out.start_bit;
-      l_len=l_out.bit_length;
-	 
-   }
-   
-   else if(i_input_type_e==ADDRESS)
-   {
-      if(i_input_index_u8<=18) // 19 delay values for Address
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=addr_lanep0[i_input_index_u8];
-            l_adr=addr_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=addr_lanep1[i_input_index_u8];
-            l_adr=addr_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=addr_lanep2[i_input_index_u8];
-            l_adr=addr_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=addr_lanep3[i_input_index_u8];
-            l_adr=addr_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=ADDRESS_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==DATA_DISABLE)
-   {
-      if(i_input_index_u8<=4) // 5 delay values for data bits disable register
-      {
-         l_block=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=DATA_DISABLE_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-      }
-      l_lane=0;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   
-   else if(i_input_type_e==COMMAND)
-   {
-      if(i_input_index_u8<=2) // 3 delay values for Command
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=cmd_lanep0[i_input_index_u8];
-            l_adr=cmd_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=cmd_lanep1[i_input_index_u8];
-            l_adr=cmd_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=cmd_lanep2[i_input_index_u8];
-            l_adr=cmd_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=cmd_lanep3[i_input_index_u8];
-            l_adr=cmd_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=COMMAND_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }   
-   
-    else if(i_input_type_e==CONTROL)
-   {
-      if(i_input_index_u8<=19) // 20 delay values for Control
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=cnt_lanep0[i_input_index_u8];
-            l_adr=cnt_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=cnt_lanep1[i_input_index_u8];
-            l_adr=cnt_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=cnt_lanep2[i_input_index_u8];
-            l_adr=cnt_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=cnt_lanep3[i_input_index_u8];
-            l_adr=cnt_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=CONTROL_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==CLOCK)
-   {
-      if(i_input_index_u8<=7) // 8 delay values for CLK
-      {
-         if((i_port_u8==0) && (l_mbapos==0))
-         {
-            l_lane=clk_lanep0[i_input_index_u8];
-            l_adr=clk_adrp0[i_input_index_u8];
-         }
-         else if((i_port_u8==1) && (l_mbapos==0))
-         {
-            l_lane=clk_lanep1[i_input_index_u8];
-            l_adr=clk_adrp1[i_input_index_u8]; 
-         }
-         else if((i_port_u8==0) && (l_mbapos==1))
-         {
-            l_lane=clk_lanep2[i_input_index_u8];
-            l_adr=clk_adrp2[i_input_index_u8]; 
-         }
-         else
-         {
-            l_lane=clk_lanep3[i_input_index_u8];
-            l_adr=clk_adrp3[i_input_index_u8]; 
-         }
-         
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=CLOCK_t;
-      if(i_verbose==1)
-      {
-         FAPI_INF("ADR=%d",l_adr);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      l_block=l_adr;
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }   
-   
-    
-   else if (i_input_type_e==RD_DQS || i_input_type_e==WR_DQS || i_input_type_e==DQS_ALIGN ||  i_input_type_e==DQS_GATE || i_input_type_e==RDCLK || i_input_type_e==DQSCLK)	    
-   {
-     
-      if(l_dimmtype==fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-      {
-         l_type=CDIMM_DQS;
-      }
-      else
-      {
-         l_type=ISDIMM_DQS;
-      }
-      
-      rc=rosetta_map(i_target_mba,i_port_u8,l_type,i_input_index_u8,i_verbose,l_val); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("C4 value is=%d",l_val);
-      }
-      rc=cross_coupled(i_target_mba,i_port_u8,l_rank_pair,i_input_type_e,l_val,i_verbose,l_out); if(rc) return rc;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_out.scom_addr);
-         FAPI_INF("start bit=%d",l_out.start_bit);
-         FAPI_INF("length=%d",l_out.bit_length); 
-      }
-      l_scom_add=l_out.scom_addr;
-      l_sbit=l_out.start_bit;
-      l_len=l_out.bit_length;   
-         
-   }
-   
-   
-   else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4) 
-   {
-      if(i_input_type_e==RAW_RDCLK_0)
-      {
-         l_block=0;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_1)
-      {
-         l_block=1;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_2)
-      {
-         l_block=2;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_3)
-      {
-         l_block=3;
-      }
-      
-      else
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3) // 4 delay values for RDCLK 
-      {
-         l_lane=i_input_index_u8;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;
-      }
-     
-      ip_type_t l_input=RAW_RDCLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4)
-   {
-      if(i_input_type_e==RAW_DQSCLK_0)
-      {
-         l_block=0;
-      }
-      
-      else if(i_input_type_e==RAW_DQSCLK_1)
-      {
-         l_block=1;
-      }
-      
-      else if(i_input_type_e==RAW_DQSCLK_2)
-      {
-         l_block=2;
-      }
-      
-      else if(i_input_type_e==RAW_DQSCLK_3)
-      {
-         l_block=3;
-      }
-      
-      else
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3) // 4 delay values for DQSCLK
-      {
-         l_lane=i_input_index_u8;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      ip_type_t l_input=RAW_DQSCLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-         
-   else if(i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4)
-   {
-      if(i_input_type_e==RAW_WR_DQ_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_WR_DQ_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_WR_DQ_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_WR_DQ_3)
-      {
-         l_block=3;
-      }
-      else
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=15) // 16 Write delay values for DQ bits
-      {
-         l_lane=i_input_index_u8;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-     
-      ip_type_t l_input=RAW_WR_DQ;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4)
-   {
-      if(i_input_type_e==RAW_RD_DQ_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_RD_DQ_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_RD_DQ_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_RD_DQ_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=15)   // 16 read delay values for DQ bits
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_RD_DQ;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4)
-   {
-      if(i_input_type_e==RAW_RD_DQS_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_RD_DQS_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_RD_DQS_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_RD_DQS_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3) // 4 Read DQS delay values 
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      
-      ip_type_t l_input=RAW_RD_DQS;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4)
-   {
-      if(i_input_type_e==RAW_DQS_ALIGN_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_DQS_ALIGN_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_DQS_ALIGN_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_DQS_ALIGN_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3)     // 4 DQS alignment delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;
-      }
-      ip_type_t l_input=RAW_DQS_ALIGN;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   
-   else if(i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4)
-   {
-      if(i_input_type_e==RAW_WR_DQS_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_WR_DQS_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_WR_DQS_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_WR_DQS_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-      if(i_input_index_u8<=3)      // 4 Write DQS delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_WR_DQS;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   else if(i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4)
-   {
-      if(i_input_type_e==RAW_SYS_CLK_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_SYS_CLK_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_SYS_CLK_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_SYS_CLK_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      } 
-      if(i_input_index_u8==0) // 1 system clock delay value
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_SYS_CLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_SYS_ADDR_CLK)
-   {
-      if(i_input_index_u8<=1)   // 1 system address clock delay value
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_SYS_ADDR_CLKS0S1;
-      if(i_verbose==1)
-      {
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   
-   else if(i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4)
-   {
-      if(i_input_type_e==RAW_WR_CLK_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_WR_CLK_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_WR_CLK_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_WR_CLK_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      } 
-      if(i_input_index_u8==0)           //  1 Write clock delay value
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_WR_CLK;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-   
-   else if(i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3)
-   {
-      if(i_input_type_e==RAW_ADDR_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_ADDR_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_ADDR_2)
-      {
-         l_block=2;
-      }
-      else 
-      {
-         l_block=3;
-      }
-      if(i_input_index_u8<=15)      //  16 Addr delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_ADDR;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   }
-  
-   else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4)
-   {
-      if(i_input_type_e==RAW_DQS_GATE_0)
-      {
-         l_block=0;
-      }
-      else if(i_input_type_e==RAW_DQS_GATE_1)
-      {
-         l_block=1;
-      }
-      else if(i_input_type_e==RAW_DQS_GATE_2)
-      {
-         l_block=2;
-      }
-      else if(i_input_type_e==RAW_DQS_GATE_3)
-      {
-         l_block=3;
-      }
-      else 
-      {
-         l_block=4;
-      }
-              
-      if(i_input_index_u8<=3)     // 4 Gate Delay values
-      {
-         l_lane=i_input_index_u8;
-      }
-      else
-      {
-         FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc; 
-      }
-      ip_type_t l_input=RAW_DQS_GATE;
-      if(i_verbose==1)
-      {
-         FAPI_INF("block=%d",l_block);
-         FAPI_INF("lane=%d",l_lane);
-      }
-      rc=get_address(i_target_mba,i_port_u8,l_rank_pair,l_input,l_block,l_lane,l_scom_add,l_start_bit,l_len8); if(rc) return rc;
-      l_sbit=l_start_bit;    
-      l_len=l_len8;
-      if(i_verbose==1)
-      {
-         FAPI_INF("scom_address=%llX",l_scom_add);
-         FAPI_INF("start bit=%d",l_start_bit);
-         FAPI_INF("length=%d",l_len8); 
-      }
-   } 
-   
-   else
-   {
-      FAPI_ERR("Wrong input index specified (%d)", i_input_index_u8);
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-      return rc;
-   } 
-     
-   if(i_access_type_e==READ)   
-   {
-      rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc;
-      rc_num= rc_num | data_buffer_64.extractToRight(&l_output,l_sbit,l_len);
-      if(rc_num)
-      {
-        FAPI_ERR( "ecmd error on l_scom_add extract");       
-	rc.setEcmdError(rc_num);
-        return rc;
-      }    
-	  	rc_num  = data_buffer_32.setWord(0,l_output);if(rc_num) return rc;
-io_value_u16=data_buffer_32.getHalfWord(1);
-      //io_value_u32=l_output;
-	  
-      //FAPI_INF(" Abhijit Delay value=%d and original=%d",io_value_u16,l_output);
-   }
-   
-   else if(i_access_type_e==WRITE)
-   {
-      
-      if(i_input_type_e==RD_DQ || i_input_type_e==RD_DQS || i_input_type_e==RAW_RD_DQ_0 || i_input_type_e==RAW_RD_DQ_1 || i_input_type_e==RAW_RD_DQ_2 || i_input_type_e==RAW_RD_DQ_3 || i_input_type_e==RAW_RD_DQ_4 || i_input_type_e==RAW_RD_DQS_0 || i_input_type_e==RAW_RD_DQS_1 || i_input_type_e==RAW_RD_DQS_2 || i_input_type_e==RAW_RD_DQS_3 || i_input_type_e==RAW_RD_DQS_4
-      || i_input_type_e==RAW_SYS_ADDR_CLK || i_input_type_e==RAW_SYS_CLK_0 || i_input_type_e==RAW_SYS_CLK_1 || i_input_type_e==RAW_SYS_CLK_2 || i_input_type_e==RAW_SYS_CLK_3 || i_input_type_e==RAW_SYS_CLK_4 || i_input_type_e==RAW_WR_CLK_0 || i_input_type_e==RAW_WR_CLK_1 || i_input_type_e==RAW_WR_CLK_2 || i_input_type_e==RAW_WR_CLK_3 || i_input_type_e==RAW_WR_CLK_4
-      || i_input_type_e==RAW_ADDR_0 || i_input_type_e==RAW_ADDR_1 || i_input_type_e==RAW_ADDR_2 || i_input_type_e==RAW_ADDR_3 || i_input_type_e==RAW_DQS_ALIGN_0 || i_input_type_e==RAW_DQS_ALIGN_1 || i_input_type_e==RAW_DQS_ALIGN_2 || i_input_type_e==RAW_DQS_ALIGN_3 || i_input_type_e==RAW_DQS_ALIGN_4
-      || i_input_type_e==DQS_ALIGN || i_input_type_e==COMMAND || i_input_type_e==ADDRESS || i_input_type_e==CONTROL || i_input_type_e==CLOCK )   
-      {
-         l_start=25;   // l_start is starting bit of delay value in the register. There are different registers and each register has a different field for delay
-      }
-      else if(i_input_type_e==WR_DQ || i_input_type_e==WR_DQS || i_input_type_e==RAW_WR_DQ_0 || i_input_type_e==RAW_WR_DQ_1 || i_input_type_e==RAW_WR_DQ_2 || i_input_type_e==RAW_WR_DQ_3 || i_input_type_e==RAW_WR_DQ_4 || i_input_type_e==RAW_WR_DQS_0 || i_input_type_e==RAW_WR_DQS_1 || i_input_type_e==RAW_WR_DQS_2 || i_input_type_e==RAW_WR_DQS_3 || i_input_type_e==RAW_WR_DQS_4 )
-      {
-         l_start=22;
-      }
-   
-      else if(i_input_type_e==RAW_DQS_GATE_0 || i_input_type_e==RAW_DQS_GATE_1 || i_input_type_e==RAW_DQS_GATE_2 || i_input_type_e==RAW_DQS_GATE_3 || i_input_type_e==RAW_DQS_GATE_4 || i_input_type_e==DQS_GATE)
-      {
-         l_start=29;
-      }
-      
-      else if(i_input_type_e==RAW_RDCLK_0 || i_input_type_e==RAW_RDCLK_1 || i_input_type_e==RAW_RDCLK_2 || i_input_type_e==RAW_RDCLK_3 || i_input_type_e==RAW_RDCLK_4 || i_input_type_e==RDCLK || i_input_type_e==RAW_DQSCLK_0 || i_input_type_e==RAW_DQSCLK_1 || i_input_type_e==RAW_DQSCLK_2 || i_input_type_e==RAW_DQSCLK_3 || i_input_type_e==RAW_DQSCLK_4 || i_input_type_e==DQSCLK)
-      {
-         l_start=30;  
-      }
-      
-      else if(i_input_type_e==DATA_DISABLE)
-      {
-         l_start=16;
-      }
-      
-      else
-      {
-         FAPI_ERR("Wrong input type specified (%d)", i_input_type_e);
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_ACCESS_DELAY_REG_SCHMOO_INVALID_INPUT);
-         return rc;      
-      }
-      if(i_verbose==1)
-      {
-         FAPI_INF("value given=%d",io_value_u16);
-      }
-      rc_num  = data_buffer_32.setHalfWord(1,io_value_u16);if(rc_num) return rc;
-	  l_value_u32  = data_buffer_32.getWord(0);
-	  
-	 // FAPI_INF("\n Abhijit the original passed=%d and the changed=%d ",io_value_u16,l_value_u32);
-      rc=fapiGetScom(i_target_mba,l_scom_add,data_buffer_64);if(rc) return rc;	  
-      rc_num=data_buffer_64.insert(l_value_u32,l_sbit,l_len,l_start);
-      if(rc_num)
-      {
-        FAPI_ERR( "ecmd error on l_scom_add extract");       
-	rc.setEcmdError(rc_num);
-        return rc;
-      }    
-      rc=fapiPutScom(i_target_mba,l_scom_add,data_buffer_64); if(rc) return rc;
-   }
-   return rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
deleted file mode 100644
index 6cb8156fe..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H
+++ /dev/null
@@ -1,355 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_access_delay_reg.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-//$Id: mss_access_delay_reg.H,v 1.12 2014/01/24 17:22:16 sasethur Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_demo_access_delay_reg.H
-// *! DESCRIPTION : Header file for mss_access_delay_reg.
-// *! OWNER NAME  : Saurabh Chadha    Email: sauchadh@in.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.12  | mjjones  |20-Jan-14| RAS Review Updates
-//   1.1   | sauchadh |15-Oct-12| First Draft.
-//------------------------------------------------------------------------------
-
-
-#ifndef MSS_ACCESS_DELAY_REG_H_
-#define MSS_ACCESS_DELAY_REG_H_
-
-//------------------------------------------------------------------------------
-// My Includes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//----------------------------------------------------------------------
-// ENUMs   
-//----------------------------------------------------------------------
-enum access_type_t {
-   READ = 0,
-   WRITE = 1
-};
-
-enum input_type_t {
-   WR_DQ,
-   RAW_WR_DQ_0,
-   RAW_WR_DQ_1,
-   RAW_WR_DQ_2,
-   RAW_WR_DQ_3,
-   RAW_WR_DQ_4,
-   RD_DQ,
-   RAW_RD_DQ_0,
-   RAW_RD_DQ_1,
-   RAW_RD_DQ_2,
-   RAW_RD_DQ_3,
-   RAW_RD_DQ_4,
-   WR_DQS,
-   RAW_WR_DQS_0,
-   RAW_WR_DQS_1,
-   RAW_WR_DQS_2,
-   RAW_WR_DQS_3,
-   RAW_WR_DQS_4,
-   RD_DQS,
-   RAW_RD_DQS_0,
-   RAW_RD_DQS_1,
-   RAW_RD_DQS_2,
-   RAW_RD_DQS_3,
-   RAW_RD_DQS_4,
-   RAW_SYS_ADDR_CLK,
-   RAW_SYS_CLK_0,
-   RAW_SYS_CLK_1,
-   RAW_SYS_CLK_2,
-   RAW_SYS_CLK_3,
-   RAW_SYS_CLK_4,
-   RAW_WR_CLK_0,
-   RAW_WR_CLK_1,
-   RAW_WR_CLK_2,
-   RAW_WR_CLK_3,
-   RAW_WR_CLK_4,
-   RAW_ADDR_0,
-   RAW_ADDR_1,
-   RAW_ADDR_2,
-   RAW_ADDR_3,
-   DQS_GATE,
-   RAW_DQS_GATE_0,
-   RAW_DQS_GATE_1,
-   RAW_DQS_GATE_2,
-   RAW_DQS_GATE_3,
-   RAW_DQS_GATE_4,
-   DQS_ALIGN,
-   RAW_DQS_ALIGN_0,
-   RAW_DQS_ALIGN_1,
-   RAW_DQS_ALIGN_2,
-   RAW_DQS_ALIGN_3,
-   RAW_DQS_ALIGN_4,
-   RAW_RDCLK_0,
-   RAW_RDCLK_1,
-   RAW_RDCLK_2,
-   RAW_RDCLK_3,
-   RAW_RDCLK_4,
-   RDCLK,
-   RAW_DQSCLK_0,
-   RAW_DQSCLK_1,
-   RAW_DQSCLK_2,
-   RAW_DQSCLK_3,
-   RAW_DQSCLK_4,
-   DQSCLK,
-   COMMAND,
-   CONTROL,
-   CLOCK,
-   ADDRESS,
-   DATA_DISABLE
-   };
-
-enum ip_type_t {
-   WR_DQ_t,
-   RAW_WR_DQ,
-   RD_DQ_t,
-   RAW_RD_DQ,
-   WR_DQS_t,
-   RAW_WR_DQS,
-   RD_DQS_t,
-   RAW_RD_DQS,
-   RD_CLK_t,
-   RAW_SYS_ADDR_CLKS0S1,
-   RAW_SYS_CLK,
-   RAW_WR_CLK,
-   RAW_ADDR,
-   DQS_GATE_t,
-   RAW_DQS_GATE,
-   DQS_ALIGN_t,
-   RAW_DQS_ALIGN,
-   RDCLK_t,
-   RAW_RDCLK,
-   DQSCLK_t,
-   RAW_DQSCLK,
-   COMMAND_t,
-   CONTROL_t,
-   CLOCK_t,
-   ADDRESS_t,
-   DATA_DISABLE_t
-};
-
-
-enum input_type {
-  ISDIMM_DQ,
-  ISDIMM_DQS,
-  CDIMM_DQS,
-  CDIMM_DQ,
-  GL_NET_DQ,
-  GL_NET_DQS
-};
-
-struct scom_location {
-   uint64_t scom_addr;
-   uint8_t start_bit;
-   uint8_t bit_length;
-};
-
-
-typedef fapi::ReturnCode (*mss_access_delay_reg_FP_t)(const fapi::Target &,
-                                                      access_type_t,
-                                                      uint8_t,
-                                                      uint8_t,
-                                                      input_type_t,
-                                                      uint8_t,
-                                                      uint8_t,
-                                                      uint32_t &);
-
-extern "C" {
-
-/**
- * @brief Reads or Writes delay values
- *
- * @param[in] i_target_mba     Reference to centaur.mba target
- * @param[in] i_access_type_e  Access type (READ or WRITE)
- * @param[in] i_port_u8        Port number
- * @param[in] i_rank_u8        Rank number
- * @param[in] i_input_type_e   Input type (from input_type_t)
- * @param[in] i_input_index_u8 Input index
- * @param[in] i_verbose        1 = Verbose tracing
- * @param[io] io_value_u32     READ=input, WRITE=output
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_access_delay_reg_schmoo(const fapi::Target & i_target_mba,
-                                             access_type_t i_access_type_e,
-                                             uint8_t i_port_u8,
-                                             uint8_t i_rank_u8,
-                                             input_type_t i_input_type_e,
-                                             uint8_t i_input_index_u8,
-                                             uint8_t i_verbose,
-                                             uint16_t &io_value_u32);
-
-/**
- * @brief Reads or Writes delay values
- *
- * @param[in] i_target_mba     Reference to centaur.mba target
- * @param[in] i_access_type_e  Access type (READ or WRITE)
- * @param[in] i_port_u8        Port number
- * @param[in] i_rank_u8        Rank number
- * @param[in] i_input_type_e   Input type (from input_type_t)
- * @param[in] i_input_index_u8 Input index
- * @param[in] i_verbose        1 = Verbose tracing
- * @param[io] io_value_u32     READ=input, WRITE=output
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_access_delay_reg(const fapi::Target & i_target_mba,
-                                      access_type_t i_access_type_e,
-                                      uint8_t i_port_u8,
-                                      uint8_t i_rank_u8,
-                                      input_type_t i_input_type_e,
-                                      uint8_t i_input_index_u8,
-                                      uint8_t i_verbose,
-                                      uint32_t &io_value_u32);
-
-/**
- * @brief cross_coupled
- *
- * @param[in]  i_target_mba   Reference to centaur.mba target
- * @param[in]  i_port         Port number
- * @param[in]  i_rank_pair    Rank pair
- * @param[in]  i_input_type_e Input type (from input_type_t)
- * @param[in]  i_input_index  Input index
- * @param[in]  i_verbose      1 = Verbose tracing
- * @param[out] out            Output
- *
- * @return ReturnCode
- */
-fapi::ReturnCode cross_coupled(const fapi::Target & i_target_mba,
-                               uint8_t i_port,
-                               uint8_t i_rank_pair,
-                               input_type_t i_input_type_e,
-                               uint8_t i_input_index,
-                               uint8_t i_verbose,
-                               scom_location& out);
-
-/**
- * @brief mss_c4_phy
- *
- * @param[in] i_target_mba   Reference to centaur.mba target
- * @param[in] i_port         Port number
- * @param[in] i_rank_pair    Rank pair
- * @param[in] i_input_type_e Input type (from input_type_t)
- * @param[in] i_input_index  Input index
- * @param[in] i_verbose      1 = Verbose tracing
- * @param[io] phy_lane       PHY Lane
- * @param[io] phy_block      PHY Block
- * @param[in] flag           Flag
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_c4_phy(const fapi::Target & i_target_mba,
-                            uint8_t i_port,
-                            uint8_t i_rank_pair,
-                            input_type_t i_input_type_e,
-                            uint8_t &i_input_index,
-                            uint8_t i_verbose,
-                            uint8_t &phy_lane,
-                            uint8_t &phy_block,
-                            uint8_t flag);
-
-/**
- * @brief get_address
- *
- * @param[in]  i_target_mba      Reference to centaur.mba target
- * @param[in]  i_port            Port number
- * @param[in]  i_rank_pair       Rank pair
- * @param[in]  i_input_type_e    Input type (from input_type_t)
- * @param[in]  i_block           Block
- * @param[in]  i_lane            Lane
- * @param[out] o_scom_address_64 Output scom address
- * @param[out] o_start_bit       Output Start bit
- * @param[out] o_len             Output length
- *
- * @return ReturnCode
- */
-fapi::ReturnCode get_address(const fapi::Target & i_target_mba,
-                             uint8_t i_port,
-                             uint8_t i_rank_pair,
-                             ip_type_t i_input_type_e,
-                             uint8_t i_block,
-                             uint8_t i_lane,
-                             uint64_t &o_scom_address_64,
-                             uint8_t &o_start_bit,
-                             uint8_t &o_len);
-
-/**
- * @brief Returns C4 bit for the corresponding ISDIMM bit
- *
- * @param[in]  i_target_mba   Reference to centaur.mba target
- * @param[in]  i_port         Port number
- * @param[in]  i_input_type_e Input type (from input_type_t)
- * @param[in]  i_input_index  Input index
- * @param[in]  i_verbose      1 = Verbose tracing
- * @param[out] o_value        Output C4 bit
- *
- * @return ReturnCode
- */
-fapi::ReturnCode rosetta_map(const fapi::Target & i_target_mba,
-                             uint8_t i_port,
-                             input_type i_input_type_e,
-                             uint8_t i_input_index,
-                             uint8_t i_verbose,
-                             uint8_t &o_value);
-
-/**
- * @brief Gets the rank pair
- *
- * @param[in]  i_target_mba     Reference to centaur.mba target
- * @param[in]  i_port           Port
- * @param[in]  i_rank           Rank
- * @param[out] o_rank_pair      Output rank pair
- * @param[out] o_rankpair_table Output rank pair table
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_getrankpair(const fapi::Target & i_target_mba,
-                                 uint8_t i_port,
-                                 uint8_t i_rank,
-                                 uint8_t *o_rank_pair,
-                                 uint8_t o_rankpair_table[]);
-
-} // extern "C"
-
-#endif // MSS_ACCESS_DELAY_REG_H
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C
deleted file mode 100644
index 9454c344d..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C
+++ /dev/null
@@ -1,2447 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_funcs.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_ddr4_funcs.C,v 1.15 2015/08/28 18:15:08 sglancy Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_ddr4_funcs.C
-// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures
-// *! OWNER NAME : jdsloat@us.ibm.com
-// *! BACKUP NAME : sglancy@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//         |          |         |
-//  1.15   | 08/28/15 | sglancy | Added RCs - addressed FW comments
-//  1.14   | 08/21/15 | sglancy | Fixed ODT initialization bug - ODT must be held low through ZQ cal 
-//  1.13   | 08/05/15 | kmack   | Commented out FAPI_DDR4 code
-//  1.12   | 07/31/15 | kmack   | Mostly removed and changed comments.  Reviewed some questions about the code. No real functional changes
-//         |          |         | Need new ATTRIBUTE, see comments with FIXME
-//  1.11   | 07/15/15 | sglancy | Addeded DDR4 Register functions and changes for DDR4 LRDIMM
-//  1.10   | 05/14/15 | sglancy | Addeded DDR4 Register functions and changes for DDR4 3DS
-//  1.7    | 03/14/14 | kcook   | Addeded DDR4 Register functions
-//  1.6    | 01/10/14 | kcook   | Updated Address mirroring swizzle (removed DIMM_TYPE_CDIMM) and
-//         |          |         | added DDR4 RDIMM support
-//  1.5    | 12/03/13 | kcook   | Updated VPD attributes.
-//  1.4    | 11/27/13 | bellows | Added using namespace fapi
-//  1.3    | 10/10/13 | bellows | Added required cvs id tag
-//  1.2    | 10/09/13 | jdsloat | Added CONSTs
-//  1.1    | 10/04/13 | jdsloat | First revision
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-#include <mss_funcs.H>
-#include <cen_scom_addresses.H>
-#include <mss_ddr4_funcs.H>
-
-using namespace fapi;
-
-//#ifdef FAPI_DDR4
-
-const uint8_t MAX_NUM_DIMMS = 2;
-const uint8_t MRS0_BA = 0;
-const uint8_t MRS1_BA = 1;
-const uint8_t MRS2_BA = 2;
-const uint8_t MRS3_BA = 3;
-const uint8_t MRS4_BA = 4;
-const uint8_t MRS5_BA = 5;
-const uint8_t MRS6_BA = 6;
-
-const uint8_t PORT_SIZE = 2;
-
-ReturnCode mss_ddr4_invert_mpr_write( Target& i_target_mba) {
-   ReturnCode rc;
-    uint32_t rank_number;
-
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    rc_num = rc_num | activate_1.setBit(0);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.clearBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.clearBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.clearBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    ecmdDataBufferBase mrs3(16);
-    uint16_t MRS3 = 0;
-    uint8_t mpr_op; // MPR Op
-
-    ecmdDataBufferBase data_buffer(64);
-
-    uint32_t io_ccs_inst_cnt = 0;
-
-    uint16_t num_ranks = 0;
-    uint8_t mpr_pattern = 0xAA;
-    
-    if(rc_num)
-    {
-    	rc.setEcmdError(rc_num);
-    	return rc;
-    }
-    
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t num_master_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, num_master_ranks_array);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target_mba, address_mirror_map);
-    if(rc) return rc;
-
-   uint8_t dram_stack[2][2];
-    rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, dram_stack);
-    if(rc) return rc;
-
-   for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) {
-      // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-      rc_num = rc_num | csn_8.setBit(0,8);
-      rc_num = rc_num | address_16.clearBit(0, 16);
-      rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-
-       FAPI_INF( "Stack Type in mss_ddr4_invert_mpr_write : %d\n", dram_stack[0][0]);
-      if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS)
-      {
-         FAPI_INF( "=============  Got in the 3DS stack loop =====================\n");
-         rc_num = rc_num | csn_8.clearBit(2,2);
-         rc_num = rc_num | csn_8.clearBit(6,2);
-        // COMMENT IN LATER!!!!!! rc_num = rc_num | cke_4.clearBit(1);
-      }
-
-      if(rc_num)
-      {
-          rc.setEcmdError(rc_num);
-          return rc;
-      }
-      rc = mss_ccs_inst_arry_0( i_target_mba,
-                                io_ccs_inst_cnt,
-                                address_16,
-                                bank_3,
-                                activate_1,
-                                rasn_1,
-                                casn_1,
-                                wen_1,
-                                cke_4,
-                                csn_8,
-                                odt_4,
-                                ddr_cal_type_4,
-                                l_port);
-      if(rc) return rc;
-      rc = mss_ccs_inst_arry_1( i_target_mba,
-                                io_ccs_inst_cnt,
-                                num_idles_16,
-                                num_repeat_16,
-                                data_20,
-                                read_compare_1,
-                                rank_cal_4,
-                                ddr_cal_enable_1,
-                                ccs_end_1);
-      if(rc) return rc;
-      io_ccs_inst_cnt ++;
-
-      for (uint8_t l_dimm = 0; l_dimm < MAX_NUM_DIMMS; l_dimm++) {
-         if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS)
-         {
-            num_ranks = num_master_ranks_array[l_port][l_dimm];
-         }
-         else {
-            num_ranks = num_ranks_array[l_port][l_dimm];
-         }
-
-         if (num_ranks == 0)
-         {
-            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", l_port, l_dimm, num_ranks);
-         }
-         else
-         {
-            // Rank 0-3
-            for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-            {
-
-                rc_num = rc_num | csn_8.setBit(0,8);
-                rc_num = rc_num | csn_8.clearBit(rank_number+4*l_dimm);
-                rc_num = rc_num | address_16.clearBit(0, 16);
-
-                // MRS CMD to CMD spacing = 12 cycles
-                rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16);
-                if(rc_num)
-                {
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-
-                if (l_port == 0) {
-                    rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer); // Need to look up Rank Group???
-		    if(rc) return rc;
-                }
-                else if ( l_port == 1 ) {
-                    rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer); // Need to look up Rank Group???
-		    if(rc) return rc;
-                }
-
-                rc_num = rc_num | data_buffer.reverse();
-                rc_num = rc_num | mrs3.insert(data_buffer, 0, 16, 0);
-                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-
-                if(rc_num)
-                {
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-
-                FAPI_INF( "CURRENT MRS 3: 0x%04X", MRS3);
-
-                mpr_op = 0xff;
-
-                rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-
-                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                FAPI_INF( "Set data flow from MPR, New MRS 3: 0x%04X", MRS3);
-
-                if (rc_num)
-                {
-                    FAPI_ERR( " Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-
-
-                rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-
-                // Indicate B-Side DRAMS BG1=1
-                rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
-
-                rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                rc_num = rc_num | bank_3.flipBit(0,3);     // Invert BA0,BA1,BG0
-
-                if (rc_num)
-                {
-                    FAPI_ERR( " Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-
-
-                if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0))
-                {
-                    rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3);
-                    if(rc) return rc;
-                }
-
-                // Send out to the CCS array
-                rc = mss_ccs_inst_arry_0( i_target_mba,
-                                  io_ccs_inst_cnt,
-                                  address_16,
-                                  bank_3,
-                                  activate_1,
-                                  rasn_1,
-                                  casn_1,
-                                  wen_1,
-                                  cke_4,
-                                  csn_8,
-                                  odt_4,
-                                  ddr_cal_type_4,
-                                  l_port);
-                if(rc) return rc;
-                rc = mss_ccs_inst_arry_1( i_target_mba,
-                                  io_ccs_inst_cnt,
-                                  num_idles_16,
-                                  num_repeat_16,
-                                  data_20,
-                                  read_compare_1,
-                                  rank_cal_4,
-                                  ddr_cal_enable_1,
-                                  ccs_end_1);
-                if(rc) return rc;
-                io_ccs_inst_cnt ++;
-
-
-                // Write pattern to MPR register
-                //Command structure setup
-                rc_num = rc_num | cke_4.flushTo1();
-                rc_num = rc_num | rasn_1.setBit(0);
-                rc_num = rc_num | casn_1.clearBit(0);
-                rc_num = rc_num | wen_1.clearBit(0);
-
-
-                //Final setup
-                rc_num = rc_num | odt_4.flushTo0();
-                rc_num = rc_num | ddr_cal_type_4.flushTo0();
-                rc_num = rc_num | activate_1.setBit(0);
-
-
-                //CCS Array 1 Setup
-                rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16);
-                rc_num = rc_num | num_repeat_16.flushTo0();
-                rc_num = rc_num | data_20.flushTo0();
-                rc_num = rc_num | read_compare_1.flushTo0();
-                rc_num = rc_num | rank_cal_4.flushTo0();
-                rc_num = rc_num | ddr_cal_enable_1.flushTo0();
-                rc_num = rc_num | ccs_end_1.flushTo0();
-
-                rc_num = rc_num | address_16.clearBit(0, 16);
-                rc_num = rc_num | address_16.insertFromRight(mpr_pattern,0, 8);
-
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-
-                // Indicate B-Side DRAMS BG1=1
-                rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
-
-                rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                rc_num = rc_num | bank_3.flipBit(0,3);     // Invert BA0,BA1,BG0
-
-                if (rc_num)
-                {
-                    FAPI_ERR( " Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-
-
-                if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0))
-                {
-                    rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3);
-                    if(rc) return rc;
-                }
-
-                FAPI_INF( "Writing MPR register with 0101 pattern");
-                // Send out to the CCS array
-                rc = mss_ccs_inst_arry_0( i_target_mba,
-                                  io_ccs_inst_cnt,
-                                  address_16,
-                                  bank_3,
-                                  activate_1,
-                                  rasn_1,
-                                  casn_1,
-                                  wen_1,
-                                  cke_4,
-                                  csn_8,
-                                  odt_4,
-                                  ddr_cal_type_4,
-                                  l_port);
-                if(rc) return rc;
-                rc = mss_ccs_inst_arry_1( i_target_mba,
-                                  io_ccs_inst_cnt,
-                                  num_idles_16,
-                                  num_repeat_16,
-                                  data_20,
-                                  read_compare_1,
-                                  rank_cal_4,
-                                  ddr_cal_enable_1,
-                                  ccs_end_1);
-                if(rc) return rc;
-                io_ccs_inst_cnt ++;
-
-                // Restore MR3 to normal MPR operation
-                //Command structure setup
-                rc_num = rc_num | cke_4.flushTo1();
-                rc_num = rc_num | rasn_1.clearBit(0);
-                rc_num = rc_num | casn_1.clearBit(0);
-                rc_num = rc_num | wen_1.clearBit(0);
-
-                rc_num = rc_num | read_compare_1.clearBit(0);
-
-                rc_num = rc_num | odt_4.flushTo0();
-                rc_num = rc_num | ddr_cal_type_4.flushTo0();
-                rc_num = rc_num | activate_1.setBit(0);
-
-                rc_num = rc_num | num_repeat_16.flushTo0();
-                rc_num = rc_num | data_20.flushTo0();
-                rc_num = rc_num | read_compare_1.flushTo0();
-                rc_num = rc_num | rank_cal_4.flushTo0();
-                rc_num = rc_num | ddr_cal_enable_1.flushTo0();
-                rc_num = rc_num | ccs_end_1.flushTo0();
-
-                rc_num = rc_num | address_16.clearBit(0, 16);
-
-                // MRS CMD to CMD spacing = 12 cycles
-                rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16);
-                if(rc_num)
-                {
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-
-                if (l_port == 0) {
-                    rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P0_0x8000C01F0301143F, data_buffer); // Need to look up Rank Group???
-		    if(rc) return rc;
-                }
-                else if ( l_port == 1 ) {
-                    rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_MR3_PRI_RP0_P1_0x8001C01F0301143F, data_buffer); // Need to look up Rank Group???
-		    if(rc) return rc;
-                }
-
-                rc_num = rc_num | data_buffer.reverse();
-                rc_num = rc_num | mrs3.insert(data_buffer, 0, 16, 0);
-                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-
-                if(rc_num)
-                {
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-
-                FAPI_INF( "CURRENT MRS 3: 0x%04X", MRS3);
-
-                mpr_op = 0x00;
-
-                rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-
-                rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-                FAPI_INF( "Set data flow from MPR, New MRS 3: 0x%04X", MRS3);
-
-                if (rc_num)
-                {
-                    FAPI_ERR( " Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-
-
-                rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-
-                // Indicate B-Side DRAMS BG1=1
-                rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
-
-                rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                rc_num = rc_num | bank_3.flipBit(0,3);     // Invert BA0,BA1,BG0
-
-
-                if (( address_mirror_map[l_port][l_dimm] & (0x08 >> rank_number) ) && (is_sim == 0))
-                {
-                    rc = mss_address_mirror_swizzle(i_target_mba, l_port, l_dimm, rank_number, address_16, bank_3);
-                    if(rc) return rc;
-                }
-
-
-                if (rc_num)
-                {
-                    FAPI_ERR( " Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-
-                // Send out to the CCS array
-                rc = mss_ccs_inst_arry_0( i_target_mba,
-                                  io_ccs_inst_cnt,
-                                  address_16,
-                                  bank_3,
-                                  activate_1,
-                                  rasn_1,
-                                  casn_1,
-                                  wen_1,
-                                  cke_4,
-                                  csn_8,
-                                  odt_4,
-                                  ddr_cal_type_4,
-                                  l_port);
-                if(rc) return rc;
-                rc = mss_ccs_inst_arry_1( i_target_mba,
-                                  io_ccs_inst_cnt,
-                                  num_idles_16,
-                                  num_repeat_16,
-                                  data_20,
-                                  read_compare_1,
-                                  rank_cal_4,
-                                  ddr_cal_enable_1,
-                                  ccs_end_1);
-                if(rc) return rc;
-                io_ccs_inst_cnt ++;
-
-             }
-          }
-      }
-   }
-
-   uint32_t NUM_POLL = 100;
-   rc = mss_execute_ccs_inst_array( i_target_mba, NUM_POLL, 60);
-
-   return rc;
-}
-
-ReturnCode mss_create_rcd_ddr4(const Target& i_target_mba) {
-   ReturnCode rc;
-   uint32_t rc_num = 0;
-
-   uint8_t l_rcd_cntl_word_0_1;
-   uint8_t l_rcd_cntl_word_2;
-   uint8_t l_rcd_cntl_word_3;
-   uint8_t l_rcd_cntl_word_4;
-   uint8_t l_rcd_cntl_word_5;
-   uint8_t l_rcd_cntl_word_6_7;
-   uint8_t l_rcd_cntl_word_8_9;
-   uint8_t l_rcd_cntl_word_10;
-   uint8_t l_rcd_cntl_word_11;
-   uint8_t l_rcd_cntl_word_12;
-   uint8_t l_rcd_cntl_word_13;
-   uint8_t l_rcd_cntl_word_14;
-   uint8_t l_rcd_cntl_word_15;
-   uint64_t l_rcd_cntl_word_0_15;
-   uint8_t stack_type[PORT_SIZE][MAX_NUM_DIMMS];
-   uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][MAX_NUM_DIMMS];
-   uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][MAX_NUM_DIMMS];
-   uint8_t l_num_master_ranks_per_dimm_u8array[PORT_SIZE][MAX_NUM_DIMMS];
-   uint8_t l_dimm_type_u8;
-   uint8_t l_dram_width_u8;
-   ecmdDataBufferBase data_buffer_8(8);
-   ecmdDataBufferBase data_buffer_64(64);
-
-
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM,&i_target_mba, l_num_master_ranks_per_dimm_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, stack_type); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc;
-
-   uint64_t l_attr_eff_dimm_cntl_word_x;
-
-   uint8_t l_rcd_cntl_word_1x;
-   uint8_t l_rcd_cntl_word_2x;
-   uint8_t l_rcd_cntl_word_3x;
-   uint8_t l_rcd_cntl_word_7x;
-   uint8_t l_rcd_cntl_word_8x;
-   uint8_t l_rcd_cntl_word_9x;
-   uint8_t l_rcd_cntl_word_Ax;
-   uint8_t l_rcd_cntl_word_Bx;
-
-   //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change)
-   rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_attr_eff_dimm_cntl_word_x); if(rc) return rc;
-
-   fapi::Target l_target_centaur;
-   uint32_t l_mss_freq = 0;
-   uint32_t l_mss_volt = 0;
-   rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc;
-
-   for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) {
-      for (uint8_t l_dimm = 0; l_dimm < MAX_NUM_DIMMS; l_dimm++) {
-
-         // Global Features, Clock Driver Enable Control Words
-         l_rcd_cntl_word_0_1   = 0x00;
-
-         // Timing and IBT Control Word
-         l_rcd_cntl_word_2 = 0;
-
-         // CA and CS Signals Driver Characteristics Control Word
-         if (l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1) {
-            l_rcd_cntl_word_3   = 6; // QxCS0_n...QxCS3_n Outputs strong drive, Address/Command moderate drive
-         } else {
-            l_rcd_cntl_word_3   = 5; // QxCS0_n...QxCS3_n Outputs moderate drive, Address/Command moderate drive
-         }
-
-         l_rcd_cntl_word_4     = 5;    // QxODT0...QxODT1 and QxCKE0...QxCKE1 Output Drivers moderate drive
-         l_rcd_cntl_word_5     = 5;    // Clock Y1_t, Y1_c, Y3_t, Y3_c and Y0_t, Y0_c, Y2_t, Y2_c Output Drivers moderate drive
-
-         // Command Space Control Word
-         l_rcd_cntl_word_6_7 = 0xf0; // No op
-         // Input/Output Configuration, Power Saving Settings Control Words
-         if(stack_type[l_port][l_dimm] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) {
-            //no master ranks found, then program to disable all CIDs
-            //master ranks should always be found so this is a bit weird - might want to throw an error here
-            if(l_num_master_ranks_per_dimm_u8array[l_port][l_dimm] == 0) {
-               l_rcd_cntl_word_8_9 = 0x30;
-            }
-            //determine stack density - 2H, 4H, or 8H
-            else {
-               uint8_t stack_height = l_num_ranks_per_dimm_u8array[l_port][l_dimm] / l_num_master_ranks_per_dimm_u8array[l_port][l_dimm];
-               FAPI_INF("3DS RCD set stack_height: %d",stack_height);
-               if(stack_height == 8) {
-                  l_rcd_cntl_word_8_9 = 0x00;
-               }
-               else if(stack_height == 4) {
-                  l_rcd_cntl_word_8_9 = 0x10;
-               }
-               else if(stack_height == 2) {
-                  l_rcd_cntl_word_8_9 = 0x20;
-               }
-               //weird, we shouldn't have 1H stacks
-               else {
-                  l_rcd_cntl_word_8_9 = 0x30;
-               }
-            }
-         }
-
-         //LR DIMM and 4 ranks
-         else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4) {
-            FAPI_INF("Creating RCD value for F0rC08 - LRDDIMM and 4 ranks -> 0x10");
-            l_rcd_cntl_word_8_9 = 0x10;
-         }
-         else {
-            l_rcd_cntl_word_8_9 = 0x30;
-         }
-
-         // RDIMM Operating Speed Control Word
-         if ( l_mss_freq <= 1733 ) {        // 1600
-            l_rcd_cntl_word_10 = 0;
-         } else if ( l_mss_freq <= 2000 ) { // 1866
-            l_rcd_cntl_word_10 = 1;
-         } else if ( l_mss_freq <= 2266 ) { // 2133
-            l_rcd_cntl_word_10 = 2;
-         } else if ( l_mss_freq <= 2533 ) { // 2400
-            l_rcd_cntl_word_10 = 3;
-         } else if ( l_mss_freq <= 2800 ) { // 2666
-            l_rcd_cntl_word_10 = 4;
-         } else if ( l_mss_freq <= 3333 ) { // 3200
-            l_rcd_cntl_word_10 = 5;
-         } else {
-            FAPI_ERR("Invalid LRDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
-         }
-
-         // Operating Voltage VDD and VREFCA Source Control Word
-         if ( l_mss_volt >= 1120 ) {        // 1.2V
-            l_rcd_cntl_word_11 = 14;
-         } else if ( l_mss_volt >= 1020 ) { // 1.0xV
-            l_rcd_cntl_word_11 = 15;
-         } else {
-            FAPI_ERR("Invalid LRDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
-         }
-
-         // Training Control Word
-         l_rcd_cntl_word_12 = 0;
-
-         // DIMM Configuration Control words
-         data_buffer_8.clearBit(0,8);
-         if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) {
-            rc_num |= data_buffer_8.setBit(3); // Direct QuadCS mode
-         }
-         if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM  ) {
-            rc_num |= data_buffer_8.setBit(1);
-         }
-         if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) {
-            rc_num |= data_buffer_8.setBit(0); // Address mirroring for MRS commands
-         }
-
-         rc_num |= data_buffer_8.extractToRight( &l_rcd_cntl_word_13, 0, 4);
-
-         // Parity Control Word
-         l_rcd_cntl_word_14 = 0;
-
-         // Command Latency Adder Control Word
-         if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM  ) {
-            l_rcd_cntl_word_15 = 4; // 0nCk latency adder
-         }
-         else {
-            l_rcd_cntl_word_15 = 0; // 1nCk latency adder with DB control bus
-         }
-
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_0_1, 0 , 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_2,   8 , 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_3,   12, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_4,   16, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_5,   20, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_6_7, 24, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_8_9, 32, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_10,  40, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_11,  44, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_12,  48, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_13,  52, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_14,  56, 4);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_15,  60, 4);
-	 
-	 if(rc_num)
-         {
-             rc.setEcmdError(rc_num);
-             return rc;
-         }
-	 
-         l_rcd_cntl_word_0_15 = data_buffer_64.getDoubleWord(0); if(rc) return rc;
-         l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] =  l_rcd_cntl_word_0_15;
-
-         // Set RCD control word x
-
-         // RC1x Internal VREF CW
-         l_rcd_cntl_word_1x = 0;
-
-         // RC2x I2C Bus Control Word
-         l_rcd_cntl_word_2x = 0;
-
-         // RC3x Fine Granularity  RDIMM Operating Speed Control Word
-         if ( l_mss_freq > 1240 && l_mss_freq < 3200 ) {
-            l_rcd_cntl_word_3x = int ((l_mss_freq - 1250) / 20);
-         } else {
-            FAPI_ERR("Invalid DIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
-         }
-
-         // RC7x IBT Control Word
-         l_rcd_cntl_word_7x = 0;
-
-         // RC8x ODT Input Buffer/IBT, QxODT Output Buffer and Timing Control Word
-         l_rcd_cntl_word_8x = 0;
-
-         // RC9x QxODT[1:0] Write Pattern CW
-         l_rcd_cntl_word_9x = 0;
-
-         // RCAx QxODT[1:0] Read Pattern CW
-         l_rcd_cntl_word_Ax = 0;
-
-         // RCBx IBT and MRS Snoop CW
-         if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) {
-            l_rcd_cntl_word_Bx = 4;
-         } else {
-            l_rcd_cntl_word_Bx = 7;
-         }
-
-
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_1x, 0 , 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_2x, 8 , 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_3x, 16, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_7x, 24, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_8x, 32, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_9x, 40, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_Ax, 48, 8);
-         rc_num |= data_buffer_64.insertFromRight(&l_rcd_cntl_word_Bx, 56, 8);
-	 if(rc_num)
-         {
-             rc.setEcmdError(rc_num);
-             return rc;
-         }
-
-         l_attr_eff_dimm_cntl_word_x = data_buffer_64.getDoubleWord(0); if(rc) return rc;
-         FAPI_INF("from data buffer: rcd control word X %llX", l_attr_eff_dimm_cntl_word_x );
-
-      } // end dimm loop
-   } // end port loop
-
-   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-
-   //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change)
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_attr_eff_dimm_cntl_word_x); if(rc) return rc;
-
-   return rc;
-
-}
-
-ReturnCode mss_rcd_load_ddr4(
-            Target& i_target,
-            uint32_t i_port_number,
-            uint32_t& io_ccs_inst_cnt
-            )    {
-
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t dimm_number;
-    uint32_t rcd_number;
-
-    ecmdDataBufferBase rcd_cntl_wrd_4(8);
-    ecmdDataBufferBase rcd_cntl_wrd_8(8);
-    ecmdDataBufferBase rcd_cntl_wrd_64(64);
-    uint16_t num_ranks;
-
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.setBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.setBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.setBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-    
-    if(rc_num)
-    {
-    	rc.setEcmdError(rc_num);
-    	return rc;
-    }
-	 
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    uint64_t rcd_array[2][2]; //[port][dimm]
-    uint8_t dimm_type;
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array);
-    if(rc) return rc;
-
-    uint32_t cntlx_offset[]= {1,2,3,7,8,9,10,11};
-    // Dummy attribute for addtitional cntl words
-    uint64_t rcdx_array;
-    // uint64_t rcdx_array[2][2];
-
-    //FIXME: ATTR_MCBIST_MAX_TIMEOUT is being used until firmware is ready with a new attribute, ATTR_EFF_LRDIMM_WORD_X (subject to change)
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target, rcdx_array);
-    if(rc) return rc;
-
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-    io_ccs_inst_cnt ++;
-
-    FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORDS FOR %s PORT %d +++++++++++++++++++++", i_target.toEcmdString(), i_port_number);
-
-    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-        num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-        if (num_ranks == 0)
-        {
-            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks);
-        }
-        else
-        {
-            FAPI_INF( "RCD SETTINGS FOR %s PORT%d DIMM%d ", i_target.toEcmdString(), i_port_number, dimm_number);
-            FAPI_INF( "RCD Control Word: 0x%016llX", rcd_array[i_port_number][dimm_number]);
-            //FAPI_INF( "RCD Control Word X: 0x%016llX", rcdx_array[i_port_number][dimm_number]);
-            FAPI_INF( "RCD Control Word X: 0x%016llX", rcdx_array);
-
-            if (rc_num)
-            {
-                FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                rc_buff.setEcmdError(rc_num);
-                return rc_buff;
-            }
-
-            // ALL active CS lines at a time.
-            rc_num = rc_num | csn_8.setBit(0,8);
-            rc_num = rc_num | csn_8.clearBit(0); //DCS0_n is LOW
-
-            // DBG1, DBG0, DBA1, DBA0 = 4`b0111
-            rc_num = rc_num | bank_3.setBit(0, 3);
-            // DACT_n is HIGH
-            rc_num = rc_num | activate_1.setBit(0);
-            // RAS_n/CAS_n/WE_n are LOW
-            rc_num = rc_num | rasn_1.clearBit(0);
-            rc_num = rc_num | casn_1.clearBit(0);
-            rc_num = rc_num | wen_1.clearBit(0);
-
-            // Propogate through the 16, 4-bit control words
-            for ( rcd_number = 0; rcd_number<= 15; rcd_number++)
-            {
-                //rc_num = rc_num | bank_3.clearBit(0, 3);
-                rc_num = rc_num | address_16.clearBit(0, 16);
-
-                rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcd_array[i_port_number][dimm_number]);
-                rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*rcd_number, 4);
-
-                //control word number code bits A[7:4]
-                rc_num = rc_num | address_16.insert(rcd_number, 7, 1, 28);
-                rc_num = rc_num | address_16.insert(rcd_number, 6, 1, 29);
-                rc_num = rc_num | address_16.insert(rcd_number, 5, 1, 30);
-                rc_num = rc_num | address_16.insert(rcd_number, 4, 1, 31);
-
-                //control word values RCD0 = A0, RCD1 = A1, RCD2 = A2, RCD3 = A3
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 0, 1, 3);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 1, 1, 2);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 2, 1, 1);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 0);
-
-                // Send out to the CCS array
-                //if ( dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM && (rcd_number == 2 || rcd_number == 10) )
-                if ( rcd_number == 2 || rcd_number == 10 )
-                {
-                   rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words
-                }
-                else
-                {
-                   rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
-                }
-
-
-                if (rc_num)
-                {
-                   FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                   rc_buff.setEcmdError(rc_num);
-                   return rc_buff;
-                }
-
-                rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                if(rc) return rc;
-                rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                if(rc) return rc;
-                io_ccs_inst_cnt ++;
-
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-            }
-
-            // 8-bit Control words
-            for ( rcd_number = 0; rcd_number<= 7; rcd_number++)
-            {
-                //rc_num = rc_num | bank_3.clearBit(0, 3);
-                rc_num = rc_num | address_16.clearBit(0, 16);
-
-                //rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcdx_array[i_port_number][dimm_number]);
-                rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, rcdx_array);
-                rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_8, 8*rcd_number, 8);
-
-                //control word number code bits A[11:8]
-                rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 11, 1, 28);
-                rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number], 10, 1, 29);
-                rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number],  9, 1, 30);
-                rc_num = rc_num | address_16.insert(cntlx_offset[rcd_number],  8, 1, 31);
-
-                //control word values RCD0 = A0, RCD1 = A1, RCD2 = A2, RCD3 = A3, RCD4=A4, RCD5=A5, RCD6=A6, RCD7=A7
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 0, 1, 7);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 1, 1, 6);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 2, 1, 5);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 3, 1, 4);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 4, 1, 3);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 5, 1, 2);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 6, 1, 1);
-                rc_num = rc_num | address_16.insert(rcd_cntl_wrd_8, 7, 1, 0);
-
-                // Send out to the CCS array
-                if ( rcd_number == 2 ) // CW RC3x
-                {
-                   rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 4000, 0 , 16 ); // wait tStab for clock timing rcd words
-                }
-                else
-                {
-                   rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
-                }
-
-                if (rc_num)
-                {
-                   FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                   rc_buff.setEcmdError(rc_num);
-                   return rc_buff;
-                }
-
-                rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                if(rc) return rc;
-                rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                if(rc) return rc;
-                io_ccs_inst_cnt ++;
-
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-            }
-        }
-    }
-    
-    rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1);
-    if(rc)
-    {
-        FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-        return rc;
-    }
-    io_ccs_inst_cnt = 0;
-    
-    rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-    if(rc)
-    {
-        FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-        return rc;
-    }
-    
-    
-    return rc;
-}
-
-ReturnCode mss_mrs_load_ddr4(
-            Target& i_target,
-            uint32_t i_port_number,
-            uint32_t& io_ccs_inst_cnt
-            )
-{
-
-    uint32_t dimm_number;
-    uint32_t rank_number;
-    uint32_t mrs_number;
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    rc_num = rc_num | activate_1.setBit(0);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.clearBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.clearBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.clearBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.clearBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.clearBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_idles_16_vref_train(16);
-    rc_num = rc_num | num_idles_16_vref_train.insertFromRight((uint32_t) 160, 0, 16);
-
-    if(rc_num) {
-       rc.setEcmdError(rc_num);
-       return rc;
-    }
-
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    ecmdDataBufferBase mrs0(16);
-    ecmdDataBufferBase mrs1(16);
-    ecmdDataBufferBase mrs2(16);
-    ecmdDataBufferBase mrs3(16);
-    ecmdDataBufferBase mrs4(16);
-    ecmdDataBufferBase mrs5(16);
-    ecmdDataBufferBase mrs6(16);
-    ecmdDataBufferBase mrs6_train_on(16);
-    uint16_t MRS0 = 0;
-    uint16_t MRS1 = 0;
-    uint16_t MRS2 = 0;
-    uint16_t MRS3 = 0;
-    uint16_t MRS4 = 0;
-    uint16_t MRS5 = 0;
-    uint16_t MRS6 = 0;
-
-    ecmdDataBufferBase data_buffer(64);
-
-
-    uint16_t num_ranks = 0;
-
-    FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number);
-
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t num_master_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_master_ranks_array);
-    if(rc) return rc;
-
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-
-    // WORKAROUNDS
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.setBit(51);
-    if(rc_num) {
-       rc.setEcmdError(rc_num);
-       return rc;
-    }
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    rc = fapiGetScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.clearBit(48);
-    if(rc_num) {
-       rc.setEcmdError(rc_num);
-       return rc;
-    }
-    rc = fapiPutScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);
-    if(rc) return rc;
-
-
-    uint8_t dram_stack[2][2];
-    rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack);
-    if(rc) return rc;
-
-    FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]);
-    if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS)
-    {
-       FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!! =====================\n");
-       rc_num = rc_num | csn_8.clearBit(2,2);
-       rc_num = rc_num | csn_8.clearBit(6,2);
-       // COMMENT IN LATER!!!! rc_num = rc_num | cke_4.clearBit(1);
-       if(rc_num) {
-          rc.setEcmdError(rc_num);
-          return rc;
-       }
-    }
-
-    //Lines commented out in the following section are waiting for xml attribute adds
-    //MRS0
-    uint8_t dram_bl;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl);
-    if(rc) return rc;
-    uint8_t read_bt; //Read Burst Type
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt);
-    if(rc) return rc;
-    uint8_t dram_cl;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl);
-    if(rc) return rc;
-    uint8_t test_mode; //TEST MODE
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode);
-    if(rc) return rc;
-    uint8_t dll_reset; //DLL Reset
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset);
-    if(rc) return rc;
-    uint8_t dram_wr; //DRAM write recovery
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr);
-    if(rc) return rc;
-    uint8_t dram_rtp; //DRAM RTP - read to precharge
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_rtp);
-    if(rc) return rc;
-    uint8_t dll_precharge; //DLL Control For Precharge
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge);
-    if(rc) return rc;
-
-    if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8)
-    {
-        dram_bl = 0x00;
-    }
-    else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF)
-    {
-        dram_bl = 0x80;
-    }
-    else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4)
-    {
-        dram_bl = 0x40;
-    }
-
-    uint8_t dram_wr_rtp = 0x00;
-    if ( (dram_wr == 10) )//&& (dram_rtp == 5) )
-    {
-        dram_wr_rtp = 0x00;
-    }
-    else if ( (dram_wr == 12) )//&& (dram_rtp == 6) )
-    {
-        dram_wr_rtp = 0x80;
-    }
-    else if ( (dram_wr == 13) )//&& (dram_rtp == 7) )
-    {
-        dram_wr_rtp = 0x40;
-    }
-    else if ( (dram_wr == 14) )//&& (dram_rtp == 8) )
-    {
-        dram_wr_rtp = 0xC0;
-    }
-    else if ( (dram_wr == 18) )//&& (dram_rtp == 9) )
-    {
-        dram_wr_rtp = 0x20;
-    }
-    else if ( (dram_wr == 20) )//&& (dram_rtp == 10) )
-    {
-        dram_wr_rtp = 0xA0;
-    }
-    else if ( (dram_wr == 24) )//&& (dram_rtp == 12) )
-    {
-        dram_wr_rtp = 0x60;
-    }
-
-    if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL)
-    {
-        read_bt = 0x00;
-    }
-    else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE)
-    {
-        read_bt = 0xFF;
-    }
-
-    if ((dram_cl > 8)&&(dram_cl < 17))
-    {
-        dram_cl = dram_cl - 9;
-    }
-    else if ((dram_cl > 17)&&(dram_cl < 25))
-    {
-        dram_cl = (dram_cl >> 1) - 1;
-    }
-    dram_cl = mss_reverse_8bits(dram_cl);
-
-    if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL)
-    {
-        test_mode = 0x00;
-    }
-    else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST)
-    {
-        test_mode = 0xFF;
-    }
-
-    if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_YES)
-    {
-        dll_reset = 0xFF;
-    }
-    else if (dll_reset == ENUM_ATTR_EFF_DRAM_DLL_RESET_NO)
-    {
-        dll_reset = 0x00;
-    }
-
-    if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
-    {
-        dll_precharge = 0x00;
-    }
-    else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT)
-    {
-        dll_precharge = 0xFF;
-    }
-
-    //MRS1
-    uint8_t dll_enable; //DLL Enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable);
-    if(rc) return rc;
-    uint8_t out_drv_imp_cntl[2][2];
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl);
-    if(rc) return rc;
-    uint8_t dram_rtt_nom[2][2][4];
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom);
-    if(rc) return rc;
-    uint8_t dram_al;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al);
-    if(rc) return rc;
-    uint8_t wr_lvl; //write leveling enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl);
-    if(rc) return rc;
-    uint8_t tdqs_enable; //TDQS Enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable);
-    if(rc) return rc;
-    uint8_t q_off; //Qoff - Output buffer Enable
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off);
-    if(rc) return rc;
-
-    if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE)
-    {
-        dll_enable = 0x00;
-    }
-    else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE)
-    {
-        dll_enable = 0xFF;
-    }
-
-    if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE)
-    {
-        dram_al = 0x00;
-    }
-    else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1)
-    {
-        dram_al = 0x80;
-    }
-    else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2)
-    {
-        dram_al = 0x40;
-    }
-
-    if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE)
-    {
-        wr_lvl = 0x00;
-    }
-    else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE)
-    {
-        wr_lvl = 0xFF;
-    }
-
-    if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE)
-    {
-        tdqs_enable = 0x00;
-    }
-    else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE)
-    {
-        tdqs_enable = 0xFF;
-    }
-
-    if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE)
-    {
-        q_off = 0xFF;
-    }
-    else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE)
-    {
-        q_off = 0x00;
-    }
-
-    //MRS2
-
-    uint8_t lpasr; // Low Power Auto Self-Refresh -- new not yet supported
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_LPASR, &i_target, lpasr);
-    if(rc) return rc;
-    uint8_t cwl; // CAS Write Latency
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl);
-    if(rc) return rc;
-    uint8_t dram_rtt_wr[2][2][4];
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr);
-    if(rc) return rc;
-    uint8_t write_crc; // CAS Write Latency
-    rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_CRC, &i_target, write_crc);
-    if(rc) return rc;
-
-    if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL)
-    {
-        lpasr = 0x00;
-    }
-    else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED)
-    {
-        lpasr = 0x80;
-    }
-    else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED)
-    {
-        lpasr = 0x40;
-    }
-    else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR)
-    {
-        lpasr = 0xFF;
-    }
-
-    if ((cwl > 8)&&(cwl < 13))
-    {
-        cwl = cwl - 9;
-    }
-    else if ((cwl > 13)&&(cwl < 19))
-    {
-        cwl = (cwl >> 1) - 3;
-    }
-    else
-    {
-       //no correcct value for CWL was found
-       FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing...");
-       cwl = 0;
-    }
-    cwl = mss_reverse_8bits(cwl);
-
-    if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE)
-    {
-        write_crc = 0xFF;
-    }
-    else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE)
-    {
-        write_crc = 0x00;
-    }
-
-    //MRS3
-    uint8_t mpr_op; // MPR Op
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op);
-    if(rc) return rc;
-    uint8_t mpr_page; // MPR Page Selection  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page);
-    if(rc) return rc;
-    uint8_t geardown_mode; // Gear Down Mode  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode);
-    if(rc) return rc;
-    uint8_t dram_access; // per dram accessibility  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_PER_DRAM_ACCESS, &i_target, dram_access);
-    if(rc) return rc;
-    uint8_t temp_readout; // Temperature sensor readout  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout);
-    if(rc) return rc;
-    uint8_t fine_refresh; // fine refresh mode  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh);
-    if(rc) return rc;
-    uint8_t wr_latency; // write latency for CRC and DM  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency);
-    if(rc) return rc;
-    uint8_t read_format; // MPR READ FORMAT  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format);
-    if(rc) return rc;
-
-    if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE)
-    {
-        mpr_op = 0xFF;
-    }
-    else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE)
-    {
-        mpr_op = 0x00;
-    }
-
-    mpr_page = mss_reverse_8bits(mpr_page);
-
-    if (dram_access == ENUM_ATTR_EFF_PER_DRAM_ACCESS_ENABLE)
-    {
-        dram_access = 0xFF;
-    }
-    else if (dram_access == ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE)
-    {
-        dram_access = 0x00;
-    }
-
-    if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF)
-    {
-         geardown_mode = 0x00;
-    }
-    else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER)
-    {
-         geardown_mode = 0xFF;
-    }
-
-    if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE)
-    {
-        temp_readout = 0xFF;
-    }
-    else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE)
-    {
-        temp_readout = 0x00;
-    }
-
-    if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL)
-    {
-        fine_refresh = 0x00;
-    }
-    else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X)
-    {
-        fine_refresh = 0x80;
-    }
-    else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X)
-    {
-        fine_refresh = 0x40;
-    }
-    else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X)
-    {
-        fine_refresh = 0xA0;
-    }
-    else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X)
-    {
-        fine_refresh = 0x60;
-    }
-
-    if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK)
-    {
-        wr_latency = 0x00;
-    }
-    else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK)
-    {
-        wr_latency = 0x80;
-    }
-    else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK)
-    {
-        wr_latency = 0xC0;
-    }
-
-    if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL)
-    {
-        read_format = 0x00;
-    }
-    else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL)
-    {
-        read_format = 0x80;
-    }
-    else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED)
-    {
-        read_format = 0x40;
-    }
-    else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP)
-    {
-        read_format = 0xC0;
-    }
-
-    //MRS4
-    uint8_t max_pd_mode; // Max Power down mode -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_MAX_POWERDOWN_MODE, &i_target, max_pd_mode);
-    if(rc) return rc;
-    uint8_t temp_ref_range; // Temp ref range -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_RANGE, &i_target, temp_ref_range);
-    if(rc) return rc;
-    uint8_t temp_ref_mode; // Temp controlled ref mode -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_MODE, &i_target, temp_ref_mode);
-    if(rc) return rc;
-    uint8_t vref_mon; // Internal Vref Monitor -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_INT_VREF_MON, &i_target, vref_mon);
-    if(rc) return rc;
-    uint8_t cs_cmd_latency; // CS to CMD/ADDR Latency -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CS_CMD_LATENCY, &i_target, cs_cmd_latency);
-    if(rc) return rc;
-    uint8_t ref_abort; // Self Refresh Abort -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_SELF_REF_ABORT, &i_target, ref_abort);
-    if(rc) return rc;
-    uint8_t rd_pre_train_mode; // Read Pre amble Training Mode -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE_TRAIN, &i_target, rd_pre_train_mode);
-    if(rc) return rc;
-    uint8_t rd_preamble; // Read Pre amble -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE, &i_target, rd_preamble);
-    if(rc) return rc;
-    uint8_t wr_preamble; // Write Pre amble -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_WR_PREAMBLE, &i_target, wr_preamble);
-    if(rc) return rc;
-
-    if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE)
-    {
-        max_pd_mode = 0xF0;
-    }
-    else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE)
-    {
-        max_pd_mode = 0x00;
-    }
-
-    if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL)
-    {
-        temp_ref_range = 0x00;
-    }
-    else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND)
-    {
-        temp_ref_range = 0xFF;
-    }
-
-    if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE)
-    {
-        temp_ref_mode = 0x80;
-    }
-    else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE)
-    {
-        temp_ref_mode = 0x00;
-    }
-
-    if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE)
-    {
-        vref_mon = 0xFF;
-    }
-    else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE)
-    {
-        vref_mon = 0x00;
-    }
-
-
-    if ( cs_cmd_latency == 3)
-    {
-        cs_cmd_latency = 0x80;
-    }
-    else if (cs_cmd_latency == 4)
-    {
-        cs_cmd_latency = 0x40;
-    }
-    else if (cs_cmd_latency == 5)
-    {
-        cs_cmd_latency = 0xC0;
-    }
-    else if (cs_cmd_latency == 6)
-    {
-        cs_cmd_latency = 0x20;
-    }
-    else if (cs_cmd_latency == 8)
-    {
-        cs_cmd_latency = 0xA0;
-    }
-
-    if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE)
-    {
-        ref_abort = 0xFF;
-    }
-    else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE)
-    {
-        ref_abort = 0x00;
-    }
-
-    if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE)
-    {
-        rd_pre_train_mode = 0xFF;
-    }
-    else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE)
-    {
-        rd_pre_train_mode = 0x00;
-    }
-
-    if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK)
-    {
-        rd_preamble = 0x00;
-    }
-    else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK)
-    {
-        rd_preamble = 0xFF;
-    }
-
-    if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK)
-    {
-        wr_preamble = 0x00;
-    }
-    else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK)
-    {
-        wr_preamble = 0xFF;
-    }
-
-
-    //MRS5
-    uint8_t ca_parity_latency; //C/A Parity Latency Mode  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_LATENCY , &i_target, ca_parity_latency);
-    if(rc) return rc;
-    uint8_t crc_error_clear; //CRC Error Clear  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CRC_ERROR_CLEAR , &i_target, crc_error_clear);
-    if(rc) return rc;
-    uint8_t ca_parity_error_status; //C/A Parity Error Status  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_ERROR_STATUS , &i_target, ca_parity_error_status);
-    if(rc) return rc;
-    uint8_t odt_input_buffer; //ODT Input Buffer during power down  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_ODT_INPUT_BUFF , &i_target, odt_input_buffer);
-    if(rc) return rc;
-    uint8_t rtt_park[2][2][4]; //RTT_Park value  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_RTT_PARK , &i_target, rtt_park);
-    if(rc) return rc;
-    uint8_t ca_parity; //CA Parity Persistance Error  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY , &i_target, ca_parity);
-    if(rc) return rc;
-    uint8_t data_mask; //Data Mask  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_DATA_MASK , &i_target, data_mask);
-    if(rc) return rc;
-    uint8_t write_dbi; //Write DBI  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_DBI , &i_target, write_dbi);
-    if(rc) return rc;
-    uint8_t read_dbi; //Read DBI  -  NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_READ_DBI , &i_target, read_dbi);
-    if(rc) return rc;
-
-
-    if (ca_parity_latency == 4)
-    {
-        ca_parity_latency = 0x80;
-    }
-    else if (ca_parity_latency == 5)
-    {
-        ca_parity_latency = 0x40;
-    }
-    else if (ca_parity_latency == 6)
-    {
-        ca_parity_latency = 0xC0;
-    }
-    else if (ca_parity_latency == 8)
-    {
-        ca_parity_latency = 0x20;
-    }
-    else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE)
-    {
-        ca_parity_latency = 0x00;
-    }
-
-    if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR)
-    {
-        crc_error_clear = 0xFF;
-    }
-    else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR)
-    {
-        crc_error_clear = 0x00;
-    }
-
-    if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR)
-    {
-        ca_parity_error_status = 0xFF;
-    }
-    else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR)
-    {
-        ca_parity_error_status = 0x00;
-    }
-
-    if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED)
-    {
-        odt_input_buffer = 0x00;
-    }
-    else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED)
-    {
-        odt_input_buffer = 0xFF;
-    }
-
-
-    if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE)
-    {
-        ca_parity = 0xFF;
-    }
-    else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE)
-    {
-        ca_parity = 0x00;
-    }
-
-    if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE)
-    {
-        data_mask = 0x00;
-    }
-    else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE)
-    {
-        data_mask = 0xFF;
-    }
-
-    if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE)
-    {
-        write_dbi = 0x00;
-    }
-    else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE)
-    {
-        write_dbi = 0xFF;
-    }
-
-    if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE)
-    {
-        read_dbi = 0x00;
-    }
-    else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE)
-    {
-        read_dbi = 0xFF;
-    }
-
-    //MRS6
-    uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value   -  NEW
-    rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value);
-    if(rc) return rc;
-    uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range   -  NEW
-    rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range);
-    if(rc) return rc;
-    uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable  -  NEW
-    rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable);
-    if(rc) return rc;
-    uint8_t tccd_l; //tccd_l  -  NEW
-    rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l);
-    if(rc) return rc;
-    if (tccd_l == 4)
-    {
-        tccd_l = 0x00;
-    }
-    else if (tccd_l == 5)
-    {
-        tccd_l = 0x80;
-    }
-    else if (tccd_l == 6)
-    {
-        tccd_l = 0x40;
-    }
-    else if (tccd_l == 7)
-    {
-        tccd_l = 0xC0;
-    }
-    else if (tccd_l == 8)
-    {
-        tccd_l = 0x20;
-    }
-
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | cke_4.setBit(0,4);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-    if(rc_num) {
-       rc.setEcmdError(rc_num);
-       return rc;
-    }
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-    io_ccs_inst_cnt ++;
-
-    // Dimm 0-1
-    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-        //if the dram stack type is a 3DS dimm
-        if(dram_stack[i_port_number][dimm_number]  == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) {
-           FAPI_INF("DIMM is a 3DS type, using num_masetr_ranks_array");
-           num_ranks = num_master_ranks_array[i_port_number][dimm_number];
-        }
-        else {
-           num_ranks = num_ranks_array[i_port_number][dimm_number];
-        }
-
-        if (num_ranks == 0)
-        {
-            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks);
-        }
-        else
-        {
-            // Rank 0-3
-            for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-            {
-                    FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number);
-
-                    rc_num = rc_num | csn_8.setBit(0,8);
-                    rc_num = rc_num | address_16.clearBit(0, 16);
-
-                    //For DDR4:
-                    //Address 14 = Address 17, Address 15 = BG1
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_bl, 0, 2, 0);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 2, 1, 0);
-                    rc_num = rc_num | mrs0.insert((uint8_t) read_bt, 3, 1, 0);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_cl, 4, 3, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) test_mode, 7, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dll_reset, 8, 1);
-                    rc_num = rc_num | mrs0.insert((uint8_t) dram_wr_rtp, 9, 3);
-                    rc_num = rc_num | mrs0.insert((uint8_t) 0x00, 12, 4);
-
-                    rc_num = rc_num | mrs0.extractPreserve(&MRS0, 0, 16, 0);
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-
-                    if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20;
-                        FAPI_INF("DRAM RTT_NOM is configured for 240 OHM which is not supported.");
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0;
-                        FAPI_INF("DRAM RTT_NOM is configured for 48 OHM which is not supported.");
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120)
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40;
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x60;
-                        FAPI_INF("DRAM RTT_NOM is configured for 80 OHM which is not supported.");
-                    }
-                    else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported
-                    {
-                        dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xE0;
-                        FAPI_INF("DRAM RTT_NOM is configured for 34 OHM which is not supported.");
-                    }
-
-                    if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34)
-                    {
-                        out_drv_imp_cntl[i_port_number][dimm_number] = 0x00;
-                    }
-                    // Not currently supported
-                    else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported
-                    {
-                        out_drv_imp_cntl[i_port_number][dimm_number] = 0x80;
-                        FAPI_INF("DRAM RON is configured for 48 OHM which is not supported.");
-                    }
-
-                    //For DDR4:
-                    //Address 14 = Address 17, Address 15 = BG1
-                    rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 2, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 5, 2);
-                    rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 8, 3, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0);
-                    rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3);
-
-
-                    rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-
-
-                    if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80;
-                    }
-                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40;
-                    }
-                    else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ)
-                    {
-                        dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0xFF;
-                    }
-
-                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 0, 3);
-                    rc_num = rc_num | mrs2.insert((uint8_t) cwl, 3, 3);
-                    rc_num = rc_num | mrs2.insert((uint8_t) lpasr, 6, 2);
-                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 8, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2);
-                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 11, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) write_crc, 12, 1);
-                    rc_num = rc_num | mrs2.insert((uint8_t) 0x00, 13, 2);
-
-                    rc_num = rc_num | mrs2.extractPreserve(&MRS2, 0, 16, 0);
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-
-                    rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2);
-                    rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-                    rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1);
-                    rc_num = rc_num | mrs3.insert((uint8_t) dram_access, 4, 1);
-                    rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1);
-                    rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3);
-                    rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2);
-                    rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2);
-                    rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2);
-
-
-                    rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-
-                    rc_num = rc_num | mrs4.insert((uint8_t) 0x00, 0, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) max_pd_mode, 1, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) temp_ref_range, 2, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) temp_ref_mode, 3, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) vref_mon, 4, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) 0x00, 5, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) cs_cmd_latency, 6, 3);
-                    rc_num = rc_num | mrs4.insert((uint8_t) ref_abort, 9, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) rd_pre_train_mode, 10, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) rd_preamble, 11, 1);
-                    rc_num = rc_num | mrs4.insert((uint8_t) wr_preamble, 12, 1);
-                    rc_num = rc_num | mrs4.extractPreserve(&MRS4, 0, 16, 0);
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-
-
-                    //MRS5
-                    if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_DISABLE)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_60OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0x80;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_40OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0xC0;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_120OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0x40;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_240OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0x20;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_48OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0xA0;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_80OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0x60;
-                    }
-                    else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_34OHM)
-                    {
-                        rtt_park[i_port_number][dimm_number][rank_number] = 0xE0;
-                    }
-
-                    rc_num = rc_num | mrs5.insert((uint8_t) ca_parity_latency, 0, 2);
-                    rc_num = rc_num | mrs5.insert((uint8_t) crc_error_clear, 3, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) ca_parity_error_status, 4, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) odt_input_buffer, 5, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) rtt_park[i_port_number][dimm_number][rank_number], 6, 3);
-                    rc_num = rc_num | mrs5.insert((uint8_t) ca_parity, 9, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) data_mask, 10, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) write_dbi, 11, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) read_dbi, 12, 1);
-                    rc_num = rc_num | mrs5.insert((uint8_t) 0x00, 13, 2);
-
-
-                    rc_num = rc_num | mrs5.extractPreserve(&MRS5, 0, 16, 0);
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-
-                    //MRS6
-
-                    vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]);
-
-                    if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1)
-                    {
-                        vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2)
-                    {
-                        vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF;
-                    }
-
-                    if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE)
-                    {
-                        vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xFF;
-                    }
-                    else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE)
-                    {
-                        vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-
-                    rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6);
-                    rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1);
-                    rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1);
-                    rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2);
-                    rc_num = rc_num | mrs6.insert((uint8_t) tccd_l, 10, 3);
-                    rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2);
-
-                    rc_num = rc_num | mrs6_train_on.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6);
-                    rc_num = rc_num | mrs6_train_on.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1);
-                    rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0xff, 7, 1);
-                    rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0x00, 8, 2);
-                    rc_num = rc_num | mrs6_train_on.insert((uint8_t) tccd_l, 10, 3);
-                    rc_num = rc_num | mrs6_train_on.insert((uint8_t) 0x00, 13, 2);
-
-
-                    rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-
-                    FAPI_INF( "MRS 0: 0x%04X", MRS0);
-                    FAPI_INF( "MRS 1: 0x%04X", MRS1);
-                    FAPI_INF( "MRS 2: 0x%04X", MRS2);
-                    FAPI_INF( "MRS 3: 0x%04X", MRS3);
-                    FAPI_INF( "MRS 4: 0x%04X", MRS4);
-                    FAPI_INF( "MRS 5: 0x%04X", MRS5);
-                    FAPI_INF( "MRS 6: 0x%04X", MRS6);
-
-                    if (rc_num)
-                    {
-                        FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-                        rc_buff.setEcmdError(rc_num);
-                        return rc_buff;
-                    }
-
-                    // Only corresponding CS to rank
-                    rc_num = rc_num | csn_8.setBit(0,8);
-                    rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-		    
-		    if(rc_num) {
-		       rc.setEcmdError(rc_num);
-                       return rc;
-		    }
-		    
-                     uint8_t dram_stack[2][2];
-                    rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack);
-                    if(rc) return rc;
-
-                    FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]);
-                    if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS)
-                    {
-                       FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!=====================\n");
-                       rc_num = rc_num | csn_8.clearBit(2+4*dimm_number,2);
-                       // COMMENT IN LATER!!!! rc_num = rc_num | cke_4.clearBit(1);
-		       if(rc_num) {
-		          rc.setEcmdError(rc_num);
-                          return rc;
-		       }
-                    }
-
-                    // Propogate through the 4 MRS cmds
-                    for ( mrs_number = 0; mrs_number < 7; mrs_number++)
-                    {
-                        //mrs_number = 1;
-                        // Copying the current MRS into address buffer matching the MRS_array order
-                        // Setting the bank address
-                        if (mrs_number == 0)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 1)
-                        {
-
-                            rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 2)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs5, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 3)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs4, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 4)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 5)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
-                        }
-                        else if ( mrs_number == 6)
-                        {
-                            rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5);
-                        }
-                        //mrs_number = 7;
-
-                       if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-                       {
-                           rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-                           if(rc) return rc;
-                       }
-
-
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-
-                        // Send out to the CCS array
-                        rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                        if(rc) return rc;
-                        rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                        if(rc) return rc;
-                        io_ccs_inst_cnt ++;
-
-
-
-                    }
-
-                    // Address inversion for RCD
-                    if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
-                    {
-                       FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n");
-
-
-                       // Propogate through the 4 MRS cmds
-                       for ( mrs_number = 0; mrs_number < 7; mrs_number++)
-                       {
-                           //mrs_number = 1;
-                           // Copying the current MRS into address buffer matching the MRS_array order
-                           // Setting the bank address
-                           if (mrs_number == 0)
-                           {
-                               rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-                           }
-                           else if ( mrs_number == 1)
-                           {
-
-
-                               rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5);
-                           }
-                           else if ( mrs_number == 2)
-                           {
-                               rc_num = rc_num | address_16.insert(mrs5, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5);
-                           }
-                           else if ( mrs_number == 3)
-                           {
-                               rc_num = rc_num | address_16.insert(mrs4, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5);
-                           }
-                           else if ( mrs_number == 4)
-                           {
-                               rc_num = rc_num | address_16.insert(mrs2, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
-                           }
-                           else if ( mrs_number == 5)
-                           {
-                               rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
-                           }
-                           else if ( mrs_number == 6)
-                           {
-                               rc_num = rc_num | address_16.insert(mrs0, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5);
-                           }
-
-                           // Indicate B-Side DRAMS BG1=1
-                           rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
-
-                           rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                           rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                           rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                           rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                           rc_num = rc_num | bank_3.flipBit(0,3);     // Invert BA0,BA1,BG0
-
-
-                           if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-                           {
-                               rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-                               if(rc) return rc;
-                           }
-
-
-                           if (rc_num)
-                           {
-                               FAPI_ERR( " Error setting up buffers");
-                               rc_buff.setEcmdError(rc_num);
-                               return rc_buff;
-                           }
-
-                           // Send out to the CCS array
-                           rc = mss_ccs_inst_arry_0( i_target,
-                                             io_ccs_inst_cnt,
-                                             address_16,
-                                             bank_3,
-                                             activate_1,
-                                             rasn_1,
-                                             casn_1,
-                                             wen_1,
-                                             cke_4,
-                                             csn_8,
-                                             odt_4,
-                                             ddr_cal_type_4,
-                                             i_port_number);
-                           if(rc) return rc;
-                           rc = mss_ccs_inst_arry_1( i_target,
-                                             io_ccs_inst_cnt,
-                                             num_idles_16,
-                                             num_repeat_16,
-                                             data_20,
-                                             read_compare_1,
-                                             rank_cal_4,
-                                             ddr_cal_enable_1,
-                                             ccs_end_1);
-                           if(rc) return rc;
-                           io_ccs_inst_cnt ++;
-
-                       }
-                 }
-
-            }
-        }
-    }
-
-    return rc;
-}
-
-//#endif
-
-
-
-
-
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C
deleted file mode 100644
index 9dd69c773..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C
+++ /dev/null
@@ -1,3503 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_ddr4_pda.C,v 1.42 2015/07/23 14:18:55 sglancy Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_ddr4_pda.C
-// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures
-// *! OWNER NAME  : Stephen Glancy       Email: sglancy@us.ibm.com
-// *! BACKUP NAME : Andre Marin     Email: aamarin@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.11   | 07/23/15 | sglancy | Changed code to address FW comments
-//  1.10   | 06/09/15 | sglancy | Fixed bug
-//  1.9    | 05/27/15 | sglancy | Fixed bug
-//  1.8    | 05/13/15 | sglancy | Added new checks, FFDC, and checked
-//  1.7    | 05/11/15 | sglancy | Fixed compile errors
-//  1.6    | 05/11/15 | sglancy | Updated for FW comments
-//  1.5    | 05/07/15 | sglancy | Updated for FW comments
-//  1.4    | 04/22/15 | sglancy | Fixed several code bugs
-//  1.3    | 04/21/15 | sglancy | Added support for R and LR DIMMs as well as x8, fixed minor bug in setup and disable code
-//  1.2    | 11/27/14 | sglancy | Updated to allow for file inputs and changed print statements
-//  1.1    | 10/27/14 | sglancy | First revision
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-#include <mss_ddr4_pda.H>
-#include <mss_funcs.H>
-#include <cen_scom_addresses.H>
-#include <mss_access_delay_reg.H>
-#include <vector>
-#include <algorithm>
-using namespace fapi;
-using namespace std;
-extern "C" {
-
-//PDA_Scom_Storage constructor
-PDA_Scom_Storage::PDA_Scom_Storage(uint64_t sa, uint32_t sb, uint32_t nb) {
-   scom_addr = sa;
-   start_bit = sb;
-   num_bits = nb;
-}
-PDA_Scom_Storage::~PDA_Scom_Storage() {}
-
-//PDA_MRS_Storage class constructor
-PDA_MRS_Storage::PDA_MRS_Storage(uint8_t ad,uint32_t an,uint8_t dr,uint8_t di,uint8_t r,uint8_t p) {
-   attribute_data = ad;
-   attribute_name = an;
-   dram = dr;
-   dimm = di;
-   rank = r;
-   port = p;
-   MRS = 0xFF;
-   pda_string[0] = '\0';
-}
-
-const uint8_t MRS0_BA = 0;
-const uint8_t MRS1_BA = 1;
-const uint8_t MRS2_BA = 2;  
-const uint8_t MRS3_BA = 3;
-const uint8_t MRS4_BA = 4;
-const uint8_t MRS5_BA = 5;
-const uint8_t MRS6_BA = 6;
-const uint8_t MAX_NUM_DP18S = 5;
-const uint8_t MAX_NUM_PORTS = 2;
-const uint8_t MAX_NUM_DIMMS = 2;
-const uint8_t PORT_SIZE = 2;
-
-//generates the string
-void PDA_MRS_Storage::generatePDAString() {
-   snprintf(pda_string,MAX_ECMD_STRING_LEN,"ATTR_NAME 0x%08x ATTR_DATA 0x%02x MRS %d P %d DI %d R %d DR %d",attribute_name,attribute_data,MRS,port,dimm,rank,dram);
-}
-
-//sends out the string
-char * PDA_MRS_Storage::c_str() {
-   //generate new string
-   generatePDAString(); //note using a separate function here in case some other function would need to call the generation of the string
-   return pda_string;
-}
-
-//Checks to make sure that 
-ReturnCode PDA_MRS_Storage::checkPDAValid(Target& i_target) {
-   ReturnCode rc;
-   
-   //checks constants first
-   //ports out of range
-   if(port >= MAX_NUM_PORTS) {
-      const uint32_t PORT_VALUE = port;
-      const uint32_t DIMM_VALUE = dimm;
-      const uint32_t RANK_VALUE = rank;
-      const uint32_t DRAM_VALUE = dram;
-      const fapi::Target & MBA_TARGET = i_target; 
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE);
-      FAPI_ERR("ERROR!! Port out of valid range! Exiting...");
-      return rc;
-   }
-   
-   //DIMMs out of range
-   if(dimm >= MAX_NUM_DIMMS) {
-      const uint32_t PORT_VALUE = port;
-      const uint32_t DIMM_VALUE = dimm;
-      const uint32_t RANK_VALUE = rank;
-      const uint32_t DRAM_VALUE = dram;
-      const fapi::Target & MBA_TARGET = i_target; 
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE);
-      FAPI_ERR("ERROR!! DIMM out of valid range! Exiting...");
-      return rc;
-   }
-   
-   //now checks based upon attributes
-   uint8_t num_ranks[2][2];
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,&i_target,num_ranks); 
-   if(rc) return rc;
-   
-   //no ranks on the selected dimm
-   if(num_ranks[port][dimm] == 0) {
-      const uint32_t PORT_VALUE = port;
-      const uint32_t DIMM_VALUE = dimm;
-      const uint32_t RANK_VALUE = rank;
-      const uint32_t DRAM_VALUE = dram;
-      const fapi::Target & MBA_TARGET = i_target; 
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE);
-      FAPI_ERR("ERROR!! DIMM has no valid ranks! Exiting...");
-      return rc;
-   }
-   
-   //rank is out of range
-   if(num_ranks[port][dimm] <= rank) {
-      const uint32_t PORT_VALUE = port;
-      const uint32_t DIMM_VALUE = dimm;
-      const uint32_t RANK_VALUE = rank;
-      const uint32_t DRAM_VALUE = dram;
-      const fapi::Target & MBA_TARGET = i_target; 
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE);
-      FAPI_ERR("ERROR!! Rank is out of bounds! Exiting...");
-      return rc;
-   }
-   
-   uint8_t num_spares[2][2][4];
-   rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE,&i_target,num_spares); 
-   if(rc) return rc;
-   
-   uint8_t dram_width;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH,&i_target,dram_width); 
-   if(rc) return rc;
-   
-   uint8_t num_spare = 0;
-   if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE) {
-      num_spare = 1;
-   }
-   if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE) {
-      num_spare = 1;
-   }
-   if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE && dram_width == ENUM_ATTR_EFF_DRAM_WIDTH_X4) {
-      num_spare = 2;
-   }
-   if(num_spares[port][dimm][rank] == ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE && dram_width == ENUM_ATTR_EFF_DRAM_WIDTH_X8) {
-      num_spare = 1;
-   }
-   
-   uint8_t num_dram = 72/dram_width + num_spare;
-   if(num_dram <= dram) {
-      const uint32_t PORT_VALUE = port;
-      const uint32_t DIMM_VALUE = dimm;
-      const uint32_t RANK_VALUE = rank;
-      const uint32_t DRAM_VALUE = dram;
-      const fapi::Target & MBA_TARGET = i_target; 
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_DRAM_DNE);
-      FAPI_ERR("ERROR!! DRAM is out of bounds! Exiting...");
-      return rc;
-   }
-   
-   return rc;
-}
-
-//sets the MRS variable based upon the inputted attribute name
-ReturnCode PDA_MRS_Storage::setMRSbyAttr(Target& i_target) {
-   fapi::ReturnCode rc;
-   switch(attribute_name) {
-   
-   //MRS0
-      case ATTR_EFF_DRAM_BL: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_RBT: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_CL: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_TM: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_DLL_RESET: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_WR: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_TRTP: MRS = MRS0_BA; break;
-      case ATTR_EFF_DRAM_DLL_PPD: MRS = MRS0_BA; break;
-
-   //MRS1
-      case ATTR_EFF_DRAM_DLL_ENABLE: MRS = MRS1_BA; break;
-      case ATTR_VPD_DRAM_RON: MRS = MRS1_BA; break;
-      case ATTR_VPD_DRAM_RTT_NOM: MRS = MRS1_BA; break;
-      case ATTR_EFF_DRAM_AL: MRS = MRS1_BA; break;
-      case ATTR_EFF_DRAM_WR_LVL_ENABLE: MRS = MRS1_BA; break;
-      case ATTR_EFF_DRAM_TDQS: MRS = MRS1_BA; break;
-      case ATTR_EFF_DRAM_OUTPUT_BUFFER: MRS = MRS1_BA; break;
-   
-   //MRS2
-      case ATTR_EFF_DRAM_LPASR: MRS = MRS2_BA; break;
-      case ATTR_EFF_DRAM_CWL: MRS = MRS2_BA; break;
-      case ATTR_VPD_DRAM_RTT_WR: MRS = MRS2_BA; break;
-      case ATTR_EFF_WRITE_CRC: MRS = MRS2_BA; break;
-
-   //MRS3
-      case ATTR_EFF_MPR_MODE: MRS = MRS3_BA; break;
-      case ATTR_EFF_MPR_PAGE: MRS = MRS3_BA; break;
-      case ATTR_EFF_GEARDOWN_MODE: MRS = MRS3_BA; break;
-      case ATTR_EFF_PER_DRAM_ACCESS: MRS = MRS3_BA; break;
-      case ATTR_EFF_TEMP_READOUT: MRS = MRS3_BA; break;
-      case ATTR_EFF_FINE_REFRESH_MODE: MRS = MRS3_BA; break;
-      case ATTR_EFF_CRC_WR_LATENCY: MRS = MRS3_BA; break;
-      case ATTR_EFF_MPR_RD_FORMAT: MRS = MRS3_BA; break;
-
-   //MRS4
-      case ATTR_EFF_MAX_POWERDOWN_MODE: MRS = MRS4_BA; break;
-      case ATTR_EFF_TEMP_REF_RANGE: MRS = MRS4_BA; break;
-      case ATTR_EFF_TEMP_REF_MODE: MRS = MRS4_BA; break;
-      case ATTR_EFF_INT_VREF_MON: MRS = MRS4_BA; break;
-      case ATTR_EFF_CS_CMD_LATENCY: MRS = MRS4_BA; break;
-      case ATTR_EFF_SELF_REF_ABORT: MRS = MRS4_BA; break;
-      case ATTR_EFF_RD_PREAMBLE_TRAIN: MRS = MRS4_BA; break;
-      case ATTR_EFF_RD_PREAMBLE: MRS = MRS4_BA; break;
-      case ATTR_EFF_WR_PREAMBLE: MRS = MRS4_BA; break;
-
-
-   //MRS5
-      case ATTR_EFF_CA_PARITY_LATENCY : MRS = MRS5_BA; break;
-      case ATTR_EFF_CRC_ERROR_CLEAR : MRS = MRS5_BA; break;
-      case ATTR_EFF_CA_PARITY_ERROR_STATUS : MRS = MRS5_BA; break;
-      case ATTR_EFF_ODT_INPUT_BUFF : MRS = MRS5_BA; break;
-      case ATTR_EFF_RTT_PARK : MRS = MRS5_BA; break;
-      case ATTR_EFF_CA_PARITY : MRS = MRS5_BA; break;
-      case ATTR_EFF_DATA_MASK : MRS = MRS5_BA; break;
-      case ATTR_EFF_WRITE_DBI : MRS = MRS5_BA; break;
-      case ATTR_EFF_READ_DBI : MRS = MRS5_BA; break;
-
-   //MRS6
-      case ATTR_VREF_DQ_TRAIN_VALUE: MRS = MRS6_BA; break;
-      case ATTR_VREF_DQ_TRAIN_RANGE: MRS = MRS6_BA; break;
-      case ATTR_VREF_DQ_TRAIN_ENABLE: MRS = MRS6_BA; break;
-      case ATTR_TCCD_L: MRS = MRS6_BA; break;
-      
-      //MRS attribute not found, error out
-      default: 
-         const uint32_t NONMRS_ATTR_NAME = attribute_name;
-	 const fapi::Target & MBA_TARGET = i_target; 
-	 FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_NONMRS_ATTR_NAME);
-	 FAPI_ERR("ERROR!! Found attribute name not associated with an MRS! Exiting...");
-   }
-   return rc;
-}//end setMRSbyAttr
-  
-//PDA_MRS_Storage class destructor
-PDA_MRS_Storage::~PDA_MRS_Storage() {}
-
-bool PDA_MRS_Storage::operator> (const PDA_MRS_Storage &PDA2) const {
-   //check on the DRAM first
-   //DRAM for A is greater than B return true
-   if(dram > PDA2.dram) return true;
-   //B > A -> false
-   else if(dram < PDA2.dram) return false;
-   //B == A, so go to port
-   //A > B -> true
-   else if(port > PDA2.port) return true;
-   //A < B -> false
-   else if(port < PDA2.port) return false;
-   //ports are equal, so start comparing dimms
-   //A > B -> true
-   else if(dimm > PDA2.dimm) return true;
-   //A < B -> false
-   else if(dimm < PDA2.dimm) return false;
-   //dimms are equal, so start comparing ranks
-   //A > B -> true
-   else if(rank > PDA2.rank) return true;
-   //A < B -> false
-   else if(rank < PDA2.rank) return false;
-   //ports are equal, so start comparing the MRS number
-   //A > B -> true
-   else if(MRS > PDA2.MRS) return true;
-   //A < B -> false
-   else if(MRS < PDA2.MRS) return false;
-   //ports are equal, so start comparing the attribute_name
-   //A > B -> true
-   else if(attribute_name > PDA2.attribute_name) return true;
-   //A < B -> false
-   else if(attribute_name < PDA2.attribute_name) return false;
-   //ports are equal, so start comparing the attribute_data
-   //A > B -> true
-   else if(attribute_data > PDA2.attribute_data) return true;
-   //equal or less than
-   return false;
-}//end operator>
-
-bool PDA_MRS_Storage::operator< (const PDA_MRS_Storage &PDA2) const {
-//check on the DRAM first
-   //DRAM for A is less than B return true
-   if(dram < PDA2.dram) return true;
-   //B < A -> false
-   else if(dram > PDA2.dram) return false;
-   //B == A, so go to port
-   //A < B -> true
-   else if(port < PDA2.port) return true;
-   //A > B -> false
-   else if(port > PDA2.port) return false;
-   //ports are equal, so start comparing dimms
-   //A < B -> true
-   else if(dimm < PDA2.dimm) return true;
-   //A > B -> false
-   else if(dimm > PDA2.dimm) return false;
-   //dimms are equal, so start comparing ranks
-   //A < B -> true
-   else if(rank < PDA2.rank) return true;
-   //A > B -> false
-   else if(rank > PDA2.rank) return false;
-   //ports are equal, so start comparing the MRS number
-   //A < B -> true
-   else if(MRS < PDA2.MRS) return true;
-   //A > B -> false
-   else if(MRS > PDA2.MRS) return false;
-   //ports are equal, so start comparing the attribute_name
-   //A < B -> true
-   else if(attribute_name < PDA2.attribute_name) return true;
-   //A > B -> false
-   else if(attribute_name > PDA2.attribute_name) return false;
-   //ports are equal, so start comparing the attribute_data
-   //A < B -> true
-   else if(attribute_data < PDA2.attribute_data) return true;
-   //equal or greater than
-   return false;
-}//end operator<
-
-
-/////////////////////////////////////////////////////////////////////////////////
-/// PDA_MRS_Storage::copy
-/// copies one PDA_MRS_Storage to this one
-/////////////////////////////////////////////////////////////////////////////////
-void PDA_MRS_Storage::copy(PDA_MRS_Storage &temp) {
-   attribute_data = temp.attribute_data;
-   attribute_name = temp.attribute_name;
-   MRS            = temp.MRS	       ;
-   dram           = temp.dram	       ;
-   dimm           = temp.dimm	       ;
-   rank           = temp.rank	       ;
-   port           = temp.port	       ;
-}
-
-/////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_checksort_pda
-/// sorts the vector of PDA_MRS_Storage, so the commands will be run in a more efficient order
-/////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_checksort_pda(Target& i_target, vector<PDA_MRS_Storage>& pda) {
-   ReturnCode rc;
-   
-   //does the check to make sure all given attributes are associated with an MRS 
-   for(uint32_t i=0;i<pda.size();i++) {
-      rc = pda[i].setMRSbyAttr(i_target);
-      if(rc) return rc;
-      rc = pda[i].checkPDAValid(i_target);
-      if(rc) return rc;
-   }
-   
-   //does the sort, sorting by the class comparator (should be DRAM first)
-   sort(pda.begin(),pda.end());
-   
-   return rc;
-}
-
-
-/////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_setup_pda
-/// sets up per-DRAM addressability funcitonality on both ports on the passed MBA
-/////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_setup_pda(
-            Target& i_target,
-            uint32_t& io_ccs_inst_cnt
-            )
-{
-    uint32_t i_port_number=0;
-    uint32_t dimm_number;
-    uint32_t rank_number;
-    const uint32_t NUM_POLL = 10;
-    const uint32_t WAIT_TIMER = 1500;
-    ReturnCode rc;  
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint64_t reg_address;
-    ecmdDataBufferBase data_buffer(64);
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    rc_num = rc_num | activate_1.setBit(0);
-    ecmdDataBufferBase rasn_1(1);
-    ecmdDataBufferBase casn_1(1);
-    ecmdDataBufferBase wen_1(1);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    ecmdDataBufferBase mrs3(16);
-    uint16_t MRS3 = 0;
-    
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-    
-    uint8_t num_ranks;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-    // WORKAROUNDS 
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.setBit(51);
-    
-    if (rc_num)
-    {
-    	FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    	rc_buff.setEcmdError(rc_num);
-    	return rc_buff;
-    }
-    
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-    
-    //loops through port 0 and port 1 on the given MBA
-    for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) {
-       // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-       rc_num = rc_num | cke_4.setBit(0,4);
-       rc_num = rc_num | csn_8.setBit(0,8);
-       rc_num = rc_num | address_16.clearBit(0, 16);
-       rc_num = rc_num | odt_4.clearBit(0,4);
-       rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-       if (rc_num)
-       {
-    	    FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    	    rc_buff.setEcmdError(rc_num);
-    	    return rc_buff;
-       }
-       
-       rc = mss_ccs_inst_arry_0( i_target,
-    				 io_ccs_inst_cnt,
-    				 address_16,
-    				 bank_3,
-    				 activate_1,
-    				 rasn_1,
-    				 casn_1,
-    				 wen_1,
-    				 cke_4,
-    				 csn_8,
-    				 odt_4,
-    				 ddr_cal_type_4,
-    				 i_port_number);	
-       if(rc) return rc;
-       rc = mss_ccs_inst_arry_1( i_target,
-    				 io_ccs_inst_cnt,
-    				 num_idles_16,
-    				 num_repeat_16,
-    				 data_20,
-    				 read_compare_1,
-    				 rank_cal_4,
-    				 ddr_cal_enable_1,
-    				 ccs_end_1);  
-       if(rc) return rc;
-       io_ccs_inst_cnt ++;
-    }
-    
-    
-    //Sets up MRS3 -> the MRS that has PDA
-    uint8_t mpr_op; // MPR Op
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op);
-    if(rc) return rc;
-    uint8_t mpr_page; // MPR Page Selection  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page);
-    if(rc) return rc;
-    uint8_t geardown_mode; // Gear Down Mode  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode);
-    if(rc) return rc;
-    uint8_t temp_readout; // Temperature sensor readout  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout);
-    if(rc) return rc;
-    uint8_t fine_refresh; // fine refresh mode  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh);
-    if(rc) return rc;
-    uint8_t wr_latency; // write latency for CRC and DM  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency);
-    if(rc) return rc;
-    uint8_t read_format; // MPR READ FORMAT  - NEW
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format);
-    if(rc) return rc;
-
-    //enables PDA mode
-    //loops through all ports
-    for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) {
-    	// Dimm 0-1
-    	for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    	{
-    	    num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-    	    if (num_ranks == 0)
-    	    {
-    		FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks);
-    	    }
-    	    else
-    	    {
-    		// Rank 0-3
-    		for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-    		{
-    		   // Only corresponding CS to rank
-    		   rc_num = rc_num | csn_8.setBit(0,8); 
-    		   rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-    			
-    		   rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-    		   rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-    		   rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-    		   
-		   //sets up MRS3 ecmd buffer
-	           rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2);
-	           rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) 0xff, 4, 1); //enables PDA mode!!!!
-	           rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3);
-	           rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2);
-	           rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2);
-	           rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2);
-	           rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-	           rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16);
-		   rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-		   
-    		   if (rc_num)
-    		   {
-    		       FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    		       rc_buff.setEcmdError(rc_num);
-    		       return rc_buff;
-    		   }
-    		   
-	           
-    		   if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-    		   {
-    		      rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-    		      if(rc) return rc;
-    		   }
-    		   
-    		   
-    		   // Send out to the CCS array 
-    		   rc = mss_ccs_inst_arry_0( i_target,
-    				     io_ccs_inst_cnt,
-    				     address_16,
-    				     bank_3,
-    				     activate_1,
-    				     rasn_1,
-    				     casn_1,
-    				     wen_1,
-    				     cke_4,
-    				     csn_8,
-    				     odt_4,
-    				     ddr_cal_type_4,
-    				     i_port_number);
-    		   if(rc) return rc;
-    		   rc = mss_ccs_inst_arry_1( i_target,
-    				     io_ccs_inst_cnt,
-    				     num_idles_16,
-    				     num_repeat_16,
-    				     data_20,
-    				     read_compare_1,
-    				     rank_cal_4,
-    				     ddr_cal_enable_1,
-    				     ccs_end_1);
-    		   if(rc) return rc;
-    		   io_ccs_inst_cnt ++;
-		   
-		   //if the DIMM is an R or LR DIMM, then run inverted for the B-Side DRAM
-                    if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) 
-                    {
-		       //reload all MRS values (removes address swizzling)
-		       // Only corresponding CS to rank
-    		       rc_num = rc_num | csn_8.setBit(0,8); 
-    		       rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-    		    	    
-    		       rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-    		       rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-    		       rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-    		       
-		       //sets up MRS3 ecmd buffer
-		       rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-		       
-		       //FLIPS all necessary bits
-		       // Indicate B-Side DRAMS BG1=1 
-                       rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
- 
-                       rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                       rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                       rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                       rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                       rc_num = rc_num | bank_3.flipBit(0,3);	  // Invert BA0,BA1,BG0
-		       
-		       if (rc_num)
-    		       {
-    		     	   FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    		     	   rc_buff.setEcmdError(rc_num);
-    		     	   return rc_buff;
-    		       }
-		     	   
-		     	   if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-    		       {
-    		     	  rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-    		     	  if(rc) return rc;
-    		       }
-    		       
-    		       // Send out to the CCS array 
-    		       rc = mss_ccs_inst_arry_0( i_target,
-    		     	 		 io_ccs_inst_cnt,
-    		     	 		 address_16,
-    		     	 		 bank_3,
-    		     	 		 activate_1,
-    		     	 		 rasn_1,
-    		     	 		 casn_1,
-    		     	 		 wen_1,
-    		     	 		 cke_4,
-    		     	 		 csn_8,
-    		     	 		 odt_4,
-    		     	 		 ddr_cal_type_4,
-    		     	 		 i_port_number);
-    		       if(rc) return rc;
-    		       rc = mss_ccs_inst_arry_1( i_target,
-    		     	 		 io_ccs_inst_cnt,
-    		     	 		 num_idles_16,
-    		     	 		 num_repeat_16,
-    		     	 		 data_20,
-    		     	 		 read_compare_1,
-    		     	 		 rank_cal_4,
-    		     	 		 ddr_cal_enable_1,
-    		     	 		 ccs_end_1);
-    		       if(rc) return rc;
-    		       io_ccs_inst_cnt ++;
-		    }
-    		}    
-    	    }
-    	}
-    }
-    
-    //runs a NOP command for 24 cycle
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16);
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | cke_4.setBit(0,4);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    rc_num = rc_num | num_idles_16.clearBit(0,16);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 24, 0, 16);
-    rc_num = rc_num | rasn_1.setBit(0,1);
-    rc_num = rc_num | casn_1.setBit(0,1);
-    rc_num = rc_num | wen_1.setBit(0,1);
-    
-    if (rc_num)
-    {
-    	FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    	rc_buff.setEcmdError(rc_num);
-    	return rc_buff;
-    }
-    
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);	     
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);  
-    
-    //Setup end bit for CCS
-    rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt);
-    if (rc) return rc;
-    
-    //Enable CCS and set RAS/CAS/WE high during idles
-   FAPI_INF("Enabling CCS\n");
-   reg_address = CCS_MODEQ_AB_REG_0x030106A7;
-   rc = fapiGetScom(i_target, reg_address, data_buffer);
-   if(rc) return rc;
-
-   rc_num |= data_buffer.setBit(29);    //Enable CCS
-   rc_num |= data_buffer.setBit(52);    //RAS high
-   rc_num |= data_buffer.setBit(53);    //CAS high
-   rc_num |= data_buffer.setBit(54);    //WE high
-   if (rc_num) {
-      FAPI_ERR( "enable ccs setup: Error setting up buffers");
-      rc.setEcmdError(rc_num);
-      return rc;
-   }
-   rc = fapiPutScom(i_target, reg_address, data_buffer);
-   if(rc) return rc;
-
-
-   //Execute the CCS array
-   FAPI_INF("Executing the CCS array\n");
-   rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER);
-   io_ccs_inst_cnt=0;
-   
-   //exits PDA
-   //loops through the DP18's and sets everything to 1's - no PDA
-   for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) {
-      for(uint8_t dp18 = 0; dp18<MAX_NUM_DP18S;dp18++) {
-   	 reg_address = 0x800000010301143full + 0x0001000000000000ull*i_port_number+ 0x0000040000000000ull*(dp18);
-   	 rc = fapiGetScom(i_target, reg_address, data_buffer);
-   	 if(rc) return rc;
-
-   	 rc_num |= data_buffer.setBit(60,4);	//Enable CCS
-   	 if (rc_num) {
-   	    FAPI_ERR( "enable ccs setup: Error setting up buffers");
-   	    rc.setEcmdError(rc_num);
-   	    return rc;
-   	 }
-   	 rc = fapiPutScom(i_target, reg_address, data_buffer);
-   	 if(rc) return rc;
-      }
-   }
-   
-   rc = fapiGetScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);
-   if(rc) return rc;
-   //Setting up CCS mode
-   rc_num = rc_num | data_buffer.setBit(48);
-   if (rc_num)
-   {
-       FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-       rc_buff.setEcmdError(rc_num);
-       return rc_buff;
-   }
-   rc = fapiPutScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);	
-   if(rc) return rc;
-   
-   rc = fapiGetScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer);
-   if(rc) return rc;
-   //Setting up CCS mode
-   rc_num = rc_num | data_buffer.setBit(48);
-   if (rc_num)
-   {
-       FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-       rc_buff.setEcmdError(rc_num);
-       return rc_buff;
-   }
-   rc = fapiPutScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer);	
-   if(rc) return rc;
-   
-   return rc;
-}// end mss_ddr4_setup_pda
-
-
-/////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_pda
-/// configures a vector of PDA accesses to run
-/////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_pda(
-            Target& i_target,
-	    vector<PDA_MRS_Storage> pda
-            )
-{
-    ReturnCode rc;
-    uint8_t dram_loop_end;
-    uint8_t dram_loop_end_with_spare;
-    
-    //gets the rank information
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-    
-    //gets the spare information
-    uint8_t num_spare[2][2][4]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_target, num_spare);
-    if(rc) return rc;
-    
-    //gets the WR VREF information
-    uint8_t wr_vref[2][2][4]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VREF_DQ_TRAIN_VALUE, &i_target, wr_vref);
-    if(rc) return rc;
-    
-    
-    uint8_t dram_width;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width);
-    if(rc) return rc;
-    
-    //sets the loop_end value, to ensure that the proper number of loops are conducted
-    if(dram_width == 0x08) {
-       dram_loop_end = 9;
-    }
-    //must be a x4 DRAM
-    else {
-       dram_loop_end = 18;
-    }
-    
-    uint8_t array[][2][19] = {{{0x18,0x18,0x1c,0x1c,0x18,0x18,0x1c,0x1c,0x18,0x1c,0x18,0x18,0x1c,0x1c,0x1c,0x18,0x1c,0x18,0x18},{0x18,0x1c,0x20,0x1c,0x20,0x1c,0x20,0x20,0x1c,0x1c,0x20,0x1c,0x18,0x1c,0x1c,0x1c,0x1c,0x18,0x18}},{{0x18,0x1c,0x1c,0x1c,0x20,0x1c,0x20,0x18,0x18,0x18,0x1c,0x1c,0x1c,0x18,0x18,0x1c,0x18,0x18,0x1c},{0x18,0x1c,0x18,0x1c,0x20,0x1c,0x18,0x1c,0x20,0x1c,0x1c,0x1c,0x1c,0x24,0x1c,0x1c,0x1c,0x1c,0x1c}}};
-
-
-    //if pda is empty then, sets up the vector for the MRS storage
-    if(pda.size() == 0) {
-    	//loops through each port each dimm each rank each dram and sets everything
-    	for(uint8_t port = 0; port < MAX_NUM_PORTS; port++) {
-    	   for(uint8_t dimm = 0; dimm < MAX_NUM_DIMMS; dimm++) {
-    	      for(uint8_t rank = 0; rank < num_ranks_array[port][dimm]; rank++) {
-    		 //DIMM has a spare, add one DRAM to the loop
-    		 if(num_spare[port][dimm][rank]) {
-    		    dram_loop_end_with_spare = dram_loop_end+1;
-    		 }
-    		 else {
-    		    dram_loop_end_with_spare = dram_loop_end;
-    		 }
-    		 //loops through all dram
-    		 for(uint8_t dram = 0; dram < dram_loop_end_with_spare; dram++) {
-    		 //uint8_t ad,uint32_t an,uint8_t d,uint8_t r,uint8_t 
-    		    if(port == 0) wr_vref[port][dimm][rank] = dram*3;
-    		    else wr_vref[port][dimm][rank] = 57-dram*3;
-    		    if(wr_vref[port][dimm][rank]  > 50) wr_vref[port][dimm][rank] = 50;
-    		    pda.push_back(PDA_MRS_Storage(array[port][dimm][dram],ATTR_VREF_DQ_TRAIN_VALUE,dram,dimm,rank,port));
-    		    FAPI_INF("PDA STRING: %d %s",pda.size()-1,pda[pda.size()-1].c_str());
-    		 }
-    	      }
-    	   }
-    	}
-    }
-    rc = mss_ddr4_run_pda(i_target,pda);
-    return rc;
-}
-
-/////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_run_pda
-/// runs per-DRAM addressability funcitonality on both ports on the passed MBA
-/////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_run_pda(
-            Target& i_target,
-	    vector<PDA_MRS_Storage> pda
-            )
-{
-    ReturnCode rc;  
-    //no PDA was entered, just exit
-    if(pda.size() == 0) return rc;
-    
-    uint32_t io_ccs_inst_cnt = 0;
-    const uint32_t NUM_POLL = 10;
-    const uint32_t WAIT_TIMER = 1500;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase address_16_backup(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    rc_num = rc_num | activate_1.setBit(0);
-    ecmdDataBufferBase rasn_1(1);
-    ecmdDataBufferBase casn_1(1);
-    ecmdDataBufferBase wen_1(1);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-    
-    //checks each MRS and saves each 
-    rc = mss_ddr4_checksort_pda(i_target,pda);
-    if(rc) return rc;
-    
-    //loads in dram type
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-    
-    //dram density
-    uint8_t dram_width;
-    
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width);
-    if(rc) return rc;
-    
-    ecmdDataBufferBase data_buffer(64);
-    
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-    rc = mss_ddr4_setup_pda(i_target, io_ccs_inst_cnt );
-    if(rc)  return rc;
-    
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 100, 0, 16);
-   
-   
-   
-    rc_num = rc_num | cke_4.setBit(0,4);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    rc_num = rc_num | rasn_1.clearBit(0,1);
-    rc_num = rc_num | casn_1.clearBit(0,1);
-    rc_num = rc_num | wen_1.clearBit(0,1);
-   
-   //gets the start PDA values
-   uint8_t prev_dram = pda[0].dram;
-   uint8_t prev_port = pda[0].port;
-   uint8_t prev_rank = pda[0].rank;
-   uint8_t prev_dimm = pda[0].dimm;
-   uint8_t prev_mrs  = pda[0].MRS;
-   rc = mss_ddr4_load_nominal_mrs_pda(i_target,bank_3,address_16, prev_mrs, prev_port, prev_dimm, prev_rank);
-   if(rc) return rc;
-   
-   vector<PDA_Scom_Storage> scom_storage;
-   scom_storage.clear();
-   rc = mss_ddr4_add_dram_pda(i_target,prev_port,prev_dram,scom_storage);
-   if(rc) return rc;
-   
-   //runs through each PDA command
-   for(uint32_t i=0;i<pda.size();i++) {
-      FAPI_INF("Target %s On PDA %d is %s",i_target.toEcmdString(),i,pda[i].c_str());
-      //dram, port, rank, dimm, and mrs are the same
-      if(prev_dram == pda[i].dram && prev_port == pda[i].port && prev_rank == pda[i].rank && prev_dimm == pda[i].dimm && prev_mrs == pda[i].MRS) {
-         //modifies this attribute
-         rc = mss_ddr4_modify_mrs_pda(i_target,address_16, pda[i].attribute_name,pda[i].attribute_data);
-         if(rc) return rc;
-      }
-      //another MRS, so set this MRS.  do additional checks to later in the code
-      else {
-         
-	 //adds values to a backup address_16 before doing the mirroring
-	 address_16_backup.clearBit(0, 16);
-	 rc_num = rc_num | address_16_backup.insert(address_16, 0, 16, 0);
-	 
-         //loads the previous DRAM
-         if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0))
-   	 {
-   	     rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3);
-   	     if(rc) return rc;
-   	 }
-	 
-	 // Only corresponding CS to rank
-   	 rc_num = rc_num | csn_8.setBit(0,8); 
-   	 rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm);
-	 
-   	 // Send out to the CCS array 
-   	 rc = mss_ccs_inst_arry_0( i_target,
-   	     	  io_ccs_inst_cnt,
-   	     	  address_16,
-   	     	  bank_3,
-   	     	  activate_1,
-   	     	  rasn_1,
-   	     	  casn_1,
-   	     	  wen_1,
-   	     	  cke_4,
-   	     	  csn_8,
-   	     	  odt_4,
-   	     	  ddr_cal_type_4,
-   	     	  prev_port);
-   	 if(rc) return rc;
-   	 rc = mss_ccs_inst_arry_1( i_target,
-   	     	  io_ccs_inst_cnt,
-   	     	  num_idles_16,
-   	     	  num_repeat_16,
-   	     	  data_20,
-   	     	  read_compare_1,
-   	     	  rank_cal_4,
-   	     	  ddr_cal_enable_1,
-   	     	  ccs_end_1);
-   	 if(rc) return rc;
-   	 io_ccs_inst_cnt ++;
-	 
-	 //is an R or LR DIMM -> do a B side MRS write
-	 if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) {
-	    //takes values from the backup
-	    address_16.clearBit(0, 16);
-	    rc_num = rc_num | address_16.insert(address_16_backup, 0, 16, 0);
-	    
-	    //FLIPS all necessary bits
-	    // Indicate B-Side DRAMS BG1=1 
-            rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
- 
-            rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-            rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-            rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-            rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-            rc_num = rc_num | bank_3.flipBit(0,3);     // Invert BA0,BA1,BG0
-	    
-	    //loads the previous DRAM
-            if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0))
-   	    {
-   	   	rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3);
-   	   	if(rc) return rc;
-   	    }
-	    
-	    // Only corresponding CS to rank
-   	    rc_num = rc_num | csn_8.setBit(0,8); 
-   	    rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm);
-	    
-   	    // Send out to the CCS array 
-   	    rc = mss_ccs_inst_arry_0( i_target,
-   	   	     io_ccs_inst_cnt,
-   	   	     address_16,
-   	   	     bank_3,
-   	   	     activate_1,
-   	   	     rasn_1,
-   	   	     casn_1,
-   	   	     wen_1,
-   	   	     cke_4,
-   	   	     csn_8,
-   	   	     odt_4,
-   	   	     ddr_cal_type_4,
-   	   	     prev_port);
-   	    if(rc) return rc;
-   	    rc = mss_ccs_inst_arry_1( i_target,
-   	   	     io_ccs_inst_cnt,
-   	   	     num_idles_16,
-   	   	     num_repeat_16,
-   	   	     data_20,
-   	   	     read_compare_1,
-   	   	     rank_cal_4,
-   	   	     ddr_cal_enable_1,
-   	   	     ccs_end_1);
-   	    if(rc) return rc;
-   	    io_ccs_inst_cnt ++;
-	 }
-	 
-	 //the DRAM are different, so kick off CCS, and clear out the MRS DRAMs and set up a new DRAM
-	 if(prev_dram != pda[i].dram) {
-	    //sets a NOP as the last command
-	    rc_num = rc_num | cke_4.setBit(0,4);
-    	    rc_num = rc_num | csn_8.setBit(0,8);
-    	    rc_num = rc_num | address_16.clearBit(0, 16);
-    	    rc_num = rc_num | rasn_1.setBit(0,1);
-    	    rc_num = rc_num | casn_1.setBit(0,1);
-    	    rc_num = rc_num | wen_1.setBit(0,1);
-	    
-	    // Send out to the CCS array 
-            rc = mss_ccs_inst_arry_0( i_target,
-                     io_ccs_inst_cnt,
-                     address_16,
-                     bank_3,
-                     activate_1,
-                     rasn_1,
-                     casn_1,
-                     wen_1,
-                     cke_4,
-                     csn_8,
-                     odt_4,
-                     ddr_cal_type_4,
-                     prev_port);
-            if(rc) return rc;
-            rc = mss_ccs_inst_arry_1( i_target,
-                     io_ccs_inst_cnt,
-                     num_idles_16,
-                     num_repeat_16,
-                     data_20,
-                     read_compare_1,
-                     rank_cal_4,
-                     ddr_cal_enable_1,
-                     ccs_end_1);
-            if(rc) return rc;
-            io_ccs_inst_cnt ++;
-	    
-	    //Setup end bit for CCS
-            rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt-1);
-            if (rc) return rc;
-   
-            //Execute the CCS array
-            FAPI_INF("Executing the CCS array\n");
-            rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER);
-            if(rc) return rc;
-	    io_ccs_inst_cnt = 0;
-	    
-	    // Sets NOP as the first command
-            rc = mss_ccs_inst_arry_0( i_target,
-                     io_ccs_inst_cnt,
-                     address_16,
-                     bank_3,
-                     activate_1,
-                     rasn_1,
-                     casn_1,
-                     wen_1,
-                     cke_4,
-                     csn_8,
-                     odt_4,
-                     ddr_cal_type_4,
-                     prev_port);
-            if(rc) return rc;
-            rc = mss_ccs_inst_arry_1( i_target,
-                     io_ccs_inst_cnt,
-                     num_idles_16,
-                     num_repeat_16,
-                     data_20,
-                     read_compare_1,
-                     rank_cal_4,
-                     ddr_cal_enable_1,
-                     ccs_end_1);
-            if(rc) return rc;
-            io_ccs_inst_cnt ++;
-	    
-	    rc_num = rc_num | cke_4.setBit(0,4);
-    	    rc_num = rc_num | csn_8.setBit(0,8);
-    	    rc_num = rc_num | address_16.clearBit(0, 16);
-    	    rc_num = rc_num | rasn_1.clearBit(0,1);
-    	    rc_num = rc_num | casn_1.clearBit(0,1);
-    	    rc_num = rc_num | wen_1.clearBit(0,1);
-	    
-	    //loops through and clears out the storage class
-	    for(uint32_t scoms = 0; scoms < scom_storage.size(); scoms++) {
-	       rc = fapiGetScom(i_target, scom_storage[scoms].scom_addr, data_buffer);
-               if(rc) return rc;
-
-   	       rc_num |= data_buffer.setBit(scom_storage[scoms].start_bit,scom_storage[scoms].num_bits);  //Enable CCS
-   	       if (rc_num) {
-   	    	  FAPI_ERR( "enable ccs setup: Error setting up buffers");
-   	    	  rc.setEcmdError(rc_num);
-   	    	  return rc;
-   	       }
-   	       rc = fapiPutScom(i_target, scom_storage[scoms].scom_addr, data_buffer);
-               if(rc) return rc;
-	    }
-	    scom_storage.clear();
-	    //enables the next dram scom
-	    rc = mss_ddr4_add_dram_pda(i_target,pda[i].port,pda[i].dram,scom_storage);
-            if(rc) return rc;
-	 }
-	 //different port but same DRAM, enable the next scom
-	 else if(prev_port != pda[i].port) {
-	    //enables the next dram scom
-	    rc = mss_ddr4_add_dram_pda(i_target,pda[i].port,pda[i].dram,scom_storage);
-            if(rc) return rc;
-	 }
-	 
-	 //loads in the nominal MRS for this target
-	 prev_dram = pda[i].dram;
-	 prev_port = pda[i].port;
-	 prev_rank = pda[i].rank;
-	 prev_dimm = pda[i].dimm;
-	 prev_mrs  = pda[i].MRS;
-	 
-	 rc = mss_ddr4_load_nominal_mrs_pda(i_target,bank_3,address_16, prev_mrs, prev_port, prev_dimm, prev_rank);
-	 //modifies the MRS
-	 rc = mss_ddr4_modify_mrs_pda(i_target,address_16, pda[i].attribute_name,pda[i].attribute_data);
-         if(rc) return rc;
-      } 
-   }      
-   
-   //runs the last PDA command
-   //adds values to a backup address_16 before doing the mirroring
-   address_16_backup.clearBit(0, 16);
-   rc_num = rc_num | address_16_backup.insert(address_16, 0, 16, 0);
-
-   //loads the previous DRAM
-   if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0))
-   {
-       rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3);
-       if(rc) return rc;
-   }
-
-   // Only corresponding CS to rank
-   rc_num = rc_num | csn_8.setBit(0,8); 
-   rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm);
-
-   // Send out to the CCS array 
-   rc = mss_ccs_inst_arry_0( i_target,
-   	    io_ccs_inst_cnt,
-   	    address_16,
-   	    bank_3,
-   	    activate_1,
-   	    rasn_1,
-   	    casn_1,
-   	    wen_1,
-   	    cke_4,
-   	    csn_8,
-   	    odt_4,
-   	    ddr_cal_type_4,
-   	    prev_port);
-   if(rc) return rc;
-   rc = mss_ccs_inst_arry_1( i_target,
-   	    io_ccs_inst_cnt,
-   	    num_idles_16,
-   	    num_repeat_16,
-   	    data_20,
-   	    read_compare_1,
-   	    rank_cal_4,
-   	    ddr_cal_enable_1,
-   	    ccs_end_1);
-   if(rc) return rc;
-   io_ccs_inst_cnt ++;
-
-   //is an R or LR DIMM -> do a B side MRS write
-   if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) {
-      //takes values from the backup
-      address_16.clearBit(0, 16);
-      rc_num = rc_num | address_16.insert(address_16_backup, 0, 16, 0);
-      
-      //FLIPS all necessary bits
-      // Indicate B-Side DRAMS BG1=1 
-      rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
- 
-      rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-      rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-      rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-      rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-      rc_num = rc_num | bank_3.flipBit(0,3);	 // Invert BA0,BA1,BG0
-      
-      //loads the previous DRAM
-      if (( address_mirror_map[prev_port][prev_dimm] & (0x08 >> prev_rank) ) && (is_sim == 0))
-      {
-   	  rc = mss_address_mirror_swizzle(i_target, prev_port, prev_dimm, prev_rank, address_16, bank_3);
-   	  if(rc) return rc;
-      }
-      
-      // Only corresponding CS to rank
-      rc_num = rc_num | csn_8.setBit(0,8); 
-      rc_num = rc_num | csn_8.clearBit(prev_rank+4*prev_dimm);
-      
-      // Send out to the CCS array 
-      rc = mss_ccs_inst_arry_0( i_target,
-   	       io_ccs_inst_cnt,
-   	       address_16,
-   	       bank_3,
-   	       activate_1,
-   	       rasn_1,
-   	       casn_1,
-   	       wen_1,
-   	       cke_4,
-   	       csn_8,
-   	       odt_4,
-   	       ddr_cal_type_4,
-   	       prev_port);
-      if(rc) return rc;
-      rc = mss_ccs_inst_arry_1( i_target,
-   	       io_ccs_inst_cnt,
-   	       num_idles_16,
-   	       num_repeat_16,
-   	       data_20,
-   	       read_compare_1,
-   	       rank_cal_4,
-   	       ddr_cal_enable_1,
-   	       ccs_end_1);
-      if(rc) return rc;
-      io_ccs_inst_cnt ++;
-   }
-   
-   
-   //sets a NOP as the last command
-   rc_num = rc_num | cke_4.setBit(0,4);
-   rc_num = rc_num | csn_8.setBit(0,8);
-   rc_num = rc_num | address_16.clearBit(0, 16);
-   rc_num = rc_num | rasn_1.setBit(0,1);
-   rc_num = rc_num | casn_1.setBit(0,1);
-   rc_num = rc_num | wen_1.setBit(0,1);
-
-   // Send out to the CCS array 
-   rc = mss_ccs_inst_arry_0( i_target,
-   	    io_ccs_inst_cnt,
-   	    address_16,
-   	    bank_3,
-   	    activate_1,
-   	    rasn_1,
-   	    casn_1,
-   	    wen_1,
-   	    cke_4,
-   	    csn_8,
-   	    odt_4,
-   	    ddr_cal_type_4,
-   	    prev_port);
-   if(rc) return rc;
-   rc = mss_ccs_inst_arry_1( i_target,
-   	    io_ccs_inst_cnt,
-   	    num_idles_16,
-   	    num_repeat_16,
-   	    data_20,
-   	    read_compare_1,
-   	    rank_cal_4,
-   	    ddr_cal_enable_1,
-   	    ccs_end_1);
-   if(rc) return rc;
-   io_ccs_inst_cnt ++;
-   
-   //Setup end bit for CCS
-   rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt-1);
-   if (rc) return rc;
-   
-   //Execute the CCS array
-   FAPI_INF("Executing the CCS array\n");
-   rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER);
-   if(rc) return rc;
-   
-   //loops through and clears out the storage class
-   for(uint32_t scoms = 0; scoms < scom_storage.size(); scoms++) {
-      rc = fapiGetScom(i_target, scom_storage[scoms].scom_addr, data_buffer);
-      if(rc) return rc;
-
-      rc_num |= data_buffer.setBit(scom_storage[scoms].start_bit,scom_storage[scoms].num_bits);  //Enable CCS
-      if (rc_num) {
-   	 FAPI_ERR( "enable ccs setup: Error setting up buffers");
-   	 rc.setEcmdError(rc_num);
-   	 return rc;
-      }
-      rc = fapiPutScom(i_target, scom_storage[scoms].scom_addr, data_buffer);
-      if(rc) return rc;
-   }
-   //}
-      
-   io_ccs_inst_cnt = 0;
-   rc = mss_ddr4_disable_pda(i_target,io_ccs_inst_cnt);
-   return rc;
-}
-
-
-//////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_add_dram_pda
-/// adds a specific DRAM on a specific port to receive the current MRS command in PDA mode
-//////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_add_dram_pda(Target& i_target,uint8_t port,uint8_t dram,vector<PDA_Scom_Storage> & scom_storage) {
-   ReturnCode rc;
-   ecmdDataBufferBase data_buffer(64);
-   //access delay regs function
-   uint8_t i_rank_pair = 0;
-   input_type_t i_input_type_e = WR_DQ;
-   uint8_t i_input_index = 75;
-   uint8_t i_verbose = 1;
-   uint8_t phy_lane = 6;
-   uint8_t phy_block = 6;
-   uint8_t flag = 0;
-   uint32_t scom_len = 0;
-   uint32_t scom_start = 0;
-   uint32_t rc_num = 0;
-   
-   
-   uint8_t dram_width;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width);
-   if(rc) return rc;
-   
-   // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1) 
-   // In this case moving from lane/block to C4 DQ to use access_delay_reg
-   i_input_index = 4*dram;
-   rc = mss_c4_phy(i_target,port,i_rank_pair,i_input_type_e,i_input_index,i_verbose,phy_lane,phy_block,flag); 
-
-   uint64_t reg_address = 0x800000010301143full + 0x0001000000000000ull*port+ 0x0000040000000000ull*(phy_block);
-   //gets the lane and number of bits to set to 0's
-   if(dram_width == 0x04) {
-      scom_start = 60 + (uint32_t)(phy_lane/4);
-      scom_len = 1;
-   }
-   //x8 DIMM
-   else {
-      scom_start = 60 + (uint32_t)((phy_lane/8)*2);
-      scom_len = 2;
-   }
-   FAPI_INF("Enabling %016llx start at %d for %d bits",reg_address,scom_start,scom_len);
-   
-   rc = fapiGetScom(i_target, reg_address, data_buffer);
-   if(rc) return rc;
-
-   rc_num |= data_buffer.clearBit(scom_start,scom_len);	 //Enable CCS
-   if (rc_num) {
-      FAPI_ERR( "enable ccs setup: Error setting up buffers");
-      rc.setEcmdError(rc_num);
-      return rc;
-   }
-   rc = fapiPutScom(i_target, reg_address, data_buffer);
-   if(rc) return rc;
-   
-   scom_storage.push_back(PDA_Scom_Storage(reg_address,scom_start,scom_len));
-   
-   return rc;
-}
-
-//////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_disable_pda
-/// disables per-DRAM addressability funcitonality on both ports on the passed MBA
-//////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_disable_pda(Target& i_target,uint32_t& io_ccs_inst_cnt) {
-    uint32_t i_port_number=0;
-    uint32_t dimm_number;
-    uint32_t rank_number;
-    const uint32_t NUM_POLL = 10;
-    const uint32_t WAIT_TIMER = 1500;
-    ReturnCode rc;  
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint64_t reg_address;
-    ecmdDataBufferBase data_buffer(64);
-    ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    rc_num = rc_num | activate_1.setBit(0);
-    ecmdDataBufferBase rasn_1(1);
-    ecmdDataBufferBase casn_1(1);
-    ecmdDataBufferBase wen_1(1);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    ecmdDataBufferBase mrs3(16);
-    uint16_t MRS3 = 0;
-    
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    
-    uint8_t num_ranks;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-    // WORKAROUNDS 
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.setBit(51);
-    if (rc_num) {
-      FAPI_ERR( "disable ccs setup: Error disabling up buffers");
-      rc_buff.setEcmdError(rc_num);
-      return rc_buff;
-    }
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;   
-    
-    //loops through port 0 and port 1 on the given MBA
-    for(i_port_number=0;i_port_number<MAX_NUM_PORTS;i_port_number++) {
-       // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-       rc_num = rc_num | cke_4.setBit(0,4);
-       rc_num = rc_num | csn_8.setBit(0,8);
-       rc_num = rc_num | address_16.clearBit(0, 16);
-       rc_num = rc_num | odt_4.clearBit(0,4);
-       rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-       if (rc_num) {
-          FAPI_ERR( "disable ccs setup: Error disabling up buffers");
-          rc_buff.setEcmdError(rc_num);
-          return rc_buff;
-       }
-       rc = mss_ccs_inst_arry_0( i_target,
-    				 io_ccs_inst_cnt,
-    				 address_16,
-    				 bank_3,
-    				 activate_1,
-    				 rasn_1,
-    				 casn_1,
-    				 wen_1,
-    				 cke_4,
-    				 csn_8,
-    				 odt_4,
-    				 ddr_cal_type_4,
-    				 i_port_number);	
-       if(rc) return rc;
-       rc = mss_ccs_inst_arry_1( i_target,
-    				 io_ccs_inst_cnt,
-    				 num_idles_16,
-    				 num_repeat_16,
-    				 data_20,
-    				 read_compare_1,
-    				 rank_cal_4,
-    				 ddr_cal_enable_1,
-    				 ccs_end_1);  
-       if(rc) return rc;
-       io_ccs_inst_cnt ++;
-    }
-    
-    
-    //Sets up MRS3 -> the MRS that has PDA
-    uint8_t mpr_op; // MPR Op
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op);
-    if(rc) return rc;
-    uint8_t mpr_page; // MPR Page Selection  
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page);
-    if(rc) return rc;
-    uint8_t geardown_mode; // Gear Down Mode  
-    rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode);
-    if(rc) return rc;
-    uint8_t temp_readout; // Temperature sensor readout  
-    rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout);
-    if(rc) return rc;
-    uint8_t fine_refresh; // fine refresh mode  
-    rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh);
-    if(rc) return rc;
-    uint8_t wr_latency; // write latency for CRC and DM  
-    rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency);
-    if(rc) return rc;
-    uint8_t read_format; // MPR READ FORMAT  
-    rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format);
-    if(rc) return rc;
-    
-    //exits PDA
-    for(i_port_number=0;i_port_number<2;i_port_number++) {
-    //loops through the DP18's and sets everything to 0's
-      for(uint8_t dp18 = 0; dp18<MAX_NUM_DP18S;dp18++) {
-   	 reg_address = 0x800000010301143full + 0x0001000000000000ull*i_port_number+ 0x0000040000000000ull*(dp18);
-   	 rc = fapiGetScom(i_target, reg_address, data_buffer);
-   	 if(rc) return rc;
-
-   	 rc_num |= data_buffer.clearBit(60,4);    //Enable CCS
-   	 if (rc_num) {
-   	    FAPI_ERR( "enable ccs setup: Error setting up buffers");
-   	    rc.setEcmdError(rc_num);
-   	    return rc;
-   	 }
-   	 rc = fapiPutScom(i_target, reg_address, data_buffer);
-   	 if(rc) return rc;
-      }
-   }
-    
-    //exits PDA
-    for(i_port_number=0;i_port_number<2;i_port_number++) {
-    	for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    	{
-    	    num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-    	    if (num_ranks == 0)
-    	    {
-    		FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks);
-    	    }
-    	    else
-    	    {
-    		// Rank 0-3
-    		for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-    		{
-    		   // Only corresponding CS to rank
-    		   rc_num = rc_num | csn_8.setBit(0,8); 
-    		   rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-    			
-    		   rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-    		   rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-    		   rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-    				
-	           //enables PDA
-	           rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2);
-	           rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 4, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1);
-	           rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3);
-	           rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2);
-	           rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2);
-	           rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2);
-	           rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-	           rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 100, 0, 16);
-		   
-		   //copies over values
-    		   rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-    		   if (rc_num)
-    		   {
-    		       FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-    		       rc_buff.setEcmdError(rc_num);
-    		       return rc_buff;
-    		   }
-		   
-    		   if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-    		   {
-    		      rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-    		      if(rc) return rc;
-    		   }
-		   
-    		   // Send out to the CCS array 
-    		   rc = mss_ccs_inst_arry_0( i_target,
-    				     io_ccs_inst_cnt,
-    				     address_16,
-    				     bank_3,
-    				     activate_1,
-    				     rasn_1,
-    				     casn_1,
-    				     wen_1,
-    				     cke_4,
-    				     csn_8,
-    				     odt_4,
-    				     ddr_cal_type_4,
-    				     i_port_number);
-    		   if(rc) return rc;
-    		   rc = mss_ccs_inst_arry_1( i_target,
-    				     io_ccs_inst_cnt,
-    				     num_idles_16,
-    				     num_repeat_16,
-    				     data_20,
-    				     read_compare_1,
-    				     rank_cal_4,
-    				     ddr_cal_enable_1,
-    				     ccs_end_1);
-    		   if(rc) return rc;
-    		   io_ccs_inst_cnt ++;
-		   
-		   //if the DIMM is an R or LR DIMM, then run inverted for the B-Side DRAM
-                   if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) 
-		   {
-		   
-		       //reload all MRS values (removes address swizzling)
-		        // Only corresponding CS to rank
-    		       rc_num = rc_num | csn_8.setBit(0,8); 
-    		       rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-    		    	    
-    		       rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-    		       rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-    		       rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-    		    		    
-	               //enables PDA
-	               rc_num = rc_num | mrs3.insert((uint8_t) mpr_page, 0, 2);
-	               rc_num = rc_num | mrs3.insert((uint8_t) mpr_op, 2, 1);
-	               rc_num = rc_num | mrs3.insert((uint8_t) geardown_mode, 3, 1);
-	               rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 4, 1);
-	               rc_num = rc_num | mrs3.insert((uint8_t) temp_readout, 5, 1);
-	               rc_num = rc_num | mrs3.insert((uint8_t) fine_refresh, 6, 3);
-	               rc_num = rc_num | mrs3.insert((uint8_t) wr_latency, 9, 2);
-	               rc_num = rc_num | mrs3.insert((uint8_t) read_format, 11, 2);
-	               rc_num = rc_num | mrs3.insert((uint8_t) 0x00, 13, 2);
-	               rc_num = rc_num | mrs3.extractPreserve(&MRS3, 0, 16, 0);
-	               rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 100, 0, 16);
-		       //copies over values
-		       rc_num = rc_num | address_16.insert(mrs3, 0, 16, 0);
-		       
-		       //FLIPS all necessary bits
-		       // Indicate B-Side DRAMS BG1=1 
-                       rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
- 
-                       rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                       rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                       rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                       rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                       rc_num = rc_num | bank_3.flipBit(0,3);	  // Invert BA0,BA1,BG0
-		       
-		       if (rc_num)
-    		       {
-    		     	   FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    		     	   rc_buff.setEcmdError(rc_num);
-    		     	   return rc_buff;
-    		       }
-		     	   
-		     	   if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-    		       {
-    		     	  rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-    		     	  if(rc) return rc;
-    		       }
-    		       
-    		       // Send out to the CCS array 
-    		       rc = mss_ccs_inst_arry_0( i_target,
-    		     	 		 io_ccs_inst_cnt,
-    		     	 		 address_16,
-    		     	 		 bank_3,
-    		     	 		 activate_1,
-    		     	 		 rasn_1,
-    		     	 		 casn_1,
-    		     	 		 wen_1,
-    		     	 		 cke_4,
-    		     	 		 csn_8,
-    		     	 		 odt_4,
-    		     	 		 ddr_cal_type_4,
-    		     	 		 i_port_number);
-    		       if(rc) return rc;
-    		       rc = mss_ccs_inst_arry_1( i_target,
-    		     	 		 io_ccs_inst_cnt,
-    		     	 		 num_idles_16,
-    		     	 		 num_repeat_16,
-    		     	 		 data_20,
-    		     	 		 read_compare_1,
-    		     	 		 rank_cal_4,
-    		     	 		 ddr_cal_enable_1,
-    		     	 		 ccs_end_1);
-    		       if(rc) return rc;
-    		       io_ccs_inst_cnt ++;
-		    }
-    		}    
-    	    }
-    	}
-   }
-   
-   //Setup end bit for CCS
-    rc = mss_ccs_set_end_bit (i_target, io_ccs_inst_cnt-1);
-    if (rc) return rc;
-   
-   //Execute the CCS array
-   FAPI_INF("Executing the CCS array\n");
-   rc = mss_execute_ccs_inst_array (i_target, NUM_POLL, WAIT_TIMER);
-   
-   //Disable CCS
-   FAPI_INF("Disabling CCS\n");
-   reg_address = CCS_MODEQ_AB_REG_0x030106A7;
-   rc = fapiGetScom(i_target, reg_address, data_buffer);
-   if(rc) return rc;
-
-
-   rc_num |= data_buffer.clearBit(29);
-   if (rc_num) {
-      FAPI_ERR( "disable ccs setup: Error disabling up buffers");
-      rc_buff.setEcmdError(rc_num);
-      return rc_buff;
-   }
-   rc = fapiPutScom(i_target, reg_address, data_buffer);
-   if(rc) return rc;
-   
-   //disables the DDR4 PDA mode writes  
-   rc = fapiGetScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.clearBit(48);
-    if (rc_num)
-    {
-    	FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    	rc_buff.setEcmdError(rc_num);
-    	return rc_buff;
-    }
-    rc = fapiPutScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);    
-    if(rc) return rc;
-    
-    rc = fapiGetScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.clearBit(48);
-    if (rc_num)
-    {
-    	FAPI_ERR( "mss_ddr4_setup_pda: Error setting up buffers");
-    	rc_buff.setEcmdError(rc_num);
-    	return rc_buff;
-    }
-    rc = fapiPutScom(i_target,  DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer);    
-    if(rc) return rc;
-   
-   FAPI_INF("Successfully exited out of PDA mode.");
-   io_ccs_inst_cnt = 0;
-   return rc;
-}
-
-//////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_modify_mrs_pda
-/// disables per-DRAM addressability funcitonality on both ports on the passed MBA
-//////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_modify_mrs_pda(Target& i_target,ecmdDataBufferBase& address_16,uint32_t attribute_name,uint8_t attribute_data) {
-   ReturnCode rc;
-   uint32_t rc_num = 0;
-   uint8_t dram_bl = attribute_data;
-   uint8_t read_bt = attribute_data; //Read Burst Type 
-   uint8_t dram_cl = attribute_data;
-   uint8_t test_mode = attribute_data; //TEST MODE 
-   uint8_t dll_reset = attribute_data; //DLL Reset 
-   uint8_t dram_wr = attribute_data; //DRAM write recovery
-   uint8_t dram_rtp = attribute_data; //DRAM RTP - read to precharge
-   uint8_t dram_wr_rtp = attribute_data;
-   uint8_t dll_precharge = attribute_data; //DLL Control For Precharge if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
-   uint8_t dll_enable = attribute_data; //DLL Enable 
-   uint8_t out_drv_imp_cntl = attribute_data;
-   uint8_t dram_rtt_nom = attribute_data;
-   uint8_t dram_al = attribute_data;
-   uint8_t wr_lvl = attribute_data; //write leveling enable
-   uint8_t tdqs_enable = attribute_data; //TDQS Enable 
-   uint8_t q_off = attribute_name; //Qoff - Output buffer Enable 
-   uint8_t lpasr = attribute_data; // Low Power Auto Self-Refresh -- new not yet supported
-   uint8_t cwl = attribute_data; // CAS Write Latency 
-   uint8_t dram_rtt_wr = attribute_data;
-   uint8_t mpr_op = attribute_data; // MPR Op
-   uint8_t mpr_page = attribute_data; // MPR Page Selection  
-   uint8_t geardown_mode = attribute_data; // Gear Down Mode  
-   uint8_t temp_readout = attribute_data; // Temperature sensor readout  
-   uint8_t fine_refresh = attribute_data; // fine refresh mode  
-   uint8_t wr_latency = attribute_data; // write latency for CRC and DM  
-   uint8_t write_crc = attribute_data; // CAS Write Latency 
-   uint8_t read_format = attribute_data; // MPR READ FORMAT  
-   uint8_t max_pd_mode = attribute_data; // Max Power down mode 
-   uint8_t temp_ref_range = attribute_data; // Temp ref range 
-   uint8_t temp_ref_mode = attribute_data; // Temp controlled ref mode 
-   uint8_t vref_mon = attribute_data; // Internal Vref Monitor 
-   uint8_t cs_cmd_latency = attribute_data; // CS to CMD/ADDR Latency 
-   uint8_t ref_abort = attribute_data; // Self Refresh Abort 
-   uint8_t rd_pre_train_mode = attribute_data; // Read Pre amble Training Mode 
-   uint8_t rd_preamble = attribute_data; // Read Pre amble 
-   uint8_t wr_preamble = attribute_data; // Write Pre amble 
-   uint8_t ca_parity_latency = attribute_data; //C/A Parity Latency Mode  
-   uint8_t crc_error_clear = attribute_data; //CRC Error Clear  
-   uint8_t ca_parity_error_status = attribute_data; //C/A Parity Error Status  
-   uint8_t odt_input_buffer = attribute_data; //ODT Input Buffer during power down  
-   uint8_t rtt_park = attribute_data; //RTT_Park value  
-   uint8_t ca_parity = attribute_data; //CA Parity Persistance Error  
-   uint8_t data_mask = attribute_data; //Data Mask  
-   uint8_t write_dbi = attribute_data; //Write DBI  
-   uint8_t read_dbi = attribute_data; //Read DBI  
-   uint8_t vrefdq_train_value = attribute_data; //vrefdq_train value   
-   uint8_t vrefdq_train_range = attribute_data; //vrefdq_train range   
-   uint8_t vrefdq_train_enable = attribute_data; //vrefdq_train enable  
-   uint8_t tccd_l = attribute_data; //tccd_l  
-   uint8_t dram_access;
-
-   switch (attribute_name) {
-       case ATTR_EFF_DRAM_BL:
-	   if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8)
-           {
-               dram_bl = 0x00;
-           }
-           else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF)
-           {
-               dram_bl = 0x80;
-           }
-           else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4)
-           {
-               dram_bl = 0x40;
-           }
-	   rc_num = rc_num | address_16.insert((uint8_t) dram_bl, 0, 2, 0);
-	   break;
-       case ATTR_EFF_DRAM_RBT:
-	   if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL)
-           {
-               read_bt = 0x00;
-           }
-           else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE)
-           {
-               read_bt = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) read_bt, 3, 1, 0);
-	   break;
-       case ATTR_EFF_DRAM_CL:
-	   if ((dram_cl > 8)&&(dram_cl < 17))
-           {
-               dram_cl = dram_cl - 9; 
-           }
-           else if ((dram_cl > 17)&&(dram_cl < 25))
-           {
-               dram_cl = (dram_cl >> 1) - 1;   
-           }
-           dram_cl = mss_reverse_8bits(dram_cl);
-           rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 2, 1, 0);
-           rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 4, 3, 1);
-	   break;
-       case ATTR_EFF_DRAM_TM:
-	   if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL)
-           {
-               test_mode = 0x00;
-           }
-           else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST)
-           {
-               test_mode = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) test_mode, 7, 1);
-	   break;
-       case ATTR_EFF_DRAM_DLL_RESET:
-	   dll_reset = 0x00;
-	   FAPI_ERR( "ERROR: ATTR_EFF_DRAM_DLL_RESET accessed during PDA functionality, overwritten");
-           rc_num = rc_num | address_16.insert((uint8_t) dll_reset, 8, 1);
-	   break;
-       case ATTR_EFF_DRAM_WR:
-           if ( (dram_wr == 10) )//&& (dram_rtp == 5) )
-           {
-               dram_wr_rtp = 0x00;
-           }
-           else if ( (dram_wr == 12) )//&& (dram_rtp == 6) )
-           {
-               dram_wr_rtp = 0x80;
-           }
-           else if ( (dram_wr == 13) )//&& (dram_rtp == 7) )
-           {
-               dram_wr_rtp = 0x40;
-           }
-           else if ( (dram_wr == 14) )//&& (dram_rtp == 8) )
-           {
-               dram_wr_rtp = 0xC0;
-           }
-           else if ( (dram_wr == 18) )//&& (dram_rtp == 9) )
-           {
-               dram_wr_rtp = 0x20;
-           }
-           else if ( (dram_wr == 20) )//&& (dram_rtp == 10) )
-           {
-               dram_wr_rtp = 0xA0;
-           }
-           else if ( (dram_wr == 24) )//&& (dram_rtp == 12) )
-           {
-               dram_wr_rtp = 0x60;
-           }
-    	   rc_num = rc_num | address_16.insert((uint8_t) dram_wr_rtp, 9, 3);
-	   break;
-       case ATTR_EFF_DRAM_TRTP:
-           if ( (dram_rtp == 5) )
-           {
-               dram_wr_rtp = 0x00;
-           }
-           else if ( (dram_rtp == 6) )
-           {
-               dram_wr_rtp = 0x80;
-           }
-           else if ( (dram_rtp == 7) )
-           {
-               dram_wr_rtp = 0x40;
-           }
-           else if ( (dram_rtp == 8) )
-           {
-               dram_wr_rtp = 0xC0;
-           }
-           else if ( (dram_rtp == 9) )
-           {
-               dram_wr_rtp = 0x20;
-           }
-           else if ( (dram_rtp == 10) )
-           {
-               dram_wr_rtp = 0xA0;
-           }
-           else if ( (dram_rtp == 12) )
-           {
-               dram_wr_rtp = 0x60;
-           }
-    	   rc_num = rc_num | address_16.insert((uint8_t) dram_wr_rtp, 9, 3);
-	   break;
-       case ATTR_EFF_DRAM_DLL_PPD:
-           if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
-	   {
-               dll_precharge = 0x00;
-           }
-           else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT)
-           {
-               dll_precharge = 0xFF;
-           }
-	   FAPI_INF("ERROR: ATTR_EFF_DRAM_DLL_PPD is an unused MRS value!!! Skipping...");
-	   break;
-       case ATTR_EFF_DRAM_DLL_ENABLE:
-           if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE)
-           {
-               dll_enable = 0x00;
-           }
-           else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE)
-           {
-               dll_enable = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) dll_enable, 0, 1, 0);
-	   break;
-       case ATTR_VPD_DRAM_RON:
-	   if (out_drv_imp_cntl == ENUM_ATTR_VPD_DRAM_RON_OHM34)
-           {
-               out_drv_imp_cntl = 0x00;
-           }
-    	   // Not currently supported
-           else if (out_drv_imp_cntl == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported
-           {
-               out_drv_imp_cntl = 0x80;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) out_drv_imp_cntl, 1, 2, 0);
-	   break;
-       case ATTR_VPD_DRAM_RTT_NOM:
-	   if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)
-           {
-               dram_rtt_nom = 0x00;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported
-           {
-               dram_rtt_nom = 0x20;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported
-           {
-               dram_rtt_nom = 0xA0;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40)
-           {
-               dram_rtt_nom = 0xC0;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60)
-           {
-               dram_rtt_nom = 0x80;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120)
-           {
-               dram_rtt_nom = 0x40;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported
-           {
-               dram_rtt_nom = 0x60;
-           }
-           else if (dram_rtt_nom == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported
-           {
-               dram_rtt_nom = 0xE0;
-           }
-	   
-           rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_nom, 8, 3, 0);
-	   break;
-       case ATTR_EFF_DRAM_AL:
-	   if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE)
-           {
-               dram_al = 0x00;
-           }
-           else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1)
-           {
-               dram_al = 0x80;
-           }
-           else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2)
-           {
-               dram_al = 0x40;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) dram_al, 3, 2, 0);
-	   break;
-       case ATTR_EFF_DRAM_WR_LVL_ENABLE:
-	   if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE)
-           {
-               wr_lvl = 0x00;
-           }
-           else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE)
-           {
-               wr_lvl = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) wr_lvl, 7, 1, 0);
-	   break;
-       case ATTR_EFF_DRAM_TDQS:
-	   if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE)
-           {
-               tdqs_enable = 0x00;
-           }
-           else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE)
-           {
-               tdqs_enable = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) tdqs_enable, 11, 1, 0);
-	   break;
-       case ATTR_EFF_DRAM_OUTPUT_BUFFER:
-           if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE)
-           {
-               q_off = 0xFF;
-           }
-           else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE)
-           {
-               q_off = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) q_off, 12, 1, 0);
-	   break;
-       case ATTR_EFF_DRAM_LPASR:
-           if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL)
-           {
-               lpasr = 0x00;
-           }
-           else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED)
-           {
-               lpasr = 0x80;
-           }
-           else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED)
-           {
-               lpasr = 0x40;
-           }
-           else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR)
-           {
-               lpasr = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) lpasr, 6, 2);
-	   break;
-       case ATTR_EFF_DRAM_CWL:
-	   if ((cwl > 8)&&(cwl < 13))
-           {
-               cwl = cwl - 9; 
-           }
-           else if ((cwl > 13)&&(cwl < 19))
-           {
-               cwl = (cwl >> 1) - 3;   
-           }
-           else
-           {
-              //no correcct value for CWL was found
-              FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing...");
-              cwl = 0;
-           }
-	   cwl = mss_reverse_8bits(cwl);
-	   rc_num = rc_num | address_16.insert((uint8_t) cwl, 3, 3);
-	   break;
-       case ATTR_VPD_DRAM_RTT_WR:
-	   if (dram_rtt_wr == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE)
-           {
-               dram_rtt_wr = 0x00;
-           }
-           else if (dram_rtt_wr == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120)
-           {
-               dram_rtt_wr = 0x80;
-           }
-           else if (dram_rtt_wr == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240)
-           {
-               dram_rtt_wr = 0x40;
-           }
-           else if (dram_rtt_wr == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ)
-           {
-               dram_rtt_wr = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_wr, 9, 2);
-           break;
-       case ATTR_EFF_WRITE_CRC:
-	   if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE)
-           {
-               write_crc = 0xFF;
-           }
-           else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE)
-           {
-               write_crc = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) write_crc, 12, 1);
-	   break;
-       case ATTR_EFF_MPR_MODE:
-	   if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE)
-           {
-               mpr_op = 0xFF;
-           }
-           else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE)
-           {
-               mpr_op = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) mpr_op, 2, 1);
-	   break;
-       case ATTR_EFF_MPR_PAGE:
-           mpr_page = mss_reverse_8bits(mpr_page);
-    	   rc_num = rc_num | address_16.insert((uint8_t) mpr_page, 0, 2);
-	   break;
-       case ATTR_EFF_GEARDOWN_MODE:
-	   if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF)
-           {
-        	geardown_mode = 0x00;
-           }
-           else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER)
-           {
-        	geardown_mode = 0xFF;
-           }
-           
-           if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE)
-           {
-               temp_readout = 0xFF;
-           }
-           else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE)
-           {
-               temp_readout = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) geardown_mode, 3, 1);
-	   break;
-       case ATTR_EFF_TEMP_READOUT:
-	   if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE)
-    	   {
-    	       temp_readout = 0xFF;
-    	   }
-    	   else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE)
-    	   {
-    	       temp_readout = 0x00;
-    	   }
-           rc_num = rc_num | address_16.insert((uint8_t) temp_readout, 5, 1);
-	   break;
-       case ATTR_EFF_FINE_REFRESH_MODE:
-	   if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL)
-           {
-               fine_refresh = 0x00;
-           }
-           else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X)
-           {
-               fine_refresh = 0x80;
-           }
-           else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X)
-           {
-               fine_refresh = 0x40;
-           }
-           else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X)
-           {
-               fine_refresh = 0xA0;
-           }
-           else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X)
-           {
-               fine_refresh = 0x60;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) fine_refresh, 6, 3);
-	   break;
-       case ATTR_EFF_CRC_WR_LATENCY:
-           if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK)
-           {
-               wr_latency = 0x00;
-           }
-           else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK)
-           {
-               wr_latency = 0x80;
-           }
-           else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK)
-           {
-               wr_latency = 0xC0;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) wr_latency, 9, 2);
-	   break;
-       case ATTR_EFF_MPR_RD_FORMAT:
-           if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL)
-           {
-               read_format = 0x00;
-           }
-           else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL)
-           {
-               read_format = 0x80;
-           }
-           else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED)
-           {
-               read_format = 0x40;
-           }
-           else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP)
-           {
-               read_format = 0xC0;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) read_format, 11, 2);
-	   break;
-       case ATTR_EFF_PER_DRAM_ACCESS:
-           FAPI_INF("ERROR: ATTR_EFF_PER_DRAM_ACCESS selected.  Forcing PDA to be on for this function");
-	   dram_access = 0xFF;
-	   rc_num = rc_num | address_16.insert((uint8_t) dram_access, 4, 1);
-	   break;
-       case ATTR_EFF_MAX_POWERDOWN_MODE:
-	   if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE)
-           {
-               max_pd_mode = 0xF0;
-           }
-           else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE)
-           {
-               max_pd_mode = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) max_pd_mode, 1, 1);
-	   break;
-       case ATTR_EFF_TEMP_REF_RANGE:
-	   if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL)
-           {
-               temp_ref_range = 0x00;
-           }
-           else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND)
-           {
-               temp_ref_range = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) temp_ref_range, 2, 1);
-	   break;
-       case ATTR_EFF_TEMP_REF_MODE:
-	   if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE)
-           {
-               temp_ref_mode = 0x80;
-           }
-           else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE)
-           {
-               temp_ref_mode = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) temp_ref_mode, 3, 1);
-	   break;
-       case ATTR_EFF_INT_VREF_MON:
-	   if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE)
-           {
-               vref_mon = 0xFF;
-           }
-           else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE)
-           {
-               vref_mon = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) vref_mon, 4, 1);
-	   break;
-       case ATTR_EFF_CS_CMD_LATENCY:
-	   if ( cs_cmd_latency == 3)
-           {
-               cs_cmd_latency = 0x80;
-           }
-           else if (cs_cmd_latency == 4)
-           {
-               cs_cmd_latency = 0x40;
-           }
-           else if (cs_cmd_latency == 5)
-           {
-               cs_cmd_latency = 0xC0;
-           }
-           else if (cs_cmd_latency == 6)
-           {
-               cs_cmd_latency = 0x20;
-           }
-           else if (cs_cmd_latency == 8)
-           {
-               cs_cmd_latency = 0xA0;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) cs_cmd_latency, 6, 3);
-	   break;
-       case ATTR_EFF_SELF_REF_ABORT:
-	   if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE)
-           {
-               ref_abort = 0xFF;
-           }
-           else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE)
-           {
-               ref_abort = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) ref_abort, 9, 1);
-	   break;
-       case ATTR_EFF_RD_PREAMBLE_TRAIN:
-	   if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE)
-           {
-               rd_pre_train_mode = 0xFF;
-           }
-           else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE)
-           {
-               rd_pre_train_mode = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) rd_pre_train_mode, 10, 1);
-	   break;
-       case ATTR_EFF_RD_PREAMBLE:
-	   if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK)
-           {
-               rd_preamble = 0x00;
-           }
-           else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK)
-           {
-               rd_preamble = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) rd_preamble, 11, 1);
-	   break;
-       case ATTR_EFF_WR_PREAMBLE:
-           if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK)
-           {
-               wr_preamble = 0x00;
-           }
-           else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK)
-           {
-               wr_preamble = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) wr_preamble, 12, 1);
-	   break;
-       case ATTR_EFF_CA_PARITY_LATENCY:
-	   if (ca_parity_latency == 4)
-           {
-               ca_parity_latency = 0x80;
-           }
-           else if (ca_parity_latency == 5)
-           {
-               ca_parity_latency = 0x40;
-           }
-           else if (ca_parity_latency == 6)
-           {
-               ca_parity_latency = 0xC0;
-           }
-           else if (ca_parity_latency == 8)
-           {
-               ca_parity_latency = 0x20;
-           }
-           else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE)
-           {
-               ca_parity_latency = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) ca_parity_latency, 0, 2);
-	   break;
-       case ATTR_EFF_CRC_ERROR_CLEAR:
-	   if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR)
-           {
-               crc_error_clear = 0xFF;
-           }
-           else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR)
-           {
-               crc_error_clear = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) crc_error_clear, 3, 1);
-	   break;
-       case ATTR_EFF_CA_PARITY_ERROR_STATUS:
-	   if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR)
-           {
-               ca_parity_error_status = 0xFF;
-           }
-           else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR)
-           {
-               ca_parity_error_status = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) ca_parity_error_status, 4, 1);
-	   break;
-       case ATTR_EFF_ODT_INPUT_BUFF:
-	   if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED)
-           {
-               odt_input_buffer = 0x00;
-           }
-           else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED)
-           {
-               odt_input_buffer = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) odt_input_buffer, 5, 1);
-	   break;
-       case ATTR_EFF_RTT_PARK:
-	   if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_DISABLE)
-           {
-               rtt_park = 0x00;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_60OHM)
-           {
-               rtt_park = 0x80;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_40OHM)
-           {
-               rtt_park = 0xC0;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_120OHM)
-           {
-               rtt_park = 0x40;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_240OHM)
-           {
-               rtt_park = 0x20;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_48OHM)
-           {
-               rtt_park = 0xA0;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_80OHM)
-           {
-               rtt_park = 0x60;
-           }
-           else if (rtt_park == ENUM_ATTR_EFF_RTT_PARK_34OHM)
-           {
-               rtt_park = 0xE0;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) rtt_park, 6, 3);
-	   break;
-       case ATTR_EFF_CA_PARITY:
-	   if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE)
-           {
-               ca_parity = 0xFF;
-           }
-           else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE)
-           {
-               ca_parity = 0x00;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) ca_parity, 9, 1);
-	   break;
-       case ATTR_EFF_DATA_MASK:
-	   if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE)
-           {
-               data_mask = 0x00;
-           }
-           else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE)
-           {
-               data_mask = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) data_mask, 10, 1);
-	   break;
-       case ATTR_EFF_WRITE_DBI:
-	   if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE)
-           {
-               write_dbi = 0x00;
-           }
-           else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE)
-           {
-               write_dbi = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) write_dbi, 11, 1);
-	   break;
-       case ATTR_EFF_READ_DBI:
-           if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE)
-           {
-               read_dbi = 0x00;
-           }
-           else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE)
-           {
-               read_dbi = 0xFF;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) read_dbi, 12, 1);
-	   break;
-       case ATTR_VREF_DQ_TRAIN_VALUE:
-	   vrefdq_train_value = mss_reverse_8bits(vrefdq_train_value);
-           rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_value, 0, 6);
-	   break;
-       case ATTR_VREF_DQ_TRAIN_RANGE:
-	   if (vrefdq_train_range == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1)
-           {
-               vrefdq_train_range = 0x00;
-           }
-           else if (vrefdq_train_range == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2)
-           {
-               vrefdq_train_range = 0xFF;
-           } 
-           rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_range, 6, 1);
-	   break;
-       case ATTR_VREF_DQ_TRAIN_ENABLE:
-	   if (vrefdq_train_enable == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE)
-           {
-               vrefdq_train_enable = 0xFF;
-           }
-           else if (vrefdq_train_enable == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE)
-           {
-               vrefdq_train_enable = 0x00;
-           }   
-           rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_enable, 7, 1);
-	   break;
-       case ATTR_TCCD_L:
-           if (tccd_l == 4)
-           {
-               tccd_l = 0x00;
-           }
-           else if (tccd_l == 5)
-           {
-               tccd_l = 0x80;
-           }
-           else if (tccd_l == 6)
-           {
-               tccd_l = 0x40;
-           }	
-           else if (tccd_l == 7)
-           {
-               tccd_l = 0xC0;
-           }
-           else if (tccd_l == 8)
-           {
-               tccd_l = 0x20;
-           }
-           rc_num = rc_num | address_16.insert((uint8_t) tccd_l, 10, 3);
-	   break;
-	//MRS attribute not found, error out
-      default: 
-         const uint32_t NONMRS_ATTR_NAME = attribute_name;
-	 const fapi::Target & MBA_TARGET = i_target; 
-	 FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_NONMRS_ATTR_NAME);
-	 FAPI_ERR("ERROR!! Found attribute name not associated with an MRS! Exiting...");
-   }
-   if (rc_num)
-   {
-       FAPI_ERR( "mss_ddr4_modify_mrs_pda: Error setting up buffers");
-       rc.setEcmdError(rc_num);
-       return rc;
-   }
-   return rc;
-}
-
-//////////////////////////////////////////////////////////////////////////////////
-/// mss_ddr4_load_nominal_mrs_pda
-/// disables per-DRAM addressability funcitonality on both ports on the passed MBA
-//////////////////////////////////////////////////////////////////////////////////
-ReturnCode mss_ddr4_load_nominal_mrs_pda(Target& i_target,ecmdDataBufferBase& bank_3,ecmdDataBufferBase& address_16,uint8_t MRS,uint8_t i_port_number, uint8_t dimm_number, uint8_t rank_number) {
-    ReturnCode rc;  
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    
-    rc_num = rc_num | address_16.clearBit(0,16);
-    rc_num = rc_num | bank_3.clearBit(0,3);
-    if (rc_num)
-    {
-    	FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-    	rc_buff.setEcmdError(rc_num);
-    	return rc_buff;
-    }
-
-    //Lines commented out in the following section are waiting for xml attribute adds
-    //MRS0
-    if(MRS == MRS0_BA) {
-    	uint8_t dram_bl;
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BL, &i_target, dram_bl);
-    	if(rc) return rc;
-    	uint8_t read_bt; //Read Burst Type 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_RBT, &i_target, read_bt);
-    	if(rc) return rc;
-    	uint8_t dram_cl;
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CL, &i_target, dram_cl);
-    	if(rc) return rc;
-    	uint8_t test_mode; //TEST MODE 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TM, &i_target, test_mode);
-    	if(rc) return rc;
-    	uint8_t dll_reset; //DLL Reset 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_RESET, &i_target, dll_reset);
-    	if(rc) return rc;
-    	uint8_t dram_wr; //DRAM write recovery
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR, &i_target, dram_wr);
-    	if(rc) return rc;
-    	uint8_t dram_rtp; //DRAM RTP - read to precharge
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TRTP, &i_target, dram_rtp);
-    	if(rc) return rc;
-    	uint8_t dll_precharge; //DLL Control For Precharge 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_PPD, &i_target, dll_precharge);
-    	if(rc) return rc;
-
-    	if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BL8)
-    	{
-    	    dram_bl = 0x00;
-    	}
-    	else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_OTF)
-    	{
-    	    dram_bl = 0x80;
-    	}
-    	else if (dram_bl == ENUM_ATTR_EFF_DRAM_BL_BC4)
-    	{
-    	    dram_bl = 0x40;
-    	}
-
-    	uint8_t dram_wr_rtp = 0x00;
-    	if ( (dram_wr == 10) )//&& (dram_rtp == 5) )
-    	{
-    	    dram_wr_rtp = 0x00;
-    	}
-    	else if ( (dram_wr == 12) )//&& (dram_rtp == 6) )
-    	{
-    	    dram_wr_rtp = 0x80;
-    	}
-    	else if ( (dram_wr == 13) )//&& (dram_rtp == 7) )
-    	{
-    	    dram_wr_rtp = 0x40;
-    	}
-    	else if ( (dram_wr == 14) )//&& (dram_rtp == 8) )
-    	{
-    	    dram_wr_rtp = 0xC0;
-    	}
-    	else if ( (dram_wr == 18) )//&& (dram_rtp == 9) )
-    	{
-    	    dram_wr_rtp = 0x20;
-    	}
-    	else if ( (dram_wr == 20) )//&& (dram_rtp == 10) )
-    	{
-    	    dram_wr_rtp = 0xA0;
-    	}
-    	else if ( (dram_wr == 24) )//&& (dram_rtp == 12) )
-    	{
-    	    dram_wr_rtp = 0x60;
-    	}
-
-    	if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_SEQUENTIAL)
-    	{
-    	    read_bt = 0x00;
-    	}
-    	else if (read_bt == ENUM_ATTR_EFF_DRAM_RBT_INTERLEAVE)
-    	{
-    	    read_bt = 0xFF;
-    	}
-
-    	if ((dram_cl > 8)&&(dram_cl < 17))
-    	{
-    	    dram_cl = dram_cl - 9; 
-    	}
-    	else if ((dram_cl > 17)&&(dram_cl < 25))
-    	{
-    	    dram_cl = (dram_cl >> 1) - 1;   
-    	}
-    	dram_cl = mss_reverse_8bits(dram_cl);
-
-    	if (test_mode == ENUM_ATTR_EFF_DRAM_TM_NORMAL)
-    	{
-    	    test_mode = 0x00;
-    	}
-    	else if (test_mode == ENUM_ATTR_EFF_DRAM_TM_TEST)
-    	{
-    	    test_mode = 0xFF;
-    	}
-	
-	FAPI_INF("Overwriting DLL reset with values to not reset the DRAM.");
-    	dll_reset = 0x00;
-
-    	if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT)
-    	{
-    	    dll_precharge = 0x00;
-    	}
-    	else if (dll_precharge == ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT)
-    	{
-    	    dll_precharge = 0xFF;
-    	}
-	//For DDR4:
-	//Address 14 = Address 17, Address 15 = BG1
-        rc_num = rc_num | address_16.insert((uint8_t) dram_bl, 0, 2, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 2, 1, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) read_bt, 3, 1, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) dram_cl, 4, 3, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) test_mode, 7, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) dll_reset, 8, 1);
-	rc_num = rc_num | address_16.insert((uint8_t) dram_wr_rtp, 9, 3);
-	rc_num = rc_num | address_16.insert((uint8_t) 0x00, 12, 4);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS0_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    
-    //MRS1
-    else if(MRS == MRS1_BA) {
-    	uint8_t dll_enable; //DLL Enable 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable);
-    	if(rc) return rc;
-    	uint8_t out_drv_imp_cntl[2][2];
-    	rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl);
-    	if(rc) return rc;
-    	uint8_t dram_rtt_nom[2][2][4];
-    	rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom);
-    	if(rc) return rc;
-    	uint8_t dram_al;
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al);
-    	if(rc) return rc;
-    	uint8_t wr_lvl; //write leveling enable
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl);
-    	if(rc) return rc;
-    	uint8_t tdqs_enable; //TDQS Enable 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable);
-    	if(rc) return rc;
-    	uint8_t q_off; //Qoff - Output buffer Enable 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off);
-    	if(rc) return rc;
-
-    	if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE)
-    	{
-    	    dll_enable = 0x00;
-    	}
-    	else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE)
-    	{
-    	    dll_enable = 0xFF;
-    	}
-
-    	if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE)
-    	{
-    	    dram_al = 0x00;
-    	}
-    	else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1)
-    	{
-    	    dram_al = 0x80;
-    	}
-    	else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2)
-    	{
-    	    dram_al = 0x40;
-    	}
-
-    	if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE)
-    	{
-    	    wr_lvl = 0x00;
-    	}
-    	else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE)
-    	{
-    	    wr_lvl = 0xFF;
-    	}
-
-    	if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE)
-    	{
-    	    tdqs_enable = 0x00;
-    	}
-    	else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE)
-    	{
-    	    tdqs_enable = 0xFF;
-    	}
-
-    	if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE)
-    	{
-    	    q_off = 0xFF;
-    	}
-    	else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE)
-    	{
-    	    q_off = 0x00;
-    	}
-        if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240) //not supported
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48) //not supported
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40)
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60)
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120)
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80) // not supported
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x60;
-        }
-        else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34) // not supported
-        {
-            dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xE0;
-        }
-
-        if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34)
-        {
-            out_drv_imp_cntl[i_port_number][dimm_number] = 0x00;
-        }
-	// Not currently supported
-        else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM48) //not supported
-        {
-            out_drv_imp_cntl[i_port_number][dimm_number] = 0x80;
-        }
-
-	//For DDR4:
-	//Address 14 = Address 17, Address 15 = BG1
-        rc_num = rc_num | address_16.insert((uint8_t) dll_enable, 0, 1, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 2, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) dram_al, 3, 2, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 5, 2);
-        rc_num = rc_num | address_16.insert((uint8_t) wr_lvl, 7, 1, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 8, 3, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) tdqs_enable, 11, 1, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) q_off, 12, 1, 0);
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 3);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    //MRS2
-    else if(MRS == MRS2_BA) {
-    	uint8_t lpasr; // Low Power Auto Self-Refresh -- new not yet supported
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_LPASR, &i_target, lpasr);
-    	if(rc) return rc;
-    	uint8_t cwl; // CAS Write Latency 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_CWL, &i_target, cwl);
-    	if(rc) return rc;
-    	uint8_t dram_rtt_wr[2][2][4];
-    	rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target, dram_rtt_wr);
-    	if(rc) return rc;
-    	uint8_t write_crc; // CAS Write Latency 
-    	rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_CRC, &i_target, write_crc);
-    	if(rc) return rc;
-
-    	if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL)
-    	{
-    	    lpasr = 0x00;
-    	}
-    	else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_REDUCED)
-    	{
-    	    lpasr = 0x80;
-    	}
-    	else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_EXTENDED)
-    	{
-    	    lpasr = 0x40;
-    	}
-    	else if (lpasr == ENUM_ATTR_EFF_DRAM_LPASR_ASR)
-    	{
-    	    lpasr = 0xFF;
-    	}
-
-    	if ((cwl > 8)&&(cwl < 13))
-    	{
-    	    cwl = cwl - 9; 
-    	}
-    	else if ((cwl > 13)&&(cwl < 19))
-    	{
-    	    cwl = (cwl >> 1) - 3;   
-    	}
-    	else
-    	{
-    	   //no correcct value for CWL was found
-    	   FAPI_INF("ERROR: Improper CWL value found. Setting CWL to 9 and continuing...");
-    	   cwl = 0;
-    	}
-    	cwl = mss_reverse_8bits(cwl);
-
-    	if ( write_crc == ENUM_ATTR_EFF_WRITE_CRC_ENABLE)
-    	{
-    	    write_crc = 0xFF;
-    	}
-    	else if (write_crc == ENUM_ATTR_EFF_WRITE_CRC_DISABLE)
-    	{
-    	    write_crc = 0x00;
-    	}
-	if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE)
-        {
-            dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x00;
-        }
-        else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120)
-        {
-            dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x80;
-        }
-        else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 240)//ENUM_ATTR_EFF_DRAM_RTT_WR_OHM240)
-        {
-            dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40;
-        }
-        else if (dram_rtt_wr[i_port_number][dimm_number][rank_number] == 0xFF)//ENUM_ATTR_EFF_DRAM_RTT_WR_HIGHZ)
-        {
-            dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0xFF;
-        }
-
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 0, 3);
-        rc_num = rc_num | address_16.insert((uint8_t) cwl, 3, 3);
-        rc_num = rc_num | address_16.insert((uint8_t) lpasr, 6, 2);
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 8, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) dram_rtt_wr[i_port_number][dimm_number][rank_number], 9, 2);
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 11, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) write_crc, 12, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS2_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    //MRS3
-    else if(MRS == MRS3_BA) {
-    	uint8_t mpr_op; // MPR Op
-    	rc = FAPI_ATTR_GET(ATTR_EFF_MPR_MODE, &i_target, mpr_op);
-    	if(rc) return rc;
-    	uint8_t mpr_page; // MPR Page Selection  - NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_MPR_PAGE, &i_target, mpr_page);
-    	if(rc) return rc;
-    	uint8_t geardown_mode; // Gear Down Mode  - NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_GEARDOWN_MODE, &i_target, geardown_mode);
-    	if(rc) return rc;
-    	uint8_t temp_readout; // Temperature sensor readout  - NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_READOUT, &i_target, temp_readout);
-    	if(rc) return rc;
-    	uint8_t fine_refresh; // fine refresh mode  - NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_FINE_REFRESH_MODE, &i_target, fine_refresh);
-    	if(rc) return rc;
-    	uint8_t wr_latency; // write latency for CRC and DM  - NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_CRC_WR_LATENCY, &i_target, wr_latency);
-    	if(rc) return rc;
-    	uint8_t read_format; // MPR READ FORMAT  - NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_MPR_RD_FORMAT, &i_target, read_format);
-    	if(rc) return rc;
-
-    	if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_ENABLE)
-    	{
-    	    mpr_op = 0xFF;
-    	}
-    	else if (mpr_op == ENUM_ATTR_EFF_MPR_MODE_DISABLE)
-    	{
-    	    mpr_op = 0x00;
-    	}
-
-    	mpr_page = mss_reverse_8bits(mpr_page);
-
-    	if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_HALF)
-    	{
-    	     geardown_mode = 0x00;
-    	}
-    	else if ( geardown_mode == ENUM_ATTR_EFF_GEARDOWN_MODE_QUARTER)
-    	{
-    	     geardown_mode = 0xFF;
-    	}
-    	
-    	if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_ENABLE)
-    	{
-    	    temp_readout = 0xFF;
-    	}
-    	else if (temp_readout == ENUM_ATTR_EFF_TEMP_READOUT_DISABLE)
-    	{
-    	    temp_readout = 0x00;
-    	}
-
-    	if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL)
-    	{
-    	    fine_refresh = 0x00;
-    	}
-    	else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_2X)
-    	{
-    	    fine_refresh = 0x80;
-    	}
-    	else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FIXED_4X)
-    	{
-    	    fine_refresh = 0x40;
-    	}
-    	else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_2X)
-    	{
-    	    fine_refresh = 0xA0;
-    	}
-    	else if (fine_refresh == ENUM_ATTR_EFF_FINE_REFRESH_MODE_FLY_4X)
-    	{
-    	    fine_refresh = 0x60;
-    	}
-
-    	if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK)
-    	{
-    	    wr_latency = 0x00;
-    	}
-    	else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_5NCK)
-    	{
-    	    wr_latency = 0x80;
-    	}
-    	else if (wr_latency == ENUM_ATTR_EFF_CRC_WR_LATENCY_6NCK)
-    	{
-    	    wr_latency = 0xC0;
-    	}
-
-    	if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL)
-    	{
-    	    read_format = 0x00;
-    	}
-    	else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_PARALLEL)
-    	{
-    	    read_format = 0x80;
-    	}
-    	else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_STAGGERED)
-    	{
-    	    read_format = 0x40;
-    	}
-    	else if (read_format == ENUM_ATTR_EFF_MPR_RD_FORMAT_RESERVED_TEMP)
-    	{
-    	    read_format = 0xC0;
-    	}
-	
-	rc_num = rc_num | address_16.insert((uint8_t) mpr_page, 0, 2);
-        rc_num = rc_num | address_16.insert((uint8_t) mpr_op, 2, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) geardown_mode, 3, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) 0xFF, 4, 1); //has PDA mode enabled!!!! just for this code!
-        rc_num = rc_num | address_16.insert((uint8_t) temp_readout, 5, 1);
-        rc_num = rc_num | address_16.insert((uint8_t) fine_refresh, 6, 3);
-        rc_num = rc_num | address_16.insert((uint8_t) wr_latency, 9, 2);
-        rc_num = rc_num | address_16.insert((uint8_t) read_format, 11, 2);
-        rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS3_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    //MRS4
-    else if(MRS == MRS4_BA) {
-    	uint8_t max_pd_mode; // Max Power down mode -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_MAX_POWERDOWN_MODE, &i_target, max_pd_mode);
-    	if(rc) return rc;
-    	uint8_t temp_ref_range; // Temp ref range -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_RANGE, &i_target, temp_ref_range);
-    	if(rc) return rc;
-    	uint8_t temp_ref_mode; // Temp controlled ref mode -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_TEMP_REF_MODE, &i_target, temp_ref_mode);
-    	if(rc) return rc;
-    	uint8_t vref_mon; // Internal Vref Monitor -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_INT_VREF_MON, &i_target, vref_mon);
-    	if(rc) return rc;
-    	uint8_t cs_cmd_latency; // CS to CMD/ADDR Latency -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_CS_CMD_LATENCY, &i_target, cs_cmd_latency);
-    	if(rc) return rc;
-    	uint8_t ref_abort; // Self Refresh Abort -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_SELF_REF_ABORT, &i_target, ref_abort);
-    	if(rc) return rc;
-    	uint8_t rd_pre_train_mode; // Read Pre amble Training Mode -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE_TRAIN, &i_target, rd_pre_train_mode);
-    	if(rc) return rc;
-    	uint8_t rd_preamble; // Read Pre amble -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_RD_PREAMBLE, &i_target, rd_preamble);
-    	if(rc) return rc;
-    	uint8_t wr_preamble; // Write Pre amble -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_WR_PREAMBLE, &i_target, wr_preamble);
-    	if(rc) return rc;
-
-    	if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_ENABLE)
-    	{
-    	    max_pd_mode = 0xF0;
-    	}
-    	else if ( max_pd_mode == ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE)
-    	{
-    	    max_pd_mode = 0x00;
-    	}
-
-    	if (temp_ref_range == ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL)
-    	{
-    	    temp_ref_range = 0x00;
-    	}
-    	else if ( temp_ref_range== ENUM_ATTR_EFF_TEMP_REF_RANGE_EXTEND)
-    	{
-    	    temp_ref_range = 0xFF;
-    	}
-
-    	if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE)
-    	{
-    	    temp_ref_mode = 0x80;
-    	}
-    	else if (temp_ref_mode == ENUM_ATTR_EFF_TEMP_REF_MODE_DISABLE)
-    	{
-    	    temp_ref_mode = 0x00;
-    	}
-
-    	if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_ENABLE)
-    	{
-    	    vref_mon = 0xFF;
-    	}
-    	else if ( vref_mon == ENUM_ATTR_EFF_INT_VREF_MON_DISABLE)
-    	{
-    	    vref_mon = 0x00;
-    	}
-
-
-    	if ( cs_cmd_latency == 3)
-    	{
-    	    cs_cmd_latency = 0x80;
-    	}
-    	else if (cs_cmd_latency == 4)
-    	{
-    	    cs_cmd_latency = 0x40;
-    	}
-    	else if (cs_cmd_latency == 5)
-    	{
-    	    cs_cmd_latency = 0xC0;
-    	}
-    	else if (cs_cmd_latency == 6)
-    	{
-    	    cs_cmd_latency = 0x20;
-    	}
-    	else if (cs_cmd_latency == 8)
-    	{
-    	    cs_cmd_latency = 0xA0;
-    	}
-
-    	if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_ENABLE)
-    	{
-    	    ref_abort = 0xFF;
-    	}
-    	else if (ref_abort == ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE)
-    	{
-    	    ref_abort = 0x00;
-    	}
-
-    	if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_ENABLE)
-    	{
-    	    rd_pre_train_mode = 0xFF;
-    	}
-    	else if (rd_pre_train_mode == ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE)
-    	{
-    	    rd_pre_train_mode = 0x00;
-    	}
-
-    	if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK)
-    	{
-    	    rd_preamble = 0x00;
-    	}
-    	else if (rd_preamble == ENUM_ATTR_EFF_RD_PREAMBLE_2NCLK)
-    	{
-    	    rd_preamble = 0xFF;
-    	}
-
-    	if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK)
-    	{
-    	    wr_preamble = 0x00;
-    	}
-    	else if (wr_preamble == ENUM_ATTR_EFF_WR_PREAMBLE_2NCLK)
-    	{
-    	    wr_preamble = 0xFF;
-    	}
-    	rc_num = rc_num | address_16.insert((uint8_t) 0x00, 0, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) max_pd_mode, 1, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) temp_ref_range, 2, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) temp_ref_mode, 3, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) vref_mon, 4, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) 0x00, 5, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) cs_cmd_latency, 6, 3);
-    	rc_num = rc_num | address_16.insert((uint8_t) ref_abort, 9, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) rd_pre_train_mode, 10, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) rd_preamble, 11, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) wr_preamble, 12, 1);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS4_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    //MRS5
-    else if(MRS == MRS5_BA) {
-    	uint8_t ca_parity_latency; //C/A Parity Latency Mode  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_LATENCY , &i_target, ca_parity_latency);
-    	if(rc) return rc;
-    	uint8_t crc_error_clear; //CRC Error Clear  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_CRC_ERROR_CLEAR , &i_target, crc_error_clear);
-    	if(rc) return rc;
-    	uint8_t ca_parity_error_status; //C/A Parity Error Status  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY_ERROR_STATUS , &i_target, ca_parity_error_status);
-    	if(rc) return rc;
-    	uint8_t odt_input_buffer; //ODT Input Buffer during power down  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_ODT_INPUT_BUFF , &i_target, odt_input_buffer);
-    	if(rc) return rc;
-    	uint8_t rtt_park[2][2][4]; //RTT_Park value  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_RTT_PARK , &i_target, rtt_park);
-    	if(rc) return rc;
-    	uint8_t ca_parity; //CA Parity Persistance Error  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_CA_PARITY , &i_target, ca_parity);
-    	if(rc) return rc;
-    	uint8_t data_mask; //Data Mask  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_DATA_MASK , &i_target, data_mask);
-    	if(rc) return rc;
-    	uint8_t write_dbi; //Write DBI  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_WRITE_DBI , &i_target, write_dbi);
-    	if(rc) return rc;
-    	uint8_t read_dbi; //Read DBI  -  NEW
-    	rc = FAPI_ATTR_GET(ATTR_EFF_READ_DBI , &i_target, read_dbi);
-    	if(rc) return rc;
-
-
-    	if (ca_parity_latency == 4)
-    	{
-    	    ca_parity_latency = 0x80;
-    	}
-    	else if (ca_parity_latency == 5)
-    	{
-    	    ca_parity_latency = 0x40;
-    	}
-    	else if (ca_parity_latency == 6)
-    	{
-    	    ca_parity_latency = 0xC0;
-    	}
-    	else if (ca_parity_latency == 8)
-    	{
-    	    ca_parity_latency = 0x20;
-    	}
-    	else if (ca_parity_latency == ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE)
-    	{
-    	    ca_parity_latency = 0x00;
-    	}
-
-    	if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR)
-    	{
-    	    crc_error_clear = 0xFF;
-    	}
-    	else if (crc_error_clear == ENUM_ATTR_EFF_CRC_ERROR_CLEAR_CLEAR)
-    	{
-    	    crc_error_clear = 0x00;
-    	}
-
-    	if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR)
-    	{
-    	    ca_parity_error_status = 0xFF;
-    	}
-    	else if (ca_parity_error_status == ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_CLEAR)
-    	{
-    	    ca_parity_error_status = 0x00;
-    	}
-
-    	if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED)
-    	{
-    	    odt_input_buffer = 0x00;
-    	}
-    	else if (odt_input_buffer == ENUM_ATTR_EFF_ODT_INPUT_BUFF_DEACTIVATED)
-    	{
-    	    odt_input_buffer = 0xFF;
-    	}
-
-
-    	if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_ENABLE)
-    	{
-    	    ca_parity = 0xFF;
-    	}
-    	else if (ca_parity == ENUM_ATTR_EFF_CA_PARITY_DISABLE)
-    	{
-    	    ca_parity = 0x00;
-    	}
-
-    	if (data_mask == ENUM_ATTR_EFF_DATA_MASK_DISABLE)
-    	{
-    	    data_mask = 0x00;
-    	}
-    	else if (data_mask == ENUM_ATTR_EFF_DATA_MASK_ENABLE)
-    	{
-    	    data_mask = 0xFF;
-    	}
-
-    	if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_DISABLE)
-    	{
-    	    write_dbi = 0x00;
-    	}
-    	else if (write_dbi == ENUM_ATTR_EFF_WRITE_DBI_ENABLE)
-    	{
-    	    write_dbi = 0xFF;
-    	}
-
-    	if (read_dbi == ENUM_ATTR_EFF_READ_DBI_DISABLE)
-    	{
-    	    read_dbi = 0x00;
-    	}
-    	else if (read_dbi == ENUM_ATTR_EFF_READ_DBI_ENABLE)
-    	{
-    	    read_dbi = 0xFF;
-    	}
-    	if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_DISABLE)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0x00;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_60OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0x80;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_40OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0xC0;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_120OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0x40;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_240OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0x20;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_48OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0xA0;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_80OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0x60;
-    	}
-    	else if (rtt_park[i_port_number][dimm_number][rank_number] == ENUM_ATTR_EFF_RTT_PARK_34OHM)
-    	{
-    	    rtt_park[i_port_number][dimm_number][rank_number] = 0xE0;
-    	}
-
-    	rc_num = rc_num | address_16.insert((uint8_t) ca_parity_latency, 0, 2);
-    	rc_num = rc_num | address_16.insert((uint8_t) crc_error_clear, 3, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) ca_parity_error_status, 4, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) odt_input_buffer, 5, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) rtt_park[i_port_number][dimm_number][rank_number], 6, 3);
-    	rc_num = rc_num | address_16.insert((uint8_t) ca_parity, 9, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) data_mask, 10, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) write_dbi, 11, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) read_dbi, 12, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS5_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    //MRS6
-    else if(MRS == MRS6_BA) {
-    	uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value   -  NEW
-    	rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value);
-    	if(rc) return rc;
-    	uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range   -  NEW
-    	rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range);
-    	if(rc) return rc;
-    	uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable  -  NEW
-    	rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable);
-    	if(rc) return rc;
-    	uint8_t tccd_l; //tccd_l  -  NEW
-    	rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l);
-    	if(rc) return rc;
-    	if (tccd_l == 4)
-    	{
-    	    tccd_l = 0x00;
-    	}
-    	else if (tccd_l == 5)
-    	{
-    	    tccd_l = 0x80;
-    	}
-    	else if (tccd_l == 6)
-    	{
-    	    tccd_l = 0x40;
-    	}    
-    	else if (tccd_l == 7)
-    	{
-    	    tccd_l = 0xC0;
-    	}
-    	else if (tccd_l == 8)
-    	{
-    	    tccd_l = 0x20;
-    	}
-
-    	vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]);
-
-    	if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1)
-    	{
-    	    vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00;
-    	}
-    	else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2)
-    	{
-    	    vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF;
-    	}   
-
-    	if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE)
-    	{
-    	    vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xFF;
-    	}
-    	else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE)
-    	{
-    	    vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00;
-    	}   
-
-    	rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6);
-    	rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1);
-    	rc_num = rc_num | address_16.insert((uint8_t) 0x00, 8, 2);
-    	rc_num = rc_num | address_16.insert((uint8_t) tccd_l, 10, 3);
-    	rc_num = rc_num | address_16.insert((uint8_t) 0x00, 13, 2);
-	
-	rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6);
-        rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5);
-	if (rc_num)
-        {
-            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-    }
-    else {
-        const uint32_t MRS_VALUE = MRS;
-	const fapi::Target & MBA_TARGET = i_target; 
-	FAPI_SET_HWP_ERROR(rc, RC_MSS_PDA_MRS_NOT_FOUND);
-	FAPI_ERR("ERROR!! Found attribute name not associated with an MRS! Exiting...");
-    }
-    
-    return rc;
-}
-}
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H
deleted file mode 100644
index ac136bdfb..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H
+++ /dev/null
@@ -1,177 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_ddr4_pda.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_ddr4_pda.H,v 1.38 2015/07/27 14:49:59 sglancy Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_ddr4_pda.H
-// *! DESCRIPTION : Tools for DDR4 DIMMs centaur procedures
-// *! OWNER NAME  : Stephen Glancy       Email: sglancy@us.ibm.com
-// *! BACKUP NAME : Andre Marin     Email: aamarin@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.5    | 05/13/15 | sglancy | Added dox and updated functions for better FFDC
-//  1.4    | 05/11/15 | sglancy | Addressed FW comments
-//  1.3    | 05/07/15 | sglancy | Updated Doxygen header
-//  1.2    | 02/13/15 | sglancy | Updated to allow for file inputs
-//  1.1    | 10/27/14 | sglancy | First revision
-
-#ifndef _MSS_DDR4_PDA_H
-#define _MSS_DDR4_PDA_H
-#include <fapi.H>
-using namespace fapi;
-using namespace std;
-class PDA_MRS_Storage {
-private:
-   char pda_string[MAX_ECMD_STRING_LEN]; //aware that this isn't threadsafe but should be called w/in each thread
-public:
-   uint8_t attribute_data;
-   uint32_t attribute_name;
-   uint8_t MRS;
-   uint8_t dimm;
-   uint8_t dram;
-   uint8_t rank;
-   uint8_t port;
-   PDA_MRS_Storage(uint8_t ad,uint32_t an,uint8_t dr,uint8_t di,uint8_t r,uint8_t p);
-   ~PDA_MRS_Storage();
-   bool operator> (const PDA_MRS_Storage &PDA2) const;
-   bool operator< (const PDA_MRS_Storage &PDA2) const;
-   void copy(PDA_MRS_Storage &temp);
-   ReturnCode setMRSbyAttr(Target& i_target);
-   ReturnCode checkPDAValid(Target& i_target);
-   char * c_str();
-   void generatePDAString();
-};
-
-class PDA_Scom_Storage {
-public:
-   uint64_t scom_addr;
-   uint32_t start_bit;
-   uint32_t num_bits;
-   PDA_Scom_Storage(uint64_t sa, uint32_t sb, uint32_t nb);
-   ~PDA_Scom_Storage();
-};
-
-typedef ReturnCode (*mss_ddr4_pda_FP_t)(Target& i_target, vector<PDA_MRS_Storage> pda);
-
-extern "C"
-{
-
-/**
- * @runs through the vector of given PDA values and issues the PDA commands to the requested DRAMs
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in]  vector:  Vector of PDA_MRS_Storage class elements - initialized by the user and contains DRAM information and attribute override information
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_run_pda(Target& i_target,vector<PDA_MRS_Storage> pda);
-/**
- * @Puts the DRAM in per-DRAM addressability mode (PDA mode)
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in/out]  io_ccs_inst_cnt: starting point of CCS array - needed to properly setup CCS
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_setup_pda(Target& i_target,uint32_t& io_ccs_inst_cnt);
-/**
- * @Takes the DRAM out of per-DRAM addressability mode (PDA mode)
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in/out]  io_ccs_inst_cnt: starting point of CCS array - needed to properly setup CCS
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_disable_pda(Target& i_target,uint32_t& io_ccs_inst_cnt);
-/**
- * @called by wrapper - sets up a PDA vector if it's not already configured
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in]  vector:  Vector of PDA_MRS_Storage class elements - initialized by the user and contains DRAM information and attribute override information
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_pda(Target& i_target,vector<PDA_MRS_Storage> pda);
-/**
- * @Checks the passed in PDA vector to ensure that all entries are good. then sorts the vector to ensure more efficient command stream
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in/out]  vector:  Vector of PDA_MRS_Storage class elements - initialized by the user and contains DRAM information and attribute override information
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_checksort_pda(Target& i_target, vector<PDA_MRS_Storage>& pda);
-/**
- * @Modifies the passed in address_16 buffer based upon the given attribute and data
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in/out]  ecmdDataBufferBase& address_16:  MRS values - this is modified by the given attribute name and data
- * @param[in]  uint32_t attribute_name:  enumerated value containing the attribute name to be modified - attr_name tells the function which bits to modify
- * @param[in]  uint8_t attribute_data:   data telss the function what values to set to the modified bits
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_modify_mrs_pda(Target& i_target,ecmdDataBufferBase& address_16,uint32_t attribute_name,uint8_t attribute_data);
-/**
- * @Adds a given DRAM into the scom_storage vector
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in]  uint8_t port:  identifies which port the given DRAM is on
- * @param[in]  uint8_t dram:  identifies which DRAM identifier is to be added
- * @param[in/out]  vector:  list of all DRAMs being modified by PDA. contains address, bit, and length
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_add_dram_pda(Target& i_target,uint8_t port,uint8_t dram,vector<PDA_Scom_Storage> & scom_storage);
-/**
- * @loads in a nominal MRS value into the address_16 and bank_3
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[out]  ecmdDataBufferBase& bank_3:  bank bits to be issued during MRS
- * @param[out]  ecmdDataBufferBase& address_16:  16 address lanes to be issued during MRS - setup during function
- * @param[in]  uint8_t MRS:  which MRS to configure
- * @param[in]  uint8_t i_port_number: the port on which to configure the MRS - used for ID'ing which attributes to use
- * @param[in]  uint8_t dimm_number: the DIMM on which to configure the MRS - used for ID'ing which attributes to use
- * @param[in]  uint8_t rank_number: the rank on which to configure the MRS - used for ID'ing which attributes to use
- *
- * @return ReturnCode
- */
-ReturnCode mss_ddr4_load_nominal_mrs_pda(Target& i_target,ecmdDataBufferBase& bank_3,ecmdDataBufferBase& address_16,uint8_t MRS,uint8_t i_port_number, uint8_t dimm_number, uint8_t rank_number);
-} // extern "C"
-
-#endif /* _MSS_DDR4_PDA_H */
-
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
deleted file mode 100644
index c62c99695..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C
+++ /dev/null
@@ -1,2036 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training_advanced.C,v 1.50 2015/08/27 21:59:32 eliner Exp $
-/* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE :mss_draminit_training_advanced.C
-// *! DESCRIPTION : Tools for centaur procedures
-// *! OWNER NAME : Preetham Hosmane              email:   preeragh@in.ibm.com
-// *! BACKUP NAME: Saravanan Sethuraman          email ID:saravanans@in.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-// General purpose funcs
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.1    | sasethur |30-Sep-11| Initial draft.
-//  1.2    | sasethur |18-Nov-11| Changed function names 
-//  1.3    | sasethur |01-Dec-11| Added details on Vref shmoo, reg addresses
-//  1.4    | sasethur |29-Jan-12| Updated wr&rd vref, removed ecmd workarounds
-//  1.5    | sasethur |13-Feb-12| Updated register naming conventions
-//  1.6    | sasethur |08-Mar-12| Changed rc_num, multiple changes to drv_imp, Vref funcs
-//  1.7    | sasethur |23-Mar-12| Added Receiver Impedance shmoo & changes to mcbist call
-//  1.8    | sasethur |30-Mar-12| Removed port from start_mcb, added 15,20,48 receiver imp settings
-//  1.9    | sasethur |03-Apr-12| Fixed warning messages
-//  1.13   | bellows  |16-Jul-12| Added in Id tag
-//  1.14   | bellows  |18-Jul-12| Disabled some checking code
-//  1.15   | gollub   |05-Sep-12| Calling mss_unmask_draminit_training_advanced_errors after mss_draminit_training_advanced_cloned
-//  1.16   | sasethur |15-Oct-12| Fixed FW review comments and modified function based on new attributes, added slew function
-//  1.17   | sasethur |17-Oct-12| Updated index bound checks
-//  1.18   | sasethur |17-Oct-12| Removed Hardcoding of Shmoo parameter value
-//  1.19   | sasethur |26-Oct-12| Updated fapi::ReturnCode, const Target& and removed fapi::RC_SUCCSESS as per FW comments
-//  1.20   | bellows  |13-Nov-12| Updated for new SI attributes
-//  1.21   | sasethur |11-Nov-12| Updated for new SI attribute change, fw review comments
-//  1.22   | sasethur |07-Dec-12| Updated for FW review comments - multiple changes
-//  1.23   | sasethur |14-Dec-12| Updated for FW review comments 
-//  1.24   | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file 
-//  1.25   | abhijsau |31-Jan-13| Removed  mss_mcbist_common.C include file , needs to be included while compiling 
-//  1.26   | abhijsau |06-Mar-13| Fixed fw comment 
-//  1.27   | sasethur |09-Apr-13| Updated for port in parallel and pass shmoo param
-//  1.28   | sasethur |22-Apr-13| Fixed fw comment 
-//  1.29   | sasethur |23-Apr-13| Fixed fw comment 
-//  1.30   | sasethur |24-Apr-13| Fixed fw comment 
-//  1.31   | sasethur |10-May-13| Added user input for test type, pattern from wrapper 
-//  1.32   | sasethur |04-Jun-13| Fixed for PortD cnfg, vref print for min setup, hold, fixed rdvref print, added set/reset mcbist attr
-//  1.33   | sasethur |12-Jun-13| Updated mcbist setup attribute 
-//  1.34   | sasethur |20-Jun-13| Fixed read_vref print, setup attribute
-//  1.35   | sasethur |08-Aug-13| Fixed fw comment
-//  1.36   | sasethur |23-Aug-13| Ability to run MCBIST is enabled.
-//  1.37   | sasethur |04-Sep-13| Fixed fw review comment
-//  1.38   | bellows  |19-SEP-13| fixed possible buffer overrun found by stradale
-//  1.39   | abhijsau |17-OCT-13| fixed a logical bug 
-//  1.40   | abhijsau |17-DEC-13| added creation and deletion of schmoo object  
-//  1.41   | abhijsau |16-JAN-14| removed EFF_DIMM_TYPE attribute
-//  1.42   | mjjones  |17-Jan-14| Fixed layout and error handling for RAS Review
-//  1.43   | jdsloat  |10-MAR-14| Edited comments
-//  1.44   |preeragh  |06-NOV-14| Added Sanity checks for wr_vref and rd_vref only at nominal and disabled any other
-//  1.45   |sglancy   |09-FEB-14| Responded to FW comments
-//  1.46   |preeragh  |22-Jun-14| DDR4 Enhancements and Optimizations
-//  1.47   |preeragh  |22-Jul-14| 64 Bit compile Fix
-//  1.48   |preeragh  |19-Aug-14| Fix FW Review Comments
-//  1.49   |eliner    |27-Aug-15| Fixing Index Overflow Bug
-//  1.50   |eliner    |27-Aug-15| Fixing Index Overflow Bug
-// This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure
-// DQ & DQS Driver impedance, Slew rate, WR_Vref shmoo would call only write_eye shmoo for margin calculation
-// DQ & DQS VREF (rd_vref), RCV_IMP shmoo would call rd_eye for margin calculation
-// Internal Vref controlled by this function & external vref 
-
-// Not supported
-// DDR4, DIMM Types
-//----------------------------------------------------------------------
-//  Includes - FAPI
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-
-//----------------------------------------------------------------------
-//Centaur functions
-//----------------------------------------------------------------------
-#include <mss_termination_control.H>
-#include "mss_mcbist.H"
-#include <mss_shmoo_common.H>
-#include <mss_generic_shmoo.H>
-#include <mss_draminit_training_advanced.H>
-#include <mss_unmask_errors.H>
-#include <mss_mrs6_DDR4.H>
-#include <mss_ddr4_pda.H>
-#include <vector>
-
-const uint32_t MASK = 1;
-const uint32_t MAX_DIMM =2;
-
-enum shmoo_param
-{
-	PARAM_NONE = 0x00,
-	DELAY_REG = 0x01,
-	DRV_IMP = 0x02, 
-	SLEW_RATE = 0x04,
-	WR_VREF = 0x08,
-	RD_VREF = 0x10,
-	RCV_IMP = 0x20 
-};
-
-
-extern "C" 
-{
-
-	using namespace fapi;
-
-	fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_target_mba);
-
-	fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid); 
-
-	fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid); 
-
-	fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid);
-	
-	fapi::ReturnCode wr_vref_shmoo_ddr4(const fapi::Target & i_target_mba);
-	fapi::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi::Target & i_target_mba);
-	fapi::ReturnCode rd_vref_shmoo_ddr4(const fapi::Target & i_target_mba);
-
-	fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid); 
-
-	fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid);
-
-	fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid, 
-	uint32_t *o_left_margin, uint32_t *o_right_margin,
-	uint32_t i_shmoo_param);
-	fapi::ReturnCode delay_shmoo_ddr4(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid, 
-	uint32_t *o_left_margin, uint32_t *o_right_margin,
-	uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2]);
-	
-	fapi::ReturnCode delay_shmoo_ddr4_pda(const fapi::Target & i_target_mba, uint8_t i_port,
-	shmoo_type_t i_shmoo_type_valid, 
-	uint32_t *o_left_margin, uint32_t *o_right_margin,
-	uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2]);
-
-	void find_best_margin(shmoo_param i_shmoo_param_valid,uint32_t i_left[], 
-	uint32_t i_right[], const uint8_t l_max, 
-	uint32_t i_param_nom, uint8_t& o_index);
-
-	fapi::ReturnCode set_attribute(const fapi::Target & i_target_mba);
-
-	fapi::ReturnCode reset_attribute(const fapi::Target & i_target_mba);
-
-
-	//-----------------------------------------------------------------------------------
-	//Function name: mss_draminit_training_advanced()
-	//Description: This function varies driver impedance, receiver impedance, slew, wr & rd vref
-	//based on attribute definition and runs either mcbist/delay shmoo based on attribute
-	//Also calls unmask function mss_unmask_draminit_training_advanced_errors() 
-	//Input : const fapi::Target MBA, i_pattern = pattern selection during mcbist @ lab, 
-	//	l_test type  = test type selection during mcbist @ lab 
-	//	Default vlaues are Zero
-	//-----------------------------------------------------------------------------------
-
-	fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba)
-	{
-		// const fapi::Target is centaur.mba
-		fapi::ReturnCode rc;
-		//FAPI_INF(" pattern bit is %d and test_type_bit is %d");   
-		rc = mss_draminit_training_advanced_cloned(i_target_mba);
-		if (rc) 
-		{
-			FAPI_ERR("Advanced DRAM Init training procedure is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-		}
-		
-		// If mss_unmask_draminit_training_advanced_errors gets it's own bad rc,
-		// it will commit the passed in rc (if non-zero), and return it's own bad rc.
-		// Else if mss_unmask_draminit_training_advanced_errors runs clean, 
-		// it will just return the passed in rc.
-		
-		rc = mss_unmask_draminit_training_advanced_errors(i_target_mba, rc);
-		if (rc) 
-		{
-			FAPI_ERR("Unmask Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		return rc;
-	}
-
-}
-//end of extern C
-
-//-----------------------------------------------------------------------------------
-// Function name: mss_draminit_training_advanced_cloned()
-// Description: This function varies driver impedance, receiver impedance, slew, wr & rd vref
-// based on attribute definition and runs either mcbist/delay shmoo based on attribute
-// Input : const fapi::Target MBA
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-//-----------------------------------------------------------------------------------
-fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_target_mba)
-{
-	//const fapi::Target is centaur.mba
-	fapi::ReturnCode rc;
-
-	FAPI_INF("+++++++ Executing mss_draminit_training_advanced +++++++");
-	
-	// Define attribute variables
-	uint32_t l_attr_mss_freq_u32 = 0;
-	uint32_t l_attr_mss_volt_u32 = 0;  
-	uint8_t l_num_drops_per_port_u8 = 2;
-	uint8_t l_num_ranks_per_dimm_u8array[MAX_PORT][MAX_DIMM] = {{0}};
-	uint8_t l_port = 0;
-	uint32_t l_left_margin=0;  
-	uint32_t l_right_margin=0;  
-	uint32_t l_shmoo_param=0; 
-	uint8_t l_dram_type=0;
-	uint8_t bin_pda=0;
-	// Define local variables
-	uint8_t l_shmoo_type_valid_t=0;
-	uint8_t l_shmoo_param_valid_t=0;
-	enum dram_type { EMPTY = 0, DDR3 = 1, DDR4 = 2};   	
-	//const fapi::Target is centaur
-	fapi::Target l_target_centaur;
-	rc = fapiGetParentChip(i_target_mba, l_target_centaur); 
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); 
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); 
-	if(rc) return rc;
-	
-	//const fapi::Target is centaur.mba   
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); 
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); 
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_type); 
-	if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MCBIST_USER_BANK, &i_target_mba, bin_pda); 
-	if(rc) return rc;
-	
-	
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-	FAPI_INF("freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString());
-	FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString());
-	FAPI_INF("num_drops_per_port = %d on %s.", l_num_drops_per_port_u8, i_target_mba.toEcmdString());
-	FAPI_INF("num_ranks_per_dimm = [%02d][%02d][%02d][%02d]",
-	l_num_ranks_per_dimm_u8array[0][0],
-	l_num_ranks_per_dimm_u8array[0][1],
-	l_num_ranks_per_dimm_u8array[1][0],
-	l_num_ranks_per_dimm_u8array[1][1]);
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-
-	rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t);  
-	if(rc) return rc; 
-	rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, l_shmoo_param_valid_t); 
-	if(rc) return rc;
-
-	shmoo_type_t l_shmoo_type_valid;
-	shmoo_param l_shmoo_param_valid;
-
-	l_shmoo_type_valid=(shmoo_type_t)l_shmoo_type_valid_t;
-	l_shmoo_param_valid=(shmoo_param)l_shmoo_param_valid_t;
-	FAPI_INF("+++++++++++++++++++++++++ Read Schmoo Attributes ++++++++++++++++++++++++++");
-	FAPI_INF("Schmoo param valid = 0x%x on %s", l_shmoo_param_valid, i_target_mba.toEcmdString());
-	FAPI_INF("Schmoo test valid = 0x%x on %s", l_shmoo_type_valid, i_target_mba.toEcmdString());
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-	//Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit 
-
-	if ((l_num_ranks_per_dimm_u8array[0][0] > 0) ||
-			(l_num_ranks_per_dimm_u8array[0][1] > 0) ||
-			(l_num_ranks_per_dimm_u8array[1][0] > 0) ||
-			(l_num_ranks_per_dimm_u8array[1][1] > 0))
-	{
-		if ((l_shmoo_param_valid != PARAM_NONE) ||
-				(l_shmoo_type_valid != TEST_NONE))
-		{
-			if ((l_shmoo_param_valid & DRV_IMP) != 0)
-			{
-				rc = drv_imped_shmoo(i_target_mba, l_port, l_shmoo_type_valid);
-				if (rc)
-				{
-					FAPI_ERR("Driver Impedance Schmoo function is Failed rc = 0x%08X (creator = %d)",
-					uint32_t(rc), rc.getCreator());
-					return rc;
-				}
-			}
-			if ((l_shmoo_param_valid & SLEW_RATE) != 0)
-			{
-				rc = slew_rate_shmoo(i_target_mba, l_port, l_shmoo_type_valid);
-				if (rc)
-				{
-					FAPI_ERR("Slew Rate Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-					uint32_t(rc), rc.getCreator());
-					return rc;
-				}
-			}
-			if ((l_shmoo_param_valid & WR_VREF) != 0)
-			{
-				if(l_dram_type==DDR3){
-					rc = wr_vref_shmoo(i_target_mba, l_port, l_shmoo_type_valid);
-					if (rc)
-					{
-						FAPI_ERR("Write Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-						uint32_t(rc), rc.getCreator());
-						return rc;
-					}
-				}
-				else{
-					if(bin_pda == 1)
-					{
-						FAPI_INF("************* Bin - PDA - Vref_Schmoo **************");
-						
-						rc = wr_vref_shmoo_ddr4_bin(i_target_mba);
-						if (rc)
-						{
-							FAPI_ERR("Write Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-							uint32_t(rc), rc.getCreator());
-							return rc;
-						}
-					}
-					else
-					{
-						rc = wr_vref_shmoo_ddr4(i_target_mba);
-						if (rc)
-						{
-							FAPI_ERR("Write Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-							uint32_t(rc), rc.getCreator());
-							return rc;
-						}
-					}
-				}
-			}
-			if ((l_shmoo_param_valid & RD_VREF) != 0)
-			{
-				if(l_dram_type==DDR3){
-					rc = rd_vref_shmoo(i_target_mba, l_port, l_shmoo_type_valid);
-					if (rc)
-					{
-						FAPI_ERR("Read Vref Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-						uint32_t(rc), rc.getCreator());
-						return rc;
-					}
-				}
-				else 
-				{
-					rc = rd_vref_shmoo_ddr4(i_target_mba);
-					if (rc)
-					{
-						FAPI_ERR("rd_vref_shmoo_ddr4 Function is Failed rc = 0x%08X (creator = %d)",
-						uint32_t(rc), rc.getCreator());
-						return rc;
-					}
-				}
-			}
-			if ((l_shmoo_param_valid & RCV_IMP) != 0)
-			{
-				rc = rcv_imp_shmoo(i_target_mba, l_port, l_shmoo_type_valid);
-				if (rc)
-				{
-					FAPI_ERR("Receiver Impedance Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-					uint32_t(rc), rc.getCreator());
-					return rc;
-				}
-			}
-			if (((l_shmoo_param_valid == PARAM_NONE)))
-			{
-				rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid,
-				&l_left_margin, &l_right_margin,
-				l_shmoo_param);
-				if (rc)
-				{
-					FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)",
-					uint32_t(rc), rc.getCreator());
-					return rc;
-				}
-			}
-		}
-	}
-	return rc;
-}
-
-//-------------------------------------------------------------------------------
-// Function name: drv_imped_shmoo()
-// This function varies the driver impedance in the nominal mode
-// for both dq/dqs & adr/cmd signals - DQ_DQS<24,30,34,40>,CMD_CNTL<15,20,30,40>
-// if there is any mcbist failure, that will be reported to put_bad_bits function
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-//-------------------------------------------------------------------------------
-
-fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba,
-uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid)
-{
-	fapi::ReturnCode rc;
-	uint8_t l_drv_imp_dq_dqs[MAX_PORT] = {0};
-	uint8_t l_drv_imp_dq_dqs_nom[MAX_PORT] = {0};
-	//uint8_t l_drv_imp_dq_dqs_new[MAX_PORT] = {0};
-	uint8_t index=0;
-	uint8_t l_slew_rate_dq_dqs[MAX_PORT] = {0};
-	uint8_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0};
-	uint32_t l_drv_imp_dq_dqs_schmoo[MAX_PORT] = {0};
-	uint8_t l_drv_imp_dq_dqs_nom_fc = 0;
-	uint8_t l_drv_imp_dq_dqs_in = 0;
-	//Temporary 
-	i_shmoo_type_valid = WR_EYE;  //Hard coded, since no other schmoo is applicable for this parameter
-	uint32_t l_left_margin_drv_imp_array[MAX_DRV_IMP] = {0};
-	uint32_t l_right_margin_drv_imp_array[MAX_DRV_IMP] = {0};
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint8_t count = 0;
-	uint8_t shmoo_param_count = 0;
-	uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address
-	
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); 
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs); 
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_drv_imp_dq_dqs_schmoo);
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo);
-	if (rc) return rc;
-	
-	FAPI_INF("+++++++++++++++++Read DRIVER IMP Attributes values++++++++++++++++");
-	FAPI_INF("CEN_DRV_IMP_DQ_DQS[%d]  = [%02d] Ohms, on %s",
-	i_port,
-	l_drv_imp_dq_dqs_nom[i_port],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_DRV_IMP_DQ_DQS_SCHMOO[0]  = [0x%x], CEN_DRV_IMP_DQ_DQS_SCHMOO[1]  = [0x%x] on %s",
-	l_drv_imp_dq_dqs_schmoo[0],
-	l_drv_imp_dq_dqs_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s",
-	l_slew_rate_dq_dqs[0],
-	l_slew_rate_dq_dqs[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s",
-	l_slew_rate_dq_dqs_schmoo[0],
-	l_slew_rate_dq_dqs_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-
-	if(l_drv_imp_dq_dqs_schmoo[i_port] == 0) //Check for any of the bits enabled in the shmoo
-	{
-		FAPI_INF("DRIVER IMP Shmoo set to FAST Mode and won't do anything");
-	}
-	else
-	{
-		for (index = 0; index < MAX_DRV_IMP; index += 1)
-		{
-			if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK)
-			{
-				l_drv_imp_dq_dqs[i_port] = drv_imp_array[index];
-				FAPI_INF("Current Driver Impedance Value = %d Ohms",
-				drv_imp_array[index]);
-				FAPI_INF("Configuring Driver Impedance Registers:");
-				rc = config_drv_imp(i_target_mba, i_port,
-				l_drv_imp_dq_dqs[i_port]);
-				if (rc) return rc;
-				l_drv_imp_dq_dqs_in = l_drv_imp_dq_dqs[i_port];
-				FAPI_INF("Configuring Slew Rate Registers:");
-				rc = config_slew_rate(i_target_mba, i_port, l_slew_type,
-				l_drv_imp_dq_dqs[i_port],
-				l_slew_rate_dq_dqs[i_port]);
-				if (rc) return rc;
-				FAPI_INF("Calling Shmoo for finding Timing Margin:");
-				if (shmoo_param_count)
-				{
-					rc = set_attribute(i_target_mba);
-					if (rc) return rc;
-				}
-				rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-				&l_left_margin, &l_right_margin,
-				l_drv_imp_dq_dqs_in);
-				if (rc) return rc;
-				l_left_margin_drv_imp_array[index] = l_left_margin;
-				l_right_margin_drv_imp_array[index] = l_right_margin;
-				shmoo_param_count++;
-			}
-			else
-			{
-				l_left_margin_drv_imp_array[index] = 0;
-				l_right_margin_drv_imp_array[index] = 0;
-			}
-			l_drv_imp_dq_dqs_schmoo[i_port] = (l_drv_imp_dq_dqs_schmoo[i_port] >> 1);
-		}
-		l_drv_imp_dq_dqs_nom_fc = l_drv_imp_dq_dqs_nom[i_port];
-		find_best_margin(DRV_IMP, l_left_margin_drv_imp_array,
-		l_right_margin_drv_imp_array, MAX_DRV_IMP,
-		l_drv_imp_dq_dqs_nom_fc, count);
-
-		if (count >= MAX_DRV_IMP)
-		{
-			FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)", count,
-			MAX_DRV_IMP);
-			const uint8_t & COUNT_DATA = count;
-			FAPI_SET_HWP_ERROR(rc, RC_DRV_IMPED_SHMOO_INVALID_MARGIN_DATA);
-			return rc;
-		}
-		else
-		{
-			FAPI_INF("Restoring the nominal values!");
-			rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba,
-			l_drv_imp_dq_dqs_nom);
-			if (rc) return rc;
-			rc = config_drv_imp(i_target_mba, i_port,
-			l_drv_imp_dq_dqs_nom[i_port]);
-			if (rc) return rc;
-			rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba,
-			l_slew_rate_dq_dqs);
-			if (rc) return rc;
-			rc = config_slew_rate(i_target_mba, i_port, l_slew_type,
-			l_drv_imp_dq_dqs_nom[i_port],
-			l_slew_rate_dq_dqs[i_port]);
-			if (rc) return rc;
-		}
-		FAPI_INF("Restoring mcbist setup attribute...");
-		rc = reset_attribute(i_target_mba);
-		if (rc) return rc;
-		FAPI_INF("++++ Driver impedance shmoo function executed successfully ++++");
-	}
-	return rc;
-}
-
-//-----------------------------------------------------------------------------------------
-// Function name: slew_rate_shmoo()
-// This function varies the slew rate of the data & adr signals (fast/slow)
-// calls the write eye shmoo which internally calls mcbist function to see for failure
-// if there is any mcbist failure, this function will report to baddqpins function
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-//-----------------------------------------------------------------------------------------
-
-fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba,
-uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid)
-{
-	fapi::ReturnCode rc;
-	uint8_t l_slew_rate_dq_dqs[MAX_PORT] = {0};
-	uint8_t l_slew_rate_dq_dqs_nom[MAX_PORT] = {0};
-	uint8_t l_slew_rate_dq_dqs_nom_fc = 0;
-	uint8_t l_slew_rate_dq_dqs_in = 0;
-	uint32_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0};
-	uint8_t l_drv_imp_dq_dqs_nom[MAX_PORT] = {0};
-	i_shmoo_type_valid = WR_EYE; // Hard coded - Other shmoo type is not valid - Temporary
-	
-	uint8_t index = 0;
-	uint8_t count = 0;
-	uint8_t shmoo_param_count = 0;
-	uint32_t l_left_margin_slew_array[MAX_NUM_SLEW_RATES] = {0};
-	uint32_t l_right_margin_slew_array[MAX_NUM_SLEW_RATES] = {0};
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address
-	
-	//Read Attributes - DRV IMP, SLEW, SLEW RATES values to be Schmoo'ed
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); 
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_nom); 
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo);
-	if (rc) return rc;
-	
-	FAPI_INF("+++++++++++++++++Read Slew Shmoo Attributes values+++++++++++++++");
-	FAPI_INF("CEN_DRV_IMP_DQ_DQS[0]  = [%02d] Ohms, CEN_DRV_IMP_DQ_DQS[1]  = [%02d] Ohms on %s",
-	l_drv_imp_dq_dqs_nom[0],
-	l_drv_imp_dq_dqs_nom[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s",
-	l_slew_rate_dq_dqs_nom[0],
-	l_slew_rate_dq_dqs_nom[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s",
-	l_slew_rate_dq_dqs_schmoo[0],
-	l_slew_rate_dq_dqs_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-	
-	if(l_slew_rate_dq_dqs_schmoo == 0) //Check for any of the bits enabled in the shmoo
-	{
-		FAPI_INF("Slew Rate Shmoo set to FAST Mode and won't do anything");
-	}
-	else
-	{
-		for (index = 0; index < MAX_NUM_SLEW_RATES; index += 1)
-		{
-			if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK)
-			{
-				l_slew_rate_dq_dqs[i_port] = slew_rate_array[index];
-				FAPI_INF("Current Slew rate value is %d V/ns",
-				slew_rate_array[index]);
-				FAPI_INF("Configuring Slew registers:");
-				rc = config_slew_rate(i_target_mba, i_port, l_slew_type,
-				l_drv_imp_dq_dqs_nom[i_port],
-				l_slew_rate_dq_dqs[i_port]);
-				if (rc) return rc;
-				l_slew_rate_dq_dqs_in = l_slew_rate_dq_dqs[i_port];
-				FAPI_INF("Calling Shmoo for finding Timing Margin:");
-				if (shmoo_param_count)
-				{
-					rc = set_attribute(i_target_mba);
-					if (rc) return rc;
-				}
-				rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-				&l_left_margin, &l_right_margin,
-				l_slew_rate_dq_dqs_in);
-				if (rc) return rc;
-				l_left_margin_slew_array[index] = l_left_margin;
-				l_right_margin_slew_array[index] = l_right_margin;
-				shmoo_param_count++;
-			}
-			else
-			{
-				l_left_margin_slew_array[index] = 0;
-				l_right_margin_slew_array[index] = 0;
-			}
-			l_slew_rate_dq_dqs_schmoo[i_port]
-			= (l_slew_rate_dq_dqs_schmoo[i_port] >> 1);
-		}
-		l_slew_rate_dq_dqs_nom_fc = l_slew_rate_dq_dqs_nom[i_port];
-		find_best_margin(SLEW_RATE, l_left_margin_slew_array,
-		l_right_margin_slew_array, MAX_NUM_SLEW_RATES,
-		l_slew_rate_dq_dqs_nom_fc, count);
-		if (count >= MAX_NUM_SLEW_RATES)
-		{
-			FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)", count,
-			MAX_NUM_SLEW_RATES);
-			const uint8_t & COUNT_DATA = count;
-			FAPI_SET_HWP_ERROR(rc, RC_SLEW_RATE_SHMOO_INVALID_MARGIN_DATA);
-			return rc;
-		}
-		else
-		{
-			FAPI_INF("Restoring the nominal values!");
-			rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba,
-			l_drv_imp_dq_dqs_nom);
-			if (rc) return rc;
-			rc = config_drv_imp(i_target_mba, i_port,
-			l_drv_imp_dq_dqs_nom[i_port]);
-			if (rc) return rc;
-			rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba,
-			l_slew_rate_dq_dqs_nom);
-			if (rc) return rc;
-			rc = config_slew_rate(i_target_mba, i_port, l_slew_type,
-			l_drv_imp_dq_dqs_nom[i_port],
-			l_slew_rate_dq_dqs_nom[i_port]);
-			if (rc) return rc;
-		}
-		FAPI_INF("Restoring mcbist setup attribute...");
-		rc = reset_attribute(i_target_mba);
-		if (rc) return rc;
-		FAPI_INF("++++ Slew Rate shmoo function executed successfully ++++");
-	}
-	return rc;
-}
-
-//----------------------------------------------------------------------------------------------
-// Function name: wr_vref_shmoo()
-// This function varies the DIMM vref using PC_VREF_DRV_CNTL register in 32 steps with vref sign
-// Calls mcbist/write eye shmoo function and look for failure, incase of failure
-// this function reports bad DQ pins matrix to put bad bits function
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-//----------------------------------------------------------------------------------------------
-
-fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba,
-uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid)
-{
-	fapi::ReturnCode rc;
-	uint32_t l_wr_dram_vref[MAX_PORT] = {0};
-	uint32_t l_wr_dram_vref_nom[MAX_PORT] = {0};
-	uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; 
-	uint32_t l_wr_dram_vref_nom_fc = 0;
-	uint32_t l_wr_dram_vref_in = 0;
-	i_shmoo_type_valid = MCBIST; 
-	
-	uint8_t index = 0;
-	uint8_t count = 0;
-	//uint8_t shmoo_param_count = 0;
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint32_t l_left_margin_wr_vref_array[MAX_WR_VREF]= {0};
-	uint32_t l_right_margin_wr_vref_array[MAX_WR_VREF]= {0};
-	
-	//Read the write vref attributes
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_nom); 
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, l_wr_dram_vref_schmoo);
-	if (rc) return rc;
-	
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - WR_VREF - Check Sanity only at 500 +++++++++++++++++++++++++++");
-	rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-	&l_left_margin, &l_right_margin,
-	l_wr_dram_vref_in);
-	if(rc) return rc;
-	FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing .....");
-	rc = set_attribute(i_target_mba);
-	if (rc) return rc;
-	
-	
-	
-	i_shmoo_type_valid = WR_EYE;
-	
-	FAPI_INF("+++++++++++++++++WRITE DRAM VREF Shmoo Attributes Values+++++++++++++++");
-	FAPI_INF("DRAM_WR_VREF[0]  = %d , DRAM_WR_VREF[1]  = %d on %s",
-	l_wr_dram_vref_nom[0],
-	l_wr_dram_vref_nom[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("DRAM_WR_VREF_SCHMOO[0] = [%x],DRAM_WR_VREF_SCHMOO[1] = [%x] on %s",
-	l_wr_dram_vref_schmoo[0],
-	l_wr_dram_vref_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-	
-	
-	if (l_wr_dram_vref_schmoo[i_port] == 0)
-	{
-		FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings");
-	}
-	else
-	{
-		for (index = 0; index < MAX_WR_VREF; index += 1)
-		{
-			if (l_wr_dram_vref_schmoo[i_port] & MASK)
-			{
-				FAPI_INF("Current Vref multiplier value is %d",
-				wr_vref_array[index]);
-				l_wr_dram_vref[i_port] = wr_vref_array[index];
-				rc = config_wr_dram_vref(i_target_mba, i_port,
-				l_wr_dram_vref[i_port]);
-				if (rc) return rc;
-				l_wr_dram_vref_in = l_wr_dram_vref[i_port];
-				//FAPI_INF(" Calling Shmoo for finding Timing Margin:");
-				
-				rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-				&l_left_margin, &l_right_margin,
-				l_wr_dram_vref_in);
-				if (rc) return rc;
-				l_left_margin_wr_vref_array[index] = l_left_margin;
-				l_right_margin_wr_vref_array[index] = l_right_margin;
-				
-				FAPI_INF("Wr Vref = %d ; Min Setup time = %d; Min Hold time = %d",
-				wr_vref_array[index],
-				l_left_margin_wr_vref_array[index],
-				l_right_margin_wr_vref_array[index]);
-			}
-			else
-			{
-				l_left_margin_wr_vref_array[index] = 0;
-				l_right_margin_wr_vref_array[index] = 0;
-			}
-			l_wr_dram_vref_schmoo[i_port] = (l_wr_dram_vref_schmoo[i_port] >> 1);
-			//FAPI_INF("Wr Vref = %d ; Min Setup time = %d; Min Hold time = %d", wr_vref_array[index],l_left_margin_wr_vref_array[index],  l_right_margin_wr_vref_array[index]);
-			//FAPI_INF("Configuring Vref registers_2:, index %d , max value %d, schmoo %x mask %d ", index, MAX_WR_VREF, l_wr_dram_vref_schmoo[i_port], MASK);
-		}
-		l_wr_dram_vref_nom_fc = l_wr_dram_vref_nom[i_port];
-		find_best_margin(WR_VREF, l_left_margin_wr_vref_array,
-		l_right_margin_wr_vref_array, MAX_WR_VREF,
-		l_wr_dram_vref_nom_fc, count);
-		if (count >= MAX_WR_VREF)
-		{
-			FAPI_ERR("Write dram vref input(%d) out of bounds, (>= %d)", count,
-			MAX_WR_VREF);
-			const uint8_t & COUNT_DATA = count;
-			FAPI_SET_HWP_ERROR(rc, RC_WR_VREF_SHMOO_INVALID_MARGIN_DATA);
-			return rc;
-		}
-		else
-		{
-			//   FAPI_INF("Nominal value will not be changed!- Restoring the original values!");
-			FAPI_INF(" Restoring the nominal values!");
-			rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba,
-			l_wr_dram_vref_nom);
-			if (rc) return rc;
-			rc = config_wr_dram_vref(i_target_mba, i_port,
-			l_wr_dram_vref_nom[i_port]);
-			if (rc) return rc;
-		}
-		FAPI_INF("Restoring mcbist setup attribute...");
-		rc = reset_attribute(i_target_mba);
-		if (rc) return rc;
-		FAPI_INF("++++ Write DRAM Vref Shmoo function executed successfully ++++");
-	}
-	return rc;
-}
-
-//////////////////////////////////////////////wr_vref schmoo for ddr4 ////////////////////////////////////////////////////////////
-fapi::ReturnCode wr_vref_shmoo_ddr4(const fapi::Target & i_target_mba)
-{
-	fapi::ReturnCode rc;
-	uint8_t max_port = 2;
-	uint8_t max_ddr4_vrefs1 = 52;
-	shmoo_type_t i_shmoo_type_valid = MCBIST; // Hard coded - Temporary
-	ecmdDataBufferBase l_data_buffer_64(64);
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint8_t l_attr_eff_dimm_type_u8 = 0;
-	uint8_t vrefdq_train_range[2][2][4];
-	uint8_t num_ranks_per_dimm[2][2];
-	uint8_t l_MAX_RANKS[2];
-	uint32_t rc_num = 0;
-	uint8_t l_SCHMOO_NIBBLES=20;
-	uint8_t base_percent = 60;
-	
-	float index_mul_print = 0.65;
-	uint8_t l_attr_schmoo_test_type_u8 = 1;
-	float vref_val_print = 0;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8); if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm); if(rc) return rc;
-	rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc;
-	if(vrefdq_train_range[0][0][0] == 1)
-	{
-		base_percent = 45;
-	}
-	
-	l_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1];
-	l_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1];
-	FAPI_INF("\n ** l_max_rank 0 = %d",l_MAX_RANKS[0]);
-	if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )
-		{
-			l_SCHMOO_NIBBLES=20;
-		}
-	else
-		{
-			l_SCHMOO_NIBBLES=18;
-		}
-		FAPI_INF(" +++  l_SCHMOO_NIBBLES = %d +++ ",l_SCHMOO_NIBBLES);
-	///// ddr4 vref //////
-	fapi::Target l_target_centaur=i_target_mba;
-	
-	uint8_t vrefdq_train_value[2][2][4]; 
-	uint8_t vrefdq_train_enable[2][2][4]; 
-	//uint32_t best_margin[2][8][20];
-	//uint32_t best_vref[50][2][8][20];
-	//uint32_t best_vref_nibble[2][8][20];
-	uint32_t vref_val=0;
-	uint32_t pda_nibble_table[2][2][16][2];
-	uint8_t i=0;
-	uint8_t j=0;
-	uint8_t k=0;
-	uint8_t a=0;
-	uint8_t c=0;
-	uint8_t l_ranks = 0;
-	uint8_t l_vref_num = 0;
-	uint8_t i_port=0;
-		
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - WR_VREF - Check Sanity only at 500 ddr4 +++++++++++++++++++++++++++");
-	rc = delay_shmoo_ddr4(i_target_mba, i_port, i_shmoo_type_valid,
-	&l_left_margin, &l_right_margin,
-	vref_val,pda_nibble_table);
-	
-	if(rc) return rc;
-	FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing .....");
-	rc = set_attribute(i_target_mba);
-	if (rc) return rc;
-	
-	
-	
-	i_shmoo_type_valid = WR_EYE;
-	l_attr_schmoo_test_type_u8 = 2;
-	rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc;
-	//Initialize all to zero
-
-for(l_vref_num=0; l_vref_num < max_ddr4_vrefs1; l_vref_num++){
-		vref_val = l_vref_num;
-		vref_val_print = base_percent + (l_vref_num * index_mul_print);	
-		
-		rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		rc_num = rc_num | l_data_buffer_64.clearBit(0); if(rc_num) return rc;
-		rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		//system("putscom cen.mba 03010432 0 1 0 -ib -all");
-		FAPI_INF("\n After Clearing Refresh");
-		for(i=0;i< max_port;i++){
-			for(j=0;j<2;j++){
-				for(k=0;k<4;k++){
-					
-					vrefdq_train_enable[i][j][k]=0x00;
-					
-				}
-			}
-		}	
-		
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc;
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc;
-		rc = mss_mrs6_DDR4(l_target_centaur);
-		if(rc)
-		{
-			//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		
-		
-		
-		for(a=0;a < max_port;a++){
-			for(l_ranks=0;l_ranks < l_MAX_RANKS[0];l_ranks++){
-				for(c=0;c<4;c++){
-					
-					vrefdq_train_value[a][l_ranks][c]=vref_val;
-					
-				}
-			}
-		}
-		
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, vrefdq_train_value);
-		
-		
-		rc = mss_mrs6_DDR4(l_target_centaur);
-		if(rc)
-		{
-			//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		
-		FAPI_INF("The Vref value is %d .... The percent voltage bump = %f ",vref_val,vref_val_print);
-		
-		for(i=0;i< max_port;i++){
-			for(j=0;j<l_MAX_RANKS[0];j++){
-				for(k=0;k<4;k++){
-					
-					vrefdq_train_enable[i][j][k]=0x01;
-					
-				}
-			}
-		}	
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc;
-		rc = mss_mrs6_DDR4(l_target_centaur);
-		if(rc)
-		{
-			//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		
-		rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		rc_num = rc_num | l_data_buffer_64.setBit(0); if(rc_num) return rc;
-		rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		
-		//system("putscom cen.mba 03010432 0 1 1 -ib -all");
-		
-		rc = delay_shmoo_ddr4(i_target_mba, i_port, i_shmoo_type_valid,
-		&l_left_margin, &l_right_margin,
-		vref_val,pda_nibble_table);
-		if (rc) return rc;
-		
-		FAPI_INF("Wr Vref = %f ; Min Setup time = %d; Min Hold time = %d",
-		vref_val_print,
-		l_left_margin,
-		l_right_margin);
-		
-		//vref_val=vref_val+1;
-	}   
-	
-	
-	
-	
-	//Read the write vref attributes
-	
-	
-	
-	return rc;
-}
-
-
-fapi::ReturnCode wr_vref_shmoo_ddr4_bin(const fapi::Target & i_target_mba)
-{
-	fapi::ReturnCode rc;
-	uint8_t MAX_PORT = 2;
-	uint8_t max_ddr4_vrefs1 = 50;
-	shmoo_type_t i_shmoo_type_valid = MCBIST;
-	ecmdDataBufferBase l_data_buffer_64(64);
-	ecmdDataBufferBase refresh_reg(64); 
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint8_t l_attr_eff_dimm_type_u8 = 0;
-	uint8_t vrefdq_train_range[2][2][4];
-	uint8_t num_ranks_per_dimm[2][2];
-	uint8_t l_MAX_RANKS[2];
-	uint32_t rc_num = 0;
-	uint8_t l_SCHMOO_NIBBLES=20;
-	uint8_t base_percent = 60;
-	uint32_t pda_nibble_table[2][2][16][2];
-	uint32_t best_pda_nibble_table[2][2][16][2];
-	float index_mul_print = 0.65;
-	uint8_t l_attr_schmoo_test_type_u8 = 1;
-	float vref_val_print = 0;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8); if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm); if(rc) return rc;
-	rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc;
-	rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc;
-	if(vrefdq_train_range[0][0][0] == 1)
-	{
-		base_percent = 45;
-	}
-	
-	l_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1];
-	l_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1];
-	FAPI_INF("\n ** l_max_rank 0 = %d Base Percent = %d",l_MAX_RANKS[0],base_percent);
-	if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )
-	{
-		l_SCHMOO_NIBBLES=20;
-	}else{
-		l_SCHMOO_NIBBLES=18;
-	}
-	///// ddr4 vref //////
-	fapi::Target l_target_centaur=i_target_mba;
-	uint8_t vrefdq_train_value[2][2][4]; 
-	uint8_t vrefdq_train_enable[2][2][4]; 
-	uint32_t best_vref[50][1];
-	uint32_t vref_val=0;
-	uint8_t index = 0;	
-	uint8_t i=0;
-	uint8_t j=0;
-	uint8_t k=0;
-	uint8_t a=0;
-	uint8_t c=0;
-	uint8_t l_ranks = 0;
-	uint8_t i_port=0;
-	uint8_t l_vref_mid = 0;
-	vector<PDA_MRS_Storage> pda;
-	pda.clear();
-
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - WR_VREF - Check Sanity only at 500 ddr4 +++++++++++++++++++++++++++");
-	rc = delay_shmoo_ddr4_pda(i_target_mba, i_port, i_shmoo_type_valid,
-	&l_left_margin, &l_right_margin,
-	vref_val,pda_nibble_table);
-	
-	if(rc) return rc;
-	FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing .....");
-	rc = set_attribute(i_target_mba);
-	if (rc) return rc;
-	i_shmoo_type_valid = WR_EYE;
-	l_attr_schmoo_test_type_u8 = 2;
-	rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc;
-	//Initialize all to zero
-	for(index = 0; index < max_ddr4_vrefs1;index++)
-	{
-		best_vref[index][0] = 0;
-	}
-	
-	//Initialise All to Zero 
-	for(int k=0;k< MAX_PORT;k++)  // port
-	{
-		for(int j=0;j < l_MAX_RANKS[0];j++)   //Rank
-		{
-			for(int i=0;i<16;i++)  //Nibble
-			{
-				pda_nibble_table[k][j][i][0] = 0;  //  Index 0 Are V-refs
-				pda_nibble_table[k][j][i][1] = 0;   // Index 1 are Total Margin Values
-				best_pda_nibble_table[k][j][i][0] = 0;   //  Index 0 Are V-refs
-				best_pda_nibble_table[k][j][i][1] = 0;    // Index 1 are Total Margin Values
-			}
-		}
-	}               
-	uint8_t imax = 	39;
-	uint8_t imin = 13;
-	uint8_t last_known_vref = 0;
-	uint8_t l_loop_count = 0;		
-	//for(l_vref_num=0; l_vref_num < max_ddr4_vrefs1; l_vref_num++){
-	//Sweep Right
-	while(imax >= imin){	
-
-		if(l_loop_count==0)
-		l_vref_mid = imin;
-		else	
-		l_vref_mid = (imax+imin)/2;
-
-		vref_val = l_vref_mid;
-		vref_val_print = base_percent + (l_vref_mid * index_mul_print);
-		
-		rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		rc_num = rc_num | l_data_buffer_64.clearBit(0); if(rc_num) return rc;
-		rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		
-		//system("putscom cen.mba 03010432 0 1 0 -ib -all");
-		FAPI_INF("\n After Clearing Refresh");
-		
-		for(i=0;i<MAX_PORT;i++){
-			for(j=0;j<l_MAX_RANKS[0];j++){
-				for(k=0;k<4;k++){
-					
-					vrefdq_train_enable[i][j][k]=0x00;
-					
-				}
-			}
-		}	
-		
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc;
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc;
-		rc = mss_mrs6_DDR4(l_target_centaur);
-		if(rc)
-		{
-			//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		
-		for(a=0;a < MAX_PORT;a++) //Port
-		{
-			for(l_ranks=0;l_ranks < l_MAX_RANKS[0];l_ranks++){
-				for(c=0;c < 4;c++){
-					
-					vrefdq_train_value[a][l_ranks][c]=vref_val;
-					
-				}
-			}
-		}
-		
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, vrefdq_train_value); if(rc) return rc;
-		
-		
-		rc = mss_mrs6_DDR4(l_target_centaur);
-		if(rc)
-		{
-			//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		
-		FAPI_INF("The Vref value is %d .... The percent voltage bump = %f ",vref_val,vref_val_print);
-		
-		for(i=0;i < MAX_PORT;i++){
-			for(j=0;j<l_MAX_RANKS[0];j++){
-				for(k=0;k<4;k++){
-					
-					vrefdq_train_enable[i][j][k]=0x01;
-					
-				}
-			}
-		}	
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc;
-		rc = mss_mrs6_DDR4(l_target_centaur);
-		if(rc)
-		{
-			//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-			return rc;
-		}
-		
-		rc = fapiGetScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		rc_num = rc_num | l_data_buffer_64.setBit(0); if(rc_num) return rc;
-		rc = fapiPutScom(i_target_mba,0x03010432,l_data_buffer_64); if(rc) return rc;
-		//system("putscom cen.mba 03010432 0 1 1 -ib -all");
-		
-		rc = delay_shmoo_ddr4_pda(i_target_mba, i_port, i_shmoo_type_valid,
-		&l_left_margin, &l_right_margin,
-		vref_val,pda_nibble_table);
-		if (rc) return rc;
-		
-		FAPI_INF("Wr Vref = %f ; Min Setup time = %d; Min Hold time = %d",
-		vref_val_print,
-		l_left_margin,
-		l_right_margin);
-		best_vref[vref_val][0] = l_right_margin+l_left_margin;
-		
-		//Get proper Criteria HERE
-		if(best_vref[vref_val][0] > best_vref[last_known_vref][0])
-		{
-			last_known_vref = vref_val;
-			//if(l_loop_count !=0)
-			imin = l_vref_mid+1;
-		}
-		//imax = l_vref_mid + (imax - l_vref_mid)/2;
-		else
-		{
-			if(l_loop_count ==0)
-			{	FAPI_INF("Safety Fuse-1 !! "); 
-				imin = l_vref_mid+1;
-			}
-			else
-			imax = ((l_vref_mid + imax )/2)-2;
-		}
-		l_loop_count ++;
-		for(int i_port=0;i_port < MAX_PORT;i_port++){
-			for(int i_rank=0;i_rank < l_MAX_RANKS[0];i_rank++){
-				for(int i_nibble=0;i_nibble < l_SCHMOO_NIBBLES;i_nibble++){
-					if (best_pda_nibble_table[i_port][i_rank][i_nibble][1] < pda_nibble_table[i_port][i_rank][i_nibble][1])
-					{
-						best_pda_nibble_table[i_port][i_rank][i_nibble][1] = pda_nibble_table[i_port][i_rank][i_nibble][1];
-						best_pda_nibble_table[i_port][i_rank][i_nibble][0] = vref_val;
-					}
-				}}}
-		
-	}
-
-	//imax = 	max_ddr4_vrefs1/2;
-	//imin = 0;
-	//Sweep Left
-	/*while(imax >= imin){	
-
-l_vref_mid = (imax+imin)/2;
-vref_val = l_vref_mid;
-vref_val_print = base_percent + (l_vref_mid * index_mul_print);	
-system("putscom cen.mba 03010432 0 1 0 -ib -all");
-FAPI_INF("\n After Clearing Refresh");
-		
-		for(i=0;i<2;i++){
-			for(j=0;j<l_MAX_RANKS[0];j++){
-				for(k=0;k<4;k++){
-					
-					vrefdq_train_enable[i][j][k]=0x00;
-					
-				}
-			}
-		}	
-		
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, vrefdq_train_range);if(rc) return rc;
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc;
-				rc = mss_mrs6_DDR4(l_target_centaur);
-			if(rc)
-			{
-				//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-				return rc;
-			}
-			
-			for(a=0;a<2;a++){
-				for(l_ranks=0;l_ranks < l_MAX_RANKS[0];l_ranks++){
-					for(c=0;c<4;c++){
-	
-					vrefdq_train_value[a][l_ranks][c]=vref_val;
-					
-					}
-				}
-			}
-		
-				rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, vrefdq_train_value);
-		
-		
-			rc = mss_mrs6_DDR4(l_target_centaur);
-			if(rc)
-			{
-				//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-				return rc;
-			}
-			
-			FAPI_INF("The Vref value is %d .... The percent voltage bump = %f ",vref_val,vref_val_print);
-			
-			for(i=0;i<2;i++){
-			for(j=0;j<l_MAX_RANKS[0];j++){
-				for(k=0;k<4;k++){
-					
-					vrefdq_train_enable[i][j][k]=0x01;
-					
-				}
-			}
-		}	
-		rc = FAPI_ATTR_SET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, vrefdq_train_enable);if(rc) return rc;
-		rc = mss_mrs6_DDR4(l_target_centaur);
-			if(rc)
-			{
-				//FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-				return rc;
-			}
-		
-		system("putscom cen.mba 03010432 0 1 1 -ib -all");
-		
-		rc = delay_shmoo_ddr4(i_target_mba, i_port, i_shmoo_type_valid,
-								&l_left_margin, &l_right_margin,
-								vref_val);
-				if (rc) return rc;
-			
-	FAPI_INF("Wr Vref = %f ; Min Setup time = %d; Min Hold time = %d",
-						vref_val_print,
-						l_left_margin,
-						l_right_margin);
-		best_vref[vref_val][0] = l_right_margin+l_left_margin;
-		
-		//Get proper Criteria HERE
-		if(best_vref[vref_val][0] > best_vref[last_known_vref][0])
-		{
-			last_known_vref = vref_val;
-			imin = l_vref_mid+1;
-		}
-		//last_known_vref = vref_val;
-		//imax = l_vref_mid + (imax - l_vref_mid)/2;
-		else
-		imax = (l_vref_mid + imax )/2;
-		}
-
-		*/
-	vref_val_print = base_percent + (last_known_vref * index_mul_print);		
-	FAPI_INF("Best V-Ref - %f  ; Total Window = %d",
-	vref_val_print,best_vref[last_known_vref][0]);
-	// What do we do Once we know best V-Ref
-	for(a=0;a<50;a++)
-	{
-		vref_val_print = base_percent + (a * index_mul_print);
-		FAPI_INF("\n V-Ref - %f  ; Total Window = %d",vref_val_print,best_vref[a][0]);
-	}
-	rc = fapiGetScom( i_target_mba,  0x03010432,  refresh_reg); if(rc) return rc;
-	refresh_reg.clearBit(0);
-	fapiPutScom( i_target_mba,  0x03010432,  refresh_reg);if(rc) return rc;
-	
-	/*for(int i_port=0;i_port < 2;i_port++){
-		for(int i_rank=0;i_rank < 2;i_rank++){
-		for(int i_nibble=0;i_nibble < 16;i_nibble++){
-		FAPI_INF("\n Port %d Rank:%d Pda_Nibble: %d  V-ref:%d  Margin:%d",i_port,i_rank,i_nibble,best_pda_nibble_table[i_port][i_rank][i_nibble][0],best_pda_nibble_table[i_port][i_rank][i_nibble][1]);
-		pda.push_back(PDA_MRS_Storage(best_pda_nibble_table[i_port][i_rank][i_nibble][0],ATTR_VREF_DQ_TRAIN_VALUE,i_nibble,i_rank,0,i_port));
-}
-FAPI_INF("FINAL %s PDA STRING: %d %s",i_target_mba.toEcmdString(),pda.size()-1,pda[pda.size()-1].c_str());
-}}
-
-rc = fapiGetScom( i_target_mba,  0x03010432,  refresh_reg);
-	refresh_reg.setBit(0);
-	fapiPutScom( i_target_mba,  0x03010432,  refresh_reg);
-			
-		
-	//Read the write vref attributes
-	
-				
-	rc = mss_ddr4_run_pda((fapi::Target &)i_target_mba,pda); 
-*/	
-	return rc;
-}
-
-
-//----------------------------------------------------------------------------------------------
-// Function name: rd_vref_shmoo()                                                               
-// Description: This function varies the Centaur IO vref in 16 steps 
-// 		Calls write eye shmoo function                 
-// Input param: const fapi::Target MBA, port = 0,1
-// 	Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// 	Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// 	Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// 	i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-//----------------------------------------------------------------------------------------------
-
-fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba,
-uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid)
-{
-	fapi::ReturnCode rc;
-	uint32_t l_rd_cen_vref[MAX_PORT] = {0};
-	uint32_t l_rd_cen_vref_nom[MAX_PORT] = {0};
-	uint32_t l_rd_cen_vref_nom_fc = 0;
-	uint32_t l_rd_cen_vref_in = 0;
-	uint32_t l_rd_cen_vref_schmoo[MAX_PORT] = {0};
-	uint8_t index  = 0;
-	uint8_t count  = 0;
-	//uint8_t shmoo_param_count = 0;
-	//i_shmoo_type_valid = RD_EYE; // Hard coded - Temporary
-	
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint32_t l_left_margin_rd_vref_array[MAX_RD_VREF] = {0};
-	uint32_t l_right_margin_rd_vref_array[MAX_RD_VREF] = {0};
-
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_nom);
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo);
-	if (rc) return rc;
-	i_shmoo_type_valid = MCBIST;
-	
-	
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF - Check Sanity only at 500000 +++++++++++++++++++++++++++");
-	rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-	&l_left_margin, &l_right_margin,
-	l_rd_cen_vref_in);
-	if(rc) return rc;
-	FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing .....");
-	rc = set_attribute(i_target_mba);
-	if (rc) return rc;
-	
-	i_shmoo_type_valid = RD_EYE;
-	FAPI_INF("+++++++++++++++++CENTAUR VREF Read Shmoo Attributes values+++++++++++++++");
-	FAPI_INF("CEN_RD_VREF[0]  = %d CEN_RD_VREF[1]  = %d on %s",
-	l_rd_cen_vref_nom[0],
-	l_rd_cen_vref_nom[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%x], CEN_RD_VREF_SCHMOO[1] = [%x] on %s",
-	l_rd_cen_vref_schmoo[0],
-	l_rd_cen_vref_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF +++++++++++++++++++++++++++");
-	
-	if (l_rd_cen_vref_schmoo[i_port] == 0)
-	{
-		FAPI_INF("FAST Shmoo Mode: This function will not change any Read Centaur VREF settings");
-	}
-	else
-	{
-		for (index = 0; index < MAX_RD_VREF; index += 1)
-		{
-			if ((l_rd_cen_vref_schmoo[i_port] & MASK) == 1)
-			{
-				l_rd_cen_vref[i_port] = rd_cen_vref_array[index];
-				FAPI_INF("Current Read Vref Multiplier value is %d",
-				rd_cen_vref_array[index]);
-				FAPI_INF("Configuring Read Vref Registers:");
-				rc = config_rd_cen_vref(i_target_mba, i_port,
-				l_rd_cen_vref[i_port]);
-				if (rc) return rc;
-				l_rd_cen_vref_in = l_rd_cen_vref[i_port];
-				//FAPI_INF(" Calling Shmoo function to find out Timing Margin:");
-				
-				rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-				&l_left_margin, &l_right_margin,
-				l_rd_cen_vref_in);
-				if (rc) return rc;
-				l_left_margin_rd_vref_array[index] = l_left_margin;
-				l_right_margin_rd_vref_array[index] = l_right_margin;
-				
-				FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d",
-				rd_cen_vref_array[index],
-				l_left_margin_rd_vref_array[index],
-				l_right_margin_rd_vref_array[index]);
-			}
-			else
-			{
-				l_left_margin_rd_vref_array[index] = 0;
-				l_right_margin_rd_vref_array[index] = 0;
-			}
-			l_rd_cen_vref_schmoo[i_port] = (l_rd_cen_vref_schmoo[i_port] >> 1);
-			/* FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d", rd_cen_vref_array[index],l_left_margin_rd_vref_array[index],  l_right_margin_rd_vref_array[index]);  */
-		}
-		l_rd_cen_vref_nom_fc = l_rd_cen_vref_nom[i_port];
-		find_best_margin(RD_VREF, l_left_margin_rd_vref_array,
-		l_right_margin_rd_vref_array, MAX_RD_VREF,
-		l_rd_cen_vref_nom_fc, count);
-		if (count >= MAX_RD_VREF)
-		{
-			FAPI_ERR("Read vref new input(%d) out of bounds, (>= %d)", count,
-			MAX_RD_VREF);
-			const uint8_t & COUNT_DATA = count;
-			FAPI_SET_HWP_ERROR(rc, RC_RD_VREF_SHMOO_INVALID_MARGIN_DATA);
-			return rc;
-		}
-		else
-		{
-			// FAPI_INF("Nominal value will not be changed!- Restoring the original values!");
-			FAPI_INF("Restoring Nominal values!");
-			rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba,
-			l_rd_cen_vref_nom);
-			if (rc) return rc;
-			rc = config_rd_cen_vref(i_target_mba, i_port,
-			l_rd_cen_vref_nom[i_port]);
-			if (rc) return rc;
-		}
-		
-		FAPI_INF("++++ Centaur Read Vref Shmoo function executed successfully ++++");
-	}
-	FAPI_INF("Restoring mcbist setup attribute...");
-	rc = reset_attribute(i_target_mba);if (rc) return rc;
-	return rc;
-}
-
-//------------------------------------------------------------------------------
-// Function name: rcv_imp_shmoo()
-// Receiver impedance shmoo function varies 9 values
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-//------------------------------------------------------------------------------
-fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba,
-uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid)
-{
-	fapi::ReturnCode rc;
-	uint8_t l_rcv_imp_dq_dqs[MAX_PORT] = {0};
-	uint8_t l_rcv_imp_dq_dqs_nom[MAX_PORT] = {0};
-	uint8_t l_rcv_imp_dq_dqs_nom_fc = 0;
-	uint8_t l_rcv_imp_dq_dqs_in = 0;
-	uint32_t l_rcv_imp_dq_dqs_schmoo[MAX_PORT] = {0};
-	uint8_t index = 0;
-	uint8_t count  = 0;
-	uint8_t shmoo_param_count = 0;
-	i_shmoo_type_valid = RD_EYE;   //Hard coded since no other shmoo is applicable - Temporary
-	
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint32_t l_left_margin_rcv_imp_array[MAX_RCV_IMP] = {0};
-	uint32_t l_right_margin_rcv_imp_array[MAX_RCV_IMP] = {0};
-
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_nom);
-	if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_rcv_imp_dq_dqs_schmoo);
-	if (rc) return rc;
-	
-	FAPI_INF("+++++++++++++++++RECIVER IMP Read Shmoo Attributes values+++++++++++++++");
-	FAPI_INF("CEN_RCV_IMP_DQ_DQS[0]  = %d , CEN_RCV_IMP_DQ_DQS[1]  = %d on %s",
-	l_rcv_imp_dq_dqs_nom[0],
-	l_rcv_imp_dq_dqs_nom[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("CEN_RCV_IMP_DQ_DQS_SCHMOO[0] = [%d], CEN_RCV_IMP_DQ_DQS_SCHMOO[1] = [%d], on %s",
-	l_rcv_imp_dq_dqs_schmoo[0],
-	l_rcv_imp_dq_dqs_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-
-	if (l_rcv_imp_dq_dqs_schmoo[i_port] == 0)
-	{
-		FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings");
-	}
-	else
-	{
-		for (index = 0; index < MAX_RCV_IMP; index += 1)
-		{
-			if ((l_rcv_imp_dq_dqs_schmoo[i_port] & MASK) == 1)
-			{
-				l_rcv_imp_dq_dqs[i_port] = rcv_imp_array[index];
-				FAPI_INF("Current Receiver Impedance: %d Ohms ",
-				rcv_imp_array[index]);
-				FAPI_INF("Configuring Receiver impedance registers:");
-				rc = config_rcv_imp(i_target_mba, i_port,
-				l_rcv_imp_dq_dqs[i_port]);
-				if (rc) return rc;
-				l_rcv_imp_dq_dqs_in = l_rcv_imp_dq_dqs[i_port];
-				//FAPI_INF("Calling Shmoo function to find out timing margin:");
-				if (shmoo_param_count)
-				{
-					rc = set_attribute(i_target_mba);
-					if (rc) return rc;
-				}
-				rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-				&l_left_margin, &l_right_margin,
-				l_rcv_imp_dq_dqs_in);
-				if (rc) return rc;
-				l_left_margin_rcv_imp_array[index] = l_left_margin;
-				l_right_margin_rcv_imp_array[index] = l_right_margin;
-				shmoo_param_count++;
-			}
-			else
-			{
-				l_left_margin_rcv_imp_array[index] = 0;
-				l_right_margin_rcv_imp_array[index] = 0;
-			}
-			l_rcv_imp_dq_dqs_schmoo[i_port] = (l_rcv_imp_dq_dqs_schmoo[i_port] >> 1);
-		}
-		l_rcv_imp_dq_dqs_nom_fc = l_rcv_imp_dq_dqs_nom[i_port];
-		find_best_margin(RCV_IMP, l_left_margin_rcv_imp_array,
-		l_right_margin_rcv_imp_array, MAX_RCV_IMP,
-		l_rcv_imp_dq_dqs_nom_fc, count);
-		if (count >= MAX_RCV_IMP)
-		{
-			FAPI_ERR("Receiver Imp new input(%d) out of bounds, (>= %d)",
-			count, MAX_RCV_IMP);
-			const uint8_t & COUNT_DATA = count;
-			FAPI_SET_HWP_ERROR(rc, RC_RCV_IMP_SHMOO_INVALID_MARGIN_DATA);
-			return rc;
-		}
-		else
-		{
-			//   FAPI_INF("Nominal value will not be changed!- Restoring the original values!");
-			FAPI_INF("Restoring the nominal values!");
-			rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba,
-			l_rcv_imp_dq_dqs_nom);
-			if (rc) return rc;
-			rc = config_rcv_imp(i_target_mba, i_port,
-			l_rcv_imp_dq_dqs_nom[i_port]);
-			if (rc) return rc;
-		}
-		FAPI_INF("Restoring mcbist setup attribute...");
-		rc = reset_attribute(i_target_mba);
-		if (rc) return rc;
-		FAPI_INF("++++ Receiver Impdeance Shmoo function executed successfully ++++");
-	}
-	return rc;
-}
-
-//------------------------------------------------------------------------------
-// Function name:delay_shmoo()
-// Calls Delay shmoo function varies delay values of each dq and returns timing margin
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-// Output param: l_left_margin = Left Margin(Setup time), 
-// l_right_margin = Right Margin (Hold time) in ps
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid,
-uint32_t *o_left_margin,
-uint32_t *o_right_margin,
-uint32_t i_shmoo_param)
-{
-	fapi::ReturnCode rc;
-	//FAPI_INF(" Inside before the delay shmoo " );
-	//Constructor CALL: generic_shmoo::generic_shmoo(uint8_t i_port, uint32_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm)
-	//generic_shmoo mss_shmoo=generic_shmoo(i_port,2,SEQ_LIN);
-	generic_shmoo * l_pShmoo = new generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN);
-	//generic_shmoo mss_shmoo=generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN);
-	rc = l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin,i_shmoo_param);
-	if(rc)
-	{
-		FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-	}
-	delete l_pShmoo;
-	return rc;
-}
-
-//------------------------------------------------------------------------------
-// Function name:delay_shmoo()
-// Calls Delay shmoo function varies delay values of each dq and returns timing margin
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS
-// Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR
-// i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg
-// Output param: l_left_margin = Left Margin(Setup time), 
-// l_right_margin = Right Margin (Hold time) in ps
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode delay_shmoo_ddr4(const fapi::Target & i_target_mba, uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid,
-uint32_t *o_left_margin,
-uint32_t *o_right_margin,
-uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2])
-{
-	fapi::ReturnCode rc;
-
-	generic_shmoo * l_pShmoo = new generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN);
-
-	rc = l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin,i_shmoo_param); if (rc) return rc;
-	
-	
-	
-	delete l_pShmoo;
-	return rc;
-}
-
-fapi::ReturnCode delay_shmoo_ddr4_pda(const fapi::Target & i_target_mba, uint8_t i_port,
-shmoo_type_t i_shmoo_type_valid,
-uint32_t *o_left_margin,
-uint32_t *o_right_margin,
-uint32_t i_shmoo_param,uint32_t pda_nibble_table[2][2][16][2])
-{
-	fapi::ReturnCode rc;
-
-	generic_shmoo * l_pShmoo = new generic_shmoo(i_port,i_shmoo_type_valid,SEQ_LIN);
-
-	rc = l_pShmoo->run(i_target_mba, o_left_margin, o_right_margin,i_shmoo_param); if (rc) return rc;
-	
-	rc = l_pShmoo->get_nibble_pda(i_target_mba,pda_nibble_table); if (rc) return rc;
-	
-	delete l_pShmoo;
-	return rc;
-}
-
-//------------------------------------------------------------------------------
-//Function name: set_attributes()
-//Description: Sets the attribute used  by all functions
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode set_attribute(const fapi::Target & i_target_mba)
-{
-	fapi::ReturnCode rc;
-	uint8_t l_mcbist_setup_multiple_set = 1;  //Hard coded it wont change
-	rc =  FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_set);
-	return rc;
-}
-
-fapi::ReturnCode rd_vref_shmoo_ddr4(const fapi::Target & i_target_mba)
-{
-	fapi::ReturnCode rc;
-	shmoo_type_t i_shmoo_type_valid = MCBIST; // Hard coded - Temporary
-	ecmdDataBufferBase l_data_buffer_64(64);
-	ecmdDataBufferBase data_buffer(64);
-	uint32_t l_rd_cen_vref_schmoo[MAX_PORT] = {0};
-	uint32_t l_left_margin = 0;
-	uint32_t l_right_margin = 0;
-	uint32_t l_rd_cen_vref_in = 0;
-	uint8_t l_attr_schmoo_test_type_u8 = 1;
-	rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc;
-	uint8_t i_port=0;
-	uint32_t diff_value = 1375;
-	uint32_t base = 70000;
-	uint32_t vref_value_print = 0;
-	uint32_t l_left_margin_rd_vref_array[16] = {0};
-	uint32_t l_right_margin_rd_vref_array[16] = {0};
-	uint32_t rc_num = 0;
-	uint8_t l_vref_num = 0;
-	
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF - Check Sanity only - DDR4 +++++++++++++++++++++++++++");
-	rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,
-	&l_left_margin, &l_right_margin,
-	l_rd_cen_vref_in);
-	if(rc) return rc;
-	FAPI_INF(" Setup and Sanity - Check disabled from now on..... Continuing .....");
-	rc = set_attribute(i_target_mba);
-	if (rc) return rc;
-	
-	i_shmoo_type_valid = RD_EYE;
-	l_attr_schmoo_test_type_u8 = 4;
-	rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_attr_schmoo_test_type_u8); if(rc) return rc;
-	//rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_nom);if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo);if (rc) return rc;
-	
-
-	FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%x], CEN_RD_VREF_SCHMOO[1] = [%x] on %s",
-	l_rd_cen_vref_schmoo[0],
-	l_rd_cen_vref_schmoo[1],
-	i_target_mba.toEcmdString());
-	FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++ Patch - Preet - RD_VREF DDR4 +++++++++++++++++++++++++++");
-
-	//For DDR3 - DDR4 Range 
-	if (l_rd_cen_vref_schmoo[i_port] == 1)
-	{
-		FAPI_INF("\n Testing Range - DDR3 to DDR4 - Vrefs");
-		base = 50000;
-	}
-	else
-	{
-		FAPI_INF("\n Testing Range - DDR4 Range Only - Vrefs");
-		
-		for(l_vref_num = 7; l_vref_num > 0 ; l_vref_num--)
-		{
-			l_rd_cen_vref_in = l_vref_num;
-			vref_value_print = base - (l_vref_num*diff_value);     
-			FAPI_INF("Current Vref value is %d",vref_value_print);
-			FAPI_INF("Configuring Read Vref Registers:");
-			rc = fapiGetScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,  
-			data_buffer); if(rc) return rc;
-			rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4);
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc_num = data_buffer.setBit(60); 
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiGetScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
-			data_buffer); if(rc) return rc;
-			rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4);
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc_num = data_buffer.setBit(60); 
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F,
-			data_buffer); if(rc) return rc;
-
-			rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,&l_left_margin, &l_right_margin,l_rd_cen_vref_in);if (rc) return rc;
-			l_left_margin_rd_vref_array[l_vref_num] = l_left_margin;
-			l_right_margin_rd_vref_array[l_vref_num] = l_right_margin;
-
-			FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d",vref_value_print, l_left_margin_rd_vref_array[l_vref_num],l_right_margin_rd_vref_array[l_vref_num]);
-		}
-		// For base + values
-
-		for(l_vref_num = 0; l_vref_num < 9; l_vref_num++)
-		{
-			
-			l_rd_cen_vref_in = l_vref_num;
-			vref_value_print = base + (l_vref_num*diff_value);     
-			FAPI_INF("Current Vref value is %d",vref_value_print);
-			FAPI_INF("Configuring Read Vref Registers:");
-			rc = fapiGetScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,  
-			data_buffer); if(rc) return rc;
-			rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4);
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc_num = data_buffer.setBit(60); 
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiGetScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
-			data_buffer); if(rc) return rc;
-			rc_num = rc_num | data_buffer.insertFromRight(l_rd_cen_vref_in,56,4);
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc_num = data_buffer.setBit(60);
-			if (rc_num)
-			{
-				FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F,
-			data_buffer); if(rc) return rc;
-
-			rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid,&l_left_margin, &l_right_margin,l_rd_cen_vref_in);if (rc) return rc;
-			l_left_margin_rd_vref_array[l_vref_num] = l_left_margin;
-			l_right_margin_rd_vref_array[l_vref_num] = l_right_margin;
-
-			FAPI_INF("Read Vref = %d ; Min Setup time = %d; Min Hold time = %d",vref_value_print, l_left_margin_rd_vref_array[l_vref_num],l_right_margin_rd_vref_array[l_vref_num]);
-		}
-		
-
-	}
-	FAPI_INF("++++ Centaur Read Vref Shmoo function DDR4 done ! ++++");
-	FAPI_INF("Restoring mcbist setup attribute...");
-	rc = reset_attribute(i_target_mba);		
-	return rc;
-}
-
-//------------------------------------------------------------------------------
-//Function name: reset_attributes()
-//Description: Sets the attribute used  by all functions
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode reset_attribute(const fapi::Target & i_target_mba)
-{
-	fapi::ReturnCode rc;
-	uint8_t l_mcbist_setup_multiple_reset = 0; //Hard coded it wont change
-	rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba, l_mcbist_setup_multiple_reset);
-	return rc;
-}
-
-//------------------------------------------------------------------------------
-// Function name:find_best_margin()
-// Finds better timing margin and returns the index
-// Input param: const fapi::Target MBA, port = 0,1
-// Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// i_left[], i_right[] - timing margin arrays, i_max = Max enum value of schmoo param
-// i_param_nom = selected shmoo parameter (DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP
-// Output param: o_index (returns index)
-//------------------------------------------------------------------------------
-
-
-void find_best_margin(shmoo_param i_shmoo_param_valid,
-uint32_t i_left[],
-uint32_t i_right[],
-const uint8_t i_max,
-uint32_t i_param_nom,
-uint8_t& o_index)
-{
-	uint32_t left_margin = 0;
-	uint32_t right_margin = 0;
-	uint32_t left_margin_nom = 0;
-	uint32_t right_margin_nom = 0;
-	uint32_t diff_margin_nom = 0;
-	//uint32_t total_margin = 0;
-	uint32_t diff_margin = 0;
-	uint8_t index = 0;
-	uint8_t index2 = 0;
-
-	for (index = 0; index < i_max; index += 1) //send max from top function
-	{
-		if (i_shmoo_param_valid & DRV_IMP)
-		{
-			if (drv_imp_array[index] == i_param_nom)
-			{
-				left_margin_nom = i_left[index];
-				right_margin_nom = i_right[index];
-				diff_margin_nom = (i_left[index] >= i_right[index]) ?
-				(i_left[index]- i_right[index]) :
-				(i_right[index] - i_left[index]);
-				//FAPI_INF("Driver impedance value (NOM): %d Ohms  Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
-				break;
-			}
-		}
-		else if (i_shmoo_param_valid & SLEW_RATE)
-		{
-			if (slew_rate_array[index] == i_param_nom)
-			{
-				left_margin_nom = i_left[index];
-				right_margin_nom = i_right[index];
-				diff_margin_nom = (i_left[index] >= i_right[index]) ?
-				(i_left[index] - i_right[index]) :
-				(i_right[index] - i_left[index]);
-				//FAPI_INF("Slew rate value (NOM): %d V/ns  Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
-				break;
-			}
-		}
-		else if (i_shmoo_param_valid & WR_VREF)
-		{
-			if (wr_vref_array_fitness[index] == i_param_nom)
-			{
-				left_margin_nom = i_left[index];
-				right_margin_nom = i_right[index];
-				diff_margin_nom = (i_left[index] >= i_right[index]) ?
-				(i_left[index] - i_right[index]) :
-				(i_right[index] - i_left[index]);
-				//FAPI_INF("Write DRAM Vref Multiplier value (NOM): %d   Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
-				break;
-			}
-		}
-		else if (i_shmoo_param_valid & RD_VREF)
-		{
-			if (rd_cen_vref_array_fitness[index] == i_param_nom)
-			{
-				left_margin_nom = i_left[index];
-				right_margin_nom = i_right[index];
-				diff_margin_nom = (i_left[index] >= i_right[index]) ?
-				(i_left[index] - i_right[index]) :
-				(i_right[index] - i_left[index]);
-				//FAPI_INF("Centaur Read Vref Multiplier value (NOM): %d  Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
-				break;
-			}
-		}
-		else if (i_shmoo_param_valid & RCV_IMP)
-		{
-			if (rcv_imp_array[index] == i_param_nom)
-			{
-				left_margin_nom = i_left[index];
-				right_margin_nom = i_right[index];
-				diff_margin_nom = (i_left[index] >= i_right[index]) ?
-				(i_left[index] - i_right[index]) :
-				(i_right[index] - i_left[index]);
-				// FAPI_INF("Receiver Impedance value (NOM): %d Ohms  Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]);
-				break;
-			}
-		}
-	}
-	for (index2 = 0; index2 < i_max; index2 += 1)
-	{
-		left_margin = i_left[index2];
-		right_margin = i_right[index2];
-		//total_margin = i_left[index2] + i_right[index2];
-		diff_margin = (i_left[index2] >= i_right[index2]) ? (i_left[index2]
-		- i_right[index2]) : (i_right[index2] - i_left[index2]);
-		if ((left_margin > 0 && right_margin > 0))
-		{
-			if ((left_margin >= left_margin_nom) && (right_margin
-						>= right_margin_nom) && (diff_margin <= diff_margin_nom))
-			{
-				o_index = index2;
-				//wont break this loop, since the purpose is to find the best parameter value & best timing margin The enum is constructed to do that
-				//  FAPI_INF("Index value %d, Min Setup Margin: %d, Min Hold Margin: %d", o_index, i_left[index2], i_right[index2]);
-			}
-		}
-	}
-}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H
deleted file mode 100755
index 34f2c11f7..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H
+++ /dev/null
@@ -1,85 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training_advanced.H,v 1.17 2014/01/23 17:10:05 sasethur Exp $
-/* File is created by SARAVANAN SETHURAMAN on Thur Sept 28 2011. */
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE :mss_draminit_training_advanced.H
-// *! DESCRIPTION : Tools for centaur procedures
-// *! OWNER NAME : SARAVANAN SETHURAMAN         email id: saravanans@in.ibm.com
-// *! BACKUP NAME :MARK D BELLOWS		email id: bellows@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-// General purpose funcs
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author:  |  Date:   | Comment:
-//---------|---------- |--------- |-----------------------------------------------
-//  1.0    | 28-Sep-11 | sasethur | First drop of Centaur
-//  1.1    | 18-Nov-11 | sasethur | Added typedef and comment update
-//  1.2    | 13-Feb-12 | sasethur | Updated scom address naming convention
-//  1.9    | 16-Jul-12 | bellows  | Added in Id tag
-//  1.10   | 15-Oct-12 | sasethur | Updated user option  
-//  1.11   | 26-Oct-12 | sasethur | Updated fapi:: and const Target & for HB environment
-//  1.12   | 15-Nov-12 | sasethur | Updated fw review comments
-//  1.13   | 07-Dec-12 | sasethur | Updated for fw review in comment section
-//  1.14   | 10-May-13 | sasethur | Added user input for test type, pattern from wrapper
-//  1.15   | 10-May-13 | sasethur | changed uint8_t to uint32_t for test type, pattern
-//  1.16   | 08-Aug-13 | sasethur | Removed Pattern and testype
-//  1.17   | 17-Jan-14 | mjjones  | RAS Review cleanup
-
-#ifndef _MSS_DRAMINIT_TRAINING_ADVANCED_H
-#define _MSS_DRAMINIT_TRAINING_ADVANCED_H
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_draminit_training_advanced_FP_t)(const fapi::Target &);
-
-
-extern "C"
-{
-/**
- * @brief Draminit training advanced procedure shmoo's drv_impedance, slew, vref and receiver impedance and get the optimum value
- *
- * @param[in] i_target Reference to MBA target
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba);
-
-} // extern C
-
-#endif// _MSS_DRAMINIT_TRAINING_ADVANCED_H 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
deleted file mode 100644
index 15177ebaf..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C
+++ /dev/null
@@ -1,4500 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_generic_shmoo.C,v 1.101 2015/09/25 20:19:34 sglancy Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_generic_shmoo.C,v $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : mss_generic_shmoo.C
-// *! TITLE                : MSS Generic Shmoo Implementation
-// *! DESCRIPTION          : Memory Subsystem Generic Shmoo -- abstraction for HB
-// *! CONTEXT              : To make all shmoos share a common abstraction layer
-// *!
-// *! OWNER  NAME          : Preetham Hosmane         Email: preeragh@in.ibm.com
-// *! BACKUP NAME          : Saravanan Sethuraman
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:   | Comment:
-// --------|--------|---------|--------------------------------------------------
-//   1.101 |sglancy |25-Sep-15| Fixed bug where shmoos only had a granularity of 2 ticks instead of 1
-//   1.100 |preeragh|25-Aug-15| More FW Review Comments
-//   1.99  |preeragh|25-Aug-15| More FW Review Comments
-//   1.98  |preeragh|19-Aug-15| FW Review Comments
-//   1.97  |preeragh|11-Aug-15| Removed -composite/bin dependency for WRT_DQS
-//   1.96  |preeragh|05-Aug-15| Optimized for Linear / Comp / Bin Schmoos
-//   1.95  |preeragh|22-Jul-15| 64bit compile fix
-//   1.94  |preeragh|22-Jun-15| DDR4 Enhancements and Optimizations
-//   1.93  |sglancy |16-Feb-15| Merged FW comments with lab needs
-//   1.92  |preeragh|15-Dec-14| Reverted Changes to v.1.87
-//   1.88  |rwheeler|10-Nov-14| Updated setup_mcbist for added variable.
-//   1.87  |abhijsau|7-Feb-14| added sanity check and error call out for schmoo's , removed printing of disconnected DQS.
-//   1.86  |abhijsau|24-Jan-14| Fixed code as per changes in access delay error check
-//   1.85  |mjjones |24-Jan-14| Fixed layout and error handling for RAS Review
-//   1.84  |abhijit |16-JAN-14| Changed EFF_DIMM_TYPE attribute to   ATTR_EFF_CUSTOM_DIMM
-//   1.83  |abhijit	|17-DEC-13| Changed the whole code structure to enable run from firmware
-//   1.81  |abhijit	|07-nov-13| Fixed memory release as per fw suggestion
-//   1.80  |abhijit	|07-nov-13| Fixed array initialization of bad bit array as per fw suggestion
-//   1.79  |abhijit	|07-nov-13| Fixed array initialization of valid_ranks[] in schmoo constructor & modified prints in report function to support 2D script
-//   1.78  |abhijit	|29-oct-13| added feature of not schmooing on bad dq and also added the target prints
-//   1.77  |abhijit	|21-oct-13| fixed the printing for tdqss min and tdqss max
-//   1.76  |abhijit	|17-oct-13| fixed the printing for dqs by 4
-//   1.74  |abhijit	|4-oct-13 | fixed fw comments
-//   1.73  |abhijit	|1-oct-13 | fixed write dqs by 8 for isdimm
-//   1.72  |abhijit	|20-sep-13| fixed printing of rd eye report as -1 for not finding left bound
-//   1.71  |abhijit	|18-sep-13| changed for mcbist call
-//   1.70  |abhijit	|12-sep-13| Fixed binary debug prints
-//   1.69  |abhijit	|12-sep-13| Fixed binary debug prints
-//   1.68  |abhijit	|11-sep-13| Added Binary Schmoo algorithm
-//   1.67  |abhijit	|4-sep-13 | fixed fw comment
-//   -		-		-			-
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include "mss_generic_shmoo.H"
-#include "mss_mcbist.H"
-#include <mss_draminit_training.H>
-#include <dimmBadDqBitmapFuncs.H>
-#include <mss_access_delay_reg.H>
-
-//#define DBG 0
-
-extern "C"
-{
-    using namespace fapi;
-
-    // START IMPLEMENTATION OF generic_shmoo CLASS METHODS
-    //! shmoo_mask - What shmoos do you want to run ... encoded as Hex 0x2,0x4,0x8,0x16
-    /*------------------------------------------------------------------------------
-    * constructor: generic_shmoo
-    * Description  :Constructor used to initialize variables and do the initial settings
-    *
-    @param uint8_t  addr:
-    @param shmoo_type_t shmoo_mask:
-    @param shmoo_algorithm_t shmoo_algorithm:
-    * ---------------------------------------------------------------------------*/
-    generic_shmoo::generic_shmoo(uint8_t addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm)
-    {
-        this->shmoo_mask=shmoo_mask; //! Sets what Shmoos the caller wants to run
-        this->algorithm=shmoo_algorithm ;
-        this->iv_shmoo_type = shmoo_mask;
-        this->iv_addr=addr;
-        iv_MAX_BYTES=10;
-        iv_DQS_ON=0;
-        iv_pattern=0;
-        iv_test_type=0;
-        iv_dmm_type=0;
-        iv_shmoo_param=0;
-        iv_binary_diff=2;
-        iv_vref_mul=0;
-        iv_SHMOO_ON = 0;
-
-        for(int p=0; p<MAX_PORT; p++)
-        {
-            for(int i=0; i<MAX_RANK; i++)
-            {
-                valid_rank1[p][i]=0;
-                valid_rank[i]=0;
-            }
-        }
-        iv_MAX_RANKS[0]=4;
-        iv_MAX_RANKS[1]=4;
-
-        if (shmoo_mask & TEST_NONE)
-        {
-            FAPI_INF("mss_generic_shmoo : NONE selected %d", shmoo_mask);
-        }
-
-        if (shmoo_mask & MCBIST)
-        {
-            FAPI_INF("mss_generic_shmoo : MCBIST selected %d", shmoo_mask);
-            iv_shmoo_type = 1;
-        }
-        if (shmoo_mask & WR_EYE)
-        {
-            FAPI_INF("mss_generic_shmoo : WR_EYE selected %d", shmoo_mask);
-            iv_shmoo_type = 2;
-        }
-
-        if (shmoo_mask & RD_EYE)
-        {
-            FAPI_INF("mss_generic_shmoo : RD_EYE selected %d", shmoo_mask);
-            iv_shmoo_type = 8;
-        }
-        if (shmoo_mask & WRT_DQS)
-        {
-            FAPI_INF("mss_generic_shmoo : WRT_DQS selected %d", shmoo_mask);
-            iv_shmoo_type = 4;
-            iv_DQS_ON = 1;
-        }
-
-        if(iv_DQS_ON==1) {
-            for (int k = 0; k < MAX_SHMOO; k++)
-            {
-                for (int i = 0; i < MAX_PORT; i++)
-                {
-                    for (int j = 0; j < iv_MAX_RANKS[i]; j++)
-                    {
-                        init_multi_array(SHMOO[k].MBA.P[i].S[j].K.nom_val, 250);
-                        init_multi_array(SHMOO[k].MBA.P[i].S[j].K.lb_regval, 0);
-                        init_multi_array(SHMOO[k].MBA.P[i].S[j].K.rb_regval, 512);
-                        init_multi_array(SHMOO[k].MBA.P[i].S[j].K.last_pass, 0);
-                        init_multi_array(SHMOO[k].MBA.P[i].S[j].K.last_fail, 0);
-                        init_multi_array(SHMOO[k].MBA.P[i].S[j].K.curr_val, 0);
-                    }
-                }
-            }
-        }
-    }
-
-    /*------------------------------------------------------------------------------
-    * Function: run
-    * Description  : ! Delegator function that runs shmoo using other  functions
-    *
-    * Parameters: i_target: mba;		iv_port: 0, 1
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,
-                                        uint32_t *o_right_min_margin,
-                                        uint32_t *o_left_min_margin,
-                                        uint32_t i_vref_mul)
-    {
-        fapi::ReturnCode rc;
-        uint8_t num_ranks_per_dimm[2][2];
-        uint8_t l_attr_eff_dimm_type_u8 = 0;
-        uint8_t l_attr_schmoo_test_type_u8 = 0;
-        uint8_t l_attr_schmoo_multiple_setup_call_u8 = 0;
-        uint8_t l_mcbist_prnt_off = 0;
-        uint64_t i_content_array[10];
-        uint8_t l_rankpgrp0[2] = { 0 };
-        uint8_t l_rankpgrp1[2] = { 0 };
-        uint8_t l_rankpgrp2[2] = { 0 };
-        uint8_t l_rankpgrp3[2] = { 0 };
-        uint8_t l_totrg_0 = 0;
-        uint8_t l_totrg_1 = 0;
-        uint8_t l_pp = 0;
-        uint8_t l_shmoo_param = 0;
-        uint8_t rank_table_port0[8] = {0};
-        uint8_t rank_table_port1[8] = {0};
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_MODE, &i_target, l_shmoo_param);
-        if (rc) return rc;
-        iv_shmoo_param = l_shmoo_param;
-        FAPI_INF(" +++++ The iv_shmoo_param = %d ++++ ",iv_shmoo_param);
-        iv_vref_mul = i_vref_mul;
-
-        ecmdDataBufferBase l_data_buffer1_64(64);
-        uint8_t l_dram_width = 0;
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width);
-        if(rc) return rc;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target, l_mcbist_prnt_off);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_per_dimm);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target, l_attr_schmoo_multiple_setup_call_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, l_rankpgrp0);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, l_rankpgrp1);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, l_rankpgrp2);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, l_rankpgrp3);
-        if(rc) return rc;
-
-        iv_MAX_RANKS[0]=num_ranks_per_dimm[0][0]+num_ranks_per_dimm[0][1];
-        iv_MAX_RANKS[1]=num_ranks_per_dimm[1][0]+num_ranks_per_dimm[1][1];
-        iv_pattern=0;
-        iv_test_type=0;
-        if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )
-        {
-            iv_MAX_BYTES=10;
-        }
-        else
-        {
-
-            iv_dmm_type=1;
-            iv_MAX_BYTES=9;
-        }
-        uint8_t i_rp = 0;
-
-        for (int l_rnk=0; l_rnk< iv_MAX_RANKS[0]; l_rnk++)
-        {   // Byte loop
-            rc = mss_getrankpair(i_target,0,0,&i_rp,rank_table_port0);
-            if(rc) return rc;
-        }
-
-        for (int l_rnk=0; l_rnk< iv_MAX_RANKS[0]; l_rnk++)
-        {   // Byte loop
-            rc = mss_getrankpair(i_target,1,0,&i_rp,rank_table_port1);
-            if(rc) return rc;
-        }
-
-        for(int l_p =0; l_p < 2; l_p++)
-        {
-            for (int l_rnk=0; l_rnk < 8; l_rnk++)
-            {   // Byte loop
-                if(l_p == 0)
-                    valid_rank1[l_p][l_rnk] = rank_table_port0[l_rnk];
-                else
-                    valid_rank1[l_p][l_rnk] = rank_table_port1[l_rnk];
-
-                FAPI_INF("PORT - %d - RANK %d\n",l_p,valid_rank1[l_p][l_rnk]);
-            }
-        }
-        FAPI_DBG("mss_generic_shmoo : run() for shmoo type %d", shmoo_mask);
-        // Check if all bytes/bits are in a pass condition initially .Otherwise quit
-
-        //Value of l_attr_schmoo_test_type_u8 are  0x01,     0x02,   0x04,      0x08,   0x10 ===
-        //                                       "MCBIST","WR_EYE","RD_EYE","WRT_DQS","RD_DQS" resp.
-
-        if (l_attr_schmoo_test_type_u8 == 0)
-        {
-            FAPI_INF("%s:This procedure wont change any delay settings",
-                     i_target.toEcmdString());
-            return rc;
-        }
-        if (l_attr_schmoo_test_type_u8 == 1)
-        {
-            rc = sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only
-
-            if (!rc.ok())
-            {
-                FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition");
-                return rc;
-            }
-        }
-        else if (l_attr_schmoo_test_type_u8 == 8)
-        {
-            if (l_rankpgrp0[0] != 255)
-            {
-                l_totrg_0++;
-            }
-            if (l_rankpgrp1[0] != 255)
-            {
-                l_totrg_0++;
-            }
-            if (l_rankpgrp2[0] != 255)
-            {
-                l_totrg_0++;
-            }
-            if (l_rankpgrp3[0] != 255)
-            {
-                l_totrg_0++;
-            }
-            if (l_rankpgrp0[1] != 255)
-            {
-                l_totrg_1++;
-            }
-            if (l_rankpgrp1[1] != 255)
-            {
-                l_totrg_1++;
-            }
-            if (l_rankpgrp2[1] != 255)
-            {
-                l_totrg_1++;
-            }
-            if (l_rankpgrp3[1] != 255)
-            {
-                l_totrg_1++;
-            }
-            if ((l_totrg_0 == 1) || (l_totrg_1 == 1))
-            {
-                rc = shmoo_save_rest(i_target, i_content_array, 0);
-                if(rc) return rc;
-                l_pp = 1;
-            }
-
-            if (l_pp == 1)
-            {
-                FAPI_INF("%s:Ping pong is disabled", i_target.toEcmdString());
-            }
-            else
-            {
-                FAPI_INF("%s:Ping pong is enabled", i_target.toEcmdString());
-            }
-
-            if ((l_pp = 1) && ((l_totrg_0 == 1) || (l_totrg_1 == 1)))
-            {
-                FAPI_INF("%s:Rank group is not good with ping pong. Hope you have set W2W gap to 10",
-                         i_target.toEcmdString());
-            }
-
-            iv_shmoo_type=4;   //for Gate Delays
-            rc=get_all_noms_dqs(i_target);
-            if(rc) return rc;
-
-            iv_shmoo_type=2; // For Access delays
-            rc=get_all_noms(i_target);
-            if(rc) return rc;
-
-            rc=schmoo_setup_mcb(i_target);
-            if(rc) return rc;
-            //Find RIGHT BOUND OR SETUP BOUND
-            rc=find_bound(i_target,RIGHT);
-            if(rc) return rc;
-
-            //Find LEFT BOUND OR HOLD BOUND
-            rc=find_bound(i_target,LEFT);
-            if(rc) return rc;
-            iv_shmoo_type=4;
-
-            if (l_dram_width == 4)
-            {
-                rc = get_margin_dqs_by4(i_target);
-                if (rc) return rc;
-            }
-            else
-            {
-                rc = get_margin_dqs_by8(i_target);
-                if (rc) return rc;
-            }
-
-            rc = print_report_dqs(i_target);
-            if (rc) return rc;
-
-            rc = get_min_margin_dqs(i_target, o_right_min_margin,o_left_min_margin);
-            if (rc) return rc;
-
-            if ((l_totrg_0 == 1) || (l_totrg_1 == 1))
-            {
-                rc = shmoo_save_rest(i_target, i_content_array, 1);
-                if(rc) return rc;
-            }
-
-            FAPI_INF("%s: Least tDQSSmin(ps)=%d ps and Least tDQSSmax=%d ps",i_target.toEcmdString(), *o_left_min_margin,*o_right_min_margin);
-        }
-        else
-        {
-            FAPI_INF("************ ++++++++++++++++++ ***************** +++++++++++++ *****************");
-            rc=get_all_noms(i_target);
-            if(rc) return rc;
-            if(l_attr_schmoo_multiple_setup_call_u8==0) {
-                rc=schmoo_setup_mcb(i_target);
-                if(rc) return rc;
-            }
-            rc=set_all_binary(i_target,RIGHT);
-            if(rc) return rc;
-
-            //Find RIGHT BOUND OR SETUP BOUND
-            rc=find_bound(i_target,RIGHT);
-            if(rc) return rc;
-            rc=set_all_binary(i_target,LEFT);
-            if(rc) return rc;
-            //Find LEFT BOUND OR HOLD BOUND
-            rc=find_bound(i_target,LEFT);
-            if(rc) return rc;
-
-            //Find the margins in Ps i.e setup margin ,hold margin,Eye width
-            rc=get_margin2(i_target);
-            if(rc) return rc;
-            //It is used to find the lowest of setup and hold margin
-            if(iv_shmoo_param==6)
-            {
-
-                rc=get_min_margin2(i_target,o_right_min_margin,o_left_min_margin);
-                if(rc) return rc;
-                rc=print_report(i_target);
-                if(rc) return rc;
-                FAPI_INF("%s:Minimum hold margin=%d ps and setup margin=%d ps",i_target.toEcmdString(), *o_left_min_margin,*o_right_min_margin);
-            }
-            else
-            {
-                rc=get_min_margin2(i_target,o_right_min_margin,o_left_min_margin);
-                if(rc) return rc;
-                rc=print_report(i_target);
-                if(rc) return rc;
-                FAPI_INF("%s:Minimum hold margin=%d ps and setup margin=%d ps",i_target.toEcmdString(), *o_left_min_margin,*o_right_min_margin);
-            }
-        }
-        l_mcbist_prnt_off=0;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target, l_mcbist_prnt_off);
-        if(rc) return rc;
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::shmoo_save_rest(const fapi::Target & i_target,
-            uint64_t i_content_array[],
-            uint8_t i_mode)
-    {
-        ReturnCode rc;
-        uint32_t rc_num;
-        uint8_t l_index = 0;
-        uint64_t l_value = 0;
-        uint64_t l_val_u64 = 0;
-        ecmdDataBufferBase l_shmoo1ab(64);
-        uint64_t l_Databitdir[10] = { 0x800000030301143full, 0x800004030301143full,
-                                      0x800008030301143full, 0x80000c030301143full, 0x800010030301143full,
-                                      0x800100030301143full, 0x800104030301143full, 0x800108030301143full,
-                                      0x80010c030301143full, 0x800110030301143full
-                                    };
-        if (i_mode == 0)
-        {
-            FAPI_INF("%s: Saving DP18 data bit direction register contents",
-                     i_target.toEcmdString());
-            for (l_index = 0; l_index < MAX_BYTE; l_index++)
-            {
-                l_value = l_Databitdir[l_index];
-                rc = fapiGetScom(i_target, l_value, l_shmoo1ab);
-                if (rc) return rc;
-                rc_num = l_shmoo1ab.setBit(57);
-                if (rc_num)
-                {
-                    FAPI_ERR("Error in function  shmoo_save_rest:");
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-                rc = fapiPutScom(i_target, l_value, l_shmoo1ab);
-                if (rc) return rc;
-                i_content_array[l_index] = l_shmoo1ab.getDoubleWord(0);
-            }
-        }
-        else if (i_mode == 1)
-        {
-            FAPI_INF("%s: Restoring DP18 data bit direction register contents",
-                     i_target.toEcmdString());
-            for (l_index = 0; l_index < MAX_BYTE; l_index++)
-            {
-                l_val_u64 = i_content_array[l_index];
-                l_value = l_Databitdir[l_index];
-                rc_num = l_shmoo1ab.setDoubleWord(0, l_val_u64);
-                if (rc_num)
-                {
-                    FAPI_ERR("Error in function  shmoo_save_rest:");
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-                rc = fapiPutScom(i_target, l_value, l_shmoo1ab);
-                if (rc) return rc;
-            }
-        }
-        else
-        {
-            FAPI_INF("%s:Invalid value of MODE", i_target.toEcmdString());
-        }
-        return rc;
-    }
-
-    /*------------------------------------------------------------------------------
-    * Function: sanity_check
-    * Description  : do intial mcbist check in nominal and report spd if any bad bit found
-    *
-    * Parameters: i_target: mba;
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        mcbist_mode = QUARTER_SLOW;
-        uint8_t l_mcb_status = 0;
-        uint8_t l_CDarray0[80] = { 0 };
-        uint8_t l_CDarray1[80] = { 0 };
-        uint8_t l_byte, l_rnk;
-        uint8_t l_nibble;
-        uint8_t l_n = 0;
-        uint8_t l_p = 0;
-        uint8_t rank = 0;
-        uint8_t l_faulted_rank = 255;
-        uint8_t l_faulted_port = 255;
-        uint8_t l_faulted_dimm = 255;
-        uint8_t l_memory_health = 0;
-        uint8_t l_max_byte = 10;
-
-        struct Subtest_info l_sub_info[30];
-
-        rc = schmoo_setup_mcb(i_target);
-        if (rc) return rc;
-        //FAPI_INF("%s:  starting  mcbist now",i_target.toEcmdString());
-        rc = start_mcb(i_target);
-        if (rc) return rc;
-        //FAPI_INF("%s:  polling   mcbist now",i_target.toEcmdString());
-        rc = poll_mcb(i_target, &l_mcb_status, l_sub_info, 1);
-        if (rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!");
-            return rc;
-        }
-        //FAPI_INF("%s:  checking error map ",i_target.toEcmdString());
-        rc = mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1,
-                           count_bad_dq);
-        if (rc) return rc;
-
-        for (l_p = 0; l_p < MAX_PORT; l_p++)
-        {
-            for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++)
-            {   // Byte loop
-                rank = valid_rank1[l_p][l_rnk];
-
-                l_n = 0;
-                for (l_byte = 0; l_byte < l_max_byte; l_byte++)
-                {
-                    //Nibble loop
-                    for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++)
-                    {
-                        if (mcbist_error_map[l_p][rank][l_byte][l_nibble] == 1)
-                        {
-                            l_memory_health = 1;
-                            l_faulted_rank = rank;
-                            l_faulted_port = l_p;
-                            if(rank>3) {
-                                l_faulted_dimm = 1;
-                            } else {
-                                l_faulted_dimm = 0;
-                            }
-                            break;
-                        }
-
-                        l_n++;
-
-                    }
-                }
-            }
-        }
-
-
-        //////////////// changed the check condition ... The error call out need to gard the dimm=l_faulted_dimm(0 or 1) //// port=l_faulted_port(0 or 1) target=i_target ...
-        if (l_memory_health)
-        {
-            FAPI_INF("generic_shmoo:sanity_check failed !! MCBIST failed on intial run , memory is not in good state needs investigation port=%d rank=%d dimm=%d",
-                     l_faulted_port, l_faulted_rank, l_faulted_dimm);
-            const fapi::Target & MBA_CHIPLET = i_target;
-            const uint8_t & MBA_PORT_NUMBER = l_faulted_port;
-            const uint8_t & MBA_DIMM_NUMBER = l_faulted_dimm;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_GENERIC_SHMOO_MCBIST_FAILED);
-            return rc;
-        }
-
-        return rc;
-    }
-    /*------------------------------------------------------------------------------
-    * Function: do_mcbist_reset
-    * Description  : do mcbist reset
-    *
-    * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass;
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::do_mcbist_reset(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint32_t rc_num = 0;
-
-        Target i_target_centaur;
-        rc = fapiGetParentChip(i_target, i_target_centaur);
-        if (rc) return rc;
-
-        ecmdDataBufferBase l_data_buffer_64(64);
-        rc_num = l_data_buffer_64.flushTo0();
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_reset_trap:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        //PORT - A
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMA1Q_0x0201166a, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMA2Q_0x0201166b, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMA3Q_0x0201166c, l_data_buffer_64);
-        if (rc) return (rc);
-
-        //PORT - B
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMB1Q_0x0201166d, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMB2Q_0x0201166e, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBEMB3Q_0x0201166f, l_data_buffer_64);
-        if (rc) return (rc);
-
-        // MBS 23
-        rc = fapiPutScom(i_target_centaur, 0x0201176a, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, 0x0201176b, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, 0x0201176c, l_data_buffer_64);
-        if (rc) return (rc);
-
-        //PORT - B
-        rc = fapiPutScom(i_target_centaur, 0x0201176d, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, 0x0201176e, l_data_buffer_64);
-        if (rc) return (rc);
-        rc = fapiPutScom(i_target_centaur, 0x0201176f, l_data_buffer_64);
-        if (rc) return (rc);
-
-        return rc;
-    }
-    /*------------------------------------------------------------------------------
-    * Function: do_mcbist_test
-    * Description  : do mcbist check for error on particular nibble
-    *
-    * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass;
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_mcb_status = 0;
-        struct Subtest_info l_sub_info[30];
-
-        rc = start_mcb(i_target);
-        if (rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: Start MCBIST failed !!");
-            return rc;
-        }
-        rc = poll_mcb(i_target, &l_mcb_status, l_sub_info, 1);
-        if (rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!");
-            return rc;
-        }
-
-        return rc;
-
-    }
-    /*------------------------------------------------------------------------------
-    * Function: check_error_map
-    * Description  : used by do_mcbist_test  to check the error map for particular nibble
-    *
-    * Parameters: iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass;
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::check_error_map(const fapi::Target & i_target,
-            uint8_t l_p,
-            uint8_t &pass)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_byte,l_rnk;
-        uint8_t l_nibble;
-        uint8_t l_byte_is;
-        uint8_t l_nibble_is;
-        uint8_t l_n=0;
-        pass=1;
-        input_type l_input_type_e =  ISDIMM_DQ;
-        uint8_t i_input_index_u8=0;
-        uint8_t l_val =0;
-        uint8_t rank=0;
-        uint8_t l_max_byte=10;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-
-        if(iv_dmm_type==1)
-        {
-            l_max_byte=9;
-            //l_max_nibble=18;
-        }
-
-        rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-            return rc;
-        }
-        // for (l_p=0;l_p<MAX_PORT;l_p++){
-        for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-        {   // Byte loop
-            //////
-            rank=valid_rank1[l_p][l_rnk];
-
-            l_n=0;
-            for(l_byte=0; l_byte<l_max_byte; l_byte++)
-            {
-                //Nibble loop
-                for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++)
-                {
-                    if(iv_dmm_type==1)
-                    {
-                        i_input_index_u8=8*l_byte+4*l_nibble;
-
-                        rc=rosetta_map(i_target,l_p,l_input_type_e,i_input_index_u8,0,l_val);
-                        if(rc) return rc;
-
-                        l_byte_is=l_val/8;
-                        l_nibble_is=l_val%8;
-                        if(l_nibble_is>3) {
-                            l_nibble_is=1;
-                        }
-                        else {
-                            l_nibble_is=0;
-                        }
-
-                        if( mcbist_error_map [l_p][rank][l_byte_is][l_nibble_is] == 1) {
-                            schmoo_error_map[l_p][rank][l_n]=1;
-                            pass = 1;
-                        }
-                        else
-                        {
-
-                            schmoo_error_map[l_p][rank][l_n]=0;
-                            pass = 0;
-                        }
-                    }
-                    else {
-                        if( mcbist_error_map [l_p][rank][l_byte][l_nibble] == 1) {
-
-                            schmoo_error_map[l_p][rank][l_n]=1;
-                            pass = 1;
-                        }
-                        else
-                        {
-                            schmoo_error_map[l_p][rank][l_n]=0;
-                            pass = 0;
-                        }
-                    }
-                    l_n++;
-                }//end of nibble loop
-            }//end byte loop
-        }//end rank loop
-        //}//end port loop
-
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::check_error_map2(const fapi::Target & i_target,uint8_t port,uint8_t &pass)
-    {
-
-        fapi::ReturnCode rc;
-        uint8_t l_byte,l_rnk;
-        uint8_t l_nibble;
-        uint8_t l_byte_is;
-        uint8_t l_nibble_is;
-        uint8_t l_n=0;
-        pass=1;
-        uint8_t l_p=0;
-        input_type l_input_type_e =  ISDIMM_DQ;
-        uint8_t i_input_index_u8=0;
-        uint8_t l_val =0;
-        uint8_t rank=0;
-        uint8_t l_max_byte=10;
-        uint8_t l_max_nibble=20;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-
-
-
-        if(iv_dmm_type==1)
-        {
-            l_max_byte=9;
-            l_max_nibble=18;
-        }
-
-        rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-            return rc;
-        }
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {   // Byte loop
-
-                rank=valid_rank1[l_p][l_rnk];
-
-                l_n=0;
-                for(l_byte=0; l_byte<l_max_byte; l_byte++)
-                {
-                    //Nibble loop
-                    for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++)
-                    {
-                        if(iv_dmm_type==1)
-                        {
-                            i_input_index_u8=8*l_byte+4*l_nibble;
-
-                            rc=rosetta_map(i_target,l_p,l_input_type_e,i_input_index_u8,0,l_val);
-                            if(rc) return rc;
-
-                            l_byte_is=l_val/8;
-                            l_nibble_is=l_val%8;
-                            if(l_nibble_is>3) {
-                                l_nibble_is=1;
-                            }
-                            else {
-                                l_nibble_is=0;
-                            }
-
-                            if( mcbist_error_map [l_p][rank][l_byte_is][l_nibble_is] == 1) {
-                                //pass=0;
-                                schmoo_error_map[l_p][rank][l_n]=1;
-
-                            }
-                            else
-                            {
-
-                                schmoo_error_map[l_p][rank][l_n]=0;
-
-
-                            }
-
-                        } else {
-
-
-                            if( mcbist_error_map [l_p][rank][l_byte][l_nibble] == 1) {
-                                //pass=0;
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                //FAPI_INF("We are in error and nibble is %d and rank is %d and port is %d \n",l_n,rank,l_p);
-                            }
-                            else
-                            {
-
-                                schmoo_error_map[l_p][rank][l_n]=0;
-
-
-                            }
-                        }
-                        l_n++;
-                    }
-                }
-            }
-        }
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {   // Byte loop
-                rank=valid_rank1[l_p][l_rnk];
-                for (l_n=0; l_n<l_max_nibble; l_n++) {
-                    if(schmoo_error_map[l_p][rank][l_n]==0) {
-
-                        pass=0;
-                    }
-
-                }
-            }
-        }
-
-
-        return rc;
-    }
-
-
-
-    /*------------------------------------------------------------------------------
-    * Function: init_multi_array
-    * Description  : This function do the initialization of various schmoo parameters
-    *
-    * Parameters: the array address and the initial value
-    * ---------------------------------------------------------------------------*/
-    void generic_shmoo::init_multi_array(uint16_t(&array)[MAX_DQ],
-                                         uint16_t init_val)
-    {
-
-        uint8_t l_byte, l_nibble, l_bit;
-        uint8_t l_dq = 0;
-        // Byte loop
-
-        for (l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++)
-        {   //Nibble loop
-            for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++)
-            {
-                //Bit loop
-                for (l_bit = 0; l_bit < MAX_BITS; l_bit++)
-                {
-                    l_dq = 8 * l_byte + 4 * l_nibble + l_bit;
-                    array[l_dq] = init_val;
-                }
-            }
-        }
-
-    }
-
-    fapi::ReturnCode generic_shmoo::set_all_binary(const fapi::Target & i_target,bound_t bound)
-    {
-
-        fapi::ReturnCode rc;
-        uint8_t l_rnk,l_byte,l_nibble,l_bit;
-        uint8_t l_dq=0;
-        uint8_t l_p=0;
-        uint32_t l_max=512;
-        uint32_t l_max_offset=64;
-        uint8_t rank = 0;
-
-        //if RD_EYE
-        if(iv_shmoo_type == 8)
-        {
-            l_max=127;
-        }
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {   // Byte loop
-
-                rank = valid_rank1[l_p][l_rnk];
-
-                for(l_byte=0; l_byte<iv_MAX_BYTES; l_byte++)
-                {   //Nibble loop
-                    for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++)
-                    {
-                        //Bit loop
-                        for(l_bit=0; l_bit<MAX_BITS; l_bit++)
-                        {
-                            l_dq=8*l_byte+4*l_nibble+l_bit;
-
-
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq];
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq];
-
-                            if(bound==RIGHT)
-                            {
-                                if((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_max_offset)>l_max) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=l_max;
-                                }
-                                else {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_max_offset;
-
-                                }
-                            }
-
-                            else
-                            {
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq] > 64)
-                                {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_max_offset;
-
-                                }
-                                else
-                                {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=0;
-
-                                }
-                            }
-                        }
-                    }
-                }
-            }
-        }
-        return rc;
-    }
-
-
-    /*------------------------------------------------------------------------------
-    * Function: get_all_noms
-    * Description  : This function gets the nominal values for each DQ
-    *
-    * Parameters: Target:MBA
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk,l_byte,l_nibble,l_bit;
-        uint8_t i_rnk=0;
-        uint16_t val=0;
-        uint8_t l_dq=0;
-        uint8_t l_p=0;
-        input_type_t l_input_type_e = WR_DQ;
-        access_type_t l_access_type_e = READ;
-        FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values");
-
-        if(iv_shmoo_type == 2)
-        {
-            l_input_type_e = WR_DQ;
-        }
-        else if(iv_shmoo_type == 8)
-        {
-            l_input_type_e = RD_DQ;
-        }
-        else if(iv_shmoo_type == 16)
-        {
-            l_input_type_e = RD_DQS;
-        }
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {   // Byte loop
-                i_rnk = valid_rank1[l_p][l_rnk];
-                for(l_byte=0; l_byte<iv_MAX_BYTES; l_byte++)
-                {   //Nibble loop
-                    for(l_nibble=0; l_nibble< MAX_NIBBLES; l_nibble++)
-                    {
-                        //Bit loop
-                        for(l_bit=0; l_bit<MAX_BITS; l_bit++)
-                        {
-                            l_dq=8*l_byte+4*l_nibble+l_bit;
-                            //printf("Before access call");
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,i_rnk,l_input_type_e,l_dq,0,val);
-                            if(rc) return rc;
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rnk].K.nom_val[l_dq]=val;
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rnk].K.rb_regval[l_dq]=val;
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rnk].K.lb_regval[l_dq]=val;
-
-                        }
-                    }
-                }
-            }
-        }
-        return rc;
-    }
-
-    ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-    fapi::ReturnCode generic_shmoo::get_all_noms_dqs(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk;
-        uint32_t val=0;
-        uint8_t l_p=0;
-        uint8_t l_max_nibble=20;
-        uint8_t rank=0;
-        uint8_t l_n=0;
-        FAPI_INF("%s:mss_generic_shmoo : get_all_noms_dqs : Reading in all nominal values and schmoo type=%d \n",i_target.toEcmdString(),1);
-        if(iv_dmm_type==1)
-        {
-
-            l_max_nibble=18;
-        }
-
-        input_type_t l_input_type_e = WR_DQS;
-        access_type_t l_access_type_e = READ ;
-        FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values");
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {   // Byte loop
-
-                rank=valid_rank1[l_p][l_rnk];
-
-                for (l_n=0; l_n<l_max_nibble; l_n++) {
-
-                    rc=mss_access_delay_reg(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_n,0,val);
-                    if(rc) return rc;
-                    SHMOO[1].MBA.P[l_p].S[rank].K.nom_val[l_n]=val;
-
-                }
-            }
-        }
-        return rc;
-    }
-
-    /*------------------------------------------------------------------------------
-    * Function: knob_update
-    * Description  : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag
-    *
-    * Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass,
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-        input_type_t l_input_type_e = WR_DQ;
-        uint8_t l_dq=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_n=0;
-        uint8_t l_i=0;
-        uint8_t l_p=0;
-        uint16_t l_delay=0;
-        uint16_t l_max_limit=500;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        //l_SCHMOO_NIBBLES = 2; //temp preet del this
-        rc=do_mcbist_reset(i_target);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::find_bound do_mcbist_reset failed");
-            return rc;
-        }
-
-        FAPI_INF("Linear in Progress FW --> %d",scenario);
-
-        if(iv_shmoo_type == 2)
-        {
-            l_input_type_e = WR_DQ;
-        }
-        else if(iv_shmoo_type == 8)
-        {
-            l_input_type_e = RD_DQ;
-            l_max_limit=127;
-        }
-        else if(iv_shmoo_type == 4)
-        {
-            l_input_type_e = WR_DQS;
-        }
-        //else if(iv_shmoo_type == 16)
-        //{l_input_type_e = RD_DQS;}
-
-        for (l_p=0; l_p < 2; l_p++) {
-            for(int i=0; i < iv_MAX_RANKS[l_p]; i++) {
-
-                rank = valid_rank1[l_p][i];
-                for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                }
-            }
-        }
-
-        if(bound==RIGHT)
-        {
-            for (l_delay=1; ((pass==0)); l_delay=l_delay+1) {
-
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-
-                            }
-                            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-                            if(rc) return rc;
-
-
-                            if(l_p == 0) {
-
-                                for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-
-                                    if(l_CDarray0[l_i]==l_dq) {
-
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            }
-                            else {
-                                for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                    if(l_CDarray1[l_i]==l_dq) {
-
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            }
-                            if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq] > l_max_limit) {
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                            }
-
-
-                            l_dq=l_dq+4;
-
-                        } //end of nibble
-                    } //end of rank
-                } //end of port loop
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 35)
-                    break;
-            } //end of Delay loop;
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    l_dq=bit;
-
-                    rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                        if(rc) return rc;
-                        l_dq=l_dq+4;
-                    }
-                }
-            }
-
-
-        }
-
-        if(bound==LEFT)
-        {
-            for (l_delay=1; (pass==0); l_delay+=1) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=bit;
-
-                        rank=valid_rank1[l_p][l_rank];
-
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-
-
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-
-                            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-                            if(rc) return rc;
-
-                            if(l_p==0) {
-                                for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-                                    if(l_CDarray0[l_i]==l_dq) {
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            } else {
-                                for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-                                    if(l_CDarray1[l_i]==l_dq) {
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            }
-
-                            if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq] == 0) {
-                                schmoo_error_map[l_p][rank][l_n] = 1;
-                            }
-
-                            l_dq=l_dq+4;
-
-                        }
-                    }
-
-                }
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                if (l_delay > 35)
-                    break;
-            }
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    l_dq=bit;
-
-                    rank=valid_rank1[l_p][l_rank];
-
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                        if(rc) return rc;
-                        l_dq=l_dq+4;
-                    }
-                }
-            }
-
-
-
-        }
-
-        return rc;
-    }
-
-
-    fapi::ReturnCode generic_shmoo::knob_update_bin(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-        input_type_t l_input_type_e = WR_DQ;
-        uint8_t l_dq=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_n=0;
-        uint8_t l_i=0;
-        uint8_t l_flag_p0=0;
-        uint8_t l_flag_p1=0;
-        FAPI_INF("Inside - Binary Schmoo FW - %d",scenario);
-        uint8_t l_p=0;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        uint8_t l_status=1;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        if(iv_shmoo_type == 2)
-        {
-            l_input_type_e = WR_DQ;
-        }
-        else if(iv_shmoo_type == 8)
-        {
-            l_input_type_e = RD_DQ;
-        }
-        else if(iv_shmoo_type == 4)
-        {
-            l_input_type_e = WR_DQS;
-        }
-        else if(iv_shmoo_type == 16)
-        {
-            l_input_type_e = RD_DQS;
-        }
-
-
-        rc=do_mcbist_reset(i_target);
-        if(rc)
-        {
-            FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed");
-            return rc;
-        }
-
-
-        //Reset schmoo_error_map
-
-        for(l_p = 0; l_p < MAX_PORT; l_p++) {
-            for(int i=0; i<iv_MAX_RANKS[l_p]; i++) {
-
-                rank=valid_rank1[l_p][i];
-                for (l_n=0; l_n < l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                    binary_done_map[l_p][rank][l_n]=0;
-                }
-            }
-        }
-        int count_cycle = 0;
-
-        if(bound==RIGHT)
-        {
-
-            //FAPI_INF("Algorithm is %d vs seq_lin %d\n",algorithm,SEQ_LIN);
-            //FAPI_INF("\n.....Inside Right Bound \n");
-            for(l_p = 0; l_p < MAX_PORT; l_p++) {
-                do {
-
-
-                    l_status=0;
-                    ////////////////////////////////////////////
-                    //FAPI_INF("\n +++ Cycle %d +++ ",count_cycle);
-                    //FAPI_INF(" . . . . .");
-
-                    ////////////////////////////////////////////
-
-
-                    //FAPI_INF("\nMBA = %d",l_mba);
-                    rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-                    if(rc) return rc;
-
-
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=bit;
-                        //////
-                        rank=valid_rank1[l_p][l_rank];
-                        //FAPI_INF ("Current Rank : %d",rank );
-
-
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            if(binary_done_map[l_p][rank][l_n]==0) {
-                                l_status=1;
-                            }
-                            l_flag_p0=0;
-                            l_flag_p1=0;
-                            if(l_p == 0) {
-                                for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-                                    if(l_CDarray0[l_i]==l_dq) {
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                        l_flag_p0=1;
-                                        //FAPI_INF(" \n I port=%d am the culprit %d ",l_p,l_dq);
-                                        //SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+1;
-                                    }
-                                }
-                            } else {
-                                for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                    if(l_CDarray1[l_i]==l_dq) {
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                        l_flag_p1=1;
-
-                                    }
-                                }
-                            }
-
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq];
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]);
-                                if(rc) return rc;
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-                                }
-                                else {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq];
-                                }
-
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) {
-                                    binary_done_map[l_p][rank][l_n]=1;
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-                                    // FAPI_INF("\n the right bound for port=%d rank=%d dq=%d is %d \n",l_p,rank,l_dq,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]);
-                                }
-                            }
-                            else {
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq];
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]);
-                                if(rc) return rc;
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-                                } else {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq];
-                                }
-                                if(l_p==0) {
-                                    if(l_flag_p0==1) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1;
-                                    }
-                                }
-                                else {
-                                    if(l_flag_p1==1) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1;
-                                    }
-                                }
-
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) {
-                                    binary_done_map[l_p][rank][l_n]=1;
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-
-                                }
-                            }
-                            l_dq=l_dq+4;
-                        }
-                    }
-
-
-                    rc=do_mcbist_reset(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed");
-                        return rc;
-                    }
-                    rc=do_mcbist_test(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-
-                    rc=check_error_map(i_target,l_p,pass);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-                    //printf("\n the status =%d \n",l_status);
-                    count_cycle++;
-                } while(l_status==1);
-            }
-
-            for(l_p = 0; l_p < MAX_PORT; l_p++)
-            {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    l_dq=bit;
-                    //////
-                    rank=valid_rank1[l_p][l_rank];
-
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                        if(rc) return rc;
-                        l_dq=l_dq+4;
-                    }
-                }
-            }
-
-
-
-
-        }
-        count_cycle = 0;
-        if(bound==LEFT)
-        {
-            for(l_p = 0; l_p < MAX_PORT; l_p++)
-            {
-                l_status = 1;
-
-                while(l_status==1)
-                {
-                    l_status=0;
-
-                    rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-                    if(rc) return rc;
-
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) {
-                        l_dq=bit;
-                        //////
-                        rank=valid_rank1[l_p][l_rank];
-
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-                            if(binary_done_map[l_p][rank][l_n]==0) {
-                                l_status=1;
-                            }
-
-                            l_flag_p0=0;
-                            l_flag_p1=0;
-                            if(l_p == 0) {
-                                for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-                                    if(l_CDarray0[l_i]==l_dq) {
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                        l_flag_p0=1;
-
-                                    }
-                                }
-                            }
-                            else {
-                                for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                    if(l_CDarray1[l_i]==l_dq) {
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                        l_flag_p1=1;
-
-                                    }
-                                }
-                            }
-
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq];
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]);
-                                if(rc) return rc;
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-                                } else {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq];
-                                }
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) {
-                                    binary_done_map[l_p][rank][l_n]=1;
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-
-                                }
-                            } else {
-
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq];
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq])/2;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq]);
-                                if(rc) return rc;
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-                                } else {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq];
-                                }
-
-
-                                if(l_p==0) {
-                                    if(l_flag_p0==1) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1;
-                                    }
-                                }
-                                else {
-                                    if(l_flag_p1==1) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]=1;
-                                    }
-                                }
-
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq]<=1) {
-                                    binary_done_map[l_p][rank][l_n]=1;
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq];
-
-                                }
-                            }
-                            l_dq=l_dq+4;
-                        }
-                    }
-                    rc=do_mcbist_reset(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed");
-                        return rc;
-                    }
-                    rc=do_mcbist_test(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-
-                    rc=check_error_map(i_target,l_p,pass);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-
-                    count_cycle++;
-                }
-            }
-
-            for(l_p = 0; l_p < MAX_PORT; l_p++)
-            {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    l_dq=bit;
-                    //////
-                    rank=valid_rank1[l_p][l_rank];
-                    //printf("Valid rank of %d %d %d %d %d %d %d %d",valid_rank1[0],valid_rank1[1],valid_rank1[2],valid_rank1[3],valid_rank1[4],valid_rank1[5],valid_rank1[6],valid_rank1[7]);
-
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                        if(rc) return rc;
-                        l_dq=l_dq+4;
-                    }
-                }
-            }
-
-        } // End of LEFT
-
-
-        return rc;
-    }
-
-    /*------------------------------------------------------------------------------
-    * Function: knob_update_dqs
-    * Description  : This is a key function is used to find right and left bound using new algorithm -- there is an option u can chose not to use it by setting a flag
-    *
-    * Parameters: Target:MBA,bound:RIGHT/LEFT,iv_SHMOO_ON:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass,
-    * --------------------------------------------------------------------------- */
-    fapi::ReturnCode generic_shmoo::knob_update_dqs_by4(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-
-        input_type_t l_input_type_e = WR_DQ;
-        input_type_t l_input_type_e_dqs = WR_DQS;
-        uint8_t l_dq=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_n=0;
-        uint8_t l_dqs=1;
-        uint8_t l_p=0;
-        uint8_t l_i=0;
-        uint16_t l_delay=0;
-        //uint32_t l_max=0;
-        uint16_t l_max_limit=500;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-        FAPI_INF("\nWRT_DQS --- > CDIMM  X4 - Scenario = %d",scenario);
-
-        rc=do_mcbist_test(i_target);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-            return rc;
-        }
-
-        rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-            return rc;
-        }
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for(int i=0; i<iv_MAX_RANKS[l_p]; i++) {
-
-                rank=valid_rank1[l_p][i];
-                for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                }
-            }
-        }
-
-        if(bound==RIGHT)
-        {
-
-            for (l_delay=1; ((pass==0)); l_delay++) {
-
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-                            if(l_p == 0) {
-
-                                for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-
-                                    if(l_CDarray0[l_i]==l_dq) {
-
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            } else {
-                                for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                    if(l_CDarray1[l_i]==l_dq) {
-
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            }
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-
-                                SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-
-                            if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dq] > l_max_limit) {
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                            }
-
-                        }
-
-
-                    }
-
-                }
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-            } //end of delay
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-
-
-                    rank=valid_rank1[l_p][l_rank];
-
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-
-                    }
-                }
-            }
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-
-                        rank=valid_rank1[l_p][l_rank];
-
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        }
-                    }
-                }
-            }
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-
-
-
-        }
-
-        if(bound==LEFT)
-        {
-
-
-            for (l_delay=1; (pass==0); l_delay++) {
-
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-
-                        rank=valid_rank1[l_p][l_rank];
-
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-
-                            if(l_p == 0) {
-
-                                for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-
-                                    if(l_CDarray0[l_i]==l_dq) {
-
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            } else {
-                                for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                    if(l_CDarray1[l_i]==l_dq) {
-
-                                        schmoo_error_map[l_p][rank][l_n]=1;
-                                    }
-                                }
-                            }
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]-l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-                            if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n] == 0) {
-                                schmoo_error_map[l_p][rank][l_n] = 1;
-                            }
-
-
-
-                        }
-                    }
-
-                }
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-
-            }
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-
-                    }
-                }
-            }
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        }
-                    }
-                }
-            }
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-                return rc;
-            }
-        }
-        return rc;
-    }
-    fapi::ReturnCode generic_shmoo::knob_update_dqs_by4_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-        //uint8_t  l_rp=0;
-        input_type_t l_input_type_e = WR_DQ;
-        input_type_t l_input_type_e_dqs = WR_DQS;
-        uint8_t l_dq=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_n=0;
-        uint8_t l_dqs=1;
-        uint8_t l_my_dqs=0;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-        uint8_t l_p=0;
-        uint16_t l_delay=0;
-        uint16_t l_max_limit=500;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        //uint8_t i_rp=0;
-
-        rc=do_mcbist_test(i_target);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-            return rc;
-        }
-
-        rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-            return rc;
-        }
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-        uint8_t l_dqs_arr[18]= {0,9,1,10,2,11,3,12,4,13,5,14,6,15,7,16,8,17};
-
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for(int i=0; i<iv_MAX_RANKS[l_p]; i++) {
-
-                rank=valid_rank1[l_p][i];
-                for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                }
-            }
-        }
-
-
-
-        if(bound==RIGHT)
-        {
-
-            for (l_delay=1; ((pass==0)); l_delay++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-                        l_my_dqs=0;
-
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-                            l_my_dqs=l_dqs_arr[l_n];
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-
-                                SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_my_dqs,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_my_dqs]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-
-                            if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dq]>l_max_limit) {
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                            }
-                        } //end of nibble loop
-                    } //end of rank
-                } //end of port
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-
-            } //end of delay loop
-
-            //////////////////////////////////////////////////////////////
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-                    }
-                }
-            }
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        }
-                    } //end of rank
-                } //end of port
-            } //end of bit
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-        }
-
-        if(bound==LEFT)
-        {
-            for (l_delay=1; (pass==0); l_delay++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-                        l_my_dqs=0;
-
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-                            l_my_dqs=l_dqs_arr[l_n];
-
-                            if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_my_dqs]=SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_my_dqs]-l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_my_dqs,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_my_dqs]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-
-                            if(SHMOO[l_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dq] == 0) {
-                                schmoo_error_map[l_p][rank][l_n] = 1;
-                            }
-                        }
-                    }
-                }
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-            } //end of delay loop
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-                    }
-                }
-            }
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        } //end of nibble
-                    } //end of rank
-                } //port loop
-            } //bit loop
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-        } //end of Left
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::knob_update_dqs_by8(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-        //uint8_t  l_rp=0;
-        input_type_t l_input_type_e = WR_DQ;
-        input_type_t l_input_type_e_dqs = WR_DQS;
-        uint8_t l_dq=0;
-        uint8_t l_dqs=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_n=0;
-        uint8_t l_scen_dqs=1;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-        uint8_t l_p=0;
-        uint16_t l_delay=0;
-        uint16_t l_max_limit=500;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-
-        FAPI_INF("\nWRT_DQS --- > CDIMM  X8 - Scenario = %d",scenario);
-        rc=do_mcbist_test(i_target);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-            return rc;
-        }
-
-        rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-            return rc;
-        }
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for(int i=0; i<iv_MAX_RANKS[l_p]; i++) {
-
-                rank=valid_rank1[l_p][i];
-                for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                } //end of nib
-            } //end of rank
-        } //end of port loop
-
-        if(bound==RIGHT)
-        {
-            for (l_delay=1; ((pass==0)); l_delay++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-                        l_dqs=0;
-
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-                            if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) {
-                                //Increase delay of DQS
-                                SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]+l_delay;
-                                //Write it to register DQS delay
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_n]);
-                                if(rc) return rc;
-
-                                //Increase Delay of DQ
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-
-                                l_dq=l_dq+1;
-
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-
-                            }
-
-                            if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq] > l_max_limit) {
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                schmoo_error_map[l_p][rank][l_n+1]=1;
-                            }
-
-                            if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) {
-
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                schmoo_error_map[l_p][rank][l_n+1]=1;
-                            }
-                            l_n=l_n+1;
-                            l_dqs=l_dqs+1;
-
-                        } //end of nibble loop
-                    } //end of rank loop
-                } //end of port loop
-
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-            } //end of delay loop
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {   rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-
-                    } //end of nib
-                } //end of rank
-            } //end of port loop
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        } //end of nib
-                    } //end of rank
-                } //end of port loop
-            } //end of bit loop
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-        }
-
-        if(bound==LEFT)
-        {
-            for (l_delay=1; (pass==0); l_delay++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-                        l_dqs=0;
-
-                        rank=valid_rank1[l_p][l_rank];
-
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-
-
-
-                            if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) {
-                                SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]-l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_n]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-                            if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq] == 0) {
-                                schmoo_error_map[l_p][rank][l_n] = 1;
-                                schmoo_error_map[l_p][rank][l_n+1] = 1;
-                            }
-
-                            if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) {
-
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                schmoo_error_map[l_p][rank][l_n+1]=1;
-                            }
-
-                            l_n=l_n+1;
-                            l_dqs=l_dq+1;
-
-                        }  //nibble loop
-                    } //rank loop
-                } //port loop
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-
-            } //end of l delay loop
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-
-                    }
-                }
-            }
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        }
-                    }
-                }
-            }
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-        } //end of bound Left
-
-        return rc;
-    }
-    fapi::ReturnCode generic_shmoo::knob_update_dqs_by8_isdimm(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-        //uint8_t  l_rp=0;
-        input_type_t l_input_type_e = WR_DQ;
-        input_type_t l_input_type_e_dqs = WR_DQS;
-        uint8_t l_dq=0;
-        uint8_t l_dqs=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_n=0;
-        uint8_t l_scen_dqs=1;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-        uint8_t l_p=0;
-        uint16_t l_delay=0;
-        uint16_t l_max_limit=500;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        //uint8_t i_rp=0;
-
-        rc=do_mcbist_test(i_target);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-            return rc;
-        }
-
-        rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-        if(rc)
-        {
-            FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-            return rc;
-        }
-
-        if(iv_dmm_type==1)
-        {
-
-            l_SCHMOO_NIBBLES=18;
-        }
-
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for(int i=0; i<iv_MAX_RANKS[l_p]; i++) {
-
-                rank=valid_rank1[l_p][i];
-                for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                }
-            }
-        }
-
-        if(bound==RIGHT)
-        {
-
-            for (l_delay=1; ((pass==0)); l_delay++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-                        l_dqs=0;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-                            l_dqs=l_n/2;
-
-                            if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) {
-
-                                SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_dqs,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]+l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq]);
-                                if(rc) return rc;
-
-                            }
-
-                            if(SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.rb_regval[l_dqs]>l_max_limit) {
-
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                schmoo_error_map[l_p][rank][l_n+1]=1;
-                            }
-
-                            if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) {
-
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                schmoo_error_map[l_p][rank][l_n+1]=1;
-                            }
-
-                            l_n=l_n+1;
-
-                        }
-
-
-                    }
-
-                }
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-            }
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    rank=valid_rank1[l_p][l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-                    }
-                }
-            }
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        }
-                    }
-                }
-            }
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-
-        }
-
-        if(bound==LEFT)
-        {
-
-            for (l_delay=1; (pass==0); l_delay++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=0;
-                        l_dqs=0;
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            l_dq=4*l_n;
-
-                            l_dqs=l_n/2;
-
-                            if((schmoo_error_map[l_p][rank][l_n]==0)&&(schmoo_error_map[l_p][rank][l_n+1]==0)) {
-                                SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs]=SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_dqs]-l_delay;
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_dqs,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs]);
-                                if(rc) return rc;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                                l_dq=l_dq+1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]-l_delay;
-
-                                rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq]);
-                                if(rc) return rc;
-                            }
-                            if(SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.lb_regval[l_dqs] == 0) {
-                                schmoo_error_map[l_p][rank][l_n] = 1;
-                                schmoo_error_map[l_p][rank][l_n+1] = 1;
-                            }
-
-                            if((schmoo_error_map[l_p][rank][l_n]==1)||(schmoo_error_map[l_p][rank][l_n+1]==1)) {
-
-                                schmoo_error_map[l_p][rank][l_n]=1;
-                                schmoo_error_map[l_p][rank][l_n+1]=1;
-                            }
-
-                            l_n=l_n+1;
-
-                        } //nibble loop
-                    } //rank loop
-                } //port loop
-
-                rc=do_mcbist_test(i_target);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-
-                rc=check_error_map2(i_target,l_p,pass);
-                if(rc)
-                {
-                    FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                    return rc;
-                }
-                if (l_delay > 70)
-                    break;
-
-            }
-
-
-            for (l_p=0; l_p<MAX_PORT; l_p++) {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    rank=valid_rank[l_rank];
-                    for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-                        rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e_dqs,l_n,0,SHMOO[l_scen_dqs].MBA.P[l_p].S[rank].K.nom_val[l_n]);
-                        if(rc) return rc;
-
-                    }
-                }
-            }
-
-            for(int l_bit=0; l_bit<4; l_bit++) {
-                for (l_p=0; l_p<MAX_PORT; l_p++) {
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        l_dq=l_bit;
-
-                        rank=valid_rank1[l_p][l_rank];
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq]);
-                            if(rc) return rc;
-                            l_dq=l_dq+4;
-                        }
-                    } //rank loop
-                } //port loop
-            } //bit loop
-
-            rc=do_mcbist_test(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed");
-                return rc;
-            }
-
-            rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!");
-
-                return rc;
-            }
-
-        } //end of LEFT
-
-        return rc;
-    }
-
-    /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-    /*------------------------------------------------------------------------------
-    * Function: find_bound
-    * Description  : This function calls the knob_update for each DQ which is used to find bound  that is left/right according to schmoo type
-    *
-    * Parameters: Target:MBA,bound:RIGHT/LEFT,
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::find_bound(const fapi::Target & i_target,
-            bound_t bound)
-    {
-        uint8_t l_bit = 0;
-        fapi::ReturnCode rc;
-        uint8_t l_comp = 0;
-        uint8_t pass = 0;
-        uint8_t l_dram_width = 0;
-        bool flag = false;
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_dram_width);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_MODE, &i_target, l_comp);
-        if(rc) return rc;
-
-        FAPI_INF("%s:\n SCHMOO IS IN PROGRESS ...... \n", i_target.toEcmdString());
-
-        //WRT_DQS Portion
-        if(iv_DQS_ON == 1)
-        {
-            rc=do_mcbist_reset(i_target);
-            if(rc)
-            {
-                FAPI_ERR("generic_shmoo::find_bound do_mcbist_reset failed");
-                return rc;
-            }
-            pass=0;
-            if(l_dram_width == 4) {
-                if(iv_dmm_type==1)
-                {
-                    rc=knob_update_dqs_by4_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag);
-                    if(rc) return rc;
-                }
-                else {
-                    rc=knob_update_dqs_by4(i_target,bound,iv_shmoo_type,l_bit,pass,flag);
-                    if(rc) return rc;
-                }
-            } //end of if dram_width 4
-            else {
-                if(iv_dmm_type==1)
-                {
-                    rc=knob_update_dqs_by8_isdimm(i_target,bound,iv_shmoo_type,l_bit,pass,flag);
-                    if(rc) return rc;
-                }
-                else {
-                    rc=knob_update_dqs_by8(i_target,bound,iv_shmoo_type,l_bit,pass,flag);
-                    if(rc) return rc;
-                }
-            }
-        } //end of if iv_DQS_ON 1 or WRT_DQS
-
-        else if(l_comp == 6) {
-            pass=0;
-            rc=knob_update_bin_composite(i_target,bound,iv_shmoo_type,l_bit,pass,flag);
-            if(rc) return rc;
-        }
-        else
-        {
-            //Bit loop
-            for (l_bit = 0; l_bit < MAX_BITS; l_bit++)
-            {
-                // preetham function here
-                pass = 0;
-
-                ////////////////////////////////////////////////////////////////////////////////////
-                if (l_comp  == 4)
-                {
-                    FAPI_INF("Calling Binary - %d",iv_shmoo_type);
-                    rc = knob_update_bin(i_target, bound, iv_shmoo_type, l_bit, pass, flag);
-                    if (rc) return rc;
-                }
-                else
-                {
-
-
-                    rc = knob_update(i_target, bound, iv_shmoo_type, l_bit, pass, flag);
-                    if (rc) return rc;
-                }
-            }
-        }
-
-        return rc;
-    }
-    /*------------------------------------------------------------------------------
-    * Function: print_report
-    * Description  : This function is used to print the information needed such as freq,voltage etc, and also the right,left and total margin
-    *
-    * Parameters: Target:MBA
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-
-        uint8_t l_rnk,l_byte,l_nibble,l_bit;
-        uint8_t l_dq=0;
-        //uint8_t l_rp=0;
-        uint8_t l_p=0;
-        uint8_t i_rank=0;
-        uint8_t l_mbapos = 0;
-        uint32_t l_attr_mss_freq_u32 = 0;
-        uint32_t l_attr_mss_volt_u32 = 0;
-        uint8_t l_attr_eff_dimm_type_u8 = 0;
-        uint8_t l_attr_eff_num_drops_per_port_u8 = 0;
-        uint8_t l_attr_eff_dram_width_u8 = 0;
-
-        fapi::Target l_target_centaur;
-
-
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if(rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);
-        if(rc) return rc;
-
-
-
-        FAPI_INF("%s:freq = %d on %s.",i_target.toEcmdString(),l_attr_mss_freq_u32, l_target_centaur.toEcmdString());
-        FAPI_INF("%s: volt = %d on %s.",i_target.toEcmdString(), l_attr_mss_volt_u32, l_target_centaur.toEcmdString());
-        FAPI_INF("%s: dimm_type = %d on %s.",i_target.toEcmdString(), l_attr_eff_dimm_type_u8, i_target.toEcmdString());
-        if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )
-        {
-            FAPI_INF("%s: It is a CDIMM",i_target.toEcmdString());
-        }
-        else
-        {
-            FAPI_INF("%s: It is an ISDIMM",i_target.toEcmdString());
-        }
-        FAPI_INF("%s: \n Number of ranks on port = 0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]);
-        FAPI_INF("%s: \n Number of ranks on port = 1 is %d \n \n",i_target.toEcmdString(),iv_MAX_RANKS[1]);
-        FAPI_INF("%s:+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++",i_target.toEcmdString());
-        //// Based on schmoo param the print will change eventually
-        if(iv_shmoo_type==2)
-        {
-            FAPI_INF("%s:Schmoo  POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate\tVref_Multiplier  ",i_target.toEcmdString());
-        }
-        else {
-            FAPI_INF("%s:Schmoo  POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tRdD_Setup(ps)\tRdD_Hold(ps)\tEye_Width(ps)\tBitRate\tVref_Multiplier  ",i_target.toEcmdString());
-        }
-
-
-        for (l_p=0; l_p < 2; l_p++) {
-            for (l_rnk=0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++)
-            {   i_rank = valid_rank1[l_p][l_rnk];
-                for(l_byte=0; l_byte < 10; l_byte++)
-                {
-
-                    //Nibble loop
-                    for(l_nibble=0; l_nibble< 2; l_nibble++)
-                    {
-                        for(l_bit=0; l_bit< 4; l_bit++)
-                        {
-                            l_dq=8*l_byte+4*l_nibble+l_bit;
-
-                            if(iv_shmoo_type==2)
-                            {
-                                FAPI_INF("%s:WR_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",i_target.toEcmdString(),l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq],l_attr_mss_freq_u32,iv_vref_mul);
-                            }
-                            if(iv_shmoo_type==8)
-                            {
-                                FAPI_INF("%s:RD_EYE %d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",i_target.toEcmdString(),l_mbapos,l_p,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq],l_attr_mss_freq_u32,iv_vref_mul);
-                            }
-
-                        }
-                    }
-                }
-            }
-        }
-
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::print_report_dqs(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-
-        uint8_t l_rnk, l_nibble;
-        uint8_t l_p = 0;
-        uint8_t i_rank = 0;
-        uint8_t l_mbapos = 0;
-        uint16_t l_total_margin = 0;
-        uint32_t l_attr_mss_freq_u32 = 0;
-        uint32_t l_attr_mss_volt_u32 = 0;
-        uint8_t l_attr_eff_dimm_type_u8 = 0;
-        uint8_t l_attr_eff_num_drops_per_port_u8 = 0;
-        uint8_t l_attr_eff_dram_width_u8 = 0;
-        fapi::Target l_target_centaur;
-        uint8_t l_SCHMOO_NIBBLES = 20;
-        uint8_t l_by8_dqs = 0;
-        char * l_pMike = new char[128];
-        char * l_str = new char[128];
-
-        uint8_t l_i = 0;
-        uint8_t l_dq = 0;
-        uint8_t l_flag = 0;
-        uint8_t l_CDarray0[80] = { 0 };
-        uint8_t l_CDarray1[80] = { 0 };
-
-        rc = mcb_error_map(i_target, mcbist_error_map, l_CDarray0, l_CDarray1,
-                           count_bad_dq);
-        if (rc)
-        {
-            FAPI_ERR("generic_shmoo::print report: mcb_error_map failed!!");
-            return rc;
-        }
-
-        if (iv_dmm_type == 1)
-        {
-            l_SCHMOO_NIBBLES = 18;
-        }
-
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if (rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target,
-                           l_attr_eff_num_drops_per_port_u8);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target,
-                           l_attr_eff_dram_width_u8);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);
-        if (rc) return rc;
-
-        if (l_attr_eff_dram_width_u8 == 8)
-        {
-            l_SCHMOO_NIBBLES = 10;
-            if (iv_dmm_type == 1)
-            {
-                l_SCHMOO_NIBBLES = 9;
-            }
-        }
-
-        //FAPI_INF("%s:Shmoonibbles val is=%d",l_SCHMOO_NIBBLES);
-
-        FAPI_INF("%s:      freq = %d on %s.", i_target.toEcmdString(),
-                 l_attr_mss_freq_u32, l_target_centaur.toEcmdString());
-        FAPI_INF("%s:volt = %d on %s.", i_target.toEcmdString(),
-                 l_attr_mss_volt_u32, l_target_centaur.toEcmdString());
-        FAPI_INF("%s:dimm_type = %d on %s.", i_target.toEcmdString(),
-                 l_attr_eff_dimm_type_u8, i_target.toEcmdString());
-        FAPI_INF("%s:\n Number of ranks on port=0 is %d ", i_target.toEcmdString(),
-                 iv_MAX_RANKS[0]);
-        FAPI_INF("%s:\n Number of ranks on port=1 is %d ", i_target.toEcmdString(),
-                 iv_MAX_RANKS[1]);
-
-        if (l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-        {
-            FAPI_INF("%s:It is a CDIMM", i_target.toEcmdString());
-        }
-        else
-        {
-            FAPI_INF("%s:It is an ISDIMM", i_target.toEcmdString());
-        }
-
-        FAPI_INF("%s:\n Number of ranks on port=0 is %d ", i_target.toEcmdString(),
-                 iv_MAX_RANKS[0]);
-        FAPI_INF("%s:\n Number of ranks on port=1 is %d \n \n",
-                 i_target.toEcmdString(), iv_MAX_RANKS[1]);
-
-        FAPI_INF(
-            "+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++");
-        sprintf(l_pMike, "Schmoo  POS\tPort\tRank\tDQS\tNominal\t\ttDQSSmin_PR_limit\ttDQSSmax_PR_limit\ttDQSSmin(ps)\ttDQSSmax(ps)\ttDQSS_Window(ps)\tBitRate  ");
-        FAPI_INF("%s", l_pMike);
-        delete[] l_pMike;
-
-        for (l_p = 0; l_p < MAX_PORT; l_p++)
-        {
-            for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                ////
-
-                i_rank = valid_rank1[l_p][l_rnk];
-                //
-                if (rc) return rc;
-
-                for (l_nibble = 0; l_nibble < l_SCHMOO_NIBBLES; l_nibble++)
-                {
-                    l_by8_dqs = l_nibble;
-                    if (iv_dmm_type == 0)
-                    {
-                        if (l_attr_eff_dram_width_u8 == 8)
-                        {
-                            l_nibble = l_nibble * 2;
-                        }
-                    }
-                    l_dq=4* l_nibble;
-                    l_flag=0;
-                    if (l_p == 0)
-                    {
-                        for (l_i = 0; l_i < count_bad_dq[0]; l_i++)
-                        {
-                            if (l_CDarray0[l_i] == l_dq)
-                            {
-                                l_flag=1;
-
-                            }
-                        }
-                    }
-                    else
-                    {
-                        for (l_i = 0; l_i < count_bad_dq[1]; l_i++)
-                        {
-                            if (l_CDarray1[l_i] == l_dq)
-                            {
-                                l_flag=1;
-
-                            }
-                        }
-                    }
-
-                    if(l_flag==1)
-                    {
-                        continue;
-                    }
-
-                    l_total_margin
-                        = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]
-                          + SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble];
-                    sprintf(l_str, "%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d",
-                            l_mbapos, l_p, i_rank, l_nibble,
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.curr_val[l_nibble],
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble],
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble],
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble],
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble],
-                            l_total_margin, l_attr_mss_freq_u32);
-
-                    FAPI_INF("WR_DQS %s", l_str);
-
-                    if (iv_dmm_type == 0)
-                    {
-                        if (l_attr_eff_dram_width_u8 == 8)
-                        {
-                            l_nibble = l_by8_dqs;
-                        }
-                    }
-
-                }
-            }
-        }
-        delete[] l_str;
-        return rc;
-    }
-
-
-
-
-    fapi::ReturnCode generic_shmoo::print_report_dqs2(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk,l_nibble;
-        uint8_t l_p=0;
-        uint8_t i_rank=0;
-        uint8_t l_mbapos = 0;
-        uint32_t l_attr_mss_freq_u32 = 0;
-        uint32_t l_attr_mss_volt_u32 = 0;
-        uint8_t l_attr_eff_dimm_type_u8 = 0;
-        uint8_t l_attr_eff_num_drops_per_port_u8 = 0;
-        uint8_t l_attr_eff_dram_width_u8 = 0;
-        fapi::Target l_target_centaur;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        uint8_t l_by8_dqs=0;
-
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if(rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);
-        if(rc) return rc;
-
-        if(l_attr_eff_dram_width_u8 == 8) {
-            l_SCHMOO_NIBBLES=10;
-            if(iv_dmm_type==1)
-            {
-                l_SCHMOO_NIBBLES=9;
-            }
-        }
-        FAPI_INF("%s:freq = %d on %s.",i_target.toEcmdString(), l_attr_mss_freq_u32, l_target_centaur.toEcmdString());
-        FAPI_INF("%s:volt = %d on %s.",i_target.toEcmdString(), l_attr_mss_volt_u32, l_target_centaur.toEcmdString());
-        FAPI_INF("%s:dimm_type = %d on %s.",i_target.toEcmdString(), l_attr_eff_dimm_type_u8, i_target.toEcmdString());
-        FAPI_INF("%s:\n Number of ranks on port=0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]);
-        FAPI_INF("%s:\n Number of ranks on port=1 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[1]);
-
-
-        if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )
-        {
-            FAPI_INF("%s:It is a CDIMM",i_target.toEcmdString());
-        }
-        else
-        {
-            FAPI_INF("%s:It is an ISDIMM",i_target.toEcmdString());
-        }
-
-        FAPI_INF("%s:\n Number of ranks on port=0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]);
-        FAPI_INF("%s:\n Number of ranks on port=1 is %d \n \n",i_target.toEcmdString(),iv_MAX_RANKS[1]);
-
-        FAPI_INF("%s:+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++",i_target.toEcmdString());
-        FAPI_INF("%s:Schmoo  POS\tPort\tRank\tDQS\tNominal\t\ttDQSSmin_PR_limit\ttDQSSmax_PR_limit\ttDQSSmin(ps)\ttDQSSmax(ps)\ttDQSS_Window(ps)\tBitRate  ",i_target.toEcmdString());
-
-        iv_shmoo_type=4;
-
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                i_rank=valid_rank1[l_p][l_rnk];
-                for(l_nibble=0; l_nibble< l_SCHMOO_NIBBLES; l_nibble++)
-                {
-                    l_by8_dqs=l_nibble;
-                    if(iv_dmm_type==0)
-                    {
-                        if(l_attr_eff_dram_width_u8 == 8)
-                        {
-                            l_nibble=l_nibble*2;
-                        }
-                    }
-
-                    FAPI_INF("%s:WR_DQS %d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\n ",i_target.toEcmdString(),l_mbapos,l_p,i_rank,l_nibble,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble],SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble],l_attr_mss_freq_u32);
-
-                    if(iv_dmm_type==0)
-                    {
-                        if(l_attr_eff_dram_width_u8 == 8)
-                        {
-                            l_nibble=l_by8_dqs;
-                        }
-                    }
-
-
-                }
-            }
-        }
-
-        //fclose(fp);
-        return rc;
-    }
-///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-    /*------------------------------------------------------------------------------
-    * Function: get_margin
-    * Description  : This function is used to get margin for setup,hold and total eye width in Ps by using frequency
-    *
-    * Parameters: Target:MBA
-    * ---------------------------------------------------------------------------*/
-    fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk, l_byte, l_nibble, l_bit;
-        uint32_t l_attr_mss_freq_margin_u32 = 0;
-        uint32_t l_freq = 0;
-        uint64_t l_cyc = 1000000000000000ULL;
-        uint8_t l_dq = 0;
-        uint8_t l_p = 0;
-        uint8_t i_rank = 0;
-        uint64_t l_factor = 0;
-        uint64_t l_factor_ps = 1000000000;
-        fapi::Target l_target_centaur;
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if (rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur,
-                           l_attr_mss_freq_margin_u32);
-        if (rc) return rc;
-        l_freq = l_attr_mss_freq_margin_u32 / 2;
-        l_cyc = l_cyc / l_freq;// converting to zepto to get more accurate data
-        l_factor = l_cyc / 128;
-        //FAPI_INF("l_factor is % llu ",l_factor);
-
-        for (l_p = 0; l_p < MAX_PORT; l_p++)
-        {
-            for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                ////
-
-                i_rank = valid_rank1[l_p][l_rnk];
-                //
-                if (rc) return rc;
-                for (l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++)
-                {
-                    //Nibble loop
-                    for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++)
-                    {
-                        for (l_bit = 0; l_bit < MAX_BITS; l_bit++)
-                        {
-                            l_dq = 8 * l_byte + 4 * l_nibble + l_bit;
-
-                            if (iv_shmoo_type == 1)
-                            {
-                                if (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] == 0)
-                                {
-
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] = 0;
-
-
-                                }
-                            }
-
-                            if (iv_shmoo_param == 4)
-                            {
-                                if (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]
-                                        > SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq])
-                                {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]
-                                        = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq] - 1;
-                                }
-                                if (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]
-                                        < SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq])
-                                {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]
-                                        = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] + 1;
-                                }
-                            }
-                            else
-                            {
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]
-                                    = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]- 1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]
-                                    = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] + 1;
-                            }
-
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]
-                                = ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]
-                                    - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq])
-                                   * l_factor) / l_factor_ps;
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]
-                                = ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]
-                                    - SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq])
-                                   * l_factor) / l_factor_ps;
-                        }
-                    }
-                }
-            }
-        }
-
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::get_margin2(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk,l_byte,l_nibble,l_bit;
-        uint32_t l_attr_mss_freq_margin_u32 = 0;
-        uint32_t l_freq=0;
-        uint64_t l_cyc = 1000000000000000ULL;
-        uint8_t l_dq=0;
-        uint8_t  l_p=0;
-        uint8_t i_rank=0;
-        uint64_t l_factor=0;
-        uint64_t l_factor_ps=1000000000;
-        fapi::Target l_target_centaur;
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32);
-        if(rc) return rc;
-        l_freq=l_attr_mss_freq_margin_u32/2;
-        l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data
-        l_factor=l_cyc/128;
-
-        for (l_p=0; l_p< 2; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                //////
-                i_rank=valid_rank1[l_p][l_rnk];
-                //////
-                for(l_byte=0; l_byte< 10; l_byte++)
-                {
-
-                    //Nibble loop
-                    for(l_nibble=0; l_nibble< 2; l_nibble++)
-                    {
-                        for(l_bit=0; l_bit< 4; l_bit++)
-                        {
-                            l_dq=8*l_byte+4*l_nibble+l_bit;
-
-                            if(iv_shmoo_type==8)
-                            {
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq] == 0) {
-
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=0;
-                                    if((iv_shmoo_param==4)||(iv_shmoo_param==6)) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]-1;
-                                    } else {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]-2;
-                                    }
-                                    //FAPI_INF("\n the value of left bound after is %d \n",SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]);
-                                }
-                            }
-
-                            if((iv_shmoo_param==4)||(iv_shmoo_param==6)) {
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]-1;
-                                }
-                                if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]<SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]+1;
-                                }
-                            } else {
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]-1;
-                                SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq]+1;
-                            }
-
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]=((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq])*l_factor)/l_factor_ps;
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]= ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128);
-                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq];
-                        }
-                    }
-                }
-            }
-        }
-
-        return rc;
-    }
-
-    /*
-    	fapi::ReturnCode generic_shmoo::print_report2(const fapi::Target & i_target)
-    	{
-    		fapi::ReturnCode rc;
-    		FAPI_INF("\nIn print report!!!\n");
-    		uint8_t l_rnk, l_nibble;
-    		uint8_t l_p = 0;
-    		uint8_t i_rank = 0;
-    		uint8_t l_mbapos = 0;
-    		uint16_t l_total_margin = 0;
-    		//uint8_t l_SCHMOO_NIBBLES = 20;
-    		char * l_pMike = new char[128];
-    		char * l_str = new char[128];
-    		uint8_t l_i = 0;
-    		uint8_t l_dq = 0;
-    		uint8_t l_byte = 0;
-    		uint8_t l_bit = 0;
-    		uint8_t l_flag = 0;
-    		uint8_t l_CDarray0[80] = { 0 };
-    		uint8_t l_CDarray1[80] = { 0 };
-    		uint8_t vrefdq_train_range[2][2][4];
-    		uint32_t l_attr_mss_freq_u32 = 0;
-    		uint32_t l_attr_mss_volt_u32 = 0;
-    		uint8_t l_attr_eff_dimm_type_u8 = 0;
-    		uint8_t l_attr_eff_num_drops_per_port_u8 = 0;
-    		uint8_t l_attr_eff_dram_width_u8 = 0;
-    		fapi::Target l_target_centaur;
-    		uint8_t l_dram_gen = 1;
-    		uint8_t base_percent = 60;
-    		float index_mul_print = 0.65;
-    		float vref_val_print = 0;
-
-
-    		rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc;
-    		rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range);if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);if(rc) return rc;
-    		rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, l_dram_gen); if(rc) return rc;
-
-
-
-    		if(vrefdq_train_range[0][0][0] == 1)
-    		{
-    			base_percent = 45;
-    		}
-
-    		vref_val_print = base_percent + (iv_vref_mul * index_mul_print);
-    		FAPI_INF("%s: freq = %d on %s.",i_target.toEcmdString(),l_attr_mss_freq_u32, l_target_centaur.toEcmdString());
-    		FAPI_INF("%s: volt = %d on %s.",i_target.toEcmdString(), l_attr_mss_volt_u32, l_target_centaur.toEcmdString());
-    		FAPI_INF("%s: dimm_type = %d on %s.",i_target.toEcmdString(), l_attr_eff_dimm_type_u8, i_target.toEcmdString());
-    		if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )
-    		{
-    			FAPI_INF("%s: It is a CDIMM",i_target.toEcmdString());
-    		}
-    		else
-    		{
-    			FAPI_INF("%s: It is an ISDIMM",i_target.toEcmdString());
-    		}
-    		FAPI_INF("%s: \n Number of ranks on port = 0 is %d ",i_target.toEcmdString(),iv_MAX_RANKS[0]);
-    		FAPI_INF("%s: \n Number of ranks on port = 1 is %d \n \n",i_target.toEcmdString(),iv_MAX_RANKS[1]);
-    		if (iv_shmoo_type == 2)
-    		{
-    			FAPI_INF("\n\n********************* WR_EYE Margins ********************** \n\n");
-    			sprintf(l_pMike, "\nSchmoo\tP\tP\tR\tB\tN\tBi\tNom\t\tRb\t\tLb\t\tSetup\t\tHold\t\tTotal\tfreq\tiv_ref_mul  ");
-
-    		}
-    		else
-    		{
-    			FAPI_INF("\n\n********************* RD_EYE Margins ********************** \n\n");
-    			sprintf(l_pMike, "\nSchmoo\tP\tP\tR\tB\tN\tBi\tNom\t\tRb\t\tLb\t\tSetup\t\tHold\t\tTotal\t\tfreq\t\tiv_ref_mul  ");
-    		}
-    		//printf("Schmoo  POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit \n");
-    		FAPI_INF("%s", l_pMike);
-    		delete[] l_pMike;
-
-
-
-    		rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);if(rc)return rc;
-
-
-    		for (l_p = 0; l_p < MAX_PORT; l_p++)
-    		{
-    			for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++)
-    			{
-    				//////
-
-    				i_rank = valid_rank1[l_p][l_rnk];
-    				////
-
-    				for (l_byte = 0; l_byte < iv_MAX_BYTES; l_byte++)
-    				{
-    					//Nibble loop
-    					for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++)
-    					{
-
-    						l_dq=8 * l_byte + 4 * l_nibble;
-    						l_flag=0;
-    						if (l_p == 0)
-    						{
-    							for (l_i = 0; l_i < count_bad_dq[0]; l_i++)
-    							{
-    								if (l_CDarray0[l_i] == l_dq)
-    								{
-    									l_flag=1;
-
-    								}
-    							}
-    						}
-    						else
-    						{
-    							for (l_i = 0; l_i < count_bad_dq[1]; l_i++)
-    							{
-    								if (l_CDarray1[l_i] == l_dq)
-    								{
-    									l_flag=1;
-
-    								}
-    							}
-    						}
-
-    						if(l_flag==1)
-    						{
-    							//printf("Would normally skip prints...\n");
-    							//continue;
-    						}
-    						for (l_bit = 0; l_bit < MAX_BITS; l_bit++)
-    						{
-    							l_dq = 8 * l_byte + 4 * l_nibble + l_bit;
-    							l_total_margin
-    							= SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]
-    							+ SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq];
-    							if(l_dram_gen ==2)
-    							{
-    								sprintf(l_str, "%d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%f",
-    								l_mbapos, l_p, i_rank, l_byte, l_nibble, l_bit,
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq],
-    								l_total_margin, l_attr_mss_freq_u32, vref_val_print);
-
-    							}
-    							else
-    							{
-    								sprintf(l_str, "%d\t%d\t%d\t%d\t%d\t%d\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d\t\t%d",
-    								l_mbapos, l_p, i_rank, l_byte, l_nibble, l_bit,
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq],
-    								SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq],
-    								l_total_margin, l_attr_mss_freq_u32, iv_vref_mul);
-    							}
-    							if (iv_shmoo_type == 2)
-    							{
-    								FAPI_INF("\nWR_EYE %s ", l_str);
-
-    							}
-    							else if (iv_shmoo_type == 8)
-    							{
-    								FAPI_INF("\nRD_EYE %s ", l_str);
-
-    							}
-    						}
-    					}
-    				}
-    			}
-    		}
-
-    		delete[] l_str;
-
-    		return rc;
-    	}
-    */  //end of print report test code
-
-    fapi::ReturnCode generic_shmoo::get_margin_dqs_by4(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk;
-        uint32_t l_attr_mss_freq_margin_u32 = 0;
-        uint32_t l_freq=0;
-        uint64_t l_cyc = 1000000000000000ULL;
-        uint8_t l_nibble=0;
-        uint8_t  l_p=0;
-        uint8_t i_rank=0;
-        uint64_t l_factor=0;
-        uint64_t l_factor_ps=1000000000;
-        uint8_t l_SCHMOO_NIBBLES=20;
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        //FAPI_INF("   the factor is % llu ",l_cyc);
-
-        fapi::Target l_target_centaur;
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32);
-        if(rc) return rc;
-        l_freq=l_attr_mss_freq_margin_u32/2;
-        l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data
-        l_factor=l_cyc/128;
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                i_rank=valid_rank1[l_p][l_rnk];
-                //Nibble loop
-
-                for(l_nibble=0; l_nibble<l_SCHMOO_NIBBLES; l_nibble++)
-                {
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-1;
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]+1;
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]=((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble])*l_factor)/l_factor_ps;
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]= ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128);
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble];
-
-                }
-            }
-        }
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::get_margin_dqs_by8(const fapi::Target & i_target)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk;
-        uint32_t l_attr_mss_freq_margin_u32 = 0;
-        uint32_t l_freq=0;
-        uint64_t l_cyc = 1000000000000000ULL;
-        //uint8_t l_dq=0;
-        uint8_t l_nibble=0;
-
-        uint8_t  l_p=0;
-        uint8_t i_rank=0;
-        uint64_t l_factor=0;
-        uint64_t l_factor_ps=1000000000;
-        uint8_t l_SCHMOO_NIBBLES=20;
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=9;
-        }
-
-        //FAPI_INF("   the factor is % llu ",l_cyc);
-
-        fapi::Target l_target_centaur;
-        rc = fapiGetParentChip(i_target, l_target_centaur);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32);
-        if(rc) return rc;
-        l_freq=l_attr_mss_freq_margin_u32/2;
-        l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data
-        l_factor=l_cyc/128;
-        //FAPI_INF("l_factor is % llu ",l_factor);
-
-
-
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            //FAPI_INF("\n Abhijit is here before %d \n",l_p);
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                i_rank=valid_rank1[l_p][l_rnk];
-                //Nibble loop
-                for(l_nibble=0; l_nibble < l_SCHMOO_NIBBLES; l_nibble++)
-                {
-                    if(iv_dmm_type==0)
-                    {
-                        if((l_nibble%2)) {
-                            continue ;
-                        }
-                    }
-
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-1;
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble]+1;
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]=((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.rb_regval[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble])*l_factor)/l_factor_ps;
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]= ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.nom_val[l_nibble]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.lb_regval[l_nibble])*l_factor)/l_factor_ps;//((1/uint32_t_freq*1000000)/128);
-                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_nibble]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble];
-                }
-            }
-
-        }
-        return rc;
-    }
-
-    fapi::ReturnCode generic_shmoo::knob_update_bin_composite(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag)
-    {
-
-        fapi::ReturnCode rc;
-        ecmdDataBufferBase data_buffer_64(64);
-        ecmdDataBufferBase data_buffer_64_1(64);
-        input_type_t l_input_type_e = WR_DQ;
-        uint8_t l_n=0;
-        access_type_t l_access_type_e = WRITE;
-        uint8_t l_dq = 0;
-        uint8_t l_i=0;
-        uint8_t l_flag_p0=0;
-        uint8_t l_flag_p1=0;
-        FAPI_INF("SHMOOING VIA COMPOSITE EYE  FW !!!!");
-        uint8_t l_p=0;
-        uint8_t rank=0;
-        uint8_t l_rank=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        uint8_t l_status=1;
-        uint8_t l_CDarray0[80]= {0};
-        uint8_t l_CDarray1[80]= {0};
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        if(iv_shmoo_type == 2)
-        {
-            l_input_type_e = WR_DQ;
-        }
-        else if(iv_shmoo_type == 8)
-        {
-            l_input_type_e = RD_DQ;
-        }
-        else if(iv_shmoo_type == 4)
-        {
-            l_input_type_e = WR_DQS;
-        }
-        else if(iv_shmoo_type == 16)
-        {
-            l_input_type_e = RD_DQS;
-        }
-
-        rc=do_mcbist_reset(i_target);
-        if(rc)
-        {
-            FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed");
-            return rc;
-        }
-
-
-        //Reset schmoo_error_map
-
-        for(l_p = 0; l_p < MAX_PORT; l_p++) {
-            for(int i=0; i<iv_MAX_RANKS[l_p]; i++) {
-
-                rank=valid_rank1[l_p][i];
-                for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                    schmoo_error_map[l_p][rank][l_n]=0;
-                    binary_done_map[l_p][rank][l_n]=0;
-                }
-            }
-        }
-        int count_cycle = 0;
-
-        if(bound==RIGHT)
-        {
-
-            for(l_p = 0; l_p < MAX_PORT; l_p++) {
-                do {
-
-
-                    l_status=0;
-
-
-                    rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-                    if(rc) return rc;
-
-
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                    {
-                        //l_dq+l_n*4=bit;
-                        //////
-                        rank=valid_rank1[l_p][l_rank];
-                        //printf ("Current Rank : %d",rank );
-
-                        for(l_dq = 0; l_dq < 4; l_dq++) {
-                            for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                                if(binary_done_map[l_p][rank][l_n]==0) {
-                                    l_status=1;
-                                }
-                                l_flag_p0=0;
-                                l_flag_p1=0;
-                                if(l_p == 0) {
-                                    for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-                                        if(l_CDarray0[l_i]==l_dq+l_n*4) {
-                                            schmoo_error_map[l_p][rank][l_n]=1;
-                                            l_flag_p0=1;
-
-                                        }
-                                    }
-                                } else {
-                                    for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                        if(l_CDarray1[l_i]==l_dq+l_n*4) {
-                                            schmoo_error_map[l_p][rank][l_n]=1;
-                                            l_flag_p1=1;
-
-                                        }
-                                    }
-                                }
-
-                                if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4];
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2;
-
-                                    rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]);
-                                    if(rc) return rc;
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-                                    }
-                                    else {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4];
-                                    }
-
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) {
-                                        binary_done_map[l_p][rank][l_n]=1;
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-                                        // printf("\n the right bound for port=%d rank=%d dq=%d is %d \n",l_p,rank,l_dq+l_n*4,FAPI_INF.MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]);
-                                    }
-                                }
-                                else {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4];
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2;
-
-                                    rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]);
-                                    if(rc) return rc;
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-                                    } else {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4];
-                                    }
-                                    if(l_p==0) {
-                                        if(l_flag_p0==1) {
-                                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1;
-                                        }
-                                    }
-                                    else {
-                                        if(l_flag_p1==1) {
-                                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1;
-                                        }
-                                    }
-
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) {
-                                        binary_done_map[l_p][rank][l_n]=1;
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.rb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-
-                                    }
-                                }
-                                //l_dq+l_n*4=l_dq+l_n*4+4;
-                            }
-                        }
-                    }
-
-
-                    rc=do_mcbist_reset(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed");
-                        return rc;
-                    }
-                    rc=do_mcbist_test(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-
-                    rc=check_error_map(i_target,l_p,pass);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-                    //FAPI_INF("\n the status =%d \n",l_status);
-                    count_cycle++;
-                } while(l_status==1);
-            }
-
-            for(l_p = 0; l_p < MAX_PORT; l_p++)
-            {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    //l_dq+l_n*4=bit;
-                    //////
-                    rank=valid_rank1[l_p][l_rank];
-                    for(l_dq = 0; l_dq < 4; l_dq++) {
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq+l_n*4]);
-                            if(rc) return rc;
-                            //l_dq+l_n*4=l_dq+l_n*4+4;
-                        }
-                    }
-                }
-            }
-
-
-
-
-        }
-        count_cycle = 0;
-        if(bound==LEFT)
-        {
-            for(l_p = 0; l_p < MAX_PORT; l_p++)
-            {
-                l_status = 1;
-                //printf("\n +++ Inside LEFT bound -- bin ");
-                while(l_status==1)
-                {
-                    l_status=0;
-
-
-                    rc=mcb_error_map(i_target,mcbist_error_map,l_CDarray0,l_CDarray1,count_bad_dq);
-                    if(rc) return rc;
-
-                    for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++) {
-                        //l_dq+l_n*4=bit;
-                        //////
-                        rank=valid_rank1[l_p][l_rank];
-                        //printf ("Current Rank : %d",rank );
-
-                        for(l_dq = 0; l_dq < 4; l_dq++) {
-                            for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-
-                                if(binary_done_map[l_p][rank][l_n]==0) {
-                                    l_status=1;
-                                }
-
-                                l_flag_p0=0;
-                                l_flag_p1=0;
-                                if(l_p == 0) {
-                                    for(l_i=0; l_i<count_bad_dq[0]; l_i++) {
-                                        if(l_CDarray0[l_i]==l_dq+l_n*4) {
-                                            schmoo_error_map[l_p][rank][l_n]=1;
-                                            l_flag_p0=1;
-
-                                        }
-                                    }
-                                }
-                                else {
-                                    for(l_i=0; l_i<count_bad_dq[1]; l_i++) {
-
-                                        if(l_CDarray1[l_i]==l_dq+l_n*4) {
-                                            schmoo_error_map[l_p][rank][l_n]=1;
-                                            l_flag_p1=1;
-
-                                        }
-                                    }
-                                }
-
-                                if(schmoo_error_map[l_p][rank][l_n]==0) {
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4];
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2;
-
-                                    rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]);
-                                    if(rc) return rc;
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-                                    } else {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4];
-                                    }
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) {
-                                        binary_done_map[l_p][rank][l_n]=1;
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-
-                                    }
-                                } else {
-
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4];
-                                    SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]=(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]+SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4])/2;
-
-                                    rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_val[l_dq+l_n*4]);
-                                    if(rc) return rc;
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]>SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]) {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-                                    } else {
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4]-SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_pass[l_dq+l_n*4];
-                                    }
-
-
-                                    if(l_p==0) {
-                                        if(l_flag_p0==1) {
-                                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1;
-                                        }
-                                    }
-                                    else {
-                                        if(l_flag_p1==1) {
-                                            SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]=1;
-                                        }
-                                    }
-
-                                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.curr_diff[l_dq+l_n*4]<=1) {
-                                        binary_done_map[l_p][rank][l_n]=1;
-                                        SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.lb_regval[l_dq+l_n*4]=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.last_fail[l_dq+l_n*4];
-
-                                    }
-                                }
-                                //l_dq+l_n*4=l_dq+l_n*4+4;
-                            }
-                        }
-                    }
-                    rc=do_mcbist_reset(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_reset failed");
-                        return rc;
-                    }
-                    rc=do_mcbist_test(i_target);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-
-                    rc=check_error_map(i_target,l_p,pass);
-                    if(rc)
-                    {
-                        FAPI_INF("generic_shmoo::find_bound do_mcbist_test failed");
-                        return rc;
-                    }
-
-
-                    //printf("\n the status =%d \n",l_status);
-                    count_cycle++;
-                }
-            }
-
-            for(l_p = 0; l_p < MAX_PORT; l_p++)
-            {
-                for (l_rank=0; l_rank<iv_MAX_RANKS[l_p]; l_rank++)
-                {
-                    //l_dq+l_n*4=bit;
-                    //////
-                    rank=valid_rank1[l_p][l_rank];
-                    //printf("Valid rank of %d %d %d %d %d %d %d %d",valid_rank1[0],valid_rank1[1],valid_rank1[2],valid_rank1[3],valid_rank1[4],valid_rank1[5],valid_rank1[6],valid_rank1[7]);
-                    for(l_dq = 0; l_dq < 4; l_dq++) {
-                        for (l_n=0; l_n<l_SCHMOO_NIBBLES; l_n++) {
-                            rc=mss_access_delay_reg_schmoo(i_target,l_access_type_e,l_p,rank,l_input_type_e,l_dq+l_n*4,0,SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[rank].K.nom_val[l_dq+l_n*4]);
-                            if(rc) return rc;
-                            //l_dq+l_n*4=l_dq+l_n*4+4;
-                        }
-                    }
-                }
-            }
-
-        } // End of LEFT
-
-
-        return rc;
-
-
-    }
-
-    fapi::ReturnCode generic_shmoo::get_nibble_pda(const fapi::Target & i_target,uint32_t pda_nibble_table[2][2][16][2])
-    {
-        fapi::ReturnCode rc;
-        uint8_t i_rank = 0;
-
-        for (int l_p=0; l_p < MAX_PORT; l_p++) {
-            for (int l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                ////
-                i_rank=valid_rank1[l_p][l_rnk];
-                for(int l_dq = 0; l_dq < 4; l_dq++) {
-                    for (int l_n=0; l_n < 16; l_n++) {
-                        // do necessary
-                        //if(pda_nibble_table[l_p][i_rank][l_n][1] < FAPI_INF.MBA.P[l_p].S[i_rank].K.total_margin[l_dq+l_n*4])
-                        {
-                            pda_nibble_table[l_p][i_rank][l_n][0] = iv_vref_mul;
-                            pda_nibble_table[l_p][i_rank][l_n][1] = SHMOO[iv_DQS_ON].MBA.P[l_p].S[i_rank].K.total_margin[l_dq+l_n*4];
-                        }
-                        //FAPI_INF("\n Port %d Rank:%d Pda_Nibble: %d  V-ref:%d  Margin:%d",l_p,i_rank,l_n,pda_nibble_table[l_p][i_rank][l_n][0],pda_nibble_table[l_p][i_rank][l_n][1]);
-                    }
-                }
-
-            }
-        }
-        return rc;
-    }
-    /*------------------------------------------------------------------------------
-    * Function: get_min_margin
-    * Description  : This function is used to get the minimum margin of all the schmoo margins
-    *
-    * Parameters: Target:MBA,right minimum margin , left minimum margin, pass fail
-    * ---------------------------------------------------------------------------*/
-
-    fapi::ReturnCode generic_shmoo::get_min_margin2(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk,l_byte,l_nibble,l_bit,i_rank;
-        uint16_t l_temp_right=4800;
-        uint16_t l_temp_left=4800;
-        uint8_t l_dq=0;
-        uint8_t l_p=0;
-        FAPI_INF("In GET_MIN_MARGIN - iv_shmoo_type = %d",iv_shmoo_type);
-
-        for (l_p = 0; l_p < 2; l_p++)
-        {
-            for (l_rnk = 0; l_rnk < iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-
-                i_rank = valid_rank1[l_p][l_rnk];
-                ////
-                if (rc) return rc;
-                for (l_byte = 0; l_byte < 10; l_byte++)
-                {
-                    //Nibble loop
-                    for (l_nibble = 0; l_nibble < 2; l_nibble++)
-                    {
-                        //l_dq=8 * l_byte + 4 * l_nibble;
-
-
-                        for (l_bit = 0; l_bit < 4; l_bit++)
-                        {
-                            l_dq = 8 * l_byte + 4 * l_nibble + l_bit;
-                            if ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq]
-                                    < l_temp_right) && (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq] != 0 ))
-                            {
-                                l_temp_right
-                                    = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_dq];
-                            }
-                            if ((SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq]
-                                    < l_temp_left) && (SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq] !=0))
-                            {
-                                l_temp_left
-                                    = SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_dq];
-                            }
-                        }
-                    }
-                }
-            }
-        }
-
-
-
-        if(iv_shmoo_type==8)
-        {
-            *o_right_min_margin=l_temp_left;
-            *o_left_min_margin=l_temp_right;
-        } else {
-            *o_right_min_margin=l_temp_right;
-            *o_left_min_margin=l_temp_left;
-        }
-        return rc;
-    }
-
-
-    fapi::ReturnCode generic_shmoo::get_min_margin_dqs(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin)
-    {
-        fapi::ReturnCode rc;
-        uint8_t l_rnk,l_nibble,i_rank;
-        uint16_t l_temp_right=4800;
-        uint16_t l_temp_left=4800;
-        uint8_t l_p=0;
-        uint8_t l_attr_eff_dram_width_u8=0;
-        uint8_t l_SCHMOO_NIBBLES=20;
-        uint8_t l_by8_dqs=0;
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8);
-        if(rc) return rc;
-
-        if(iv_dmm_type==1)
-        {
-            l_SCHMOO_NIBBLES=18;
-        }
-
-        if(l_attr_eff_dram_width_u8 == 8) {
-            l_SCHMOO_NIBBLES=10;
-            if(iv_dmm_type==1)
-            {
-                l_SCHMOO_NIBBLES=9;
-            }
-        }
-        iv_shmoo_type=4;
-
-        for (l_p=0; l_p<MAX_PORT; l_p++) {
-            for (l_rnk=0; l_rnk<iv_MAX_RANKS[l_p]; l_rnk++)
-            {
-                i_rank=valid_rank1[l_p][l_rnk];
-
-
-                for(l_nibble=0; l_nibble< l_SCHMOO_NIBBLES; l_nibble++)
-                {
-
-                    l_by8_dqs=l_nibble;
-                    if(iv_dmm_type==0)
-                    {
-                        if(l_attr_eff_dram_width_u8 == 8)
-                        {
-                            l_nibble=l_nibble*2;
-                        }
-                    }
-
-                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble]<l_temp_right)
-                    {
-                        l_temp_right=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.right_margin_val[l_nibble];
-                    }
-                    if(SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble]<l_temp_left)
-                    {
-                        l_temp_left=SHMOO[iv_SHMOO_ON].MBA.P[l_p].S[i_rank].K.left_margin_val[l_nibble];
-                    }
-
-                    if(iv_dmm_type==0)
-                    {
-                        if(l_attr_eff_dram_width_u8 == 8)
-                        {
-                            l_nibble=l_by8_dqs;
-                        }
-                    }
-                }
-            }
-        }
-
-
-        // hacked for now till schmoo is running
-        if(iv_shmoo_type==8)
-        {
-            *o_right_min_margin=l_temp_left;
-            *o_left_min_margin=l_temp_right;
-        } else {
-            *o_right_min_margin=l_temp_right;
-            *o_left_min_margin=l_temp_left;
-        }
-        return rc;
-    }
-    ///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
-
-    fapi::ReturnCode generic_shmoo::schmoo_setup_mcb(const fapi::Target & i_target)
-    {
-
-        struct Subtest_info l_sub_info[30];
-        uint32_t l_pattern = 0;
-        uint32_t l_testtype = 0;
-        mcbist_byte_mask i_mcbbytemask1;
-        char l_str_cust_addr[] = "ba0,ba1,mr3,mr2,mr1,mr0,ba2,ba3,cl2,cl3,cl4,cl5,cl6,cl7,cl8,cl9,cl11,cl13,r0,r1,r2,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,sl2,sl1,sl0";
-
-        i_mcbbytemask1 = UNMASK_ALL;
-
-        fapi::ReturnCode rc;
-
-        l_pattern = iv_pattern;
-        l_testtype = iv_test_type;
-
-        if (iv_shmoo_type == 16)
-        {
-            FAPI_INF("%s:\n Read DQS is running \n", i_target.toEcmdString());
-            if (iv_SHMOO_ON == 1)
-            {
-                l_testtype = 3;
-            }
-            if (iv_SHMOO_ON == 2)
-            {
-                l_testtype = 4;
-            }
-        }
-        //send shmoo mode to vary the address range
-        if (iv_shmoo_type == 16)
-        {
-            rc = FAPI_ATTR_SET(ATTR_MCBIST_PATTERN, &i_target, l_pattern);
-            if (rc) return rc;//-----------i_mcbpatt------->run
-            rc = FAPI_ATTR_SET(ATTR_MCBIST_TEST_TYPE, &i_target, l_testtype);
-            if (rc) return rc;//---------i_mcbtest------->run
-        }
-
-        rc = setup_mcbist(i_target, i_mcbbytemask1, 0,0x0ull ,l_sub_info,l_str_cust_addr);
-        if (rc) return rc;
-
-        return rc;
-    }
-
-}//Extern C
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
deleted file mode 100644
index f18bb550d..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H
+++ /dev/null
@@ -1,232 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_generic_shmoo.H,v 1.29 2015/08/07 11:28:52 sasethur Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : mss_generic_shmoo.H
-// *! TITLE                : MSS Generic Shmoo 
-// *! DESCRIPTION          : Memory Subsystem Generic Shmoo -- abstraction for HB
-// *! CONTEXT              : To make all shmoos share a common abstraction layer
-// *!
-// *! OWNER  NAME          : Preetham Hosmane         Email:  preeragh@in.ibm.com
-// *! BACKUP NAME          : Saravanan Sethuraman  
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-// 	 1.29  |preeragh|30/07/15| Optimized for FW Linear/Composite/Bin
-//   1.28  |preeragh|06/22/14|DDR4 Mods
-//   1.27  |mjjones |01/24/14|RAS Review Updates
-//   1.26  |abhijit |01/17/14|enabled one more function
-//   1.24  |abhijit |12/17/13|modified as per to support firmware 
-//   1.22  |abhijit |8/08/13 |added binary schmoo functions 
-//   1.20  |abhijit |7/17/13 |added functions for read dqs 
-//   1.11  |abhijit |1/21/13 |fixed constructor definition  
-//   1.9   |abhijit |06/12/12|fixed fw review comments 
-//   1.4   |abhijit |09/27/11|made changes according to new design
-//   1.5   |abhijit |10/29/12|made changes after target and returncode 
-//   1.6   |abhijit |10/29/12|made changes  
-//   1.7   |abhijit |11/15/12|made changes for fw review comments 
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-#ifndef generic_shmoo_H
-#define generic_shmoo_H
-
-using namespace fapi;
-//! Globals
-#define SHMOO_DEBUG 0
-#define SHMOO_DEBUG2 0
-#include "mss_shmoo_common.H"
-#include "mss_mcbist.H"
-
-//! MSS Generic Shmoo Class.. Inherits from PHY access class and the knob abstraction 
-class generic_shmoo
-{
-private:
-
-    //! MBS Config : Port + Socket + Knobs
-    struct SHMOO_SCENARIO
-    {
-        struct MBS_CONFIG
-        {
-            struct PORT
-            {
-                struct RANK
-                {
-                    shmoo_knob_data_t K; // Set of knobs used by this shmoo
-                }S[MAX_RANK];       //Max Rank are 8
-            }P[MAX_PORT];			// Max Port 2
-        }MBA;
-        shmoo_knob_config_t static_knob; // Static info regarding the knob
-    }SHMOO[MAX_SHMOO]; // Denote max shmoo scenarios we have; Have 2; so that one for WR/RD and other Clock.
-
-    //! Result Data
-    uint8_t convergence_gap;
-    shmoo_algorithm_t algorithm;
-    shmoo_mode mcbist_mode;
-    uint8_t mcbist_error_map[MAX_PORT][MAX_RANK][MAX_BYTE][MAX_NIBBLES];    //MAX byte is 10; Max Nibble are 2; 
-    uint8_t count_bad_dq[MAX_PORT];
-    uint8_t schmoo_error_map[MAX_PORT][MAX_RANK][20];
-    uint8_t binary_done_map[MAX_PORT][MAX_RANK][20];
-    shmoo_type_t shmoo_mask;
-    uint8_t iv_addr;
-    uint8_t iv_MAX_RANKS[MAX_PORT];
-    uint8_t iv_MAX_BYTES;
-    uint32_t iv_pattern;
-    uint32_t iv_test_type;
-    uint8_t iv_dmm_type;
-    uint8_t iv_SHMOO_ON;
-	uint8_t iv_DQS_ON;
-    uint8_t iv_shmoo_type;
-    uint16_t iv_shmoo_param;
-    uint16_t iv_binary_diff;
-    uint16_t iv_vref_mul;
-    uint8_t valid_rank[MAX_RANK];
-	uint8_t valid_rank1[MAX_PORT][MAX_RANK];
-
-public:
-
-    enum bound_t {LEFT, RIGHT};
-
-    generic_shmoo(uint8_t iv_addr,shmoo_type_t shmoo_mask,shmoo_algorithm_t shmoo_algorithm);// Constructor
-    generic_shmoo(){};
-    ~generic_shmoo(){};
-
-    //initialize multi dim arrays to known value
-    void init_multi_array(uint16_t (&array)[MAX_DQ],
-                          uint16_t init_val);
-
-    // Read in all the Nominal values of the relevant knobs
-    fapi::ReturnCode get_all_noms(const fapi::Target & i_target);
-    
-    fapi::ReturnCode set_all_binary(const fapi::Target & i_target,
-                                    bound_t bound);
-
-    // Read in all the Nominal values of the relevant knobs
-    fapi::ReturnCode get_all_noms_dqs(const fapi::Target & i_target);
-
-    // generic Right bound
-    fapi::ReturnCode find_bound(const fapi::Target & i_target,bound_t);
-
-    // Increment or decrement the knob
-    fapi::ReturnCode knob_update(const fapi::Target & i_target,
-                                 bound_t bound,
-                                 uint8_t scenario,
-                                 uint8_t bit,
-                                 uint8_t pass,
-                                 bool &flag);
-
-    fapi::ReturnCode knob_update_bin(const fapi::Target & i_target,
-                                     bound_t bound,
-                                     uint8_t scenario,
-                                     uint8_t bit,
-                                     uint8_t pass,
-                                     bool &flag);
-
-    fapi::ReturnCode knob_update_dqs_by8(const fapi::Target & i_target,
-                                         bound_t bound,
-                                         uint8_t scenario,
-                                         uint8_t bit,
-                                         uint8_t pass,
-                                         bool &flag);
-
-    fapi::ReturnCode knob_update_dqs_by4(const fapi::Target & i_target,
-                                         bound_t bound,
-                                         uint8_t scenario,
-                                         uint8_t bit,
-                                         uint8_t pass,
-                                         bool &flag);
-
-    // Print Shmoo report to  STDOUT
-    fapi::ReturnCode print_report(const fapi::Target & i_target);
-
-    fapi::ReturnCode print_report_dqs(const fapi::Target & i_target);
-	fapi::ReturnCode print_report_dqs2(const fapi::Target & i_target);
-
-    fapi::ReturnCode get_margin(const fapi::Target & i_target);
-	fapi::ReturnCode get_margin2(const fapi::Target & i_target);
-
-    fapi::ReturnCode get_margin_dqs_by8(const fapi::Target & i_target);
-
-    fapi::ReturnCode get_margin_dqs_by4(const fapi::Target & i_target);
-
-    fapi::ReturnCode get_min_margin(const fapi::Target & i_target,
-                                    uint32_t *o_right_min_margin,
-                                    uint32_t *o_left_min_margin);
-	fapi::ReturnCode get_min_margin2(const fapi::Target & i_target,
-                                    uint32_t *o_right_min_margin,
-                                    uint32_t *o_left_min_margin);
-
-    fapi::ReturnCode get_min_margin_dqs(const fapi::Target & i_target,
-                                        uint32_t *o_right_min_margin,
-                                        uint32_t *o_left_min_margin);
-
-    fapi::ReturnCode do_mcbist_test(const fapi::Target & i_target);
-
-    fapi::ReturnCode do_mcbist_reset(const fapi::Target & i_target);
-
-    fapi::ReturnCode check_error_map(const fapi::Target & i_target,
-                                     uint8_t port,uint8_t &pass);
-	fapi::ReturnCode check_error_map2(const fapi::Target & i_target,
-                                     uint8_t port,uint8_t &pass);
-
-    fapi::ReturnCode sanity_check(const fapi::Target & i_target);
-
-    fapi::ReturnCode schmoo_setup_mcb(const fapi::Target & i_target);
-
-    fapi::ReturnCode knob_update_dqs_by8_isdimm(const fapi::Target & i_target,
-                                                bound_t bound,
-                                                uint8_t scenario,
-                                                uint8_t bit,
-                                                uint8_t pass,
-                                                bool &flag);
-
-    fapi::ReturnCode knob_update_dqs_by4_isdimm(const fapi::Target & i_target,
-                                                bound_t bound,
-                                                uint8_t scenario,
-                                                uint8_t bit,
-                                                uint8_t pass,
-                                                bool &flag);
-
-    fapi::ReturnCode run(const fapi::Target & i_target,
-                         uint32_t *right_min_margin,
-                         uint32_t *left_min_margin,
-                         uint32_t i_vref_mul);
-
-    fapi::ReturnCode shmoo_save_rest(const fapi::Target & i_target,
-                                     uint64_t i_content_array[],
-                                     uint8_t i_mode);
-	fapi::ReturnCode get_nibble_pda(const fapi::Target & i_target,uint32_t pda_nibble_table[2][2][16][2]);
-	fapi::ReturnCode knob_update_bin_composite(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t bit,uint8_t pass,bool &flag);
-	fapi::ReturnCode print_report2(const fapi::Target & i_target);
-
-};
-#endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C
deleted file mode 100755
index c70653e08..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C
+++ /dev/null
@@ -1,1145 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist.C,v 1.57 2015/08/26 16:17:41 sasethur Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : mss_mcbist.C
-// *! TITLE                : 
-// *! DESCRIPTION          : MCBIST Procedures
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Hosmane, Preetham             Email: preeragh@in.ibm.com
-// *! BACKUP               : Sethuraman, Saravanan         Email: saravanans@in.ibm.com
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.57  |preeragh|08/25/15| FW Review Comments  MPR
-//   1.53  |preeragh|06/22/15| Added MPR
-//   1.52  |sglancy |02/16/15| Merged in FW comments with lab needs
-//   1.51  |sglancy |02/09/15| Fixed FW comments and adjusted whitespace
-//   1.50  |preeragh|01/16/15| Fixed FW comments
-//   1.48  |preeragh|01/05/15| Added FW workaround for drand
-//   1.48  |preeragh|12/16/14| Revert back changes. v.1.46
-//   1.47  |rwheeler|11/19/14|option to pass in rotate data seed
-//   1.46  |mjjones |01/20/14|RAS Review Updates
-//   1.45  |aditya  |12/17/13|Added Simple_fix_rf
-//   1.43  |aditya  |10/05/13|Updated fw comments
-//   1.42  |aditya  |09/18/13|Updated Call for functions
-//   1.41  |aditya  |08/10/13|Minor Fix for Hostboot compile
-//   1.40  |aditya  |06/11/13|Added attributes ATTR_MCBIST_PRINTING_DISABLE and ATTR_MCBIST_DATA_ENABLE
-//   1.39  |aditya  |05/22/13|updated parameters for Subtest Printing
-//   1.38  |aditya  |05/14/13|updated parameters for cfg_mcb_dgen
-//   1.37  |aditya  |02/19/13|updated testtypes
-//   1.34  |aditya  |02/13/13|updated testtypes
-//   1.33  |aditya  |02/12/13|updated testtypes
-//   1.32  |aditya  |02/11/13|updated testtypes  
-//   1.31  |aditya  |02/06/13|Updated SIMPLE_RAND test_type
-//   1.30  |aditya  |01/30/13|Updated fw comments
-//   1.29  |aditya  |01/11/13|Updated  cfg_mcb_dgen function
-//   1.28  |aditya  |01/11/13|Updated  cfg_mcb_dgen function
-//   1.27  |aditya  |01/11/13|Updated  cfg_mcb_dgen function
-//   1.26  |aditya  |01/07/13|Updated Review Comments
-//   1.25  |aditya  |01/03/13| Updated FW Comments 
-//   1.23  |aditya  |12/18/12| Updated Review Comments 
-//   1.22  |aditya  |12/14/12| Updated FW review comments   
-//   1.22  |aditya  |12/6/12 | Updated Review Comments
-//   1.21  |aditya  |11/15/12| Updated for FIRMWARE REVIEW COMMENTS
-//   1.20  |aditya  |10/29/12| updated fw review comments 
-//   1.18  |aditya  |10/29/12| Updated from ReturnCode to fapi::ReturnCode and Target to const fapi::Target &  
-//   1.17  |aditya  |10/18/12| Replaced insertFromHexRight by SetDoubleWord   
-//   1.16  |aditya  |10/17/12| updated code to be compatible with ecmd 13 release
-//   1.15  |aditya  |10/01/12| updated fw review comments, datapattern, testtype, addressing	
-//   1.14  |mwuu    |07/17/12| updated dram_width tests to new definition
-//   1.13  |bellows |07/16/12| added in Id tag
-//   1.10  |gaushard|04/26/12| Added ONE_SHMOO parameter
-//   1.9   |gaushard|03/26/12| Updated start_mcbist 
-//   1.8   |gaushard|03/26/12| Removed Extra Comments/Codes
-//   1.7   |gaushard|03/26/12| Added new shmoo modes
-//   1.6   |sasethur|03/23/12| Corrected Warning Messages 
-//   1.5   |sasethur|03/23/12| Corrected Warning messages
-//   1.4   |gaushard|03/22/12| Added Address generation
-//   1.3   |gaushard|02/29/12| Added rc_num for Buffer operation
-//   1.2   |gaushard|02/14/12| Added rc_buff for buffer access
-//   1.1   |gaushard|02/13/12| Updated scom addresses
-//   1.0   |gaushard|01/19/12| Initial Version
-//------------------------------------------------------------------------------
-
-#include "mss_mcbist.H"
-extern "C"
-{
-using namespace fapi;
-
-const uint8_t MAX_BYTE = 10;
-//*****************************************************************/
-// Funtion name : cfg_mcb_test_mem
-// Description  : This function executes different MCBIST subtests
-// Input Parameters :
-//     const fapi::Target & i_target_mba      Centaur.mba
-//     mcbist_test_mem i_test_type      Subtest Type
-//****************************************************************/
-
-fapi::ReturnCode cfg_mcb_test_mem(const fapi::Target & i_target_mba,
-                                  mcbist_test_mem i_test_type,
-                                  struct Subtest_info l_sub_info[30])
-{
-    fapi::ReturnCode rc;
-    uint8_t l_print = 0;
-    uint32_t l_mcbtest;
-    uint8_t l_index, l_data_flag, l_random_flag, l_count, l_data_attr;
-    l_index = 0;
-    l_data_flag = 0;
-    l_random_flag = 0;
-    l_data_attr = 0;
-    uint8_t test_array_count[44] = { 0, 2, 2, 1, 1, 1, 6, 6, 30, 30,
-                                     2, 7, 4, 2, 1, 5, 4, 2, 1, 1,
-                                     3, 1, 1, 4, 2, 1, 1, 1, 1, 10,
-                                     0, 5, 3, 3, 3, 3, 9, 4, 30, 1,
-                                     2, 2, 3, 3 };
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, l_print);
-    if (rc) return rc;
-    if (l_print == 0)
-    {
-        FAPI_INF("Function Name: cfg_mcb_test_mem");
-        FAPI_INF("Start Time");
-    }
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, l_mcbtest);
-    if (rc) return rc;
-
-    if (l_print == 0)
-    {
-        FAPI_INF("Function - cfg_mcb_test_mem");
-    }
-
-    uint8_t l_done_bit = 0;
-    rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-    if (rc) return rc;
-
-    if (i_test_type == CENSHMOO)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : CENSHMOO ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 1, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 1, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == MEMWRITE)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : MEMWRITE ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == MEMREAD)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : MEMREAD ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 0, 0, 0, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == SIMPLE_FIX)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : SIMPLE_FIX ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info);
-        if (rc) return rc;
-
-        l_done_bit = 1;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9,
-                                RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info);
-        if (rc)
-            return rc;
-    }
-    else if (i_test_type == SIMPLE_RAND)
-    {
-        if (l_print == 0)
-            FAPI_INF("Current MCBIST TESTTYPE : SIMPLE_RAND ");
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                WR, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info);
-        if (rc) return rc;
-
-        l_done_bit = 1;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 1, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, RF, DATA_RF, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9,
-                                RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == WR_ONLY)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : WR_ONLY ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info);
-        if (rc) return rc;
-
-        l_done_bit = 1;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9,
-                                RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == W_ONLY)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : W_ONLY ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info);
-        if (rc) return rc;
-
-        l_done_bit = 1;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, FIX, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4,
-                                l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9,
-                                RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == R_ONLY)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Current MCBIST TESTTYPE : R_ONLY ");
-        }
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info);
-        if (rc) return rc;
-
-        l_done_bit = 1;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                GOTO, 0, SF, FIX, 0, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, RF, FIX, 0, DEFAULT, FIX_ADDR, 2, 2, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                OPER_RAND, 0, RF, FIX, 1, DEFAULT, FIX_ADDR, 3, 3, 4, l_sub_info);
-        if (rc) return rc;
-
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR1Q_0x030106a9,
-                                RW, 4, RF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 4, 4, l_sub_info);
-        if (rc) return rc;
-    }
-    else if (i_test_type == SIMPLE_FIX_RF)
-    {
-        FAPI_DBG("%s:Current MCBIST TESTTYPE : SIMPLE_FIX_RF ",
-                 i_target_mba.toEcmdString());
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                W, 0, SF, DATA_RF, 0, DEFAULT, FIX_ADDR, 0, 0, 4, l_sub_info);
-        if (rc) return rc;
-        rc = mcb_write_test_mem(i_target_mba, MBA01_MCBIST_MCBMR0Q_0x030106a8,
-                                R, 0, SF, DATA_RF, 1, DEFAULT, FIX_ADDR, 1, 1, 4, l_sub_info);
-        if (rc) return rc;
-        l_done_bit = 1;
-        rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-        if (rc) return rc;
-    }
-    else
-    {
-        FAPI_ERR("Invalid MCBIST test type (%d)! cfg_mcb_test_mem Function",
-                 i_test_type);
-        const mcbist_test_mem & TEST_TYPE_PARAM = i_test_type;
-        FAPI_SET_HWP_ERROR(rc, RC_CFG_MCB_TEST_MEM_INVALID_INPUT);
-        return rc;
-    }
-
-    if (l_print == 0)
-    {
-        FAPI_INF("Function Name: cfg_mcb_test_mem");
-        FAPI_INF("Stop Time");
-    }
-
-    l_count = test_array_count[l_mcbtest];
-    for (l_index = 0; l_index < l_count; l_index++)
-    {
-        if (l_sub_info[l_index].l_fixed_data_enable == 1)
-        {
-            l_data_flag = 1;
-        }
-        if (l_sub_info[l_index].l_random_data_enable == 1)
-        {
-            l_random_flag = 1;
-        }
-    }
-    if ((l_data_flag == 0) && (l_random_flag == 1))
-    {
-        l_data_attr = 1;
-    }
-    else if ((l_data_flag == 1) && (l_random_flag == 0))
-    {
-        l_data_attr = 2;
-    }
-    else if ((l_data_flag == 1) && (l_random_flag == 1))
-    {
-        l_data_attr = 3;
-    }
-    else
-    {
-        l_data_attr = 3;
-    }
-    rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, l_data_attr);
-    if (rc) return rc;
-
-    return rc;
-
-}
-
-//*****************************************************************/
-// Funtion name : cfg_mcb_dgen
-// Description  : This function writes data patterns based on i_datamode passed
-// Input Parameters :
-//     const fapi::Target & i_target_mba      Centaur.mba
-//     mcbist_data_gen i_datamode       MCBIST Data mode 
-//     uint8_t i_mcbrotate              Provides the number of bit to shift per burst
-//     uint64_t i_mcbrotdata            Provides the data seed to shift per burst
-//****************************************************************/
-fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba,
-                              mcbist_data_gen i_datamode,
-                              uint8_t i_mcbrotate,
-                              uint64_t i_mcbrotdata)
-{
-    uint8_t l_print = 0;
-
-    uint8_t l_data_attr, l_random_flag, l_data_flag;
-    l_data_flag = 1;
-    l_random_flag = 1;
-    l_data_attr = 3;
-    uint8_t l_seed_choice;
-    uint32_t i_seed;
-    i_seed = 0x20;
-    l_seed_choice = 1;
-    ecmdDataBufferBase l_data_buffer_64(64);
-    ecmdDataBufferBase l_var_data_buffer_64(64);
-    ecmdDataBufferBase l_var1_data_buffer_64(64);
-    ecmdDataBufferBase l_spare_data_buffer_64(64);
-    ecmdDataBufferBase l_data_buffer_32(32);
-    ecmdDataBufferBase l_data_buffer_16(16);
-    ecmdDataBufferBase l_data_buffer_4(4);
-    ecmdDataBufferBase l_data_buffer1_4(4);
-    uint64_t l_var = 0x0000000000000000ull;
-    uint64_t l_var1 = 0x0000000000000000ull;
-    uint64_t l_spare = 0x0000000000000000ull;
-    uint8_t l_rotnum = 0;
-    uint32_t l_mba01_mcb_pseudo_random[MAX_BYTE] = {
-        MBA01_MCBIST_MCBFD0Q_0x030106be, MBA01_MCBIST_MCBFD1Q_0x030106bf,
-        MBA01_MCBIST_MCBFD2Q_0x030106c0, MBA01_MCBIST_MCBFD3Q_0x030106c1,
-        MBA01_MCBIST_MCBFD4Q_0x030106c2, MBA01_MCBIST_MCBFD5Q_0x030106c3,
-        MBA01_MCBIST_MCBFD6Q_0x030106c4, MBA01_MCBIST_MCBFD7Q_0x030106c5,
-        MBA01_MCBIST_MCBFDQ_0x030106c6, MBA01_MCBIST_MCBFDSPQ_0x030106c7 };
-    uint32_t l_mba01_mcb_random[MAX_BYTE] = { MBA01_MCBIST_MCBRDS0Q_0x030106b2,
-        MBA01_MCBIST_MCBRDS1Q_0x030106b3, MBA01_MCBIST_MCBRDS2Q_0x030106b4,
-        MBA01_MCBIST_MCBRDS3Q_0x030106b5, MBA01_MCBIST_MCBRDS4Q_0x030106b6,
-        MBA01_MCBIST_MCBRDS5Q_0x030106b7, MBA01_MCBIST_MCBRDS6Q_0x030106b8,
-        MBA01_MCBIST_MCBRDS7Q_0x030106b9, MBA01_MCBIST_MCBRDS8Q_0x030106ba,
-        0x030106bb };
-    uint32_t l_mbs01_mcb_random[MAX_BYTE] = { 0x02011675, 0x02011676,
-        0x02011677, 0x02011678, 0x02011679, 0x0201167a, 0x0201167b, 0x0201167c,
-        0x0201167d, 0x0201167e };
-    uint32_t l_mbs23_mcb_random[MAX_BYTE] = { 0x02011775, 0x02011776,
-        0x02011777, 0x02011778, 0x02011779, 0x0201177a, 0x0201177b, 0x0201177c,
-        0x0201177d, 0x0201177e };
-
-    uint8_t l_index, l_index1 = 0;
-    uint32_t l_rand_32 = 0;
-    uint32_t l_rand_8 = 0;
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    if (l_print == 0)
-    {
-        FAPI_INF("Function Name: cfg_mcb_dgen");
-        FAPI_INF(" Data mode is %d ", i_datamode);
-    }
-    uint8_t l_mbaPosition = 0;
-
-    fapi::Target i_target_centaur;
-    rc = fapiGetParentChip(i_target_mba, i_target_centaur);
-    if (rc)
-    {
-        if (l_print == 0)
-        {
-            FAPI_INF("Error in getting parent chip!");
-        }
-        return rc;
-    }
-
-    if (l_print == 0)
-    {
-        FAPI_INF("Function cfg_mcb_dgen");
-    }
-    //Read MBA position attribute 0 - MBA01 1 - MBA23
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition);
-    if (rc)
-    {
-        FAPI_ERR("Error getting MBA position");
-        return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, l_print);
-    if (rc) return rc;
-
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, l_data_attr);
-    if (rc) return rc;
-
-    if (l_data_attr == 1)
-    {
-        l_data_flag = 0;
-        l_random_flag = 1;
-    }
-    else if (l_data_attr == 2)
-    {
-        l_data_flag = 1;
-        l_random_flag = 0;
-    }
-    else if (l_data_attr == 3)
-    {
-        l_data_flag = 1;
-        l_random_flag = 1;
-    }
-    else
-    {
-        l_data_flag = 1;
-        l_random_flag = 1;
-    }
-
-    if (l_data_flag == 1)
-    {
-        if (i_datamode == MCBIST_2D_CUP_PAT5)
-        {
-            l_var = 0xFFFF0000FFFF0000ull;
-            l_var1 = 0x0000FFFF0000FFFFull;
-            l_spare = 0xFF00FF00FF00FF00ull;
-
-            rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64);
-            if (rc) return rc;
-        }
-        else if (i_datamode == MCBIST_2D_CUP_PAT8)
-        {
-            l_var = 0xFFFFFFFFFFFFFFFFull;
-            l_var1 = 0x0000000000000000ull;
-            l_spare = 0xFFFF0000FFFF0000ull;
-            rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64);
-            if (rc) return rc;
-        }
-        else if (i_datamode == ABLE_FIVE)
-        {
-            l_var = 0xA5A5A5A5A5A5A5A5ull;
-            l_var1 = 0x5A5A5A5A5A5A5A5Aull;
-            l_spare = 0xA55AA55AA55AA55Aull;
-
-            rc_num = l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            rc_num |= l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64);
-            if (rc) return rc;
-        }
-		else if(i_datamode == MPR)
-		{
-			l_var = 0x0000000000000000ull;
-			l_var1 =0xFFFFFFFFFFFFFFFFull;
-			l_spare = 0x00FF00FF00FF00FFull;
-			
-			rc_num = l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            rc_num |= l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64); if(rc) return rc;
-		 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64); if(rc) return rc;
-		 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64); if(rc) return rc;
-	  
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64); if(rc) return rc;
-		 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64); if(rc) return rc;
-		 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64); if(rc) return rc;
- 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64); if(rc) return rc;	
-		 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64); if(rc) return rc;
-	 
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6 , l_spare_data_buffer_64); if(rc) return rc;
-		
-		rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7 , l_spare_data_buffer_64); if(rc) return rc;
-		}
-		else if ((i_datamode == DATA_GEN_DELTA_I) ||
-                 (i_datamode == MCBIST_2D_CUP_PAT0))
-        {
-            l_var = 0xFFFFFFFFFFFFFFFFull;
-            l_var1 = 0x0000000000000000ull;
-            l_spare = 0xFF00FF00FF00FF00ull;
-            rc_num = l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            rc_num |= l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD0Q_0x030106be, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD1Q_0x030106bf, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD2Q_0x030106c0, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD3Q_0x030106c1, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD4Q_0x030106c2, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD5Q_0x030106c3, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD6Q_0x030106c4, l_var_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFD7Q_0x030106c5, l_var1_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDQ_0x030106c6, l_spare_data_buffer_64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBFDSPQ_0x030106c7, l_spare_data_buffer_64);
-            if (rc) return rc;
-        }
-        else if (i_datamode == PSEUDORANDOM)
-        {
-            l_rand_32 = 0xFFFFFFFF;//Hard Coded Temporary Fix till random function is fixed
-            // srand(2);
-            if (l_seed_choice == 1)
-            {
-                if (i_seed == 0)
-                {
-                    i_seed = 0xFFFFFFFF;
-                }
-                l_rand_32 = i_seed;
-            }
-
-            for (l_index = 0; l_index < (MAX_BYTE); l_index++)
-            {
-                //l_rand_32 = rand();
-
-                rc_num |= l_data_buffer_32.insertFromRight(l_rand_32, 0, 32);
-                rc_num |= l_data_buffer_64.insert(l_data_buffer_32, 0, 32, 0);
-                //l_rand_32 = rand();
-                rc_num |= l_data_buffer_32.insertFromRight(l_rand_32, 0, 32);
-                rc_num |= l_data_buffer_64.insert(l_data_buffer_32, 32, 32, 0);
-                if (rc_num)
-                {
-                    FAPI_ERR("cfg_mcb_dgen:");
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                }
-                rc = fapiPutScom(i_target_mba, l_mba01_mcb_pseudo_random[l_index],
-                                 l_data_buffer_64);
-                if (rc) return rc;
-            }
-        }
-        else
-        {
-            FAPI_ERR("cfg_mcb_dgen: Invalid data mode (%d)", i_datamode);
-            const mcbist_data_gen & DATA_MODE_PARAM = i_datamode;
-            FAPI_SET_HWP_ERROR(rc, RC_CFG_MCB_DGEN_INVALID_INPUT);
-            return rc;
-        }
-
-        if (i_datamode == MCBIST_2D_CUP_PAT5)
-        {
-            l_var = 0xFFFF0000FFFF0000ull;
-            l_var1 = 0x0000FFFF0000FFFFull;
-            l_spare = 0xFF00FF00FF00FF00ull;
-
-            rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            if (l_mbaPosition == 0)
-            {
-                //Writing MBS 01 pattern registers for comparison mode
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-            else if (l_mbaPosition == 1)
-            {
-                //Writing MBS 23 pattern registers for comparison mode
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-        }
-        else if (i_datamode == MCBIST_2D_CUP_PAT8)
-        {
-            l_var = 0xFFFFFFFFFFFFFFFFull;
-            l_var1 = 0x0000000000000000ull;
-            l_spare = 0xFFFF0000FFFF0000ull;
-
-            rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            if (l_mbaPosition == 0)
-            {
-                //Writing MBS 01 pattern registers for comparison mod
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-            else if (l_mbaPosition == 1)
-            {
-                //Writing MBS 23 pattern registers for comparison mod
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-        }
-        else if (i_datamode == ABLE_FIVE)
-        {
-            l_var = 0xA5A5A5A5A5A5A5A5ull;
-            l_var1 = 0x5A5A5A5A5A5A5A5Aull;
-            l_spare = 0xA55AA55AA55AA55Aull;
-
-            rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            if (l_mbaPosition == 0)
-            {
-                //Writing MBS 01 pattern registers for comparison mod
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689,  l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-            else if (l_mbaPosition == 1)
-            {
-                //Writing MBS 23 pattern registers for comparison mod
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-        }
-        else if ((i_datamode == DATA_GEN_DELTA_I) || (i_datamode
-            == MCBIST_2D_CUP_PAT0))
-        {
-            l_var = 0xFFFFFFFFFFFFFFFFull;
-            l_var1 = 0x0000000000000000ull;
-            l_spare = 0xFF00FF00FF00FF00ull;
-
-            rc_num = l_var_data_buffer_64.setDoubleWord(0, l_var);
-            rc_num |= l_var1_data_buffer_64.setDoubleWord(0, l_var1);
-            rc_num |= l_spare_data_buffer_64.setDoubleWord(0, l_spare);
-            if (rc_num)
-            {
-                FAPI_ERR("cfg_mcb_dgen:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            if (l_mbaPosition == 0)
-            {
-                //Writing MBS 01 pattern registers for comparison mod
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD0Q_0x02011681, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur,MBS_MCBIST01_MBS_MCBFD1Q_0x02011682, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD2Q_0x02011683, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD3Q_0x02011684, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD4Q_0x02011685, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD5Q_0x02011686, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD6Q_0x02011687, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFD7Q_0x02011688, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDQ_0x02011689, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MBS_MCBFDSPQ_0x0201168A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-            else if (l_mbaPosition == 1)
-            {
-                //Writing MBS 23 pattern registers for comparison mod
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD0Q_0x02011781, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD1Q_0x02011782, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD2Q_0x02011783, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD3Q_0x02011784, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD4Q_0x02011785, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD5Q_0x02011786, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD6Q_0x02011787, l_var_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFD7Q_0x02011788, l_var1_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDQ_0x02011789, l_spare_data_buffer_64);
-                if (rc) return rc;
-                rc = fapiPutScom(i_target_centaur, MBS_MCBIST23_MBS_MCBFDSPQ_0x0201178A, l_spare_data_buffer_64);
-                if (rc) return rc;
-            }
-        }
-        else
-        {
-            FAPI_ERR("cfg_mcb_dgen: Invalid data mode (%d)", i_datamode);
-            const mcbist_data_gen & DATA_MODE_PARAM = i_datamode;
-            FAPI_SET_HWP_ERROR(rc, RC_CFG_MCB_DGEN_INVALID_INPUT);
-            return rc;
-        }
-    }
-
-    if (l_random_flag == 1)
-    {
-        for (l_index = 0; l_index < MAX_BYTE; l_index++)
-        {
-
-            for (l_index1 = 0; l_index1 < 8; l_index1++)
-            {
-                //l_rand_8 = rand();
-                l_rand_8 = 0xFF;
-                rc_num = l_data_buffer_64.insert(l_rand_8, 8 * l_index1, 8, 24);
-                if (rc_num)
-                {
-                    FAPI_ERR("cfg_mcb_dgen:");
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                } // Source start in sn is given as 24 -- need to ask
-            }
-            rc = fapiPutScom(i_target_mba, l_mba01_mcb_random[l_index], l_data_buffer_64);
-            if (rc) return rc;
-
-            if (l_mbaPosition == 0)
-            {
-                rc = fapiPutScom(i_target_centaur, l_mbs01_mcb_random[l_index], l_data_buffer_64);
-                if (rc) return rc;
-
-            }
-            else
-            {
-                rc = fapiPutScom(i_target_centaur, l_mbs23_mcb_random[l_index], l_data_buffer_64);
-                if (rc) return rc;
-            }
-        }
-    }
-    
-    #ifdef FAPI_MSSLABONLY
-    struct drand48_data randBuffer;
-    double l_rand_D = 0;
-    uint8_t l_rand_l = 0; 
-    #endif
-    uint64_t l_data_buffer_64_value = 0;
-
-    // get the rotate value loaded into reg, if rotate value 0 / not defined the default to rotate =13
-    if(i_mcbrotate == 0)
-    {
-        FAPI_DBG("%s:i_mcbrotate == 0 , the l_rotnum is set to 13",i_target_mba.toEcmdString());
-        l_rotnum = 13;   // for random data generation - basic setup
-    }
-    else
-    {
-        l_rotnum = i_mcbrotate;
-    }
-	
-	
-    rc_num = rc_num | l_data_buffer_64.flushTo0();
-    
-    // get the rotate data seed loaded into reg, if rotate data value = 0 / not defined the default rotate pttern is randomlly generated.    
-    if(i_mcbrotdata == 0)
-    {   // generate the random number
-        
-	#ifdef FAPI_MSSLABONLY
-     	for(l_index1 = 0; l_index1 < 8; l_index1++)
-     	{
-     	   //l_rand_8 = drand48_r();
-     	   drand48_r(&randBuffer, &l_rand_D);
-     	   //l_rand_l = (uint8_t)l_rand_D;
-     	   l_rand_l = static_cast<unsigned int>((l_rand_D * 100) + 0.5);
-     	   if(l_rand_l == 0x00)
-     	   {
-     	      l_rand_l = 0xFF;
-     	   }
-     	   //FAPI_INF("%s:Value of seed drand48_r : %02X",i_target_mba.toEcmdString(), l_rand_l  );
-     	   rc_num = rc_num | l_data_buffer_64.insert(l_rand_l,8*l_index1,8);	   // Source start in sn is given as 24 -- need to ask
-	   if (rc_num)
-           {
-              FAPI_ERR( "cfg_mcb_dgen: setting up mcbrotate data error");       // Error setting up buffers
-              rc.setEcmdError(rc_num);
-              return rc;
-           }
-     	}
-        #else
-	   rc_num = rc_num | l_data_buffer_64.setDoubleWord(0,0x863A822CDF2924C4ull);
-	   if (rc_num)
-           {
-              FAPI_ERR( "cfg_mcb_dgen: setting up mcbrotate data error");       // Error setting up buffers
-              rc.setEcmdError(rc_num);
-              return rc;
-           }
-	#endif
-    }
-    else
-    {
-     	rc_num = rc_num | l_data_buffer_64.setDoubleWord(0,i_mcbrotdata);	
-	if (rc_num)
-        {
-          FAPI_ERR( "cfg_mcb_dgen:");       // Error setting up buffers
-          rc.setEcmdError(rc_num);
-          return rc;
-       }
-    }
-    
-    // load the mcbist and mba with rotnum and rotdata.
-    rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBDRSRQ_0x030106bc , l_data_buffer_64); if(rc) return rc;//added
-    if(l_mbaPosition == 0)
-    {
-       rc = fapiPutScom(i_target_centaur, 0x0201167F , l_data_buffer_64); if(rc) return rc;
-       l_data_buffer_64_value = l_data_buffer_64.getDoubleWord (0);
-       FAPI_INF("%s:Value of Rotate data seed %016llX for reg %08X",i_target_mba.toEcmdString(), l_data_buffer_64_value, 0x0201167F );
-       
-       rc_num = rc_num | l_data_buffer_16.insert(l_data_buffer_64,0,16); 
-       rc = fapiGetScom(i_target_centaur, 0x02011680 , l_data_buffer_64); if(rc) return rc;
-       rc_num = rc_num | l_data_buffer_64.insert(l_rotnum,0,4,4);
-       rc_num = rc_num | l_data_buffer_64.insert(l_data_buffer_16,4,16);
-       if (rc_num)
-       {
-          FAPI_ERR( "cfg_mcb_dgen:");       // Error setting up buffers
-          rc.setEcmdError(rc_num);
-          return rc;
-       }	   
-       rc = fapiPutScom(i_target_centaur, 0x02011680 , l_data_buffer_64); if(rc) return rc;
-       
-    }
-    else
-    {
-       rc = fapiPutScom(i_target_centaur, 0x0201177F , l_data_buffer_64); if(rc) return rc;//added
-       l_data_buffer_64_value = l_data_buffer_64.getDoubleWord (0);
-       FAPI_INF("%s:Value of Rotate data seed %016llX for reg %08X",i_target_mba.toEcmdString(), l_data_buffer_64_value, 0x0201177F );
-
-       rc_num = rc_num | l_data_buffer_16.insert(l_data_buffer_64,0,16);        
-       rc = fapiGetScom(i_target_centaur, 0x02011780 , l_data_buffer_64); if(rc) return rc;
-       rc_num = rc_num | l_data_buffer_64.insert(l_rotnum,0,4,4);
-       rc_num = rc_num | l_data_buffer_64.insert(l_data_buffer_16,4,16);
-       if (rc_num)
-       {
-          FAPI_ERR( "cfg_mcb_dgen:");       // Error setting up buffers
-          rc.setEcmdError(rc_num);
-          return rc;
-       }	  	   
-       rc = fapiPutScom(i_target_centaur, 0x02011780 , l_data_buffer_64); if(rc) return rc;
-       
-    }
-
-    FAPI_DBG("%s: Preet Clearing bit 20 of MBA01_MCBIST_MCBDRCRQ_0x030106bd to avoid inversion of data to the write data flow",i_target_mba.toEcmdString());
-    rc_num = rc_num | l_data_buffer_64.clearBit(20,2); 
-    if (rc_num)
-    {
-       FAPI_ERR( "cfg_mcb_dgen:");	 // Error setting up buffers
-       rc.setEcmdError(rc_num);
-       return rc;
-    }
-    rc = fapiPutScom(i_target_mba,MBA01_MCBIST_MCBDRCRQ_0x030106bd,l_data_buffer_64); 
-   
-    return rc;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
deleted file mode 100755
index 9782c338a..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H
+++ /dev/null
@@ -1,368 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist.H,v 1.49 2015/08/07 11:09:15 sasethur Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             :  mss_mcbist.H
-// *! TITLE                :
-// *! DESCRIPTION          : MCBIST procedures
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Preetham Hosmane        Email: preeragh@in.ibm.com
-// *! BACKUP               : Sethuraman, Saravanan        Email: saravanans@in.ibm.com
-// *!***************************************************************************
-// CHANGE HISTORY:
-//-------------------------------------------------------------------------------
-// Version:|Author: | Date:   | Comment:
-// --------|--------|---------|--------------------------------------------------
-//   1.49  |preeragh|7/26/15  | Added RW infinite
-//   1.48  |lapietra|6/26/15  | Added RMWFIX and RMWFIX_I tests
-//   1.47  |sglancy |12/16/14| Merged FW comments with lab debugging needs
-//   1.46  |preeragh|12/15/14| Revert back, removed rwheeler changes
-//   1.43  |rwheeler|11/19/14|option to pass in rotate data seed
-//   1.42  |mjjones |01/20/14 |RAS Review Updates
-//   1.41  |aditya  |12/17/13 |Updated mcb_error_map function parameters
-//   1.40  |rwheeler|10/29/13 |added W_ONLY_INFINITE_RAND test
-//   1.39  |aditya  |10/29/13 |Updated mcb_error_map function parameters
-//   1.38  |aditya  |09/18/13 |Updated parameters for random seed attribute
-//   1.37  |aditya  |08/02/13 |Updated parameters in mcb_error_map_print function
-//   1.36  |aditya  |07/09/13 |Added l_random_addr_enable and l_fixed_addr_enable for struct Subtest_info
-//   1.35  |aditya  |06/11/13 |Added l_random_data_enable and l_fixed_data_enable for struct Subtest_info
-//   1.34  |aditya  |05/23/13 |Added TEST_RR and TEST_RF testtypes
-//   1.33  |aditya  |05/22/13 |updated parameters for Subtest Printing
-//   1.32  |aditya  |05/14/13 |updated parameters for cfg_mcb_dgen and random seed details
-//   1.31  |aditya  |05/07/13 |Changed Parameter Passing in Functions
-//   1.30  |aditya  |04/22/13 |updated testtypes
-//   1.27  |aditya  |02/13/13 |updated testtypes
-//   1.25  |aditya  |02/12/13 |updated testtypes
-//   1.24  |aditya  |01/30/13 |Updated fw comments
-//   1.23  |aditya  |01/16/13 |added a parameter to setup_mcbist function
-//   1.22  |aditya  |01/11/13 |added a parameter to setup_mcbist function
-//   1.21  |aditya  |01/07/13 | Updated FW Review Comments
-//   1.20  |aditya  |01/03/13 | Updated FW Comments
-//   1.18  |aditya  |12/18/12 | Updated Review Comments
-//   1.17  |aditya  |12/14/12 |Updated FW review comments
-//   1.16  |aditya  |12/6/12  | Updated Review Comments
-//   1.15  |aditya  |11/15/12 | Updated for FW REVIEW COMMENTS
-//   1.13  |aditya  |10/29/12 | Updated from ReturnCode to fapi::ReturnCode and Target to const fapi::Target &
-//   1.12  |aditya  |10/18/12 | Changed Parameters for Function mcb_write_test_mem
-//   1.11  |aditya  |10/17/12 | updated code to be compatible with ecmd 13 release
-//   1.10  |aditya  |15-Oct-12| Moved scom address to cen_scom_addresses.H, added user option
-//   1.9   |bellows |16-Jul-12| Added in Id tag
-//   1.6   |gaushard|26/03/12 | Removed Extra Comments/Codes
-//   1.5   |gaushard|26/03/12 | Updated Function Declaration
-//   1.4   |sasethur|23/03/12 | Added enum for shmoo mode
-//   1.3   |gaushard|22/03/12 | Added address generation function
-//   1.2   |sasethur|24/02/12 | Updated Typo
-//   1.1   |gaushard|14/02/12 | Shifted register address from .C file to .H file
-//   1.0   |gaushard|12/01/12 | Initial version
-//------------------------------------------------------------------------------
-#ifndef MSS_MCBIST_H
-#define MSS_MCBIST_H
-/****************************************************************************************/
-/* mss_mcbist.H                                                                           */
-/****************************************************************************************/
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <mss_access_delay_reg.H>
-
-extern "C"
-{
-using namespace fapi;
-
-//############### Global variables ################
-
-enum mcbist_test_mem
-{
-    USER_MODE,
-    CENSHMOO,
-    SUREFAIL,
-    MEMWRITE,
-    MEMREAD,
-    CBR_REFRESH,
-    MCBIST_SHORT,
-    SHORT_SEQ,
-    DELTA_I,
-    DELTA_I_LOOP,
-    SHORT_RAND,
-    LONG1,
-    BUS_TAT,
-    SIMPLE_FIX,
-    SIMPLE_RAND,
-    SIMPLE_RAND_2W,
-    SIMPLE_RAND_FIXD,
-    SIMPLE_RA_RD_WR,
-    SIMPLE_RA_RD_R,
-    SIMPLE_RA_FD_R,
-    SIMPLE_RA_FD_R_INF,
-    SIMPLE_SA_FD_R,
-    SIMPLE_RA_FD_W,
-    INFINITE,
-    WR_ONLY,
-    W_ONLY,
-    R_ONLY,
-    W_ONLY_RAND,
-    R_ONLY_RAND,
-    R_ONLY_MULTI,
-    SHORT,
-    SIMPLE_RAND_BARI,
-    W_R_INFINITE,
-    W_R_RAND_INFINITE,
-    R_INFINITE1,
-    R_INFINITE_RF,
-    MARCH,
-    SIMPLE_FIX_RF,
-    SHMOO_STRESS,
-    SIMPLE_RAND_RA,
-    SIMPLE_FIX_RA,
-    SIMPLE_FIX_RF_RA,
-    TEST_RR,
-    TEST_RF,
-    W_ONLY_INFINITE_RAND,
-    MCB_2D_CUP_SEQ,
-    MCB_2D_CUP_RAND,
-    SHMOO_STRESS_INFINITE,
-    HYNIX_1_COL,
-    RMWFIX,
-    RMWFIX_I,
-    W_INFINITE,
-    R_INFINITE
-};
-
-enum mcbist_data_gen
-{
-    ABLE_FIVE,
-    USR_MODE,
-    ONEHOT,
-    DQ0_00011111_RESTALLONE,
-    DQ0_11100000_RESTALLZERO,
-    ALLZERO,
-    ALLONE,
-    BYTE_BURST_SIGNATURE,
-    BYTE_BURST_SIGNATURE_V1,
-    BYTE_BURST_SIGNATURE_V2,
-    BYTE_BURST_SIGNATURE_V3,
-    DATA_GEN_DELTA_I,
-    MCBIST_2D_CUP_PAT0,
-    MPR,
-    MPR03,
-    MPR25,
-    MPR47,
-    DELTA_I1,
-    MCBIST_2D_CUP_PAT1,
-    MHC_55,
-    MHC_DQ_SIM,
-    MCBIST_2D_CUP_PAT2,
-    MCBIST_2D_CUP_PAT3,
-    MCBIST_2D_CUP_PAT4,
-    MCBIST_2D_CUP_PAT5,
-    MCBIST_2D_CUP_PAT6,
-    MCBIST_2D_CUP_PAT7,
-    MCBIST_2D_CUP_PAT8,
-    MCBIST_2D_CUP_PAT9,
-    CWLPATTERN,
-    GREY1,
-    DC_ONECHANGE,
-    DC_ONECHANGEDIAG,
-    GREY2,
-    FIRST_XFER,
-    MCBIST_222_XFER,
-    MCBIST_333_XFER,
-    MCBIST_444_XFER,
-    MCBIST_555_XFER,
-    MCBIST_666_XFER,
-    MCBIST_777_XFER,
-    MCBIST_888_XFER,
-    FIRST_XFER_X4MODE,
-    MCBIST_LONG,
-    PSEUDORANDOM,
-    CASTLE
-};
-
-enum mcbist_oper_type
-{
-    W,
-    R,
-    RW,
-    WR,
-    RWR,
-    RWW,
-    OPER_RAND,
-    GOTO
-};
-
-enum mcbist_data_mode
-{
-    FIX,
-    DATA_RF,
-    DATA_RR,
-    RECCF,
-    RECCB,
-    DEA,
-    DRL,
-    DRR
-    	      	
-};
-
-enum mcbist_addr_mode
-{
-    SF,
-    SR,
-    RF,
-    RR
-};
-
-enum mcbist_add_select_mode
-{
-    FIX_ADDR,
-    PORTA0_RANDOM,
-    PORTA1_RANDOM,
-    PORTA0_SEQ
-};
-
-enum mcbist_data_select_mode
-{
-    DEFAULT,
-    BURST0,
-    BURST1,
-    BURST2
-};
-
-enum mcbist_byte_mask
-{
-    BYTE0,
-    BYTE1,
-    BYTE2,
-    BYTE3,
-    BYTE4,
-    BYTE5,
-    BYTE6,
-    BYTE7,
-    BYTE8,
-    BYTE9,
-    UNMASK_ALL,
-    NONE
-};
-
-enum shmoo_mode
-{
-   FAST = 0,
-   ONE_SLOW = 1,
-   QUARTER_SLOW = 2,
-   HALF_SLOW = 3,
-   FULL_SLOW = 4,
-   ONE_CHAR = 5,
-   QUARTER_CHAR = 6,
-   HALF_CHAR = 7,
-   FULL_CHAR = 8
-};
-
-enum shmoo_addr_mode
-{
-   FEW_ADDR= 0,
-   QUARTER_ADDR = 1,
-   HALF_ADDR = 2,
-   FULL_ADDR = 3
-};
-
-struct Subtest_info
-{
-uint8_t l_operation_type;
-uint8_t l_data_mode;
-uint8_t l_addr_mode;
-uint8_t l_random_data_enable;
-uint8_t l_fixed_data_enable;
-uint8_t l_random_addr_enable;
-uint8_t l_fixed_addr_enable;
-};
-
-
-fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,
-                          uint8_t *o_mcb_status,
-                          struct Subtest_info l_sub_info[30],
-                          uint8_t i_flag);
-
-fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba,
-                               uint8_t  o_error_map[][8][10][2],
-                               uint8_t i_CDarray0[80],
-                               uint8_t i_CDarray1[80],
-                               uint8_t count_bad_dq[2]);
-
-fapi::ReturnCode mcb_write_test_mem(const fapi::Target & i_target_mba,
-                                    const uint64_t i_reg_addr,
-                                    mcbist_oper_type i_operation_type,
-                                    uint8_t i_cfg_test_123_cmd,
-                                    mcbist_addr_mode i_addr_mode,
-                                    mcbist_data_mode i_data_mode,
-                                    uint8_t i_done,
-                                    mcbist_data_select_mode i_data_select_mode,
-                                    mcbist_add_select_mode i_addr_select_mode,
-                                    uint8_t i_testnumber,
-                                    uint8_t i_testnumber1,
-                                    uint8_t i_total_no,
-                                    struct Subtest_info l_sub_info[30]);
-
-fapi::ReturnCode cfg_mcb_test_mem(const fapi::Target & i_target_mba,
-                                  mcbist_test_mem i_test_type,
-                                  struct Subtest_info l_sub_info[30]);
-
-fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba);
-
-fapi::ReturnCode cfg_mcb_dgen(const fapi::Target & i_target_mba,
-                              mcbist_data_gen i_datamode,
-                              uint8_t i_mcbrotate,
-			      uint64_t i_mcbrotdata);
-
-fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba);
-
-fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba);
-
-fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba,
-                              mcbist_byte_mask i_mcbbytemask,
-                              uint8_t i_mcbrotate,
-                              uint64_t i_mcbrotdata,
-                              struct Subtest_info l_sub_info[30],
-			      char * l_str_cust_addr);
-
-fapi::ReturnCode  mcb_error_map_print(const fapi::Target & i_target_mba,
-                                      ecmdDataBufferBase & l_mcb_fail_160,
-                                      uint8_t i_port,
-                                      uint8_t l_array[80],
-                                      uint8_t l_number,
-                                      ecmdDataBufferBase l_data_buf_port,
-                                      ecmdDataBufferBase l_data_buf_spare);
-
-fapi::ReturnCode mss_conversion_testtype(const fapi::Target & i_target_mba,
-                                         uint8_t l_pattern,
-                                         mcbist_test_mem &i_mcbtest);
-
-fapi::ReturnCode mss_conversion_data(const fapi::Target & i_target_mba,
-                                     uint8_t l_pattern,
-                                     mcbist_data_gen &i_mcbpatt);
-}
-#endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
deleted file mode 100644
index 2d353e388..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C
+++ /dev/null
@@ -1,1692 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_address.C,v 1.26 2015/07/24 08:32:13 sasethur Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             :  mss_mcbist_address_default.C
-// *! TITLE                : 
-// *! DESCRIPTION          : MCBIST procedures
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Preetham Hosmane | preeragh@in.ibm.com
-// *! BACKUP               : Saravanan Sethuraman
-// *!***************************************************************************
-// CHANGE HISTORY:
-//-------------------------------------------------------------------------------
-// Version:|Author: | Date:   | Comment:
-// --------|--------|---------|--------------------------------------------------
-// 1.26    |preeragh|22-Jul-15| 64bit compile fix
-// 1.25    |preeragh|22-Jun-15| DDR4 - Mods and fixes
-// 1.24    |lwmulkey|15-JUN-15| Add 2H CDIMM support
-// 1.20    |lwmulkey|06-JUN-15| Add slave rank support
-// 1.17    |sglancy |16-FEB-15| Merged FW comments with lab debugging needs
-// 1.17    |preeragh|15-Dec-14| Fix FW Review Comments
-// 1.16    |rwheeler|10-Nov-14| Update to address_generation for custom address string
-// 1.15    |preeragh|03-Nov-14| Fix for 128GB Schmoo
-// 1.14    |mjjones |20-Jan-13| RAS Review Updates
-// 1.13    |preet   |18-Dec-13| Added 64K default for few addr_mode
-// 1.12    |preet   |17-Dec-13| Added Addr modes
-// 1.11	   |preeragh|17-May-13| Fixed FW Review Comments
-// 1.10	   |preeragh|30-Apr-13| Fixed FW Review Comment
-// 1.9     |bellows |04-Apr-13| Changed program to be Hostboot compliant
-// 1.2     |bellows |03-Apr-13| Added Id and cleaned up a warning msg.
-// 1.1     |        |xx-Apr-13| Copied from original which is now known as mss_mcbist_address_default/_lab.C
-// 1.2 	   Preetham | xx - Apr -13| Fixed rc_num call
-//------------------------------------------------------------------------------
-
-#include "mss_mcbist_address.H"
-extern "C"
-{
-using namespace fapi;
-
-#define MAX_ADDR_BITS 37
-#define MAX_VALUE_TWO 2
-
-#define DELIMITERS ","
-
-fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,uint8_t i_port,mcbist_addr_mode i_addr_type,interleave_type i_add_inter_type,uint8_t i_rank,uint64_t &io_start_address, uint64_t &io_end_address, char * l_str_cust_addr)
-{
-    fapi::ReturnCode rc;
-    uint8_t l_num_ranks_per_dimm[MAX_VALUE_TWO][MAX_VALUE_TWO];
-    uint8_t l_num_master_ranks[MAX_VALUE_TWO][MAX_VALUE_TWO];
-    uint8_t l_dram_banks = 0;
-    uint8_t l_dram_rows = 0;
-    uint8_t l_dram_cols = 0;
-    //uint8_t l_dram_density = 0;
-    //uint8_t l_dram_width = 0;
-    uint8_t l_addr_inter = 0;
-    uint8_t l_num_ranks_p0_dim0,l_num_ranks_p0_dim1,l_num_ranks_p1_dim0,l_num_ranks_p1_dim1;
-    uint8_t l_master_ranks_p0_dim0,l_master_ranks_p0_dim1,l_master_ranks_p1_dim0;
-    uint8_t mr3_valid, mr2_valid, mr1_valid,sl0_valid,sl1_valid,sl2_valid;
-    uint32_t rc_num;
-    char S0[] = "b";
-    //Choose a default buffer for the below
-    //0			1	2		3	4	5	6	7	8	9	10	11	12	13	14	15	16	17	18	19	20	21	22	23	24	25	26	27	28	29	30	31	32	33	34	35	36
-    //MR0(MSB)	MR1	MR2 	MR3	BA0	BA1	BA2	BA3	C3	C4	C5	C6	C7	C8	C9	C10	C11	R0	R1	R2	R3	R4	R5	R6	R7	R8	R9	R10	R11	R12	R13	R14	R15	R16	SL0(MSB)	SL1	SL2
-    ecmdDataBufferBase l_default_add_buffer(64);
-    ecmdDataBufferBase l_new_add_buffer(64);
-
-    rc_num = l_default_add_buffer.flushTo0();
-    rc_num |= l_new_add_buffer.flushTo0();
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  addr_gen:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba,l_num_master_ranks);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_BANKS, &i_target_mba, l_dram_banks);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ROWS, &i_target_mba, l_dram_rows);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_COLS, &i_target_mba, l_dram_cols);
-    if (rc) return rc;
-    //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, l_dram_density);
-    //if (rc) return rc;
-    //rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width);
-    //if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_INTER, &i_target_mba, l_addr_inter);
-    if (rc) return rc;
-
-    //------------------------------ Debug Stuff -------------------------------
-   //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][0]);
-   //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[0][1]);
-   //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][0]);
-   //FAPI_INF("ATTR_EFF_NUM_RANKS_PER_DIMM is %d ",l_num_ranks_per_dimm[1][1]);
-   //------------------------------ Debug Stuff -------------------------------
-   //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim0 is %d ",l_num_master_ranks[0][0]);
-   //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p0_dim1 is %d ",l_num_master_ranks[0][1]);
-   //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim0 is %d ",l_num_master_ranks[1][0]);
-   //FAPI_INF("ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM l_num_master_p1_dim1 is %d ",l_num_master_ranks[1][1]);
-   //-------------------------------------------------------------------------------
-
-l_num_ranks_p0_dim0 = l_num_ranks_per_dimm[0][0];
-l_num_ranks_p0_dim1 = l_num_ranks_per_dimm[0][1];
-l_num_ranks_p1_dim0 = l_num_ranks_per_dimm[1][0];
-l_num_ranks_p1_dim1 = l_num_ranks_per_dimm[1][1];
-l_master_ranks_p0_dim0 = l_num_master_ranks[0][0];
-l_master_ranks_p0_dim1 = l_num_master_ranks[0][1];
-l_master_ranks_p1_dim0 = l_num_master_ranks[1][0];
-//l_master_ranks_p1_dim1 = l_num_master_ranks[1][1];
-//Initial all ranks are invalid
-mr3_valid = 0;
-mr2_valid = 0;
-mr1_valid = 0;
-sl2_valid = 0;
-sl1_valid = 0;
-sl0_valid = 0;
-
-if( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 0) )   //Single Rank case   -- default0
-	{
-		//do rank-only stuff for this
-		FAPI_DBG("%s:--- INSIDE 1R",i_target_mba.toEcmdString());
-		l_addr_inter=3;
-	}
-	
-else if ( (l_num_ranks_p0_dim0 == 1 && l_num_ranks_p0_dim1 == 1) || (l_num_ranks_p1_dim0 == 1 && l_num_ranks_p1_dim1 == 1) )
-{
-	FAPI_DBG("%s:--- INSIDE p0d0 valid and p0d1 valid --- 0 4----  2R",i_target_mba.toEcmdString());
-	mr1_valid=1;
-}
-
-else if ( (l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 0) )
-{
-	FAPI_DBG("%s:--- INSIDE p0d0 valid and p0d1 valid --- 0 1----  2R",i_target_mba.toEcmdString());
-	mr3_valid=1;
-}
-else if (((l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 2)|| (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 2)) && (l_master_ranks_p0_dim0 != 1 && l_master_ranks_p0_dim1 != 1))   //Rank 01 and 45 case
-	{
-		FAPI_DBG("%s:--- INSIDE  --- 2R   0145",i_target_mba.toEcmdString());
-		mr3_valid = 1;
-		mr1_valid=1;
-	}
-
-else if((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 0 )|| (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 0 ))	//Rank 0123 on single dimm case
-	{
-		mr3_valid = 1;mr2_valid = 1;
-	}
-else if (((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 4)) && l_master_ranks_p0_dim0 == 1) //1r 4h stack
-{
-        mr1_valid = 0; //DDC
-	sl1_valid = 1;
-	sl2_valid = 1;
-}
-
-else if (((l_num_ranks_p0_dim0 == 8 && l_num_ranks_p0_dim1 == 0) || (l_num_ranks_p1_dim0 == 8 && l_num_ranks_p1_dim1 == 0)) && ((l_master_ranks_p0_dim0 == 2) || (l_master_ranks_p0_dim1 == 0 && l_master_ranks_p1_dim0 == 2))) //2rx4 4h ddr4 3ds 
-{
-	l_addr_inter = 4;
-	//l_str_cust_addr = "sl2,sl1,ba0,mr3,cl3,cl4,cl5,ba1,cl6,cl7,cl8,ba2,r0,r1,r2,ba3,cl2,cl9,cl11,cl13,r3,r4,r5,r6,r7,r8,r9,r10,r11,r12,r13,r14,r15,r16,sl0,mr2,mr1,mr0"; //DDC
-        mr3_valid = 1; //DDC
-	sl1_valid = 1;
-	sl2_valid = 1;
-}
-else if ((l_num_ranks_p0_dim0 == 4 && l_num_ranks_p0_dim1 == 4) || (l_num_ranks_p1_dim0 == 4 && l_num_ranks_p1_dim1 == 4)) //Rank 0123 and 4567 case
-{
-	mr3_valid = 1;
-	mr2_valid = 1;
-	mr1_valid = 1;
-}
-    else if (((l_num_ranks_p0_dim0 == 2 && l_num_ranks_p0_dim1 == 2) ||
-              (l_num_ranks_p1_dim0 == 2 && l_num_ranks_p1_dim1 == 2)) &&
-              (l_master_ranks_p0_dim0 == 1 && l_master_ranks_p0_dim1 == 1)) //1rx4 2h ddr4 3ds 2 dimm, CDIMM
-    {
-        sl1_valid = 0;
-        sl2_valid = 1;
-	mr1_valid = 1;
-    }
-
-    else
-    {
-        FAPI_INF("-- Error ---- mcbist_addr_Check dimm_Config ----- ");
-    }
-
-    //FAPI_INF("ATTR_EFF_DRAM_GEN is %d ",l_dram_gen);
-    //FAPI_INF("ATTR_EFF_DRAM_BANKS is %d ",l_dram_banks);
-    //FAPI_INF("ATTR_EFF_DRAM_ROWS is %d ",l_dram_rows);
-    //FAPI_INF("ATTR_EFF_DRAM_COLS is %d ",l_dram_cols);
-    //FAPI_INF("ATTR_EFF_DRAM_DENSITY is %d ",l_dram_density);
-    //FAPI_INF("ATTR_EFF_DRAM_WIDTH is %d ",l_dram_width);
-    //FAPI_INF("ATTR_ADDR_INTER Mode is %d ",l_addr_inter);
-    //FAPI_INF("--- BANK-RANK  Address interleave ---");
-    //custom addressing string is not to be used
-    if(l_addr_inter != 4) {
-       rc = parse_addr(i_target_mba, S0, mr3_valid, mr2_valid, mr1_valid,
-                    l_dram_rows, l_dram_cols, l_addr_inter,sl2_valid,sl1_valid,sl0_valid);
-       if (rc) return rc;
-    }
-    else {
-       FAPI_DBG("Custom addressing flag was selected");
-       rc = parse_addr(i_target_mba, l_str_cust_addr, mr3_valid, mr2_valid, mr1_valid,
-                    l_dram_rows, l_dram_cols, l_addr_inter,sl2_valid,sl1_valid,sl0_valid);
-       if (rc) return rc;
-    }
-
-    return rc;
-}
-
-fapi::ReturnCode parse_addr(const fapi::Target & i_target_mba,
-                            char addr_string[],
-                            uint8_t mr3_valid,
-                            uint8_t mr2_valid,
-                            uint8_t mr1_valid,
-                            uint8_t l_dram_rows,
-                            uint8_t l_dram_cols,
-                            uint8_t l_addr_inter,
-			    uint8_t sl2_valid,
-                            uint8_t sl1_valid,
-                            uint8_t sl0_valid)
-{
-    fapi::ReturnCode rc;
-    uint8_t i = MAX_ADDR_BITS;
-
-    uint8_t l_value;
-    uint32_t l_value32 = 0;
-    uint32_t l_sbit, rc_num;
-    uint32_t l_start = 0;
-    uint32_t l_len = 0;
-    uint64_t l_readscom_value = 0;
-    uint64_t l_end = 0;
-    uint64_t l_start_addr = 0;
-    uint8_t l_value_zero = 0;
-    uint8_t l_user_end_addr = 0;
-    ecmdDataBufferBase l_data_buffer_64(64);
-    ecmdDataBufferBase l_data_buffer_rd64(64);
-    uint8_t l_attr_addr_mode = 0;
-    uint8_t l_num_cols = 0;
-    uint8_t l_num_rows = 0;
-	uint8_t l_dram_gen = 0;
-	
-    rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_NUM_COLS, &i_target_mba, l_num_cols);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_NUM_ROWS, &i_target_mba, l_num_rows);
-    if (rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen);
-    if (rc) return rc;
-
-    if (l_num_cols == 0)
-    {
-        l_num_cols = l_dram_cols;
-    }
-
-    if (l_num_rows == 0)
-    {
-        l_num_rows = l_dram_rows;
-    }
-
-    //Set all the addr reg to 0
-    //Define Custom String
-    //Set all Params based on the string.
-    rc_num = l_data_buffer_64.flushTo0();
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    l_sbit = 0;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    i--;
-
-    l_sbit = 54;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    i--;
-	
-	////FAPI_INF("Inside strcmp mr3");
-    l_sbit = 18;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    if (mr3_valid == 1)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-        if (rc) return rc;
-        //FAPI_INF("mr3 Invalid");
-		
-        
-    }
-
-    ////FAPI_INF("Inside strcmp mr2");
-    l_sbit = 12;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    if (mr2_valid == 1)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        //FAPI_INF("Inside mr2 --- l_addr_inter");
-        rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-        if (rc) return rc;
-        //FAPI_INF("mr2 Invalid");
-		
-        
-    }
-
-    ////FAPI_INF("Inside strcmp mr1");
-    l_sbit = 6;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    if (mr1_valid == 1)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        //FAPI_INF("Inside mr1 --- l_addr_inter");
-        rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num =  l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-        if (rc) return rc;
-        //FAPI_INF("mr1 Invalid");
-		
-        
-    }
-
-
-    ////FAPI_INF("Inside strcmp ba2");
-    l_sbit = 48;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    i--;
-
-    ////FAPI_INF("Inside strcmp ba3");
-    l_sbit = 42;
-    l_value = i;
-    //------- Enable these for DDR4 --- for now constant map to zero
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    //FAPI_INF("ba3 Invalid");
-	if (l_dram_gen == 2){
-    rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-	i--;
-}
-else
-{
-	rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-	
-}
-
-
-    ////FAPI_INF("Inside strcmp mr0");
-    l_sbit = 0;
-    l_value = i;
-    //------- Enable these for DDR4 --- for now constant map to zero
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num =  l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-	
-    
-    ////FAPI_INF("Value of i = %d",i);
-    //FAPI_INF("mr0 Invalid\n");
-
-    ////FAPI_INF("Inside strcmp cl3");
-    l_sbit = 42;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-	
-	///////////////////////////////////////////////////////////////////
-    
-    //FAPI_INF("col2 Invalid");
-    ////FAPI_INF("Value of i = %d",i);
-    ////FAPI_INF("Inside strcmp cl3");
-    l_sbit = 36;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 1)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 3 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp cl4");
-    l_sbit = 30;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 2)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 4 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp cl5");
-    l_sbit = 24;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 3)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 5 -- Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp cl6");
-    l_sbit = 18;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 4)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 6 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp cl7");
-    l_sbit = 12;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 5)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num =  l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 7 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp cl8");
-    l_sbit = 6;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 6)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 8 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp cl9");
-    l_sbit = 0;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 7)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106cb, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 9 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp cl11");
-    l_sbit = 54;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 11)
-    {
-        if (l_dram_cols >= 11)
-        {
-            rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  parse_addr:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-            if (rc) return rc;
-            //FAPI_DBG("%s: Inside l_dram_cols > 10");
-            i--;
-        }
-        else
-        {
-            rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  parse_addr:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-            if (rc) return rc;
-			
-            FAPI_DBG("%s:Col 11 -- Invalid", i_target_mba.toEcmdString());
-            
-        }
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 11 -- Invalid");
-        
-    }
-
-    ////FAPI_INF("Value of i = %d",i);
-    ////FAPI_INF("Inside strcmp cl13");
-    l_sbit = 48;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_cols >= 12)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("Col 13 Invalid");
-        
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    ////FAPI_INF("Inside strcmp r0");
-    l_sbit = 42;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 0)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 0 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r1");
-    l_sbit = 36;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 1)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 1 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r2");
-    l_sbit = 30;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 2)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 2 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r3");
-    l_sbit = 24;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 3)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 3 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r4");
-    l_sbit = 18;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 4)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 4 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r5");
-    l_sbit = 12;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 5)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 5 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r6");
-    l_sbit = 6;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 6)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 6 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r7");
-    l_sbit = 0;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 7)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106ca, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 7 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r8");
-    l_sbit = 54;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 8)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 8 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r9");
-    l_sbit = 48;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 9)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 9 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r10");
-    l_sbit = 42;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 10)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 10 --  Invalid");
-        
-    }
-
-    ////FAPI_INF("Inside strcmp r11");
-    l_sbit = 36;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 11)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 11 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r12");
-    l_sbit = 30;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 12)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 12 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r13");
-    l_sbit = 24;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 13)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 13 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r14");
-    l_sbit = 18;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 14)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 14 --  Invalid");
-       
-    }
-
-    ////FAPI_INF("Inside strcmp r15");
-    l_sbit = 12;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_num_rows > 15)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-        //FAPI_INF("row 15 --  Invalid");
-       
-    }
-    ////FAPI_INF("Value of i = %d",i);
-    ////FAPI_INF("Inside strcmp r16 and l_dram_rows = %d",l_dram_rows);
-    l_sbit = 6;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-    if (rc) return rc;
-    if (l_dram_rows >= 17)
-    {
-        rc_num = l_data_buffer_64.insertFromRight(l_value, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-        i--;
-    }
-    else
-    {
-        ////FAPI_INF("r16 not used");
-        rc_num = l_data_buffer_64.insertFromRight(l_value_zero, l_sbit, 6);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        //FAPI_INF("Row 16 Invalid");
-        rc = fapiPutScom(i_target_mba, 0x030106c9, l_data_buffer_64);
-        if (rc) return rc;
-		
-       
-    }
-    ////FAPI_INF("Value of i = %d",i);
-
-
-    ////FAPI_INF("Inside strcmp sl2");
-    l_sbit = 36;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    if(sl2_valid==1)
-    {
-	  rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
-      if (rc_num)
-      {
-         FAPI_ERR( "Error in function  parse_addr:");
-         rc.setEcmdError(rc_num);
-         return rc;
-      }
-      rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
-	  i--;
-    }
-    else
-    {
-        rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);
-        if (rc_num)
-        {
-            FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
-        if(rc) return rc;
-        FAPI_DBG("%s:sl2 Invalid",i_target_mba.toEcmdString());
-        //FAPI_DBG("%s:Value of i = %d",i);
-     }
-
-    ////FAPI_INF("Inside strcmp sl1");
-    l_sbit = 30;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    //------- Enable these for later --- for now constant map to zero
-    if(sl1_valid==1)
-    {
-
-      rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
-      if (rc_num)
-      {
-         FAPI_ERR( "Error in function  parse_addr:");
-         rc.setEcmdError(rc_num);
-         return rc;
-      }
-      rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
-      if(rc) return rc;
-	  i--;
-    }
-    else
-    {
-        rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);
-        if (rc_num)
-        {
-            FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);
-        if(rc) return rc;
-        FAPI_DBG("%s:sl1 Invalid",i_target_mba.toEcmdString());
-        //FAPI_DBG("%s:Value of i = %d",i);
-     }
-    FAPI_INF("Inside strcmp sl0");
-    l_sbit = 24;
-    l_value = i;
-    rc = fapiGetScom(i_target_mba, 0x030106c8, l_data_buffer_64);
-    if (rc) return rc;
-    //------- Enable these for later --- for now constant map to zero
-    if(sl0_valid==1)
-    {
-
-      rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value,l_sbit ,6);
-      if (rc_num)
-      {
-         FAPI_ERR( "Error in function  parse_addr:");
-         rc.setEcmdError(rc_num);
-         return rc;
-      }
-      rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);  
-      if(rc) return rc;
-	  i--;
-    }
-    else
-    {
-        rc_num = rc_num| l_data_buffer_64.insertFromRight(l_value_zero,l_sbit ,6);
-        if (rc_num)
-        {
-            FAPI_ERR( "Error in function  parse_addr:");rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba,0x030106c8,l_data_buffer_64);  
-        if(rc) return rc;
-        FAPI_DBG("%s:sl0 Invalid",i_target_mba.toEcmdString());
-        //FAPI_DBG("%s:Value of i = %d",i);
-     }
-
-
-
-    //------ Setting Start and end addr counters
-
-    FAPI_INF("Debug - --------------- Setting Start and End Counters -----------\n");
-    rc_num = l_data_buffer_rd64.flushTo0();
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x030106d0, l_data_buffer_rd64);
-    if (rc) return rc;
-    l_value = i+1;
-    FAPI_INF("Setting end_addr Value of i = %d",i);
-    rc_num = l_data_buffer_rd64.flushTo0();
-
-    //Calculate and set Valid bits for end_addr
-    for (i = l_value; i <= 37; i++)
-    {
-        rc_num |= l_data_buffer_rd64.clearBit(i);
-        rc_num |= l_data_buffer_rd64.setBit(i);
-    }
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  parse_addr:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    l_readscom_value = l_data_buffer_rd64.getDoubleWord(0);
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, l_attr_addr_mode);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_START_ADDR, &i_target_mba, l_start_addr);
-    if (rc) return rc;
-    //FAPI_INF("User Defined ATTR - Start = %016llX",l_start_addr);
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_END_ADDR, &i_target_mba, l_end);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_RANK, &i_target_mba, l_user_end_addr);
-    if (rc) return rc;
-
-    if (l_user_end_addr == 1)
-    {
-        //Setting start and end Temp
-        rc_num = l_data_buffer_rd64.setDoubleWord(0, l_start_addr);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106d0, l_data_buffer_rd64);
-        if (rc) return rc;
-        rc = fapiPutScom(i_target_mba, 0x030106d1, l_data_buffer_rd64);
-        if (rc) return rc;
-
-        rc_num = l_data_buffer_rd64.setDoubleWord(0, l_end);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  parse_addr:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64);
-        if (rc) return rc;
-        rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64);
-        if (rc) return rc;
-    }
-
-    else
-    {
-        if (l_attr_addr_mode == 0)
-        {
-            FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- Few Address Mode --------",l_attr_addr_mode);
-            l_sbit = 32;
-            rc_num = l_data_buffer_rd64.flushTo0();
-            l_start = 24;
-            l_len = 8;
-            l_value32 = 28;
-            rc_num |= l_data_buffer_rd64.insert(l_value32, l_sbit, l_len,  l_start);
-            l_readscom_value = 0x000003FFF8000000ull;
-            rc_num |= l_data_buffer_rd64.setDoubleWord(0, l_readscom_value);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  parse_addr:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64);
-            if (rc) return rc;
-            l_readscom_value = l_data_buffer_rd64.getDoubleWord(0);
-            //FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value);
-        }
-        else if (l_attr_addr_mode == 1)
-        {
-            FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- QUARTER ADDRESSING Mode --------",l_attr_addr_mode);
-            l_readscom_value = l_readscom_value >> 2;
-            FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value);
-            rc_num = l_data_buffer_rd64.setDoubleWord(0, l_readscom_value);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  parse_addr:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64);
-            if (rc) return rc;
-        }
-        else if (l_attr_addr_mode == 2)
-        {
-            FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- HALF ADDRESSING Mode --------",l_attr_addr_mode);
-            l_readscom_value = l_readscom_value >> 1;
-            FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value);
-            rc_num = l_data_buffer_rd64.setDoubleWord(0, l_readscom_value);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  parse_addr:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64);
-            if (rc) return rc;
-        }
-        else
-        {
-            FAPI_INF("ATTR_EFF_SCHMOO_ADDR_MODE - %d ---- FULL Address Mode --------",l_attr_addr_mode);
-            FAPI_INF("Debug - Final End addr for 0x030106d2 = %016llX",l_readscom_value);
-            rc = fapiPutScom(i_target_mba, 0x030106d2, l_data_buffer_rd64);
-            if (rc) return rc;
-            rc = fapiPutScom(i_target_mba, 0x030106d3, l_data_buffer_rd64);
-            if (rc) return rc;
-        }
-    }
-
-    return rc;
-}
-}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H
deleted file mode 100644
index ecf6f2ed9..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H
+++ /dev/null
@@ -1,94 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_address.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_address.H,v 1.9 2015/06/03 15:09:03 lwmulkey Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             :  mss_mcbist_address.H
-// *! TITLE                : 
-// *! DESCRIPTION          : MCBIST procedures
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : 
-// *! BACKUP               : 
-// *!***************************************************************************
-// CHANGE HISTORY:
-//-------------------------------------------------------------------------------
-// Version:|Author: | Date:   | Comment:
-//  1.3    |bellows |03-Apr-13| Added Id for firmware
-//  1.4    |preeragh|17-Dec-14| Removed unwanted header includes
-//  1.5    |mjjones |20-Jan-14| RAS Review Updates
-//  1.7    |preeragh|15-Dec-14| Fix FW review comments
-//  1.8    |preeragh|16-FEB-14| Added in lab needs
-// --------|--------|---------|--------------------------------------------------
-//------------------------------------------------------------------------------
-#ifndef MSS_MCBIST_ADDRESS_H
-#define MSS_MCBIST_ADDRESS_H
-
-/*****************************************************************************/
-/* mss_mcbist_address.H                                                      */
-/*****************************************************************************/
-#include <fapi.H>
-#include <cen_scom_addresses.H>
-#include <mss_access_delay_reg.H>
-#include <mss_mcbist.H>
-#include <string.h>
-extern "C"
-{
-using namespace fapi;
-
-enum interleave_type
-{
-    BANK_RANK,
-    RANK_BANK,
-    BANK_ONLY,
-    RANK_ONLY,
-    RANKS_DIMM0,
-    RANKS_DIMM1,
-    USER_PATTERN
-};
-
-fapi::ReturnCode address_generation(const fapi:: Target & i_target_mba,
-                                    uint8_t i_port,
-                                    mcbist_addr_mode i_addr_type,
-                                    interleave_type i_add_inter_type,
-                                    uint8_t i_rank,
-                                    uint64_t &io_start_address,
-                                    uint64_t &io_end_address,
-				    char * l_str_cust_addr);
-
-fapi::ReturnCode parse_addr(const fapi:: Target & i_target_mba,
-                            char addr_string[],
-                            uint8_t mr3_valid,
-                            uint8_t mr2_valid,
-                            uint8_t mr1_valid,
-                            uint8_t l_dram_rows,
-                            uint8_t l_dram_cols,
-                            uint8_t l_addr_inter,uint8_t sl2_valid,uint8_t sl1_valid,uint8_t sl0_valid);
-
-}
-#endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
deleted file mode 100644
index a8929723b..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C
+++ /dev/null
@@ -1,3040 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mcbist_common.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mcbist_common.C,v 1.76 2015/08/07 11:08:45 sasethur Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : mss_mcbist_common.C
-// *! TITLE                :
-// *! DESCRIPTION          : MCBIST Procedures
-// *! CONTEXT              :
-// *!
-// *! OWNER  NAME          : Preetham Hosmane        	   Email: preeragh@in.ibm.com
-// *! BACKUP               : Sethuraman, Saravanan         Email: saravanans@in.ibm.com
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.76  |preeragh|07/15/15|R_W Infinite Added
-//   1.75  |lapietra|06/26/15|added RMWFIX and RMWFIX_I tests
-//   1.74  |preeragh|06/15/15|o_error_map Correction
-//   1.73  |sglancy |02/16/15|Merged in lab needs
-//   1.72  |sglancy |02/09/15|Fixed FW comments and addressed bugs
-//   1.71  |preeragh|01/16/15|Fixed FW comments
-//   1.70  |preeragh|12/16/14|Revert to FW build v.1.66
-//   1.68  |rwheeler|11/19/14|option to pass in rotate data seed
-//   1.67  |sglancy |11/03/14|Fixed MCBIST to allow for a custom user generated address - removed forcing of l_new_addr=1
-//   1.66  |preeragh|11/03/14|Fix Addressing Map and enable Refresh
-//   1.65  |        | -      | - 
-//   1.64  |rwheeler|10/24/14|Added thermal sensor data 
-//   1.63  |adityamd|02/07/14|RAS Review Updates
-//   1.62  |mjjones |01/17/14|RAS Review Updates
-//   1.61  |aditya  |01/15/14|Updated attr ATTR_EFF_CUSTOM_DIMM
-//   1.60  |aditya  |12/20/13|Updated max timeout for Mcbist Polling
-//   1.59  |aditya  |12/17/13|Updated mcb_error_map function parameters
-//   1.58  |aditya  |12/10/13|Updated Target for MBS registers
-//   1.57  |rwheeler|10/29/13 |added W_ONLY_INFINITE_RAND test
-//   1.56  |aditya  |10/29/13|Updated mcb_error_map function parameters
-//   1.55  |aditya  |10/24/13|Removed DD2.0 attribute check  for  ECC setup
-//   1.54  |aditya  |10/17/13|Minor fix in byte mask function
-//   1.53  |aditya  |10/05/13|Updated fw comments
-//   1.52  |aditya  |09/27/13|Updated for Host Boot Compile
-//   1.51  |aditya  |09/18/13|Updated parameters for random seed attribute and Error map masking
-//   1.50  |aditya  |08/08/13|Updated for Host Boot Compile
-//   1.49  |aditya  |08/02/13|Updated Error Map  function
-//   1.48  |aditya  |07/09/13|Added l_random_addr_enable and l_fixed_addr_enable for struct Subtest_info
-//   1.47  |aditya  |06/11/13|Replaced FAPI_INF to FAPI_DBG,Added target details for Prints
-//   1.46  |aditya  |06/11/13|Enabled pattern and testtype prints
-//   1.45  |aditya  |06/11/13|Added attributes ATTR_MCBIST_PRINTING_DISABLE
-//   1.44  |aditya  |05/23/13|Added TEST_RR and TEST_RF testtypes
-//   1.43  |aditya  |05/22/13|updated parameters for Subtest Printing
-//   1.41  |aditya  |05/14/13|updated parameters for random seed details
-//   1.40  |aditya  |05/07/13|Small Fix
-//   1.39  |aditya  |05/07/13|Moved some parameters to attributes.
-//   1.38  |aditya  |04/30/13|Minor fix for firmware
-//   1.37  |aditya  |04/22/13|Minor Fix
-//   1.36  |aditya  |04/09/13|Updated cfg_byte_mask and setup_mcbist functions
-//   1.35  |aditya  |03/18/13|Updated cfg_byte_mask and error map functions
-//   1.34  |aditya  |03/15/13|Added ISDIMM error map
-//   1.33  |aditya  |03/06/13|Updated Error map and addressing
-//   1.32  |aditya  |02/27/13|removed Port looping
-//   1.29  |aditya  |02/19/13|Updated Testtypes and removed rank looping
-//   1.26  |aditya  |02/13/13|Modified Addressing
-//   1.24  |aditya  |02/12/13|Modified Addressing
-//   1.23  |aditya  |02/07/13|Added MBS23 registers
-//   1.22  |abhijit |02/06/13|Updated cfg_byte_mask function
-//   1.21  |abhijit |01/30/13|Updated cfg_byte_mask function
-//   1.20  |aditya  |01/30/13|Updated fw comments
-//   1.18  |aditya  |01/30/13|Updated fw comments
-//   1.17  |aditya  |01/16/13|Updated setup_mcbist function
-//   1.16  |aditya  |01/11/13|Updated function headers
-//   1.15  |aditya  |01/11/13|added  parameters to setup_mcbist function
-//   1.14  |aditya  |01/07/13|Updated Review Comments
-//   1.13  |aditya  |01/03/13| Updated FW Comments
-//   1.10  |sasethur|12/14/12| Updated for warnings
-//   1.9   |aditya  |12/14/12| Updated FW review comments
-//   1.8   |aditya  |12/6/12 | Updated Review Comments
-//   1.7   |aditya  |11/15/12| Updated for FW REVIEW COMMENTS
-//   1.6   |aditya  |10/31/12| Fixed issue in mcb_error_map function
-//   1.5   |abhijit |10/29/12| fixed issue in byte mask function
-//   1.4   |aditya  |10/29/12| Updated from ReturnCode to fapi::ReturnCode and Target to const fapi::Target &
-//   1.3   |aditya  |10/18/12| Replaced insertFromBin by InsertFromRight
-//   1.2   |aditya  |10/17/12| updated code to be compatible with ecmd 13 release
-//   1.1   |aditya  |10/01/12| updated fw review comments, datapattern, testtype, addressing	
-//
-//
-//This File mss_mcbist_common.C contains the definition of common procedures for the files mss_mcbist.C and mss_mcbist_lab.C
-//------------------------------------------------------------------------------
-#include "mss_mcbist.H"
-#include "mss_mcbist_address.H"
-#include <mss_access_delay_reg.H>
-#include <fapiTestHwpDq.H>
-#include <dimmBadDqBitmapFuncs.H>
-#ifdef FAPI_MSSLABONLY
-#include <mss_cen_dimm_temp_sensor.H>
-#endif
-extern "C"
-{
-using namespace fapi;
-
-#define MCB_DEBUG
-#define MCB_DEBUG1
-#define MCB_DEBUG2
-
-const uint8_t MAX_PORT = 2;
-const uint8_t MAX_DRAM = 20;
-const uint8_t MAX_ISDIMM_DQ = 72;
-const uint8_t MAX_BYTE = 10;
-const uint8_t MAX_RANK = 8;
-const uint8_t MAX_NIBBLES = 2;
-const uint8_t MCB_TEST_NUM = 16;
-const uint64_t MCB_MAX_TIMEOUT = 0000000000060000ull;
-const uint64_t DELAY_100US = 100000; // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz)
-const uint64_t DELAY_2000SIMCYCLES = 2000; // general purpose 2000 sim cycle delay for sim mode     (100 ns if simclk = 20Ghz)
-
-const uint64_t END_ADDRESS = 0x0000000010000000ull; //Will be fixed later, once the address generation function is ready
-const uint64_t START_ADDRESS = 0x0000000004000000ull;
-const uint64_t FEW_INTERVAL = 0x000000000C000000ull;
-const uint64_t FOUR = 0x0000000000000004ull;
-
-//*****************************************************************/
-// Funtion name : setup_mcbist
-// Description  : Will setup the required MCBIST configuration register
-// Input Parameters :
-//     const fapi::Target &            Centaur.mba
-//     uint8_t i_port                   Port on which we are operating.
-
-//     mcbist_data_gen i_mcbpatt        Data pattern
-//     mcbist_test_mem i_mcbtest        subtest Type
-//     mcbist_byte_mask i_mcbbytemask   It is used to mask bad bits read from SPD
-//     uint8_t i_mcbrotate              Provides the number of bit to shift per burst
-//     uint64_t i_mcbrotdata            Provides the rotate data to shift per burst
-
-//     uint8_t i_pattern                Data Pattern
-//     uint8_t i_test_type              Subtest Type
-//     uint8_t i_rank                   Current Rank
-//     ,uint8_t i_bit32                 Flag to set bit 32 of register 02011674
-//uint64_t i_start                      Flag to set start address
-// uint64_t i_end                       Flag to set End address
-//uint8_t new_address_map				Flag to Enable Custom Address Map
-//****************************************************************/
-
-fapi::ReturnCode setup_mcbist(const fapi::Target & i_target_mba,
-                              mcbist_byte_mask i_mcbbytemask,
-                              uint8_t i_mcbrotate,
-                              uint64_t i_mcbrotdata,
-                              struct Subtest_info l_sub_info[30],
-			      char * l_str_cust_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint8_t l_bit32 = 0;
-
-    FAPI_DBG("%s:Function Setup_MCBIST", i_target_mba.toEcmdString());
-    FAPI_DBG("Custom Addr Mode %s",l_str_cust_addr);
-    ecmdDataBufferBase l_data_buffer_64(64);
-    ecmdDataBufferBase l_data_bufferx1_64(64);
-    ecmdDataBufferBase l_data_bufferx2_64(64);
-    ecmdDataBufferBase l_data_bufferx3_64(64);
-    ecmdDataBufferBase l_data_bufferx4_64(64);
-    uint64_t io_start_address = 0;
-    uint64_t io_end_address = 0;
-    uint8_t l_new_addr = 1;
-    uint32_t i_mcbpatt, i_mcbtest;
-
-    mcbist_test_mem i_mcbtest1;
-    mcbist_data_gen i_mcbpatt1;
-    i_mcbtest1 = CENSHMOO;
-    i_mcbpatt1 = ABLE_FIVE;
-
-    uint8_t l_index = 0;
-    uint8_t l_flag = 0;
-    uint64_t scom_array[8] = {
-        MBA01_MBABS0_0x03010440, MBA01_MBABS1_0x03010441,
-        MBA01_MBABS2_0x03010442, MBA01_MBABS3_0x03010443,
-        MBA01_MBABS4_0x03010444, MBA01_MBABS5_0x03010445,
-        MBA01_MBABS6_0x03010446, MBA01_MBABS7_0x03010447 };
-
-    uint64_t l_scom_array_MBS[16] = {
-        MBS_ECC0_MBSBS2_0x02011460, MBS_ECC0_MBSBS3_0x02011461,
-        MBS_ECC0_MBSBS4_0x02011462, MBS_ECC0_MBSBS5_0x02011463,
-        MBS_ECC0_MBSBS6_0x02011464, MBS_ECC0_MBSBS7_0x02011465,
-        MBS_ECC1_MBSBS0_0x0201149E, MBS_ECC1_MBSBS1_0x0201149F,
-        MBS_ECC1_MBSBS2_0x020114A0, MBS_ECC1_MBSBS3_0x020114A1,
-        MBS_ECC1_MBSBS4_0x020114A2, MBS_ECC1_MBSBS5_0x020114A3,
-        MBS_ECC1_MBSBS6_0x020114A4, MBS_ECC1_MBSBS7_0x020114A5,
-        MBS_ECC0_MBSBS0_0x0201145E, MBS_ECC0_MBSBS1_0x0201145F };
-
-    Target i_target_centaur;
-    rc = fapiGetParentChip(i_target_mba, i_target_centaur);
-    if (rc) return rc;
-
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_PATTERN, &i_target_mba, i_mcbpatt);
-    if (rc) return rc;//-----------i_mcbpatt------->run
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, i_mcbtest);
-    if (rc) return rc;//---------i_mcbtest------->run
-
-    rc = mss_conversion_testtype(i_target_mba, i_mcbtest, i_mcbtest1);
-    if (rc) return rc;
-    rc = mss_conversion_data(i_target_mba, i_mcbpatt, i_mcbpatt1);
-    if (rc) return rc;
-
-    rc = mcb_reset_trap(i_target_mba);
-    if (rc) return rc;
-    //shd set attr for this 1st 8 or last 8
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_ERROR_CAPTURE, &i_target_mba, l_bit32);
-    if (rc) return rc;
-    if (l_bit32 == 1)
-    {
-        FAPI_DBG("%s: error capture set to last 8 Bits", i_target_mba.toEcmdString());
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer_64);
-        if (rc) return rc;
-        rc_num = l_data_buffer_64.setBit(32);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  setup_mcbist:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-
-        rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer_64);
-        if (rc) return rc;
-
-        rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer_64);
-        if (rc) return rc;
-        rc_num = l_data_buffer_64.setBit(32);
-        if (rc_num)
-        {
-            FAPI_ERR("Buffer error in function setup_mcbist");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-
-        rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer_64);
-        if (rc) return rc;
-    }
-
-    rc = fapiGetScom(i_target_mba, 0x0301040d, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.clearBit(5);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function setup_mcbist");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target_mba, 0x0301040d, l_data_buffer_64);
-    if (rc) return rc;
-
-    //#RRQ FIFO Mode OFF
-    rc = fapiGetScom(i_target_mba, 0x0301040e, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.setBit(6);
-    rc_num |= l_data_buffer_64.setBit(7);
-    rc_num |= l_data_buffer_64.setBit(8);
-    rc_num |= l_data_buffer_64.setBit(9);
-    rc_num |= l_data_buffer_64.setBit(10);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function setup_mcbist");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target_mba, 0x0301040e, l_data_buffer_64);
-    if (rc) return rc;
-
-    //power bus ECC setting for random data
-    //# MBA01_MBA_WRD_MODE - disbale powerbus ECC checking and correction
-    rc = fapiGetScom(i_target_mba, 0x03010449, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.setBit(0);
-    rc_num |= l_data_buffer_64.setBit(1);
-    rc_num |= l_data_buffer_64.setBit(5);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function setup_mcbist");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, 0x03010449, l_data_buffer_64);
-    if (rc) return rc;
-    //# MBS_ECC01_MBSECCQ - set EEC checking On but ECC correction OFF
-    rc = fapiGetScom(i_target_centaur, 0x0201144a, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.clearBit(0);
-    rc_num |= l_data_buffer_64.setBit(1);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function setup_mcbist");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_centaur, 0x0201144a, l_data_buffer_64);
-    if (rc) return rc;
-
-    rc = fapiGetScom(i_target_centaur, 0x0201148a, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.clearBit(0);
-    rc_num |= l_data_buffer_64.setBit(1);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function setup_mcbist");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_centaur, 0x0201148a, l_data_buffer_64);
-    if (rc) return rc;
-
-    rc = fapiGetScom(i_target_mba, MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.clearBit(29);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function setup_mcbist");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target_mba, MBA01_CCS_MODEQ_0x030106a7, l_data_buffer_64);
-    if (rc) return rc;
-
-    for (l_index = 0; l_index < 8; l_index++)
-    {
-        rc = fapiGetScom(i_target_mba, scom_array[l_index], l_data_buffer_64);
-        if (rc) return rc;
-        l_flag = (l_data_buffer_64.getDoubleWord(0)) ? 1 : 0;
-        if (l_flag == 1)
-        {
-            break;
-        }
-    }
-
-    for (l_index = 0; l_index < 16; l_index++)
-    {
-        rc = fapiGetScom(i_target_centaur, l_scom_array_MBS[l_index], l_data_buffer_64);
-        if (rc) return rc;
-        l_flag = (l_data_buffer_64.getDoubleWord(0)) ? 1 : 0;
-        if (l_flag == 1)
-        {
-            break;
-        }
-    }
-
-    if (l_flag == 1)
-    {
-        FAPI_DBG("%s:WARNING: Bit Steering  is enabled !!!", i_target_mba.toEcmdString());
-    }
-    else
-    {
-        FAPI_DBG("%s:steer mode is not enabled", i_target_mba.toEcmdString());
-    }
-
-    rc = cfg_mcb_test_mem(i_target_mba, i_mcbtest1, l_sub_info);
-    if (rc) return rc;
-    rc = cfg_mcb_dgen(i_target_mba, i_mcbpatt1, i_mcbrotate, i_mcbrotdata);
-    if (rc) return rc;
-    uint8_t i_port = 0;
-    uint8_t i_rank = 0;
-
-  FAPI_DBG("%s:DEBUG-----Print----Address Gen ",i_target_mba.toEcmdString());
-  rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, l_new_addr);
-  if (rc) return rc;
-  FAPI_DBG("DEBUG----- l_new_addr = %d ",l_new_addr);
-
-    if (l_new_addr != 0)
-    {
-        rc = address_generation(i_target_mba, i_port, SF, BANK_RANK, i_rank,
-                                io_start_address, io_end_address, l_str_cust_addr);
-        if (rc)
-        {
-            FAPI_DBG("%s:BAD - RC ADDR Generation\n", i_target_mba.toEcmdString());
-            return rc;
-        }
-    }
-	
- FAPI_INF( "+++ Enabling Refresh +++");
-
-	rc = fapiGetScom(i_target_mba, 0x03010432, l_data_buffer_64);
-	if(rc) return rc;
-	//Bit 0 is enable		   
-	rc_num = rc_num | l_data_buffer_64.setBit(0);
-        if(rc_num)
-        {
-           rc.setEcmdError(rc_num);
-           return rc;
-        }
-	rc = fapiPutScom(i_target_mba, 0x03010432, l_data_buffer_64);
-        if(rc)return rc;
-        
-    if (i_mcbbytemask != NONE)
-    {
-        rc = cfg_byte_mask(i_target_mba);
-        if (rc) return rc;
-    }
-
-    return rc;
-}
-
-//*****************************************************************/
-// Funtion name : mcb_reset_trap
-// Description: Clears all the trap registers in MCBIST engine
-//Input Parameters :
-//     const fapi::Target &            centaur.mba
-//*****************************************************************/
-
-fapi::ReturnCode mcb_reset_trap(const fapi::Target & i_target_mba)
-{
-    ecmdDataBufferBase l_data_buffer_64(64);
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint8_t l_mbaPosition = 0;
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition);
-
-    Target i_target_centaur;
-    rc = fapiGetParentChip(i_target_mba, i_target_centaur);
-    if (rc) return rc;
-    FAPI_DBG("%s:Function - mcb_reset_trap", i_target_mba.toEcmdString());
-    //FAPI_DBG("%s:Using MCB Reset Trap Function -- This automatically resets error log RA, error counters, Status Reg and error map",i_target_mba.toEcmdString());
-    //Reset the MCBIST runtime counter
-    FAPI_DBG("%s:Clearing the MCBIST Runtime Counter ", i_target_mba.toEcmdString());
-    rc_num = l_data_buffer_64.flushTo0();
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  mcb_reset_trap:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiGetScom(i_target_mba, MBA01_MCBIST_RUNTIMECTRQ_0x030106b0, l_data_buffer_64);
-    if (rc) return rc;
-    rc_num = l_data_buffer_64.clearBit(0, 37);
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  mcb_reset_trap:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = fapiPutScom(i_target_mba, MBA01_MCBIST_RUNTIMECTRQ_0x030106b0, l_data_buffer_64);
-    if (rc) return rc;
-
-    //FAPI_DBG("%s:To clear Port error map registers ",i_target_mba.toEcmdString());
-    rc_num = l_data_buffer_64.flushTo0();
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  mcb_reset_trap:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer_64);
-    if (rc) return (rc);
-    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer_64);
-    if (rc) return (rc);
-    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer_64);
-    if (rc) return (rc);
-    rc = fapiPutScom(i_target_centaur, 0x02011772, l_data_buffer_64);
-    if (rc) return (rc);
-    rc = fapiPutScom(i_target_centaur, 0x02011773, l_data_buffer_64);
-    if (rc) return (rc);
-    rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer_64);
-    if (rc) return (rc);
-
-    return rc;
-}
-
-//*****************************************************************/
-// Funtion name : start_mcb
-// Description: Checks for dimms drop in the particular port & starts MCBIST
-//Input Parameters :
-//     const fapi::Target &            Centaur.mba
-//*****************************************************************/
-
-fapi::ReturnCode start_mcb(const fapi::Target & i_target_mba)
-{
-    ecmdDataBufferBase l_data_buffer_64(64);
-    ecmdDataBufferBase l_data_buffer_trap_64(64);
-    uint8_t l_num_ranks_per_dimm[2][2];
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    FAPI_DBG("%s:Function - start_mcb", i_target_mba.toEcmdString());
-
-    rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBAGRAQ_0x030106d6, l_data_buffer_64);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm);
-    if (rc) return rc;
-
-    if (l_num_ranks_per_dimm[0][0] > 0)
-    {
-        FAPI_DBG("%s: Socket 0 Configured", i_target_mba.toEcmdString());
-        rc_num = l_data_buffer_64.setBit(24);
-        rc_num |= l_data_buffer_64.clearBit(25);
-        if (rc_num)
-        {
-            FAPI_ERR("Buffer error in function start_mcb");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-    }
-    else if (l_num_ranks_per_dimm[0][1] > 0)
-    {
-        FAPI_DBG("%s: Socket 1 Configured", i_target_mba.toEcmdString());
-        rc_num = l_data_buffer_64.clearBit(24);
-        rc_num |= l_data_buffer_64.setBit(25);
-        if (rc_num)
-        {
-            FAPI_ERR("Buffer error in function start_mcb");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-    }
-    else if ((l_num_ranks_per_dimm[0][0] > 0) && (l_num_ranks_per_dimm[0][1] > 0))
-    {
-        FAPI_DBG("%s: Socket 0, 1 Configured", i_target_mba.toEcmdString());
-        rc_num = l_data_buffer_64.setBit(24);
-        rc_num |= l_data_buffer_64.setBit(25);
-        if (rc_num)
-        {
-            FAPI_ERR("Buffer error in function start_mcb");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-    }
-    else
-    {
-        FAPI_DBG("%s:No Socket found", i_target_mba.toEcmdString());
-    }
-
-    //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
-
-    rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBAGRAQ_0x030106d6, l_data_buffer_64);
-    if (rc) return rc;
-    FAPI_DBG("%s:STARTING MCBIST for Centaur Target", i_target_mba.toEcmdString());
-    rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc, l_data_buffer_64);
-    if (rc) return rc;
-
-    if (l_data_buffer_64.isBitSet(0))
-    {
-        FAPI_DBG("%s:MCBIST already in progess, wait till MCBIST completes",
-                 i_target_mba.toEcmdString());
-        return rc;
-    }
-
-    rc_num = l_data_buffer_64.flushTo0();
-    rc_num |= l_data_buffer_64.setBit(0);
-    if (rc_num)
-    {
-        FAPI_ERR("Buffer error in function start_mcb");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCB_CNTLQ_0x030106db, l_data_buffer_64);
-    if (rc) return rc;
-
-    //rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);if(rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
-
-    return rc;
-}
-
-//*****************************************************************/
-// Funtion name : poll_mcb
-// Description  : Will check the MCBIST Configuration Register for mcb fail, in progress
-//                fail. It will print the corresponding  centaur on which MCBIST has
-//                been completed, in progress or failed.
-// Input Parameters :
-//    const fapi::Target &             Centaur.mba
-//    bool           l_mcb_stop_on_fail       Whether MCBIST should stop on fail or not
-//    uint64_t i_time                          Sets the max Time out value
-// Output Parameter :
-//    uint32    status  = 1                 MCBIST done with fail or MCBIST not complete (default value)
-//                      = 0                 MCBIST Done without fail
-//****************************************************************/
-fapi::ReturnCode poll_mcb(const fapi::Target & i_target_mba,
-                          uint8_t *o_mcb_status,
-                          struct Subtest_info l_sub_info[30],
-                          uint8_t i_flag)
-{
-    fapi::ReturnCode rc; // return value after each SCOM access/buffer modification
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase l_data_buffer_64(64);
-    ecmdDataBufferBase l_data_buffer1_64(64);
-    ecmdDataBufferBase l_data_buffer_trap_64(64);
-    ecmdDataBufferBase l_stop_on_fail_buffer_64(64);
-    //Current status of the MCB (done, fail, in progress)
-    uint8_t l_mcb_done = 0;
-    uint8_t l_mcb_fail = 0;
-    uint8_t l_mcb_ip = 0;
-    //Time out variables
-    uint64_t l_mcb_timeout = 0;
-    uint32_t l_count = 0;
-    uint64_t l_time = 0;
-    uint32_t l_time_count = 0;
-    uint8_t l_index = 0;
-    uint8_t l_Subtest_no = 0;
-    uint64_t l_counter = 0x0ll;
-    uint32_t i_mcbtest = 0;
-    uint32_t l_st_ln = 0;
-    uint32_t l_len = 0;
-    uint32_t l_dts_0 = 0;
-    uint32_t l_dts_1 = 0;
-    uint8_t l_mcb_stop_on_fail = 0;
-    mcbist_test_mem i_mcbtest1;
-    Target i_target_centaur;
-    rc = fapiGetParentChip(i_target_mba, i_target_centaur);
-    if (rc) return rc;
-    // Clear to register to zero;
-
-    //Should get the attributes l_time
-    uint8_t test_array_count[44] = { 0, 2, 2, 1, 1, 1, 6, 6, 30, 30,
-                                     2, 7, 4, 2, 1, 5, 4, 2, 1, 1,
-                                     3, 1, 1, 4, 2, 1, 1, 1, 1, 10,
-                                     0, 5, 3, 3, 3, 3, 9, 4, 30, 1,
-                                     2, 2, 3, 3 };
-
-    FAPI_DBG("%s:Function Poll_MCBIST", i_target_mba.toEcmdString());
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, l_time);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_STOP_ON_ERROR, &i_target_mba, l_mcb_stop_on_fail);
-    if (rc) return rc;
-
-    if (l_time == 0x0000000000000000)
-    {
-        l_time = MCB_MAX_TIMEOUT;
-    }
-    FAPI_DBG("%s:Value  of max time %016llX", i_target_mba.toEcmdString(), l_time);
-
-    while ((l_mcb_done == 0) && (l_mcb_timeout <= l_time))
-    {
-        rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES);
-        if (rc) return rc; // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
-        rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc, l_data_buffer_64);
-        if (rc) return rc;
-        if (l_data_buffer_64.isBitSet(0))
-        {
-            l_time_count++;
-            if (l_time_count == 500)
-            {
-                l_time_count = 0;
-                FAPI_DBG("%s:POLLING STATUS:POLLING IN PROGRESS...........",
-                         i_target_mba.toEcmdString());
-		#ifdef FAPI_MSSLABONLY
-		rc = mss_cen_dimm_temp_sensor(i_target_centaur);if (rc) return rc;
-		#endif
-		rc = fapiGetScom(i_target_centaur, 0x02050000, l_data_buffer_64);if (rc) return rc;
-                rc_num = l_data_buffer_64.extractToRight(&l_dts_0, 0, 12);
-                rc_num = rc_num | l_data_buffer_64.extractToRight(&l_dts_1, 16, 12);
-		if (rc_num)
-                {
-                     FAPI_ERR("Buffer error in function poll_mcb");
-                     rc.setEcmdError(rc_num);
-                     return rc;
-                 }
-
-                FAPI_DBG("%s:DTS Thermal Sensor 0 Results %d", i_target_centaur.toEcmdString(), l_dts_0);
-                FAPI_DBG("%s:DTS Thermal Sensor 1 Results %d", i_target_centaur.toEcmdString(), l_dts_1);
-		
-                if (i_flag == 0)
-                {
-                    // Read Counter Reg
-                    
-                    rc = fapiGetScom(i_target_mba, 0x030106b0, l_data_buffer_64);
-                    if (rc) return rc;
-                    l_counter = l_data_buffer_64.getDoubleWord (0);
-                   
-                   FAPI_DBG("%s:MCBCounter  %016llX  ", i_target_mba.toEcmdString(), l_counter);
-                    
-                    //Read Sub-Test number
-                    rc = fapiGetScom(i_target_centaur, 0x02011670, l_data_buffer_64);
-                    if (rc) return rc;
-                    l_st_ln = 3;
-                    l_len = 5;
-                    rc_num = l_data_buffer_64.extract(&l_Subtest_no, l_st_ln, l_len);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Buffer error in function poll_mcb");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                     
-                    //FAPI_DBG("%s:SUBTEST No  %08x  ", i_target_mba.toEcmdString(), l_Subtest_no);
-                    rc = FAPI_ATTR_GET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, i_mcbtest);
-                    if (rc) return rc;//---------i_mcbtest------->run
-                    rc = mss_conversion_testtype(i_target_mba, i_mcbtest, i_mcbtest1);
-                    if (rc) return rc;
-
-                    //l_Subtest_no = Extracted value from 3 to 7
-                    l_index = test_array_count[i_mcbtest];
-                    //FAPI_DBG("%s:INDEX No  %d  ",l_index);
-
-                    if (l_Subtest_no < l_index)
-                    {
-                        switch (l_sub_info[l_Subtest_no].l_operation_type)
-                        {
-                        case 0:
-                            FAPI_DBG("%s:SUBTEST        :WRITE", i_target_mba.toEcmdString());
-                            break;
-                        case 1:
-                            FAPI_DBG("%s:SUBTEST        :READ", i_target_mba.toEcmdString());
-                            break;
-                        case 2:
-                            FAPI_DBG("%s:SUBTEST        :READ - WRITE", i_target_mba.toEcmdString());
-                            break;
-                        case 3:
-                            FAPI_DBG("%s:SUBTEST        :WRITE - READ", i_target_mba.toEcmdString());
-                            break;
-                        case 4:
-                            FAPI_DBG("%s:SUBTEST        :READ - WRITE - READ", i_target_mba.toEcmdString());
-                            break;
-                        case 5:
-                            FAPI_DBG("%s:SUBTEST        :READ - WRITE - WRITE", i_target_mba.toEcmdString());
-                            break;
-                        case 6:
-                            FAPI_DBG("%s:SUBTEST        :RANDOM COMMAND SEQUENCE", i_target_mba.toEcmdString());
-                            break;
-                        case 7:
-                            FAPI_DBG("%s:SUBTEST        :GOTO SUBTEST N OR REFRESH ONLY", i_target_mba.toEcmdString());
-                            break;
-                        default:
-                            FAPI_DBG("%s:Wrong Operation selected for Subtest", i_target_mba.toEcmdString());
-                        }
-
-                        switch (l_sub_info[l_Subtest_no].l_data_mode)
-                        {
-                        case 0:
-                            FAPI_DBG("%s:DATA MODE      :FIXED DATA", i_target_mba.toEcmdString());
-                            break;
-                        case 1:
-                            FAPI_DBG("%s:DATA MODE      :DATA_RANDOM_FORWARD", i_target_mba.toEcmdString());
-                            break;
-                        case 2:
-                            FAPI_DBG("%s:DATA MODE      :DATA_RANDOM_REVERSE", i_target_mba.toEcmdString());
-                            break;
-                        case 3:
-                            FAPI_DBG("%s:DATA MODE      :RANDOM w/ECC FORWARD", i_target_mba.toEcmdString());
-                            break;
-                        case 4:
-                            FAPI_DBG("%s:DATA MODE      :RANDOM w/ECC REVERSE", i_target_mba.toEcmdString());
-                            break;
-                        case 5:
-                            FAPI_DBG("%s:DATA MODE      :DATA EQUAL ADDRESS", i_target_mba.toEcmdString());
-                            break;
-                        case 6:
-                            FAPI_DBG("%s:DATA MODE      :DATA ROTATE LEFT", i_target_mba.toEcmdString());
-                            break;
-                        case 7:
-                            FAPI_DBG("%s:DATA MODE      :DATA ROTATE RIGHT", i_target_mba.toEcmdString());
-                            break;
-                        default:
-                            FAPI_DBG("%s:Wrong Data Mode selected for Subtest", i_target_mba.toEcmdString());
-                        }
-
-                        switch (l_sub_info[l_Subtest_no].l_addr_mode)
-                        {
-                        case 0:
-                            FAPI_DBG("%s:ADDRESS MODE   :SEQUENTIAL FORWARD", i_target_mba.toEcmdString());
-                            break;
-                        case 1:
-                            FAPI_DBG("%s:ADDRESS MODE   :SEQUENTIAL REVERSE", i_target_mba.toEcmdString());
-                            break;
-                        case 2:
-                            FAPI_DBG("%s:ADDRESS MODE   :RANDOM FORWARD", i_target_mba.toEcmdString());
-                            break;
-                        case 3:
-                            FAPI_DBG("%s:ADDRESS MODE   :RANDOM REVERSE", i_target_mba.toEcmdString());
-                            break;
-                        default:
-                            FAPI_DBG("%s:Wrong Address Mode selected for Subtest", i_target_mba.toEcmdString());
-                        }
-                    }
-                }
-            }
-            l_mcb_ip = 1;
-        }
-        if (l_data_buffer_64.isBitSet(1))
-        {
-            FAPI_DBG("%s:POLLING STATUS:MCBIST POLLING DONE",
-                     i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MCBIST is done", i_target_mba.toEcmdString());
-            l_mcb_ip = 0;
-            l_mcb_done = 1;
-
-            rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer_64.clearBit(60);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  Poll_mcb:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64);
-            if (rc) return rc;
-
-        }
-        if (l_data_buffer_64.isBitSet(2))
-        {
-            l_mcb_fail = 1;
-            FAPI_DBG("%s:POLLING STATUS:MCBIST FAILED", i_target_mba.toEcmdString());
-
-            if (l_mcb_stop_on_fail == 1) //if stop on error is 1, break after the current subtest completes
-            {
-                rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_stop_on_fail_buffer_64);
-                if (rc) return rc;
-                rc_num = l_stop_on_fail_buffer_64.setBit(62);
-                if (rc_num)
-                {
-                    FAPI_ERR("Error in function  poll_mcb:");
-                    rc.setEcmdError(rc_num);
-                    return rc;
-                } // Set bit 61 to break after current subtest
-                rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0,
-                                 l_stop_on_fail_buffer_64);
-                if (rc) return rc;
-                FAPI_DBG("%s:MCBIST will break after Current Subtest",
-                         i_target_mba.toEcmdString());
-
-                while (l_mcb_done == 0) // Poll till MCBIST is done
-                {
-                    rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCB_CNTLSTATQ_0x030106dc, l_data_buffer_64);
-                    if (rc) return rc;
-                    if (l_data_buffer_64.isBitSet(1))
-                    {
-                        l_mcb_ip = 0;
-                        l_mcb_done = 1;
-
-                        rc = fapiGetScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64);
-                        if (rc) return rc;
-                        rc_num = l_data_buffer_64.clearBit(60);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  Poll_mcb:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_data_buffer_trap_64);
-                        if (rc) return rc;
-
-                        FAPI_DBG("%s:MCBIST Done", i_target_mba.toEcmdString());
-                        rc_num = l_stop_on_fail_buffer_64.clearBit(62);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  poll_mcb:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        } // Clearing bit 61 to avoid breaking after current subtest
-                        rc = fapiPutScom(i_target_mba, MBA01_MCBIST_MCBCFGQ_0x030106e0, l_stop_on_fail_buffer_64);
-                        if (rc) return rc;
-                    }
-                }
-            }
-        }
-        l_mcb_timeout++;
-        if (l_mcb_timeout >= l_time)
-        {
-            FAPI_ERR("poll_mcb:Maximun time out");
-            const fapi::Target & MBA_CHIPLET = i_target_mba;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_MCBIST_TIMEOUT_ERROR);
-            return rc;
-        }
-
-#ifdef MCB_DEBUG_1
-        //if((l_count%100 == 0)&&(l_print == 0))//Can be changed later
-        if(l_count%100 == 0)
-        {
-            FAPI_DBG("%s:MCB done bit : l_mcb_done",i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MCB fail bit : l_mcb_fail",i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MCB IP   bit : l_mcb_ip",i_target_mba.toEcmdString());
-        }
-#endif
-        l_count++;
-    }
-
-    if ((l_mcb_done == 1) && (l_mcb_fail == 1) && (l_mcb_stop_on_fail == true))
-    {
-        *o_mcb_status = 1; /// MCB fail
-#ifdef MCB_DEBUG_2
-        FAPI_DBG("%s:*************************************************",i_target_mba.toEcmdString());
-        FAPI_DBG("%s:MCB done bit : %d",i_target_mba.toEcmdString(),l_mcb_done);
-        FAPI_DBG("%s:MCB fail bit : %d",i_target_mba.toEcmdString(),l_mcb_fail);
-        FAPI_DBG("%s:MCB IP   bit : %d",i_target_mba.toEcmdString(),l_mcb_ip);
-        FAPI_DBG("%s:*************************************************",i_target_mba.toEcmdString());
-#endif
-    }
-    else if ((l_mcb_done == 1) && (l_mcb_fail == 0))
-    {
-        *o_mcb_status = 0;//pass;
-#ifdef MCB_DEBUG2
-        FAPI_DBG("%s:*************************************************",
-                 i_target_mba.toEcmdString());
-        FAPI_DBG("%s:MCB done bit : %d", i_target_mba.toEcmdString(),
-                 l_mcb_done);
-        FAPI_DBG("%s:MCB fail bit : %d", i_target_mba.toEcmdString(),
-                 l_mcb_fail);
-        FAPI_DBG("%s:MCB IP   bit : %d", i_target_mba.toEcmdString(), l_mcb_ip);
-        FAPI_DBG("%s:*************************************************",
-                 i_target_mba.toEcmdString());
-#endif
-    }
-    else if ((l_mcb_done == 0) && (l_mcb_ip == 1) && (l_mcb_timeout == l_time))
-    {
-        *o_mcb_status = 1;//fail;
-#ifdef MCB_DEBUG2
-        FAPI_DBG("%s:****************************************",
-                 i_target_mba.toEcmdString());
-        FAPI_DBG("%s:MCB done bit : %d", i_target_mba.toEcmdString(),
-                 l_mcb_done);
-        FAPI_DBG("%s:MCB fail bit : %d", i_target_mba.toEcmdString(),
-                 l_mcb_fail);
-        FAPI_DBG("%s:MCB IP   bit : %d", i_target_mba.toEcmdString(), l_mcb_ip);
-        FAPI_DBG("%s:****************************************",
-                 i_target_mba.toEcmdString());
-
-#endif
-    }
-
-    if (*o_mcb_status == 1)
-    {
-        FAPI_DBG("poll_mcb:MCBIST failed");
-	return rc;
-    }
-
-    return rc;
-}
-fapi::ReturnCode mcb_error_map_print(const fapi::Target & i_target_mba,
-                                     ecmdDataBufferBase & i_mcb_fail_160,
-                                     uint8_t i_port,
-                                     uint8_t i_array[80],
-                                     uint8_t i_number,
-                                     ecmdDataBufferBase i_data_buf_port,
-                                     ecmdDataBufferBase i_data_buf_spare)
-{
-    ReturnCode rc;
-    uint32_t rc_num=0;
-    uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT];
-    uint8_t l_rankpair_table[MAX_RANK];
-    uint8_t l_cur_rank = 0;
-    uint16_t l_index0, l_index1, l_byte, l_nibble;
-    uint8_t l_max_rank = 0;
-    uint8_t l_rank_pair = 0;
-    char l_str1[200] = "";
-    ecmdDataBufferBase l_mcb(64);
-    uint8_t i_rank = 0;
-    uint8_t l_mbaPosition = 0;
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba,
-                       l_num_ranks_per_dimm);
-    if (rc) return rc;
-    l_max_rank = l_num_ranks_per_dimm[i_port][0] + l_num_ranks_per_dimm[i_port][1];
-
-    uint64_t l_generic_buffer;
-    uint32_t l_sbit, l_len;
-    uint16_t l_output;
-
-    rc = mss_getrankpair(i_target_mba, i_port, 0, &l_rank_pair, l_rankpair_table);
-    if (rc) return rc;
-    if (l_max_rank == 0)
-    {
-        FAPI_DBG("%s: NO RANK FOUND ON PORT %d ", i_target_mba.toEcmdString(), i_port);
-        return rc;
-    }
-    else
-    {
-        for (l_cur_rank = 0; l_cur_rank < l_max_rank; l_cur_rank++)
-        {
-            i_rank = l_rankpair_table[l_cur_rank];
-            //FAPI_DBG("%s:i am rank  %d cur_index %d",i_target_mba.toEcmdString(),i_rank,l_cur_rank);
-            if (i_rank > MAX_RANK)
-            {
-                break;
-            }
-        }
-    }
-
-    if (i_port == 0)
-    {
-        if (l_mbaPosition == 0)
-        {
-            l_sbit = 0;
-            l_len = 16;
-            l_generic_buffer = i_data_buf_port.getDoubleWord(0);
-            rc_num |= i_data_buf_spare.extractToRight(&l_output, l_sbit, l_len);
-            FAPI_DBG("%s:################# MBA01 ###########################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:################# PORT0  ERROR MAP #################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Byte      00112233445566778899", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Nibble    01010101010101010101", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MASK      %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output);
-        }
-        else
-        {
-            l_sbit = 0;
-            l_len = 16;
-            l_generic_buffer = i_data_buf_port.getDoubleWord(0);
-            rc_num |= i_data_buf_spare.extractToRight(&l_output, l_sbit, l_len);
-            FAPI_DBG("%s:################# MBA23 ###########################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:################# PORT0 ERROR MAP #################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Byte      00112233445566778899", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Nibble    01010101010101010101", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MASK      %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output);
-        }
-    }
-    else
-    {
-        if (l_mbaPosition == 0)
-        {
-            l_sbit = 16;
-            l_len = 16;
-            l_generic_buffer = i_data_buf_port.getDoubleWord(0);
-            rc_num |= i_data_buf_spare.extractToRight(&l_output, l_sbit, l_len);
-            FAPI_DBG("%s:################# MBA01 ###########################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:################# PORT1 ERROR MAP #################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Byte      00112233445566778899", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Nibble    01010101010101010101", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MASK      %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output);
-        }
-        else
-        {
-            l_sbit = 16;
-            l_len = 16;
-            l_generic_buffer = i_data_buf_port.getDoubleWord(0);
-            rc_num = rc_num | i_data_buf_spare.extractToRight(&l_output,
-                                                              l_sbit, l_len);
-            FAPI_DBG("%s:################# MBA23 ###########################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:################# PORT1 ERROR MAP #################\n", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Byte      00112233445566778899", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:Nibble    01010101010101010101", i_target_mba.toEcmdString());
-            FAPI_DBG("%s:MASK      %016llX%04X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output);
-        }
-    }
-
-    uint8_t l_index, l_value, l_value1;
-    uint8_t l_marray0[80] = { 0 };
-    ecmdDataBufferBase l_data_buffer1_64(64), l_data_buffer3_64(64);
-
-    rc_num |= l_data_buffer1_64.flushTo0();
-    //FAPI_ERR("Buffer error in function mcb_error_map_print");
-	
-	if (rc_num) //The check for if bad rc_num was misplaced
-        {
-            FAPI_ERR("Error in function  mcb_error_map_print:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-
-    uint8_t l_num, io_num, l_inter, l_num2, l_index2;
-    l_num = 0;
-    //FAPI_INF("%s:l_max_rank%d",i_target_mba.toEcmdString(),l_max_rank);
-    //FAPI_INF("%s:rank:%d",i_target_mba.toEcmdString(),i_rank);
-    for (l_index = 0; l_index < i_number; l_index++)
-    {
-        l_value = i_array[l_index];
-        l_inter = (l_value / 4);
-        l_num2 = l_num - 1;
-        if (l_inter == l_marray0[l_num2] && (l_num != 0))
-        {
-            continue;
-        }
-
-        l_value1 = l_inter;
-        l_marray0[l_num] = l_value1;
-        l_num++;
-        //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num);
-    }
-
-    //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num);
-    io_num = l_num;
-
-    //To be in error map print function
-
-    //Debug Prints
-    /*
-     uint8_t l_i;
-     l_i = 0;
-
-
-     FAPI_INF("________________________________________________________________________________________________________");
-     for(l_i = 0;l_i < i_number;l_i++)
-     {
-     FAPI_INF("%s:INITIAL ARRAY:%d",i_target_mba.toEcmdString(),i_array[l_i] );
-     }
-     FAPI_INF("________________________________________________________________________________________________________");
-     for(l_i = 0;l_i < io_num;l_i++)
-     {
-     FAPI_INF("%s:FINAL ARRAY:%d",i_target_mba.toEcmdString(),l_marray0[l_i] );
-     }
-     FAPI_INF("________________________________________________________________________________________________________");*/
-
-    l_cur_rank = 0;
-    i_rank = 0;
-    l_num = 0;
-    l_value = 0;
-
-    //FAPI_DBG("%s:          --------------------",i_target_mba.toEcmdString());
-
-    rc = mss_getrankpair(i_target_mba, i_port, 0, &l_rank_pair, l_rankpair_table);
-    if (rc) return rc;
-    for (l_cur_rank = 0; l_cur_rank < l_max_rank; l_cur_rank++)
-    {
-        l_index2 = 0;
-        l_num = 0;
-        i_rank = l_rankpair_table[l_cur_rank];
-        sprintf(l_str1, "%s:%-4s%d%5s", i_target_mba.toEcmdString(), "RANK", i_rank, "");
-        for (l_byte = 0; l_byte < MAX_BYTE; l_byte++)
-        {
-            for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++)
-            {
-                l_value = l_marray0[l_num];
-                //FAPI_DBG("%s:l_value %d l_num %d",i_target_mba.toEcmdString(),l_value,l_num);
-                l_index0 = (i_rank * 20) + (l_byte * 2) + l_nibble;
-                l_index2 = (l_byte * 2) + l_nibble;
-                l_index1 = l_index0;
-                if ((l_value == l_index2) && (l_num < io_num))
-                {
-                    strcat(l_str1, "M");
-                    //FAPI_DBG("%s:l_value %d l_num %d",i_target_mba.toEcmdString(),l_value,l_num);
-                    l_num++;
-                }
-                else
-                {
-                    if (i_mcb_fail_160.isBitSet(l_index1))
-                    {
-                        strcat(l_str1, "X");
-                    }
-                    else
-                    {
-                        strcat(l_str1, ".");
-                    }
-                }
-            }
-        }
-        FAPI_DBG("%s", l_str1);
-    }
-
-    return rc;
-}
-
-/*****************************************************************/
-// Funtion name : mcb_error_map
-// Description  : Reads the nibblewise Error map registers into o_error_map
-// Input Parameters :
-//    const fapi::Target &             Centaur.mba
-//    uint8_t i_port                   Current port
-//    uint8_t i_rank                   Current Rank
-// Output Parameter :
-//    uint8_t o_error_map[][8][10][2]   Contains the error map
-//****************************************************************/
-fapi::ReturnCode mcb_error_map(const fapi::Target & i_target_mba,
-                               uint8_t o_error_map[][8][10][2],
-                               uint8_t i_CDarray0[80],
-                               uint8_t i_CDarray1[80],
-                               uint8_t count_bad_dq[2])
-{
-    ecmdDataBufferBase l_mcbem1ab(64);
-    ecmdDataBufferBase l_mcbem2ab(64);
-    ecmdDataBufferBase l_mcbem3ab(64);
-    ecmdDataBufferBase l_data_buffer_64(64);
-
-    ecmdDataBufferBase l_mcb_fail_320(320);
-    ecmdDataBufferBase l_mcb_fail_160(160);
-    ecmdDataBufferBase l_mcb_fail1_160(160);
-    ecmdDataBufferBase l_mcb(64);
-    ecmdDataBufferBase l_ISDIMM_BUF1(64), l_ISDIMM_BUF0(64);
-    ecmdDataBufferBase l_ISDIMM_spare1(8), l_ISDIMM_spare0(8);
-    uint8_t l_max_rank0, l_max_rank1;
-
-    uint8_t i_rank, i_port;
-    fapi::Target i_target_centaur;
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint16_t l_index0 = 0;
-    uint32_t l_index1 = 0;
-    uint8_t l_port = 0;
-    uint8_t l_rank = 0;
-    uint8_t l_byte = 0;
-    uint8_t l_nibble = 0;
-    uint8_t l_num_ranks_per_dimm[MAX_PORT][MAX_PORT];
-    uint8_t l_mbaPosition = 0;
-    uint8_t rank_pair, i_byte, i_nibble, i_input_index_u8, o_val, i_byte1, i_nibble1;
-
-    uint8_t l_index, l_i, l_number, l_value, l_value1, l_number1;//l_cur_rank,
-    l_number1 = 0; //HB
-    uint8_t l_array[80] = { 0 };
-    uint8_t l_marray11[80] = { 0 };
-    uint8_t l_array0[80] = { 0 };
-    uint8_t l_marray0[80] = { 0 };
-    uint8_t l_array1[80] = { 0 };
-    uint8_t l_marray1[80] = { 0 };
-    uint8_t l_marray[80] = { 0 };
-    uint8_t cdimm_dq0[72] = { 0 };
-    uint8_t cdimm_dq1[72] = { 0 };
-    uint8_t cdimm_dq[80] = { 0 };
-    uint8_t l_ISarray1[80] = { 0 };
-    uint8_t l_ISarray0[80] = { 0 };
-    uint8_t l_ISarray[80] = { 0 };
-    uint8_t l_rankpair_table[MAX_RANK];
-    ecmdDataBufferBase l_data_buffer1_64(64), l_data_buffer3_64(64),
-        l_data_buf_port0(64), l_data_buf_port1(64), l_data_buf_spare(64);
-    uint64_t l_generic_buffer0, l_generic_buffer1, l_generic_buffer;
-    uint32_t l_sbit, l_len;
-    uint8_t l_output0, l_output1, l_output, l_j;
-
-    input_type l_input_type_e = ISDIMM_DQ;
-    uint8_t valid_rank[MAX_RANK];
-    char l_str[200] = "";
-    uint8_t l_max_bytes = 9;
-    uint8_t l_max_rank;
-    uint8_t l_attr_eff_dimm_type_u8;
-    FAPI_DBG("%s:Function MCB_ERROR_MAP", i_target_mba.toEcmdString());
-
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition);
-    if (rc)
-    {
-        FAPI_ERR("Error getting MBA position");
-        return rc;
-    }
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba,
-                       l_num_ranks_per_dimm);
-    if (rc) return rc;
-
-    l_max_rank0 = l_num_ranks_per_dimm[0][0] + l_num_ranks_per_dimm[0][1];
-    l_max_rank1 = l_num_ranks_per_dimm[1][0] + l_num_ranks_per_dimm[1][1];
-
-    rc = fapiGetParentChip(i_target_mba, i_target_centaur);
-    if (rc)
-    {
-        FAPI_ERR("Error in getting Parent Chiplet");
-        return rc;
-    }
-
-    if (l_mbaPosition == 0)
-    {
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMA1Q_0x0201166a, l_mcbem1ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail_160.insert(l_mcbem1ab, 0, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMA2Q_0x0201166b, l_mcbem2ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail_160.insert(l_mcbem2ab, 60, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMA3Q_0x0201166c, l_mcbem3ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail_160.insert(l_mcbem3ab, 120, 40, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMB1Q_0x0201166d, l_mcbem1ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail1_160.insert(l_mcbem1ab, 0, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMB2Q_0x0201166e, l_mcbem2ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail1_160.insert(l_mcbem2ab, 60, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBEMB3Q_0x0201166f, l_mcbem3ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail1_160.insert(l_mcbem3ab, 120, 40, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-    }
-    else if (l_mbaPosition == 1)
-    {
-        rc = fapiGetScom(i_target_centaur, 0x0201176a, l_mcbem1ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail_160.insert(l_mcbem1ab, 0, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, 0x0201176b, l_mcbem2ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail_160.insert(l_mcbem2ab, 60, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, 0x0201176c, l_mcbem3ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail_160.insert(l_mcbem3ab, 120, 40, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, 0x0201176d, l_mcbem1ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail1_160.insert(l_mcbem1ab, 0, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, 0x0201176e, l_mcbem2ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail1_160.insert(l_mcbem2ab, 60, 60, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-        rc = fapiGetScom(i_target_centaur, 0x0201176f, l_mcbem3ab);
-        if (rc) return rc;
-        rc_num = l_mcb_fail1_160.insert(l_mcbem3ab, 120, 40, 0);
-        if (rc_num)
-        {
-            FAPI_ERR("Error in function  mcb_error_map:");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-    }
-
-    for (l_port = 0; l_port < MAX_PORT; l_port++)
-    {
-        rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, valid_rank);
-        if (rc) return rc;
-
-        if (l_port == 0)
-        {
-            l_max_rank = l_max_rank0;
-        }
-        else
-        {
-            l_max_rank = l_max_rank1;
-        }
-
-        for (l_rank = 0; l_rank < l_max_rank; l_rank++)
-        {
-            i_rank = valid_rank[l_rank];
-
-            for (l_byte = 0; l_byte < MAX_BYTE; l_byte++)
-            {
-                for (l_nibble = 0; l_nibble < MAX_NIBBLES; l_nibble++)
-                {
-                    if (l_port == 0)
-                    {
-                        l_index0 = (i_rank * 20) + (l_byte * 2) + l_nibble;
-                        l_index1 = l_index0;
-
-                        if ((l_mcb_fail_160.isBitSet(l_index1)))
-                        {
-                            o_error_map[l_port][i_rank][l_byte][l_nibble] = 1;
-                        }
-                        else
-                        {
-                            o_error_map[l_port][i_rank][l_byte][l_nibble] = 0;
-                        }
-                    }
-                    else if (l_port == 1)
-                    {
-
-                        l_index0 = (i_rank * 20) + (l_byte * 2) + l_nibble;
-                        l_index1 = l_index0;
-                        if ((l_mcb_fail1_160.isBitSet(l_index1)))
-                        {
-
-                            o_error_map[l_port][i_rank][l_byte][l_nibble] = 1;
-                        }
-                        else
-                        {
-                            o_error_map[l_port][i_rank][l_byte][l_nibble] = 0;
-                        }
-                    }
-                }
-            }
-        }
-    }
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8);
-    if (rc) return rc;
-
-    l_i = 0;
-    rc_num = l_data_buffer1_64.flushTo0();
-    i_port = 0;
-
-    while (i_port < 2)
-    {
-        rc_num = l_data_buffer1_64.flushTo0();
-        rc_num = l_data_buffer3_64.flushTo0();
-        if (l_mbaPosition == 0)
-        {
-            if (i_port == 0)
-            {
-                //FAPI_INF("l_array:%d",l_i);
-                l_i = 0;
-                rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buf_port0);
-                if (rc)
-                    return rc;
-                rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buf_spare);
-                if (rc) return rc;
-                for (l_index = 0; l_index < 64; l_index++)
-                {
-                    if (l_data_buf_port0.isBitSet(l_index))
-                    {
-                        l_array0[l_i] = l_index;
-                        l_i++;
-                        //FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                for (l_index = 0; l_index < 16; l_index++)
-                {
-                    if (l_data_buf_spare.isBitSet(l_index))
-                    {
-                        l_array0[l_i] = l_index + 64;
-                        l_i++;
-                        //FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                l_number1 = l_i;
-            }
-
-            else
-            {
-                //FAPI_INF("l_array:%d",l_i);
-                l_i = 0;
-                rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buf_port1);
-                if (rc) return rc;
-                rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buf_spare);
-                if (rc) return rc;
-                for (l_index = 0; l_index < 64; l_index++)
-                {
-                    if (l_data_buf_port1.isBitSet(l_index))
-                    {
-                        l_array1[l_i] = l_index;
-                        l_i++;//FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                for (l_index = 16; l_index < 32; l_index++)
-                {
-                    if (l_data_buf_spare.isBitSet(l_index))
-                    {
-                        l_array1[l_i] = l_index + 64 - 16;
-                        l_i++;//FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                l_number = l_i;
-            }
-        }
-        else
-        {
-            if (i_port == 0)
-            {
-                //FAPI_INF("l_array:%d",l_i);
-                l_i = 0;
-                rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buf_spare);
-                if (rc) return rc;
-                rc = fapiGetScom(i_target_centaur, 0x02011772, l_data_buf_port0);
-                if (rc) return rc;
-                for (l_index = 0; l_index < 64; l_index++)
-                {
-                    if (l_data_buf_port0.isBitSet(l_index))
-                    {
-                        l_array0[l_i] = l_index;
-                        l_i++;//FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                for (l_index = 0; l_index < 16; l_index++)
-                {
-                    if (l_data_buf_spare.isBitSet(l_index))
-                    {
-                        l_array0[l_i] = l_index + 64;
-                        l_i++;//FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                l_number1 = l_i;
-            }
-            else
-            {
-                l_i = 0;
-                //FAPI_INF("l_array:%d",l_i);
-                rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buf_spare);
-                if (rc) return rc;
-                rc = fapiGetScom(i_target_centaur, 0x02011773, l_data_buf_port1);
-                if (rc) return rc;
-                for (l_index = 0; l_index < 64; l_index++)
-                {
-                    if (l_data_buf_port1.isBitSet(l_index))
-                    {
-                        l_array1[l_i] = l_index;
-                        l_i++;//FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                for (l_index = 16; l_index < 32; l_index++)
-                {
-                    if (l_data_buf_spare.isBitSet(l_index))
-                    {
-                        l_array1[l_i] = l_index + 64 - 16;
-                        l_i++;//FAPI_INF("l_array:%d",l_i);
-                    }
-                }
-                l_number = l_i;
-            }
-        }
-        i_port++;
-    }
-
-    //Conversion from CDIMM larray to ISDIMM larray
-    //port 0
-    for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++)
-    {
-        rc = rosetta_map(i_target_mba, 0, l_input_type_e, l_i, 0, o_val);
-        if (rc) return rc;
-        cdimm_dq0[o_val] = l_i;
-    }
-
-    //port 1
-    for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++)
-    {
-        rc = rosetta_map(i_target_mba, 1, l_input_type_e, l_i, 0, o_val);
-        if (rc) return rc;
-        cdimm_dq1[o_val] = l_i;
-    }
-
-    uint8_t l_num, io_num, io_num0, io_num1, l_inter, l_flag, l_n;
-    l_n = 0;
-    io_num0 = 0;
-    io_num1 = 0;
-
-    //FAPI_INF("%s:l_max_rank%d",i_target_mba.toEcmdString(),l_max_rank);
-    l_port = 0;
-    while (l_port < 2)
-    {
-        l_num = 0;
-        if (l_port == 0)
-        {
-            for (l_index = 0; l_index < l_number1; l_index++)
-            {
-                l_array[l_index] = l_array0[l_index];
-            }
-            l_n = l_number1;
-            rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, l_rankpair_table);
-            if (rc) return rc;
-
-            for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++)
-            {
-                cdimm_dq[l_i] = cdimm_dq0[l_i];
-            }
-        }
-        else
-        {
-            for (l_index = 0; l_index < l_number; l_index++)
-            {
-                l_array[l_index] = l_array1[l_index];
-                l_n = l_number;
-            }
-            rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, l_rankpair_table);
-            if (rc) return rc;
-
-            for (l_i = 0; l_i < MAX_ISDIMM_DQ; l_i++)
-            {
-                cdimm_dq[l_i] = cdimm_dq1[l_i];
-            }
-        }
-        //Getting array for converting CDIMM values as index and ISDIMM values as value of array for that index
-        for (l_index = 0; l_index < l_n; l_index++)
-        {
-            l_value = l_array[l_index];
-
-            l_value1 = cdimm_dq[l_value];
-            if (l_value >= 72)
-            {
-                l_value1 = 255;
-            }
-
-            l_ISarray[l_index] = l_value1;
-            //FAPI_INF("L_ISARRAY port %d index %d  value %d ",l_port,l_index,l_ISarray[l_index]);
-        }
-
-        if (l_attr_eff_dimm_type_u8 != ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-        {
-            //For ISDIMM marray
-            for (l_index = 0; l_index < l_n; l_index++)
-            {
-                l_value = l_ISarray[l_index];
-                l_inter = (l_value / 4);
-                l_value1 = l_num - 1;
-                l_marray[l_num] = l_inter * 4;
-                l_num++;
-                //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num);
-            }
-        }
-        else
-        {
-            //For CDIMM marray
-            for (l_index = 0; l_index < l_n; l_index++)
-            {
-                l_value = l_array[l_index];
-                l_inter = (l_value / 4);
-                l_value1 = l_num - 1;
-                l_marray[l_num] = l_inter * 4;
-                l_num++;
-                //FAPI_INF("%s:l_value,l_value1,l_num:%d,%d,%d",i_target_mba.toEcmdString(),l_value,l_value1,l_num);
-            }
-        }
-
-        //Loop to sort Masked ISDIMM array
-        for (l_i = 0; l_i < l_num - 1; l_i++)
-        {
-            for (l_j = l_i + 1; l_j < l_num; l_j++)
-            {
-                if (l_marray[l_i] > l_marray[l_j])
-                {
-                    l_value = l_marray[l_j];
-                    l_marray[l_j] = l_marray[l_i];
-                    l_marray[l_i] = l_value;
-                    //FAPI_INF("port %d value %d index %d",l_port,l_marray[l_i],l_i);
-                }
-            }
-        }
-
-        //loop to remove repetition elements
-        l_j = 0;
-        for (l_i = 0; l_i < l_num; l_i++)
-        {
-            l_flag = 0;
-
-            if ((l_marray[l_i] == l_marray[l_i + 1]) && (l_num != 0))
-            {
-                l_flag = 1;
-            }
-
-            if (l_flag == 0)
-            {
-                l_marray11[l_j] = l_marray[l_i];
-                l_j++;
-            }
-        }
-        l_num = l_j;
-
-        if (l_port == 0)
-        {
-            io_num0 = l_num;
-            if (io_num0 >= 21)
-            {
-                io_num0 = 21;
-            }
-            for (l_index = 0; l_index < io_num0; l_index++)
-            {
-                l_marray0[l_index] = l_marray11[l_index];
-            }
-
-            for (l_index = 0; l_index < l_number1; l_index++)
-            {
-
-                l_ISarray0[l_index] = l_ISarray[l_index];
-            }
-        }
-        else
-        {
-            io_num1 = l_num;
-            if (io_num1 >= 21)
-            {
-                io_num1 = 21;
-            }
-            for (l_index = 0; l_index < io_num1; l_index++)
-            {
-                l_marray1[l_index] = l_marray11[l_index];
-            }
-            for (l_index = 0; l_index < l_number; l_index++)
-            {
-
-                l_ISarray1[l_index] = l_ISarray[l_index];
-            }
-        }
-        l_port++;
-    }
-
-    count_bad_dq[0] = l_number1;
-    count_bad_dq[1] = l_number;
-    // FAPI_INF("\n abhijit's number is  number=%d and %d \n",count_bad_dq[0],count_bad_dq[1]);
-    for (l_i = 0; l_i < l_number1; l_i++)
-    {
-        i_CDarray0[l_i] = l_array0[l_i];
-    }
-    for (l_i = 0; l_i < l_number; l_i++)
-    {
-        i_CDarray1[l_i] = l_array1[l_i];
-    }
-
-    if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)  //Calling ISDIMM error mAP and LRDIMM
-    {
-        FAPI_DBG("%s:#################  Error MAP for ISDIMM #################",
-                 i_target_mba.toEcmdString());
-        for (l_port = 0; l_port < 2; l_port++)
-        {
-            if (l_port == 0)
-            {
-                l_max_rank = l_max_rank0;
-
-                io_num = io_num0;
-                for (l_index = 0; l_index < io_num; l_index++)
-                {
-                    l_marray[l_index] = l_marray0[l_index];
-                }
-            }
-            else
-            {
-                l_max_rank = l_max_rank1;
-
-                io_num = io_num1;
-                for (l_index = 0; l_index < io_num; l_index++)
-                {
-                    l_marray[l_index] = l_marray1[l_index];
-                }
-            }
-
-            if (l_max_rank == 0)
-            {
-                FAPI_DBG("%s: NO RANKS FOUND ON  PORT  %d", i_target_mba.toEcmdString(), l_port);
-            }
-            else
-            {
-                //To set the mask print in error map
-                l_value = 0;
-                if (l_port == 0)
-                {
-                    //For Port 0
-                    for (l_index = 0; l_index < l_number1; l_index++)
-                    {
-                        l_flag = 0;
-                        l_value = l_ISarray0[l_index];
-                        //FAPI_INF("Value is %d for index %d", l_value,l_index);
-                        if (l_value >= 72)
-                        {
-                            l_flag = 1;
-                            //FAPI_INF("Value (72)is here for index %d",l_index);
-                        }
-                        if ((l_value >= 64) && (l_value < 72))
-                        {
-                            l_value1 = l_value - 64;
-                            l_flag = 2;
-                            //FAPI_INF("Value (64)is here for index %d,l_value1 %d",l_index,l_value1);
-                            rc_num = l_ISDIMM_spare0.setBit(l_value1);
-                            if (rc_num)
-                            {
-                                FAPI_ERR("Error in function  Error Map:");
-                                rc.setEcmdError(rc_num);
-                                return rc;
-                            }
-                        }
-                        if (l_flag == 0)
-                        {
-                            rc_num = l_ISDIMM_BUF0.setBit(l_value);
-                            if (rc_num)
-                            {
-                                FAPI_ERR("Error in function  Error Map:");
-                                rc.setEcmdError(rc_num);
-                                return rc;
-                            }
-                        }
-                        //FAPI_INF("VALUE OF FLAG %d",l_flag);
-                    }
-
-                    l_generic_buffer0 = 0;
-                    l_output0 = 0;
-                    l_generic_buffer0 = l_ISDIMM_BUF0.getDoubleWord(0);
-                    l_sbit = 0;
-                    l_len = 8;
-                    rc_num |= l_ISDIMM_spare0.extractToRight(&l_output0, l_sbit, l_len);
-                    //FAPI_DBG("%s:MASK      %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer0,l_output0);
-                    l_generic_buffer = l_generic_buffer0;
-                    l_output = l_output0;
-                }
-                else
-                {
-                    for (l_index = 0; l_index < l_number; l_index++)
-                    {
-                        l_flag = 0;
-                        l_value = l_ISarray1[l_index];
-                        //FAPI_INF("Value is %d for index %d", l_value,l_index);
-                        if (l_value >= 72)
-                        {
-                            l_flag = 1;
-                            //FAPI_INF("Value (72)is here for index %d",l_index);
-                        }
-                        if ((l_value >= 64) && (l_value < 72))
-                        {
-                            l_value1 = l_value - 64;
-                            l_flag = 2;
-                            //FAPI_INF("Value (64)is here for index %d,l_value1 %d",l_index,l_value1);
-                            rc_num = l_ISDIMM_spare1.setBit(l_value1);
-                            if (rc_num)
-                            {
-                                FAPI_ERR("Error in function  Error Map:");
-                                rc.setEcmdError(rc_num);
-                                return rc;
-                            }
-                        }
-                        if (l_flag == 0)
-                        {
-                            rc_num = l_ISDIMM_BUF1.setBit(l_value);
-                            if (rc_num)
-                            {
-                                FAPI_ERR("Error in function  Error Map:");
-                                rc.setEcmdError(rc_num);
-                                return rc;
-                            }
-                        }
-                        //FAPI_INF("VALUE OF FLAG %d",l_flag);
-                    }
-
-                    l_generic_buffer1 = 0;
-                    l_output1 = 0;
-                    l_generic_buffer1 = l_ISDIMM_BUF1.getDoubleWord(0);
-                    l_sbit = 0;
-                    l_len = 8;
-                    rc_num |= l_ISDIMM_spare1.extractToRight(&l_output1, l_sbit, l_len);
-                    //FAPI_DBG("%s:MASK      %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer1,l_output1);
-                    l_generic_buffer = l_generic_buffer1;
-                    l_output = l_output1;
-                }
-
-                //Mask calculation Ends
-
-                if (l_mbaPosition == 0)
-                {
-                    //FAPI_DBG("%s:MASK      %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer0,l_output0);
-                    FAPI_DBG("%s:################# MBA01 ###########################\n", i_target_mba.toEcmdString());
-                    FAPI_DBG("%s:################# PORT%d ERROR MAP #################\n", i_target_mba.toEcmdString(), l_port);
-                    FAPI_DBG("%s:Byte      001122334455667788", i_target_mba.toEcmdString());
-                    FAPI_DBG("%s:Nibble    010101010101010101", i_target_mba.toEcmdString());
-                    FAPI_DBG("%s:MASK      %016llX%02X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output);
-                }
-                else
-                {
-                    //FAPI_DBG("%s:MASK      %016llX%02X\n",i_target_mba.toEcmdString(),l_generic_buffer1,l_output1);
-                    FAPI_DBG("%s:################# MBA23 ###########################\n", i_target_mba.toEcmdString());
-                    FAPI_DBG(
-                             "%s:################# PORT%d ERROR MAP #################\n",i_target_mba.toEcmdString(), l_port);
-                    FAPI_DBG("%s:Byte      001122334455667788", i_target_mba.toEcmdString());
-                    FAPI_DBG("%s:Nibble    010101010101010101", i_target_mba.toEcmdString());
-                    FAPI_DBG("%s:MASK      %016llX%02X\n", i_target_mba.toEcmdString(), l_generic_buffer, l_output);
-                }
-
-                for (l_rank = 0; l_rank < l_max_rank; l_rank++)
-                {
-                    l_num = 0;
-                    rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, valid_rank);
-                    if (rc) return rc;
-                    i_rank = valid_rank[l_rank];
-                    sprintf(l_str, "%s:%-4s%d%5s", i_target_mba.toEcmdString(), "RANK", i_rank, "");
-                    l_flag = 0;
-                    for (i_byte = 0; i_byte < l_max_bytes; i_byte++)
-                    {
-                        for (i_nibble = 0; i_nibble < 2; i_nibble++)
-                        {
-                            l_flag = 0;
-                            l_inter = l_marray[l_num];
-
-                            i_input_index_u8 = (8 * i_byte) + (4 * i_nibble);
-
-                            if ((l_inter == i_input_index_u8) && (l_num < io_num))
-                            {
-                                //FAPI_INF("l_flag %d,l_inter %d,i_input_index_u8 %d",l_flag,l_inter,i_input_index_u8);
-                                l_num++;
-                                l_flag = 1;
-                            }
-
-                            //FAPI_INF("l_flag %d,l_inter %d,i_input_index_u8 %d",l_flag,l_inter,i_input_index_u8);
-                            rc = rosetta_map(i_target_mba, l_port,
-                                             l_input_type_e, i_input_index_u8,
-                                             0, o_val);
-                            if (rc) return rc;
-                            i_byte1 = o_val / 8;
-                            i_nibble1 = o_val % 8;
-                            if (i_nibble1 > 3)
-                            {
-                                i_nibble1 = 1;
-                            }
-                            else
-                            {
-                                i_nibble1 = 0;
-                            }
-                            if (l_flag == 1)
-                            {
-                                strcat(l_str, "M");
-                            }
-                            else
-                            {
-                                if (o_error_map[l_port][i_rank][i_byte1][i_nibble1] == 1)
-                                {
-                                    strcat(l_str, "X");
-                                }
-                                else
-                                {
-                                    strcat(l_str, ".");
-                                }
-                            }
-                        }
-                    }
-                    FAPI_DBG("%s", l_str);
-                }
-            }
-        }
-    }
-
-    else //Calling CDIMM error Map print
-    {
-        FAPI_DBG("%s:################# CDIMM ERROR MAP ###########################\n", i_target_mba.toEcmdString());
-        i_port = 0;
-        mcb_error_map_print(i_target_mba, l_mcb_fail_160, i_port, l_array0,
-                            l_number1, l_data_buf_port0, l_data_buf_spare);
-
-        i_port = 1;
-        mcb_error_map_print(i_target_mba, l_mcb_fail1_160, i_port, l_array1,
-                            l_number, l_data_buf_port1, l_data_buf_spare);
-    }
-
-    return rc;
-}
-
-/*****************************************************************/
-// Funtion name : mcb_write_test_mem
-// Description  :   : Based on parameters passed we write data into Register being passed
-// Input Parameters :
-//    const fapi::Target &                     Centaur.mba
-//    const uint64_t i_reg_addr                 Register address
-//    mcbist_oper_type i_operation_type         Operation Type
-//    mcbist_addr_mode i_addr_mode              Sequential or Random address modes
-//    mcbist_data_mode i_data_mode              Data Mode
-//    uint8_t i_done                               Done Bit
-//   mcbist_data_select_mode i_data_select_mode Different BURST modes or DEFAULT
-//    mcbist_add_select_mode i_addr_select_mode Address Select mode
-//    uint8_t i_testnumber                      Subtest number
-//    uint8_t i_cfg_test_123_cmd                Integer value
-
-//****************************************************************/
-fapi::ReturnCode mcb_write_test_mem(const fapi::Target & i_target_mba,
-                                    const uint64_t i_reg_addr,
-                                    mcbist_oper_type i_operation_type,
-                                    uint8_t i_cfg_test_123_cmd,
-                                    mcbist_addr_mode i_addr_mode,
-                                    mcbist_data_mode i_data_mode,
-                                    uint8_t i_done,
-                                    mcbist_data_select_mode i_data_select_mode,
-                                    mcbist_add_select_mode i_addr_select_mode,
-                                    uint8_t i_testnumber,
-                                    uint8_t i_testnumber1,
-                                    uint8_t total_subtest_no,
-                                    struct Subtest_info l_sub_info[30])
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint8_t l_index = 0;
-    uint8_t l_operation_type = i_operation_type;
-    uint8_t l_cfg_test_123_cmd = i_cfg_test_123_cmd;
-    uint8_t l_addr_mode = i_addr_mode;
-    uint8_t l_data_mode = i_data_mode;
-    uint8_t l_data_select_mode = i_data_select_mode;
-    uint8_t l_addr_select_mode = i_addr_select_mode;
-    ecmdDataBufferBase l_data_buffer_64(64);
-
-    FAPI_DBG("%s:Function mcb_write_test_mem", i_target_mba.toEcmdString());
-    rc = fapiGetScom(i_target_mba, i_reg_addr, l_data_buffer_64);
-    if (rc) return rc;
-    l_index = i_testnumber * (MCB_TEST_NUM);
-
-    uint8_t l_done_bit;
-    rc = FAPI_ATTR_GET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, l_done_bit);
-    if (rc) return rc;
-    if (l_done_bit == 1)
-    {
-        return rc;
-    }
-
-    l_sub_info[i_testnumber1].l_operation_type = l_operation_type;
-    l_sub_info[i_testnumber1].l_data_mode = l_data_mode;
-    l_sub_info[i_testnumber1].l_addr_mode = l_addr_mode;
-
-    // Operation type
-    rc_num |= l_data_buffer_64.insertFromRight(l_operation_type, l_index, 3);
-    rc_num |= l_data_buffer_64.insertFromRight(l_cfg_test_123_cmd, l_index + 3, 3);
-    // ADDR MODE
-    rc_num |=  l_data_buffer_64.insertFromRight(l_addr_mode, l_index + 6, 2);
-    // DATA MODE
-    rc_num |= l_data_buffer_64.insertFromRight(l_data_mode, l_index + 8, 3);
-    // Done bit
-    rc_num |=  l_data_buffer_64.insertFromRight(i_done, l_index + 11, 1);
-    // Data Select Mode
-    rc_num |= l_data_buffer_64.insertFromRight(l_data_select_mode, l_index + 12, 2);
-
-    // Address Select mode
-    rc_num |= l_data_buffer_64.insertFromRight(l_addr_select_mode, l_index + 14, 2);
-
-    if (rc_num)
-    {
-        FAPI_ERR("Error in function  mcb_write_test_mem:");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target_mba, i_reg_addr, l_data_buffer_64);
-    if (rc) return rc;
-    rc = fapiGetScom(i_target_mba, i_reg_addr, l_data_buffer_64);
-    if (rc) return rc;
-
-    FAPI_DBG("%s:SUBTEST %d of %d in Progress.................... ",
-             i_target_mba.toEcmdString(), i_testnumber1, total_subtest_no);
-    //FAPI_DBG("%s:SUBTEST %d  in Progress.................... ",i_testnumber);
-    FAPI_DBG("%s:SUBTEST DETAILS", i_target_mba.toEcmdString());
-
-    switch (l_operation_type)
-    {
-    case 0:
-        FAPI_DBG("%s:SUBTEST        :WRITE", i_target_mba.toEcmdString());
-        break;
-    case 1:
-        FAPI_DBG("%s:SUBTEST        :READ", i_target_mba.toEcmdString());
-        break;
-    case 2:
-        FAPI_DBG("%s:SUBTEST        :READ - WRITE", i_target_mba.toEcmdString());
-        break;
-    case 3:
-        FAPI_DBG("%s:SUBTEST        :WRITE - READ", i_target_mba.toEcmdString());
-        break;
-    case 4:
-        FAPI_DBG("%s:SUBTEST        :READ - WRITE - READ", i_target_mba.toEcmdString());
-        break;
-    case 5:
-        FAPI_DBG("%s:SUBTEST        :READ - WRITE - WRITE", i_target_mba.toEcmdString());
-        break;
-    case 6:
-        FAPI_DBG("%s:SUBTEST        :RANDOM COMMAND SEQUENCE", i_target_mba.toEcmdString());
-        break;
-    case 7:
-        FAPI_DBG("%s:SUBTEST        :GOTO SUBTEST N OR REFRESH ONLY", i_target_mba.toEcmdString());
-        break;
-    default:
-        FAPI_DBG("%s:Wrong Operation selected for Subtest", i_target_mba.toEcmdString());
-    }
-
-    switch (l_data_mode)
-    {
-    case 0:
-        FAPI_DBG("%s:DATA MODE      :FIXED DATA", i_target_mba.toEcmdString());
-        break;
-    case 1:
-        FAPI_DBG("%s:DATA MODE      :DATA_RANDOM_FORWARD", i_target_mba.toEcmdString());
-        break;
-    case 2:
-        FAPI_DBG("%s:DATA MODE      :DATA_RANDOM_REVERSE", i_target_mba.toEcmdString());
-        break;
-    case 3:
-        FAPI_DBG("%s:DATA MODE      :RANDOM w/ECC FORWARD", i_target_mba.toEcmdString());
-        break;
-    case 4:
-        FAPI_DBG("%s:DATA MODE      :RANDOM w/ECC REVERSE", i_target_mba.toEcmdString());
-        break;
-    case 5:
-        FAPI_DBG("%s:DATA MODE      :DATA EQUAL ADDRESS", i_target_mba.toEcmdString());
-        break;
-    case 6:
-        FAPI_DBG("%s:DATA MODE      :DATA ROTATE LEFT", i_target_mba.toEcmdString());
-        break;
-    case 7:
-        FAPI_DBG("%s:DATA MODE      :DATA ROTATE RIGHT", i_target_mba.toEcmdString());
-        break;
-    default:
-        FAPI_DBG("%s:Wrong Data Mode selected for Subtest", i_target_mba.toEcmdString());
-    }
-
-    switch (l_addr_mode)
-    {
-    case 0:
-        FAPI_DBG("%s:ADDRESS MODE   :SEQUENTIAL FORWARD", i_target_mba.toEcmdString());
-        break;
-    case 1:
-        FAPI_DBG("%s:ADDRESS MODE   :SEQUENTIAL REVERSE", i_target_mba.toEcmdString());
-        break;
-    case 2:
-        FAPI_DBG("%s:ADDRESS MODE   :RANDOM FORWARD", i_target_mba.toEcmdString());
-        break;
-    case 3:
-        FAPI_DBG("%s:ADDRESS MODE   :RANDOM REVERSE", i_target_mba.toEcmdString());
-        break;
-    default:
-        FAPI_DBG("%s:Wrong Address Mode selected for Subtest", i_target_mba.toEcmdString());
-    }
-
-    FAPI_DBG("%s:SUBTEST %d of %d done ", i_target_mba.toEcmdString(),
-             i_testnumber1, total_subtest_no);
-
-    if (i_done == 1)
-    {
-        FAPI_DBG("%s:DONE BIT IS SET FOR CURRENT SUBTEST %d",
-                 i_target_mba.toEcmdString(), i_testnumber1);
-        //FAPI_DBG("%s:DONE BIT IS SET FOR CURRENT SUBTEST %d",i_testnumber);
-    }
-    if ((l_data_mode == 0) || (l_data_mode == 6) || (l_data_mode == 7)|| (l_data_mode == 5))
-    {
-        //FAPI_DBG("%s:fixed set and value of datamode is %d",l_data_mode);
-        l_sub_info[i_testnumber1].l_fixed_data_enable = 1;
-    }
-    else if ((l_data_mode == 1) || (l_data_mode == 2) || (l_data_mode == 3) || (l_data_mode == 4))
-    {
-        l_sub_info[i_testnumber1].l_random_data_enable = 1;
-        //FAPI_DBG("%s:random set and value of datamode is %d",l_data_mode);
-    }
-
-    if ((l_addr_mode == 0) || (l_addr_mode == 1))
-    {
-        //FAPI_DBG("fixed addr and value of addrmode is %d",l_addr_mode);
-        l_sub_info[i_testnumber1].l_fixed_addr_enable = 1;
-    }
-    else if ((l_addr_mode == 2) || (l_addr_mode == 3))
-    {
-        l_sub_info[i_testnumber1].l_random_addr_enable = 1;
-        //FAPI_DBG("random addr and value of addrmode is %d",l_addr_mode);
-    }
-    return rc;
-}
-
-/*****************************************************************/
-// Funtion name : cfg_byte_mask
-// Description  :
-// Input Parameters :  It is used to mask bad bits read from SPD
-//    const fapi::Target &                     Centaur.mba
-//    uint8_t i_rank                            Current Rank
-//    uint8_t i_port                            Current Port
-//****************************************************************/
-
-fapi::ReturnCode cfg_byte_mask(const fapi::Target & i_target_mba)
-{
-    uint32_t rc_num;
-    uint8_t l_port = 0;
-    uint8_t l_dimm = 0;
-    uint8_t l_rank = 0;
-    uint8_t l_max_0 = 0;
-    uint8_t l_max_1 = 0;
-    fapi::ReturnCode rc;
-    uint8_t l_rnk = 0;
-    uint8_t num_ranks_per_dimm[2][2];
-    uint8_t l_MAX_RANKS = 8;
-    uint8_t rank_pair = 0;
-    uint64_t l_var = 0xFFFFFFFFFFFFFFFFull;
-    uint16_t l_spare = 0xFFFF;
-    ecmdDataBufferBase l_data_buffer1_64(64);
-    Target i_target_centaur;
-    rc = fapiGetParentChip(i_target_mba, i_target_centaur);
-    if (rc) return rc;
-    uint8_t valid_rank[l_MAX_RANKS];
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm);
-    if (rc) return rc;
-    uint8_t l_mbaPosition = 0;
-    uint8_t l_attr_eff_dimm_type_u8 = 0;
-    rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_attr_eff_dimm_type_u8);
-    if (rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_mbaPosition);
-    if (rc) return rc;
-
-    for (l_port = 0; l_port < 2; l_port++)
-    {
-        l_MAX_RANKS = num_ranks_per_dimm[l_port][0] + num_ranks_per_dimm[l_port][1];
-        rc = mss_getrankpair(i_target_mba, l_port, 0, &rank_pair, valid_rank);
-        if (rc) return rc;
-
-        for (l_rank = 0; l_rank < l_MAX_RANKS; l_rank++)
-        {
-            l_rnk = valid_rank[l_rank];
-            if (l_rnk == 255)
-            {
-                continue;
-            }
-
-            ecmdDataBufferBase l_data_buffer2_64(64);
-            ecmdDataBufferBase l_data_buffer3_64(64);
-            ecmdDataBufferBase l_data_buffer4_64(64);
-            ecmdDataBufferBase l_data_buffer5_64(64);
-
-            l_max_0 = num_ranks_per_dimm[0][0] + num_ranks_per_dimm[0][1];
-            l_max_1 = num_ranks_per_dimm[1][0] + num_ranks_per_dimm[1][1];
-
-            rc_num = l_data_buffer3_64.flushTo0();
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE];
-            uint8_t l_dq[8] = { 0 };
-            uint8_t l_sp[2] = { 0 };
-            uint16_t l_index0 = 0;
-            uint8_t l_index_sp = 0;
-            uint16_t l_sp_isdimm = 0xff;
-
-            FAPI_DBG("%s:Function cfg_byte_mask", i_target_mba.toEcmdString());
-            if (l_rnk > 3)
-            {
-                l_dimm = 1;
-                l_rnk = l_rnk - 4;
-            }
-            else
-            {
-                l_dimm = 0;
-            }
-            rc = dimmGetBadDqBitmap(i_target_mba, l_port, l_dimm, l_rnk, l_dqBitmap);
-            if (rc) return rc;
-
-            for (l_index0 = 0; l_index0 < DIMM_DQ_RANK_BITMAP_SIZE; l_index0++)
-            {
-                if (l_index0 < 8)
-                {
-                    l_dq[l_index0] = l_dqBitmap[l_index0];
-                    if (l_dqBitmap[l_index0])
-                    {
-                        FAPI_DBG("%s:\n the port=%d  bad dq=%x on dq=%d",
-                                 i_target_mba.toEcmdString(), l_port,
-                                 l_dqBitmap[l_index0], l_index0);
-                    }
-                }
-                else
-                {
-                    if (l_dqBitmap[l_index0])
-                    {
-                        FAPI_DBG("%s:\n the port=%d  bad dq=%x on dq=%d",
-                                 i_target_mba.toEcmdString(), l_port,
-                                 l_dqBitmap[l_index0], l_index0);
-                    }
-                    l_sp[l_index_sp] = l_dqBitmap[l_index0];
-                    l_index_sp++;
-                }
-            }
-
-            rc_num = l_data_buffer1_64.insertFromRight(l_dq, 0, 64);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            if (l_mbaPosition == 0)
-            {
-                if (l_port == 0)
-                {
-                    if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 8, 8);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp, 0, 8);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    else
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp, 0, 16);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer4_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer1_64);
-                    if (rc) return rc;
-                    rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer5_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer2_64);
-                    if (rc) return rc;
-                }
-                else
-                {
-                    rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer2_64);
-                    if (rc) return rc;
-                    if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 24, 8);
-                        rc_num |= l_data_buffer2_64.insertFromRight(l_sp, 16, 8);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    else
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp, 16, 16);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer4_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer1_64);
-                    if (rc) return rc;
-                    rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer5_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer2_64);
-                    if (rc) return rc;
-                }
-            }
-            else
-            {
-                if (l_port == 0)
-                {
-                    if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 8, 8);
-                        rc_num |= l_data_buffer2_64.insertFromRight(l_sp, 0, 8);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    else
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp, 0, 16);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    rc = fapiGetScom(i_target_centaur, 0x02011772, l_data_buffer4_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, 0x02011772, l_data_buffer1_64);
-                    if (rc) return rc;
-                    rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer5_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer2_64);
-                    if (rc) return rc;
-                }
-                else
-                {
-                    rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer2_64);
-                    if (rc) return rc;
-                    if(l_attr_eff_dimm_type_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp_isdimm, 24, 8);
-                        rc_num |= l_data_buffer2_64.insertFromRight(l_sp, 16, 8);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-                    else
-                    {
-                        rc_num = l_data_buffer2_64.insertFromRight(l_sp, 16, 16);
-                        if (rc_num)
-                        {
-                            FAPI_ERR("Error in function  cfg_byte_mask:");
-                            rc.setEcmdError(rc_num);
-                            return rc;
-                        }
-                    }
-
-                    rc = fapiGetScom(i_target_centaur, 0x02011773, l_data_buffer4_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer1_64.setOr(l_data_buffer4_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, 0x02011773,
-                                     l_data_buffer1_64);
-                    if (rc) return rc;
-                    rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer5_64);
-                    if (rc) return rc;
-                    rc_num = l_data_buffer2_64.setOr(l_data_buffer5_64, 0, 64);
-                    if (rc_num)
-                    {
-                        FAPI_ERR("Error in function  cfg_byte_mask:");
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-                    rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer2_64);
-                    if (rc) return rc;
-                }
-            }
-        }
-    }
-
-    if (l_max_0 == 0)
-    {
-        if (l_mbaPosition == 0)
-        {
-            rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.setDoubleWord(0, l_var);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMA1Q_0x02011672, l_data_buffer1_64);
-            if (rc) return rc;
-            rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.insertFromRight(l_spare, 0, 16);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64);
-            if (rc) return rc;
-        }
-        else
-        {
-            rc = fapiGetScom(i_target_centaur, 0x02011772, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.setDoubleWord(0, l_var);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, 0x02011772, l_data_buffer1_64);
-            if (rc) return rc;
-            rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.insertFromRight(l_spare, 0, 16);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer1_64);
-            if (rc) return rc;
-        }
-    }
-
-    if (l_max_1 == 0)
-    {
-        if (l_mbaPosition == 0)
-        {
-            rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.setDoubleWord(0, l_var);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMB1Q_0x02011673, l_data_buffer1_64);
-            if (rc) return rc;
-            rc = fapiGetScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64);
-            if (rc)  return rc;
-            rc_num = l_data_buffer1_64.insertFromRight(l_spare, 16, 16);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, MBS_MCBIST01_MCBCMABQ_0x02011674, l_data_buffer1_64);
-            if (rc) return rc;
-        }
-        else
-        {
-            rc = fapiGetScom(i_target_centaur, 0x02011773, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.setDoubleWord(0, l_var);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, 0x02011773, l_data_buffer1_64);
-            if (rc) return rc;
-            rc = fapiGetScom(i_target_centaur, 0x02011774, l_data_buffer1_64);
-            if (rc) return rc;
-            rc_num = l_data_buffer1_64.insertFromRight(l_spare, 16, 16);
-            if (rc_num)
-            {
-                FAPI_ERR("Error in function  cfg_byte_mask:");
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-            rc = fapiPutScom(i_target_centaur, 0x02011774, l_data_buffer1_64);
-            if (rc) return rc;
-        }
-    }
-
-    return rc;
-}
-
-fapi::ReturnCode mss_conversion_testtype(const fapi::Target & i_target_mba,
-                                         uint8_t l_pattern,
-                                         mcbist_test_mem &i_mcbtest)
-{
-    ReturnCode rc;
-
-    FAPI_INF("%s:value of testtype is %d", i_target_mba.toEcmdString(), l_pattern);
-    switch (l_pattern)
-    {
-    case 0:
-        i_mcbtest = USER_MODE;
-        FAPI_INF("%s:TESTTYPE :USER_MODE", i_target_mba.toEcmdString());
-        break;
-    case 1:
-        i_mcbtest = CENSHMOO;
-        FAPI_INF("%s:TESTTYPE :CENSHMOO", i_target_mba.toEcmdString());
-        break;
-    case 2:
-        i_mcbtest = SUREFAIL;
-        FAPI_INF("%s:TESTTYPE :SUREFAIL", i_target_mba.toEcmdString());
-        break;
-    case 3:
-        i_mcbtest = MEMWRITE;
-        FAPI_INF("%s:TESTTYPE :MEMWRITE", i_target_mba.toEcmdString());
-        break;
-    case 4:
-        i_mcbtest = MEMREAD;
-        FAPI_INF("%s:TESTTYPE :MEMREAD", i_target_mba.toEcmdString());
-        break;
-    case 5:
-        i_mcbtest = CBR_REFRESH;
-        FAPI_INF("%s:TESTTYPE :CBR_REFRESH", i_target_mba.toEcmdString());
-        break;
-    case 6:
-        i_mcbtest = MCBIST_SHORT;
-        FAPI_INF("%s:TESTTYPE :MCBIST_SHORT", i_target_mba.toEcmdString());
-        break;
-    case 7:
-        i_mcbtest = SHORT_SEQ;
-        FAPI_INF("%s:TESTTYPE :SHORT_SEQ", i_target_mba.toEcmdString());
-        break;
-    case 8:
-        i_mcbtest = DELTA_I;
-        FAPI_INF("%s:TESTTYPE :DELTA_I", i_target_mba.toEcmdString());
-        break;
-    case 9:
-        i_mcbtest = DELTA_I_LOOP;
-        FAPI_INF("%s:TESTTYPE :DELTA_I_LOOP", i_target_mba.toEcmdString());
-        break;
-    case 10:
-        i_mcbtest = SHORT_RAND;
-        FAPI_INF("%s:TESTTYPE :SHORT_RAND", i_target_mba.toEcmdString());
-        break;
-    case 11:
-        i_mcbtest = LONG1;
-        FAPI_INF("%s:TESTTYPE :LONG1", i_target_mba.toEcmdString());
-        break;
-    case 12:
-        i_mcbtest = BUS_TAT;
-        FAPI_INF("%s:TESTTYPE :BUS_TAT", i_target_mba.toEcmdString());
-        break;
-    case 13:
-        i_mcbtest = SIMPLE_FIX;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_FIX", i_target_mba.toEcmdString());
-        break;
-    case 14:
-        i_mcbtest = SIMPLE_RAND;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RAND", i_target_mba.toEcmdString());
-        break;
-    case 15:
-        i_mcbtest = SIMPLE_RAND_2W;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_2W", i_target_mba.toEcmdString());
-        break;
-    case 16:
-        i_mcbtest = SIMPLE_RAND_FIXD;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_FIXD", i_target_mba.toEcmdString());
-        break;
-    case 17:
-        i_mcbtest = SIMPLE_RA_RD_WR;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RA_RD_WR", i_target_mba.toEcmdString());
-        break;
-    case 18:
-        i_mcbtest = SIMPLE_RA_RD_R;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RA_RD_R", i_target_mba.toEcmdString());
-        break;
-    case 19:
-        i_mcbtest = SIMPLE_RA_FD_R;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RA_FD_R", i_target_mba.toEcmdString());
-        break;
-    case 20:
-        i_mcbtest = SIMPLE_RA_FD_R_INF;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RA_FD_R_INF", i_target_mba.toEcmdString());
-        break;
-    case 21:
-        i_mcbtest = SIMPLE_SA_FD_R;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_SA_FD_R", i_target_mba.toEcmdString());
-        break;
-    case 22:
-        i_mcbtest = SIMPLE_RA_FD_W;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RA_FD_W", i_target_mba.toEcmdString());
-        break;
-    case 23:
-        i_mcbtest = INFINITE;
-        FAPI_INF("%s:TESTTYPE :INFINITE", i_target_mba.toEcmdString());
-        break;
-    case 24:
-        i_mcbtest = WR_ONLY;
-        FAPI_INF("%s:TESTTYPE :WR_ONLY", i_target_mba.toEcmdString());
-        break;
-    case 25:
-        i_mcbtest = W_ONLY;
-        FAPI_INF("%s:TESTTYPE :W_ONLY", i_target_mba.toEcmdString());
-        break;
-    case 26:
-        i_mcbtest = R_ONLY;
-        FAPI_INF("%s:TESTTYPE :R_ONLY", i_target_mba.toEcmdString());
-        break;
-    case 27:
-        i_mcbtest = W_ONLY_RAND;
-        FAPI_INF("%s:TESTTYPE :W_ONLY_RAND", i_target_mba.toEcmdString());
-        break;
-    case 28:
-        i_mcbtest = R_ONLY_RAND;
-        FAPI_INF("%s:TESTTYPE :R_ONLY_RAND", i_target_mba.toEcmdString());
-        break;
-    case 29:
-        i_mcbtest = R_ONLY_MULTI;
-        FAPI_INF("%s:TESTTYPE :R_ONLY_MULTI", i_target_mba.toEcmdString());
-        break;
-    case 30:
-        i_mcbtest = SHORT;
-        FAPI_INF("%s:TESTTYPE :SHORT", i_target_mba.toEcmdString());
-        break;
-    case 31:
-        i_mcbtest = SIMPLE_RAND_BARI;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_BARI", i_target_mba.toEcmdString());
-        break;
-    case 32:
-        i_mcbtest = W_R_INFINITE;
-        FAPI_INF("%s:TESTTYPE :W_R_INFINITE", i_target_mba.toEcmdString());
-        break;
-    case 33:
-        i_mcbtest = W_R_RAND_INFINITE;
-        FAPI_INF("%s:TESTTYPE :W_R_RAND_INFINITE", i_target_mba.toEcmdString());
-        break;
-    case 34:
-        i_mcbtest = R_INFINITE1;
-        FAPI_INF("%s:TESTTYPE :R_INFINITE1", i_target_mba.toEcmdString());
-        break;
-    case 35:
-        i_mcbtest = R_INFINITE_RF;
-        FAPI_INF("%s:TESTTYPE :R_INFINITE_RF", i_target_mba.toEcmdString());
-        break;
-    case 36:
-        i_mcbtest = MARCH;
-        FAPI_INF("%s:TESTTYPE :MARCH", i_target_mba.toEcmdString());
-        break;
-    case 37:
-        i_mcbtest = SIMPLE_FIX_RF;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_FIX_RF", i_target_mba.toEcmdString());
-        break;
-    case 38:
-        i_mcbtest = SHMOO_STRESS;
-        FAPI_INF("%s:TESTTYPE :SHMOO_STRESS", i_target_mba.toEcmdString());
-        break;
-    case 39:
-        i_mcbtest = SIMPLE_RAND_RA;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_RAND_RA", i_target_mba.toEcmdString());
-        break;
-    case 40:
-        i_mcbtest = SIMPLE_FIX_RA;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_FIX_RA", i_target_mba.toEcmdString());
-        break;
-    case 41:
-        i_mcbtest = SIMPLE_FIX_RF_RA;
-        FAPI_INF("%s:TESTTYPE :SIMPLE_FIX_RF_RA", i_target_mba.toEcmdString());
-        break;
-    case 42:
-        i_mcbtest = TEST_RR;
-        FAPI_INF("%s:TESTTYPE :TEST_RR", i_target_mba.toEcmdString());
-        break;
-    case 43:
-        i_mcbtest = TEST_RF;
-        FAPI_INF("%s:TESTTYPE :TEST_RF", i_target_mba.toEcmdString());
-        break;
-    case 44:
-        i_mcbtest = W_ONLY_INFINITE_RAND;
-        FAPI_INF("%s:TESTTYPE :W_ONLY_INFINITE_RAND", i_target_mba.toEcmdString());
-        break;
-    case 45:
-        i_mcbtest = MCB_2D_CUP_SEQ;
-        FAPI_INF("%s:TESTTYPE :MCB_2D_CUP_SEQ", i_target_mba.toEcmdString());
-        break;
-    case 46:
-        i_mcbtest = MCB_2D_CUP_RAND;
-        FAPI_INF("%s:TESTTYPE :MCB_2D_CUP_RAND", i_target_mba.toEcmdString());
-        break;
-    case 47:
-        i_mcbtest = SHMOO_STRESS_INFINITE;
-        FAPI_INF("%s:TESTTYPE :SHMOO_STRESS_INFINITE", i_target_mba.toEcmdString());
-        break;
-    case 48:
-        i_mcbtest = HYNIX_1_COL;
-        FAPI_INF("%s:TESTTYPE :HYNIX_1_COL", i_target_mba.toEcmdString());
-        break;
-    case 49:
-        i_mcbtest = RMWFIX;
-        FAPI_INF("%s:TESTTYPE :RMWFIX", i_target_mba.toEcmdString());
-        break;
-    case 50:
-        i_mcbtest = RMWFIX_I;
-        FAPI_INF("%s:TESTTYPE :RMWFIX_I", i_target_mba.toEcmdString());
-        break;
-    case 51:
-        i_mcbtest = W_INFINITE;
-        FAPI_INF("%s:TESTTYPE :W_INFINITE", i_target_mba.toEcmdString());
-        break;
-    case 52:
-        i_mcbtest = R_INFINITE;
-        FAPI_INF("%s:TESTTYPE :R_INFINITE", i_target_mba.toEcmdString());
-        break;
-
-
-    default:
-        FAPI_INF("%s:Wrong Test_type,so using default test_type",
-                 i_target_mba.toEcmdString());
-    }
-
-    return rc;
-}
-
-fapi::ReturnCode mss_conversion_data(const fapi::Target & i_target_mba,
-                                     uint8_t l_pattern,
-                                     mcbist_data_gen &i_mcbpatt)
-{
-    ReturnCode rc;
-    FAPI_INF("%s:value of pattern is %d", i_target_mba.toEcmdString(), l_pattern);
-    switch (l_pattern)
-    {
-    case 0:
-        i_mcbpatt = ABLE_FIVE;
-        FAPI_INF("%s:PATTERN :ABLE_FIVE", i_target_mba.toEcmdString());
-        break;
-    case 1:
-        i_mcbpatt = USR_MODE;
-        FAPI_INF("%s:PATTERN :USER_MODE", i_target_mba.toEcmdString());
-        break;
-    case 2:
-        i_mcbpatt = ONEHOT;
-        FAPI_INF("%s:PATTERN :ONEHOT", i_target_mba.toEcmdString());
-        break;
-    case 3:
-        i_mcbpatt = DQ0_00011111_RESTALLONE;
-        FAPI_INF("%s:PATTERN :DQ0_00011111_RESTALLONE", i_target_mba.toEcmdString());
-        break;
-    case 4:
-        i_mcbpatt = DQ0_11100000_RESTALLZERO;
-        FAPI_INF("%s:PATTERN :DQ0_11100000_RESTALLZERO", i_target_mba.toEcmdString());
-        break;
-    case 5:
-        i_mcbpatt = ALLZERO;
-        FAPI_INF("%s:PATTERN :ALLZERO", i_target_mba.toEcmdString());
-        break;
-    case 6:
-        i_mcbpatt = ALLONE;
-        FAPI_INF("%s:PATTERN :ALLONE", i_target_mba.toEcmdString());
-        break;
-    case 7:
-        i_mcbpatt = BYTE_BURST_SIGNATURE;
-        FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE", i_target_mba.toEcmdString());
-        break;
-    case 8:
-        i_mcbpatt = BYTE_BURST_SIGNATURE_V1;
-        FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE_V1", i_target_mba.toEcmdString());
-        break;
-    case 9:
-        i_mcbpatt = BYTE_BURST_SIGNATURE_V2;
-        FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE_V2", i_target_mba.toEcmdString());
-        break;
-    case 10:
-        i_mcbpatt = BYTE_BURST_SIGNATURE_V3;
-        FAPI_INF("%s:PATTERN :BYTE_BURST_SIGNATURE_V3", i_target_mba.toEcmdString());
-        break;
-    case 11:
-        i_mcbpatt = DATA_GEN_DELTA_I;
-        FAPI_INF("%s:PATTERN :DATA_GEN_DELTA_I", i_target_mba.toEcmdString());
-        break;
-    case 12:
-        i_mcbpatt = MCBIST_2D_CUP_PAT0;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT0", i_target_mba.toEcmdString());
-        break;
-    case 13:
-        i_mcbpatt = MPR;
-        FAPI_INF("%s:PATTERN :MPR", i_target_mba.toEcmdString());
-        break;
-    case 14:
-        i_mcbpatt = MPR03;
-        FAPI_INF("%s:PATTERN :MPR03", i_target_mba.toEcmdString());
-        break;
-    case 15:
-        i_mcbpatt = MPR25;
-        FAPI_INF("%s:PATTERN :MPR25", i_target_mba.toEcmdString());
-        break;
-    case 16:
-        i_mcbpatt = MPR47;
-        FAPI_INF("%s:PATTERN :MPR47", i_target_mba.toEcmdString());
-        break;
-    case 17:
-        i_mcbpatt = DELTA_I1;
-        FAPI_INF("%s:PATTERN :DELTA_I1", i_target_mba.toEcmdString());
-        break;
-    case 18:
-        i_mcbpatt = MCBIST_2D_CUP_PAT1;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT1", i_target_mba.toEcmdString());
-        break;
-    case 19:
-        i_mcbpatt = MHC_55;
-        FAPI_INF("%s:PATTERN :MHC_55", i_target_mba.toEcmdString());
-        break;
-    case 20:
-        i_mcbpatt = MHC_DQ_SIM;
-        FAPI_INF("%s:PATTERN :MHC_DQ_SIM", i_target_mba.toEcmdString());
-        break;
-    case 21:
-        i_mcbpatt = MCBIST_2D_CUP_PAT2;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT2", i_target_mba.toEcmdString());
-        break;
-    case 22:
-        i_mcbpatt = MCBIST_2D_CUP_PAT3;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT3", i_target_mba.toEcmdString());
-        break;
-    case 23:
-        i_mcbpatt = MCBIST_2D_CUP_PAT4;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT4", i_target_mba.toEcmdString());
-        break;
-    case 24:
-        i_mcbpatt = MCBIST_2D_CUP_PAT5;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT5", i_target_mba.toEcmdString());
-        break;
-    case 25:
-        i_mcbpatt = MCBIST_2D_CUP_PAT6;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT6", i_target_mba.toEcmdString());
-        break;
-    case 26:
-        i_mcbpatt = MCBIST_2D_CUP_PAT7;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT7", i_target_mba.toEcmdString());
-        break;
-    case 27:
-        i_mcbpatt = MCBIST_2D_CUP_PAT8;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT8", i_target_mba.toEcmdString());
-        break;
-    case 28:
-        i_mcbpatt = MCBIST_2D_CUP_PAT9;
-        FAPI_INF("%s:PATTERN :MCBIST_2D_CUP_PAT9", i_target_mba.toEcmdString());
-        break;
-    case 29:
-        i_mcbpatt = CWLPATTERN;
-        FAPI_INF("%s:PATTERN :CWLPATTERN", i_target_mba.toEcmdString());
-        break;
-    case 30:
-        i_mcbpatt = GREY1;
-        FAPI_INF("%s:PATTERN :GREY1", i_target_mba.toEcmdString());
-        break;
-    case 31:
-        i_mcbpatt = DC_ONECHANGE;
-        FAPI_INF("%s:PATTERN :DC_ONECHANGE", i_target_mba.toEcmdString());
-        break;
-    case 32:
-        i_mcbpatt = DC_ONECHANGEDIAG;
-        FAPI_INF("%s:PATTERN :DC_ONECHANGEDIAG", i_target_mba.toEcmdString());
-        break;
-    case 33:
-        i_mcbpatt = GREY2;
-        FAPI_INF("%s:PATTERN :GREY2", i_target_mba.toEcmdString());
-        break;
-    case 34:
-        i_mcbpatt = FIRST_XFER;
-        FAPI_INF("%s:PATTERN :FIRST_XFER", i_target_mba.toEcmdString());
-        break;
-    case 35:
-        i_mcbpatt = MCBIST_222_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_222_XFER", i_target_mba.toEcmdString());
-        break;
-    case 36:
-        i_mcbpatt = MCBIST_333_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_333_XFER", i_target_mba.toEcmdString());
-        break;
-    case 37:
-        i_mcbpatt = MCBIST_444_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_444_XFER", i_target_mba.toEcmdString());
-        break;
-    case 38:
-        i_mcbpatt = MCBIST_555_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_555_XFER", i_target_mba.toEcmdString());
-        break;
-    case 39:
-        i_mcbpatt = MCBIST_666_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_666_XFER", i_target_mba.toEcmdString());
-        break;
-    case 40:
-        i_mcbpatt = MCBIST_777_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_777_XFER", i_target_mba.toEcmdString());
-        break;
-    case 41:
-        i_mcbpatt = MCBIST_888_XFER;
-        FAPI_INF("%s:PATTERN :MCBIST_888_XFER", i_target_mba.toEcmdString());
-        break;
-    case 42:
-        i_mcbpatt = FIRST_XFER_X4MODE;
-        FAPI_INF("%s:PATTERN :FIRST_XFER_X4MODE", i_target_mba.toEcmdString());
-        break;
-    case 43:
-        i_mcbpatt = MCBIST_LONG;
-        FAPI_INF("%s:PATTERN :MCBIST_LONG", i_target_mba.toEcmdString());
-        break;
-    case 44:
-        i_mcbpatt = PSEUDORANDOM;
-        FAPI_INF("%s:PATTERN :PSEUDORANDOM", i_target_mba.toEcmdString());
-        break;
-    case 45:
-        i_mcbpatt = CASTLE;
-        FAPI_INF("%s:PATTERN :CASTLE", i_target_mba.toEcmdString());
-        break;
-    default:
-        FAPI_INF("%s:Wrong Data Pattern,so using default pattern",
-                 i_target_mba.toEcmdString());
-    }
-
-    return rc;
-}
-
-}
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C
deleted file mode 100644
index 36892a768..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C
+++ /dev/null
@@ -1,626 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mrs6_DDR4.C,v 1.6 2015/09/04 02:03:31 kmack Exp $
-
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.05   | 09/03/15 | kmack   | RC updates
-//  1.04   | 08/05/15 | sglancy | Fixed FW compile error
-//  1.03   | 08/04/15 | sglancy | Changed to address FW comments
-//  1.02   | 05/07/15 | sglancy | Fixed enable disable bug and added 3DS support
-//  1.00   | 06/27/14 | abhijsau | Initial Draft
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-#include <mss_funcs.H>
-#include <cen_scom_addresses.H>
-#include <mss_mrs6_DDR4.H>
-using namespace fapi;
-
-extern "C"
-{
-
-// loads and runs MRS6 commands on a given MBA
-ReturnCode mss_mrs6_DDR4( fapi::Target& i_target)
-{
-ReturnCode rc;
-uint32_t port_number;
-uint32_t ccs_inst_cnt=0;
-
-for ( port_number = 0; port_number < 2; port_number++)
-        {
-            // Step four: Load MRS Setting
-            FAPI_INF("Loading MRS6 for port %d",port_number);
-            rc = mss_mr6_loader(i_target, port_number, ccs_inst_cnt);
-            if(rc)
-            {
-                FAPI_ERR(" mrs_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                return rc;
-            }
-
-        }
-
-// Execute the contents of CCS array
-        if (ccs_inst_cnt  > 0)
-        {
-            // Set the End bit on the last CCS Instruction
-            rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1);
-            if(rc)
-            {
-                FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                return rc;
-            }
-
-            rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-            if(rc)
-            {
-                FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                return rc;
-            }
-
-            ccs_inst_cnt = 0;
-        }
-
-          return rc;
-
-}
-
-//Adds a NOP to CCS
-fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase &addr_16, uint32_t instruction_number,uint8_t rank,uint8_t bank,uint32_t delay,uint8_t port) {
-   fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-   fapi::ReturnCode l_rc_buff = fapi::FAPI_RC_SUCCESS;
-   uint32_t l_ecmd_rc = 0;
-
-   //CCS Array 0 buffers
-   ecmdDataBufferBase bank_3(3);
-   ecmdDataBufferBase ddr4_activate_1(1);
-   ecmdDataBufferBase rasn_1(1);
-   ecmdDataBufferBase casn_1(1);
-   ecmdDataBufferBase wen_1(1);
-   ecmdDataBufferBase cke_4(4);
-   ecmdDataBufferBase csn_8(8);
-   ecmdDataBufferBase odt_4(4);
-   ecmdDataBufferBase cal_type_4(4);
-
-   //CCS Array 1 buffers
-   ecmdDataBufferBase idles_16(16);
-   ecmdDataBufferBase repeat_16(16);
-   ecmdDataBufferBase pattern_20(20);
-   ecmdDataBufferBase read_compare_1(1);
-   ecmdDataBufferBase rank_cal_4(4);
-   ecmdDataBufferBase cal_enable_1(1);
-   ecmdDataBufferBase ccs_end_1(1);
-   FAPI_INF("\n Running NO -OP command");
-
-   //CCS Array 0 Setup
-
-   //Buffer conversions from inputs
-   l_ecmd_rc |= addr_16.reverse();
-   l_ecmd_rc |= bank_3.insertFromRight(bank, 0, 3);
-   l_ecmd_rc |= bank_3.reverse();  //Banks are 0:2
-   l_ecmd_rc |= csn_8.flushTo1();
-   l_ecmd_rc |= csn_8.clearBit(rank);
-
-   //Command structure setup
-   l_ecmd_rc |= cke_4.flushTo1();
-   l_ecmd_rc |= rasn_1.setBit(0);
-   l_ecmd_rc |= casn_1.setBit(0);
-   l_ecmd_rc |= wen_1.setBit(0);
-
-   l_ecmd_rc |= read_compare_1.clearBit(0);
-
-   //Final setup
-   l_ecmd_rc |= odt_4.flushTo0();
-   l_ecmd_rc |= cal_type_4.flushTo0();
-   l_ecmd_rc |= ddr4_activate_1.setBit(0);
-
-   if (l_ecmd_rc) {
-      FAPI_ERR( "add_activate_to_ccs: Error setting up buffers");
-      l_rc_buff.setEcmdError(l_ecmd_rc);
-      return l_rc_buff;
-   }
-
-   l_rc = mss_ccs_inst_arry_0(i_target_mba, instruction_number, addr_16, bank_3, ddr4_activate_1, rasn_1, casn_1, wen_1, cke_4, csn_8, odt_4, cal_type_4, port);
-   if (l_rc) return l_rc;
-
-
-   //CCS Array 1 Setup
-   l_ecmd_rc |= idles_16.insertFromRight(delay, 0, 16);
-   l_ecmd_rc |= repeat_16.flushTo0();
-   l_ecmd_rc |= pattern_20.flushTo0();
-   l_ecmd_rc |= read_compare_1.flushTo0();
-   l_ecmd_rc |= rank_cal_4.flushTo0();
-   l_ecmd_rc |= cal_enable_1.flushTo0();
-   l_ecmd_rc |= ccs_end_1.flushTo0();
-
-   if (l_ecmd_rc) {
-      FAPI_ERR( "add_activate_to_ccs: Error setting up buffers");
-      l_rc_buff.setEcmdError(l_ecmd_rc);
-      return l_rc_buff;
-   }
-
-   l_rc = mss_ccs_inst_arry_1(i_target_mba, instruction_number, idles_16, repeat_16, pattern_20, read_compare_1, rank_cal_4, cal_enable_1, ccs_end_1);
-   if (l_rc) return l_rc;
-
-   return l_rc;
-}
-
-//Loads MRS6 commands for a given port into the CCS array
-ReturnCode mss_mr6_loader( fapi::Target& i_target,uint32_t i_port_number,uint32_t& io_ccs_inst_cnt)
-{
-
-    const uint8_t MRS6_BA = 6;
-    uint32_t dimm_number;
-    uint32_t rank_number;
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-        uint8_t tmod_delay = 12;
-    ecmdDataBufferBase data_buffer_64(64);
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    rc_num = rc_num | activate_1.setBit(0);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.clearBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.clearBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.clearBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.clearBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.clearBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    uint32_t instruction_number;
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-    ecmdDataBufferBase mrs0(16);
-    ecmdDataBufferBase mrs1(16);
-    ecmdDataBufferBase mrs2(16);
-    ecmdDataBufferBase mrs3(16);
-    ecmdDataBufferBase mrs4(16);
-    ecmdDataBufferBase mrs5(16);
-    ecmdDataBufferBase mrs6(16);
-
-    uint16_t MRS6 = 0;
-
-    ecmdDataBufferBase data_buffer(64);
-    instruction_number = 0;
-
-    uint16_t num_ranks = 0;
-
-    FAPI_INF( "+++++++++++++++++++++ LOADING MRS SETTINGS FOR PORT %d +++++++++++++++++++++", i_port_number);
-
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-
-    // WORKAROUNDS
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.setBit(51);
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_mr6_loader: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-        if(i_port_number==0){
-    rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.clearBit(48);
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_mr6_loader: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-    rc = fapiPutScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P0_0x8000CC050301143F, data_buffer);
-    if(rc) return rc;
-        }
-        else{
-
-        rc = fapiGetScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer);
-    if(rc) return rc;
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.clearBit(48);
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_mr6_loader: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-    rc = fapiPutScom(i_target,DPHY01_DDRPHY_WC_CONFIG3_P1_0x8001CC050301143F, data_buffer);
-    if(rc) return rc;
-        }
-
-    //Lines commented out in the following section are waiting for xml attribute adds
-
-    uint8_t dram_stack[2][2];
-    rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, dram_stack);
-    if(rc) return rc;
-
-    FAPI_INF( "Stack Type: %d\n", dram_stack[0][0]);
-
-
-    //MRS6
-    uint8_t vrefdq_train_value[2][2][4]; //vrefdq_train value   -  NEW
-    rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_VALUE, &i_target, vrefdq_train_value);
-    if(rc) return rc;
-    uint8_t vrefdq_train_range[2][2][4]; //vrefdq_train range   -  NEW
-    rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_RANGE, &i_target, vrefdq_train_range);
-    if(rc) return rc;
-    uint8_t vrefdq_train_enable[2][2][4]; //vrefdq_train enable  -  NEW
-    rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, vrefdq_train_enable);
-    if(rc) return rc;
-
-    FAPI_INF("enable attribute %d",vrefdq_train_enable[0][0][0]);
-
-
-
-     uint8_t tccd_l; //tccd_l  -  NEW
-    rc = FAPI_ATTR_GET( ATTR_TCCD_L, &i_target, tccd_l);
-    if(rc) return rc;
-    if (tccd_l == 4)
-    {
-        tccd_l = 0x00;
-    }
-    else if (tccd_l == 5)
-    {
-        tccd_l = 0x80;
-    }
-    else if (tccd_l == 6)
-    {
-        tccd_l = 0x40;
-    }
-    else if (tccd_l == 7)
-    {
-        tccd_l = 0xC0;
-    }
-    else if (tccd_l == 8)
-    {
-        tccd_l = 0x20;
-    }
-
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | cke_4.setBit(0,4);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_mr6_loader: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-    io_ccs_inst_cnt ++;
-
-    // Dimm 0-1
-    for ( dimm_number = 0; dimm_number < 2; dimm_number++)
-    {
-        num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-        if (num_ranks == 0)
-        {
-            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d ", i_port_number, dimm_number, num_ranks);
-        }
-        else
-        {
-            // Rank 0-3
-            for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-            {
-                    FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number);
-
-                    rc_num = rc_num | csn_8.setBit(0,8);
-                    rc_num = rc_num | address_16.clearBit(0, 16);
-
-                    //MRS6
-
-                    vrefdq_train_value[i_port_number][dimm_number][rank_number] = mss_reverse_8bits(vrefdq_train_value[i_port_number][dimm_number][rank_number]);
-
-                    if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE1)
-                    {
-                        vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0x00;
-                    }
-                    else if (vrefdq_train_range[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_RANGE_RANGE2)
-                    {
-                        vrefdq_train_range[i_port_number][dimm_number][rank_number] = 0xFF;
-                    }
-
-                    if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE)
-                    {
-                        vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0xff;FAPI_INF("ENABLE is enabled");
-                    }
-                    else if (vrefdq_train_enable[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE)
-                    {
-                        vrefdq_train_enable[i_port_number][dimm_number][rank_number] = 0x00;FAPI_INF("DISABLE is enabled");
-                    }
-
-                    rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_value[i_port_number][dimm_number][rank_number], 0, 6);
-                    rc_num = rc_num | mrs6.insert((uint8_t) vrefdq_train_range[i_port_number][dimm_number][rank_number], 6, 1);
-                    rc_num = rc_num | mrs6.insertFromRight((uint8_t) vrefdq_train_enable[i_port_number][dimm_number][rank_number], 7, 1);
-
-                    rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 8, 2);
-                    rc_num = rc_num | mrs6.insert((uint8_t) tccd_l, 10, 3);
-                    rc_num = rc_num | mrs6.insert((uint8_t) 0x00, 13, 2);
-
-                    rc_num = rc_num | mrs6.extractPreserve(&MRS6, 0, 16, 0);
-
-                   FAPI_INF( "MRS 6: 0x%04X", MRS6);
-
-                    if (rc_num)
-                    {
-                        FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-                        rc_buff.setEcmdError(rc_num);
-                        return rc_buff;
-                    }
-
-                    // Only corresponding CS to rank
-                    rc_num = rc_num | csn_8.setBit(0,8);
-                    rc_num = rc_num | csn_8.clearBit(rank_number+4*dimm_number);
-
-                    if (dram_stack[0][0] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS)
-                    {
-                       FAPI_INF( "=============  Got in the 3DS stack loop CKE !!!!=====================\n");
-                       rc_num = rc_num | csn_8.clearBit(2+4*dimm_number,2);
-                       // I'm leaving this commented out - I need to double check it with Luke Mulkey to see which CS's are wired to which CKE's
-                       // rc_num = rc_num | cke_4.clearBit(1);
-                    }
-
-                    // Propogate through the 4 MRS cmds
-                        // Copying the current MRS into address buffer matching the MRS_array order
-                        // Setting the bank address
-                            rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6);
-                            rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5);
-
-                        if (rc_num)
-                        {
-                            FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-                            rc_buff.setEcmdError(rc_num);
-                            return rc_buff;
-                        }
-
-                        if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-                        {
-                            rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-                                if(rc) return rc;
-                        }
-
-                        // Send out to the CCS array
-                        rc = mss_ccs_inst_arry_0( i_target,
-                                          io_ccs_inst_cnt,
-                                          address_16,
-                                          bank_3,
-                                          activate_1,
-                                          rasn_1,
-                                          casn_1,
-                                          wen_1,
-                                          cke_4,
-                                          csn_8,
-                                          odt_4,
-                                          ddr_cal_type_4,
-                                          i_port_number);
-                        if(rc) return rc;
-                        rc = mss_ccs_inst_arry_1( i_target,
-                                          io_ccs_inst_cnt,
-                                          num_idles_16,
-                                          num_repeat_16,
-                                          data_20,
-                                          read_compare_1,
-                                          rank_cal_4,
-                                          ddr_cal_enable_1,
-                                          ccs_end_1);
-                        if(rc) return rc;
-                        io_ccs_inst_cnt ++;
-
-                                                    // Address inversion for RCD
-                    if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_RDIMM || dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
-                    {
-                       FAPI_INF( "Sending out MRS with Address Inversion to B-side DRAMs\n");
-
-
-                       // Propogate through the 4 MRS cmds
-                           // Copying the current MRS into address buffer matching the MRS_array order
-                           // Setting the bank address
-                               rc_num = rc_num | address_16.insert(mrs6, 0, 16, 0);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 0, 1, 7);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 1, 1, 6);
-                               rc_num = rc_num | bank_3.insert((uint8_t) MRS6_BA, 2, 1, 5);
-
-                           // Indicate B-Side DRAMS BG1=1
-                           rc_num = rc_num | address_16.setBit(15);  // Set BG1 = 1
-
-                           rc_num = rc_num | address_16.flipBit(3,7); // Invert A3:A9
-                           rc_num = rc_num | address_16.flipBit(11);  // Invert A11
-                           rc_num = rc_num | address_16.flipBit(13);  // Invert A13
-                           rc_num = rc_num | address_16.flipBit(14);  // Invert A17
-                           rc_num = rc_num | bank_3.flipBit(0,3);     // Invert BA0,BA1,BG0
-
-
-                           if (rc_num)
-                           {
-                               FAPI_ERR( " Error setting up buffers");
-                               rc_buff.setEcmdError(rc_num);
-                               return rc_buff;
-                           }
-
-                           if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-                           {
-                               rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-                               if(rc) return rc;
-                           }
-
-                           // Send out to the CCS array
-                           rc = mss_ccs_inst_arry_0( i_target,
-                                             io_ccs_inst_cnt,
-                                             address_16,
-                                             bank_3,
-                                             activate_1,
-                                             rasn_1,
-                                             casn_1,
-                                             wen_1,
-                                             cke_4,
-                                             csn_8,
-                                             odt_4,
-                                             ddr_cal_type_4,
-                                             i_port_number);
-                           if(rc) return rc;
-                           rc = mss_ccs_inst_arry_1( i_target,
-                                             io_ccs_inst_cnt,
-                                             num_idles_16,
-                                             num_repeat_16,
-                                             data_20,
-                                             read_compare_1,
-                                             rank_cal_4,
-                                             ddr_cal_enable_1,
-                                             ccs_end_1);
-                           if(rc) return rc;
-                           io_ccs_inst_cnt ++;
-
-
-                 }
-instruction_number = io_ccs_inst_cnt;
-
-rc = add_nop_to_ccs (i_target, address_16,instruction_number,rank_number,MRS6_BA,tmod_delay,i_port_number);
-io_ccs_inst_cnt = instruction_number;
-io_ccs_inst_cnt++;
-if (rc) return rc;
-
-            }
-        }
-    }
-
-
-
-
-
-    return rc;
-}
-
-
-
-
-
-}
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H
deleted file mode 100644
index 5abc286d8..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H
+++ /dev/null
@@ -1,99 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_mrs6_DDR4.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_mrs6_DDR4.H,v 1.2 2015/08/04 18:47:26 sglancy Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998, 2013
-// *!           All Rights Reserved -- Property of IBM
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             :  mss_mrs6_DDR4.H
-// *! TITLE                : 
-// *! DESCRIPTION          : MRS6 setting procedures
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : 
-// *! BACKUP               : 
-// *!***************************************************************************
-// CHANGE HISTORY:
-//-------------------------------------------------------------------------------
-// Version:|Author: 	| Date:   | Comment:
-//  1.2    | sglancy    | 08/04/15| Changed to address FW comments
-//  1.1    | abhijsau   | 06/27/14| Initial Version
-// --------|--------|---------|--------------------------------------------------
-//------------------------------------------------------------------------------
-#ifndef MSS_MR6_DDR4_H
-#define MSS_MR6_DDR4_H
-
-
-/****************************************************************************************/
-/* mss_mcbist_address.H                                                                           */
-/****************************************************************************************/
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_mrs6_DDR4_FP_t)(const fapi::Target& i_target);
-
-extern "C"
-{
-
-using namespace fapi;
-/**
- * @sets up and runs Mode Register Set 6 on a centaur.mba level target
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode mss_mrs6_DDR4(fapi::Target& i_target);
-/**
- * @Adds a no-op (NOP) command to the CCS array
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in]  addr_16: 16 wide ecmdDataBufferBase to be used for the address bus
- * @param[in]  instruction_number: current location in the CCS array
- * @param[in]  rank: current rank
- * @param[in]  bank: current bank
- * @param[in]  delay: delay to add for the command
- * @param[in]  port: current port to execute the NOP on
- *
- * @return ReturnCode
- */
-fapi::ReturnCode add_nop_to_ccs(fapi::Target& i_target_mba, ecmdDataBufferBase &addr_16, uint32_t instruction_number,uint8_t rank,uint8_t bank,uint32_t delay,uint8_t port);
-/**
- * @Loads in MRS6 for a given port number
- *
- * @param[in]  target:  Reference to centaur.mba target, 
- * @param[in]  i_port:  Current port to operate on
- * @param[in/out]  io_ccs_inst_cnt:  Reference to current CCS array position
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_mr6_loader(fapi::Target& i_target,uint32_t i_port_number,uint32_t& io_ccs_inst_cnt);
-} // extern "C"
-
-#endif // MSS_MR6_DDR4_H
-
-
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
deleted file mode 100644
index d535405ee..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H
+++ /dev/null
@@ -1,108 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_shmoo_common.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_shmoo_common.H,v 1.21 2015/08/07 11:29:09 sasethur Exp $
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM 
-// *!                   ***  ***
-// *!***************************************************************************
-// *! FILENAME             : mss_shmoo_common.H
-// *! TITLE                : MSS Shmoo common defines
-// *! DESCRIPTION          : Memory Subsystem Shmoo common defines
-// *! CONTEXT              : To make all shmoos share a common defines
-// *!
-// *! OWNER  NAME          : Preetham Hosmane 				 Email - preeragh@in.ibm.com
-// *! BACKUP NAME          : Saravanan Sethuraman            Email:     
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:   | Comment:
-// 1.21    |preeragh| 30/07/15| Optimized for FW Linear/Composite/Bin
-// 1.20    |preeragh| 22/06/15| DDR4 - Mods
-// 1.18    |mjjones | 24/01/14| RAS Review Updates
-// 1.15    |abhijit |8/8/12   | Updated Review Comments
-// 1.9     |aditya  |12/6/12  | Updated Review Comments
-// 1.8     | abhijit| 15/11/12| made changes fw review comments 
-// 1.7     | abhijit| 22/10/12| made changes to variables
-// 1.6     | abhijit| 22/10/12| made changes according to the new design 
-// --------|--------|-------- |--------------------------------------------------
-#ifndef MSS_SHMOO_COMMON_H
-#define MSS_SHMOO_COMMON_H
-
-enum shmoo_type_t
-{
-    TEST_NONE = 0,
-    MCBIST    = 1,
-    WR_EYE    = 2,
-    WRT_DQS   = 8,
-    RD_EYE    = 4,
-    RD_GATE   = 16
-};
-
-enum shmoo_algorithm_t
-{
-    SEQ_LIN  // Parallel bytes/ranks here .. no parallel targets in HB
-};
-
-const uint8_t NINE = 9;
-const uint8_t MAX_SHMOO=2;
-const uint8_t MAX_RANK_DIMM=4;
-const uint8_t MAX_NIBBLES=2;
-const uint8_t MAX_BITS=4;
-const uint8_t MAX_DQ=80;
-const uint8_t MAX_DQS=20;
-const uint8_t SCHMOO_NIBBLES=20;
-const uint8_t MAX_PORT = 2;
-const uint8_t MAX_BYTE = 10;
-const uint8_t MAX_RANK = 8;
-
-//! Defines the structure of a knob ..Holds static info regarding a knob
-struct shmoo_knob_config_t
-{
-    //! These are const values that define a knob , will not change during
-    //! shmoo runtime
-    uint16_t min_val; //Minimum value that can be taken by the knob
-    uint16_t max_val; //Maximum value that can be taken by the knob
-};
-
-//! Defines the structure of a knob ..Holds dynamic runtime info of a knob
-struct shmoo_knob_data_t
-{
-    // placeholder for the datastructure that will hold all the shmoo
-    // config data and results
-    bool done;
-    uint16_t lb_regval[MAX_DQ]; // Left Bound register/Hex value
-    uint16_t rb_regval[MAX_DQ];// Right Bound register/Hex value
-    uint16_t nom_val[MAX_DQ]; // nominal value of this instance of the knob
-    uint16_t last_pass[MAX_DQ];
-	uint16_t total_margin[MAX_DQ];
-	uint16_t curr_diff[MAX_DQ];
-    uint16_t last_fail[MAX_DQ];
-    uint16_t curr_val[MAX_DQ];
-    uint16_t right_margin_val[MAX_DQ];
-    uint16_t left_margin_val[MAX_DQ];
-};
-#endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
deleted file mode 100644
index 11905cba1..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ /dev/null
@@ -1,7513 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.C,v 1.103 2015/09/22 19:13:20 kmack Exp $
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|------------------------------------------------
-//  1.103  | kmack    |16-SEP-15| Replaced sleep with fapiDelay
-//  1.102  | kmack    |16-SEP-15| DQS Alignment Workaround
-//  1.101  | sglancy  |14-JUL-15| Fixed compile issue
-//  1.100  | sglancy  |13-JUL-15| Fixed compile issue
-//  1.99   | sglancy  |13-JUL-15| Fixed LR DIMM order of operations and addressed FW comments
-//  1.98   | sglancy  |24-JUN-15| Added call to DQS offset function
-//  1.97   | sglancy  |10-JUN-15| Fixed BBM set code call - removed comment of code
-//  1.96   | sglancy  |27-MAY-15| Added changes for DDR4 3DS
-//  1.95   | sglancy  |12-MAY-15| Added DDR4 WR VREF set
-//  1.94   | jdsloat  |27-JAN-14| Addressed FW concerns from gerrit.
-//  1.93   | jdsloat  |22-JAN-14| Moved the initialization of rank_invalid within BYTE DISABLE WORKAROUND
-//  1.92   | jdsloat  |20-JAN-14| Added new workaround for BYTE DISABLE and for WR LVL DISABLE.  This affects  RAS/BBM work.
-//  1.91   | jdsloat  |24-SEP-14| Disabling spare CKE bit modify for SW275629.  This bit will be modified via initfile.
-//  1.90   | jdsloat  |29-JUL-14| disable for delay reset call moved to system level
-//  1.89   | jdsloat  |29-JUL-14| Added a disable for delay reset call
-//  1.88   | jdsloat  |14-JUL-14| Fixed delay reset call
-//  1.87   | jdsloat  |09-JUN-14| Fixed log numbering... Added additonal error logs for more debug ability in a training error situation.
-//  1.85   | jdsloat  |23-APL-14| Fixed attribute variable l_disable1_rdclk_fixed unitialized error in SW25701/v1.83
-//  1.84   | jdsloat  |23-APL-14| Fixed FAPI_ERR message within v1.83, mss_set_bbm_regs
-//  1.83   | jdsloat  |18-APL-14| SW25701 Workaround - mss_set_bbm_regs - x4s will not mask out RDCLKs on Bad Bits to avoid translation issues
-//  1.82   | jdsloat  |14-APL-14| Gerrit Review. Rc checks.
-//  1.81   | jdsloat  |11-APL-14| HW278227 BBM workaround: Masking out the same bits/bytes across all ranks.
-//  1.80   | jdsloat  |01-APL-14| RAS review edits/changes
-//  1.79   | jdsloat  |01-APL-14| RAS review edits/changes
-//  1.78   | jdsloat  |28-MAR-14| RAS review edits/changes
-//  1.77   | jdsloat  |28-MAR-14| Added ifdef around #include for mss_lrdimm_ddr4_funcs.H
-//  1.76   | mwuu     |14-MAR-14| Fixed CDIMM full spare case in getC4dq2reg (bbm)
-//  1.75   | kcook    |14-MAR-14| Fixed mss_mxd_training stub function definition
-//  1.74   | kcook    |14-MAR-14| Added calls to DDR4 LRDIMM training functions
-//  1.73   | mwuu     |25-FEB-14| Fixed ISDIMM spare case for bad bitmap
-//  1.72   | mwuu     |14-FEB-14| Fixed x4 spare case when mss_c4_phy returns bad
-//         |          |         | data with workaround
-//  1.71   | mwuu     |13-FEB-14| Updated get/setC4dq2reg, mss_set/get_bbm_regs FNs
-//         |          |         | to use access_delay_regs for dq/dqs pin mapping.
-//         |          |         | Added mss_get_dqs_lane helper FN.
-//  1.70   | jdsloat  | 11/11/13| Changed EFF attributes to VPD named attributes
-//  1.69   | jdsloat  |06-OCT-13| Removed Control Switch Attribute
-//  1.68   | bellows  |16-SEP-13| Hostboot compile update
-//  1.67   | kcook    |13-SEP-13| Updated define FAPI_LRDIMM token.
-//  1.66   | kcook    |27-AUG-13| Moved main LRDIMM sections into separate file.
-//         |          |         | Removed reference to ATTR_LAB_USE_JTAG_MODE.
-//         | mwuu     |         | Added ATTR_MSS_DISABLE1_REG_FIXED for bbm FN for DD2.
-//  1.65   | kcook    |16-AUG-13| Added LRDIMM support. Use with mss_funcs.C v1.32.
-//  1.64   | jdsloat  |01-AUG-13| Fixed dimm/rank conversion in address mirroring mode for a 4 rank dimm scenario
-//  1.63   | jdsloat  |29-JUN-13| Added JTAG mode and CONTROL SWITCH attribute checks to bad bit mask function calls.
-//  1.62   | mwuu     |17-JUN-13| Fixed set_bbm function to disable0,disable1,wr_clk registers
-//         |          |         | In x4 single bit fails disables entire nibble in set/get_bbm FN
-//  1.61   | jdsloat  |13-JUN-13| Added a single RC check
-//  1.60   | jdsloat  |11-JUN-13| Added a single RC check
-//  1.59   | jdsloat  |04-JUN-13| Added RC checks and port 1 to delay reset function
-//  1.58   | jdsloat  |20-MAY-13| Added a delay reset function for multiple training runs
-//         |          |         | changed mss_rtt_nom_rtt_wr_swap to use mirror mode function in mss_funcs
-//         |          |         | changed mss_rtt_nom_rtt_wr_swap to only execute on ddr3
-//         |          |         | Mirror mode keyed off of mba level mirror_mode attribute.
-//  1.57   | jdsloat  |27-FEB-13| Added second workaround adjustment to waterfall problem in order to use 2 rank pairs.
-//  1.56   | jdsloat  |27-FEB-13| Fixed rtt_nom and rtt_wr swap bug during condition of rtt_nom = diabled and rtt_wr = non-disabled
-//         |          |         | Added workaround on a per quad resolution
-//         |          |         | Added workaround as a seperate sub
-//         |          |         | Added framework of binning workaround based on timing reference
-//         |          |         | Added putscom to enable spare cke mirroring
-//  1.55   | jdsloat  |25-FEB-13| Added MBA/Port info to debug messages.
-//  1.54   | jdsloat  |22-FEB-13| Edited WRITE_READ workaround to also edit DQSCLK PHASE
-//  1.53   | jdsloat  |14-FEB-13| Fixed WRITE_READ workaround so it will execute in a partial substep case
-//         |          |         | Edited mss_rtt_nom_rtt_wr_swap to only write rtt_nom with rtt_wr or supplied rtt_nom
-//         |          |         | Moved location of mss_rtt_nom_rtt_wr_swap around wr_lvl substep
-//         |          |         | Added Address Mirror Mode.
-//  1.52   | jdsloat  |07-FEB-13| Fixed address typo for RP3 in WRITE_READ workaround.
-//  1.51   | gollub   |31-JAN-13| Uncommenting mss_unmask_draminit_training_errors
-//  1.50   | jdsloat  |16-JAN-13| Fixed rank group enable within PC_INIT_CAL reg
-//  1.49   | jdsloat  |08-JAN-13| Added clearing RD PHASE SELECT values post Read Centering Workaround.
-//  1.48   | jdsloat  |08-JAN-13| Cleared Cal Config in PC_INIT_CAL on opposing port.
-//  1.47   | jdsloat  |08-JAN-13| Fixed port 1 cal setup RMW and fixed doing individual rank pairs.  Both in PC_INIT_CAL_CONFIG0 regs.
-//  1.46   | jdsloat  |03-JAN-13| RM temp edits to CAL0q and CAL1q; Cleared INIT_CAL_STATUS and INIT_CAL_ERROR Regs before every subtest, edited debug messages
-//  1.45   | gollub   |21-DEC-12| Calling mss_unmask_draminit_training_errors after mss_draminit_training_cloned
-//  1.43   | jdsloat  |20-DEC-12| Temporarily disabled RTT_NOM swap
-//  1.42   | bellows  |06-DEC-12| Fixed up review comments
-//  1.41   | jdsloat  |02-DEC-12| Fixed RTT_NOM swap for Port 1
-//  1.40   | jdsloat  |30-NOV-12| Temporarily comment Bad Bit Mask.
-
-//  1.39   | jdsloat  |18-NOV-12| Fixed CAL_STEP to allow Zq Cal.
-//  1.38   | jdsloat  |16-NOV-12| Fixed Error Place holder and port addressing with BBM
-//  1.37   | jdsloat  |12-NOV-12| Fixed a bracket typo.
-//  1.36   | jdsloat  |07-NOV-12| Changed procedure to proceed through ALL rank_pair, Ports before reporting
-//         |          |         | error status for partial good support. Added Bad Bit Mask to disable regs function
-//         |          |        //  1.57   | jdsloat  |27-FEB-13|  | and disable regs to Bad Bit Mask function.
-//  1.35   | jdsloat  |08-OCT-12| Changed Write to Read,Modify,Write of Phy Init Cal Config Reg
-//  1.34   | jdsloat  |25-SEP-12| Bit 0 of Cal Step Attribute now offers an all at once option - bit 0 =1 if stepbystep
-//  1.33   | jdsloat  |07-SEP-12| Broke init_cal down to step by step keyed off of CAL_STEP_ENABLE attribute
-//  1.32   | jdsloat  |29-AUG-12| Fixed mss_rtt_nom_rtt_wr_swap and verified with regression
-//  1.31   | bellows  |28-AUG-12| Revert back to 1.29 until regression pass again
-//  1.30   | jdsloat  |23-AUG-12| Added mss_rtt_nom_rtt_wr_swap pre and post init_cal
-//  1.29   | bellows  |16-Jul-12| bellows | added in Id tag
-//  1.28   | bellows  |02-May-12| cal ranks are 4 bits, this needed to be adjusted
-//  1.26   | asaetow  |12-Apr-12| Added "if(rc) return rc;" at line 180.
-//  1.25   | asaetow  |06-Apr-12| Added "if(rc) return rc;" at line 165.
-//  1.24   | asaetow  |03-Apr-12| Changed FAPI_INF to FAPI_ERR where applicable from lines 275 to 324, per Mike Jones.
-//  1.23   | asaetow  |29-Mar-12| Fixed FAPI_SET_HWP_ERROR using temp error callout RC_MSS_PLACE_HOLDER_ERROR.
-//         |          |         | Changed uint32_t NUM_POLL to const.
-//  1.22   | divyakum |29-Mar-12| Fixed rc assignment. Added comments for error handling.
-//  1.21   | divyakum |06-Mar-12| Added cal status checking function.
-//         |          |         | Fixed init cal issue via CCS to account for both ports.
-//  1.20   | divyakum |         | Modified to execute CCS after every instruction.
-//         |          |         | Added error checking for calibration. Needs cen_scom_addresses.H v.1.15 or newer.
-//  1.19   | divyakum |01-Mar-12| Fixed ddr_cal_enable_buffer_1 value for ZQ cal long
-//  1.18   | divyakum |29-Feb-12| Removed call to ccs_mode function. writing to scom directly
-//         |          |         | Fixed wen_buffer value when re-issuing zqcal
-//         |          |         | Fixed test_buffer value when re-issuing zqcal
-//         |          |         | Added cen_scom_addresses.H in include
-//  1.17   | divyakum |20-Feb-12| Adding comments to include i_target type
-//  1.16   | divyakum |20-Feb-12| Replaced calls to insertFromBin with setHalfWord and setBit functions
-//  1.15   | divyakum |14-Feb-12| Removed port field from mss_ccs_mode, mss_ccs_inst_arry_1, mss_execute_ccs_inst_array.
-//         |          |         | NOTE: compatible with mss_funcs.H v1.19 or newer
-//  1.14   | divyakum |10-Feb-12| Added/Modified error codes, var names and declarations to meet coding guidlines
-//  1.13   | divyakum |08-Feb-12| Modified Attributes to FAPI attributes
-//         |          |         | Added rc checking
-//  1.12   | divyakum |31-Jan-12| Modified number of ports to work with Brent's userlevel.
-//  1.11   | divyakum |20-Jan-12| Modified print messages. Fixed indentations
-//  1.16   | divyakum |20-Jan-12| Fixed CCS func names to match mss_funcs.H ver 1.16
-//         | divyakum |         | Added resetn initialization.
-//  1.15   | bellows  |23-Dec-11| Set poll count to 100, set the end bit and when to execute the array time
-//  1.14   | divyakum |21-Dec-11| Added more info prints. Fixed Execution of CCS
-//  1.13   | bellows  |20-Dec-11| Fixed up rank loop so that it goes over both DIMMs
-//  1.12   | jdsloat  |23-Nov-11| Incremented instruction number, added info messages
-//  1.11   | jdsloat  |21-Nov-11| Got rid of GOTO argument in CCS cmds.
-//  1.10   | divyakum |18-Nov-11| Fixed function calls to match procedure name.
-//  1.9    | divyakum |11-Oct-11| Fix to include mss_funcs instead of cen_funcs.
-//         |          |         | Changed usage of array attributes.
-//         |          |         | NOTE: Needs to be compiled with mss_funcs v1.3.
-//  1.8    | divyakum |03-Oct-11| Removed primary_ranks_arrayvariable. Fixed rank loop for Socket1
-//  1.7    | divyakum |30-Sep-11| First drop for Centaur. This code compiles
-//  1.6    | divyakum |28-Sep-11| Added Error path with cal fails.
-//         |          |         | Modified CCS_MODE, CCS_EXECUTE call
-//  1.5    | divyakum |27-Sep-11| Updated code to match with cen_funcs.H v.1.5
-//  1.4    | divyakum |27-Sep-11| Added capability to issue CCS cmds to a port pair where possible.
-//  1.3    | divyakum |26-Sep-11| Added calls to attributes and CCS array for ZQ and initial calibrations.
-//         |          |         | Added rank loopers.
-//  1.2    | jdsloat  |14-Jul-11| Proper call name fix
-//  1.1    | jdsloat  |22-Apr-11| Initial draft
-
-
-//----------------------------------------------------------------------
-//  FAPI function Includes
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-#include <fapiUtil.H>
-
-//----------------------------------------------------------------------
-//  Centaur function Includes
-//----------------------------------------------------------------------
-#include <cen_scom_addresses.H>
-#include <mss_funcs.H>
-#include <dimmBadDqBitmapFuncs.H>
-#include <mss_unmask_errors.H>
-#include <mss_lrdimm_funcs.H>
-#include "mss_access_delay_reg.H"
-#include <mss_mrs6_DDR4.H>
-#ifdef FAPI_LRDIMM
-#include <mss_lrdimm_ddr4_funcs.H>
-#endif
-
-#ifndef FAPI_LRDIMM
-using namespace fapi;
-fapi::ReturnCode mss_execute_lrdimm_mb_dram_training(Target& i_target)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-fapi::ReturnCode mss_mrep_training(Target& i_target, uint32_t port)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-fapi::ReturnCode mss_mxd_training(Target& i_target, uint8_t port,  uint8_t i_type)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-fapi::ReturnCode mss_dram_write_leveling(Target& i_target, uint32_t port)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR);
-   return rc;
-
-}
-#endif
-
-//------------End My Includes-------------------------------------------
-
-//----------------------------------------------------------------------
-//  Constants
-//----------------------------------------------------------------------
-const uint8_t MRS1_BA = 1;
-const uint8_t MRS2_BA = 2;
-
-#define MAX_PORTS 2
-#define MAX_DIMMS 2
-#define MAX_PRI_RANKS 4
-#define TOTAL_BYTES 10
-#define BITS_PER_REG 16
-#define DP18_INSTANCES 5
-#define BITS_PER_PORT (BITS_PER_REG*DP18_INSTANCES)
-
-//----------------------------------------------------------------------
-//  Enums
-//----------------------------------------------------------------------
-
-enum mss_draminit_training_result
-{
-    MSS_INIT_CAL_COMPLETE = 1,
-    MSS_INIT_CAL_PASS = 2,
-    MSS_INIT_CAL_STALL = 3,
-    MSS_INIT_CAL_FAIL = 4
-};
-
-
-extern "C" {
-
-
-//Sets the DQS offset to be 16 instead of 8, recommended training settings
-fapi::ReturnCode mss_setup_dqs_offset(Target &i_target);
-
-using namespace fapi;
-
-ReturnCode mss_draminit_training(Target& i_target);
-ReturnCode mss_draminit_training_cloned(Target& i_target);
-ReturnCode mss_check_cal_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group,  mss_draminit_training_result& io_status);
-ReturnCode mss_check_error_status(Target& i_target, uint8_t i_mbaPosition, uint8_t i_port, uint8_t i_group,  uint8_t cur_cal_step, mss_draminit_training_result& io_status, uint8_t i_max_cal_retry);
-ReturnCode mss_rtt_nom_rtt_wr_swap( Target& i_target, uint8_t i_mbaPosition, uint32_t i_port_number, uint8_t i_rank, uint32_t i_rank_pair_group, uint32_t& io_ccs_inst_cnt, uint8_t& io_dram_rtt_nom_original);
-ReturnCode mss_read_center_workaround(Target& i_target, uint8_t i_mbaPosition, uint32_t i_port, uint32_t i_rank_group);
-ReturnCode mss_read_center_second_workaround(Target& i_target);
-ReturnCode mss_disable_workaround( Target& i_target);
-ReturnCode mss_wr_lvl_disable_workaround( Target& i_target);
-ReturnCode mss_reset_delay_values(Target& i_target);
-
-ReturnCode getC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg, uint8_t &is_clean);
-ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port, const uint8_t i_dimm, const uint8_t i_rank, const ecmdDataBufferBase &i_reg);
-ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target);
-ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target, uint8_t i_training_success);
-ReturnCode mss_get_dqs_lane (const fapi::Target & i_mba, const uint8_t i_port, const uint8_t i_block, const uint8_t i_quad, uint8_t &lane);
-
-
-ReturnCode mss_draminit_training(Target& i_target)
-{
-    // Target is centaur.mba
-
-    fapi::ReturnCode l_rc;
-    uint8_t reset_disable;
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_DRAMINIT_RESET_DISABLE, NULL, reset_disable);
-    if(l_rc) return l_rc;
-
-
-    if (reset_disable != ENUM_ATTR_MSS_DRAMINIT_RESET_DISABLE_DISABLE)
-    {
-
-        l_rc = mss_reset_delay_values(i_target);
-        if (l_rc)
-        {
-        return l_rc;
-        }
-
-    }
-
-    l_rc = mss_draminit_training_cloned(i_target);
-    if (l_rc)
-    {
-        return l_rc;
-    }
-
-        // If mss_unmask_draminit_training_errors gets it's own bad rc,
-        // it will commit the passed in rc (if non-zero), and return it's own bad rc.
-        // Else if mss_unmask_draminit_training_errors runs clean,
-        // it will just return the passed in rc.
-        l_rc = mss_unmask_draminit_training_errors(i_target, l_rc);
-    if (l_rc)
-    {
-        return l_rc;
-    }
-
-        return l_rc;
-}
-
-
-
-
-ReturnCode mss_draminit_training_cloned(Target& i_target)
-{
-    // Target is centaur.mba
-    //Enums and Constants
-    enum size
-    {
-       MAX_NUM_PORT = 2,
-       MAX_NUM_DIMM = 2,
-       MAX_NUM_GROUP = 4,
-       MAX_CAL_STEPS = 7, //read course and write course will occur at the sametime
-       MAX_DQS_RETRY = 10, //Used for the DQS Alignment workaround.  Determines the number of DQS alignment retries.
-       INVALID = 255,
-       DELAY_0P5S = 500000000,
-       DELAY_LOOP = 6,
-       DELAY_SIM500  = 500
-    };
-
-    const uint32_t NUM_POLL = 10000;
-
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-
-    //Issue ZQ Cal first per rank
-    uint32_t instruction_number = 0;
-    ecmdDataBufferBase address_buffer_16(16);
-    rc_num = rc_num | address_buffer_16.flushTo0();
-    ecmdDataBufferBase bank_buffer_8(8);
-    rc_num = rc_num | bank_buffer_8.flushTo0();
-    ecmdDataBufferBase activate_buffer_1(1);
-    rc_num = rc_num | activate_buffer_1.flushTo0();
-    ecmdDataBufferBase rasn_buffer_1(1);
-    ecmdDataBufferBase casn_buffer_1(1);
-    ecmdDataBufferBase wen_buffer_1(1);
-    ecmdDataBufferBase cke_buffer_8(8);
-    rc_num = rc_num | cke_buffer_8.flushTo1();
-    ecmdDataBufferBase csn_buffer_8(8);
-    rc_num = rc_num | csn_buffer_8.flushTo1();
-    ecmdDataBufferBase odt_buffer_8(8);
-    rc_num = rc_num | odt_buffer_8.flushTo0();
-    ecmdDataBufferBase test_buffer_4(4);
-
-    ecmdDataBufferBase num_idles_buffer_16(16);
-    rc_num = rc_num | num_idles_buffer_16.flushTo1();
-    ecmdDataBufferBase num_repeat_buffer_16(16);
-    rc_num = rc_num | num_repeat_buffer_16.flushTo0();
-    ecmdDataBufferBase data_buffer_20(20);
-    rc_num = rc_num | data_buffer_20.flushTo0();
-    ecmdDataBufferBase read_compare_buffer_1(1);
-    rc_num = rc_num | read_compare_buffer_1.flushTo0();
-    ecmdDataBufferBase rank_cal_buffer_4(4);
-    rc_num = rc_num | rank_cal_buffer_4.flushTo0();
-    ecmdDataBufferBase ddr_cal_enable_buffer_1(1);
-    ecmdDataBufferBase ccs_end_buffer_1(1);
-    rc_num = rc_num | ccs_end_buffer_1.flushTo1();
-
-
-    ecmdDataBufferBase stop_on_err_buffer_1(1);
-    rc_num = rc_num | stop_on_err_buffer_1.flushTo0();
-    ecmdDataBufferBase cal_timeout_cnt_buffer_16(16);
-    rc_num = rc_num | cal_timeout_cnt_buffer_16.flushTo1();
-    ecmdDataBufferBase resetn_buffer_1(1);
-    rc_num = rc_num | resetn_buffer_1.setBit(0);
-    ecmdDataBufferBase cal_timeout_cnt_mult_buffer_2(2);
-    rc_num = rc_num | cal_timeout_cnt_mult_buffer_2.flushTo1();
-
-    ecmdDataBufferBase data_buffer_64(64);
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    uint8_t port = 0;
-    uint8_t group = 0;
-    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
-    uint8_t cal_steps = 0;
-    uint8_t delay_loop_cnt =0;
-    uint8_t dqs_try = 0;        //part of DQS alignment workaround
-    uint8_t dqs_retry_num = 0;  //part of DQS alignment workaround
-    uint8_t max_cal_retry = 0;  //part of DQS alignment workaround added this to be a more generic var to pass into a proc.  May be used if we need to add a retry to another cal step
-    uint8_t cur_cal_step = 0;
-    ecmdDataBufferBase cal_steps_8(8);
-
-    uint8_t l_nwell_misplacement = 0;
-    uint8_t dram_rtt_nom_original = 0;
-    uint8_t training_success = 0;
-
-    fapi::Target l_target_centaur;
-    rc = fapiGetParentChip(i_target, l_target_centaur);
-    if(rc) return rc;
-
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-
-    uint8_t dram_gen = 0;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
-    if(rc) return rc;
-
-    uint8_t waterfall_broken = 0;
-    rc = FAPI_ATTR_GET(ATTR_MSS_BLUEWATERFALL_BROKEN, &l_target_centaur, waterfall_broken);
-    if(rc) return rc;
-
-    enum mss_draminit_training_result cur_complete_status = MSS_INIT_CAL_COMPLETE;
-    enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS;
-
-    enum mss_draminit_training_result complete_status = MSS_INIT_CAL_COMPLETE;
-    enum mss_draminit_training_result error_status = MSS_INIT_CAL_PASS;
-
-    //populate primary_ranks_arrays_array
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
-    if(rc) return rc;
-
-    rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, l_nwell_misplacement);
-    if(rc) return rc;
-
-    uint8_t mbaPosition;
-    // Get MBA position: 0 = mba01, 1 = mba23
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition);
-    if(rc)
-    {
-        FAPI_ERR("Error getting MBA position");
-        return rc;
-    }
-
-
-
-    //Get which training steps we are to run
-    rc = FAPI_ATTR_GET(ATTR_MSS_CAL_STEP_ENABLE, &i_target, cal_steps);
-    if(rc) return rc;
-    rc_num = rc_num | cal_steps_8.insert(cal_steps, 0, 8, 0);
-
-    /*
-    Disabling spare CKE bit modify for SW275629.  This bit will be modified via initfile.
-
-
-    //Setup SPARE CKE enable bit
-    rc = fapiGetScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64);
-    if(rc) return rc;
-    rc_num = rc_num | data_buffer_64.setBit(42);
-    rc = fapiPutScom(i_target, MBA01_MBARPC0Q_0x03010434, data_buffer_64);
-    if(rc) return rc;
-
-    */
-
-    //Set up CCS Mode Reg for Init cal
-    rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
-    if(rc) return rc;
-
-    rc_num = rc_num | data_buffer_64.insert(stop_on_err_buffer_1, 0, 1, 0);
-    rc_num = rc_num | data_buffer_64.insert(cal_timeout_cnt_buffer_16, 8, 16, 0);
-    rc_num = rc_num | data_buffer_64.insert(resetn_buffer_1, 24, 1, 0);
-    rc_num = rc_num | data_buffer_64.insert(cal_timeout_cnt_mult_buffer_2, 30, 2, 0);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
-    if(rc) return rc;
-
-
-    rc = mss_set_bbm_regs (i_target);
-    if(rc)
-    {
-        FAPI_ERR( "Error Moving bad bit information to the Phy regs. Exiting.");
-        return rc;
-    }
-
-
-
-    if ( ( cal_steps_8.isBitSet(0) ) ||
-         ( (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) &&
-           (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) &&
-           (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
-           (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) ))
-    {
-        FAPI_INF( "Performing External ZQ Calibration on %s.", i_target.toEcmdString());
-
-        //Execute ZQ_CAL
-        for(port = 0; port < MAX_NUM_PORT; port++)
-        {
-            rc = mss_execute_zq_cal(i_target, port);
-            if(rc) return rc;
-
-        }
-
-        if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) &&
-                                (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
-        {
-            FAPI_INF("Performing LRDIMM MB-DRAM training");
-
-            // Execute MB-DRAM training
-            rc = mss_execute_lrdimm_mb_dram_training(i_target);
-            if (rc) return rc;
-        }
-        //executes the following to ensure that DRAMS have a good intial WR VREF DQ
-        //1) enter training mode w/ old value (nominal VREF DQ)
-        //2) set value in training mode (nominal VREF DQ)
-        //3) exit training mode (nominal VREF DQ)
-        else if(dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) {
-           FAPI_INF("For DDR4, setting VREFDQ to have an initial value!!!!");
-           uint8_t train_enable[2][2][4];
-           uint8_t train_enable_override_on[2][2][4] ={{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}},{{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE},{ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE,ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_ENABLE}}};
-
-           rc = FAPI_ATTR_GET( ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable);
-           if(rc) return rc;
-
-           rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable_override_on);
-           if(rc) return rc;
-
-           //runs new values w/ train enable forces on
-           FAPI_INF("RUN MRS6 1ST");
-           rc = mss_mrs6_DDR4(  i_target);
-           if(rc) return rc;
-           FAPI_INF("RUN MRS6 2ND");
-           rc = mss_mrs6_DDR4( i_target);
-           if(rc) return rc;
-
-           //set old train enable value
-           rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target, train_enable);
-           if(rc) return rc;
-
-           FAPI_INF("RUN MRS6 3RD");
-           rc = mss_mrs6_DDR4( i_target);
-           if(rc) return rc;
-
-           //sets up the DQS offset to be 16 instead of 8
-           rc = mss_setup_dqs_offset(i_target);
-           if(rc) return rc;
-        }
-        //have to do ZQ cal, then DDR4 training mode for initial VREF setup, then do LR training
-        for(port = 0; port < MAX_NUM_PORT; port++)
-        {
-
-            // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
-            if ( (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4) &&
-                 (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
-            {
-                 rc = mss_mrep_training(i_target, port);
-                 if(rc) return rc;
-                 rc = mss_mxd_training(i_target,port,0);
-                 if(rc) return rc;
-            }
-        }
-    }
-
-    for(port = 0; port < MAX_NUM_PORT; port++)
-    {
-
-        for(group = 0; group < MAX_NUM_GROUP; group++)
-        {
-
-            //Check if rank group exists
-            if(primary_ranks_array[group][port] != INVALID)
-            {
-
-                //Set up for Init Cal - Done per port pair
-                rc_num = rc_num | test_buffer_4.setBit(0, 2); //Init Cal test = 11XX
-                rc_num = rc_num | wen_buffer_1.flushTo1(); //Init Cal ras/cas/we = 1/1/1
-                rc_num = rc_num | casn_buffer_1.flushTo1();
-                rc_num = rc_num | rasn_buffer_1.flushTo1();
-                rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1(); //Init cal
-
-                FAPI_INF( "+++ Setting up Init Cal on %s Port: %d rank group: %d cal_steps: 0x%02X +++", i_target.toEcmdString(), port, group, cal_steps);
-
-                for(cur_cal_step = 1; cur_cal_step < MAX_CAL_STEPS; cur_cal_step++) //Cycle through all possible cal steps
-                {
-                    //DQS alignment workaround
-                    max_cal_retry = 0;
-
-                    //Clearing any status or errors bits that may have occured in previous training subtest.
-                    if(port == 0)
-                    {
-                        //clear status reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear error reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 11);
-                        rc_num = rc_num | data_buffer_64.clearBit(60, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear other port
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48);
-                        rc_num = rc_num | data_buffer_64.clearBit(50);
-                        rc_num = rc_num | data_buffer_64.clearBit(51);
-                        rc_num = rc_num | data_buffer_64.clearBit(52);
-                        rc_num = rc_num | data_buffer_64.clearBit(53);
-                        rc_num = rc_num | data_buffer_64.clearBit(54);
-                        rc_num = rc_num | data_buffer_64.clearBit(55);
-                        rc_num = rc_num | data_buffer_64.clearBit(58);
-                        rc_num = rc_num | data_buffer_64.clearBit(60);
-                        rc_num = rc_num | data_buffer_64.clearBit(61);
-                        rc_num = rc_num | data_buffer_64.clearBit(62);
-                        rc_num = rc_num | data_buffer_64.clearBit(63);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //Setup the Config Reg bit for the only cal step we want
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                    }
-                    else
-                    {
-                        //clear status reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear error reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 11);
-                        rc_num = rc_num | data_buffer_64.clearBit(60, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear other port
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48);
-                        rc_num = rc_num | data_buffer_64.clearBit(50);
-                        rc_num = rc_num | data_buffer_64.clearBit(51);
-                        rc_num = rc_num | data_buffer_64.clearBit(52);
-                        rc_num = rc_num | data_buffer_64.clearBit(53);
-                        rc_num = rc_num | data_buffer_64.clearBit(54);
-                        rc_num = rc_num | data_buffer_64.clearBit(55);
-                        rc_num = rc_num | data_buffer_64.clearBit(58);
-                        rc_num = rc_num | data_buffer_64.clearBit(60);
-                        rc_num = rc_num | data_buffer_64.clearBit(61);
-                        rc_num = rc_num | data_buffer_64.clearBit(62);
-                        rc_num = rc_num | data_buffer_64.clearBit(63);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //Setup the Config Reg bit for the only cal step we want
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                    }
-
-                    //Clear training cnfg
-                    rc_num = rc_num | data_buffer_64.clearBit(48);
-                    rc_num = rc_num | data_buffer_64.clearBit(50);
-                    rc_num = rc_num | data_buffer_64.clearBit(51);
-                    rc_num = rc_num | data_buffer_64.clearBit(52);
-                    rc_num = rc_num | data_buffer_64.clearBit(53);
-                    rc_num = rc_num | data_buffer_64.clearBit(54);
-                    rc_num = rc_num | data_buffer_64.clearBit(55);
-                    rc_num = rc_num | data_buffer_64.clearBit(60);
-                    rc_num = rc_num | data_buffer_64.clearBit(61);
-                    rc_num = rc_num | data_buffer_64.clearBit(62);
-                    rc_num = rc_num | data_buffer_64.clearBit(63);
-
-                    //Set stop on error
-                    rc_num = rc_num | data_buffer_64.setBit(58);
-
-                    //cnfg rank groups
-                    if(group == 0){
-                        rc_num = rc_num | data_buffer_64.setBit(60);
-                    }
-                    else if(group == 1){
-                        rc_num = rc_num | data_buffer_64.setBit(61);
-                    }
-                    else if(group == 2){
-                        rc_num = rc_num | data_buffer_64.setBit(62);
-                    }
-                    else if(group == 3){
-                        rc_num = rc_num | data_buffer_64.setBit(63);
-                    }
-
-                    if ( (cur_cal_step == 1) && (cal_steps_8.isBitClear(0)) && (cal_steps_8.isBitClear(1)) &&
-                         (cal_steps_8.isBitClear(2)) && (cal_steps_8.isBitClear(3)) &&
-                         (cal_steps_8.isBitClear(4)) && (cal_steps_8.isBitClear(5)) &&
-                         (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitClear(7)) )
-                    {
-                        FAPI_INF( "+++ Executing ALL Cal Steps at the same time on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(48);
-                        rc_num = rc_num | data_buffer_64.setBit(50);
-                        rc_num = rc_num | data_buffer_64.setBit(51);
-                        rc_num = rc_num | data_buffer_64.setBit(52);
-                        rc_num = rc_num | data_buffer_64.setBit(53);
-                        rc_num = rc_num | data_buffer_64.setBit(54);
-                        rc_num = rc_num | data_buffer_64.setBit(55);
-                    }
-                    else if ( (cur_cal_step == 1) && (cal_steps_8.isBitSet(1)) )
-                    {
-                        FAPI_INF( "+++ Write Leveling (WR_LVL) on %s Port %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(48);
-                    }
-                    else if ( (cur_cal_step == 2) && (cal_steps_8.isBitSet(2)) )
-                    {
-                        max_cal_retry = 0;
-                        dqs_try = dqs_retry_num + 1;
-                        FAPI_INF( "+++ DQS Align (DQS_ALIGN) attempt %d on %s Port: %d rank group: %d +++", dqs_try,i_target.toEcmdString(), port, group);
-                        if (dqs_try == MAX_DQS_RETRY)
-                        {
-                           max_cal_retry = 1;
-                           FAPI_INF( "+++ DQS Align (DQS_ALIGN) final attempt!");
-
-                        }
-                        rc_num = rc_num | data_buffer_64.setBit(50);
-                    }
-                    else if ( (cur_cal_step == 3) && (cal_steps_8.isBitSet(3)) )
-                    {
-                        FAPI_INF( "+++ RD CLK Align (RDCLK_ALIGN) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(51);
-                    }
-                    else if ( (cur_cal_step == 4) && (cal_steps_8.isBitSet(4)) )
-                    {
-                        FAPI_INF( "+++ Read Centering (READ_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(52);
-                    }
-                    else if ( (cur_cal_step == 5) && (cal_steps_8.isBitSet(5)) )
-                    {
-                        FAPI_INF( "+++ Write Centering (WRITE_CTR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(53);
-                    }
-                    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitClear(7)) )
-                    {
-                        FAPI_INF( "+++ Initial Course Write (COURSE_WR) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(54);
-                    }
-                    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitClear(6)) && (cal_steps_8.isBitSet(7)) )
-                    {
-                        FAPI_INF( "+++ Course Read (COURSE_RD) on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(55);
-                    }
-                    else if ( (cur_cal_step == 6) && (cal_steps_8.isBitSet(6)) && (cal_steps_8.isBitSet(7)) )
-                    {
-                        FAPI_INF( "+++ Initial Course Write (COURSE_WR) and Course Read (COURSE_RD) simultaneously on %s Port: %d rank group: %d +++", i_target.toEcmdString(), port, group);
-                        rc_num = rc_num | data_buffer_64.setBit(54);
-                        rc_num = rc_num | data_buffer_64.setBit(55);
-                    }
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-                    if ( !( data_buffer_64.isBitClear(48, 8) ) ) // Only execute if we are doing a Cal Step
-                    {
-
-                        // Before WR_LVL --- Change the RTT_NOM to RTT_WR pre-WR_LVL
-                        if ( (cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3))
-                        {
-                            if ( dimm_type != fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
-                            {
-
-                               dram_rtt_nom_original = 0xFF;
-                               rc = mss_rtt_nom_rtt_wr_swap(i_target,
-                                                         mbaPosition,
-                                                         port,
-                                                         primary_ranks_array[group][port],
-                                                         group,
-                                                         instruction_number,
-                                                         dram_rtt_nom_original);
-                               if(rc) return rc;
-                            }
-                        }
-                        // Should only be called for DDR4 LRDIMMs, training code is in development. Does not effect any other configs
-                        else if ( (group == 0) && (cur_cal_step == 1)
-                                  && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-                                  && (dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) )
-                        {
-                           rc = mss_dram_write_leveling(i_target, port);
-                           if(rc) return rc;
-                        }
-
-                        //Set the config register
-                        if(port == 0)
-                        {
-                            rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                            if(rc) return rc;
-                        }
-                        else
-                        {
-                            rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                            if(rc) return rc;
-                        }
-
-                        rc = mss_ccs_inst_arry_0(i_target,
-                                                 instruction_number,
-                                                 address_buffer_16,
-                                                 bank_buffer_8,
-                                                 activate_buffer_1,
-                                                 rasn_buffer_1,
-                                                 casn_buffer_1,
-                                                 wen_buffer_1,
-                                                 cke_buffer_8,
-                                                 csn_buffer_8,
-                                                 odt_buffer_8,
-                                                 test_buffer_4,
-                                                 port);
-
-                        if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-                        FAPI_INF( "primary_ranks_array[%d][0]: %d [%d][1]: %d", group, primary_ranks_array[group][0], group, primary_ranks_array[group][1]);
-
-
-                        rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[group][port], 0, 4, 4); // 8 bit storage, need last 4 bits
-                        if(rc_num)
-                        {
-                                rc.setEcmdError(rc_num);
-                                return rc;
-                        }
-
-                        rc = mss_ccs_inst_arry_1(i_target,
-                                                 instruction_number,
-                                                 num_idles_buffer_16,
-                                                 num_repeat_buffer_16,
-                                                 data_buffer_20,
-                                                 read_compare_buffer_1,
-                                                 rank_cal_buffer_4,
-                                                 ddr_cal_enable_buffer_1,
-                                                 ccs_end_buffer_1);
-
-                        if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-
-                        rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
-                        if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-                        //Check to see if the training completes
-                        rc = mss_check_cal_status(i_target, mbaPosition, port, group, cur_complete_status);
-                        if(rc) return rc;
-
-                        if (cur_complete_status == MSS_INIT_CAL_STALL)
-                        {
-                            complete_status = cur_complete_status;
-                        }
-
-                        //Check to see if the training errored out
-                        rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status, max_cal_retry);
-                        if(rc) return rc;
-
-                        if (cur_error_status == MSS_INIT_CAL_FAIL)
-                        {
-                            error_status = cur_error_status;
-
-                        }
-
-                        // Following WR_LVL -- Restore RTT_NOM to orignal value post-wr_lvl
-                        if ((cur_cal_step == 1) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3))
-                        {
-                            if ( dimm_type != fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
-                            {
-
-                               rc = mss_rtt_nom_rtt_wr_swap(i_target,
-                                                         mbaPosition,
-                                                         port,
-                                                         primary_ranks_array[group][port],
-                                                         group,
-                                                         instruction_number,
-                                                         dram_rtt_nom_original);
-                               if(rc) return rc;
-                            }
-                        }
-
-                        // Following Read Centering -- Enter into READ CENTERING WORKAROUND
-                        if  ( (cur_cal_step == 4) &&
-                            ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE  ) )
-                        {
-                                rc = mss_read_center_workaround(i_target, mbaPosition, port, group);
-                                if(rc) return rc;
-                        }
-
-                        // DQS Alignment workaround
-                        if (cur_cal_step == 2)
-                        {
-                           // Because the DQS cal step failed we need to rerun the step and clear out any bad bits
-                           if (cur_error_status == MSS_INIT_CAL_FAIL)
-                           {
-
-                              if (dqs_try < MAX_DQS_RETRY)
-                              {
-                                 dqs_retry_num++;
-                                 cur_cal_step-- ;
-                                 for(delay_loop_cnt = 1; delay_loop_cnt <= DELAY_LOOP; delay_loop_cnt++)
-                                 {
-                                    rc = fapiDelay(DELAY_0P5S, DELAY_SIM500);
-                                    if(rc) return rc;
-                                 }
-                                 delay_loop_cnt = 0;
-                              }
-                              else if (dqs_try == MAX_DQS_RETRY)
-                              {
-                                 dqs_retry_num = 0;
-                              }
-                           }
-                           //If the DQS cal step passes on a retry, we need to reset the error status to a pass.
-                           else if (cur_error_status == MSS_INIT_CAL_PASS)
-                           {
-                              if (dqs_try > 1)
-                              {
-                                 error_status = MSS_INIT_CAL_PASS;
-                                 dqs_retry_num = 0;
-                              }
-
-                              dqs_retry_num = 0;
-
-                           }
-
-                        }
-
-
-                    }
-                }//end of step loop
-            }
-        }//end of group loop
-    }//end of port loop
-
-    // Make sure the DQS_CLK values of each byte have matching nibble values, using the lowest
-    if ( waterfall_broken == fapi::ENUM_ATTR_MSS_BLUEWATERFALL_BROKEN_TRUE )
-    {
-                rc = mss_read_center_second_workaround(i_target);
-                if(rc) return rc;
-    }
-
-    if ((error_status != MSS_INIT_CAL_FAIL) && (error_status != MSS_INIT_CAL_STALL))
-    {
-        training_success = 0xFF;
-    }
-
-    rc = mss_get_bbm_regs(i_target, training_success);
-    if(rc)
-    {
-        FAPI_ERR( "Error Moving bad bit information from the Phy regs. Exiting.");
-        return rc;
-    }
-
-    //Executes if we do "all at once" or on the last cal steps
-    //Must be a successful run.
-    if (error_status == MSS_INIT_CAL_PASS &&
-        ((cal_steps_8.isBitSet(6) && cal_steps_8.isBitSet(7)) ||
-         (cal_steps_8.isBitClear(0) && cal_steps_8.isBitClear(1) &&
-          cal_steps_8.isBitClear(2) && cal_steps_8.isBitClear(3) &&
-          cal_steps_8.isBitClear(4) && cal_steps_8.isBitClear(5) &&
-          cal_steps_8.isBitClear(6) && cal_steps_8.isBitClear(7) ) ) )
-    {
-
-        FAPI_INF( "WR LVL DISABLE WORKAROUND: Running wr_lvl workaround on %s", i_target.toEcmdString());
-        rc = mss_wr_lvl_disable_workaround(i_target);
-        if(rc) return rc;
-    }
-
-
-    // If we hit either of these States, the error callout originates from Mike Jones Bad Bit code.
-    if (complete_status == MSS_INIT_CAL_STALL)
-    {
-        FAPI_ERR( "+++ Partial/Full calibration stall. Check Debug trace. +++");
-    }
-    else if (error_status == MSS_INIT_CAL_FAIL)
-    {
-        FAPI_ERR( "+++ Partial/Full calibration fail. Check Debug trace. +++");
-    }
-    else
-    {
-        FAPI_INF( "+++ Full calibration successful. +++");
-    }
-
-    return rc;
-}
-
-ReturnCode mss_check_cal_status( Target& i_target,
-                                 uint8_t i_mbaPosition,
-                                 uint8_t i_port,
-                                 uint8_t i_group,
-                                 mss_draminit_training_result& io_status
-                               )
-{
-    ecmdDataBufferBase cal_status_buffer_64(64);
-
-    uint8_t poll_count = 1;
-    uint32_t cal_status_reg_offset;
-
-    cal_status_reg_offset = 48 + i_group;
-
-    ReturnCode rc;
-
-    if(i_port == 0)
-    {
-        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, cal_status_buffer_64);
-        if(rc) return rc;
-    }
-    else
-    {
-        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, cal_status_buffer_64);
-        if(rc) return rc;
-    }
-
-    while((!cal_status_buffer_64.isBitSet(cal_status_reg_offset)) &&
-          (poll_count <= 20))
-    {
-        FAPI_INF( "+++ Calibration on %s port: %d rank group: %d in progress. Poll count: %d +++", i_target.toEcmdString(), i_port, i_group, poll_count);
-
-        poll_count++;
-        if(i_port == 0)
-        {
-            rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, cal_status_buffer_64);
-            if(rc) return rc;
-        }
-        else
-        {
-            rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, cal_status_buffer_64);
-            if(rc) return rc;
-        }
-
-    }
-
-    if(cal_status_buffer_64.isBitSet(cal_status_reg_offset))
-    {
-        FAPI_INF( "+++ Calibration on %s port: %d rank group: %d finished. +++", i_target.toEcmdString(), i_port, i_group);
-        io_status = MSS_INIT_CAL_COMPLETE;
-    }
-    else
-    {
-        FAPI_ERR( "+++ Calibration on %s port: %d rank group: %d has stalled! +++", i_target.toEcmdString(), i_port, i_group);
-        io_status = MSS_INIT_CAL_STALL;
-    }
-
-    return rc;
-}
-
-
-
-ReturnCode mss_check_error_status( Target& i_target,
-                                 uint8_t i_mbaPosition,
-                                 uint8_t i_port,
-                                 uint8_t i_group,
-                                 uint8_t cur_cal_step,
-                                 mss_draminit_training_result& io_status,
-                                 uint8_t i_max_cal_retry
-                               )
-{
-
-    ecmdDataBufferBase cal_error_buffer_64(64);
-    ReturnCode rc;
-
-    uint8_t MBA_POSITION;
-    uint8_t PORT_POSITION;
-    uint8_t RANKGROUP_POSITION;
-
-    if(i_port == 0)
-    {
-        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, cal_error_buffer_64);
-        if(rc) return rc;
-    }
-    else
-    {
-        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, cal_error_buffer_64);
-        if(rc) return rc;
-    }
-
-    if((cal_error_buffer_64.isBitSet(60)) || (cal_error_buffer_64.isBitSet(61)) || (cal_error_buffer_64.isBitSet(62)) || (cal_error_buffer_64.isBitSet(63)))
-    {
-        io_status = MSS_INIT_CAL_FAIL;
-
-        if(cal_error_buffer_64.isBitSet(48))
-        {
-            FAPI_ERR( "+++ Write leveling error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_LVL_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(50))
-        {
-            FAPI_ERR( "+++ DQS Alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-
-            // Error Callout ByPass for Work Around:
-            //FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR);
-            //fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            //rc = FAPI_RC_SUCCESS;
-
-            // DQS Alignment Work Around:
-            if (i_max_cal_retry == 0)
-            {
-                FAPI_INF( "+++ DQS Alignment recovery attempt on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-                uint64_t disable_bit_addr_for_dp18_0 = 0;
-                uint64_t disable_bit_addr_for_dp18_1 = 0;
-                uint64_t disable_bit_addr_for_dp18_2 = 0;
-                uint64_t disable_bit_addr_for_dp18_3 = 0;
-                uint64_t disable_bit_addr_for_dp18_4 = 0;
-                if (i_port == 0) {
-                   if (i_group == 0) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F;
-                   } else if (i_group == 1) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F;
-                   } else if (i_group == 2) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F;
-                   } else if (i_group == 3) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F;
-                   } else {
-                      FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-                      FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR);
-                      fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-                      rc = FAPI_RC_SUCCESS;
-                   }
-                } else if (i_port == 1) {
-                   if (i_group == 0) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F;                              disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F;
-                   } else if (i_group == 1) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F;                              disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F;
-                   } else if (i_group == 2) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F;
-                   } else if (i_group == 3) {
-                      disable_bit_addr_for_dp18_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F;
-                      disable_bit_addr_for_dp18_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F;
-                      disable_bit_addr_for_dp18_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F;
-                      disable_bit_addr_for_dp18_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F;
-                      disable_bit_addr_for_dp18_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F;
-                   } else {
-                      FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-                      FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR);
-                      fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-                      rc = FAPI_RC_SUCCESS;
-                   }
-                } else {
-                      FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-                      FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR);
-                      fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-                      rc = FAPI_RC_SUCCESS;
-                }
-                ecmdDataBufferBase disable_bit_data_for_dp18_buffer_64(64);
-                disable_bit_data_for_dp18_buffer_64.flushTo0();
-                rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_0, disable_bit_data_for_dp18_buffer_64); if(rc) return rc;
-                rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_1, disable_bit_data_for_dp18_buffer_64); if(rc) return rc;
-                rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_2, disable_bit_data_for_dp18_buffer_64); if(rc) return rc;
-                rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_3, disable_bit_data_for_dp18_buffer_64); if(rc) return rc;
-                rc = fapiPutScom(i_target, disable_bit_addr_for_dp18_4, disable_bit_data_for_dp18_buffer_64); if(rc) return rc;
-            } else {
-                FAPI_ERR( "+++ DQS Alignment Recovery error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DQS_ALIGNMENT_ERROR);
-                fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-                rc = FAPI_RC_SUCCESS;
-            }
-
-        }
-        if(cal_error_buffer_64.isBitSet(51))
-        {
-            FAPI_ERR( "+++ RDCLK to SysClk alignment error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CLK_SYS_CLK_ALIGNMENT_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(52))
-        {
-            FAPI_ERR( "+++ Read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_RD_CENTERING_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(53))
-        {
-            FAPI_ERR( "+++ Write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_WR_CENTERING_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(55))
-        {
-            FAPI_ERR( "+++ Coarse read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_COURSE_RD_CENTERING_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(56))
-        {
-            FAPI_ERR( "+++ Custom pattern read centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_RD_CENTERING_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(57))
-        {
-            FAPI_ERR( "+++ Custom pattern write centering error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_CUSTOM_PATTERN_WR_CENTERING_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-        if(cal_error_buffer_64.isBitSet(58))
-        {
-            FAPI_ERR( "+++ Digital eye error occured on %s port: %d rank group: %d! +++", i_target.toEcmdString(), i_port, i_group);
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-            MBA_POSITION = i_mbaPosition;
-            PORT_POSITION = i_port;
-            RANKGROUP_POSITION = i_group;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIGITAL_EYE_ERROR);
-            fapiLogError(rc, FAPI_ERRL_SEV_RECOVERED);
-            rc = FAPI_RC_SUCCESS;
-        }
-    }
-    else
-    {
-        if (cur_cal_step == 1)
-        {
-            FAPI_INF( "+++ Write_leveling on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
-        }
-        else if (cur_cal_step == 2)
-        {
-            FAPI_INF( "+++ DQS Alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
-        }
-        else if (cur_cal_step == 3)
-        {
-            FAPI_INF( "+++ RDCLK to SysClk alignment on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
-        }
-        else if (cur_cal_step == 4)
-        {
-            FAPI_INF( "+++ Read Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
-        }
-        else if (cur_cal_step == 5)
-        {
-            FAPI_INF( "+++ Write Centering on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
-        }
-        else if (cur_cal_step == 6)
-        {
-            FAPI_INF( "+++ Course Read and/or Course Write on %s port: %d rank group: %d was successful. +++", i_target.toEcmdString(), i_port, i_group);
-        }
-
-        io_status = MSS_INIT_CAL_PASS;
-    }
-
-    return rc;
-}
-
-
-
-
-
-
-
-ReturnCode mss_read_center_workaround(
-            Target& i_target,
-            uint8_t i_mbaPosition,
-            uint32_t i_port,
-            uint32_t i_rank_group
-            )
-{
-
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer_64(64);
-
-
-    uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0;
-    uint64_t RD_TIMING_REF0_ADDR_0 = 0;
-    uint64_t RD_TIMING_REF0_ADDR_1 = 0;
-    uint64_t RD_TIMING_REF0_ADDR_2 = 0;
-    uint64_t RD_TIMING_REF0_ADDR_3 = 0;
-    uint64_t RD_TIMING_REF0_ADDR_4 = 0;
-    uint64_t RD_TIMING_REF1_ADDR_0 = 0;
-    uint64_t RD_TIMING_REF1_ADDR_1 = 0;
-    uint64_t RD_TIMING_REF1_ADDR_2 = 0;
-    uint64_t RD_TIMING_REF1_ADDR_3 = 0;
-    uint64_t RD_TIMING_REF1_ADDR_4 = 0;
-    uint8_t l_value_u8 = 0;
-    uint8_t l_new_value_u8 = 0;
-    uint8_t quad0_workaround_type = 2;
-    uint8_t quad1_workaround_type = 2;
-    uint8_t quad2_workaround_type = 2;
-    uint8_t quad3_workaround_type = 2;
-    uint8_t dqs_clk_increment_wa0 = 0;
-    uint8_t dqs_clk_increment_wa1 = 3;
-    uint8_t dqs_clk_increment_wa2 = 2;
-    uint8_t read_phase_value_wa0 = 0;
-    uint8_t read_phase_value_wa1 = 0;
-    uint8_t read_phase_value_wa2 = 0;
-    uint8_t dqs_clk_increment_quad0 = 2;
-    uint8_t dqs_clk_increment_quad1 = 2;
-    uint8_t dqs_clk_increment_quad2 = 2;
-    uint8_t dqs_clk_increment_quad3 = 2;
-    uint8_t read_phase_value_quad0 = 0;
-    uint8_t read_phase_value_quad1 = 0;
-    uint8_t read_phase_value_quad2 = 0;
-    uint8_t read_phase_value_quad3 = 0;
-    uint8_t l_timing_ref_quad0 = 0;
-    uint8_t l_timing_ref_quad1 = 0;
-    uint8_t l_timing_ref_quad2 = 0;
-    uint8_t l_timing_ref_quad3 = 0;
-
-    FAPI_INF( "+++ Read Centering Workaround on %s Port: %d rank group: %d +++", i_target.toEcmdString(), i_port, i_rank_group);
-    FAPI_INF( "+++ Choosing New RD PHASE SELECT values based on timing values. +++");
-    FAPI_INF( "+++ Incrementing DQS CLK PHASE SELECT regs based on timing values. +++");
-
-    if ( i_port == 0 )
-    {
-
-        RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_0_0x800000700301143F;
-        RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_1_0x800004700301143F;
-        RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_2_0x800008700301143F;
-        RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_3_0x80000C700301143F;
-        RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P0_4_0x800010700301143F;
-        RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_0_0x800000710301143F;
-        RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_1_0x800004710301143F;
-        RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_2_0x800008710301143F;
-        RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_3_0x80000C710301143F;
-        RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P0_4_0x800010710301143F;
-
-        if ( i_rank_group == 0 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-
-        }
-        else if ( i_rank_group == 1 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-
-        }
-        else if ( i_rank_group == 2 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-
-        }
-        else if ( i_rank_group == 3 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-
-        }
-    }
-    else if (i_port == 1 )
-    {
-
-        RD_TIMING_REF0_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_0_0x800100700301143F;
-        RD_TIMING_REF0_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_1_0x800104700301143F;
-        RD_TIMING_REF0_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_2_0x800108700301143F;
-        RD_TIMING_REF0_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_3_0x80010C700301143F;
-        RD_TIMING_REF0_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE0_P1_4_0x800110700301143F;
-        RD_TIMING_REF1_ADDR_0 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_0_0x800100710301143F;
-        RD_TIMING_REF1_ADDR_1 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_1_0x800104710301143F;
-        RD_TIMING_REF1_ADDR_2 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_2_0x800108710301143F;
-        RD_TIMING_REF1_ADDR_3 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_3_0x80010C710301143F;
-        RD_TIMING_REF1_ADDR_4 = DPHY01_DDRPHY_DP18_READ_TIMING_REFERENCE1_P1_4_0x800110710301143F;
-
-        if ( i_rank_group == 0 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-
-        }
-        else if ( i_rank_group == 1 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-
-
-        }
-        else if ( i_rank_group == 2 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-
-        }
-        else if ( i_rank_group == 3 )
-        {
-            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-
-        }
-    }
-
-    //Block 0
-    rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_0, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7);
-    rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_0, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7);
-
-        if(rc_num)
-        {
-        rc.setEcmdError(rc_num);
-        return rc;
-        }
-
-    if ( quad0_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa0;
-        read_phase_value_quad0 = read_phase_value_wa0;
-    }
-    else if ( quad0_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa1;
-        read_phase_value_quad0 = read_phase_value_wa1;
-    }
-    else if ( quad0_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
-        read_phase_value_quad0 = read_phase_value_wa2;
-    }
-    FAPI_INF( "+++ ALL Blocks ALL Quads using workaround number %d with dqs_clk_increment: %d read_phase_value: %d +++", quad0_workaround_type, dqs_clk_increment_quad0, read_phase_value_quad0);
-
-    if ( quad1_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa0;
-        read_phase_value_quad1 = read_phase_value_wa0;
-    }
-    else if ( quad1_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa1;
-        read_phase_value_quad1 = read_phase_value_wa1;
-    }
-    else if ( quad1_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
-        read_phase_value_quad1 = read_phase_value_wa2;
-    }
-
-    if ( quad2_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa0;
-        read_phase_value_quad2 = read_phase_value_wa0;
-    }
-    else if ( quad2_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa1;
-        read_phase_value_quad2 = read_phase_value_wa1;
-    }
-    else if ( quad2_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
-        read_phase_value_quad2 = read_phase_value_wa2;
-    }
-
-    if ( quad3_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa0;
-        read_phase_value_quad3 = read_phase_value_wa0;
-    }
-    else if ( quad3_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa1;
-        read_phase_value_quad3 = read_phase_value_wa1;
-    }
-    else if ( quad3_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
-        read_phase_value_quad3 = read_phase_value_wa2;
-    }
-
-    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-    if (rc) return rc;
-
-    // Set Read Phase.
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2);
-
-    //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2)
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2);
-
-    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-    if (rc) return rc;
-
-    //Block 1
-    rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_1, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7);
-    rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_1, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7);
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    if ( quad0_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa0;
-        read_phase_value_quad0 = read_phase_value_wa0;
-    }
-    else if ( quad0_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa1;
-        read_phase_value_quad0 = read_phase_value_wa1;
-    }
-    else if ( quad0_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
-        read_phase_value_quad0 = read_phase_value_wa2;
-    }
-
-    if ( quad1_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa0;
-        read_phase_value_quad1 = read_phase_value_wa0;
-    }
-    else if ( quad1_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa1;
-        read_phase_value_quad1 = read_phase_value_wa1;
-    }
-    else if ( quad1_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
-        read_phase_value_quad1 = read_phase_value_wa2;
-    }
-
-    if ( quad2_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa0;
-        read_phase_value_quad2 = read_phase_value_wa0;
-    }
-    else if ( quad2_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa1;
-        read_phase_value_quad2 = read_phase_value_wa1;
-    }
-    else if ( quad2_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
-        read_phase_value_quad2 = read_phase_value_wa2;
-    }
-
-    if ( quad3_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa0;
-        read_phase_value_quad3 = read_phase_value_wa0;
-    }
-    else if ( quad3_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa1;
-        read_phase_value_quad3 = read_phase_value_wa1;
-    }
-    else if ( quad3_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
-        read_phase_value_quad3 = read_phase_value_wa2;
-    }
-
-
-    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-    if (rc) return rc;
-
-    // Set Read Phase.
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2);
-
-    //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2)
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2);
-
-    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-    if (rc) return rc;
-
-    //Block 2
-    rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_2, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7);
-    rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_2, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7);
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    if ( quad0_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa0;
-        read_phase_value_quad0 = read_phase_value_wa0;
-    }
-    else if ( quad0_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa1;
-        read_phase_value_quad0 = read_phase_value_wa1;
-    }
-    else if ( quad0_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
-        read_phase_value_quad0 = read_phase_value_wa2;
-    }
-
-    if ( quad1_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa0;
-        read_phase_value_quad1 = read_phase_value_wa0;
-    }
-    else if ( quad1_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa1;
-        read_phase_value_quad1 = read_phase_value_wa1;
-    }
-    else if ( quad1_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
-        read_phase_value_quad1 = read_phase_value_wa2;
-    }
-
-    if ( quad2_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa0;
-        read_phase_value_quad2 = read_phase_value_wa0;
-    }
-    else if ( quad2_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa1;
-        read_phase_value_quad2 = read_phase_value_wa1;
-    }
-    else if ( quad2_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
-        read_phase_value_quad2 = read_phase_value_wa2;
-    }
-
-    if ( quad3_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa0;
-        read_phase_value_quad3 = read_phase_value_wa0;
-    }
-    else if ( quad3_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa1;
-        read_phase_value_quad3 = read_phase_value_wa1;
-    }
-    else if ( quad3_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
-        read_phase_value_quad3 = read_phase_value_wa2;
-    }
-
-
-    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-    if (rc) return rc;
-
-    // Set Read Phase.
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2);
-
-    //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2)
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2);
-
-    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-    if (rc) return rc;
-
-    //Block 3
-    rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_3, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7);
-    rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_3, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7);
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    if ( quad0_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa0;
-        read_phase_value_quad0 = read_phase_value_wa0;
-    }
-    else if ( quad0_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa1;
-        read_phase_value_quad0 = read_phase_value_wa1;
-    }
-    else if ( quad0_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
-        read_phase_value_quad0 = read_phase_value_wa2;
-    }
-
-    if ( quad1_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa0;
-        read_phase_value_quad1 = read_phase_value_wa0;
-    }
-    else if ( quad1_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa1;
-        read_phase_value_quad1 = read_phase_value_wa1;
-    }
-    else if ( quad1_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
-        read_phase_value_quad1 = read_phase_value_wa2;
-    }
-
-    if ( quad2_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa0;
-        read_phase_value_quad2 = read_phase_value_wa0;
-    }
-    else if ( quad2_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa1;
-        read_phase_value_quad2 = read_phase_value_wa1;
-    }
-    else if ( quad2_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
-        read_phase_value_quad2 = read_phase_value_wa2;
-    }
-
-    if ( quad3_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa0;
-        read_phase_value_quad3 = read_phase_value_wa0;
-    }
-    else if ( quad3_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa1;
-        read_phase_value_quad3 = read_phase_value_wa1;
-    }
-    else if ( quad3_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
-        read_phase_value_quad3 = read_phase_value_wa2;
-    }
-
-
-    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-    if (rc) return rc;
-
-    // Set Read Phase.
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2);
-
-    //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2)
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2);
-
-    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-    if (rc) return rc;
-
-    //Block 4
-    rc = fapiGetScom(i_target, RD_TIMING_REF0_ADDR_4, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad0, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad1, 57, 7);
-    rc = fapiGetScom(i_target, RD_TIMING_REF1_ADDR_4, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad2, 49, 7);
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_timing_ref_quad3, 57, 7);
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    if ( quad0_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa0;
-        read_phase_value_quad0 = read_phase_value_wa0;
-    }
-    else if ( quad0_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa1;
-        read_phase_value_quad0 = read_phase_value_wa1;
-    }
-    else if ( quad0_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad0 = dqs_clk_increment_wa2;
-        read_phase_value_quad0 = read_phase_value_wa2;
-    }
-
-    if ( quad1_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa0;
-        read_phase_value_quad1 = read_phase_value_wa0;
-    }
-    else if ( quad1_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa1;
-        read_phase_value_quad1 = read_phase_value_wa1;
-    }
-    else if ( quad1_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad1 = dqs_clk_increment_wa2;
-        read_phase_value_quad1 = read_phase_value_wa2;
-    }
-
-    if ( quad2_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa0;
-        read_phase_value_quad2 = read_phase_value_wa0;
-    }
-    else if ( quad2_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa1;
-        read_phase_value_quad2 = read_phase_value_wa1;
-    }
-    else if ( quad2_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad2 = dqs_clk_increment_wa2;
-        read_phase_value_quad2 = read_phase_value_wa2;
-    }
-
-    if ( quad3_workaround_type == 0 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa0;
-        read_phase_value_quad3 = read_phase_value_wa0;
-    }
-    else if ( quad3_workaround_type == 1 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa1;
-        read_phase_value_quad3 = read_phase_value_wa1;
-    }
-    else if ( quad3_workaround_type == 2 )
-    {
-        dqs_clk_increment_quad3 = dqs_clk_increment_wa2;
-        read_phase_value_quad3 = read_phase_value_wa2;
-    }
-
-
-    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-    if (rc) return rc;
-
-    // Set Read Phase.
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad0, 50, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad1, 54, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad2, 58, 2);
-    rc_num = rc_num | data_buffer_64.insertFromRight(read_phase_value_quad3, 62, 2);
-
-    //Increment dqs clk. 4 is the limit, wrap around (IE 5 = 1, 6 = 2)
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 48, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad0) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 48, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 52, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad1) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 52, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 56, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad2) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 56, 2);
-    l_value_u8 = 0;
-    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_u8, 60, 2);
-    l_new_value_u8 = (l_value_u8 + dqs_clk_increment_quad3) % 4;
-    rc_num = rc_num | data_buffer_64.insertFromRight(&l_new_value_u8, 60, 2);
-
-    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-    if (rc) return rc;
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    return rc;
-}
-
-ReturnCode mss_read_center_second_workaround(
-            Target& i_target
-            )
-{
-    //MBA target level
-    //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte
-    //Across all byte lanes
-
-    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
-    ecmdDataBufferBase data_buffer_64(64);
-    uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0;
-    uint64_t GATE_DELAY_ADDR_0 = 0;
-    uint64_t GATE_DELAY_ADDR_1 = 0;
-    uint64_t GATE_DELAY_ADDR_2 = 0;
-    uint64_t GATE_DELAY_ADDR_3 = 0;
-    uint64_t GATE_DELAY_ADDR_4 = 0;
-    uint8_t port = 0;
-    uint8_t rank_group = 0;
-    uint8_t l_value_n0_u8 = 0;
-    uint8_t l_value_n1_u8 = 0;
-    //uint8_t l_lowest_value_u8 = 0;
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-
-    uint32_t block;
-    uint32_t maxblocks = 5;
-    uint32_t byte;
-    uint32_t maxbytes = 2;
-    uint32_t nibble;
-    uint32_t maxnibbles = 2;
-
-    uint8_t l_lowest_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
-    uint8_t l_gate_delay_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
-
-
-    //populate primary_ranks_arrays_array
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
-    if(rc) return rc;
-
-
-    for(port = 0; port < MAX_PORTS; port++)
-    {
-
-
-        //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on  %s  PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
-
-        //Gather all the byte information
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-             //Initialize values
-             for(block = 0; block < maxblocks; block++)
-             {
-                for (byte = 0; byte < maxbytes; byte++)
-                {
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-                                l_lowest_value_u8[rank_group][block][byte][nibble] = 255;
-                                l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255;
-                        }
-                }
-             }
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-                FAPI_INF( "DQS_CLK Byte matching Workaround being applied on  %s  PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
-                if ( port == 0 )
-                {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-
-                        }
-                    }
-
-
-                    // PHY BLOCK 0
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 1
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 2
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 3
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 4
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal to the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-                }
-        }
-
-        //Finding the lowest Value
-        for(block = 0; block < maxblocks; block++)
-        {
-                for (byte = 0; byte < maxbytes; byte++)
-                {
-
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-
-                            if ( (l_lowest_value_u8[0][block][byte][nibble] == 0) ||
-                                 (l_lowest_value_u8[1][block][byte][nibble] == 0) ||
-                                 (l_lowest_value_u8[2][block][byte][nibble] == 0) ||
-                                 (l_lowest_value_u8[3][block][byte][nibble] == 0) )
-                            {
-                                    if ( (l_lowest_value_u8[0][block][byte][nibble] == 3) ||
-                                         (l_lowest_value_u8[1][block][byte][nibble] == 3) ||
-                                         (l_lowest_value_u8[2][block][byte][nibble] == 3) ||
-                                         (l_lowest_value_u8[3][block][byte][nibble] == 3) )
-                                    {
-
-                                        //In this case alone we make all gate values equal the gate of the lowest DQSCLK
-                                        if (l_lowest_value_u8[0][block][byte][nibble] == 3)
-                                        {
-                                                l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble];
-                                                l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble];
-                                                l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[0][block][byte][nibble];
-                                        }
-                                        else if (l_lowest_value_u8[1][block][byte][nibble] == 3)
-                                        {
-                                                l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble];
-                                                l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble];
-                                                l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[1][block][byte][nibble];
-                                        }
-                                        else if (l_lowest_value_u8[2][block][byte][nibble] == 3)
-                                        {
-                                                l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble];
-                                                l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble];
-                                                l_gate_delay_value_u8[3][block][byte][nibble] = l_gate_delay_value_u8[2][block][byte][nibble];
-                                        }
-                                        else if (l_lowest_value_u8[3][block][byte][nibble] == 3)
-                                        {
-                                                l_gate_delay_value_u8[0][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble];
-                                                l_gate_delay_value_u8[1][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble];
-                                                l_gate_delay_value_u8[2][block][byte][nibble] = l_gate_delay_value_u8[3][block][byte][nibble];
-                                        }
-
-                                        l_lowest_value_u8[0][block][byte][nibble] = 3;
-                                        l_lowest_value_u8[1][block][byte][nibble] = 3;
-                                        l_lowest_value_u8[2][block][byte][nibble] = 3;
-                                        l_lowest_value_u8[3][block][byte][nibble] = 3;
-                                    }
-                                    else
-                                    {
-                                        l_lowest_value_u8[0][block][byte][nibble] = 0;
-                                        l_lowest_value_u8[1][block][byte][nibble] = 0;
-                                        l_lowest_value_u8[2][block][byte][nibble] = 0;
-                                        l_lowest_value_u8[3][block][byte][nibble] = 0;
-
-                                    }
-                            }
-                            else if ( (l_lowest_value_u8[0][block][byte][nibble] == 2) ||
-                                    (l_lowest_value_u8[1][block][byte][nibble] == 2) ||
-                                    (l_lowest_value_u8[2][block][byte][nibble] == 2) ||
-                                    (l_lowest_value_u8[3][block][byte][nibble] == 2) )
-                            {
-                                    if ( (l_lowest_value_u8[0][block][byte][nibble] == 1) ||
-                                         (l_lowest_value_u8[1][block][byte][nibble] == 1) ||
-                                         (l_lowest_value_u8[2][block][byte][nibble] == 1) ||
-                                         (l_lowest_value_u8[3][block][byte][nibble] == 1) )
-                                    {
-                                        l_lowest_value_u8[0][block][byte][nibble] = 1;
-                                        l_lowest_value_u8[1][block][byte][nibble] = 1;
-                                        l_lowest_value_u8[2][block][byte][nibble] = 1;
-                                        l_lowest_value_u8[3][block][byte][nibble] = 1;
-
-                                    }
-                                    else
-                                    {
-                                        l_lowest_value_u8[0][block][byte][nibble] = 2;
-                                        l_lowest_value_u8[1][block][byte][nibble] = 2;
-                                        l_lowest_value_u8[2][block][byte][nibble] = 2;
-                                        l_lowest_value_u8[3][block][byte][nibble] = 2;
-
-                                    }
-                            }
-
-                        }
-                }
-
-        }
-
-
-        //Scoming in the New Values
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-
-                if ( port == 0 )
-                {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-
-                        }
-                    }
-
-                    //BLOCK 0
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 60, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-
-                    //BLOCK 1
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 60, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-
-                    //BLOCK 2
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 60, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-
-                    //BLOCK 3
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 60, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-
-                    //Block 4
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 60, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3);
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-                }
-        }
-    }
-
-    return rc;
-}
-
-
-ReturnCode mss_disable_workaround(
-            Target& i_target
-            )
-{
-    //MBA target level
-    //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte
-    //Across all byte lanes
-
-    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
-    ecmdDataBufferBase data_buffer_64(64);
-    uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0;
-    uint64_t DISABLE_ADDR_0 = 0;
-    uint64_t DISABLE_ADDR_1 = 0;
-    uint64_t DISABLE_ADDR_2 = 0;
-    uint64_t DISABLE_ADDR_3 = 0;
-    uint64_t DISABLE_ADDR_4 = 0;
-    uint64_t GATE_DELAY_ADDR_0 = 0;
-    uint64_t GATE_DELAY_ADDR_1 = 0;
-    uint64_t GATE_DELAY_ADDR_2 = 0;
-    uint64_t GATE_DELAY_ADDR_3 = 0;
-    uint64_t GATE_DELAY_ADDR_4 = 0;
-    uint8_t port = 0;
-    uint8_t rank_group = 0;
-    uint8_t l_value_n0_u8 = 0;
-    uint8_t l_value_n1_u8 = 0;
-    //uint8_t l_lowest_value_u8 = 0;
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-
-    uint32_t block;
-    uint32_t maxblocks = 5;
-    uint32_t byte;
-    uint32_t maxbytes = 2;
-    uint32_t nibble;
-    uint32_t maxnibbles = 2;
-    uint8_t l_min_gate_delay = 255;
-    uint8_t l_min_dqs_clk = 255;
-
-    uint8_t l_lowest_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
-    uint8_t l_gate_delay_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
-    uint8_t l_disable_value_u8[4][5][2][2];
-
-
-    //populate primary_ranks_arrays_array
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
-    if(rc) return rc;
-
-
-    for(port = 0; port < MAX_PORTS; port++)
-    {
-
-
-        //FAPI_INF( "DQS_CLK Byte matching Workaround being applied on  %s  PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
-
-        //Gather all the byte information
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-             //Initialize values
-             for(block = 0; block < maxblocks; block++)
-             {
-                for (byte = 0; byte < maxbytes; byte++)
-                {
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-                                l_lowest_value_u8[rank_group][block][byte][nibble] = 255;
-                                l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255;
-                                l_disable_value_u8[rank_group][block][byte][nibble] = 0;
-                        }
-                }
-             }
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-                FAPI_INF( "DISABLE Workaround being applied on  %s  PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
-                if ( port == 0 )
-                {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F;
-
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F;
-
-                        }
-                    }
-
-
-                    // PHY BLOCK 0
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_lowest_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_lowest_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 1
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_lowest_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_lowest_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 2
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_lowest_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_lowest_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 3
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_lowest_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_lowest_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 4
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_lowest_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_lowest_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_lowest_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-                }
-        }
-
-
-
-
-        //Finding the lowest Values on disabled bytes, then resetting mask.
-        for(block = 0; block < maxblocks; block++)
-        {
-                for (byte = 0; byte < maxbytes; byte++)
-                {
-
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-                                if ( (l_disable_value_u8[0][block][byte][nibble] != 0) || (l_disable_value_u8[1][block][byte][nibble] != 0)
-                                  || (l_disable_value_u8[2][block][byte][nibble] != 0) || (l_disable_value_u8[3][block][byte][nibble] != 0) )
-                                {
-
-                                        FAPI_INF( "Located disabled block %d byte %d nibble %d", block, byte, nibble);
-
-                                        l_min_gate_delay = 255;
-                                        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-                                        {
-                                                if ( (l_gate_delay_value_u8[rank_group][block][byte][nibble] < l_min_gate_delay)
-                                                  && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) )
-                                                {
-                                                        l_min_gate_delay = l_gate_delay_value_u8[rank_group][block][byte][nibble];
-                                                }
-                                        }
-
-                                        FAPI_INF( "Lowest gate_delay %d", l_min_gate_delay);
-
-                                        l_min_dqs_clk = 255;
-                                        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-                                        {
-                                                if ( (l_lowest_value_u8[rank_group][block][byte][nibble] < l_min_dqs_clk)
-                                                  && (l_disable_value_u8[rank_group][block][byte][nibble] == 0) )
-                                                {
-                                                        l_min_dqs_clk = l_lowest_value_u8[rank_group][block][byte][nibble];
-                                                }
-                                        }
-
-
-                                        FAPI_INF( "Lowest rdclk phase %d", l_min_dqs_clk);
-
-                                        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-                                        {
-                                                if (l_disable_value_u8[rank_group][block][byte][nibble] != 0)
-                                                {
-                                                        l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_min_gate_delay;
-                                                        l_lowest_value_u8[rank_group][block][byte][nibble] = l_min_dqs_clk;
-                                                        //l_disable_value_u8[rank_group][block][byte][nibble] = 0;
-                                                }
-                                        }
-
-                                }
-                        }
-                }
-
-        }
-
-
-        //Scoming in the New Values
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-
-                if ( port == 0 )
-                {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F;
-
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F;
-
-                        }
-                    }
-
-                    //BLOCK 0
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][0][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-
-                    //BLOCK 1
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][1][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-
-                    //BLOCK 2
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][2][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-
-                    //BLOCK 3
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][3][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-
-                    //Block 4
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_lowest_value_u8[rank_group][4][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-
-                }
-        }
-    }
-
-    return rc;
-}
-
-ReturnCode mss_wr_lvl_disable_workaround(
-            Target& i_target
-            )
-{
-    //MBA target level
-    //DQS_CLK for each nibble of a byte is being adjusted to the lowest value for the given byte
-    //Across all byte lanes
-
-    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
-    ecmdDataBufferBase data_buffer_64(64);
-    uint64_t DISABLE_ADDR_0 = 0;
-    uint64_t DISABLE_ADDR_1 = 0;
-    uint64_t DISABLE_ADDR_2 = 0;
-    uint64_t DISABLE_ADDR_3 = 0;
-    uint64_t DISABLE_ADDR_4 = 0;
-
-    uint64_t DQSCLK_RD_PHASE_ADDR_0 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_1 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_2 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_3 = 0;
-    uint64_t DQSCLK_RD_PHASE_ADDR_4 = 0;
-    uint64_t GATE_DELAY_ADDR_0 = 0;
-    uint64_t GATE_DELAY_ADDR_1 = 0;
-    uint64_t GATE_DELAY_ADDR_2 = 0;
-    uint64_t GATE_DELAY_ADDR_3 = 0;
-    uint64_t  GATE_DELAY_ADDR_4 = 0;
-    uint8_t port = 0;
-    uint8_t rank_group = 0;
-    uint8_t l_value_n0_u8 = 0;
-    uint8_t l_value_n1_u8 = 0;
-
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-
-    uint8_t block;
-    uint32_t maxblocks = 5;
-    uint32_t byte;
-    uint32_t maxbytes = 2;
-    uint32_t nibble;
-    uint32_t maxnibbles = 2;
-
-
-    uint8_t l_dqsclk_phase_value_u8[4][5][2][2]; // l_lowest_value_u8[group][block][byte_of_reg][nibble_of_byte]
-    uint8_t l_disable_value_u8[4][5][2][2];
-    uint8_t l_disable_old_value_u8[4][5][2][2];
-    uint8_t l_gate_delay_value_u8[4][5][2][2];
-    uint8_t l_rdclk_phase_value_u8[4][5][2][2];
-
-
-
-    //populate primary_ranks_arrays_array
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
-    if(rc) return rc;
-
-    FAPI_DBG("WR LVL DISABLE WORKAROUND: Entered WR_LVL workaround");
-
-    for(port = 0; port < MAX_PORTS; port++)
-    {
-        //Gather all the byte information
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-             //Initialize values
-             for(block = 0; block < maxblocks; block++)
-             {
-                for (byte = 0; byte < maxbytes; byte++)
-                {
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-                                l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = 255;
-                                l_gate_delay_value_u8[rank_group][block][byte][nibble] = 255;
-                                l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = 255;
-                                l_disable_value_u8[rank_group][block][byte][nibble] = 0;
-                                l_disable_old_value_u8[rank_group][block][byte][nibble] = 0;
-
-                        }
-                }
-             }
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-                FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLE Workaround being applied on  %s  PORT: %d RP: %d", i_target.toEcmdString(), port, rank_group);
-
-                if ( port == 0 )
-                {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F;
-
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F;
-
-                        }
-                    }
-
-
-                    // PHY BLOCK 0
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_dqsclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_dqsclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_rdclk_phase_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_rdclk_phase_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][0][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][0][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][0][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][0][1][1] = l_value_n1_u8;
-
-
-                    // PHY BLOCK 1
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_dqsclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_dqsclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_rdclk_phase_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_rdclk_phase_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][1][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][1][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][1][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][1][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 2
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_dqsclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_dqsclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_rdclk_phase_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_rdclk_phase_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][2][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][2][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][2][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][2][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 3
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_dqsclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_dqsclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_rdclk_phase_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_rdclk_phase_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][3][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][3][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][3][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][3][1][1] = l_value_n1_u8;
-
-                    // PHY BLOCK 4
-
-                    rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 4);
-                    l_disable_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 4);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 4);
-                    l_disable_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_disable_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-                    l_disable_old_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_disable_old_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 48, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 52, 2);
-                    l_dqsclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 56, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 60, 2);
-                    l_dqsclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_dqsclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 50, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 54, 2);
-                    l_rdclk_phase_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 58, 2);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 62, 2);
-                    l_rdclk_phase_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_rdclk_phase_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    // Grabbing 2 nibbles of the same byte and making them equal the same lowest value
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 49, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 53, 3);
-                    l_gate_delay_value_u8[rank_group][4][0][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][4][0][1] = l_value_n1_u8;
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n0_u8, 57, 3);
-                    rc_num = rc_num | data_buffer_64.extractToRight(&l_value_n1_u8, 61, 3);
-                    l_gate_delay_value_u8[rank_group][4][1][0] = l_value_n0_u8;
-                    l_gate_delay_value_u8[rank_group][4][1][1] = l_value_n1_u8;
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-                }
-        }
-
-        uint8_t ranks_array[4][4][2]; //[group][rank_group position][port]
-        // Determine rank and rank group matching
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, ranks_array[0][0]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, ranks_array[1][0]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, ranks_array[2][0]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, ranks_array[3][0]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target, ranks_array[0][1]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target, ranks_array[1][1]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target, ranks_array[2][1]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target, ranks_array[3][1]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target, ranks_array[0][2]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target, ranks_array[1][2]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target, ranks_array[2][2]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target, ranks_array[3][2]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target, ranks_array[0][3]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target, ranks_array[1][3]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target, ranks_array[2][3]); if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target, ranks_array[3][3]); if(rc) return rc;
-
-
-        access_type_t l_access_type_e = READ;
-        //READ
-        //WRITE
-        input_type_t l_input_type_e = WR_DQS;
-        //WR_DQ_t,
-        //RAW_WR_DQ,
-        //WR_DQS_t,
-        //RAW_WR_DQS,
-        uint8_t l_flag = 0;
-        uint8_t l_verbose = 0;
-        uint8_t l_rank_u8;
-        uint32_t l_old_delay_value_u32 = 0;
-        uint32_t l_old_DQS_delay_value_u32 = 0;
-        uint32_t l_delay_value_u32 = 0;
-        uint32_t l_DQS_delay_value_u32 = 0;
-        uint8_t l_index_u8 = 0;
-        uint8_t mask;
-        uint8_t nibble_dq;
-        uint8_t lane;
-        uint8_t rg;
-        uint8_t rank_2;
-        uint8_t width;
-        uint8_t dqs_index;
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, width);
-
-            uint32_t instruction_number = 0;
-            ecmdDataBufferBase address_buffer_16(16);
-            rc_num = rc_num | address_buffer_16.flushTo0();
-            ecmdDataBufferBase bank_buffer_8(8);
-            rc_num = rc_num | bank_buffer_8.flushTo0();
-            ecmdDataBufferBase activate_buffer_1(1);
-            rc_num = rc_num | activate_buffer_1.flushTo0();
-            ecmdDataBufferBase rasn_buffer_1(1);
-            ecmdDataBufferBase casn_buffer_1(1);
-            ecmdDataBufferBase wen_buffer_1(1);
-            ecmdDataBufferBase cke_buffer_8(8);
-            rc_num = rc_num | cke_buffer_8.flushTo1();
-            ecmdDataBufferBase csn_buffer_8(8);
-            rc_num = rc_num | csn_buffer_8.flushTo1();
-            ecmdDataBufferBase odt_buffer_8(8);
-            rc_num = rc_num | odt_buffer_8.flushTo0();
-            ecmdDataBufferBase test_buffer_4(4);
-            rc_num = rc_num | test_buffer_4.setBit(0,4);
-
-            ecmdDataBufferBase num_idles_buffer_16(16);
-            rc_num = rc_num | num_idles_buffer_16.flushTo1();
-            ecmdDataBufferBase num_repeat_buffer_16(16);
-            rc_num = rc_num | num_repeat_buffer_16.flushTo0();
-            ecmdDataBufferBase data_buffer_20(20);
-            rc_num = rc_num | data_buffer_20.flushTo0();
-            ecmdDataBufferBase read_compare_buffer_1(1);
-            rc_num = rc_num | read_compare_buffer_1.flushTo0();
-            ecmdDataBufferBase rank_cal_buffer_4(4);
-            rc_num = rc_num | rank_cal_buffer_4.flushTo0();
-            ecmdDataBufferBase ddr_cal_enable_buffer_1(1);
-            rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo1();
-            ecmdDataBufferBase ccs_end_buffer_1(1);
-            rc_num = rc_num | ccs_end_buffer_1.flushTo1();
-            uint8_t group = 255;
-            const uint32_t NUM_POLL = 10000;
-
-
-            uint8_t cur_cal_step = 2;
-            enum mss_draminit_training_result cur_error_status = MSS_INIT_CAL_PASS;
-            uint8_t mbaPosition;
-            // Get MBA position: 0 = mba01, 1 = mba23
-            rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, mbaPosition);
-            if(rc)
-            {
-                FAPI_ERR("Error getting MBA position");
-                return rc;
-            }
-
-
-
-        //Resetting Disable mask.  Avoid spares.
-        for(block = 0; block < maxblocks; block++)
-        {
-                for (byte = 0; byte < 2; byte++)
-                {
-
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-
-                                for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-                                {
-
-                                    //Check if rank group exists
-                                    if(primary_ranks_array[rank_group][port] != 255)
-                                    {
-
-
-                                        if ( port == 0 )
-                                        {
-
-                                                if ( rank_group == 0 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F;
-
-                                                }
-                                                else if ( rank_group == 1 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F;
-
-                                                }
-                                                else if ( rank_group == 2 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F;
-
-                                                }
-                                                else if ( rank_group == 3 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F;
-
-                                                }
-                                            }
-                                            else if (port == 1 )
-                                            {
-
-                                                if ( rank_group == 0 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F;
-
-                                                }
-                                                else if ( rank_group == 1 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F;
-
-
-                                                }
-                                                else if ( rank_group == 2 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F;
-
-
-                                                }
-                                                else if ( rank_group == 3 )
-                                                {
-
-                                                    DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F;
-                                                    DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F;
-                                                    DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F;
-                                                    DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F;
-                                                    DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F;
-
-                                                }
-                                            }
-
-                                        lane = byte * 8 + nibble*4;
-                                        l_input_type_e = WR_DQ;
-                                        l_flag = 1;
-                                        // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1)
-                                        // In this case moving from  lane/block to C4 DQ to determine spare
-                                        rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag);
-                                        if (rc) return rc;
-
-                                        dqs_index = l_index_u8 / 8;
-
-
-                                        if ( ((dqs_index % 9 == 0)&&(dqs_index/9 > 0)) && (l_disable_value_u8[rank_group][block][byte][nibble] != 0x0))
-                                        {
-                                                //This is a spare.  Unmark it in the old map for the rest of the workaround to not operate on a spare
-                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: Denoting Spare that is disabled for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]);
-                                                l_disable_old_value_u8[rank_group][block][byte][nibble] = 0x00;
-
-                                        }
-                                        else if (l_disable_value_u8[rank_group][block][byte][nibble] != 0x00)
-                                        {
-                                                //This is not a spare.  Unmark into what will be scommed back in; to be able to reset the disable mask.
-                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: Unmasking disable for block: %d byte: %d nibble: %d Previous Value: 0x%02X", block, byte, nibble, l_disable_value_u8[rank_group][block][byte][nibble]);
-                                                l_disable_value_u8[rank_group][block][byte][nibble] = 0x00;
-
-                                        }
-
-
-                                            //BLOCK 0
-                                            rc = fapiGetScom(i_target, DISABLE_ADDR_0, data_buffer_64);
-                                            if (rc) return rc;
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][0], 48, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][0][1], 52, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][0], 56, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][0][1][1], 60, 4);
-                                            rc = fapiPutScom(i_target, DISABLE_ADDR_0, data_buffer_64);
-                                            if (rc) return rc;
-
-                                            //BLOCK 1
-
-                                            rc = fapiGetScom(i_target, DISABLE_ADDR_1, data_buffer_64);
-                                            if (rc) return rc;
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][0], 48, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][0][1], 52, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][0], 56, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][1][1][1], 60, 4);
-                                            rc = fapiPutScom(i_target, DISABLE_ADDR_1, data_buffer_64);
-                                            if (rc) return rc;
-
-                                            //BLOCK 2
-
-                                            rc = fapiGetScom(i_target, DISABLE_ADDR_2, data_buffer_64);
-                                            if (rc) return rc;
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][0], 48, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][0][1], 52, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][0], 56, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][2][1][1], 60, 4);
-                                            rc = fapiPutScom(i_target, DISABLE_ADDR_2, data_buffer_64);
-                                            if (rc) return rc;
-
-
-                                            //BLOCK 3
-
-                                            rc = fapiGetScom(i_target, DISABLE_ADDR_3, data_buffer_64);
-                                            if (rc) return rc;
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][0], 48, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][0][1], 52, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][0], 56, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][3][1][1], 60, 4);
-                                            rc = fapiPutScom(i_target, DISABLE_ADDR_3, data_buffer_64);
-                                            if (rc) return rc;
-
-
-                                            //Block 4
-                                            rc = fapiGetScom(i_target, DISABLE_ADDR_4, data_buffer_64);
-                                            if (rc) return rc;
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][0], 48, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][0][1], 52, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][0], 56, 4);
-                                            rc_num = rc_num | data_buffer_64.insertFromRight(&l_disable_value_u8[rank_group][4][1][1], 60, 4);
-                                            rc = fapiPutScom(i_target, DISABLE_ADDR_4, data_buffer_64);
-                                            if (rc) return rc;
-
-
-                                    }
-                              }
-                        }
-                }
-        }
-
-
-        //Re-run DQS ALIGN for only rank_group/ports that had a disable.
-
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-                group = 255;
-                for(block = 0; block < maxblocks; block++)
-                {
-                        for (byte = 0; byte < maxbytes; byte++)
-                        {
-
-                                for (nibble = 0; nibble < maxnibbles; nibble++)
-                                {
-                                    //Check if rank group exists
-                                    if(primary_ranks_array[rank_group][port] != 255)
-                                    {
-                                        if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x0)
-                                        {
-                                                group = rank_group;
-                                        }
-                                    }
-
-                                }
-                        }
-                }
-                FAPI_DBG("WR LVL DISABLE WORKAROUND: DQS ALIGN LOOP on group: %d rank_group: %d port: %d", group, rank_group, port);
-                if (group != 255)
-                {
-
-                     FAPI_DBG("WR LVL DISABLE WORKAROUND: Re-Running DQS ALIGN on rank_group: %d port: %d", group, port);
-                    //Clearing any status or errors bits that may have occured in previous training subtest.
-                    if(port == 0)
-                    {
-                        //clear status reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P0_0x8000C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear error reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 11);
-                        rc_num = rc_num | data_buffer_64.clearBit(60, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P0_0x8000C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear other port
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48);
-                        rc_num = rc_num | data_buffer_64.clearBit(50);
-                        rc_num = rc_num | data_buffer_64.clearBit(51);
-                        rc_num = rc_num | data_buffer_64.clearBit(52);
-                        rc_num = rc_num | data_buffer_64.clearBit(53);
-                        rc_num = rc_num | data_buffer_64.clearBit(54);
-                        rc_num = rc_num | data_buffer_64.clearBit(55);
-                        rc_num = rc_num | data_buffer_64.clearBit(58);
-                        rc_num = rc_num | data_buffer_64.clearBit(60);
-                        rc_num = rc_num | data_buffer_64.clearBit(61);
-                        rc_num = rc_num | data_buffer_64.clearBit(62);
-                        rc_num = rc_num | data_buffer_64.clearBit(63);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //Setup the Config Reg bit for the only cal step we want
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                    }
-                    else
-                    {
-                        //clear status reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_STATUS_P1_0x8001C0190301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear error reg
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48, 11);
-                        rc_num = rc_num | data_buffer_64.clearBit(60, 4);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_ERROR_P1_0x8001C0180301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //clear other port
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-                        rc_num = rc_num | data_buffer_64.clearBit(48);
-                        rc_num = rc_num | data_buffer_64.clearBit(50);
-                        rc_num = rc_num | data_buffer_64.clearBit(51);
-                        rc_num = rc_num | data_buffer_64.clearBit(52);
-                        rc_num = rc_num | data_buffer_64.clearBit(53);
-                        rc_num = rc_num | data_buffer_64.clearBit(54);
-                        rc_num = rc_num | data_buffer_64.clearBit(55);
-                        rc_num = rc_num | data_buffer_64.clearBit(58);
-                        rc_num = rc_num | data_buffer_64.clearBit(60);
-                        rc_num = rc_num | data_buffer_64.clearBit(61);
-                        rc_num = rc_num | data_buffer_64.clearBit(62);
-                        rc_num = rc_num | data_buffer_64.clearBit(63);
-                        rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                        //Setup the Config Reg bit for the only cal step we want
-                        rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                        if(rc) return rc;
-
-                    }
-
-                    //Clear training cnfg
-                    rc_num = rc_num | data_buffer_64.clearBit(48);
-                    rc_num = rc_num | data_buffer_64.setBit(50);
-                    rc_num = rc_num | data_buffer_64.clearBit(51);
-                    rc_num = rc_num | data_buffer_64.clearBit(52);
-                    rc_num = rc_num | data_buffer_64.clearBit(53);
-                    rc_num = rc_num | data_buffer_64.clearBit(54);
-                    rc_num = rc_num | data_buffer_64.clearBit(55);
-                    rc_num = rc_num | data_buffer_64.clearBit(60);
-                    rc_num = rc_num | data_buffer_64.clearBit(61);
-                    rc_num = rc_num | data_buffer_64.clearBit(62);
-                    rc_num = rc_num | data_buffer_64.clearBit(63);
-
-                    if(group == 0){
-                        rc_num = rc_num | data_buffer_64.setBit(60);
-                    }
-                    else if(group == 1){
-                        rc_num = rc_num | data_buffer_64.setBit(61);
-                    }
-                    else if(group == 2){
-                        rc_num = rc_num | data_buffer_64.setBit(62);
-                    }
-                    else if(group == 3){
-                        rc_num = rc_num | data_buffer_64.setBit(63);
-                    }
-
-                        //Set the config register
-                        if(port == 0)
-                        {
-                            rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P0_0x8000C0160301143F, data_buffer_64);
-                            if(rc) return rc;
-                        }
-                        else
-                        {
-                            rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_INIT_CAL_CONFIG0_P1_0x8001C0160301143F, data_buffer_64);
-                            if(rc) return rc;
-                        }
-
-                        rc = mss_ccs_inst_arry_0(i_target,
-                                                 instruction_number,
-                                                 address_buffer_16,
-                                                 bank_buffer_8,
-                                                 activate_buffer_1,
-                                                 rasn_buffer_1,
-                                                 casn_buffer_1,
-                                                 wen_buffer_1,
-                                                 cke_buffer_8,
-                                                 csn_buffer_8,
-                                                 odt_buffer_8,
-                                                 test_buffer_4,
-                                                 port);
-
-                        if(rc) return rc;
-                        rc_num = rc_num | rank_cal_buffer_4.insert(primary_ranks_array[rank_group][port], 0, 4, 4); // 8 bit storage, need last 4 bits
-                        if(rc_num)
-                        {
-                                rc.setEcmdError(rc_num);
-                                return rc;
-                        }
-
-                        rc = mss_ccs_inst_arry_1(i_target,
-                                                 instruction_number,
-                                                 num_idles_buffer_16,
-                                                 num_repeat_buffer_16,
-                                                 data_buffer_20,
-                                                 read_compare_buffer_1,
-                                                 rank_cal_buffer_4,
-                                                 ddr_cal_enable_buffer_1,
-                                                 ccs_end_buffer_1);
-                        if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-                        rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
-                        if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-                        //Check to see if the training errored out
-                        rc = mss_check_error_status(i_target, mbaPosition, port, group, cur_cal_step, cur_error_status, 1);
-                        if(rc) return rc;
-
-                        if (cur_error_status == MSS_INIT_CAL_FAIL)
-                        {
-                                //RC/Log is generated in mss_check_error_status
-                                FAPI_ERR("Error returned on workaround Re-run of DQS_ALIGN on %s  PORT: %d RP: %d", i_target.toEcmdString(), port, group);
-                        }
-
-                }
-        }
-
-        uint8_t curr_bit;
-
-        //Finding the lowest Values on disabled bytes, then resetting mask.
-        for(block = 0; block < maxblocks; block++)
-        {
-                for (byte = 0; byte < maxbytes; byte++)
-                {
-
-                        for (nibble = 0; nibble < maxnibbles; nibble++)
-                        {
-
-                                for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-                                {
-                                        for (nibble_dq = 0; nibble_dq < 4; nibble_dq++)
-                                        {
-
-
-                                                if (l_disable_old_value_u8[rank_group][block][byte][nibble] != 0x00)
-                                                {
-
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: DISABLED block: %d byte: %d nibble: %d disable value: 0x%02X", block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]);
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]);
-                                                        //SWAPPING DQSCLK PHASE SELECT
-                                                        for (rg = 0; rg < MAX_PRI_RANKS; rg++)
-                                                        {
-                                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK possible replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]);
-
-                                                                if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_dqsclk_phase_value_u8[rg][block][byte][nibble] < l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]) )
-                                                                {
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble);
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: DQSCLK replacement value: %d", l_dqsclk_phase_value_u8[rg][block][byte][nibble]);
-                                                                        l_dqsclk_phase_value_u8[rank_group][block][byte][nibble] = l_dqsclk_phase_value_u8[rg][block][byte][nibble];
-                                                                }
-                                                        }
-
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]);
-                                                        //SWAPPING RDCLK PHASE SELECT
-                                                        for (rg = 0; rg < MAX_PRI_RANKS; rg++)
-                                                        {
-                                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK possible replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]);
-
-                                                                if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_rdclk_phase_value_u8[rg][block][byte][nibble] < l_rdclk_phase_value_u8[rank_group][block][byte][nibble]) )
-                                                                {
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement: block: %d byte: %d nibble: %d", block, byte, nibble);
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: RDCLK replacement value: %d", l_rdclk_phase_value_u8[rg][block][byte][nibble]);
-                                                                        l_rdclk_phase_value_u8[rank_group][block][byte][nibble] = l_rdclk_phase_value_u8[rg][block][byte][nibble];
-                                                                }
-                                                        }
-
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d current value: %d", block, byte, nibble, l_dqsclk_phase_value_u8[rank_group][block][byte][nibble]);
-                                                        //SWAPPING RDCLK PHASE SELECT
-                                                        for (rg = 0; rg < MAX_PRI_RANKS; rg++)
-                                                        {
-                                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY possible replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]);
-
-                                                                if ( (l_disable_old_value_u8[rg][block][byte][nibble] == 0) && (l_gate_delay_value_u8[rg][block][byte][nibble] < l_gate_delay_value_u8[rank_group][block][byte][nibble]) )
-                                                                {
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement: block: %d byte: %d nibble: %d", block, byte, nibble);
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: GATE DELAY replacement value: %d", l_gate_delay_value_u8[rg][block][byte][nibble]);
-                                                                        l_gate_delay_value_u8[rank_group][block][byte][nibble] = l_gate_delay_value_u8[rg][block][byte][nibble];
-                                                                }
-                                                        }
-
-                                                        //SWAPPING DQ AND DQS
-                                                        mask = 0x8 >> nibble_dq;
-                                                        curr_bit = l_disable_old_value_u8[rank_group][block][byte][nibble] & mask;
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP MASK: 0x%02X DISABLE BIT: 0x%02X CURR BIT: 0x%02X", mask, l_disable_old_value_u8[rank_group][block][byte][nibble] & mask, curr_bit);
-
-                                                        if (curr_bit)
-                                                        {
-
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: DQ/DQS SWAP RANK_GROUP: %d BLOCK: %d BYTE: %d NIBBLE: %d DISABLE VALUE: 0x%02X", rank_group, block, byte, nibble, l_disable_old_value_u8[rank_group][block][byte][nibble]);
-
-                                                        //Figure out which lane to investigate
-                                                        l_index_u8 = nibble_dq + 4 * nibble + 8 * byte;
-                                                        lane = l_index_u8;
-
-                                                        l_input_type_e = WR_DQ;
-                                                        l_flag = 1;
-                                                        // C4 DQ to lane/block (flag = 0) in PHY or lane/block to C4 DQ (flag = 1)
-                                                        // In this case moving from lane/block to C4 DQ to use access_delay_reg
-                                                        rc = mss_c4_phy(i_target, port, rank_group, l_input_type_e, l_index_u8, l_verbose, lane, block, l_flag);
-
-
-                                                        l_access_type_e = READ;
-                                                        l_rank_u8 = ranks_array[rank_group][0][0];
-                                                        if (l_rank_u8 == 255)
-                                                        continue;
-
-                                                        // Getting old DQ Value
-                                                        l_input_type_e = WR_DQ;
-                                                        rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_old_delay_value_u32);
-                                                        if(rc) return rc;
-
-
-                                                        if (width == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8)
-                                                        {
-                                                                dqs_index = l_index_u8 / 8;
-                                                        }
-                                                        else
-                                                        {
-                                                                dqs_index = l_index_u8 / 4;
-                                                        }
-
-                                                        // Getting old DQS Value
-                                                        l_input_type_e = WR_DQS;
-                                                        rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_old_DQS_delay_value_u32);
-                                                        if(rc) return rc;
-
-                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: Value being replaced C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X ", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_old_delay_value_u32, l_old_DQS_delay_value_u32);
-
-                                                        for (rg = 0; rg < MAX_PRI_RANKS; rg++)
-                                                        {
-                                                                l_access_type_e = READ;
-                                                                rank_2 = ranks_array[rg][0][0];
-                                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: RANK: %d DISABLE VALUE: 0x%02X MASKED: 0x%02X", rank_2, l_disable_old_value_u8[rg][block][byte][nibble], l_disable_old_value_u8[rg][block][byte][nibble] & mask);
-                                                                if ( (rank_2 != 255) && (l_disable_old_value_u8[rg][block][byte][nibble] == 0 ) )
-                                                                {
-                                                                        // Getting New DQ Value
-                                                                        l_input_type_e = WR_DQ;
-                                                                        rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32);
-                                                                        if(rc) return rc;
-
-                                                                        // Getting New DQS Value
-                                                                        l_input_type_e = WR_DQS;
-                                                                        rc = mss_access_delay_reg(i_target, l_access_type_e, port, rank_2, l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32);
-                                                                        if(rc) return rc;
-
-                                                                        FAPI_DBG("WR LVL DISABLE WORKAROUND: Possible Replacement Value C4: %d C4 DQS: %d Rank:%d DQ DELAY VALUE: 0x%03X DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, rank_2, l_delay_value_u32, l_DQS_delay_value_u32);
-
-                                                                        if ( l_delay_value_u32 < l_old_delay_value_u32)
-                                                                        {
-                                                                                l_old_delay_value_u32 = l_delay_value_u32;
-                                                                                // Writing DQ Value
-                                                                                l_access_type_e = WRITE;
-                                                                                l_rank_u8 = ranks_array[rank_group][0][0];
-                                                                                l_input_type_e = WR_DQ;
-                                                                                rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, l_index_u8, l_verbose, l_delay_value_u32);
-                                                                                if(rc) return rc;
-
-                                                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQ: Value C4: %d C4 DQS: %d Rank:%d DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_delay_value_u32);
-                                                                        }
-                                                                        if ( l_DQS_delay_value_u32 < l_old_DQS_delay_value_u32)
-                                                                        {
-                                                                                l_old_DQS_delay_value_u32 = l_DQS_delay_value_u32;
-                                                                                // Writing DQS Value
-                                                                                l_access_type_e = WRITE;
-                                                                                l_rank_u8 = ranks_array[rank_group][0][0];
-                                                                                l_input_type_e = WR_DQS;
-                                                                                rc = mss_access_delay_reg(i_target, l_access_type_e, port, ranks_array[rank_group][0][0], l_input_type_e, dqs_index, l_verbose, l_DQS_delay_value_u32);
-                                                                                if(rc) return rc;
-
-                                                                                FAPI_DBG("WR LVL DISABLE WORKAROUND: Replacing DQS: Value C4: %d C4 DQS: %d Rank:%d DQS DELAY VALUE: 0x%03X", l_index_u8, dqs_index, ranks_array[rank_group][0][0], l_DQS_delay_value_u32);
-                                                                        }
-
-                                                                 }
-
-                                                          }
-
-
-                                                          }
-                                                }
-                                        }
-
-                                }
-                        }
-
-                }
-        }
-
-
-        //Scoming in the New Values
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-
-
-                if ( port == 0 )
-                {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_0_0x800000090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_1_0x800004090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_2_0x800008090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_3_0x80000C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P0_4_0x800010090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F;
-
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_0_0x800001090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_1_0x800005090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_2_0x800009090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_3_0x80000D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P0_4_0x800011090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_0_0x800002090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_1_0x800006090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_2_0x80000A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_3_0x80000E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P0_4_0x800012090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_0_0x800003090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_1_0x800007090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_2_0x80000B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_3_0x80000F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P0_4_0x800013090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_0_0x800100090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_1_0x800104090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_2_0x800108090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_3_0x80010C090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR0_P1_4_0x800110090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_0_0x800101090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_1_0x800105090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_2_0x800109090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_3_0x80010D090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR1_P1_4_0x800111090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_0_0x800102090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_1_0x800106090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_2_0x80010A090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_3_0x80010E090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR2_P1_4_0x800112090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-                            DQSCLK_RD_PHASE_ADDR_0 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_0_0x800103090301143F;
-                            DQSCLK_RD_PHASE_ADDR_1 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_1_0x800107090301143F;
-                            DQSCLK_RD_PHASE_ADDR_2 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_2_0x80010B090301143F;
-                            DQSCLK_RD_PHASE_ADDR_3 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_3_0x80010F090301143F;
-                            DQSCLK_RD_PHASE_ADDR_4 = DPHY01_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR3_P1_4_0x800113090301143F;
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-                            DISABLE_ADDR_0 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F;
-                            DISABLE_ADDR_1 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F;
-                            DISABLE_ADDR_2 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F;
-                            DISABLE_ADDR_3 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F;
-                            DISABLE_ADDR_4 = DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F;
-
-                        }
-                    }
-
-                    //Block 0
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][0][1][1], 60, 2);
-
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][0][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][0][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-
-                    //Block 1
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][1][1][1], 60, 2);
-
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][1][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][1][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-
-                    //Block 2
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][2][1][1], 60, 2);
-
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][2][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][2][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-
-                    //Block 3
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][3][1][1], 60, 2);
-
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][3][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][3][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-
-
-                    //Block 4
-                    rc = fapiGetScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][0], 48, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][0][1], 52, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][0], 56, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_dqsclk_phase_value_u8[rank_group][4][1][1], 60, 2);
-
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][0], 50, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][0][1], 54, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][0], 58, 2);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_rdclk_phase_value_u8[rank_group][4][1][1], 62, 2);
-                    rc = fapiPutScom(i_target, DQSCLK_RD_PHASE_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-                    rc = fapiGetScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][0], 49, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][0][1], 53, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][0], 57, 3);
-                    rc_num = rc_num | data_buffer_64.insertFromRight(&l_gate_delay_value_u8[rank_group][4][1][1], 61, 3);
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-
-                }
-        }
-    }
-
-    return rc;
-}
-
-
-
-
-ReturnCode mss_reset_delay_values(
-            Target& i_target
-            )
-{
-    //MBA target level
-    //Reset Wr_level delays and Gate Delays
-    //Across all configed rank pairs, in order
-
-    uint8_t primary_ranks_array[4][2]; //primary_ranks_array[group][port]
-    ecmdDataBufferBase data_buffer_64(64);
-    uint64_t GATE_DELAY_ADDR_0 = 0;
-    uint64_t GATE_DELAY_ADDR_1 = 0;
-    uint64_t GATE_DELAY_ADDR_2 = 0;
-    uint64_t GATE_DELAY_ADDR_3 = 0;
-    uint64_t GATE_DELAY_ADDR_4 = 0;
-    uint8_t port = 0;
-    uint8_t rank_group = 0;
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-
-
-    //populate primary_ranks_arrays_array
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target, primary_ranks_array[0]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target, primary_ranks_array[1]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target, primary_ranks_array[2]);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target, primary_ranks_array[3]);
-    if(rc) return rc;
-
-    //Hit the reset button for wr_lvl values
-    //These won't reset until the next run of wr_lvl
-    rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P0_0x8000CC020301143F, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.insertFromRight((uint8_t) 0xFF, 63, 1);
-    rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P0_0x8000CC020301143F, data_buffer_64);
-    if (rc) return rc;
-
-    rc = fapiGetScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P1_0x8001CC020301143F, data_buffer_64);
-    if (rc) return rc;
-    rc_num = rc_num | data_buffer_64.insertFromRight((uint8_t) 0xFF, 63, 1);
-    rc = fapiPutScom(i_target, DPHY01_DDRPHY_WC_CONFIG2_P1_0x8001CC020301143F, data_buffer_64);
-    if (rc) return rc;
-
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    //Scoming in zeros into the Gate delay registers.
-    for(port = 0; port < MAX_PORTS; port++)
-    {
-
-        for(rank_group = 0; rank_group < MAX_PRI_RANKS; rank_group++)
-        {
-
-            //Check if rank group exists
-            if(primary_ranks_array[rank_group][port] != 255)
-            {
-
-                   if ( port == 0 )
-                   {
-
-                        if ( rank_group == 0 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_0_0x800000130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_1_0x800004130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_2_0x800008130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_3_0x80000C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P0_4_0x800010130301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_0_0x800001130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_1_0x800005130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_2_0x800009130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_3_0x80000D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P0_4_0x800011130301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_0_0x800002130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_1_0x800006130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_2_0x80000A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_3_0x80000E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P0_4_0x800012130301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_0_0x800003130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_1_0x800007130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_2_0x80000B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_3_0x80000F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P0_4_0x800013130301143F;
-
-                        }
-                    }
-                    else if (port == 1 )
-                    {
-
-                        if ( rank_group == 0 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_0_0x800100130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_1_0x800104130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_2_0x800108130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_3_0x80010C130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP0_P1_4_0x800110130301143F;
-
-                        }
-                        else if ( rank_group == 1 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_0_0x800101130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_1_0x800105130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_2_0x800109130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_3_0x80010D130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP1_P1_4_0x800111130301143F;
-
-                        }
-                        else if ( rank_group == 2 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_0_0x800102130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_1_0x800106130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_2_0x80010A130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_3_0x80010E130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP2_P1_4_0x800112130301143F;
-
-                        }
-                        else if ( rank_group == 3 )
-                        {
-
-                            GATE_DELAY_ADDR_0 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_0_0x800103130301143F;
-                            GATE_DELAY_ADDR_1 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_1_0x800107130301143F;
-                            GATE_DELAY_ADDR_2 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_2_0x80010B130301143F;
-                            GATE_DELAY_ADDR_3 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_3_0x80010F130301143F;
-                            GATE_DELAY_ADDR_4 = DPHY01_DDRPHY_DP18_GATE_DELAY_RP3_P1_4_0x800113130301143F;
-
-                        }
-                    }
-
-                    rc_num = rc_num | data_buffer_64.flushTo0();
-                    if(rc_num)
-                    {
-                        rc.setEcmdError(rc_num);
-                        return rc;
-                    }
-
-                    //BLOCK 0
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_0, data_buffer_64);
-                    if (rc) return rc;
-                    //BLOCK 1
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_1, data_buffer_64);
-                    if (rc) return rc;
-                    //BLOCK 2
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_2, data_buffer_64);
-                    if (rc) return rc;
-                    //BLOCK 3
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_3, data_buffer_64);
-                    if (rc) return rc;
-                    //BLOCK 4
-                    rc = fapiPutScom(i_target, GATE_DELAY_ADDR_4, data_buffer_64);
-                    if (rc) return rc;
-
-
-                }
-           }
-
-        }
-
-
-    return rc;
-}
-
-ReturnCode mss_rtt_nom_rtt_wr_swap(
-            Target& i_target,
-            uint8_t i_mbaPosition,
-            uint32_t i_port_number,
-            uint8_t i_rank,
-            uint32_t i_rank_pair_group,
-            uint32_t& io_ccs_inst_cnt,
-            uint8_t& io_dram_rtt_nom_original
-            )
-{
-    // Target MBA level
-    // This is a function written specifically for mss_draminit_training
-    // Meant for placing RTT_WR into RTT_NOM within MR1 before wr_lvl
-    // If the function argument dram_rtt_nom_original has a value of 0xFF it will put the original rtt_nom there
-    // and write rtt_wr to the rtt_nom value
-    // If the function argument dram_rtt_nom_original has any value besides 0xFF it will try to write that value to rtt_nom.
-
-
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.clearBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.clearBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.clearBit(0);
-    ecmdDataBufferBase cke_4(4);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.setBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    ecmdDataBufferBase mrs1_16(16);
-    ecmdDataBufferBase mrs2_16(16);
-
-    ecmdDataBufferBase data_buffer_64(64);
-
-    uint16_t MRS1 = 0;
-    uint16_t MRS2 = 0;
-    uint8_t dimm = 0;
-    uint8_t dimm_rank = 0;
-
-    // dimm 0, dimm_rank 0-3 = ranks 0-3; dimm 1, dimm_rank 0-3 = ranks 4-7
-    dimm = (i_rank) / 4;
-    dimm_rank = i_rank - 4*dimm;
-
-
-    uint8_t dimm_type;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-    uint8_t is_sim = 0;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-    if(rc) return rc;
-
-    uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-    if(rc) return rc;
-
-
-    // Raise CKE high with NOPS, waiting min Reset CKE exit time (tXPR) - 400 cycles
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-    io_ccs_inst_cnt ++;
-
-    rc_num = rc_num | csn_8.setBit(0,8);
-    if (i_rank == 0)
-    {
-        rc_num = rc_num | csn_8.clearBit(0);
-    }
-    else if (i_rank == 1)
-    {
-        rc_num = rc_num | csn_8.clearBit(1);
-    }
-    else if (i_rank == 2)
-    {
-        rc_num = rc_num | csn_8.clearBit(2);
-    }
-    else if (i_rank == 3)
-    {
-        rc_num = rc_num | csn_8.clearBit(3);
-    }
-    else if (i_rank == 4)
-    {
-        rc_num = rc_num | csn_8.clearBit(4);
-    }
-    else if (i_rank == 5)
-    {
-        rc_num = rc_num | csn_8.clearBit(5);
-    }
-    else if (i_rank == 6)
-    {
-        rc_num = rc_num | csn_8.clearBit(6);
-    }
-    else if (i_rank == 7)
-    {
-        rc_num = rc_num | csn_8.clearBit(7);
-    }
-
-    // MRS CMD to CMD spacing = 12 cycles
-    rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    FAPI_INF( "Editing RTT_NOM during wr_lvl for %s PORT: %d RP: %d", i_target.toEcmdString(), i_port_number, i_rank_pair_group);
-
-    //MRS1
-    // Get contents of MRS 1 Shadow Reg
-
-    if (i_port_number == 0){
-        if (i_rank_pair_group == 0)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P0_0x8000C01D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 1)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P0_0x8000C11D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 2)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P0_0x8000C21D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 3)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P0_0x8000C31D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-    }
-    else if (i_port_number == 1){
-        if (i_rank_pair_group == 0)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP0_P1_0x8001C01D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 1)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP1_P1_0x8001C11D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 2)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP2_P1_0x8001C21D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 3)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR1_PRI_RP3_P1_0x8001C31D0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-    }
-
-    rc_num = rc_num | data_buffer_64.reverse();
-    rc_num = rc_num | mrs1_16.insert(data_buffer_64, 0, 16, 0);
-    rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    FAPI_INF( "CURRENT MRS 1: 0x%04X", MRS1);
-
-    uint8_t dll_enable = 0x00; //DLL Enable
-    if (mrs1_16.isBitSet(0))
-    {
-        // DLL disabled
-        dll_enable = 0xFF;
-    }
-    else if (mrs1_16.isBitClear(0))
-    {
-        // DLL enabled
-        dll_enable = 0x00;
-    }
-
-    uint8_t out_drv_imp_cntl = 0x00;
-    if ( (mrs1_16.isBitClear(1)) && (mrs1_16.isBitClear(5)) )
-    {
-        // out_drv_imp_ctrl set to 40 (Rzq/6)
-        out_drv_imp_cntl = 0x00;
-    }
-    else if ( (mrs1_16.isBitSet(1)) && (mrs1_16.isBitClear(5)) )
-    {
-        // out_drv_imp_ctrl set to 34 (Rzq/7)
-        out_drv_imp_cntl = 0x80;
-    }
-
-    uint8_t dram_rtt_nom = 0x00;
-    if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitClear(9)) )
-    {
-        // RTT_NOM set to disabled
-        FAPI_INF( "DRAM_RTT_NOM orignally set to Disabled.");
-        dram_rtt_nom = 0x00;
-
-    }
-    else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) )
-    {
-        // RTT_NOM set to 20
-        FAPI_INF( "DRAM_RTT_NOM orignally set to 20 Ohm.");
-        dram_rtt_nom = 0x20;
-    }
-    else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitClear(6)) && (mrs1_16.isBitSet(9)) )
-    {
-        // RTT_NOM set to 30
-        FAPI_INF( "DRAM_RTT_NOM orignally set to 30 Ohm.");
-        dram_rtt_nom = 0xA0;
-    }
-    else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) )
-    {
-        // RTT_NOM set to 40
-        FAPI_INF( "DRAM_RTT_NOM orignally set to 40 Ohm.");
-        dram_rtt_nom = 0xC0;
-    }
-    else if ( (mrs1_16.isBitSet(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) )
-    {
-        // RTT_NOM set to 60
-        FAPI_INF( "DRAM_RTT_NOM orignally set to 60 Ohm.");
-        dram_rtt_nom = 0x80;
-    }
-    else if ( (mrs1_16.isBitClear(2)) && (mrs1_16.isBitSet(6)) && (mrs1_16.isBitClear(9)) )
-    {
-        // RTT_NOM set to 120
-        FAPI_INF( "DRAM_RTT_NOM orignally set to 120 Ohm.");
-        dram_rtt_nom = 0x40;
-    }
-
-    uint8_t dram_al = 0x00;
-    if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitClear(4)) )
-    {
-        //AL DISABLED
-        dram_al = 0x00;
-    }
-    else if ( (mrs1_16.isBitSet(3)) && (mrs1_16.isBitClear(4)) )
-    {
-        // AL = CL -1
-        dram_al = 0x80;
-    }
-    else if ( (mrs1_16.isBitClear(3)) && (mrs1_16.isBitSet(4)) )
-    {
-        // AL = CL -2
-        dram_al = 0x40;
-    }
-
-    uint8_t wr_lvl = 0x00; //write leveling enable
-    if (mrs1_16.isBitClear(7))
-    {
-        // WR_LVL DISABLED
-        wr_lvl = 0x00;
-    }
-    else if (mrs1_16.isBitSet(7))
-    {
-        // WR_LVL ENABLED
-        wr_lvl = 0xFF;
-    }
-
-    uint8_t tdqs_enable = 0x00; //TDQS Enable
-    if (mrs1_16.isBitClear(11))
-    {
-        //TDQS DISABLED
-        tdqs_enable = 0x00;
-    }
-    else if (mrs1_16.isBitSet(11))
-    {
-        //TDQS ENABLED
-        tdqs_enable = 0xFF;
-    }
-
-    uint8_t q_off = 0x00; //Qoff - Output buffer Enable
-    if (mrs1_16.isBitSet(12))
-    {
-        //Output Buffer Disabled
-        q_off = 0xFF;
-    }
-    else if (mrs1_16.isBitClear(12))
-    {
-        //Output Buffer Enabled
-        q_off = 0x00;
-    }
-
-
-    // Get contents of MRS 2 Shadow Reg
-    if (i_port_number == 0){
-        if (i_rank_pair_group == 0)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P0_0x8000C01E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 1)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P0_0x8000C11E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 2)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P0_0x8000C21E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 3)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P0_0x8000C31E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-    }
-    else if (i_port_number == 1){
-        if (i_rank_pair_group == 0)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP0_P1_0x8001C01E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 1)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP1_P1_0x8001C11E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 2)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP2_P1_0x8001C21E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-        else if (i_rank_pair_group == 3)
-        {
-                rc = fapiGetScom(i_target, DPHY01_DDRPHY_PC_MR2_PRI_RP3_P1_0x8001C31E0301143F, data_buffer_64);
-                if(rc) return rc;
-        }
-    }
-
-    rc_num = rc_num | data_buffer_64.reverse();
-    rc_num = rc_num | mrs2_16.insert(data_buffer_64, 0, 16, 0);
-    rc_num = rc_num | mrs2_16.extractPreserve(&MRS2, 0, 16, 0);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-    FAPI_INF( "MRS 2: 0x%04X", MRS2);
-
-    uint8_t dram_rtt_wr = 0x00;
-    if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitClear(10)) )
-    {
-        //RTT WR DISABLE
-        FAPI_INF( "DRAM_RTT_WR currently set to Disable.");
-        dram_rtt_wr = 0x00;
-
-        //RTT NOM CODE FOR THIS VALUE IS
-        // dram_rtt_nom = 0x00
-
-    }
-    else if ( (mrs2_16.isBitSet(9)) && (mrs2_16.isBitClear(10)) )
-    {
-        //RTT WR 60 OHM
-        FAPI_INF( "DRAM_RTT_WR currently set to 60 Ohm.");
-        dram_rtt_wr = 0x80;
-
-        //RTT NOM CODE FOR THIS VALUE IS
-        // dram_rtt_nom = 0x80
-
-    }
-    else if ( (mrs2_16.isBitClear(9)) && (mrs2_16.isBitSet(10)) )
-    {
-        //RTT WR 120 OHM
-        FAPI_INF( "DRAM_RTT_WR currently set to 120 Ohm.");
-        dram_rtt_wr = 0x40;
-
-        //RTT NOM CODE FOR THIS VALUE IS
-        // dram_rtt_nom = 0x40
-
-    }
-
-
-    // If you have a 0 value in dram_rtt_nom_orignal
-    // you will use dram_rtt_nom_original to save the original value
-    if (io_dram_rtt_nom_original  == 0xFF)
-    {
-        io_dram_rtt_nom_original = dram_rtt_nom;
-        dram_rtt_nom = dram_rtt_wr;
-
-        if (dram_rtt_wr == 0x00)
-        {
-            FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is Disable.");
-        }
-        else if (dram_rtt_wr == 0x80)
-        {
-            FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 60 Ohm.");
-        }
-        else if (dram_rtt_wr == 0x40)
-        {
-            FAPI_INF( "DRAM_RTT_NOM to be set to DRAM_RTT_WR which is 120 Ohm.");
-        }
-    }
-    else if (io_dram_rtt_nom_original != 0xFF)
-    {
-        dram_rtt_nom = io_dram_rtt_nom_original;
-
-        if ( dram_rtt_nom == 0x00 )
-        {
-            // RTT_NOM set to disabled
-            FAPI_INF( "DRAM_RTT_NOM being set back to Disabled.");
-
-        }
-        else if ( dram_rtt_nom == 0x20 )
-        {
-            // RTT_NOM set to 20
-            FAPI_INF( "DRAM_RTT_NOM being set back to 20 Ohm.");
-        }
-        else if ( dram_rtt_nom == 0xA0 )
-        {
-            // RTT_NOM set to 30
-            FAPI_INF( "DRAM_RTT_NOM being set back to 30 Ohm.");
-        }
-        else if ( dram_rtt_nom == 0xC0 )
-        {
-            // RTT_NOM set to 40
-            FAPI_INF( "DRAM_RTT_NOM being set back to 40 Ohm.");
-        }
-        else if ( dram_rtt_nom == 0x80 )
-        {
-            // RTT_NOM set to 60
-            FAPI_INF( "DRAM_RTT_NOM being set back to 60 Ohm.");
-        }
-        else if ( dram_rtt_nom == 0x40 )
-        {
-            // RTT_NOM set to 120
-            FAPI_INF( "DRAM_RTT_NOM being set back to 120 Ohm.");
-        }
-        else
-        {
-            FAPI_INF( "Proposed DRAM_RTT_NOM value is a non-supported.  Using Disabled.");
-            dram_rtt_nom = 0x00;
-        }
-    }
-
-
-    rc_num = rc_num | mrs1_16.insert((uint8_t) dll_enable, 0, 1, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 1, 1, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 2, 1, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_al, 3, 2, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) out_drv_imp_cntl, 5, 1, 1);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 6, 1, 1);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) wr_lvl, 7, 1, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 8, 1);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) dram_rtt_nom, 9, 1, 2);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 10, 1);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) tdqs_enable, 11, 1, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) q_off, 12, 1, 0);
-    rc_num = rc_num | mrs1_16.insert((uint8_t) 0x00, 13, 3);
-
-    rc_num = rc_num | mrs1_16.extractPreserve(&MRS1, 0, 16, 0);
-    FAPI_INF( "NEW MRS 1: 0x%04X", MRS1);
-
-    // Copying the current MRS into address buffer matching the MRS_array order
-    // Setting the bank address
-
-    rc_num = rc_num | address_16.insert(mrs1_16, 0, 16, 0);
-    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-    rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
-
-
-
-    if ( ( address_mirror_map[i_port_number][dimm] & (0x08 >> dimm_rank) ) && (is_sim == 0))
-    {
-        //dimm and rank are only for print trace only, functionally not needed
-        rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm, dimm_rank, address_16, bank_3);
-        if(rc) return rc;
-
-    }
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    ccs_end_1.setBit(0);
-
-    // Send out to the CCS array
-    rc = mss_ccs_inst_arry_0( i_target,
-                              io_ccs_inst_cnt,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              i_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              io_ccs_inst_cnt,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-
-    uint32_t NUM_POLL = 100;
-    rc = mss_execute_ccs_inst_array( i_target, NUM_POLL, 60);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-    io_ccs_inst_cnt = 0;
-
-    return rc;
-
-}
-
-
-
-fapi::ReturnCode mss_set_bbm_regs (const fapi::Target & mba_target)
-{
-    // Flash to registers.
-        // disable0=dq bits, disable1=dqs(+,-)
-        // wrclk_en=dqs follows quad, same as disable0
-
-        const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = {
-        /* port 0 */
-        {       // primary rank pair 0
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F},
-                // primary rank pair 1
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F},
-                // primary rank pair 2
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F},
-                // primary rank pair 3
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F}
-        },
-        /* port 1 */
-        {
-           // primary rank pair 0
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F},
-           // primary rank p1
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F},
-           // primary rank pair 2
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F},
-           // primary rank pair 3
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F}
-        }};
-        const uint8_t rg_invalid[] = {
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID,
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID,
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID,
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID,
-        };
-
-        const uint16_t wrclk_disable_mask[] = {         // by quads
-                0x8800, 0x4400, 0x2280, 0x1140
-        };
-
-        uint8_t l_dram_width, l_disable1_fixed, l_disable1_rdclk_fixed;
-        uint64_t l_addr;
-        // 0x8000007d0301143f    from disable0 register
-        const uint64_t l_disable1_addr_offset = 0x0000000100000000ull;
-        // 0x800000050301143f    from disable1 register
-        const uint64_t l_wrclk_en_addr_mask   = 0xFFFFFF07FFFFFFFFull;
-
-        ReturnCode rc;
-        ecmdDataBufferBase data_buffer(64);
-        ecmdDataBufferBase db_reg(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank0(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank1(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank2(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank3(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank4(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank5(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank6(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_rank7(BITS_PER_PORT);
-        uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
-        uint8_t prg[MAX_PRI_RANKS][MAX_PORTS];          // primary rank group values
-
-        FAPI_INF("Running flash->registers(set)");
-
-        std::vector<Target> mba_dimms;
-        rc = fapiGetAssociatedDimms(mba_target, mba_dimms);     // functional dimms
-        if(rc) return rc;
-
-        // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port],
-        //                                               GROUP2[port], GROUP3[port]
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]);
-        if(rc) return rc;
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]);
-        if(rc) return rc;
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]);
-        if(rc) return rc;
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]);
-        if(rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width);
-        if(rc) return rc;
-
-
-
-        fapi::Target l_target_centaur;
-        rc = fapiGetParentChip(mba_target, l_target_centaur);
-        if(rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_REG_FIXED, &l_target_centaur, l_disable1_fixed);
-        if(rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_RDCLK_REG_FIXED, &l_target_centaur, l_disable1_rdclk_fixed);
-        if(rc) return rc;
-
-        switch (l_dram_width)
-        {
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X4:
-                        l_dram_width = 4;
-                        break;
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X8:
-                        l_dram_width = 8;
-                        break;
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X16:
-                        l_dram_width = 16;
-                        break;
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X32:
-                        l_dram_width = 32;
-                        break;
-                default:
-                        //DECONFIG and FFDC INFO
-                        const fapi::Target & TARGET_MBA_ERROR = mba_target;
-                        const uint8_t & WIDTH = l_dram_width;
-
-                        FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_SETBBM);
-                        return rc;
-        }
-
-        l_ecmdRc = data_buffer.flushTo0();
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-                 FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                 "- rc 0x%.8X", l_ecmdRc);
-                 rc.setEcmdError(l_ecmdRc);
-                 return rc;
-        }
-        for (uint8_t port = 0; port < MAX_PORTS; port++ )       // [0:1]
-        {
-                db_reg_rank0.flushTo0();
-                db_reg_rank1.flushTo0();
-                db_reg_rank2.flushTo0();
-                db_reg_rank3.flushTo0();
-                db_reg_rank4.flushTo0();
-                db_reg_rank5.flushTo0();
-                db_reg_rank6.flushTo0();
-                db_reg_rank7.flushTo0();
-                uint8_t is_clean = 1;
-
-                uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid
-                uint8_t l_rank1_invalid = 1;
-                uint8_t l_rank2_invalid = 1;
-                uint8_t l_rank3_invalid = 1;
-                uint8_t l_rank4_invalid = 1;
-                uint8_t l_rank5_invalid = 1;
-                uint8_t l_rank6_invalid = 1;
-                uint8_t l_rank7_invalid = 1;
-
-                // Gather all ranks first
-                // loop through primary ranks [0:3]
-                for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
-                {
-
-                        is_clean = 1;
-                        if (prg[prank][port] == rg_invalid[prank])      // invalid rank
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-
-                                continue;
-                        }
-
-                        if ( prg[prank][port] == 0)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 0, 0, db_reg_rank0, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 0, 0,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank0_invalid = 0;
-                        }
-
-                        if ( prg[prank][port] == 1)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 0, 1, db_reg_rank1, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 0, 1,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank1_invalid = 0;
-                        }
-
-                        if ( prg[prank][port] == 2)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 0, 2, db_reg_rank2, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 0, 2,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank2_invalid = 0;
-                        }
-
-
-                        if ( prg[prank][port] == 3)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 0, 3, db_reg_rank3, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 0, 3,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank3_invalid = 0;
-                        }
-
-
-
-                        if ( prg[prank][port] == 4)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 1, 0, db_reg_rank4, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 1, 0,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank4_invalid = 0;
-                        }
-
-
-                        if ( prg[prank][port] == 5)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 1, 1, db_reg_rank5, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 1, 1,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank5_invalid = 0;
-                        }
-
-
-                        if ( prg[prank][port] == 6)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 1, 2, db_reg_rank6, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 1, 2,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank6_invalid = 0;
-                        }
-
-
-                        if ( prg[prank][port] == 7)
-                        {
-                                FAPI_DBG("BYTE DISABLE WORKAROUND  Primary rank group (prank) %i port %d rank value: %d Not INVALID, Marking and continuing...",
-                                                prank, port, prg[prank][port]);
-                                rc = getC4dq2reg(mba_target, port, 1, 3, db_reg_rank7, is_clean);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                        "dimm=%i, rank=%i rc=%i", port, 1, 3,
-                                                        static_cast<uint32_t>(rc));
-                                        return rc;
-                                }
-                                l_rank7_invalid = 0;
-                        }
-
-                }
-
-                // loop through primary ranks [0:3]
-                for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
-                {
-                        uint8_t dimm = prg[prank][port] >> 2;
-                        uint8_t rank = prg[prank][port] & 0x03;
-                        uint16_t l_data = 0;
-                        uint16_t l_data_rank0 = 0;
-                        uint16_t l_data_rank1 = 0;
-                        uint16_t l_data_rank2 = 0;
-                        uint16_t l_data_rank3 = 0;
-                        uint16_t l_data_rank4 = 0;
-                        uint16_t l_data_rank5 = 0;
-                        uint16_t l_data_rank6 = 0;
-                        uint16_t l_data_rank7 = 0;
-                        is_clean = 1;
-
-                        if (prg[prank][port] == rg_invalid[prank])      // invalid rank
-                        {
-                                FAPI_DBG("Primary rank group %i: INVALID, continuing...",
-                                                prank);
-                                continue;
-                        }
-
-                        rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg, is_clean);
-                        if (rc)
-                        {
-                                FAPI_ERR("Error from getting register bitmap port=%i: "
-                                                "dimm=%i, rank=%i rc=%i", port, dimm, rank,
-                                                static_cast<uint32_t>(rc));
-                                return rc;
-                        }
-
-
-
-                        // quick test to move on to next rank if no bits need to be set
-                        if (is_clean == 1)                      // Note ignores spares that match attribute
-                        {
-                                FAPI_INF("Primary rank group %i: No bad bits found for "
-                                                "p%i:d%i:r%i:cs%i", prank, port, dimm, rank,
-                                                prg[prank][port]);
-                                continue;
-                        }
-                        for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4]
-                        {
-                                uint8_t disable1_data = 0;
-                                uint16_t wrclk_mask = 0;
-
-                                // check or not to check(always set register)?
-                                l_data = db_reg.getHalfWord(i);
-                                l_data_rank0 = db_reg_rank0.getHalfWord(i);
-                                l_data_rank1 = db_reg_rank1.getHalfWord(i);
-                                l_data_rank2 = db_reg_rank2.getHalfWord(i);
-                                l_data_rank3 = db_reg_rank3.getHalfWord(i);
-                                l_data_rank4 = db_reg_rank4.getHalfWord(i);
-                                l_data_rank5 = db_reg_rank5.getHalfWord(i);
-                                l_data_rank6 = db_reg_rank6.getHalfWord(i);
-                                l_data_rank7 = db_reg_rank7.getHalfWord(i);
-
-                                if (l_data == 0)
-                                {
-                                        FAPI_DBG("\tDP18_%i has no bad bits set, continuing...", i);
-                                        continue;
-                                }
-                                // clear bits 48:63
-                                l_ecmdRc = data_buffer.flushTo0();
-                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                {
-                                         FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                         rc.setEcmdError(l_ecmdRc);
-                                         return rc;
-                                }
-
-                                uint16_t mask = 0xF000;
-                                // Temp 0xE removed.
-                                //uint16_t emask = 0xE000;
-                                uint8_t all_F_mask = 0;
-                                for (uint8_t n=0; n < 4; n++) { // check each nibble
-                                        uint16_t nmask = mask >> (4*n);
-                                        // Temp 0xE removed.
-                                        //uint16_t e_nmask = emask >> (4*n);
-
-
-                                        if ((nmask & l_data) == nmask) {
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND  Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data);
-                                                if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) &&
-                                                     ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) &&
-                                                     ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) &&
-                                                     ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) &&
-                                                     ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) &&
-                                                     ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) &&
-                                                     ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) &&
-                                                     ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) )   )
-                                                {
-                                                        //Leave it an F.
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND  All ranks are a F so writing an 0xF to disable regs.");
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND  data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 );
-                                                        all_F_mask = 1;
-                                                }
-                                                else
-                                                {
-                                                        //Replacing F nibble with E nibble
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND  Single rank is a 0xF so writing an 0x0 to disable regs. PRE DATA: 0x%04X", l_data);
-                                                        l_data = l_data & ~(nmask);
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND  POST DATA: 0x%04X", l_data);
-                                                }
-                                        }
-
-                                        // Temporarily removing the 0xE case
-                                        /*
-                                        if ((nmask & l_data) == e_nmask) {
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND  Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data=0x%04X", n, port, dimm, prank, rank, l_data);
-
-                                                //Leave it an E.
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND  Found a 0xE so writing an 0xE to disable regs.");
-
-                                        }
-                                        */
-
-                                        uint16_t wrclk_nmask = 0xF000 >> (4*n);
-                                        if (l_dram_width != 4) // x8 only disable the wrclk
-                                        {
-
-                                                if (((wrclk_nmask & l_data)>>(4*(3-n))) == 0x0F)
-                                                {
-                                                        wrclk_mask |= wrclk_disable_mask[n];
-                                                }
-                                        }
-
-                                }
-
-
-                                if (all_F_mask ==1) {
-                                FAPI_INF("Entering into all F across all ranks case. Need to Disable WRCLK Enable as well.");
-                                for (uint8_t n=0; n < 4; n++)   // check each nibble
-                                {
-                                        uint16_t nmask = 0xF000 >> (4*n);
-                                        if (l_dram_width == 4)
-                                        {
-                                                if ((nmask & l_data) == nmask)          // bad bit(s) in nibble
-                                                {
-                                                         //     For Marc Gollub, since repair for x4 DRAM is in nibble
-                                                         //     granularity.  Also due to higher chance of hitting dq0 of
-                                                         //     Micron causing write leveling to fail for entire x4 DRAM.
-                                                         //     Will also save a re-training loop.  Complement in get_bbm_regs.
-
-
-                                                        FAPI_INF("Disabling entire nibble %i",n);
-                                                        rc = mss_get_dqs_lane(mba_target, port, i, n,
-                                                                        disable1_data);
-                                                        if (rc) return rc;
-                                                        wrclk_mask |= wrclk_disable_mask[n];
-                                                }
-                                        }  // end x4
-                                        else    // width == 8+?
-                                        {
-                                                if ((n % 2) == 0)
-                                                {
-                                                        nmask = 0xFF00 >> (4*n);
-                                                        if ((nmask & l_data) == nmask)  // entire byte bad
-                                                        {
-                                                                disable1_data |= (0xF0 >> (n*2));
-                                                        }
-                                                }
-                                                if (((nmask & l_data)>>(4*(3-n))) == 0x0F)
-                                                {
-                                                        wrclk_mask |= wrclk_disable_mask[n];
-                                                }
-                                        }
-                                }
-
-                                }
-
-
-                                FAPI_DBG("\t\tdisable1_data=0x%04X", disable1_data);
-
-                                // set disable0(dq) reg
-                                l_ecmdRc |= data_buffer.setHalfWord(3, l_data);
-
-                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                {
-                                         FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                         rc.setEcmdError(l_ecmdRc);
-                                         return rc;
-                                }
-
-                                l_addr = disable_reg[port][prank][i];
-
-                                FAPI_INF("+++ Setting Disable0 Bad Bit Mask p%i: DIMM%i PRG%i "
-                                        "Rank%i dp18_%i addr=0x%llx, data=0x%04X", port,
-                                        dimm, prank, prg[prank][port], i, l_addr , l_data);
-
-                                rc = fapiPutScomUnderMask(mba_target, l_addr, data_buffer,
-                                                data_buffer);
-
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from fapiPutScom writing disable0 reg");
-                                        return rc;
-                                }
-
-                                if (all_F_mask ==1) {
-                                        FAPI_INF("Entering into all F across ranks case. Need to Disable DQS as well.");
-                                        // set address for disable1(dqs) register
-                                        l_addr += l_disable1_addr_offset;
-                                        if (disable1_data != 0)
-                                        {
-                                                l_ecmdRc = data_buffer.flushTo0();  // clear buffer
-                                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                                {
-                                                FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                                                "- rc 0x%.8X", l_ecmdRc);
-
-                                                rc.setEcmdError(l_ecmdRc);
-                                                return rc;
-                                                }
-
-                                                l_ecmdRc = data_buffer.setByte(6, disable1_data);
-                                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                                {
-                                                FAPI_ERR("Error from ecmdDataBuffer setByte() "
-                                                                "- rc 0x%.8X", l_ecmdRc);
-
-                                                rc.setEcmdError(l_ecmdRc);
-                                                return rc;
-                                                }
-
-                                                // write disable1(dqs) register
-                                                rc = fapiPutScomUnderMask(mba_target, l_addr,
-                                                data_buffer, data_buffer);
-                                                if (rc)
-                                                {
-                                                FAPI_ERR("Error from PutScom writing disable1 reg");
-                                                return rc;
-                                                }
-                                        } // end disable1_data != 0
-
-
-                                        // set address for wrclk_en register
-                                        l_addr &= l_wrclk_en_addr_mask;
-
-                                        if (wrclk_mask != 0)
-                                        {
-                                                l_ecmdRc = data_buffer.flushTo0();      // clear buffer
-                                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                                {
-                                                         FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                         rc.setEcmdError(l_ecmdRc);
-                                                         return rc;
-                                                }
-                                                ecmdDataBufferBase put_mask(64);
-                                                l_ecmdRc = put_mask.setHalfWord(3, wrclk_mask);
-                                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                                {
-                                                         FAPI_ERR("Error from ecmdDataBuffer setHalfWord()"
-                                                                         " for wrclk_mask - rc 0x%.8X", l_ecmdRc);
-
-                                                         rc.setEcmdError(l_ecmdRc);
-                                                         return rc;
-                                                }
-
-                                                if (!l_disable1_fixed)
-                                                {
-                                                        // clear(0) out the unused quads for wrclkdb_reg
-                                                        rc = fapiPutScomUnderMask(mba_target, l_addr,
-                                                                        data_buffer, put_mask);
-                                                        if (rc)
-                                                        {
-                                                                FAPI_ERR("Error from fapiPutScomUnderMask writing "
-                                                                                "wrclk_en reg");
-                                                                return rc;
-                                                        }
-                                                }
-                                                // does disabling read clocks for unused bytes cause problems?
-                                                // SW25701 Workaround - x4s will not mask out RDCLKs on Bad Bits to avoid translation issues
-                                                else if ( (!l_disable1_rdclk_fixed) && (l_dram_width != 4) )
-                                                {
-                                                        uint64_t rdclk_addr =
-                                                                disable_reg[port][prank][i] & 0xFFFFFF040FFFFFFFull;
-                                                        // clear(0) out the unused quads for rdclk
-                                                        rc = fapiPutScomUnderMask(mba_target, rdclk_addr,
-                                                                data_buffer, put_mask);
-                                                        if (rc)
-                                                        {
-                                                                FAPI_ERR("Error from fapiPutScomUnderMask writing "
-                                                                                        "rdclk_en reg");
-                                                                return rc;
-                                                        }
-
-                                                        FAPI_DBG("rdclk_addr=0x%llx, wrclk_addr=0x%llx, "
-                                                                "wrclk_mask=0x%04X", rdclk_addr, l_addr, wrclk_mask);
-                                                }
-                                        } // end wrclk_mask != 0
-                                }
-
-
-                        } // end DP18 instance loop
-                } // end primary rank loop
-        } // end port loop
-    return rc;
-} // end mss_set_bbm_regs
-
-
-fapi::ReturnCode mss_get_dqs_lane (const fapi::Target & i_mba,
-                const uint8_t i_port, const uint8_t i_block, const uint8_t i_quad,
-                uint8_t &o_lane)
-{
-// input  = mba, port, dp18 block, quad
-// output = OR'd in lane of the dqs for the specified input
-
-        ReturnCode rc;
-        uint8_t dq, dqs;
-        uint8_t phy_lane = i_quad * 4;
-        uint8_t l_block = i_block;
-        // returns dq
-        rc=mss_c4_phy(i_mba,i_port,0,RD_DQ,dq,1,phy_lane,l_block,1);
-        if (rc) return rc;
-        FAPI_INF("DQ returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dq,phy_lane,l_block);
-
-        dqs = dq / 4;
-        // returns phy_lane
-        rc=mss_c4_phy(i_mba,i_port,0,WR_DQS,dqs,1,phy_lane,l_block,0);
-        if (rc) return rc;
-        FAPI_INF("phy_lane returning mss_c4_phy inputs port: %d input index: %d phy_lane: %d block: %d",i_port,dqs,phy_lane,l_block);
-
-        if (l_block != i_block)
-        {
-                FAPI_ERR("\t !!!  blocks don't match from c4 to phy i_block=%i,"
-                           " o_block=%i", i_block, l_block);
-        }
-
-        switch (phy_lane)
-        {
-                case 16:
-                case 17:
-                        o_lane |= 0xC0;
-                        break;
-                case 18:
-                case 19:
-                        o_lane |= 0x30;
-                        break;
-                case 20:
-                case 21:
-                        o_lane |= 0x0C;
-                        break;
-                case 22:
-                case 23:
-                        o_lane |= 0x03;
-                        break;
-                default:
-                        //DECONFIG and FFDC INFO
-                        const fapi::Target & TARGET_MBA_ERROR = i_mba;
-                        const uint8_t & PORT = i_port;
-                        const uint8_t & BLOCK = i_block;
-                        const uint8_t & QUAD = i_quad;
-                        const uint8_t & PHYLANE = phy_lane;
-
-                        FAPI_ERR("\t!!!  (Port%i, dp18_%i, q=%i)  phy_lane(%i)"
-                                "returned from mss_c4_phy is invalid",
-                                i_port, i_block, i_quad, phy_lane);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_C4_PHY_TRANSLATION_ERROR);
-        }
-        return rc;
-} //end mss_get_dqs_lane
-
-fapi::ReturnCode mss_get_bbm_regs (const fapi::Target & mba_target, uint8_t i_training_success)
-{
-// Registers to Flash.
-
-        const uint64_t disable_reg[MAX_PORTS][MAX_PRI_RANKS][DP18_INSTANCES] = {
-        /* port 0 */
-        {       // primary rank pair 0
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_0_0x8000007c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_1_0x8000047c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_2_0x8000087c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_3_0x80000c7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P0_4_0x8000107c0301143F},
-                // primary rank pair 1
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_0_0x8000017c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_1_0x8000057c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_2_0x8000097c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_3_0x80000d7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P0_4_0x8000117c0301143F},
-                // primary rank pair 2
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_0_0x8000027c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_1_0x8000067c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_2_0x80000a7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_3_0x80000e7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P0_4_0x8000127c0301143F},
-                // primary rank pair 3
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_0_0x8000037c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_1_0x8000077c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_2_0x80000b7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_3_0x80000f7c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P0_4_0x8000137c0301143F}
-        },
-        /* port 1 */
-        {
-           // primary rank pair 0
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_0_0x8001007c0301143F,
-                DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_1_0x8001047c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_2_0x8001087c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_3_0x80010c7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP0_P1_4_0x8001107c0301143F},
-           // primary rank pair 1
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_0_0x8001017c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_1_0x8001057c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_2_0x8001097c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_3_0x80010d7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP1_P1_4_0x8001117c0301143F},
-           // primary rank pair 2
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_0_0x8001027c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_1_0x8001067c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_2_0x80010a7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_3_0x80010e7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP2_P1_4_0x8001127c0301143F},
-           // primary rank pair 3
-           {DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_0_0x8001037c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_1_0x8001077c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_2_0x80010b7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_3_0x80010f7c0301143F,
-            DPHY01_DDRPHY_DP18_DATA_BIT_DISABLE0_RP3_P1_4_0x8001137c0301143F}
-
-        }};
-
-        const uint8_t rg_invalid[] = {
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP0_INVALID,
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP1_INVALID,
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP2_INVALID,
-                ENUM_ATTR_EFF_PRIMARY_RANK_GROUP3_INVALID,
-        };
-
-        ReturnCode rc;
-        ecmdDataBufferBase data_buffer(64);
-        ecmdDataBufferBase db_reg(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_vpd(BITS_PER_PORT);
-        uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
-        uint8_t prg[MAX_PRI_RANKS][MAX_PORTS];          // primary rank group values
-        uint8_t l_dram_width;
-        uint8_t dimm;
-        uint8_t l_rank0_invalid = 1; //0 = valid, 1 = invalid
-        uint8_t l_rank1_invalid = 1;
-        uint8_t l_rank2_invalid = 1;
-        uint8_t l_rank3_invalid = 1;
-        uint8_t l_rank4_invalid = 1;
-        uint8_t l_rank5_invalid = 1;
-        uint8_t l_rank6_invalid = 1;
-        uint8_t l_rank7_invalid = 1;
-
-        //Storing all the errors across rank/eff dimm
-        ecmdDataBufferBase db_reg_dimm0_rank0(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm0_rank1(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm0_rank2(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm0_rank3(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm1_rank0(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm1_rank1(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm1_rank2(BITS_PER_PORT);
-        ecmdDataBufferBase db_reg_dimm1_rank3(BITS_PER_PORT);
-
-
-        FAPI_INF("Running (get)registers->flash");
-
-        std::vector<Target> mba_dimms;
-        rc = fapiGetAssociatedDimms(mba_target, mba_dimms);     // functional dimms
-        if(rc) return rc;
-
-        // 4 dimms per MBA, 2 per port
-        // ATTR_EFF_PRIMARY_RANK_GROUP0[port], GROUP1[port],
-        //                                               GROUP2[port], GROUP3[port]
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP0, &mba_target, prg[0]);
-        if(rc) return rc;
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP1, &mba_target, prg[1]);
-        if(rc) return rc;
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP2, &mba_target, prg[2]);
-        if(rc) return rc;
-        rc=FAPI_ATTR_GET(ATTR_EFF_PRIMARY_RANK_GROUP3, &mba_target, prg[3]);
-        if(rc) return rc;
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &mba_target, l_dram_width);
-        if(rc) return rc;
-
-        switch (l_dram_width)
-        {
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X4:
-                        l_dram_width = 4;
-                        break;
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X8:
-                        l_dram_width = 8;
-                        break;
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X16:
-                        l_dram_width = 16;
-                        break;
-                case ENUM_ATTR_EFF_DRAM_WIDTH_X32:
-                        l_dram_width = 32;
-                        break;
-                default:
-                        //DECONFIG and FFDC INFO
-                        const fapi::Target & TARGET_MBA_ERROR = mba_target;
-                        const uint8_t & WIDTH = l_dram_width;
-
-                        FAPI_ERR("ATTR_EFF_DRAM_WIDTH is invalid %u", l_dram_width);
-                        FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DRAM_WIDTH_INPUT_ERROR_GETBBM);
-                        return rc;
-        }
-
-        l_ecmdRc = data_buffer.flushTo0();
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-                 FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                 "- rc 0x%.8X", l_ecmdRc);
-
-                 rc.setEcmdError(l_ecmdRc);
-                 return rc;
-        }
-        for (uint8_t port = 0; port < MAX_PORTS; port++ )       // [0:1]
-        {
-                // Initialize all the stored errors to 0.
-                l_ecmdRc |= db_reg_dimm0_rank0.flushTo0();
-                l_ecmdRc |= db_reg_dimm0_rank1.flushTo0();
-                l_ecmdRc |= db_reg_dimm0_rank2.flushTo0();
-                l_ecmdRc |= db_reg_dimm0_rank3.flushTo0();
-                l_ecmdRc |= db_reg_dimm1_rank0.flushTo0();
-                l_ecmdRc |= db_reg_dimm1_rank1.flushTo0();
-                l_ecmdRc |= db_reg_dimm1_rank2.flushTo0();
-                l_ecmdRc |= db_reg_dimm1_rank3.flushTo0();
-                l_rank0_invalid = 1; //0 = valid, 1 = invalid
-                l_rank1_invalid = 1;
-                l_rank2_invalid = 1;
-                l_rank3_invalid = 1;
-                l_rank4_invalid = 1;
-                l_rank5_invalid = 1;
-                l_rank6_invalid = 1;
-                l_rank7_invalid = 1;
-
-                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                {
-                         FAPI_ERR("Error from ecmdDataBuffer setHalfWord()"
-                                         " for wrclk_mask - rc 0x%.8X", l_ecmdRc);
-
-                         rc.setEcmdError(l_ecmdRc);
-                         return rc;
-                }
-
-                // loop through primary ranks [0:3]
-                for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
-                {
-                        dimm = prg[prank][port] >> 2;
-                        uint8_t rank = prg[prank][port] & 0x03;
-                        uint16_t l_data = 0;
-
-                        if (prg[prank][port] == rg_invalid[prank])      // invalid rank
-                        {
-                                FAPI_DBG("Primary rank group %i is INVALID, continuing...",
-                                                prank);
-                                if ( prg[prank][port] == 0)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank0.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-                                if ( prg[prank][port] == 1)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank1.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-                                if ( prg[prank][port] == 2)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank2.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-
-                                if ( prg[prank][port] == 3)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank3.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-
-
-                                if ( prg[prank][port] == 4)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank0.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-
-                                if ( prg[prank][port] == 5)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank1.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-
-                                if ( prg[prank][port] == 6)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank2.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-
-                                if ( prg[prank][port] == 7)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank3.flushTo1();
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-                                }
-
-                                continue;
-                        }
-
-                        // create the db_reg (all the failed bits of the port)
-                        l_ecmdRc = db_reg.flushTo0();
-                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                        {
-                                 FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                                 "- rc 0x%.8X", l_ecmdRc);
-
-                                 rc.setEcmdError(l_ecmdRc);
-                                 return rc;
-                        }
-
-                        FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank);
-                        for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4]
-                        {
-                                // clear bits 48:63
-                                l_ecmdRc = data_buffer.clearBit(48, BITS_PER_REG);
-                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                {
-                                         FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                         rc.setEcmdError(l_ecmdRc);
-                                         return rc;
-                                }
-
-                                rc = fapiGetScom(mba_target, disable_reg[port][prank][i],
-                                                data_buffer);
-                                if (rc)
-                                {
-                                        FAPI_ERR("Error from fapiPutScom writing disable reg");
-                                        return rc;
-                                }
-
-                                l_data = data_buffer.getHalfWord(3);
-
-                                FAPI_DBG("dp18_%i  0x%llx = 0x%x", i,
-                                                disable_reg[port][prank][i], l_data);
-
-                                if (l_data != 0)
-                                {
-
-                                        l_ecmdRc = db_reg.setHalfWord(i, l_data);
-                                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                        {
-                                                 FAPI_ERR("Error from ecmdDataBuffer setHalfWord() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                                 rc.setEcmdError(l_ecmdRc);
-                                                 return rc;
-                                        }
-
-                                        FAPI_INF("+++ Setting Bad Bit Mask p%i: DIMM%i PRG%i "
-                                                "Rank%i \tdp18_%i addr=0x%llx, data=0x%04X", port,
-                                                dimm, prank, prg[prank][port], i,
-                                                disable_reg[port][prank][i], l_data);
-                                }
-                        } // end DP18 instance loop
-
-                        if (prg[prank][port] == rg_invalid[prank])      // invalid rank
-                        {
-                                FAPI_DBG("Primary rank group %i: INVALID, continuing...",
-                                                prank);
-
-                                continue;
-                        }
-
-
-                        if (dimm == 0)
-                        {
-                                if (rank == 0)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank0);
-                                        l_rank0_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                                else if (rank == 1)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank1);
-                                        l_rank1_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                                else if (rank == 2)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank2);
-                                        l_rank2_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                                else if (rank == 3)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm0_rank3);
-                                        l_rank3_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                        }
-                        else if (dimm == 1)
-                        {
-                                if (rank == 0)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank0);
-                                        l_rank4_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                                else if (rank == 1)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank1);
-                                        l_rank5_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                                else if (rank == 2)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank2);
-                                        l_rank6_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                                else if (rank == 3)
-                                {
-                                        l_ecmdRc |= db_reg.copy(db_reg_dimm1_rank3);
-                                        l_rank7_invalid = 0; //0 = valid, 1 = invalid
-                                }
-                        }
-
-                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                        {
-                                 FAPI_ERR("Error from ecmdDataBuffer copy() "
-                                         "- rc 0x%.8X", l_ecmdRc);
-
-                                 rc.setEcmdError(l_ecmdRc);
-                                 return rc;
-                        }
-
-                } // end primary rank loop
-
-
-                // loop through primary ranks [0:3]
-                for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
-                {
-
-                        dimm = prg[prank][port] >> 2;
-                        uint8_t rank = prg[prank][port] & 0x03;
-                        uint16_t l_data = 0;
-                        uint16_t l_data_rank0 = 0;
-                        uint16_t l_data_rank1 = 0;
-                        uint16_t l_data_rank2 = 0;
-                        uint16_t l_data_rank3 = 0;
-                        uint16_t l_data_rank4 = 0;
-                        uint16_t l_data_rank5 = 0;
-                        uint16_t l_data_rank6 = 0;
-                        uint16_t l_data_rank7 = 0;
-                        uint16_t l_data_curr_vpd = 0;
-
-                        if (prg[prank][port] == rg_invalid[prank])      // invalid rank
-                        {
-                                FAPI_DBG("Primary rank group %i is INVALID, continuing...",
-                                                prank);
-                                continue;
-                        }
-
-                        FAPI_DBG("Port%i, dimm=%i, prg%i rank=%i", port, dimm, prank, rank);
-                        for ( uint8_t i=0; i < DP18_INSTANCES; i++ ) // dp18 [0:4]
-                        {
-
-
-                                l_data_rank0 = db_reg_dimm0_rank0.getHalfWord(i);
-                                l_data_rank1 = db_reg_dimm0_rank1.getHalfWord(i);
-                                l_data_rank2 = db_reg_dimm0_rank2.getHalfWord(i);
-                                l_data_rank3 = db_reg_dimm0_rank3.getHalfWord(i);
-                                l_data_rank4 = db_reg_dimm1_rank0.getHalfWord(i);
-                                l_data_rank5 = db_reg_dimm1_rank1.getHalfWord(i);
-                                l_data_rank6 = db_reg_dimm1_rank2.getHalfWord(i);
-                                l_data_rank7 = db_reg_dimm1_rank3.getHalfWord(i);
-
-
-
-                                if (dimm == 0)
-                                {
-                                        if (rank == 0)
-                                        {
-                                                l_data = l_data_rank0;
-                                        }
-                                        else if (rank == 1)
-                                        {
-                                                l_data = l_data_rank1;
-                                        }
-                                        else if (rank == 2)
-                                        {
-                                                l_data = l_data_rank2;
-                                        }
-                                        else if (rank == 3)
-                                        {
-                                                l_data = l_data_rank3;
-                                        }
-                                }
-                                else if (dimm == 1)
-                                {
-                                        if (rank == 0)
-                                        {
-                                                l_data = l_data_rank4;
-                                        }
-                                        else if (rank == 1)
-                                        {
-                                                l_data = l_data_rank5;
-                                        }
-                                        else if (rank == 2)
-                                        {
-                                                l_data = l_data_rank6;
-                                        }
-                                        else if (rank == 3)
-                                        {
-                                                l_data = l_data_rank7;
-                                        }
-                                }
-
-
-                                uint8_t is_clean = 1;
-                                rc = getC4dq2reg(mba_target, port, dimm, rank, db_reg_vpd, is_clean);
-                                l_data_curr_vpd = db_reg_vpd.getHalfWord(i);
-
-                                uint16_t mask = 0xF000;
-                                // Temp remove of 0xE case
-                                //uint16_t emask = 0xE000;
-                                for (uint8_t n=0; n < 4; n++) { // check each nibble
-                                        uint16_t nmask = mask >> (4*n);
-                                        // Temp remove of 0xE case
-                                        //uint16_t e_nmask = emask >> (4*n);
-
-
-                                        if ((nmask & l_data_curr_vpd) == nmask) {
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XF on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data);
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND: data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 );
-                                                if (i_training_success)
-                                                {       //Leave it an F.
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xF to VPD. PRE data: 0x%04X", l_data);
-                                                        l_data = l_data | nmask;
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data);
-                                                }
-                                                else
-                                                {
-                                                        if ( ( ((nmask & l_data_rank0) == nmask) || (l_rank0_invalid) ) &&
-                                                             ( ((nmask & l_data_rank1) == nmask) || (l_rank1_invalid) ) &&
-                                                             ( ((nmask & l_data_rank2) == nmask) || (l_rank2_invalid) ) &&
-                                                             ( ((nmask & l_data_rank3) == nmask) || (l_rank3_invalid) ) &&
-                                                             ( ((nmask & l_data_rank4) == nmask) || (l_rank4_invalid) ) &&
-                                                             ( ((nmask & l_data_rank5) == nmask) || (l_rank5_invalid) ) &&
-                                                             ( ((nmask & l_data_rank6) == nmask) || (l_rank6_invalid) ) &&
-                                                             ( ((nmask & l_data_rank7) == nmask) || (l_rank7_invalid) )   )
-                                                        {
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: All ranks were F's and training was not successful.  Uncool.");
-                                                                continue;
-                                                        }
-                                                        else
-                                                        {
-
-                                                                //Temprorarily removing 0xE version. Skipping Straight to 0xFs to all ranks.
-                                                                /*
-                                                                //Replacing F nibble with E nibble
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Training was not successful so writing an 0xE to VPD. PRE DATA: 0x%04X", l_data);
-                                                                l_data = (l_data & ~(nmask)) | e_nmask;
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data);
-                                                                */
-
-                                                                //Replacing E nibble with F nibble
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks.");
-                                                                l_data = l_data  | nmask;
-                                                                l_data_rank0 = l_data_rank0  | nmask;
-                                                                l_data_rank1 = l_data_rank1  | nmask;
-                                                                l_data_rank2 = l_data_rank2  | nmask;
-                                                                l_data_rank3 = l_data_rank3  | nmask;
-                                                                l_data_rank4 = l_data_rank4  | nmask;
-                                                                l_data_rank5 = l_data_rank5  | nmask;
-                                                                l_data_rank6 = l_data_rank6  | nmask;
-                                                                l_data_rank7 = l_data_rank7  | nmask;
-
-                                                        }
-                                                }
-                                        }
-                                        else if ( ((nmask & l_data_curr_vpd) != nmask) && ((nmask & l_data_curr_vpd) > 0)) {
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Found a non-zero, non-F nibble. Applying to all ranks.");
-
-                                                        if (l_dram_width == 4)
-                                                        {
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x4 so turning it to a 0xF. PRE DATA: 0x%04X", l_data);
-                                                                l_data = l_data  | nmask;
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: POST DATA: 0x%04X", l_data);
-
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 );
-                                                                l_data_rank0 = l_data_rank0  | nmask;
-                                                                l_data_rank1 = l_data_rank1  | nmask;
-                                                                l_data_rank2 = l_data_rank2  | nmask;
-                                                                l_data_rank3 = l_data_rank3  | nmask;
-                                                                l_data_rank4 = l_data_rank4  | nmask;
-                                                                l_data_rank5 = l_data_rank5  | nmask;
-                                                                l_data_rank6 = l_data_rank6  | nmask;
-                                                                l_data_rank7 = l_data_rank7  | nmask;
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 );
-
-                                                        }
-                                                        else if (l_dram_width == 8)
-                                                        {
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Its a x8 so leaving it the same.");
-
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: PRE data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 );
-                                                                l_data_rank0 = (l_data_rank0) | ( l_data & nmask);
-                                                                l_data_rank1 = (l_data_rank1) | ( l_data & nmask);
-                                                                l_data_rank2 = (l_data_rank2) | ( l_data & nmask);
-                                                                l_data_rank3 = (l_data_rank3) | ( l_data & nmask);
-                                                                l_data_rank4 = (l_data_rank4) | ( l_data & nmask);
-                                                                l_data_rank5 = (l_data_rank5) | ( l_data & nmask);
-                                                                l_data_rank6 = (l_data_rank6) | ( l_data & nmask);
-                                                                l_data_rank7 = (l_data_rank7) | ( l_data & nmask);
-
-                                                                FAPI_DBG("BYTE DISABLE WORKAROUND: POST data rank 0 =0x%04X rank 1 =0x%04X rank 2 =0x%04X rank 3 =0x%04X rank 4 =0x%04X rank 5 =0x%04X rank 6 =0x%04X rank 7 =0x%04X", l_data_rank0,l_data_rank1,l_data_rank2,l_data_rank3,l_data_rank4,l_data_rank5,l_data_rank6,l_data_rank7 );
-                                                        }
-
-
-
-
-                                        }
-                                        // Temporarily Removing the 0xE case with this workaround.
-                                        /*
-                                        else if ((nmask & l_data_curr_vpd) == e_nmask) {
-                                                FAPI_DBG("BYTE DISABLE WORKAROUND: Found a 0XE on nibble=%i Port%i, dimm=%i, prg%i rank=%i data= 0x%04X", n, port, dimm, prank, rank, l_data);
-                                                if (i_training_success)
-                                                {
-                                                        //Leave it an E.
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND: Training was successful so writing an 0xE to VPD.");
-                                                }
-                                                else
-                                                {
-                                                        //Replacing E nibble with F nibble
-                                                        FAPI_DBG("BYTE DISABLE WORKAROUND: Training failed so writing an 0xF to VPD for all ranks.");
-                                                        l_data = l_data  | nmask;
-                                                        l_data_rank0 = l_data_rank0  | nmask;
-                                                        l_data_rank1 = l_data_rank1  | nmask;
-                                                        l_data_rank2 = l_data_rank2  | nmask;
-                                                        l_data_rank3 = l_data_rank3  | nmask;
-                                                        l_data_rank4 = l_data_rank4  | nmask;
-                                                        l_data_rank5 = l_data_rank5  | nmask;
-                                                        l_data_rank6 = l_data_rank6  | nmask;
-                                                        l_data_rank7 = l_data_rank7  | nmask;
-                                                }
-                                        }
-                                        */
-                                }
-
-                                if (dimm == 0)
-                                {
-                                        if (rank == 0)
-                                        {
-                                                l_data_rank0 = l_data;
-                                        }
-                                        else if (rank == 1)
-                                        {
-                                                l_data_rank1 = l_data;
-                                        }
-                                        else if (rank == 2)
-                                        {
-                                                l_data_rank2 = l_data;
-                                        }
-                                        else if (rank == 3)
-                                        {
-                                                l_data_rank3 = l_data;
-                                        }
-                                }
-                                else if (dimm == 1)
-                                {
-                                        if (rank == 0)
-                                        {
-                                                l_data_rank4 = l_data;
-                                        }
-                                        else if (rank == 1)
-                                        {
-                                                l_data_rank5 = l_data;
-                                        }
-                                        else if (rank == 2)
-                                        {
-                                                l_data_rank6 = l_data;
-                                        }
-                                        else if (rank == 3)
-                                        {
-                                                l_data_rank7 = l_data;
-                                        }
-                                }
-
-
-                                l_ecmdRc |= db_reg_dimm0_rank0.setHalfWord(i, l_data_rank0);
-                                l_ecmdRc |= db_reg_dimm0_rank1.setHalfWord(i, l_data_rank1);
-                                l_ecmdRc |= db_reg_dimm0_rank2.setHalfWord(i, l_data_rank2);
-                                l_ecmdRc |= db_reg_dimm0_rank3.setHalfWord(i, l_data_rank3);
-
-                                l_ecmdRc |= db_reg_dimm1_rank0.setHalfWord(i, l_data_rank4);
-                                l_ecmdRc |= db_reg_dimm1_rank1.setHalfWord(i, l_data_rank5);
-                                l_ecmdRc |= db_reg_dimm1_rank2.setHalfWord(i, l_data_rank6);
-                                l_ecmdRc |= db_reg_dimm1_rank3.setHalfWord(i, l_data_rank7);
-
-                                if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                                {
-                                         FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                                         "- rc 0x%.8X", l_ecmdRc);
-                                         rc.setEcmdError(l_ecmdRc);
-                                         return rc;
-                                }
-
-
-                        }
-
-
-                }// end of primary rank loop
-
-
-                // loop through primary ranks [0:3]
-                for (uint8_t prank = 0; prank < MAX_PRI_RANKS; prank++ )
-                {
-                        dimm = prg[prank][port] >> 2;
-                        uint8_t rank = prg[prank][port] & 0x03;
-                        FAPI_DBG("BYTE DISABLE WORKAROUND: Looping through dimm: %d rank: %d ", dimm, rank);
-
-                        if (prg[prank][port] == rg_invalid[prank])      // invalid rank
-                        {
-                                FAPI_DBG("Primary rank group %i is INVALID, continuing...",
-                                                prank);
-                                continue;
-                        }
-
-                        if (dimm == 0)
-                        {
-                                if (rank == 0)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank0.copy(db_reg);
-                                }
-                                else if (rank == 1)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank1.copy(db_reg);
-                                }
-                                else if (rank == 2)
-                                {
-                                        l_ecmdRc |= db_reg_dimm0_rank2.copy(db_reg);
-                                }
-                                else if (rank == 3)
-                                {
-
-                                        l_ecmdRc |= db_reg_dimm0_rank3.copy(db_reg);
-                                }
-                        }
-                        else if (dimm == 1)
-                        {
-                                if (rank == 0)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank0.copy(db_reg);
-                                }
-                                else if (rank == 1)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank1.copy(db_reg);
-                                }
-                                else if (rank == 2)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank2.copy(db_reg);
-                                }
-                                else if (rank == 3)
-                                {
-                                        l_ecmdRc |= db_reg_dimm1_rank3.copy(db_reg);
-                                }
-                        }
-
-                        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-                        {
-                                 FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                                                 "- rc 0x%.8X", l_ecmdRc);
-                                 rc.setEcmdError(l_ecmdRc);
-                                 return rc;
-                        }
-
-                        FAPI_INF("Setting BBM across dimm: %d rank: %d", dimm, rank);
-                        rc = setC4dq2reg(mba_target, port, dimm, rank, db_reg);
-                        if (rc)
-                        {
-                                FAPI_ERR("Error from setting register bitmap p%i: "
-                                        "dimm=%i, rank=%i rc=%i", port, dimm, rank,
-                                        static_cast<uint32_t>(rc));
-                                return rc;
-                        }
-
-                }// end of primary rank loop
-
-
-
-        } // end port loop
-    return rc;
-} // end mss_get_bbm_regs
-
-
-ReturnCode getC4dq2reg(const Target & i_mba, const uint8_t i_port,
-                const uint8_t i_dimm, const uint8_t i_rank, ecmdDataBufferBase &o_reg, uint8_t &is_clean)
-{
-// used by set_bbm(flash to registers)
-// calls dimmGetBadDqBitmap and converts the data to phy order in a databuffer
-// output reg = in phy based order(lanes)
-
-    uint8_t l_bbm[TOTAL_BYTES] = {0};   // bad bitmap from dimmGetBadDqBitmap
-    ReturnCode rc;
-    uint32_t ecmdrc = ECMD_DBUF_SUCCESS;
-        uint8_t dq;
-        uint8_t phy_lane, phy_block;
-
-    ecmdrc = o_reg.flushTo0();          // clear output databuffer
-    if (ecmdrc != ECMD_DBUF_SUCCESS)
-    {
-                FAPI_ERR("Error from ecmdDataBuffer flushTo0() "
-                         "- rc 0x%.8X", ecmdrc);
-
-                rc.setEcmdError(ecmdrc);
-                return rc;
-    }
-
-    // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
-    rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
-    if (rc)
-    {
-                FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: "
-                         "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank,
-                         static_cast<uint32_t>(rc));
-                return rc;
-    }
-
-        uint8_t dimm_spare[MAX_PORTS][MAX_DIMMS][MAX_PRI_RANKS];
-        rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_SPARE, &i_mba, dimm_spare);
-        if(rc) return rc;
-
-        for (uint8_t byte=0; byte < TOTAL_BYTES; byte++)
-        {
-                if (l_bbm[byte] != 0)
-                {
-                        if (byte == (TOTAL_BYTES-1))            // spare byte
-                        {
-                                uint8_t spare_bitmap = 0;
-
-                                switch (dimm_spare[i_port][i_dimm][i_rank])
-                        {
-                                case ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE: // 0xFF
-                                    continue;                                                   // ignore bbm data for nonexistent spare
-                            break;
-                                case ENUM_ATTR_VPD_DIMM_SPARE_LOW_NIBBLE:
-                                    spare_bitmap = 0x0F;
-                            break;
-                                case ENUM_ATTR_VPD_DIMM_SPARE_HIGH_NIBBLE:
-                                    spare_bitmap = 0xF0;
-                            break;
-                                case ENUM_ATTR_VPD_DIMM_SPARE_FULL_BYTE:
-                                    spare_bitmap = 0x00;
-                            break;
-                                        default:
-
-                                                //DECONFIG and FFDC INFO
-                                                const fapi::Target & TARGET_MBA_ERROR = i_mba;
-                                                const uint8_t & SPARE = dimm_spare[i_port][i_dimm][i_rank];
-                                                const uint8_t & PORT = i_port;
-                                                const uint8_t & DIMM = i_dimm;
-                                                const uint8_t & RANK = i_rank;
-
-                                                FAPI_ERR("ATTR_VPD_DIMM_SPARE is invalid %u",
-                                                        dimm_spare[i_port][i_dimm][i_rank]);
-                                                FAPI_SET_HWP_ERROR(rc, RC_MSS_DRAMINIT_TRAINING_DIMM_SPARE_INPUT_ERROR);
-                                                return rc;
-                                }
-
-                                if (l_bbm[byte] == spare_bitmap)        // spare already set via initfile
-                                        continue;
-                        }
-
-                        uint8_t bs=0;
-                        uint8_t be=8;
-                        uint8_t loc=0;
-                        is_clean = 0;
-
-                        if ((l_bbm[byte] & 0xF0) == 0xF0)       // 0xF?
-                        {
-                                dq = (byte * 8);                // for first lane
-                                // input=cen_c4_dq, output=phy block, lane
-                                rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq,
-                                                0, phy_lane,phy_block, 0);
-                                if (rc) return rc;
-
-                                if (l_bbm[byte] == 0xFF)
-                                {       // block lanes + 1st lane{0,8}
-                                        loc = (phy_block * 16) + (phy_lane & 0x08);
-                                        o_reg.setBit(loc, 8);   // set dq byte
-                                        FAPI_DBG("0xFF  byte=%i, lbbm=0x%02x  dp%i_%i dq=%i o=%i",
-                                                byte, l_bbm[byte], phy_block, phy_lane, dq, loc);
-                                        continue;
-                                }
-                                // block lanes + 1st lane{0,4,8,12}
-                                loc = (phy_block * 16) + (phy_lane & 0x0C);
-                                o_reg.setBit(loc, 4);           // set dq nibble0
-                                FAPI_DBG("0xF0  byte=%i, lbbm=0x%02x  dp%i_%i dq=%i o=%i",
-                                        byte, l_bbm[byte], phy_block, phy_lane, dq, loc);
-
-                                if (l_bbm[byte] == 0xF0)                        // done with byte
-                                        continue;
-                                bs=4;           // processed the first 4 bits already
-                        }
-                        else if ((l_bbm[byte] & 0x0F) == 0x0F)  // 0x?F
-                        {
-                                dq = (byte * 8) + 4;            // for first lane of dq
-                                rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq,
-                                                0, phy_lane, phy_block, 0);
-                                if (rc) return rc;
-                                // block lanes + 1st lane{0,4,8,12}
-                                loc = (phy_block * 16) + (phy_lane & 0x0C);
-                                FAPI_DBG("0x0F  byte=%i, lbbm=0x%02x  dp%i_%i dq=%i o=%i",
-                                        byte, l_bbm[byte], phy_block, phy_lane, dq, loc);
-                                o_reg.setBit(loc, 4);                           // set dq nibble1
-                                if (l_bbm[byte] == 0x0F)                        // done with byte
-                                        continue;
-                                be=4;           // processed the last 4 bits already
-                        }
-                        else if ((l_bbm[byte] >> 4) == 0)       // 0x0?
-                                bs=4;
-                        else if ((l_bbm[byte] & 0x0F) == 0)     // 0x?0
-                                be=4;
-
-                        for (uint8_t b=bs; b < be; b++)         // test each bit
-                        {
-                                if ((l_bbm[byte] & (0x80 >> b)) > 0)            // bit is set,
-                                {
-                                        dq = (byte * 8) + b;
-                                        rc=mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq,
-                                                   0, phy_lane, phy_block, 0);
-                                        if (rc) return rc;
-                                        loc = (phy_block * 16) + phy_lane;
-                                        o_reg.setBit(loc);
-                                        FAPI_DBG("b=%i  byte=%i, lbbm=0x%02x  dp%i_%i dq=%i "
-                                                "loc=%i bs=%i be=%i", b, byte, l_bbm[byte],
-                                                phy_block, phy_lane, dq, loc, bs, be);
-                                }
-                        }
-                } // end if not clean
-        } // end byte
-        return rc;
-} // end getC4dq2reg
-
-
-ReturnCode setC4dq2reg(const Target &i_mba, const uint8_t i_port,
-   const uint8_t i_dimm, const uint8_t i_rank, const ecmdDataBufferBase &i_reg)
-{
-// used by get_bbm(registers to flash)
-// Converts the data from phy order (i_reg) to cen_c4_dq array
-// for dimmSetBadDqBitmap to write flash with
-
-        ReturnCode rc;
-        uint8_t l_bbm [TOTAL_BYTES] = {0};
-        uint8_t dq=0;
-        uint8_t phy_lane;
-        uint8_t phy_block;
-        uint8_t data;
-
-
-    // get Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
-    rc = dimmGetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
-    if (rc)
-    {
-                FAPI_ERR("Error from dimmGetBadDqBitmap on port %i: "
-                         "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank,
-                         static_cast<uint32_t>(rc));
-                return rc;
-    }
-
-        for (uint8_t byte=0; byte < TOTAL_BYTES; byte++)
-        {
-                data = i_reg.getByte(byte);
-                if (data != 0)                          // need to check bits
-                {
-                        uint8_t bs=0;
-                        uint8_t be=8;
-
-                        phy_block = (byte / 2);         // byte=[0..9], block=[0..4]
-                        FAPI_DBG("\n\t\t\t\t\t\tbyte=%i, data=0x%02x  phy_block=%i  ",
-                                byte, data, phy_block);
-                        if ((data & 0xF0) == 0xF0)      // 0xF?
-                        {
-                                phy_lane = 8 * (byte % 2);      // lane=[0,8]
-                                // input=block, lane  output=cen_dq
-                                rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ,dq,
-                                                0, phy_lane, phy_block, 1);
-                                if (rc) return rc;
-
-                                if (data == 0xFF)
-                                {       // set 8 consecutive bits of the cen_c4_dq
-                                        l_bbm[(dq/8)] = 0xFF;
-                                        FAPI_DBG("0xFF dp%i_%i dq=%i, lbbm=0x%02x",
-                                                phy_block, phy_lane, dq, l_bbm[dq/8]);
-                                        continue;
-                                }
-
-                                l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F;
-                                FAPI_DBG("0xF0 dp%i_%i dq=%i, lbbm=0x%02x",
-                                        phy_block, phy_lane, dq, l_bbm[dq/8]);
-
-                                if (data == 0xF0)                       // done with byte
-                                        continue;
-                                bs=4;                   // need to work on other bits
-                        }
-                        else if ((data & 0x0F) == 0x0F) // 0x?F
-                        {
-                                phy_lane = (8 * (byte % 2)) + 4;        // lane=[4,12]
-                                rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq,
-                                                0, phy_lane, phy_block, 1);
-                                if (rc) return rc;
-
-                                l_bbm[(dq/8)] |= ((dq % 8) < 4) ? 0xF0 : 0x0F;
-                                FAPI_DBG("0x0F dp%i_%i dq=%i, lbbm=0x%02x",
-                                           phy_block, phy_lane, dq, l_bbm[dq/8]);
-
-                                if (data == 0x0F)                       // done with byte
-                                        continue;
-                                be=4;                   // need to work on other bits
-                        }
-                        else if ((data >> 4) == 0)      // 0x0?
-                                bs=4;
-                        else if ((data & 0x0F) == 0)    // 0x?0
-                                be=4;
-
-                        for (uint8_t b=bs; b < be; b++)         // test each bit
-                        {
-                                if ((data & (0x80 >> b)) > 0)           // bit is set,
-                                {
-                                        phy_lane = (8 * (byte % 2)) + b;
-                                        rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq,
-                                                        0, phy_lane, phy_block, 1);
-                                        if (rc) return rc;
-                                        l_bbm[(dq/8)] |= (0x80 >> (dq % 8));
-
-                                }
-                                else            // bit is not set,
-                                {
-                                        phy_lane = (8 * (byte % 2)) + b;
-                                        rc = mss_c4_phy(i_mba, i_port, 0, RD_DQ, dq,
-                                                        0, phy_lane, phy_block, 1);
-                                        if (rc) return rc;
-                                        l_bbm[(dq/8)] &= (~(0x80 >> (dq % 8)));
-
-                                }
-                        }
-                } //end if not clean
-        } //end byte
-
-        // set Centaur dq bitmap (C4 signal) order=[0:79], array of bytes
-        rc = dimmSetBadDqBitmap(i_mba, i_port, i_dimm, i_rank, l_bbm);
-        if (rc)
-        {
-
-                FAPI_ERR("Error from dimmSetBadDqBitmap on port %i: "
-                        "dimm=%i, rank=%i rc=%i", i_port, i_dimm, i_rank,
-                        static_cast<uint32_t>(rc));
-                return rc;
-        }
-
-        return rc;
-} //end setC4dq2reg
-
-
-//Sets the DQS offset to be 16 instead of 8, recommended training settings
-fapi::ReturnCode mss_setup_dqs_offset(Target &i_target) {
-   fapi::ReturnCode rc;
-   uint32_t rc_num = 0;
-   ecmdDataBufferBase buffer(64);
-   uint64_t scom_addr_array[10] = {DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_0_0x800000370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_1_0x800004370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_2_0x800008370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_3_0x80000C370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P0_4_0x800010370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_0_0x800100370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_1_0x800104370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_2_0x800108370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_3_0x80010C370301143F ,
-      DPHY01_DDRPHY_DP18_DQSCLK_OFFSET_P1_4_0x800110370301143F};
-
-   FAPI_INF("DDR4: setting up DQS offset to be 16");
-   for(uint8_t scom_addr = 0; scom_addr < 10; ++scom_addr) {
-      rc = fapiGetScom(i_target, scom_addr_array[scom_addr], buffer);
-      if(rc) return rc;
-      //Setting up CCS mode
-      rc_num = rc_num | buffer.insertFromRight ((uint32_t)16, 49, 7);
-      if (rc_num)
-      {
-         FAPI_ERR( "mss_setup_dqs: Error setting up buffers");
-         rc.setEcmdError(rc_num);
-         return rc;
-      }
-      rc = fapiPutScom(i_target, scom_addr_array[scom_addr], buffer);
-      if(rc) return rc;
-   }
-
-   return rc;
-}
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
deleted file mode 100644
index 7e64ce845..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
+++ /dev/null
@@ -1,56 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit_training.H,v 1.3 2012/07/17 13:22:42 bellows Exp $
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|   Date:  | Author:  | Comment:
-//---------|----------|----------|-----------------------------------------------
-//  1.3    | 07/16/12 | bellows | added in Id tag
-//  1.1    | 02/20/12 | divyakum | Added target description
-//  1.0    | 11/14/11 | divyakum | First draft.
-
-#ifndef mss_draminit_training_H_
-#define mss_draminit_training_H_
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_draminit_training_FP_t)(const fapi::Target target);
-
-extern "C"
-{
-
-/**
- * @brief Draminit Training procedure. Calibrating DRAMs
- *
- * @param[in]  target  Reference to centaur.mba target
- *
- * @return ReturnCode
- */
-
-fapi::ReturnCode mss_draminit_training(const fapi::Target target);
-
-} // extern "C"
-
-#endif // mss_draminit_training_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
deleted file mode 100644
index 2c1accbf6..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C
+++ /dev/null
@@ -1,1020 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $                  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_funcs.C,v 1.43 2015/09/10 14:57:26 thi Exp $
-/* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE : mss_funcs.C
-// *! DESCRIPTION : Tools for centaur procedures
-// *! OWNER NAME : jdsloat@us.ibm.com
-// *! BACKUP NAME :
-// #! ADDITIONAL COMMENTS :
-//
-// General purpose funcs
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.43   | thi      |10-SEP-15| Fixed more RC stuff
-//  1.42   | kmack    |03-SEP-15| Fixed up some RC stuff
-//  1.41   | sglancy  |21-AUG-15| Fixed ODT initialization bug - ODT must be held low through ZQ cal
-//  1.40   | sglancy  |09-JUL-15| Added fixes to ZQ cal bug
-//  1.39   | sglancy  |27-MAY-15| Added fixes to ZQ cal for 3DS DIMMs
-//  1.38   | jdsloat  |01-APL-14| RAS review edits/changes
-//  1.37   | jdsloat  |28-MAR-14| RAS review edits/changes
-//  1.36   | kcook    | 03/12/14| Added check for DDR3 LRDIMM during mss_execut_zq_cal.
-//  1.35   | jdsloat  | 02/21/14| Fixed an inf loop with edit 1.34 and 128GB DIMMs.
-//  1.34   | jdsloat  | 02/20/14| Edited set_end_bit to add a NOP to the end of every CCS execution per CCS defect
-//  1.33   | kcook    | 08/27/13| Removed LRDIMM functions to mss_lrdimm_funcs.C. Use with mss_funcs.H v1.16.
-//  1.32   | kcook    | 08/16/13| Added LRDIMM support. Use with mss_funcs.H v1.15.
-//  1.31   | jdsloat  | 05/20/13| Added ddr_gen determination in address mirror mode function
-//  1.30   | jdsloat  | 04/09/13| Moved Address mirror mode sub function in  from mss_draminit
-//  1.29   | jsabrow  | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern
-//  1.28   | bellows  | 07/16/12|added in Id tag
-//  1.27   | divyakum | 3/22/12 | Fixed warnings from mss_execute_zq_cal function
-//  1.26   | divyakum | 3/22/12 | Fixed mss_execute_zq_cal function variable name mismatch
-//  1.25   | divyakum | 3/21/12 | Added mss_execute_zq_cal function
-//  1.24   | jdsloat  | 3/20/12 | ccs_inst_arry0 bank fields reverse function removed
-//  1.23   | jdsloat  | 3/05/12 | ccs_inst_arry0 address fields reversed - needed to delete commented code out
-//  1.22   | jdsloat  | 2/17/12 | ccs_inst_arry0 address fields reversed
-//  1.21   | jdsloat  | 2/17/12 | FAPI ERRORs uncommented
-//  1.20   | jdsloat  | 2/16/12 | Initialize rc_num
-//  1.19   | 2/14/12  |  jdsloat| MBA translation, elminate unnecesary RC returns, got rid of some port arguments
-//  1.18   | 2/08/12  |  jdsloat| Target to Target&, Added Error reporting
-//  1.17   | 2/02/12  |  jdsloat| Initialized reg_address to 0
-//  1.16   | 1/19/12  |  jdsloat| tabs to 4 spaces - properly, cke fix in mss_ccs_inst_arry_0
-//  1.15   | 1/16/12  |  jdsloat| tabs to 4 spaces
-//  1.14   | 1/13/12  |  jdsloat| Capatilization, curley brackets, "mss_" prefix, adding rc checks, argument prefixes, includes, RC checks
-//  1.13   | 1/6/12   |  jdsloat| Got rid of Globals
-//  1.12   | 12/23/11 | bellows | Printout poll count
-//  1.11   | 12/20/11 | bellows | Fixed up ODT default value of 00 for CCS
-//  1.10   | 12/16/11 | bellows | Bit number correction for ras,cas,wen and cal_type
-//  1.9    | 12/14/11 | bellows | Fixed Bank and Address bit reversals restored others
-//  1.8    | 12/13/11 | jdsloat | Insert from right fix
-//  1.7    | 12/13/11 | jdsloat | Bank Address shift for reserved bit - 3 bits long, invert several fields in CCS0
-//  1.6    | 10/31/11 | jdsloat | CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix
-//  1.5    | 10/18/11 | jdsloat | Debug Messages
-//  1.4    | 10/13/11 | jdsloat | End of CCS array check fix
-//  1.3    | 10/11/11 | jdsloat | Fix CS Lines, dataBuffer.insert functions
-//  1.2    | 10/05/11 | jdsloat | Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE
-//  1.1    | 10/04/11 | jdsloat | First drop of Centaur in FAPI dir
-//---------|----------|---------|-----------------------------------------------
-//  1.7    | 09/29/11 | jdsloat | Functional Changes: port flow, CCS changes, only configed CS, CCS overflow precaution etc.  Compiles.
-//  1.6    | 09/26/11 | jdsloat | Added port information.
-//  1.5    | 09/22/11 | jdsloat | Full update to FAPI.  Functional changes to match procedure.
-//  1.4    | 09/13/11 | jdsloat | First attempt at FAPI upgrade - attributes still in ecmd.
-//  1.1    | 06/27/11 | jdsloat | CCS function update
-//  1.00   | 04/22/11 | jdsloat | First drop of Centaur
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-#include <mss_funcs.H>
-#include <cen_scom_addresses.H>
-using namespace fapi;
-
-ReturnCode mss_ccs_set_end_bit(
-            Target& i_target,
-            uint32_t i_instruction_number
-              )
-{
-    uint32_t rc_num = 0;
-    ReturnCode rc;
-    ecmdDataBufferBase data_buffer(64);
-
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    ecmdDataBufferBase rasn_1(1);
-    ecmdDataBufferBase casn_1(1);
-    ecmdDataBufferBase wen_1(1);
-    ecmdDataBufferBase cke_4(4);
-    ecmdDataBufferBase csn_8(8);
-    ecmdDataBufferBase odt_4(4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    uint32_t l_port_number = 0xFFFFFFFF;
-
-    i_instruction_number = i_instruction_number + 1;
-
-    FAPI_INF( "Setting End Bit on instruction (NOP): %d.", i_instruction_number);
-
-    // Single NOP with CKE raised high and the end bit set high
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | address_16.clearBit(0, 16);
-    rc_num = rc_num | num_idles_16.clearBit(0, 16);
-    rc_num = rc_num | odt_4.clearBit(0,4);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    rc_num = rc_num | cke_4.setBit(0,4);
-    rc_num = rc_num | wen_1.clearBit(0);
-    rc_num = rc_num | casn_1.clearBit(0);
-    rc_num = rc_num | rasn_1.clearBit(0);
-    rc_num = rc_num | ccs_end_1.setBit(0);
-
-    if (rc_num)
-    {
-        FAPI_ERR( "Error setting up buffers");
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-
-    rc = mss_ccs_inst_arry_0( i_target,
-                              i_instruction_number,
-                              address_16,
-                              bank_3,
-                              activate_1,
-                              rasn_1,
-                              casn_1,
-                              wen_1,
-                              cke_4,
-                              csn_8,
-                              odt_4,
-                              ddr_cal_type_4,
-                              l_port_number);
-    if(rc) return rc;
-    rc = mss_ccs_inst_arry_1( i_target,
-                              i_instruction_number,
-                              num_idles_16,
-                              num_repeat_16,
-                              data_20,
-                              read_compare_1,
-                              rank_cal_4,
-                              ddr_cal_enable_1,
-                              ccs_end_1);
-    if(rc) return rc;
-
-    return rc;
-}
-
-
-ReturnCode mss_address_mirror_swizzle(
-            Target& i_target,
-            uint32_t i_port,
-            uint32_t i_dimm,
-            uint32_t i_rank,
-            ecmdDataBufferBase& io_address,
-            ecmdDataBufferBase& io_bank
-              )
-{
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase address_post_swizzle_16(16);
-    ecmdDataBufferBase bank_post_swizzle_3(3);
-    uint16_t mirror_mode_ba = 0;
-    uint16_t mirror_mode_ad  = 0;
-    uint8_t dram_gen = 0;
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
-    if(rc) return rc;
-
-        FAPI_INF( "ADDRESS MIRRORING ON %s PORT%d DIMM%d RANK%d", i_target.toEcmdString(), i_port, i_dimm, i_rank);
-
-        rc_num = rc_num | io_address.extractPreserve(&mirror_mode_ad, 0, 16, 0);
-        FAPI_INF( "PRE - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad);
-        rc_num = rc_num | io_bank.extractPreserve(&mirror_mode_ba, 0, 3, 0);
-        FAPI_INF( "PRE - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba);
-
-        //Initialize address and bank address as the same pre mirror mode swizzle
-        rc_num = rc_num | address_post_swizzle_16.insert(io_address, 0, 16, 0);
-        rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 3, 0);
-
-        if (rc_num)
-        {
-            FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-        if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3)
-        {
-                //Swap A3 and A4
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4);
-
-                //Swap A5 and A6
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6);
-
-                //Swap A7 and A8
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8);
-
-                //Swap BA0 and BA1
-                rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0);
-                rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1);
-
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-        }
-        else if (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-        {
-                //Swap A3 and A4
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 4, 1, 3);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 3, 1, 4);
-
-                //Swap A5 and A6
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 6, 1, 5);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 5, 1, 6);
-
-                //Swap A7 and A8
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 8, 1, 7);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 7, 1, 8);
-
-                //Swap A11 and A13
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 13, 1, 11);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_address, 11, 1, 13);
-
-                //Swap BA0 and BA1
-                rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 1, 1, 0);
-                rc_num = rc_num | bank_post_swizzle_3.insert(io_bank, 0, 1, 1);
-
-                //Swap BG0 and BG1 (BA2 and ADDR 15)
-                rc_num = rc_num | bank_post_swizzle_3.insert(io_address, 2, 1, 15);
-                rc_num = rc_num | address_post_swizzle_16.insert(io_bank, 15, 1, 2);
-
-                if (rc_num)
-                {
-                    FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers");
-                    rc_buff.setEcmdError(rc_num);
-                    return rc_buff;
-                }
-        }
-
-        rc_num = rc_num | address_post_swizzle_16.extractPreserve(&mirror_mode_ad, 0, 16, 0);
-        FAPI_INF( "POST - MIRROR MODE ADDRESS: 0x%04X", mirror_mode_ad);
-        rc_num = rc_num | bank_post_swizzle_3.extractPreserve(&mirror_mode_ba, 0, 3, 0);
-        FAPI_INF( "POST - MIRROR MODE BANK ADDRESS: 0x%04X", mirror_mode_ba);
-
-        //copy address and bank address back to the IO variables
-        rc_num = rc_num | io_address.insert(address_post_swizzle_16, 0, 16, 0);
-        rc_num = rc_num | io_bank.insert(bank_post_swizzle_3, 0, 3, 0);
-
-        if (rc_num)
-        {
-            FAPI_ERR( "mss_address_mirror_swizzle: Error setting up buffers");
-            rc_buff.setEcmdError(rc_num);
-            return rc_buff;
-        }
-
-    return rc;
-}
-
-ReturnCode mss_ccs_inst_arry_0(
-            Target& i_target,
-            uint32_t& io_instruction_number,
-            ecmdDataBufferBase i_address,
-            ecmdDataBufferBase i_bank,
-            ecmdDataBufferBase i_activate,
-            ecmdDataBufferBase i_rasn,
-            ecmdDataBufferBase i_casn,
-            ecmdDataBufferBase i_wen,
-            ecmdDataBufferBase i_cke,
-            ecmdDataBufferBase i_csn,
-            ecmdDataBufferBase i_odt,
-            ecmdDataBufferBase i_ddr_cal_type,
-            uint32_t i_port
-              )
-{
-    //Example Use:
-    //CCS_INST_ARRY_0( i_target, io_instruction_number, i_address, i_bank, i_activate, i_rasn, i_casn, i_wen, i_cke, i_csn, i_odt, i_ddr_cal_type, i_port);
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t reg_address = 0;
-    ecmdDataBufferBase data_buffer(64);
-
-    if ((io_instruction_number >= 30)&&(i_port != 0xFFFFFFFF))
-    {
-        uint32_t num_retry = 10;
-        uint32_t timer = 10;
-        rc = mss_ccs_set_end_bit( i_target, 29);
-        if(rc) return rc;
-        rc = mss_execute_ccs_inst_array( i_target, num_retry, timer);
-        if(rc) return rc;
-        io_instruction_number = 0;
-    }
-
-    if (i_port == 0xFFFFFFFF)
-    {
-        i_port = 0;
-    }
-
-    reg_address = io_instruction_number + CCS_INST_ARRY0_AB_REG0_0x03010615;
-
-    rc_num = rc_num | data_buffer.flushTo0();
-    rc_num = rc_num | data_buffer.insert(i_cke, 24, 4, 0);
-    rc_num = rc_num | data_buffer.insert(i_cke, 28, 4, 0);
-
-    if (i_port == 0)
-    {
-        rc_num = rc_num | data_buffer.insert(i_csn, 32, 8, 0);
-        rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0xFF,40,8);
-        rc_num = rc_num | data_buffer.insert(i_odt, 48, 4, 0);
-        rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0x00,52,4);
-    }
-    else
-    {
-        rc_num = rc_num | data_buffer.insert((uint8_t)0xFF,32,8);
-        rc_num = rc_num | data_buffer.insert(i_csn, 40, 8, 0);
-        rc_num = rc_num | data_buffer.insertFromRight((uint8_t)0x00,48,4);
-        rc_num = rc_num | data_buffer.insert(i_odt, 52, 4, 0);
-    }
-
-    //Placing bits into the data buffer
-    rc_num = rc_num | data_buffer.insert( i_address, 0, 16, 0);
-    rc_num = rc_num | data_buffer.insert( i_bank, 17, 3, 0);
-    rc_num = rc_num | data_buffer.insert( i_activate, 20, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_rasn, 21, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_casn, 22, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_wen, 23, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_ddr_cal_type, 56, 4, 0);
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_ccs_inst_arry_0: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = fapiPutScom(i_target, reg_address, data_buffer);
-
-    return rc;
-}
-
-ReturnCode mss_ccs_inst_arry_1(
-            Target& i_target,
-            uint32_t& io_instruction_number,
-            ecmdDataBufferBase i_num_idles,
-            ecmdDataBufferBase i_num_repeat,
-            ecmdDataBufferBase i_data,
-            ecmdDataBufferBase i_read_compare,
-            ecmdDataBufferBase i_rank_cal,
-            ecmdDataBufferBase i_ddr_cal_enable,
-            ecmdDataBufferBase i_ccs_end
-            )
-{
-
-    //Example Use:
-    //CCS_INST_ARRY_1( i_target, io_instruction_number, i_num_idles, i_num_repeat, i_data, i_read_compare, i_rank_cal, i_ddr_cal_enable, i_ccs_end);
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t reg_address = 0;
-    ecmdDataBufferBase goto_inst(5);
-
-    if ((io_instruction_number >= 30)&&(i_ccs_end.isBitClear(0)))
-    {
-        uint32_t num_retry = 10;
-        uint32_t timer = 10;
-        rc = mss_ccs_set_end_bit( i_target, 29);
-        if(rc) return rc;
-        rc = mss_execute_ccs_inst_array( i_target, num_retry, timer);
-        if(rc) return rc;
-        io_instruction_number = 0;
-    }
-
-    reg_address = io_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635;
-
-    ecmdDataBufferBase data_buffer(64);
-
-    rc_num = rc_num | goto_inst.insertFromRight(io_instruction_number + 1, 0, 5);
-
-    //Setting up a CCS Instruction Array Type 1
-    rc_num = rc_num | data_buffer.insert( i_num_idles, 0, 16, 0);
-    rc_num = rc_num | data_buffer.insert( i_num_repeat, 16, 16, 0);
-    rc_num = rc_num | data_buffer.insert( i_data, 32, 20, 0);
-    rc_num = rc_num | data_buffer.insert( i_read_compare, 52, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_rank_cal, 53, 4, 0);
-    rc_num = rc_num | data_buffer.insert( i_ddr_cal_enable, 57, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_ccs_end, 58, 1, 0);
-    rc_num = rc_num | data_buffer.insert( goto_inst, 59, 5, 0);
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_ccs_inst_arry_1: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = fapiPutScom(i_target, reg_address, data_buffer);
-
-    return rc;
-}
-
-//--------------
-ReturnCode mss_ccs_load_data_pattern(
-            Target& i_target,
-            uint32_t io_instruction_number,
-            mss_ccs_data_pattern data_pattern)
-{
-    //Example Use:
-    //
-    ReturnCode rc;
-
-    if (data_pattern == MSS_CCS_DATA_PATTERN_00)
-      {
-        rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00000000);
-      }
-    else if (data_pattern == MSS_CCS_DATA_PATTERN_0F)
-      {
-        rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x00055555);
-      }
-    else if (data_pattern == MSS_CCS_DATA_PATTERN_F0)
-      {
-        rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000aaaaa);
-      }
-    else if (data_pattern == MSS_CCS_DATA_PATTERN_FF)
-      {
-        rc = mss_ccs_load_data_pattern(i_target, io_instruction_number, 0x000fffff);
-      }
-
-    return rc;
-}
-
-
-ReturnCode mss_ccs_load_data_pattern(
-            Target& i_target,
-            uint32_t io_instruction_number,
-            uint32_t data_pattern)
-{
-    //Example Use:
-    //
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t reg_address = 0;
-
-    if (io_instruction_number > 31)
-    {
-        FAPI_INF("mss_ccs_load_data_pattern: CCS Instruction Array index out of bounds");
-    }
-    else
-    {
-      reg_address = io_instruction_number + CCS_INST_ARRY1_AB_REG0_0x03010635;
-      ecmdDataBufferBase data_buffer(64);
-
-      //read current array1 reg
-      rc = fapiGetScom(i_target, reg_address, data_buffer);
-      if(rc) return rc;
-
-      //modify data bits for specified pattern
-      rc_num = rc_num | data_buffer.insertFromRight(data_pattern, 32, 20);
-      if (rc_num)
-        {
-        FAPI_ERR( "mss_ccs_load_data_pattern: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-        }
-
-      //write array1 back out
-      rc = fapiPutScom(i_target, reg_address, data_buffer);
-      if(rc) return rc;
-    }
-
-    return rc;
-}
-//--------------
-
-
-
-ReturnCode mss_ccs_mode(
-            Target& i_target,
-            ecmdDataBufferBase i_stop_on_err,
-            ecmdDataBufferBase i_ue_disable,
-            ecmdDataBufferBase i_data_sel,
-            ecmdDataBufferBase i_pclk,
-            ecmdDataBufferBase i_nclk,
-            ecmdDataBufferBase i_cal_time_cnt,
-            ecmdDataBufferBase i_resetn,
-            ecmdDataBufferBase i_reset_recover,
-            ecmdDataBufferBase i_copy_spare_cke
-              )
-{
-    ecmdDataBufferBase data_buffer(64);
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-
-
-    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    //Setting up CCS mode
-    rc_num = rc_num | data_buffer.insert( i_stop_on_err, 0, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_ue_disable, 1, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_data_sel, 2, 2, 0);
-    rc_num = rc_num | data_buffer.insert( i_nclk, 4, 2, 0);
-    rc_num = rc_num | data_buffer.insert( i_pclk, 6, 2, 0);
-    rc_num = rc_num | data_buffer.insert( i_cal_time_cnt, 8, 16, 0);
-    rc_num = rc_num | data_buffer.insert( i_resetn, 24, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_reset_recover, 25, 1, 0);
-    rc_num = rc_num | data_buffer.insert( i_copy_spare_cke, 26, 1, 0);
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_ccs_mode: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    return rc;
-}
-
-ReturnCode mss_ccs_start_stop(
-            Target& i_target,
-            bool i_start_stop
-              )
-{
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer(64);
-
-
-    rc = fapiGetScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer);
-    if(rc) return rc;
-
-    if (i_start_stop == MSS_CCS_START)
-    {
-        rc_num = rc_num | data_buffer.setBit(0,1);
-        FAPI_INF(" Executing contents of CCS." );
-    }
-    else if (i_start_stop == MSS_CCS_STOP)
-    {
-        rc_num = rc_num | data_buffer.setBit(1,1);
-        FAPI_INF(" Halting execution of the CCS." );
-    }
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_ccs_start_stop: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = fapiPutScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer);
-
-    return rc;
-}
-
-ReturnCode mss_ccs_status_query( Target& i_target, mss_ccs_status_query_result& io_status)    {
-
-    ecmdDataBufferBase data_buffer(64);
-    ReturnCode rc;
-
-    rc = fapiGetScom(i_target, CCS_STATQ_AB_REG_0x030106A6, data_buffer);
-    if(rc) return rc;
-
-    if (data_buffer.getBit(2))
-    {
-        io_status = MSS_STAT_QUERY_FAIL;
-        return rc;
-    }
-    else if (data_buffer.getBit(0))
-    {
-        io_status = MSS_STAT_QUERY_IN_PROGRESS;
-        return rc;
-    }
-    else if (data_buffer.getBit(1))
-    {
-        io_status = MSS_STAT_QUERY_PASS;
-    }
-    else
-    {
-        FAPI_INF("CCS Status Undetermined.");
-    }
-    return rc;
-}
-
-ReturnCode mss_ccs_fail_type(
-            Target& i_target
-            )
-{
-    ecmdDataBufferBase data_buffer(64);
-    ReturnCode rc;
-
-    rc = fapiGetScom(i_target, CCS_STATQ_AB_REG_0x030106A6, data_buffer);
-    if(rc) return rc;
-
-    if (data_buffer.getBit(3))
-    {
-        //DECONFIG and FFDC INFO
-        const fapi::Target & TARGET_MBA_ERROR = i_target;
-        const ecmdDataBufferBase & REG_CONTENTS = data_buffer;
-
-        FAPI_ERR("CCS returned a FAIL condtion of \"Read Miscompare\" ");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_READ_MISCOMPARE);
-    }
-    else if (data_buffer.getBit(4))
-    {
-        //DECONFIG and FFDC INFO
-        const fapi::Target & TARGET_MBA_ERROR = i_target;
-        const ecmdDataBufferBase & REG_CONTENTS = data_buffer;
-
-        FAPI_ERR("CCS returned a FAIL condition of \"UE or SUE Error\" ");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_UE_SUE);
-    }
-    else if (data_buffer.getBit(5))
-    {
-        //DECONFIG and FFDC INFO
-        const fapi::Target & TARGET_MBA_ERROR = i_target;
-        const ecmdDataBufferBase & REG_CONTENTS = data_buffer;
-
-        FAPI_ERR("CCS returned a FAIL condition of \"Calibration Operation Time Out\" ");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_CAL_TIMEOUT);
-    }
-
-    return rc;
-}
-
-ReturnCode mss_execute_ccs_inst_array(
-        Target& i_target,
-        uint32_t i_num_poll,
-        uint32_t i_wait_timer
-            )
-{
-    enum mss_ccs_status_query_result status = MSS_STAT_QUERY_IN_PROGRESS;
-    uint32_t count = 0;
-    ReturnCode rc;
-
-    rc = mss_ccs_start_stop( i_target, MSS_CCS_START);
-    if(rc) return rc;
-
-    while ((count < i_num_poll) && (status == MSS_STAT_QUERY_IN_PROGRESS))
-    {
-        rc = mss_ccs_status_query( i_target, status);
-        if(rc) return rc;
-        count++;
-        fapiDelay(i_wait_timer, i_wait_timer);
-    }
-
-    FAPI_INF("CCS Executed Polling %d times.", count);
-
-    if (status == MSS_STAT_QUERY_FAIL)
-    {
-        FAPI_ERR("CCS FAILED");
-        rc = mss_ccs_fail_type(i_target);
-        if(rc) return rc;
-        FAPI_ERR("CCS has returned a fail.");
-    }
-    else if (status == MSS_STAT_QUERY_IN_PROGRESS)
-    {
-        FAPI_ERR("CCS Operation Hung");
-        FAPI_ERR("CCS has returned a IN_PROGRESS status and considered Hung.");
-        rc = mss_ccs_fail_type(i_target);
-        if(rc)
-        {
-            return rc;
-        }
-        else
-        {
-            //DECONFIG and FFDC INFO
-            const fapi::Target & TARGET_MBA_ERROR = i_target;
-
-            FAPI_ERR("Returning a CCS HUNG RC Value.");
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_CCS_HUNG);
-            return rc;
-        }
-    }
-    else if (status == MSS_STAT_QUERY_PASS)
-    {
-        FAPI_INF("CCS Executed Successfully.");
-    }
-    else
-    {
-        FAPI_INF("CCS Status Undetermined.");
-    }
-
-    return rc;
-}
-
-uint32_t mss_reverse_32bits(uint32_t i_x)
-{
-    //reversing bit order of a 32 bit uint
-    i_x = (((i_x & 0xaaaaaaaa) >> 1) | ((i_x & 0x55555555) << 1));
-    i_x = (((i_x & 0xcccccccc) >> 2) | ((i_x & 0x33333333) << 2));
-    i_x = (((i_x & 0xf0f0f0f0) >> 4) | ((i_x & 0x0f0f0f0f) << 4));
-    i_x = (((i_x & 0xff00ff00) >> 8) | ((i_x & 0x00ff00ff) << 8));
-    return((i_x >> 16) | (i_x << 16));
-}
-
-uint8_t mss_reverse_8bits(uint8_t i_number){
-
-    //reversing bit order of a 8 bit uint
-    uint8_t temp = 0;
-    for (uint8_t loop = 0; loop < 8; loop++)
-    {
-        uint8_t bit = (i_number&(1<<loop))>>loop;
-        temp |= bit<<(7-loop);
-    }
-    return temp;
-}
-
-
-
-ReturnCode mss_rcd_parity_check(
-            Target& i_target,
-            uint32_t i_port
-            )
-{
-    //checks all ports for a parity error
-    ecmdDataBufferBase data_buffer(64);
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint8_t port_0_error = 0;
-    uint8_t port_1_error = 0;
-    uint8_t rcd_parity_fail = 0;
-
-    rc = fapiGetScom(i_target, MBA01_CALFIR_REG_0x03010402, data_buffer);
-    if(rc) return rc;
-
-    rc_num = rc_num | data_buffer.extract(&port_0_error, 4, 1);
-    rc_num = rc_num | data_buffer.extract(&port_1_error, 7, 1);
-    rc_num = rc_num | data_buffer.extract(&rcd_parity_fail, 5, 1);
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_rcd_parity_check: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    FAPI_INF("Checking for RCD Parity Error.");
-
-    if (rcd_parity_fail)
-    {
-        //DECONFIG and FFDC INFO
-        const fapi::Target & TARGET_MBA_ERROR = i_target;
-
-        FAPI_ERR("Ports 0 and 1 has exceeded a maximum number of RCD Parity Errors.");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_LIMIT);
-    }
-    else if ((port_0_error) && (i_port == 0))
-    {
-        //DECONFIG and FFDC INFO
-        const fapi::Target & TARGET_MBA_ERROR = i_target;
-
-        FAPI_ERR("Port 0 has recorded an RCD Parity Error. ");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT0);
-    }
-    else if ((port_1_error) && (i_port == 1))
-    {
-        //DECONFIG and FFDC INFO
-        const fapi::Target & TARGET_MBA_ERROR = i_target;
-
-        FAPI_ERR("Port 1 has recorded an RCD Parity Error. ");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_RCD_PARITY_ERROR_PORT1);
-    }
-    else
-    {
-        FAPI_INF("No RCD Parity Errors on Port %d.", i_port);
-    }
-
-    return rc;
-}
-
-//ZQ Cal
-ReturnCode mss_execute_zq_cal(
-            Target& i_target,
-            uint8_t i_port
-            )
-{
-    //Enums and Constants
-    enum size
-    {
-       MAX_NUM_DIMM = 2,
-    };
-
-    uint32_t NUM_POLL = 100;
-
-    uint32_t instruction_number = 0;
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-
-    //adds a NOP before ZQ cal
-    ecmdDataBufferBase address_buffer_16(16);
-    rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0000); //Set A10 bit for ZQCal Long
-    ecmdDataBufferBase bank_buffer_8(8);
-    rc_num = rc_num | bank_buffer_8.flushTo0();
-    ecmdDataBufferBase activate_buffer_1(1);
-    rc_num = rc_num | activate_buffer_1.flushTo1();
-    ecmdDataBufferBase rasn_buffer_1(1);
-    rc_num = rc_num | rasn_buffer_1.flushTo1(); //For NOP rasn = 1; casn = 1; wen = 1;
-    ecmdDataBufferBase casn_buffer_1(1);
-    rc_num = rc_num | casn_buffer_1.flushTo1();
-    ecmdDataBufferBase wen_buffer_1(1);
-    rc_num = rc_num | wen_buffer_1.flushTo1();
-    ecmdDataBufferBase cke_buffer_8(8);
-    rc_num = rc_num | cke_buffer_8.flushTo1();
-    ecmdDataBufferBase csn_buffer_8(8);
-    rc_num = rc_num | csn_buffer_8.flushTo1();;
-    ecmdDataBufferBase odt_buffer_8(8);
-    rc_num = rc_num | odt_buffer_8.flushTo0();
-    ecmdDataBufferBase test_buffer_4(4);
-    rc_num = rc_num | test_buffer_4.flushTo0(); // 01XX:External ZQ calibration
-    rc_num = rc_num | test_buffer_4.setBit(1);
-    ecmdDataBufferBase num_idles_buffer_16(16);
-    rc_num = rc_num | num_idles_buffer_16.setHalfWord(0, 0x0400); //1024 for ZQCal
-    ecmdDataBufferBase num_repeat_buffer_16(16);
-    rc_num = rc_num | num_repeat_buffer_16.flushTo0();
-    ecmdDataBufferBase data_buffer_20(20);
-    rc_num = rc_num | data_buffer_20.flushTo0();
-    ecmdDataBufferBase read_compare_buffer_1(1);
-    rc_num = rc_num | read_compare_buffer_1.flushTo0();
-    ecmdDataBufferBase rank_cal_buffer_3(3);
-    rc_num = rc_num | rank_cal_buffer_3.flushTo0();
-    ecmdDataBufferBase ddr_cal_enable_buffer_1(1);
-    rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo0();
-    ecmdDataBufferBase ccs_end_buffer_1(1);
-    rc_num = rc_num | ccs_end_buffer_1.flushTo0();
-
-    ecmdDataBufferBase stop_on_err_buffer_1(1);
-    rc_num = rc_num | stop_on_err_buffer_1.flushTo0();
-    ecmdDataBufferBase resetn_buffer_1(1);
-    rc_num = rc_num | resetn_buffer_1.setBit(0);
-    ecmdDataBufferBase data_buffer_64(64);
-    rc_num = rc_num | data_buffer_64.flushTo0();
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_execute_zq_cal: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-    rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-    rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-    rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-    rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-    rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-    rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
-    if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-
-    instruction_number = 1;
-
-    //now sets up for ZQ CAL
-    rc_num = rc_num | address_buffer_16.setHalfWord(0, 0x0020); //Set A10 bit for ZQCal Long
-    rc_num = rc_num | bank_buffer_8.flushTo0();
-    rc_num = rc_num | activate_buffer_1.flushTo1();
-    rc_num = rc_num | rasn_buffer_1.flushTo1(); //For ZQCal rasn = 1; casn = 1; wen = 0;
-    rc_num = rc_num | casn_buffer_1.flushTo1();
-    rc_num = rc_num | wen_buffer_1.flushTo0();
-    rc_num = rc_num | cke_buffer_8.flushTo1();
-    rc_num = rc_num | odt_buffer_8.flushTo0();
-    rc_num = rc_num | test_buffer_4.flushTo0(); // 01XX:External ZQ calibration
-    rc_num = rc_num | test_buffer_4.setBit(1);
-    rc_num = rc_num | num_idles_buffer_16.setHalfWord(0, 0x0400); //1024 for ZQCal
-    rc_num = rc_num | num_repeat_buffer_16.flushTo0();
-    rc_num = rc_num | data_buffer_20.flushTo0();
-    rc_num = rc_num | read_compare_buffer_1.flushTo0();
-    rc_num = rc_num | rank_cal_buffer_3.flushTo0();
-    rc_num = rc_num | ddr_cal_enable_buffer_1.flushTo0();
-    rc_num = rc_num | ccs_end_buffer_1.flushTo0();
-    rc_num = rc_num | stop_on_err_buffer_1.flushTo0();
-    rc_num = rc_num | resetn_buffer_1.setBit(0);
-    rc_num = rc_num | data_buffer_64.flushTo0();
-
-    if (rc_num)
-    {
-        FAPI_ERR( "mss_execute_zq_cal: Error setting up buffers");
-        rc_buff.setEcmdError(rc_num);
-        return rc_buff;
-    }
-
-
-    uint8_t current_rank = 0;
-    uint8_t start_rank = 0;
-    uint8_t num_master_ranks_array[2][2];
-    uint8_t num_ranks_array[2][2]; //num_ranks_array[port][dimm]
-    uint8_t stack_type[2][2];
-    uint8_t dimm_type;
-    uint8_t lrdimm_rank_mult_mode;
-    uint8_t dram_gen = 0;
-    uint8_t rank_end = 0;
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target, dram_gen);
-    if(rc) return rc;
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target, stack_type);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target, num_master_ranks_array);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, dimm_type);
-    if(rc) return rc;
-
-    //Set up CCS Mode Reg for ZQ cal long and Init cal
-    rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
-    if(rc) return rc;
-
-    rc_num = rc_num | data_buffer_64.insert(stop_on_err_buffer_1, 0, 1, 0);
-    rc_num = rc_num | data_buffer_64.insert(resetn_buffer_1, 24, 1, 0);
-    if(rc_num)
-    {
-        rc.setEcmdError(rc_num);
-        return rc;
-    }
-     rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer_64);
-    if(rc) return rc;
-
-    for(uint8_t dimm = 0; dimm < MAX_NUM_DIMM; dimm++)
-    {
-        start_rank=(4 * dimm);
-
-        if ( (dimm_type == ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) && (dram_gen == ENUM_ATTR_EFF_DRAM_GEN_DDR3) )
-        {
-           rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target, lrdimm_rank_mult_mode);
-           if(rc) return rc;
-
-           if ( num_ranks_array[i_port][dimm] == 8 && lrdimm_rank_mult_mode == 4)
-           { // For LRDIMM 8 Rank, RM=4, CS0 and CS1 to execute ZQ cal
-              rank_end = 2;
-           }
-        }
-        else if(stack_type[i_port][dimm] == ENUM_ATTR_EFF_STACK_TYPE_STACK_3DS) {
-           rank_end = num_master_ranks_array[i_port][dimm];
-        }
-        else {
-           rank_end = num_ranks_array[i_port][dimm];
-        }
-
-        for(current_rank = start_rank; current_rank < start_rank + rank_end; current_rank++) {
-            FAPI_INF( "+++++++++++++++ Sending zqcal to port: %d rank: %d +++++++++++++++", i_port, current_rank);
-            rc_num = rc_num | csn_buffer_8.flushTo1();
-            rc_num = rc_num | csn_buffer_8.clearBit(current_rank);
-            if(rc_num)
-            {
-                rc.setEcmdError(rc_num);
-                return rc;
-            }
-
-            //Issue execute.
-            FAPI_INF( "+++++++++++++++ Execute CCS array on port: %d +++++++++++++++", i_port);
-            rc = mss_ccs_inst_arry_0(i_target, instruction_number, address_buffer_16, bank_buffer_8, activate_buffer_1, rasn_buffer_1, casn_buffer_1, wen_buffer_1, cke_buffer_8, csn_buffer_8, odt_buffer_8, test_buffer_4, i_port);
-            if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-            rc = mss_ccs_inst_arry_1(i_target, instruction_number, num_idles_buffer_16, num_repeat_buffer_16, data_buffer_20, read_compare_buffer_1, rank_cal_buffer_3, ddr_cal_enable_buffer_1, ccs_end_buffer_1);
-            if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-            rc = mss_ccs_set_end_bit(i_target,instruction_number);
-            if(rc) return rc;
-            rc = mss_execute_ccs_inst_array(i_target, NUM_POLL, 60);
-            instruction_number = 1;
-            if(rc) return rc; //Error handling for mss_ccs_inst built into mss_funcs
-        }
-    }
-return rc;
-}
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
deleted file mode 100644
index 2ea52798d..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.H
+++ /dev/null
@@ -1,266 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $                  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_funcs.H,v 1.16 2013/08/27 22:23:53 kcook Exp $
-/* File mss_funcs.H created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_funcs.H
-// *! DESCRIPTION : Tools for centaur procedures
-// *! OWNER NAME :
-// *! BACKUP NAME :
-// #! ADDITIONAL COMMENTS :
-//
-// CCS related and general utility functions.
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.16   | kcook    | 08/27/13| Removed LRDIMM functions to mss_lrdimm_funcs.H. Use with mss_funcs.C v1.33.
-//  1.15   | kcook    | 08/16/13| Added LRDIMM support. Use with mss_funcs.C v1.32.
-//  1.14   | jdsloat  | 04/09/13| Moved Address mirror mode sub function in  from mss_draminit
-//  1.13   | jsabrow  | 11/19/12| added CCS data loader: mss_ccs_load_data_pattern
-//  1.12   | 07/16/12 | bellows | added in Id tag
-//  1.11   | 3/21/12  | divyakum| Added mss_execute_zq_cal function 
-//  1.10   | 2/14/12  | jdsloat | Comment section filled in, elimated unnecessary constant, added enums
-//  1.9    | 2/08/12  | jdsloat | Target to Target&
-//  1.8    | 2/02/12  | jdsloat | Added fapi:: to arguments in function prototypes
-//  1.7    | 1/13/12  | jdsloat | Capatilization, cleaned up includes, address names, "mss_" prefix, argument prefix
-//  1.6    | 1/6/12   | jdsloat | Added a function call
-//  1.5    | 1/5/12   | jdsloat | Got rid of Globals
-//  1.4    | 10/31/11 | jdsloat | CCS Update - goto_inst now assumed to be +1, CCS_fail fix, CCS_status fix
-//  1.3    | 10/06/11 | jdsloat | argument data type fix
-//  1.2    | 10/05/11 | jdsloat | Convert integers to ecmdDataBufferBase in CCS_INST_1, CCS_INST_2, CCS_MODE
-//  1.1    | 10/04/11 | jdsloat | First drop of Centaur in FAPI dir
-//---------|----------|---------|-----------------------------------------------
-//  1.6    | 09/29/11 | jdsloat | global CCS counts, port added to calls, temp dimms defined as #
-//  1.5    | 09/27/11 | jdsloat | Added port information.
-//  1.4    | 09/22/11 | jdsloat | Full update to FAPI.  Functional changes to match procedure.
-//  1.3    | 09/13/11 | jdsloat | First attempt at FAPI upgrade - attributes still in ecmd
-//  1.00   | 04/22/11 | jdsloat | First drop of Centaur
-
-#ifndef _MSS_FUNCS_H
-#define _MSS_FUNCS_H
-
-//----------------------------------------------------------------------
-//  Constants for CCS Operations
-//----------------------------------------------------------------------
-const uint64_t CCS_INST_ARRY0_AB_REG0_0x03010615 = 0x03010615;
-const uint64_t CCS_INST_ARRY1_AB_REG0_0x03010635 = 0x03010635;
-
-const uint64_t CCS_CNTLQ_AB_REG_0x030106A5 =   0x030106A5;
-const uint64_t CCS_MODEQ_AB_REG_0x030106A7 =   0x030106A7;
-const uint64_t CCS_STATQ_AB_REG_0x030106A6 =   0x030106A6;
-const uint64_t MBA01_CALFIR_REG_0x03010402 =   0x03010402;
-
-
-//----------------------------------------------------------------------
-//  Enums for CCS Operations
-//----------------------------------------------------------------------
-
-enum mss_ccs_status_query_result
-{
-    MSS_STAT_QUERY_PASS = 1,
-    MSS_STAT_QUERY_IN_PROGRESS = 2,
-    MSS_STAT_QUERY_FAIL = 3
-};
-
-
-enum mss_ccs_data_pattern
-{
-    MSS_CCS_DATA_PATTERN_00 = 1,
-    MSS_CCS_DATA_PATTERN_0F = 2,
-    MSS_CCS_DATA_PATTERN_F0 = 3,
-    MSS_CCS_DATA_PATTERN_FF = 4
-};
-
-
-const bool MSS_CCS_START = 0;
-const bool MSS_CCS_STOP = 1;
-
-
-//----------------------------------------------------------------------
-//  CCS FUNCS
-//----------------------------------------------------------------------
-
-//--------------------------------------------------------------
-// mss_ccs_inst_arry_0
-// Adding information to the CCS - 0 instruction array by index
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_ccs_inst_arry_0( fapi::Target& i_target,
-                                      uint32_t& io_instruction_number,
-                                      ecmdDataBufferBase i_address,
-                                      ecmdDataBufferBase i_bank,
-                                      ecmdDataBufferBase i_activate,
-                                      ecmdDataBufferBase i_rasn,
-                                      ecmdDataBufferBase i_casn,
-                                      ecmdDataBufferBase i_wen,
-                                      ecmdDataBufferBase i_cke,
-                                      ecmdDataBufferBase i_csn,
-                                      ecmdDataBufferBase i_odt,
-                                      ecmdDataBufferBase i_ddr_cal_type,
-                                      uint32_t i_port);
-
-//--------------------------------------------------------------
-// mss_ccs_inst_arry_1
-// Adding information to the CCS - 1 instruction array by index
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_ccs_inst_arry_1( fapi::Target& i_target,
-                                      uint32_t& io_instruction_number,
-                                      ecmdDataBufferBase i_num_idles,
-                                      ecmdDataBufferBase i_num_repeat,
-                                      ecmdDataBufferBase i_data,
-                                      ecmdDataBufferBase i_read_compare,
-                                      ecmdDataBufferBase i_rank_cal,
-                                      ecmdDataBufferBase i_ddr_cal_enable,
-                                      ecmdDataBufferBase i_ccs_end);
-
-
-//---------------------------------------------------------------
-// mss_ccs_load_data_pattern
-// load predefined pattern (enum) into specified array1 index
-// Target = centaur.mba
-//---------------------------------------------------------------
-fapi::ReturnCode mss_ccs_load_data_pattern( fapi::Target& i_target,
-					    uint32_t io_instruction_number,
-                                            mss_ccs_data_pattern data_pattern);
-
-
-//---------------------------------------------------------------
-// mss_ccs_load_data_pattern
-// load specified pattern (20 bits) into specified array1 index
-// Target = centaur.mba
-//---------------------------------------------------------------
-fapi::ReturnCode mss_ccs_load_data_pattern( fapi::Target& i_target,
-					    uint32_t io_instruction_number,
-                                            uint32_t data_pattern);
-
-
-//-----------------------------------------
-// mss_ccs_status_query
-// Querying the status of the CCS
-// Target = centaur.mba
-//-----------------------------------------
-fapi::ReturnCode mss_ccs_status_query( fapi::Target& i_target,
-                                       mss_ccs_status_query_result& io_status);
-
-
-//-----------------------------------------
-// mss_ccs_start_stop
-// Issuing a start or stop of the CCS
-// Target = centaur.mba
-//-----------------------------------------
-fapi::ReturnCode mss_ccs_start_stop( fapi::Target& i_target,
-                                     uint32_t i_start_stop);
-
-//----------------------------------------------
-// mss_ccs_mode
-// Adding info the the Mode Register of the CCS
-// Target = centaur.mba
-//----------------------------------------------
-fapi::ReturnCode mss_ccs_mode( fapi::Target& i_target,
-                               ecmdDataBufferBase i_stop_on_err,
-                               ecmdDataBufferBase i_ue_disable,
-                               ecmdDataBufferBase i_data_sel,
-                               ecmdDataBufferBase i_pclk,
-                               ecmdDataBufferBase i_nclk,
-                               ecmdDataBufferBase i_cal_time_cnt,
-                               ecmdDataBufferBase i_resetn,
-                               ecmdDataBufferBase i_reset_recover,
-                               ecmdDataBufferBase i_copy_spare_cke);
-
-//-----------------------------------------
-// mss_ccs_fail_type
-// Extracting the type of ccs fail
-// Target = centaur.mba
-//-----------------------------------------
-fapi::ReturnCode mss_ccs_fail_type( fapi::Target& i_target);
-
-
-//-----------------------------------
-// mss_execute_ccs_inst_array
-// Execute the CCS intruction array
-// Target = centaur.mba
-//-----------------------------------
-fapi::ReturnCode mss_execute_ccs_inst_array( fapi::Target& i_target,
-                                             uint32_t i_num_poll,
-                                             uint32_t i_wait_timer);
-
-//-------------------------------------------
-// mss_ccs_set_end_bit
-// Setting the End location of the CCS array
-// Target = centaur.mba
-//-------------------------------------------
-fapi::ReturnCode mss_ccs_set_end_bit( fapi::Target& i_target,
-                                      uint32_t i_instruction_number);
-
-//--------------------------------------------------------
-// mss_rcd_parity_check
-// Checking the Parity Error Bits associated with the RCD
-// Target = centaur.mba
-//--------------------------------------------------------
-fapi::ReturnCode mss_rcd_parity_check(fapi::Target& i_target,
-                                      uint32_t i_port);
-
-//-----------------------------------------
-// mss_reverse_32bits, mss_reverse_8bits
-// Reversing bit order of 8 or 32 bit uint
-//-----------------------------------------
-uint32_t mss_reverse_32bits( uint32_t i_x);
-uint8_t mss_reverse_8bits(uint8_t i_number);
-
-
-//-----------------------------------------
-// mss_execute_zq_cal
-// execute init ZQ Cal on given target and port
-// Target = centaur.mba
-//-----------------------------------------
-fapi::ReturnCode mss_execute_zq_cal(fapi::Target& i_target, 
-                                    uint8_t i_port);
-
-
-//-----------------------------------------
-// mss_address_mirror_swizzle
-// swizzle the address bus and bank address bus for address mirror mode
-// Target = centaur.mba
-//-----------------------------------------
-fapi::ReturnCode mss_address_mirror_swizzle(fapi::Target& i_target,
-            				    uint32_t i_port,
-	    				    uint32_t i_dimm,
-	    				    uint32_t i_rank,
-            				    ecmdDataBufferBase& io_address,
-            				    ecmdDataBufferBase& io_bank);
-
-#endif /* _MSS_FUNCS_H */
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H
deleted file mode 100644
index 8025af461..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H
+++ /dev/null
@@ -1,218 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_ddr4_funcs.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_lrdimm_ddr4_funcs.H,v 1.1 2014/03/14 16:05:51 kcook Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_lrdimm_funcs.H
-// *! DESCRIPTION : Tools for lrdimm centaur procedures
-// *! OWNER NAME : KCOOK
-// *! BACKUP NAME : MWUU
-// #! ADDITIONAL COMMENTS :
-//
-// CCS related and general utility functions.
-// Provides functions for mss_eff_conifg, mss_draminit, and mss_draminit_training
-// for DDR4 LRDIMM.
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.1    | 03/14/14 | kcook   | First drop of Centaur
-
-#ifndef _MSS_LRDIMM_DDR4_FUNCS_H
-#define _MSS_LRDIMM_DDR4_FUNCS_H
-
-//#define LRDIMM 1
-
-//----------------------------------------------------------------------
-//  Constants 
-//----------------------------------------------------------------------
-const uint64_t MAINT0_MBA_MAINT_BUFF0_DATA_ECC0_0x0301065d = 0x0301065d;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_0_0x800000010301183F = 0x800000010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_1_0x800004010301183F = 0x800004010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_2_0x800008010301183F = 0x800008010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_3_0x80000C010301183F = 0x80000C010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P0_4_0x800010010301183F = 0x800010010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_0_0x800100010301183F = 0x800100010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_1_0x800104010301183F = 0x800104010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_2_0x800108010301183F = 0x800108010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_3_0x80010C010301183F = 0x80010C010301183Full;
-const uint64_t DPHY23_DDRPHY_DP18_DATA_BIT_ENABLE1_P1_4_0x800110010301183F = 0x800110010301183Full;
-//----------------------------------------------------------------------
-//  Enums 
-//----------------------------------------------------------------------
-//----------------------------------------------------------------------
-// LRDIMM FUNCS
-//----------------------------------------------------------------------
-//--------------------------------------------------------------
-// mss_create_db_ddr4  
-// Determines DB control words and stores in attribute
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_create_db_ddr4( const fapi::Target& i_target_mba);
-
-//--------------------------------------------------------------
-// mss_lrdimm_ddr4_term_atts  
-// eff config termination rewrite odts 
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_ddr4_term_atts( const fapi::Target& i_target_mba);
-
-//--------------------------------------------------------------
-// mss_lrdimm_ddr4_db_load  
-// Writes initial  DB control words to DB from attributes
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_ddr4_db_load( fapi::Target& i_target, 
-                                          uint32_t i_port_number, 
-                                          uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// mss_bcw_write 
-// Writes single BCW to DB
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_bcw_write( fapi::Target& i_target_mba, uint32_t i_port_number,
-                         uint8_t bcw_width, uint8_t bcw, uint8_t bcw_value,
-                         uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// mss_dram_write_leveling
-// Executes DB-DRAM write leveing
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_dram_write_leveling( fapi::Target& i_target_mba, uint32_t i_port_number);
-
-//--------------------------------------------------------------
-// mss_store_db_delay
-// Used at end of training steps to write found delay values to DB control word registers
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_store_db_delay(fapi::Target& i_target_mba, uint8_t i_mbaPosition, uint32_t i_port_number,
-                                    uint32_t i_dimm_number, uint32_t i_rank_number,
-                                    uint8_t i_cw_reg, uint8_t i_nibble_delay[],
-                                    uint32_t& io_ccs_inst_cnt, uint8_t i_split_fine=0);
-//--------------------------------------------------------------
-// mss_step_delay_cw0
-// Used in mxd training to step DB CW  delay register and query data bus
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_step_delay_cw0(fapi::Target& i_target_mba, uint8_t i_port_number, uint8_t i_dimm_number, uint8_t i_rank_number,
-		uint8_t i_num_wr_rd, uint8_t o_nibble_delay[], uint8_t i_type, uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// mss_step_delay_cw
-// Used in dram_write_leveling and mrep_training to step DB CW delay registers and query data bus
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_step_delay_cw(fapi::Target& i_target_mba, uint32_t i_port_number, uint32_t i_dimm_number, uint32_t i_rank_number,
-                                   uint8_t i_cw_reg, uint8_t i_num_reads, uint8_t o_nibble_delay[],
-                                   uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// mss_mr1_wr_lvl  
-// Send MR1 command to set DRAM to write leveling mode or normal mode
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_mr1_wr_lvl(fapi::Target& i_target_mba, uint32_t i_port_number,
-                                uint8_t wr_lvl, uint32_t& io_ccs_inst_cnt);
-
-
-
-//--------------------------------------------------------------
-// mss_mrep_training
-// Conducts MDQ Receive Enable Phase Training between DB and DRAM
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_mrep_training( fapi::Target& i_target_mba, uint32_t i_port_number);
-//--------------------------------------------------------------
-// mss_mxd_training
-// Conducts MRD or MWD coarse, normal, or find training. Still in development
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_mxd_training( fapi::Target& i_target_mba, uint8_t i_port_number, uint8_t i_type);
-//--------------------------------------------------------------
-// mss_add_rdmpr 
-// Adds read command without activate to ccs
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_add_rdmpr( fapi::Target& i_target_mba, 
-                               uint32_t i_port_number, uint32_t dimm_number, uint32_t rank_number,
-                               uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// mss_mpr_operation
-// Sets MR3 command to MPR data flow or normal data flow
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_mpr_operation( fapi::Target& i_target_mba, uint32_t i_port_number,
-                             uint8_t mpr_op,
-                         uint32_t& io_ccs_inst_cnt);
-
-//--------------------------------------------------------------
-// mss_force_fifo_capture
-// Sets force_fifo_capture bit in rd_dia_config5 registers to Force DQ capture or normal operation
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_force_fifo_capture(fapi::Target& i_target_centaur, uint8_t i_mbaPosition, 
-                                        uint32_t i_port_number,
-                            uint32_t force_fifo);
-
-//--------------------------------------------------------------
-// mss_data_bit_set
-// Sets single DQ byte or all DQ bytes to 0 or 1 through DATA_BIT_DIR registers. 
-// Used with DFT_FORCE_OUTPUT during PBA mode
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_data_bit_set(fapi::Target& i_target_mba, uint8_t i_mbaPosition, 
-                                        uint32_t i_port_number,
-                            uint8_t byte, uint8_t dq_value);
-
-//--------------------------------------------------------------
-// mss_dft_force_outputs
-// Sets DFT_FORCE_OUTPUTS bit to 0 or 1 to control DQ bus during PBA mode
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_dft_force_outputs(fapi::Target& i_target_centaur, uint8_t i_mbaPosition, 
-                                        uint32_t i_port_number,
-                            uint32_t force_outputs);
-
-//--------------------------------------------------------------
-
-
-
-
-
-
-
-
-#endif /* _MSS_LRDIMM_DDR4_FUNCS_H */
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C
deleted file mode 100644
index 499b1e867..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C
+++ /dev/null
@@ -1,1995 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_lrdimm_funcs.C,v 1.10 2015/03/16 21:37:44 jdsloat Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_lrdimm_funcs.C
-// *! DESCRIPTION : Tools for LRDIMM centaur procedures
-// *! OWNER NAME : kcook@us.ibm.com
-// *! BACKUP NAME : mwuu@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.10   | jdsloat  |16-MAR-15| Fixed 2 declarations of ecmddatabuffer to ecmddatabufferbase
-//  1.8    | kcook    |13-FEB-14| More FW updates.
-//  1.7    | kcook    |12-FEB-14| Updated HWP_ERROR per RAS review to be used with memory_mss_lrdimm_funcs.xml
-//  1.6    | bellows  |02-JAN-14| VPD attribute removal
-//  1.5    | kcook    |12/03/13 | Updated VPD attributes. 
-//  1.4    | bellows  |09/16/13 | Hostboot compile update
-//  1.3    | bellows  |09/16/13 | Added ID tag.
-//  1.2    | kcook    |09/13/13 | Updated define FAPI_LRDIMM token.
-//  1.1    | kcook    |08/27/13 | First drop of Centaur
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-#include <mss_lrdimm_funcs.H>
-#include <mss_funcs.H>
-
-#ifdef FAPI_LRDIMM
-const uint8_t MAX_NUM_DIMMS = 2;
-const uint8_t MAX_NUM_LR_RANKS = 8;
-const uint8_t MRS1_BA = 1;
-const uint8_t PORT_SIZE = 2;
-const uint8_t DIMM_SIZE = 2;
-const uint8_t RANK_SIZE = 4;
-const uint32_t MSS_EFF_VALID = 255;
-
-
-using namespace fapi;
-
-fapi::ReturnCode mss_lrdimm_rcd_load( fapi::Target& i_target, uint32_t port_number, uint32_t& ccs_inst_cnt)
-{
-    ReturnCode rc;
-    uint8_t num_drops_per_port;
-    // LRDIMM
-    uint8_t func1_rcd_number_array_u8[12] = {7,0,1,2,8,9,10,11,12,13,14,15};
-    uint8_t func2_rcd_number_array_u8[8] = {7,0,1,2,3,4,5,6};
-    uint8_t func3_rcd_number_array_u8[7] = {7,0,1,2,6,8,9};
-    uint8_t funcODT_rcd_number_array_u8[3] = {7,10,11};
-    uint8_t *p_func_num_arr;
-    ecmdDataBufferBase data_buff_rcd_word(64);
-    uint64_t func_rcd_control_word[2];
-    uint8_t num_ranks_array[2][2]; //[port][dimm]
-    uint8_t dimm_number;
-    uint8_t rank_number;
-    uint64_t spd_func_words;
-    uint64_t att_spd_func_words[2][2];
-    uint8_t num_rows;
-    uint8_t num_cols;
-    uint8_t dram_width;
-    uint64_t l_func1_mask = 0x00000000F00FFFFFLL;
-    uint8_t l_rcd_cntl_word_0;
-    uint8_t l_rcd_cntl_word_1;
-    uint8_t l_rcd_cntl_word_2;
-    uint8_t l_rcd_cntl_word_3;
-    uint8_t l_rcd_cntl_word_4;
-    uint8_t l_rcd_cntl_word_5;
-    uint8_t l_rcd_cntl_word_6;
-    uint8_t l_rcd_cntl_word_7;
-    uint8_t l_rcd_cntl_word_8;
-    uint8_t l_rcd_cntl_word_9;
-    uint8_t l_rcd_cntl_word_10;
-    uint8_t l_rcd_cntl_word_11;
-    uint8_t dimm_func_vec;
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target, att_spd_func_words);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_ROWS, &i_target, num_rows);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_COLS, &i_target, num_cols);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, dram_width);
-    if (rc) return rc;
-    rc=FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target, dimm_func_vec);
-    if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, num_drops_per_port);
-    if(rc) return rc;
-
-
-    // Fucntion 1
-    for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-
-       if ( num_ranks_array[port_number][dimm_number] != 0 )
-       {
-          //F[1]RC0 IBT settings for DCS pins
-          l_rcd_cntl_word_0 = 0; // IBT DCS[1:0] 100 Ohm,  DCS[3:2] IBT as defined DCS[1:0]
-          l_rcd_cntl_word_1 = 0; //IBT DCKE 100 Ohm
-          l_rcd_cntl_word_2 = 0; //IBT DODT[1:0] 100 Ohm
-
-          l_rcd_cntl_word_7 = 1; //Function select
-          l_rcd_cntl_word_9 = 0; //Refresh stagger = 0clocks
-          l_rcd_cntl_word_10 = 0; //Refresh stagger limit = unimited
-
-          data_buff_rcd_word.clearBit(0,64);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_0, 0,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_1, 4,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_2, 8,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_9, 36,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_10, 40,4);
-
-          func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-          if(rc) return rc;
-          spd_func_words = att_spd_func_words[port_number][dimm_number] & l_func1_mask; // SPD for F[1]RC8,11-15
-          func_rcd_control_word[dimm_number] = func_rcd_control_word[dimm_number] | spd_func_words;
-       }
-    }
-
-    FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-    p_func_num_arr = func1_rcd_number_array_u8;
-    rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr,
-                           sizeof(func1_rcd_number_array_u8)/sizeof(func1_rcd_number_array_u8[0]),
-                           func_rcd_control_word , ccs_inst_cnt,1);
-    if(rc)
-    {
-       FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-       return rc;
-    }
-
-    // Function 2
-    for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-       if ( num_ranks_array[port_number][dimm_number] != 0 )
-       {
-          l_rcd_cntl_word_0 = 0; // Transparent mode
-          l_rcd_cntl_word_1 = 0; // Reset control
-          l_rcd_cntl_word_2 = 0; // SMBus access control
-          l_rcd_cntl_word_3 = 8; // Training control & Errorout enable driven Low when Training
-          l_rcd_cntl_word_4 = 0; // MEMBIST Rank control
-
-          //RC5 DRAM row & column addressing
-          if ( num_rows == 13 )
-          {
-             if ( num_cols == 10 )
-             {
-                l_rcd_cntl_word_5 = 0;
-             }
-             else if ( num_cols == 11 )
-             {
-                l_rcd_cntl_word_5 = 1;
-             }
-             else if ( num_cols == 12 )
-             {
-                l_rcd_cntl_word_5 = 2;
-             }
-             else if ( num_cols == 3 )
-             {
-                l_rcd_cntl_word_5 = 3;
-             }
-          }
-          else if ( num_rows == 14 )
-          {
-             if ( num_cols == 10 )
-             {
-                l_rcd_cntl_word_5 = 4;
-             }
-             else if ( num_cols == 11 )
-             {
-                l_rcd_cntl_word_5 = 5;
-             }
-             else if ( num_cols == 12 )
-             {
-                l_rcd_cntl_word_5 = 6;
-             }
-             else if ( num_cols == 3 )
-             {
-                l_rcd_cntl_word_5 = 7;
-             }
-          }
-          else if ( num_rows == 15 )
-          {
-             if ( num_cols == 10 )
-             {
-                l_rcd_cntl_word_5 = 8;
-             }
-             else if ( num_cols == 11 )
-             {
-                l_rcd_cntl_word_5 = 9;
-             }
-             else if ( num_cols == 12 )
-             {
-                l_rcd_cntl_word_5 = 10;
-             }
-             else if ( num_cols == 3 )
-             {
-                l_rcd_cntl_word_5 = 11;
-             }
-          }
-          else if ( num_rows == 16 )
-          {
-             if ( num_cols == 10 )
-             {
-                l_rcd_cntl_word_5 = 12;
-             }
-             else if ( num_cols == 11 )
-             {
-                l_rcd_cntl_word_5 = 13;
-             }
-             else if ( num_cols == 12 )
-             {
-                l_rcd_cntl_word_5 = 14;
-             }
-             else if ( num_cols == 3 )
-             {
-                l_rcd_cntl_word_5 = 15;
-             }
-          }
-
-          l_rcd_cntl_word_6 = 0; // MEMBIST control
-          l_rcd_cntl_word_7 = 2; //Function select
-
-          data_buff_rcd_word.clearBit(0,64);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_0, 0,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_1, 4,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_2, 8,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_3,12,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_4,16,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_5,20,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_6,24,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);
-
-          func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-        
-          //check for rc but not seeing where rc is set in this loop/if statment
-          if(rc) return rc;
-       }
-    }
-
-
-    FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-    p_func_num_arr = func2_rcd_number_array_u8;
-    rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr,
-                           sizeof(func2_rcd_number_array_u8)/sizeof(func2_rcd_number_array_u8[0]),
-                           func_rcd_control_word , ccs_inst_cnt,1);
-    if(rc)
-    {
-       FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-       return rc;
-    }
-
-    // Function 3
-    for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-       if ( num_ranks_array[port_number][dimm_number] != 0 )
-       {
-          data_buff_rcd_word.setDoubleWord(0, att_spd_func_words[port_number][dimm_number]);
-          data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_8 , 40, 4); // f[3]RC8 is in space RCD10
-          data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_9 , 36, 4);
-
-          //F[3]RC0 connector interface DQ RTT_Nom Termination, TDQS control
-          if ( num_drops_per_port == ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL )
-          { // Single rank, dual drop
-             if ( dram_width == 8 )
-             {
-                l_rcd_cntl_word_0 = 9; // RTT_Nom 60 Ohm, TDQS enabled
-             }
-             else
-             {
-                l_rcd_cntl_word_0 = 1; // RTT_NOM 60 Ohm, TDQS disabled
-             }
-          }
-          else
-          { // Single rank, Single drop
-             if ( dram_width == 8 )
-             {
-                l_rcd_cntl_word_0 = 9; // RTT_Nom 60 Ohm, TDQS enabled
-             }
-             else
-             {
-                l_rcd_cntl_word_0 = 1; // RTT_NOM 60 Ohm, TDQS disabled
-             }
-          }
-
-          //F[3]RC1 connector interface DQ RTT_WR termination & Reference voltage
-          if ( num_drops_per_port == ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL )
-          { // Single rank, dual drop
-             l_rcd_cntl_word_1 = 2; // RTT_WR 120 Ohm , VrefDQ input pin
-             l_rcd_cntl_word_2 = 1; // Connecter interface DQ/DQS output driver imp 34 Ohm, DQ/DQS drivers enabled
-          }
-          else
-          { // Single rank, Single drop
-             l_rcd_cntl_word_1 = 0; // RTT_WR disabled, VrefDQ input pin
-             l_rcd_cntl_word_2 = 1; // Connecter interface DQ/DQS output driver imp 34 Ohm, DQ/DQS drivers enabled
-          }
-
-          FAPI_INF("Using ATTR_EFF_SCHMOO_TEST_VALID for dq LRDIMM timing mode");
-          rc=FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_rcd_cntl_word_6);
-
-          l_rcd_cntl_word_7 = 3; //Function select
-
-          data_buff_rcd_word.clearBit(0,64);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_0, 0,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_1, 4,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_2, 8,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_6,24,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_8,32,4);
-          data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_9, 36,4);
-
-          func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-          //why check rc here and not at the FAPI_ATTR_GET line
-          if(rc) return rc;
-       }
-    }
-
-    FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-    p_func_num_arr = func3_rcd_number_array_u8;
-    rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr,
-                           sizeof(func3_rcd_number_array_u8)/sizeof(func3_rcd_number_array_u8[0]),
-                           func_rcd_control_word , ccs_inst_cnt,1);
-    if(rc)
-    {
-       FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-       return rc;
-    }
-
-    for ( rank_number = 0; rank_number < MAX_NUM_LR_RANKS; rank_number++ )
-    {
-       for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++)
-       {
-          if ( num_ranks_array[port_number][dimm_number] != 0 )
-          {
-             data_buff_rcd_word.setDoubleWord(0, att_spd_func_words[port_number][dimm_number]);
-             data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_10 , rank_number/2*8, 4);   // RC10 is in space RCD0/2/4/6
-             data_buff_rcd_word.extractToRight(&l_rcd_cntl_word_11 , rank_number/2*8+4, 4); // RC11 is in space RCD1/3/5/7
-
-             l_rcd_cntl_word_7 = rank_number + 3; // Function word select 3:10 for Ranks 0-7
-
-             data_buff_rcd_word.clearBit(0,64);
-             data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);
-             data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_10,40,4);
-             data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_11,44,4);
-
-             func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-             //not sure why the rc check is here since there are no rc calls
-             if(rc) return rc;
-          }
-       }
-
-       FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-       p_func_num_arr = funcODT_rcd_number_array_u8;
-       rc = mss_spec_rcd_load(i_target, port_number, p_func_num_arr,
-                              sizeof(funcODT_rcd_number_array_u8)/sizeof(funcODT_rcd_number_array_u8[0]),
-                              func_rcd_control_word , ccs_inst_cnt,1);
-       if(rc)
-       {
-          FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-          return rc;
-       }
-    } // end rank loop
-
-    // Function 13
-    l_rcd_cntl_word_7 = 13;
-    FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-
-    uint8_t Rx_MR1_2_DATA[2][2];
-    rc=FAPI_ATTR_GET(ATTR_LRDIMM_MR12_REG, &i_target, Rx_MR1_2_DATA);
-    if(rc) return rc;
-
-    uint8_t rcw = 7;
-    uint64_t rcd0_15[2] = { 0x0000000D00000000ll,           // select FN 13  dimm0
-                            0x0000000D00000000ll };         //     "         dimm1
-
-    // set FN 13 via RC 7
-    rc = mss_spec_rcd_load( i_target, port_number, &rcw, 1, rcd0_15, ccs_inst_cnt,1);
-    if(rc)
-    {
-       FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)",
-       uint32_t(rc), rc.getCreator());
-       return rc;
-    }
-
-    uint8_t func13_rcd_number_array_size = 4;
-    uint8_t func13_rcd_number_array_u8[4] = { 10, 11, 14, 15 };
-    p_func_num_arr = func13_rcd_number_array_u8;
-
-    data_buff_rcd_word.clearBit(0,64);
-    data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);  // select F13
-
-    const uint8_t num_ecw = 11;          // number of external funcs
-    uint8_t R2_7_MR1_2_DATA[2][2];
-    R2_7_MR1_2_DATA[port_number][0] = Rx_MR1_2_DATA[port_number][0] & 0xE3; // disable RTT_NOM on ranks 2:7
-    R2_7_MR1_2_DATA[port_number][1] = Rx_MR1_2_DATA[port_number][1] & 0xE3; // disable RTT_NOM on ranks 2:7
-
-
-         // extended control word                        addr, data
-    uint8_t   ext_funcs[MAX_NUM_DIMMS][num_ecw][2] = {
-                                                      {
-                                                       {0xAC, 0x00},      // MRS_CTRL = 0xAC;     snoop/forward/store
-                                                                          // MRx_SNOOP = 0xC8-CF  MR(0:3) MR to DRAM      0xC8/C9-CE/CF
-                                                       {0xC8, 0x00},      // MR0_SNOOP(0:7)  = 0xC8       MR0 to DRAM
-                                                       {0xC9, 0x00},      // MR0_SNOOP(8:15) = 0xC9;      MR0 to DRAM
-                                                                          // Rx_MR1_2 = 0xB8-BF;  R(0:7) ranks, RTT_WR, RTT_NOM, D_IMP
-                                                       {0xB8, Rx_MR1_2_DATA[port_number][0]},   // rank 0
-                                                       {0xB9, Rx_MR1_2_DATA[port_number][0]},   // rank 1
-                                                       {0xBA, R2_7_MR1_2_DATA[port_number][0]}, // rank 2
-                                                       {0xBB, R2_7_MR1_2_DATA[port_number][0]}, // rank 3
-                                                       {0xBC, R2_7_MR1_2_DATA[port_number][0]}, // rank 4
-                                                       {0xBD, R2_7_MR1_2_DATA[port_number][0]}, // rank 5
-                                                       {0xBE, R2_7_MR1_2_DATA[port_number][0]}, // rank 6
-                                                       {0xBF, R2_7_MR1_2_DATA[port_number][0]}  // rank 7
-                                                      },
-                                                      {
-                                                       {0xAC, 0x00},      // MRS_CTRL = 0xAC;     snoop/forward/store
-                                                                          // MRx_SNOOP = 0xC8-CF  MR(0:3) MR to DRAM      0xC8/C9-CE/CF
-                                                       {0xC8, 0x00},      // MR0_SNOOP(0:7)  = 0xC8       MR0 to DRAM
-                                                       {0xC9, 0x00},      // MR0_SNOOP(8:15) = 0xC9;      MR0 to DRAM
-                                                                          // Rx_MR1_2 = 0xB8-BF;  R(0:7) ranks, RTT_WR, RTT_NOM, D_IMP
-                                                       {0xB8, Rx_MR1_2_DATA[port_number][1]},   // rank 0
-                                                       {0xB9, Rx_MR1_2_DATA[port_number][1]},   // rank 1
-                                                       {0xBA, R2_7_MR1_2_DATA[port_number][1]}, // rank 2
-                                                       {0xBB, R2_7_MR1_2_DATA[port_number][1]}, // rank 3
-                                                       {0xBC, R2_7_MR1_2_DATA[port_number][1]}, // rank 4
-                                                       {0xBD, R2_7_MR1_2_DATA[port_number][1]}, // rank 5
-                                                       {0xBE, R2_7_MR1_2_DATA[port_number][1]}, // rank 6
-                                                       {0xBF, R2_7_MR1_2_DATA[port_number][1]}  // rank 7
-                                                      }
-                                                     };
-    for (uint8_t i=0; i < num_ecw; i++)
-    {
-       // set func_rcd_control_word[dimm_number]
-       for (dimm_number = 0;dimm_number < MAX_NUM_DIMMS; dimm_number++)
-       {
-          if ( num_ranks_array[port_number][dimm_number] != 0 )
-          {
-             // load address
-             data_buff_rcd_word.insertFromRight(ext_funcs[dimm_number][i][0],40,4);        // lsb address
-             data_buff_rcd_word.insert(ext_funcs[dimm_number][i][0],44,4); // msb address
-             // load data
-             data_buff_rcd_word.insertFromRight(ext_funcs[dimm_number][i][1], 56,4);       // lsb data
-             data_buff_rcd_word.insert(ext_funcs[dimm_number][i][1], 60,4);        // msb data
-
-             func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-            
-            //not sure where the rc call is made
-             if(rc) return rc;
-           } // end if  has ranks
-       } // end dimm loop
-
-
-       // load CCS with F13 RC 10:11, 14:15
-       rc = mss_spec_rcd_load( i_target, port_number, p_func_num_arr, func13_rcd_number_array_size,
-       func_rcd_control_word , ccs_inst_cnt,1);
-       if(rc)
-       {
-          FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-          return rc;
-       }
-    } // end # extended control words to write
-    // end Function 13
-
-    // set FN 0 via RC 7
-    rcd0_15[0] = 0;
-    rcd0_15[1] = 0;
-    rc = mss_spec_rcd_load( i_target, port_number, &rcw, 1, rcd0_15, ccs_inst_cnt,1);
-    if(rc)
-    {
-       FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)",
-       uint32_t(rc), rc.getCreator());
-       return rc;
-    }
-
-    // force execute of remaining rcd               !! not necessary???  !!
-    // Execute the contents of CCS array
-    if (ccs_inst_cnt  > 0)
-    {
-    // Set the End bit on the last CCS Instruction
-       rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1);
-       if(rc)
-       {
-           FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-           return rc;
-       }
-
-       rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-       if(rc)
-       {
-           FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)",
-                                           uint32_t(rc), rc.getCreator());
-           return rc;
-       }
-
-       ccs_inst_cnt = 0;
-    }
-    // end force execute of rcd
-
-
-    return rc;
-
-}
-
-fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target , uint32_t i_port_number,uint32_t dimm_number, uint32_t& io_ccs_inst_cnt)
-{
-     // For LRDIMM  Set Rtt_nom, rtt_wr, driver impedance for R0 and R1
-     // turn off  MRS broadcast
-        ReturnCode rc;
-        ReturnCode rc_buff;
-        uint32_t rc_num = 0;
-        ecmdDataBufferBase csn_8(8);
-        rc_num = rc_num | csn_8.setBit(0,8);
-        ecmdDataBufferBase address_16(16);
-        ecmdDataBufferBase bank_3(3);
-        ecmdDataBufferBase activate_1(1);
-        ecmdDataBufferBase rasn_1(1);
-        rc_num = rc_num | rasn_1.clearBit(0);
-        ecmdDataBufferBase casn_1(1);
-        rc_num = rc_num | casn_1.clearBit(0);
-        ecmdDataBufferBase wen_1(1);
-        rc_num = rc_num | wen_1.clearBit(0);
-        ecmdDataBufferBase cke_4(4);
-        rc_num = rc_num | cke_4.setBit(0,4);
-        ecmdDataBufferBase odt_4(4);
-        rc_num = rc_num | odt_4.setBit(0,4);
-        ecmdDataBufferBase ddr_cal_type_4(4);
-        ecmdDataBufferBase csn_setup_8(8);
-        rc_num = rc_num | csn_setup_8.setBit(0,8);
-
-        ecmdDataBufferBase num_idles_16(16);
-        rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 400, 0, 16);
-        ecmdDataBufferBase num_idles_setup_16(16);
-        rc_num = rc_num | num_idles_setup_16.insertFromRight((uint32_t) 400, 0, 16);
-        ecmdDataBufferBase num_repeat_16(16);
-        ecmdDataBufferBase data_20(20);
-        ecmdDataBufferBase read_compare_1(1);
-        ecmdDataBufferBase rank_cal_4(4);
-        ecmdDataBufferBase ddr_cal_enable_1(1);
-        ecmdDataBufferBase ccs_end_1(1);
-
-        ecmdDataBufferBase mrs1(16);
-        uint16_t MRS1 = 0;
-        //uint32_t mrs_number;
-        uint8_t address_mirror_map[2][2]; //address_mirror_map[port][dimm]
-        uint8_t is_sim = 0;
-        uint8_t dram_2n_mode = 0;
- 
-        uint32_t rank_number;
-        uint16_t num_ranks = 2;
-        uint8_t func13_rcd_number_array_size;
-        uint8_t func13_rcd_number_array_u8[4] = {10,11,14,15};
-        ecmdDataBufferBase data_buff_rcd_word(64);
-        uint8_t l_rcd_cntl_word_7 = 0;
-        uint64_t func_rcd_control_word[2];
-        uint8_t l_rcd_cntl_word_14;
-        uint64_t rcd_array[2][2]; //[port][dimm]
-        uint8_t num_ranks_array[2][2];
-
-        // cs 0:7                   R0   R1   R2   R3   R4   R5   R6   R7
-        uint8_t lrdimm_cs8n [] = { 0x4, 0x8, 0x6, 0xA, 0x5, 0x9, 0x7, 0xB };
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target, rcd_array);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_ADDRESS_MIRRORING, &i_target, address_mirror_map);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-        if(rc) return rc;
-        rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target, dram_2n_mode);
-        if(rc) return rc;
-
-        //MRS1
-        uint8_t dll_enable;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target, dll_enable);
-        if(rc) return rc;
-        uint8_t out_drv_imp_cntl[2][2];
-        rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target, out_drv_imp_cntl);
-        if(rc) return rc;
-        uint8_t dram_rtt_nom[2][2][4];
-        rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target, dram_rtt_nom);
-        if(rc) return rc;
-        uint8_t dram_al;
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target, dram_al);
-        if(rc) return rc;
-        uint8_t wr_lvl; //write leveling enable
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target, wr_lvl);
-        if(rc) return rc;
-        uint8_t tdqs_enable; //TDQS Enable
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_TDQS, &i_target, tdqs_enable);
-        if(rc) return rc;
-        uint8_t q_off; //Qoff - Output buffer Enable
-        rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target, q_off);
-        if(rc) return rc;
-
-
-        if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_ENABLE)
-        {
-            dll_enable = 0x00;
-        }
-        else if (dll_enable == ENUM_ATTR_EFF_DRAM_DLL_ENABLE_DISABLE)
-        {
-            dll_enable = 0xFF;
-        }
-
-        if (dram_al == ENUM_ATTR_EFF_DRAM_AL_DISABLE)
-        {
-            dram_al = 0x00;
-        }
-        else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1)
-        {
-            dram_al = 0x80;
-        }
-        else if (dram_al == ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2)
-        {
-            dram_al = 0x40;
-        }
-
-        if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_DISABLE)
-        {
-            wr_lvl = 0x00;
-        }
-        else if (wr_lvl == ENUM_ATTR_EFF_DRAM_WR_LVL_ENABLE_ENABLE)
-        {
-            wr_lvl = 0xFF;
-        }
-
-        if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_DISABLE)
-        {
-            tdqs_enable = 0x00;
-        }
-        else if (tdqs_enable == ENUM_ATTR_EFF_DRAM_TDQS_ENABLE)
-        {
-            tdqs_enable = 0xFF;
-        }
-
-        if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_DISABLE)
-        {
-            q_off = 0xFF;
-        }
-        else if (q_off == ENUM_ATTR_EFF_DRAM_OUTPUT_BUFFER_ENABLE)
-        {
-            q_off = 0x00;
-        }
-
-        for (uint8_t dimm_num = 0;dimm_num < MAX_NUM_DIMMS; dimm_num++)
-        {
-
-           if ( num_ranks_array[i_port_number][dimm_num] != 0 )
-           {
-              l_rcd_cntl_word_14 = (rcd_array[i_port_number][dimm_num] & 0xF0) >> 4;  // MRS broadcast
-              FAPI_INF("current F0RC14 = 0x%X",l_rcd_cntl_word_14);
-              l_rcd_cntl_word_14 = l_rcd_cntl_word_14 | 0x4;
-              FAPI_INF("setting F0RC14 = 0x%X",l_rcd_cntl_word_14);
-              data_buff_rcd_word.clearBit(0,64);
-              data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_14, 56,4);
-              func_rcd_control_word[dimm_num] = data_buff_rcd_word.getDoubleWord(0);
-            
-              //not sure need this rc check
-              if(rc) return rc;
-           }
-        }
-
-        FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-
-        uint8_t *p_func_num_arr;
-        uint8_t func0_rcd_number_array_size = 2;
-        uint8_t func0_rcd_number_array_u8[] = { 7, 14 };
-        p_func_num_arr = func0_rcd_number_array_u8;
-        rc = mss_spec_rcd_load(i_target, i_port_number, p_func_num_arr, func0_rcd_number_array_size,
-                                  func_rcd_control_word , io_ccs_inst_cnt,1);
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-
-        // set FN 0 via RC 7
-        func_rcd_control_word[0]=0;
-        func_rcd_control_word[1]=0;
-        func0_rcd_number_array_u8 [0] = 7;
-        rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, 1,
-                                func_rcd_control_word, io_ccs_inst_cnt,1);
-
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-     // end turn off MRS broadcast
-
-     // Disable MRS snooping
-        l_rcd_cntl_word_7 = 13;
-        FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-
-        // extended control word  addr, data
-        uint8_t ext_func[2] =   { 0xAC, 0x04};                  // MRS_CTRL = 0xAC;     snoop/forward/store
-        uint8_t rcw = 7;
-        uint64_t rcd0_15[2] = { 0x0000000D00000000ll,           // select FN 13  dimm0
-                                0x0000000D00000000ll };         // "             dimm1
-
-        // set FN 13 via RC 7
-        rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1);
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)",
-                            uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-        func13_rcd_number_array_size = 4;
-        p_func_num_arr = func13_rcd_number_array_u8;
-
-        data_buff_rcd_word.clearBit(0,64);
-        data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);   // select F13
-
-        // set func_rcd_control_word[dimm_number]
-        if ( num_ranks_array[i_port_number][dimm_number] != 0 ) {
-           // load address
-           data_buff_rcd_word.insertFromRight(ext_func[0],40,4);    // lsb address
-           data_buff_rcd_word.insert(ext_func[0],44,4);     // msb address
-           // load data
-           data_buff_rcd_word.insertFromRight(ext_func[1], 56,4);   // lsb data
-           data_buff_rcd_word.insert(ext_func[1], 60,4);    // msb data
-
-           func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-           //not sure need this rc check
-           if(rc) return rc;
-        } // end if  has ranks
-
-        // load CCS with F13 RC 10:11, 14:15
-        rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, func13_rcd_number_array_size,
-                                       func_rcd_control_word , io_ccs_inst_cnt,1);
-        if(rc)
-        {
-               FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-               return rc;
-        }
-
-        // set FN 0 via RC 7
-        rcd0_15[0] = 0;
-        rcd0_15[1] = 0;
-        rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1);
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)",
-                           uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-     // force execute of remaining rcd               !! not necessary???  !!
-        // Execute the contents of CCS array
-        if (io_ccs_inst_cnt  > 0)
-        {
-           // Set the End bit on the last CCS Instruction
-           rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1);
-           if(rc)
-           {
-                   FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                   return rc;
-           }
-
-           rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-           if(rc)
-           {
-                   FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                   return rc;
-           }
-
-           io_ccs_inst_cnt = 0;
-        }
-     // end force execute of rcd
-
-     // Set RTT_nom, rtt_wr, driver impdance through MR1
-        for ( rank_number = 0; rank_number < num_ranks; rank_number++)
-        {
-           FAPI_INF( "MRS SETTINGS FOR PORT%d DIMM%d RANK%d", i_port_number, dimm_number, rank_number);
-
-           rc_num = rc_num | csn_8.setBit(0,8);
-           rc_num = rc_num | address_16.clearBit(0, 16);
-
-           if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE)
-           {
-               dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x00;
-           }
-           else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20)
-           {
-               dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x20;
-           }
-           else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30)
-           {
-               dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xA0;
-           }
-           else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40)
-           {
-               dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0xC0;
-           }
-           else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60)
-           {
-               dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x80;
-           }
-           else if (dram_rtt_nom[i_port_number][dimm_number][rank_number] == ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120)
-           {
-               dram_rtt_nom[i_port_number][dimm_number][rank_number] = 0x40;
-           }
-
-           if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM40)
-           {
-               out_drv_imp_cntl[i_port_number][dimm_number] = 0x00;
-           }
-           else if (out_drv_imp_cntl[i_port_number][dimm_number] == ENUM_ATTR_VPD_DRAM_RON_OHM34)
-           {
-               out_drv_imp_cntl[i_port_number][dimm_number] = 0x80;
-           }
-
-
-           rc_num = rc_num | mrs1.insert((uint8_t) dll_enable, 0, 1, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 1, 1, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 2, 1, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) dram_al, 3, 2, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) out_drv_imp_cntl[i_port_number][dimm_number], 5, 1, 1);
-           rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 6, 1, 1);
-           rc_num = rc_num | mrs1.insert((uint8_t) wr_lvl, 7, 1, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 8, 1);
-           rc_num = rc_num | mrs1.insert((uint8_t) dram_rtt_nom[i_port_number][dimm_number][rank_number], 9, 1, 2);
-           rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 10, 1);
-           rc_num = rc_num | mrs1.insert((uint8_t) tdqs_enable, 11, 1, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) q_off, 12, 1, 0);
-           rc_num = rc_num | mrs1.insert((uint8_t) 0x00, 13, 3);
-
-           rc_num = rc_num | mrs1.extractPreserve(&MRS1, 0, 16, 0);
-
-           FAPI_INF( "MRS 1: 0x%04X", MRS1);
-
-           if (rc_num)
-           {
-               FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-               rc_buff.setEcmdError(rc_num);
-               return rc_buff;
-           }
-
-           // Only corresponding CS to rank
-           rc_num = rc_num | csn_8.setBit(0,8);
-           rc_num = rc_num | csn_8.insert(lrdimm_cs8n[rank_number],(4*dimm_number),4,4);
-           //mrs_number = 2;
-
-           // Copying the current MRS into address buffer matching the MRS_array order
-           // Setting the bank address
-           rc_num = rc_num | address_16.insert(mrs1, 0, 16, 0);
-           rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 0, 1, 7);
-           rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 1, 1, 6);
-           rc_num = rc_num | bank_3.insert((uint8_t) MRS1_BA, 2, 1, 5);
-
-
-           if (rc_num)
-           {
-               FAPI_ERR( "mss_mrs_load: Error setting up buffers");
-               rc_buff.setEcmdError(rc_num);
-               return rc_buff;
-           }
-
-           if (( address_mirror_map[i_port_number][dimm_number] & (0x08 >> rank_number) ) && (is_sim == 0))
-           {
-               rc = mss_address_mirror_swizzle(i_target, i_port_number, dimm_number, rank_number, address_16, bank_3);
-           }
-
-
-           if (dram_2n_mode  == ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE)
-           {
-
-              // Send out to the CCS array
-              rc = mss_ccs_inst_arry_0( i_target,
-                                io_ccs_inst_cnt,
-                                address_16,
-                                bank_3,
-                                activate_1,
-                                rasn_1,
-                                casn_1,
-                                wen_1,
-                                cke_4,
-                                csn_setup_8,
-                                odt_4,
-                                ddr_cal_type_4,
-                                i_port_number);
-              if(rc) return rc;
-              rc = mss_ccs_inst_arry_1( i_target,
-                                io_ccs_inst_cnt,
-                                num_idles_setup_16,
-                                num_repeat_16,
-                                data_20,
-                                read_compare_1,
-                                rank_cal_4,
-                                ddr_cal_enable_1,
-                                ccs_end_1);
-              if(rc) return rc;
-              io_ccs_inst_cnt ++;
-           }
-
-           // Send out to the CCS array
-           rc = mss_ccs_inst_arry_0( i_target,
-                             io_ccs_inst_cnt,
-                             address_16,
-                             bank_3,
-                             activate_1,
-                             rasn_1,
-                             casn_1,
-                             wen_1,
-                             cke_4,
-                             csn_8,
-                             odt_4,
-                             ddr_cal_type_4,
-                             i_port_number);
-           if(rc) return rc;
-           rc = mss_ccs_inst_arry_1( i_target,
-                             io_ccs_inst_cnt,
-                             num_idles_16,
-                             num_repeat_16,
-                             data_20,
-                             read_compare_1,
-                             rank_cal_4,
-                             ddr_cal_enable_1,
-                             ccs_end_1);
-           if(rc) return rc;
-           io_ccs_inst_cnt ++;
-
-        } // end rank loop
-
-     // turn on  MRS broadcast
-
-        l_rcd_cntl_word_7 = 0;
-
-        for (uint8_t dimm_num = 0;dimm_num < MAX_NUM_DIMMS; dimm_num++)
-        {
-
-           if ( num_ranks_array[i_port_number][dimm_num] != 0 )
-           {
-              l_rcd_cntl_word_14 = (rcd_array[i_port_number][dimm_num] & 0xF0) >> 4;  // MRS broadcast
-              FAPI_INF("current F0RC14 = 0x%X",l_rcd_cntl_word_14);
-              l_rcd_cntl_word_14 = l_rcd_cntl_word_14 & 0xB;
-              FAPI_INF("setting F0RC14 = 0x%X",l_rcd_cntl_word_14);
-              ecmdDataBufferBase data_buff_rcd_word(64);
-              data_buff_rcd_word.clearBit(0,64);
-              data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_14, 56,4);
-              func_rcd_control_word[dimm_num] = data_buff_rcd_word.getDoubleWord(0);
-
-              //not sure if need the rc check
-              if(rc) return rc;
-           }
-        }
-
-        FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-
-        func0_rcd_number_array_size = 2;
-        p_func_num_arr = func0_rcd_number_array_u8;
-        rc = mss_spec_rcd_load(i_target, i_port_number, p_func_num_arr, func0_rcd_number_array_size,
-                                  func_rcd_control_word , io_ccs_inst_cnt,1);
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-
-        // set FN 0 via RC 7
-        func_rcd_control_word[0]=0;
-        func_rcd_control_word[1]=0;
-        func0_rcd_number_array_u8 [0] = 7;
-        rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, 1,
-                                 func_rcd_control_word, io_ccs_inst_cnt,1);
-
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-     // end turn on MRS broadcast
-
-     // Enable MRS snooping
-        l_rcd_cntl_word_7 = 13;
-        FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-
-        // extended control word  data
-        ext_func[1] = 0x00;                  // MRS_CTRL = 0xAC;     snoop/forward/store
-        rcw = 7;
-        rcd0_15[0] = 0x0000000D00000000ll;          // select FN 13  dimm0
-        rcd0_15[1] = 0x0000000D00000000ll ;         // "             dimm1
-
-        // set FN 13 via RC 7
-        rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1);
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)",
-                            uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-        func13_rcd_number_array_size = 4;
-        p_func_num_arr = func13_rcd_number_array_u8;
-
-        data_buff_rcd_word.clearBit(0,64);
-        data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28,4);   // select F13
-
-        // set func_rcd_control_word[dimm_number]
-        if ( num_ranks_array[i_port_number][dimm_number] != 0 ) {
-           // load address
-           data_buff_rcd_word.insertFromRight(ext_func[0],40,4);    // lsb address
-           data_buff_rcd_word.insert(ext_func[0],44,4);     // msb address
-           // load data
-           data_buff_rcd_word.insertFromRight(ext_func[1], 56,4);   // lsb data
-           data_buff_rcd_word.insert(ext_func[1], 60,4);    // msb data
-
-           func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0); if(rc) return rc;
-        } // end if  has ranks
-
-
-        // load CCS with F13 RC 10:11, 14:15
-        rc = mss_spec_rcd_load( i_target, i_port_number, p_func_num_arr, func13_rcd_number_array_size,
-                       func_rcd_control_word , io_ccs_inst_cnt,1);
-        if(rc)
-        {
-               FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-               return rc;
-        }
-
-        // set FN 0 via RC 7
-        rcd0_15[0] = 0;
-        rcd0_15[1] = 0;
-        rc = mss_spec_rcd_load( i_target, i_port_number, &rcw, 1, rcd0_15, io_ccs_inst_cnt,1);
-        if(rc)
-        {
-           FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)",
-                           uint32_t(rc), rc.getCreator());
-           return rc;
-        }
-
-     // force execute of remaining rcd               !! not necessary???  !!
-        // Execute the contents of CCS array
-        if (io_ccs_inst_cnt  > 0)
-        {
-           // Set the End bit on the last CCS Instruction
-           rc = mss_ccs_set_end_bit( i_target, io_ccs_inst_cnt-1);
-           if(rc)
-           {
-                   FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                   return rc;
-           }
-
-           rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-           if(rc)
-           {
-                   FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-                   return rc;
-           }
-
-           io_ccs_inst_cnt = 0;
-        }
-     // end force execute of rcd
-     // End enable MRS snooping
-
-
-    return rc;
-}
-
-fapi::ReturnCode  mss_execute_lrdimm_mb_dram_training(fapi::Target &i_target)
-{
-   ReturnCode rc;
-   uint8_t l_rcd_cntl_word_7;
-   uint8_t l_rcd_cntl_word_12;
-   ecmdDataBufferBase data_buff_rcd_word(64);
-   uint32_t port;
-   uint8_t dimm_number;
-   const uint8_t MAX_NUM_DIMMS = 2;
-   const uint8_t MAX_NUM_PORT = 2;
-   uint8_t num_ranks_array[MAX_NUM_PORT][MAX_NUM_DIMMS];
-   uint64_t func_rcd_control_word[2];
-   uint8_t *p_func_num_arr;
-   uint8_t funcTRAIN_rcd_number_array_u8[2] = {7,12};
-
-   uint32_t ccs_inst_cnt = 0;
-   uint32_t rc_num = 0;
-   ecmdDataBufferBase address_16(16);
-   ecmdDataBufferBase bank_3(3);
-   ecmdDataBufferBase activate_1(1);
-   ecmdDataBufferBase rasn_1(1);
-   rc_num = rc_num | rasn_1.setBit(0);
-   ecmdDataBufferBase casn_1(1);
-   rc_num = rc_num | casn_1.setBit(0);
-   ecmdDataBufferBase wen_1(1);
-   rc_num = rc_num | wen_1.setBit(0);
-   ecmdDataBufferBase cke_4(4);
-   rc_num = rc_num | cke_4.setBit(0,4);
-   ecmdDataBufferBase csn_8(8);
-   rc_num = rc_num | csn_8.setBit(0,2);
-   rc_num = rc_num | csn_8.setBit(4,2);
-   ecmdDataBufferBase odt_4(4);
-   rc_num = rc_num | odt_4.setBit(0,4);
-   ecmdDataBufferBase ddr_cal_type_4(4);
-
-   if(rc_num)
-   {
-       rc.setEcmdError(rc_num);
-       return rc;
-   }
-   ecmdDataBufferBase num_idles_16(16);
-   ecmdDataBufferBase num_repeat_16(16);
-   ecmdDataBufferBase data_20(20);
-   ecmdDataBufferBase read_compare_1(1);
-   ecmdDataBufferBase rank_cal_4(4);
-   ecmdDataBufferBase ddr_cal_enable_1(1);
-   ecmdDataBufferBase ccs_end_1(1);
-
-   uint32_t l_mss_freq;
-   uint32_t l_num_idles_delay=20;
-
-   fapi::Target l_target_centaur;
-   rc = fapiGetParentChip(i_target, l_target_centaur);
-   if(rc) return rc;
-
-   rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq);
-   if(rc) return rc;
-
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-   if(rc) return rc;
-
-   for ( port = 0; port < MAX_NUM_PORT; port++ )
-   {
-      // MB-DRAM training
-      l_rcd_cntl_word_7 = 0;
-      l_rcd_cntl_word_12 = 2; // Training control, start DRAM interface training
-
-      data_buff_rcd_word.clearBit(0,64);
-      data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_7, 28, 4);
-      data_buff_rcd_word.insertFromRight(&l_rcd_cntl_word_12, 48, 4);
-
-      for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++ )
-      {
-         if ( num_ranks_array[port][dimm_number] != 0 )
-         {
-            func_rcd_control_word[dimm_number] = data_buff_rcd_word.getDoubleWord(0);
-            if(rc) return rc;
-         }
-      }
-
-      FAPI_INF("SELECTING FUNCTION %d", l_rcd_cntl_word_7);
-      p_func_num_arr = funcTRAIN_rcd_number_array_u8;
-      rc = mss_spec_rcd_load(i_target, port, p_func_num_arr,
-                            (uint8_t) sizeof(funcTRAIN_rcd_number_array_u8)/(uint8_t)sizeof(funcTRAIN_rcd_number_array_u8[0]),
-                            func_rcd_control_word , ccs_inst_cnt,1);
-      if(rc)
-      {
-         FAPI_ERR(" spec_rcd_load Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-         return rc;
-      }
-
-
-      rc_num = rc_num | address_16.clearBit(0, 16);
-      rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) l_num_idles_delay, 0, 16);
-      if(rc_num)
-      {
-          rc.setEcmdError(rc_num);
-          return rc;
-      }
-
-      rc = mss_ccs_inst_arry_0( i_target,
-                                 ccs_inst_cnt,
-                                 address_16,
-                                 bank_3,
-                                 activate_1,
-                                 rasn_1,
-                                 casn_1,
-                                 wen_1,
-                                 cke_4,
-                                 csn_8,
-                                 odt_4,
-                                 ddr_cal_type_4,
-                                 port);
-      if(rc) return rc;
-      rc = mss_ccs_inst_arry_1( i_target,
-                                 ccs_inst_cnt,
-                                 num_idles_16,
-                                 num_repeat_16,
-                                 data_20,
-                                 read_compare_1,
-                                 rank_cal_4,
-                                 ddr_cal_enable_1,
-                                 ccs_end_1);
-      if(rc) return rc;
-      ccs_inst_cnt++;
-   }
-
-   // Execute the contents of CCS array
-   if (ccs_inst_cnt  > 0)
-   {
-   // Set the End bit on the last CCS Instruction
-      rc = mss_ccs_set_end_bit( i_target, ccs_inst_cnt-1);
-      if(rc)
-      {
-              FAPI_ERR("CCS_SET_END_BIT FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-              return rc;
-      }
-
-      rc = mss_execute_ccs_inst_array(i_target, 10, 10);
-      if(rc)
-      {
-              FAPI_ERR(" EXECUTE_CCS_INST_ARRAY FAILED rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
-              return rc;
-      }
-
-      ccs_inst_cnt = 0;
-   }// end force execute of rcd
-   return rc;
-}
-
-fapi::ReturnCode mss_lrdimm_eff_config(const fapi::Target &i_target_mba, 
-                                 uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE],
-                                 uint32_t mss_freq, uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE])
-{
-   ReturnCode rc;
-
-   std::vector<fapi::Target> l_target_dimm_array;
-   uint8_t l_cur_mba_port = 0;
-   uint8_t l_cur_mba_dimm = 0;
-
-   mss_lrdimm_spd_data *p_l_lr_spd_data = new mss_lrdimm_spd_data();
-   memset( p_l_lr_spd_data, 0, sizeof(mss_lrdimm_spd_data) );
-
-   uint8_t lrdimm_mr12_reg[PORT_SIZE][DIMM_SIZE];
-   uint64_t lrdimm_additional_cntl_words[PORT_SIZE][DIMM_SIZE];
-   uint8_t lrdimm_rank_mult_mode;
-   uint8_t eff_ibm_type[PORT_SIZE][DIMM_SIZE];
-   uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
-
-   do 
-   {
-      rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array);
-      if(rc)
-      {
-          FAPI_ERR("Error retrieving assodiated dimms");
-          break;
-      }
-   
-      for (uint8_t l_dimm_index = 0; l_dimm_index < l_target_dimm_array.size(); l_dimm_index += 1)
-      {
-         rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[l_dimm_index],
-                 l_cur_mba_port);
-         if(rc)
-         {
-             FAPI_ERR("Error retrieving ATTR_MBA_PORT");
-             break;
-         }
-   //------------------------------------------------------------------------
-         rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[l_dimm_index], l_cur_mba_dimm);
-         if(rc)
-         {
-             FAPI_ERR("Error retrieving ATTR_MBA_DIMM");
-             break;
-         }
-   
-         // Setup SPD attributes
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_ADDR_MIRRORING, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_addr_mirroring[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F0RC3_F0RC2, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F0RC5_F0RC4, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F1RC11_F1RC8, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F1RC13_F1RC12, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F1RC15_F1RC14, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F3RC9_F3RC8_FOR_800_1066, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F34RC11_F34RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f34rc11_f34rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F56RC11_F56RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f56rc11_f56rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F78RC11_F78RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F910RC11_F910RC10_FOR_800_1066, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_MR12_FOR_800_1066, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_mr12_for_800_1066[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F3RC9_F3RC8_FOR_1333_1600, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F34RC11_F34RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F56RC11_F56RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F78RC11_F78RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F910RC11_F910RC10_FOR_1333_1600, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_MR12_FOR_1333_1600, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_mr12_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F3RC9_F3RC8_FOR_1866_2133, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F34RC11_F34RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F56RC11_F56RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F78RC11_F78RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_F910RC11_F910RC10_FOR_1866_2133, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-         rc = FAPI_ATTR_GET(ATTR_SPD_LR_MR12_FOR_1866_2133, &l_target_dimm_array[l_dimm_index],
-             p_l_lr_spd_data->lr_mr12_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm]);
-         if(rc) break;
-      }
-   
-      if(rc)
-      {
-          FAPI_ERR("Error reading spd data from caller");
-          break;
-      }
-   
-   
-      // Setup attributes
-      for (int l_cur_mba_port = 0; l_cur_mba_port < PORT_SIZE; l_cur_mba_port += 1)
-      {
-         for (int l_cur_mba_dimm = 0; l_cur_mba_dimm < DIMM_SIZE; l_cur_mba_dimm += 1)
-         {
-            if (cur_dimm_spd_valid_u8array[l_cur_mba_port][l_cur_mba_dimm] == MSS_EFF_VALID)
-            {
-               FAPI_INF("  !! LRDIMM Detected  -MW");
-   
-               ecmdDataBufferBase rcd(64);
-               rcd.flushTo0();
-   
-               rcd.setDoubleWord(0,eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm]);
-               FAPI_INF("rcd0_15=0x%016llX",rcd.getDoubleWord(0));
-   
-               rcd.insert(p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm],12,4,0);  //rcd3
-               rcd.insert(p_l_lr_spd_data->lr_f0rc3_f0rc2[l_cur_mba_port][l_cur_mba_dimm],8,4,4);   //rcd2
-   
-               rcd.insert(p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm],20,4,0);  //rcd5
-               rcd.insert(p_l_lr_spd_data->lr_f0rc5_f0rc4[l_cur_mba_port][l_cur_mba_dimm],16,4,4);  //rcd4
-   
-               rcd.insert(p_l_lr_spd_data->lr_addr_mirroring[l_cur_mba_port][l_cur_mba_dimm],59,1,7); // address mirroring
-   
-               eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm]=rcd.getDoubleWord(0);
-   
-               ecmdDataBufferBase rcd_1(64);
-               rcd_1.flushTo0();
-                    // F[1]RC11,8
-               rcd_1.insert(p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm],44,4,0);  //F[1]RC11 -> rcd11
-               rcd_1.insert(p_l_lr_spd_data->lr_f1rc11_f1rc8[l_cur_mba_port][l_cur_mba_dimm],32,4,4);  //F[1]RC8  -> rcd8
-   
-                    // F[1]RC13,12
-               rcd_1.insert(p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm],52,4,0);  //F[1]RC13 -> rcd13
-               rcd_1.insert(p_l_lr_spd_data->lr_f1rc13_f1rc12[l_cur_mba_port][l_cur_mba_dimm],48,4,4);  //F[1]RC12 -> rcd12
-   
-                    // F[1]RC15,14
-               rcd_1.insert(p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm],60,4,0);  //F[1]RC15 -> rcd15
-               rcd_1.insert(p_l_lr_spd_data->lr_f1rc15_f1rc14[l_cur_mba_port][l_cur_mba_dimm],56,4,4);  //F[1]RC14 -> rcd14
-   
-   
-               if ( mss_freq > 1733 ) {
-                    rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],36,4,0);       // F[3]RC9 -> rcd9
-                    rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],40,4,4);       // F[3]RC8 -> rcd10
-                    rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],4,4,0);    // F[3,4]RC11 -> rcd1
-                    rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],0,4,4);    // F[3,4]RC10 -> rcd0
-                    rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],12,4,0);   // F[6,6]RC11 -> rcd3
-                    rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],8,4,4);    // F[5,6]RC10 -> rcd2
-                    rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],20,4,0);   // F[7,8]RC11 -> rcd5
-                    rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],16,4,4);   // F[7,8]RC10 -> rcd4
-                    rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7
-                    rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6
-   
-                    lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_1866_2133[l_cur_mba_port][l_cur_mba_dimm];
-   
-               } else if ( mss_freq > 1200 )  {
-                    rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],36,4,0);       // F[3]RC9 -> rcd9
-                    rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],40,4,4);       // F[3]RC8 -> rcd10
-                    rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],4,4,0);    // F[3,4]RC11 -> rcd1
-                    rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],0,4,4);    // F[3,4]RC10 -> rcd0
-                    rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],12,4,0);   // F[6,6]RC11 -> rcd3
-                    rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],8,4,4);    // F[5,6]RC10 -> rcd2
-                    rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],20,4,0);   // F[7,8]RC11 -> rcd5
-                    rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],16,4,4);   // F[7,8]RC10 -> rcd4
-                    rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7
-                    rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6
-   
-                    lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_1333_1600[l_cur_mba_port][l_cur_mba_dimm];
-   
-               } else {
-                    rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],36,4,0);       // F[3]RC9 -> rcd9
-                    rcd_1.insert(p_l_lr_spd_data->lr_f3rc9_f3rc8_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],40,4,4);       // F[3]RC8 -> rcd10
-                    rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],4,4,0);    // F[3,4]RC11 -> rcd1
-                    rcd_1.insert(p_l_lr_spd_data->lr_f34rc11_f34rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],0,4,4);    // F[3,4]RC10 -> rcd0
-                    rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],12,4,0);   // F[6,6]RC11 -> rcd3
-                    rcd_1.insert(p_l_lr_spd_data->lr_f56rc11_f56rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],8,4,4);    // F[5,6]RC10 -> rcd2
-                    rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],20,4,0);   // F[7,8]RC11 -> rcd5
-                    rcd_1.insert(p_l_lr_spd_data->lr_f78rc11_f78rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],16,4,4);   // F[7,8]RC10 -> rcd4
-                    rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],28,4,0); // F[9,10]RC11 -> rcd7
-                    rcd_1.insert(p_l_lr_spd_data->lr_f910rc11_f910rc10_for_800_1066[l_cur_mba_port][l_cur_mba_dimm],24,4,4); // F[9,10]RC10 -> rcd6
-   
-                    lrdimm_mr12_reg[l_cur_mba_port][l_cur_mba_dimm] = p_l_lr_spd_data->lr_mr12_for_800_1066[l_cur_mba_port][l_cur_mba_dimm];
-               }
-   
-               uint64_t rcd1 = rcd_1.getDoubleWord(0);
-               lrdimm_additional_cntl_words[l_cur_mba_port][l_cur_mba_dimm] = rcd1;
-   
-               if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 8 ) {
-                  lrdimm_rank_mult_mode = 4; // Default for 8R is 4x mult mode
-               }
-   
-                   // ========================================================================================
-   
-   
-                                // FIX finding stack type properly.
-               if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1 ) {
-                  //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
-                  eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5A;
-               } else if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 2 ) {
-                  //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
-                  eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5B;
-               } else if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 4 ) {
-                  //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP;
-                  eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5C;
-               } else if ( eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 8 ) {
-                  //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP;
-                  eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5D;
-               } else {
-                  //p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
-                  eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
-                  FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
-                  uint8_t IBM_TYPE = eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm];
-                  const fapi::Target& TARGET = i_target_mba;
-                  fapi::Target& DIMM = l_target_dimm_array[l_cur_mba_dimm];
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_UNSUPPORTED_TYPE);
-                  return rc;
-               }
-            } // end valid dimm
-         } // end dimm loop
-      } // end port loop
-   
-      rc = FAPI_ATTR_SET(ATTR_EFF_IBM_TYPE, &i_target_mba,
-              eff_ibm_type);
-      rc = FAPI_ATTR_SET(ATTR_LRDIMM_MR12_REG, &i_target_mba,
-              lrdimm_mr12_reg);
-      rc = FAPI_ATTR_SET(ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target_mba,
-              lrdimm_additional_cntl_words);
-      rc = FAPI_ATTR_SET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target_mba,
-              lrdimm_rank_mult_mode);
-      rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba,
-              eff_dimm_rcd_cntl_word_0_15);
-   
-      if(rc)
-      {
-         FAPI_ERR("Error setting attributes");
-         break;
-      }
-   } while(0);
-
-   return rc;
-}
-
-fapi::ReturnCode mss_lrdimm_rewrite_odt(const fapi::Target& i_target_mba, uint32_t * p_b_var_array, uint32_t *var_array_p_array[5])
-{
-   ReturnCode rc;
-   uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
-//   uint8_t l_arr_offset;
-   uint32_t l_mss_freq = 0;
-   uint8_t l_dram_width_u8;
-   
-   //   uint32_t *odt_array;
-
-   // For dual drop, Set ODT_RD as 2rank (8R LRDIMM) or 4rank (4R LRDIMM)
-   fapi::Target l_target_centaur;
-   rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc;
-
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc;
-
-//   uint8_t l_start=44, l_end=60;
-// 8/4/2014 kahnevan - ifdefing this out to avoid 64 bit compiler warnings for unused odt_array variable.
-// With the code at the bottom commented out, (comment from mdb) nothing was being done with the value.
-#if 0
-   if ( (l_num_ranks_per_dimm_u8array[0][1] == 4) || (l_num_ranks_per_dimm_u8array[1][1] == 4) ) {
-     odt_array = var_array_p_array[0];
-      FAPI_INF("Setting LRDIMM ODT_RD as 4 rank dimm");
-   } else if ( (l_num_ranks_per_dimm_u8array[0][1] == 8) || (l_num_ranks_per_dimm_u8array[1][1] == 8) ) {
-      if ( l_mss_freq <= 1466 ) { // 1333Mbps
-         if ( l_dram_width_u8 == 4 ) {
-	   odt_array = var_array_p_array[1];
-         } else if ( l_dram_width_u8 == 8 ) {
-            odt_array = var_array_p_array[2];
-         }
-      } else if ( l_mss_freq <= 1733 ) { // 1600 Mbps
-         if ( l_dram_width_u8 == 4 ) {
-	   odt_array = var_array_p_array[3];
-         } else if ( l_dram_width_u8 == 8 ) {
-	   odt_array = var_array_p_array[4];
-         }
-      }
-      FAPI_INF("Setting LRDIMM ODT_RD as 2 logical rank dimm");
-   }
-#endif
-
-// mdb - we do not have eff config attributes, so we can't set this array.  This function probably goes away
-//   for ( l_arr_offset = l_start; l_arr_offset < l_end; l_arr_offset++ ) {
-//      *(p_b_var_array + l_arr_offset) = *(odt_array + l_arr_offset);
-//   }
-
-   return rc;
-}
-
-fapi::ReturnCode mss_lrdimm_term_atts(const fapi::Target& i_target_mba)
-{
-   ReturnCode rc;
-
-   uint8_t l_dram_ron[PORT_SIZE][DIMM_SIZE];
-   uint8_t l_dram_rtt_wr[PORT_SIZE][DIMM_SIZE];
-   uint8_t l_dram_rtt_nom[PORT_SIZE][DIMM_SIZE];
-
-   uint8_t attr_eff_dram_ron[PORT_SIZE][DIMM_SIZE];
-   uint8_t attr_eff_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-   uint8_t attr_eff_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-   uint8_t attr_eff_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-
-   uint32_t l_mss_freq = 0;
-   uint32_t l_mss_volt = 0;
-   uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
-   uint8_t l_num_drops_per_port;
-   uint8_t l_dram_density;
-   uint8_t l_dram_width_u8;
-   
-   uint8_t l_lrdimm_mr12_u8array[PORT_SIZE][DIMM_SIZE];
-   uint8_t l_lrdimm_rank_mult_mode;
-
-   uint8_t l_rcd_cntl_word_0_1;
-   uint8_t l_rcd_cntl_word_6_7;
-   uint8_t l_rcd_cntl_word_8_9;
-   uint8_t l_rcd_cntl_word_10;
-   uint8_t l_rcd_cntl_word_11;
-   uint8_t l_rcd_cntl_word_12;
-   uint8_t l_rcd_cntl_word_13;
-   uint8_t l_rcd_cntl_word_14;
-   uint8_t l_rcd_cntl_word_15;
-   uint64_t l_rcd_cntl_word_0_15;
-   uint64_t l_rcd_cntl_word_2_5_mask = 0x00FFFF0000000010LL;
-   ecmdDataBufferBase data_buffer_64(64);
-   ecmdDataBufferBase data_buffer_8(8);
-
-   // Fetch impacted attributes
-   uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
-   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc;
-
-   // Fetch impacted attributes
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_DENSITY, &i_target_mba, l_dram_density); if(rc) return rc;
-
-   fapi::Target l_target_centaur;
-   rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc;
-
-   // Fetch SPD MR1,2
-   rc = FAPI_ATTR_GET(ATTR_LRDIMM_MR12_REG, &i_target_mba, l_lrdimm_mr12_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_LRDIMM_RANK_MULT_MODE, &i_target_mba, l_lrdimm_rank_mult_mode); if(rc) return rc;
-
-   for (uint8_t l_port = 0; l_port < PORT_SIZE; l_port++) {
-      for (uint8_t l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm++) {
-
-         // Set RCD control word
-         FAPI_INF("before setting: rcd control word 0-15 %.16llX", l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] );
-         l_rcd_cntl_word_0_1   = 0x00; // Global features,  Clock driver enable
-         FAPI_INF("rcd control word 0-1 %X", l_rcd_cntl_word_0_1 );
-
-         // RCD cntl words 2-5 from SPD
-
-         l_rcd_cntl_word_6_7   = 0x00; // CKE & ODT management, Function select
-         FAPI_INF("rcd control word 6-7 %X", l_rcd_cntl_word_6_7 );
-
-         if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) {
-            l_rcd_cntl_word_8_9   = 0x20; // IBT=200 Ohm & Vref settings for address, command, par_in, Power saving settings
-         }
-         else {
-            l_rcd_cntl_word_8_9   = 0x00; // IBT=100 Ohm & Vref settings for address, command, par_in, Power saving settings
-         }
-         FAPI_INF("rcd control word 8-9 %X", l_rcd_cntl_word_8_9 );
-
-
-        const fapi::Target& TARGET = i_target_mba;
-         // RC10 LRDIMM operating speed
-         if ( l_mss_freq <= 933 ) {         // 800Mbps
-            l_rcd_cntl_word_10 = 0;
-         } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
-            l_rcd_cntl_word_10 = 1;
-         } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
-            l_rcd_cntl_word_10 = 2;
-         } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            l_rcd_cntl_word_10 = 3;
-         } else if ( l_mss_freq <= 2000 ) { // 1866Mbps
-            l_rcd_cntl_word_10 = 4;
-         } else {
-            FAPI_ERR("Invalid LRDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
-            uint32_t& L_MSS_FREQ = l_mss_freq;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_MSS_FREQ); return rc;
-         }
-         FAPI_INF("rcd control word 10 %X", l_rcd_cntl_word_10 );
-
-         // RC11 Operating voltage & parity calculation (buffer does not include A17:16)
-         if ( l_mss_volt >= 1420 ) {        // 1.5V
-            l_rcd_cntl_word_11 = 4;
-         } else if ( l_mss_volt >= 1270 ) { // 1.35V
-            l_rcd_cntl_word_11 = 5;
-         } else if ( l_mss_volt >= 1170 ) { // 1.25V
-            l_rcd_cntl_word_11 = 6;
-         } else {
-            FAPI_ERR("Invalid LRDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString());
-            uint32_t& L_MSS_VOLT = l_mss_volt;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_MSS_VOLT); return rc;
-         }
-         FAPI_INF("rcd control word 11 %X", l_rcd_cntl_word_11 );
-
-         l_rcd_cntl_word_12 = 0; //Training
-         FAPI_INF("rcd control word 12 %X", l_rcd_cntl_word_12 );
-
-         // rC13 DIMM configuration
-         if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 8 ) {
-            l_rcd_cntl_word_13 = 4;       // 8 physical ranks, 2 logical ranks, RM=4
-         } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) {
-            l_rcd_cntl_word_13 = 9;       // 4 physical ranks, 4 logical ranks, direct rank mapping
-      //   } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 2 ) {
-      //      l_rcd_cntl_word_13 = 6;       // 2 physical ranks, 2 logical ranks, direct rank mapping
-      //   } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 1 ) {
-      //      l_rcd_cntl_word_13 = 3;       // 1 physical rank, 1 logical rank, direct rank mapping
-         } else {
-            l_rcd_cntl_word_13 = 0;
-         }
-         FAPI_INF("rcd control word 13 %X", l_rcd_cntl_word_13 );
-
-         // RC14 DRAM configuration & DRAM command
-         if ( l_lrdimm_rank_mult_mode != 0 ) {
-            data_buffer_8.setBit(2);         // turn off refresh broadcast
-         }
-         if ( l_dram_width_u8 == 8 )  {
-            data_buffer_8.setBit(0);
-         }
-         data_buffer_8.extractToRight( &l_rcd_cntl_word_14, 0, 4);
-         FAPI_INF("rcd control word 14 %X", l_rcd_cntl_word_14 );
-         uint8_t& L_LRDIMM_RANK_MULT_MODE=l_lrdimm_rank_mult_mode;
-         uint8_t& L_DRAM_DENSITY=l_dram_density;
-
-         // RC15 Rank multiplication
-         if ( l_lrdimm_rank_mult_mode == 4 ) {
-            if ( l_dram_density == 1 ) {
-               l_rcd_cntl_word_15 = 5;    // A[15:14]; 4x multiplication, 1 Gbit DDR3 SDRAM
-            } else if ( l_dram_density == 2 ) {
-               l_rcd_cntl_word_15 = 6;    // A[16:15]; 4x multiplication, 2 Gbit DDR3 SDRAM               
-            } else if ( l_dram_density == 4 ) {
-               l_rcd_cntl_word_15 = 7;    // A[17:16]; 4x multiplication, 4 Gbit DDR3 SDRAM
-            } else {
-               FAPI_ERR("Invalid LRDIMM Rank mult mode =%d, ATTR_EFF_DRAM_DENSITY = %d on %s!", l_lrdimm_rank_mult_mode, l_dram_density, i_target_mba.toEcmdString());
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_RANK_MULT_MODE); return rc;
-            }
-         } else if ( l_lrdimm_rank_mult_mode == 2 ) {
-            if ( l_dram_density == 1 ) {
-               l_rcd_cntl_word_15 = 1;    // A[14]; 2x multiplication, 1 Gbit DDR3 SDRAM
-            } else if ( l_dram_density == 2 ) {
-               l_rcd_cntl_word_15 = 2;    // A[15]; 2x multiplication, 2 Gbit DDR3 SDRAM
-            } else if ( l_dram_density == 4 ) {
-               l_rcd_cntl_word_15 = 3;    // A[16]; 2x multiplication, 4 Gbit DDR3 SDRAM
-            } else {
-               FAPI_ERR("Invalid LRDIMM Rank Mult mode = %d,  ATTR_EFF_DRAM_DENSITY = %d on %s!", l_lrdimm_rank_mult_mode, l_dram_density, i_target_mba.toEcmdString());
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_DRAM_DENSITY_MULT_2); return rc;
-            }
-         } else {
-            l_rcd_cntl_word_15 = 0;
-         }
-         FAPI_INF("rcd control word 15 %X", l_rcd_cntl_word_15 );
-
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_0_1, 0, 8);
-         data_buffer_64.clearBit( 8, 16);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_6_7, 24, 8);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_8_9, 32, 8);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_10,  40, 4);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_11,  44, 4);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_12,  48, 4);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_13,  52, 4);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_14,  56, 4);
-         data_buffer_64.insertFromRight(&l_rcd_cntl_word_15,  60, 4);
-         l_rcd_cntl_word_0_15 = data_buffer_64.getDoubleWord(0); if(rc) return rc;
-         FAPI_INF("from data buffer: rcd control word 0-15 %llX", l_rcd_cntl_word_0_15 );
-         l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_cntl_word_2_5_mask;
-         l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_cntl_word_0_15;
-
-         FAPI_INF("after mask: rcd control word 0-15 %.16llX", l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] );
-
-        // Setup LRDIMM drive impedance, rtt nom, rtt wr, odt wr
-         l_dram_ron[l_port][l_dimm] = l_lrdimm_mr12_u8array[l_port][l_dimm] & 0x03; // Pulled from SPD LR MR1,2 DRAM DriverImpedance [1:0]
-         l_dram_rtt_nom[l_port][l_dimm] = (l_lrdimm_mr12_u8array[l_port][l_dimm] & 0x1C) >> 2; // Pulled from SPD LR MR1,2 DRAM RTT_nom for ranks 0/1 [4:2]
-         l_dram_rtt_wr[l_port][l_dimm]  = (l_lrdimm_mr12_u8array[l_port][l_dimm] & 0xC0) >> 6; // Pulled from SPD LR MR1,2 DRAM RTT_WR [7:6]
-
-         if ( l_dram_ron[l_port][l_dimm] == 0 ) {
-            l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RON_OHM40;
-         } else if ( l_dram_ron[l_port][l_dimm] == 1 ) {
-            l_dram_ron[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34;
-         } else {
-            uint8_t& L_DRAM_RON = l_dram_ron[l_port][l_dimm];
-            FAPI_ERR("Invalid SPD LR MR1,2 DRAM drv imp on %s!", i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_SPD_DRV_IMP); return rc;
-         }
-
-         attr_eff_dram_ron[l_port][l_dimm] = l_dram_ron[l_port][l_dimm];
-         FAPI_INF("Set LRDIMM DRAM_RON to SPD LR MR1,2 DRAM drv imp");
-
-         switch (l_dram_rtt_nom[l_port][l_dimm]) {
-            case 0 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE;
-                break;
-            case 1 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60;
-                break;
-            case 2 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120;
-                break;
-            case 3 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40;
-                break;
-            case 4 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20;
-                break;
-            case 5 : l_dram_rtt_nom[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30;
-                break;
-            default: FAPI_ERR("Invalid SPD LR MR1,2 DRAM RTT_NOM on %s!", i_target_mba.toEcmdString());
-                uint8_t& L_DRAM_RTT_NOM = l_dram_rtt_nom[l_port][l_dimm];
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_SPD_RTT_NOM);
-                return rc;
-         }
-
-         switch (l_dram_rtt_wr[l_port][l_dimm]) {
-            case 0 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE;
-                break;
-            case 1 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60;
-                break;
-            case 2 : l_dram_rtt_wr[l_port][l_dimm] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120;
-                break;
-            default: FAPI_ERR("Invalid SPD LR MR1,2 DRAM RTT_WR on %s!", i_target_mba.toEcmdString());
-                uint8_t& L_DRAM_RTT_WR = l_dram_rtt_wr[l_port][l_dimm];
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_LRDIMM_INVALID_SPD_RTT_WR);
-                return rc;
-         }
-
-         uint8_t l_rank;
-         for ( l_rank = 0; l_rank < RANK_SIZE; l_rank++ ) {           // clear RTT_NOM & RTT_WR
-            attr_eff_dram_rtt_nom[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE;
-            attr_eff_dram_rtt_wr[l_port][l_dimm][l_rank] = fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE;
-         }
-
-         if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 0 ) { // Set RTT_NOM Rank 0 for multi rank LRDIMM
-            attr_eff_dram_rtt_nom[l_port][l_dimm][0] = l_dram_rtt_nom[l_port][l_dimm]; // set attr_eff_dram_rtt_nom[0][0][0]
-            attr_eff_dram_rtt_wr[l_port][l_dimm][0] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][0]
-
-            FAPI_INF("Setting Port0 Rank 0 LRDIMM RTT_NOM & RTT_WR from SPD LR MR1,2");
-
-            if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) { // Set RTT_NOM Rank 1 for 4rank or 8rank LRDIMM
-               attr_eff_dram_rtt_nom[l_port][l_dimm][1] = l_dram_rtt_nom[l_port][l_dimm]; // set attr_eff_dram_rtt_nom[0][0][1]
-               attr_eff_dram_rtt_wr[l_port][l_dimm][1] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][1]
-
-               attr_eff_dram_rtt_wr[l_port][l_dimm][2] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][2]
-               attr_eff_dram_rtt_wr[l_port][l_dimm][3] = l_dram_rtt_wr[l_port][l_dimm]; // set attr_eff_dram_rtt_wr[0][0][3]
-               FAPI_INF("Setting Port0 Rank 1+ LRDIMM RTT_NOM & RTT_WR from SPD LR MR1,2");
-            }
-         }
-
-//-------------------------------------------------------------------------------------------------------------
-
-         // Set ODT_WR for each valid rank as single RDIMM rank value.
-         if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] > 1 ) { // SET ODT_WR Rank 1 for multi rank LRDIMM (8R or 4R)
-            attr_eff_odt_wr[l_port][l_dimm][1] = attr_eff_odt_wr[l_port][l_dimm][0]; // set attr_eff_odt_wr[0][0][1] to attr_eff_odt_wr[0][0][0]
-            if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) { // Set ODT_WR Rankd 2,3 for 4 rank LRDIMM
-               attr_eff_odt_wr[l_port][l_dimm][2] = attr_eff_odt_wr[l_port][l_dimm][0]; // set attr_eff_odt_wr[0][0][2] to attr_eff_odt_wr[0][0][0]
-               attr_eff_odt_wr[l_port][l_dimm][3] = attr_eff_odt_wr[l_port][l_dimm][0]; // set attr_eff_odt_wr[0][0][3] to attr_eff_odt_wr[0][0][0]
-            }
-         }
-
-      } // end dimm loop
-   } // end port loop
-
-   // Set adjusted attributes
-   rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_eff_dram_ron); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_eff_dram_rtt_nom); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_eff_dram_rtt_wr); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_VPD_ODT_WR, &i_target_mba, attr_eff_odt_wr); if(rc) return rc;
-
-   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-
-   return rc;
-}
-
-fapi::ReturnCode mss_spec_rcd_load( fapi::Target& i_target,  uint32_t i_port_number, uint8_t  *p_i_rcd_num_arr, uint8_t i_rcd_num_arr_length, uint64_t  i_rcd_word[], uint32_t& io_ccs_inst_cnt,uint8_t i_keep_cke_high)
-{
-    const uint8_t MAX_NUM_PORTS=2;
-    const uint8_t MAX_NUM_DIMMS=2;
-    ReturnCode rc;
-    ReturnCode rc_buff;
-    uint32_t rc_num = 0;
-    uint32_t dimm_number;
-    uint8_t spec_rcd;
-
-    ecmdDataBufferBase rcd_cntl_wrd_4(8);
-    ecmdDataBufferBase rcd_cntl_wrd_64(64);
-    uint16_t num_ranks;
-
-    uint16_t num_idles_delay = 20; // default=12 klc
-
-    ecmdDataBufferBase address_16(16);
-    ecmdDataBufferBase bank_3(3);
-    ecmdDataBufferBase activate_1(1);
-    ecmdDataBufferBase rasn_1(1);
-    rc_num = rc_num | rasn_1.setBit(0);
-    ecmdDataBufferBase casn_1(1);
-    rc_num = rc_num | casn_1.setBit(0);
-    ecmdDataBufferBase wen_1(1);
-    rc_num = rc_num | wen_1.setBit(0);
-    ecmdDataBufferBase cke_4(4);
-    if (i_keep_cke_high == 1)
-        rc_num = rc_num | cke_4.setBit(0,4);
-    else
-        rc_num = rc_num | cke_4.clearBit(0,4);
-    ecmdDataBufferBase csn_8(8);
-    rc_num = rc_num | csn_8.setBit(0,8);
-    ecmdDataBufferBase odt_4(4);
-    rc_num = rc_num | odt_4.setBit(0,4);
-    ecmdDataBufferBase ddr_cal_type_4(4);
-
-    ecmdDataBufferBase num_idles_16(16);
-    ecmdDataBufferBase num_repeat_16(16);
-    ecmdDataBufferBase data_20(20);
-    ecmdDataBufferBase read_compare_1(1);
-    ecmdDataBufferBase rank_cal_4(4);
-    ecmdDataBufferBase ddr_cal_enable_1(1);
-    ecmdDataBufferBase ccs_end_1(1);
-
-    uint8_t num_ranks_array[MAX_NUM_PORTS][MAX_NUM_DIMMS]; //[port][dimm]
-
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_array);
-    if(rc) return rc;
-
-    FAPI_INF( "+++++++++++++++++++++ LOADING RCD CONTROL WORD FOR PORT %d +++++++++++++++++++++", i_port_number);
-
-    for ( dimm_number = 0; dimm_number < MAX_NUM_DIMMS; dimm_number++)
-    {
-        num_ranks = num_ranks_array[i_port_number][dimm_number];
-
-        if (num_ranks == 0)
-        {
-            FAPI_INF( "PORT%d DIMM%d not configured. Num_ranks: %d", i_port_number, dimm_number, num_ranks);
-        }
-        else
-        {
-            FAPI_INF( "RCD SETTINGS FOR PORT%d DIMM%d ", i_port_number, dimm_number);
-            FAPI_INF( "RCD Control Word: 0x%016llX", i_rcd_word[dimm_number]);
-            FAPI_INF( "Loading function specific RCD Control Words");
-
-            if (rc_num)
-            {
-                FAPI_ERR( "mss_spec_rcd_load: Error setting up buffers");
-                rc_buff.setEcmdError(rc_num);
-                return rc_buff;
-            }
-
-            rc_num = rc_num | csn_8.setBit(0,8);        // reset CS lines
-            // for dimm0 use CS0,1 (active low); for dimm1 use CS4,5 (active low)
-            rc_num = rc_num | csn_8.clearBit( (dimm_number * 4), 2 );
-            // set specific control words
-            for ( spec_rcd = 0; spec_rcd < i_rcd_num_arr_length; spec_rcd++ )
-            {
-               rc_num = rc_num | bank_3.clearBit(0, 3);
-               rc_num = rc_num | address_16.clearBit(0, 16);
-
-               rc_num = rc_num | rcd_cntl_wrd_64.setDoubleWord(0, i_rcd_word[dimm_number]);
-               rc_num = rc_num | rcd_cntl_wrd_64.extract(rcd_cntl_wrd_4, 4*p_i_rcd_num_arr[spec_rcd], 4);
-
-               //control word number code bits A0, A1, A2, BA2
-               rc_num = rc_num | bank_3.insert(p_i_rcd_num_arr[spec_rcd], 2, 1, 4);  // BA2(MSB) from array bit 4
-               rc_num = rc_num | address_16.insert(p_i_rcd_num_arr[spec_rcd], 2, 1, 5);  // A2
-               rc_num = rc_num | address_16.insert(p_i_rcd_num_arr[spec_rcd], 1, 1, 6);  // A1
-               rc_num = rc_num | address_16.insert(p_i_rcd_num_arr[spec_rcd], 0, 1, 7);  // A0
-
-               //control word values RCD0 = A3, RCD1 = A4, RCD2 = BA0, RCD3 = BA1
-               rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 1, 1, 0);                        // BA1 (MSB)
-               rc_num = rc_num | bank_3.insert(rcd_cntl_wrd_4, 0, 1, 1);                        // BA0
-               rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 4, 1, 2);            // A4
-               rc_num = rc_num | address_16.insert(rcd_cntl_wrd_4, 3, 1, 3);            // A3
-
-               FAPI_INF("Loading RCD %d (0x%02x) = 0x%01X",  p_i_rcd_num_arr[spec_rcd],
-                                           p_i_rcd_num_arr[spec_rcd],
-                                           (rcd_cntl_wrd_4.getByte(0)>>4));
-
-               // Send out to the CCS array
-               rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) num_idles_delay, 0, 16);
-               rc = mss_ccs_inst_arry_0( i_target,
-                                         io_ccs_inst_cnt,
-                                         address_16,
-                                         bank_3,
-                                         activate_1,
-                                         rasn_1,
-                                         casn_1,
-                                         wen_1,
-                                         cke_4,
-                                         csn_8,
-                                         odt_4,
-                                         ddr_cal_type_4,
-                                         i_port_number);
-               if(rc) return rc;
-               rc = mss_ccs_inst_arry_1( i_target,
-                                         io_ccs_inst_cnt,
-                                         num_idles_16,
-                                         num_repeat_16,
-                                         data_20,
-                                         read_compare_1,
-                                         rank_cal_4,
-                                         ddr_cal_enable_1,
-                                         ccs_end_1);
-               if(rc) return rc;
-               io_ccs_inst_cnt ++;
-
-               if (rc_num)
-               {
-                   FAPI_ERR( "mss_rcd_load: Error setting up buffers");
-                   rc_buff.setEcmdError(rc_num);
-                   return rc_buff;
-               }
-           } //end control word loop
-        } // end valid rank
-    } // end dimm loop
-    return rc;
-}
-
-#endif
diff --git a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H
deleted file mode 100644
index f478d8aa3..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H
+++ /dev/null
@@ -1,167 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs/mss_lrdimm_funcs.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_lrdimm_funcs.H,v 1.2 2013/09/16 13:28:55 bellows Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_lrdimm_funcs.H
-// *! DESCRIPTION : Tools for lrdimm centaur procedures
-// *! OWNER NAME : KCOOK
-// *! BACKUP NAME : MWUU
-// #! ADDITIONAL COMMENTS :
-//
-// CCS related and general utility functions.
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.2    | 09/16/13 | bellows | Added ID tag
-//  1.1    | 08/27/13 | kcook   | First drop of Centaur
-
-#ifndef _MSS_LRDIMM_FUNCS_H
-#define _MSS_LRDIMM_FUNCS_H
-
-//#define LRDIMM 1
-
-//----------------------------------------------------------------------
-//  Constants 
-//----------------------------------------------------------------------
-const uint8_t PORT = 2;
-const uint8_t DIMM = 2;
-const uint8_t RANK = 4;
-//----------------------------------------------------------------------
-//  Enums 
-//----------------------------------------------------------------------
-
-struct mss_lrdimm_spd_data 
-{
-    uint8_t lr_addr_mirroring[PORT][DIMM];
-    uint8_t lr_f0rc3_f0rc2[PORT][DIMM];
-    uint8_t lr_f0rc5_f0rc4[PORT][DIMM];
-    uint8_t lr_f1rc11_f1rc8[PORT][DIMM];
-    uint8_t lr_f1rc13_f1rc12[PORT][DIMM];
-    uint8_t lr_f1rc15_f1rc14[PORT][DIMM];
-    uint8_t lr_f3rc9_f3rc8_for_800_1066[PORT][DIMM];
-    uint8_t lr_f34rc11_f34rc10_for_800_1066[PORT][DIMM];
-    uint8_t lr_f56rc11_f56rc10_for_800_1066[PORT][DIMM];
-    uint8_t lr_f78rc11_f78rc10_for_800_1066[PORT][DIMM];
-    uint8_t lr_f910rc11_f910rc10_for_800_1066[PORT][DIMM];
-    uint8_t lr_mr12_for_800_1066[PORT][DIMM];
-    uint8_t lr_f3rc9_f3rc8_for_1333_1600[PORT][DIMM];
-    uint8_t lr_f34rc11_f34rc10_for_1333_1600[PORT][DIMM];
-    uint8_t lr_f56rc11_f56rc10_for_1333_1600[PORT][DIMM];
-    uint8_t lr_f78rc11_f78rc10_for_1333_1600[PORT][DIMM];
-    uint8_t lr_f910rc11_f910rc10_for_1333_1600[PORT][DIMM];
-    uint8_t lr_mr12_for_1333_1600[PORT][DIMM];
-    uint8_t lr_f3rc9_f3rc8_for_1866_2133[PORT][DIMM];
-    uint8_t lr_f34rc11_f34rc10_for_1866_2133[PORT][DIMM];
-    uint8_t lr_f56rc11_f56rc10_for_1866_2133[PORT][DIMM];
-    uint8_t lr_f78rc11_f78rc10_for_1866_2133[PORT][DIMM];
-    uint8_t lr_f910rc11_f910rc10_for_1866_2133[PORT][DIMM];
-    uint8_t lr_mr12_for_1866_2133[PORT][DIMM];
-};
-
-
-//----------------------------------------------------------------------
-// LRDIMM FUNCS
-//----------------------------------------------------------------------
-
-//--------------------------------------------------------------
-// mss_lrimm_rcd_load
-// Set Function 1-13 RCD words
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_rcd_load( fapi::Target& i_target, 
-                                      uint32_t port_number,
-                                      uint32_t& ccs_inst_cnt );
-
-//--------------------------------------------------------------
-// mss_lrdimm_mrs_load
-// Set MRS1 settings for Rank 0 and Rank 1
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_mrs_load( fapi::Target& i_target,
-                                      uint32_t i_port_number,
-                                      uint32_t dimm_number,
-                                      uint32_t& io_ccs_inst_cnt);
-//--------------------------------------------------------------
-// mss_execute_lrdimm_mb_dram_training
-// run lrdimm memory buffer training
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_execute_lrdimm_mb_dram_training( fapi::Target& i_target); 
-
-//--------------------------------------------------------------
-// mss_lrdimm_eff_config
-// run lrdimm attribute set up
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_eff_config( const fapi::Target& i_target_mba,
-                                  uint8_t cur_dimm_spd_valid_u8array[PORT][DIMM],
-                                  uint32_t mss_freq,
-                                  uint8_t eff_num_ranks_per_dimm[PORT][DIMM]);
-
-//--------------------------------------------------------------
-// mss_lrdimm_rewrite_odt
-// eff config termination rewrite odts for dual drop
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_rewrite_odt( const fapi::Target& i_target_mba,
-                                         uint32_t *p_b_var_array,
-                                         uint32_t *var_array_p_array[5]);
-
-
-//--------------------------------------------------------------
-// mss_lrdimm_term_atts  
-// eff config termination rewrite odts for dual drop
-// Target = centaur.mba
-//--------------------------------------------------------------
-fapi::ReturnCode mss_lrdimm_term_atts( const fapi::Target& i_target_mba);
-
-
-
-//-----------------------------------------
-// mss_spec_rcd_load
-// execute RCD loads of specific control words. For LRDIMM.
-// Target = centaur.mba
-//-----------------------------------------
-fapi::ReturnCode mss_spec_rcd_load(fapi::Target& i_target,
-                                   uint32_t i_port_number,
-                                   uint8_t * p_i_rcd_num_arr,
-                                   uint8_t i_rcd_num_arr_length,
-                                   uint64_t  i_rcd_word[],
-                                   uint32_t& io_ccs_inst_cnt,
-                                   uint8_t i_keep_cke_high=0);
-
-
-
-#endif /* _MSS_LRDIMM_FUNCS_H */
-
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
deleted file mode 100644
index c9ae89d86..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
+++ /dev/null
@@ -1,244 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_scominit.C,v 1.19 2014/08/05 15:06:52 kahnevan Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_scominit
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Menlo Wuu         Email: menlowuu@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure execute memory initfiles in proper sequence.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//	 1.18  | menlowuu |14-NOV-13| Added Mike Jones changes for callouts
-//	 1.17  | menlowuu |02-JUL-13| Fixed vector insert for L4 targets
-//	 1.16  | menlowuu |02-JUL-13| Added L4 targets for MBS initfile
-//	 1.15  | menlowuu |11-NOV-12| Removed include of dimmBadDqBitmapFuncs.H>
-//   1.14  | menlowuu |09-NOV-12| Removed mss_set_bbm_regs FN since now handled
-//  							  in draminit_training.
-//   1.13  | menlowuu |26-SEP-12| Changed ORing of port to SCOM address
-//   1.12  | menlowuu |19-SEP-12| Fixed some return codes.
-//   1.11  | menlowuu |22-AUG-12| Added return code for mss_set_bbm_regs FN.
-//   1.10  | menlowuu |21-AUG-12| Removed running *_mcbist files since it was
-//      					moved into the *_def files.
-//   1.9   | menlowuu |15-AUG-12| Added disable bit set FN, reused rc, added
-//   					mbs/mba_mcbist.if to the scominit FN.
-//   1.8   | bellows  |16-JUL-12| added in Id tag
-//   1.7   | menlowuu |14-JUN-12| Added fixes suggested by Mike,
-//	 					replace rc_num with ReturnCode, created RC for when
-//	 					MBAs != 2, and return on all errors
-//   1.6   | menlowuu |08-JUN-12| Fixed inserting centaur vector & return code.
-//   1.5   | menlowuu |06-JUN-12| Added code to use
-//  		 primary centaur target, secondary mba[0/1] for mbs.if;
-//   		 primary mba[0|1] target, secondary centaur for mba.if, phy.if
-//   1.4   | menlowuu |05-JUN-12| Added vector target for fapiHwpExecInitFile
-//   1.3   | menlowuu |15-MAY-12| Added fapi namespace to rc_num definition
-//   0.1   | menlowuu |01-DEC-11| First Draft.
-
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-#include <mss_scominit.H>
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-#include <fapiHwpExecInitFile.H>
-
-//----------------------------------------------------------------------
-//  Constants
-//----------------------------------------------------------------------
-#define MAX_PORTS 2
-#define MAX_PRI_RANKS 4
-#define TOTAL_BYTES 10
-
-extern "C" {
-    using namespace fapi;
-
-//******************************************************************************
-//
-//******************************************************************************
-ReturnCode mss_scominit(const Target & i_target) {
-
-	ReturnCode rc;
-	std::vector<Target> vector_targets, vector_l4_targets;
-	const char* mbs_if[] = {
-		"mbs_def.if",
-		/* "mbs_mcbist.if"	// moved into mbs_def file */
-	};
-	const char* mba_if[] = {
-		"mba_def.if",
-		/* "mba_mcbist.if",	// moved into mba_def file */
-		"cen_ddrphy.if"
-	};
-
-	FAPI_INF("Performing HWP: mss_scominit");
-
-	// Print the ecmd string of the chip
-	FAPI_INF("Input Target: %s", i_target.toEcmdString());
-
-	// Get a vector of the present MBA targets
-	rc = fapiGetChildChiplets(i_target, TARGET_TYPE_MBA_CHIPLET,
-							vector_targets, TARGET_STATE_PRESENT);
-
-	if (rc)
-	{
-		FAPI_ERR("Error from fapiGetChildChiplets getting present MBA's!");
-		FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc));
-		return (rc);
-	}
-	else if (vector_targets.size() != 2)
-	{
-		FAPI_ERR("fapiGetChildChiplets returned %zd present MBAs, expected 2",
-                 vector_targets.size());
-        uint32_t NUM_MBAS = vector_targets.size();
-		FAPI_SET_HWP_ERROR(rc, RC_MSS_SCOMINIT_NUM_MBA_ERROR);
-		return (rc);
-	}
-	else
-	{
-		// insert centaur target at beginning of vector
-		vector_targets.insert(vector_targets.begin(),i_target);
-
-		FAPI_INF("Getting L4 targets");
-		// Get L4 vectors
-		rc = fapiGetChildChiplets(i_target, TARGET_TYPE_L4,
-								vector_l4_targets, TARGET_STATE_PRESENT);
-
-		if (rc)
-		{
-			FAPI_ERR("Error from fapiGetChildChiplets getting L4 targets!");
-			FAPI_ERR("RC = 0x%x", static_cast<uint32_t>(rc));
-			return (rc);
-		}
-		
-		if (vector_l4_targets.size() != 1)
-		{
-			FAPI_ERR("fapiGetChildChiplets returned %zd present L4s, expected 1",
-                     vector_l4_targets.size());
-            uint32_t NUM_L4S = vector_l4_targets.size();
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_SCOMINIT_NUM_L4_ERROR);
-			return (rc);
-		}
-
-		// insert L4 targets at the end	
-		vector_targets.insert(vector_targets.end(),vector_l4_targets.begin(), vector_l4_targets.end());
-
-		// run mbs initfile...
-		uint8_t num_mbs_files = sizeof(mbs_if)/sizeof(char*);
-		for (uint8_t itr=0; itr < num_mbs_files; itr++)
-		{
-			FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, vector_targets, mbs_if[itr]);
-
-			if (rc)
-			{
-				FAPI_ERR("  !!!  Error running MBS %s, RC = 0x%x",
-						mbs_if[itr], static_cast<uint32_t>(rc));
-				return (rc);
-			}
-			else
-			{
-				FAPI_INF("MBS scom initfile %s passed", mbs_if[itr]);
-			}
-		}
-	}
-
-	// Clear vector targets
-	vector_targets.clear();
-
-	// Get a vector of the functional MBA targets
-	rc=fapiGetChildChiplets(i_target, TARGET_TYPE_MBA_CHIPLET, vector_targets);
-
-	if (rc)
-	{
-		FAPI_ERR("Error from fapiGetChildChiplets getting functional MBA's!");
-		return (rc);
-	}
-	else
-	{
-		uint8_t l_unitPos = 0;
-
-		FAPI_INF("Found %zi functional MBA chiplets", vector_targets.size());
-
-		// Iterate through the returned chiplets
-		for (uint32_t i = 0; i < vector_targets.size(); i++)
-		{
-			// Find the position of the MBA chiplet
-			rc=FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &vector_targets[i], l_unitPos);
-
-			if (rc)
-			{
-				FAPI_ERR("Error getting ATTR_CHIP_UNIT_POS for MBA");
-				return (rc);
-			}
-			else
-			{
-				std::vector<Target> mba_cen_targets;
-
-				FAPI_INF("MBA%i valid", l_unitPos);
-
-				// push current mba target then centaur target
-				mba_cen_targets.push_back(vector_targets[i]);
-				mba_cen_targets.push_back(i_target);
-
-				// run mba initfiles...
-				uint8_t num_mba_files = sizeof(mba_if)/sizeof(char*);
-				for (uint8_t itr=0; itr < num_mba_files; itr++)
-				{
-					FAPI_EXEC_HWP(rc, fapiHwpExecInitFile, mba_cen_targets,
-							mba_if[itr]);
-
-					if (rc)
-					{
-						FAPI_ERR("  !!!  Error running MBA %s, RC = 0x%x",
-								mba_if[itr], static_cast<uint32_t>(rc));
-						return (rc);
-					}
-					else
-					{
-						FAPI_INF("MBA scom initfile %s passed", mba_if[itr]);
-					}
-				} // end for loop, running MBA/PHY initfiles
-			} // end else, MBA fapiHwpExecInitFile
-		} // end for loop, valid chip unit pos
-	} // found functional MBAs
-
-	return (rc);
-} // end mss_scominit
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
deleted file mode 100644
index 68946c1e8..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
+++ /dev/null
@@ -1,85 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_scominit.H,v 1.7 2012/11/10 02:53:17 mwuu Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_scominit.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Menlo Wuu         Email: menlowuu@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_scominit.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.7   | menlowuu |09-NOV-12| Removed mss_set_bbm_regs since now done in
-//   							  draminit_training
-//   1.6   | menlowuu |15-AUG-12| added bad bitmask function
-//   1.5   |bellows   |16-JUL-12| added in Id tag
-//   1.4   | menlowuu |20-JUN-12| added type to the typedef
-//   1.3   | menlowuu |13-JUN-12| added & to reference i_target in FP_t function
-//	 							  added comment expecting centaur target
-//   1.2   | menlowuu |06-JUN-12| Removed char* parameter for function
-//   0.1   | menlowuu |01-DEC-11| First Draft.
-
-
-#ifndef MSS_SCOMINIT_H_
-#define MSS_SCOMINIT_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_scominit_FP_t)(const fapi::Target & i_target);
-
-extern "C" {
-
-//******************************************************************************
-// mss_scominit
-//******************************************************************************
-// mss_scominit procedure [Calls the vaious memory initfiles]
-// param[in] i_target [Reference to target, expecting centaur(MEMBUF) target]
-// return ReturnCode
-
-fapi::ReturnCode mss_scominit(const fapi::Target & i_target);
-
-} // extern "C"
-
-#endif // MSS_SCOMINIT_H_
diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C b/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
deleted file mode 100644
index c18bce0dd..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.C
+++ /dev/null
@@ -1,1620 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_termination_control.C $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_termination_control.C,v 1.27 2014/02/25 21:08:15 mwuu Exp $
-/* File is created by SARAVANAN SETHURAMAN on Thur 29 Sept 2011. */
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE :mss_draminit_training_advanced.C
-// *! DESCRIPTION : Tools for centaur procedures
-// *! OWNER NAME : Saravanan Sethuraman          email ID:saravanans@in.ibm.com
-// *! BACKUP NAME: Menlo Wuu	 	         email ID:menlowuu@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-// General purpose funcs
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.27   | mwuu     |25-Feb-14| Fixed setting opposite port slew values in 
-//         |          |         | config_slew_rate
-//  1.26   | mjjones  |31-Jan-14| RAS Reviewed 
-//  1.25   | mjjones  |22-Jan-14| Removed firmware header
-//  1.24   | abhijsau |21-Jan-14| mike and menlo fixed ras review comments
-//  1.23   | bellows  |02-Dec-13| VPD attribute update
-//  1.22   | mwuu     |20-Sep-13| Updated ADR DDR3 slew calibration table for 1 setting,
-//  							  1066 20ohms, 4V/ns, changed from 11 to 10.
-//  1.21   | sasethur |16-Apr-13| Added DDR4 settings for rd_vref
-//  1.20   | sasethur |09-Apr-13| Changed wr_vref register settings as per ddr3spec
-//  1.19   | sasethur |05-Apr-13| Updated for port in parallel 
-//  1.18   | mwuu     |25-Feb-13| Added return code per port for config slew FN
-//  1.17   | mwuu     |07-Feb-13| Improved the debug and trace messages.
-//  1.16   | mwuu     |24-Jan-13| Fixed cal_slew extraction of bits.
-//  1.15   | mwuu     |14-Jan-13| Altered error message for unsupported slew rate
-//  1.14   | mwuu     |14-Jan-13| Removed error messages from slew cal fail when
-//         |          |         | in SIM and using unsupported slew rates.
-//  1.13   | mwuu     |18-Dec-12| Took out initialization of array_rcs in declaration.
-//  1.12   | mwuu     |14-Dec-12| Updated additional fw review comments
-//  1.11   | sasethur |07-Dec-12| Updated for fw review comments
-//  1.10   | mwuu     |28-Nov-12| Added changes suggested from FW team.
-//  1.9    | mwuu     |20-Nov-12| Changed warning status to not cause error.
-//  1.8    | sasethur |19-Nov-12| Updated for fw review comments
-//  1.7	   | mwuu     |14-Nov-12| Switched some old attributes to new, added
-//  							  Partial good support in slew_cal FN.
-//  1.6    | bellows  |13-Nov-12| SI attribute Updates
-//  1.5    | mwuu     |29-Oct-12| fixed config_drv_imp missed a '&'
-//  1.4    | mwuu     |26-Oct-12| Added mss_slew_cal FN, not 100% complete
-//  1.3    | sasethur |26-Oct-12| Updated FW review comments - fapi::, const fapi:: Target
-//  1.2    | mwuu     |17-Oct-12| Updated return codes to use common error, also
-//         |          |         | updates to the slew function
-//  1.1    | sasethur |15-Oct-12| Functions defined & moved from training adv,
-//  							  Menlo upated slew function
-
-// Saravanan - Yet to update DRV_IMP new attribute enum change
-
-// Not supported
-// DDR4, DIMM Types
-//----------------------------------------------------------------------
-//  Includes - FAPI
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-
-//----------------------------------------------------------------------
-//Centaur functions
-//----------------------------------------------------------------------
-#include <mss_termination_control.H>
-#include <cen_scom_addresses.H>
-#include <mss_draminit_training_advanced.H>
-
-/*------------------------------------------------------------------------------
- * Function: config_drv_imp()
- * This function will configure the Driver impedance values to the registers
- *
- * Parameters: target: mba;		port: 0, 1
- * Driver_imp: OHM24 = 24, OHM30 = 30, OHM34 = 34, OHM40 = 40
- * ---------------------------------------------------------------------------*/
-
-fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_drv_imp_dq_dqs)
-{
-
-    ecmdDataBufferBase data_buffer(64);
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint8_t enslice_drv = 0xFF;
-    uint8_t enslice_ffedrv = 0xF;
-    uint8_t i = 0;
-
-    //Driver impedance settings are per PORT basis
-
-    if (i_port > 1)
-    {
-	FAPI_ERR("Driver impedance port input(%u) out of bounds", i_port);
-	const uint8_t & PORT_PARAM = i_port;
-	FAPI_SET_HWP_ERROR(rc, RC_CONFIG_DRV_IMP_INVALID_INPUT);
-	return rc;
-    }
-    for(i=0; i< MAX_DRV_IMP; i++)
-    {
-	if (drv_imp_array[i] == i_drv_imp_dq_dqs)
-	{
-	    switch (i)
-	    {
-		case 0:   //40 ohms
-		enslice_drv = 0x3C;
-		enslice_ffedrv =0xF;
-		break;
-		case 1:   //34 ohms
-		enslice_drv = 0x7C;
-		enslice_ffedrv =0xF;
-		break;
-		case 2:  //30 ohms
-		enslice_drv = 0x7E;
-		enslice_ffedrv = 0xF;
-		break;
-		case 3:   //24 ohms
-		enslice_drv = 0xFF;
-		enslice_ffedrv = 0xF;
-		break;
-            }
-	break;
-	}
-    }
-
-        rc = fapiGetScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F,
-		    data_buffer); if(rc) return rc;
-	rc_num = data_buffer.insertFromRight(enslice_drv,48,8);
-        rc_num = rc_num | data_buffer.insertFromRight(enslice_ffedrv,56,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_drv_imp: Error in setting up buffer ");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_0_0x800000780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_1_0x800004780301143F,
-		    data_buffer); if(rc) return rc;
-        rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_2_0x800008780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_3_0x80000C780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P0_4_0x800010780301143F,
-		    data_buffer); if(rc) return rc;
-       	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_0_0x800000790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_1_0x800004790301143F,
-		    data_buffer); if(rc) return rc;
-        rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_2_0x800008790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_3_0x80000C790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P0_4_0x800010790301143F,
-		    data_buffer); if(rc) return rc;
-        
- 	rc = fapiGetScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F,
-		    data_buffer); if(rc) return rc;
-	rc_num = data_buffer.insertFromRight(enslice_drv,48,8);
-        rc_num = rc_num | data_buffer.insertFromRight(enslice_ffedrv,56,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_drv_imp: Error in setting up buffer ");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_0_0x800100780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_1_0x800104780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_2_0x800108780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_3_0x80010C780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_SLICE_P1_4_0x800110780301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_0_0x800100790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_1_0x800104790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_2_0x800108790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_3_0x80010C790301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_SLICE_P1_4_0x800110790301143F,
-		    data_buffer); if(rc) return rc;
-    return rc;
-}
-
-
-/*------------------------------------------------------------------------------
- * Function: config_rcv_imp()
- * This function will configure the Receiver impedance values to the registers
- *
- * Parameters: target: mba;		port: 0, 1
- * receiver_imp:OHM15 = 15, OHM20 = 20, OHM30 = 30, OHM40 = 40, OHM48 = 48,
- * OHM60 = 60,  OHM80 = 80, OHM120 = 120, OHM160 = 160, OHM240 = 240
- * ---------------------------------------------------------------------------*/
-
-fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba, uint8_t i_port, uint8_t i_rcv_imp_dq_dqs)
-{
-
-    ecmdDataBufferBase data_buffer(64);
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint8_t enslicepterm = 0xFF;
-    uint8_t enslicepffeterm = 0;
-    uint8_t i = 0;
-
-    if (i_port > 1)
-    {
-	FAPI_ERR("Receiver impedance port input(%u) out of bounds", i_port);
-	const uint8_t & PORT_PARAM = i_port;
-	FAPI_SET_HWP_ERROR(rc, RC_CONFIG_RCV_IMP_INVALID_INPUT);
-	return rc;
-    }
-
-
-    for(i=0; i< MAX_RCV_IMP; i++)
-    {
-	if (rcv_imp_array[i] == i_rcv_imp_dq_dqs)
-	{
-            switch (i)
-   	    {
- 		case 0:  //120 OHMS
-		enslicepterm = 0x10;
-		enslicepffeterm =0x0;
-		break;
-	        case 1:   //80 OHMS
-		enslicepterm = 0x10;
-		enslicepffeterm =0x2;
-		break;
-	        case 2:   //60 OHMS
-		enslicepterm = 0x18;
-		enslicepffeterm =0x0;
-		break;
-	        case 3:   //48 OHMS
-		enslicepterm = 0x18;
-		enslicepffeterm =0x2;
-		break;
-	        case 4:   //40 OHMS
-		enslicepterm = 0x18;
-		enslicepffeterm =0x6;
-		break;
-	        case 5:   //34 OHMS
-		enslicepterm = 0x38;
-		enslicepffeterm =0x2;
-		break;
-	        case 6:   //30 OHMS
-		enslicepterm = 0x3C;
-		enslicepffeterm =0x0;
-		break;
-	        case 7:   //20 OHMS
-		enslicepterm = 0x7E;
-		enslicepffeterm = 0x0;
-		break;
-  	        case 8:    //15 OHMS
-		enslicepterm = 0xFF;
-		enslicepffeterm = 0x0;
-		break;
- 	    }
-	break;
-	}
-    }
-
-
-        rc = fapiGetScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc_num = data_buffer.insertFromRight(enslicepterm,48,8);
-        rc_num = rc_num | data_buffer.insertFromRight(enslicepffeterm,56,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_rcv_imp: Error in setting up buffer ");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_0_0x8000007A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_1_0x8000047A0301143F,
-		    data_buffer); if(rc) return rc;
-        rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_2_0x8000087A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_3_0x80000C7A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P0_4_0x8000107A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_0_0x8000007B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_1_0x8000047B0301143F,
-		    data_buffer); if(rc) return rc;
-        rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_2_0x8000087B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_3_0x80000C7B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P0_4_0x8000107B0301143F,
-		    data_buffer); if(rc) return rc;
-        
-	rc = fapiGetScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc_num = data_buffer.insertFromRight(enslicepterm,48,8);
-        rc_num = rc_num | data_buffer.insertFromRight(enslicepffeterm,56,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_rcv_imp: Error in setting up buffer ");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_0_0x8001007A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_1_0x8001047A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_2_0x8001087A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_3_0x80010C7A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_NFET_TERM_P1_4_0x8001107A0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_0_0x8001007B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_1_0x8001047B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_2_0x8001087B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_3_0x80010C7B0301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_IO_TX_PFET_TERM_P1_4_0x8001107B0301143F,
-		    data_buffer); if(rc) return rc;
-    return rc;
-}
-
-/*------------------------------------------------------------------------------
- * Function: config_slew_rate()
- * This function will configure the Slew rate values to the registers
- *
- * Parameters: target: mba;		port: 0, 1
- * i_slew_type: SLEW_TYPE_DATA=0, SLEW_TYPE_ADR_ADDR=1, SLEW_TYPE_ADR_CNTL=2
- * i_slew_imp: OHM15=15, OHM20=20, OHM24=24, OHM30=30, OHM34=34, OHM40=40
- *		note: 15, 20, 30, 40 valid for ADR; 24, 30, 34, 40 valid for DATA
- * i_slew_rate: SLEW_3V_NS=3, SLEW_4V_NS=4, SLEW_5V_NS=5, SLEW_6V_NS=6,
- * SLEW_MAXV_NS=7 (note SLEW_MAXV_NS bypasses slew calibration.)
- * ---------------------------------------------------------------------------*/
-fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba,
-	const uint8_t i_port, const uint8_t i_slew_type, const uint8_t i_slew_imp,
-	const uint8_t i_slew_rate)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase data_buffer(64);
-    uint32_t rc_num = 0;
-    uint8_t slew_cal_value = 0;
-    uint8_t imp_idx = 255;
-    uint8_t slew_idx = 255;
-    // array for ATTR_MSS_SLEW_RATE_DATA/ADR [2][4][4]
-	// port,imp,slew_rat	cal'd slew settings
-    uint8_t calibrated_slew_rate_table
-		[MAX_NUM_PORTS][MAX_NUM_IMP][MAX_NUM_CAL_SLEW_RATES]={{{0}}};
-
-    // FFDC for bad parameters
-    const uint8_t & PORT_PARAM = i_port;
-    const uint8_t & SLEW_TYPE_PARAM = i_slew_type;
-    const uint8_t & SLEW_IMP_PARAM = i_slew_imp;
-    const uint8_t & SLEW_RATE_PARAM = i_slew_rate;
-
-    if (i_port >= MAX_NUM_PORTS)
-    {
-		FAPI_ERR("Slew port input(%u) out of bounds", i_port);
-		FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT);
-		return rc;
-    }
-
-    if (i_slew_type >= MAX_NUM_SLEW_TYPES)
-    {
-		FAPI_ERR("Slew type input(%u) out of bounds, (>= %u)",
-				i_slew_type, MAX_NUM_SLEW_TYPES);
-		FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT);
-		return rc;
-    }
-
-	switch (i_slew_rate)		// get slew index
-	{
-		case SLEW_MAXV_NS:			// max slew
-			FAPI_INF("Slew rate is set to MAX, using bypass mode");
-			slew_cal_value = 0;		// slew cal value for bypass mode
-			break;
-		case SLEW_6V_NS:
-			slew_idx = 3;
-			break;
-		case SLEW_5V_NS:
-			slew_idx = 2;
-			break;
-		case SLEW_4V_NS:
-			slew_idx = 1;
-			break;
-		case SLEW_3V_NS:
-			slew_idx = 0;
-			break;
-		default:
-			FAPI_ERR("Slew rate input(%u) out of bounds", i_slew_rate);
-			FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT);
-			return rc;
-    }
-
-    if (i_slew_type == SLEW_TYPE_DATA)
-    {
-        switch (i_slew_imp)		// get impedance index for data
-   	    {
- 		case OHM40:
-			imp_idx = 3;
-			break;
-		case OHM34:
-			imp_idx = 2;
-			break;
-		case OHM30:
-			imp_idx = 1;
-			break;
-		case OHM24:
-			imp_idx = 0;
-			break;
-		default:			// OHM15 || OHM20 not valid for data
-	    	FAPI_ERR("Slew impedance input(%u) invalid "
-			   "or out of bounds, index=%u", i_slew_imp, imp_idx);
-		    FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT);
-	    	return rc;
-		}
-
-		if (i_slew_rate != SLEW_MAXV_NS)
-		{
-			rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba,
-				calibrated_slew_rate_table); if(rc) return rc;
-
-			slew_cal_value =
-				calibrated_slew_rate_table[i_port][imp_idx][slew_idx];
-		}
-
-		if (slew_cal_value > MAX_SLEW_VALUE)
-		{
-			FAPI_INF("WARNING:  Slew rate(0x%02x) unsupported, "
-					"but continuing... !!",	slew_cal_value);
-			slew_cal_value = slew_cal_value & 0x0F;
-		}
-
-		FAPI_INF("Setting DATA (dq/dqs) slew register, imped=%i, slewrate=%i, "
-				"reg_val=0x%X",	i_slew_imp, i_slew_rate, slew_cal_value);
-
-		FAPI_DBG("port%u type=%u imp_idx=%u slew_idx=%u cal_slew=%u",
-			i_port, i_slew_type, imp_idx, slew_idx, slew_cal_value);
-
-		if (i_port == 0)	 // port 0 dq/dqs slew
-		{
-			rc = fapiGetScom(i_target_mba,
-				DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F,
-				data_buffer); if(rc) return rc;
-
-			rc_num |= data_buffer.insertFromRight(slew_cal_value, 56, 4);
-			if (rc_num)
-			{
-			FAPI_ERR("Error in setting up DATA slew buffer");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-		// switch this later to use broadcast address, 0x80003C750301143F P0_[0:4]
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_0_0x800000750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_1_0x800004750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_2_0x800008750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_3_0x80000C750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P0_4_0x800010750301143F,
-					data_buffer); if(rc) return rc;
-		}
-		else	 // port 1 dq/dqs slew
-		{
-			rc = fapiGetScom(i_target_mba,
-				DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F,
-				data_buffer); if(rc) return rc;
-
-			rc_num |= data_buffer.insertFromRight(slew_cal_value, 56, 4);
-			if (rc_num)
-			{
-			FAPI_ERR("Error in setting up DATA slew buffer");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-		// switch this later to use broadcast address, 0x80013C750301143F P1_[0:4]
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_0_0x800100750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_1_0x800104750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_2_0x800108750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_3_0x80010C750301143F,
-					data_buffer); if(rc) return rc;
-				rc = fapiPutScom(i_target_mba,
-					DPHY01_DDRPHY_DP18_IO_TX_CONFIG0_P1_4_0x800110750301143F,
-					data_buffer); if(rc) return rc;
-		}
-	} // end DATA
-    else	// Slew type = ADR
-    {
-		uint8_t adr_pos = 48;	// SLEW_CTL0(48:51) of reg for ADR command slew
-
-		for(uint8_t i=0; i < MAX_NUM_IMP; i++)	// find ADR imp index
-		{
-			if (adr_imp_array[i] == i_slew_imp)
-			{
-				imp_idx = i;
-				break;
-			}
-		}
-		if ((i_slew_imp == OHM24) || (i_slew_imp == OHM34) ||
-			(imp_idx >= MAX_NUM_IMP))
-		{
-			FAPI_ERR("Slew impedance input(%u) out of bounds", i_slew_imp);
-			FAPI_SET_HWP_ERROR(rc, RC_CONFIG_SLEW_RATE_INVALID_INPUT);
-			return rc;
-		}
-
-		if (i_slew_rate == SLEW_MAXV_NS)
-		{
-			slew_cal_value = 0;
-		}
-		else
-		{
-			rc = FAPI_ATTR_GET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba,
-				calibrated_slew_rate_table); if(rc) return rc;
-
-			slew_cal_value =
-				calibrated_slew_rate_table[i_port][imp_idx][slew_idx];
-		}
-
-		if (slew_cal_value > MAX_SLEW_VALUE)
-		{
-			FAPI_INF("!! Slew rate(0x%02x) unsupported, but continuing... !!",
-					slew_cal_value);
-			slew_cal_value = slew_cal_value & 0x0F;
-		}
-
-		switch (i_slew_type)		// get impedance index for data
-		{
-			case SLEW_TYPE_ADR_ADDR:
-				// CTL0 for command slew (A0:15, BA0:3, ACT, PAR, CAS, RAS, WE)
-				FAPI_INF("Setting ADR command/address slew in CTL0 register "
-					"imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp,
-					i_slew_rate, slew_cal_value);
-				adr_pos = 48;
-				break;
-			case SLEW_TYPE_ADR_CNTL:
-				// CTL1 for control slew (CKE0:1, CKE4:5, ODT0:3, CSN0:3)
-				FAPI_INF("Setting ADR control slew in CTL1 register "
-					"imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp,
-					i_slew_rate, slew_cal_value);
-				adr_pos = 52;
-				break;
-			case SLEW_TYPE_ADR_CLK:
-				// CTL2 for clock slew (CLK0:3)
-				FAPI_INF("Setting ADR clock slew in CTL2 register "
-					"imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp,
-				    i_slew_rate, slew_cal_value);
-				adr_pos = 56;
-				break;
-			case SLEW_TYPE_ADR_SPCKE:
-				// CTL3 for spare clock  slew (CKE2:3)
-				FAPI_INF("Setting ADR Spare clock in CTL3 register "
-					"imped=%i, slewrate=%i, reg_val=0x%X", i_slew_imp,
-					i_slew_rate, slew_cal_value);
-				adr_pos = 60;
-				break;
-		}
-
-		FAPI_DBG("port%u type=%u slew_idx=%u imp_idx=%u cal_slew=%u",
-			i_port, i_slew_type, slew_idx, imp_idx, slew_cal_value);
-
-		if (i_port == 0)	 // port 0 adr slew
-		{
-			rc = fapiGetScom(i_target_mba,
-				DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F,
-				data_buffer); if(rc) return rc;
-
-			rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4);
-			if (rc_num)
-			{
-				FAPI_ERR( "Error in setting up ADR slew buffer");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-	// switch this later to use broadcast address, 0x80007C1A0301143f ADR[0:3]
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR0_0x8000401A0301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR1_0x8000441A0301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR2_0x8000481A0301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P0_ADR3_0x80004C1A0301143F,
-			data_buffer); if(rc) return rc;
-		}
-		else				 // port 1 adr slew
-		{
-			rc = fapiGetScom(i_target_mba,
-				DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F,
-				data_buffer); if(rc) return rc;
-			rc_num |= data_buffer.insertFromRight(slew_cal_value, adr_pos, 4);
-			if (rc_num)
-			{
-				FAPI_ERR( "Error in setting up ADR slew buffer");
-				rc.setEcmdError(rc_num);
-				return rc;
-			}
-	// switch this later to use broadcast address, 0x80017C1A0301143f ADR[0:3]
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR0_0x8001401A0301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR1_0x8001441A0301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR2_0x8001481A0301143F,
-			data_buffer); if(rc) return rc;
-			rc = fapiPutScom(i_target_mba,
-			DPHY01_DDRPHY_ADR_IO_SLEW_CTL_VALUE_P1_ADR3_0x80014C1A0301143F,
-			data_buffer); if(rc) return rc;
-		}
-    } // end ADR
-    return rc;
-}
-
-/*------------------------------------------------------------------------------
- * Function: config_wr_dram_vref()
- * This function configures PC_VREF_DRV_CONTROL registers to vary the DIMM VREF
- *
- * Parameters: target: mba;		port: 0, 1
- * Wr_dram_vref: VDD420 = 420, VDD425 = 425, VDD430 = 430, VDD435 = 435, VDD440 = 440,
- * VDD445 = 445, VDD450 = 450, VDD455 = 455, VDD460 = 460, VDD465 = 465, VDD470 = 470,
- * VDD475 = 475, VDD480 = 480, VDD485 = 485, VDD490 = 490, VDD495 = 495, VDD500 = 500,
- * VDD505 = 505, VDD510 = 510, VDD515 = 515, VDD520 = 520, VDD525 = 525, VDD530 = 530,
- * VDD535 = 535, VDD540 = 540, VDD545 = 545, VDD550 = 550, VDD555 = 555, VDD560 = 560,
- * VDD565 = 565, VDD570 = 570, VDD575 = 575
- * ---------------------------------------------------------------------------*/
-
-fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba, uint8_t i_port, uint32_t i_wr_dram_vref)
-{
-
-    ecmdDataBufferBase data_buffer(64);
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint32_t pcvref = 0;
-    uint32_t sign = 0;
-
-    // For DDR3 vary from VDD*0.42 to VDD*575
-    // For DDR4 internal voltage is there this function is not required
-    if (i_port > 1)
-    {
-	FAPI_ERR("Write Vref port input(%u) out of bounds", i_port);
-	const uint8_t & PORT_PARAM = i_port;
-	FAPI_SET_HWP_ERROR(rc, RC_CONFIG_WR_DRAM_VREF_INVALID_INPUT);
-	return rc;
-    }
-	
-    if(i_wr_dram_vref < 500)
-    {
-        sign = 1;
-    }
-    else
-    {
-        sign = 0;
-    } 
-    if((i_wr_dram_vref == 420) || (i_wr_dram_vref == 575)) 
-    {
-        pcvref = 0xF;
-    }
-    else if((i_wr_dram_vref == 425) || (i_wr_dram_vref == 570)) 
-    {
-        pcvref = 0x7;
-    }
-    else if((i_wr_dram_vref == 430) || (i_wr_dram_vref == 565)) 
-    {
-        pcvref = 0xB;
-    }
-    else if((i_wr_dram_vref == 435) || (i_wr_dram_vref == 560)) 
-    {
-        pcvref = 0x3;
-    }
-    else if((i_wr_dram_vref == 440) || (i_wr_dram_vref == 555)) 
-    {
-        pcvref = 0xD;
-    }
-    else if((i_wr_dram_vref == 445) || (i_wr_dram_vref == 550)) 
-    {
-        pcvref = 0x5;
-    }
-    else if((i_wr_dram_vref == 450) || (i_wr_dram_vref == 545)) 
-    {
-        pcvref = 0x9;
-    }
-    else if((i_wr_dram_vref == 455) || (i_wr_dram_vref == 540)) 
-    {
-        pcvref = 0x1;
-    }
-    else if((i_wr_dram_vref == 460) || (i_wr_dram_vref == 535)) 
-    {
-        pcvref = 0xE;
-    }
-    else if((i_wr_dram_vref == 465) || (i_wr_dram_vref == 530)) 
-    {
-        pcvref = 0x6;
-    }
-    else if((i_wr_dram_vref == 470) || (i_wr_dram_vref == 525)) 
-    {
-        pcvref = 0xA;
-    }
-    else if((i_wr_dram_vref == 475) || (i_wr_dram_vref == 520)) 
-    {
-        pcvref = 0x2;
-    }
-    else if((i_wr_dram_vref == 480) || (i_wr_dram_vref == 515)) 
-    {
-        pcvref = 0xC;
-    }
-    else if((i_wr_dram_vref == 485) || (i_wr_dram_vref == 510)) 
-    {
-        pcvref = 0x4;
-    }
-    else if((i_wr_dram_vref == 490) || (i_wr_dram_vref == 505)) 
-    {
-        pcvref = 0x8;
-    }
-    else if((i_wr_dram_vref == 495) || (i_wr_dram_vref == 500)) 
-    {
-        pcvref = 0x0;
-    }
-
-	rc = fapiGetScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc;
-        rc_num = rc_num | data_buffer.insertFromRight(sign,48,1);
-        rc_num = rc_num | data_buffer.insertFromRight(sign,53,1);
-        rc_num = rc_num | data_buffer.insertFromRight(pcvref,49,4);
-        rc_num = rc_num | data_buffer.insertFromRight(pcvref,54,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_wr_vref: Error in setting up buffer ");
-	    rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P0_0x8000C0150301143F, data_buffer); if(rc) return rc;
-        rc_num = rc_num | data_buffer.insertFromRight(sign,48,1);
-        rc_num = rc_num | data_buffer.insertFromRight(sign,53,1);
-        rc_num = rc_num | data_buffer.insertFromRight(pcvref,49,4);
-        rc_num = rc_num | data_buffer.insertFromRight(pcvref,54,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_wr_vref: Error in setting up buffer ");
-	    rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba, DPHY01_DDRPHY_PC_VREF_DRV_CONTROL_P1_0x8001C0150301143F, data_buffer); if(rc) return rc;
-    return rc;
-}
-/*------------------------------------------------------------------------------
- * Function: config_rd_cen_vref()
- * This function configures read vref registers to vary the CEN VREF
- *
- * Parameters: target: mba;		port: 0, 1
- * Rd_cen_Vref: VDD40375 = 40375, VDD41750 = 41750, VDD43125 = 43125, VDD44500 = 44500,
- * VDD45875 = 45875, VDD47250 = 47250, VDD48625 = 48625, VDD50000 = 50000, VDD51375 = 51375,
- * VDD52750 = 52750, VDD54125 = 54125, VDD55500 = 55500, VDD56875 = 56875, VDD58250 = 58250,
- * VDD59625 = 59625, VDD61000 = 61000, VDD60375 = 60375, VDD61750 = 61750, VDD63125 = 63125,
- * VDD64500 = 64500, VDD65875 = 65875, VDD67250 = 67250, VDD68625 = 68625, VDD70000 = 70000,
- * VDD71375 = 71375, VDD72750 = 72750, VDD74125 = 74125, VDD75500 = 75500, VDD76875 = 76875,
- * VDD78250 = 78250, VDD79625 = 79625, VDD81000 = 81000
- * DDR3 supports upto 61000, DDR4 - full range
- * ---------------------------------------------------------------------------*/
-
-fapi::ReturnCode config_rd_cen_vref (const fapi::Target & i_target_mba, uint8_t i_port, uint32_t i_rd_cen_vref)
-{
-
-    ecmdDataBufferBase data_buffer(64);
-    fapi::ReturnCode rc;
-    uint32_t rc_num = 0;
-    uint32_t rd_vref = 0;
-
-    if (i_port > 1)
-    {
-	FAPI_ERR("Read vref port input(%u) out of bounds", i_port);
-	const uint8_t & PORT_PARAM = i_port;
-	FAPI_SET_HWP_ERROR(rc, RC_CONFIG_RD_CEN_VREF_INVALID_INPUT);
-	return rc;
-    }
-    
-    //if (rd_cen_vref == DDR3 rd_vref ) || (rd_cen_vref == DDR4)
-    
-    if((i_rd_cen_vref == 61000) || (i_rd_cen_vref == 81000)) 
-    {
-        rd_vref = 0xF;
-    }
-    else if((i_rd_cen_vref == 59625) || (i_rd_cen_vref == 79625))        
-    {                                                                    
-        rd_vref = 0xE;                                                   
-    }                                                                    
-    else if((i_rd_cen_vref == 58250) || (i_rd_cen_vref == 78250))        
-    {                                                                    
-        rd_vref = 0xD;                                                   
-    }                                                                    
-    else if((i_rd_cen_vref == 56875) || (i_rd_cen_vref == 76875))        
-    {                                                                                                                     
-        rd_vref = 0xC;
-    }
-    else if((i_rd_cen_vref == 55500) || (i_rd_cen_vref == 75500)) 
-    {
-        rd_vref = 0xB;
-    }
-    else if((i_rd_cen_vref == 54125) || (i_rd_cen_vref == 74125)) 
-    {
-        rd_vref = 0xA;
-    }
-    else if((i_rd_cen_vref == 52750) || (i_rd_cen_vref == 72750)) 
-    {
-        rd_vref = 0x9;
-    }
-    else if((i_rd_cen_vref == 51375) || (i_rd_cen_vref == 71375)) 
-    {
-        rd_vref = 0x8;
-    }
-    else if((i_rd_cen_vref == 50000) || (i_rd_cen_vref == 70000)) 
-    {
-        rd_vref = 0x0;
-    }
-    else if((i_rd_cen_vref == 48625) || (i_rd_cen_vref == 68625))    
-    {                                                                
-        rd_vref = 0x1;                                               
-    }                                                                
-    else if((i_rd_cen_vref == 47250) || (i_rd_cen_vref == 67250))    
-    {                                                                
-        rd_vref = 0x2;                                               
-    }                                                                
-    else if((i_rd_cen_vref == 45875) || (i_rd_cen_vref == 65875)) 
-    {
-        rd_vref = 0x3;
-    }
-    else if((i_rd_cen_vref == 44500) || (i_rd_cen_vref == 64500)) 
-    {
-        rd_vref = 0x4;
-    }
-    else if((i_rd_cen_vref == 43125) || (i_rd_cen_vref == 63125)) 
-    {
-        rd_vref = 0x5;
-    }
-    else if((i_rd_cen_vref == 41750) || (i_rd_cen_vref == 61750)) 
-    {
-        rd_vref = 0x6;
-    }
-    else if((i_rd_cen_vref == 40375) || (i_rd_cen_vref == 60375)) 
-    {
-        rd_vref = 0x7;        
-    }
-    else
-    {
-    	rd_vref = 0x0;
-    }
-
-	rc = fapiGetScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,  
-		    data_buffer); if(rc) return rc;
-        rc_num = rc_num | data_buffer.insertFromRight(rd_vref,56,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_0_0x800000060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_1_0x800004060301143F,
-		    data_buffer); if(rc) return rc;
-    	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_2_0x800008060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_3_0x80000c060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P0_4_0x800010060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiGetScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
-		    data_buffer); if(rc) return rc;
-        rc_num = rc_num | data_buffer.insertFromRight(rd_vref,56,4);
-        if (rc_num)
-        {
-            FAPI_ERR( "config_rd_vref: Error in setting up buffer ");
-            rc.setEcmdError(rc_num);
-            return rc;
-        }
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_0_0x800100060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_1_0x800104060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_2_0x800108060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_3_0x80010c060301143F,
-		    data_buffer); if(rc) return rc;
-	rc = fapiPutScom(i_target_mba,
-		    DPHY01_DDRPHY_DP18_RX_PEAK_AMP_P1_4_0x800110060301143F,
-		    data_buffer); if(rc) return rc;
-    return rc;
-}
-/*------------------------------------------------------------------------------
- * Function: mss_slew_cal()
- * This function runs the slew calibration engine to configure MSS_SLEW_DATA/ADR
- * attributes and calls config_slew_rate to set the slew rate in the registers.
- *
- * Parameters: target: mba;
- * ---------------------------------------------------------------------------*/
-
-fapi::ReturnCode mss_slew_cal(const fapi::Target &i_target_mba)
-{
-	fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-	fapi::ReturnCode array_rcs[MAX_NUM_PORTS]; // capture rc per port loop
-    uint32_t poll_count = 0;
-	uint8_t ports_valid = 0;
-	uint8_t is_sim = 0;
-
-	uint8_t freq_idx = 0;		// freq index into lookup table
-	uint32_t ddr_freq = 0;		// current ddr freq
-	uint8_t	ddr_idx = 0;		// ddr type index into lookup table
-	uint8_t ddr_type = 0;		// ATTR_EFF_DRAM_GEN{0=invalid, 1=ddr3, 2=ddr4}
-
-	uint8_t cal_status = 0;
-	// bypass slew (MAX slew rate) not included since it is not calibrated.
-	// for output ATTR_MSS_SLEW_RATE_DATA(0),
-	//            ATTR_MSS_SLEW_RATE_ADR(1), [port=2][imp=4][slew=4]
-	uint8_t calibrated_slew[2][MAX_NUM_PORTS][MAX_NUM_IMP]
-		[MAX_NUM_CAL_SLEW_RATES] = {{{{ 0 }}}};
-
-	fapi::Target l_target_centaur;	// temporary target for parent
-
-	ecmdDataBufferBase ctl_reg(64);
-	ecmdDataBufferBase stat_reg(64);
-	
-	// DD level 1.0-1.1, Version 1.0
-	// [ddr3/4][dq/adr][speed][impedance][slew_rate]
-	// note: Assumes standard voltage for DDR3(1.35V), DDR4(1.2V),
-	// little endian, if >=128, lab only debug.
-	//
-	// ddr_type(2)	ddr3=0, ddr4=1
-	// data/adr(2)	data(dq/dqs)=0, adr(cmd/cntl)=1
-	// speed(4)		1066=0, 1333=1, 1600=2, 1866=3
-	// imped(4)		24ohms=0, 30ohms=1, 34ohms=2, 40ohms=3 for DQ/DQS
-	// imped(4)		15ohms=0, 20ohms=1, 30ohms=2, 40ohms=3 for ADR driver
-	// slew(3)		3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3
-	const uint8_t slew_table[2][2][4][4][4] = {
-//	NOTE: bit 7 = unsupported slew, and actual value is in bits 4:0
-
-/*	DDR3(0)	*/
-	{ {
-	// dq/dqs(0)
-/* Imp. ________24ohms______..________30ohms______..________34ohms______..________40ohms______
-   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
-/*1066*/{{ 12,   9,   7, 134}, { 13,   9,   7, 133}, { 13,  10,   7, 134}, { 14,  10,   7, 132}},
-/*1333*/{{ 15,  11,   8, 135}, { 16,  12,   9, 135}, { 17,  12,   9, 135}, { 17,  12,   8, 133}},
-/*1600*/{{ 18,  13,  10, 136}, { 19,  14,  10, 136}, { 20,  15,  11, 136}, { 21,  14,  10, 134}},
-/*1866*/{{149, 143, 140, 138}, {151, 144, 140, 137}, {151, 145, 141, 138}, {152, 145, 139, 135}}
-	}, {
-	// adr(1),
-/* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______
-   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
-// 1066 {{ 17,  13,  10,   8}, { 13,  11,   7,   6}, { 12,   8,   5, 131}, {  7,   4, 131, 131}}, // old before May 2013
-/*1066*/{{ 17,  13,  10,   8}, { 13,  10,   7,   6}, { 12,   8,   5, 131}, {  7,   4, 131, 131}},
-/*1333*/{{ 21,  16,  12,  10}, { 17,  12,   9,   7}, { 15,  10,   6, 132}, {  6,   5, 132, 132}},
-/*1600*/{{ 25,  19,  15,  12}, { 20,  14,  13,   8}, { 19,  12,   7, 133}, {  7,   6, 133, 133}},
-/*1866*/{{157, 150, 145, 142}, {151, 145, 141, 138}, {150, 142, 136, 134}, {141, 134, 134, 134}}
-	} },
-/* DDR4(1) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ */
-	{ {
-	// dq/dqs(0)
-/* Imp. ________24ohms______..________30ohms______..________34ohms______..________40ohms______
-   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
-/*1066*/{{138, 135, 134, 133}, {139, 136, 134, 132}, {140, 136, 134, 132}, {140, 136, 132, 132}},
-/*1333*/{{139, 137, 135, 134}, {142, 138, 135, 133}, {143, 138, 135, 133}, {143, 138, 133, 132}},
-/*1600*/{{ 15,  11,   9, 135}, { 17,  11,   9, 135}, { 18,  13,   9, 134}, { 18,  11,   6, 133}},
-/*1866*/{{ 18,  13,  10, 137}, { 19,  13,  10, 136}, { 21,  15,  10, 135}, { 21,  13,   8, 134}}
-	}, {
-	// adr(1)
-/* Imp. ________15ohms______..________20ohms______..________30ohms______..________40ohms______
-   Slew    3    4    5    6      3    4    5    6      3    4    5    6      3    4    5    6  (V/ns) */
-/*1066*/{{142, 139, 136, 134}, {140, 136, 134, 133}, {138, 134, 131, 131}, {133, 131, 131, 131}},
-/*1333*/{{145, 142, 139, 136}, {143, 138, 135, 134}, {140, 135, 132, 132}, {134, 132, 132, 132}},
-/*1600*/{{ 21,  16,  13,  10}, { 18,  12,   9, 135}, { 15,   8, 133, 133}, {  7, 133, 133, 133}},
-/*1866*/{{ 24,  19,  15,  11}, { 21,  14,  10, 136}, { 17,  10, 134, 134}, {  9, 134, 134, 134}}
-	} }
-	};
-
-	// slew calibration control register
-	const uint64_t slew_cal_cntl[] = {
-		DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F, // port 0
-		DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P1_ADR32S0_0x800180390301143F  // port 1
-	};
-	// slew calibration status registers
-	const uint64_t slew_cal_stat[] = {
-		DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F,
-		DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P1_ADR32S0_0x800180340301143F
-	};
-	const uint8_t ENABLE_BIT = 48;
-	const uint8_t START_BIT = 49;
-	const uint8_t BB_LOCK_BIT = 56;
-	// general purpose 100 ns delay for HW mode  (2000 sim cycles if simclk = 20ghz)
-	const uint16_t	DELAY_100NS		= 100;
-	const uint16_t	DELAY_2000NCLKS	= 4000;		// roughly 2000 nclks if DDR freq >= 1066
-	// normally 2000, but since cal doesn't work in SIM, setting to 1
-	const uint16_t	DELAY_SIMCYCLES	= 1;	
-	const uint8_t	MAX_POLL_LOOPS	= 20;
-
-	// verify which ports are functional
-	rc = FAPI_ATTR_GET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR,
-			&i_target_mba, ports_valid);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: "
-				"ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR");
-		return rc;
-	}
-
-	// Check if in SIM
-	rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, is_sim);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_IS_SIMULATION");
-		return rc;
-	}
-	// Get DDR type (DDR3 or DDR4)
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, ddr_type);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_EFF_DRAM_GEN");
-		return rc;
-	}
-	// ddr_type(2)	ddr3=0, ddr4=1
-	if (ddr_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) {	//type=2
-		ddr_idx = 1;
-	} else if (ddr_type == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { //type=1
-		ddr_idx = 0;
-	} else {
-		FAPI_ERR("Invalid ATTR_DRAM_DRAM_GEN = %d, %s!", ddr_type,
-				i_target_mba.toEcmdString());
-		const uint8_t & DRAM_GEN = ddr_type;
-		FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_INVALID_DRAM_GEN);
-		return rc;
-	}
-
-	// get freq from parent
-	rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
-	rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, ddr_freq);
-	if(rc) return rc;
-
-	if (ddr_freq == 0) {
-		FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", ddr_freq,
-				i_target_mba.toEcmdString());
-		FAPI_SET_HWP_ERROR(rc, RC_MSS_SLEW_CAL_INVALID_FREQ);
-		return rc;
-	}
-	// speed(4)		1066=0, 1333=1, 1600=2, 1866=3
-	if (ddr_freq > 1732) {
-		freq_idx= 3;		// for 1866+
-	} else if ((ddr_freq > 1460) && (ddr_freq <= 1732)) {
-		freq_idx = 2;		// for 1600
-	} else if ((ddr_freq > 1200) && (ddr_freq <= 1460)) {
-		freq_idx = 1;		// for 1333
-	} else {		// (ddr_freq <= 1200)
-		freq_idx = 0;		// for 1066-
-	}
-
-	for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++)
-	{
-		uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port)));
-
-		if (port_val == 0) {
-			FAPI_INF("WARNING:  port %u is invalid from "
-					"ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR (0x%02x), skipping.",
-					l_port, ports_valid);
-			continue;
-		}
-	//	Step A: Configure ADR registers and MCLK detect (done in ddr_phy_reset)
-	// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
-		rc = fapiGetScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
-		if (rc)
-		{
-			FAPI_ERR("Error reading DDRPHY_ADR_SLEW_CAL_CNTL register.");
-			return rc;
-		}
-
-		rc_ecmd = ctl_reg.flushTo0();
-		rc_ecmd |= ctl_reg.setBit(ENABLE_BIT);		// set enable (bit49) to 1
-		if (rc_ecmd)
-		{
-			FAPI_ERR("Error setting enable bit in ADR Slew calibration "
-					"control register.");
-			rc.setEcmdError(rc_ecmd);
-			return rc;
-		}
-
-		FAPI_INF("Enabling slew calibration engine on port %i: DDR%i(%u) "
-			   "%u(%u) in %s", l_port, (ddr_type+2), ddr_idx, ddr_freq,
-			   freq_idx, i_target_mba.toEcmdString());
-
-		// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
-		rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
-		if (rc)
-		{
-			FAPI_ERR("Error enabling slew calibration engine in "
-					"DDRPHY_ADR_SLEW_CAL_CNTL register.");
-			return rc;
-		}
-		// Note: must be 2000 nclks+ after setting enable bit
-		rc = fapiDelay(DELAY_2000NCLKS, 1);
-		if (rc) {
-			FAPI_ERR("Error executing fapiDelay of 2000 nclks or 1 simcycle");
-			return rc;
-		}
-
-		//---------------------------------------------------------------------/
-		//	Step 1. Check for BB lock.
-		FAPI_DBG("Wait for BB lock in status register, bit %u", BB_LOCK_BIT);
-		for (poll_count=0; poll_count < MAX_POLL_LOOPS; poll_count++)
-		{
-			rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES);
-			if (rc) {
-				FAPI_ERR("Error executing fapiDelay of 100ns or 2000simcycles");
-				return rc;
-			}
-	// DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port
-			rc = fapiGetScom(i_target_mba, slew_cal_stat[l_port], stat_reg);
-			if (rc)
-			{
-				FAPI_ERR("Error reading DDRPHY_ADR_SYSCLK_PR_VALUE_RO register "
-						"for BB_Lock.");
-				return rc;
-			}
-			FAPI_DBG("stat_reg = 0x%04x, count=%i",stat_reg.getHalfWord(3),
-					poll_count);
-
-			if (stat_reg.isBitSet(BB_LOCK_BIT)) break;
-		}
-
-		if (poll_count == MAX_POLL_LOOPS) {
-			FAPI_INF("WARNING: Timeout on polling BB_Lock, continuing...");
-		}
-		else
-		{
-			FAPI_DBG("polling finished in %i loops (%u ns)\n",
-					poll_count, (100*poll_count));
-		}
-
-		//---------------------------------------------------------------------/
-		// Create calibrated slew settings
-		// dq/adr(2)	dq/dqs=0, adr=1
-		// slew(4)		3V/ns=0, 4V/ns=1, 5V/ns=2, 6V/ns=3
-		for (uint8_t data_adr=0; data_adr < 2; data_adr++)
-		{
-			FAPI_INF("Starting %s(%i) slew calibration...", 
-					(data_adr ? "ADR" : "DATA"), data_adr);
-			for (uint8_t imp=0; imp < MAX_NUM_IMP; imp++)
-			{
-				uint8_t cal_slew;
-
-				for (uint8_t slew=0; slew < MAX_NUM_CAL_SLEW_RATES; slew++)
-				{
-					cal_slew =
-						slew_table[ddr_idx][data_adr][freq_idx][imp][slew];
-
-					// set slew phase rotator from slew_table
-					// slew_table[ddr3/4][dq/adr][freq][impedance][slew_rate]
-					rc_ecmd |= ctl_reg.insertFromRight(cal_slew, 59, 5);
-
-					rc_ecmd |= ctl_reg.setBit(START_BIT);	// set start bit(48)
-					if (rc_ecmd)
-					{
-						FAPI_ERR("Error setting start bit or cal input value.");
-						rc.setEcmdError(rc_ecmd);
-						return rc;
-					}
-
-					FAPI_DBG("Slew data_adr=%i, imp_idx=%i, slewrate=%i, "
-						"i_slew=%i,0x%02X (59:63) cntl_reg(48:63)=0x%04X",
-						data_adr, imp, (slew+3), cal_slew, cal_slew,
-						ctl_reg.getHalfWord(3));
-
-	// DPHY01_DDRPHY_ADR_SLEW_CAL_CNTL_P0_ADR32S0_0x800080390301143F + port
-					rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
-					if (rc)
-					{
-						FAPI_ERR("Error starting slew calibration.");
-						return rc;
-					}
-
-					// poll for calibration status done or timeout...
-					for (poll_count=0; poll_count < MAX_POLL_LOOPS;
-							poll_count++)
-					{
-	// DPHY01_DDRPHY_ADR_SYSCLK_PR_VALUE_RO_P0_ADR32S0_0x800080340301143F + port
-						rc = fapiGetScom(i_target_mba, slew_cal_stat[l_port],
-								stat_reg);
-						if (rc)
-						{
-							FAPI_ERR("Error reading "
-									"DDRPHY_ADR_SYSCLK_PR_VALUE_RO "
-									"register for calibration status.");
-							return rc;
-						}
-						rc_ecmd = stat_reg.extractToRight(&cal_status, 58, 2);
-						if (rc_ecmd)
-						{
-							FAPI_ERR("Error getting calibration status bits");
-							rc.setEcmdError(rc_ecmd);
-							return rc;
-						}
-						if (cal_status != 0)
-							break;
-						 // wait (1020 mclks / MAX_POLL_LOOPS)
-						rc = fapiDelay(DELAY_100NS, DELAY_SIMCYCLES);
-						if(rc)
-						{
-							return rc;
-						}
-					}
-
-					if (cal_status > 1)
-					{
-						if (cal_status == 3)
-						{
-							FAPI_DBG("slew calibration completed successfully,"
-								" loop=%i input=0x%02x",	poll_count, 
-								(cal_slew & 0x1F));
-						}
-						else if (cal_status == 2)
-						{
-                            FAPI_INF("WARNING: occurred during slew calibration"
-                                     ", imped=%i, slewrate=%i %s ddr_idx[%i]",
-                                     data_adr ? adr_imp_array[imp] :
-                                       drv_imp_array[(4-imp)], (slew+3),
-                                     i_target_mba.toEcmdString(), ddr_idx);
-                            FAPI_INF("data_adr[%i], freq_idx[%i], imp[%i], slew[%i]",
-                                     data_adr, freq_idx, imp, slew);
-                            FAPI_INF("input=0x%02X, ctrl=0x%04X, status=0x%04X",
-                                     (cal_slew & 0x1F), ctl_reg.getHalfWord(3),
-                                     stat_reg.getHalfWord(3));
-						}
-						cal_slew = cal_slew & 0x80;	// clear bits 6:0
-						rc_ecmd = stat_reg.extractPreserve(&cal_slew, 60, 4, 4);
-						FAPI_DBG("MSS_SLEW_RATE_%s port[%i]imp[%i]slew[%i] = "
-								"0x%02x\n",	(data_adr ? "ADR" : "DATA"), l_port,
-								imp, slew, (cal_slew & 0xF));
-						if (rc_ecmd)
-						{
-							FAPI_ERR("Error getting calibration output "
-									"slew value");
-							rc.setEcmdError(rc_ecmd);
-							return rc;
-						}
-						calibrated_slew[data_adr][l_port][imp][slew] = cal_slew;
-					}
-					else
-					{
-						if (is_sim) {
-							// Calibration fails in sim since bb_lock not
-							// possible in cycle simulator, putting initial
-							// to be cal'd value in output table
-							FAPI_INF("In SIM setting input slew value in array"
-									", status(%i) NOT clean.", cal_status);
-							calibrated_slew[data_adr][l_port][imp][slew] =
-								cal_slew;
-						}
-						else
-						{
-                            FAPI_ERR("Slew calibration failed on %s slew: "
-                                "imp_idx=%d(%i ohms)",
-                                (data_adr ? "ADR" : "DATA"), imp,
-                                (data_adr ? adr_imp_array[imp] :
-                                 drv_imp_array[(4-imp)]));
-                            FAPI_ERR("slew_idx=%d(%i V/ns), slew_table=0x%02X",
-                                     slew, (slew+3), cal_slew);
-                            FAPI_ERR("ctl_reg=0x%04X, status=0x%04X on %s!",
-                                     stat_reg.getHalfWord(3),
-                                     ctl_reg.getHalfWord(3),
-                                     i_target_mba.toEcmdString());
-
-                            const uint8_t & DATA_ADR = data_adr;
-                            const uint8_t & IMP = imp;
-                            const uint8_t & SLEW = slew;
-                            const fapi::Target & MBA_IN_ERROR = i_target_mba;
-                            const ecmdDataBufferBase & STAT_REG = stat_reg;
-
-                            if (cal_status == 1)
-                            {
-                                if (l_port == 0)
-                                {
-                                    FAPI_ERR("Error occurred during slew calibration on port 0");
-                                    FAPI_SET_HWP_ERROR(rc,
-                                        RC_MSS_SLEW_CAL_ERROR_PORT0);
-                                }
-                                else
-                                {
-                                    FAPI_ERR("Error occurred during slew calibration on port 1");
-                                    FAPI_SET_HWP_ERROR(rc,
-                                        RC_MSS_SLEW_CAL_ERROR_PORT1);
-                                }
-                            }
-                            else
-                            {
-                                if (l_port == 0)
-                                {
-                                    FAPI_ERR("Slew calibration timed out on port 0, loop=%i",
-                                        poll_count);
-                                    FAPI_SET_HWP_ERROR(rc,
-                                        RC_MSS_SLEW_CAL_TIMEOUT_PORT0);
-                                }
-                                else
-                                {
-                                    FAPI_ERR("Slew calibration timed out on port 1, loop=%i",
-                                        poll_count);
-                                    FAPI_SET_HWP_ERROR(rc,
-                                        RC_MSS_SLEW_CAL_TIMEOUT_PORT1);
-                                }
-                            }
-
-							array_rcs[l_port]=rc;
-							continue;
-						}
-					} // end error check
-				} // end slew
-			} // end imp
-		} // end data_adr
-
-		// disable calibration engine for port
-		ctl_reg.clearBit(ENABLE_BIT);
-		rc = fapiPutScom(i_target_mba, slew_cal_cntl[l_port], ctl_reg);
-		if (rc)
-		{
-			FAPI_ERR("Error disabling slew calibration engine in "
-					"DDRPHY_ADR_SLEW_CAL_CNTL register.");
-			return rc;
-		}
-		else
-		{
-			FAPI_INF("Finished slew calibration on port %i: "
-					"disabling cal engine\n", l_port);
-		}
-	} // end port loop
-
-	for (uint8_t rn=0; rn < MAX_NUM_PORTS; rn++)
-	{
-		if (array_rcs[rn] != fapi::FAPI_RC_SUCCESS)
-		{
-			FAPI_ERR("Returning ERROR RC for port %u",rn);
-			return array_rcs[rn];
-		}
-	}
-	FAPI_INF("Setting output slew tables ATTR_MSS_SLEW_RATE_DATA/ADR\n");
-	// ATTR_MSS_SLEW_RATE_DATA [2][4][4]	port, imped, slew_rate
-	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_DATA, &i_target_mba, calibrated_slew[0]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_DATA");
-		return rc;
-	}
-	// ATTR_MSS_SLEW_RATE_ADR [2][4][4]		port, imped, slew_rate
-	rc = FAPI_ATTR_SET(ATTR_MSS_SLEW_RATE_ADR, &i_target_mba, calibrated_slew[1]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to set attribute: ATTR_MSS_SLEW_RATE_ADR");
-		return rc;
-	}
-
-/******************************************************************************/
-	uint8_t slew_imp_val [MAX_NUM_SLEW_TYPES][2][MAX_NUM_PORTS]={{{0}}};
-	enum {
-		SLEW = 0,
-		IMP = 1,
-	};
-
-	// Get desired dq/dqs slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_DATA][SLEW]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_SLEW_RATE_DQ_DQS");
-		return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_DATA][IMP]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_EFF_CEN_DRV_IMP_DQ_DQS");
-		return rc;
-	}
-	// convert enum value to actual ohms.
-	for (uint8_t j=0; j < MAX_NUM_PORTS; j++)
-	{
-//		FAPI_INF("DQ_DQS IMP Attribute[%i] = %u", j,
-//				slew_imp_val[SLEW_TYPE_DATA][IMP][j]);
-	
-		switch (slew_imp_val[SLEW_TYPE_DATA][IMP][j])
-		{
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM24_FFE0:
-				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=24;
-				break;
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE0:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE480:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE240:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE160:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM30_FFE120:
-				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=30;
-				break;
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE480:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE240:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE160:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM34_FFE120:
-				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=34;
-				break;
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE480:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE240:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE160:
-			case fapi::ENUM_ATTR_EFF_CEN_DRV_IMP_DQ_DQS_OHM40_FFE120:
-				slew_imp_val[SLEW_TYPE_DATA][IMP][j]=40;
-				break;
-			default:
-				FAPI_INF("WARNING: EFF_CEN_DRV_IMP_DQ_DQS attribute "
-						"invalid, using value of 0");
-		}
-//		FAPI_DBG("switched imp to value of %u",
-//				slew_imp_val[SLEW_TYPE_DATA][IMP][j]);
-	}
-	// Get desired ADR control slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_CNTL, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_CNTL][SLEW]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_CNTL");
-		return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_CNTL, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_CNTL][IMP]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_CNTL");
-		return rc;
-	}
-	// Get desired ADR command slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_ADDR, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_ADDR][SLEW]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_ADDR");
-		return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_ADDR, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_ADDR][IMP]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_ADDR");
-		return rc;
-	}
-	// Get desired ADR clock slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_CLK, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_CLK][SLEW]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_CLK");
-		return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_CLK, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_CLK][IMP]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_CLK");
-		return rc;
-	}
-	// Get desired ADR Spare clock slew rate & impedance from attribute
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_SPCKE, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_SPCKE][SLEW]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_SLEW_RATE_SPCKE");
-		return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_SPCKE, &i_target_mba,
-			slew_imp_val[SLEW_TYPE_ADR_SPCKE][IMP]);
-	if (rc)
-	{
-		FAPI_ERR("Failed to get attribute: ATTR_VPD_CEN_DRV_IMP_SPCKE");
-		return rc;
-	}
-
-	for (uint8_t l_port=0; l_port < MAX_NUM_PORTS; l_port++)
-	{
-		//uint8_t ports_mask = 0xF0;  // bits 0:3 = port0, bits 4:7 = port1
-		uint8_t port_val = (ports_valid & (0xF0 >> (4 * l_port)));
-
-		if (port_val == 0)
-		{
-			FAPI_INF("WARNING:  port %u is invalid from "
-					"ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, 0x%02x "
-					"skipping configuration of slew rate on this port",
-					l_port, ports_valid);
-			continue;
-		}
-		FAPI_INF("Setting slew registers for port %i", l_port);
-		for (uint8_t slew_type=0; slew_type < MAX_NUM_SLEW_TYPES; slew_type++)
-		{
-		    fapi::ReturnCode config_rc =
-		        config_slew_rate(i_target_mba, l_port, slew_type,
-					slew_imp_val[slew_type][IMP][l_port],
-					slew_imp_val[slew_type][SLEW][l_port]);
-		    if (config_rc)
-		    {
-		        array_rcs[l_port] = config_rc;
-		    }
-		}
-	}
-
-	for (uint8_t rn=0; rn < MAX_NUM_PORTS; rn++)
-	{
-		if (array_rcs[rn] != fapi::FAPI_RC_SUCCESS)
-		{
-			FAPI_ERR("Returning ERROR RC for port %u",rn);
-			return array_rcs[rn];
-		}
-	}
-	return rc;
-}
diff --git a/src/usr/hwpf/hwp/dram_training/mss_termination_control.H b/src/usr/hwpf/hwp/dram_training/mss_termination_control.H
deleted file mode 100644
index cbebdda94..000000000
--- a/src/usr/hwpf/hwp/dram_training/mss_termination_control.H
+++ /dev/null
@@ -1,344 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/dram_training/mss_termination_control.H $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_termination_control.H,v 1.12 2014/01/22 15:39:22 mjjones Exp $
-/* File is created by SARAVANAN SETHURAMAN on Thur Sept 28 2011. */
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2007
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE :mss_draminit_training_advanced.H
-// *! DESCRIPTION : Tools for centaur procedures
-// *! OWNER NAME :  Saravanan sethuraman    Email ID: saravanans@in.ibm.com
-// *! BACKUP NAME : Menlo Wuu               Email ID: menlowuu@us.ibm.com
-// #! ADDITIONAL COMMENTS :
-//
-// General purpose funcs
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author:  |  Date:   | Comment:
-//---------|---------- |--------- |---------------------------------------------
-//  1.12   | 22-Jan-14 | mjjones  | Removed FW header
-//  1.11   | 21-Jan-14 | abhijsau | mike and menlo fixed ras review comments
-//  1.10   | 14-Dec-12 | sasethur | Updated for fw review comments
-//  1.9    | 07-Dec-12 | sasethur | Updated for fw review comments
-//  1.8	   | 16-Nov-12 | mwuu	  | Added typedef for external call of
-//                                  mss_slew_cal F
-//  1.7	   | 14-Nov-12 | mwuu	  | Changed "l_" variables to "i_" in 
-//  								config_slew_rate FN
-//  1.6	   | 14-Nov-12 | mwuu	  | Fixed revision numbering in comments
-//  1.5    | 14-Nov-12 | mwuu     | Added additional slew rates, and new const
-//  1.4    | 26-Oct-12 | mwuu     | Added additional slew types enums, need to
-//  								change MAX_NUM_SLEW_TYPES when attributes
-//  								updated.
-//  1.3    | 26-Oct-12 | sasethur | Updated FW review comments fapi::,
-//  								const fapi::Target
-//  1.2	   | 17-Oct-12 | mwuu	  | updates to enum and consts
-//  1.1    | 28-Sep-12 | sasethur | First draft
-
-
-#ifndef MSS_TERMINATION_CONTROL_H
-#define MSS_TERMINATION_CONTROL_H
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-enum {
-	SLEW_TYPE_DATA = 0,
-	SLEW_TYPE_ADR_ADDR = 1,
-	SLEW_TYPE_ADR_CNTL = 2,
-	SLEW_TYPE_ADR_CLK = 3,
-	SLEW_TYPE_ADR_SPCKE = 4,
-
-	OHM15 = 15,
-	OHM20 = 20,
-	OHM24 = 24,
-	OHM30 = 30,
-	OHM34 = 34,
-	OHM40 = 40,
-
-	SLEW_3V_NS = 3,
-	SLEW_4V_NS = 4,
-	SLEW_5V_NS = 5,
-	SLEW_6V_NS = 6,
-	SLEW_MAXV_NS = 7,
-};
-
-const uint8_t MAX_NUM_PORTS = 2;		// max number of ports
-const uint8_t MAX_NUM_SLEW_TYPES = 5;	// data(dq/dqs), adr_cmd, adr_cntl, clk, spcke, used by slew_cal FN only
-const uint8_t MAX_NUM_IMP = 4;		// number of impedances valid per slew type
-
-//Address shmoo is not done as a part of Training advanced, so the order matches
-//attribute enum
-const uint8_t adr_imp_array[] = {
-	15,
-	20,
-	30,
-	40,
-};
-
-// bypass slew (MAX slew rate) not included since it is not calibrated.
-const uint8_t MAX_NUM_CAL_SLEW_RATES = 4 ;	// 3V/ns, 4V/ns, 5V/ns, 6V/n
-const uint8_t MAX_NUM_SLEW_RATES = 4;	// 3V/ns, 4V/ns, 5V/ns, 6V/n, MAX?
-const uint8_t slew_rate_array[] = {
-	6,
-	5,
-	4,
-    3,
-};
-
-const uint8_t MAX_SLEW_VALUE = 15;		// 4 bit value
-const uint8_t MAX_WR_VREF = 32;
-
-const uint32_t wr_vref_array[] = {
-	420,
-	425,
-	430,
-	435,
-	440,
-	445,
-	450,
-	455,
-	460,
-	465,
-	470,
-	475,
-	480,
-	485,
-	490,
-	495,
-	500,
-	505,
-	510,
-	515,
-	520,
-	525,
-	530,
-	535,
-	540,
-	545,
-	550,
-	555,
-	560,
-	565,
-	570,
-	575
-	};
-
-
-//The Array is re-arranged inorder to find the best Eye margin based on the
-//Fitness level - 500 is the best value
-const uint32_t wr_vref_array_fitness[] = {
-	420,
-	425,
-	575,
-	430,
-	570,
-	435,
-	565,
-	440,
-	560,
-	445,
-	555,
-	450,
-	550,
-	455,
-	545,
-	460,
-	540,
-	465,
-	535,
-	470,
-	530,
-	475,
-	525,
-	480,
-	520,
-	485,
-	515,
-	490,
-	510,
-	495,
-	505,
-	500
-	};
-
-const uint8_t MAX_RD_VREF = 16;
-const uint32_t rd_cen_vref_array[] = {
-	40375,
-	41750,
-	43125,
-	44500,
-	45875,
-	47250,
-	48625,
-	50000,
-	51375,
-	52750,
-	54125,
-	55500,
-	56875,
-	58250,
-	59625,
-	61000
-	};
-
-//The Array is re-arranged inorder to find the best Eye margin based on the
-//Fitness level - 50000 is the best value
-const uint32_t rd_cen_vref_array_fitness[] = {
-	61000,
-	59625,
-	40375,
-	58250,
-	41750,
-	56875,
-	43125,
-	55500,
-	44500,
-	54125,
-	45875,
-	52750,
-	47250,
-	51375,
-	48625,
-	50000
-	};
-
-//The Array is re-arranged inorder to find the best Eye margin based on the
-//Fitness level - 24 is the best value
-const uint8_t MAX_DRV_IMP = 4;
-const uint8_t drv_imp_array[] = {
-	40,
-	34,
-	30,
-	24
-	};
-
-//The Array is re-arranged inorder to find the best Eye margin based on the
-//Fitness level - 15 is the best value
-const uint8_t MAX_RCV_IMP = 9;
-const uint8_t rcv_imp_array[] = {
-	120,
-    80,
-    60,
-    48,
-    40,
-    34,
-    30,
-    20,
-    15
-    };
-
-extern "C"
-{
-/**
- * @brief configures PC_VREF_DRV_CONTROL registers to vary the DRAM VREF
- *
- * @param[in] i_target_mba   Reference to centaur.mba target
- * @param[in] i_port         MBA Port
- * @param[in] i_wr_dram_vref DRAM VREF to set
- *
- * @return ReturnCode
- */
-fapi::ReturnCode config_wr_dram_vref(const fapi::Target & i_target_mba,
-                                     uint8_t i_port,
-                                     uint32_t i_wr_dram_vref);
-
-/**
- * @brief configures read vref registers to vary the CEN VREF
- *
- * @param[in] i_target_mba   Reference to centaur.mba target
- * @param[in] i_port         MBA Port
- * @param[in] i_rd_cen_vref  CEN VREF to set
- *
- * @return ReturnCode
- */
-fapi::ReturnCode config_rd_cen_vref(const fapi::Target & i_target_mba,
-                                    uint8_t i_port,
-                                    uint32_t i_rd_cen_vref);
-
-/**
- * @brief configures the Driver impedance values to the registers
- *
- * @param[in] i_target_mba     Reference to centaur.mba target
- * @param[in] i_port           MBA Port
- * @param[in] i_drv_imp_dq_dqs Driver impedance values
- *
- * @return ReturnCode
- */
-fapi::ReturnCode config_drv_imp(const fapi::Target & i_target_mba,
-                                uint8_t i_port,
-                                uint8_t i_drv_imp_dq_dqs);
-
-/**
- * @brief configures the Receiver impedance values to the registers
- *
- * @param[in] i_target_mba     Reference to centaur.mba target
- * @param[in] i_port           MBA Port
- * @param[in] i_rcv_imp_dq_dqs Receiver impedance values
- *
- * @return ReturnCode
- */
-fapi::ReturnCode config_rcv_imp(const fapi::Target & i_target_mba,
-                                uint8_t i_port,
-                                uint8_t i_rcv_imp_dq_dqs);
-
-/**
- * @brief configures the Slew rate values to the registers
- *
- * @param[in] i_target_mba Reference to centaur.mba target
- * @param[in] i_port       MBA Port
- * @param[in] i_slew_type  Slew Type
- * @param[in] i_slew_imp   Slew Impedance
- * @param[in] i_slew_rate  Slew Rate
- *
- * @return ReturnCode
- */
-fapi::ReturnCode config_slew_rate(const fapi::Target & i_target_mba,

-	                              const uint8_t i_port,
-	                              const uint8_t i_slew_type,
-	                              const uint8_t i_slew_imp,

-	                              const uint8_t i_slew_rate);
-
-/**
- * @brief runs the slew calibration engine
- *
- * Configures MSS_SLEW_DATA/ADR attributes and calls config_slew_rate to set
- * the slew rate in the registers.
- *
- * @param[in] i_target_mba     Reference to centaur.mba target
- *
- * @return ReturnCode
- */
-fapi::ReturnCode mss_slew_cal(const fapi::Target & i_target_mba);
-
-} // extern C
-#endif
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C
deleted file mode 100755
index 66b498a03..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C
+++ /dev/null
@@ -1,32 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#include <fapi.H>
-#include "io_dccal.H"
-
-extern "C" {
-
-ReturnCode fabric_io_dccal(const Target &target){
-     return io_dccal(target);
-}
-
-} // extern 
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H
deleted file mode 100755
index eaf478c99..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H
+++ /dev/null
@@ -1,35 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal/fabric_io_dccal.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef FABRIC_IO_DCCAL_H_
-#define FABRIC_IO_DCCAL_H_
-
-using namespace fapi;
-
-extern "C"
-{
-
-fapi::ReturnCode fabric_io_dccal(const fapi::Target &target);
-
-} // extern "C"
-
-#endif // FABRIC_IO_DCCAL_H
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.C b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.C
deleted file mode 100644
index 62548316a..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.C
+++ /dev/null
@@ -1,32 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#include <fapi.H>
-#include "io_run_training.H"
-
-extern "C" {
-
-ReturnCode fabric_io_run_training(const Target &master_target,const Target &slave_target){
-     return io_run_training(master_target,slave_target);
-}
-
-} // extern 
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.H b/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.H
deleted file mode 100644
index e06d6a24c..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.H
+++ /dev/null
@@ -1,35 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training/fabric_io_run_training.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef FABRIC_IO_RUN_TRAINING_H_
-#define FABRIC_IO_RUN_TRAINING_H_
-
-using namespace fapi;
-
-extern "C"
-{
-
-fapi::ReturnCode fabric_io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);
-
-} // extern "C"
-
-#endif // FABRIC_IO_RUN_TRAINING_H
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/makefile b/src/usr/hwpf/hwp/edi_ei_initialization/makefile
deleted file mode 100644
index 10f732ea0..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/makefile
+++ /dev/null
@@ -1,69 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/edi_ei_initialization/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = edi_ei_initialization
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
-
-##  NOTE: add the base istep dir here.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_pre_trainadv
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_post_trainadv
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += smp_unfencing_inter_enclosure_abus_links.o
-OBJS += proc_fab_iovalid.o
-OBJS += fabric_io_run_training.o
-OBJS += fabric_io_dccal.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/<HWP_dir>
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_run_training
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/fabric_io_dccal
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_pre_trainadv
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training/io_post_trainadv
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C
deleted file mode 100644
index 8e0ac420f..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C
+++ /dev/null
@@ -1,690 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_fab_iovalid.C,v 1.15 2014/02/12 18:55:11 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_fab_iovalid.C
-// *! DESCRIPTION : Manage X/A link iovalid controls (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_fab_iovalid.H>
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine which writes AND/OR mask register to
-//           set/clear desired bits
-// parameters: i_target        => target
-//             i_active_mask   => bit mask defining active bits to act on
-//             i_set_not_clear => define desired operation
-//                                (true=set, false=clear)
-//             i_and_mask_addr => SCOM address for AND mask register
-//             i_or_mask_addr  => SCOM address for OR mask register
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid_write_active_mask(
-    const fapi::Target& i_target,
-    ecmdDataBufferBase& i_active_mask,
-    bool i_set_not_clear,
-    const uint32_t& i_and_mask_addr,
-    const uint32_t& i_or_mask_addr)
-{
-    // data buffer to hold final bit mask
-    ecmdDataBufferBase mask(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_iovalid_write_active_mask: Start");
-
-    do
-    {
-        // copy input mask
-        rc_ecmd = i_active_mask.copy(mask);
-        // form final mask based on desired operation (set/clear)
-        if (!i_set_not_clear)
-        {
-            FAPI_DBG("proc_fab_iovalid_write_active_mask: Inverting active mask");
-            rc_ecmd |= mask.invert();
-        }
-
-        // check return code from buffer manipulation operations
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_fab_iovalid_write_active_mask: Error 0x%x setting up active mask data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write register (use OR mask address for set operation,
-        // AND mask address for clear operation)
-        rc = fapiPutScom(i_target,
-                         i_set_not_clear?i_or_mask_addr:i_and_mask_addr,
-                         mask);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_write_active_mask: fapiPutScom error (0x%08X)",
-                     i_set_not_clear?i_or_mask_addr:i_and_mask_addr);
-            break;
-        }
-
-    } while (0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_iovalid_write_active_mask: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set/clear X bus iovalid bits on one chip
-// parameters: i_proc_chip     => structure providing:
-//                                o target for this chip
-//                                o X busses to act on
-//             i_set_not_clear => define desired operation (true=set,
-//                                false=clear)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid_manage_x_links(
-    const proc_fab_iovalid_proc_chip& i_proc_chip,
-    bool i_set_not_clear)
-{
-    ecmdDataBufferBase gp0_iovalid_active(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_iovalid_manage_x_links: Start");
-
-    do
-    {
-        if (i_proc_chip.x0)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X0 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X0_IOVALID_BIT);
-        }
-        if (i_proc_chip.x1)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X1 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X1_IOVALID_BIT);
-        }
-        if (i_proc_chip.x2)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X2 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X2_IOVALID_BIT);
-        }
-        if (i_proc_chip.x3)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_links: Adding link X3 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(X_GP0_X3_IOVALID_BIT);
-        }
-
-        // check aggregate return code from buffer manipulation operations
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_x_links: Error 0x%x setting up active link mask data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write appropriate GP0 mask register to perform desired operation
-        rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip,
-                                                gp0_iovalid_active,
-                                                i_set_not_clear,
-                                                X_GP0_AND_0x04000004,
-                                                X_GP0_OR_0x04000005);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_x_links: Error from proc_fab_iovalid_write_active_mask");
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_iovalid_manage_x_links: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set/clear A bus iovalid bits on one chip
-// parameters: i_proc_chip     => structure providing:
-//                                o target for this chip
-//                                o A busses to act on
-//             i_set_not_clear => define desired operation (true=set,
-//                                false=clear)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid_manage_a_links(
-    const proc_fab_iovalid_proc_chip& i_proc_chip,
-    bool i_set_not_clear)
-{
-    ecmdDataBufferBase gp0_iovalid_active(64);
-    ecmdDataBufferBase secure_iovalid_data(64);
-    ecmdDataBufferBase secure_iovalid_mask(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // secure iovalid attribute
-    uint8_t secure_iovalid_present_attr = 1;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_iovalid_manage_a_links: Start");
-
-    do
-    {
-        // query secure iovalid attribute, used to qualify iovalid set only
-        rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT,
-                           &(i_proc_chip.this_chip),
-                           secure_iovalid_present_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_a_links: Error querying ATTR_CHIP_EC_FEATURE_SECURE_IOVALID_PRESENT");
-            break;
-        }
-            
-        if (i_proc_chip.a0)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A0 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(A_GP0_A0_IOVALID_BIT);
-            if (secure_iovalid_present_attr && i_set_not_clear)
-            {
-                FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A0 to active link mask (secure)");
-                if (i_set_not_clear)
-                {
-                    rc_ecmd |= secure_iovalid_data.setBit(ADU_IOS_LINK_EN_A0_IOVALID_BIT);
-                }
-                rc_ecmd |= secure_iovalid_mask.setBit(ADU_IOS_LINK_EN_A0_IOVALID_BIT);
-            }
-        }
-        if (i_proc_chip.a1)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A1 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(A_GP0_A1_IOVALID_BIT);
-            if (secure_iovalid_present_attr && i_set_not_clear)
-            {
-                FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A1 to active link mask (secure)");
-                if (i_set_not_clear)
-                {
-                    rc_ecmd |= secure_iovalid_data.setBit(ADU_IOS_LINK_EN_A1_IOVALID_BIT);
-                }
-                rc_ecmd |= secure_iovalid_mask.setBit(ADU_IOS_LINK_EN_A1_IOVALID_BIT);
-            }
-        }
-        if (i_proc_chip.a2)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A2 to active link mask");
-            rc_ecmd |= gp0_iovalid_active.setBit(A_GP0_A2_IOVALID_BIT);
-            if (secure_iovalid_present_attr && i_set_not_clear)
-            {
-                FAPI_DBG("proc_fab_iovalid_manage_a_links: Adding link A2 to active link mask (secure)");
-                if (i_set_not_clear)
-                {
-                    rc_ecmd |= secure_iovalid_data.setBit(ADU_IOS_LINK_EN_A2_IOVALID_BIT);
-                }
-                rc_ecmd |= secure_iovalid_mask.setBit(ADU_IOS_LINK_EN_A2_IOVALID_BIT);
-            }
-        }
-        
-        // check aggregate return code from buffer manipulation operations
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_a_links: Error 0x%x setting up active link mask data buffersa",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write appropriate GP0 mask register to perform desired operation
-        rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip,
-                                                gp0_iovalid_active,
-                                                i_set_not_clear,
-                                                A_GP0_AND_0x08000004,
-                                                A_GP0_OR_0x08000005);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_a_links: Error from proc_fab_iovalid_write_active_mask");
-            break;
-        }
-
-        // manage secure iovalids if present
-        // do not attempt to drop secure iovalid
-        // running on FSP (stopclocks), this code will be unable to adjust this register
-        // clearing the GP0 settings should be sufficient to drop the downstream iovalids
-        if (secure_iovalid_present_attr && i_set_not_clear)
-        {
-            rc = fapiPutScomUnderMask(i_proc_chip.this_chip,
-                                      ADU_IOS_LINK_EN_0x02020019,
-                                      secure_iovalid_data,
-                                      secure_iovalid_mask);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_fab_iovalid_manage_a_links: fapiPutScomUnderMask error (ADU_IOS_LINK_EN_0x02020019)");
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_iovalid_manage_a_links: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manage PB RAS FIR setup
-// parameters: i_proc_chip     => structure providing:
-//                                o target for this chip
-//                                o A/X busses to act on
-//             i_set_not_clear => define desired iovalid operation (true=set,
-//                                false=clear)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid_manage_ras_fir(
-    const proc_fab_iovalid_proc_chip& i_proc_chip,
-    bool i_set_not_clear)
-{
-    ecmdDataBufferBase mask_active(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Start");
-
-    do
-    {
-        if (i_proc_chip.x0)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X0");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X0_BIT);
-        }
-        if (i_proc_chip.x1)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X1");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X1_BIT);
-        }
-        if (i_proc_chip.x2)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X2");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X2_BIT);
-        }
-        if (i_proc_chip.x3)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link X3");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_X3_BIT);
-        }
-        if (i_proc_chip.a0)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link A0");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_A0_BIT);
-        }
-        if (i_proc_chip.a1)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link A1");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_A1_BIT);
-        }
-        if (i_proc_chip.a2)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_ras_fir: Configuring RAS FIR for link A2");
-            rc_ecmd |= mask_active.setBit(PB_RAS_FIR_A2_BIT);
-        }
-
-        // check aggregate return code from buffer manipulation operations
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_ras_fir: Error 0x%x setting up active link mask data buffers",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write appropriate RAS FIR mask register to perform desired operation
-        rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip,
-                                                mask_active,
-                                                !i_set_not_clear,
-                                                PB_RAS_FIR_MASK_AND_0x02010C72,
-                                                PB_RAS_FIR_MASK_OR_0x02010C73);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_ras_fir: Error from proc_fab_iovalid_write_active_mask");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_iovalid_manage_ras_fir: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manage PB A FIR setup
-// parameters: i_proc_chip     => structure providing:
-//                                o target for this chip
-//                                o A/X busses to act on
-//             i_set_not_clear => define desired iovalid operation (true=set,
-//                                false=clear)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid_manage_a_fir(
-    const proc_fab_iovalid_proc_chip& i_proc_chip,
-    bool i_set_not_clear)
-{
-    ecmdDataBufferBase or_data(64);
-    ecmdDataBufferBase mask_active(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_iovalid_manage_a_fir: Start");
-
-    do
-    {
-        if (i_proc_chip.a0)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_a_fir: Configuring A FIR for link A0");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_A_FIR_A0_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-        if (i_proc_chip.a1)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_a_fir: Configuring A FIR for link A1");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_A_FIR_A1_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-        if (i_proc_chip.a2)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_a_fir: Configuring A FIR for link A2");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_A_FIR_A2_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-
-        // check aggregate return code from buffer manipulation operations
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_a_fir: Error 0x%x setting up active link mask data buffers",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write appropriate RAS FIR mask register to perform desired operation
-        rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip,
-                                                mask_active,
-                                                !i_set_not_clear,
-                                                PB_A_FIR_MASK_AND_0x08010804,
-                                                PB_A_FIR_MASK_OR_0x08010805);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_a_fir: Error from proc_fab_iovalid_write_active_mask");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_iovalid_manage_a_fir: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to manage PB X FIR setup
-// parameters: i_proc_chip     => structure providing:
-//                                o target for this chip
-//                                o A/X busses to act on
-//             i_set_not_clear => define desired iovalid operation (true=set,
-//                                false=clear)
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid_manage_x_fir(
-    const proc_fab_iovalid_proc_chip& i_proc_chip,
-    bool i_set_not_clear)
-{
-    ecmdDataBufferBase or_data(64);
-    ecmdDataBufferBase mask_active(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("proc_fab_iovalid_manage_x_fir: Start");
-
-    do
-    {
-        if (i_proc_chip.x0)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_fir: Configuring X FIR for link X0");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_X_FIR_X0_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-        if (i_proc_chip.x1)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_fir: Configuring X FIR for link X1");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_X_FIR_X1_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-        if (i_proc_chip.x2)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_fir: Configuring X FIR for link X2");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_X_FIR_X2_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-        if (i_proc_chip.x3)
-        {
-            FAPI_DBG("proc_fab_iovalid_manage_x_fir: Configuring X FIR for link X3");
-            rc_ecmd |= or_data.setDoubleWord(0, PB_X_FIR_X3_BIT_MASK);
-            rc_ecmd |= mask_active.setOr(or_data, 0, 64);
-        }
-
-        // check aggregate return code from buffer manipulation operations
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_x_fir: Error 0x%x setting up active link mask data buffers",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write appropriate RAS FIR mask register to perform desired operation
-        rc = proc_fab_iovalid_write_active_mask(i_proc_chip.this_chip,
-                                                mask_active,
-                                                !i_set_not_clear,
-                                                PB_X_FIR_MASK_AND_0x04010C04,
-                                                PB_X_FIR_MASK_OR_0x04010C05);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_fab_iovalid_manage_x_fir: Error from proc_fab_iovalid_write_active_mask");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("proc_fab_iovalid_manage_x_fir: End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// HWP entry point
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid(
-    std::vector<proc_fab_iovalid_proc_chip>& i_proc_chips,
-    bool i_set_not_clear)
-{
-    // return code
-    fapi::ReturnCode rc;
-    // iterator for HWP input vector
-    std::vector<proc_fab_iovalid_proc_chip>::const_iterator iter;
-
-    // partial good attributes
-    uint8_t abus_enable_attr;
-    uint8_t xbus_enable_attr;
-    bool x_changed = false;
-    bool a_changed = false;
-
-    // mark HWP entry
-    FAPI_IMP("proc_fab_iovalid: Entering ...");
-
-    do
-    {
-        // loop over all chips in input vector
-        for (iter = i_proc_chips.begin();
-             iter != i_proc_chips.end();
-             iter++)
-        {
-            // process X links
-            if (iter->x0 ||
-                iter->x1 ||
-                iter->x2 ||
-                iter->x3)
-            {
-                // query XBUS partial good attribute
-                rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE,
-                                   &(iter->this_chip),
-                                   xbus_enable_attr);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error querying ATTR_PROC_X_ENABLE");
-                    break;
-                }
-
-                if (xbus_enable_attr != fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE)
-                {
-                    FAPI_ERR("proc_fab_iovalid: Partial good attribute error");
-                    const fapi::Target & TARGET = iter->this_chip;
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_X_PARTIAL_GOOD_ERR);
-                    break;
-                }
-
-                rc = proc_fab_iovalid_manage_x_links(*iter, i_set_not_clear);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_x_links");
-                    break;
-                }
-
-                rc = proc_fab_iovalid_manage_x_fir(*iter, i_set_not_clear);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_x_fir");
-                    break;
-                }
-
-                x_changed = true;
-            }
-
-            // process A links
-            if (iter->a0 ||
-                iter->a1 ||
-                iter->a2)
-            {
-                // query ABUS partial good attribute
-                rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
-                                   &(iter->this_chip),
-                                   abus_enable_attr);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error querying ATTR_PROC_A_ENABLE");
-                    break;
-                }
-
-                if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE)
-                {
-                    FAPI_ERR("proc_fab_iovalid: Partial good attribute error");
-                    const fapi::Target & TARGET = iter->this_chip;
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_FAB_IOVALID_A_PARTIAL_GOOD_ERR);
-                    break;
-                }
-
-                rc = proc_fab_iovalid_manage_a_links(*iter, i_set_not_clear);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_a_links");
-                    break;
-                }
-
-                rc = proc_fab_iovalid_manage_a_fir(*iter, i_set_not_clear);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_a_fir");
-                    break;
-                }
-
-                a_changed = true;
-            }
-
-            if (x_changed || a_changed)
-            {
-                rc = proc_fab_iovalid_manage_ras_fir(*iter, i_set_not_clear);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_fab_iovalid: Error from proc_fab_iovalid_manage_ras_fir");
-                    break;
-                }
-            }
-        }
-    } while(0);
-
-    // log function exit
-    FAPI_IMP("proc_fab_iovalid: Exiting ...");
-    return rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H
deleted file mode 100644
index 90b5f941f..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H
+++ /dev/null
@@ -1,155 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_fab_iovalid.H,v 1.10 2013/05/15 04:18:04 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_fab_iovalid.H
-// *! DESCRIPTION : Manage X/A link iovalid controls (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *! Manage fabric X/A link iovalid controls, which control the
-// *! logical link layer fabric traffic.
-// *!
-// *! The iovalid controls are intended to be raised in the IPL flow
-// *! after the underlying physical link layer is running, to start the
-// *! flow of fabric frames.
-// *!
-// *! The iovalid controls are intended to be lowered prior to stopping
-// *! the clocks in the dump process (to provide a clean dump state,
-// *! assuming that the logical layer is quiesced).
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_FAB_IOVALID_H_
-#define _PROC_FAB_IOVALID_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// HWP argument structure defining properties of this chip
-struct proc_fab_iovalid_proc_chip
-{
-    // target for this chip
-    fapi::Target this_chip;
-
-    // X busses to operate on
-    bool x0;
-    bool x1;
-    bool x2;
-    bool x3;
-
-    // A busses to operate on
-    bool a0;
-    bool a1;
-    bool a2;
-};
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_fab_iovalid_FP_t)(std::vector<proc_fab_iovalid_proc_chip>&,
-                         bool);
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// GP0 register bit/field definitions
-const uint8_t X_GP0_X0_IOVALID_BIT = 48;
-const uint8_t X_GP0_X1_IOVALID_BIT = 49;
-const uint8_t X_GP0_X2_IOVALID_BIT = 50;
-const uint8_t X_GP0_X3_IOVALID_BIT = 51;
-
-const uint8_t A_GP0_A0_IOVALID_BIT = 48;
-const uint8_t A_GP0_A1_IOVALID_BIT = 49;
-const uint8_t A_GP0_A2_IOVALID_BIT = 50;
-
-// ADU Secure Iovalid register bit/field definitions
-const uint8_t ADU_IOS_LINK_EN_A0_IOVALID_BIT = 0;
-const uint8_t ADU_IOS_LINK_EN_A1_IOVALID_BIT = 1;
-const uint8_t ADU_IOS_LINK_EN_A2_IOVALID_BIT = 2;
-
-// PB RAS FIR register bit/field definitions
-const uint8_t PB_RAS_FIR_X0_BIT = 0;
-const uint8_t PB_RAS_FIR_X1_BIT = 1;
-const uint8_t PB_RAS_FIR_X2_BIT = 2;
-const uint8_t PB_RAS_FIR_X3_BIT = 3;
-const uint8_t PB_RAS_FIR_A0_BIT = 4;
-const uint8_t PB_RAS_FIR_A1_BIT = 5;
-const uint8_t PB_RAS_FIR_A2_BIT = 6;
-
-// PB X FIR register bit/field definitions
-const uint64_t PB_X_FIR_X0_BIT_MASK = 0xA000800000000000ULL;
-const uint64_t PB_X_FIR_X1_BIT_MASK = 0x1400400000000000ULL;
-const uint64_t PB_X_FIR_X2_BIT_MASK = 0x0280200000000000ULL;
-const uint64_t PB_X_FIR_X3_BIT_MASK = 0x0050100000000000ULL;
-
-// PB A FIR register bit/field definitions
-const uint64_t PB_A_FIR_A0_BIT_MASK = 0x9281980040000000ULL;
-const uint64_t PB_A_FIR_A1_BIT_MASK = 0x4850066020000000ULL;
-const uint64_t PB_A_FIR_A2_BIT_MASK = 0x240A001990000000ULL;
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// function: FAPI proc_fab_iovalid HWP entry point
-//           operates on chips passed in i_proc_chips argument to perform
-//           desired iovalid manipulation (set or clear) on specified X/A busses
-// parameters: i_proc_chips    => vector of proc_fab_iovalid_proc_chip
-//                                structures which defines busses to
-//                                act on
-//             i_set_not_clear => define target iovalid operation (true=set,
-//                                false=clear)
-// returns: FAPI_RC_SUCCESS if all specified operations complete successfully,
-//          else return code for failing operation
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_fab_iovalid(
-    std::vector<proc_fab_iovalid_proc_chip>& i_proc_chips,
-    bool i_set_not_clear);
-
-} // extern "C"
-
-#endif // _PROC_FAB_IOVALID_H_
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.C b/src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.C
deleted file mode 100644
index 1b10c0c7d..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.C
+++ /dev/null
@@ -1,236 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#include    <stdint.h>
-#include    <map>
-
-#include    <trace/interface.H>
-#include    <initservice/taskargs.H>
-#include    <errl/errlentry.H>
-
-#include    <isteps/hwpisteperror.H>
-#include    <errl/errludtarget.H>
-
-#include    <initservice/isteps_trace.H>
-
-#include    <hwas/common/deconfigGard.H>
-#include    <hwas/common/hwasCommon.H>
-
-#include    <sbe/sbeif.H>
-
-//  targeting support
-#include    <targeting/common/commontargeting.H>
-#include    <targeting/common/utilFilter.H>
-#include    <targeting/common/trace.H>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-
-#include    <pbusLinkSvc.H>
-
-//  Uncomment these files as they become available:
-#include    "io_restore_erepair.H"
-// #include    "fabric_io_dccal/fabric_io_dccal.H"
-// #include    "fabric_erepair/fabric_erepair.H"
-#include    "fabric_io_run_training/fabric_io_run_training.H"
-#include    "io_pre_trainadv.H"
-#include    "io_post_trainadv.H"
-// #include    "host_startprd_pbus/host_startprd_pbus.H"
-// #include    "host_attnlisten_proc/host_attnlisten_proc.H"
-#include    "proc_fab_iovalid/proc_fab_iovalid.H"
-#include    <diag/prdf/prdfMain.H>
-#include    "fabric_io_dccal/fabric_io_dccal.H"
-
-// eRepair Restore
-#include <erepairAccessorHwpFuncs.H>
-
-#ifdef CONFIG_IPLTIME_CHECKSTOP_ANALYSIS
-    #include    <occ/occ_common.H>
-#endif
-
-namespace EDI_EI_INITIALIZATION
-{
-/*
- *
- * brief function to check if peer target is present.
- *
- * returns true if peer is present, else false
- *
- */
-bool isPeerPresent(TARGETING::TargetHandle_t i_targetPtr)
-{
-    bool l_flag = false;
-
-    do
-    {
-        if( NULL == i_targetPtr)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "isPeerPresent:ERR: Null input target");
-            break;
-        }
-
-        EntityPath l_peerPath;
-        bool l_exists = i_targetPtr->tryGetAttr<ATTR_PEER_PATH>(l_peerPath);
-
-        if( false == l_exists)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "isPeerPresent:ERR: Failed to get ATTR_PEER_PATH for "
-                      "target HUID:0x%08x", get_huid(i_targetPtr));
-            break;
-        }
-
-        EntityPath::PathElement l_pa = l_peerPath.pathElementOfType(TYPE_NODE);
-
-        if(l_pa.type == TYPE_NA)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "isPeerPresent:ERR: Cannot find Node into in peer path: "
-                      "[%s],target HUID:0x%08x", l_peerPath.toString(),
-                      get_huid(i_targetPtr));
-            break;
-        }
-
-        TARGETING::Target * sys = NULL;
-        TARGETING::targetService().getTopLevelTarget( sys );
-        assert(sys != NULL);
-
-        TARGETING::ATTR_HB_EXISTING_IMAGE_type hb_images =
-            sys->getAttr<TARGETING::ATTR_HB_EXISTING_IMAGE>();
-
-        // ATTR_HB_EXISTING_IMAGE only gets set on a multi-drawer system.
-        // Currently set up in host_sys_fab_iovalid_processing() which only
-        // gets called if there are multiple physical nodes.   It eventually
-        // needs to be setup by a hb routine that snoops for multiple nodes.
-        if(hb_images == 0)
-        {
-            // Single node system
-            break;
-        }
-
-        // continue - multi-node
-        uint8_t node_map[8];
-        l_exists =
-        sys->tryGetAttr<TARGETING::ATTR_FABRIC_TO_PHYSICAL_NODE_MAP>(node_map);
-
-        if( false == l_exists )
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "isPeerPresent:ERR: Failed to get "
-                      "ATTR_FABRIC_TO_PHYSICAL_NODE_MAP "
-                      "for system target. Input target HUID:0x%08x",
-                      get_huid(i_targetPtr));
-            break;
-        }
-
-        if(l_pa.instance < (sizeof(TARGETING::ATTR_HB_EXISTING_IMAGE_type) * 8))
-        {
-            // set mask
-            TARGETING::ATTR_HB_EXISTING_IMAGE_type mask = 0x1 <<
-                      ((sizeof(TARGETING::ATTR_HB_EXISTING_IMAGE_type) * 8) -1);
-
-            if( 0 != ((mask >> l_pa.instance) & hb_images ) )
-            {
-                l_flag = true;
-            }
-        }
-
-    }while(0);
-
-    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-              "isPeerPresent:[%d], HUID:0x%08x",l_flag,get_huid(i_targetPtr));
-
-    return l_flag;
-}
-//
-//  function to unfence inter-enclosure abus links
-//
-errlHndl_t  smp_unfencing_inter_enclosure_abus_links()
-{
-    errlHndl_t l_errl = NULL;
-/*
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "smp_unfencing_inter_enclosure_abus_links entry" );
-
-    // Get all chip/chiplet targets
-    TARGETING::TargetHandleList l_cpuTargetList;
-    getAllChips(l_cpuTargetList, TYPE_PROC);
-
-    std::vector<proc_fab_iovalid_proc_chip> l_smp;
-
-    for (TargetHandleList::const_iterator l_cpu_iter = l_cpuTargetList.begin();
-         l_cpu_iter != l_cpuTargetList.end();
-         ++l_cpu_iter)
-    {
-        proc_fab_iovalid_proc_chip l_procEntry;
-
-        TARGETING::TargetHandle_t l_pTarget = *l_cpu_iter;
-        fapi::Target l_fapiproc_target(TARGET_TYPE_PROC_CHIP, l_pTarget);
-
-        l_procEntry.this_chip = l_fapiproc_target;
-        l_procEntry.a0 = false;
-        l_procEntry.a1 = false;
-        l_procEntry.a2 = false;
-        l_procEntry.x0 = false;
-        l_procEntry.x1 = false;
-        l_procEntry.x2 = false;
-        l_procEntry.x3 = false;
-
-        TARGETING::TargetHandleList l_abuses;
-        getChildChiplets( l_abuses, l_pTarget, TYPE_ABUS );
-        bool l_flag = false;
-        for (TargetHandleList::const_iterator l_abus_iter = l_abuses.begin();
-            l_abus_iter != l_abuses.end();
-            ++l_abus_iter)
-        {
-            TARGETING::TargetHandle_t l_pAbusTarget = *l_abus_iter;
-            ATTR_CHIP_UNIT_type l_srcID;
-            l_srcID = l_pAbusTarget->getAttr<ATTR_CHIP_UNIT>();
-            l_flag = isPeerPresent(l_pAbusTarget);
-            switch (l_srcID)
-            {
-                case 0: l_procEntry.a0 = l_flag; break;
-                case 1: l_procEntry.a1 = l_flag; break;
-                case 2: l_procEntry.a2 = l_flag; break;
-               default: break;
-            }
-        }
-
-        l_smp.push_back(l_procEntry);
-    }
-
-    FAPI_INVOKE_HWP( l_errl, proc_fab_iovalid, l_smp, true );
-
-    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "%s : proc_fab_iovalid HWP.",
-                (l_errl ? "ERROR" : "SUCCESS"));
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "smp_unfencing_inter_enclosure_abus_links exit" );
-*/
-    return l_errl;
-}
-};
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.H b/src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.H
deleted file mode 100644
index 5cba6a0f4..000000000
--- a/src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.H
+++ /dev/null
@@ -1,43 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/edi_ei_initialization/smp_unfencing_inter_enclosure_abus_links.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef  __SMP_UNFENCING_INTER_ENCLOSURE_ABUS_LINKS_H
-#define  __SMP_UNFENCING_INTER_ENCLOSURE_ABUS_LINKS_H
-
-#include <errl/errlentry.H>
-
-namespace   EDI_EI_INITIALIZATION
-{
-
-/**
- *  @brief   smp_unfencing_inter_enclosure_abus_links
- *
- *           Lower functional fences of inter-enclosure Abus links
- *
- *  return  errlHndl if an error occurs
- *
- */
-errlHndl_t  smp_unfencing_inter_enclosure_abus_links();
-
-}
-
-#endif
diff --git a/src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.C b/src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.C
deleted file mode 100644
index 633bc4a62..000000000
--- a/src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.C
+++ /dev/null
@@ -1,688 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file establish_system_smp.C
- *
- *  Support file for IStep: establish_system_smp
- *   Establish System SMP
- *
- *  *****************************************************************
- *  THIS FILE WAS GENERATED ON 2012-04-11:1611
- *  *****************************************************************
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-#include <sys/time.h>
-
-#include    <trace/interface.H>
-#include    <initservice/taskargs.H>
-#include    <errl/errlentry.H>
-
-#include    <initservice/isteps_trace.H>
-
-#include    <isteps/hwpisteperror.H>
-#include    <errl/errludtarget.H>
-
-#include    <istep_mbox_msgs.H>
-#include    <vfs/vfs.H>
-
-//  targeting support
-#include    <targeting/common/commontargeting.H>
-#include    <smp_unfencing_inter_enclosure_abus_links.H>
-#include    <targeting/common/utilFilter.H>
-#include    <targeting/common/attributes.H>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-#include    <isteps/hwpf_reasoncodes.H>
-
-#include    "establish_system_smp.H"
-#include    <mbox/ipc_msg_types.H>
-#include    <intr/interrupt.H>
-
-//  Uncomment these files as they become available:
-// #include    "host_coalesce_host/host_coalesce_host.H"
-#include    "p8_block_wakeup_intr/p8_block_wakeup_intr.H"
-#include    "p8_cpu_special_wakeup.H"
-#include    <initservice/istepdispatcherif.H>
-
-namespace   ESTABLISH_SYSTEM_SMP
-{
-
-using   namespace   ISTEP;
-using   namespace   ISTEP_ERROR;
-using   namespace   ERRORLOG;
-using   namespace   TARGETING;
-using   namespace   fapi;
-using   namespace   EDI_EI_INITIALIZATION;
-
-/******************************************************************************/
-// Globals/Constants
-/******************************************************************************/
-const uint8_t HB_COALESCE_WAITING_FOR_MSG = 0x0;
-const uint8_t HB_COALESCE_MSG_DONE = 0x1;
-const uint32_t MAX_TIME_ALLOWED_MS = 10000;
-const uint8_t NUMBER_OF_POSSIBLE_NODES = 8;
-const uint8_t CONTINUE_WAIT_FOR_MSGS = 0x2;
-const uint8_t TIME_EXPIRED=0x3;
-
-//******************************************************************************
-//host_coalese_timer function
-//******************************************************************************
-void* host_coalese_timer(void* i_msgQPtr)
-
-{
-    int rc=0;
-
-    msg_t* msg = msg_allocate();
-    msg->type = HOST_COALESCE_TIMER_MSG;
-    uint32_t l_time_ms =0;
-
-    msg_q_t* msgQ = static_cast<msg_q_t*>(i_msgQPtr);
-
-
-    //this loop will be broken when the main thread recieves
-    //all the messages and the timer thread recieves the
-    //HB_COALESCE_MSG_DONE message
-
-    do
-    {
-        if (l_time_ms < MAX_TIME_ALLOWED_MS)
-        {
-            msg->data[1] = CONTINUE_WAIT_FOR_MSGS;
-        }
-        else
-        {
-            msg->data[1]=TIME_EXPIRED;
-        }
-
-        rc= msg_sendrecv(*msgQ, msg);
-        if (rc)
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                        "coalese host message timer failed msg sendrecv.");
-        }
-        if (msg->data[1] == HB_COALESCE_MSG_DONE)
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                        "coalese host message timer not needed.");
-            break;
-        }
-
-        nanosleep(0,NS_PER_MSEC);
-        l_time_ms++;
-
-    }while(1);
-
-    msg_free(msg);
-
-    return NULL;
-}
-
-//******************************************************************************
-// call_host_coalesce_host function
-//******************************************************************************
-errlHndl_t call_host_coalesce_host( )
-{
-    errlHndl_t  l_errl  =   NULL;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_host_coalesce_host entry" );
-
-    std::vector<TARGETING::EntityPath> present_drawers;
-
-
-    TARGETING::Target * sys = NULL;
-    TARGETING::targetService().getTopLevelTarget( sys );
-    if (sys == NULL)
-    {
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_host_coalesce_host: error getting system target");
-        assert(0);
-    }
-
-    TARGETING::ATTR_HB_EXISTING_IMAGE_type hb_existing_image = 0;
-
-    hb_existing_image = sys->getAttr<TARGETING::ATTR_HB_EXISTING_IMAGE>();
-
-    if (hb_existing_image == 0)
-    {
-        //single node system so do nothing
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_host_coalesce_host on a single node system is a no-op" );
-    }
-    else
-    {
-
-        // This msgQ catches the reponses to messages sent from each
-        //node to verify the IPC connection
-        msg_q_t msgQ = msg_q_create();
-        l_errl = MBOX::msgq_register(MBOX::HB_COALESCE_MSGQ,msgQ);
-
-        if(l_errl)
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "call_host_coalesce_host:msgq_register failed" );
-            return l_errl;
-        }
-
-        //multi-node system
-        uint8_t node_map[NUMBER_OF_POSSIBLE_NODES];
-        uint64_t msg_count = 0;
-
-        bool rc =
-            sys->tryGetAttr<TARGETING::ATTR_FABRIC_TO_PHYSICAL_NODE_MAP>
-            (node_map);
-        if (rc == false)
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "call_host_coalesce_host:failed to get node map" );
-            assert(0);
-        }
-
-        // The assertion is that the hostboot instance must be equal to
-        // the logical node we are running on. The ideal would be to have
-        // a function call that would return the HB instance number.
-        const INTR::PIR_t masterCpu = task_getcpuid();
-        uint64_t this_node = masterCpu.nodeId;
-
-        //loop though all possible drawers whether they exist or not
-        // An invalid or non-existant logical node number in that drawer
-        // indicates that the drawer does not exist.
-        TARGETING::ATTR_HB_EXISTING_IMAGE_type mask = 0x0;
-        TARGETING::ATTR_HB_EXISTING_IMAGE_type master_node_mask = 0x0;
-
-        for(uint16_t drawer = 0; drawer < NUMBER_OF_POSSIBLE_NODES; ++drawer)
-        {
-            uint16_t node = node_map[drawer];
-
-            if(node < NUMBER_OF_POSSIBLE_NODES)
-            {
-
-                // set mask to msb
-                mask = 0x1 <<
-                    (NUMBER_OF_POSSIBLE_NODES -1);
-
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "mask=%X,hb_existing_image=%X",
-                           mask,hb_existing_image);
-                if( 0 != ((mask >> node) & hb_existing_image ) )
-                {
-                    //The first nonzero bit in hb_existing_image represents the
-                    // master node, set mask for later comparison
-                    if (master_node_mask == 0)
-                    {
-                        master_node_mask = mask;
-                    }
-                    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "send coalese host message to drawer %d",
-                               drawer );
-                    ++msg_count;
-                    msg_t * msg = msg_allocate();
-                    msg->type = IPC::IPC_TEST_CONNECTION;
-                    msg->data[0] = drawer;     // target drawer
-                    msg->data[1] = this_node;  // node to send a msg back to
-                    l_errl = MBOX::send(MBOX::HB_IPC_MSGQ, msg, node);
-                    if (l_errl)
-                    {
-                        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                                "MBOX::send failed");
-                        break;
-                    }
-                }
-            }
-        }
-
-        //if the send failed we just want to indicate that the
-        //istep failed and not wait for messages to come back from
-        //the other nodes
-        if(l_errl == NULL)
-        {
-            // reset mask to msb
-            mask = 0x1 << (NUMBER_OF_POSSIBLE_NODES -1);
-            //create mask to apply to hb_existing_image for this particular node
-            mask = mask >> this_node;
-
-            if (master_node_mask & (hb_existing_image & mask))
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "Master Node detected, continue allowing "
-                               "istep messages to this node.");
-                INITSERVICE::setAcceptIstepMessages(true);
-            }
-            else
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "This node is not the master node, no longer "
-                               "respond to istep messages.");
-                INITSERVICE::setAcceptIstepMessages(false);
-            }
-
-            //wait for all hb images to respond
-            //want to spawn a timer thread
-            tid_t l_progTid = task_create(
-                       ESTABLISH_SYSTEM_SMP::host_coalese_timer,&msgQ);
-            assert( l_progTid > 0 );
-            while(msg_count)
-            {
-                msg_t* msg = msg_wait(msgQ);
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                        "coalese host message for drawer %d completed.",
-                         msg->data[0]);
-                if (msg->type == HOST_COALESCE_TIMER_MSG)
-                {
-                    if (msg->data[1] == TIME_EXPIRED)
-                    {
-                        //timer has expired
-                        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                                "call_host_coalesce_host failed to "
-                                "receive messages from all hb images in time" );
-                        //tell the timer thread to exit
-                        msg->data[1] = HB_COALESCE_MSG_DONE;
-                        msg_respond(msgQ,msg);
-
-                        //generate an errorlog
-                        /*@
-                         *  @errortype      ERRL_SEV_CRITICAL_SYS_TERM
-                         *  @moduleid       fapi::MOD_HOST_COALESCE_HOST,
-                         *  @reasoncode     fapi::RC_HOST_TIMER_EXPIRED,
-                         *  @userdata1      MAX_TIME_ALLOWED_MS
-                         *  @userdata2      Number of nodes that have not
-                         *                  responded
-                         *
-                         *  @devdesc        messages from other nodes have
-                         *                  not returned in time
-                         */
-                        l_errl = new ERRORLOG::ErrlEntry(
-                                        ERRORLOG::ERRL_SEV_CRITICAL_SYS_TERM,
-                                        fapi::MOD_HOST_COALESCE_HOST,
-                                        fapi::RC_HOST_TIMER_EXPIRED,
-                                        MAX_TIME_ALLOWED_MS,
-                                        msg_count   );
-                        l_errl->collectTrace("ISTEPS_TRACE");
-                        l_errl->collectTrace("IPC");
-                        l_errl->collectTrace("MBOXMSG");
-                        return l_errl;
-
-                    }
-                    else if( msg->data[1] == CONTINUE_WAIT_FOR_MSGS)
-                    {
-                        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                            "coalese host timer continue waiting message.");
-                        msg->data[1] =HB_COALESCE_WAITING_FOR_MSG;
-                        msg_respond(msgQ,msg);
-                    }
-                }
-                else if (msg->type == IPC::IPC_TEST_CONNECTION)
-                {
-                   TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                              "Got response from node %d", msg->data[0] );
-                    --msg_count;
-                    msg_free(msg);
-                }
-
-            }
-
-            //the msg_count should be 0 at this point to have
-            //exited from the loop above.  If the msg count
-            //is not zero then the timer must have expired
-            //and the code would have asserted
-            //Now need to tell the child timer thread to exit
-
-            //temp change while simics takes a long time for BRAZOS to IPL
-            //tmp check to tell the child timer thread to exit if didn't
-            //already timeout
-            if (msg_count ==0)
-            {
-                msg_t* msg = msg_wait(msgQ);
-                if (msg->type == HOST_COALESCE_TIMER_MSG)
-                {
-                    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                            "call_host_coalesce_host received all hb "
-                            "images in time");
-
-                    msg->data[1] = HB_COALESCE_MSG_DONE;
-                    msg_respond(msgQ,msg);
-                }
-            }
-
-            //wait for the child thread to end
-            int l_childsts =0;
-            void* l_childrc = NULL;
-            tid_t l_tidretrc = task_wait_tid(l_progTid,&l_childsts,&l_childrc);
-            if ((static_cast<int16_t>(l_tidretrc) < 0)
-                || (l_childsts != TASK_STATUS_EXITED_CLEAN ))
-            {
-                // the launched task failed or crashed,
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "task_wait_tid failed; l_tidretrc=0x%x, l_childsts=0x%x",
-                    l_tidretrc, l_childsts);
-
-                        //generate an errorlog
-                        /*@
-                         *  @errortype      ERRL_SEV_CRITICAL_SYS_TERM
-                         *  @moduleid       fapi::MOD_HOST_COALESCE_HOST,
-                         *  @reasoncode     fapi::RC_HOST_TIMER_THREAD_FAIL,,
-                         *  @userdata1      l_tidretrc,
-                         *  @userdata2      l_childsts,
-                         *
-                         *  @devdesc        host coalesce host timer thread
-                         *                  failed
-                         */
-                        l_errl = new ERRORLOG::ErrlEntry(
-                                        ERRORLOG::ERRL_SEV_CRITICAL_SYS_TERM,
-                                        fapi::MOD_HOST_COALESCE_HOST,
-                                        fapi::RC_HOST_TIMER_THREAD_FAIL,
-                                        l_tidretrc,
-                                        l_childsts);
-
-                        l_errl->collectTrace("ISTEPS_TRACE");
-                        return l_errl;
-            }
-        }
-
-        MBOX::msgq_unregister(MBOX::HB_COALESCE_MSGQ);
-        msg_q_destroy(msgQ);
-
-
-    }
-
-
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_host_coalesce_host exit" );
-
-    // end task, returning any errorlogs to IStepDisp
-    return l_errl;
-}
-
-//******************************************************************************
-// host_sys_fab_iovalid_processing function
-//******************************************************************************
-void *host_sys_fab_iovalid_processing(void* io_ptr )
-{
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "host_sys_fab_iovalid_processing entry" );
-    // input parameter is actually a msg_t pointer
-    msg_t* io_pMsg = static_cast<msg_t *>(io_ptr);
-    // assume success, unless we hit an error later.
-    io_pMsg->data[0] = INITSERVICE::HWSVR_MSG_SUCCESS;
-
-    errlHndl_t l_errl = NULL;
-
-    // if there is extra data, start processing it
-    if(io_pMsg->extra_data)
-    {
-        iovalid_msg * drawerData = (iovalid_msg *)io_pMsg->extra_data;
-
-        // setup a pointer to the first drawer entry in our data
-        TARGETING::EntityPath * ptr = drawerData->drawers;
-
-        const uint16_t count = drawerData->count;
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                "Master node %s List size = %d bytes Drawer count = %d",
-                ptr->toString(), drawerData->size, count);
-
-        // get FABRIC_TO_PHYSICAL_NODE_MAP
-        TARGETING::Target * sys = NULL;
-        TARGETING::targetService().getTopLevelTarget( sys );
-        assert(sys != NULL);
-
-        uint8_t node_map[8];
-        bool rc = sys->tryGetAttr<TARGETING::ATTR_FABRIC_TO_PHYSICAL_NODE_MAP>
-                    (node_map);
-        assert(rc == true);
-
-        TARGETING::ATTR_HB_EXISTING_IMAGE_type hb_existing_image = 0;
-
-        // create a vector with the present drawers
-        std::vector<TARGETING::EntityPath> present_drawers;
-
-        for(uint8_t i = 0; i < count; i++)
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                    "list entry[%d] - %s", i, ptr->toString());
-
-            present_drawers.push_back(*ptr);
-
-            TARGETING::EntityPath::PathElement pe =
-                ptr->pathElementOfType(TARGETING::TYPE_NODE);
-
-            // pe.instance is the drawer number - convert to logical node
-            uint8_t logical_node = node_map[pe.instance];
-
-            // set mask to msb of bitmap
-            TARGETING::ATTR_HB_EXISTING_IMAGE_type mask = 0x1 <<
-                (NUMBER_OF_POSSIBLE_NODES -1);
-
-            // set bit for this logical node.
-            hb_existing_image |= (mask >> logical_node);
-
-            ptr++;
-        }
-
-        sys->setAttr<TARGETING::ATTR_HB_EXISTING_IMAGE>(hb_existing_image);
-
-        // $TODO RTC:63128 - exchange between present drawers to agree
-        // on valid endpoints
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                  "$TODO RTC:63128 - hb instances exchange and agree on cfg");
-
-        // after agreement, open abuses as required
-        l_errl = smp_unfencing_inter_enclosure_abus_links();
-        if (l_errl)
-        {
-            io_pMsg->data[0] = l_errl->plid();
-            errlCommit(l_errl, HWPF_COMP_ID);
-        }
-    }
-    else
-    {
-        // message needs to have at least one entry
-        // in the drawer list, else we will say invalid msg
-        io_pMsg->data[0] = INITSERVICE::HWSVR_INVALID_MESSAGE;
-    }
-
-    io_pMsg->data[1] = 0;
-
-    // if there wasn't an error
-    if (io_pMsg->data[0] == INITSERVICE::HWSVR_MSG_SUCCESS)
-    {
-        uint32_t l_plid = 0;
-
-        // loop thru all proc and find all functional ex units
-        // Get all functional proc chip targets
-        TARGETING::TargetHandleList l_procTargetList;
-        getAllChips(l_procTargetList, TYPE_PROC);
-        for (TargetHandleList::const_iterator l_procIter =
-             l_procTargetList.begin();
-             l_procIter != l_procTargetList.end();
-             ++l_procIter)
-        {
-            const TARGETING::Target* l_pChipTarget = *l_procIter;
-
-            // Get EX list under this proc
-            TARGETING::TargetHandleList l_exList;
-            getChildChiplets( l_exList, l_pChipTarget, TYPE_EX );
-
-            for (TargetHandleList::const_iterator
-                l_exIter = l_exList.begin();
-                l_exIter != l_exList.end();
-                ++l_exIter)
-            {
-                const TARGETING::Target * l_exTarget = *l_exIter;
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                    "Running p8_block_wakeup_intr(SET) on EX target HUID %.8X",
-                    TARGETING::get_huid(l_exTarget));
-
-                fapi::Target l_fapi_ex_target( TARGET_TYPE_EX_CHIPLET,
-                         (const_cast<TARGETING::Target*>(l_exTarget)) );
-
-                FAPI_INVOKE_HWP(l_errl,
-                                p8_block_wakeup_intr,
-                                l_fapi_ex_target,
-                                BLKWKUP_SET);
-                if ( l_errl )
-                {
-                    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                              "ERROR : p8_block_wakeup_intr(SET)" );
-                    // capture the target data in the elog
-                    ErrlUserDetailsTarget(l_exTarget).addToLog( l_errl );
-                    if (l_plid != 0)
-                    {
-                        // use the same plid as the previous
-                        l_errl->plid(l_plid);
-                    }
-                    else
-                    {
-                        // set this plid for the caller to see
-                        l_plid = l_errl->plid();
-                        io_pMsg->data[0] = l_errl->plid();
-                    }
-                    errlCommit( l_errl, HWPF_COMP_ID );
-                }
-                else
-                {
-                    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "SUCCESS : p8_block_wakeup_intr(SET)" );
-                }
-
-                // disable special wakeup
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                    "Running p8_cpu_special_wakeup (DISABLE) on EX target"
-                    " HUID %.8X",
-                    TARGETING::get_huid(l_exTarget));
-
-                FAPI_INVOKE_HWP(l_errl,
-                                p8_cpu_special_wakeup,
-                                l_fapi_ex_target,
-                                SPCWKUP_DISABLE,
-                                HOST);
-
-                if(l_errl)
-                {
-                    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                               "Disable p8_cpu_special_wakeup ERROR :"
-                               " Returning errorlog, reason=0x%x",
-                               l_errl->reasonCode() );
-
-                    // capture the target data in the elog
-                    ErrlUserDetailsTarget(l_exTarget).addToLog( l_errl );
-
-                    break;
-                }
-                else
-                {
-                    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                              "SUCCESS: Disable special wakeup");
-                }
-            } // for ex
-        } // for proc
-    }
-
-    // response will be sent by calling routine
-    // IStepDispatcher::handleProcFabIovalidMsg()
-    // which will also execute the procedure to winkle all cores
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "host_sys_fab_iovalid_processing exit data[0]=0x%X",
-            io_pMsg->data[0]);
-    return NULL;
-}
-
-
-errlHndl_t enableSpecialWakeup()
-{
-    errlHndl_t l_errl = NULL;
-    // loop thru all proc and find all functional ex units
-    TARGETING::TargetHandleList l_procTargetList;
-    getAllChips(l_procTargetList, TYPE_PROC);
-    for (TargetHandleList::const_iterator l_procIter =
-         l_procTargetList.begin();
-         l_procIter != l_procTargetList.end();
-         ++l_procIter)
-    {
-        const TARGETING::Target* l_pChipTarget = *l_procIter;
-
-        // Get EX list under this proc
-        TARGETING::TargetHandleList l_exList;
-        getChildChiplets( l_exList, l_pChipTarget, TYPE_EX );
-
-        for (TargetHandleList::const_iterator
-             l_exIter = l_exList.begin();
-             l_exIter != l_exList.end();
-             ++l_exIter)
-        {
-            const TARGETING::Target * l_exTarget = *l_exIter;
-
-            fapi::Target l_fapi_ex_target
-                ( TARGET_TYPE_EX_CHIPLET,
-                  (const_cast<TARGETING::Target*>(l_exTarget)) );
-
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "Running p8_cpu_special_wakeup(ENABLE) "
-                      "on EX target HUID %.8X",
-                      TARGETING::get_huid(l_exTarget));
-
-            FAPI_INVOKE_HWP(l_errl,
-                            p8_cpu_special_wakeup,
-                            l_fapi_ex_target,
-                            SPCWKUP_ENABLE,
-                            HOST);
-
-            if(l_errl)
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "Enable p8_cpu_special_wakeup ERROR :"
-                           " Returning errorlog, reason=0x%x",
-                           l_errl->reasonCode() );
-
-                // capture the target data in the elog
-                ErrlUserDetailsTarget(l_exTarget).addToLog( l_errl );
-
-                break;
-            }
-            else
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                          "SUCCESS: Enable special wakeup");
-            }
-        }
-        if(l_errl)
-        {
-            break;
-        }
-    }
-    return l_errl;
-}
-
-};   // end namespace
diff --git a/src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.H b/src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.H
deleted file mode 100644
index 34565adee..000000000
--- a/src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.H
+++ /dev/null
@@ -1,126 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/establish_system_smp/establish_system_smp.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef  __ESTABLISH_SYSTEM_SMP_ESTABLISH_SYSTEM_SMP_H
-#define  __ESTABLISH_SYSTEM_SMP_ESTABLISH_SYSTEM_SMP_H
-
-/**
- *  @file establish_system_smp.H
- *
- *  Establish System SMP
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  *****************************************************************
- *  THIS FILE WAS GENERATED ON 2012-04-11:1611
- *  *****************************************************************
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
- /*  @tag isteplist
- *  @docversion     v1.35 (04/11/13)
- *  @istepname      establish_system_smp
- *  @istepnum       18
- *  @istepdesc      Establish System SMP
- *
- *  @{
- *      @substepnum     9
- *      @substepname    host_sys_fab_iovalid_processing
- *      @substepdesc    : Lower functional fences on sys SMP
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     12
- *      @substepname    host_coalesce_host
- *      @substepdesc    : Create single host image
- *          @target_sched   serial
- *  @}
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-namespace   ESTABLISH_SYSTEM_SMP
-{
-
- /**
- *  @brief   structure to hold iovalid processing data
- *
- */
-    struct iovalid_msg {
-        uint32_t               size;       //!Data length in bytes
-        uint16_t               type;       //! IPL/CCM type message
-        uint16_t               count;      //! Number of drawers in data
-        TARGETING::EntityPath drawers[0];  //! Place holder for data
-    };
-
- /**
- *  enum used for sending messages within establishing system smp
- */
-    enum
-    {
-        HOST_COALESCE_TIMER_MSG =   0xA1,
-    };
-
-/**
- *  @brief   host_coalesce_host
- *
- *           Create single host image
- *
- *  param[in,out] io_pMsg - input message buffer
- *                          also used for response message to FSP
- *
- *  return any errlogs to istep
- *
- */
-errlHndl_t call_host_coalesce_host( );
-
-/**
- *  @brief   host_sys_fab_iovalid_processing
- *
- *           Do hostboot side processing for fsp istep
- *           sys_proc_fab_iovalid
- *
- *  param[in,out] io_pMsg - input message buffer with drawer info,
- *                          also used for response message to FSP
- *  return NULL
- */
-void* host_sys_fab_iovalid_processing( void* io_pMsg );
-
-/**
- * @brief  enableSpecialWakeup on all functional cores after
- *         winkle wakeup.
- *
- * @return error log handle
- */
-errlHndl_t enableSpecialWakeup();
-
-};   // end namespace
-
-#endif
-
diff --git a/src/usr/hwpf/hwp/establish_system_smp/makefile b/src/usr/hwpf/hwp/establish_system_smp/makefile
deleted file mode 100644
index 3af914fad..000000000
--- a/src/usr/hwpf/hwp/establish_system_smp/makefile
+++ /dev/null
@@ -1,60 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/establish_system_smp/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2012,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = establish_system_smp
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/usr/initservice/istepdispatcher
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  NOTE: add the base istep dir here.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/establish_system_smp
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization
-
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/establish_system_smp/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += establish_system_smp.o
-
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/establish_system_smp/<HWP_dir>
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/fapiHwpExecInitFile.C b/src/usr/hwpf/hwp/fapiHwpExecInitFile.C
deleted file mode 100644
index f1b61b26e..000000000
--- a/src/usr/hwpf/hwp/fapiHwpExecInitFile.C
+++ /dev/null
@@ -1,2895 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/hwpf/working/hwp/fapiHwpExecInitFile.C,v $                      */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file fapiHwpExecInitFile.C
- *
- *  @brief Implements a Hardware Procedure to execute an initfile.
- */
-// $Id: fapiHwpExecInitFile.C,v 1.22 2014/08/05 15:04:40 kahnevan Exp $
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          camvanng    09/29/2011  Created.
- *                          andrewg     11/09/2011  Multi-dimension array support
- *                          camvanng    11/16/2011  Support endianness &
- *                                                  32-bit platforms.  Support
- *                                                  system & target attributes.
- *                          camvanng    12/06/2011  Optimize code to check for
- *                                                  endianness at compile time
- *                          camvanng    01/06/2012  Support for writing an
- *                                                  attribute to a SCOM register
- *                          mjjones     01/13/2012  Use new ReturnCode interfaces
- *                          camvanng    01/20/2012  Support for using a range
- *                                                  indexes for array attributes
- *                          mjjones     02/21/2012  Use new Target toEcmdString
- *                          camvanng    04/12/2012  Right justify SCOM data
- *                          camvanng    04/30/2012  Optimization - Minimize scom
- *                                                  operations by combining
- *                                                  PutScomUnderMask ops to same
- *                                                  Scom register
- *                                                  Turn off most debug traces
- *                          camvanng    05/07/2012  Support for associated target
- *                                                  attributes
- *                          camvanng    05/22/2012  Ability to do simple operations
- *                                                  on attributes in the scom
- *                                                  data column
- *          SW146714        camvanng    06/08/2012  Use two bytes to store row
- *                                                  rpn sequence byte count
- *                          camvanng    06/15/2012  Ability to do bitwise OR and AND operations
- *                          camvanng    06/27/2012  Fix bug in targetId
- *                          camvanng    09/07/2012  Optimization - do PutScom vs PutScomUnderMask
- *                                                  if the combined bit mask enables all 64 bits
- *                          camvanng    12/15/2012  For PutScomUnderMask ops, grab only valid bits
- *                                                  of the data when the data length is greater
- *                                                  then number of bits specified.
- *          SW187788        mww         02/27/2013  Add minimal succinct trace
- *          SW195717        mww         04/22/2013  Add function to dump ffdc
- *                                                  and trace.
- *          SW251791        muqahmed    03/14/2014  Fixed compile warning
- */
-
-#include <fapiHwpExecInitFile.H>
-#include <fapiUtil.H>
-#include <fapiAttributeService.H>
-#include <string.h>
-#include <vector>
-#include <endian.h>
-#include <stdlib.h>
-
-#include <string.h>
-
-extern "C"
-{
-
-#ifndef SUPPRESS_UNUSED_VARIABLE
-#define SUPPRESS_UNUSED_VARIABLE(...)
-#endif
-
-//  --------------------------------------------------------------------
-//  enable minimal debug.  This will trace:
-//      Attr table, literal table, scoms, rows, and expressions being processed.
-//  Unfortunately this still adds a lot of trace, turn off before checking in.
-//  --------------------------------------------------------------------
-// #define HWPEXECINITFILE_DEBUG
-#ifdef  HWPEXECINITFILE_DEBUG
-#define IF_DBG(_fmt_, _args_...) FAPI_IMP(_fmt_, ##_args_)
-#else
-#define IF_DBG(_fmt_, _args_...) SUPPRESS_UNUSED_VARIABLE(NULL, ##_args_)
-#endif
-
-//  --------------------------------------------------------------------
-//  enable malloc debug.  This will trace:
-//      malloc/new/free/delete 's
-//  Turn off before checking in.
-//  --------------------------------------------------------------------
-// #define HWPEXECINITFILE_MALLOC_DEBUG
-#ifdef  HWPEXECINITFILE_MALLOC_DEBUG
-#define IF_MDBG(_fmt_, _args_...) FAPI_IMP(_fmt_, ##_args_)
-#else
-#define IF_MDBG(_fmt_, _args_...) SUPPRESS_UNUSED_VARIABLE(NULL, ##_args_)
-#endif
-
-//  --------------------------------------------------------------------
-//  enable attribute debug.  This will trace getAttr's
-//  Make sure this is off before checking in.
-//  --------------------------------------------------------------------
-// #define HWPEXECINITFILE_ATTR_DEBUG
-#ifdef  HWPEXECINITFILE_ATTR_DEBUG
-#define IF_ADBG(_fmt_, _args_...) FAPI_IMP(_fmt_, ##_args_)
-#else
-#define IF_ADBG(_fmt_, _args_...) SUPPRESS_UNUSED_VARIABLE(NULL, ##_args_)
-#endif
-
-//  --------------------------------------------------------------------
-//  enable ridiculous amounts of debug.  This will slow execution down by ~50%
-//  Make sure this is off before checking in
-//  --------------------------------------------------------------------
-// #define HWPEXECINITFILE_DEBUG2
-#ifdef HWPEXECINITFILE_DEBUG2
-#define IF_DBG2(_fmt_, _args_...) FAPI_INF(_fmt_, ##_args_)
-#else
-#define IF_DBG2(_fmt_, _args_...) SUPPRESS_UNUSED_VARIABLE(NULL, ##_args_)
-#endif
-
-//******************************************************************************
-// Enumerations
-//******************************************************************************
-
-//Flag indicating ANY operand
-enum IfAnyFlags
-{
-    IF_NOT_ANY = 0,
-    IF_ANY = 1,
-    IF_ONE_SIDED_ANY = 2
-};
-
-//Special variables & literals
-enum IfSpecialIds
-{
-    IF_VAL_ANY = 0x4000,
-    IF_EXPR    = 0x8000
-};
-
-/**
-* Offsets of certain elements in the initfile.
-*/
-enum IfHeader
-{
-    // Initfile Header
-    //-----------------
-    IF_VERSION_LOC            = 0,
-    IF_CVS_VERSION_LOC        = 4,
-    IF_ATTR_TABLE_OFFSET_LOC   = 12,
-    IF_LIT_TABLE_OFFSET_LOC   = 16,
-    IF_SCOM_SECTION_OFFSET_LOC= 20,
-    IF_SCOM_NUM_LOC           = 24,
-
-    IF_VERSION_SIZE            = 4,
-    IF_CVS_VERSION_SIZE        = 8,
-
-    IF_ATTR_TABLE_OFFSET_SIZE   = 4,
-    IF_LIT_TABLE_OFFSET_SIZE   = 4,
-    IF_SCOM_SECTION_OFFSET_SIZE= 4,
-    IF_SCOM_NUM_SIZE           = 4,
-
-    // Supported Syntax Version
-    IF_SYNTAX_VERSION          = 1,
-};
-
-//******************************************************************************
-// typedefs and structs
-//******************************************************************************
-
-//RPN stack
-typedef std::vector<uint64_t> rpnStack_t;
-
-//InitFile address, size and current offset
-typedef struct ifInfo
-{
-    const char * addr;
-    size_t size;
-    size_t offset;
-}ifInfo_t;
-
-//Attribute Symbol Table entry
-typedef struct attrTableEntry
-{
-    uint8_t  type;
-    uint32_t attrId;
-}attrTableEntry_t;
-
-//Scom Section Data entry
-typedef struct scomData
-{
-    uint16_t   len;
-    uint16_t   offset;
-    uint16_t   addrId;  //numeric literal
-    uint16_t   numCols;
-    uint16_t   numRows;
-    char **    data;    //scom data to write
-    bool       hasExpr; //has "expr" column
-    char *     colId;   //an attribute plus its target#
-    char **    rowData;
-}scomData_t;
-
-//Init File Data
-typedef struct ifData
-{
-    const std::vector<fapi::Target> * pTarget;
-    uint16_t                 numAttrs;
-    uint16_t                 numLits;
-    uint32_t                 numScoms;
-    attrTableEntry_t *       attrs;
-    uint64_t *               numericLits;
-    scomData_t **            scoms;
-    rpnStack_t *             rpnStack;
-}ifData_t;
-
-// The scom to write
-typedef struct scomToWrite
-{
-    uint16_t scomNum;  //the scom entry number
-    uint16_t row;      //the row within the scom entry
-}scomToWrite_t;
-
-//A list of the scoms to write
-typedef std::vector<scomToWrite_t> scomList_t;
-
-
-//  ------------------------------------------------------------------------
-//  @class  InitFileStats
-//  collect statistics to dump if we hit an error.
-//  ------------------------------------------------------------------------
-class   InitFileStats
-{
-
-public:
-    /**
-     * @brief Constructor
-     *
-     *  @param  pointer to init file name
-     *  @param  init file version
-     *  @param  pointer to initfile image
-     *  @param  initfile image size
-     *
-     */
-    InitFileStats(  const char  *i_initfile,
-                    uint32_t    i_version,
-                    const char  *i_addr,
-                    size_t      i_size )
-        :   iv_ok(true),
-            iv_pAttrSymbolTableAddr( NULL ),
-            iv_attrSymbolTableSize( 0 ),
-
-            iv_pLitSymbolTableAddr( NULL ),
-            iv_litSymbolTableSize( 0 ),
-
-            iv_pScomSectionAddr( NULL ),
-            iv_scomSectionSize( 0 ),
-
-            iv_column( 0 ),
-            iv_row( 0 ),
-            iv_pStack( NULL )
-    {
-        iv_pInitFileName    =   i_initfile;
-        iv_initFileVersion  =   i_version;
-
-        iv_pInitFileAddr    =   i_addr;
-        iv_initFileSize     =   i_size;
-    }
-
-    /**
-     * @brief Destructor
-     */
-    ~InitFileStats()
-    {
-    }
-
-    /**
-     *  @brief  save address and size of attr table for dumping if necessary
-     *
-     *  @param  i_addr  address of attr table
-     *  @param  i_size  number of attributes in table
-     *
-     *  @return none.
-    */
-    void attrSymbolTable(   attrTableEntry  *i_addr,
-                            const uint16_t  i_size )
-    {
-        iv_pAttrSymbolTableAddr =   i_addr;
-        iv_attrSymbolTableSize  =   i_size;
-    }
-
-    /**
-     *  @brief  save address and size of lit table for dumping if necessary
-     *
-     *  @param  i_addr  address of lit table
-     *  @param  i_size  number of literals in table
-     *
-     *  @return none.
-    */
-    void litSymbolTable(    uint64_t         *i_addr,
-                            const int16_t    i_size )
-    {
-        iv_pLitSymbolTableAddr  =   i_addr;
-        iv_litSymbolTableSize   =   i_size;
-    }
-
-    /**
-     *  @brief  save address and size of scom section for dumping if necessary
-     *
-     *  @param  i_addr  address of scom section
-     *  @param  i_size  number of scoms in table
-     *
-     *  @return none.
-    */
-    void scomSection(   scomData_t  **i_addr,
-                        uint32_t    i_size )
-    {
-        iv_pScomSectionAddr =   i_addr;
-        iv_scomSectionSize  =   i_size;
-    }
-
-    /**
-     *  @brief save current Targets for dumping if necessary
-     *
-     *  @param  i_pTargets    pointer to target list.
-     *
-     *  @return none.
-     */
-    void    saveTargets(const std::vector<fapi::Target> * i_pTargets   )
-    {
-
-        iv_pTargets   =   i_pTargets;
-    }
-
-
-    /**
-     *  @brief save current Stack for dumping if necessary
-     *
-    *  @param  i_pStack    pointer to rpnStack.
-     *
-     *  @return none.
-    */
-    void    saveStack(  rpnStack_t      *i_pStack   )
-    {
-
-        iv_pStack   =   i_pStack;
-    }
-
-    /**
-     *  @brief save current column for dumping if necessary
-     *
-    *  @param  i_col    column we're working on
-     *
-     *  @return none.
-    */
-    void    saveCol(    uint32_t        i_col   )
-    {
-
-        iv_column   =   i_col;
-    }
-
-    /**
-     *  @brief save current row for dumping if necessary
-     *
-    *  @param  i_row       row we're working on
-     *
-     *  @return none.
-    */
-    void    saveRow(    uint32_t        i_row  )
-    {
-        iv_row  =   i_row;
-    }
-
-    /**
-     *  @brief  save current scom data for dumping if necessary
-     *
-     *  @param  i_scomData  scomData we are working on
-     *
-     *  @return none.
-    */
-    void    saveScom(   const scomData_t  *i_scomData )
-    {
-
-        iv_scomData         =   *i_scomData;
-    }
-
-    /**
-     *  @brief  dump saved values, and records that an error has ocurred.
-     *
-     *  @return none
-     *          sets iv_ok to false.
-     */
-    void    dump( );
-
-    /**
-     *  @brief  return ffdc information
-     *          Fills in FFDC values for a fapi Returncode.
-     *
-     *  @param  ref to fapi rc to fill in
-     *
-     *  @return none
-     *          filled in fapi RC
-     */
-    void    generateError( fapi::ReturnCode &o_fapiRc );
-
-
-    /**
-     *  Return whether dump() was called somewhere so we can log the error.
-     *
-     *  @return true or false, depending on whether dump() was called.
-    */
-    bool    ok()
-    {
-        return  iv_ok;
-    }
-
-private:
-    /**
-     *  Disable copy constructor and assignment operator
-     */
-    InitFileStats(const InitFileStats& i_right);
-    InitFileStats& operator=(const InitFileStats& i_right);
-
-    bool            iv_ok;
-    const char      *iv_pInitFileName;
-    uint32_t        iv_initFileVersion;
-    const char      *iv_pInitFileAddr;
-    size_t          iv_initFileSize;
-
-    attrTableEntry  *iv_pAttrSymbolTableAddr;
-    uint16_t        iv_attrSymbolTableSize;
-
-    uint64_t        *iv_pLitSymbolTableAddr;
-    uint16_t        iv_litSymbolTableSize;
-
-    scomData_t      **iv_pScomSectionAddr;
-    uint32_t        iv_scomSectionSize;
-
-    const std::vector<fapi::Target> * iv_pTargets;
-
-    uint32_t        iv_column;
-    uint32_t        iv_row;
-    scomData_t      iv_scomData;
-    rpnStack_t      *iv_pStack;
-
-};  // end class    InitFileStats
-
-
-
-//******************************************************************************
-// Forward Declarations
-//******************************************************************************
-void ifSeek(ifInfo_t & io_ifInfo, size_t i_offset);
-
-void ifRead(ifInfo_t & io_ifInfo, void * o_data, uint32_t i_size,
-            bool i_swap = true);
-
-void loadAttrSymbolTable(ifInfo_t & io_ifInfo,ifData_t & io_ifData );
-
-void  unloadAttrSymbolTable(ifData_t & io_ifData);
-
-fapi::ReturnCode getAttr(const ifData_t & i_ifData,
-                 const uint16_t i_id,
-                 uint64_t & o_val,
-                 const uint32_t i_targetNum,
-                 const uint16_t i_arrayIndex[MAX_ATTRIBUTE_ARRAY_DIMENSION],
-                 InitFileStats  &i_stats );
-
-void loadLitSymbolTable(ifInfo_t & io_ifInfo, ifData_t & io_ifData );
-
-void unloadLitSymbolTable(ifData_t & io_ifData);
-
-fapi::ReturnCode getLit(const ifData_t & i_ifData,
-                        const uint16_t i_id,
-                        uint64_t & o_val,
-                        InitFileStats   &i_stats );
-
-void loadScomSection(ifInfo_t & io_ifInfo, ifData_t & io_ifData );
-
-void unloadScomSection(ifData_t & io_ifData);
-
-fapi::ReturnCode executeScoms(ifData_t & io_ifData,
-                              InitFileStats &i_stats );
-
-fapi::ReturnCode writeScom(ifData_t & i_ifData,
-                           const scomList_t & i_scomList,
-                           InitFileStats    &i_stats );
-
-fapi::ReturnCode getAttrArrayDimension(const ifData_t & i_ifData,
-                                       const uint16_t i_id,
-                                       uint8_t & o_attrDimension);
-
-void rpnPush(rpnStack_t * io_rpnStack,
-             uint64_t i_val );
-
-uint64_t rpnPop(rpnStack_t * io_rpnStack,
-                InitFileStats   &i_stats   );
-
-void rpnDumpStack(rpnStack_t * i_rpnStack);
-
-uint64_t rpnUnaryOp(IfRpnOp i_op,
-                    uint64_t i_val,
-                    uint32_t i_any,
-                    InitFileStats   &i_stats   );
-
-uint64_t rpnBinaryOp(IfRpnOp i_op,
-                     uint64_t i_val1,
-                     uint64_t i_val2,
-                     uint32_t i_any,
-                     InitFileStats  &i_stats   );
-
-fapi::ReturnCode rpnDoPush(ifData_t & io_ifData,
-                const uint16_t i_id,
-                uint32_t & io_any,
-                const uint32_t i_targetNum,
-                const uint16_t i_arrayIndex[MAX_ATTRIBUTE_ARRAY_DIMENSION],
-                           InitFileStats    &i_stats   );
-
-fapi::ReturnCode rpnDoOp(rpnStack_t * io_rpnStack,
-                         IfRpnOp i_op,
-                         uint32_t i_any,
-                         InitFileStats  &i_stats   );
-
-fapi::ReturnCode evalRpn(ifData_t & i_ifData,
-                         char * i_expr,
-                         uint32_t i_len,
-                         bool i_isColExpr,
-                         bool i_hasExpr,
-                         InitFileStats  &i_stats   );
-
-//
-void    InitFileStats::dump()
-{
-        iv_ok   =   false;
-
-        FAPI_IMP( "dump stats: initfile %s version %u, addr=%p, size = %zu",
-                  iv_pInitFileName,
-                  iv_initFileVersion,
-                  iv_pInitFileAddr,
-                  iv_initFileSize );
-        FAPI_IMP( "dump stats: attribute symbol table addr=%p, num attrs= %u",
-                  iv_pAttrSymbolTableAddr,
-                  iv_attrSymbolTableSize );
-        for ( int i=0; i<iv_attrSymbolTableSize; i++ )
-        {
-            FAPI_IMP( "    %.4d    0x%x    0x%08x",
-                i,
-                iv_pAttrSymbolTableAddr[i].type,
-                iv_pAttrSymbolTableAddr[i].attrId );
-        }
-        FAPI_IMP( "dump stats: literal symbol table addr=%p, num lits = %u",
-                  iv_pLitSymbolTableAddr,
-                  iv_litSymbolTableSize );
-        for ( int i=0; i<iv_litSymbolTableSize; i++ )
-        {
-            FAPI_IMP( "    0xX%03x    0x%08llx",
-                i+1,
-                iv_pLitSymbolTableAddr[i] );
-        }
-        FAPI_IMP( "dump stats: scomSection addr=%p, num scoms = %u",
-                  iv_pScomSectionAddr,
-                  iv_scomSectionSize );
-        FAPI_IMP( "dump stats: current column is 0x%x", iv_column );
-        FAPI_IMP( "dump stats: current row is 0x%x", iv_row );
-
-        FAPI_IMP( "dump stats: iv_scomData.len      is 0x%x",
-                  iv_scomData.len    );
-        FAPI_IMP( "dump stats: iv_scomData.offset   is 0x%x",
-                  iv_scomData.offset );
-        FAPI_IMP( "dump stats: iv_scomData.addrId   is 0x%x",
-                  iv_scomData.addrId );
-        FAPI_IMP( "dump stats: iv_scomData.numCols  is 0x%x",
-                  iv_scomData.numCols);
-        FAPI_IMP( "dump stats: iv_scomData.numRows  is 0x%x",
-                  iv_scomData.numRows);
-        FAPI_IMP( "dump stats: iv_scomData.data     addr is %p",
-                  iv_scomData.data   );
-        FAPI_IMP( "dump stats: iv_scomData.hasExpr  is 0x%x",
-                  iv_scomData.hasExpr);
-        FAPI_IMP( "dump stats: iv_scomData.colId    addr is %p",
-                  iv_scomData.colId  );
-        FAPI_IMP( "dump stats: iv_scomData.rowData  addr is %p",
-                  iv_scomData.rowData);
-
-        rpnDumpStack( iv_pStack );
-}
-
-
-//
-void    InitFileStats::generateError( fapi::ReturnCode &o_fapiRc )
-{
-    //  fill in ffdc info
-    uint16_t    &FFDC_SCOM_ADDRID   =   iv_scomData.addrId;
-    uint16_t    &FFDC_SCOM_OFFSET   =   iv_scomData.offset;
-    uint16_t    &FFDC_SCOM_LEN      =   iv_scomData.len;
-    uint32_t    &FFDC_COLUMN        =   iv_column;
-    uint32_t    &FFDC_ROW           =   iv_row;
-
-    FAPI_SET_HWP_ERROR( o_fapiRc, RC_INITFILE_EXECUTION_ERROR );
-
-}
-
-
-//******************************************************************************
-// fapiHwpExecInitFile function
-//******************************************************************************
-
-/**  @brief Execute the initfile
- *
- * This HWP can be called to execute a binary initfile.
- *
- * @param[in] i_target  Reference to std::vector<fapi::Target>
- * @param[in] i_file    The binary if filename: <initfile>.if
- *
- * @return ReturnCode. Zero on success.
- */
-fapi::ReturnCode fapiHwpExecInitFile(const std::vector<fapi::Target> & i_target,
-                                     const char * i_file)
-{
-    FAPI_INF(">> fapiHwpExecInitFile: Performing HWP for %s", i_file);
-
-    // Print the ecmd string of the targets
-    FAPI_IMP( "fapiHwpExecInitFile: SCOM target: %s",
-              i_target.front().toEcmdString());
-    for (size_t i = 1; i < i_target.size(); i++)
-    {
-        FAPI_IMP( "fapiHwpExecInitFile: Associated target: %s",
-                  i_target.at(i).toEcmdString());
-    }
-
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-    fapi::ReturnCode l_tmpRc = fapi::FAPI_RC_SUCCESS;
-    size_t l_ifSize = 0;
-    const char * l_ifAddr = NULL;
-
-
-    // Load the binary initfile
-    l_rc = fapiLoadInitFile(i_target.front(), i_file, l_ifAddr, l_ifSize);
-
-    if (l_rc.ok())
-    {
-        FAPI_IMP( "fapiHwpExecInitFile: initfile addr = %p, size = %zu",
-                  l_ifAddr,
-                  l_ifSize );
-
-        //Save the data
-        ifInfo_t l_ifInfo;
-        memset(&l_ifInfo, 0, sizeof(ifInfo_t));
-        l_ifInfo.addr = l_ifAddr;
-        l_ifInfo.size = l_ifSize;
-        l_ifInfo.offset = IF_VERSION_LOC;
-
-        //Check endianness
-        #ifdef __BYTE_ORDER
-            #if (__BYTE_ORDER == __BIG_ENDIAN)
-                FAPI_INF("fapiHwpExecInitFile: big endian mode");
-            #elif (__BYTE_ORDER == __LITTLE_ENDIAN)
-                FAPI_INF("fapiHwpExecInitFile: little endian mode");
-            #else
-            #error "Unknown byte order"
-            #endif
-        #else
-        #error "Byte order not defined"
-        #endif
-
-        //Check the version
-        uint32_t l_version;
-        ifRead(l_ifInfo, reinterpret_cast<void*>(&l_version), IF_VERSION_SIZE);
-
-        if (IF_SYNTAX_VERSION != l_version)
-        {
-            FAPI_ERR( "fapiHwpExecInitFile: %s Syntax version %u"
-                      "Expected version %u",
-                      i_file,
-                      l_version,
-                      IF_SYNTAX_VERSION );
-
-            uint32_t & FFDC_IF_VER = l_version; // GENERIC IDENTIFIER
-            FAPI_SET_HWP_ERROR(l_rc, RC_INITFILE_INCORRECT_VER);
-
-            // Unload the initfile, disregard this rc
-            l_tmpRc = fapiUnloadInitFile(i_file, l_ifAddr, l_ifSize);
-            if (!l_tmpRc.ok())
-            {
-                //Log error
-                fapiLogError(l_tmpRc);
-            }
-        }
-        else
-        {
-            char l_cvsVersion[IF_CVS_VERSION_SIZE];
-            ifRead( l_ifInfo, reinterpret_cast<void*>(&l_cvsVersion),
-                    IF_CVS_VERSION_SIZE,
-                    false );
-
-            FAPI_IMP("fapiHwpExecInitFile: %s Syntax version %u CVS version %s",
-                     i_file,
-                     l_version,
-                     l_cvsVersion );
-
-            //  create a stats object to collect initfile statistics -
-            //  this will be used if things break.
-            InitFileStats   l_stats( i_file, l_version, l_ifAddr, l_ifSize );
-
-            ifData_t l_ifData;
-            memset(&l_ifData, 0, sizeof(ifData_t));
-
-            //--------------------------------
-            // Load the Attribute Symbol Table
-            //--------------------------------
-            loadAttrSymbolTable(l_ifInfo, l_ifData  );
-            FAPI_IMP( "fapiHwpExecInitFile: Addr of attribute symbol table %p, "
-                    "num attrs %u",
-                    l_ifData.attrs,
-                    l_ifData.numAttrs );
-            l_stats.attrSymbolTable(
-                l_ifData.attrs,
-                l_ifData.numAttrs );
-
-            //--------------------------------
-            // Load the Literal Symbol Table
-            //--------------------------------
-            loadLitSymbolTable(l_ifInfo, l_ifData );
-            FAPI_IMP( "fapiHwpExecInitFile: Addr of literal symbol table %p, "
-                    "num lits %u",
-                    l_ifData.numericLits,
-                    l_ifData.numLits );
-            l_stats.litSymbolTable(
-                l_ifData.numericLits,
-                l_ifData.numLits );
-
-            //--------------------------------
-            // Load the SCOM Section
-            //--------------------------------
-            loadScomSection(l_ifInfo, l_ifData );
-            FAPI_IMP( "fapiHwpExecInitFile: Addr of scom section %p, "
-                    "num scoms %u",
-                    l_ifData.scoms,
-                    l_ifData.numScoms );
-            l_stats.scomSection(
-                l_ifData.scoms,
-                l_ifData.numScoms );
-
-            //--------------------------------
-            // Execute SCOMs
-            //--------------------------------
-            l_ifData.pTarget = &i_target;
-
-            l_rc = executeScoms(l_ifData, l_stats );
-
-
-            //--------------------------------
-            // Unload
-            //--------------------------------
-
-            // Unload the Attribute Symbol Table
-            unloadAttrSymbolTable(l_ifData);
-
-            // Unload the Literal Symbol Table
-            unloadLitSymbolTable(l_ifData);
-
-            // Unload the Scom Section
-            unloadScomSection(l_ifData);
-        }
-
-        // Unload the initfile
-        l_tmpRc = fapiUnloadInitFile(i_file, l_ifAddr, l_ifSize);
-
-        // return code from executeScoms takes precedence
-        if (l_rc.ok())
-        {
-            l_rc = l_tmpRc;
-        }
-        else if (!l_tmpRc.ok())
-        {
-            //Log error
-            fapiLogError(l_tmpRc);
-        }
-    }
-
-    FAPI_INF("<< fapiHwpExecInitFile: Performing HWP for %s", i_file);
-    return l_rc;
-}
-
-
-//******************************************************************************
-// Helper functions to read initfiles
-//******************************************************************************
-
-/**  @brief Seek to the specified offset in the binary initfile
- *
- * Seeks from the start of the file to the position passed in.
- *
- * @param[in,out] io_ifInfo   Reference to ifInfo_t which contains addr, size,
- *                            and current offset of the initfile
- * @param[in]     i_offset    Position to seek to.
- */
-void ifSeek(ifInfo_t & io_ifInfo, size_t i_offset)
-{
-    if (i_offset > io_ifInfo.size)
-    {
-        FAPI_ERR("fapiHwpExecInitFile: ifSeek: offset out of range 0x%zX",
-                 i_offset );
-        fapiAssert(false);
-    }
-
-    //Advance the offset
-    io_ifInfo.offset = i_offset;
-}
-
-/**  @brief Reads the initfile
- *
- * Reads the binary initfile at the current offset.
- *
- * @param[in,out] io_ifInfo   Reference to ifInfo_t which contains addr, size,
- *                            and current offset of the initfile
- * @param[out] o_data         Ptr to buffer where data read will be stored
- * @param[in] i_size          number of bytes to read
- * @param[in] i_swap          If true, will swap bytes to account for endianness if needed.
- */
-void ifRead(ifInfo_t & io_ifInfo, void * o_data, uint32_t i_size, bool i_swap)
-{
-    if ((true == i_swap) &&
-        !((1 == i_size) || (2 == i_size) || (4 == i_size) || (8 == i_size)))
-    {
-        FAPI_ERR("fapiHwpExecInitFile: ifRead: invalid number of bytes %d",
-                 i_size );
-        fapiAssert(false);
-    }
-
-    if ((io_ifInfo.offset + i_size) > io_ifInfo.size)
-    {
-        FAPI_ERR( "fapiHwpExecInitFile: ifRead: offset 0x%zX + size 0x%X "
-                  "out of range",
-                  io_ifInfo.offset,
-                  i_size );
-        fapiAssert(false);
-    }
-
-    //Copy the data
-    #if (__BYTE_ORDER == __LITTLE_ENDIAN)
-    if ((1 < i_size) && (true == i_swap))
-    {
-        //Account for endianness
-        const char * l_pSrc = io_ifInfo.addr + io_ifInfo.offset + i_size - 1;
-        char * l_pDst = static_cast<char *>(o_data);
-        do
-        {
-            *l_pDst = *l_pSrc;
-            l_pSrc--;
-            l_pDst++;
-        } while (l_pSrc >= io_ifInfo.addr + io_ifInfo.offset);
-    }
-    else
-    {
-        memcpy(o_data, io_ifInfo.addr + io_ifInfo.offset, i_size);
-    }
-    #else
-    memcpy(o_data, io_ifInfo.addr + io_ifInfo.offset, i_size);
-    #endif
-
-    //Advance the offset
-    io_ifInfo.offset += i_size;
-}
-
-//******************************************************************************
-// Helper functions for Attributes
-//******************************************************************************
-
-/**  @brief Loads the Attribute Symbol Table
- *
- * Loads the Attribute Symbol Table from the binary initfile.
- *
- * @param[in,out] io_ifInfo   Reference to ifInfo_t which contains addr, size,
- *                            and current offset of the initfile
- * @param[in,out] io_ifData   Reference to ifData_t which contains initfile data
- */
-void loadAttrSymbolTable(ifInfo_t & io_ifInfo,
-                         ifData_t & io_ifData  )
-{
-    IF_DBG( ">> fapiHwpExecInitFile: loadAttrSymbolTable" );
-
-    attrTableEntry_t * l_attrs = NULL;
-    uint16_t l_numAttrs = 0;
-    uint32_t l_attrTableOffset = 0;
-
-    //Seek to the Attribute Symbol Table offset
-    ifSeek(io_ifInfo, IF_ATTR_TABLE_OFFSET_LOC);
-
-    //Read the offset to the Attribute Symbol Table
-    ifRead(io_ifInfo, &l_attrTableOffset, IF_ATTR_TABLE_OFFSET_SIZE);
-
-    //Seek to the Attribute Symbol Table
-    ifSeek(io_ifInfo, l_attrTableOffset);
-
-    //Read the number of attributes
-    ifRead(io_ifInfo, &l_numAttrs, sizeof(l_numAttrs));
-    IF_DBG( "loadAttrSymbolTable: Offset of Attr Symbol Table 0x%X "
-             "num attrs %u",
-             l_attrTableOffset,
-             l_numAttrs );
-
-    //Now read the individual attribute entry
-    if (0 < l_numAttrs)
-    {
-        //Allocate memory to hold the attribute data
-        l_attrs = reinterpret_cast<attrTableEntry_t *>
-            (malloc(l_numAttrs * sizeof(attrTableEntry_t)));
-        memset(l_attrs, 0, l_numAttrs * sizeof(attrTableEntry_t));
-
-        for (uint16_t i = 0; i < l_numAttrs; i++)
-        {
-            //Read the attribute type
-            ifRead(io_ifInfo, &(l_attrs[i].type), sizeof(l_attrs[i].type));
-
-            //Read the attribute id
-            ifRead(io_ifInfo, &(l_attrs[i].attrId), sizeof(l_attrs[i].attrId));
-
-            IF_DBG( "loadAttrSymbolTable: attr[%u]: type 0x%x, id 0x%x",
-                     i, l_attrs[i].type, l_attrs[i].attrId);
-        }
-    }
-
-    io_ifData.attrs = l_attrs;
-    io_ifData.numAttrs = l_numAttrs;
-
-    IF_DBG( "<< fapiHwpExecInitFile: loadAttrSymbolTable at %p",
-            io_ifData.attrs );
-}
-
-/**  @brief Unloads the Attribue Symbol Table from memory
- *
- * Unloads the Attribute Symbol Table from memory
- *
- * @param[in, out] i_ifData   Reference to ifData_t which contains initfile data
- */
-void unloadAttrSymbolTable(ifData_t & io_ifData)
-{
-    IF_DBG( "fapiHwpExecInitFile: unloadAttrSymbolTable at %p",
-            io_ifData.attrs );
-    // Deallocate memory
-    free(io_ifData.attrs);
-    io_ifData.attrs = NULL;
-}
-
-/**  @brief Get an InitFile attribute value
- *
- * This function gets a copy of an attribute. In the case of an array attribute,
- * The value in the specified index is retrieved.
- *
- * If there are ever attributes with more than 4 dimensions then this function
- * will need to be updated.
- *
- * @param[in]  i_ifData        Reference to ifData_t which contains initfile data
- * @param[in]  i_id            AttributeID
- * @param[out] o_val           Reference to uint64_t where attribute value is set
- * @param[in]  i_arrayIndex    Array of attribute array index's (when needed)
- *
- * @return ReturnCode. Zero if success.
- */
-//******************************************************************************
-fapi::ReturnCode getAttr(const ifData_t & i_ifData,
-                 const uint16_t i_id,
-                 uint64_t & o_val,
-                 const uint32_t i_targetNum,
-                 const uint16_t i_arrayIndex[MAX_ATTRIBUTE_ARRAY_DIMENSION],
-                 InitFileStats  &i_stats )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: getAttr: id 0x%x target# %u",
-             i_id, i_targetNum);
-
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-
-    do {
-
-        //Mask out the type bits and zero-base
-        uint16_t l_id = (i_id & IF_ID_MASK) - 1;
-        IF_DBG2( "fapiHwpExecInitFile: getAttr: id 0x%x", l_id);
-
-        if (l_id < i_ifData.numAttrs)
-        {
-            const fapi::Target * l_pTarget = &(i_ifData.pTarget->front());
-
-            if ((i_id & IF_TYPE_MASK) == IF_SYS_ATTR_TYPE)
-            {
-                l_pTarget = NULL;
-            }
-            else if ((i_id & IF_TYPE_MASK) == IF_ASSOC_TGT_ATTR_TYPE)
-            {
-                if (0 == i_targetNum)
-                {
-                    //Expect nonzero targetNum
-                    FAPI_ERR( "fapiHwpExecInitFile: "
-                              "getAttr: Expect nonzero targetNum" );
-                    // dump trace and return error
-                    i_stats.dump( );
-                    i_stats.generateError( l_rc );
-                    break;
-                }
-                else if (i_ifData.pTarget->size() <= i_targetNum)
-                {
-                    FAPI_ERR( "fapiHwpExecInitFile: "
-                              "getAttr: target# %u is greater "
-                              "than number of targets %zu passed in",
-                              i_targetNum,
-                              i_ifData.pTarget->size() );
-
-                    const uint32_t & FFDC_IF_TGT_NUM = i_targetNum;
-                    size_t l_ffdc = i_ifData.pTarget->size();
-                    size_t & FFDC_IF_NUM_TGTS_PASSED_IN = l_ffdc;
-                    FAPI_SET_HWP_ERROR(l_rc, RC_INITFILE_TGT_NUM_OUT_OF_RANGE);
-                    i_stats.dump();
-                    break;
-
-                }
-
-                l_pTarget = &(i_ifData.pTarget->at(i_targetNum));
-            }
-
-            fapi::AttributeId l_attrId =
-                static_cast<fapi::AttributeId>(i_ifData.attrs[l_id].attrId);
-            IF_DBG2( "fapiHwpExecInitFile: getAttr: attrId 0x%x",
-            l_attrId );
-
-            l_rc = fapi::fapiGetInitFileAttr(l_attrId, l_pTarget, o_val,
-                                             i_arrayIndex[0], i_arrayIndex[1],
-                                             i_arrayIndex[2], i_arrayIndex[3]);
-
-            if (l_rc)
-            {
-                FAPI_ERR("fapiHwpExecInitFile: "
-                         "getAttr: GetInitFileAttr failed rc 0x%x",
-                         static_cast<uint32_t>(l_rc) );
-                i_stats.dump();
-                break;
-            }
-            if ( l_pTarget )
-            {
-                IF_ADBG( "fapiHwpExecInitFile: "
-                         "getAttr: target %s attrId 0x%x val 0x%.16llx",
-                         l_pTarget->toEcmdString(),
-                         l_attrId,
-                         o_val );
-            }
-            else
-            {
-                IF_ADBG( "fapiHwpExecInitFile: "
-                         "getAttr: target NULL attrId 0x%x val 0x%.16llx",
-                         l_attrId,
-                         o_val );
-            }
-        }
-        else
-        {
-            FAPI_ERR("fapiHwpExecInitFile: getAttr: id 0x%x out of range",
-                     i_id );
-
-            //  GENERIC IDENTIFIER
-            const uint16_t & FFDC_IF_ATTR_ID_OUT_OF_RANGE = i_id;
-            FAPI_SET_HWP_ERROR(l_rc, RC_INITFILE_ATTR_ID_OUT_OF_RANGE);
-            i_stats.dump();
-            break;
-        }
-    }
-    while (0);
-
-    IF_DBG2( "<< fapiHwpExecInitFile: getAttr" );
-    return l_rc;
-}
-
-
-//******************************************************************************
-// Helper functions for Literals
-//******************************************************************************
-
-/**  @brief Loads the Literal Symbol Table
- *
- * Loads the Literal Symbol Table from the binary initfile.
- *
- * @param[in,out] io_ifInfo   Reference to ifInfo_t which contains addr, size,
- *                            and current offset of the initfile
- * @param[in,out] io_ifData   Reference to ifData_t which contains initfile data
- */
-void loadLitSymbolTable(ifInfo_t & io_ifInfo,
-                        ifData_t & io_ifData )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: loadLitSymbolTable" );
-
-    uint64_t * l_numericLits = NULL;
-    uint16_t l_numLits = 0;
-    uint32_t l_litTableOffset = 0;
-
-    //Seek to the Literal Symbol Table offset
-    ifSeek(io_ifInfo, IF_LIT_TABLE_OFFSET_LOC);
-
-    //Read the offset to the Literal Symbol Table
-    ifRead(io_ifInfo, &l_litTableOffset, IF_LIT_TABLE_OFFSET_SIZE);
-
-    //Seek to the Literal Symbol Table
-    ifSeek(io_ifInfo, l_litTableOffset);
-
-    //Read the number of literals
-    ifRead(io_ifInfo, &l_numLits, sizeof(l_numLits));
-    IF_DBG2( "loadLitSymbolTable: Offset of Literal Symbol Table 0x%X "
-             "num literals %u",
-             l_litTableOffset,
-             l_numLits );
-
-    if (0 < l_numLits)
-    {
-        //Now read the individual literal entry
-
-        uint8_t l_litSize = 0;
-
-        l_numericLits =
-            reinterpret_cast<uint64_t *>(malloc(l_numLits * sizeof(uint64_t)));
-        memset(l_numericLits, 0, l_numLits * sizeof(uint64_t));
-
-        for (uint16_t i = 0; i < l_numLits; i++)
-        {
-            //Read the literal size in bytes
-            ifRead(io_ifInfo, &l_litSize, sizeof(l_litSize));
-
-            if ((l_litSize > 0) && (l_litSize <= sizeof(uint64_t)))
-            {
-                //Read the literal value
-                ifRead(io_ifInfo, &(l_numericLits[i]), l_litSize);
-
-                #if (__BYTE_ORDER == __BIG_ENDIAN)
-                //In big endian mode, if the literal is less then 8 bytes,
-                //need to right justify so it is a regular 64-byte number.
-                //In little endian mode, the bytes are swapped by ifRead()
-                //so the literal is already justified.
-                l_numericLits[i] >>= (64 - (l_litSize * 8));
-                #endif
-
-                IF_DBG( "loadLitSymbolTable:lit[%u]:size 0x%x,value 0x%016llx",
-                         i,
-                         l_litSize,
-                         l_numericLits[i] );
-            }
-            else
-            {
-                //Expect nonzero literal size of 1 to 8 bytes
-                FAPI_ERR( "loadLitSymbolTable: lit[%u]:  invalid size %u",
-                          i,
-                          l_litSize );
-                fapiAssert(false);
-            }
-        }
-    }
-
-    io_ifData.numericLits = l_numericLits;
-    io_ifData.numLits = l_numLits;
-
-    IF_DBG2( "<< fapiHwpExecInitFile: loadLitSymbolTable at %p",
-             io_ifData.numericLits );
-}
-
-/**  @brief Unloads the Literal Symbol Table from memory
- *
- * Unloads the Literal Symbol Table from memory
- *
- * @param[in, out] i_ifData   Reference to ifData_t which contains initfile data
- */
-void unloadLitSymbolTable(ifData_t & io_ifData)
-{
-    IF_DBG( "fapiHwpExecInitFile: unloadLitSymbolTable at %p",
-            io_ifData.numericLits );
-
-    // Deallocate memory
-    free(io_ifData.numericLits);
-    io_ifData.numericLits = NULL;
-}
-
-/**  @brief Get an InitFile numeric literal value
- *
- * This function gets a copy of a numeric literal.
- *
- * @param[in]  i_ifData      Reference to ifData_t which contains initfile data
- * @param[in]  i_id          Numeric Literal id
- * @param[out] o_val         Reference to uint64_t where literal value is set
- *
- * @return ReturnCode. Zero if success.
- */
-//******************************************************************************
-fapi::ReturnCode getLit(const ifData_t & i_ifData,
-                        const uint16_t i_id,
-                        uint64_t & o_val,
-                        InitFileStats   &i_stats    )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: getLit: id 0x%X",
-             i_id );
-
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-
-    //Mask out the type bits and zero-base
-    uint16_t l_id = (i_id & IF_ID_MASK) - 1;
-
-    if (l_id < i_ifData.numLits)
-    {
-        o_val = i_ifData.numericLits[l_id];
-        IF_DBG2( "fapiHwpExecInitFile: getLit: id 0x%x val 0x%.16llX",
-                 i_id,
-                 o_val );
-    }
-    else
-    {
-        FAPI_ERR("fapiHwpExecInitFile: getLit: id 0x%x out of range", i_id);
-
-        //  GENERIC IDENTIFIER
-        const uint16_t & FFDC_IF_LIT_ID_OUT_OF_RANGE = i_id;
-        FAPI_SET_HWP_ERROR(l_rc, RC_INITFILE_LIT_ID_OUT_OF_RANGE);
-        //  dump trace
-        i_stats.dump();
-
-    }
-
-    return l_rc;
-}
-
-
-//******************************************************************************
-// Helper functions for Scoms
-//******************************************************************************
-
-/**  @brief Loads the Scom Section
- *
- * Loads the Scom Section from the binary initfile.
- *
- * @param[in,out] io_ifInfo   Reference to ifInfo_t which contains addr, size,
- *                            and current offset of the initfile
- * @param[in,out] io_ifData   Reference to ifData_t which contains initfile data
- */
-void loadScomSection(ifInfo_t & io_ifInfo,
-                     ifData_t & io_ifData )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: loadScomSection" );
-
-    scomData_t ** l_scoms = NULL;
-    uint32_t l_numScoms = 0;
-    uint32_t l_scomSectionOffset = 0;
-
-    //Seek to the Scom Section offset
-    ifSeek(io_ifInfo, IF_SCOM_SECTION_OFFSET_LOC);
-
-    //Read the offset to the Scom Section
-    ifRead(io_ifInfo, &l_scomSectionOffset, IF_SCOM_SECTION_OFFSET_SIZE);
-
-    //Read the number of Scoms
-    ifRead(io_ifInfo, &l_numScoms, sizeof(l_numScoms));
-    IF_DBG( "loadScomSection: Offset of Scom Section 0x%X "
-             "num scoms %u",
-             l_scomSectionOffset,
-             l_numScoms );
-
-    //Seek to the Scom Section
-    ifSeek(io_ifInfo, l_scomSectionOffset);
-
-    if (0 < l_numScoms)
-    {
-        //------------------------------------
-        //Now read the individual SCOM entry
-        //------------------------------------
-
-        //Allocate memory to hold the data
-        l_scoms = new scomData_t*[l_numScoms];
-        IF_MDBG( ">>>> new l_scoms @ %p",
-                 l_scoms );
-
-        for (uint32_t i = 0; i < l_numScoms; i++)
-        {
-            // Allocate SCOM.
-            l_scoms[i] = new scomData_t;
-            memset(l_scoms[i], '\0', sizeof(scomData_t));
-            IF_MDBG( ">>>> new l_scoms[%d] @ %p",
-                     i,
-                     l_scoms[i] );
-
-            //Read the SCOM len
-            ifRead(io_ifInfo, &(l_scoms[i]->len), sizeof(l_scoms[i]->len));
-
-            //Read the SCOM offset
-            ifRead( io_ifInfo, &(l_scoms[i]->offset),
-                    sizeof(l_scoms[i]->offset) );
-
-            //Read the SCOM address id
-            ifRead( io_ifInfo, &(l_scoms[i]->addrId),
-                    sizeof(l_scoms[i]->addrId) );
-
-            //Expect numeric literal id, 1-based
-            if ( ! ((IF_NUM_TYPE == (l_scoms[i]->addrId & IF_TYPE_MASK)) &&
-                (IF_NUM_TYPE < l_scoms[i]->addrId)) )
-            {
-                FAPI_ERR( "loadScomSection: scom[%u]: "
-                          "addrId not a numeric literal",
-                          i );
-                fapiAssert(false);
-            }
-
-            //Read the number of columns
-            ifRead( io_ifInfo, &(l_scoms[i]->numCols),
-                    sizeof(l_scoms[i]->numCols));
-
-            //Read the number of rows
-            ifRead( io_ifInfo, &(l_scoms[i]->numRows),
-                    sizeof(l_scoms[i]->numRows));
-
-            IF_DBG( "loadScomSection: scom[%u]: len %u, offset %u",
-                    i,
-                    l_scoms[i]->len,
-                    l_scoms[i]->offset );
-            IF_DBG( "loadScomSection: addr id 0x%x, #cols %u, #rows %u",
-                    l_scoms[i]->addrId,
-                    l_scoms[i]->numCols,
-                    l_scoms[i]->numRows );
-
-            //Expect at least one row
-            if (0 >= l_scoms[i]->numRows)
-            {
-                FAPI_ERR( "loadScomSection: scom[%u]: num rows %u <= 0",
-                         i,
-                         l_scoms[i]->numRows );
-                fapiAssert(false);
-            }
-
-            //-----------------------------------
-            //Read the scom data
-            //-----------------------------------
-
-            uint8_t l_rowSize = 0;
-            char * l_rowPtr = NULL;
-
-            //Allocate memory to hold the scom data
-            l_scoms[i]->data =
-                reinterpret_cast<char**>
-                    (malloc(l_scoms[i]->numRows * sizeof(char**)));
-            memset(l_scoms[i]->data, 0, l_scoms[i]->numRows * sizeof(char**));
-            IF_MDBG( "malloc l_scoms[%d]->data @ %p",
-                     i,
-                     l_scoms[i]->data );
-
-            //Read the scom data for each row
-            for (uint16_t j = 0; j < l_scoms[i]->numRows; j++)
-            {
-                //Read the row size; i.e. # of bytes
-                ifRead(io_ifInfo, &l_rowSize, sizeof(l_rowSize));
-
-                //Expect non-zero row size
-                if (0 >= l_rowSize)
-                {
-                    FAPI_ERR("loadScomSection: scom[%u]: scom data row size %u",
-                             i,
-                             l_rowSize );
-                    fapiAssert(false);
-                }
-
-                //Allocate the space for the scom data and its size
-                l_scoms[i]->data[j] = reinterpret_cast<char *>
-                    (malloc(l_rowSize + 1));
-                memset(l_scoms[i]->data[j], 0, l_rowSize + 1);
-                l_rowPtr = l_scoms[i]->data[j];
-                IF_MDBG( "malloc l_scoms[%d]->data[%d] @ %p",
-                         i,
-                         j,
-                         l_scoms[i]->data[j] );
-
-                //Save the size of the scom data
-                *l_rowPtr++ = l_rowSize;
-
-                //Read in the scom data
-                //Don't swap the bytes, scom data will parsed by byte later in code
-                ifRead(io_ifInfo, l_rowPtr, l_rowSize, false);
-                #ifdef HWPEXECINITFILE_DEBUG
-                for (uint8_t k = 0; k < l_rowSize; k++)
-                {
-                    IF_DBG2( "loadScomSection: scom[%u]: data[%u] "
-                           "0x%02x",
-                           i,
-                           j,
-                           *l_rowPtr++ );
-                }
-                #endif
-            }
-
-            // Set to default
-            l_scoms[i]->hasExpr = false;
-
-            //-----------------------------------
-            //Load the column data
-            //-----------------------------------
-            if (0 < l_scoms[i]->numCols)
-            {
-                //Allocate memory to hold the column data plus its target id
-                l_scoms[i]->colId =
-                    reinterpret_cast<char *>
-                        (malloc(l_scoms[i]->numCols * 2 * sizeof(uint16_t)));
-                memset(l_scoms[i]->colId, 0,
-                    l_scoms[i]->numCols * 2 * sizeof(uint16_t));
-                IF_MDBG( "malloc l_scoms[%d]->colId @ %p",
-                         i,
-                         l_scoms[i]->colId );
-
-                //Read Column Id
-                uint16_t l_colId = 0;
-                char *l_pCol = l_scoms[i]->colId;
-                for (uint16_t j = 0; j < l_scoms[i]->numCols; j++)
-                {
-                    //Don't swap the bytes - colId is parsed by bytes later in code.
-                    ifRead(io_ifInfo, l_pCol, sizeof(uint16_t), false);
-                    l_colId = *l_pCol++ << 8;
-                    l_colId |= *l_pCol++;
-
-                    IF_DBG2( "loadScomSection: scom[%u]: colId[%u] "
-                             "0x%02x",
-                             i,
-                             j,
-                             l_colId );
-
-                    //Is this an associated target attribute
-                    if ((l_colId & IF_TYPE_MASK) == IF_ASSOC_TGT_ATTR_TYPE)
-                    {
-                        //Read the target Id
-                        //Don't swap the bytes - it is parsed by bytes later in code.
-                        ifRead(io_ifInfo, l_pCol, sizeof(uint16_t), false);
-                        #ifdef HWPEXECINITFILE_DEBUG2
-                            uint16_t l_colTgtId = 0;
-                            l_colTgtId = (*l_pCol << 8) | (*(l_pCol+1));
-                            IF_DBG2( "loadScomSection: colTgtId[%u] 0x%02x",
-                                     j,
-                                     l_colTgtId );
-                        #endif
-                    }
-                    l_pCol += 2; //advance past the target Id
-                }
-
-                //Is the last column an EXPR column
-                if (IF_EXPR == l_colId)
-                {
-                    IF_DBG2( "loadScomSection: scom[%u]: has expression",
-                             i );
-                    l_scoms[i]->hasExpr = true;
-                }
-            }
-
-            //-----------------------------------
-            //Load the row data for each columns
-            //-----------------------------------
-            if (0 == l_scoms[i]->numCols)
-            {
-                // Set the row data ptr to NULL & discard 1-byte row size
-                l_scoms[i]->rowData = NULL;
-                ifSeek(io_ifInfo, io_ifInfo.offset + 1);
-            }
-            else
-            {
-                //Allocate memory to hold the row data
-                l_scoms[i]->rowData =
-                    reinterpret_cast<char**>
-                        (malloc(l_scoms[i]->numRows * sizeof(char**)));
-                memset(l_scoms[i]->rowData, 0,
-                    l_scoms[i]->numRows * sizeof(char**));
-                IF_MDBG( "malloc l_scoms[%d]->rowData @ %p",
-                         i,
-                         l_scoms[i]->rowData );
-
-                // Determine the number of simple columns (not an expr columns)
-                uint16_t l_numSimpleCols = l_scoms[i]->numCols;
-                if (l_scoms[i]->hasExpr)
-                {
-                    l_numSimpleCols--;
-                }
-
-                //Read the row data for each row
-                uint16_t l_rowSize = 0;
-                l_rowPtr = NULL;
-                uint32_t c;
-
-                for (uint16_t j = 0; j < l_scoms[i]->numRows; j++)
-                {
-                    //Read the row size; i.e. # of bytes
-                    ifRead(io_ifInfo, &l_rowSize, sizeof(l_rowSize));
-
-                    //Expect non-zero row size
-                    if (0 >= l_rowSize)
-                    {
-                        FAPI_ERR( "loadScomSection: scom[%u]: row size %u",
-                                 i,
-                                 l_rowSize );
-                        fapiAssert(false);
-                    }
-
-                    //If have expr column, need another two bytes to store its length
-                    if (l_scoms[i]->hasExpr)
-                    {
-                        l_rowSize += 2;
-                    }
-
-                    //Allocate the space
-                    l_scoms[i]->rowData[j] = reinterpret_cast<char *>
-                        (malloc(l_rowSize));
-                    l_rowPtr = l_scoms[i]->rowData[j];
-                    IF_MDBG( "malloc l_scoms[%d]->rowData[%d] @ %p",
-                             i,
-                             j,
-                             l_scoms[i]->rowData );
-
-                    //Read in the simple column entries in the rows
-                    for (uint16_t k = 0; k < l_numSimpleCols; k++)
-                    {
-                        //Keep reading in data until we hit a non push, which
-                        //would be an operator
-                        while (1)
-                        {
-                            //Read the first byte of the Push, or an operator
-                            ifRead(io_ifInfo, l_rowPtr, sizeof(char));
-                            IF_DBG2( "loadScomSection: scom[%u]: rowData[%u] "
-                                     "0x%02x",
-                                     i,
-                                     j,
-                                     *l_rowPtr );
-
-                            c = *l_rowPtr++;
-                            l_rowSize--;
-
-                            //If it's not a push, then it must be an operator,
-                            //so we're done
-                            if (!(c & PUSH_MASK))
-                            {
-                                break;
-                            }
-
-                            //It was a push, so read in the 2nd byte of it
-                            ifRead(io_ifInfo, l_rowPtr, sizeof(char));
-                            IF_DBG2( "loadScomSection: scom[%u]: rowData[%u] "
-                                     "0x%02x",
-                                     i,
-                                     j,
-                                     *l_rowPtr );
-                            l_rowPtr++;
-                            l_rowSize--;
-                        }
-                    }
-
-                    //After the simple columns comes the expression column,
-                    //if present
-                    if (l_scoms[i]->hasExpr)
-                    {
-                        //Save the length of the expr
-                        l_rowSize -= 2;
-                        *l_rowPtr++ = (uint8_t)(l_rowSize >> 8);
-                        *l_rowPtr++ = (uint8_t)l_rowSize;
-                        IF_DBG2( "loadScomSection: scom[%u]: rowData[%u] "
-                                 "expr len 0x%02x%02x",
-                                 i,
-                                 j,
-                                 *(l_rowPtr-2),
-                                 *(l_rowPtr-1) );
-
-                        //Read in the rest of the expression, which goes to the
-                        //end of the row
-                        while (l_rowSize--)
-                        {
-                            ifRead(io_ifInfo, l_rowPtr, sizeof(char));
-                            IF_DBG2( "loadScomSection: scom[%u]: rowData[%u] "
-                                     "0x%02x",
-                                     i,
-                                     j,
-                                     *l_rowPtr );
-                            l_rowPtr++;
-                        }
-                    }
-                }
-            }
-        }
-    }
-
-    io_ifData.scoms = l_scoms;
-    io_ifData.numScoms = l_numScoms;
-
-    IF_DBG( "<< fapiHwpExecInitFile: loadScomSection" );
-}
-
-/**  @brief Unloads the Scom Section from memory
- *
- * @param[in, out] i_ifData   Reference to ifData_t which contains initfile data
- */
-void unloadScomSection(ifData_t & io_ifData)
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: unloadScomSection" );
-
-    //Deallocate memory
-    for (uint32_t i = 0; i < io_ifData.numScoms; i++)
-    {
-        if (NULL != io_ifData.scoms[i]->data)
-        {
-            for (uint16_t j = 0; j < io_ifData.scoms[i]->numRows; j++)
-            {
-                IF_MDBG( "free(io_ifData.scoms[%d]->data[%d] @ %p)",
-                         i,
-                         j,
-                         io_ifData.scoms[i]->data[j] );
-                free(io_ifData.scoms[i]->data[j]);
-                io_ifData.scoms[i]->data[j] = NULL;
-            }
-
-            IF_MDBG( "free(io_ifData.scoms[%d]->data @ %p)",
-                     i,
-                     io_ifData.scoms[i]->data );
-            free(io_ifData.scoms[i]->data);
-            io_ifData.scoms[i]->data = NULL;
-        }
-
-        IF_MDBG( "free(io_ifData.scoms[%d]->colId @ %p)",
-                 i,
-                 io_ifData.scoms[i]->colId );
-        free(io_ifData.scoms[i]->colId);
-        io_ifData.scoms[i]->colId = NULL;
-
-        if (NULL != io_ifData.scoms[i]->rowData)
-        {
-            for (uint16_t j = 0; j < io_ifData.scoms[i]->numRows; j++)
-            {
-                IF_MDBG( "free(io_ifData.scoms[%d]->rowData[%d] @ %p)",
-                         i,
-                         j,
-                         io_ifData.scoms[i]->rowData[j] );
-                free(io_ifData.scoms[i]->rowData[j]);
-                io_ifData.scoms[i]->rowData[j] = NULL;
-            }
-
-            IF_MDBG( "free(io_ifData.scoms[%d]->rowData @ %p)",
-                     i,
-                     io_ifData.scoms[i]->rowData );
-            free(io_ifData.scoms[i]->rowData);
-            io_ifData.scoms[i]->rowData = NULL;
-        }
-
-        IF_MDBG( "delete (io_ifData.scoms[%d] @ %p)",
-                 i,
-                 io_ifData.scoms[i] );
-        delete io_ifData.scoms[i];
-        io_ifData.scoms[i] = NULL;
-    }   // endfor i
-
-    IF_MDBG( "delete[] (io_ifData.scoms @ %p)",
-             io_ifData.scoms );
-    delete[] io_ifData.scoms;
-    io_ifData.scoms = NULL;
-
-    IF_DBG( "<< fapiHwpExecInitFile: unloadScomSection" );
-}
-
-/**  @brief Execute the Scom Section
- *
- * @param[in] i_ifData   Reference to ifData_t which contains initfile data
- *
- * @return ReturnCode. Zero if success.
- */
-fapi::ReturnCode executeScoms(ifData_t & i_ifData, InitFileStats &i_stats )
-{
-    FAPI_INF(">> fapiHwpExecInitFile: executeScoms");
-
-    fapi::ReturnCode l_rc;
-    uint16_t l_numSimpleCols = 0;
-    uint16_t l_len = 0;
-    char * l_rowExpr = NULL;
-    char * l_colExpr = NULL;
-    uint16_t l_row;
-    bool l_goToNextRow = false;
-    rpnStack_t l_rpnStack;
-    uint64_t result = 0;
-    scomToWrite_t l_scom;
-    scomList_t l_scomList;
-
-    //Create RPN stack
-    l_rpnStack.reserve(128);
-
-    i_ifData.rpnStack = &l_rpnStack;
-
-    i_stats.saveTargets( i_ifData.pTarget );
-    i_stats.saveStack(  &l_rpnStack );
-
-    for (uint32_t i = 0; i < i_ifData.numScoms; i++)
-    {
-        //  save values for debug
-        i_stats.saveScom( i_ifData.scoms[i] );
-
-        //Get the number of simple columns
-        l_numSimpleCols = i_ifData.scoms[i]->numCols;
-        if (i_ifData.scoms[i]->hasExpr)
-        {
-            l_numSimpleCols--;
-        }
-
-        IF_DBG2( "fapiHwpExecInitFile:executeScoms:scoms[%d]:#simple cols %u",
-                 i,
-                 l_numSimpleCols );
-
-        for (l_row = 0; l_row < i_ifData.scoms[i]->numRows; l_row++)
-        {
-            IF_DBG( ">> fapiHwpExecInitFile: executeScoms: scom %u row %u",
-                    i,
-                    l_row );
-            //  save values for debug
-            i_stats.saveRow(l_row);
-
-            //Nothing to check if there are no columns
-            //We found a row match
-            if ((0 == i_ifData.scoms[i]->numCols) ||
-                (NULL == i_ifData.scoms[i]->rowData))
-            {
-                IF_DBG2( "fapiHwpExecInitFile: executeScoms: no cols" );
-                break;
-            }
-
-            //Get a pointer to the row expressions
-            l_rowExpr = i_ifData.scoms[i]->rowData[l_row];
-
-            //Get a pointer to the column expressions
-            if (l_numSimpleCols > 0)
-            {
-                l_colExpr = i_ifData.scoms[i]->colId;
-            }
-
-            //Evaluate the simple columns (not the 'expr' column)
-            for (uint16_t col= 0; col < l_numSimpleCols; col++)
-            {
-                //  save values for debug
-                i_stats.saveCol( col );
-
-                //Evaluate the col id & target number
-                l_rc = evalRpn(i_ifData, l_colExpr, 4, true, false, i_stats );
-
-                if (l_rc)
-                {
-                    FAPI_ERR( "fapiHwpExecInitFile: "
-                              "Simple Column evalRpn failed" );
-                    break;
-                }
-
-                l_colExpr += 4; //advance past calculation
-
-                //This might be several pushes or just a push and an operator,
-                //so loop to read in the pushes
-                //An OP marks the end of a simple column RPN
-                while (static_cast<uint32_t>(*l_rowExpr) & PUSH_MASK)
-                {
-                    uint32_t l_byteCount = 2;
-                    if((static_cast<uint16_t>(*l_rowExpr << 8) & IF_TYPE_MASK)
-                       == IF_ASSOC_TGT_ATTR_TYPE)
-                    {
-                        //Read the target# also
-                        l_byteCount += 2;
-                    }
-
-                    // PUSH  (SYMBOL)
-                    l_rc = evalRpn(i_ifData,
-                                   l_rowExpr,
-                                   l_byteCount,
-                                   false,
-                                   false,
-                                   i_stats );
-                    l_rowExpr += l_byteCount; //advance past the calculation
-
-                    if (l_rc)
-                    {
-                        FAPI_ERR( "fapiHwpExecInitFile: "
-                                  "Simple Column evalRpn failed"
-                                 " on scom 0x%X",
-                                 i_ifData.scoms[i]->addrId);
-                        break;
-                    }
-                }
-
-                if (l_rc)
-                {
-                    break;
-                }
-
-                //If the op is TRUE_OP or FALSE_OP then pop the extra column
-                //symbol off the Rpn stack since it won't be consumed by the OP
-                if((*l_rowExpr == FALSE_OP) || (*l_rowExpr == TRUE_OP))
-                {
-                    //Unconditional OP; throw pushed COL symbol away
-                    rpnPop(i_ifData.rpnStack, i_stats );
-                    if ( !i_stats.ok() )
-                    {
-                        FAPI_ERR( "rpnPop failure" );
-                        i_stats.generateError( l_rc );
-                        break;
-                    }
-                    IF_DBG2( "fapiHwpExecInitFile: executeScoms: "
-                             "True or False op" );
-                }
-
-                l_rc = evalRpn(i_ifData, l_rowExpr, 1, false, false, i_stats );
-                l_rowExpr++;
-
-                if (l_rc)
-                {
-                    FAPI_ERR("fapiHwpExecInitFile: Simple Column evalRpn "
-                             "failed on scom 0x%X",
-                             i_ifData.scoms[i]->addrId );
-                    break;
-                }
-
-                result = rpnPop(i_ifData.rpnStack,i_stats );
-                if ( !i_stats.ok() )
-                {
-                    FAPI_ERR( "rpnPop failure" );
-                    i_stats.generateError( l_rc );
-                    break;
-                }
-                IF_DBG2( "fapiHwpExecInitFile: executeScoms: Simple Col: "
-                         "result 0x%llX",
-                         result );
-
-
-                //If zero, continue on to the next row.
-                if (0 == result)
-                {
-                  l_goToNextRow = true;
-                  break; //break out of simple column for loop
-                }
-
-            } //End looping on simple columns
-
-            if (l_rc)
-            {
-                break;
-            }
-
-            //Skip over to the next row
-            if (l_goToNextRow)
-            {
-                IF_DBG2( "fapiHwpExecInitFile: executeScoms: check next row" );
-
-                l_goToNextRow = false;
-                continue;
-            }
-
-            //Now evaluate the expression, if there is one
-            if (i_ifData.scoms[i]->hasExpr)
-            {
-                IF_DBG( "fapiHwpExecInitFile: Evaluate expr @ %p",
-                        l_rowExpr );
-
-                // fetch 2 bytes and combine to get a uint16_t len
-                l_len = *((uint8_t*)l_rowExpr);
-                l_rowExpr++;
-                l_len = (l_len << 8) + *((uint8_t*)l_rowExpr);
-                l_rowExpr++;
-
-                l_rc = evalRpn(i_ifData,
-                               l_rowExpr,
-                               l_len,
-                               false,
-                               true,
-                               i_stats );
-
-                if (l_rc)
-                {
-                    FAPI_ERR( "fapiHwpExecInitFile: "
-                              "Row expression evalRpn failed on scom 0x%X",
-                              i_ifData.scoms[i]->addrId );
-                    break;
-                }
-
-                result = rpnPop(i_ifData.rpnStack, i_stats );
-                if ( !i_stats.ok() )
-                {
-                    FAPI_ERR( "rpnPop failure" );
-                    i_stats.generateError( l_rc );
-                    break;
-                }
-                IF_DBG2( "fapiHwpExecInitFile: executeScoms: Expr: "
-                         "result 0x%llX",
-                         result );
-
-                //If nonzero, we're done so break out of row loop, otherwise
-                //let it go down to the next row
-                if (0 != result)
-                {
-                  IF_DBG2( "fapiHwpExecInitFile: executeScoms: Expr: "
-                           "found valid row" );
-                  break;
-                }
-            }
-            else
-            {
-                //No expression, and we're at the end, so we must
-                //have found a match in the columns
-                IF_DBG2( "fapiHwpExecInitFile: executeScoms: found valid row" );
-                break;
-            }
-
-        } // end looping for all rows
-
-        if (l_rc)
-        {
-            break;
-        }
-
-        IF_DBG2( "fapiHwpExecInitFile: executeScoms: scom %u row %u",
-                i,
-                l_row );
-
-        //Can tell we found a match by checking if we broke out of the
-        //for loop early
-        if (l_row < i_ifData.scoms[i]->numRows)
-        {
-            //Set the scom entry number and it's row
-            l_scom.scomNum = i;
-            l_scom.row = l_row;
-
-            //push the scom entry and its row into the list to write
-            l_scomList.push_back(l_scom);
-
-            IF_DBG2( "fapiHwpExecInitFile: executeScoms: "
-                     "found valid scom# %u row %u",
-                      l_scom.scomNum,
-                      l_scom.row );
-        }
-
-        IF_DBG2( "fapiHwpExecInitFile: executeScoms: l_scomList size %u",
-                 l_scomList.size() );
-
-        if (l_scomList.size())
-        {
-            //Look ahead to see if we can combine Scoms for optimization.
-            //Scoms can be combined if they're PutScomUnderMask ops to the
-            //same Scom registers.  Write the scoms in the list if we're at
-            //the last scom entry (no more entries to process or compare),
-            //if this or the next scom entry is a PutScom op (scom len = 0),
-            //or if the next entry is an op to a different Scom register
-            //(addrIds don't match), else go to the next scom.
-            if (((i+1) == i_ifData.numScoms)    ||                          //last scom entry
-                (0 == i_ifData.scoms[i]->len)   ||
-                (0 == i_ifData.scoms[i+1]->len) ||                          //not PutScomUnderMask
-                (i_ifData.scoms[i]->addrId != i_ifData.scoms[i+1]->addrId)) //different Scom regs
-            {
-                // Perform a scom operation on the chip
-                #ifdef HWPEXECINITFILE_DEBUG2
-                for (size_t j = 0; j < l_scomList.size(); j++)
-                {
-                    IF_DBG2( "fapiHwpExecInitFile: executeScoms: "
-                             "will write scom# %u row %u",
-                             l_scomList[j].scomNum,
-                             l_scomList[j].row );
-                }
-                #endif
-
-                l_rc = writeScom(i_ifData, l_scomList, i_stats );
-
-                // Clear the scom list
-                l_scomList.clear();
-
-                if (l_rc)
-                {
-                    break;
-                }
-            }
-        }
-    } // end looping for all scoms
-
-    // Clear the scom list; the only time the scom list is not empty
-    // is if we have pending scoms to write but we broke out of the above for
-    // loop early due to an error (l_rc != 0).
-    if (l_scomList.size())
-    {
-        FAPI_ERR( "fapiHwpExecInitFile: executeScoms: scom list size = %zu, "
-                  "expecting zero",
-                  l_scomList.size() );
-        l_scomList.clear();
-    }
-
-    //  Clear the stack, clear the external pointer to it
-    l_rpnStack.clear();
-    i_ifData.rpnStack = NULL;
-
-    // clear it in stats as well.
-    i_stats.saveStack( NULL );
-
-    FAPI_INF("<< fapiHwpExecInitFile: executeScoms");
-    return l_rc;
-}
-
-/**  @brief Write Scom
- *
- * @param[in] i_ifData   Reference to ifData_t which contains initfile data
- * @param[in] i_scomList The list of scoms to write
- *
- * @return ReturnCode. Zero if success.
- */
-fapi::ReturnCode writeScom(ifData_t & i_ifData,
-                           const scomList_t & i_scomList,
-                           InitFileStats  &i_stats )
-{
-    FAPI_DBG(">> fapiHwpExecInitFile: writeScom");
-
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-    uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
-
-    const fapi::Target l_target = i_ifData.pTarget->front();
-
-    uint64_t l_data = 0; // aggregate scom data to write
-    uint64_t l_mask = 0; // aggregate mask for PutScomUnderMask op
-
-    uint16_t l_scomNum = 0;
-    uint16_t l_row = 0;
-    uint64_t l_tmpData = 0;
-    uint16_t l_addrId = 0;
-    uint64_t l_addr = 0;
-    char *   l_rowExpr = NULL;  // pointer to scom data expression
-    uint8_t  l_rowSize = 0;     // size of scom data
-
-    do
-    {
-        for (size_t l_entry = 0; l_entry < i_scomList.size(); l_entry++)
-        {
-            l_scomNum = i_scomList.at(l_entry).scomNum;
-            l_row = i_scomList.at(l_entry).row;
-            l_tmpData = 0;
-
-            if (0 == l_entry)
-            {
-                //Get the the scom address
-                l_addrId = i_ifData.scoms[l_scomNum]->addrId;
-                l_rc = getLit(i_ifData, l_addrId, l_addr, i_stats );
-                if (l_rc)
-                {
-                    break;
-                }
-            }
-            else if (l_addrId != i_ifData.scoms[l_scomNum]->addrId)
-            {
-                //Address should be the same for all scoms in the list
-                FAPI_ERR( "fapiHwpExecInitFile: writeScom: have scomList "
-                          "of different Scom addresses!" );
-                // dump trace & ffdc
-                i_stats.dump( );
-                i_stats.generateError( l_rc );
-                break;
-            }
-
-            //Get the scom data
-            IF_DBG2( "fapiHwpExecInitFile: writeScom: Evaluate scom data" );
-
-            l_rowExpr = i_ifData.scoms[l_scomNum]->data[l_row];
-            l_rowSize = *((uint8_t*)l_rowExpr); //size of the scom data
-            l_rowExpr++;
-
-            l_rc = evalRpn(i_ifData,
-                           l_rowExpr,
-                           l_rowSize,
-                           false,
-                           false,
-                           i_stats);
-
-            if (l_rc)
-            {
-                FAPI_ERR("fapiHwpExecInitFile: writeScom: scom data expression "
-                         "evalRpn failed on scom 0x%X",
-                         i_ifData.scoms[l_scomNum]->addrId );
-                break;
-            }
-
-            l_tmpData = rpnPop(i_ifData.rpnStack, i_stats );
-            if ( !i_stats.ok() )
-            {
-                FAPI_ERR( "rpnPop failure" );
-                i_stats.generateError( l_rc );
-                break;
-            }
-            IF_DBG2( "fapiHwpExecInitFile: writeScom: Scom data 0x%llX",
-                     l_tmpData );
-
-            IF_DBG2( "fapiHwpExecInitFile: writeScom: addr 0x%.16llX, "
-                     "data 0x%.16llX",
-                     l_addr,
-                     l_tmpData );
-
-            //Check if this is a bit operation
-            if (i_ifData.scoms[l_scomNum]->len)
-            {
-                //Get offset and len
-                uint16_t l_offset = i_ifData.scoms[l_scomNum]->offset;
-                uint16_t l_len = i_ifData.scoms[l_scomNum]->len;
-                uint64_t l_tmpMask = 0; // mask for PutScomUnderMask ops
-
-                //Create mask
-                for (uint64_t i = l_offset; i < (l_offset + l_len); i++)
-                {
-                    l_tmpMask |= (0x8000000000000000ll >> i);
-                }
-                l_mask |= l_tmpMask;
-
-                //Shift data to the right offset and grab only the valid
-                //bits; data is right aligned
-                l_tmpData <<= (64 - (l_offset + l_len));
-                l_tmpData &= l_tmpMask;
-                l_data |= l_tmpData;
-
-                FAPI_DBG("fapiHwpExecInitFile: writeScom: data 0x%.16llX "
-                         "mask 0x%.16llX len %u offset %u",
-                         l_tmpData, l_tmpMask, l_len, l_offset);
-            }
-            else
-            {
-                if (1 < i_scomList.size())
-                {
-                    //There should only be one entry in the scom list if this not
-                    //a bit op
-                    FAPI_ERR("fapiHwpExecInitFile: writeScom: "
-                             "scomList size > 1 for PutScom op!" );
-                    // dump trace & ffdc
-                    i_stats.dump( );
-                    i_stats.generateError( l_rc );
-                    break;
-                }
-
-                l_data = l_tmpData;
-            }
-        }
-
-        if (l_rc)
-        {
-            break;
-        }
-
-        IF_DBG2( "fapiHwpExecInitFile: writeScom: "
-                 "data 0x%.16llX mask 0x%.16llX",
-                 l_data,
-                 l_mask );
-
-        //Create a 64 bit data buffer
-        ecmdDataBufferBase l_scomData(64);
-
-        #ifdef HWPEXECINITFILE_DEBUG2
-        l_rc = fapiGetScom(l_target, l_addr, l_scomData);
-        IF_DBG2( "fapiHwpExecInitFile: writeScom: Data read 0x%.16llX",
-                 l_scomData.getDoubleWord(0) );
-        #endif
-
-        l_ecmdRc = l_scomData.setDoubleWord(0, l_data);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-             FAPI_ERR("fapiHwpExecInitFile: writeScom: error from "
-                      "ecmdDataBuffer setDoubleWord() - rc 0x%.8X",
-                      l_ecmdRc );
-
-             l_rc.setEcmdError(l_ecmdRc);
-             break;
-        }
-
-        if (l_mask && (l_mask != 0xFFFFFFFFFFFFFFFFull))
-        {
-            //Perform a PutScomUnderMask operation on the target
-
-            //Create a 64 bit data buffer
-            ecmdDataBufferBase l_scomMask(64);
-            l_ecmdRc = l_scomMask.setDoubleWord(0, l_mask);
-            if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-            {
-                 FAPI_ERR("fapiHwpExecInitFile: writeScom: error from "
-                          "ecmdDataBuffer setDoubleWord() - rc 0x%.8X",
-                          l_ecmdRc);
-
-                 l_rc.setEcmdError(l_ecmdRc);
-                 break;
-            }
-
-            FAPI_DBG("fapiHwpExecInitFile: writeScom: PutScomUnderMask: "
-                     "0x%.16llX = 0x%.16llX mask 0x%.16llX",
-                     l_addr, l_scomData.getDoubleWord(0),
-                     l_scomMask.getDoubleWord(0));
-
-            l_rc = fapiPutScomUnderMask(l_target, l_addr, l_scomData,
-                                        l_scomMask);
-            if (l_rc)
-            {
-                FAPI_ERR("fapiHwpExecInitFile: "
-                         "Error from fapiPutScomUnderMask");
-                break;
-            }
-        }
-        else
-        {
-           //Perform a PutScom operation on the target
-
-            IF_DBG2( "fapiHwpExecInitFile: writeScom: PutScom: "
-                     "0x%.16llX = 0x%.16llX",
-                     l_addr,
-                     l_scomData.getDoubleWord(0) );
-
-            l_rc = fapiPutScom(l_target, l_addr, l_scomData);
-
-            if (l_rc)
-            {
-                FAPI_ERR( "fapiHwpExecInitFile: Error from fapiPutScom" );
-                break;
-            }
-        }
-
-        #ifdef HWPEXECINITFILE_DEBUG2
-            l_rc = fapiGetScom(l_target, l_addr, l_scomData);
-            IF_DBG2( "fapiHwpExecInitFile: writeScom: Data read 0x%.16llX",
-                     l_scomData.getDoubleWord(0) );
-        #endif
-
-    } while(0);
-
-    FAPI_DBG("<< fapiHwpExecInitFile: writeScom");
-    return l_rc;
-}
-
-
-/**  @brief Get the attribute array dimension.
- *
- * @param[in] i_ifData   Reference to ifData_t which contains initfile data
- * @param[in] i_id       attribute Id
- *
- * @return the attribute dimension
- */
-fapi::ReturnCode getAttrArrayDimension(const ifData_t & i_ifData,
-                                       const uint16_t i_id,
-                                       uint8_t & o_attrDimension)
-{
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-
-    o_attrDimension = 0;
-
-    //Mask out the type bits and zero-based
-    uint16_t l_id = (i_id & IF_ID_MASK) - 1;
-    if (l_id < i_ifData.numAttrs)
-    {
-        // Get the attribute dimension & shift it to the LS nibble
-        o_attrDimension =
-            (i_ifData.attrs[l_id].type & ATTR_DIMENSION_MASK) >> 4;
-
-        IF_DBG2( "fapiHwpExecInitFile: getAttrArrayDimension: Attr ID:0x%.4X "
-                 "has dimension %u of type 0x%.4X",
-                 i_id,
-                 o_attrDimension,
-                 i_ifData.attrs[l_id].type );
-    }
-    else
-    {
-        FAPI_ERR( "fapiHwpExecInitFile: getAttrArrayDimension: "
-                  "id 0x%x out of range",
-                  i_id );
-
-        //  GENERIC IDENTIFIER
-        const uint16_t & FFDC_IF_ATTR_ID_OUT_OF_RANGE = i_id;
-        FAPI_SET_HWP_ERROR(l_rc, RC_INITFILE_ATTR_ID_OUT_OF_RANGE);
-    }
-
-    return l_rc;
-}
-
-
-//******************************************************************************
-// RPN Calculator functions
-//******************************************************************************
-
-/** @brief Pushes a value onto the RPN stack.
- *
- * @param[in,out] io_rpnStack  Ptr to RPN stack
- * @param[in]     i_val        Value to push
- */
-void rpnPush(rpnStack_t * io_rpnStack,
-             uint64_t i_val )
-{
-    IF_DBG2( "fapiHwpExecInitFile: rpnPush 0x%llX",
-             i_val );
-
-    io_rpnStack->push_back(i_val);
-}
-
-/** @brief Pops the top value off of the RPN stack.
- *
- * @param[in,out] io_rpnStack  Ptr to RPN stack
- * @return uint64_t            Value from top of stack
- */
-uint64_t rpnPop(rpnStack_t * io_rpnStack, InitFileStats &i_stats )
-{
-    IF_DBG2( "fapiHwpExecInitFile: rpnPop" );
-    uint64_t l_val = 0;
-
-    if (0 == io_rpnStack->size())
-    {
-        FAPI_ERR( "fapiHwpExecInitFile: rpnPop: rpn stack is empty. " );
-
-        // dump trace here, register an error to be handled by caller.
-        i_stats.dump( );
-    }
-    else
-    {
-        l_val = io_rpnStack->back();
-        io_rpnStack->pop_back();
-
-        IF_DBG2( "fapiHwpExecInitFile: rpnPop 0x%llX",
-                 l_val );
-    }
-    return l_val;
-}
-
-/** @brief Dumps out the RPN stack
- *
- * @param[in] i_rpnStack  Ptr to RPN stack
- */
-void rpnDumpStack(rpnStack_t * i_rpnStack)
-{
-
-    if ( i_rpnStack != NULL )
-    {
-        FAPI_IMP( ">> fapiHwpExecInitFile: rpnDumpStack: %p, stack size = %zd",
-                  i_rpnStack,
-                  i_rpnStack->size() );
-
-        uint64_t l_val = 0;
-
-        for (ssize_t i = i_rpnStack->size() - 1; i >= 0; i--)
-        {
-            l_val = i_rpnStack->at(i);
-            FAPI_IMP( "Stack: Value = 0x%llX",
-                      l_val );
-        }
-
-        FAPI_IMP( "<< fapiHwpExecInitFile: rpnDumpStack" );
-    }
-
-}
-
-/** @brief Executes the unary operations - the ones with 1 operand.
- *
- * @param[in] i_op   Operation to perform
- * @param[in] i_val  Value to perform it on
- * @param[in] i_any  Flag indicating if this is an ANY op
- * @return uint64_t  The result
- */
-uint64_t rpnUnaryOp(    IfRpnOp i_op,
-                        uint64_t i_val,
-                        uint32_t i_any,
-                        InitFileStats   &i_stats
-                        )
-{
-    IF_DBG2( "fapiHwpExecInitFile: rpnUnaryOp" );
-    uint64_t result = 0;
-
-    if (i_op == NOT)
-    {
-        if (i_any & IF_ANY) //everything returns true
-        {
-            result = 1;
-        }
-        else
-        {
-            result = (i_val == 0) ? 1 : 0;
-        }
-    }
-    else
-    {
-        FAPI_ERR( "fapiHwpExecInitFile: rpnUnaryOp: Invalid Op %u",
-                  i_op );
-        // dump trace and register an error to be handled by caller.
-        i_stats.dump( );
-    }
-
-    return result;
-}
-
-/** @brief Executes the binary operations - the ones with 2 operands.
- *
- * @param[in] IfRpnOp i_op     Operation to perform
- * @param[in] uint64_t i_val1  The first operand
- * @param[in] uint64_t i_val2  The second operand
- * @return uint64_t            The result
- */
-uint64_t rpnBinaryOp(   IfRpnOp i_op,
-                        uint64_t i_val1,
-                        uint64_t i_val2,
-                        uint32_t i_any,
-                        InitFileStats   &i_stats
-                        )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: rpnBinaryOp 0x%X",
-             i_op );
-
-    uint64_t result = 0;
-
-    //If either of these are ANY, then just return nonzero/true
-    if (i_any & IF_ANY)
-    {
-        result = 1;
-        IF_DBG2( "fapiHwpExecInitFile: rpnBinaryOp: ANY" );
-    }
-    else
-    {
-        switch (i_op)
-        {
-            case (AND):
-                result = i_val1 && i_val2;
-                break;
-
-            case (OR):
-                result = i_val1 || i_val2;
-                break;
-
-            case (EQ):
-                result = i_val1 == i_val2;
-                break;
-
-            case (NE):
-                result = i_val1 != i_val2;
-                break;
-
-            case (GT):
-                result = i_val1 > i_val2;
-                break;
-
-            case (GE):
-                result = i_val1 >= i_val2;
-                break;
-
-            case (LT):
-                result = i_val1 < i_val2;
-                break;
-
-            case (LE):
-                result = i_val1 <= i_val2;
-                break;
-
-            case (PLUS):
-                result = i_val1 + i_val2;
-                break;
-
-            case (MINUS):
-                result = i_val1 - i_val2;
-                break;
-
-            case (MULT):
-                result = i_val1 * i_val2;
-                break;
-
-            case (DIVIDE):
-                if (0 == i_val2)
-                {
-                    FAPI_ERR( "fapiHwpExecInitFile: rpnBinaryOp: "
-                              "Division by zero, i_val1 = 0x%llx",
-                              i_val1 );
-                    //  dump stats and flag an error to be handled by caller
-                    i_stats.dump();
-                    result  =   0;
-                }
-                else
-                {
-                    result = i_val1 / i_val2;
-                }
-                break;
-
-            case (MOD):
-                if (0 == i_val2)
-                {
-                    FAPI_ERR( "fapiHwpExecInitFile: rpnBinaryOp: "
-                              "Mod by zero, i_val1 = 0x%llx",
-                              i_val1 );
-                    //  dump stats and register an error to be handled by caller
-                    i_stats.dump();
-                    result  =   0;
-                }
-                else
-                {
-                    result = i_val1 % i_val2;
-                }
-                break;
-
-            case (SHIFTLEFT):
-                result = i_val1 << i_val2;
-                break;
-
-            case (SHIFTRIGHT):
-                result = i_val1 >> i_val2;
-                break;
-
-            case (BITWISEAND):
-                result = i_val1 & i_val2;
-                break;
-
-            case (BITWISEOR):
-                result = i_val1 | i_val2;
-                break;
-
-            default:
-              FAPI_ERR("fapiHwpExecInitFile: rpnBinaryOp, invalid operator %d",
-                       i_op);
-              // dump trace and register an error to be handled by caller
-              i_stats.dump();
-              result    =   0;
-              break;
-        }
-    }
-
-    IF_DBG2( "<< fapiHwpExecInitFile: rpnBinaryOp: result 0x%llX",
-             result );
-    return result;
-}
-
-/** @brief Pushes an attribute or literal value onto the RPN stack.
- *
- * Pushes the attribute or literal value specified by i_id onto the RPN stack.
- * It uses the appropriate symbol table to resolve the value first.
- *
- * @param[in,out] io_ifData    Reference to ifData_t which contains initfile data
- * @param[in]     i_id         Id of element to push
- * @param[in,out] io_any       Set if ANY op
- * @param[in] i_arrayIndex  Array of attribute array index's
-                                (when attribute is array type)
- * @return fapi::ReturnCode    Zero on success
- */
-fapi::ReturnCode rpnDoPush(ifData_t & io_ifData, const uint16_t i_id,
-                   uint32_t & io_any, const uint32_t i_targetNum,
-                   const uint16_t i_arrayIndex[MAX_ATTRIBUTE_ARRAY_DIMENSION],
-                           InitFileStats    &i_stats
-                   )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: rpnDoPush: id 0x%X",
-             i_id );
-
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-    uint64_t l_val = 0;
-
-    do
-    {
-
-        if (i_id & IF_ATTR_TYPE) //It's an attribute
-        {
-            l_rc = getAttr(io_ifData,
-                           i_id,
-                           l_val,
-                           i_targetNum,
-                           i_arrayIndex,
-                           i_stats
-                           );
-            if (l_rc)
-            {
-              break;
-            }
-
-            IF_DBG2( "fapiHwpExecInitFile: rpnDoPush: getAttr: id = 0x%X, "
-                     "target# = %u, value = 0x%llX",
-                     i_id,
-                     i_targetNum,
-                     l_val );
-
-            rpnPush(io_ifData.rpnStack, l_val);
-        }
-        else //It's a literal
-        {
-            //If it's not 'ANY'
-            if (i_id != IF_VAL_ANY)
-            {
-                l_rc = getLit(io_ifData, i_id, l_val, i_stats );
-                if (l_rc)
-                {
-                  FAPI_ERR( "fapiHwpExecInitFile: rpnDoPush: "
-                            "getLit: id 0x%X failed",
-                            i_id);
-                  break;
-                }
-
-                IF_DBG2( "fapiHwpExecInitFile: rpnDoPush: Literal lookup: "
-                         "id = 0x%X, value = 0x%llX",
-                         i_id,
-                         l_val );
-
-                rpnPush(io_ifData.rpnStack, l_val);
-            }
-            else //It's 'ANY', which will always return true
-            {
-                io_any |= IF_ANY;
-
-                l_val = 1;
-                rpnPush(io_ifData.rpnStack, l_val);
-
-                //If this is set, then we will see a PUSH ANY on the stack
-                //without the 2nd operand for the binary operator EQ.  This
-                //happens when parsing the expression column
-                if (io_any & IF_ONE_SIDED_ANY)
-                {
-                   //To get the second operand, push a fake one on the stack
-                   uint64_t l_temp = 0;
-                   rpnPush(io_ifData.rpnStack, l_temp);
-                }
-
-                IF_DBG2( "fapiHwpExecInitFile: rpnDoPush: "
-                         "Literal ANY pushed on stack" );
-            }
-        }
-
-    } while(0);
-
-    IF_DBG2( "<< fapiHwpExecInitFile: rpnDoPush" );
-    return l_rc;
-}
-
-/** @brief Execute the operation
- *
- * Executes the operation passed in, and places the result onto
- *
- * @param[in,out] io_rpnStack  Ptr to RPN stack
- * @param[in,out] i_op         Operation to perform
- * @param[in]     i_any        Set if ANY op
- * @return fapi::ReturnCode    Zero on success
- */
-fapi::ReturnCode rpnDoOp(rpnStack_t * io_rpnStack,
-                         IfRpnOp i_op,
-                         uint32_t i_any,
-                         InitFileStats  &i_stats   )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: rpnDoOp 0x%X",
-             i_op );
-
-#ifdef HWPEXECINITFILE_DEBUG2
-    rpnDumpStack(io_rpnStack);
-#endif
-
-    fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-    uint64_t val1   = 0;
-    uint64_t val2   = 0;
-    uint64_t result = 0;
-
-    switch (i_op)
-    {
-        //Do all of the binary ops
-        case (AND):
-        case (OR):
-        case (GT):
-        case (GE):
-        case (LT):
-        case (LE):
-        case (EQ):
-        case (NE):
-        case (PLUS):
-        case (MINUS):
-        case (MULT):
-        case (DIVIDE):
-        case (MOD):
-        case (SHIFTLEFT):
-        case (SHIFTRIGHT):
-        case (BITWISEAND):
-        case (BITWISEOR):
-
-            //pop the first value
-            val2 = rpnPop(io_rpnStack, i_stats );
-            if ( !i_stats.ok() )
-            {
-                FAPI_ERR( "rpnPop failure" );
-                i_stats.generateError( l_rc );
-                break;
-            }
-
-            //pop the second value
-            val1 = rpnPop(io_rpnStack, i_stats );
-            if ( !i_stats.ok() )
-            {
-                FAPI_ERR( "rpnPop failure" );
-                i_stats.generateError( l_rc );
-                break;
-            }
-
-            //Calculate the result
-            result = rpnBinaryOp(i_op, val1, val2, i_any, i_stats );
-            if ( !i_stats.ok() )
-            {
-                FAPI_ERR( "rpnPop failure" );
-                i_stats.generateError( l_rc );
-                break;
-            }
-
-            //Push the result onto the stack
-            rpnPush(io_rpnStack, result );
-
-            break;
-
-        case (NOT):
-
-            //Pop the value
-            val1 = rpnPop(io_rpnStack, i_stats );
-            if ( !i_stats.ok() )
-            {
-                FAPI_ERR( "rpnPop failure" );
-                i_stats.generateError( l_rc );
-                break;
-            }
-
-            //Calculate the result
-            result = rpnUnaryOp(i_op, val1, i_any, i_stats );
-            if ( !i_stats.ok() )
-            {
-                FAPI_ERR( "rpnPop failure" );
-                i_stats.generateError( l_rc );
-                break;
-            }
-
-            //Push the result onto the stack
-            rpnPush(io_rpnStack, result );
-
-            break;
-
-        case (FALSE_OP):
-
-            result = 0;
-            rpnPush(io_rpnStack, result );
-            break;
-
-        case (TRUE_OP):
-
-           result = 1;
-           rpnPush(io_rpnStack, result );
-           break;
-
-        default:
-           FAPI_ERR( "fapiHwpExecInitFile: rpnDoOp: invalid op 0x%X",
-                     i_op );
-           // dump trace & ffdc
-           i_stats.dump();
-           i_stats.generateError( l_rc );
-           break;
-    }
-
-    IF_DBG2( "<< fapiHwpExecInitFile: rpnDoOp: result %llu",
-             result );
-    return l_rc;
-}
-
-/** @brief Evaluates the RPN expression
- *
- * Evaluates the expression passed in and places the result on the RPN stack.
- *
- * @param[in,out] io_ifData   Reference to ifData_t which contains initfile data
- * @param[in]     i_expr      Expression to evaluate
- * @param[in]     i_len       Length of expression
- * @param[in]     i_hasExpr   True if EXPR column
- * @param[in]     i_stats    ref to InitFileStatus object
- *
- * @return fapi::ReturnCode   Zero on success
- */
-fapi::ReturnCode evalRpn( ifData_t & io_ifData,
-                          char *i_expr,
-                          uint32_t i_len,
-                          const bool i_isColExpr,
-                          const bool i_hasExpr,
-                          InitFileStats    &i_stats )
-{
-    IF_DBG2( ">> fapiHwpExecInitFile: evalRpn" );
-
-    fapi::ReturnCode l_rc;
-    IfRpnOp l_op;
-    uint16_t l_id;
-    uint64_t l_targetNum = 0;
-    uint32_t l_any = IF_NOT_ANY;
-
-    IF_DBG2( "fapiHwpExecInitFile: evalRpn: len %u",
-             i_len );
-
-    //If we're in an expression column, then an 'ANY' will just be one sided,
-    //and won't have the 2nd operand needed for the upcoming EQ operator
-    if (i_hasExpr)
-    {
-        IF_DBG2( "fapiHwpExecInitFile: evalRpn: this is an expr" );
-        l_any = IF_ONE_SIDED_ANY;
-    }
-
-    while (i_len--)
-    {
-        l_op = static_cast<IfRpnOp>((*i_expr++) & OP_MASK);
-        IF_DBG2( "fapiHwpExecInitFile: evalRpn: op? 0x%.2X",
-                 l_op );
-
-        if (l_op & PUSH_MASK) //Push
-        {
-            l_id = static_cast<uint16_t>((l_op << 8) | ((*i_expr++) & OP_MASK));
-            --i_len;
-
-            IF_DBG2( "fapiHwpExecInitFile: evalRpn: id 0x%.2X",
-                     l_id );
-
-            //Check for attribute of array type
-            uint16_t l_arrayIndexs[MAX_ATTRIBUTE_ARRAY_DIMENSION] = {0};
-
-            if (l_id & IF_ATTR_TYPE)
-            {
-                // If it's a column Id or an associated target attribute
-                if (i_isColExpr ||
-                    (l_id & IF_TYPE_MASK) == IF_ASSOC_TGT_ATTR_TYPE)
-                {
-                    // Read the target# id
-                    uint16_t l_targetId = *i_expr++ << 8;
-                    l_targetId |= *i_expr++;
-                    IF_DBG2( "target Id 0x%x",
-                             l_targetId );
-
-                    if (l_targetId)
-                    {
-                        // Retrieve the actual value for the target
-                        //  number (using it's id)
-                        l_rc = getLit(io_ifData,
-                                      l_targetId,
-                                      l_targetNum,
-                                      i_stats);
-                        if (l_rc)
-                        {
-                            break;
-                        }
-                    }
-                    i_len -= 2;
-                }
-
-                // Get the attribute dimension
-                uint8_t l_attrDimension = 0;
-                l_rc = getAttrArrayDimension(io_ifData, l_id, l_attrDimension);
-                if (l_rc)
-                {
-                    break;
-                }
-
-                // Read out all dimensions for the attribute
-                for(uint8_t j=0; j<l_attrDimension; j++)
-                {
-                    // Read out array index id
-                    uint16_t l_arrayIdxId = 0;
-                    l_arrayIdxId = *i_expr++ << 8;
-                    l_arrayIdxId |= *i_expr++;
-
-                    uint64_t l_tmpIdx = 0;
-
-                    // Retrieve the actual value for the array index (using it's id)
-                    l_rc = getLit(io_ifData,l_arrayIdxId,l_tmpIdx, i_stats );
-                    if (l_rc)
-                    {
-                        break;
-                    }
-                    l_arrayIndexs[j] = l_tmpIdx;
-                    i_len -= 2;
-                }
-            }
-
-            // Handle error from above for loop
-            if(l_rc)
-            {
-                break;
-            }
-
-            l_rc = rpnDoPush( io_ifData,
-                              l_id,
-                              l_any,
-                              l_targetNum,
-                              l_arrayIndexs,
-                              i_stats );
-        }
-        else
-        {
-            l_rc = rpnDoOp(io_ifData.rpnStack,
-                           l_op,
-                           l_any,
-                           i_stats );
-        }
-
-        if (l_rc)
-        {
-            break;
-        }
-    }
-
-    IF_DBG2( "<< fapiHwpExecInitFile: evalRpn" );
-    return l_rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/fapiTestHwp.C b/src/usr/hwpf/hwp/fapiTestHwp.C
deleted file mode 100644
index 86abbcef5..000000000
--- a/src/usr/hwpf/hwp/fapiTestHwp.C
+++ /dev/null
@@ -1,299 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/fapiTestHwp.C $                              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file fapiTestHwp.C
- *
- *  @brief Implements a simple test Hardware Procedure
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     04/21/2011  Created.
- *                          mjjones     06/02/2011  Use ecmdDataBufferBase
- *                          mjjones     06/28/2011  Removed attribute tests
- *                          andrewg     07/07/2011  Added test for hw team to fill in
- *                          mjjones     08/10/2011  Removed clock HWP
- *                          mjjones     09/01/2011  Call toString in InitialTest
- *                          mjjones     09/14/2011  Update to scom function name
- *                          camvanng    09/28/2011  Added test for initfile
- *                          camvanng    11/16/2011  Change function name
- *                                                  fapiHwpExecInitFile()
- *                          mjjones     01/13/2012  Use new ReturnCode interfaces
- *                          mjjones     02/21/2012  Use new Target toEcmdString
- *                          camvanng    05/07/2012  Suppport for associated
- *                                                  target attributes
- *
- *  HWP_IGNORE_VERSION_CHECK
- */
-
-#include <fapiTestHwp.H>
-#include <fapiHwAccess.H>
-#include <fapiHwpExecInitFile.H>
-extern "C"
-{
-
-//******************************************************************************
-// hwpInitialTest function - Override with whatever you want here
-//******************************************************************************
-fapi::ReturnCode hwpInitialTest(const std::vector<fapi::Target> & i_target)
-{
-    FAPI_INF("Performing HWP: hwpInitialTest");
-
-    // Print the ecmd string of the target(s)
-    for (size_t i = 0; i < i_target.size(); i++)
-    {
-        FAPI_INF("hwpInitialTest: target[%u]: %s", i, i_target.at(i).toEcmdString());
-    }
-
-    fapi::ReturnCode l_rc;
-    uint32_t l_ecmdRc = ECMD_DBUF_SUCCESS;
-
-    do
-    {
-        // Use PORE_GPE0_SCRATCH2_0x0006000C Scom register for testing
-        const uint64_t l_addr = 0x0006000C;
-        ecmdDataBufferBase l_ScomData(64);
-        uint64_t l_originalScomData = 0;
-
-        // --------------------------------------------------------
-        // 1. fapiGetScom test
-        // --------------------------------------------------------
-        l_rc = fapiGetScom(i_target.front(), l_addr, l_ScomData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiGetScom");
-            break;
-        }
-        else
-        {
-            // Save the original data so we can restore it later
-            l_originalScomData = l_ScomData.getDoubleWord(0);
-            FAPI_INF("hwpInitialTest: GetScom data 0x%.16llX", l_originalScomData);
-        }
-
-        // --------------------------------------------------------
-        // 2. fapiPutScom test
-        // --------------------------------------------------------
-        uint64_t l_scomWriteValue = 0x9000000000000000ULL;
-
-        l_ecmdRc = l_ScomData.setDoubleWord(0, l_scomWriteValue);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: fapiPutScom test, error from ecmdDataBuffer setDoubleWord() - rc 0x%.8X", l_ecmdRc);
-            l_rc.setEcmdError(l_ecmdRc);
-            break;
-        }
-
-        l_rc = fapiPutScom(i_target.front(), l_addr, l_ScomData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiPutScom");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: PutScom data 0x%.16llX", l_scomWriteValue);
-        }
-
-        // --------------------------------------------------------
-        // 3. fapiPutScomUnderMask test
-        // --------------------------------------------------------
-        l_scomWriteValue = 0xA000000000000000ULL;
-        uint64_t l_mask  = 0x3000000000000000ULL;
-        ecmdDataBufferBase l_maskData(64);
-
-        l_ecmdRc = l_ScomData.setDoubleWord(0, l_scomWriteValue);
-        l_ecmdRc |= l_maskData.setDoubleWord(0, l_mask);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: fapiPutScomUnderMask test, error from ecmdDataBuffer setDoubleWord() - rc 0x%.8X", l_ecmdRc);
-            l_rc.setEcmdError(l_ecmdRc);;
-            break;
-        }
-
-
-        l_rc = fapiPutScomUnderMask(i_target.front(), l_addr, l_ScomData, l_maskData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiPutScomUnderMask");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: fapiPutScomUnderMask data 0x%.16llX, mask 0x%.16llX",
-                     l_scomWriteValue, l_mask);
-        }
-
-        // --------------------------------------------------------
-        // 4. fapiPutScom to restore original value
-        // --------------------------------------------------------
-        l_ecmdRc = l_ScomData.setDoubleWord(0, l_originalScomData);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: fapiPutScom to restore, error from ecmdDataBuffer setDoubleWord() - rc 0x%.8X", l_ecmdRc);
-            l_rc.setEcmdError(l_ecmdRc);
-            break;
-        }
-
-        l_rc = fapiPutScom(i_target.front(), l_addr, l_ScomData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiPutScom");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: PutScom data 0x%.16llX", l_originalScomData);
-        }
-
-#if 0
-// @todo
-// Per Dean, there's no access to the CFAM engines on the master processor, therefore,
-// we *should not* allow access to them on any processor in any position
-// from a FAPI standpoint.
-// This means that get/put/modifyCfamRegister can't not be called on any of the processors.
-// These functions, therefore, can only be called on the Centaur, which is not available
-// at this time.
-// When Centaur is supported:
-//  - Don't use i_target.front() (a processor) as a target. Set the target as one of the Centaurs.
-//  - Enable this block of code and test the cfam access functions on the Centaur.
-
-        // --------------------------------------------------------
-        // 5. fapiGetCfamRegister test
-        // --------------------------------------------------------
-        ecmdDataBufferBase l_cfamData(32); // 32-bit cfam data holder
-        uint32_t l_originalCfamData = 0;
-        const uint32_t l_cfamAddr = 0x100A; // ChipID register
-        l_rc = fapiGetCfamRegister(i_target.front(), l_cfamAddr, l_cfamData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiGetCfamRegister");
-            break;
-        }
-        else
-        {
-            l_originalCfamData = l_cfamData.getWord(0);
-            FAPI_INF("hwpInitialTest: fapiGetCfamRegister data 0x%.8X",
-                    l_originalCfamData);
-        }
-
-        // --------------------------------------------------------
-        // 6. fapiPutCfamRegister test
-        // --------------------------------------------------------
-        uint32_t l_cfamWriteValue = 0x90000000;
-        l_ecmdRc = l_cfamData.setWord(0, l_cfamWriteValue);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: fapiPutCfamRegister test, error from ecmdDataBuffer setWord() - rc 0x%.8X", l_ecmdRc);
-            l_rc.setEcmdError(l_ecmdRc);;
-            break;
-        }
-
-
-        l_rc = fapiPutCfamRegister(i_target.front(), l_cfamAddr, l_cfamData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiPutCfamRegister");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: fapiPutCfamRegister data 0x%.8X",
-                    l_cfamData.getWord(0));
-        }
-
-        // --------------------------------------------------------
-        // 7. fapiModifyCfamRegister test
-        // --------------------------------------------------------
-        l_cfamWriteValue = 0xA0000000;
-        l_ecmdRc = l_cfamData.setWord(0, l_cfamWriteValue);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: fapiModifyCfamRegister test, error from ecmdDataBuffer setWord() - rc 0x%.8X", l_ecmdRc);
-            l_rc.setEcmdError(l_ecmdRc);;
-            break;
-        }
-
-        l_rc = fapiModifyCfamRegister(i_target.front(), l_cfamAddr,
-                l_cfamData, fapi::CHIP_OP_MODIFY_MODE_AND);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiPutCfamRegister");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: fapiPutCfamRegister data 0x%.8X",
-                    l_cfamData.getWord(0));
-        }
-
-        // --------------------------------------------------------
-        // 8. fapiPutCfamRegister to restore original CFAM value
-        // --------------------------------------------------------
-        l_ecmdRc = l_cfamData.setWord(0, l_originalCfamData);
-        if (l_ecmdRc != ECMD_DBUF_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: fapiPutCfamRegister to restore, error from ecmdDataBuffer setWord() - rc 0x%.8X", l_ecmdRc);
-            l_rc.setEcmdError(l_ecmdRc);;
-            break;
-        }
-
-        l_rc = fapiPutCfamRegister(i_target.front(), l_cfamAddr, l_cfamData);
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiPutCfamRegister to restore");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: fapiPutCfamRegister data 0x%.8X",
-                    l_cfamData.getWord(0));
-        }
-
-#endif
-
-        // --------------------------------------------------------
-        // 9. fapiHwpExecInitFile test
-        // --------------------------------------------------------
-
-        //Call Hwp to execute the sample initfile
-        FAPI_EXEC_HWP(l_rc, fapiHwpExecInitFile, i_target, "sample.if");
-        if (l_rc != fapi::FAPI_RC_SUCCESS)
-        {
-            FAPI_ERR("hwpInitialTest: Error from fapiHwpExecInitFile");
-            break;
-        }
-        else
-        {
-            FAPI_INF("hwpInitialTest: fapiHwpExecInitFile passed");
-        }
-
-    } while (0);
-
-    return l_rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/fapiTestHwpConfig.C b/src/usr/hwpf/hwp/fapiTestHwpConfig.C
deleted file mode 100644
index 82263748d..000000000
--- a/src/usr/hwpf/hwp/fapiTestHwpConfig.C
+++ /dev/null
@@ -1,151 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/fapiTestHwpConfig.C $                        */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file fapiTestHwpConfig.C
- *
- *  @brief Implements a Hardware Procedure that exercises the FAPI System Config
- *         Query functions.
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     09/12/2011  Created.
- *                          mjjones     10/06/2011  Updated traces.
- *                          camvang     10/26/2011  Updated traces.
- *                          mjjones     01/13/2012  Use new ReturnCode interfaces
- *                          mjjones     02/21/2012  Use new Target toEcmdString
- *
- *  HWP_IGNORE_VERSION_CHECK
- */
-
-#include <fapiTestHwpConfig.H>
-
-extern "C"
-{
-
-//******************************************************************************
-// hwpTestConfig
-//******************************************************************************
-fapi::ReturnCode hwpTestConfig(const fapi::Target & i_chip)
-{
-    FAPI_INF("hwpTestConfig: Start HWP");
-
-    // Print the ecmd string of the chip
-    FAPI_INF("hwpTestConfig: Chip: %s", i_chip.toEcmdString());
-
-    fapi::ReturnCode l_rc;
-    std::vector<fapi::Target> l_targets;
-
-    do {
-
-       // Call fapiGetChildChiplets to get the child MCS chiplets
-       l_rc = fapiGetChildChiplets(i_chip, fapi::TARGET_TYPE_MCS_CHIPLET,
-                                l_targets);
-
-       if (l_rc)
-       {
-           FAPI_ERR("hwpTestConfig: Error from fapiGetChildChiplets");
-           break;
-       }
-
-       FAPI_INF("hwpTestConfig: %d MCS chiplets", l_targets.size());
-
-       if (l_targets.size() == 0)
-       {
-           FAPI_ERR("hwpTestConfig: No MCS chiplets");
-           FAPI_SET_HWP_ERROR(l_rc, RC_TEST_CONFIG_NO_MCS_CHIPLETS);
-           break;
-       }
-
-       // Save the first MCS target
-       fapi::Target l_mcs = l_targets[0];
-
-       // Call fapiGetAssociatedDimms to get the dimms for this MCS
-       l_rc = fapiGetAssociatedDimms(l_mcs, l_targets);
-
-       if (l_rc)
-       {
-           FAPI_ERR("hwpTestConfig: Error from fapiGetAssociatedDimms");
-           break;
-       }
-
-       FAPI_INF("hwpTestConfig: %d dimms", l_targets.size());
-
-       // Call fapiGetParentChip to get the parent of the MCS
-       fapi::Target l_chip;
-
-       l_rc = fapiGetParentChip(l_mcs, l_chip);
-
-       if (l_rc)
-       {
-           FAPI_ERR("hwpTestConfig: Error from fapiGetParentChip");
-           break;
-       }
-
-       // Check that the parent chip is is same as the input chip
-       if (i_chip != l_chip)
-       {
-           FAPI_ERR("hwpTestConfig: Chip mismatch");
-           FAPI_SET_HWP_ERROR(l_rc, RC_TEST_CONFIG_PARENT_CHIP_MISMATCH);
-           break;
-       }
-
-       // Call  fapiGetOtherSideOfMemChannel to get mem buffer
-       fapi::Target l_mb;
-       fapi::Target l_mcs2;
-
-       FAPI_INF("hwpTestConfig: mcs: %s", l_mcs.toEcmdString());
-            
-       l_rc = fapiGetOtherSideOfMemChannel(l_mcs, l_mb);
-       if (l_rc)
-       {
-           FAPI_ERR("hwpTestConfig: Error from fapiGetOtherSideOfMemChannel");
-           break;
-       }
-       FAPI_INF("hwpTestConfig: mem buf: %s", l_mb.toEcmdString());
-
-       // Call  fapiGetOtherSideOfMemChannel to get back to the same mcs
-       l_rc = fapiGetOtherSideOfMemChannel(l_mb, l_mcs2);
-       if (l_rc)
-       {
-           FAPI_ERR("hwpTestConfig: Error from fapiGetOtherSideOfMemChannel");
-           break;
-       }
-       FAPI_INF("hwpTestConfig: mcs: %s", l_mcs2.toEcmdString());
-
-       if (l_mcs != l_mcs2) 
-       {
-           FAPI_ERR("hwpTestConfig: fapiGetOtherSideOfMemChannel wrong mcs");
-           FAPI_SET_HWP_ERROR(l_rc, RC_TEST_WRONG_MCS_RETURNED);
-           break;
-       }
-
-    } while (0);
-
-    FAPI_INF("hwpTestConfig: End HWP");
-    return l_rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/fapiTestHwpDq.C b/src/usr/hwpf/hwp/fapiTestHwpDq.C
deleted file mode 100644
index ad90c986e..000000000
--- a/src/usr/hwpf/hwp/fapiTestHwpDq.C
+++ /dev/null
@@ -1,201 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/fapiTestHwpDq.C $                            */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: fapiTestHwpDq.C,v 1.3 2013/08/13 20:37:24 mjjones Exp $
-/**
- *  @file fapiTestHwpDq.C
- *
- *  @brief Implements a Test Hardware Procedure that exercises the bad DQ data
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     02/21/2012  Created
- *                          mjjones     06/14/2012  Test functional DIMM
- *
- *  HWP_IGNORE_VERSION_CHECK
- */
-
-#include <fapiTestHwpDq.H>
-#include <dimmBadDqBitmapFuncs.H>
-
-extern "C"
-{
-
-fapi::ReturnCode fapiTestHwpDq(const fapi::Target & i_mba)
-{
-    FAPI_INF(">>fapiTestHwpDq: %s", i_mba.toEcmdString());
-
-    fapi::ReturnCode l_rc;
-    uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE];
-
-    do
-    {
-        // Get the bad DQ Bitmap with an incorrect port
-        l_rc = dimmGetBadDqBitmap(i_mba, 5, 0, 0, l_dqBitmap);
-
-        if (!l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Did not get expected error from dimmGetBadDqBitmap");
-            FAPI_SET_HWP_ERROR(l_rc, RC_TEST_DQ_NO_ERR_ON_BAD_PARAMS);
-            break;
-        }
-
-        // Do not log error to avoid adding an expected error to the log
-        FAPI_INF("fapiTestHwpDq: Got expected error from dimmGetBadDqBitmap");
-        l_rc = fapi::FAPI_RC_SUCCESS;
-
-        // Get associated functional DIMMs
-        std::vector<fapi::Target> l_dimms;
-        l_rc = fapiGetAssociatedDimms(i_mba, l_dimms);
-
-        if (l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Error from fapiGetAssociatedDimms");
-            break;
-        }
-
-        if (l_dimms.size() == 0)
-        {
-            FAPI_ERR("fapiTestHwpDq: Did not find any functional DIMMs, skipping");
-            break;
-        }
-
-        // Use the last DIMM
-        fapi::Target & l_dimmTarg = l_dimms.back();
-
-        // Get the DIMM's port and dimm number
-        uint8_t l_port = 0;
-        uint8_t l_dimm = 0;
-
-        l_rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_dimmTarg, l_port);
-
-        if (l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Error getting ATTR_MBA_PORT");
-            break;
-        }
-
-        l_rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_dimmTarg, l_dimm);
-
-        if (l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Error getting ATTR_MBA_DIMM");
-            break;
-        }
-
-        FAPI_INF("fapiTestHwpDq: Using dimm with MBA port:%d, dimm:%d",
-                 l_port, l_dimm);
-
-        // Get the bad DQ Bitmap for all ranks and print any non-zero data
-        const uint8_t NUM_RANKS = 4;
-        uint8_t l_rank = 0;
-        for (l_rank = 0; l_rank < NUM_RANKS; l_rank++)
-        {
-            // Get the bad DQ Bitmap for the rank
-            l_rc = dimmGetBadDqBitmap(i_mba, l_port, l_dimm, l_rank,
-                                      l_dqBitmap);
-
-            if (l_rc)
-            {
-                FAPI_ERR("fapiTestHwpDq: Error from dimmGetBadDqBitmap");
-                break;
-            }
-
-            // Trace any bad DQs
-            for (uint8_t i = 0; i < DIMM_DQ_RANK_BITMAP_SIZE; i++)
-            {
-                if (l_dqBitmap[i] != 0)
-                {
-                    FAPI_INF("fapiTestHwpDq: Non-zero DQ data. Rank:%d, Byte:%d, Val:0x%02x",
-                             l_rank, i, l_dqBitmap[i]);
-                }
-            }
-        }
-
-        if (l_rc)
-        {
-            break;
-        }
-
-        // Record the two bytes of the bad DQ bitmap that this function
-        // will change so that it can be restored
-        uint8_t l_origDq2 = l_dqBitmap[2];
-        uint8_t l_origDq6 = l_dqBitmap[6];
-
-        // Set 2 bad DQ bits
-        l_dqBitmap[2] = 0x40;
-        l_dqBitmap[6] = 0x20;
-
-        // Set the bad DQ Bitmap for the last rank
-        l_rc = dimmSetBadDqBitmap(i_mba, l_port, l_dimm, l_rank - 1, l_dqBitmap);
-
-        if (l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Error from dimmSetBadDqBitmap");
-            break;
-        }
-
-        // Check that the data can be read back
-        l_dqBitmap[2] = 0;
-        l_dqBitmap[6] = 0;
-
-        l_rc = dimmGetBadDqBitmap(i_mba, l_port, l_dimm, l_rank - 1, l_dqBitmap);
-
-        if (l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Error from dimmGetBadDqBitmap (2)");
-            break;
-        }
-
-        if ((l_dqBitmap[2] != 0x40) || (l_dqBitmap[6] != 0x20))
-        {
-            FAPI_ERR("fapiTestHwpDq: Got bad data 0x%x:0x%x",
-                     l_dqBitmap[2], l_dqBitmap[6]);
-            uint8_t & FFDC_DATA1 = l_dqBitmap[2];
-            uint8_t & FFDC_DATA2 = l_dqBitmap[6];
-            FAPI_SET_HWP_ERROR(l_rc, RC_TEST_DQ_BAD_DATA);
-            break;
-        }
-
-        // Write the original data back
-        l_dqBitmap[2] = l_origDq2;
-        l_dqBitmap[6] = l_origDq6;
-
-        l_rc = dimmSetBadDqBitmap(i_mba, l_port, l_dimm, l_rank - 1, l_dqBitmap);
-
-        if (l_rc)
-        {
-            FAPI_ERR("fapiTestHwpDq: Error from dimmSetBadDqBitmap (2)");
-            break;
-        }
-
-    } while (0);
-
-    FAPI_INF("<<fapiTestHwpDq");
-    return l_rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/fapiTestHwpError.C b/src/usr/hwpf/hwp/fapiTestHwpError.C
deleted file mode 100644
index 0491e1596..000000000
--- a/src/usr/hwpf/hwp/fapiTestHwpError.C
+++ /dev/null
@@ -1,143 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/fapiTestHwpError.C $                         */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file fapiTestHwpError.C
- *
- *  @brief Implements a simple test Hardware Procedure that returns an error
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     08/08/2011  Created.
- *                          camvanng    09/06/2011  Added code to test
- *                                                  fapiLogError
- *                          mjjones     10/06/2011  Major updates due to new
- *                                                  ErrorInfo design
- *                          mjjones     10/17/2011  Moved AnalyzeError to new file
- *                          rjknight    09/28/2013  Added callout test for MBA
- *                                                  dimm callout support
- *                          whs         03/11/2014  Add FW traces to error logs
- *
- *
- *  HWP_IGNORE_VERSION_CHECK
- */
-
-#include <fapiTestHwpError.H>
-
-extern "C"
-{
-
-//******************************************************************************
-// hwpTestError function
-//******************************************************************************
-fapi::ReturnCode hwpTestError(const fapi::Target & i_procTarget,
-                              const fapi::Target & i_mbaTarget )
-{
-    FAPI_INF("hwpTestError: Start HWP");
-
-    fapi::ReturnCode l_rc;
-
-    // Test ability for FAPI to request FW traces added to error log
-    FAPI_ERR("hwpTestError: Generating RC_TEST_COLLECT_TRACE");
-    uint32_t  FFDC_VALUE = 0xBEF2;
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_COLLECT_TRACE);
-    // Log the error
-    fapiLogError(l_rc, fapi::FAPI_ERRL_SEV_PREDICTIVE, true);
-
-    // Local data that needs to be captured as FFDC
-    uint32_t l_ffdc = 0x12345678;
-    ecmdDataBufferBase l_buf(65);
-    l_buf.setBit(1);
-    l_buf.setBit(64);
-
-    FAPI_ERR("hwpTestError: Generating RC_TEST_ERROR_A");
-    const fapi::Target & UNIT_TEST_CHIP_TARGET = i_procTarget;
-    const fapi::Target & UNIT_TEST_MBA_TARGET = i_mbaTarget;
-    uint32_t & UNIT_TEST_FFDC_DATA_INTEGER = l_ffdc;
-    ecmdDataBufferBase & UNIT_TEST_FFDC_DATA_BUF = l_buf;
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_ERROR_A);
-
-    // Log the error
-    fapiLogError(l_rc, fapi::FAPI_ERRL_SEV_PREDICTIVE, true);
-
-    // Check that the return code is set to success
-    if (!l_rc.ok())
-    {
-        FAPI_ERR("Performing HWP: hwpTestError: rc is 0x%x, "
-                 "expected success", static_cast<uint32_t>(l_rc));
-    }
-
-    FAPI_INF("Test calling out all DIMMs based on mba port 0");
-
-    // all dimms on a specific port
-    FAPI_ERR("Generating RC_TEST_DIMM_CALLOUT_MBA_A");
-    uint8_t UNIT_TEST_MBA_PORT_NUMBER = 0x0;
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_DIMM_CALLOUT_MBA_A);
-    fapiLogError( l_rc,fapi::FAPI_ERRL_SEV_PREDICTIVE, true );
-
-    // specific dimm on a specific port
-    FAPI_INF("Test calling out DIMM3 based on port and dimm number");
-
-    UNIT_TEST_MBA_PORT_NUMBER = 0x1;
-    uint8_t UNIT_TEST_DIMM_NUMBER = 0x01;
-
-    FAPI_ERR("Generating RC_TEST_DIMM_CALLOUT_MBA_B");
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_DIMM_CALLOUT_MBA_B);
-    fapiLogError( l_rc,fapi::FAPI_ERRL_SEV_PREDICTIVE, true );
-
-    FAPI_INF("Test calling out all dimms of an mba");
-    // all dimms on an mba target
-    FAPI_ERR("Generating RC_TEST_DIMM_CALLOUT_MBA_C");
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_DIMM_CALLOUT_MBA_C);
-    fapiLogError( l_rc,fapi::FAPI_ERRL_SEV_PREDICTIVE, true );
-
-    // commented out due to ci test failing on deconfigured parts
-    FAPI_INF("Test deconfigure all dimms of mba with port 0 specified");
-    UNIT_TEST_MBA_PORT_NUMBER = 0x0;
-
-    // deconfigure all dimms on port 0
-    FAPI_ERR("Generating RC_TEST_DIMM_DECONFIGURE_MBA_A ");
-    FAPI_SET_HWP_ERROR(l_rc,RC_TEST_DIMM_DECONFIGURE_MBA_A);
-    fapiLogError( l_rc,fapi::FAPI_ERRL_SEV_PREDICTIVE, true );
-
-    FAPI_INF("Test gard of DIMM2");
-    // gard dimm 0 onn port 1
-    UNIT_TEST_DIMM_NUMBER = 0x00;
-    UNIT_TEST_MBA_PORT_NUMBER = 0x01;
-
-    FAPI_ERR("Generating RC_TEST_DIMM_GARD_MBA_B ");
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_DIMM_GARD_MBA_B);
-    fapiLogError( l_rc,fapi::FAPI_ERRL_SEV_PREDICTIVE, true );
-
-    // Generate the same error again need to return an error
-    // to make the test code happy
-    FAPI_ERR("hwpTestError: Generating RC_TEST_ERROR_A again");
-    FAPI_SET_HWP_ERROR(l_rc, RC_TEST_ERROR_A);
-
-    FAPI_INF("hwpTestError: End HWP");
-    return l_rc;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/fapiTestHwpFfdc.C b/src/usr/hwpf/hwp/fapiTestHwpFfdc.C
deleted file mode 100644
index e3fffd6f2..000000000
--- a/src/usr/hwpf/hwp/fapiTestHwpFfdc.C
+++ /dev/null
@@ -1,65 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/fapiTestHwpFfdc.C $                          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2011,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file fapiTestHwpFfdc.C
- *
- *  @brief Implements a simple test Hardware Procedure that collects FFDC data
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     08/08/2011  Created.
- *                          mjjones     10/06/2011  Updated due to new ErrorInfo
- *                                                  design.
- *
- *
- *  HWP_IGNORE_VERSION_CHECK
- */
-
-#include <fapiTestHwpFfdc.H>
-
-extern "C"
-{
-
-//******************************************************************************
-// hwpTestFfdc1 function
-//******************************************************************************
-fapi::ReturnCode hwpTestFfdc1(const fapi::Target & i_target,
-                              fapi::ReturnCode & o_rc)
-{
-    FAPI_INF("hwpTestFfdc1: Start HWP (FFDC HWP)");
-
-    // Collect a uint64_t worth of FFDC
-    uint64_t l_ffdc = 0x1122334455667788ULL;
-
-    // Add FFDC specified by RC_TEST_ERROR_B
-    uint64_t & UNIT_TEST_FFDC_DATA = l_ffdc;
-    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_TEST_ERROR_B);
-
-    FAPI_INF("hwpTestFfdc1: End HWP");
-    return fapi::FAPI_RC_SUCCESS;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/hwp.mk b/src/usr/hwpf/hwp/hwp.mk
deleted file mode 100644
index 6af31d0b7..000000000
--- a/src/usr/hwpf/hwp/hwp.mk
+++ /dev/null
@@ -1,46 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/hwp.mk $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2014,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-
-#   CompressedScanData struct needed for getRepairRings()
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build
-
-OBJS += dimmBadDqBitmapAccessHwp.o
-OBJS += dimmBadDqBitmapFuncs.o
-OBJS += fapiTestHwpError.o
-OBJS += fapiTestHwpFfdc.o
-OBJS += fapiTestHwpConfig.o
-
-include ${ROOTPATH}/src/usr/hwpf/hwp/mvpd_accessors/mvpd.mk
-include ${ROOTPATH}/src/usr/hwpf/hwp/pll_accessors/pll.mk
-include ${ROOTPATH}/src/usr/hwpf/hwp/winkle_ring_accessors/winkle_ring.mk
-include ${ROOTPATH}/src/usr/hwpf/hwp/utility_procedures/utils.mk
-include ${ROOTPATH}/src/usr/hwpf/hwp/chip_accessors/chip.mk
-include ${ROOTPATH}/src/usr/hwpf/hwp/spd_accessors/spd.mk
-include ${ROOTPATH}/src/usr/hwpf/hwp/tp_dbg_data_accessors/tp_dbg.mk
diff --git a/src/usr/hwpf/hwp/makefile b/src/usr/hwpf/hwp/makefile
deleted file mode 100644
index 81bb38267..000000000
--- a/src/usr/hwpf/hwp/makefile
+++ /dev/null
@@ -1,64 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2016
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../..
-HWPPATH = ./
-MODULE = hwp
-
-EXTRAINCDIR += ${ROOTPATH}/src/usr/initservice/istepdispatcher
-
-include hwp.mk
-
-OBJS += fapiTestHwp.o
-OBJS += fapiTestHwpDq.o
-OBJS += fapiHwpExecInitFile.o
-
-#Temporarily compiling these here to avoid linker errors
-#This file will eventually be deleted when we delete hwpf/
-OBJS += ../isteps/hwpisteperror.o
-OBJS += ../isteps/hwpistepud.o
-
-SUBDIRS	+= dmi_training.d
-SUBDIRS	+= sbe_centaur_init.d
-SUBDIRS	+= dram_training.d
-SUBDIRS	+= activate_powerbus.d
-SUBDIRS	+= build_winkle_images.d
-SUBDIRS	+= core_activate.d
-SUBDIRS	+= dram_initialization.d
-SUBDIRS	+= edi_ei_initialization.d
-SUBDIRS	+= establish_system_smp.d
-SUBDIRS	+= bus_training.d
-SUBDIRS	+= occ.d
-SUBDIRS	+= tod_init.d
-SUBDIRS	+= nest_chiplets.d
-SUBDIRS	+= start_payload.d
-SUBDIRS	+= slave_sbe.d
-SUBDIRS	+= pstates.d
-SUBDIRS	+= proc_hwreconfig.d
-SUBDIRS	+= runtime.d
-SUBDIRS	+= secure_boot.d
-SUBDIRS	+= mvpd_accessors.d
-
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/mc_config/makefile b/src/usr/hwpf/hwp/mc_config/makefile
deleted file mode 100644
index 908d9983f..000000000
--- a/src/usr/hwpf/hwp/mc_config/makefile
+++ /dev/null
@@ -1,75 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/mc_config/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-MODULE = mc_config
-
-CFLAGS += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), -D FAPI_MSSLABONLY -D FAPI_LRDIMM)
-EXTRAINCDIR += $(if $(CONFIG_VPD_GETMACRO_USE_EFF_ATTR), ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_draminit)
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures/
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/???
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_volt
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_freq
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/dram_training/mss_lrdimm_funcs
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_attr_cleanup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave
-
-OBJS += mss_eff_config.o
-OBJS += mss_eff_grouping.o
-OBJS += opt_memmap.o
-OBJS += mss_eff_config_thermal.o
-OBJS += mss_eff_config_termination.o
-OBJS += mss_eff_config_rank_group.o
-OBJS += mss_eff_config_cke_map.o
-OBJS += mss_bulk_pwr_throttles.o
-OBJS += mss_util_to_throttle.o
-OBJS += mss_throttle_to_power.o
-OBJS += mss_eff_config_shmoo.o
-OBJS += mss_error_support.o
-OBJS += mss_eff_pre_config.o
-OBJS += mss_count_active_centaurs.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_config
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/mc_config/mss_eff_mb_interleave
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
deleted file mode 100644
index 28e891c5a..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C
+++ /dev/null
@@ -1,580 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_bulk_pwr_throttles.C,v 1.32 2015/10/05 19:49:06 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_bulk_pwr_throttles
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Jacob Sloat       Email: jdsloat@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// applicable CQ component memory_screen
-//
-// DESCRIPTION:
-// The purpose of this procedure is to set the throttle attributes based on a
-// power limit for the dimms on the channel pair
-// At the end, output attributes will be updated with throttle values that will
-// have dimms at or below the limit
-// NOTE:  ISDIMMs and CDIMMs are handled differently
-//   ISDIMMs use a power per DIMM for the thermal power limit from the MRW
-//   CDIMM will use power per CDIMM (power for all virtual dimms) for the
-//    thermal power limit from the MRW
-// Plan is to have ISDIMM use the per-slot throttles (thermal throttles) or
-//  per-mba throttles (power throttles), and CDIMM to use the per-chip throttles
-// Note that throttle_n_per_mba takes on different meanings depending on how
-// cfg_nm_per_slot_enabled is set
-//   Can be slot0/slot1 OR slot0/MBA throttling
-// Note that throttle_n_per_chip takes on different meaning depending on how
-// cfg_count_other_mba_dis is set
-//  Can be per-chip OR per-mba throttling
-// These inits here are done in mss_scominit
-// ISDIMM:  These registers need to be setup to these values, will be able to
-//  do per slot or per MBA throttling
-//   cfg_nm_per_slot_enabled = 1
-//   cfg_count_other_mba_dis = 1
-// CDIMM:  These registers need to be setup to these values, will be able to
-//  do per mba or per chip throttling
-//   cfg_nm_per_slot_enabled = 0
-//   cfg_count_other_mba_dis = 0
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.32  | pardeik  | 07/31/15| Support new CDIMM total power curves (SW316162)
-//   1.31  | pardeik  |15-MAY-15| split FAPI_INF statement up to limit variables
-//   1.30  | pardeik  |12-FEB-15| Review change to check for l_throttle_n_per_chip
-//         |          |         |   being zero (shouldn't have any impact to hwp)
-//   1.29  | pardeik  |12-FEB-15| CDIMM DDR4 throttle updates (set Nmba to Nchip)
-//   1.28  | pardeik  |01-DEC-14| Gerrit review updates
-//         |          |         |   changed MAX_UTIL to max_util
-//         |          |         |   changed MIN_UTIL const to min_util float
-//         |          |         |   changed IDLE_UTIL const to idle_util float
-//   1.27  | pardeik  |13-NOV-14| initialize l_channel_power_intercept and 
-//         |          |         | l_channel_power_slope to zero to prevent 
-//         |          |         | compile errors
-//   1.26  | pardeik  |05-NOV-14| removed strings in trace statements
-//         |          |         | changed FAPI_IMP to FAPI_INF
-//   1.25  | pardeik  |31-OCT-14| change ISDIMM_MEMORY_THROTTLE_PERCENT to 65
-//   1.24  | pardeik  |31-OCT-14| fixed equation using ISDIMM_MEMORY_THROTTLE_PERCENT
-//         |          |         | use power instead of utilization for error check
-//         |          |         |  RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER
-//   1.23  | pardeik  |27-OCT-14| Change to not call mss_power_to_throttle_calc
-//         |          |         | Make throttle determination more efficient
-//         |          |         | Non Custom DIMMs use hardcoded values and do
-//         |          |         |   not use power curves for these
-//         |          |         | Remove mss_throttle_to_power.H include
-//   1.22  | pardeik  |21-MAY-14| Removed section that adjusts power limit
-//         |          |         | (was not getting correct throttle values
-//         |          |         | to have channel pair power be under limit)
-//         |          |         | Limit channel pair power limit to thermal limit
-//         |          |         | Start with runtime throttle attributes
-//   1.21  | jdsloat  |10-MAR-14| Edited comments
-//   1.20  | pardeik  |06-MAR-14| RAS update for HWP error
-//         |          |         |   (changed the callout from centaur to mba)
-//   1.19  | pardeik  |24-JAN-14| RAS update for HWP error
-//   1.18  | pardeik  |23-JAN-14| gerrit review updates to break out of for loop
-//   1.17  | pardeik  |21-JAN-14| updates to prevent a negative power limit
-//   1.16  | pardeik  |06-JAN-14| use max utiliation from MRW for MAX_UTIL
-//         |          |         | Use ATTR_MRW_MEM_THROTTLE_DENOMINATOR instead
-//         |          |         |  of ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR
-//   1.15  | pardeik  |13-NOV-13| changed MAX_UTIL from 75 to 56.25
-//         |          |         | get default M throttle value from MRW
-//         |          |         | return error if not enough memory power
-//         |          |         | comment fixes to align with scominit settings
-//   1.14  | bellows  |19-SEP-13| fixed possible buffer overrun found by stradale
-//   1.13  | pardeik  |19-JUL-13| removed code to identify if throttles are 
-//         |          |         |   based on thermal or power reasons since the
-//         |          |         |   runtime throttles will now be determined
-//         |          |         |   whenever mss_eff_config_thermal runs
-//   1.12  | pardeik  |08-JUL-13| Update to use CUSTOM_DIMM instead of DIMM_TYPE
-//         |          |         | removed incrementing of throttle denominator
-//         |          |         | set throttle per_mba at end of procedure
-//   1.11  | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
-//         |          |         | added FAPI_ERR before return code lines
-//         |          |         | made trace statements for procedure FAPI_IMP
-//         |          |         | updates for FAPI_SET_HWP_ERROR
-//   1.10  | pardeik  |08-NOV-12| attribute name update for runtime per chip
-//         |          |         | throttles
-//   1.9   | pardeik  |25-OCT-12| updated FAPI_ERR sections, use per_chip
-//         |          |         | variables (in if statements) in the throttle
-//         |          |         | update section when channel pair power is
-//         |          |         | greater than the limit, added CQ component
-//         |          |         | comment line
-//   1.8   | pardeik  |19-OCT-12| Changed throttle_n_per_chip to be based on
-//         |          |         | num_mba_with_dimms
-//         | pardeik  |19-OCT-12| Updated default throttle values to represent
-//         |          |         | cmd bus utilization instead of dram bus
-//         |          |         | utilization
-//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram
-//         |          |         | utilization
-//   1.7   | pardeik  |10-OCT-12| Changed throttle attributes and call new
-//         |          |         | function (mss_throttle_to_power) to calculate
-//         |          |         | the power
-//   1.6   | pardeik  |10-APR-12| power calculation fixes and updates
-//   1.5   | pardeik  |04-APR-12| moved cdimm power calculation to end of
-//         |          |         |section instead of having it in multiple places
-//   1.4   | pardeik  |04-APR-12| do channel throttle denominator check as zero
-//         |          |         |only if there are ranks present
-//         | pardeik  |04-APR-12| use else if instead of if after checking
-//         |          |         | throttle denominator to zero
-//   1.3   | pardeik  |03-APR-12| added cdimm power calculation for half of
-//         |          |         |cdimm, changed i_target from mbs to mba
-//   1.2   | pardeik  |03-APR-12| call mss_eff_config_thermal directly
-//   1.1   | pardeik  |28-MAR-12| Updated to use Attributes
-//         | pardeik  |11-NOV-11| First Draft.
-
-
-//------------------------------------------------------------------------------
-//  My Includes
-//------------------------------------------------------------------------------
-#include <mss_bulk_pwr_throttles.H>
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-extern "C" {
-
-    using namespace fapi;
-
-
-//------------------------------------------------------------------------------
-// Funtions in this file
-//------------------------------------------------------------------------------
-    fapi::ReturnCode mss_bulk_pwr_throttles(
-					    const fapi::Target & i_target_mba
-					    );
-
-//------------------------------------------------------------------------------
-// @brief mss_bulk_pwr_throttles(): This function determines the throttle values
-// from a MBA channel pair power limit
-//
-// @param[in]	const fapi::Target & i_target_mba:  MBA Target passed in
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba
-					    )
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_bulk_pwr_throttles ***");
-
-	const uint8_t MAX_NUM_PORTS = 2;
-	const uint8_t MAX_NUM_DIMMS = 2;
-	float idle_util = 0; // in percent
-	float min_util = 1; // in percent
-// These are the constants to use for ISDIMM power/throttle support
-// Note that these are hardcoded and ISDIMMs will not use power curves
-// No Throttling if available power is >= ISDIMM_MAX_DIMM_POWER
-// Throttle when ISDIMM_MIN_DIMM_POWER <= available power <= ATTR_MSS_MEM_WATT_TARGET
-//   Throttle value will be maximum throttle * ISDIMM_MEMORY_THROTTLE_PERCENT
-	const uint32_t ISDIMM_MAX_DIMM_POWER = 1200;  // cW, max ISDIMM power for no throttling
-	const uint32_t ISDIMM_MIN_DIMM_POWER = 800;   // cW, min ISDIMM power for throttling
-	const uint8_t ISDIMM_MEMORY_THROTTLE_PERCENT = 65;  // percent, throttle impact when limit is between min and max power.  A value of 0 would be for no throttle impact.
-
-	uint32_t l_total_power_slope_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	uint32_t l_total_power_int_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	uint8_t l_dimm_ranks_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	uint8_t l_port;
-	uint8_t l_dimm;
-	float l_dimm_power_array_idle[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	float l_dimm_power_array_max[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	float l_channel_power_array_idle[MAX_NUM_PORTS];
-	float l_channel_power_array_max[MAX_NUM_PORTS];
-	uint8_t l_power_curve_percent_uplift;
-	uint8_t l_power_curve_percent_uplift_idle;
-	uint32_t l_max_dram_databus_util;
-	uint8_t l_num_mba_with_dimms;
-	uint8_t l_custom_dimm;
-	fapi::Target l_target_chip;
-	std::vector<fapi::Target> l_target_mba_array;
-	std::vector<fapi::Target> l_target_dimm_array;
-	uint8_t l_mba_index;
-	uint32_t l_throttle_d;
-	float l_channel_pair_power_idle;
-	float l_channel_pair_power_max;
-	uint32_t l_channel_pair_watt_target;
-	float l_utilization;
-	uint32_t l_number_of_dimms;
-	float l_channel_power_slope = 0;
-	float l_channel_power_intercept = 0;
-	uint32_t l_throttle_n_per_mba;
-	uint32_t l_throttle_n_per_chip;
-	uint32_t channel_pair_power;
-	uint32_t runtime_throttle_n_per_mba;
-	uint32_t runtime_throttle_n_per_chip;
-	uint8_t l_dram_gen;
-
-// get input attributes
-	rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_custom_dimm);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_CUSTOM_DIMM");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_MAX_DRAM_DATABUS_UTIL,
-			   NULL, l_max_dram_databus_util);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MAX_DRAM_DATABUS_UTIL");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_MEM_THROTTLE_DENOMINATOR, NULL, l_throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_WATT_TARGET,
-			   &i_target_mba, l_channel_pair_watt_target);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_WATT_TARGET");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
-			   &i_target_mba, runtime_throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
-			   &i_target_mba, runtime_throttle_n_per_chip);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN,
-			   &i_target_mba, l_dram_gen);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_GEN");
-	    return rc;
-	}
-
-// other attributes for custom dimms to get
-	if (l_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-	    rc = FAPI_ATTR_GET(ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT,
-			       NULL, l_power_curve_percent_uplift);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_GET(ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE,
-			       NULL, l_power_curve_percent_uplift_idle);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_GET(ATTR_MSS_TOTAL_POWER_SLOPE,
-			       &i_target_mba, l_total_power_slope_array);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_MSS_TOTAL_POWER_SLOPE");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_GET(ATTR_MSS_TOTAL_POWER_INT,
-			       &i_target_mba, l_total_power_int_array);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_MSS_TOTAL_POWER_INT");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,
-			       &i_target_mba, l_dimm_ranks_array);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_EFF_NUM_RANKS_PER_DIMM");
-		return rc;
-	    }
-	}
-
-// Maximum theoretical data bus utilization (percent of max) (for ceiling)
-// Comes from MRW value in c% - convert to %
-	float max_util = (float) l_max_dram_databus_util / 100;
-
-// determine the dimm power
-// For custom dimms, use the VPD power curve data
-	if (l_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-// get number of mba's with dimms
-// Get Centaur target for the given MBA
-	    rc = fapiGetParentChip(i_target_mba, l_target_chip);
-	    if (rc) {
-		FAPI_ERR("Error calling fapiGetParentChip");
-		return rc;
-	    }
-// Get MBA targets from the parent chip centaur
-	    rc = fapiGetChildChiplets(l_target_chip,
-				      fapi::TARGET_TYPE_MBA_CHIPLET,
-				      l_target_mba_array,
-				      fapi::TARGET_STATE_PRESENT);
-	    if (rc) {
-		FAPI_ERR("Error calling fapiGetChildChiplets");
-		return rc;
-	    }
-	    l_num_mba_with_dimms = 0;
-	    for (l_mba_index=0; l_mba_index < l_target_mba_array.size(); l_mba_index++)
-	    {
-		rc = fapiGetAssociatedDimms(l_target_mba_array[l_mba_index],
-					    l_target_dimm_array,
-					    fapi::TARGET_STATE_PRESENT);
-		if (rc) {
-		    FAPI_ERR("Error calling fapiGetAssociatedDimms");
-		    return rc;
-		}
-		if (l_target_dimm_array.size() > 0)
-		{
-		    l_num_mba_with_dimms++;
-		}
-	    }
-
-// add up the power from all dimms for this MBA (across both channels)
-// for IDLE (utilization=0) and maximum utilization
-	    l_channel_pair_power_idle = 0;
-	    l_channel_pair_power_max = 0;
-	    for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
-	    {
-		l_channel_power_array_idle[l_port] = 0;
-		l_channel_power_array_max[l_port] = 0;
-		for (l_dimm=0; l_dimm < MAX_NUM_DIMMS; l_dimm++)
-		{
-// default dimm power is zero (used for dimms that are not physically present)
-		    l_dimm_power_array_idle[l_port][l_dimm] = 0;
-		    l_dimm_power_array_max[l_port][l_dimm] = 0;
-// See if there are any ranks present on the dimm (configured or deconfigured)
-		    if (l_dimm_ranks_array[l_port][l_dimm] > 0)
-		    {
-			l_dimm_power_array_idle[l_port][l_dimm] = l_dimm_power_array_idle[l_port][l_dimm] + (idle_util / 100 * l_total_power_slope_array[l_port][l_dimm]) + l_total_power_int_array[l_port][l_dimm];
-			l_dimm_power_array_max[l_port][l_dimm] = l_dimm_power_array_max[l_port][l_dimm] + (max_util / 100 * l_total_power_slope_array[l_port][l_dimm]) + l_total_power_int_array[l_port][l_dimm];
-		    }
-// Include any system uplift here too
-		    if (l_dimm_power_array_idle[l_port][l_dimm] > 0)
-		    {
-			l_dimm_power_array_idle[l_port][l_dimm] =
-			  l_dimm_power_array_idle[l_port][l_dimm] *
-			       (1 + (float)l_power_curve_percent_uplift_idle / 100);
-		    }
-		    if (l_dimm_power_array_max[l_port][l_dimm] > 0)
-		    {
-			l_dimm_power_array_max[l_port][l_dimm] =
-			  l_dimm_power_array_max[l_port][l_dimm] *
-			       (1 + (float)l_power_curve_percent_uplift / 100);
-		    }
-// calculate channel power by adding up the power of each dimm
-		    l_channel_power_array_idle[l_port] = l_channel_power_array_idle[l_port] + l_dimm_power_array_idle[l_port][l_dimm];
-		    l_channel_power_array_max[l_port] = l_channel_power_array_max[l_port] + l_dimm_power_array_max[l_port][l_dimm];
-		    FAPI_DBG("[P%d:D%d][CH Util %4.2f/%4.2f][Slope:Int %d:%d][UpliftPercent idle/max %d/%d)][Power min/max %4.2f/%4.2f cW]", l_port, l_dimm, idle_util, max_util, l_total_power_slope_array[l_port][l_dimm], l_total_power_int_array[l_port][l_dimm], l_power_curve_percent_uplift_idle, l_power_curve_percent_uplift, l_dimm_power_array_idle[l_port][l_dimm], l_dimm_power_array_max[l_port][l_dimm]);
-		}
-		FAPI_DBG("[P%d][CH Util %4.2f/%4.2f][Power %4.2f/%4.2f cW]", l_port, min_util, max_util, l_channel_power_array_idle[l_port], l_channel_power_array_max[l_port]);
-		l_channel_pair_power_idle = l_channel_pair_power_idle + l_channel_power_array_idle[l_port];
-		l_channel_pair_power_max = l_channel_pair_power_max + l_channel_power_array_max[l_port];
-	    }
-
-// calculate the slope/intercept values from power values just calculated above
-	    l_channel_power_slope = (l_channel_pair_power_max - l_channel_pair_power_idle) / ( (max_util / 100) - (idle_util / 100) );
-	    l_channel_power_intercept = l_channel_pair_power_idle;
-
-// calculate the utilization needed to be under power limit
-	    l_utilization = 0;
-	    if (l_channel_pair_watt_target > l_channel_power_intercept)
-	    {
-		l_utilization = (l_channel_pair_watt_target - l_channel_power_intercept) / l_channel_power_slope * 100;
-		if (l_utilization > max_util)
-		{
-		    l_utilization = max_util;
-		}
-	    }
-
-// Calculate the NperChip and NperMBA Throttles
-	    l_throttle_n_per_chip = int((l_utilization / 100 * l_throttle_d / 4) * l_num_mba_with_dimms);
-	    if (l_throttle_n_per_chip > (max_util / 100 * l_throttle_d / 4) )
-	    {
-		l_throttle_n_per_mba = int((max_util / 100 * l_throttle_d / 4));
-	    }
-	    else
-	    {
-		l_throttle_n_per_mba = l_throttle_n_per_chip;
-	    }
-
-// Calculate the channel power at the utilization determined
-	    channel_pair_power = int(l_utilization / 100 * l_channel_power_slope + l_channel_power_intercept);
-
-	FAPI_DBG("[Channel Pair Power min/max %4.2f/%4.2f cW][Slope/Intercept %4.2f/%4.2f cW][Utilization Percent %4.2f, Power %d cW]", l_channel_pair_power_idle, l_channel_pair_power_max, l_channel_power_slope, l_channel_power_intercept, l_utilization, channel_pair_power);
-	}
-
-// for non custom dimms, use hardcoded values
-// If power limit is at or above max power, use unthrottled settings
-// If between min and max power, use a static throttle point
-// If below min power, return an error
-	else
-	{
-// get number of dimms attached to this mba
-	    rc = fapiGetAssociatedDimms(i_target_mba,
-					l_target_dimm_array,
-					fapi::TARGET_STATE_PRESENT);
-	    if (rc) {
-		FAPI_ERR("Error calling fapiGetAssociatedDimms");
-		return rc;
-	    }
-	    l_number_of_dimms = l_target_dimm_array.size();
-
-// ISDIMMs, set to a value of one since throttles are handled on a per MBA basis
-	    l_num_mba_with_dimms = 1;
-
-// MBA Power Limit is higher than dimm power, run unthrottled
-	    if (l_channel_pair_watt_target >= (ISDIMM_MAX_DIMM_POWER * l_number_of_dimms))
-	    {
-		l_utilization = max_util;
-		channel_pair_power = ISDIMM_MAX_DIMM_POWER * l_number_of_dimms;
-	    }
-	    else if (l_channel_pair_watt_target >= (ISDIMM_MIN_DIMM_POWER * l_number_of_dimms))
-	    {
-		if (ISDIMM_MEMORY_THROTTLE_PERCENT > 99)
-		{
-		    l_utilization = min_util;
-		}
-		else
-		{
-		    l_utilization = max_util * (1 - (float)ISDIMM_MEMORY_THROTTLE_PERCENT / 100);
-		}
-		channel_pair_power = ISDIMM_MIN_DIMM_POWER * l_number_of_dimms;
-	    }
-	    else
-	    {
-		// error case, available power less than allocated minimum dimm power
-		l_utilization = 0;
-		channel_pair_power = ISDIMM_MIN_DIMM_POWER * l_number_of_dimms;
-	    }
-	    l_throttle_n_per_mba = int(l_utilization / 100 * l_throttle_d / 4);
-	    l_throttle_n_per_chip = l_throttle_n_per_mba;
-
-	FAPI_DBG("[Power/DIMM min/max %d/%d cW][Utilization Percent %4.2f][Number of DIMMs %d]", ISDIMM_MIN_DIMM_POWER, ISDIMM_MAX_DIMM_POWER, l_utilization, l_number_of_dimms);
-
-	}
-
-// adjust the throttles to minimum utilization if needed
-	if (l_utilization < min_util)
-	{
-	    l_throttle_n_per_mba = int(min_util / 100 * l_throttle_d / 4);
-	    l_throttle_n_per_chip = l_throttle_n_per_mba * l_num_mba_with_dimms;
-	}
-
-// ensure that N throttle values are not zero, if so set to lowest values possible
-	if ( (l_throttle_n_per_mba == 0) || (l_throttle_n_per_chip == 0))
-	{
-	    l_throttle_n_per_mba = 1;
-	    l_throttle_n_per_chip = l_throttle_n_per_mba * l_num_mba_with_dimms;
-	}
-
-// for better custom dimm performance for DDR4, set the per mba throttle to the per chip throttle
-// Not planning on doing this for DDR3
-	if ( (l_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-	     && (l_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) )
-	    {
-		l_throttle_n_per_mba = l_throttle_n_per_chip;
-	    }
-
-// adjust the throttles to the MRW thermal limit throttles (ie.  thermal/power limit less than available power)
-	if ( (l_throttle_n_per_mba > runtime_throttle_n_per_mba) ||
-	     (l_throttle_n_per_chip > runtime_throttle_n_per_chip) )
-	{
-	    FAPI_DBG("Throttles [%d/%d/%d] will be limited by power/thermal limit [%d/%d/%d].", l_throttle_n_per_mba, l_throttle_n_per_chip, l_throttle_d, runtime_throttle_n_per_mba, runtime_throttle_n_per_chip, l_throttle_d);
-	    if (l_throttle_n_per_mba > runtime_throttle_n_per_mba) {
-		l_throttle_n_per_mba = runtime_throttle_n_per_mba;
-	    }
-	    if (l_throttle_n_per_chip > runtime_throttle_n_per_chip) {
-		l_throttle_n_per_chip = runtime_throttle_n_per_chip;
-	    }
-	    
-	}
-
-// Calculate out the utilization at the final throttle settings
-	l_utilization = (float)l_throttle_n_per_chip * 4 / l_throttle_d / l_num_mba_with_dimms * 100;
-
-// Calculate out the utilization at this new utilization setting for custom dimms
-// does not matter for non custom dimms since those do not use power curves
-	if (l_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-	    channel_pair_power = int(l_utilization / 100 * l_channel_power_slope + l_channel_power_intercept);
-	}
-
-	FAPI_INF("[Available Channel Pair Power %d cW][UTIL %4.2f][Channel Pair Power %d cW]", l_channel_pair_watt_target, l_utilization, channel_pair_power);
-	FAPI_INF("[Throttles %d/%d/%d]", l_throttle_n_per_mba, l_throttle_n_per_chip, l_throttle_d);
-
-// Update output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
-			   &i_target_mba, l_throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
-			   &i_target_mba, l_throttle_n_per_chip);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
-			   &i_target_mba, l_throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_CHANNEL_PAIR_MAXPOWER,
-			   &i_target_mba, channel_pair_power);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_CHANNEL_PAIR_MAXPOWER");
-	    return rc;
-	}
-
-// Check to see if there is not enough available power at min_util or higher
-	if (channel_pair_power > l_channel_pair_watt_target)
-	{
-	    FAPI_ERR("Not enough available memory power [Channel Pair Power %d/%d cW]", channel_pair_power, l_channel_pair_watt_target);
-	    const uint32_t & PAIR_POWER = channel_pair_power;
-	    const uint32_t & PAIR_WATT_TARGET = l_channel_pair_watt_target;
-	    const fapi::Target & MEM_MBA = i_target_mba;
-	    FAPI_SET_HWP_ERROR(rc, RC_MSS_NOT_ENOUGH_AVAILABLE_DIMM_POWER);
-	    return rc;
-
-	}
-
-	FAPI_INF("*** mss_bulk_pwr_throttles COMPLETE ***");
-	return rc;
-
-    }
-
-} //end extern C
-
-
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
deleted file mode 100644
index ee9683ccd..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H
+++ /dev/null
@@ -1,83 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_bulk_pwr_throttles.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_bulk_pwr_throttles.H,v 1.4 2012/12/12 20:10:44 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_bulk_pwr_throttles.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_bulk_pwr_throttles.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
-// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_bulk_pwr_throttles.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.4   | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
-//         |          |         | removed variable names in typedef
-//   1.3   | pardeik  |11-OCT-12| change i_target to i_target_mba
-//   1.2   | pardeik  |03-APR-12| use mba target intead of mbs
-//   1.1   | pardeik  |11-NOV-11| First Draft.
-
-
-#ifndef MSS_BULK_PWR_THROTTLES_H_
-#define MSS_BULK_PWR_THROTTLES_H_
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_bulk_pwr_throttles_FP_t)
-(
- const fapi::Target &
- );
-
-extern "C"
-{
-//------------------------------------------------------------------------------
-// @brief mss_bulk_pwr_throttles procedure. Set dimm and channel
-// throttle attributes based on available centaur mba port power
-//
-// @param[in]  i_target_mba  Reference to centaur mba target
-//
-// @return ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_bulk_pwr_throttles(const fapi::Target & i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_BULK_PWR_THROTTLES_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
deleted file mode 100644
index 321d9fe08..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C
+++ /dev/null
@@ -1,3057 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.C $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config.C,v 1.55 2015/10/02 19:49:34 sglancy Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_eff_config.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Briana Foxworth   Email: beforwor@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// The purpose of this procedure is to setup attributes used in other mss
-// procedures.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.55  | sglancy  |02-OCT-15| Fixed RCD support for DDR4 ISRDIMMs
-//   1.54  | asaetow  |13-AUG-15| Added ATTR_SPD_SDRAM_ROWS=R17 and ATTR_SPD_SDRAM_ROWS=R18 for DDR4.
-//   1.53  | asaetow  |31-JUL-15| Changed code based on FW code review.
-//         |          |         | Added RC_MSS_EFF_CONFIG_INVALID_DDR4_SPD_TB and RC_MSS_EFF_CONFIG_INCOMPATABLE_SPD_DRAM_GEN.
-//         |          |         | Fixed attribute naming convension from ATTR_TCCD_L to ATTR_EFF_DRAM_TCCD_L and ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS to ATTR_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS.
-//         |          |         | NOTE: DO NOT pickup w/o memory_attributes.xml v1.153 or newer
-//         |          |         | NOTE: DO NOT pickup w/o memory_mss_eff_config.xml v1.6 or newer
-//   1.52  | asaetow  |10-MAY-15| Added initial official DDR4 support to mainline.
-//         |          |         | NOTE: Merge of mss_eff_config_ddr4.C v1.1 from Menlo.
-//         |          |         | NOTE: LRDIMM and TSV not fully supported in this version.
-//         |          |         | Changed backup owner.
-//   1.51  | asaetow  |13-MAR-15| Changed DRAM_AL to be CL-2 in 2N/2T mode and CL-1 in 1N/1T mode.
-//   1.50  | jdsloat  |03-DEC-14| Removed string data types that are not supported.
-//   1.49  | asaetow  |01-DEC-14| Added RDIMM SPD/VPD support for ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15 to take in SPD bits69:76 thru new VPD attribute ATTR_VPD_DIMM_RCD_CNTL_WORD_0_15.
-//         |          |         | Added ATTR_VPD_DIMM_RCD_IBT and ATTR_VPD_DIMM_RCD_OUTPUT_TIMING merge, per meeting with Ken and Dan P.
-//         |          |         | NOTE: DO NOT pickup w/o getMBvpdTermData.C v1.18 or newer from Dan.C and Corey.
-//         |          |         | NOTE: DO NOT pickup w/o getMBvpdTermData.H v1.6 or newer from Dan.C and Corey.
-//         |          |         | NOTE: DO NOT pickup w/o dimm_spd_attributes.xml v1.44 or newer.
-//         |          |         | NOTE: DO NOT pickup w/o memory_mss_eff_config.xml v1.3 or newer.
-//         |          |         | Added hardcode for RC0-DA4=0b0 and RC9-DBA1-DBA0-DA4-DA3=0b00X0, per meeting with Ken and Dan P.
-//         |          |         | Changed l_mss_volt to p_l_mss_eff_config_data->mss_volt.
-//   1.48  | asaetow  |13-OCT-14| Removed call to mss_eff_config_termination() for Palmetto and Habanero using ifdef "FAPI_MSSLABONLY", moving to liveVPD.
-//         |          |         | Note: Stradale, Glacier, KG3, and DDR4 will still need ifdef "FAPI_MSSLABONLY".
-//   1.47  | asaetow  |15-SEP-14| Changed ATTR_MSS_POWER_CONTROL_REQUESTED to ATTR_MRW_POWER_CONTROL_REQUESTED.
-//         |          |         | NOTE: Do NOT pickup without memory_attributes.xml v1.135
-//   1.46  | asaetow  |06-AUG-14| Added ATTR_MSS_POWER_CONTROL_REQUESTED to determine ATTR_EFF_DRAM_DLL_PPD. 
-//   1.45  | sglancy  |05-AUG-14| Updated comments.
-//   1.44  | sglancy  |17-JUL-14| Fixed DDR4 ifdef flag - TARGET_MBA error definition
-//   1.43  | jdsloat  |04-APR-14| Fixed DDR4 ifdef flag
-//   1.42  | asaetow  |31-MAR-14| Added ifdef for three #include from Thi and Jake FW Code review.
-//         |          |         | Added back in bus_width_extension check from SPD byte8[4:3]. 
-//         |          |         | NOTE: Only 64bit with ECC extension is allowed.
-//         |          |         | Added FFDC error callout from Andrea's FW RAS review.
-//         |          |         | NOTE: Do NOT pickup without memory_mss_eff_config.xml v1.2
-//         |          |         | Added comments for commended out code.
-//   1.41  | jdsloat  |20-MAR-14| FASTEXIT settings in mba_def.initfile are causing fails.  Workaround to use SLOWEXIT. SW249561
-//   1.40  | kcook    |14-MAR-14| Added call to DDR4 function support
-//   1.39  | dcadiga  |04-MAR-14| Added isdimm support pass 1
-//   1.38  | asaetow  |17-JAN-14| Removed mss_eff_config_cke_map, now empty, data from vpd.
-//         |          |         | Removed mss_eff_config_termination from normal/FW code flow.
-//         |          |         | Added mss_eff_config_termination to lab only code flow.
-//         |          |         | Removed CDIMM as a valid EFF_DIMM_TYPE, use EFF_CUSTOM_DIMM instead.
-//         |          |         | Added ATTR_MSS_CAL_STEP_ENABLE attribute set to "always run all cal steps".
-//         |          |         | NOTE: Needs mss_eff_config_termination.C v1.42 and mss_eff_config_termination.H v1.2
-//   1.37  | bellows  |17-JAN-14| Fixed VPD version when only single drop
-//   1.36  | bellows  |13-JAN-14| Make VPD version available at mba level
-//   1.35  | asaetow  |13-JAN-14| Fixed ATTR_EFF_DRAM_DLL_PPD from SLOWEXIT to FASTEXIT.
-//         |          |         | Added comments and converted some attr to use enums.
-//   1.34  | bellows  |02-JAN-14| VPD attribute removal
-//   1.33  | bellows  |16-SEP-13| Hostboot compile update
-//   1.32  | kcook    |13-SEP-13| Added using namespace fapi.
-//   1.31  | kcook    |13-SEP-13| Updated define FAPI_LRDIMM token.
-//   1.30  | kcook    |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C.
-//   1.29  | kcook    |16-AUG-13| Added LRDIMM support.
-//   1.28  | asaetow  |06-AUG-13| Added call to mss_eff_pre_config().
-//         |          |         | Removed call to mss_eff_config_thermal().
-//         |          |         | NOTE: Do NOT pickup without mss_eff_pre_config.C v1.1 or newer.
-//   1.27  | asaetow  |05-AUG-13| Restored EFF_STACK_TYPE_DDP_QDP support v1.25.
-//         |          |         | NOTE: Do NOT pickup without mss_eff_config_termination.C v1.28 or newer, contains workaround for incorrect byte33 SPD data in early lab OLD 16G/32G CDIMMs.
-//   1.26  | bellows  |21-JUN-13| Removed last update because caused lab problems
-//   1.25  | asaetow  |20-JUN-13| Added EFF_STACK_TYPE_DDP_QDP support.
-//   1.24  | asaetow  |19-APR-13| Fixed X4 CDIMM spare for RCB to use LOW_NIBBLE only.
-//   1.23  | asaetow  |17-APR-13| Added 10% margin to TRFI per defect HW248225
-//   1.22  | asaetow  |11-APR-13| Changed eff_dram_tdqs from 0 back to 1 for X8 ISDIMMs. 
-//   1.21  | asaetow  |22-MAR-13| Changed ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL back to enable.
-//         |          |         | NOTE: Need mba_def.initfile v1.27 or newer
-//   1.20  | asaetow  |28-FEB-13| Changed temporary ATTR_EFF_ZQCAL_INTERVAL and ATTR_EFF_MEMCAL_INTERVAL to disable.
-//         |          |         | NOTE: Temporary until we get timeout error fixed.
-//   1.19  | sauchadh |26-FEB-13| Added MCBIST related attributes
-//   1.18  | asaetow  |12-FEB-13| Changed eff_dram_tdqs from 1 to 0.
-//   1.17  | asaetow  |30-JAN-13| Changed "ATTR_SPD_MODULE_TYPE_CDIMM is obsolete..." message from error to warning.
-//   1.16  | bellows  |24-JAN-13| Added in CUSTOM bit of SPD and CUSTOM Attr
-//         |          |         | settings.  
-//   1.15  | asaetow  |15-NOV-12| Added call to mss_eff_config_cke_map().
-//         |          |         | NOTE: DO NOT pick-up without
-//         |          |         | mss_eff_config_cke_map.C v1.3 or newer.
-//         |          |         | Added ATTR_MSS_ALLOW_SINGLE_PORT check. 
-//         |          |         | Added ATTR_EFF_DIMM_SPARE.
-//         |          |         | Fixed NUM_RANKS_PER_DIMM for single drop. 
-//         |          |         | Fixed calc_timing_in_clk() for negative. 
-//         |          |         | Fixed IBM_TYPE and STACK_TYPE. 
-//   1.14  | asaetow  |08-NOV-12| Changed to match new memory_attributes.xml
-//         |          |         | v1.45 or newer.
-//         |          |         | NOTE: DO NOT pick-up without
-//         |          |         | memory_attributes.xml v1.45 or newer.
-//   1.13  | asaetow  |11-OCT-12| Added ATTR_EFF_SCHMOO_ADDR_MODE, 
-//         |          |         | ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN,
-//         |          |         | ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN,
-//         |          |         | ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN,
-//         |          |         | ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN,
-//         |          |         | ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN,
-//         |          |         | ATTR_EFF_DRAM_WR_VREF_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_RD_VREF_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_DRV_IMP_CMD_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO,
-//         |          |         | ATTR_EFF_CEN_SLEW_RATE_CMD_SCHMOO,
-//         |          |         | and ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO.
-//   1.12  | asaetow  |26-SEP-12| Added initial equation for
-//         |          |         | ATTR_EFF_ZQCAL_INTERVAL and
-//         |          |         | ATTR_EFF_MEMCAL_INTERVAL from Ken.
-//   1.11  | kjpower  |26-SEP-12| Restructured code, added modularity
-//   1.10  | bellows  |02-AUG-12| Added in DIMM functional vector for Daniel
-//   1.9   | asaetow  |29-MAY-12| Added divide by 0 check for mss_freq.
-//         |          |         | Added 9 new attributes from
-//         |          |         | memory_attributes.xml v1.23
-//         |          |         | Changed plug_config to
-//         |          |         | my_attr_eff_num_drops_per_port.
-//         |          |         | NOTE: DO NOT pick-up without
-//         |          |         | memory_attributes.xml v1.23 or newer.
-//         |          |         | NOTE: Some hard code still in place awaiting
-//         |          |         | SPD attributes bytes[76:68,33,8].
-//   1.8   | asaetow  |04-MAY-12| Fixed my_attr_eff_dimm_size calcualtion and
-//         |          |         | use new ATTR_EFF_DRAM_WIDTH enum from
-//         |          |         | memory_attributes.xml v1.22
-//         |          |         | NOTE: DO NOT pick-up without
-//         |          |         | memory_attributes.xml v1.22 or newer.
-//   1.7   | asaetow  |04-MAY-12| Removed calc_u8_timing_in_clk().
-//         |          |         | Changed calc_u32_timing_in_clk() to
-//         |          |         | calc_timing_in_clk() and changed params.
-//         |          |         | Removed currently unused vars.
-//   1.6   | asaetow  |03-MAY-12| Removed FAPI_ATTR_SET(ATTR_EFF_DRAM_CL), moved
-//         |          |         | to mss_freq.C.
-//         |          |         | Fixed "suggest parentheses around && within
-//         |          |         | ||", per Mike Jones.
-//         |          |         | Changed tCK_in_ps calc to reduce num of
-//         |          |         | operations.
-//   1.5   | asaetow  |02-MAY-12| Removed #include <*.C>, per FW.
-//         |          |         | Added #include <mss_eff_config_thermal.H>
-//         |          |         | Added call to sub-procedure
-//         |          |         | mss_eff_config_thermal().
-//   1.4   | asaetow  |30-APR-12| Changed procedure to use SPD attributes.
-//         |          |         | Added calls to sub-procedures
-//         |          |         | mss_eff_config_rank_group() and
-//         |          |         | mss_eff_config_termination().
-//   1.3   | asaetow  |18-APR-12| Changed procedure to print use
-//         |          |         | mss_eff_config_sim.C until 30APR2012.
-//   1.2   | asaetow  |03-NOV-11| Fixed to comply with mss_eff_config.H.
-//         |          |         | Added calls to mss_eff_config_rank_group()
-//         |          |         | and mss_eff_config_thermal().
-//   1.1   | asaetow  |01-NOV-11| First Draft.
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// My Includes
-//------------------------------------------------------------------------------
-#include <mss_eff_config.H>
-#include <mss_eff_pre_config.H>
-#include <mss_eff_config_rank_group.H>
-#include <mss_eff_config_shmoo.H>
-
-#ifdef FAPI_MSSLABONLY
-#include <mss_eff_config_termination.H>
-#endif
-
-#ifdef FAPI_LRDIMM
-#include <mss_lrdimm_funcs.H>
-#endif
-
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Constants
-//------------------------------------------------------------------------------
-const uint32_t MSS_EFF_EMPTY = 0;
-const uint32_t MSS_EFF_VALID = 255;
-const uint32_t TWO_MHZ = 2000000;
-const uint8_t PORT_SIZE = 2;
-const uint8_t DIMM_SIZE = 2;
-const uint8_t RANK_SIZE = 4;
-
-using namespace fapi;
-
-#ifndef FAPI_LRDIMM
-fapi::ReturnCode mss_lrdimm_eff_config( const Target& i_target_mba,
-                                  uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE],
-                                  uint32_t mss_freq, 
-                                  uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE])
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_LRDIMM_INVALID_EXEC);
-   return rc;
-
-}
-#endif
-
-#ifndef FAPI_MSSLABONLY
-fapi::ReturnCode mss_eff_config_termination( const Target& i_target_mba)
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of MSSLABONLY function on %s!", i_target_mba.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_TERM_EXEC);
-   return rc;
-
-}
-#endif
-
-
-
-//------------------------------------------------------------------------------
-// Structure
-// @brief struct mss_eff_config_data
-// @brief holds the the variables used in many function calls
-//        in mss_eff_config.C
-//------------------------------------------------------------------------------
-struct mss_eff_config_data
-{
-    uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE];
-    uint8_t dimm_functional;
-    uint8_t allow_single_port;
-    uint8_t cur_dram_density;
-    uint32_t mss_freq;
-    uint32_t mss_volt;
-    uint32_t mtb_in_ps_u32array[PORT_SIZE][DIMM_SIZE];
-    uint32_t ftb_in_fs_u32array[PORT_SIZE][DIMM_SIZE];
-    //uint8_t dram_taa;
-    uint32_t dram_tfaw;
-    uint32_t dram_tras;
-    uint32_t dram_trc;
-    uint8_t dram_trcd;
-    uint32_t dram_trfc;
-    uint8_t dram_trp;
-    uint8_t dram_trrd;
-    uint8_t dram_trtp;
-    uint8_t dram_twtr;
-    uint8_t dram_wr;
-    uint8_t dram_trrdl;
-    uint8_t dram_tccdl;
-    uint8_t dram_twtrl;
-};
-
-//------------------------------------------------------------------------------
-// Structure
-// @brief struct mss_eff_config_spd_data
-// @brief holds the DIMM SPD data for an MBA
-//------------------------------------------------------------------------------
-struct mss_eff_config_spd_data
-{
-    uint8_t dram_device_type[PORT_SIZE][DIMM_SIZE];
-    uint8_t sdram_device_type[PORT_SIZE][DIMM_SIZE];
-    uint8_t module_type[PORT_SIZE][DIMM_SIZE];
-    uint8_t custom[PORT_SIZE][DIMM_SIZE];
-    uint8_t sdram_banks[PORT_SIZE][DIMM_SIZE];
-    uint8_t sdram_density[PORT_SIZE][DIMM_SIZE];
-    uint8_t sdram_rows[PORT_SIZE][DIMM_SIZE];
-    uint8_t sdram_columns[PORT_SIZE][DIMM_SIZE];
-    //uint8_t module_nominal_voltage[PORT_SIZE][DIMM_SIZE];
-    uint8_t num_ranks[PORT_SIZE][DIMM_SIZE];
-    uint8_t dram_width[PORT_SIZE][DIMM_SIZE];
-    uint8_t module_memory_bus_width[PORT_SIZE][DIMM_SIZE];
-    uint8_t ftb_dividend[PORT_SIZE][DIMM_SIZE];
-    uint8_t ftb_divisor[PORT_SIZE][DIMM_SIZE];
-    uint8_t mtb_dividend[PORT_SIZE][DIMM_SIZE];
-    uint8_t mtb_divisor[PORT_SIZE][DIMM_SIZE];
-    //uint8_t tckmin[PORT_SIZE][DIMM_SIZE];
-    //uint32_t cas_latencies_supported[PORT_SIZE][DIMM_SIZE];
-    //uint8_t taamin[PORT_SIZE][DIMM_SIZE];
-    uint8_t twrmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t trcdmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t trrdmin[PORT_SIZE][DIMM_SIZE]; // DDR3 only
-    uint8_t trpmin[PORT_SIZE][DIMM_SIZE];
-    uint32_t trasmin[PORT_SIZE][DIMM_SIZE];
-    uint32_t trcmin[PORT_SIZE][DIMM_SIZE];
-    uint32_t trfcmin[PORT_SIZE][DIMM_SIZE]; // DDR3 only
-    uint8_t twtrmin[PORT_SIZE][DIMM_SIZE]; // DDR3 only
-    uint8_t trtpmin[PORT_SIZE][DIMM_SIZE];
-    uint32_t tfawmin[PORT_SIZE][DIMM_SIZE];
-
-    // DDR4 only
-    uint8_t trrdsmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t trrdlmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t tccdlmin[PORT_SIZE][DIMM_SIZE];
-    uint32_t trfc1min[PORT_SIZE][DIMM_SIZE];
-    uint32_t trfc2min[PORT_SIZE][DIMM_SIZE];
-    uint32_t trfc4min[PORT_SIZE][DIMM_SIZE];
-    uint8_t twtrsmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t twtrlmin[PORT_SIZE][DIMM_SIZE];
-
-    // Not needed for GA1 CDIMM, will need to enable check for ISDIMM.
-    //uint8_t sdram_optional_features[PORT_SIZE][DIMM_SIZE];
-    //uint8_t sdram_thermal_and_refresh_options[PORT_SIZE][DIMM_SIZE];
-    //uint8_t module_thermal_sensor[PORT_SIZE][DIMM_SIZE];
-
-    uint8_t fine_offset_tckmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t fine_offset_taamin[PORT_SIZE][DIMM_SIZE];
-    uint8_t fine_offset_trcdmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t fine_offset_trpmin[PORT_SIZE][DIMM_SIZE];
-    uint8_t fine_offset_trcmin[PORT_SIZE][DIMM_SIZE];
-
-    // ATTR_SPD_MODULE_SPECIFIC_SECTION, Located in DDR3 SPD bytes 60d - 116d
-    //uint8_t module_specific_section[PORT_SIZE][DIMM_SIZE][57];         
-    uint64_t rdimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];         
-
-    // Moved from DIMM to MBA[port][dimm] attr per DanC. see dimm_spd_attributes.xml v1.40
-    //uint32_t rdimm_rcd_ibt[PORT_SIZE][DIMM_SIZE];         
-    //uint8_t rdimm_rcd_output_timing[PORT_SIZE][DIMM_SIZE];         
-
-    // See "svpdMFGtool --inventory"
-    //uint32_t module_id_module_manufacturers_jedec_id_code[PORT_SIZE][DIMM_SIZE];
-    //uint8_t module_id_module_manufacturing_location[PORT_SIZE][DIMM_SIZE];
-    //uint32_t module_id_module_manufacturing_date[PORT_SIZE][DIMM_SIZE];
-    //uint32_t module_id_module_serial_number[PORT_SIZE][DIMM_SIZE];
-    //uint32_t cyclical_redundancy_code[PORT_SIZE][DIMM_SIZE];
-    //uint8_t module_part_number[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_18];
-    //uint32_t module_revision_code[PORT_SIZE][DIMM_SIZE];
-    //uint32_t dram_manufacturer_jedec_id_code[PORT_SIZE][DIMM_SIZE];
-
-    // See VPD parser #A keyword
-    //uint8_t bad_dq_data[PORT_SIZE][DIMM_SIZE][SPD_ATTR_SIZE_80];
-
-    uint32_t vpd_version[PORT_SIZE][DIMM_SIZE];
-};
-
-//------------------------------------------------------------------------------
-// Structure
-// @brief struct mss_eff_config_atts
-// @brief holds the effective configuration attributes
-//------------------------------------------------------------------------------
-struct mss_eff_config_atts
-{
-    uint8_t eff_dimm_ranks_configed[PORT_SIZE][DIMM_SIZE];
-    // Using SPD byte68,69:76, enabled in GA2 for full RDIMM support
-    uint64_t eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
-    uint64_t eff_lrdimm_additional_cntl_words[PORT_SIZE][DIMM_SIZE]; // LRDIMMs only
-    uint8_t eff_dimm_size[PORT_SIZE][DIMM_SIZE];
-    uint8_t eff_dimm_type;
-    uint8_t eff_custom_dimm;
-    uint8_t eff_dram_al; // Based on 2N/2T or 1N/1T enable
-    uint8_t eff_dram_asr;
-    uint8_t eff_dram_bl;
-    uint8_t eff_dram_banks;
-
-    // See mss_freq.C
-    //uint8_t eff_dram_cl;
-
-    uint8_t eff_dram_cols;
-    uint8_t eff_dram_cwl;
-    uint8_t eff_dram_density;
-    uint8_t eff_dram_dll_enable;
-    uint8_t eff_dram_dll_ppd; // Check MRW, ATTR_MRW_POWER_CONTROL_REQUESTED attr
-    uint8_t eff_dram_dll_reset; // Always reset DLL at start of IPL.
-    uint8_t eff_dram_gen;
-    uint8_t eff_dram_output_buffer;
-    uint8_t eff_dram_pasr;
-    uint8_t eff_dram_rbt;
-    uint8_t eff_dram_rows;
-    uint8_t eff_dram_srt; // Always use extended operating temp range.
-    uint8_t eff_dram_tdqs;
-    uint8_t eff_dram_tfaw;
-    uint32_t eff_dram_tfaw_u32;
-    uint8_t eff_dram_tm;
-    uint8_t eff_dram_tras;
-    uint32_t eff_dram_tras_u32;
-    uint8_t eff_dram_trc;
-    uint32_t eff_dram_trc_u32;
-    uint8_t eff_dram_trcd;
-    uint32_t eff_dram_trfc;
-    uint32_t eff_dram_trfi;
-    uint8_t eff_dram_trp;
-    uint8_t eff_dram_trrd;
-    uint8_t eff_dram_trtp;
-    uint8_t eff_dram_twtr;
-    uint8_t eff_dram_width;
-    uint8_t eff_dram_wr;
-    uint8_t eff_dram_wr_lvl_enable;
-    uint8_t eff_ibm_type[PORT_SIZE][DIMM_SIZE];
-    uint32_t eff_memcal_interval;
-    uint8_t eff_mpr_loc;
-    uint8_t eff_mpr_mode;
-
-    // AST HERE: Needs SPD DDR3 byte33[6:4], DDR4 byte6[6:4] currently hard coded to 0
-    uint8_t eff_num_dies_per_package[PORT_SIZE][DIMM_SIZE];
-
-    uint8_t eff_num_drops_per_port;
-    uint8_t eff_num_master_ranks_per_dimm[PORT_SIZE][DIMM_SIZE];
-
-    // AST HERE: Needs source data, currently hard coded to 0
-    uint8_t eff_num_packages_per_rank[PORT_SIZE][DIMM_SIZE];
-
-    uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE];
-    uint8_t eff_schmoo_mode;
-
-    uint8_t eff_schmoo_addr_mode;
-    uint8_t eff_schmoo_wr_eye_min_margin;
-    uint8_t eff_schmoo_rd_eye_min_margin;
-    uint8_t eff_schmoo_dqs_clk_min_margin;
-    uint8_t eff_schmoo_rd_gate_min_margin;
-    uint8_t eff_schmoo_addr_cmd_min_margin;
-    uint32_t eff_cen_rd_vref_schmoo[PORT_SIZE];
-    uint32_t eff_dram_wr_vref_schmoo[PORT_SIZE];
-    uint32_t eff_cen_rcv_imp_dq_dqs_schmoo[PORT_SIZE];
-    uint32_t eff_cen_drv_imp_dq_dqs_schmoo[PORT_SIZE];
-    uint8_t eff_cen_drv_imp_cntl_schmoo[PORT_SIZE];
-    uint8_t eff_cen_drv_imp_clk_schmoo[PORT_SIZE];
-    uint8_t eff_cen_drv_imp_spcke_schmoo[PORT_SIZE];
-    uint8_t eff_cen_slew_rate_dq_dqs_schmoo[PORT_SIZE];
-    uint8_t eff_cen_slew_rate_cntl_schmoo[PORT_SIZE];
-    uint8_t eff_cen_slew_rate_addr_schmoo[PORT_SIZE];
-    uint8_t eff_cen_slew_rate_clk_schmoo[PORT_SIZE];
-    uint8_t eff_cen_slew_rate_spcke_schmoo[PORT_SIZE];
-
-    uint8_t eff_schmoo_param_valid;
-    uint8_t eff_schmoo_test_valid;
-    uint8_t eff_stack_type[PORT_SIZE][DIMM_SIZE];
-    uint32_t eff_zqcal_interval;
-    uint8_t dimm_functional_vector;
-    uint8_t mss_cal_step_enable; // Always run all cal steps
-    uint32_t eff_vpd_version;
-    uint8_t eff_dram_trrdl;
-    uint8_t eff_dram_tccdl;
-    uint8_t eff_dram_twtrl;
-};
-
-//------------------------------------------------------------------------------
-// Function Prototypes
-//------------------------------------------------------------------------------
-/*
-fapi::ReturnCode mss_eff_config_get_spd_data(const fapi::Target &i_target_mba,
-                                mss_eff_config_data *p_i_mss_eff_config_data,
-                                mss_eff_config_spd_data *p_o_spd_data,
-                                mss_eff_config_atts *p_i_atts);
-
-
-fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm,
-                                mss_eff_config_spd_data *p_o_spd_data,
-                                uint8_t i_port, uint8_t i_dimm);
-
-fapi::ReturnCode mss_eff_config_verify_plug_rules(
-                                const fapi::Target  &i_target_mba,
-                                mss_eff_config_data *p_i_mss_eff_config_data,
-                                mss_eff_config_atts *p_i_atts);
-
-fapi::ReturnCode mss_eff_config_verify_spd_data(
-                                const fapi::Target &i_target_mba,
-                                mss_eff_config_atts *p_i_atts,
-                                mss_eff_config_spd_data *p_i_data);
-
-fapi::ReturnCode mss_eff_config_setup_eff_atts(const fapi::Target &i_target_mba,
-                                mss_eff_config_data *p_i_mss_eff_config_data,
-                                mss_eff_config_spd_data *p_i_data,
-                                mss_eff_config_atts *p_o_atts);
-
-
-fapi::ReturnCode mss_eff_config_write_eff_atts(const fapi::Target &i_target_mba,
-                                mss_eff_config_atts *p_i_atts);
-*/
-//------------------------------------------------------------------------------
-// extern encapsulation
-//------------------------------------------------------------------------------
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// @brief calc_timing_in_clk(): This function calculates clock timing
-//
-// @param unit32_t i_mtb_in_ps:
-// @param unit32_t i_ftb_in_fs:
-// @param unit32_t i_unit:
-// @param unit32_t i_offset:
-// @param uint32_t i_mss_freq:
-//
-// @return unit32_t l_timing_in_clk
-//------------------------------------------------------------------------------
-uint32_t calc_timing_in_clk(uint32_t i_mtb_in_ps, uint32_t i_ftb_in_fs,
-        uint32_t i_unit, uint8_t i_offset, uint32_t i_mss_freq)
-{
-    uint64_t l_timing;
-    uint32_t l_timing_in_clk;
-    uint32_t l_tCK_in_ps;
-    // perform calculations
-    l_tCK_in_ps = TWO_MHZ/i_mss_freq;
-    if ( i_offset >= 128 ) {
-       i_offset = 256 - i_offset;
-       l_timing = (i_unit * i_mtb_in_ps) - (i_offset * i_ftb_in_fs);
-    } else {
-       l_timing = (i_unit * i_mtb_in_ps) + (i_offset * i_ftb_in_fs);
-    }
-    // ceiling()
-    l_timing_in_clk = l_timing / l_tCK_in_ps;
-    // check l_timing
-    if ( (l_timing_in_clk * l_tCK_in_ps) < l_timing )
-    {
-        l_timing_in_clk += 1;
-    }
-    // DEBUG HERE:
-    //FAPI_INF("calc_timing_in_clk: l_timing_in_clk = %d, l_tCK_in_ps = %d, i_mtb_in_ps = %d, i_ftb_in_fs = %d, i_unit = %d, i_offset = %d", l_timing_in_clk, l_tCK_in_ps, i_mtb_in_ps, i_ftb_in_fs, i_unit, i_offset);
-
-    return l_timing_in_clk;
-} // end calc_timing_in_clk()
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_read_spd_data(): This function reads DIMM SPD data
-//
-// @param      fapi::Target i_target_dimm: target dimm
-// @param      mss_eff_config_spd_data *p_o_spd_data: Pointer to
-//              mss_eff configuration spd data structure
-// @param      uint8_t i_port: current mba port
-// @param      uint8_t i_dimm: current mba dimm
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config_read_spd_data(fapi::Target i_target_dimm,
-                                        mss_eff_config_spd_data *p_o_spd_data,
-                                        uint8_t i_port, uint8_t i_dimm)
-{
-    fapi::ReturnCode rc;
-    const fapi::Target& TARGET_DIMM = i_target_dimm;
-    // Grab DIMM/SPD data.
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &i_target_dimm,
-                p_o_spd_data->dram_device_type[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_DEVICE_TYPE, &i_target_dimm,
-                p_o_spd_data->sdram_device_type[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_TYPE, &i_target_dimm,
-            p_o_spd_data->module_type[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM, &i_target_dimm,
-            p_o_spd_data->custom[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS, &i_target_dimm,
-            p_o_spd_data->sdram_banks[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_DENSITY, &i_target_dimm,
-            p_o_spd_data->sdram_density[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_ROWS, &i_target_dimm,
-            p_o_spd_data->sdram_rows[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_COLUMNS, &i_target_dimm,
-            p_o_spd_data->sdram_columns[i_port][i_dimm]);
-        if(rc) break;
-
-        // See mss_volt.C
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE, &i_target_dimm,
-            //p_o_spd_data->module_nominal_voltage[i_port][i_dimm]);
-        //if(rc) break;
-
-        rc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS, &i_target_dimm,
-            p_o_spd_data->num_ranks[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_WIDTH, &i_target_dimm,
-            p_o_spd_data->dram_width[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_MEMORY_BUS_WIDTH, &i_target_dimm,
-            p_o_spd_data->module_memory_bus_width[i_port][i_dimm]);
-        if(rc) break;
-
-        // See mss_freq.C
-        //rc = FAPI_ATTR_GET(ATTR_SPD_TCKMIN, &i_target_dimm,
-            //p_o_spd_data->tckmin[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_CAS_LATENCIES_SUPPORTED, &i_target_dimm,
-            //p_o_spd_data->cas_latencies_supported[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_TAAMIN, &i_target_dimm,
-            //p_o_spd_data->taamin[i_port][i_dimm]);
-        //if(rc) break;
-        
-        if (p_o_spd_data->dram_device_type[i_port][i_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-           // DDR3 only
-           rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVIDEND, &i_target_dimm,
-               p_o_spd_data->ftb_dividend[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_FTB_DIVISOR, &i_target_dimm,
-               p_o_spd_data->ftb_divisor[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVIDEND, &i_target_dimm,
-               p_o_spd_data->mtb_dividend[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_MTB_DIVISOR, &i_target_dimm,
-               p_o_spd_data->mtb_divisor[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_TRRDMIN, &i_target_dimm,
-               p_o_spd_data->trrdmin[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_TRFCMIN, &i_target_dimm,
-               p_o_spd_data->trfcmin[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_TWTRMIN, &i_target_dimm,
-               p_o_spd_data->twtrmin[i_port][i_dimm]);
-           if(rc) break;
-           
-           rc = FAPI_ATTR_GET(ATTR_SPD_TWRMIN, &i_target_dimm,
-               p_o_spd_data->twrmin[i_port][i_dimm]);
-           if(rc) break;
-           rc = FAPI_ATTR_GET(ATTR_SPD_TRTPMIN, &i_target_dimm,
-               p_o_spd_data->trtpmin[i_port][i_dimm]);
-           if(rc) break;
-
-        } else if (p_o_spd_data->dram_device_type[i_port][i_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-           // DDR4 only
-                        uint8_t l_spd_tb_mtb_ddr4, l_spd_tb_ftb_ddr4;
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TIMEBASE_MTB_DDR4, &i_target_dimm,
-                                        l_spd_tb_mtb_ddr4);
-                        if (rc) break;
-
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TIMEBASE_FTB_DDR4, &i_target_dimm,
-                                        l_spd_tb_ftb_ddr4);
-                        if (rc) break;
-
-                        if ( (l_spd_tb_mtb_ddr4 != 0)||(l_spd_tb_ftb_ddr4 != 0) )
-                        {
-                                FAPI_ERR("Invalid DDR4 MTB/FTB Timebase received from SPD attribute on %s!", i_target_dimm.toEcmdString());
-                                FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_DDR4_SPD_TB);
-                                break;
-                        }
-            // AST HERE: !If DDR4 spec changes to include other values, this section needs to be updated!
-                        // for 1000fs = 1ps = 1000 * 1 / 1
-                        p_o_spd_data->ftb_dividend[i_port][i_dimm] = 1;
-                        p_o_spd_data->ftb_divisor[i_port][i_dimm] = 1;
-                        // for 125ps = 1000 * 1 / 8
-                        p_o_spd_data->mtb_dividend[i_port][i_dimm] = 1;
-                        p_o_spd_data->mtb_divisor[i_port][i_dimm] = 8;
-
-                        // not available in ddr4 spd, these are replacements.  need to double check
-                        // 15 ns for all speeds
-                        p_o_spd_data->twrmin[i_port][i_dimm] = 15000 / (
-                                (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) /
-                        p_o_spd_data->mtb_divisor[i_port][i_dimm]);
-
-                        // 7.5ns = 7500ps; work backwards to figure out value.  no FTB
-                        p_o_spd_data->trtpmin[i_port][i_dimm] = 7500 / (
-                                (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) /
-                        p_o_spd_data->mtb_divisor[i_port][i_dimm]);
-
-                        // 3 trfc values, 1x, 2x, 4x
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TRFC1MIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->trfc1min[i_port][i_dimm]);
-                        if(rc) break;
-
-// FW is reading out and giving the data in big endian format for some reason.
-// need to fix this...  XML is documented correctly.
-/* //                   if (p_o_spd_data->trfc1min[i_port][i_dimm] > 0xFFF) {
-                                p_o_spd_data->trfc1min[i_port][i_dimm] |= 
-                                        (p_o_spd_data->trfc1min[i_port][i_dimm] & 0xFF) << 16;
-                                p_o_spd_data->trfc1min[i_port][i_dimm] =
-                                        p_o_spd_data->trfc1min[i_port][i_dimm] >> 8;
-//                      }
-*/
-//  need to look at this more sometimes the bytes are swapped in SPD...
-                        switch(p_o_spd_data->trfc1min[i_port][i_dimm])
-                        {
-                        case 0x0005:
-                            p_o_spd_data->trfc1min[i_port][i_dimm] = 0x0500;
-                            break;
-                        case 0x2008:
-                            p_o_spd_data->trfc1min[i_port][i_dimm] = 0x0820;
-                            break;
-                        case 0xF00A:
-                            p_o_spd_data->trfc1min[i_port][i_dimm] = 0x0AF0;
-                            break;
-                        }
-
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TRFC2MIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->trfc2min[i_port][i_dimm]);
-                        if(rc) break;
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TRFC4MIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->trfc4min[i_port][i_dimm]);
-                        if(rc) break;
-
-                        // ddr4 has 's' (short; different bank group) and
-                        // 'l' (long; same bank group) values
-                        // tRRD needs to be used by Yuen's mba initfile...
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TRRDSMIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->trrdsmin[i_port][i_dimm]);
-                        if(rc) break;
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TRRDLMIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->trrdlmin[i_port][i_dimm]);
-                        if(rc) break;
-
-                        // tccdl
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TCCDLMIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->tccdlmin[i_port][i_dimm]);
-                        if(rc) break;
-
-                        // should be constant based on MTB and FTB after calculations
-                        // where is this used??
-/*                              SPD attributes not available yet
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TWTRSMIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->twtrsmin[i_port][i_dimm]);        // 2.5ns
-                        if(rc) break;
-                        rc = FAPI_ATTR_GET(ATTR_SPD_TWTRLMIN_DDR4, &i_target_dimm,
-                                p_o_spd_data->twtrlmin[i_port][i_dimm]);        // 7.5ns
-                        if(rc) break;
-*/
-                        p_o_spd_data->twtrsmin[i_port][i_dimm] = 2500 / (       // 2.5 ns
-                (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) /
-                                            p_o_spd_data->mtb_divisor[i_port][i_dimm]);
-                        p_o_spd_data->twtrlmin[i_port][i_dimm] = 7500 / (       // 7.5 ns
-                (p_o_spd_data->mtb_dividend[i_port][i_dimm] * 1000) /
-                                            p_o_spd_data->mtb_divisor[i_port][i_dimm]);
-        } else {
-           FAPI_ERR("Incompatable SPD DRAM generation on %s!", i_target_dimm.toEcmdString());
-           FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_SPD_DRAM_GEN);
-           return rc;
-        }
-
-        // Common for DDR3 and DDR4
-        rc = FAPI_ATTR_GET(ATTR_SPD_TRCDMIN, &i_target_dimm,
-            p_o_spd_data->trcdmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_TRPMIN, &i_target_dimm,
-            p_o_spd_data->trpmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_TRASMIN, &i_target_dimm,
-            p_o_spd_data->trasmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_TRCMIN, &i_target_dimm,
-            p_o_spd_data->trcmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_TFAWMIN, &i_target_dimm,
-            p_o_spd_data->tfawmin[i_port][i_dimm]);
-        if(rc) break;
-
-        // Not needed for GA1 CDIMM, will need to enable check for ISDIMM.
-        //rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_OPTIONAL_FEATURES, &i_target_dimm,
-            //p_o_spd_data->sdram_optional_features[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_THERMAL_AND_REFRESH_OPTIONS,
-            //&i_target_dimm,
-            //p_o_spd_data->sdram_thermal_and_refresh_options[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_THERMAL_SENSOR, &i_target_dimm,
-            //p_o_spd_data->module_thermal_sensor[i_port][i_dimm]);
-        //if(rc) break;
-
-        rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TCKMIN, &i_target_dimm,
-            p_o_spd_data->fine_offset_tckmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TAAMIN, &i_target_dimm,
-            p_o_spd_data->fine_offset_taamin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TRCDMIN, &i_target_dimm,
-            p_o_spd_data->fine_offset_trcdmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TRPMIN, &i_target_dimm,
-            p_o_spd_data->fine_offset_trpmin[i_port][i_dimm]);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_SPD_FINE_OFFSET_TRCMIN, &i_target_dimm,
-            p_o_spd_data->fine_offset_trcmin[i_port][i_dimm]);
-        if(rc) break;
-
-
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_SPECIFIC_SECTION,                    // LRDIMM needed.
-            //&i_target_dimm,
-            //p_o_spd_data->module_specific_section[i_port][i_dimm]);
-        //if(rc) break;
-
-
-        rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_RCD_CNTL_WORD_0_15,                    // Needed for RDIMM.
-            &i_target_dimm,
-            p_o_spd_data->rdimm_rcd_cntl_word_0_15[i_port][i_dimm]);
-        if(rc) break;
-
-        // Moved from DIMM to MBA[port][dimm] attr per DanC. see dimm_spd_attributes.xml v1.40
-        //rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_RCD_IBT,                               // Needed for RDIMM.
-        //    &i_target_dimm,
-        //    p_o_spd_data->rdimm_rcd_ibt[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,                     // Needed for RDIMM.
-        //    &i_target_dimm,
-        //    p_o_spd_data->rdimm_rcd_output_timing[i_port][i_dimm]);
-        //if(rc) break;
-
-
-        // See "svpdMFGtool --inventory"
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURERS_
-            //JEDEC_ID_CODE,
-            //&i_target_dimm,
-            //p_o_spd_data->
-        //module_id_module_manufacturers_jedec_id_code[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_LOCATION,
-            //&i_target_dimm,
-            //p_o_spd_data->module_id_module_manufacturing_location
-            //[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_MANUFACTURING_DATE,
-            //&i_target_dimm,
-            //p_o_spd_data->module_id_module_manufacturing_date
-            //[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_ID_MODULE_SERIAL_NUMBER,
-            //&i_target_dimm,
-            //p_o_spd_data->module_id_module_serial_number[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_CYCLICAL_REDUNDANCY_CODE,
-            //&i_target_dimm,
-            //p_o_spd_data->cyclical_redundancy_code[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_PART_NUMBER,
-            //&i_target_dimm,
-            //p_o_spd_data->module_part_number[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_REVISION_CODE,
-            //&i_target_dimm,
-            //p_o_spd_data->module_revision_code[i_port][i_dimm]);
-        //if(rc) break;
-        //rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_MANUFACTURER_JEDEC_ID_CODE,
-            //&i_target_dimm,
-            //p_o_spd_data->dram_manufacturer_jedec_id_code[i_port][i_dimm]);
-        //if(rc) break;
-
-        // See VPD parser #A keyword
-        //rc = FAPI_ATTR_GET(ATTR_SPD_BAD_DQ_DATA, &i_target_dimm,
-            //p_o_spd_data->bad_dq_data[i_port][i_dimm]);
-        //if(rc) break;
-
-        rc = FAPI_ATTR_GET(ATTR_VPD_VERSION, &i_target_dimm,
-                           p_o_spd_data->vpd_version[i_port][i_dimm]);
-        if(rc) break;
-
-    } while(0);
-
-    return rc;
-} // end of mss_eff_config_read_spd_data()
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_get_spd_data(): This function sets gathers the
-//              DIMM info then uses mss_eff_config_read_spd_data() as a
-//              helper function to read the spd data
-//
-// @param const fapi::Target &i_target_mba: the fapi target
-// @param       mss_eff_config_data *p_i_mss_eff_config_data: Pointer to
-//              mss_eff_config_data variable structure
-// @param const mss_eff_config_spd_data *p_o_spd_data: Pointer to mss_eff
-//              configuration spd data structure
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config_get_spd_data(
-                                const fapi::Target &i_target_mba,
-                                mss_eff_config_data *p_i_mss_eff_config_data,
-                                mss_eff_config_spd_data *p_o_spd_data,
-                                mss_eff_config_atts *p_i_atts)
-{
-    fapi::ReturnCode rc;
-    std::vector<fapi::Target> l_target_dimm_array;
-    uint8_t l_cur_mba_port = 0;
-    uint8_t l_cur_mba_dimm = 0;
-    // Grab all DIMM/SPD data.
-    do
-    {
- //------------------------------------------------------------------------------
-// initialize vpd_version
-      for(l_cur_mba_port=0; l_cur_mba_port < PORT_SIZE ; l_cur_mba_port++)
-        for(l_cur_mba_dimm=0; l_cur_mba_dimm < DIMM_SIZE ; l_cur_mba_dimm++)
-          p_o_spd_data->vpd_version[l_cur_mba_port][l_cur_mba_dimm]=0xFFFFFFFF;
-//------------------------------------------------------------------------------
-
-       rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array);
-        if(rc)
-        {
-            FAPI_ERR("Error retrieving assodiated dimms");
-            break;
-        }
-//------------------------------------------------------------------------------
-        // call mss_eff_config_read_spd_data()
-        for (uint8_t l_dimm_index = 0; l_dimm_index <
-                l_target_dimm_array.size(); l_dimm_index += 1)
-        {
-            rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[l_dimm_index],
-                    l_cur_mba_port);
-            if(rc)
-            {
-                FAPI_ERR("Error retrieving ATTR_MBA_PORT");
-                break;
-            }
-//------------------------------------------------------------------------------
-            rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[l_dimm_index
-                    ], l_cur_mba_dimm);
-            if(rc)
-            {
-                FAPI_ERR("Error retrieving ATTR_MBA_DIMM");
-                break;
-            }
-//------------------------------------------------------------------------------
-            p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array
-                [l_cur_mba_port][l_cur_mba_dimm] = MSS_EFF_VALID;
-            rc = FAPI_ATTR_GET(ATTR_FUNCTIONAL,
-                    &l_target_dimm_array[l_dimm_index],
-                    p_i_mss_eff_config_data->dimm_functional);
-            if(rc)
-            {
-                FAPI_ERR("Error retrieving functional fapi attribute");
-                break;
-            }
-//------------------------------------------------------------------------------
-            (p_i_mss_eff_config_data->dimm_functional ==
-             fapi::ENUM_ATTR_FUNCTIONAL_FUNCTIONAL)
-                ? p_i_mss_eff_config_data->dimm_functional=1
-                : p_i_mss_eff_config_data->dimm_functional=0;
-            p_i_atts->dimm_functional_vector |=
-                p_i_mss_eff_config_data->dimm_functional
-                << ((4*(1-(l_cur_mba_port)))+(4-(l_cur_mba_dimm))-1);
-
-            rc = mss_eff_config_read_spd_data(l_target_dimm_array[l_dimm_index],
-                    p_o_spd_data, l_cur_mba_port, l_cur_mba_dimm);
-            if(rc)
-            {
-                FAPI_ERR("Error reading spd data from caller");
-                break;
-            }
-        }
-    } while(0);
-
-    return rc;
-} // end of mss_eff_config_get_spd_data()
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_verify_plug_rules(): This function verifies DIMM
-//              plug rules based on which dimms are present
-//
-// @param       mss_eff_config_data *p_i_mss_eff_config_data: Pointer to
-//              mss_eff_config_data variable structure
-// @param const fapi::Target &i_target_mba: the fapi target
-// @param       mss_eff_config_data *p_i_mss_eff_config_data: Pointer to
-//              mss_eff_config_data variable structure
-// @param       mss_eff_config_atts *p_i_atts: Pointer to mss_eff
-//              configuration attributes structure
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config_verify_plug_rules(
-                                const fapi::Target &i_target_mba,
-                                mss_eff_config_data *p_i_mss_eff_config_data,
-                                mss_eff_config_atts *p_i_atts)
-{
-    fapi::ReturnCode rc;
-    const fapi::Target& TARGET_MBA = i_target_mba;
-    uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_0_0 = 
-             p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[0][0];
-    uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_0_1 = 
-             p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[0][1];
-    uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_1_0 = 
-             p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[1][0];
-    uint8_t& CUR_DIMM_SPD_VALID_U8ARRAY_1_1 = 
-             p_i_mss_eff_config_data->cur_dimm_spd_valid_u8array[1][1];
-
-    // Identify/Verify DIMM plug rule
-    if (
-            (p_i_mss_eff_config_data->
-             cur_dimm_spd_valid_u8array[0][0] == MSS_EFF_EMPTY)
-            &&
-            (
-                (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_VALID)
-                ||
-                (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[1][0] == MSS_EFF_VALID)
-                ||
-                (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[1][1] == MSS_EFF_VALID)
-            )
-       )
-    {
-        FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString());
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MISMATCH_EMPTY);
-        return rc;
-    }
-    if ( (
-            ((p_i_mss_eff_config_data->
-              cur_dimm_spd_valid_u8array[0][0] == MSS_EFF_VALID)
-             && (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[1][0] == MSS_EFF_EMPTY))
-            ||
-            ((p_i_mss_eff_config_data->
-              cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_VALID)
-             && (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[1][1] == MSS_EFF_EMPTY))
-       ) && (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) )
-    {
-        FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString());
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MISMATCH_SIDE);
-        return rc;
-    }
-    if ( (
-            (p_i_mss_eff_config_data->
-              cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_VALID)
-             || (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[1][0] == MSS_EFF_VALID)
-             || (p_i_mss_eff_config_data->
-                 cur_dimm_spd_valid_u8array[1][1] == MSS_EFF_VALID)
-       ) && (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_TRUE) )
-    {
-        FAPI_ERR("Plug rule violation on %s!", i_target_mba.toEcmdString());
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MISMATCH_TOP);
-        return rc;
-    }
-    if ((p_i_mss_eff_config_data->
-                cur_dimm_spd_valid_u8array[0][0] == MSS_EFF_VALID)
-            && (p_i_mss_eff_config_data->
-                cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_VALID))
-    {
-        p_i_atts->eff_num_drops_per_port
-            = fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL;
-    }
-    else if ((p_i_mss_eff_config_data->
-                cur_dimm_spd_valid_u8array[0][0] == MSS_EFF_VALID)
-            && (p_i_mss_eff_config_data->
-                cur_dimm_spd_valid_u8array[0][1] == MSS_EFF_EMPTY))
-    {
-        p_i_atts->eff_num_drops_per_port
-            = fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE;
-    }
-    else
-    {
-        p_i_atts->eff_num_drops_per_port
-            = fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_EMPTY;
-    }
-    // end Indetify/Verify DIMM plug rule
-
-    return rc;
-} // end of mss_eff_config_verify_plug_rules()
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_verify_spd_data(): This function verifies DIMM
-//              SPD data
-//
-// @param const fapi::Target &i_target_mba: the fapi target
-// @param       mss_eff_config_atts *p_i_atts: Pointer to mss_eff
-//              configuration attributes structure
-// @param       mss_eff_config_spd_data *p_i_data: Pointer to mss_eff
-//              configuration spd data structure
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config_verify_spd_data(
-                                    const fapi::Target &i_target_mba,
-                                    mss_eff_config_atts *p_i_atts,
-                                    mss_eff_config_spd_data *p_i_data)
-{
-    fapi::ReturnCode rc;
-    const fapi::Target& TARGET_MBA = i_target_mba;
-
-    // Start Identify/Verify/Assigning values to attributes
-    // Identify/Verify DIMM compatability
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->dram_device_type[0][0]
-             != p_i_data->dram_device_type[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                        (p_i_data->dram_device_type[0][1]
-                         != p_i_data->dram_device_type[1][1])
-                        ||
-                        (p_i_data->dram_device_type[0][0]
-                         != p_i_data->dram_device_type[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DRAM generation on %s!",
-                i_target_mba.toEcmdString());
-        uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-        uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-        uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-        uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->module_type[0][0]
-             != p_i_data->module_type[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->module_type[0][1]
-                     != p_i_data->module_type[1][1])
-                    ||
-                    (p_i_data->module_type[0][0]
-                     != p_i_data->module_type[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DIMM type on %s!", i_target_mba.toEcmdString());
-        uint8_t& MODULE_TYPE_0_0 = p_i_data->module_type[0][0];
-        uint8_t& MODULE_TYPE_0_1 = p_i_data->module_type[0][1];
-        uint8_t& MODULE_TYPE_1_0 = p_i_data->module_type[1][0];
-        uint8_t& MODULE_TYPE_1_1 = p_i_data->module_type[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_TYPE);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->num_ranks[0][0]
-             != p_i_data->num_ranks[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->num_ranks[0][1]
-                     != p_i_data->num_ranks[1][1])
-                    ||
-                    (p_i_data->num_ranks[0][0]
-                     != p_i_data->num_ranks[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DIMM ranks on %s!", i_target_mba.toEcmdString());
-        uint8_t& NUM_RANKS_0_0 = p_i_data->num_ranks[0][0];
-        uint8_t& NUM_RANKS_0_1 = p_i_data->num_ranks[0][1];
-        uint8_t& NUM_RANKS_1_0 = p_i_data->num_ranks[1][0];
-        uint8_t& NUM_RANKS_1_1 = p_i_data->num_ranks[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_RANKS);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->sdram_banks[0][0]
-             != p_i_data->sdram_banks[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->sdram_banks[0][1]
-                     != p_i_data->sdram_banks[1][1])
-                    ||
-                    (p_i_data->sdram_banks[0][0]
-                     != p_i_data->sdram_banks[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DIMM banks on %s!", i_target_mba.toEcmdString());
-                uint8_t& SDRAM_BANKS_0_0 = p_i_data->sdram_banks[0][0];
-                uint8_t& SDRAM_BANKS_0_1 = p_i_data->sdram_banks[0][1];
-                uint8_t& SDRAM_BANKS_1_0 = p_i_data->sdram_banks[1][0];
-                uint8_t& SDRAM_BANKS_1_1 = p_i_data->sdram_banks[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_BANKS);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->sdram_rows[0][0]
-             != p_i_data->sdram_rows[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->sdram_rows[0][1]
-                     != p_i_data->sdram_rows[1][1])
-                    ||
-                    (p_i_data->sdram_rows[0][0]
-                     != p_i_data->sdram_rows[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DIMM rows on %s!", i_target_mba.toEcmdString());
-                uint8_t& SDRAM_ROWS_0_0 = p_i_data->sdram_rows[0][0];
-                uint8_t& SDRAM_ROWS_0_1 = p_i_data->sdram_rows[0][1];
-                uint8_t& SDRAM_ROWS_1_0 = p_i_data->sdram_rows[1][0];
-                uint8_t& SDRAM_ROWS_1_1 = p_i_data->sdram_rows[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_ROWS);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->sdram_columns[0][0]
-             != p_i_data->sdram_columns[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->sdram_columns[0][1]
-                     != p_i_data->sdram_columns[1][1])
-                    ||
-                    (p_i_data->sdram_columns[0][0]
-                     != p_i_data->sdram_columns[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DIMM cols on %s!", i_target_mba.toEcmdString());
-                uint8_t& SDRAM_COLS_0_0 = p_i_data->sdram_columns[0][0];
-                uint8_t& SDRAM_COLS_0_1 = p_i_data->sdram_columns[0][1];
-                uint8_t& SDRAM_COLS_1_0 = p_i_data->sdram_columns[1][0];
-                uint8_t& SDRAM_COLS_1_1 = p_i_data->sdram_columns[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DIMM_COLUMNS);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->module_memory_bus_width[0][0]
-             != p_i_data->module_memory_bus_width[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->module_memory_bus_width[0][1]
-                     != p_i_data->module_memory_bus_width[1][1])
-                    ||
-                    (p_i_data->module_memory_bus_width[0][0]
-                     != p_i_data->module_memory_bus_width[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DRAM primary bus width on %s!",
-                i_target_mba.toEcmdString());
-                uint8_t& BUS_WIDTH_0_0 = p_i_data->module_memory_bus_width[0][0];
-                uint8_t& BUS_WIDTH_0_1 = p_i_data->module_memory_bus_width[0][1];
-                uint8_t& BUS_WIDTH_1_0 = p_i_data->module_memory_bus_width[1][0];
-                uint8_t& BUS_WIDTH_1_1 = p_i_data->module_memory_bus_width[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_BUS_WIDTH);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    // ATTR_SPD_MODULE_MEMORY_BUS_WIDTH, SPD byte8[4:3], only 64bit with ECC extension is allowed
-    if ( p_i_data->module_memory_bus_width[0][0] != 
-         fapi::ENUM_ATTR_SPD_MODULE_MEMORY_BUS_WIDTH_WE64 )
-    {
-        FAPI_ERR("Unsupported DRAM bus width on %s!",
-            i_target_mba.toEcmdString());
-            uint8_t& MODULE_MEMORY_BUS_WIDTH = p_i_data->module_memory_bus_width[0][0];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_UNSUPPORTED_MODULE_MEMORY_BUS_WIDTH);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    if (
-            (p_i_data->dram_width[0][0]
-             != p_i_data->dram_width[1][0])
-            ||
-            (
-                (p_i_atts->eff_num_drops_per_port
-                 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)
-                &&
-                (
-                    (p_i_data->dram_width[0][1]
-                     != p_i_data->dram_width[1][1])
-                    ||
-                    (p_i_data->dram_width[0][0]
-                     != p_i_data->dram_width[0][1])
-                )
-            )
-        )
-    {
-        FAPI_ERR("Incompatable DRAM width on %s!", i_target_mba.toEcmdString());
-                uint8_t& DRAM_WIDTH_0_0 = p_i_data->dram_width[0][0];
-                uint8_t& DRAM_WIDTH_0_1 = p_i_data->dram_width[0][1];
-                uint8_t& DRAM_WIDTH_1_0 = p_i_data->dram_width[1][0];
-                uint8_t& DRAM_WIDTH_1_1 = p_i_data->dram_width[1][1];
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_WIDTH);
-        return rc;
-    }
-//------------------------------------------------------------------------------
-    return rc;
-} // end of mss_eff_config_verify_spd_data()
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_setup_eff_atts(): This function sets up the
-//             effective configuration attributes and does some extra
-//             verification of SPD data
-//
-// @param const fapi::Target &i_target_mba: the fapi target
-// @param       mss_eff_config_data *p_i_mss_eff_config_data: Pointer to
-//              mss_eff_config_data variable structure
-// @param       mss_eff_config_spd_data *p_i_data: Pointer to mss_eff
-//              configuration spd data structure
-// @param       mss_eff_config_atts *p_o_atts: Pointer to mss_eff
-//              configuration attributes structure
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config_setup_eff_atts(
-                                const fapi::Target &i_target_mba,
-                                mss_eff_config_data *p_i_mss_eff_config_data,
-                                mss_eff_config_spd_data *p_i_data,
-                                mss_eff_config_atts *p_o_atts)
-{
-    fapi::ReturnCode rc;
-    const fapi::Target& TARGET_MBA = i_target_mba;
-
-    uint8_t mss_dram_2n_mode_enable;
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target_mba, mss_dram_2n_mode_enable);
-    if(rc) return rc;
-    // set select atts members to non-zero
-    if ( mss_dram_2n_mode_enable == fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE ) {
-       p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_2; // Always use AL = CL - 2 for 2N/2T mode
-    } else {
-       p_o_atts->eff_dram_al = fapi::ENUM_ATTR_EFF_DRAM_AL_CL_MINUS_1; // Always use AL = CL - 1 for 1N/1T mode
-    }
-
-    // Transfer powerdown request from system attr to DRAM attr
-    uint8_t mss_power_control_requested;
-    rc = FAPI_ATTR_GET(ATTR_MRW_POWER_CONTROL_REQUESTED, NULL, mss_power_control_requested); 
-    if(rc) return rc;
-    if ( mss_power_control_requested == fapi::ENUM_ATTR_MRW_POWER_CONTROL_REQUESTED_FASTEXIT) {
-       p_o_atts->eff_dram_dll_ppd = fapi::ENUM_ATTR_EFF_DRAM_DLL_PPD_FASTEXIT;
-    } else {
-       p_o_atts->eff_dram_dll_ppd = fapi::ENUM_ATTR_EFF_DRAM_DLL_PPD_SLOWEXIT; // if "OFF" default to SLOWEXIT, FASTEXIT settings in mba_def.initfile are causing fails.  Workaround to use SLOWEXIT.
-    }
-
-    p_o_atts->eff_dram_dll_reset = fapi::ENUM_ATTR_EFF_DRAM_DLL_RESET_YES; // Always reset DLL at start of IPL.
-    p_o_atts->eff_dram_srt = fapi::ENUM_ATTR_EFF_DRAM_SRT_EXTEND; // Always use extended operating temp range.
-    p_o_atts->mss_cal_step_enable = 0xFF; // Always run all cal steps
-    // array init
-    for(int i = 0; i < PORT_SIZE; i++)
-    {
-        for(int j = 0; j < DIMM_SIZE; j++)
-        {
-            // i <-> PORT_SIZE, j <-> DIMM_SIZE
-            p_o_atts->eff_stack_type[i][j] = 0;
-            p_o_atts->eff_ibm_type[i][j] = 0;
-        }
-    }
-
-    // Assigning values to attributes
-//------------------------------------------------------------------------------
-    p_o_atts->eff_schmoo_wr_eye_min_margin = 70;
-    p_o_atts->eff_schmoo_rd_eye_min_margin = 70;
-    p_o_atts->eff_schmoo_dqs_clk_min_margin = 140;
-    p_o_atts->eff_schmoo_rd_gate_min_margin = 100;
-    p_o_atts->eff_schmoo_addr_cmd_min_margin = 140;
-//------------------------------------------------------------------------------
-    switch(p_i_data->dram_device_type[0][0])
-    {
-        case fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3:
-            p_o_atts->eff_dram_gen = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3;
-            break;
-        case fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4:
-            p_o_atts->eff_dram_gen = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4;
-            break;
-        default:
-                        uint8_t& DRAM_DEVICE_TYPE=p_i_data->dram_device_type[0][0];
-            FAPI_ERR("Unknown DRAM type on %s!", i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_DEVICE_ERROR);
-            return rc;
-    }
-//------------------------------------------------------------------------------
-    switch(p_i_data->module_type[0][0])
-    {
-        // Removed CDIMM as a valid EFF_DIMM_TYPE.
-        //case fapi::ENUM_ATTR_SPD_MODULE_TYPE_CDIMM:
-        //    p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM;
-        //    FAPI_INF("WARNING: ATTR_SPD_MODULE_TYPE_CDIMM is obsolete.  Check your VPD for correct definition on %s!", i_target_mba.toEcmdString());
-        //    break;
-        case fapi::ENUM_ATTR_SPD_MODULE_TYPE_RDIMM:
-            p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM;
-            break;
-        case fapi::ENUM_ATTR_SPD_MODULE_TYPE_UDIMM:
-            // Removed CDIMM as a valid EFF_DIMM_TYPE.
-            //if(p_i_data->custom[0][0]) {
-            //  p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM;
-            //}
-            //else {
-              p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM;
-            //}
-            break;
-        case fapi::ENUM_ATTR_SPD_MODULE_TYPE_LRDIMM:
-            p_o_atts->eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM;
-            break;
-        default:
-            FAPI_ERR("Unknown DIMM type on %s!", i_target_mba.toEcmdString());
-            uint8_t& MOD_TYPE = p_i_data->module_type[0][0];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MOD_TYPE_ERROR);
-            return rc;
-    }
-//------------------------------------------------------------------------------
-    // Moved from DIMM to MBA[port][dimm] attr per DanC. see dimm_spd_attributes.xml v1.40
-    uint32_t l_rdimm_rcd_ibt[PORT_SIZE][DIMM_SIZE];
-    uint8_t l_rdimm_rcd_output_timing[PORT_SIZE][DIMM_SIZE];
-    if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) {
-       rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_RCD_IBT, &i_target_mba, l_rdimm_rcd_ibt);
-       if (rc) return rc;
-       rc = FAPI_ATTR_GET(ATTR_VPD_DIMM_RCD_OUTPUT_TIMING, &i_target_mba, l_rdimm_rcd_output_timing);
-       if (rc) return rc;
-    }
-//------------------------------------------------------------------------------
-    if(p_i_data->custom[0][0] == fapi::ENUM_ATTR_SPD_CUSTOM_YES) {
-      p_o_atts->eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES;
-    }
-    else {
-      p_o_atts->eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO;
-    }
-//------------------------------------------------------------------------------
-    switch(p_i_data->sdram_banks[0][0])
-    {
-        case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B4:
-            p_o_atts->eff_dram_banks = 4;                       // DDR4 only
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8:
-            p_o_atts->eff_dram_banks = 8;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B16:
-            p_o_atts->eff_dram_banks = 16;
-            break;
-        case  fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B32:
-            p_o_atts->eff_dram_banks = 32;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B64:
-            p_o_atts->eff_dram_banks = 64;
-            break;
-        default:
-            FAPI_ERR("Unknown DRAM banks on %s!", i_target_mba.toEcmdString());
-                        uint8_t& SDRAM_BANKS= p_i_data->sdram_banks[0][0];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_SDRAM_BANK_ERROR);
-            return rc;
-    }
-//------------------------------------------------------------------------------
-    switch (p_i_data->sdram_rows[0][0])
-    {
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R12:
-            p_o_atts->eff_dram_rows = 12;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R13:
-            p_o_atts->eff_dram_rows = 13;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R14:
-            p_o_atts->eff_dram_rows = 14;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R15:
-            p_o_atts->eff_dram_rows = 15;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R16:
-            p_o_atts->eff_dram_rows = 16;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R17:
-            p_o_atts->eff_dram_rows = 17;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_ROWS_R18:
-            p_o_atts->eff_dram_rows = 18;
-            break;
-        default:
-            FAPI_ERR("Unknown DRAM rows on %s!", i_target_mba.toEcmdString());
-                        uint8_t& SDRAM_ROWS= p_i_data->sdram_rows[0][0];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_SDRAM_ROWS_ERROR);
-            return rc;
-    }
-//------------------------------------------------------------------------------
-    switch (p_i_data->sdram_columns[0][0])
-    {
-        case fapi::ENUM_ATTR_SPD_SDRAM_COLUMNS_C9:
-            p_o_atts->eff_dram_cols = 9;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_COLUMNS_C10:
-            p_o_atts->eff_dram_cols = 10;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_COLUMNS_C11:
-            p_o_atts->eff_dram_cols = 11;
-            break;
-        case fapi::ENUM_ATTR_SPD_SDRAM_COLUMNS_C12:
-            p_o_atts->eff_dram_cols = 12;
-            break;
-        default:
-            FAPI_ERR("Unknown DRAM cols on %s!", i_target_mba.toEcmdString());
-                        uint8_t& SDRAM_COLS= p_i_data->sdram_columns[0][0];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_SDRAM_COLS_ERROR);
-            return rc;
-    }
-//------------------------------------------------------------------------------
-         uint8_t& DRAM_WIDTH= p_i_data->dram_width[0][0];
-    if (p_i_data->dram_width[0][0]
-            == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W4)
-    {
-        p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4;
-        p_o_atts->eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE;
-    }
-    else if (p_i_data->dram_width[0][0]
-            == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W8)
-    {
-        p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8;
-        // NOTE: TDQS enable MR1(A11) is only avaliable for X8 in DDR3
-        // TDQS disabled for X8 DDR3 CDIMM, enable for ISDIMM
-        if ( p_o_atts->eff_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO ) {
-           p_o_atts->eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_ENABLE;
-        } else {
-           p_o_atts->eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE;
-        }
-    }
-    else if (p_i_data->dram_width[0][0]
-            == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W16)
-    {
-        p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X16;
-        FAPI_ERR("Unsupported DRAM width x16 on %s!",
-                i_target_mba.toEcmdString());
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_WIDTH_16_ERROR);
-        return rc;
-    }
-    else if (p_i_data->dram_width[0][0]
-            == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W32)
-    {
-        p_o_atts->eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X32;
-        FAPI_ERR("Unsupported DRAM width x32 on %s!",
-                i_target_mba.toEcmdString());
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_WIDTH_32_ERROR);
-        return rc;
-
-    }
-    else
-    {
-         FAPI_ERR("Unknown DRAM width on %s!", i_target_mba.toEcmdString());
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_WIDTH_ERROR);
-         return rc;
-    }
-//------------------------------------------------------------------------------
-    p_o_atts->eff_dram_density = 16;
-
-    uint8_t allow_port_size = 1;
-    if (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) {
-       allow_port_size = PORT_SIZE;
-    }
-    for (int l_cur_mba_port = 0; l_cur_mba_port < allow_port_size; l_cur_mba_port += 1)
-    {
-        for (int l_cur_mba_dimm = 0; l_cur_mba_dimm <
-                p_o_atts->eff_num_drops_per_port; l_cur_mba_dimm += 1)
-        {
-            if (p_i_data->sdram_density[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D16GB)
-            {
-               p_i_mss_eff_config_data->cur_dram_density = 16;
-            }
-            else if (p_i_data->sdram_density[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D8GB)
-            {
-               p_i_mss_eff_config_data->cur_dram_density = 8;
-            }
-            else if (p_i_data->sdram_density[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D4GB)
-            {
-               p_i_mss_eff_config_data->cur_dram_density = 4;
-            }
-            else if (p_i_data->sdram_density[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D2GB)
-            {
-               p_i_mss_eff_config_data->cur_dram_density = 2;
-            }
-            else if (p_i_data->sdram_density[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_SDRAM_DENSITY_D1GB)
-            {
-               p_i_mss_eff_config_data->cur_dram_density = 1;
-            }
-            else
-            {
-                           uint8_t& SDRAM_DENSITY = p_i_data->sdram_density[l_cur_mba_port][l_cur_mba_dimm];
-               p_i_mss_eff_config_data->cur_dram_density = 1;
-               if (p_i_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE) {
-                  FAPI_ERR("Unsupported DRAM density on %s!",
-                          i_target_mba.toEcmdString());
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DRAM_DENSITY_ERR);
-                  return rc;
-               }
-            }
-//------------------------------------------------------------------------------
-            if (p_o_atts->eff_dram_density >
-                    p_i_mss_eff_config_data->cur_dram_density)
-            {
-               p_o_atts->eff_dram_density =
-                   p_i_mss_eff_config_data->cur_dram_density;
-            }
-//------------------------------------------------------------------------------
-            // Identify/Verify DIMM voltage compatability
-            // See mss_volt.C
-//------------------------------------------------------------------------------
-            // Identify/Assign minimum timing
-            p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                [l_cur_mba_dimm] =
-                (p_i_data->mtb_dividend[l_cur_mba_port]
-                 [l_cur_mba_dimm] * 1000)
-                /
-                p_i_data->mtb_divisor[l_cur_mba_port]
-                [l_cur_mba_dimm];
-//------------------------------------------------------------------------------
-            p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                [l_cur_mba_dimm] =
-                (p_i_data->ftb_dividend[l_cur_mba_port]
-                 [l_cur_mba_dimm] * 1000)
-                /
-                p_i_data->ftb_divisor[l_cur_mba_port]
-                [l_cur_mba_dimm];
-//------------------------------------------------------------------------------
-            // Calculate CL
-            // See mss_freq.C
-            // call calc_timing_in_clk()
-            p_i_mss_eff_config_data->dram_wr = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->twrmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-
-                                            );
-            if (p_i_mss_eff_config_data->dram_wr > p_o_atts->eff_dram_wr)
-            {
-                p_o_atts->eff_dram_wr = p_i_mss_eff_config_data->dram_wr;
-            }
-//------------------------------------------------------------------------------
-            // call calc_timing_in_clk()
-            p_i_mss_eff_config_data->dram_trcd = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trcdmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->fine_offset_trcdmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_trcd >
-                    p_o_atts->eff_dram_trcd)
-            {
-                p_o_atts->eff_dram_trcd =
-                    p_i_mss_eff_config_data->dram_trcd;
-            }
-//------------------------------------------------------------------------------
-         if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-            // DDR3
-            p_i_mss_eff_config_data->dram_trrd = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trrdmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_trrd >
-                    p_o_atts->eff_dram_trrd)
-            {
-                p_o_atts->eff_dram_trrd =
-                    p_i_mss_eff_config_data->dram_trrd;
-            }
-         } else if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { 
-            // DDR4
-            FAPI_INF("DDR4 Check: spd tRRDs=0x%x, tRRDl=0x%x, mtb=%i, ftb=%i, width=%i",
-                    p_i_data->trrdsmin[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_data->trrdlmin[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                    p_o_atts->eff_dram_width);
-                    const uint8_t min_delay_clocks = 4;
-                    uint32_t max_delay;             // in ps
-                    // bool is_2K_page = 0;    
-
-                    // get the spd min trrd in clocks
-                    p_i_mss_eff_config_data->dram_trrd = calc_timing_in_clk
-                    (
-                       p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                       p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                       p_i_data->trrdsmin[l_cur_mba_port][l_cur_mba_dimm],
-                       0,  // need to put in the trrdsmin_ftb here...
-                       p_i_mss_eff_config_data->mss_freq
-                    );
-
-                    // trrdsmin from SPD is absolute min of DIMM.
-                    // need to know page size, then use 6ns for (2k page) otherwise 5ns
-
-                    FAPI_INF("DDR4 Check:  p_i_tRRD_s(nCK) = %i",  p_i_mss_eff_config_data->dram_trrd);
-                    FAPI_INF("Attribute p_o_eff_dram_trrd = %i",  p_o_atts->eff_dram_trrd);
-                    // need a table here for other speeds/page sizes
-
-                    // trrd_s = 2K page @ 1600, max(4nCK,6ns)       since min nCK=1.25ns, const 6ns
-                    // 1/2 or 1K   page @ 1600, max(4nCK, 5ns)
-
-                    // 1600 1866 2133 2400 (data rate)
-                    // 6,   5.3, 5.3, 5.3 ns        for 2k page size (x16)
-                    // 5,   4.2, 3.7, 3.3 ns        for 0.5k or 1k page size (x8)
-                    // !! NOTE !!  NOT supporting 2k page size (with check for width above should cause error out).
-
-                    if (p_i_mss_eff_config_data->mss_freq < 1733)           // 1600
-                    {
-                       max_delay = 5000;       // in ps
-                    }
-                    else if (p_i_mss_eff_config_data->mss_freq < 2000)      // 1866
-                    {
-                       max_delay = 4200;       // in ps
-                    }
-                    else if (p_i_mss_eff_config_data->mss_freq < 2267)      // 2133
-                    {
-                       max_delay = 3700;       // in ps
-                    }
-                    else // if (p_i_mss_eff_config_data->mss_freq < 2533)   // 2400
-                    {
-                       max_delay = 3300;       // in ps
-                    }
-/*                  else if (p_i_mss_eff_config_data->mss_freq < 2933)      // 2666
-                    {
-                       max_delay = ??00;       // in ps
-                    }
-                    else // if (p_i_mss_eff_config_data->mss_freq < ????)   // 3200
-                    {
-                       max_delay = ??00;       // in ps
-                    }
-                                        
-*/
-                    uint8_t max_delay_clocks = calc_timing_in_clk
-                         (1, 0, max_delay, 0, p_i_mss_eff_config_data->mss_freq);
-
-                    // find max between min_delay_clocks, max_delay_clocks and dev_min
-
-                    if (min_delay_clocks > max_delay_clocks)
-                       max_delay_clocks = min_delay_clocks;
-
-                    if (p_i_mss_eff_config_data->dram_trrd > max_delay_clocks)
-                       max_delay_clocks = p_i_mss_eff_config_data->dram_trrd;
-
-                    if (max_delay_clocks > p_o_atts->eff_dram_trrd)
-                       p_o_atts->eff_dram_trrd = max_delay_clocks;
-
-//---------------------------------------------------------------------------------------
-// trrd_l = max(4nCK,7.5ns)
-        // 1600 1866 2133 2400 (data rate)
-        // 7.5  6.4, 6.4, 6.4 ns        for 2k page size (x16)
-        // 6,   5.3, 5.3, 4.9 ns        for 0.5k or 1k page size (x8)
-        // !! NOTE !!  NOT supporting 2k page size (with check for width above should cause error out).
-                p_i_mss_eff_config_data->dram_trrdl = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_data->trrdlmin[l_cur_mba_port][l_cur_mba_dimm],
-                    0, // need to put in the trrdlmin_ftb here...
-                    p_i_mss_eff_config_data->mss_freq
-                );
-
-                                // condense this later with the if/else above...
-                                if (p_i_mss_eff_config_data->mss_freq < 1733)           // 1600
-                                {
-                                        max_delay = 6000;       // in ps
-                                }
-                                else if (p_i_mss_eff_config_data->mss_freq < 2000)      // 1866
-                                {
-                                        max_delay = 5300;       // in ps
-                                }
-                                else if (p_i_mss_eff_config_data->mss_freq < 2267)      // 2133
-                                {
-                                        max_delay = 5300;       // in ps
-                                }
-                                else // if (p_i_mss_eff_config_data->mss_freq < 2533)   // 2400
-                                {
-                                        max_delay = 4900;       // in ps
-                                }
-/*                              else if (p_i_mss_eff_config_data->mss_freq < 2933)      // 2666
-                                {
-                                        max_delay = ??00;       // in ps
-                                }
-                                else // if (p_i_mss_eff_config_data->mss_freq < ????)   // 3200
-                                {
-                                        max_delay = ??00;       // in ps
-                                }
-                                        
-*/
-                max_delay_clocks = calc_timing_in_clk
-                                        (1, 0, max_delay, 0, p_i_mss_eff_config_data->mss_freq);
-                                if (max_delay_clocks > p_o_atts->eff_dram_trrdl)
-                                {
-                                        p_o_atts->eff_dram_trrdl = max_delay_clocks;
-                                }
-                                else if (p_i_mss_eff_config_data->dram_trrdl > p_o_atts->eff_dram_trrdl)
-                                {
-                                        p_o_atts->eff_dram_trrdl = p_i_mss_eff_config_data->dram_trrdl;
-                                }
-                FAPI_INF("DDR4 tRRDs = %i, tRRDl = %i", p_o_atts->eff_dram_trrd, p_o_atts->eff_dram_trrdl);
-         } else {
-            FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-            uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-            uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-            uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-            uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-            return rc;
-         }
-//------------------------------------------------------------------------------
-         if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) { 
-            p_i_mss_eff_config_data->dram_tccdl = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->tccdlmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_tccdl >
-                    p_o_atts->eff_dram_tccdl)
-            {
-                p_o_atts->eff_dram_tccdl =
-                    p_i_mss_eff_config_data->dram_tccdl;
-            }
-         }
-//------------------------------------------------------------------------------
-            p_i_mss_eff_config_data->dram_trp = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trpmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->fine_offset_trpmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_trp > p_o_atts->eff_dram_trp)
-            {
-                p_o_atts->eff_dram_trp = p_i_mss_eff_config_data->dram_trp;
-            }
-//------------------------------------------------------------------------------
-         if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-            p_i_mss_eff_config_data->dram_twtr = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->twtrmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_twtr > p_o_atts->eff_dram_twtr)
-            {
-               p_o_atts->eff_dram_twtr = p_i_mss_eff_config_data->dram_twtr;
-            }
-         } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-            p_i_mss_eff_config_data->dram_twtr = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->twtrsmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            // twtr_s = max(2nCK,2.5ns)   since min nCK=1.25ns, const 2.5ns
-            //FAPI_INF("DDR4 Check:  tWTR in CLKS = %i (2.5ns)",  p_i_mss_eff_config_data->dram_twtr);
-            //FAPI_INF("Attribute eff_dram_twtr = %i",  p_o_atts->eff_dram_twtr);
-            p_o_atts->eff_dram_twtr = p_i_mss_eff_config_data->dram_twtr;
-
-            // twtr_l = max(4nCK,7.5ns)
-            p_i_mss_eff_config_data->dram_twtrl = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->twtrlmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-
-            if (p_i_mss_eff_config_data->dram_twtrl < 4) {
-               p_o_atts->eff_dram_twtrl = 4;
-            } else {
-               p_o_atts->eff_dram_twtrl = p_i_mss_eff_config_data->dram_twtrl;
-            }
-            FAPI_INF("DDR4 twtrs = %i, twtrl = %i", p_o_atts->eff_dram_twtr, p_o_atts->eff_dram_twtrl);
-         } else {
-            FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-            uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-            uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-            uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-            uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-            return rc;
-         }
-//------------------------------------------------------------------------------
-            p_i_mss_eff_config_data->dram_trtp = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trtpmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-         if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-            if (p_i_mss_eff_config_data->dram_trtp > p_o_atts->eff_dram_trtp) {
-               p_o_atts->eff_dram_trtp = p_i_mss_eff_config_data->dram_trtp;
-            }
-         } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-            // max (4nCK, 7.5ns), 7.5ns=
-            //FAPI_INF("DDR4 Check:  tRTP in CLKS = %i (should be 6)",  p_i_mss_eff_config_data->dram_trtp);
-            //FAPI_INF("Attribute eff_dram_trtp= %i",  p_o_atts->eff_dram_trtp);
-            if (p_i_mss_eff_config_data->dram_trtp < 4)
-            {
-               p_o_atts->eff_dram_trtp = 4;
-            } else {
-               p_o_atts->eff_dram_trtp = p_i_mss_eff_config_data->dram_trtp;
-            }
-         } else {
-            FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-            uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-            uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-            uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-            uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-            return rc;
-         }
-
-//------------------------------------------------------------------------------
-            p_i_mss_eff_config_data->dram_tras = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trasmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_tras >
-                    p_o_atts->eff_dram_tras_u32)
-            {
-                p_o_atts->eff_dram_tras_u32 =
-                    p_i_mss_eff_config_data->dram_tras;
-            }
-//------------------------------------------------------------------------------
-            p_i_mss_eff_config_data->dram_trc = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trcmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->fine_offset_trcmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_trc >
-                    p_o_atts->eff_dram_trc_u32)
-            {
-                p_o_atts->eff_dram_trc_u32 =
-                    p_i_mss_eff_config_data->dram_trc;
-            }
-//------------------------------------------------------------------------------
-         if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-            p_i_mss_eff_config_data->dram_trfc = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trfcmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_trfc >
-                    p_o_atts->eff_dram_trfc)
-            {
-                p_o_atts->eff_dram_trfc =
-                    p_i_mss_eff_config_data->dram_trfc;
-            }
-         } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-            p_i_mss_eff_config_data->dram_trfc = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->trfc1min[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            FAPI_INF("DDR4 Check: spd trfc = 0x%x (%i clks), o_attr=0x%x",
-               p_i_data->trfc1min[l_cur_mba_port][l_cur_mba_dimm],
-               p_i_mss_eff_config_data->dram_trfc,
-               p_o_atts->eff_dram_trfc
-            );
-            if (p_i_mss_eff_config_data->dram_trfc >
-                    p_o_atts->eff_dram_trfc)
-            {
-                p_o_atts->eff_dram_trfc =
-                    p_i_mss_eff_config_data->dram_trfc;
-            }
-            // AST HERE: Need DDR4 attributes for other refresh rates, 2x, 4x
-
-         } else {
-            FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-            uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-            uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-            uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-            uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-            return rc;
-         }
-//------------------------------------------------------------------------------
-         if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-            p_i_mss_eff_config_data->dram_tfaw = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    p_i_data->tfawmin[l_cur_mba_port]
-                    [l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-            if (p_i_mss_eff_config_data->dram_tfaw >
-                    p_o_atts->eff_dram_tfaw_u32)
-            {
-                p_o_atts->eff_dram_tfaw_u32 =
-                    p_i_mss_eff_config_data->dram_tfaw;
-            }
-         } else if (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-            p_i_mss_eff_config_data->dram_tfaw = calc_timing_in_clk
-                (
-                    p_i_mss_eff_config_data->mtb_in_ps_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_mss_eff_config_data->ftb_in_fs_u32array[l_cur_mba_port][l_cur_mba_dimm],
-                    p_i_data->tfawmin[l_cur_mba_port][l_cur_mba_dimm],
-                    0,
-                    p_i_mss_eff_config_data->mss_freq
-                );
-FAPI_DBG("DDR4 Check:  SPD=0x%x, p_i_tFAWmin (nCK) = %i",
-                p_i_data->tfawmin[l_cur_mba_port][l_cur_mba_dimm], p_i_mss_eff_config_data->dram_tfaw);
-
-                                // example x8, 1600, min= 25ns => 25/1.25 = 20 clocks
-                                const uint8_t min_clks [][6] = {        // width, data rate
-                                // NOTE: 2666 and 3200 are TBD, using guess values
-                                // 1600 1866 2133 2400 2666 3200
-                                  { 16,  16,  16,  16,  16,  16},               // x4 (page size = 1/2K)
-                                  { 20,  22,  23,  26,  29,  32}                // x8 (page size = 1K)
-                                //{ xx,  xx,  xx,  xx,  TBD, TBD},              // x16(page size = 2K)
-                                };
-
-                                uint8_t speed_idx;
-                                uint8_t width_idx;
-
-                                if (p_i_data->dram_width[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W4)
-                                {
-                                                width_idx = 0;
-                                }
-                                else //(p_i_data->dram_width[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W8)
-                                {
-                                                width_idx = 1;
-                                }
-                                //else (p_i_data->dram_width == fapi::ENUM_ATTR_SPD_DRAM_WIDTH_W16)
-
-
-                                if (p_i_mss_eff_config_data->mss_freq < 1733)           // 1600
-                                {
-                                        speed_idx  = 0;                 // 1.25ns
-                                }
-                                else if (p_i_mss_eff_config_data->mss_freq < 2000)      // 1866
-                                {
-                                        speed_idx  = 1;                 // 1.0718ns
-                                }
-                                else if (p_i_mss_eff_config_data->mss_freq < 2267)      // 2133
-                                {
-                                        speed_idx  = 2;                 // 0.9376ns
-                                }
-                                else // if (p_i_mss_eff_config_data->mss_freq < 2533)   // 2400
-                                {
-                                        speed_idx  = 3;                 // 0.8333ns
-                                }
-        //                      else if (p_i_mss_eff_config_data->mss_freq < 2933)      // 2666
-        //                      {
-        //                              speed_idx  = 4;                 // 0.7502ns
-        //                      }
-        //                      else // if (p_i_mss_eff_config_data->mss_freq < ????)   // 3200
-        //                      {
-        //                              speed_idx  = 5;                 // 0.625ns
-        //                      }
-
-                                if (p_o_atts->eff_dram_tfaw_u32 < min_clks[width_idx][speed_idx])
-                                {
-                                        p_o_atts->eff_dram_tfaw_u32 =  min_clks[width_idx][speed_idx];
-                                }
-/*                              
-    fapi::Target l_target_centaur;
-        rc = fapiGetParentChip(i_target_mba, l_target_centaur);
-    if(rc) break;
-        uint8_t ec_tfaw_16_problem;
-        // need ATTRIBUTE for this....
-    rc = FAPI_ATTR_GET(ATTR_MSS_DISABLE1_REG_FIXED, &i_target_centaur, ec_tfaw_16_problem);
-    if(rc) break;
-*/
-                                if (p_o_atts->eff_dram_tfaw_u32 == 16)  // due to logic bug above
-                                {
-                                        p_o_atts->eff_dram_tfaw_u32 = 15;
-                                        FAPI_INF("setting tFAW to 15 due to bug");
-                                }
-                        FAPI_DBG("Attribute p_o_eff_dram_tfaw = %i",  p_o_atts->eff_dram_tfaw_u32);
-         } else {
-            FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-            uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-            uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-            uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-            uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-            return rc;
-         }
-//------------------------------------------------------------------------------
-        } // inner for loop
-    } // outter for loop
-
-    // Calculate CWL
-    if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) {
-       if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 2500)
-       {
-           p_o_atts->eff_dram_cwl = 5;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1875)
-       {
-           p_o_atts->eff_dram_cwl = 6;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1500)
-       {
-           p_o_atts->eff_dram_cwl = 7;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1250)
-       {
-           p_o_atts->eff_dram_cwl = 8;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 1070)
-       {
-           p_o_atts->eff_dram_cwl = 9;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 935)
-       {
-           p_o_atts->eff_dram_cwl = 10;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 833)
-       {
-           p_o_atts->eff_dram_cwl = 11;
-       }
-       else if ((TWO_MHZ/p_i_mss_eff_config_data->mss_freq) >= 750)
-       {
-           p_o_atts->eff_dram_cwl = 12;
-       }
-       else
-       {
-           const uint16_t& CWL_VAL = (TWO_MHZ/p_i_mss_eff_config_data->mss_freq);
-           FAPI_ERR("Error calculating CWL");
-           FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_CWL_CALC_ERR);
-           return rc;
-       }
-    } else if (p_i_data->dram_device_type[0][0] == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-                // 1st set only
-                // need to look at this again...
-                if (p_i_mss_eff_config_data->mss_freq <= (1600 * 1.05)) // 1600 
-                {
-                        p_o_atts->eff_dram_cwl = 9;
-                }
-                else if (p_i_mss_eff_config_data->mss_freq <= (1866 * 1.05))    // 1866
-                {
-                        p_o_atts->eff_dram_cwl = 10;
-                }
-                else if (p_i_mss_eff_config_data->mss_freq <= (2133 * 1.05))    // 2133
-                {
-                        p_o_atts->eff_dram_cwl = 11;
-                }
-                else if (p_i_mss_eff_config_data->mss_freq <= (2400 * 1.05))    // 2400
-                {
-                        p_o_atts->eff_dram_cwl = 12;
-                }
-                else if (p_i_mss_eff_config_data->mss_freq <= (2666 * 1.05))    // 2666
-                {
-                        p_o_atts->eff_dram_cwl = 14;
-                }
-                else if (p_i_mss_eff_config_data->mss_freq <= (3200 * 1.05))    // 2666
-                {
-                        p_o_atts->eff_dram_cwl = 16;
-                }
-                else
-                {
-                   const uint16_t& CWL_VAL = (TWO_MHZ/p_i_mss_eff_config_data->mss_freq);
-                   FAPI_ERR("Error calculating CWL");
-                   FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_CWL_CALC_ERR);
-                   return rc;
-                }
-    } else {
-         FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-         uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-         uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-         uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-         uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-         FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-         return rc;
-    }
-//------------------------------------------------------------------------------
-    // Calculate ZQCAL Interval based on the following equation from Ken:
-    //            0.5
-    //  ------------------------------ = 13.333ms 
-    //  (1.5 * 10) + (0.15 * 150)
-
-    //p_o_atts->eff_zqcal_interval = 0;
-    p_o_atts->eff_zqcal_interval = ( 13333 *
-            p_i_mss_eff_config_data->mss_freq) / 2;
-//------------------------------------------------------------------------------
-    // Calculate MEMCAL Interval based on 1sec interval across all bits per DP18
-
-    //p_o_atts->eff_memcal_interval = 0;
-    p_o_atts->eff_memcal_interval = (62500 *
-            p_i_mss_eff_config_data->mss_freq) / 2;
-//------------------------------------------------------------------------------
-    // Calculate tRFI
-    p_o_atts->eff_dram_trfi = (3900 *
-            p_i_mss_eff_config_data->mss_freq) / 2000;
-    // Added 10% margin to TRFI per defect HW248225
-    p_o_atts->eff_dram_trfi = (p_o_atts->eff_dram_trfi * 9) / 10;
-
-    p_o_atts->eff_vpd_version = 0xFFFFFF; // set VPD version to a large number, searching for smallest
-    // the VPD version is 2 ASCI characters, so this is always later than that
-
-    // Assigning dependent values to attributes
-    for (int l_cur_mba_port = 0; l_cur_mba_port <
-            PORT_SIZE; l_cur_mba_port += 1)
-    {
-        for (int l_cur_mba_dimm = 0; l_cur_mba_dimm <
-                DIMM_SIZE; l_cur_mba_dimm += 1)
-        {
-          if (p_i_mss_eff_config_data->
-              cur_dimm_spd_valid_u8array[l_cur_mba_port][l_cur_mba_dimm] == MSS_EFF_VALID)
-          {
-             if (p_i_data->num_ranks[l_cur_mba_port]
-                    [l_cur_mba_dimm] == 0x04)                 // for 8R LRDIMM  since no ENUM defined yet for SPD of 8R
-//                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R8)
-            {
-                p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 8;
-                p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0x80;                            // DD0/1: 1 master rank
-            }
-            else if (p_i_data->num_ranks[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R4)
-            {
-                p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 4;
-                p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0xF0;
-            }
-            else if (p_i_data->num_ranks[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R2)
-            {
-                p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 2;
-                p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0xC0;
-            }
-            else if (p_i_data->num_ranks[l_cur_mba_port]
-                    [l_cur_mba_dimm] == fapi::ENUM_ATTR_SPD_NUM_RANKS_R1)
-            {
-                p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 1;
-                p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0x80;
-            } else
-            {
-                p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0;
-                p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0x00;
-            }
-
-            if ( p_i_data->sdram_device_type[l_cur_mba_port][l_cur_mba_dimm] == 
-                 fapi::ENUM_ATTR_SPD_SDRAM_DEVICE_TYPE_NON_STANDARD) {
-               p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP;
-            } else {
-               p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
-            }
-
-                        uint8_t& UNSUPPORTED_VAL = p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm];
-            // AST HERE: Needed SPD byte33[7,1:0], for expanded IBM_TYPE
-            if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) {
-               if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1) {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1A;
-               } else if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 2) {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1B;
-               } else if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 4) {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1D;
-               } else {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
-                  FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RDIMM_UNSUPPORTED_TYPE); return rc;
-               }
-            } else if (( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM ) && ( p_o_atts->eff_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES )) {
-               if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 1) {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1A;
-               } else if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 2) {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_1B;
-               } else {
-                  p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
-                  FAPI_ERR("Currently unsupported IBM_TYPE on %s!", i_target_mba.toEcmdString());
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_UDIMM_UNSUPPORTED_TYPE); return rc;
-               }
-            } else if ( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               if (p_o_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) {
-                  FAPI_INF("Will set LR atts after orig eff_config functions");
-               } else if (p_o_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) {   // need to update this later...
-                  if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 4) {
-                        p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_TYPE_5C;
-                  } else {
-                     FAPI_INF("Will set LR atts after orig eff_config functions");
-                  }
-               } else {
-                  FAPI_ERR("Incompatable DRAM generation on %s!",i_target_mba.toEcmdString());
-                  uint8_t& DRAM_DEVICE_TYPE_0_0 = p_i_data->dram_device_type[0][0];
-                  uint8_t& DRAM_DEVICE_TYPE_0_1 = p_i_data->dram_device_type[0][1];
-                  uint8_t& DRAM_DEVICE_TYPE_1_0 = p_i_data->dram_device_type[1][0];
-                  uint8_t& DRAM_DEVICE_TYPE_1_1 = p_i_data->dram_device_type[1][1];
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INCOMPATABLE_DRAM_GEN);
-                  return rc;
-               }
-            } else {
-               p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
-               FAPI_ERR("Currently unsupported DIMM_TYPE on %s!", i_target_mba.toEcmdString());
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_DIMM_UNSUPPORTED_TYPE); return rc;
-            }
-          } else {
-             p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                 [l_cur_mba_dimm] = 0;
-             p_o_atts->eff_dimm_ranks_configed[l_cur_mba_port]
-                 [l_cur_mba_dimm] = 0x00;
-            p_o_atts->eff_stack_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
-            p_o_atts->eff_ibm_type[l_cur_mba_port][l_cur_mba_dimm] = fapi::ENUM_ATTR_EFF_IBM_TYPE_UNDEFINED;
-          }
-//------------------------------------------------------------------------------
-          
-//------------------------------------------------------------------------------
-            if (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] != 0)
-            {
-                // structured equations as such due to long names
-                // example: answer = ((num1)*(num2)*(const)) / ((const) * (num3));
-                // becomes:
-                //          answer =
-                //              (
-                //                  (num1)
-                //                  *
-                //                  (num2)
-                //                  *
-                //                  (const)
-                //              )
-                //              /
-                //              (
-                //                  (const)
-                //                  *
-                //                  (num3)
-                //              );
-                //
-                // dimm_size = dram_density / 8 * primary_bus_width
-                //             / dram_width * num_ranks_per_dimm
-                p_o_atts->eff_dimm_size[l_cur_mba_port][l_cur_mba_dimm] =
-                    (
-                        (p_o_atts->eff_dram_density)
-                        *
-                        (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                         [l_cur_mba_dimm])
-                        *
-                        64
-                    )
-                    /
-                    (
-                        8
-                        *
-                        (p_o_atts->eff_dram_width)
-                    );
-            }
-            else
-            {
-                p_o_atts->eff_dimm_size[l_cur_mba_port]
-                    [l_cur_mba_dimm] = 0;
-            }
-
-
-            if ( (p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) &&
-                    (p_i_data->dram_device_type[l_cur_mba_port][l_cur_mba_dimm] ==
-                                              fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) &&
-                       (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] == 8) )
-            {
-                p_o_atts->eff_num_master_ranks_per_dimm[l_cur_mba_port]
-                        [l_cur_mba_dimm] = 1;
-            } 
-            else 
-            {
-                // AST HERE: Needs SPD byte33[7,1:0],
-                //  currently hard coded to no stacking
-                p_o_atts->eff_num_master_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm] =
-                    p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port]
-                    [l_cur_mba_dimm];
-            }
-
-            // Populate RCD_CNTL_WORD for RDIMM, add hardcode to RC0-DA4=0b0 RC9-DBA1-DBA0-DA4-DA3=0b00X0, merge in ATTR_VPD_DIMM_RCD_IBT ATTR_VPD_DIMM_RCD_OUTPUT_TIMING, and adjust in RC10 and RC11 for freq/voltage
-            if (( p_o_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) && (p_o_atts->eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm] != 0)) {
-
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_i_data->rdimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm];
-
-               uint64_t l_rcd_hardcode_mask      = 0xDFFFFFFFF2FFFFFFLL;
-               uint64_t l_mss_freq_mask          = 0xFFFFFFFFFF8FFFFFLL;
-               uint64_t l_mss_volt_mask          = 0xFFFFFFFFFFFCFFFFLL;
-               uint64_t l_rcd_ibt_mask           = 0xFFBFFFFF8FFFFFFFLL;
-               uint64_t l_rcd_output_timing_mask = 0xFFDFFFFFFFFFFFFFLL;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] & l_rcd_hardcode_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] & l_mss_freq_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] & l_mss_volt_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] & l_rcd_ibt_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] & l_rcd_output_timing_mask;
-
-               if ( p_i_mss_eff_config_data->mss_freq <= 933 ) {         // 800Mbps
-                  l_mss_freq_mask = 0x0000000000000000LL;
-               } else if ( p_i_mss_eff_config_data->mss_freq <= 1200 ) { // 1066Mbps
-                  l_mss_freq_mask = 0x0000000000100000LL;
-               } else if ( p_i_mss_eff_config_data->mss_freq <= 1466 ) { // 1333Mbps
-                  l_mss_freq_mask = 0x0000000000200000LL;
-               } else if ( p_i_mss_eff_config_data->mss_freq <= 1733 ) { // 1600Mbps
-                  l_mss_freq_mask = 0x0000000000300000LL;
-               } else {                           // 1866Mbps
-                  FAPI_ERR("Invalid RDIMM ATTR_MSS_FREQ = %d on %s!", p_i_mss_eff_config_data->mss_freq, i_target_mba.toEcmdString());
-                  uint32_t& INVALID_RDIMM_FREQ = p_i_mss_eff_config_data->mss_freq;
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_RDIMM_FREQ); return rc;
-               }
-               
-	       //1.5V DDR3 or 1.2V DDR4
-               if ( p_i_mss_eff_config_data->mss_volt >= 1420 || (p_o_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 && p_i_mss_eff_config_data->mss_volt >= 1130 && p_i_mss_eff_config_data->mss_volt <= 1270)) {        // 1.5V
-                  l_mss_volt_mask = 0x0000000000000000LL;
-               } else if ( p_i_mss_eff_config_data->mss_volt >= 1270 && p_o_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // 1.35V and DDR3
-                  l_mss_volt_mask = 0x0000000000010000LL;
-               } else {                           // not valid DDR3 or DDR4 setting
-                  FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", p_i_mss_eff_config_data->mss_volt, i_target_mba.toEcmdString());
-                  uint32_t& INVALID_RDIMM_VOLT = p_i_mss_eff_config_data->mss_volt;
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_RDIMM_VOLT); return rc;
-               }
-
-               if ( l_rdimm_rcd_ibt[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_IBT_IBT_OFF ) {
-                  l_rcd_ibt_mask = 0x0000000070000000LL;
-               } else if ( l_rdimm_rcd_ibt[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_IBT_IBT_100 ) {
-                  l_rcd_ibt_mask = 0x0000000000000000LL;
-               } else if ( l_rdimm_rcd_ibt[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_IBT_IBT_150 ) {
-                  l_rcd_ibt_mask = 0x0040000000000000LL;
-               } else if ( l_rdimm_rcd_ibt[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_IBT_IBT_200 ) {
-                  l_rcd_ibt_mask = 0x0000000020000000LL;
-               } else if ( l_rdimm_rcd_ibt[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_IBT_IBT_300 ) {
-                  l_rcd_ibt_mask = 0x0000000040000000LL;
-               } else {
-                  FAPI_ERR("Invalid RDIMM_RCD_IBT = %d port %d dimm %d on %s!", l_rdimm_rcd_ibt[l_cur_mba_port][l_cur_mba_dimm], l_cur_mba_port, l_cur_mba_dimm, i_target_mba.toEcmdString());
-                  uint32_t& INVALID_RDIMM_RCD_IBT_U32ARRAY_0_0 = l_rdimm_rcd_ibt[0][0];
-                  uint32_t& INVALID_RDIMM_RCD_IBT_U32ARRAY_0_1 = l_rdimm_rcd_ibt[0][1];
-                  uint32_t& INVALID_RDIMM_RCD_IBT_U32ARRAY_1_0 = l_rdimm_rcd_ibt[1][0];
-                  uint32_t& INVALID_RDIMM_RCD_IBT_U32ARRAY_1_1 = l_rdimm_rcd_ibt[1][1];
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_RDIMM_RCD_IBT); return rc;
-               }
-
-               if ( l_rdimm_rcd_output_timing[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_OUTPUT_TIMING_1T ) {
-                  l_rcd_output_timing_mask = 0x0000000000000000LL;
-               } else if ( l_rdimm_rcd_output_timing[l_cur_mba_port][l_cur_mba_dimm] == fapi::ENUM_ATTR_VPD_DIMM_RCD_OUTPUT_TIMING_3T ) {
-                  l_rcd_output_timing_mask = 0x0020000000000000LL;
-               } else {
-                  FAPI_ERR("Invalid RDIMM_RCD_OUTPUT_TIMING = %d port %d dimm %d on %s!", l_rdimm_rcd_output_timing[l_cur_mba_port][l_cur_mba_dimm], l_cur_mba_port, l_cur_mba_dimm, i_target_mba.toEcmdString());
-                  uint8_t& INVALID_RDIMM_RCD_OUTPUT_TIMING_U8ARRAY_0_0 = l_rdimm_rcd_output_timing[0][0];
-                  uint8_t& INVALID_RDIMM_RCD_OUTPUT_TIMING_U8ARRAY_0_1 = l_rdimm_rcd_output_timing[0][1];
-                  uint8_t& INVALID_RDIMM_RCD_OUTPUT_TIMING_U8ARRAY_1_0 = l_rdimm_rcd_output_timing[1][0];
-                  uint8_t& INVALID_RDIMM_RCD_OUTPUT_TIMING_U8ARRAY_1_1 = l_rdimm_rcd_output_timing[1][1];
-                  FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_INVALID_RDIMM_RCD_OUTPUT_TIMING); return rc;
-               }
-
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] | l_mss_freq_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] | l_mss_volt_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] | l_rcd_ibt_mask;
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] | l_rcd_output_timing_mask;
-            } else {
-               p_o_atts->eff_dimm_rcd_cntl_word_0_15[l_cur_mba_port][l_cur_mba_dimm] = 0x0000000000000000LL;
-            }
-
-            // DEBUG HERE:
-            //FAPI_INF("size=%d density=%d ranks=%d width=%d on %s",
-            // p_o_atts->eff_dimm_size[l_cur_mba_port][l_cur_mba_dimm],
-            // p_o_atts->eff_dram_density, p_o_atts->
-            // attr_eff_num_ranks_per_dimm[l_cur_mba_port][l_cur_mba_dimm],
-            // p_o_atts->eff_dram_width, i_target_mba.toEcmdString());
-//------------------------------------------------------------------------------
-            if(p_o_atts->eff_vpd_version == 0xFFFFFF ||
-               p_i_data->vpd_version[l_cur_mba_port][l_cur_mba_dimm] < p_o_atts->eff_vpd_version ) { // find the smallest VPD
-                p_o_atts->eff_vpd_version = p_i_data->vpd_version[l_cur_mba_port][l_cur_mba_dimm];
-            }
-//------------------------------------------------------------------------------
-
-        } // inner for loop
-    } // outer for loop
-    return rc;
-} // end mss_eff_config_setup_eff_atts()
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_write_eff_atts(): This function writes the
-//              effective configuration attributes
-//
-// @param const fapi::Target &i_target_mba: the fapi target
-// @param       mss_eff_config_data *p_i_mss_eff_config_data: Pointer to
-//              mss_eff_config_data variable structure
-// @param const mss_eff_config_atts *p_i_atts: Pointer to mss_eff
-//              configuration attributes structure
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config_write_eff_atts(
-                                            const fapi::Target &i_target_mba,
-                                            mss_eff_config_atts *p_i_atts)
-{
-    fapi::ReturnCode rc;
-
-    p_i_atts->eff_dram_tras = uint8_t (p_i_atts->eff_dram_tras_u32);
-    p_i_atts->eff_dram_trc = uint8_t (p_i_atts->eff_dram_trc_u32);
-    p_i_atts->eff_dram_tfaw = uint8_t (p_i_atts->eff_dram_tfaw_u32);
-
-    do
-    {
-        // Set attributes
-        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba,
-                p_i_atts->eff_dimm_ranks_configed);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target_mba,
-                p_i_atts->eff_lrdimm_additional_cntl_words);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_LRDIMM_ADDITIONAL_CNTL_WORDS, &i_target_mba,
-                p_i_atts->eff_lrdimm_additional_cntl_words);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba,
-                p_i_atts->eff_dimm_rcd_cntl_word_0_15);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_SIZE, &i_target_mba,
-                p_i_atts->eff_dimm_size);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba,
-                p_i_atts->eff_dimm_type);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba,
-                p_i_atts->eff_custom_dimm);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba,
-                p_i_atts->eff_dram_al);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_ASR, &i_target_mba,
-                p_i_atts->eff_dram_asr);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_BANKS, &i_target_mba,
-                p_i_atts->eff_dram_banks);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_BL, &i_target_mba,
-                p_i_atts->eff_dram_bl);
-        if(rc) break;
-
-        // See mss_freq.C
-        //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CL, &i_target_mba,
-            //p_i_atts->eff_dram_cl);
-        //if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_COLS, &i_target_mba,
-                p_i_atts->eff_dram_cols);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_CWL, &i_target_mba,
-                p_i_atts->eff_dram_cwl);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DENSITY, &i_target_mba,
-                p_i_atts->eff_dram_density);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_ENABLE, &i_target_mba,
-                p_i_atts->eff_dram_dll_enable);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_PPD, &i_target_mba,
-                p_i_atts->eff_dram_dll_ppd);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_DLL_RESET, &i_target_mba,
-                p_i_atts->eff_dram_dll_reset);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_GEN, &i_target_mba,
-                p_i_atts->eff_dram_gen);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_OUTPUT_BUFFER, &i_target_mba,
-                p_i_atts->eff_dram_output_buffer);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_PASR, &i_target_mba,
-                p_i_atts->eff_dram_pasr);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_RBT, &i_target_mba,
-                p_i_atts->eff_dram_rbt);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_ROWS, &i_target_mba,
-                p_i_atts->eff_dram_rows);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_SRT, &i_target_mba,
-                p_i_atts->eff_dram_srt);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TDQS, &i_target_mba,
-                p_i_atts->eff_dram_tdqs);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TFAW, &i_target_mba,
-                p_i_atts->eff_dram_tfaw);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TM, &i_target_mba,
-                p_i_atts->eff_dram_tm);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRAS, &i_target_mba,
-                p_i_atts->eff_dram_tras);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRC, &i_target_mba,
-                p_i_atts->eff_dram_trc);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRCD, &i_target_mba,
-                p_i_atts->eff_dram_trcd);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRFC, &i_target_mba,
-                p_i_atts->eff_dram_trfc);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRFI, &i_target_mba,
-                p_i_atts->eff_dram_trfi);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRP, &i_target_mba,
-                p_i_atts->eff_dram_trp);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRRD, &i_target_mba,
-                p_i_atts->eff_dram_trrd);
-        if(rc) break;
-        // DDR4 only
-        // AST HERE: Need ATTR added
-        //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRRD_L, &i_target_mba,
-        //        p_i_atts->eff_dram_trrd);
-        //if(rc) break;
-        // DDR4 only
-        rc = FAPI_ATTR_SET(ATTR_TCCD_L, &i_target_mba,
-                p_i_atts->eff_dram_tccdl);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TCCD_L, &i_target_mba,
-                p_i_atts->eff_dram_tccdl);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TRTP, &i_target_mba,
-                p_i_atts->eff_dram_trtp);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TWTR, &i_target_mba,
-                p_i_atts->eff_dram_twtr);
-        if(rc) break;
-        // DDR4 only
-        // AST HERE: Need ATTR added
-        //rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TWTRL, &i_target_mba,
-        //p_i_atts->eff_dram_twtrl);
-        //if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WIDTH, &i_target_mba,
-                p_i_atts->eff_dram_width);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR, &i_target_mba,
-                p_i_atts->eff_dram_wr);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_LVL_ENABLE, &i_target_mba,
-                p_i_atts->eff_dram_wr_lvl_enable);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_IBM_TYPE, &i_target_mba,
-                p_i_atts->eff_ibm_type);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_MEMCAL_INTERVAL, &i_target_mba,
-                p_i_atts->eff_memcal_interval);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_MPR_LOC, &i_target_mba,
-                p_i_atts->eff_mpr_loc);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_MPR_MODE, &i_target_mba,
-                p_i_atts->eff_mpr_mode);
-        if(rc) break;
-
-        // AST HERE: Needs SPD byte33[6:4], currently hard coded to 0, removed for GA1
-        rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DIES_PER_PACKAGE, &i_target_mba,
-                p_i_atts->eff_num_dies_per_package);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba,
-                p_i_atts->eff_num_drops_per_port);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba,
-                p_i_atts->eff_num_master_ranks_per_dimm);
-        if(rc) break;
-
-        // AST HERE: Needs source data, currently hard coded to 0, removed for GA1
-        rc = FAPI_ATTR_SET(ATTR_EFF_NUM_PACKAGES_PER_RANK, &i_target_mba,
-                p_i_atts->eff_num_packages_per_rank);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba,
-                p_i_atts->eff_num_ranks_per_dimm);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_MODE, &i_target_mba,
-                p_i_atts->eff_schmoo_mode);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba,
-                p_i_atts->eff_schmoo_addr_mode);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba,
-                p_i_atts->eff_schmoo_param_valid);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba,
-                p_i_atts->eff_schmoo_test_valid);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN, &i_target_mba,
-                p_i_atts->eff_schmoo_wr_eye_min_margin);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN, &i_target_mba,
-                p_i_atts->eff_schmoo_rd_eye_min_margin);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN, &i_target_mba,
-                p_i_atts->eff_schmoo_dqs_clk_min_margin);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN, &i_target_mba,
-                p_i_atts->eff_schmoo_rd_gate_min_margin);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN, &i_target_mba,
-                p_i_atts->eff_schmoo_addr_cmd_min_margin);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_rd_vref_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba,
-                p_i_atts->eff_dram_wr_vref_schmoo);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_rcv_imp_dq_dqs_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_drv_imp_dq_dqs_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_drv_imp_cntl_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_drv_imp_clk_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_drv_imp_spcke_schmoo);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_slew_rate_dq_dqs_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_slew_rate_cntl_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_slew_rate_addr_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_slew_rate_clk_schmoo);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba,
-                p_i_atts->eff_cen_slew_rate_spcke_schmoo);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_EFF_STACK_TYPE, &i_target_mba,
-                p_i_atts->eff_stack_type);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_EFF_ZQCAL_INTERVAL, &i_target_mba,
-                p_i_atts->eff_zqcal_interval);
-        if(rc) break;
-        rc = FAPI_ATTR_SET(ATTR_MSS_EFF_DIMM_FUNCTIONAL_VECTOR, &i_target_mba,
-                p_i_atts->dimm_functional_vector);
-        if(rc) break;
-
-        rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba,
-                p_i_atts->mss_cal_step_enable);
-        if(rc) break;
-
-        // Make the final VPD version be a number and not ascii
-        p_i_atts->eff_vpd_version=((p_i_atts->eff_vpd_version & 0x0f00)>> 4)|
-          ((p_i_atts->eff_vpd_version & 0x000f)>> 0);
-        rc = FAPI_ATTR_SET(ATTR_MSS_EFF_VPD_VERSION, &i_target_mba,
-                p_i_atts->eff_vpd_version);
-        if(rc) break;
-
-    } while(0);
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config(): This function is the main function which calls
-//                          helper functions that read and verify spd data as
-//                          well as configure effective attributes.
-//
-// @param const fapi::Target i_target_mba: the fapi target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba)
-{
-    /* Initialize Variables */
-    const fapi::Target& TARGET_MBA = i_target_mba;
-    fapi::ReturnCode rc;
-    fapi::Target l_target_centaur;
-    // Changed l_mss_volt to p_l_mss_eff_config_data->mss_volt.
-    //uint32_t l_mss_volt;
-    // mss_eff_config_data_variable struct
-    mss_eff_config_data *p_l_mss_eff_config_data = new mss_eff_config_data();
-    // mss_eff_config_spd_data struct
-    mss_eff_config_spd_data *p_l_spd_data = new mss_eff_config_spd_data();
-    // mss_eff_config_atts struct
-    mss_eff_config_atts *p_l_atts = new mss_eff_config_atts();
-    /* End Variable Initialization */
-
-    /* zero out struct elements */
-    memset( p_l_mss_eff_config_data, 0, sizeof(mss_eff_config_data) );
-    memset( p_l_spd_data, 0, sizeof(mss_eff_config_spd_data) );
-    memset( p_l_atts, 0, sizeof(mss_eff_config_atts) );
-
-    FAPI_INF("STARTING mss_eff_config on %s \n",
-            i_target_mba.toEcmdString());
-
-    do
-    {
-      FAPI_INF("Setup and VPD attributes if needbe\n");
-
-#ifdef FAPI_MSSLABONLY
-      FAPI_INF("Lab only: Setup and VPD attributes if needbe\n");
-
-      rc = mss_eff_config_termination_vpd(i_target_mba); if(rc) break;
-      if(rc)
-      {
-        FAPI_ERR("Error from mss_eff_config_termination_vpd()");
-        break;
-      }
-#endif
-
-    // Added call to mss_eff_pre_config() for Mike Pardeik (power/thermal).
-    rc = mss_eff_pre_config(i_target_mba); if(rc) return rc;
-
-     
-//------------------------------------------------------------------------------
-        // Grab allow single port data
-        rc = FAPI_ATTR_GET(ATTR_MSS_ALLOW_SINGLE_PORT, &i_target_mba, p_l_mss_eff_config_data->allow_single_port);
-        if(rc) break;
-        if ( p_l_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_TRUE ) {
-           FAPI_INF("WARNING: allow_single_port = %d on %s.", p_l_mss_eff_config_data->allow_single_port, i_target_mba.toEcmdString());
-        }
-//------------------------------------------------------------------------------
-        // Grab freq/volt data
-        rc = fapiGetParentChip(i_target_mba, l_target_centaur);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur,
-                p_l_mss_eff_config_data->mss_freq);
-        if(rc) break;
-        rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, p_l_mss_eff_config_data->mss_volt);
-        if(rc) break;
-        if (p_l_mss_eff_config_data->mss_freq == 0)
-        {
-            FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!",
-                    p_l_mss_eff_config_data->mss_freq,
-                    i_target_mba.toEcmdString());
-                        uint32_t& FREQ_VAL = p_l_mss_eff_config_data->mss_freq;
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MSS_FREQ);
-            break;
-        }
-        FAPI_INF("mss_freq = %d, tCK_in_ps= %d on %s.",
-                p_l_mss_eff_config_data->mss_freq,
-                TWO_MHZ/p_l_mss_eff_config_data->mss_freq,
-                l_target_centaur.toEcmdString());
-        FAPI_INF("mss_volt = %d on %s.", p_l_mss_eff_config_data->mss_volt,
-                l_target_centaur.toEcmdString());
-
-//------------------------------------------------------------------------------
-        /* Function calls */
-        // get SPD data
-        rc = mss_eff_config_get_spd_data( i_target_mba,
-                p_l_mss_eff_config_data, p_l_spd_data, p_l_atts );
-        if(rc)
-        {
-            FAPI_ERR("Error from mss_eff_config_get_spd_data()");
-            break;
-        }
-
-        // verify dimm plug rules
-        rc = mss_eff_config_verify_plug_rules( i_target_mba,
-                p_l_mss_eff_config_data, p_l_atts );
-        if(rc)
-        {
-            FAPI_ERR("Error from mss_eff_config_verify_plug_rules()");
-            break;
-        }
-
-        // verify SPD data
-        if(( p_l_atts->eff_num_drops_per_port
-                != fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_EMPTY )
-          && ( p_l_mss_eff_config_data->allow_single_port == fapi::ENUM_ATTR_MSS_ALLOW_SINGLE_PORT_FALSE ))
-        {
-            rc = mss_eff_config_verify_spd_data( i_target_mba,
-                    p_l_atts, p_l_spd_data );
-            if(rc)
-            {
-                FAPI_ERR("Error from mss_eff_config_verify_spd_data()");
-                break;
-            }
-        }
-
-        // setup effective configuration attributes
-        rc = mss_eff_config_setup_eff_atts( i_target_mba,
-                p_l_mss_eff_config_data, p_l_spd_data, p_l_atts );
-        if(rc)
-        {
-            FAPI_ERR("Error from mss_eff_config_setup_eff_atts()");
-            break;
-        }
-
-        // write effective configuration attributes
-        rc = mss_eff_config_write_eff_atts( i_target_mba,
-                p_l_atts );
-        if(rc)
-        {
-            FAPI_ERR("Error from mss_eff_config_write_eff_atts()");
-            break;
-        }
-
-
-
-        // Calls to sub-procedures
-
-        // LRDIMM attributes
-        if ( p_l_atts->eff_dimm_type == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM )
-        {
-           rc = mss_lrdimm_eff_config(i_target_mba, p_l_mss_eff_config_data->cur_dimm_spd_valid_u8array,
-                                      p_l_mss_eff_config_data->mss_freq, p_l_atts->eff_num_ranks_per_dimm);
-           if(rc)
-           {
-               FAPI_ERR("Error from mss_lrdimm_eff_config()");
-               break;
-           }
-        }
- 
-        rc = mss_eff_config_rank_group(i_target_mba); if(rc) break;
-
-        // Removed call to mss_eff_config_cke_map(), 
-        //rc = mss_eff_config_cke_map(i_target_mba); if(rc) break;
-
-
-// Removed call to mss_eff_config_termination() for Palmetto and Habanero using ifdef "FAPI_MSSLABONLY", moving to liveVPD.
-// Note: Stradale, KG3, and DDR4 will still need ifdef "FAPI_MSSLABONLY"
-#ifdef FAPI_MSSLABONLY
-        // If MSS Lab/Development override, for now everything except DDR3 CDIMMs
-        if ((p_l_atts->eff_custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO) || (p_l_atts->eff_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)) {
-           rc = mss_eff_config_termination(i_target_mba); if(rc) break;
-           if(rc)
-           {
-               FAPI_ERR("Error from mss_eff_config_termination()");
-               break;
-           }
-        }
-#endif
-
-
-        // Removed call to mss_eff_config_thermal(), it is now called externally.
-        //rc = mss_eff_config_thermal(i_target_mba); if(rc) break;
-
-        rc = mss_eff_config_shmoo(i_target_mba); if(rc) break;
-
-
-
-        FAPI_INF("mss_eff_config on %s COMPLETE\n",
-                i_target_mba.toEcmdString());
-
-    } while(0);
-    /* free memory */
-    delete p_l_mss_eff_config_data;
-    delete p_l_spd_data;
-    delete p_l_atts;
-
-    return rc;
-} // end mss_eff_config()
-} // extern "C"
-
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.H
deleted file mode 100644
index b49c794ea..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.H
+++ /dev/null
@@ -1,86 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config.H $  */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config.H,v 1.3 2012/09/25 17:58:36 mjjones Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur
-//          /working/procedures/ipl/fapi/mss_eff_config.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config.H
-// *! DESCRIPTION : Header file for mss_eff_config.
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.4   |          |         |
-//   1.3   | kjpower  |27-AUG_12| Restructured code, added modularity
-//   1.2   | asaetow  |14-FEB-12| Fixed "fapi::" for hostboot, added "const",
-//         |          |         | renamed "i_target_mba", and changed comments.
-//   1.1   | asaetow  |03-NOV-11| First Draft.
-//------------------------------------------------------------------------------
-
-
-#ifndef MSS_EFF_CONFIG_H_
-#define MSS_EFF_CONFIG_H_
-
-//------------------------------------------------------------------------------
-// My Includes
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_eff_config_FP_t)(const fapi::Target i_target_mba);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config(): This function is the main functionw which calls
-//                          helper functions that read and verify spd data as
-//                          well as configure effective attributes.
-//
-// @param const fapi::Target i_target_mba: the fapi target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_config(const fapi::Target i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_EFF_CONFIG_H
-
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
deleted file mode 100644
index 5abb41da3..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C
+++ /dev/null
@@ -1,96 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_cke_map.C,v 1.5 2014/01/07 21:50:06 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_cke_map
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// This procedure takes in attributes and determines proper cke map.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.5   | bellows  |02-JAN-14| VPD attribute removal
-//   1.4   | kcook    |16-AUG-12| Added LRDIMM support.
-//   1.3   | asaetow  |14-NOV-12| Added ATTR_EFF_SPCKE_MAP. 
-//   1.2   | asaetow  |13-NOV-12| Added FAPI_ERR for else "Undefined IBM_TYPE". 
-//         |          |         | Removed outter NUM_DROPS_PER_PORT check.
-//   1.1   | asaetow  |07-NOV-12| First Draft.
-
-
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-
-extern "C" {
-
-//----------------------------------------------------------------------
-// ENUMs and CONSTs
-//----------------------------------------------------------------------
-
-
-
-//******************************************************************************
-//* name=mss_eff_config_cke_map, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba) {
-   fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-   const char * const PROCEDURE_NAME = "mss_eff_config_cke_map";
-   FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
-
-
-   // Define attribute array size
-
-   // Set attributes
-
-   FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
-   return rc;
-}
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
deleted file mode 100755
index 73bcd3fa7..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H
+++ /dev/null
@@ -1,76 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_cke_map.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_cke_map.H,v 1.1 2012/11/14 01:28:48 asaetow Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_cke_map.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_cke_map.H
-// *! DESCRIPTION : Header file for mss_eff_config_cke_map.
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.2   |          |         |
-//   1.1   | asaetow  |13-NOV-12| First Draft.
-
-
-#ifndef MSS_EFF_CONFIG_CKE_MAP_H_
-#define MSS_EFF_CONFIG_CKE_MAP_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-typedef fapi::ReturnCode (*mss_eff_config_cke_map_FP_t)(const fapi::Target i_target_mba);
-
-extern "C" {
-
-//******************************************************************************
-//* name=mss_eff_config_cke_map, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_cke_map(const fapi::Target i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_EFF_CONFIG_CKE_MAP_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
deleted file mode 100644
index 6b2b0c0df..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C
+++ /dev/null
@@ -1,339 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_rank_group.C,v 1.12 2014/04/01 17:10:21 asaetow Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_rank_group
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// This procedure takes in attributes and determines proper rank groupings that will be apply to the system and used during draminit_training and draminit_training_adv. Each valid rank in the system will be assigned to one of twelve attributes below. Only the primary rank group will be calibrated and have values stored in the delay registers.
-//    EFF_PRIMARY_RANK_GROUP0,    EFF_PRIMARY_RANK_GROUP1,    EFF_PRIMARY_RANK_GROUP2,    EFF_PRIMARY_RANK_GROUP3
-//    EFF_SECONDARY_RANK_GROUP0,  EFF_SECONDARY_RANK_GROUP1,  EFF_SECONDARY_RANK_GROUP2,  EFF_SECONDARY_RANK_GROUP3
-//    EFF_TERTIARY_RANK_GROUP0,   EFF_TERTIARY_RANK_GROUP1,   EFF_TERTIARY_RANK_GROUP2,   EFF_TERTIARY_RANK_GROUP3
-//    EFF_QUATERNARY_RANK_GROUP0, EFF_QUATERNARY_RANK_GROUP1, EFF_QUATERNARY_RANK_GROUP2, EFF_QUATERNARY_RANK_GROUP3
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.13  |          |         | 
-//   1.12  | asaetow  |31-MAR-13| Added FFDC error callout from Andrea's FW RAS review. 
-//         |          |         | NOTE: Do NOT pickup without memory_mss_eff_config_rank_group.xml v1.2 
-//   1.11  | kcook    |16-AUG-13| Added LRDIMM support.
-//   1.10  | asaetow  |17-APR-13| Removed 32G CDIMM 1R dualdrop workaround.
-//         |          |         | NOTE: Needs mss_draminit_training.C v1.57 or newer.
-//   1.9   | asaetow  |01-APR-13| Added 32G CDIMM 1R dualdrop workaround.
-//         |          |         | NOTE: Normally primary_rank_group0=0, primary_rank_group1=4.
-//   1.8   | asaetow  |29-AUG-12| Fixed variable init for rank_group to INVALID for PORT1. 
-//   1.7   | asaetow  |24-AUG-12| Fixed variable init for rank_group to INVALID. 
-//   1.6   | asaetow  |30-APR-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments.
-//         |          |         | Changed message to standardized format.
-//         |          |         | Changed BACKUP to Mark Bellows.
-//   1.5   | asaetow  |20-MAR-12| Changed EFF_CONFIG_RANK_GROUP_RC_ERROR_001A to RC_MSS_PLACE_HOLDER_ERROR temporary until Cronus is ready to pick up error code xml. 
-//   1.4   | asaetow  |08-FEB-12| Added INVALID(255) into ranks that do not exist.
-//         |          |         | Removed support for mix ATTR_EFF_NUM_RANKS_PER_DIMM within a port.
-//         |          |         | Changed "rc =" to "FAPI_SET_HWP_ERROR(rc, EFF_CONFIG_RANK_GROUP_RC_ERROR_001A)".
-//   1.3   | asaetow  |24-JAN-12| Removed all temp hard code work around and enabled FAPI_ATTR_GET(). 
-//         |          |         | Added mem_attr write back support, enabled FAPI_ATTR_SET().
-//         |          |         | Removed triple-drop support.
-//         |          |         | Changed PORT_SIZE and DIMM_SIZE to const 2 to match mem_attr. 
-//         |          |         | Added extern "C" so that procedure can be run independently.
-//   1.2   | asaetow  |03-NOV-11| Fixed to comply with mss_eff_config_rank_group.H
-//   1.1   | asaetow  |01-NOV-11| First Draft.
-
-
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-
-//----------------------------------------------------------------------
-// ENUMs
-//----------------------------------------------------------------------
-enum {
-   CDIMM = 0,
-   RDIMM = 1,
-   UDIMM = 2,
-   LRDIMM = 3,
-   INVALID = 255,
-};
-
-
-
-extern "C" {
-
-
-
-//******************************************************************************
-//* name=mss_eff_config_rank_group, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba) {
-   fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-   const char * const PROCEDURE_NAME = "mss_eff_config_rank_group";
-   const fapi::Target& TARGET_MBA = i_target_mba;
-   FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
-
-   const uint8_t PORT_SIZE = 2;
-   const uint8_t DIMM_SIZE = 2;
-   // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2,
-   // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,
-   uint8_t num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
-   uint8_t dram_gen_u8;
-   uint8_t dimm_type_u8;
-
-   rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, num_ranks_per_dimm_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, dram_gen_u8); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, dimm_type_u8); if(rc) return rc;
-
-   uint8_t primary_rank_group0_u8array[PORT_SIZE];
-   uint8_t primary_rank_group1_u8array[PORT_SIZE];
-   uint8_t primary_rank_group2_u8array[PORT_SIZE];
-   uint8_t primary_rank_group3_u8array[PORT_SIZE];
-   uint8_t secondary_rank_group0_u8array[PORT_SIZE];
-   uint8_t secondary_rank_group1_u8array[PORT_SIZE];
-   uint8_t secondary_rank_group2_u8array[PORT_SIZE];
-   uint8_t secondary_rank_group3_u8array[PORT_SIZE];
-   uint8_t tertiary_rank_group0_u8array[PORT_SIZE];
-   uint8_t tertiary_rank_group1_u8array[PORT_SIZE];
-   uint8_t tertiary_rank_group2_u8array[PORT_SIZE];
-   uint8_t tertiary_rank_group3_u8array[PORT_SIZE];
-   uint8_t quanternary_rank_group0_u8array[PORT_SIZE];
-   uint8_t quanternary_rank_group1_u8array[PORT_SIZE];
-   uint8_t quanternary_rank_group2_u8array[PORT_SIZE];
-   uint8_t quanternary_rank_group3_u8array[PORT_SIZE];
-
-   for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) {
-      //Removed 32G CDIMM 1R dualdrop workaround.
-      //NOTE: Needs mss_draminit_training.C v1.57 or newer.
-      //if ((dimm_type_u8 == CDIMM) && (num_ranks_per_dimm_u8array[cur_port][0] == 1) && (num_ranks_per_dimm_u8array[cur_port][1] == 1)) {
-         // NOTE: 32G CDIMM 1R dualdrop workaround, normally primary_rank_group0=0, primary_rank_group1=4.
-         //primary_rank_group0_u8array[cur_port] = 0;
-         //primary_rank_group1_u8array[cur_port] = INVALID;
-         //primary_rank_group2_u8array[cur_port] = INVALID;
-         //primary_rank_group3_u8array[cur_port] = INVALID;
-         //secondary_rank_group0_u8array[cur_port] = 4;
-         //secondary_rank_group1_u8array[cur_port] = INVALID;
-         //secondary_rank_group2_u8array[cur_port] = INVALID;
-         //secondary_rank_group3_u8array[cur_port] = INVALID;
-         //tertiary_rank_group0_u8array[cur_port] = INVALID;
-         //tertiary_rank_group1_u8array[cur_port] = INVALID;
-         //tertiary_rank_group2_u8array[cur_port] = INVALID;
-         //tertiary_rank_group3_u8array[cur_port] = INVALID;
-         //quanternary_rank_group0_u8array[cur_port] = INVALID;
-         //quanternary_rank_group1_u8array[cur_port] = INVALID;
-         //quanternary_rank_group2_u8array[cur_port] = INVALID;
-         //quanternary_rank_group3_u8array[cur_port] = INVALID;
-      //} else if (dimm_type_u8 == LRDIMM) {
-      if (dimm_type_u8 == LRDIMM) {
-         primary_rank_group2_u8array[cur_port] = INVALID;
-         secondary_rank_group2_u8array[cur_port] = INVALID;
-         tertiary_rank_group2_u8array[cur_port] = INVALID;
-         quanternary_rank_group2_u8array[cur_port] = INVALID;
-
-         primary_rank_group3_u8array[cur_port] = INVALID;
-         secondary_rank_group3_u8array[cur_port] = INVALID;
-         tertiary_rank_group3_u8array[cur_port] = INVALID;
-         quanternary_rank_group3_u8array[cur_port] = INVALID;
-
-         // dimm 0 (far socket)
-         switch (num_ranks_per_dimm_u8array[cur_port][0]) {
-           case 4:               // 4 rank lrdimm
-                 primary_rank_group0_u8array[cur_port] = 0;
-                 secondary_rank_group0_u8array[cur_port] = 1;
-                 tertiary_rank_group0_u8array[cur_port] = 2;
-                 quanternary_rank_group0_u8array[cur_port] = 3;
-                 break;
-           case 8:               // 8 rank lrdimm falls through to 2 rank case
-         // Rank Multiplication mode needed, CS2 & CS3 used as address lines into LRBuffer
-         // RM=4 -> only 2 CS valid, each CS controls 4 ranks with CS2 & CS3 as address
-         // CS0 = rank 0, 2, 4, 6;  CS1 = rank 1, 3, 5, 7
-           case 2:               // 2 rank lrdimm
-                 primary_rank_group0_u8array[cur_port] = 0;
-                 secondary_rank_group0_u8array[cur_port] = 1;
-                 tertiary_rank_group0_u8array[cur_port] = INVALID;
-                 quanternary_rank_group0_u8array[cur_port] = INVALID;
-                 break;
-           case 1:               // 1 rank lrdimm
-                 primary_rank_group0_u8array[cur_port] = 0;
-                 secondary_rank_group0_u8array[cur_port] = INVALID;
-                 tertiary_rank_group0_u8array[cur_port] = INVALID;
-                 quanternary_rank_group0_u8array[cur_port] = INVALID;
-                 break;
-           default:              // not 1, 2, 4, or 8 ranks
-                 primary_rank_group0_u8array[cur_port] = INVALID;
-                 secondary_rank_group0_u8array[cur_port] = INVALID;
-                 tertiary_rank_group0_u8array[cur_port] = INVALID;
-                 quanternary_rank_group0_u8array[cur_port] = INVALID;
-         }
-         // dimm 1 (near socket)
-         switch (num_ranks_per_dimm_u8array[cur_port][1]) {
-           case 4:               // 4 rank lrdimm
-                 primary_rank_group1_u8array[cur_port] = 4;
-                 secondary_rank_group1_u8array[cur_port] = 5;
-                 tertiary_rank_group1_u8array[cur_port] = 6;
-                 quanternary_rank_group1_u8array[cur_port] = 7;
-                 break;
-           case 8:               // 8 rank lrdimm falls through to case 2
-         // Rank Multiplication mode needed, CS6 & CS7 used as address lines into LRBuffer
-         // RM=4 -> only 2 CS valid, each CS controls 4 ranks with CS6 & CS7 as address
-         // CS4 = rank 0, 2, 4, 6;  CS5 = rank 1, 3, 5, 7
-           case 2:               // 2 rank lrdimm, RM=0
-                 primary_rank_group1_u8array[cur_port] = 4;
-                 secondary_rank_group1_u8array[cur_port] = 5;
-                 tertiary_rank_group1_u8array[cur_port] = INVALID;
-                 quanternary_rank_group1_u8array[cur_port] = INVALID;
-                 break;
-           case 1:               // 1 rank lrdimm
-                 primary_rank_group1_u8array[cur_port] = 4;
-                 secondary_rank_group1_u8array[cur_port] = INVALID;
-                 tertiary_rank_group1_u8array[cur_port] = INVALID;
-                 quanternary_rank_group1_u8array[cur_port] = INVALID;
-                 break;
-           default:              // not 1, 2, 4, or 8 ranks
-                 primary_rank_group1_u8array[cur_port] = INVALID;
-                 secondary_rank_group1_u8array[cur_port] = INVALID;
-                 tertiary_rank_group1_u8array[cur_port] = INVALID;
-                 quanternary_rank_group1_u8array[cur_port] = INVALID;
-         }
-
-      } else { // RDIMM or CDIMM
-         if ((num_ranks_per_dimm_u8array[cur_port][0] > 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) {
-            primary_rank_group0_u8array[cur_port] = 0;
-            if (num_ranks_per_dimm_u8array[cur_port][0] > 1) {
-               primary_rank_group1_u8array[cur_port] = 1;
-            } else {
-               primary_rank_group1_u8array[cur_port] = INVALID;
-            }
-            if (num_ranks_per_dimm_u8array[cur_port][0] > 2) {
-               primary_rank_group2_u8array[cur_port] = 2;
-               primary_rank_group3_u8array[cur_port] = 3;
-            } else {
-               primary_rank_group2_u8array[cur_port] = INVALID;
-               primary_rank_group3_u8array[cur_port] = INVALID;
-            }
-            secondary_rank_group0_u8array[cur_port] = INVALID;
-            secondary_rank_group1_u8array[cur_port] = INVALID;
-            secondary_rank_group2_u8array[cur_port] = INVALID;
-            secondary_rank_group3_u8array[cur_port] = INVALID;
-         } else if ((num_ranks_per_dimm_u8array[cur_port][0] > 0) && (num_ranks_per_dimm_u8array[cur_port][1] > 0)) {
-            if (num_ranks_per_dimm_u8array[cur_port][0] != num_ranks_per_dimm_u8array[cur_port][1]) {
-               FAPI_ERR("%s: FAILED!", PROCEDURE_NAME);
-               FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port);
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RANK_GROUP_NON_MATCH_RANKS);
-               return rc;
-            }
-            primary_rank_group0_u8array[cur_port] = 0;
-            primary_rank_group1_u8array[cur_port] = 4;
-            primary_rank_group2_u8array[cur_port] = INVALID;
-            primary_rank_group3_u8array[cur_port] = INVALID;
-            secondary_rank_group0_u8array[cur_port] = INVALID;
-            secondary_rank_group1_u8array[cur_port] = INVALID;
-            secondary_rank_group2_u8array[cur_port] = INVALID;
-            secondary_rank_group3_u8array[cur_port] = INVALID;
-            if (num_ranks_per_dimm_u8array[cur_port][0] == 2) {
-               primary_rank_group2_u8array[cur_port] = 1;
-               primary_rank_group3_u8array[cur_port] = 5;
-            } else if (num_ranks_per_dimm_u8array[cur_port][0] == 4) {
-               primary_rank_group2_u8array[cur_port] = 2;
-               primary_rank_group3_u8array[cur_port] = 6;
-               secondary_rank_group0_u8array[cur_port] = 1;
-               secondary_rank_group1_u8array[cur_port] = 5;
-               secondary_rank_group2_u8array[cur_port] = 3;
-               secondary_rank_group3_u8array[cur_port] = 7;
-            } else if (num_ranks_per_dimm_u8array[cur_port][0] != 1) {
-               FAPI_ERR("%s: FAILED!", PROCEDURE_NAME);
-               FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port);
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RANK_GROUP_NUM_RANKS_NEQ1);
-               return rc;
-            }
-         } else if ((num_ranks_per_dimm_u8array[cur_port][0] == 0) && (num_ranks_per_dimm_u8array[cur_port][1] == 0)) {
-            primary_rank_group0_u8array[cur_port] = INVALID;
-            primary_rank_group1_u8array[cur_port] = INVALID;
-            primary_rank_group2_u8array[cur_port] = INVALID;
-            primary_rank_group3_u8array[cur_port] = INVALID;
-            secondary_rank_group0_u8array[cur_port] = INVALID;
-            secondary_rank_group1_u8array[cur_port] = INVALID;
-            secondary_rank_group2_u8array[cur_port] = INVALID;
-            secondary_rank_group3_u8array[cur_port] = INVALID;
-         } else {
-            FAPI_ERR("%s: FAILED!", PROCEDURE_NAME);
-            FAPI_ERR("Plug rule violation, num_ranks_per_dimm=%d[0],%d[1] on %s PORT%d!", num_ranks_per_dimm_u8array[cur_port][0], num_ranks_per_dimm_u8array[cur_port][1], i_target_mba.toEcmdString(), cur_port);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_RANK_GROUP_NO_MATCH);
-            return rc;
-         }
-         tertiary_rank_group0_u8array[cur_port] = INVALID;
-         tertiary_rank_group1_u8array[cur_port] = INVALID;
-         tertiary_rank_group2_u8array[cur_port] = INVALID;
-         tertiary_rank_group3_u8array[cur_port] = INVALID;
-         quanternary_rank_group0_u8array[cur_port] = INVALID;
-         quanternary_rank_group1_u8array[cur_port] = INVALID;
-         quanternary_rank_group2_u8array[cur_port] = INVALID;
-         quanternary_rank_group3_u8array[cur_port] = INVALID;
-      }
-      FAPI_INF("P[%02d][%02d][%02d][%02d],S[%02d][%02d][%02d][%02d],T[%02d][%02d][%02d][%02d],Q[%02d][%02d][%02d][%02d] on %s PORT%d.", primary_rank_group0_u8array[cur_port], primary_rank_group1_u8array[cur_port], primary_rank_group2_u8array[cur_port], primary_rank_group3_u8array[cur_port], secondary_rank_group0_u8array[cur_port], secondary_rank_group1_u8array[cur_port], secondary_rank_group2_u8array[cur_port], secondary_rank_group3_u8array[cur_port], tertiary_rank_group0_u8array[cur_port], tertiary_rank_group1_u8array[cur_port], tertiary_rank_group2_u8array[cur_port], tertiary_rank_group3_u8array[cur_port], quanternary_rank_group0_u8array[cur_port], quanternary_rank_group1_u8array[cur_port], quanternary_rank_group2_u8array[cur_port], quanternary_rank_group3_u8array[cur_port], i_target_mba.toEcmdString(), cur_port);
-   }
-   rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP0, &i_target_mba, primary_rank_group0_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP1, &i_target_mba, primary_rank_group1_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP2, &i_target_mba, primary_rank_group2_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_PRIMARY_RANK_GROUP3, &i_target_mba, primary_rank_group3_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP0, &i_target_mba, secondary_rank_group0_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP1, &i_target_mba, secondary_rank_group1_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP2, &i_target_mba, secondary_rank_group2_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SECONDARY_RANK_GROUP3, &i_target_mba, secondary_rank_group3_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP0, &i_target_mba, tertiary_rank_group0_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP1, &i_target_mba, tertiary_rank_group1_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP2, &i_target_mba, tertiary_rank_group2_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_TERTIARY_RANK_GROUP3, &i_target_mba, tertiary_rank_group3_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP0, &i_target_mba, quanternary_rank_group0_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP1, &i_target_mba, quanternary_rank_group1_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP2, &i_target_mba, quanternary_rank_group2_u8array); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_QUATERNARY_RANK_GROUP3, &i_target_mba, quanternary_rank_group3_u8array); if(rc) return rc;
-
-   FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
-   return rc;
-}
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.H
deleted file mode 100644
index 2a074b73f..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.H
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_rank_group.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_rank_group.H,v 1.3 2012/02/15 01:39:30 asaetow Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_rank_group.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_rank_group.H
-// *! DESCRIPTION : Header file for mss_eff_config_rank_group.
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.4   |          |         |
-//   1.3   | asaetow  |14-FEB-12| Fixed "fapi::" for hostboot, added "const", renamed "i_target_mba", and changed comments.
-//   1.2   | asaetow  |24-JAN-12| Added typedef and extern "C".
-//   1.1   | asaetow  |03-NOV-11| First Draft.
-
-
-#ifndef MSS_EFF_CONFIG_RANK_GROUP_H_
-#define MSS_EFF_CONFIG_RANK_GROUP_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-typedef fapi::ReturnCode (*mss_eff_config_rank_group_FP_t)(const fapi::Target i_target_mba);
-
-extern "C" {
-
-//******************************************************************************
-//* name=mss_eff_config_rank_group, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_rank_group(const fapi::Target i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_EFF_CONFIG_RANK_GROUP_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C
deleted file mode 100644
index 47eaf1034..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C
+++ /dev/null
@@ -1,209 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_shmoo.C,v 1.10 2014/01/26 13:52:49 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_shmoo
-// *! DESCRIPTION : Additional attributes for MCBIST 
-// *! OWNER NAME  : Saurabh Chadha    Email: sauchadh@in.ibm.com
-// *! BACKUP NAME :                   Email: 
-// *! ADDITIONAL COMMENTS :
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.1   | sauchadh |26-Feb-13| Added MCBIST related attributes
-//   1.2   | sauchadh |13-Mar-13| Added Schmoo related attributes from mss_eff_config.C 
-//   1.3   | sauchadh |17-Apr-13| Changed mcbist_addr_modes value to 1
-//   1.4   | sauchadh |10-May-13| Fixed FW comments
-//   1.5   | sauchadh |15-May-13| Fixed FW comments
-//   1.6   | sauchadh |6-Jun-13 | Added some more attributes
-//   1.7   | bellows  |09-Aug-13| Set default pattern to 0, per Sarvanan Req
-//   1.8   | sauchadh |2- Sep-13| Added random seed attribute
-//   1.9   | sauchadh |20-Dec-13| change test type to 38 
-//   1.10  | bellows  |26-Jan-14| moved driver attribute setting from eff termination 
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-extern "C" {
-
-
-
-//******************************************************************************
-//* name=mss_eff_config_shmoo, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target & i_target_mba) {
-   fapi::ReturnCode rc; 
-   const char * const PROCEDURE_NAME = "mss_eff_config_shmoo";
-   FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
-
-   uint32_t datapattern=0; // mdb - type 8 is not valid per Saravanan's Sametime
-   uint32_t testtype=37;  // SIMPLE_FIX_RF
-   uint8_t addr_modes=1;
-   uint8_t  rank=0;
-   uint64_t start_addr=0;
-   uint64_t end_addr=0;
-   uint8_t error_capture=0;
-   uint64_t max_timeout=0;
-   uint8_t print_port=0;
-   uint8_t stop_on_error=0;
-   uint32_t data_seed=0;
-   uint8_t addr_inter=0;
-   uint8_t addr_num_rows=0;
-   uint8_t addr_num_cols=0;
-   uint8_t addr_rank=0;
-   uint8_t addr_bank=0;
-   uint8_t addr_slave_rank_on=0;
-   uint64_t adr_str_map=0;
-   uint8_t addr_rand=0;
-   uint8_t shmoo_mode=0;
-   uint8_t shmoo_addr_mode=3;
-   uint8_t shmoo_param_valid=0;
-   uint8_t shmoo_test_valid=0;
-   uint8_t wr_eye_min_margin=0x46;
-   uint8_t rd_eye_min_margin=0x46;
-   uint8_t dqs_clk_min_margin=0x8c;
-   uint8_t rd_gate_min_margin=0x64;
-   uint8_t adr_cmd_min_margin=0x8c;
-   uint32_t cen_rd_vref_shmoo[2] = { 0x00000000, 0x00000000 };
-   uint32_t dram_wr_vref_schmoo[2]= { 0x00000000 ,0x00000000 };
-   uint32_t cen_rcv_imp_dq_dqs_schmoo[2]= { 0x00000000, 0x00000000 };
-   uint32_t cen_drv_imp_dq_dqs_schmoo[2]= { 0x00000000, 0x00000000 };
-   uint8_t cen_drv_imp_cntl_schmoo[2] = { 0x00, 0x00 };
-   uint8_t cen_drv_imp_clk_schmoo[2] =  { 0x00, 0x00 };
-   uint8_t cen_drv_imp_spcke_schmoo[2] = { 0x00, 0x00 }; 
-   uint8_t cen_slew_rate_dq_dqs_schmoo[2] = { 0x00, 0x00 }; 
-   uint8_t cen_slew_rate_cntl_schmoo[2] = { 0x00, 0x00 };
-   uint8_t cen_slew_rate_addr_schmoo[2] = { 0x00, 0x00 };
-   uint8_t cen_slew_rate_clk_schmoo[2] = { 0x00, 0x00 };
-   uint8_t cen_slew_rate_spcke_schmoo[2] = { 0x00, 0x00 };
-   uint8_t mcb_print_disable=0;
-   uint8_t mcb_data_en=0;
-   uint8_t mcb_user_rank=0;
-   uint8_t mcb_user_bank=0;
-   uint8_t shmoo_mul_setup_call=0;
-   uint32_t rand_seed_val=0;
-   uint8_t rand_seed_type=0x01;
-
-   // space for VPD attributes that need to be read from VPD and put into scratch pads
-   const uint8_t PORT_SIZE = 2;
-
-   uint32_t attr_eff_cen_rd_vref[PORT_SIZE];
-   uint32_t attr_eff_dram_wr_vref[PORT_SIZE];
-   uint8_t attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE];
-   uint8_t attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE];
-   uint8_t attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE];
-   
-
-   // get these attributes from the VPD but allow the code to override later
-   rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
-
-   // attriubtes that are needing to be copied from VPD into scratch pads
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
-
-   
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINTING_DISABLE, &i_target_mba, mcb_print_disable); if(rc) return rc; 
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_ENABLE, &i_target_mba, mcb_data_en); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_USER_RANK, &i_target_mba, mcb_user_rank); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_USER_BANK, &i_target_mba, mcb_user_bank); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_SCHMOO_MULTIPLE_SETUP_CALL, &i_target_mba,shmoo_mul_setup_call); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_PATTERN, &i_target_mba, datapattern); if(rc) return rc; 
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_TEST_TYPE, &i_target_mba, testtype); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_MODES, &i_target_mba, addr_modes); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_RANK, &i_target_mba, rank); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_START_ADDR, &i_target_mba, start_addr); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_END_ADDR, &i_target_mba, end_addr); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ERROR_CAPTURE, &i_target_mba, error_capture); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_MAX_TIMEOUT, &i_target_mba, max_timeout); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_PRINT_PORT, &i_target_mba, print_port); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_STOP_ON_ERROR, &i_target_mba, stop_on_error); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_DATA_SEED, &i_target_mba, data_seed); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_INTER, &i_target_mba, addr_inter); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_NUM_ROWS, &i_target_mba, addr_num_rows); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_NUM_COLS, &i_target_mba, addr_num_cols); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_RANK, &i_target_mba, addr_rank); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_BANK, &i_target_mba, addr_bank); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_SLAVE_RANK_ON, &i_target_mba, addr_slave_rank_on); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_STR_MAP, &i_target_mba, adr_str_map); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_ADDR_RAND, &i_target_mba, addr_rand); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_MODE, &i_target_mba, shmoo_mode); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_MODE, &i_target_mba, shmoo_addr_mode); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, shmoo_param_valid); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, shmoo_test_valid); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_WR_EYE_MIN_MARGIN, &i_target_mba, wr_eye_min_margin); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_EYE_MIN_MARGIN, &i_target_mba, rd_eye_min_margin); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_DQS_CLK_MIN_MARGIN, &i_target_mba, dqs_clk_min_margin); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_RD_GATE_MIN_MARGIN, &i_target_mba, rd_gate_min_margin); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_SCHMOO_ADDR_CMD_MIN_MARGIN, &i_target_mba, adr_cmd_min_margin); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, cen_rd_vref_shmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, dram_wr_vref_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, cen_rcv_imp_dq_dqs_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, cen_drv_imp_dq_dqs_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CNTL_SCHMOO, &i_target_mba, cen_drv_imp_cntl_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_CLK_SCHMOO, &i_target_mba, cen_drv_imp_clk_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_SPCKE_SCHMOO, &i_target_mba, cen_drv_imp_spcke_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba, cen_slew_rate_dq_dqs_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CNTL_SCHMOO, &i_target_mba, cen_slew_rate_cntl_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_ADDR_SCHMOO, &i_target_mba, cen_slew_rate_addr_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_CLK_SCHMOO, &i_target_mba, cen_slew_rate_clk_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_SPCKE_SCHMOO, &i_target_mba, cen_slew_rate_spcke_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_RANDOM_SEED_VALUE, &i_target_mba, rand_seed_val); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_MCBIST_RANDOM_SEED_TYPE, &i_target_mba, rand_seed_type); if(rc) return rc;
-   
-
-       
-   FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
-   return rc;
-}
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H
deleted file mode 100644
index 8ff456a4e..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H
+++ /dev/null
@@ -1,75 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_shmoo.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_shmoo.H,v 1.1 2013/02/26 12:38:36 lapietra Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_shmoo.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_shmoo.H
-// *! DESCRIPTION : Header file for mss_eff_config_shmoo.C
-// *! OWNER NAME  : Saurabh Chadha    Email: sauchadh@in.ibm.com 
-// *! BACKUP NAME :                   Email: 
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.1   | sauchadh |26-Feb-13| First Draft
-
-
-#ifndef MSS_EFF_CONFIG_SHMOO_H_
-#define MSS_EFF_CONFIG_SHMOO_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-typedef fapi::ReturnCode (*mss_eff_config_shmoo_FP_t)(const fapi::Target i_target_mba);
-
-extern "C" {
-
-//******************************************************************************
-//* name=mss_eff_config_shmoo, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_shmoo(const fapi::Target i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_EFF_CONFIG_SHMOO_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
deleted file mode 100644
index fa71f0490..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C
+++ /dev/null
@@ -1,2398 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_termination.C,v 1.51 2015/09/04 18:16:24 thi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_termination
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Dave Cadigan      Email: dcadiga@us.ibm.com
-// *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// This procedure is a place holder for attributes set by the machine parsable workbook.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.50  | sglancy  |28-Aug-15| Added RC checks - addressed FW comments
-//   1.49  | kmack    |05-Aug-15| Commented out FAPI_DDR4 code
-//   1.48  | asaetow  |01-OCT-14| Added setting for single-drop 4G1Rx8 and 16G2Rx4 from Ken/Anil for habanero at 1333Mbps under "rdimm_habanero_1333_r10_mba0", "rdimm_habanero_1333_r10_mba1", "rdimm_habanero_1333_r20_mba0", and "rdimm_habanero_1333_r20_mba1".
-//         |          |         | Added place holder setting for dual-drop 4G1Rx8 and 16G2Rx4 for habanero at 1333Mbps under "rdimm_habanero_1333_r11_mba0", "rdimm_habanero_1333_r11_mba1", "rdimm_habanero_1333_r22_mba0", and "rdimm_habanero_1333_r22_mba1".
-//   1.47  | dcadiga  |07-APR-14| FFDC Updates
-//   1.46  | kcook    |14-MAR-14| Fixed create_db_ddr4 stub function definition
-//   1.45  | kcook    |14-MAR-14| Added DDR4 support
-//   1.44  | mjjones  |07-MAR-14| Only compile if FAPI_MSSLABONLY defined
-//   1.43  | dcadiga  |04-MAR-14| Added in ISDimm support for KG
-//   1.42  | asaetow  |22-JAN-14| Fixed target "const fapi::Target" to "const fapi::Target&" for mss_eff_config.C v1.38 and mss_eff_config_termination.H v1.2
-//   1.41  | dcadiga  |13-JAN-14| Removed checking of dimm type attribute for CDIMM, replaced with custom dimm type attribute
-//   1.40  | bellows  |02-JAN-14| VPD attribute removal
-//   1.39  | bellows  |25-NOV-13| removed dimm spare temp, added using namespace fapi
-//   1.38  | dcadiga  |22-NOV-13| DDR4 ATTR_VREF_DQ_TRAIN_VALUE change for Menlo (0 to 16)
-//   1.37  | dcadiga  |22-NOV-13| New Settings for RC/A and RC/C from Nov5/2013 Spreadsheet, DDR4 Enum Update
-//   1.36  | bellows  |19-SEP-13| Patched the AM keyword workaround.for >1 ranks
-//   1.35  | bellows  |16-SEP-13| Hostboot compile update.
-//   1.34  | kcook    |13-SEP-13| Updated define FAPI_LRDIMM token.
-//   1.33  | bellows  |12-SEP-13| set_vpd_dimm_spare function added before AM keyword shows up
-//   1.32  | kcook    |27-AUG-13| Removed LRDIMM support to mss_lrdimm_funcs.C.
-//   1.31  | kcook    |16-AUG-13| Added LRDIMM support.
-//   1.30  | dcadiga  |07-AUG-13| Fixed hostboot compile issue
-//   1.29  | dcadiga  |05-AUG-13| KG3 allowed, ifdef removed for lab card uint declaration, added 4R support to 1600, changed 4Rx4 / 4Rx8 RCD Drive Settings
-//   1.28  | asaetow  |05-AUG-13| Added temp workaround for incorrect byte33 SPD data in early lab OLD 16G/32G CDIMMs.
-//         |          |         | NOTE: Do NOT pickup without mss_eff_config.C v1.27 or newer, contains EFF_STACK_TYPE_DDP_QDP support.
-//   1.27  | bellows  |24-JUL-13| KG3 support #def for cronus only compiles
-//   1.26  | dcadiga  |28-JUN-13| Fixed checking of lab_only_rc
-//   1.25  | dcadiga  |26-JUN-13| B4 Change to run regardless of ranks configured, Set code to point back to B4 settings instead of B settings (was test mode)
-//   1.24  | dcadiga  |25-JUN-13| KG3 Settings, RLO Settings,WLO,GPO Settings. KG3 DISABLED FOR NOW.  Also added lab_rc check and set
-//   1.23  | dcadiga  |03-JUN-13| Updated B4 settings and 2 Socket ISDIMM Configs
-//   1.22  | asaetow  |17-MAY-13| Added DDR4 attr and ATTR_EFF_DRAM_ADDRESS_MIRRORING attr.
-//   1.21  | dcadiga  |07-MAY-13| Fixed RC/A Clk Drive and Impedance Settings, Added RC B4 and some patches to make it work, Added in fix for AL in 2N mode
-//   1.20  | dcadiga  |30-APR-13| Fixed Hostboot Compile Error LN 972
-//   1.19  | dcadiga  |19-APR-13| Added Cdimm RCB/RCC, changed RDIMM settings for MBA0 so that a 1R card will work and a 4R card will work
-//   1.18  | dcadiga  |10-APR-13| Added UDIMM for ICICLE DDR4, fixed DD0 Clk shift
-//   1.17  | asaetow  |26-MAR-13| Removed width check for RDIMM MBA0 4Rank 1333.
-//   1.16  | dcadiga  |25-MAR-13| Added in 2N Addressing Mode.
-//   1.15  | dcadiga  |14-MAR-13| Fixed simulation issue.
-//   1.14  | dcadiga  |12-MAR-13| Code re-write for new dimms.  Confirmed working on all systems
-//   1.13  | asaetow  |19-FEB-12| Changed default SI value for CDIMM, turned of Rtt_NOM and disabled Rtt_WR for DIMM1.
-//   1.12  | asaetow  |07-FEB-12| Added check for Centaur EC10 ADR Centerlane NWELL workaround.
-//   1.11  | asaetow  |22-DEC-12| Added CDIMM workaround for EC10 ADR Centerlane race condition, subtract 32ticks.
-//         |          |         | NOTE: Need EC check for Centaur EC10 ADR Centerlane NWELL workaround.
-//   1.10  | asaetow  |22-DEC-12| Added Centaur EC10 ADR Centerlane PR=0x7F workaround for NWELL LVS issue.
-//         |          |         | NOTE: Need EC check for Centaur EC10 ADR Centerlane NWELL workaround.
-//         |          |         | Fixed (l_attr_is_simulation || 1) to (l_attr_is_simulation != 0) from v1.8 and v1.9.
-//   1.9   | bellows  |12-DEC-12| Changed phase rotators for sim to 0x40 for clocks
-//   1.8   | bellows  |06-DEC-12| Added sim leg for rotator values
-//   1.7   | asaetow  |18-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0x7F back to 0xFF.
-//   1.6   | asaetow  |17-NOV-12| Fixed uint8_t attr_eff_odt_wr for 4R RDIMMs.
-//   1.5   | asaetow  |17-NOV-12| Added PR settings.
-//         |          |         | Fixed RCD settings for RDIMM.
-//   1.4   | asaetow  |17-NOV-12| Changed ATTR_MSS_CAL_STEP_ENABLE from 0xFF to 0x7F.
-//   1.3   | asaetow  |05-NOV-12| Added Paul's SI value for pre-machine parsable workbook.
-//         |          |         | NOTE: DO NOT pick-up without memory_attributes.xml v1.45 or newer.
-//   1.2   | asaetow  |05-SEP-12| Added ATTR_MSS_CAL_STEP_ENABLE.
-//   1.1   | asaetow  |30-APR-12| First Draft.
-
-#ifdef FAPI_MSSLABONLY
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-#include <mss_lrdimm_funcs.H>
-#include <mss_ddr4_funcs.H>
-#include <mss_lrdimm_ddr4_funcs.H>
-
-using namespace fapi;
-
-
-
-#ifndef FAPI_LRDIMM
-using namespace fapi;
-fapi::ReturnCode mss_lrdimm_rewrite_odt( const Target& i_target_mba,
-                                  uint32_t *p_b_var_array,
-                                  uint32_t *var_array_p_array[5])
-{
-   ReturnCode rc;
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_REWRITE_INVALID_EXEC);
-   return rc;
-
-}
-ReturnCode mss_lrdimm_term_atts(const Target& i_target_mba)
-{
-   ReturnCode rc;
-
-
-   FAPI_ERR("Invalid exec of LRDIMM function on %s!", i_target_mba.toEcmdString());
-   FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_TERM_INVALID_EXEC);
-   return rc;
-
-}
-#endif
-
-//----------------------------------------------------------------------
-// ENUMs and CONSTs
-//----------------------------------------------------------------------
-
-// Define attribute array size
-const uint8_t PORT_SIZE = 2;
-const uint8_t DIMM_SIZE = 2;
-const uint8_t RANK_SIZE = 4;
-
-// Define the size of the array that holds the values to set - Now done when we determine if isdimm
-const uint8_t STORE_ARRAY_SIZE = 10;
-
-//Declare all Static Arrays
-
-uint32_t attr_eff_dimm_rcd_ibt[PORT_SIZE][DIMM_SIZE];
-uint8_t attr_eff_dimm_rcd_mirror_mode[PORT_SIZE][DIMM_SIZE];
-uint32_t attr_eff_cen_rd_vref[PORT_SIZE];
-uint32_t attr_eff_dram_wr_vref[PORT_SIZE];
-uint8_t attr_eff_dram_wrddr4_vref[PORT_SIZE];
-uint8_t attr_eff_cen_rcv_imp_dq_dqs[PORT_SIZE];
-uint8_t attr_eff_cen_drv_imp_dq_dqs[PORT_SIZE];
-uint8_t attr_eff_cen_slew_rate_dq_dqs[PORT_SIZE];
-uint8_t l_attr_vpd_2n_mode_enabled;
-uint8_t attr_eff_dram_al;
-uint8_t attr_eff_rlo[PORT_SIZE];
-uint8_t attr_eff_wlo[PORT_SIZE];
-uint8_t attr_eff_gpo[PORT_SIZE];
-uint8_t attr_eff_dram_2n_mode_enabled[PORT_SIZE];
-
-
-
-
-//Declare all Static Arrays
-
-uint8_t attr_vpd_dram_ron[PORT_SIZE][DIMM_SIZE];
-uint8_t attr_vpd_dram_rtt_nom[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-uint8_t attr_vpd_dram_rtt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-uint8_t attr_vpd_odt_rd[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-uint8_t attr_vpd_odt_wr[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-uint8_t attr_vpd_cen_drv_imp_cntl[PORT_SIZE];
-uint8_t attr_vpd_cen_drv_imp_addr[PORT_SIZE];
-uint8_t attr_vpd_cen_drv_imp_clk[PORT_SIZE];
-uint8_t attr_vpd_cen_drv_imp_spcke[PORT_SIZE];
-uint8_t attr_vpd_cen_slew_rate_cntl[PORT_SIZE];
-uint8_t attr_vpd_cen_slew_rate_addr[PORT_SIZE];
-uint8_t attr_vpd_cen_slew_rate_clk[PORT_SIZE];
-uint8_t attr_vpd_cen_slew_rate_spcke[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_clk_p0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_clk_p1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_clk_p0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_clk_p1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a2[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a3[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a4[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a5[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a6[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a7[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a8[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a9[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a10[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a11[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a12[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a13[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a14[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_a15[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_bA0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_bA1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_bA2[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_casn[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_rasn[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_cmd_wen[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_par[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m_actn[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_cke0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_cke1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_cke2[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_cke3[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_csn0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_csn1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_csn2[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_csn3[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_odt0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m0_cntl_odt1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_cke0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_cke1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_cke2[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_cke3[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_csn0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_csn1[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_csn2[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_csn3[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_odt0[PORT_SIZE];
-uint8_t attr_vpd_cen_phase_rot_m1_cntl_odt1[PORT_SIZE];
-
-
-//Declare the different dimms here:
-//Cdimm rc_A
-uint32_t cdimm_default[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
-};
-
-uint32_t cdimm_rca_1r_1333_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
-};
-
-uint32_t cdimm_rca_1r_1600_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
-};
-
-//Cdimm rc_A DD1.0
-
-//RCB
-
-//RCB4
-
-uint32_t cdimm_rcb4_2r_1600_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,93,91,90,92,4,5,5,4,0,0,4,2,5,4,10,3,6,3,5,10,9,8,11,12,11,11,11,12,10,0,27,0,2,0,0,0,6,0,10,0,29,0,16,0,0,0,8,0,91,98,93,98,11,8,12,4,1,0,3,0,10,4,12,5,10,8,6,10,7,6,11,13,16,13,7,5,10,0,30,0,8,0,0,0,7,0,12,0,31,0,10,0,0,0,4,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t cdimm_rcb4_2r_1600_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM20,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,108,117,108,117,18,18,17,22,21,22,24,24,28,17,15,18,17,20,18,15,19,21,14,14,18,14,15,14,10,0,55,0,15,0,0,0,0,0,13,0,56,0,0,0,0,0,13,0,117,114,117,113,21,22,26,22,23,24,25,24,25,27,18,26,20,24,26,20,21,22,19,20,17,18,24,29,0,0,53,0,1,0,0,0,0,0,0,0,52,0,11,0,0,0,1,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-//RCC
-
-/*
-
-//RDIMM A/B Ports MBA0 Glacier
-uint32_t rdimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r20e_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r20e_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r20b_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r20b_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r40_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-
-//RDIMM C/D Ports MBA1 Glacier
-
-uint32_t rdimm_glacier_1333_r10_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r20e_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r20e_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r20b_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r20b_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1066_r40_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r11_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r11_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r22e_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r22e_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1333_r22b_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1600_r22b_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_glacier_1066_r44_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
-};
-
-//UDIMM TEMP FOR JAKE ICICLE
-uint32_t udimm_glacier_1600_r10_mba0[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
-};
-
-uint32_t udimm_glacier_1600_r10_mba1[STORE_ARRAY_SIZE] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF
-};
-
-
-//KG3
-
-uint32_t rdimm_kg3_1333_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1333_r1_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r1_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r1_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1333_r2b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1333_r2b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r2b_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-
-uint32_t rdimm_kg3_1600_r2b_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-
-uint32_t rdimm_kg3_1333_r2e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1333_r2e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r2e_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r2e_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1333_r4_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1333_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r4_mba0[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-
-uint32_t rdimm_kg3_1600_r4_mba1[STORE_ARRAY_SIZE] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON
-};
-*/
-
-
-//RDIMM A/B Ports MBA0 Glacier
-uint32_t rdimm_glacier_1600_r10_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r20e_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,67,0,0,0,1,2,2,4,0,1,3,2,5,2,6,3,3,3,2,7,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,1,3,0,0,3,7,2,9,1,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r20e_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,66,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,75,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r20b_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,2,2,4,0,1,3,2,5,2,6,3,3,3,2,6,7,7,6,8,6,7,7,0,2,10,0,0,0,10,2,10,2,9,0,0,0,0,0,0,0,0,0,0,68,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,2,10,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r20b_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,8,9,11,11,4,0,3,5,0,0,5,10,3,12,3,13,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r40_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,4,1,1,4,3,5,2,7,3,4,3,3,7,7,7,7,8,7,8,7,0,3,11,0,0,1,11,3,11,3,10,0,0,0,0,0,0,0,0,0,0,71,0,0,0,7,5,7,3,2,0,2,1,8,1,8,2,6,5,3,5,5,4,6,7,9,9,3,0,2,4,0,0,4,8,3,10,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-//RDIMM C/D Ports MBA1 Glacier
-
-uint32_t rdimm_glacier_1333_r10_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r10_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r20e_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,0,0,12,11,12,11,8,12,13,13,16,12,9,12,11,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,73,0,0,0,10,10,13,11,11,13,13,12,13,13,9,13,10,12,13,10,10,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r20e_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,9,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,77,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,13,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,3,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r20b_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,12,10,12,11,8,11,13,13,16,12,9,12,10,14,12,7,9,10,7,8,11,6,9,0,8,1,0,0,10,1,10,4,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,10,10,13,10,10,13,13,12,13,13,8,13,10,12,13,10,9,10,9,10,8,8,12,0,4,11,0,0,4,12,4,11,3,9,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r20b_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,14,13,15,14,10,14,16,17,21,15,11,15,13,17,15,9,11,13,8,10,14,7,11,0,10,1,0,0,13,2,12,5,4,1,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,16,10,16,12,15,17,12,12,12,11,12,9,9,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1066_r40_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,0xC0,0x40,0xC0,0x40,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,69,0,0,0,10,9,10,9,7,10,11,11,14,10,7,10,9,12,10,6,7,8,5,7,9,5,7,0,7,1,0,0,9,1,8,3,3,1,0,0,0,0,0,0,0,0,0,0,69,0,0,0,8,8,11,8,9,10,11,10,11,11,7,11,8,10,11,8,8,8,7,8,6,6,10,0,3,10,0,0,3,10,3,9,2,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r11_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,18,17,18,17,14,18,19,19,22,18,15,18,17,20,18,13,15,16,13,14,17,12,15,0,11,5,0,0,14,5,13,7,7,5,11,2,0,0,3,3,5,3,8,2,73,0,69,0,16,16,19,16,17,19,19,18,19,19,15,19,16,18,19,16,16,16,15,16,14,14,18,0,7,15,0,0,7,15,7,14,6,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r11_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x20,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,0xA0,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,76,0,71,0,21,20,22,20,17,21,23,23,27,22,18,22,20,24,21,15,18,20,15,17,20,14,18,0,14,6,0,0,17,6,17,10,9,6,13,2,0,0,4,3,5,3,10,3,76,0,71,0,19,20,23,20,20,23,23,22,23,23,17,23,19,22,23,19,19,19,18,19,16,16,22,0,9,19,0,0,9,20,9,18,8,16,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r22e_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,77,0,72,0,17,16,18,17,14,17,18,19,22,18,15,18,16,19,17,13,14,16,12,14,17,11,14,0,12,5,0,0,14,5,14,8,7,5,11,2,0,0,3,3,5,3,8,2,77,0,72,0,16,16,19,16,16,18,19,18,19,19,14,18,16,18,19,16,15,16,15,16,13,13,18,0,8,15,0,0,8,16,8,15,7,13,4,12,0,0,9,14,9,11,4,11,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r22e_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,81,0,77,0,21,19,21,20,16,21,22,23,27,22,17,21,19,23,21,15,17,19,14,16,20,13,17,0,13,5,0,0,16,5,15,8,7,5,13,2,0,0,4,3,5,3,10,2,81,0,77,0,19,19,23,19,19,22,23,21,23,23,17,22,19,21,23,19,18,19,18,19,16,16,22,0,7,17,0,0,8,18,8,16,7,15,4,15,0,0,11,17,10,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1333_r22b_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,73,0,69,0,16,14,16,15,12,16,17,17,21,16,12,16,14,18,16,10,12,14,10,12,15,9,12,0,12,6,0,0,15,6,14,8,8,6,11,2,0,0,3,3,5,3,8,2,73,0,69,0,14,14,17,14,14,17,17,16,17,17,12,17,14,16,17,13,13,14,13,14,11,11,16,0,8,16,0,0,8,17,8,15,7,14,4,12,0,0,9,14,9,11,4,10,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1600_r22b_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0x20,0x10,0x00,0x00,0x80,0x40,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,0xA0,0x50,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,78,0,71,0,20,18,20,19,15,20,21,22,26,21,16,21,18,23,20,14,16,18,13,15,19,12,16,0,16,8,0,0,20,8,19,12,11,8,14,2,0,0,4,3,6,3,10,3,78,0,71,0,17,18,22,18,18,21,22,20,22,22,15,21,17,20,22,17,17,17,16,17,14,14,21,0,11,21,0,0,11,22,11,20,10,18,4,15,0,0,11,17,11,13,5,13,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_glacier_1066_r44_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0x20,0x20,0x20,0x20,0x80,0x80,0x80,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,0xA0,0x20,0x60,0x20,0xA0,0x80,0x90,0x80,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,74,0,68,0,15,14,15,14,12,15,16,16,19,15,12,15,14,17,15,11,12,14,10,12,14,9,12,0,12,7,0,0,15,7,14,9,9,7,9,1,0,0,3,2,4,3,7,2,74,0,68,0,13,14,16,14,14,16,16,15,16,16,12,16,13,15,16,13,13,13,12,13,11,11,15,0,9,15,0,0,9,16,9,15,8,14,3,10,0,0,8,12,7,9,3,9,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-//UDIMM TEMP FOR JAKE ICICLE
-uint32_t udimm_glacier_1600_r10_mba0[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,63,0,0,0,2,3,2,5,0,1,4,3,6,2,8,3,4,3,3,8,8,8,8,9,8,9,8,0,3,12,0,0,0,12,2,12,3,11,0,0,0,0,0,0,0,0,0,0,70,0,0,0,8,6,9,4,2,0,3,2,10,1,9,3,7,6,3,6,6,5,7,9,11,10,4,0,3,5,0,0,4,10,3,12,3,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t udimm_glacier_1600_r10_mba1[210] =
-{fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM40_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,15,13,15,14,10,15,16,17,21,15,11,15,13,18,15,9,11,13,8,10,14,7,11,0,10,2,0,0,13,2,12,5,4,2,0,0,0,0,0,0,0,0,0,0,71,0,0,0,12,13,16,13,13,16,16,15,16,17,11,16,12,15,17,12,12,13,11,12,9,10,15,0,4,14,0,0,4,15,4,13,4,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-
-//KG3
-
-uint32_t rdimm_kg3_1333_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1333_r1_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r1_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1333_r2b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1333_r2b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r2b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-
-uint32_t rdimm_kg3_1600_r2b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-
-uint32_t rdimm_kg3_1333_r2e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1333_r2e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r2e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r2e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1333_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1333_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg3_1600_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,0x40,0x40,0x80,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-//KG4
-
-uint32_t rdimm_kg4_1600_r1_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r1_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r2b_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r2b_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r2e_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r2e_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r4_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,70,0,0,0,2,2,2,3,1,1,4,2,4,2,7,3,3,3,2,7,7,7,7,8,7,8,0,0,2,11,0,0,0,11,2,12,2,10,0,0,0,0,0,0,0,0,0,0,66,0,0,0,6,4,7,3,0,0,2,0,8,0,7,1,6,4,2,6,5,5,7,8,11,9,0,0,1,4,0,0,2,10,1,11,1,11,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-uint32_t rdimm_kg4_1600_r4_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,0x40,0x80,0x40,0x80,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,24,24,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,71,0,0,0,8,8,8,8,7,8,10,9,12,8,6,9,7,11,9,5,5,7,4,4,8,4,0,0,10,2,0,0,12,1,11,2,3,0,0,0,0,0,0,0,0,0,0,0,68,0,0,0,2,3,5,2,3,4,5,4,5,5,1,5,2,4,5,2,2,2,1,2,0,1,0,0,1,10,0,0,1,11,1,9,1,8,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE
-};
-
-// habanero_1333 single-drop
-uint32_t rdimm_habanero_1333_r10_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-uint32_t rdimm_habanero_1333_r10_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-uint32_t rdimm_habanero_1333_r20_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-uint32_t rdimm_habanero_1333_r20_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-// habanero_1333 dual-drop
-uint32_t rdimm_habanero_1333_r11_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-uint32_t rdimm_habanero_1333_r11_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-uint32_t rdimm_habanero_1333_r22_mba0[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,86,0,0,0,7,7,7,7,7,9,7,8,10,6,14,8,9,2,3,15,15,14,12,15,17,16,14,0,12,19,0,0,9,18,4,22,7,17,0,0,0,0,0,0,0,0,0,0,80,0,0,0,12,10,13,12,9,10,11,10,14,10,13,10,14,5,12,15,12,11,12,9,13,11,9,0,10,14,0,0,11,9,11,12,10,12,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-uint32_t rdimm_habanero_1333_r22_mba1[210] = {fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100,fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x40,0x00,0x00,0x00,0x00,0x00,0x00,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_RCV_IMP_DQ_DQS_OHM60,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_DQ_DQS_OHM34_FFE0,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CNTL_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_ADDR_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_CLK_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_DRV_IMP_SPCKE_OHM40,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS,82,0,0,0,15,15,15,12,15,15,16,16,16,15,13,16,12,12,15,13,13,12,11,6,15,11,12,0,20,7,0,0,11,11,11,9,11,10,0,0,0,0,0,0,0,0,0,0,85,0,0,0,9,13,18,14,11,16,17,17,18,19,0,18,14,17,18,15,14,4,13,11,11,12,16,0,14,25,0,0,11,22,3,20,10,19,0,0,0,0,0,0,0,0,0,0,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE,fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE};
-
-
-
-
-//Base Array Which Is Used For Looper To Setup Data
-uint32_t base_var_array[210];
-
-
-extern "C" {
-
-
-//******************************************************************************
-//* name=mss_eff_config_termination, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-  fapi::ReturnCode mss_eff_config_termination(const fapi::Target& i_target_mba) {
-    fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-    const char * const PROCEDURE_NAME = "mss_eff_config_termination";
-    FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
-   // Fetch dependent attributes
-    uint8_t l_target_mba_pos = 0;
-    uint32_t l_mss_freq = 0;
-    uint32_t l_mss_volt = 0;
-    uint8_t l_nwell_misplacement = 0;
-    uint8_t l_num_ranks_per_dimm_u8array[PORT_SIZE][DIMM_SIZE];
-    uint8_t l_stack_type_u8array[PORT_SIZE][DIMM_SIZE];
-    uint8_t l_dimm_size_u8array[PORT_SIZE][DIMM_SIZE];
-   // ATTR_EFF_DRAM_GEN: EMPTY = 0, DDR3 = 1, DDR4 = 2,
-    uint8_t l_dram_gen_u8;
-   // ATTR_EFF_DIMM_TYPE: CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3,
-    uint8_t l_dimm_type_u8;
-    uint8_t l_dimm_custom_u8;
-    uint8_t l_num_drops_per_port;
-    uint8_t l_dram_width_u8;
-
-   //for xml error usage
-   const fapi::Target& TARGET_MBA = i_target_mba;
-
-// this statement makes only lab version of this code have a raw card attribute
-#ifdef FAPIECMD
-    uint8_t l_lab_raw_card_u8 = 0;
-#endif
-    uint8_t l_bluewaterfall_broken = 0;
-    uint8_t l_dimm_rc_u8 = 0; //THIS VAR MATCHES LAB_RAW_CARD for enum position / card type (ie 5 is kg3, 0 is RC/A etc
-    rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_mba, l_target_mba_pos);
-    fapi::Target l_target_centaur;
-    rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_mss_freq); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_mss_volt); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MSS_NWELL_MISPLACEMENT, &l_target_centaur, l_nwell_misplacement); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_MSS_BLUEWATERFALL_BROKEN, &l_target_centaur, l_bluewaterfall_broken); if(rc) return rc;
-// Look up a lab only attribute in non-host boot environments
-#ifdef FAPIECMD
-    rc = FAPI_ATTR_GET(ATTR_LAB_ONLY_RAW_CARD, NULL, l_lab_raw_card_u8); if(rc) return rc;
-    //l_lab_raw_card_u8 = fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3;
-#endif
-
-
-
-    rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
-
-
-
-
-    if (l_mss_freq <= 0) {
-      FAPI_ERR("Invalid ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
-      FAPI_SET_HWP_ERROR(rc,RC_MSS_EFF_CONFIG_TERMINATION_INVALID_FREQ); return rc;
-    }
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_AL, &i_target_mba, attr_eff_dram_al); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_STACK_TYPE, &i_target_mba, l_stack_type_u8array); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN, &i_target_mba, l_dram_gen_u8); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, l_dimm_custom_u8); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, l_dram_width_u8); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &i_target_mba, l_dimm_size_u8array); if(rc) return rc;
-
-   // Temp workaround for incorrect byte33 SPD data "ATTR_EFF_STACK_TYPE" in early lab CDIMMs.
-    uint8_t l_stack_type_modified = 0;
-    for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) {
-      for (uint8_t cur_dimm = 0; cur_dimm < DIMM_SIZE; cur_dimm += 1) {
-        if ((l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) && (l_stack_type_u8array[cur_port][cur_dimm] == fapi::ENUM_ATTR_EFF_STACK_TYPE_DDP_QDP) && (l_dram_width_u8 == fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X8) && (l_dimm_size_u8array[cur_port][cur_dimm] == 4)) {
-          FAPI_INF("WARNING: Wrong Byte33 SPD detected for OLD 16G/32G CDIMM on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm);
-          FAPI_INF("WARNING: Implimenting workaround on %s PORT%d DIMM%d!", i_target_mba.toEcmdString(), cur_port, cur_dimm);
-          l_stack_type_modified = 1;
-          l_stack_type_u8array[cur_port][cur_dimm] = fapi::ENUM_ATTR_EFF_STACK_TYPE_NONE;
-        }
-      }
-    }
-    if (l_stack_type_modified == 1) {
-      FAPI_INF("WARNING: ATTR_EFF_STACK_TYPE is being set to ENUM_ATTR_EFF_STACK_TYPE_NONE. Check Byte33 of your SPD on %s!", i_target_mba.toEcmdString());
-      rc = FAPI_ATTR_SET(ATTR_EFF_STACK_TYPE, &i_target_mba, l_stack_type_u8array); if(rc) return rc;
-    }
-
-
-   // Fetch impacted attributes
-    uint64_t l_attr_eff_dimm_rcd_cntl_word_0_15[PORT_SIZE][DIMM_SIZE];
-    rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-
-   // find out if we are in simulation mode
-    uint8_t l_attr_is_simulation;
-    rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION, NULL, l_attr_is_simulation); if(rc) return rc;
-
-
-   // Define local attribute variables
-    uint8_t l_attr_mss_cal_step_enable = 0xFF;
-   //DEBUG MESSAGE!
-    FAPI_INF("DRAM GEN %d WIDTH %d 00R %d 10R %d 01R %d 11R %d DPP %d stack %d type %d custom %d\n",l_dram_gen_u8,l_dram_width_u8,l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[0][1],l_num_ranks_per_dimm_u8array[1][1],l_num_drops_per_port,l_stack_type_u8array[0][0],l_dimm_type_u8,l_dimm_custom_u8);
-
-
-   //Now, Determine The Type Of Dimm We Are Using
-   //l_target_mba_pos == 0,1 - MBA POS
-   //l_num_drops_per_port == drops / port
-   //if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM )
-    if(l_attr_is_simulation != 0) {
-      FAPI_INF("In Sim Detected %s on %s value is %d", PROCEDURE_NAME, i_target_mba.toEcmdString(), l_attr_is_simulation);
-      if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) ||  (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) ){
-        memcpy(base_var_array,cdimm_default,STORE_ARRAY_SIZE*sizeof(uint32_t));
-
-      }
-      else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){
-        memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,STORE_ARRAY_SIZE*sizeof(uint32_t));
-
-      }
-      else{
-        FAPI_ERR("Invalid Dimm SIM This Should Never Happen!\n");
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_DIMM_USE_ERROR); return rc;
-
-      }
-
-
-    }
-// lab only settings
-#ifdef FAPIECMD
-    else if(l_lab_raw_card_u8 == fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3){
-      //KG3
-      //FAPI_ERR("RUNNING AS KG3 LAB CARD TYPE, KG3 IS DISABLED UNTIL THE INITIAL SETTINGS ARE VERIFIED\n");
-      //FAPI_SET_HWP_ERROR(rc, RC_MSS_PLACE_HOLDER_ERROR); return rc;
-      if( l_target_mba_pos == 0){
-        if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
-            memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_kg3_1333_r2e_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
-            memcpy(base_var_array,rdimm_kg3_1333_r1_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r1 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_kg3_1333_r2b_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r2b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-            memcpy(base_var_array,rdimm_kg3_1333_r4_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r4 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps); return rc;
-
-          }
-
-
-        } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               //Removed Width Check, use settings for either x8 or x4
-            memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - KG3 LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4
-            memcpy(base_var_array,rdimm_kg3_1600_r1_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-
-            memcpy(base_var_array,rdimm_kg3_1600_r2e_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_kg3_1600_r2b_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-            memcpy(base_var_array,rdimm_kg3_1600_r4_mba0,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-
-          else{
-            FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps); return rc;
-
-          }
-        }//1600
-      }//MBA0
-      else{
-        if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               //Removed Width Check, use settings for either x8 or x4,
-            memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_kg3_1333_r2e_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r2e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
-            memcpy(base_var_array,rdimm_kg3_1333_r1_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r1 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_kg3_1333_r2b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r2b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-            memcpy(base_var_array,rdimm_kg3_1333_r4_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r4 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1333Mbps_MBA1); return rc;
-
-          }
-
-
-        } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-          if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               //Removed Width Check, use settings for either x8 or x4
-            memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - KG3 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4
-            memcpy(base_var_array,rdimm_kg3_1600_r1_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-
-            memcpy(base_var_array,rdimm_kg3_1600_r2e_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_kg3_1600_r2b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-            memcpy(base_var_array,rdimm_kg3_1600_r4_mba1,210*sizeof(uint32_t));
-            FAPI_INF("KG3 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-
-          else{
-            FAPI_ERR("Invalid Dimm Type KG3 FREQ %d MBA0\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG3_FREQ_1600Mbps_MBA1); return rc;
-
-          }
-        }//1600
-      }//MBA1
-    }
-#endif
-
-   else if ( (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) && ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) {
-      //KG4
-      if( l_target_mba_pos == 0){
-         if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               //Removed Width Check, use settings for either x8 or x4
-               memcpy(base_var_array,rdimm_kg4_1600_r1_mba0,210*sizeof(uint32_t));
-               FAPI_INF("LRDIMM: Base - KG4 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4
-               memcpy(base_var_array,rdimm_kg4_1600_r1_mba0,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-
-               memcpy(base_var_array,rdimm_kg4_1600_r2e_mba0,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-               memcpy(base_var_array,rdimm_kg4_1600_r2b_mba0,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               memcpy(base_var_array,rdimm_kg4_1600_r4_mba0,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-
-            else{
-               FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq);
-
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1333Mbps); return rc;
-            }
-              //    memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t));
-              //    FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n");
-         }//1600
-      }//MBA0
-      else{
-         if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ) {
-               //Removed Width Check, use settings for either x8 or x4
-               memcpy(base_var_array,rdimm_kg4_1600_r1_mba1,210*sizeof(uint32_t));
-               FAPI_INF("LRDIMM: Base - KG4 RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4
-               memcpy(base_var_array,rdimm_kg4_1600_r1_mba1,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-
-               memcpy(base_var_array,rdimm_kg4_1600_r2e_mba1,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-               memcpy(base_var_array,rdimm_kg4_1600_r2b_mba1,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               memcpy(base_var_array,rdimm_kg4_1600_r4_mba1,210*sizeof(uint32_t));
-               FAPI_INF("KG4 r40 %d MBA%s Using 1333 Settings\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-
-            else{
-               FAPI_ERR("Invalid Dimm Type KG4 FREQ %d MBA0\n",l_mss_freq);
-
-               FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_KG4_FREQ_1600Mbps); return rc;
-            }
-         }//1600
-      }//MBA1
-   }
-
-
-    else if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_UDIMM) || (l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)){
-      if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) {
-
-         //This is a CDIMM!
-         if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) {
-           //2R Cdimm RCB4
-            l_dimm_rc_u8 = 2;
-            if ( l_mss_freq <= 1733 ) { // 1600Mbps
-               if(l_target_mba_pos == 0){
-                  memcpy(base_var_array,cdimm_rcb4_2r_1600_mba0,210*sizeof(uint32_t));
-                  FAPI_INF("CDIMM rcb4_2r_1600 MBA0 \n");
-                  //memcpy(base_var_array,cdimm_rcb_2r_1600_mba0,210*sizeof(uint32_t));
-                  //FAPI_INF("CDIMM rcb4 Running with RCB DDR3 Settings MBA0\n");
-
-               }
-               else if(l_target_mba_pos == 1){
-                  memcpy(base_var_array,cdimm_rcb4_2r_1600_mba1,210*sizeof(uint32_t));
-                  FAPI_INF("CDIMM rcb4_2r_1600 MBA1 \n");
-                  //memcpy(base_var_array,cdimm_rcb_2r_1600_mba1,210*sizeof(uint32_t));
-                  //FAPI_INF("CDIMM rcb4 Running with RCB DDR3 Settings MBA1\n");
-
-
-               }
-              else{
-                 FAPI_ERR("Invalid Dimm Type CDIMM RCB4 FREQ %d\n",l_mss_freq);
-
-                 FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_B4_1600Mbps); return rc;
-              }
-            }
-         }//CDIMM RCB4
-         else {
-           memcpy(base_var_array,cdimm_default,210*sizeof(uint32_t));
-         }
-      }//End CDIMM
-      else{
-         //This is a UDIMM!
-        l_dimm_rc_u8 = 7;
-        if( l_target_mba_pos == 0 ){
-          if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-              memcpy(base_var_array,udimm_glacier_1600_r10_mba0,210*sizeof(uint32_t));
-              FAPI_INF("UDIMM ICICLE r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else{
-              FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq);
-
-              FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc;
-
-            }
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA0\n",l_mss_freq);
-
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA0); return rc;
-          }
-        }
-        else{
-          if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-              memcpy(base_var_array,udimm_glacier_1600_r10_mba1,210*sizeof(uint32_t));
-              FAPI_INF("UDIMM ICICLE r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-            }
-            else{
-              FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq);
-
-              FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc;
-
-            }
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type UDIMM FREQ %d MBA1\n",l_mss_freq);
-
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_UDIMM_1600Mbps_MBA1); return rc;
-          }
-        }
-
-
-
-
-      }//End UDIMM
-    }
-    else if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ){
-      l_dimm_rc_u8 = 7;
-      if( l_target_mba_pos == 0){
-        if ( l_mss_freq <= 1466 ) { // 1333Mbps
-
-          if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_glacier_1333_r20e_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
-            memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_glacier_1333_r20b_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-            memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1333Mbps); return rc;
-
-          }
-
-        } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-          if((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //Removed Width Check, use settings for either x8 or x4
-            memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 4)){
-
-            memcpy(base_var_array,rdimm_glacier_1600_r20e_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)  && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_glacier_1600_r20b_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)){
-               //USE 1333 settings at 1600
-            memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-
-          else{
-            FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA0\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA0_1600Mbps); return rc;
-
-          }
-        }//1600
-      }//MBA0
-      else{
-        if ( l_mss_freq <= 1200 ) { // 1066Mbps
-          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 4)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 4)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
-            memcpy(base_var_array,rdimm_glacier_1066_r44_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-            memcpy(base_var_array,rdimm_glacier_1066_r40_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r44 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1066Mbps); return rc;
-
-          }
-
-        } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-            memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
-            memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_glacier_1333_r20e_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_glacier_1333_r20b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_glacier_1333_r22e_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_glacier_1333_r22b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-               //Use 4R MBA0 settings for CD only!
-            memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-
-
-          else{
-            FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d HERE MBA1\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1333Mbps); return rc;
-
-          }
-        } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-
-          if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-            memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 1) && (l_num_ranks_per_dimm_u8array[0][1] == 1)) || ((l_num_ranks_per_dimm_u8array[1][0] == 1) && (l_num_ranks_per_dimm_u8array[1][1] == 1)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
-            memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_glacier_1600_r20e_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 0)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE) && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_glacier_1600_r20b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r20b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 4)){
-            memcpy(base_var_array,rdimm_glacier_1600_r22e_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r22e %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( ( ((l_num_ranks_per_dimm_u8array[0][0] == 2) && (l_num_ranks_per_dimm_u8array[0][1] == 2)) || ((l_num_ranks_per_dimm_u8array[1][0] == 2) && (l_num_ranks_per_dimm_u8array[1][1] == 2)) ) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL) && (l_dram_width_u8 == 8)){
-            memcpy(base_var_array,rdimm_glacier_1600_r22b_mba1,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r22b %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if((((l_num_ranks_per_dimm_u8array[0][0] == 4) && (l_num_ranks_per_dimm_u8array[0][1] == 0)) || ((l_num_ranks_per_dimm_u8array[1][0] == 4) && (l_num_ranks_per_dimm_u8array[1][1] == 0))) && (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-               //Use 4R MBA0 1333 settings for CD only!
-            memcpy(base_var_array,rdimm_glacier_1333_r40_mba0,210*sizeof(uint32_t));
-            FAPI_INF("RDIMM r40 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type RDIMM FREQ %d MBA1\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_MBA1_1600Mbps); return rc;
-
-          }
-        }//1600
-      }//MBA1
-    }//End RDIMM
-    else if( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM ){
-      l_dimm_rc_u8 = 7;
-      // Set LRDIMM base var array as 1Rank RDIMM
-      if( l_target_mba_pos == 0){
-        if ( l_mss_freq <= 1466 ) { // 1333Mbps
-            //Removed Width Check, use settings for either x8 or x4, use 1600 settings for 1333!
-          memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,210*sizeof(uint32_t));
-          FAPI_INF("LRDIMM: Base - RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-
-        } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            //Removed Width Check, use settings for either x8 or x4
-          memcpy(base_var_array,rdimm_glacier_1600_r10_mba0,210*sizeof(uint32_t));
-          FAPI_INF("LRDIMM: Base - LRDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-        }
-      }//MBA0
-      else{
-        if ( l_mss_freq <= 1466 ) { // 1333Mbps
-          if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-            memcpy(base_var_array,rdimm_glacier_1333_r10_mba1,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
-            memcpy(base_var_array,rdimm_glacier_1333_r11_mba1,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d HERE MBA1\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1333Mbps); return rc;
-
-          }
-        } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-
-          if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE)){
-            memcpy(base_var_array,rdimm_glacier_1600_r10_mba1,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - RDIMM r10 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else if( (l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL)){
-            memcpy(base_var_array,rdimm_glacier_1600_r11_mba1,210*sizeof(uint32_t));
-            FAPI_INF("LRDIMM: Base - RDIMM r11 %d MBA%s\n",l_mss_freq,i_target_mba.toEcmdString());
-          }
-          else{
-            FAPI_ERR("Invalid Dimm Type LRDIMM FREQ %d MBA1\n",l_mss_freq);
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_LRDIMM_MBA1_1600Mbps); return rc;
-
-          }
-        }
-      }//MBA1
-
-//----------------------------------------------------------------------------------------------------------------
-
-      // For dual drop, Set ODT_RD as 2rank (8R LRDIMM) or 4rank (4R LRDIMM)
-      if ( l_num_drops_per_port == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) {
-        uint32_t *p_1066_mba1_array = &rdimm_glacier_1066_r44_mba1[0];
-        uint32_t *p_1333_x4_mba1_array = &rdimm_glacier_1333_r22e_mba1[0];
-        uint32_t *p_1333_x8_mba1_array = &rdimm_glacier_1333_r22b_mba1[0];
-        uint32_t *p_1600_x4_mba1_array = &rdimm_glacier_1600_r22e_mba1[0];
-        uint32_t *p_1600_x8_mba1_array = &rdimm_glacier_1600_r22b_mba1[0];
-
-        uint32_t *p_b_var_array = &base_var_array[0];
-
-        uint32_t *var_array_p_array[] = {p_1066_mba1_array, p_1333_x4_mba1_array, p_1333_x8_mba1_array,
-        p_1600_x4_mba1_array, p_1600_x8_mba1_array};
-
-        rc = mss_lrdimm_rewrite_odt(i_target_mba, p_b_var_array, var_array_p_array);
-
-        if(rc)
-        {
-          FAPI_ERR("FAILED LRDIMM rewrite ODT_RD");
-
-          FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_LRDIMM_ODT_RD); return rc;
-        }
-      }
-    } // LRDIMM
-    else{
-      FAPI_ERR("Invalid Dimm Type of %d", l_dimm_type_u8);
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_TYPE); return rc;
-
-    }
-
-   // Now Set All The Attributes
-    uint8_t i = 0;
-    attr_eff_dimm_rcd_ibt[0][0] = base_var_array[i++];             // keep 0
-    attr_eff_dimm_rcd_ibt[0][1] = base_var_array[i++];             // keep 1
-    attr_eff_dimm_rcd_ibt[1][0] = base_var_array[i++];             // keep 2
-    attr_eff_dimm_rcd_ibt[1][1] = base_var_array[i++];             // keep 3
-    attr_eff_dimm_rcd_mirror_mode[0][0] = base_var_array[i++];     // keep 4
-    attr_eff_dimm_rcd_mirror_mode[0][1] = base_var_array[i++];     // keep 5
-    attr_eff_dimm_rcd_mirror_mode[1][0] = base_var_array[i++];     // keep 6
-    attr_eff_dimm_rcd_mirror_mode[1][1] = base_var_array[i++];     // keep 7
-
-
-   //Fix for VPD Mode for lab rdimm
-    if(((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) || ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ) && (l_lab_raw_card_u8 != fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3)){
-      FAPI_INF("RON i %d SHOULD NOT BE HERE\n",i);
-      attr_vpd_dram_ron[0][0] = base_var_array[i++];
-      attr_vpd_dram_ron[0][1] = base_var_array[i++];
-      attr_vpd_dram_ron[1][0] = base_var_array[i++];
-      attr_vpd_dram_ron[1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][3] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][0] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][1] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][2] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][3] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][0] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][1] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][2] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][3] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][0] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][1] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][2] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][3] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][0] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][1] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][2] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][3] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][0] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][1] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][2] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][3] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][0] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][1] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][2] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][3] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][0] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][1] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][2] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][3] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][0] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][1] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][2] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][3] = base_var_array[i++];
-      attr_eff_cen_rd_vref[0] = base_var_array[i++];
-      attr_eff_cen_rd_vref[1] = base_var_array[i++];
-      if(l_dram_gen_u8 == 1){
-        attr_eff_dram_wr_vref[0] = base_var_array[i++];
-        attr_eff_dram_wr_vref[1] = base_var_array[i++];
-      }
-      else if(l_dram_gen_u8 == 2){
-        attr_eff_dram_wrddr4_vref[0] = base_var_array[i++];
-        attr_eff_dram_wrddr4_vref[1] = base_var_array[i++];
-        attr_eff_dram_wrddr4_vref[0] = base_var_array[i++];
-        attr_eff_dram_wrddr4_vref[1] = base_var_array[i++];
-      }
-      attr_eff_cen_rcv_imp_dq_dqs[0] = base_var_array[i++];
-      attr_eff_cen_rcv_imp_dq_dqs[1] = base_var_array[i++];
-      attr_eff_cen_drv_imp_dq_dqs[0] = base_var_array[i++];
-      attr_eff_cen_drv_imp_dq_dqs[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_cntl[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_cntl[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_addr[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_addr[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_clk[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_clk[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_spcke[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_spcke[1] = base_var_array[i++];
-      attr_eff_cen_slew_rate_dq_dqs[0] = base_var_array[i++];
-      attr_eff_cen_slew_rate_dq_dqs[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_cntl[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_cntl[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_addr[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_addr[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_clk[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_clk[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_spcke[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_spcke[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a4[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a5[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a6[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a7[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a8[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a9[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a10[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a11[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a12[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a13[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a14[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a15[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_casn[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_rasn[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_wen[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_par[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_actn[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a4[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a5[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a6[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a7[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a8[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a9[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a10[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a11[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a12[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a13[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a14[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a15[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_casn[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_rasn[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_wen[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_par[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_actn[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt1[1] = base_var_array[i++];
-
-    }
-
-#ifdef FAPIECMD
-    if(l_lab_raw_card_u8 == fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3 ){
-      FAPI_INF("In KG3 Incrementing I for ron i is %d\n",i);
-      attr_vpd_dram_ron[0][0] = base_var_array[i++];
-      attr_vpd_dram_ron[0][1] = base_var_array[i++];
-      attr_vpd_dram_ron[1][0] = base_var_array[i++];
-      attr_vpd_dram_ron[1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[0][1][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_nom[1][1][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[0][1][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][0][3] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][0] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][1] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][2] = base_var_array[i++];
-      attr_vpd_dram_rtt_wr[1][1][3] = base_var_array[i++];
-      FAPI_INF("In KG3 Incrementing I for odt_rd i is %d\n",i);
-
-      attr_vpd_odt_rd[0][0][0] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][1] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][2] = base_var_array[i++];
-      attr_vpd_odt_rd[0][0][3] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][0] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][1] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][2] = base_var_array[i++];
-      attr_vpd_odt_rd[0][1][3] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][0] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][1] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][2] = base_var_array[i++];
-      attr_vpd_odt_rd[1][0][3] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][0] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][1] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][2] = base_var_array[i++];
-      attr_vpd_odt_rd[1][1][3] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][0] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][1] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][2] = base_var_array[i++];
-      attr_vpd_odt_wr[0][0][3] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][0] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][1] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][2] = base_var_array[i++];
-      attr_vpd_odt_wr[0][1][3] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][0] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][1] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][2] = base_var_array[i++];
-      attr_vpd_odt_wr[1][0][3] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][0] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][1] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][2] = base_var_array[i++];
-      attr_vpd_odt_wr[1][1][3] = base_var_array[i++];
-      attr_eff_cen_rd_vref[0] = base_var_array[i++];
-      attr_eff_cen_rd_vref[1] = base_var_array[i++];
-      if(l_dram_gen_u8 == 1){
-        attr_eff_dram_wr_vref[0] = base_var_array[i++];
-        attr_eff_dram_wr_vref[1] = base_var_array[i++];
-      }
-      else if(l_dram_gen_u8 == 2){
-        attr_eff_dram_wrddr4_vref[0] = base_var_array[i++];
-        attr_eff_dram_wrddr4_vref[1] = base_var_array[i++];
-        attr_eff_dram_wrddr4_vref[0] = base_var_array[i++];
-        attr_eff_dram_wrddr4_vref[1] = base_var_array[i++];
-      }
-      attr_eff_cen_rcv_imp_dq_dqs[0] = base_var_array[i++];
-      attr_eff_cen_rcv_imp_dq_dqs[1] = base_var_array[i++];
-      attr_eff_cen_drv_imp_dq_dqs[0] = base_var_array[i++];
-      attr_eff_cen_drv_imp_dq_dqs[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_cntl[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_cntl[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_addr[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_addr[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_clk[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_clk[1] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_spcke[0] = base_var_array[i++];
-      attr_vpd_cen_drv_imp_spcke[1] = base_var_array[i++];
-      attr_eff_cen_slew_rate_dq_dqs[0] = base_var_array[i++];
-      attr_eff_cen_slew_rate_dq_dqs[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_cntl[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_cntl[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_addr[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_addr[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_clk[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_clk[1] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_spcke[0] = base_var_array[i++];
-      attr_vpd_cen_slew_rate_spcke[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a4[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a5[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a6[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a7[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a8[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a9[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a10[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a11[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a12[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a13[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a14[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a15[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_casn[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_rasn[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_wen[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_par[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_actn[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn2[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn3[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt0[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt1[0] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_clk_p1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_clk_p1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a4[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a5[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a6[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a7[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a8[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a9[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a10[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a11[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a12[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a13[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a14[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_a15[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_bA2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_casn[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_rasn[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_cmd_wen[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_par[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m_actn[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_cke3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_csn3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m0_cntl_odt1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_cke3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn1[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn2[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_csn3[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt0[1] = base_var_array[i++];
-      attr_vpd_cen_phase_rot_m1_cntl_odt1[1] = base_var_array[i++];
-
-    }
-#endif
-
-
-
-
-
-
-
-
-
-
-   // set these attributes from the VPD but allow the code to override later
-    rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_WRDDR4_VREF, &i_target_mba, attr_eff_dram_wrddr4_vref); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_VPD_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-    rc = FAPI_ATTR_GET(ATTR_VPD_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
-
-  //Now Setup the RCD - Done Here to Steal Code From Anuwats Version Of Eff Config Termination
-
-    if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 &&
-         ( (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) ||
-           (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) ) ) {
-
-      rc = mss_create_rcd_ddr4(i_target_mba);
-      
-      if (rc)
-      {
-        FAPI_ERR("Setting DDR4 RCD words failed \n");
-        return rc;
-      }
-
-      if (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM) {
-         rc = mss_create_db_ddr4(i_target_mba);
-      }
-
-      if (rc)
-      {
-        FAPI_ERR("Setting DDR4 RCD words failed \n");
-        return rc;
-      }
-
-    }
-    else if ( l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM ) {
-      for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) {
-        for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) {
-          uint64_t l_mss_freq_mask        = 0xFFFFFFFFFFCFFFFFLL;
-          uint64_t l_mss_volt_mask        = 0xFFFFFFFFFFFEFFFFLL;
-          uint64_t l_rcd_ibt_mask         = 0xFFBFFFFF8FFFFFFFLL;
-          uint64_t l_rcd_mirror_mode_mask = 0xFFFFFFFF7FFFFFFFLL;
-          if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 4 ) {
-            if(l_dram_width_u8 == 4){
-              l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005050080210000LL;
-            }
-            else {
-              l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005550080210000LL;
-
-            }
-          } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 2 ) {
-            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0005550000210000LL;
-          } else if ( l_num_ranks_per_dimm_u8array[l_port][l_dimm] == 1 ) {
-            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0C00000001210000LL;
-          } else {
-            l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = 0x0000000000000000LL;
-          }
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_freq_mask;
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_mss_volt_mask;
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_ibt_mask;
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] & l_rcd_mirror_mode_mask;
-          if ( l_mss_freq <= 933 ) {         // 800Mbps
-            l_mss_freq_mask = 0x0000000000000000LL;
-          } else if ( l_mss_freq <= 1200 ) { // 1066Mbps
-            l_mss_freq_mask = 0x0000000000100000LL;
-          } else if ( l_mss_freq <= 1466 ) { // 1333Mbps
-            l_mss_freq_mask = 0x0000000000200000LL;
-          } else if ( l_mss_freq <= 1733 ) { // 1600Mbps
-            l_mss_freq_mask = 0x0000000000300000LL;
-          } else {                           // 1866Mbps
-            FAPI_ERR("Invalid RDIMM ATTR_MSS_FREQ = %d on %s!", l_mss_freq, i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_FREQ); return rc;
-          }
-          if ( l_mss_volt >= 1420 ) {        // 1.5V
-            l_mss_volt_mask = 0x0000000000000000LL;
-          } else if ( l_mss_volt >= 1270 ) { // 1.35V
-            l_mss_volt_mask = 0x0000000000010000LL;
-          } else {                           // 1.2V
-            FAPI_ERR("Invalid RDIMM ATTR_MSS_VOLT = %d on %s!", l_mss_volt, i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_RDIMM_VOLT); return rc;
-
-          }
-          if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_OFF ) {
-            l_rcd_ibt_mask = 0x0000000070000000LL;
-          } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_100 ) {
-            l_rcd_ibt_mask = 0x0000000000000000LL;
-          } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_150 ) {
-            l_rcd_ibt_mask = 0x0040000000000000LL;
-          } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_200 ) {
-            l_rcd_ibt_mask = 0x0000000020000000LL;
-          } else if ( attr_eff_dimm_rcd_ibt[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_IBT_IBT_300 ) {
-            l_rcd_ibt_mask = 0x0000000040000000LL;
-          } else {
-            FAPI_ERR("Invalid DIMM_RCD_IBT on %s!", i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_IBT); return rc;
-
-          }
-          if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_OFF ) {
-            l_rcd_mirror_mode_mask = 0x0000000000000000LL;
-          } else if ( attr_eff_dimm_rcd_mirror_mode[l_port][l_dimm] == fapi::ENUM_ATTR_EFF_DIMM_RCD_MIRROR_MODE_IBT_BACK_ON ) {
-            l_rcd_mirror_mode_mask = 0x0000000080000000LL;
-          } else {
-            FAPI_ERR("Invalid DIMM_RCD_MIRROR_MODE on %s!", i_target_mba.toEcmdString());
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_DIMM_RCD_MIRROR_MODE); return rc;
-
-
-          }
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_freq_mask;
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_mss_volt_mask;
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_ibt_mask;
-          l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] = l_attr_eff_dimm_rcd_cntl_word_0_15[l_port][l_dimm] | l_rcd_mirror_mode_mask;
-        }
-      }
-    }
-
-
-   // For DDR4
-    uint8_t l_attr_eff_dram_lpasr = ENUM_ATTR_EFF_DRAM_LPASR_MANUAL_NORMAL;     // 0
-    uint8_t l_attr_eff_write_crc = ENUM_ATTR_EFF_WRITE_CRC_DISABLE;                     // 0; change ENUMS: DISABLE=0, ENABLE=1
-    uint8_t l_attr_eff_mpr_page = 0;                                                                    // 0; maybe add ENUMS: PG0=0, PG1=1, PG2=2, PG3=3       for more readability?
-    uint8_t l_attr_eff_geardown_mode = ENUM_ATTR_EFF_GEARDOWN_MODE_HALF;                // 0
-    uint8_t l_attr_eff_per_dram_access = ENUM_ATTR_EFF_PER_DRAM_ACCESS_DISABLE; // 1; change ENUMS: DISABLE=0; ENABLE=1
-    uint8_t l_attr_eff_temp_readout = ENUM_ATTR_EFF_TEMP_READOUT_DISABLE;               // 1; change ENUMS: DISABLE=0; ENABLE=1
-    uint8_t l_attr_eff_fine_refresh_mode = ENUM_ATTR_EFF_FINE_REFRESH_MODE_NORMAL;      // 4; maybe change ENUMS: NORMAL=0; FIXED_2X=1, FIXED_4X=2, FLY_2X=5, FLY_4X=6   to align with spec better
-    uint8_t l_attr_eff_crc_wr_latency = ENUM_ATTR_EFF_CRC_WR_LATENCY_4NCK;              // 0; change ENUMS:  4NCK=4, 5NCK=5, 6NCK=6             following convention
-    uint8_t l_attr_eff_mpr_rd_format = ENUM_ATTR_EFF_MPR_RD_FORMAT_SERIAL;              // 0
-    uint8_t l_attr_eff_max_powerdown_mode = ENUM_ATTR_EFF_MAX_POWERDOWN_MODE_DISABLE;   // 1; change ENUMS: DISABLE=0, ENABLE=1
-    uint8_t l_attr_eff_temp_ref_range = ENUM_ATTR_EFF_TEMP_REF_RANGE_NORMAL;    // 0
-    uint8_t l_attr_eff_temp_ref_mode = ENUM_ATTR_EFF_TEMP_REF_MODE_ENABLE;              // 0; change ENUMS: DISABLE=0, ENABLE=1
-    uint8_t l_attr_eff_int_vref_mon = ENUM_ATTR_EFF_INT_VREF_MON_DISABLE;               // change to disable; change ENUMS: DISABLE=0, ENABLE=1
-    uint8_t l_attr_eff_cs_cmd_latency = 0;                                                              // 0; maybe add ENUMS: DISABLE=0, 3CYC=3, 4CYC=4, 5CYC=5, 6CYC=6, 8CYC=8   for better readability
-    uint8_t l_attr_eff_self_ref_abort = ENUM_ATTR_EFF_SELF_REF_ABORT_DISABLE;           // 1; change ENUMS: DISABLE=0, ENABLE=1
-    uint8_t l_attr_eff_rd_preamble_train = ENUM_ATTR_EFF_RD_PREAMBLE_TRAIN_DISABLE;     // 1; change ENUMS: DISABLE=0, ENABLE=1
-    uint8_t l_attr_eff_rd_preamble = ENUM_ATTR_EFF_RD_PREAMBLE_1NCLK;                   // 0; change ENUMS:  1NCK=1, 2NCK=2             following convention
-    uint8_t l_attr_eff_wr_preamble = ENUM_ATTR_EFF_WR_PREAMBLE_1NCLK;                   // 0; change ENUMS:  1NCK=1, 2NCK=2             following convention
-    uint8_t l_attr_eff_ca_parity_latency = ENUM_ATTR_EFF_CA_PARITY_LATENCY_DISABLE;     // 0; add ENUMS: PL4=4, PL5=5, PL6=6, PL8=8,    for better readability
-    uint8_t l_attr_eff_crc_error_clear = ENUM_ATTR_EFF_CRC_ERROR_CLEAR_ERROR;           // 0; change ENUMS: CLEAR=0, ERROR=1    to match spec.
-    uint8_t l_attr_eff_ca_parity_error_status = ENUM_ATTR_EFF_CA_PARITY_ERROR_STATUS_ERROR;     // 0; change ENUMS: CLEAR=0, ERROR=1    to match spec
-    uint8_t l_attr_eff_odt_input_buff = ENUM_ATTR_EFF_ODT_INPUT_BUFF_ACTIVATED; // 0; change ENUMS: DEACTIVATED=0, ACTIVATED=1
-    uint8_t l_attr_eff_ca_parity = ENUM_ATTR_EFF_CA_PARITY_DISABLE;                     // change to disable;  change ENUMS: DISABLE=0, ENABLE=1        to match spec
-    uint8_t l_attr_eff_data_mask = ENUM_ATTR_EFF_DATA_MASK_DISABLE;                     // 0
-    uint8_t l_attr_eff_write_dbi = ENUM_ATTR_EFF_WRITE_DBI_DISABLE;                     // 0
-    uint8_t l_attr_eff_read_dbi = ENUM_ATTR_EFF_READ_DBI_DISABLE;                               // 0
-//   uint8_t l_attr_tccd_l = ENUM_ATTR_TCCD_L_5NCK;                                             // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability
-   // uint8_t l_attr_tccd_l = 5;                                             // 5; maybe add ENUMS: 4NCK=4, 5NCK=5, 6NCK=6; 7NCK=7, 8NCK=8 for better readability
-
-/*
- * Remove Before COMMIT
-   uint8_t l_attr_eff_dram_lpasr = 0;
-   uint8_t l_attr_eff_write_crc = 0;
-   uint8_t l_attr_eff_mpr_page = 0;
-   uint8_t l_attr_eff_geardown_mode = 0;
-   uint8_t l_attr_eff_per_dram_access = 1;
-   uint8_t l_attr_eff_temp_readout = 1;
-   uint8_t l_attr_eff_fine_refresh_mode = 4;
-   uint8_t l_attr_eff_crc_wr_latency = 0;
-   uint8_t l_attr_eff_mpr_rd_format = 0;
-   uint8_t l_attr_eff_max_powerdown_mode = 1;
-   uint8_t l_attr_eff_temp_ref_range = 0;
-   uint8_t l_attr_eff_temp_ref_mode = 0;
-   uint8_t l_attr_eff_int_vref_mon = 0;
-   uint8_t l_attr_eff_cs_cmd_latency = 0;
-   uint8_t l_attr_eff_self_ref_abort = 1;
-   uint8_t l_attr_eff_rd_preamble_train = 1;
-   uint8_t l_attr_eff_rd_preamble = 0;
-   uint8_t l_attr_eff_wr_preamble = 0;
-   uint8_t l_attr_eff_ca_parity_latency = 0;
-   uint8_t l_attr_eff_crc_error_clear = 0;
-   uint8_t l_attr_eff_ca_parity_error_status = 0;
-   uint8_t l_attr_eff_odt_input_buff = 0;
-   uint8_t l_attr_eff_ca_parity = 0;
-   uint8_t l_attr_eff_data_mask = 0;
-   uint8_t l_attr_eff_write_dbi = 0;
-   uint8_t l_attr_eff_read_dbi = 0;
-   uint8_t l_attr_tccd_l = 5;
-*/
-    uint8_t l_attr_eff_rtt_park[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-    uint8_t l_attr_vref_dq_train_value[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-    uint8_t l_attr_vref_dq_train_range[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-    uint8_t l_attr_vref_dq_train_enable[PORT_SIZE][DIMM_SIZE][RANK_SIZE];
-
-    for( int l_port = 0; l_port < PORT_SIZE; l_port += 1 ) {
-      for( int l_dimm = 0; l_dimm < DIMM_SIZE; l_dimm += 1 ) {
-        for( int l_rank = 0; l_rank < RANK_SIZE; l_rank += 1 ) {
-          l_attr_eff_rtt_park[l_port][l_dimm][l_rank] = 0;
-          l_attr_vref_dq_train_value[l_port][l_dimm][l_rank] = 16;
-          l_attr_vref_dq_train_range[l_port][l_dimm][l_rank] = 0;
-          l_attr_vref_dq_train_enable[l_port][l_dimm][l_rank] = ENUM_ATTR_VREF_DQ_TRAIN_ENABLE_DISABLE;
-        }
-      }
-    }
-
-
-   //RLO Settings
-    FAPI_INF("Card Type is %d BW %d NW %d POS %d\n",l_dimm_rc_u8,l_bluewaterfall_broken,l_nwell_misplacement,l_target_mba_pos);
-    if(l_dimm_custom_u8 == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES){
-      //if((l_lab_raw_card_u8 == 0) || (l_lab_raw_card_u8 == 1) || (l_lab_raw_card_u8 == 2) || (l_lab_raw_card_u8 == 3)){
-         //These are cdimms, RLO on all ports is 1!
-         //WLO,RLO,GPO all come from VPD NOW
-/*
-         if((l_bluewaterfall_broken == 1) && (l_nwell_misplacement == 0) && (l_dimm_rc_u8 == 3) && (l_target_mba_pos == 0)){
-            FAPI_INF("DD1.01 RC/C, Applying Port A Workaround For RLO!\n");
-            attr_eff_rlo[0] = (uint8_t)2;
-            attr_eff_rlo[1] = (uint8_t)1;
-          }
-         else if((l_bluewaterfall_broken == 1) && (l_nwell_misplacement == 0) && (l_dimm_rc_u8 == 3) && (l_target_mba_pos == 1)){
-            FAPI_INF("DD1.01 RC/C, Applying Port BC Workaround For RLO!\n");
-            attr_eff_rlo[0] = (uint8_t)1;
-            attr_eff_rlo[1] = (uint8_t)1;
-          }
-          else if((l_bluewaterfall_broken == 0) && (l_nwell_misplacement == 0) && (l_dimm_rc_u8 == 3)){
-             attr_eff_rlo[0] = (uint8_t)1;
-             attr_eff_rlo[1] = (uint8_t)1;
-
-          }
-          else{
-             attr_eff_rlo[0] = (uint8_t)0;
-             attr_eff_rlo[1] = (uint8_t)0;
-          }
-
-          //Set WLO and GPO
-          attr_eff_wlo[0] = (uint8_t)0;
-          attr_eff_wlo[1] = (uint8_t)0;
-          attr_eff_gpo[0] = (uint8_t)5;
-          attr_eff_gpo[1] = (uint8_t)5;
-*/
-      if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) {
-      // Set for CDIMM B4
-          attr_eff_rlo[0] = (uint8_t)0;
-          attr_eff_rlo[1] = (uint8_t)0;
-          attr_eff_wlo[0] = (uint8_t)0;
-          attr_eff_wlo[1] = (uint8_t)0;
-          attr_eff_gpo[0] = (uint8_t)5;
-          attr_eff_gpo[1] = (uint8_t)5;
-      }
-
-    }
-    else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM){
-  //else if((l_lab_raw_card_u8 == 5) || (l_lab_raw_card_u8 == 6) || (l_lab_raw_card_u8 == 7)){
-       //RDIMM
-      attr_eff_rlo[0] = (uint8_t)2;
-      attr_eff_rlo[1] = (uint8_t)2;
-       //Set WLO and GPO
-      attr_eff_wlo[0] = (uint8_t)1;
-      attr_eff_wlo[1] = (uint8_t)1;
-      attr_eff_gpo[0] = (uint8_t)5;
-      attr_eff_gpo[1] = (uint8_t)5;
-
-    }
-    else if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM){
-       //LRDIMM
-       if ( l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4 ) {
-         attr_eff_rlo[0] = (uint8_t)5;
-         attr_eff_rlo[1] = (uint8_t)5;
-         attr_eff_wlo[0] = (uint8_t)1;
-         attr_eff_wlo[1] = (uint8_t)1;
-       }
-       else {
-         attr_eff_rlo[0] = (uint8_t)6;
-         attr_eff_rlo[1] = (uint8_t)6;
-         attr_eff_wlo[0] = (uint8_t)255; // WLO = -1, 2's complement
-         attr_eff_wlo[1] = (uint8_t)255;
-      }
-      attr_eff_gpo[0] = (uint8_t)7;
-      attr_eff_gpo[1] = (uint8_t)7;
-
-    }
-    else{
-      FAPI_ERR("Invalid Card Type RLO Settings \n");
-      FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_TERMINATION_INVALID_CARD_TYPE_RLO); return rc;
-
-
-    }
-
-
-
-    FAPI_INF("About To Set Attributes\n");
-
-
-    rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_LPASR, &i_target_mba, l_attr_eff_dram_lpasr); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_WRITE_CRC, &i_target_mba, l_attr_eff_write_crc); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_MPR_PAGE, &i_target_mba, l_attr_eff_mpr_page); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_GEARDOWN_MODE, &i_target_mba, l_attr_eff_geardown_mode); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_PER_DRAM_ACCESS, &i_target_mba, l_attr_eff_per_dram_access); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_TEMP_READOUT, &i_target_mba, l_attr_eff_temp_readout); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_FINE_REFRESH_MODE, &i_target_mba, l_attr_eff_fine_refresh_mode); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CRC_WR_LATENCY, &i_target_mba, l_attr_eff_crc_wr_latency); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_MPR_RD_FORMAT, &i_target_mba, l_attr_eff_mpr_rd_format); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_MAX_POWERDOWN_MODE, &i_target_mba, l_attr_eff_max_powerdown_mode); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_TEMP_REF_RANGE, &i_target_mba, l_attr_eff_temp_ref_range); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_TEMP_REF_MODE, &i_target_mba, l_attr_eff_temp_ref_mode); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_INT_VREF_MON, &i_target_mba, l_attr_eff_int_vref_mon); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CS_CMD_LATENCY, &i_target_mba, l_attr_eff_cs_cmd_latency); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_SELF_REF_ABORT, &i_target_mba, l_attr_eff_self_ref_abort); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_RD_PREAMBLE_TRAIN, &i_target_mba, l_attr_eff_rd_preamble_train); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_RD_PREAMBLE, &i_target_mba, l_attr_eff_rd_preamble); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_WR_PREAMBLE, &i_target_mba, l_attr_eff_wr_preamble); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CA_PARITY_LATENCY, &i_target_mba, l_attr_eff_ca_parity_latency); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CRC_ERROR_CLEAR, &i_target_mba, l_attr_eff_crc_error_clear); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CA_PARITY_ERROR_STATUS, &i_target_mba, l_attr_eff_ca_parity_error_status); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_ODT_INPUT_BUFF, &i_target_mba, l_attr_eff_odt_input_buff); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_RTT_PARK, &i_target_mba, l_attr_eff_rtt_park); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CA_PARITY, &i_target_mba, l_attr_eff_ca_parity); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_DATA_MASK, &i_target_mba, l_attr_eff_data_mask); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_WRITE_DBI, &i_target_mba, l_attr_eff_write_dbi); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_READ_DBI, &i_target_mba, l_attr_eff_read_dbi); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_VALUE, &i_target_mba, l_attr_vref_dq_train_value); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_RANGE, &i_target_mba, l_attr_vref_dq_train_range); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_VREF_DQ_TRAIN_ENABLE, &i_target_mba, l_attr_vref_dq_train_enable); if(rc) return rc;
-   // rc = FAPI_ATTR_SET(ATTR_TCCD_L, &i_target_mba, l_attr_tccd_l); if(rc) return rc;
-    FAPI_INF("Set some attributes, setting more\n");
-
-   // Set attributes
-    rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc;
-    if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD
-       rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-    }
-    rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-    rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, attr_eff_cen_slew_rate_dq_dqs); if(rc) return rc;
-
-   //Set AL to be 1 less IF 2N Mode Is Enabled
-    rc = FAPI_ATTR_GET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target_mba, l_attr_vpd_2n_mode_enabled); if(rc) return rc;
-    FAPI_INF("Still alive here\n");
-    if(l_attr_vpd_2n_mode_enabled == fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE ) {
-      FAPI_INF("Changing Additive Latency For 2N Mode\nCurrent AL IS %d\n",attr_eff_dram_al);
-      if(attr_eff_dram_al == 1){
-        attr_eff_dram_al = 2;
-      }
-      rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_AL, &i_target_mba, attr_eff_dram_al); if(rc) return rc;
-
-    }
-    FAPI_INF("AFTER AL SW\n");
-
-    uint8_t l_attr_vpd_dimm_spare[2][2][4];
-
-    if(l_dimm_custom_u8 != fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) {
-      memset(l_attr_vpd_dimm_spare,ENUM_ATTR_VPD_DIMM_SPARE_NO_SPARE,2*2*4);
-      rc = FAPI_ATTR_SET(ATTR_VPD_DIMM_SPARE, &i_target_mba, l_attr_vpd_dimm_spare); if(rc) return rc;
-    }
-
-
-    FAPI_INF("Setting more VPD ATTRS\n");
-
-   //Fix for VPD Mode for lab rdimm and CDIMM B4
-    if((l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_RDIMM) || (l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)
-       || (l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4) ){
-      FAPI_INF("IN RDIMM ATTR SETTING\n");
-      rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc;
-      if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3) { // do not override DDR4 RCD
-        rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-      }
-      rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_CNTL, &i_target_mba, attr_vpd_cen_drv_imp_cntl); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_ADDR, &i_target_mba, attr_vpd_cen_drv_imp_addr); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_CLK, &i_target_mba, attr_vpd_cen_drv_imp_clk); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_SPCKE, &i_target_mba, attr_vpd_cen_drv_imp_spcke); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_CNTL, &i_target_mba, attr_vpd_cen_slew_rate_cntl); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_ADDR, &i_target_mba, attr_vpd_cen_slew_rate_addr); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_CLK, &i_target_mba, attr_vpd_cen_slew_rate_clk); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_SPCKE, &i_target_mba, attr_vpd_cen_slew_rate_spcke); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_vpd_dram_ron); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_vpd_dram_rtt_nom); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_vpd_dram_rtt_wr); if(rc) return rc;
-      if(l_dram_gen_u8 == 2){
-        rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_WRDDR4_VREF, &i_target_mba, attr_eff_dram_wrddr4_vref); if(rc) return rc;
-      }
-      rc = FAPI_ATTR_SET(ATTR_VPD_ODT_RD, &i_target_mba, attr_vpd_odt_rd); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_ODT_WR, &i_target_mba, attr_vpd_odt_wr); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, attr_vpd_cen_phase_rot_m0_clk_p0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1, &i_target_mba, attr_vpd_cen_phase_rot_m0_clk_p1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0, &i_target_mba, attr_vpd_cen_phase_rot_m1_clk_p0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1, &i_target_mba, attr_vpd_cen_phase_rot_m1_clk_p1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a4); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a5); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a6); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a7); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a8); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a9); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a10); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a11); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a12); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a13); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a14); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a15); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_bA0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_bA1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_bA2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_casn); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_rasn); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_wen); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_PAR, &i_target_mba, attr_vpd_cen_phase_rot_m_par); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_ACTN, &i_target_mba, attr_vpd_cen_phase_rot_m_actn); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_odt0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_odt1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_odt0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_odt1); if(rc) return rc;
-//   rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_2N_MODE_ENABLED, &i_target_mba, attr_eff_dram_2n_mode_enabled); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_RLO, &i_target_mba, attr_eff_rlo); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_WLO, &i_target_mba, attr_eff_wlo); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_GPO, &i_target_mba, attr_eff_gpo); if(rc) return rc;
-
-    }
-#ifdef FAPIECMD
-    if(l_lab_raw_card_u8 == fapi::ENUM_ATTR_LAB_ONLY_RAW_CARD_KG3){
-      FAPI_INF("IN KGC ATTR SET\n");
-      rc = FAPI_ATTR_SET(ATTR_MSS_CAL_STEP_ENABLE, &i_target_mba, l_attr_mss_cal_step_enable); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_CNTL_WORD_0_15, &i_target_mba, l_attr_eff_dimm_rcd_cntl_word_0_15); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_IBT, &i_target_mba, attr_eff_dimm_rcd_ibt); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RCD_MIRROR_MODE, &i_target_mba, attr_eff_dimm_rcd_mirror_mode); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_RD_VREF, &i_target_mba, attr_eff_cen_rd_vref); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_WR_VREF, &i_target_mba, attr_eff_dram_wr_vref); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_RCV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_rcv_imp_dq_dqs); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS, &i_target_mba, attr_eff_cen_drv_imp_dq_dqs); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_CNTL, &i_target_mba, attr_vpd_cen_drv_imp_cntl); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_ADDR, &i_target_mba, attr_vpd_cen_drv_imp_addr); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_CLK, &i_target_mba, attr_vpd_cen_drv_imp_clk); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_SPCKE, &i_target_mba, attr_vpd_cen_drv_imp_spcke); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_CNTL, &i_target_mba, attr_vpd_cen_slew_rate_cntl); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_ADDR, &i_target_mba, attr_vpd_cen_slew_rate_addr); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_CLK, &i_target_mba, attr_vpd_cen_slew_rate_clk); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_SPCKE, &i_target_mba, attr_vpd_cen_slew_rate_spcke); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RON, &i_target_mba, attr_vpd_dram_ron); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_NOM, &i_target_mba, attr_vpd_dram_rtt_nom); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_RTT_WR, &i_target_mba, attr_vpd_dram_rtt_wr); if(rc) return rc;
-      if(l_dram_gen_u8 == 2){
-        rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_WRDDR4_VREF, &i_target_mba, attr_eff_dram_wrddr4_vref); if(rc) return rc;
-      }
-      rc = FAPI_ATTR_SET(ATTR_VPD_ODT_RD, &i_target_mba, attr_vpd_odt_rd); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_ODT_WR, &i_target_mba, attr_vpd_odt_wr); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0, &i_target_mba, attr_vpd_cen_phase_rot_m0_clk_p0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1, &i_target_mba, attr_vpd_cen_phase_rot_m0_clk_p1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0, &i_target_mba, attr_vpd_cen_phase_rot_m1_clk_p0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1, &i_target_mba, attr_vpd_cen_phase_rot_m1_clk_p1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a4); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a5); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a6); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a7); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a8); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a9); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a10); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a11); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a12); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a13); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a14); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_a15); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_bA0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_bA1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_bA2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_casn); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_rasn); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN, &i_target_mba, attr_vpd_cen_phase_rot_m_cmd_wen); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_PAR, &i_target_mba, attr_vpd_cen_phase_rot_m_par); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M_ACTN, &i_target_mba, attr_vpd_cen_phase_rot_m_actn); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_cke3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_csn3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_odt0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1, &i_target_mba, attr_vpd_cen_phase_rot_m0_cntl_odt1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_cke3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn1); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn2); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_csn3); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_odt0); if(rc) return rc;
-      rc = FAPI_ATTR_SET(ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1, &i_target_mba, attr_vpd_cen_phase_rot_m1_cntl_odt1); if(rc) return rc;
-
-    }
-#endif
-
-
-    if(l_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM)
-    {
-       if(l_dram_gen_u8 == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3)
-       {
-          rc = mss_lrdimm_term_atts(i_target_mba);
-       }
-       else
-       {
-          rc = mss_lrdimm_ddr4_term_atts(i_target_mba);
-       }
-
-      if (rc)
-      {
-        FAPI_ERR("Setting LR term atts failed \n");
-        return rc;
-      }
-    }
-
-    FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
-    return rc;
-
-  }
-
- ////////////////////////////////////////////////////////////////////////////////////////////
-  fapi::ReturnCode mss_eff_config_termination_vpd(const fapi::Target& i_target_mba) {
-    fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-    const char * const PROCEDURE_NAME = "mss_eff_config_termination_vpd";
-    FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
-
-   //for xml error usage
-   const fapi::Target& TARGET_MBA = i_target_mba;
-
-    do {
-      std::vector<fapi::Target> l_target_dimm_array;
-      uint8_t spd_custom;
-      uint8_t spd_device_type;
-
-      rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array);
-      if(rc)
-      {
-        FAPI_ERR("Error retrieving assodiated dimms");
-        return rc;
-      }
-//------------------------------------------------------------------------------
-      for (uint8_t l_dimm_index = 0; l_dimm_index <
-        l_target_dimm_array.size(); l_dimm_index += 1)
-      {
-        rc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM, &l_target_dimm_array[l_dimm_index],
-                           spd_custom);
-        if(rc) break;
-
-        rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &l_target_dimm_array[l_dimm_index],
-                           spd_device_type);
-        if(rc) break;
-      }
-      if(rc) break;
-
-      if ((spd_custom == fapi::ENUM_ATTR_SPD_CUSTOM_NO) || spd_device_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4) {
-
- // update soem constants for ISDIMMs
-
-           // Get a vector of DIMM targets
-        rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array, fapi::TARGET_STATE_PRESENT);
-        if (rc) return rc;
-        for (uint32_t k=0; k < l_target_dimm_array.size(); k++)
-        {
-          uint32_t version0 = 0x00;
-          rc = FAPI_ATTR_SET(ATTR_VPD_VERSION, &l_target_dimm_array[k], version0); // early VPD versions use fixed TSYS,
-          if (rc) return rc;
-        }
-
-        uint32_t attr_vpd_cke_pri_map[2] = { 0x00008484, 0x00002121 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CKE_PRI_MAP, &i_target_mba, attr_vpd_cke_pri_map);
-        if (rc) return rc;
-
-        uint64_t attr_vpd_cke_pwr_map = 0xde007b00de007b00ull;
-        rc = FAPI_ATTR_SET(ATTR_VPD_CKE_PWR_MAP,  &i_target_mba,  attr_vpd_cke_pwr_map);
-        if (rc) return rc;
-
-        uint8_t attr_vpd_dram_2n_mode_enabled = 0x00;
-        rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_2N_MODE_ENABLED,  &i_target_mba,  attr_vpd_dram_2n_mode_enabled);
-        if (rc) return rc;
-
-        uint8_t l_attr_vpd_dimm_spare[2][2][4] = {{{0,0,0,0},{0,0,0,0}},{{0,0,0,0},{0,0,0,0}}};
-        rc = FAPI_ATTR_SET(ATTR_VPD_DIMM_SPARE, &i_target_mba, l_attr_vpd_dimm_spare); if(rc) return rc;
-        if(rc) return rc;
-
-        uint32_t attr_vpd_cen_rd_vref[2] = { 0x0000c350, 0x0000c350 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_RD_VREF,  &i_target_mba, attr_vpd_cen_rd_vref);
-        if (rc) return rc;
-
-        uint32_t attr_vpd_dram_wr_vref[2] = { 0x000001f4, 0x000001f4 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_WR_VREF,  &i_target_mba, attr_vpd_dram_wr_vref);
-        if (rc) return rc;
-
-        uint8_t attr_vpd_dram_wrddr4_vref[2] = { 0x18, 0x18};
-        rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_WRDDR4_VREF,  &i_target_mba, attr_vpd_dram_wrddr4_vref);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_rcv_imp_dq_dqs[2] = {  0x3c, 0x3c };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_RCV_IMP_DQ_DQS,  &i_target_mba, attr_vpd_cen_rcv_imp_dq_dqs);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_drv_imp_dq_dqs[2] = {  0x07, 0x07 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_DQ_DQS,  &i_target_mba, attr_vpd_cen_drv_imp_dq_dqs);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_drv_imp_cntl[2] = {  0x28, 0x28 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_CNTL,  &i_target_mba, attr_vpd_cen_drv_imp_cntl);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_drv_imp_addr[2] = {  0x28, 0x28 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_ADDR,  &i_target_mba, attr_vpd_cen_drv_imp_addr);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_drv_imp_clk[2] = {  0x28, 0x28 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_CLK,  &i_target_mba, attr_vpd_cen_drv_imp_clk);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_drv_imp_spcke[2] = {  0x28, 0x28 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_DRV_IMP_SPCKE,  &i_target_mba, attr_vpd_cen_drv_imp_spcke);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_slew_rate_dq_dqs[2] = {  0x04, 0x04 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_DQ_DQS,  &i_target_mba, attr_vpd_cen_slew_rate_dq_dqs);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_slew_rate_cntl[2] = {  0x03, 0x03 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_CNTL,  &i_target_mba, attr_vpd_cen_slew_rate_cntl);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_slew_rate_addr[2] = {  0x03, 0x03 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_ADDR,  &i_target_mba, attr_vpd_cen_slew_rate_addr);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_slew_rate_clk[2] = {  0x03, 0x03 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_CLK,  &i_target_mba, attr_vpd_cen_slew_rate_clk);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_cen_slew_rate_spcke[2] = {  0x03, 0x03 };
-        rc = FAPI_ATTR_SET(ATTR_VPD_CEN_SLEW_RATE_SPCKE,  &i_target_mba, attr_vpd_cen_slew_rate_spcke);
-        if(rc) return rc;
-
-        uint8_t attr_vpd_dram_address_mirroring[2][2] = {{  0x00, 0x00 },{0x00, 0x00}};
-        rc = FAPI_ATTR_SET(ATTR_VPD_DRAM_ADDRESS_MIRRORING,  &i_target_mba, attr_vpd_dram_address_mirroring);
-        if(rc) return rc;
-
- ////////////////////////////////////////////////////////////////////////////////////////////
-
-        fapi::Target target_chip;
-        rc = fapiGetParentChip(i_target_mba, target_chip);
-        if (rc) {
-          FAPI_ERR("Error calling fapiGetParentChip");
-          return rc;
-        }
-
-        uint32_t slope = 0x0000c1be;
-        uint32_t intercept = 0x0000c06a;
-        rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_MASTER_POWER_SLOPE, &target_chip, slope);
-        if (rc) return rc;
-
-        rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT, &target_chip, intercept);
-        if (rc) return rc;
-
-        rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE, &target_chip, slope);
-        if (rc) return rc;
-
-        rc = FAPI_ATTR_SET(ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT, &target_chip, intercept);
-        if (rc) return rc;
-      }
-      if(rc) break;
- ////////////////////////////////////////////////////////////////////////////////////////////
-
-
-    } while (0);
-
-    FAPI_INF("%s on %s COMPLETE", PROCEDURE_NAME, i_target_mba.toEcmdString());
-    return rc;
-
-  }
- ////////////////////////////////////////////////////////////////////////////////////////////
-
-
-} // extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.H
deleted file mode 100644
index de5037f37..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.H
+++ /dev/null
@@ -1,79 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_termination.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_termination.H,v 1.3 2014/03/05 21:16:57 dcadiga Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_config_termination.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_termination.H
-// *! DESCRIPTION : Header file for mss_eff_config_termination.
-// *! OWNER NAME  : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.4   | dcadiga  |05-MAR-14|Added term vpd
-//   1.3   |          |         |
-//   1.2   | asaetow  |22-JAN-14| Fixed target "const fapi::Target" to "const fapi::Target&" for mss_eff_config.C v1.38 and mss_eff_config_termination.C v1.42
-//   1.1   | asaetow  |25-APR-12| First Draft.
-
-
-#ifndef MSS_EFF_CONFIG_TERMINATION_H_
-#define MSS_EFF_CONFIG_TERMINATION_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-typedef fapi::ReturnCode (*mss_eff_config_termination_FP_t)(const fapi::Target& i_target_mba);
-
-extern "C" {
-
-//******************************************************************************
-//* name=mss_eff_config_termination, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_config_termination(const fapi::Target& i_target_mba);
-fapi::ReturnCode mss_eff_config_termination_vpd(const fapi::Target& i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_EFF_CONFIG_TERMINATION_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
deleted file mode 100644
index dc8d30b30..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C
+++ /dev/null
@@ -1,995 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.C,v 1.34 2015/10/20 13:44:46 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_thermal
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Jacob Sloat       Email: jdsloat@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// applicable CQ component memory_screen
-//
-// DESCRIPTION:
-// The purpose of this procedure is to set the default throttle and power
-// attributes for dimms in a given system
-// -- The power attributes are the slope/intercept values.  Note that these
-//    values are in cW.
-//    -- ISDIMM will calculate values based on various attributes
-//    -- CDIMM will get values from VPD
-// -- The throttle attributes will setup values for IPL and runtime
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.34  | pardeik  | 10/20/15| change fapilogerror (not recoverable)
-//   1.33  | pardeik  | 07/31/15| Support new CDIMM total power curves (SW316162)
-//         |          |         | Only log one error per MBA intead of per DIMM 
-//   1.32  | pardeik  | 06/16/15| fix for ISDIMM systems to prevent a zero
-//         |          |         |   ATTR_MSS_MEM_WATT_TARGET value
-//         |          |         | Removed unneeded TODO commented section
-//   1.31  | pardeik  | 04/06/15 | attribute name changed for adjustment enable
-//   1.30  | pardeik  |12-FEB-15| CDIMM DDR4 throttle updates (set Nmba to Nchip)
-//         |          |         | Support for vmem regulator power adjustment
-//   1.29  | pardeik  |06-NOV-14| removed strings in trace statements
-//         |          |         | changed FAPI_IMP to FAPI_INF
-//         |          |         | removed unused constants
-//   1.28  | pardeik  |28-OCT-14| Updates for non custom dimm power procedure
-//         |          |         |  Removed mss_eff_config_thermal_term
-//         |          |         |  Removed mss_eff_config_thermal_get_wc_term
-//         |          |         |  Removed mss_eff_config_thermal_get_cen_drv_value
-//         |          |         |  Updates to mss_eff_config_thermal_powercurve
-//   1.27  | pardeik  |22-MAY-14| Removed attribute update section not needed
-//         |          |         | Initialize runtime throttle attributes before
-//         |          |         |   calling bulk_pwr_throttles
-//         |          |         | RAS update to split code into smaller
-//         |          |         |   subfunctions (powercurve and throttles)
-//   1.26  | jdsloat  |10-MAR-14| Edited comments
-//   1.25  | pardeik  |21-JAN-14| fixed default power curve values for CDIMM
-//         |          |         | removed unneeded comments
-//   1.24  | pardeik  |20-DEC-13| only get power curve attributes if custom dimm
-//   1.23  | pardeik  |02-DEC-13| enable supplier power curve attributes
-//   1.22  | pardeik  |18-NOV-13| rename attributes (eff to vpd)
-//   1.21  | pardeik  |14-NOV-13| hardcode supplier power curves until lab is
-//         |          |         | using read VPD
-//   1.20  | pardeik  |13-NOV-13| enable power curve attribute data from VPD
-//   1.19  | pardeik  |23-SEP-13| initial support for the ras/cas increments
-//   1.18  | bellows  |19-SEP-13| fixed possible buffer overrun found by stradale
-//   1.17  | pardeik  |19-JUL-13| Use runtime throttles for IPL for scominit
-//         |          |         | Removed MRW safemode throttle stuff
-//         |          |         | Always determine runtime throttles now
-//   1.16  | pardeik  |08-JUL-13| Using CUSTOM_DIMM attribute
-//         |          |         | Initialize some termination variables to zero
-//         |          |         | changed handling of TYPE_1D
-//         |          |         | only get NUM_OF_REGISTERS_USED_ON_RDIMM 
-//         |          |         |   for RDIMM (non custom)
-//         |          |         | get thermal power limit from MRW
-//   1.15  | pardeik  |11-FEB-13| set safemode throttles to unthrottled value
-//         |          |         | for lab until fw sets runtime throttles
-//   1.14  | pardeik  |03-DEC-12| update lines to have a max width of 80 chars
-//         |          |         | added FAPI_ERR before return code lines
-//         |          |         | made trace statements for procedures FAPI_IMP
-//         |          |         | changed some FAPI_INF to FAPI_DBG
-//         |          |         | set per_chip safemode throttles to 32
-//         |          |         | updates for FAPI_SET_HWP_ERROR
-//   1.13  | pardeik  |28-NOV-12| fixed hostboot compile errors
-//   1.12  | pardeik  |07-NOV-12| updated to use new SI attributes and their
-//         |          |         | enums
-//   1.11  | pardeik  |22-OCT-12| Use the schmoo attributes to find wc
-//         |          |         | termination, updated hwp errors, removed
-//         |          |         | unneeded variables, added CQ component comment
-//         |          |         | line, updated safemode throttle default values
-//   1.10  | pardeik  |19-OCT-12| Enable TYPE_1D for ODT mapping.  Set ISDIMM
-//         |          |         | supplier power curve to master power curve
-//   1.9   | pardeik  |11-OCT-12| updated to use new attributes, termination
-//         |          |         | power calculation added in
-//   1.8   | pardeik  |13-JUN-12| Major rewrite to have dimm power determined by
-//         |          |         | dram generation and width, with uplifts
-//         |          |         | applied (not based on dimm size lookup table
-//         |          |         | any longer)
-//   1.7   | pardeik  |04-MAY-12| removed typedef from structures, use fapi to
-//         |          |         | define dimm type enums
-//   1.6   | pardeik  |10-APR-12| update cdimm power/int default, change
-//         |          |         | power_thermal_values_t to use int32_t instead
-//         |          |         | of uint32_t in order to identify a negative
-//         |          |         | value correctly, added dimm config to the
-//         |          |         | messages printed out
-//   1.5   | pardeik  |03-APR-12| fix cdimm size/rank addition to cycle through
-//         |          |         | both mba's
-//   1.4   | pardeik  |26-MAR-12| Rewrite to iterate through the MBA's using
-//         |          |         | fapi functions
-//         | pardeik  |01-DEC-11| Updated to align with procedure definition
-//   1.3   | asaetow  |03-NOV-11| Fixed to comply with mss_eff_config_thermal.H
-//   1.2   | asaetow  |03-NOV-11| Changed format of file and made function lower
-//         |          |         | case. 
-//   1.1   | pardeik  |01-NOV-11| First Draft.
-
-
-//------------------------------------------------------------------------------
-//  My Includes
-//------------------------------------------------------------------------------
-#include <mss_eff_config_thermal.H>
-#include <mss_bulk_pwr_throttles.H>
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-//  Constants
-//------------------------------------------------------------------------------
-const uint8_t NUM_PORTS = 2;
-const uint8_t NUM_DIMMS = 2;
-const uint8_t NUM_RANKS = 4;
-// Only use values here (not any valid bits or flag bits)
-const uint32_t CDIMM_POWER_SLOPE_DEFAULT = 0x0358;
-const uint32_t CDIMM_POWER_INT_DEFAULT = 0x00CE;
-
-extern "C" {
-
-    using namespace fapi;
-
-//------------------------------------------------------------------------------
-// Funtions in this file
-//------------------------------------------------------------------------------
-    fapi::ReturnCode mss_eff_config_thermal(
-					    const fapi::Target & i_target_mba
-					    );
-
-    fapi::ReturnCode mss_eff_config_thermal_powercurve(
-					    const fapi::Target & i_target_mba
-					    );
-
-    fapi::ReturnCode mss_eff_config_thermal_throttles(
-					    const fapi::Target & i_target_mba
-					    );
-
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal(): This function determines the
-// power curve and throttle attribute values to use
-//
-// @param[in]	const fapi::Target & i_target_mba:  MBA Target passed in
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba)
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_eff_config_thermal on %s ***",
-		 i_target_mba.toEcmdString());
-
-	rc = mss_eff_config_thermal_powercurve(i_target_mba);
-	if (rc)
-	{
-	    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_powercurve", static_cast<uint32_t>(rc));
-	    return rc;
-	}
-	rc = mss_eff_config_thermal_throttles(i_target_mba);
-	if (rc)
-	{
-	    FAPI_ERR("Error (0x%x) calling mss_eff_config_thermal_throttles", static_cast<uint32_t>(rc));
-	    return rc;
-	}
-
-
-	FAPI_INF("*** mss_eff_config_thermal COMPLETE on %s ***",
-		 i_target_mba.toEcmdString());
-	return rc;
-    }
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal_powercurve(): This function determines the
-// power curve attribute values to use
-//
-// @param[in]	const fapi::Target & i_target_mba:  MBA Target passed in
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_eff_config_thermal_powercurve(const fapi::Target & i_target_mba)
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_eff_config_thermal_powercurve on %s ***",
-		 i_target_mba.toEcmdString());
-
-// other variables used in this function
-	fapi::Target target_chip;
-	uint8_t port;
-	uint8_t dimm;
-	uint8_t custom_dimm;
-	uint8_t dimm_ranks_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t power_slope_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t power_int_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t power_slope2_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t power_int2_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t total_power_slope_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t total_power_int_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t total_power_slope2_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t total_power_int2_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t cdimm_master_power_slope;
-	uint32_t cdimm_master_power_intercept;
-	uint32_t cdimm_supplier_power_slope;
-	uint32_t cdimm_supplier_power_intercept;
-	uint32_t cdimm_master_total_power_slope = 0;
-	uint32_t cdimm_master_total_power_intercept = 0;
-	uint32_t cdimm_supplier_total_power_slope = 0;
-	uint32_t cdimm_supplier_total_power_intercept = 0;
-	uint8_t l_dram_gen;
-	uint8_t l_logged_error_power_curve = 0;
-	uint8_t l_logged_error_total_power_curve = 0;
-//------------------------------------------------------------------------------
-// Get input attributes
-//------------------------------------------------------------------------------
-
-// Get Centaur target for the given MBA
-	rc = fapiGetParentChip(i_target_mba, target_chip);
-	if (rc) {
-	    FAPI_ERR("Error from fapiGetParentChip");
-	    return rc;
-	}
-
-	rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, custom_dimm);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_CUSTOM_DIMM");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,
-			   &i_target_mba, dimm_ranks_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_RANKS_PER_DIMM");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN,
-			   &i_target_mba, l_dram_gen);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_GEN");
-	    return rc;
-	}
-	// Only get power curve values for custom dimms to prevent errors
-	if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-	    // These are the CDIMM power curve values for only VMEM (DDR3 and DDR4)
-	    rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_POWER_SLOPE,
-			       &target_chip, cdimm_master_power_slope);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_POWER_SLOPE");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT,
-			       &target_chip, cdimm_master_power_intercept);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_POWER_INTERCEPT");
-		return rc;
-	    }
-
-	    rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE,
-			       &target_chip, cdimm_supplier_power_slope);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_POWER_SLOPE");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT,
-			       &target_chip, cdimm_supplier_power_intercept);
-	    if (rc) {
-		FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_POWER_INTERCEPT");
-		return rc;
-	    }
-
-	    // These are for the total CDIMM power (VMEM+VPP for DDR4)
-	    if (l_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-	    {
-
-		rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_TOTAL_POWER_SLOPE,
-				   &target_chip, cdimm_master_total_power_slope);
-		if (rc) {
-		    FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_TOTAL_POWER_SLOPE");
-		    return rc;
-		}
-		rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_MASTER_TOTAL_POWER_INTERCEPT,
-				   &target_chip, cdimm_master_total_power_intercept);
-		if (rc) {
-		    FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_MASTER_TOTAL_POWER_INTERCEPT");
-		    return rc;
-		}
-
-		rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_TOTAL_POWER_SLOPE,
-				   &target_chip, cdimm_supplier_total_power_slope);
-		if (rc) {
-		    FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_TOTAL_POWER_SLOPE");
-		    return rc;
-		}
-		rc = FAPI_ATTR_GET(ATTR_CDIMM_VPD_SUPPLIER_TOTAL_POWER_INTERCEPT,
-				   &target_chip, cdimm_supplier_total_power_intercept);
-		if (rc) {
-		    FAPI_ERR("Error getting attribute ATTR_CDIMM_VPD_SUPPLIER_TOTAL_POWER_INTERCEPT");
-		    return rc;
-		}
-	    }
-	    else
-	    {
-// Set total power curve variables to the VMEM power curve variables for DDR3
-		cdimm_master_total_power_slope = cdimm_master_power_slope;
-		cdimm_master_total_power_intercept = cdimm_master_power_intercept;
-		cdimm_supplier_total_power_slope = cdimm_supplier_power_slope;
-		cdimm_supplier_total_power_intercept = cdimm_supplier_power_intercept;
-	    }
-	}
-
-//------------------------------------------------------------------------------
-// Power Curve Determination
-//------------------------------------------------------------------------------
-// Iterate through the MBA ports to get power slope/intercept values
-	for (port=0; port < NUM_PORTS; port++)
-	{
-// iterate through the dimms on each port again to determine power slope and
-// intercept
-	    for (dimm=0; dimm < NUM_DIMMS; dimm++)
-	    {
-// initialize dimm entries to zero
-		power_slope_array[port][dimm] = 0;
-		power_int_array[port][dimm] = 0;
-		power_slope2_array[port][dimm] = 0;
-		power_int2_array[port][dimm] = 0;
-		total_power_slope_array[port][dimm] = 0;
-		total_power_int_array[port][dimm] = 0;
-		total_power_slope2_array[port][dimm] = 0;
-		total_power_int2_array[port][dimm] = 0;
-// only update values for dimms that are physically present
-		if (dimm_ranks_array[port][dimm] > 0)
-		{
-
-// CDIMM power slope/intercept will come from VPD
-// Data in VPD needs to be the power per virtual dimm on the CDIMM
-		    if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-		    {
-			power_slope_array[port][dimm] =
-			  cdimm_master_power_slope;
-			power_int_array[port][dimm] =
-			  cdimm_master_power_intercept;
-			power_slope2_array[port][dimm] =
-			  cdimm_supplier_power_slope;
-			power_int2_array[port][dimm] =
-			  cdimm_supplier_power_intercept;
-			total_power_slope_array[port][dimm] =
-			  cdimm_master_total_power_slope;
-			total_power_int_array[port][dimm] =
-			  cdimm_master_total_power_intercept;
-			total_power_slope2_array[port][dimm] =
-			  cdimm_supplier_total_power_slope;
-			total_power_int2_array[port][dimm] =
-			  cdimm_supplier_total_power_intercept;
-
-// check to see if VMEM power curve data is valid
-			if (
-			    (((cdimm_master_power_slope & 0x8000) != 0) &&
-			     ((cdimm_master_power_intercept & 0x8000) != 0))
-			    &&
-			    (((cdimm_supplier_power_slope & 0x8000) != 0) &&
-			     ((cdimm_supplier_power_intercept & 0x8000) != 0))
-			    )
-			{
-			    power_slope_array[port][dimm] =
-			      cdimm_master_power_slope & 0x1FFF;
-			    power_int_array[port][dimm] =
-			      cdimm_master_power_intercept & 0x1FFF;
-			    power_slope2_array[port][dimm] =
-			      cdimm_supplier_power_slope & 0x1FFF;
-			    power_int2_array[port][dimm] =
-			      cdimm_supplier_power_intercept & 0x1FFF;
-// check to see if data is lab data
-			    if (
-				(((cdimm_master_power_slope & 0x4000) == 0) ||
-				 ((cdimm_master_power_intercept & 0x4000) == 0))
-				||
-				(((cdimm_supplier_power_slope & 0x4000) == 0) ||
-				 ((cdimm_supplier_power_intercept &
-				   0x4000) == 0))
-				)
-			    {
-				FAPI_INF("WARNING:  VMEM power curve data is lab data, not ship level data. Using data anyways.");
-			    }
-// check total power curve (VMEM+VPP) values for DDR4
-			    if (l_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-			    {
-				if (
-				    (((cdimm_master_total_power_slope & 0x8000) != 0) &&
-				     ((cdimm_master_total_power_intercept & 0x8000) != 0))
-				    &&
-				    (((cdimm_supplier_total_power_slope & 0x8000) != 0) &&
-				     ((cdimm_supplier_total_power_intercept & 0x8000) != 0))
-				    )
-				{
-				    total_power_slope_array[port][dimm] =
-				      cdimm_master_total_power_slope & 0x1FFF;
-				    total_power_int_array[port][dimm] =
-				      cdimm_master_total_power_intercept & 0x1FFF;
-				    total_power_slope2_array[port][dimm] =
-				      cdimm_supplier_total_power_slope & 0x1FFF;
-				    total_power_int2_array[port][dimm] =
-				      cdimm_supplier_total_power_intercept & 0x1FFF;
-// check to see if data is lab data
-				    if (
-					(((cdimm_master_total_power_slope & 0x4000) == 0) ||
-					 ((cdimm_master_total_power_intercept & 0x4000) == 0))
-					||
-					(((cdimm_supplier_total_power_slope & 0x4000) == 0) ||
-					 ((cdimm_supplier_total_power_intercept &
-					   0x4000) == 0))
-					)
-				    {
-					FAPI_INF("WARNING:  Total power curve data is lab data, not ship level data. Using data anyways.");
-				    }
-				}
-				else
-				{
-// Set to VMEM power curve values if total values are not valid and log an error
-// early DDR4 CDIMMs will have the total power curve entries all zero (not valid)
-				    total_power_slope_array[port][dimm] =
-				      power_slope_array[port][dimm];
-				    total_power_int_array[port][dimm] =
-				      power_int_array[port][dimm];
-				    total_power_slope2_array[port][dimm] =
-				      power_slope2_array[port][dimm];
-				    total_power_int2_array[port][dimm] =
-				      power_int2_array[port][dimm];
-// only log the error once per MBA, since all dimms will have the same power curve values
-				    if (l_logged_error_total_power_curve == 0)
-				    {
-					l_logged_error_total_power_curve = 1;
-					FAPI_ERR("Total power curve data not valid, use default values");
-					const fapi::Target & MEM_CHIP =
-					  target_chip;
-					uint32_t FFDC_DATA_1 =
-					  cdimm_master_total_power_slope;
-					uint32_t FFDC_DATA_2 =
-					  cdimm_master_total_power_intercept;
-					uint32_t FFDC_DATA_3 =
-					  cdimm_supplier_total_power_slope;
-					uint32_t FFDC_DATA_4 =
-					  cdimm_supplier_total_power_intercept;
-					FAPI_SET_HWP_ERROR
-					  (rc, RC_MSS_DIMM_POWER_CURVE_DATA_INVALID);
-					if (rc) fapiLogError(rc);
-				    }
-				}
-			    }
-			    else
-			    {
-// Set total power curve values to VMEM power curve values for anything other than DDR4 (ie.  DDR3)
-				total_power_slope_array[port][dimm] =
-				  power_slope_array[port][dimm];
-				total_power_int_array[port][dimm] =
-				  power_int_array[port][dimm];
-				total_power_slope2_array[port][dimm] =
-				  power_slope2_array[port][dimm];
-				total_power_int2_array[port][dimm] =
-				  power_int2_array[port][dimm];
-			    }
-			}
-			else
-			{
-// Set to default values and log an error if VMEM power curve values are not valid
-			    power_slope_array[port][dimm] =
-			      CDIMM_POWER_SLOPE_DEFAULT;
-			    power_int_array[port][dimm] =
-			      CDIMM_POWER_INT_DEFAULT;
-			    power_slope2_array[port][dimm] =
-			      CDIMM_POWER_SLOPE_DEFAULT;
-			    power_int2_array[port][dimm] =
-			      CDIMM_POWER_INT_DEFAULT;
-			    total_power_slope_array[port][dimm] =
-			      CDIMM_POWER_SLOPE_DEFAULT;
-			    total_power_int_array[port][dimm] =
-			      CDIMM_POWER_INT_DEFAULT;
-			    total_power_slope2_array[port][dimm] =
-			      CDIMM_POWER_SLOPE_DEFAULT;
-			    total_power_int2_array[port][dimm] =
-			      CDIMM_POWER_INT_DEFAULT;
-// only log the error once per MBA, since all dimms will have the same power curve values
-			    if (l_logged_error_power_curve == 0)
-			    {
-				l_logged_error_power_curve = 1;
-				FAPI_ERR("VMEM power curve data not valid, use default values");
-				const fapi::Target & MEM_CHIP =
-				  target_chip;
-				uint32_t FFDC_DATA_1 =
-				  cdimm_master_power_slope;
-				uint32_t FFDC_DATA_2 =
-				  cdimm_master_power_intercept;
-				uint32_t FFDC_DATA_3 =
-				  cdimm_supplier_power_slope;
-				uint32_t FFDC_DATA_4 =
-				  cdimm_supplier_power_intercept;
-				FAPI_SET_HWP_ERROR
-				  (rc, RC_MSS_DIMM_POWER_CURVE_DATA_INVALID);
-				if (rc) fapiLogError(rc);
-			    }
-			}
-			FAPI_DBG("CDIMM VMEM Power [P%d:D%d][SLOPE=%d:INT=%d cW][SLOPE2=%d:INT2=%d cW]", port, dimm, power_slope_array[port][dimm], power_int_array[port][dimm], power_slope2_array[port][dimm], power_int2_array[port][dimm]);
-			FAPI_DBG("CDIMM Total Power [P%d:D%d][VMEM SLOPE=%d:INT=%d cW][VMEM SLOPE2=%d:INT2=%d cW]", port, dimm, total_power_slope_array[port][dimm], total_power_int_array[port][dimm], total_power_slope2_array[port][dimm], total_power_int2_array[port][dimm]);
-		    }
-// non custom dimms will no longer use power curves
-// These will use a simplified approach of using throttle values for certain ranges of power
-// in mss_bulk_pwr_throttles.
-		}
-	    }
-	}
-
-// write output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE,
-			   &i_target_mba, power_slope_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_SLOPE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT, &i_target_mba, power_int_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_INT");
-	    return rc;
-	}
-
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_SLOPE2,
-			   &i_target_mba, power_slope2_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_SLOPE2");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_POWER_INT2,
-			   &i_target_mba, power_int2_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_POWER_INT2");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_SLOPE,
-			   &i_target_mba, total_power_slope_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_SLOPE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_INT, &i_target_mba, total_power_int_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_INT");
-	    return rc;
-	}
-
-	rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_SLOPE2,
-			   &i_target_mba, total_power_slope2_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_SLOPE2");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_INT2,
-			   &i_target_mba, total_power_int2_array);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_INT2");
-	    return rc;
-	}
-
-	FAPI_INF("*** mss_eff_config_thermal_powercurve COMPLETE on %s ***",
-		 i_target_mba.toEcmdString());
-	return rc;
-    }
-
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal_throttles(): This function determines the
-// throttle attribute values to use
-//
-// @param[in]	const fapi::Target & i_target_mba:  MBA Target passed in
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_eff_config_thermal_throttles(const fapi::Target & i_target_mba)
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_eff_config_thermal_throttles on %s ***",
-		 i_target_mba.toEcmdString());
-
-// variables used in this function
-	fapi::Target target_chip;
-	std::vector<fapi::Target> target_mba_array;
-	std::vector<fapi::Target> target_dimm_array;
-	uint8_t custom_dimm;
-	uint8_t num_dimms_on_port;
-	uint32_t runtime_throttle_n_per_mba;
-	uint32_t runtime_throttle_n_per_chip;
-	uint32_t runtime_throttle_d;
-	uint32_t dimm_thermal_power_limit;
-	uint32_t channel_pair_thermal_power_limit;
-	uint8_t num_mba_with_dimms = 0;
-	uint8_t mba_index;
-	uint8_t ras_increment;
-	uint8_t cas_increment;
-	uint32_t l_max_dram_databus_util;
-	uint32_t l_dimm_reg_power_limit_per_dimm_adj;
-	uint32_t l_dimm_reg_power_limit_per_dimm;
-	uint8_t l_max_number_dimms_per_reg;
-	uint8_t l_dimm_reg_power_limit_adj_enable;
-	uint8_t l_reg_max_dimm_count;
-	uint8_t l_dram_gen;
-	uint32_t l_power_slope_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t l_power_int_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t l_total_power_slope_array[NUM_PORTS][NUM_DIMMS];
-	uint32_t l_total_power_int_array[NUM_PORTS][NUM_DIMMS];
-
-//------------------------------------------------------------------------------
-// Get input attributes
-//------------------------------------------------------------------------------
-
-// Get Centaur target for the given MBA
-	rc = fapiGetParentChip(i_target_mba, target_chip);
-	if (rc) {
-	    FAPI_ERR("Error from fapiGetParentChip");
-	    return rc;
-	}
-
-	rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, custom_dimm);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_CUSTOM_DIMM");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT,
-			   &i_target_mba, num_dimms_on_port);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_DROPS_PER_PORT");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT,
-			   NULL, dimm_thermal_power_limit);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_THERMAL_MEMORY_POWER_LIMIT");
-	    return rc;
-	}
-
-	rc = FAPI_ATTR_GET(ATTR_MRW_MEM_THROTTLE_DENOMINATOR, NULL, runtime_throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_MAX_DRAM_DATABUS_UTIL,
-			   NULL, l_max_dram_databus_util);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MAX_DRAM_DATABUS_UTIL");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM,
-			   NULL, l_dimm_reg_power_limit_per_dimm);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_VMEM_REGULATOR_MEMORY_POWER_LIMIT_PER_DIMM");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR,
-			   NULL, l_max_number_dimms_per_reg);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MAX_NUMBER_DIMMS_POSSIBLE_PER_VMEM_REGULATOR");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE,
-			   NULL, l_dimm_reg_power_limit_adj_enable);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT,
-			   NULL, l_reg_max_dimm_count);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_VMEM_REGULATOR_MAX_DIMM_COUNT");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_GEN,
-			   &i_target_mba, l_dram_gen);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_DRAM_GEN");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_SLOPE,
-			   &i_target_mba, l_power_slope_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_SLOPE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT,
-			   &i_target_mba, l_power_int_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_INT");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_TOTAL_POWER_SLOPE,
-			   &i_target_mba, l_total_power_slope_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_TOTAL_POWER_SLOPE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_TOTAL_POWER_INT,
-			   &i_target_mba, l_total_power_int_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_TOTAL_POWER_INT");
-	    return rc;
-	}
-
-// Get number of Centaur MBAs that have dimms present
-// Custom dimms (CDIMMs) use mba/chip throttling, so count number of mbas that have dimms
-	if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-	    rc = fapiGetChildChiplets(target_chip,
-				      fapi::TARGET_TYPE_MBA_CHIPLET,
-				      target_mba_array,
-				      fapi::TARGET_STATE_PRESENT);
-	    if (rc) {
-		FAPI_ERR("Error from fapiGetChildChiplets");
-		return rc;
-	    }
-	    num_mba_with_dimms = 0;
-	    for (mba_index=0; mba_index < target_mba_array.size(); mba_index++)
-	    {
-		rc = fapiGetAssociatedDimms(target_mba_array[mba_index],
-					    target_dimm_array,
-					    fapi::TARGET_STATE_PRESENT);
-		if (rc) {
-		    FAPI_ERR("Error from fapiGetAssociatedDimms");
-		    return rc;
-		}
-		if (target_dimm_array.size() > 0)
-		{
-		    num_mba_with_dimms++;
-		}
-	    }
-	}
-// ISDIMM (non custom dimm) uses dimm/mba throttling, so set num_mba_with_dimms to 1
-	else
-	{
-	    num_mba_with_dimms = 1;
-	}
-
-
-//------------------------------------------------------------------------------
-// Memory Throttle Determination
-//------------------------------------------------------------------------------
-
-// Determine memory throttle settings needed based on dimm thermal power limit
-
-//------------------------------------------------------------------------------
-// Determine the thermal power limit to use, which represents a single channel
-// pair power limit for the dimms on that channel pair (ie.  power for all dimms
-// attached to one MBA).   The procedure mss_bulk_power_throttles takes the
-// input of channel pair power to determine throttles.
-// CDIMM thermal power limit from MRW is per CDIMM, so divide by number of mbas
-// that have dimms to get channel pair power
-// CDIMM:  Allow all commands to be directed toward one MBA to achieve the power
-// limit
-//   This means that the power limit for a MBA channel pair must be the total
-// CDIMM power limit minus the idle power of the other MBAs logical dimms
-//------------------------------------------------------------------------------
-
-// adjust the regulator power limit per dimm if enabled and use this if less than the thermal limit
-// If reg power limit is zero, then set to thermal limit - needed for ISDIMM systems since some of these MRW attributes are not defined
-	if (l_dimm_reg_power_limit_per_dimm == 0)
-	{
-	    l_dimm_reg_power_limit_per_dimm = dimm_thermal_power_limit;
-	}
-	l_dimm_reg_power_limit_per_dimm_adj = l_dimm_reg_power_limit_per_dimm;
-	if (l_dimm_reg_power_limit_adj_enable == fapi::ENUM_ATTR_MRW_VMEM_REGULATOR_POWER_LIMIT_PER_DIMM_ADJ_ENABLE_TRUE)
-	{
-// adjust reg power limit per cdimm only if l_reg_max_dimm_count>0 and l_reg_max_dimm_count<l_max_number_dimms_per_reg
-	    if (
-		(l_reg_max_dimm_count > 0)
-		 && (l_reg_max_dimm_count < l_max_number_dimms_per_reg)
-		)
-	    {
-		l_dimm_reg_power_limit_per_dimm_adj =
-		  l_dimm_reg_power_limit_per_dimm
-		  * l_max_number_dimms_per_reg
-		  / l_reg_max_dimm_count;
-		FAPI_INF("VMEM Regulator Power/DIMM Limit Adjustment from %d to %d cW (DIMMs under regulator %d/%d)", l_dimm_reg_power_limit_per_dimm, l_dimm_reg_power_limit_per_dimm_adj, l_reg_max_dimm_count, l_max_number_dimms_per_reg);
-	    }
-	}
-// Use the smaller of the thermal limit and regulator power limit per dimm
-	if (l_dimm_reg_power_limit_per_dimm_adj < dimm_thermal_power_limit)
-	{
-	    dimm_thermal_power_limit = l_dimm_reg_power_limit_per_dimm_adj;
-	}
-
-// Adjust the thermal/power limit to represent the power for all dimms under an MBA
-	if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-	    channel_pair_thermal_power_limit =
-	      dimm_thermal_power_limit / num_mba_with_dimms;
-	}
-// ISDIMMs thermal power limit from MRW is per DIMM, so multiply by number of dimms on channel to get channel power and multiply by 2 to get channel pair power
-	else
-	{
-		// ISDIMMs
-	    channel_pair_thermal_power_limit =
-	      dimm_thermal_power_limit * num_dimms_on_port * 2;
-	}
-
-// Update the channel pair power limit attribute
-	rc = FAPI_ATTR_SET(ATTR_MSS_MEM_WATT_TARGET,
-			   &i_target_mba, channel_pair_thermal_power_limit);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_MEM_WATT_TARGET");
-	    return rc;
-	}
-
-// Initialize the runtime throttle attributes to an unthrottled value for mss_bulk_pwr_throttles
-// max utilization comes from MRW value in c% - convert to %
-	float MAX_UTIL = (float) l_max_dram_databus_util / 100;
-	runtime_throttle_n_per_mba = (int)(runtime_throttle_d * (MAX_UTIL / 100) / 4);
-	runtime_throttle_n_per_chip = (int)(runtime_throttle_d * (MAX_UTIL / 100) / 4) *
-	  num_mba_with_dimms;
-
-// for better custom dimm performance for DDR4, set the per mba throttle to the per chip throttle
-// Not planning on doing this for DDR3
-	if ( (l_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-	     && (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES) )
-	{
-	    runtime_throttle_n_per_mba = runtime_throttle_n_per_chip;
-	}
-
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
-			   &i_target_mba, runtime_throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
-			   &i_target_mba, runtime_throttle_n_per_chip);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR,
-			   &i_target_mba, runtime_throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-
-	FAPI_INF("Min Power/Thermal Limit per MBA %d cW.  Unthrottled values [%d/%d/%d].", channel_pair_thermal_power_limit, runtime_throttle_n_per_mba, runtime_throttle_n_per_chip, runtime_throttle_d);
-
-
-// For DDR4, use the VMEM power to determine the runtime throttle settings that are based
-//  on a VMEM power limit (not a VMEM+VPP power limit which is to be used at runtime for tmgt)
-// Need to temporarily override attributes for mss_bulk_pwr_throttles to use
-// Needed to determines runtime memory throttle settings based on any VMEM power limits
-	if (l_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-	{
-	    rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_SLOPE,
-			       &i_target_mba, l_power_slope_array);
-	    if (rc) {
-		FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_SLOPE");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_INT, &i_target_mba, l_power_int_array);
-	    if (rc) {
-		FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_INT");
-		return rc;
-	    }
-	}
-
-// Call the procedure function that takes a channel pair power limit and
-// converts it to throttle values
-	FAPI_EXEC_HWP(rc, mss_bulk_pwr_throttles, i_target_mba);
-	if (rc)
-	{
-	    FAPI_ERR("Error (0x%x) calling mss_bulk_pwr_throttles", static_cast<uint32_t>(rc));
-	    return rc;
-	}
-
-// Reset the total power curve attributes back to the original values
-	if (l_dram_gen == fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR4)
-	{
-	    rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_SLOPE,
-			       &i_target_mba, l_total_power_slope_array);
-	    if (rc) {
-		FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_SLOPE");
-		return rc;
-	    }
-	    rc = FAPI_ATTR_SET(ATTR_MSS_TOTAL_POWER_INT, &i_target_mba, l_total_power_int_array);
-	    if (rc) {
-		FAPI_ERR("Error writing attribute ATTR_MSS_TOTAL_POWER_INT");
-		return rc;
-	    }
-	}
-
-// Read back in the updated throttle attribute values (these are now set to
-// values that will give dimm/channel power underneath the thermal power limit)
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
-			   &i_target_mba, runtime_throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
-			   &i_target_mba, runtime_throttle_n_per_chip);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
-			   &i_target_mba, runtime_throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-
-// Setup the RAS and CAS increments used in the throttling register
-	ras_increment=0;
-	cas_increment=1;
-
-// update output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA,
-			   &i_target_mba, runtime_throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP,
-			   &i_target_mba, runtime_throttle_n_per_chip);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_NUMERATOR_PER_CHIP");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR,
-			   &i_target_mba, runtime_throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_RUNTIME_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT,
-			   &i_target_mba, ras_increment);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT");
-	    return rc;
-	}
-	rc = FAPI_ATTR_SET(ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT,
-			   &i_target_mba, cas_increment);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT");
-	    return rc;
-	}
-
-	FAPI_INF("*** mss_eff_config_thermal_throttles COMPLETE on %s ***",
-		 i_target_mba.toEcmdString());
-	return rc;
-    }
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
deleted file mode 100644
index 8d0ee2f82..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H
+++ /dev/null
@@ -1,85 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_config_thermal.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_config_thermal.H,v 1.5 2012/12/12 20:10:37 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_eff_config_thermal.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_config_thermal.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
-// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_eff_config_thermal.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.5   | pardeik  |03-DEC-12| update lines to have a max width of 80 chars
-//         |          |         | removed variable names in typedef
-//   1.4   | pardeik  |11-OCT-12| change i_target to i_target_mba
-//   1.3   | pardeik  |03-APR-12| use mba target instead of mbs
-//   1.2   | pardeik  |26-MAR-12| Removed structure (going into .C file)
-//         | pardeik  |01-DEC-11| Added structures and defines
-//   1.1   | asaetow  |03-NOV-11| First Draft.
-
-
-#ifndef MSS_EFF_CONFIG_THERMAL_H_
-#define MSS_EFF_CONFIG_THERMAL_H_
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_eff_config_thermal_FP_t)
-(
- const fapi::Target &
- );
-
-
-extern "C" {
-//------------------------------------------------------------------------------
-// @brief mss_eff_config_thermal procedure. Sets up dimm power curve attributes
-//  and dimm and channel throttle attributes
-//
-// @param[in]  i_target_mba  Reference to centaur mba target
-//
-// @return ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_eff_config_thermal(const fapi::Target & i_target_mba);
-
-} //extern C
-
-#endif // MSS_EFF_CONFIG_THERMAL_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
deleted file mode 100644
index ced4133b8..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C
+++ /dev/null
@@ -1,2243 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_grouping.C,v 1.34 2014/09/29 16:25:38 gpaulraj Exp $
-// Mike Jones - modified version from 1.28 to 1.00 because it is a sandbox version
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_grouping.C
-// *! DESCRIPTION : see additional comments below
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-//Owner :- Girisankar paulraj
-//Back-up owner :- Mark bellows
-//
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.34   |gpaulraj  | 09-23-14| fixed last check in issue
-//  1.33   |gpaulraj  | 09-23-14| fixed 2 MCS/group issue on starting with odd MCS grouping
-//  1.32   |gpaulraj  | 06-26-14| support MEM_MIRROR_PLACEMENT_POLICY_FLIPPED_DRAWER for Brazos
-//  1.31   | thi      | 05-23-14| Support MEM_MIRROR_PLACEMENT_POLICY_DRAWER for Brazos
-//  1.30   | jdsloat  | 04-10-14| Mike Jones's rewrite.
-//  1.29   | gpaulraj | 04-20-14| Updated Dimm call out/FW defect/Mike's Feedback
-//  1.28   | gpaulraj | 11-21-13| modified 8MCS/group id as per spec
-//  1.27   | gpaulraj | 08-13-13| Fixed alternate BAR settings for Mirror
-//  1.26   | gpaulraj | 08-12-13| added mirror policy and HTM/OCC Bar setup
-//  1.25   | gpaulraj | 05-23-13| Fixed FW review feedback
-//  1.24   | bellows  | 04-09-13| Updates that really allow checkboard and all group sizes.  Before, group size of 1 was all that was possible
-//  1.23   | bellows  | 03-26-13| Allow for checkboard mode with more than one mcs per group
-//  1.22   | bellows  | 03-21-13| Error Logging support
-//  1.21   | bellows  | 03-11-13| Fixed syntax error with respect to the fapi macro under cronus
-//  1.20   | bellows  | 03-08-13| Proper way to deconfigure mulitple/variable MCS
-//  1.19   | bellows  | 02-27-13| Added back in mirror overlap check.  Added in error rc for grouping
-//  1.18   | asaetow  | 02-01-13| Removed FAPI_ERR("Mirror Base address overlaps with memory base address. "); temporarily.
-//         |          |         | NOTE: Need Giri to check mirroring enable before checking for overlaps.
-//  1.17   | gpaulraj | 01-31-13| Error place holders added
-//  1.16   | gpaulraj | 12-14-12| Modified "nnable to group dimm size" as Error message
-//  1.15   | bellows  | 12-11-12| Picked up latest updates from Girisankar
-//  1.14   | bellows  | 12-11-12| added ; to DBG line
-//  1.13   | bellows  | 12-07-12| fix for interleaving attr and array bounds
-//  1.11   | bellows  | 11-27-12| review updates
-//  1.10   | bellows  | 09-27-12| Additional Review Updates
-//  1.9    | bellows  | 09-25-12| updates from review, code from Girisankar
-//  1.8    | bellows  | 09-06-12| updates suggested by Van
-//  1.7    | bellows  | 08-31-12| updates from Girisankar: C++ Object. Also use 32 bit Attribute
-//  1.6    | bellows  | 08-29-12| expanded group id temporaily to 32 bits, fixed compiler warnings
-//         |          |         | Read old 8bit attr, and move to 32
-//         |          |         | Removed read of attr that has not been written
-//  1.2    | bellows  | 07-16-12| bellows | added in Id tag
-//  1.1    | gpaulraj | 03-19-12| First drop for centaur
-
-//-----------------------------------------------------------------------------
-//  Includes
-//-----------------------------------------------------------------------------
-#include <fapi.H>
-#include <mss_eff_grouping.H>
-#include <cen_scom_addresses.H>
-#include <mss_error_support.H>
-
-extern "C"
-{
-
-// Used for decoding ATTR_MSS_INTERLEAVE_ENABLE (iv_groupsAllowed)
-const uint8_t MCS_GROUP_8 = 0x8;
-const uint8_t MCS_GROUP_4 = 0x4;
-const uint8_t MCS_GROUP_2 = 0x2;
-const uint8_t MCS_GROUP_1 = 0x1;
-
-// MCS positions
-const uint8_t MCSID_0 = 0x0;
-const uint8_t MCSID_1 = 0x1;
-const uint8_t MCSID_2 = 0x2;
-const uint8_t MCSID_3 = 0x3;
-const uint8_t MCSID_4 = 0x4;
-const uint8_t MCSID_5 = 0x5;
-const uint8_t MCSID_6 = 0x6;
-const uint8_t MCSID_7 = 0x7;
-
-// System structure
-const uint8_t NUM_MBA_PORTS = 2;
-const uint8_t NUM_MBA_DIMMS = 2; // DIMMs per port
-const uint8_t NUM_MBA_PER_MCS = 2;
-const uint8_t NUM_MCS_PER_PROC = 8;
-
-// Constants used for EffGroupingData
-const uint8_t DATA_GROUPS = 16;   // 8 regular groups, 8 mirrored groups
-const uint8_t MIRR_OFFSET = 8;  // Start of mirrored offset in DATA_GROUPS
-const uint8_t DATA_ELEMENTS = 16; // 16 items of data for each group
-
-// Indexes used for EffGroupingData::iv_data DATA ELEMENTS
-const uint8_t MCS_SIZE = 0;           // Memory Size of each MCS in group (GB)
-const uint8_t MCS_IN_GROUP = 1;       // Number of MCSs in group
-const uint8_t GROUP_SIZE = 2;         // Memory Size of entire group (GB)
-const uint8_t BASE_ADDR = 3;          // Base Address
-#define MEMBER_IDX(X) ((X) + 4)       // List of MCSs in group
-const uint8_t ALT_VALID = 12;         // Alt Memory Valid
-const uint8_t ALT_SIZE = 13;          // Alt Memory Size
-const uint8_t ALT_BASE_ADDR = 14;     // Alt Base Address
-const uint8_t LARGEST_MBA_SIZE = 15;  // Largest MBA size
-
-/**
- * @struct EffGroupingData
- *
- * Contains Effective Grouping Data for a processor chip
- */
-struct EffGroupingData
-{
-    /**
-     * @brief Default constructor. Initializes instance variables to zero
-     */
-    EffGroupingData();
-
-    // The ATTR_MSS_MCS_GROUP_32 attribute
-    uint32_t iv_data[DATA_GROUPS][DATA_ELEMENTS];
-
-    // The MCSs that have been grouped
-    bool iv_mcsGrouped[NUM_MCS_PER_PROC];
-
-    // The number of groups
-    uint8_t iv_numGroups;
-
-    // The total non-mirrored memory size in GB
-    uint32_t iv_totalSizeNonMirr;
-};
-
-/**
- * @struct EffGroupingMemInfo
- *
- * Contains Memory Information for a processor chip
- */
-struct EffGroupingMemInfo
-{
-    /**
-     * @brief Default constructor. Initializes instance variables to zero
-     */
-    EffGroupingMemInfo();
-
-    /**
-     * @brief Gets the memory information
-     *
-     * @param[in]  i_assocCentaurs Reference to vector of Centaur Chips
-     *                             associated with the Proc Chip
-     * @return fapi::ReturnCode
-     */
-    fapi::ReturnCode getMemInfo(
-        const std::vector<fapi::Target> & i_assocCentaurs);
-
-    // MCS memory sizes
-    uint32_t iv_mcsSize[NUM_MCS_PER_PROC];
-
-    // MBA memory sizes
-    uint32_t iv_mbaSize[NUM_MCS_PER_PROC][NUM_MBA_PER_MCS];
-
-    // Largest MBA memory sizes
-    uint32_t iv_largestMbaSize[NUM_MCS_PER_PROC];
-
-    // Membuf chip associated with each MCS (for deconfiguring if cannot group)
-    fapi::Target iv_membufs[NUM_MCS_PER_PROC];
-};
-
-/**
- * @struct EffGroupingSysAttrs
- *
- * Contains system attributes
- */
-struct EffGroupingSysAttrs
-{
-    /**
-     * @brief Default Constructor. Initializes attributes
-     */
-    EffGroupingSysAttrs() : iv_mcsInterleaveMode(0),
-                            iv_selectiveMode(0),
-                            iv_enhancedNoMirrorMode(0) {}
-    /**
-     * @brief Gets attributes
-     */
-    fapi::ReturnCode getAttrs();
-
-    // Public data
-    uint8_t iv_mcsInterleaveMode;    // ATTR_ALL_MCS_IN_INTERLEAVING_GROUP
-    uint8_t iv_selectiveMode;        // ATTR_MEM_MIRROR_PLACEMENT_POLICY
-    uint8_t iv_enhancedNoMirrorMode; // ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING
-};
-
-/**
- * @struct EffGroupingProcAttrs
- *
- * Contains attributes for a Processor Chip
- */
-struct EffGroupingProcAttrs
-{
-    /**
-     * @brief Default Constructor. Initializes attributes
-     */
-    EffGroupingProcAttrs() : iv_groupsAllowed(0),
-                             iv_memBaseAddr(0),
-                             iv_mirrorBaseAddr(0),
-                             iv_htmBarSize(0),
-                             iv_occSandboxSize(0) {}
-    /**
-     * @brief Gets attributes
-     *
-     * @param[in] i_proc Reference to Processor Chip Target
-     */
-    fapi::ReturnCode getAttrs(const fapi::Target & i_proc);
-
-    // Public data
-    uint8_t  iv_groupsAllowed;  // ATTR_MSS_INTERLEAVE_ENABLE
-    uint64_t iv_memBaseAddr;    // ATTR_PROC_MEM_BASE >> 30
-    uint64_t iv_mirrorBaseAddr; // ATTR_PROC_MIRROR_BASE >> 30
-    uint64_t iv_htmBarSize;     // ATTR_PROC_HTM_BAR_SIZE
-    uint64_t iv_occSandboxSize; // ATTR_PROC_OCC_SANDBOX_SIZE
-};
-
-/**
- * @struct EffGroupingMembufAttrs
- *
- * Contains attributes for a Membuf Chip
- */
-struct EffGroupingMembufAttrs
-{
-    /**
-     * @brief Default Constructor. Initializes attributes
-     *
-     * @param[in] i_procTarget Reference to Processor Chip Target
-     */
-    EffGroupingMembufAttrs() : iv_pos(0), iv_mcsPos(0) {}
-
-    /**
-     * @brief Gets attributes
-     *
-     * @param[in] i_membuf Reference to membuf Chip Target
-     */
-    fapi::ReturnCode getAttrs(const fapi::Target & i_membuf);
-
-    uint32_t iv_pos;    // ATTR_POS (Position)
-    uint32_t iv_mcsPos; // Associated MCS unit position derived from iv_pos)
-};
-
-/**
- * @struct EffGroupingMbaAttrs
- *
- * Contains attributes for an MBA Chiplet
- */
-struct EffGroupingMbaAttrs
-{
-    /**
-     * @brief Default Constructor. Initializes attributes
-     *
-     * @param[in] i_procTarget Reference to Processor Chip Target
-     */
-    EffGroupingMbaAttrs();
-
-    /**
-     * @brief Gets attributes
-     *
-     * @param[in] i_mba Reference to MBA chiplet Target
-     */
-    fapi::ReturnCode getAttrs(const fapi::Target & i_mba);
-
-    // Unit Position (ATTR_CHIP_UNIT_POS)
-    uint8_t iv_unitPos;
-
-    // Dimm Size (ATTR_EFF_DIMM_SIZE)
-    uint8_t iv_effDimmSize[NUM_MBA_PORTS][NUM_MBA_DIMMS];
-};
-
-//------------------------------------------------------------------------------
-EffGroupingData::EffGroupingData() : iv_numGroups(0), iv_totalSizeNonMirr(0)
-{
-    // Initialize all instance variables to zero
-    for (uint32_t i = 0; i < DATA_GROUPS; i++)
-    {
-        for (uint32_t j = 0; j < DATA_ELEMENTS; j++)
-        {
-            iv_data[i][j] = 0;
-        }
-    }
-
-    for (uint32_t i = 0; i < NUM_MCS_PER_PROC; i++)
-    {
-        iv_mcsGrouped[i] = false;
-    }
-}
-
-//------------------------------------------------------------------------------
-EffGroupingMemInfo::EffGroupingMemInfo()
-{
-    // Initialize all instance variables to zero
-    for (uint32_t i = 0; i < NUM_MCS_PER_PROC; i++)
-    {
-        iv_mcsSize[i] = 0;
-        for (uint32_t j = 0; j < NUM_MBA_PER_MCS; j++)
-        {
-            iv_mbaSize[i][j] = 0;
-        }
-        iv_largestMbaSize[i] = 0;
-    }
-}
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode EffGroupingMemInfo::getMemInfo (
-    const std::vector<fapi::Target> & i_assocCentaurs)
-{
-    fapi::ReturnCode rc;
-
-    for (uint32_t i = 0; i < i_assocCentaurs.size(); i++)
-    {
-        const fapi::Target & cenTarget = i_assocCentaurs[i];
-
-        // Get the Centaur attributes
-        EffGroupingMembufAttrs centaurAttrs;
-        rc = centaurAttrs.getAttrs(cenTarget);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error getting Centaur chip attributes");
-            break;
-        }
-
-        // Store the Centaur Target in iv_membufs (indexed by MCS position)
-        iv_membufs[centaurAttrs.iv_mcsPos] = cenTarget;
-
-        // Get the functional MBA children of the Centaur
-        std::vector <fapi::Target> l_mba_chiplets;
-        rc = fapiGetChildChiplets(cenTarget,
-                                  fapi::TARGET_TYPE_MBA_CHIPLET,
-                                  l_mba_chiplets);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error getting child MBA chiplets");
-            break;
-        }
-
-        for (uint32_t j = 0; j < l_mba_chiplets.size(); j++)
-        {
-            fapi::Target & mbaTarget = l_mba_chiplets[j];
-
-            // Get the MBA Chiplet attributes
-            EffGroupingMbaAttrs mbaAttrs;
-            rc = mbaAttrs.getAttrs(mbaTarget);
-            if (rc)
-            {
-                FAPI_ERR("mss_eff_grouping: Error getting MBA attributes");
-                break;
-            }
-
-            // Add each Effective DIMM size to iv_mcsSize and iv_mbaSize
-            for (uint8_t port = 0; port < NUM_MBA_PORTS; port++)
-            {
-                for (uint8_t dimm = 0; dimm < NUM_MBA_DIMMS; dimm++)
-                {
-                    iv_mcsSize[centaurAttrs.iv_mcsPos]
-                        += mbaAttrs.iv_effDimmSize[port][dimm];
-                    iv_mbaSize[centaurAttrs.iv_mcsPos][mbaAttrs.iv_unitPos]
-                        += mbaAttrs.iv_effDimmSize[port][dimm];
-                }
-            }
-
-            FAPI_INF("mss_eff_grouping: Cen Pos %u, MBA UPos %u, MBA total size %u GB",
-                     centaurAttrs.iv_pos, mbaAttrs.iv_unitPos,
-                     iv_mbaSize[centaurAttrs.iv_mcsPos][mbaAttrs.iv_unitPos]);
-        }
-        if (rc)
-        {
-            break;
-        }
-    }
-
-    if (!rc)
-    {
-        // Calculate max MBA size
-        for (uint8_t i = 0; i < NUM_MCS_PER_PROC; i++)
-        {
-            iv_largestMbaSize[i] = iv_mbaSize[i][0];
-
-            for (uint32_t j = 1; j < NUM_MBA_PER_MCS; j++)
-            {
-                if (iv_mbaSize[i][j] > iv_largestMbaSize[i])
-                {
-                    iv_largestMbaSize[i] = iv_mbaSize[i][j];
-                }
-            }
-        }
-
-        // Trace sizes
-        for (uint8_t i = 0; i < NUM_MCS_PER_PROC; i++)
-        {
-            FAPI_INF("mss_eff_grouping: MCS Pos %u, MCS Size %u GB, "
-                     "MBA0 Size %u GB, MBA1 Size %u GB",
-                     i, iv_mcsSize[i], iv_mbaSize[i][0], iv_mbaSize[i][1]);
-        }
-    }
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode EffGroupingSysAttrs::getAttrs()
-{
-    fapi::ReturnCode rc;
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,
-                           iv_mcsInterleaveMode);
-        if (rc)
-        {
-            FAPI_ERR("Error querying sys chip ATTR_ALL_MCS_IN_INTERLEAVING_GROUP");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_MEM_MIRROR_PLACEMENT_POLICY, NULL,
-                           iv_selectiveMode);
-        if (rc)
-        {
-            FAPI_ERR("Error querying sys ATTR_MEM_MIRROR_PLACEMENT_POLICY");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING, NULL,
-                           iv_enhancedNoMirrorMode);
-        if (rc)
-        {
-            FAPI_ERR("Error querying sys ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING");
-            break;
-        }
-
-        FAPI_INF("mss_eff_grouping::EffGroupingSysAttrs: "
-                 "ALL_MCS_IN_INTERLEAVING_GROUP 0x%02x, "
-                 "MEM_MIRROR_PLACEMENT_POLICY 0x%02x, "
-                 "MRW_ENHANCED_GROUPING_NO_MIRRORING 0x%02x",
-                 iv_mcsInterleaveMode, iv_selectiveMode,
-                 iv_enhancedNoMirrorMode);
-    } while(0);
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode EffGroupingProcAttrs::getAttrs(const fapi::Target & i_proc)
-{
-    fapi::ReturnCode rc;
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_MSS_INTERLEAVE_ENABLE, &i_proc,
-                           iv_groupsAllowed);
-        if (rc)
-        {
-            FAPI_ERR("Error querying proc chip ATTR_MSS_INTERLEAVE_ENABLE for %s",
-                     i_proc.toEcmdString());
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE, &i_proc, iv_memBaseAddr);
-        if (rc)
-        {
-            FAPI_ERR("Error querying proc chip ATTR_PROC_MEM_BASE for %s",
-                     i_proc.toEcmdString());
-            break;
-        }
-        iv_memBaseAddr >>= 30;
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE, &i_proc, iv_mirrorBaseAddr);
-        if (rc)
-        {
-            FAPI_ERR("Error querying proc chip ATTR_PROC_MIRROR_BASE for %s",
-                     i_proc.toEcmdString());
-            break;
-        }
-        iv_mirrorBaseAddr >>= 30;
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_HTM_BAR_SIZE, &i_proc, iv_htmBarSize);
-        if (rc)
-        {
-            FAPI_ERR("Error querying proc chip ATTR_PROC_HTM_BAR_SIZE for %s",
-                     i_proc.toEcmdString());
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_OCC_SANDBOX_SIZE, &i_proc,
-                           iv_occSandboxSize);
-        if (rc)
-        {
-            FAPI_ERR("Error querying proc chip ATTR_PROC_OCC_SANDBOX_SIZE for %s",
-                     i_proc.toEcmdString());
-            break;
-        }
-
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: "
-                 "MSS_INTERLEAVE_ENABLE 0x%02x", iv_groupsAllowed);
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: 1 MCSs per group %s",
-                 (iv_groupsAllowed & MCS_GROUP_1) ?
-                     "supported" : "not supported");
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: 2 MCSs per group %s",
-                 (iv_groupsAllowed & MCS_GROUP_2) ?
-                     "supported" : "not supported");
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: 4 MCSs per group %s",
-                 (iv_groupsAllowed & MCS_GROUP_4) ?
-                     "supported" : "not supported");
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: 8 MCSs per group %s",
-                 (iv_groupsAllowed & MCS_GROUP_8) ?
-                     "supported" : "not supported");
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: "
-                 "ATTR_PROC_MEM_BASE >> 30 0x%016llx, "
-                 "ATTR_PROC_MIRROR_BASE >> 30 0x%016llx",
-                 iv_memBaseAddr, iv_mirrorBaseAddr);
-        FAPI_INF("mss_eff_grouping::EffGroupingProcAttrs: "
-                 "ATTR_PROC_HTM_BAR_SIZE 0x%016llx, "
-                 "ATTR_PROC_OCC_SANDBOX_SIZE 0x%016llx",
-                 iv_htmBarSize, iv_occSandboxSize);
-    } while(0);
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-fapi::ReturnCode EffGroupingMembufAttrs::getAttrs(const fapi::Target & i_membuf)
-{
-    fapi::ReturnCode rc;
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_POS, &i_membuf, iv_pos);
-        if (rc)
-        {
-            FAPI_ERR("Error querying membuf chip ATTR_POS for %s",
-                     i_membuf.toEcmdString());
-            break;
-        }
-
-        // Assumption is that
-        // Chip pos 0: MCS unit-pos 0: Membuf pos 0
-        // Chip pos 0: MCS unit-pos 1: Membuf pos 1
-        // Chip pos 0: MCS unit-pos 2: Membuf pos 2
-        // Chip pos 0: MCS unit-pos 3: Membuf pos 3
-        // Chip pos 0: MCS unit-pos 4: Membuf pos 4
-        // Chip pos 0: MCS unit-pos 5: Membuf pos 5
-        // Chip pos 0: MCS unit-pos 6: Membuf pos 6
-        // Chip pos 0: MCS unit-pos 7: Membuf pos 7
-        // Chip pos 1: MCS unit-pos 0: Membuf pos 8
-        // Chip pos 1: MCS unit-pos 1: Membuf pos 9
-        // Chip pos 1: MCS unit-pos 2: Membuf pos 10
-        // Chip pos 1: MCS unit-pos 3: Membuf pos 11
-        // Chip pos 1: MCS unit-pos 4: Membuf pos 12
-        // Chip pos 1: MCS unit-pos 5: Membuf pos 13
-        // Chip pos 1: MCS unit-pos 6: Membuf pos 14
-        // Chip pos 1: MCS unit-pos 7: Membuf pos 15
-        // etc.
-        iv_mcsPos = iv_pos % 8;
-
-        FAPI_INF("mss_eff_grouping::EffGroupingMembufAttrs: "
-                 "%s: POS %u, mcsPos %u",
-                 i_membuf.toEcmdString(), iv_pos, iv_mcsPos);
-    } while(0);
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-EffGroupingMbaAttrs::EffGroupingMbaAttrs() : iv_unitPos(0)
-{
-    for (uint8_t i = 0; i < NUM_MBA_PORTS; i++)
-    {
-        for (uint8_t j = 0; j < NUM_MBA_DIMMS; j++)
-        {
-            iv_effDimmSize[i][j] = 0;
-        }
-    }
-}
-//------------------------------------------------------------------------------
-fapi::ReturnCode EffGroupingMbaAttrs::getAttrs(const fapi::Target & i_mba)
-{
-    fapi::ReturnCode rc;
-
-    do
-    {
-        rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_mba, iv_unitPos);
-        if (rc)
-        {
-            FAPI_ERR("Error querying MBA ATTR_CHIP_UNIT_POS for %s",
-                     i_mba.toEcmdString());
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &i_mba, iv_effDimmSize);
-        if (rc)
-        {
-            FAPI_ERR("Error querying MBA ATTR_EFF_DIMM_SIZE for %s",
-                     i_mba.toEcmdString());
-            break;
-        }
-
-        FAPI_INF("mss_eff_grouping::EffGroupingMbaAttrs: %s: CHIP_UNIT_POS %u",
-                 i_mba.toEcmdString(), iv_unitPos);
-
-        for (uint8_t i = 0; i < NUM_MBA_PORTS; i++)
-        {
-            for (uint8_t j = 0; j < NUM_MBA_DIMMS; j++)
-            {
-                FAPI_INF("mss_eff_grouping::EffGroupingMbaAttrs: MBA %u: "
-                         "EFF_DIMM_SIZE[%u][%u] %u GB",
-                         iv_unitPos, i, j, iv_effDimmSize[i][j]);
-            }
-        }
-    } while(0);
-
-    return rc;
-}
-
-/**
- * @brief checks that attributes are valid
- *
- * @param[in] i_sysAttrs  Reference to system attributes
- * @param[in] i_procAttrs Reference to proc chip attributes
- *
- * @return fapi::ReturnCode
- */
-fapi::ReturnCode grouping_checkValidAttributes(
-    const EffGroupingSysAttrs & i_sysAttrs,
-    const EffGroupingProcAttrs & i_procAttrs)
-{
-    fapi::ReturnCode rc;
-    do
-    {
-        if (i_sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            if (i_sysAttrs.iv_selectiveMode ==
-                fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
-            {
-                FAPI_ERR("mss_eff_grouping: Mirroring disabled, selective mode invalid");
-                const uint8_t & MIRROR_PLACEMENT_POLICY =
-                    i_sysAttrs.iv_selectiveMode;
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MIRROR_DISABLED);
-                break;
-            }
-
-            if (i_sysAttrs.iv_selectiveMode ==
-                fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED)
-            {
-                FAPI_ERR("mss_eff_grouping: Mirroring disabled, flipped mode invalid");
-                const uint8_t & MIRROR_PLACEMENT_POLICY =
-                    i_sysAttrs.iv_selectiveMode;
-                FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_CONFIG_MIRROR_DISABLED);
-                break;
-            }
-        }
-
-        if (i_sysAttrs.iv_mcsInterleaveMode)
-        {
-            // Fabric interleaving mode, must be 2, 4 or 8 MCSs per group
-            if ( ((!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_2)) &&
-                  (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_4)) &&
-                  (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_8))) ||
-                 (i_procAttrs.iv_groupsAllowed & MCS_GROUP_1) )
-            {
-                FAPI_ERR("mss_eff_grouping: Interleaving mode, but MCSs per group invalid (0x%02x)",
-                         i_procAttrs.iv_groupsAllowed);
-                const uint8_t ALL_MCS_IN_INTERLEAVING_GROUP =
-                    i_sysAttrs.iv_mcsInterleaveMode;
-                const uint8_t MSS_INTERLEAVE_ENABLE =
-                    i_procAttrs.iv_groupsAllowed;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_MSS_EFF_CONFIG_INTERLEAVE_MODE_INVALID_MCS_PER_GROUP);
-                break;
-            }
-        }
-        else
-        {
-            // Fabric checkerboard mode, all MCSs per group allowed, but more
-            // than 1 MCS per group will will have a performance impact
-            if ( (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_1)) &&
-                 (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_2)) &&
-                 (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_4)) &&
-                 (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_8)) )
-            {
-                FAPI_ERR("mss_eff_grouping: Checkerboard mode, but MCSs per group invalid (0x%02x)",
-                         i_procAttrs.iv_groupsAllowed);
-                const uint8_t ALL_MCS_IN_INTERLEAVING_GROUP =
-                    i_sysAttrs.iv_mcsInterleaveMode;
-                const uint8_t MSS_INTERLEAVE_ENABLE =
-                    i_procAttrs.iv_groupsAllowed;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_MSS_EFF_CONFIG_CHECKERBOARD_MODE_INVALID_MCS_PER_GROUP);
-                break;
-            }
-
-            if (!(i_procAttrs.iv_groupsAllowed & MCS_GROUP_1))
-            {
-                FAPI_INF("mss_eff_grouping: Fabric is in checkerboard mode "
-                         "with more than 1 MCS per group, performance would "
-                         "be better in interleaving mode");
-            }
-        }
-
-        if (i_sysAttrs.iv_selectiveMode ==
-            fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
-        {
-            if (i_procAttrs.iv_htmBarSize != 0 ||
-                i_procAttrs.iv_occSandboxSize != 0)
-            {
-                FAPI_ERR("mss_eff_grouping: Selective mode does not support "
-                         "HTM and OCC Sandbox BARs");
-                const uint64_t & HTM_BAR_SIZE = i_procAttrs.iv_htmBarSize;
-                const uint64_t & OCC_SANDBOX_BAR_SIZE =
-                    i_procAttrs.iv_occSandboxSize;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_MSS_EFF_GROUPING_SELCTIVE_MODE_HTM_OCC_BAR);
-                break;
-            }
-        }
-    } while (0);
-
-    return rc;
-}
-
-/**
- * @brief Attempts to group 8 MCSs per group
- *
- * If they can be grouped, fills in the following fields in o_groupData:
- * - iv_data[<group>][MCS_SIZE]
- * - iv_data[<group>][MCS_IN_GROUP]
- * - iv_data[<group>][GROUP_SIZE]
- * - iv_data[<group>][MEMBER_IDX(<members>)]
- * - iv_data[<group>][LARGEST_MBA_SIZE]
- * - iv_mcsGrouped[<group>]
- * - iv_numGroups
- *
- * @param[in]  i_memInfo   Reference to EffGroupingMemInfo structure
- * @param[out] o_groupData Reference to output data
- */
-void grouping_group8McsPerGroup(const EffGroupingMemInfo & i_memInfo,
-                                EffGroupingData & o_groupData)
-{
-    // There are 8 MCSs in a proc chip, they can be grouped together if they all
-    // have the same memory size. Assume that no MCSs have already been grouped
-    FAPI_INF("mss_eff_grouping: Attempting to group 8 MCSs per group");
-    uint8_t & g = o_groupData.iv_numGroups;
-
-    if ((NUM_MCS_PER_PROC == 8) && (i_memInfo.iv_mcsSize[0] != 0))
-    {
-        // MCS 0 has memory
-        bool grouped = true;
-        uint32_t maxMbaSize = i_memInfo.iv_largestMbaSize[0];
-
-        for (uint8_t pos = 1; pos < NUM_MCS_PER_PROC; pos++)
-        {
-            if (i_memInfo.iv_mcsSize[0] != i_memInfo.iv_mcsSize[pos])
-            {
-                // This MCS does not have the same size as MCS 0
-                grouped = false;
-                break;
-            }
-            else if (i_memInfo.iv_largestMbaSize[pos] > maxMbaSize)
-            {
-                maxMbaSize = i_memInfo.iv_largestMbaSize[pos];
-            }
-        }
-
-        if (grouped)
-        {
-            // All 8 MCSs are the same size and can be grouped
-            FAPI_INF("mss_eff_grouping: Grouped all 8 MCSs");
-            o_groupData.iv_data[g][MCS_SIZE] = i_memInfo.iv_mcsSize[0];
-            o_groupData.iv_data[g][MCS_IN_GROUP] = 8;
-            o_groupData.iv_data[g][GROUP_SIZE] = 8 * i_memInfo.iv_mcsSize[0];
-            o_groupData.iv_data[g][MEMBER_IDX(0)] = MCSID_0;
-            o_groupData.iv_data[g][MEMBER_IDX(1)] = MCSID_4;
-            o_groupData.iv_data[g][MEMBER_IDX(2)] = MCSID_2;
-            o_groupData.iv_data[g][MEMBER_IDX(3)] = MCSID_6;
-            o_groupData.iv_data[g][MEMBER_IDX(4)] = MCSID_1;
-            o_groupData.iv_data[g][MEMBER_IDX(5)] = MCSID_5;
-            o_groupData.iv_data[g][MEMBER_IDX(6)] = MCSID_3;
-            o_groupData.iv_data[g][MEMBER_IDX(7)] = MCSID_7;
-            o_groupData.iv_data[g][LARGEST_MBA_SIZE] = maxMbaSize;
-            g++;
-
-            // Record which MCSs were grouped
-            for (uint8_t i = 0; i < NUM_MCS_PER_PROC; i++)
-            {
-                o_groupData.iv_mcsGrouped[i] = true;
-            }
-        }
-    }
-}
-
-/**
- * @brief Attempts to group 4 MCSs per group
- *
- * If they can be grouped, fills in the following fields in o_groupData:
- * - iv_data[<group>][MCS_SIZE]
- * - iv_data[<group>][MCS_IN_GROUP]
- * - iv_data[<group>][GROUP_SIZE]
- * - iv_data[<group>][MEMBER_IDX(<members>)]
- * - iv_data[<group>][LARGEST_MBA_SIZE]
- * - iv_mcsGrouped[<group>]
- * - iv_numGroups
- *
- * @param[in]  i_memInfo   Reference to EffGroupingMemInfo structure
- * @param[out] o_groupData Reference to output data
- */
-void grouping_group4McsPerGroup(const EffGroupingMemInfo & i_memInfo,
-                                EffGroupingData & o_groupData)
-{
-    // The following is all the allowed ways of grouping 4 MCSs per group.
-    // Earlier array entries are higher priority.
-    // First try to group 2 sets of 4 (0/1, 2/3 or 4/5)
-    // If no success then try to group 1 set of 4
-    FAPI_INF("mss_eff_grouping: Attempting to group 4 MCSs per group");
-    uint8_t & g = o_groupData.iv_numGroups;
-    const uint8_t NUM_WAYS_4MCS_PER_GROUP = 6;
-    const uint8_t CFG_4MCS[NUM_WAYS_4MCS_PER_GROUP][4] =
-        { { MCSID_0, MCSID_1, MCSID_4, MCSID_5 },
-          { MCSID_2, MCSID_3, MCSID_6, MCSID_7 },
-          { MCSID_0, MCSID_1, MCSID_6, MCSID_7 },
-          { MCSID_2, MCSID_3, MCSID_4, MCSID_5 },
-          { MCSID_0, MCSID_1, MCSID_2, MCSID_3 },
-          { MCSID_4, MCSID_5, MCSID_6, MCSID_7 } };
-
-    // Array recording which groups of 4 can potentially be grouped
-    uint8_t config4_gp[NUM_WAYS_4MCS_PER_GROUP] = {0};
-
-    // Figure out which groups of 4 can potentially be grouped
-    for (uint8_t i = 0; i < NUM_WAYS_4MCS_PER_GROUP; i++)
-    {
-        if ((!o_groupData.iv_mcsGrouped[CFG_4MCS[i][0]]) &&
-            (i_memInfo.iv_mcsSize[CFG_4MCS[i][0]] != 0))
-        {
-            // First MCS of group is not already grouped and has memory
-            bool potential_group = true;
-            for (uint8_t j = 1; j < 4; j++)
-            {
-                if ( (o_groupData.iv_mcsGrouped[CFG_4MCS[i][j]]) ||
-                     (i_memInfo.iv_mcsSize[CFG_4MCS[i][0]] !=
-                         i_memInfo.iv_mcsSize[CFG_4MCS[i][j]]) )
-                {
-                    // This MCS is already grouped or does not have the same
-                    // size as MCS 0
-                    potential_group = false;
-                    break;
-                }
-            }
-            if (potential_group)
-            {
-                FAPI_INF("mss_eff_grouping: Potential group MCSs %u, %u, %u, %u",
-                         CFG_4MCS[i][0], CFG_4MCS[i][1],
-                         CFG_4MCS[i][2], CFG_4MCS[i][3]);
-                config4_gp[i] = 1;
-            }
-        }
-    }
-
-    // Figure out which groups of 4 to actually group
-    uint8_t gp1 = 0xff;
-    uint8_t gp2 = 0xff;
-
-    // Check if 2 groups of 4 are possible (0/1, 2/3 or 4/5)
-    for (uint8_t i = 0; i < NUM_WAYS_4MCS_PER_GROUP; i += 2)
-    {
-        if (config4_gp[i] && config4_gp[i + 1])
-        {
-            FAPI_INF("mss_eff_grouping: Grouped MCSs %u, %u, %u, %u",
-                     CFG_4MCS[i][0], CFG_4MCS[i][1],
-                     CFG_4MCS[i][2], CFG_4MCS[i][3]);
-            FAPI_INF("mss_eff_grouping: Grouped MCSs %u, %u, %u, %u",
-                     CFG_4MCS[i + 1][0], CFG_4MCS[i + 1][1],
-                     CFG_4MCS[i + 1][2], CFG_4MCS[1 + 1][3]);
-            gp1 = i;
-            gp2 = i + 1;
-            break;
-        }
-    }
-
-    if (gp1 == 0xff)
-    {
-        // 2 groups of 4 are not possible, look for 1 group of 4
-        for (uint8_t i = 0; i < NUM_WAYS_4MCS_PER_GROUP; i++)
-        {
-            if (config4_gp[i])
-            {
-                FAPI_INF("mss_eff_grouping: Grouped MCSs %u, %u, %u, %u",
-                         CFG_4MCS[i][0], CFG_4MCS[i][1],
-                         CFG_4MCS[i][2], CFG_4MCS[i][3]);
-                gp1 = i;
-                break;
-            }
-        }
-    }
-
-    if (gp1 != 0xff)
-    {
-        // Figure out the maximum MBA size for group 1
-        uint32_t maxMbaSize = i_memInfo.iv_largestMbaSize[CFG_4MCS[gp1][0]];
-        for (uint8_t i = 1; i < 4; i++)
-        {
-            if (i_memInfo.iv_largestMbaSize[CFG_4MCS[gp1][i]] > maxMbaSize)
-            {
-                maxMbaSize = i_memInfo.iv_largestMbaSize[CFG_4MCS[gp1][i]];
-            }
-        }
-
-        o_groupData.iv_data[g][MCS_SIZE] =
-            i_memInfo.iv_mcsSize[CFG_4MCS[gp1][0]];
-        o_groupData.iv_data[g][MCS_IN_GROUP] = 4;
-        o_groupData.iv_data[g][GROUP_SIZE] =
-            4 * i_memInfo.iv_mcsSize[CFG_4MCS[gp1][0]];
-        o_groupData.iv_data[g][MEMBER_IDX(0)] = CFG_4MCS[gp1][0];
-        o_groupData.iv_data[g][MEMBER_IDX(1)] = CFG_4MCS[gp1][2];
-        o_groupData.iv_data[g][MEMBER_IDX(2)] = CFG_4MCS[gp1][1];
-        o_groupData.iv_data[g][MEMBER_IDX(3)] = CFG_4MCS[gp1][3];
-        o_groupData.iv_data[g][LARGEST_MBA_SIZE] = maxMbaSize;
-        g++;
-
-        // Record which MCSs were grouped
-        for (uint8_t i = 0; i < 4; i++)
-        {
-            o_groupData.iv_mcsGrouped[CFG_4MCS[gp1][i]] = true;
-        }
-    }
-
-    if (gp2 != 0xff)
-    {
-        // Figure out the maximum MBA size for group 2
-        uint32_t maxMbaSize =
-            i_memInfo.iv_largestMbaSize[CFG_4MCS[gp2][0]];
-        for (uint8_t i = 1; i < 4; i++)
-        {
-            if (i_memInfo.iv_largestMbaSize[CFG_4MCS[gp2][i]] > maxMbaSize)
-            {
-                maxMbaSize = i_memInfo.iv_largestMbaSize[CFG_4MCS[gp2][i]];
-            }
-        }
-
-        o_groupData.iv_data[g][MCS_SIZE] =
-            i_memInfo.iv_mcsSize[CFG_4MCS[gp2][0]];
-        o_groupData.iv_data[g][MCS_IN_GROUP] = 4;
-        o_groupData.iv_data[g][GROUP_SIZE] =
-            4 * i_memInfo.iv_mcsSize[CFG_4MCS[gp2][0]];
-        o_groupData.iv_data[g][MEMBER_IDX(0)] = CFG_4MCS[gp2][0];
-        o_groupData.iv_data[g][MEMBER_IDX(1)] = CFG_4MCS[gp2][2];
-        o_groupData.iv_data[g][MEMBER_IDX(2)] = CFG_4MCS[gp2][1];
-        o_groupData.iv_data[g][MEMBER_IDX(3)] = CFG_4MCS[gp2][3];
-        o_groupData.iv_data[g][LARGEST_MBA_SIZE] = maxMbaSize;
-        g++;
-
-        // Record which MCSs were grouped
-        for (uint8_t i = 0; i < 4; i++)
-        {
-            o_groupData.iv_mcsGrouped[CFG_4MCS[gp2][i]] = true;
-        }
-    }
-}
-
-/**
- * @brief Attempts to group 2 MCSs per group
- *
- * If they can be grouped, fills in the following fields in o_groupData:
- * - iv_data[<group>][MCS_SIZE]
- * - iv_data[<group>][MCS_IN_GROUP]
- * - iv_data[<group>][GROUP_SIZE]
- * - iv_data[<group>][MEMBER_IDX(<members>)]
- * - iv_data[<group>][LARGEST_MBA_SIZE]
- * - iv_mcsGrouped[<group>]
- * - iv_numGroups
- *
- * @param[in]  i_memInfo   Reference to EffGroupingMemInfo structure
- * @param[out] o_groupData Reference to output data
- */
-void grouping_group2McsPerGroup(const EffGroupingMemInfo & i_memInfo,
-                                EffGroupingData & o_groupData)
-{
-    // 2 adjacent MCSs are grouped if they have the same size
-    // 0/1, 2/3, 4/5, 6/7
-    FAPI_INF("mss_eff_grouping: Attempting to group 2 MCSs per group");
-    uint8_t & g = o_groupData.iv_numGroups;
-
-    for (uint8_t pos = 0; pos < NUM_MCS_PER_PROC - 1; pos = pos+2)
-    {
-        if ((!o_groupData.iv_mcsGrouped[pos]) &&
-            (!o_groupData.iv_mcsGrouped[pos + 1]) &&
-            (i_memInfo.iv_mcsSize[pos] != 0) &&
-            (i_memInfo.iv_mcsSize[pos] == i_memInfo.iv_mcsSize[pos + 1]))
-        {
-            // These 2 MCSs are not already grouped and have the same amount of
-            // memory
-            FAPI_INF("mss_eff_grouping: Grouped MCSs %u and %u", pos, pos + 1);
-            o_groupData.iv_data[g][MCS_SIZE] = i_memInfo.iv_mcsSize[pos];
-            o_groupData.iv_data[g][MCS_IN_GROUP] = 2;
-            o_groupData.iv_data[g][GROUP_SIZE] = 2 * i_memInfo.iv_mcsSize[pos];
-            o_groupData.iv_data[g][MEMBER_IDX(0)] = pos;
-            o_groupData.iv_data[g][MEMBER_IDX(1)] = pos + 1;
-            if (i_memInfo.iv_largestMbaSize[pos] >
-                i_memInfo.iv_largestMbaSize[pos + 1])
-            {
-                o_groupData.iv_data[g][LARGEST_MBA_SIZE] =
-                    i_memInfo.iv_largestMbaSize[pos];
-            }
-            else
-            {
-                o_groupData.iv_data[g][LARGEST_MBA_SIZE] =
-                    i_memInfo.iv_largestMbaSize[pos + 1];
-            }
-            g++;
-
-            // Record which MCSs were grouped
-            o_groupData.iv_mcsGrouped[pos] = true;
-            o_groupData.iv_mcsGrouped[pos + 1] = true;
-           
-        }
-    }
-}
-
-/**
- * @brief Attempts to group 1 MCS per group
- *
- * If they can be grouped, fills in the following fields in o_groupData:
- * - iv_data[<group>][MCS_SIZE]
- * - iv_data[<group>][MCS_IN_GROUP]
- * - iv_data[<group>][GROUP_SIZE]
- * - iv_data[<group>][MEMBER_IDX(<members>)]
- * - iv_data[<group>][LARGEST_MBA_SIZE]
- * - iv_mcsGrouped[<group>]
- * - iv_numGroups
- *
- * @param[in]  i_memInfo   Reference to EffGroupingMemInfo structure
- * @param[out] o_groupData Reference to output data
- */
-void grouping_group1McsPerGroup(const EffGroupingMemInfo & i_memInfo,
-                                EffGroupingData & o_groupData)
-{
-    // Any MCS with a non-zero size can be 'grouped'
-    FAPI_INF("mss_eff_grouping: Attempting to group 1 MCSs per group");
-    uint8_t & g = o_groupData.iv_numGroups;
-    for (uint8_t pos = 0; pos < NUM_MCS_PER_PROC; pos++)
-    {
-        if ((!o_groupData.iv_mcsGrouped[pos]) &&
-            (i_memInfo.iv_mcsSize[pos] != 0))
-        {
-            // This MCS is not already grouped and has memory
-            FAPI_INF("mss_eff_grouping: MCS %u grouped", pos);
-            o_groupData.iv_data[g][MCS_SIZE] = i_memInfo.iv_mcsSize[pos];
-            o_groupData.iv_data[g][MCS_IN_GROUP] = 1;
-            o_groupData.iv_data[g][GROUP_SIZE] = i_memInfo.iv_mcsSize[pos];
-            o_groupData.iv_data[g][MEMBER_IDX(0)] = pos;
-            o_groupData.iv_data[g][LARGEST_MBA_SIZE] =
-                i_memInfo.iv_largestMbaSize[pos];
-            g++;
-
-            // Record which MCS was grouped
-            o_groupData.iv_mcsGrouped[pos] = true;
-        }
-    }
-}
-
-/**
- * @brief Finds ungrouped MCSs
- *
- * If any are found then their associated Membuf chip is deconfigured
- *
- * @param[in] i_memInfo   Reference to Memory Info
- * @param[in] i_groupData Reference to Group data
- *
- * @return fapi::ReturnCode
- */
-fapi::ReturnCode grouping_findUngroupedMCSs(
-    const EffGroupingMemInfo & i_memInfo,
-    const EffGroupingData & i_groupData)
-{
-    fapi::ReturnCode rc;
-
-    bool ungrouped = false;
-    for (uint8_t i = 0; i < NUM_MCS_PER_PROC; i++)
-    {
-        if ((i_memInfo.iv_mcsSize[i] != 0) &&
-            (i_groupData.iv_mcsGrouped[i] == false))
-        {
-            FAPI_ERR("mss_eff_grouping: Unable to group MCS %u", i);
-            ungrouped = true;
-            const fapi::Target & MEMBUF = i_memInfo.iv_membufs[i];
-            FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_GROUPING_UNABLE_TO_GROUP_MCS);
-            fapiLogError(rc);
-            rc = fapi::FAPI_RC_SUCCESS;
-        }
-    }
-
-    if (ungrouped)
-    {
-        // One or more MCSs could not be grouped and errors were logged to
-        // callout the memory plug procedure and deconfigure the membuf.
-        // Return an error
-        FAPI_SET_HWP_ERROR(rc, RC_MSS_EFF_GROUPING_UNABLE_TO_GROUP);
-    }
-
-    return rc;
-}
-
-/**
- * @brief Calculates the number of 1s in a memory size
- *
- * @param[i] i_size Memory Size
- *
- * @return Number of 1s
- */
-uint8_t grouping_num1sInSize(uint32_t i_size)
-{
-    uint8_t numOnes = 0;
-    uint32_t l_size = i_size;
-
-    while (l_size != 0)
-    {
-        if (l_size & 1)
-        {
-            numOnes++;
-        }
-        l_size >>= 1;
-    }
-
-    FAPI_DBG("mss_eff_grouping: Num 1s in 0x%08x is %u", i_size, numOnes);
-    return numOnes;
-}
-
-/**
- * @brief Calculate Alt Memory
- *
- * @param[io] io_groupData Group Data
- */
-void grouping_calcAltMemory(EffGroupingData & io_groupData)
-{
-    FAPI_INF("mss_eff_grouping: Calculating Alt Memory");
-    for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
-    {
-        // Find the number of 1s in the group size
-        uint8_t numOnes = grouping_num1sInSize(
-            io_groupData.iv_data[pos][GROUP_SIZE]);
-
-        if (numOnes > 1)
-        {
-            FAPI_INF("mss_eff_grouping: Group %u needs alt bars definition, group size %u GB",
-                     pos, io_groupData.iv_data[pos][GROUP_SIZE]);
-
-            // New group size is the largest MBA size of the group
-            // multiplied by the number of MBAs in the group
-            io_groupData.iv_data[pos][GROUP_SIZE] =
-                io_groupData.iv_data[pos][LARGEST_MBA_SIZE] *
-                    NUM_MBA_PER_MCS *
-                        io_groupData.iv_data[pos][MCS_IN_GROUP];
-            FAPI_INF("mss_eff_grouping: New Group Size is %u GB",
-                     io_groupData.iv_data[pos][GROUP_SIZE]);
-
-            // Alt size is the number of MCSs in the group multiplied by
-            // (the MCS size minus the largest MBA size)
-            io_groupData.iv_data[pos][ALT_SIZE] =
-                io_groupData.iv_data[pos][MCS_IN_GROUP] *
-                    (io_groupData.iv_data[pos][MCS_SIZE] -
-                     io_groupData.iv_data[pos][LARGEST_MBA_SIZE]);
-            FAPI_INF("mss_eff_grouping: Alt Size is %u GB",
-                     io_groupData.iv_data[pos][ALT_SIZE]);
-
-            io_groupData.iv_data[pos][ALT_VALID] = 1;
-        }
-    }
-}
-
-/**
- * @brief Sorts groups from high to low memory size
- *
- * @param[io] io_groupData Group Data
- */
-void grouping_sortGroups(EffGroupingData & io_groupData)
-{
-    // Done with a simple bubble sort
-    FAPI_INF("mss_eff_grouping: Sorting Groups");
-    if (io_groupData.iv_numGroups)
-    {
-        uint32_t temp[DATA_ELEMENTS];
-        bool swapped = true;
-        while (swapped == true)
-        {
-            // Make a pass over the groups swapping adjacent sizes as needed
-            swapped = false;
-            for (uint8_t pos = 0; pos < io_groupData.iv_numGroups - 1; pos++)
-            {
-                if (io_groupData.iv_data[pos][GROUP_SIZE] <
-                    io_groupData.iv_data[pos + 1][GROUP_SIZE])
-                {
-                    FAPI_INF("mss_eff_grouping: Swapping groups %u and %u",
-                             pos, pos + 1);
-                    for (uint32_t j = 0; j < DATA_ELEMENTS; j++)
-                    {
-                        temp[j] = io_groupData.iv_data[pos][j];
-                    }
-                    for (uint32_t j = 0; j < DATA_ELEMENTS; j++)
-                    {
-                        io_groupData.iv_data[pos][j] =
-                            io_groupData.iv_data[pos + 1][j];
-                    }
-                    for (uint32_t j = 0; j < DATA_ELEMENTS; j++)
-                    {
-                        io_groupData.iv_data[pos + 1][j] = temp[j];
-                    }
-                    swapped = true;
-                }
-            }
-        }
-    }
-}
-
-/**
- * @brief Calculate Mirror Memory base and alt-base addresses
- *
- * @param[in] i_target           Reference to processor chip target
- * @param[io] io_procAttrs       Processor Attributes (iv_mirrorBaseAddr can be
- *                                                     updated)
- * @param[io] io_groupData       Group Data
- * @param[in] i_totalSizeNonMirr Total non mirrored size
- *
- * @return fapi::ReturnCode
- */
-fapi::ReturnCode grouping_calcMirrorMemory(const fapi::Target & i_target,
-                                           EffGroupingProcAttrs & io_procAttrs,
-                                           EffGroupingData & io_groupData)
-{
-    FAPI_INF("mss_eff_grouping: Calculating Mirror Memory");
-    fapi::ReturnCode rc;
-
-    // Calculate mirrored group size and non mirrored group size
-    for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
-    {
-        if (io_groupData.iv_data[pos][MCS_IN_GROUP] > 1)
-        {
-            // Mirrored size is half the group size
-            io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE] =
-                io_groupData.iv_data[pos][GROUP_SIZE] / 2;
-
-            if (io_groupData.iv_data[pos][ALT_VALID])
-            {
-                FAPI_INF("mss_eff_grouping: Mirrored group %u needs alt bars definition, group size %u GB",
-                         pos, io_groupData.iv_data[pos][GROUP_SIZE]);
-                io_groupData.iv_data[pos + MIRR_OFFSET][ALT_SIZE] =
-                    io_groupData.iv_data[pos][ALT_SIZE] / 2;
-                io_groupData.iv_data[pos + MIRR_OFFSET][ALT_VALID] = 1;
-            }
-        }
-    }
-
-    // Check if the memory base address overlaps with the mirror base address
-    if ( (io_procAttrs.iv_memBaseAddr >
-          (io_procAttrs.iv_mirrorBaseAddr +
-           io_groupData.iv_totalSizeNonMirr / 2)) ||
-         (io_procAttrs.iv_mirrorBaseAddr >
-          (io_procAttrs.iv_memBaseAddr + io_groupData.iv_totalSizeNonMirr)) )
-    {
-        for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
-        {
-            if (pos == 0)
-            {
-                io_groupData.iv_data[pos][BASE_ADDR] =
-                    io_procAttrs.iv_memBaseAddr;
-                if (io_groupData.iv_data[pos][ALT_VALID])
-                {
-                    io_groupData.iv_data[pos][ALT_BASE_ADDR] =
-                        io_groupData.iv_data[pos][BASE_ADDR] +
-                        io_groupData.iv_data[pos][GROUP_SIZE] / 2;
-                }
-            }
-            else
-            {
-                io_groupData.iv_data[pos][BASE_ADDR] =
-                    io_groupData.iv_data[pos - 1][BASE_ADDR] +
-                    io_groupData.iv_data[pos - 1][GROUP_SIZE];
-                if (io_groupData.iv_data[pos][ALT_VALID])
-                {
-                    io_groupData.iv_data[pos][ALT_BASE_ADDR] =
-                        io_groupData.iv_data[pos][BASE_ADDR] +
-                        io_groupData.iv_data[pos][GROUP_SIZE] / 2;
-                }
-            }
-
-            if (io_groupData.iv_data[pos][MCS_IN_GROUP] > 1)
-            {
-                io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] =
-                    io_procAttrs.iv_mirrorBaseAddr;
-                io_procAttrs.iv_mirrorBaseAddr =
-                    io_procAttrs.iv_mirrorBaseAddr +
-                    io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE];
-                if (io_groupData.iv_data[pos][ALT_VALID])
-                {
-                    io_groupData.iv_data[pos + MIRR_OFFSET][ALT_BASE_ADDR] =
-                        io_groupData.iv_data[pos + MIRR_OFFSET][BASE_ADDR] +
-                        io_groupData.iv_data[pos + MIRR_OFFSET][GROUP_SIZE] / 2;
-                    io_groupData.iv_data[pos + MIRR_OFFSET][ALT_VALID] = 1;
-                }
-            }
-        }
-    }
-    else
-    {
-        FAPI_ERR("mss_eff_grouping: Mirror Base address overlaps with memory base address");
-        const fapi::Target & PROC_CHIP = i_target;
-        const uint64_t & MEM_BASE_ADDR = io_procAttrs.iv_memBaseAddr;
-        const uint64_t & MIRROR_BASE_ADDR = io_procAttrs.iv_mirrorBaseAddr;
-        const uint32_t & SIZE_NON_MIRROR = io_groupData.iv_totalSizeNonMirr;
-        FAPI_SET_HWP_ERROR(rc,
-            RC_MSS_EFF_GROUPING_BASE_ADDRESS_OVERLAPS_MIRROR_ADDRESS);
-    }
-
-    return rc;
-}
-
-/**
- * @brief Calculate Non-mirror Memory base and alt-base addresses
- *
- * @param[in] i_procAttrs  Processor Chip Attributes
- * @param[io] io_groupData Group Data
- */
-void grouping_calcNonMirrorMemory(const EffGroupingProcAttrs & i_procAttrs,
-                                  EffGroupingData & io_groupData)
-{
-    FAPI_INF("mss_eff_grouping: Calculating Mirror Memory");
-
-    // Assign mirroring and non-mirroring base address for each group
-    for (uint8_t pos = 0; pos < io_groupData.iv_numGroups; pos++)
-    {
-        if (pos == 0)
-        {
-            io_groupData.iv_data[pos][BASE_ADDR] = i_procAttrs.iv_memBaseAddr;
-            if (io_groupData.iv_data[pos][ALT_VALID])
-            {
-                io_groupData.iv_data[pos][ALT_BASE_ADDR] =
-                    io_groupData.iv_data[pos][BASE_ADDR] +
-                    io_groupData.iv_data[pos][GROUP_SIZE] / 2;
-            }
-        }
-        else
-        {
-            io_groupData.iv_data[pos][BASE_ADDR] =
-                io_groupData.iv_data[pos - 1][BASE_ADDR] +
-                io_groupData.iv_data[pos - 1][GROUP_SIZE];
-            if (io_groupData.iv_data[pos][ALT_VALID])
-            {
-                io_groupData.iv_data[pos][ALT_BASE_ADDR] =
-                    io_groupData.iv_data[pos][BASE_ADDR] +
-                    io_groupData.iv_data[pos][GROUP_SIZE] / 2;
-            }
-        }
-    }
-}
-
-/**
- * @brief Sets the ATTR_MSS_MEM_MC_IN_GROUP attribute
- *
- * @param[in] i_target    Reference to Processor Chip target
- * @param[in] i_groupData Group Data
- *
- * @return fapi::ReturnCode
- */
-fapi::ReturnCode grouping_setATTR_MSS_MEM_MC_IN_GROUP(
-    const fapi::Target & i_target,
-    const EffGroupingData & i_groupData)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase MC_IN_GP(8);
-    uint8_t mcs_in_group[8] = {0};
-
-    for (uint8_t i = 0; i < i_groupData.iv_numGroups; i++)
-    {
-        MC_IN_GP.flushTo0();
-        uint8_t count = i_groupData.iv_data[i][MCS_IN_GROUP];
-        for (uint8_t j = 0; j < count; j++)
-        {
-            MC_IN_GP.setBit(i_groupData. iv_data[i][MEMBER_IDX(j)]);
-        }
-        mcs_in_group[i] = MC_IN_GP.getByte(0);
-    }
-
-    FAPI_INF("mss_eff_grouping: ATTR_MSS_MEM_MC_IN_GROUP[0][1][2][3]: "
-             "0x%02x, 0x%02x, 0x%02x, 0x%02x",
-             mcs_in_group[0], mcs_in_group[1], mcs_in_group[2],
-             mcs_in_group[3]);
-    FAPI_INF("mss_eff_grouping: ATTR_MSS_MEM_MC_IN_GROUP[4][5][6][7]: "
-             "0x%02x, 0x%02x, 0x%02x, 0x%02x",
-             mcs_in_group[4], mcs_in_group[5], mcs_in_group[6],
-             mcs_in_group[7]);
-
-    rc = FAPI_ATTR_SET(ATTR_MSS_MEM_MC_IN_GROUP, &i_target, mcs_in_group);
-    if (rc)
-    {
-        FAPI_ERR("Error writing ATTR_MSS_MEM_MC_IN_GROUP");
-    }
-
-    return rc;
-}
-
-/**
- * @brief Traces the Grouping Data
- *
- * @param[in] i_sysAttrs  System Attributes
- * @param[in] i_groupData Group Data
- */
-void grouping_traceData(const EffGroupingSysAttrs & i_sysAttrs,
-                        const EffGroupingData & i_groupData)
-{
-    for (uint8_t i = 0; i < i_groupData.iv_numGroups; i++)
-    {
-        FAPI_INF("mss_eff_grouping: Group %u, MCS Size %u GB, "
-                 "Num MCSs %u, GroupSize %u GB", i,
-                 i_groupData.iv_data[i][MCS_SIZE],
-                 i_groupData.iv_data[i][MCS_IN_GROUP],
-                 i_groupData.iv_data[i][GROUP_SIZE]);
-
-        FAPI_INF("mss_eff_grouping: Group %u, Base Add 0x%08x", i,
-                 i_groupData.iv_data[i][BASE_ADDR]);
-
-        if (!i_sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            FAPI_INF("mss_eff_grouping: Group %u, Mirror Group Size %u GB, "
-                     "Mirror Base Addr 0x%08x", i,
-                     i_groupData.iv_data[i + MIRR_OFFSET][GROUP_SIZE],
-                     i_groupData.iv_data[i + MIRR_OFFSET][BASE_ADDR]);
-        }
-        for (uint8_t j = 0; j <  i_groupData.iv_data[i][MCS_IN_GROUP]; j++)
-        {
-            FAPI_INF("mss_eff_grouping: Group %u, Contains MCS %u", i,
-                     i_groupData.iv_data[i][MEMBER_IDX(j)]);
-        }
-        FAPI_INF("mss_eff_grouping: Group %u, Alt-bar valid %u, "
-                 "Alt-bar size %u GB, Alt-bar base addr 0x%08x", i,
-                 i_groupData.iv_data[i][ALT_VALID],
-                 i_groupData.iv_data[i][ALT_SIZE],
-                 i_groupData.iv_data[i][ALT_BASE_ADDR]);
-        if (!i_sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            FAPI_INF("mss_eff_grouping: Group %u, Mirror Alt-bar valid %u, "
-                     "Mirror Alt-bar Size %u GB, "
-                     "Mirror Alt-bar Base Addr 0x%08x", i,
-                     i_groupData.iv_data[i + MIRR_OFFSET][ALT_VALID],
-                     i_groupData.iv_data[i + MIRR_OFFSET][ALT_SIZE],
-                     i_groupData.iv_data[i + MIRR_OFFSET][ALT_BASE_ADDR]);
-        }
-    }
-}
-
-/**
- * @brief Sets Base and Size FAPI Attributes
- *
- * Attributes set:
- * - ATTR_PROC_MEM_BASES
- * - ATTR_PROC_MEM_BASES_ACK
- * - ATTR_PROC_MEM_SIZES
- * - ATTR_PROC_MEM_SIZES_ACK
- * - ATTR_MSS_MCS_GROUP_32
- * - ATTR_PROC_MIRROR_BASES
- * - ATTR_PROC_MIRROR_BASES_ACK
- * - ATTR_PROC_MIRROR_SIZES
- * - ATTR_PROC_MIRROR_SIZES_ACK
- * - ATTR_PROC_HTM_BAR_BASE_ADDR
- * - ATTR_PROC_OCC_SANDBOX_BASE_ADDR
- *
- * @param[in] i_target    Reference to Processor Chip Target
- * @param[in] i_sysAttrs  System Attributes
- * @param[in] i_procAttrs Processor Chip Attributes (iv_htmBarSize set)
- * @param[in] i_groupData Group Data
- */
-fapi::ReturnCode grouping_setBaseSizeAttrs(
-    const fapi::Target & i_target,
-    const EffGroupingSysAttrs & i_sysAttrs,
-    EffGroupingProcAttrs & io_procAttrs,
-    EffGroupingData & i_groupData)
-{
-    FAPI_INF("mss_eff_grouping: Setting Base/Size attributes");
-    fapi::ReturnCode rc;
-
-    do
-    {
-        uint64_t occ_sandbox_base = 0;
-        uint64_t htm_bar_base = 0;
-        uint64_t mem_bases[8] = {0};
-        uint64_t mem_bases_ack[8] = {0};
-        uint64_t l_memory_sizes[8] = {0};
-        uint64_t l_memory_sizes_ack[8] = {0};
-        uint64_t mirror_bases[4] = {0};
-        uint64_t mirror_bases_ack[4] = {0};
-        uint64_t l_mirror_sizes[4] = {0};
-        uint64_t l_mirror_sizes_ack[4] = {0};
-
-        // base addresses for distinct non-mirrored ranges
-        mem_bases[0] = i_groupData.iv_data[0][BASE_ADDR];
-        mem_bases[1] = i_groupData.iv_data[1][BASE_ADDR];
-        mem_bases[2] = i_groupData.iv_data[2][BASE_ADDR];
-        mem_bases[3] = i_groupData.iv_data[3][BASE_ADDR];
-        mem_bases[4] = i_groupData.iv_data[4][BASE_ADDR];
-        mem_bases[5] = i_groupData.iv_data[5][BASE_ADDR];
-        mem_bases[6] = i_groupData.iv_data[6][BASE_ADDR];
-        mem_bases[7] = i_groupData.iv_data[7][BASE_ADDR];
-        mem_bases_ack[0] = i_groupData.iv_data[0][BASE_ADDR];
-        mem_bases_ack[1] = i_groupData.iv_data[1][BASE_ADDR];
-        mem_bases_ack[2] = i_groupData.iv_data[2][BASE_ADDR];
-        mem_bases_ack[3] = i_groupData.iv_data[3][BASE_ADDR];
-        mem_bases_ack[4] = i_groupData.iv_data[4][BASE_ADDR];
-        mem_bases_ack[5] = i_groupData.iv_data[5][BASE_ADDR];
-        mem_bases_ack[6] = i_groupData.iv_data[6][BASE_ADDR];
-        mem_bases_ack[7] = i_groupData.iv_data[7][BASE_ADDR];
-
-        // Base size modified for selective mode to do better packing memory
-        // which helps to do bare metal exerciser memory stressing
-        if (i_sysAttrs.iv_selectiveMode ==
-            fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
-        {
-            l_memory_sizes[0] = i_groupData.iv_data[0][GROUP_SIZE] / 2;
-            l_memory_sizes[1] = i_groupData.iv_data[1][GROUP_SIZE] / 2;
-            l_memory_sizes[2] = i_groupData.iv_data[2][GROUP_SIZE] / 2;
-            l_memory_sizes[3] = i_groupData.iv_data[3][GROUP_SIZE] / 2;
-            l_memory_sizes[4] = i_groupData.iv_data[4][GROUP_SIZE] / 2;
-            l_memory_sizes[5] = i_groupData.iv_data[5][GROUP_SIZE] / 2;
-            l_memory_sizes[6] = i_groupData.iv_data[6][GROUP_SIZE] / 2;
-            l_memory_sizes[7] = i_groupData.iv_data[7][GROUP_SIZE] / 2;
-        }
-        else
-        {
-            // sizes for distinct non-mirrored ranges
-            l_memory_sizes[0] = i_groupData.iv_data[0][MCS_SIZE]
-                * i_groupData.iv_data[0][MCS_IN_GROUP];
-            l_memory_sizes[1] = i_groupData.iv_data[1][MCS_SIZE]
-                * i_groupData.iv_data[1][MCS_IN_GROUP];
-            l_memory_sizes[2] = i_groupData.iv_data[2][MCS_SIZE]
-                * i_groupData.iv_data[2][MCS_IN_GROUP];
-            l_memory_sizes[3] = i_groupData.iv_data[3][MCS_SIZE]
-                * i_groupData.iv_data[3][MCS_IN_GROUP];
-            l_memory_sizes[4] = i_groupData.iv_data[4][MCS_SIZE]
-                * i_groupData.iv_data[4][MCS_IN_GROUP];
-            l_memory_sizes[5] = i_groupData.iv_data[5][MCS_SIZE]
-                * i_groupData.iv_data[5][MCS_IN_GROUP];
-            l_memory_sizes[6] = i_groupData.iv_data[6][MCS_SIZE]
-                * i_groupData.iv_data[6][MCS_IN_GROUP];
-            l_memory_sizes[7] = i_groupData.iv_data[7][MCS_SIZE]
-                * i_groupData.iv_data[7][MCS_IN_GROUP];
-        }
-
-        l_memory_sizes_ack[0] = i_groupData.iv_data[0][GROUP_SIZE];
-        l_memory_sizes_ack[1] = i_groupData.iv_data[1][GROUP_SIZE];
-        l_memory_sizes_ack[2] = i_groupData.iv_data[2][GROUP_SIZE];
-        l_memory_sizes_ack[3] = i_groupData.iv_data[3][GROUP_SIZE];
-        l_memory_sizes_ack[4] = i_groupData.iv_data[4][GROUP_SIZE];
-        l_memory_sizes_ack[5] = i_groupData.iv_data[5][GROUP_SIZE];
-        l_memory_sizes_ack[6] = i_groupData.iv_data[6][GROUP_SIZE];
-        l_memory_sizes_ack[7] = i_groupData.iv_data[7][GROUP_SIZE];
-
-        if (!i_sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            // Process mirrored ranges
-            if (i_sysAttrs.iv_selectiveMode ==
-                fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
-            {
-                uint8_t groupcount = 0;
-                for (uint8_t i = 0; i < NUM_MCS_PER_PROC; i++)
-                {
-                    if (i_groupData.iv_data[i][GROUP_SIZE] > 1)
-                    {
-                        groupcount++;
-                    }
-                }
-                if (groupcount < 7)
-                {
-                    mem_bases[groupcount + 0] =
-                        i_groupData.iv_data[8][BASE_ADDR] +
-                            (i_groupData.iv_data[8][GROUP_SIZE] / 2);
-                    mem_bases[groupcount + 1] =
-                        i_groupData.iv_data[9][BASE_ADDR] +
-                            (i_groupData.iv_data[9][GROUP_SIZE] / 2);
-                    mem_bases[groupcount + 2] =
-                        i_groupData.iv_data[10][BASE_ADDR] +
-                            (i_groupData.iv_data[10][GROUP_SIZE] / 2);
-                    mem_bases[groupcount + 3] =
-                        i_groupData.iv_data[11][BASE_ADDR] +
-                            (i_groupData.iv_data[11][GROUP_SIZE] / 2);
-                }
-
-                // Selective mode - Mirroring will be moved in non-mirroring
-                // space virutally
-                mirror_bases[0] = 0;
-                mirror_bases[1] = 0;
-                mirror_bases[2] = 0;
-                mirror_bases[3] = 0;
-            }
-            else
-            {
-                // base addresses for distinct mirrored ranges
-                mirror_bases[0] = i_groupData.iv_data[8][BASE_ADDR];
-                mirror_bases[1] = i_groupData.iv_data[9][BASE_ADDR];
-                mirror_bases[2] = i_groupData.iv_data[10][BASE_ADDR];
-                mirror_bases[3] = i_groupData.iv_data[11][BASE_ADDR];
-            }
-            mirror_bases_ack[0] = i_groupData.iv_data[8][BASE_ADDR];
-            mirror_bases_ack[1] = i_groupData.iv_data[9][BASE_ADDR];
-            mirror_bases_ack[2] = i_groupData.iv_data[10][BASE_ADDR];
-            mirror_bases_ack[3] = i_groupData.iv_data[11][BASE_ADDR];
-
-            if (i_sysAttrs.iv_selectiveMode ==
-                fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_SELECTIVE)
-            {
-                uint8_t groupcount = 0;
-                for (uint8_t i = 0; i < NUM_MCS_PER_PROC; i++)
-                {
-                    if (i_groupData.iv_data[i][MCS_IN_GROUP] > 1)
-                    {
-                        groupcount++;
-                    }
-                }
-                if (groupcount < 7)
-                {
-                    l_memory_sizes[groupcount + 0] =
-                        i_groupData.iv_data[8][GROUP_SIZE] / 2;
-                    l_memory_sizes[groupcount + 1] =
-                        i_groupData.iv_data[9][GROUP_SIZE] / 2;
-                    l_memory_sizes[groupcount + 2] =
-                        i_groupData.iv_data[10][GROUP_SIZE] / 2;
-                    l_memory_sizes[groupcount + 3] =
-                        i_groupData.iv_data[11][GROUP_SIZE] / 2;
-                }
-                l_mirror_sizes[0] = 0;
-                l_mirror_sizes[1] = 0;
-                l_mirror_sizes[2] = 0;
-                l_mirror_sizes[3] = 0;
-            }
-            else
-            {
-                // sizes for distinct mirrored ranges
-                for (uint8_t i = 0; i < 4; i++)
-                {
-                    if (i_groupData.iv_data[i][MCS_IN_GROUP] > 1)
-                    {
-                        l_mirror_sizes[i] =
-                            (i_groupData.iv_data[i][MCS_SIZE] *
-                             i_groupData.iv_data[0][MCS_IN_GROUP]) / 2;
-                    }
-                    else
-                    {
-                        l_mirror_sizes[i] = 0;
-                    }
-                }
-            }
-            l_mirror_sizes_ack[0] = i_groupData.iv_data[8][GROUP_SIZE];
-            l_mirror_sizes_ack[1] = i_groupData.iv_data[9][GROUP_SIZE];
-            l_mirror_sizes_ack[2] = i_groupData.iv_data[10][GROUP_SIZE];
-            l_mirror_sizes_ack[3] = i_groupData.iv_data[11][GROUP_SIZE];
-        }
-
-        mem_bases[0] = mem_bases[0] << 30;
-        mem_bases[1] = mem_bases[1] << 30;
-        mem_bases[2] = mem_bases[2] << 30;
-        mem_bases[3] = mem_bases[3] << 30;
-        mem_bases[4] = mem_bases[4] << 30;
-        mem_bases[5] = mem_bases[5] << 30;
-        mem_bases[6] = mem_bases[6] << 30;
-        mem_bases[7] = mem_bases[7] << 30;
-        mem_bases_ack[0] = mem_bases_ack[0] << 30;
-        mem_bases_ack[1] = mem_bases_ack[1] << 30;
-        mem_bases_ack[2] = mem_bases_ack[2] << 30;
-        mem_bases_ack[3] = mem_bases_ack[3] << 30;
-        mem_bases_ack[4] = mem_bases_ack[4] << 30;
-        mem_bases_ack[5] = mem_bases_ack[5] << 30;
-        mem_bases_ack[6] = mem_bases_ack[6] << 30;
-        mem_bases_ack[7] = mem_bases_ack[7] << 30;
-        l_memory_sizes[0] = l_memory_sizes[0] << 30;
-        l_memory_sizes[1] = l_memory_sizes[1] << 30;
-        l_memory_sizes[2] = l_memory_sizes[2] << 30;
-        l_memory_sizes[3] = l_memory_sizes[3] << 30;
-        l_memory_sizes[4] = l_memory_sizes[4] << 30;
-        l_memory_sizes[5] = l_memory_sizes[5] << 30;
-        l_memory_sizes[6] = l_memory_sizes[6] << 30;
-        l_memory_sizes[7] = l_memory_sizes[7] << 30;
-        l_memory_sizes_ack[0] = l_memory_sizes_ack[0] << 30;
-        l_memory_sizes_ack[1] = l_memory_sizes_ack[1] << 30;
-        l_memory_sizes_ack[2] = l_memory_sizes_ack[2] << 30;
-        l_memory_sizes_ack[3] = l_memory_sizes_ack[3] << 30;
-        l_memory_sizes_ack[4] = l_memory_sizes_ack[4] << 30;
-        l_memory_sizes_ack[5] = l_memory_sizes_ack[5] << 30;
-        l_memory_sizes_ack[6] = l_memory_sizes_ack[6] << 30;
-        l_memory_sizes_ack[7] = l_memory_sizes_ack[7] << 30;
-
-        if (!i_sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            mirror_bases[0] = mirror_bases[0] << 30;
-            mirror_bases[1] = mirror_bases[1] << 30;
-            mirror_bases[2] = mirror_bases[2] << 30;
-            mirror_bases[3] = mirror_bases[3] << 30;
-            mirror_bases_ack[0] = mirror_bases_ack[0] << 30;
-            mirror_bases_ack[1] = mirror_bases_ack[1] << 30;
-            mirror_bases_ack[2] = mirror_bases_ack[2] << 30;
-            mirror_bases_ack[3] = mirror_bases_ack[3] << 30;
-            l_mirror_sizes[0] = l_mirror_sizes[0] << 30;
-            l_mirror_sizes[1] = l_mirror_sizes[1] << 30;
-            l_mirror_sizes[2] = l_mirror_sizes[2] << 30;
-            l_mirror_sizes[3] = l_mirror_sizes[3] << 30;
-            FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[0]: 0x%016llx", l_mirror_sizes[0]);
-            FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[1]: 0x%016llx", l_mirror_sizes[1]);
-            FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[2]: 0x%016llx", l_mirror_sizes[2]);
-            FAPI_DBG("  ATTR_PROC_MIRROR_SIZES[3]: 0x%016llx", l_mirror_sizes[3]);
-            l_mirror_sizes_ack[0] = l_mirror_sizes_ack[0] << 30;
-            l_mirror_sizes_ack[1] = l_mirror_sizes_ack[1] << 30;
-            l_mirror_sizes_ack[2] = l_mirror_sizes_ack[2] << 30;
-            l_mirror_sizes_ack[3] = l_mirror_sizes_ack[3] << 30;
-        }
-
-        //------------------------------------------------------------------
-        // Defining HTM and OCC base address based on HTM/OCC bar size
-        //------------------------------------------------------------------
-        if ((i_sysAttrs.iv_selectiveMode ==
-             fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) ||
-            (i_sysAttrs.iv_selectiveMode ==
-             fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_DRAWER))
-        {
-            uint64_t total_size = 0;
-            uint8_t memhole = 0;
-            for (uint8_t i = 0; i < 8; i++)
-            {
-                total_size += l_memory_sizes[i];
-                if (i_groupData.iv_data[i][ALT_VALID])
-                {
-                    memhole++;
-                }
-            }
-            if ((total_size >=
-                 (io_procAttrs.iv_htmBarSize +
-                  io_procAttrs.iv_occSandboxSize)) &&
-                ((io_procAttrs.iv_htmBarSize +
-                  io_procAttrs.iv_occSandboxSize) > 0))
-            {
-                uint64_t other_bar_size = io_procAttrs.iv_htmBarSize +
-                                          io_procAttrs.iv_occSandboxSize;
-                uint64_t non_mirroring_size = total_size - other_bar_size;
-                uint64_t temp_size = 0;
-                uint8_t done = 0;
-                uint8_t j = 0;
-                uint8_t i = 0;
-                while (!done)
-                {
-                    if ((temp_size <= non_mirroring_size) &&
-                        (non_mirroring_size <=
-                            (temp_size += l_memory_sizes[i++])))
-                    {
-                        done = 1;
-                    }
-                }
-                j = i;
-
-                if (memhole)
-                {
-                    if (l_memory_sizes[j - 1] < other_bar_size)
-                    {
-                        FAPI_ERR("mss_eff_grouping: Memory HTM/OCC BAR not "
-                                 "possible (normal), Total Memory 0x%016llx",
-                                 l_memory_sizes[j - 1]);
-                        const uint64_t TOTAL_SIZE = l_memory_sizes[j - 1];
-                        const uint64_t & HTM_BAR_SIZE =
-                            io_procAttrs.iv_htmBarSize;
-                        const uint64_t & OCC_SANDBOX_BAR_SIZE =
-                            io_procAttrs.iv_occSandboxSize;
-                        const uint8_t & MIRROR_PLACEMENT_POLICY =
-                            i_sysAttrs.iv_selectiveMode;
-                        FAPI_SET_HWP_ERROR(rc,
-                            RC_MSS_EFF_GROUPING_HTM_OCC_BAR_NOT_POSSIBLE);
-                        break;
-                    }
-                    else
-                    {
-                        l_memory_sizes[i - 1] = l_memory_sizes[i - 1]
-                            - (temp_size - non_mirroring_size);
-                    }
-                }
-                else
-                {
-                    l_memory_sizes[i - 1] = l_memory_sizes[i - 1] - (temp_size
-                        - non_mirroring_size);
-                    for (; i < 8; i++)
-                    {
-                        if (l_memory_sizes[i])
-                        {
-                            l_memory_sizes[i] = 0;
-                        }
-                    }
-                }
-                if (io_procAttrs.iv_htmBarSize < io_procAttrs.iv_occSandboxSize)
-                {
-                    occ_sandbox_base = mem_bases[j - 1] + l_memory_sizes[j - 1];
-                    htm_bar_base = occ_sandbox_base +
-                        io_procAttrs.iv_occSandboxSize;
-                }
-                else
-                {
-                    htm_bar_base = mem_bases[j - 1] + l_memory_sizes[j - 1];
-                    occ_sandbox_base = htm_bar_base + io_procAttrs.iv_htmBarSize;
-                }
-                FAPI_DBG("mss_eff_grouping: TOTAL MEMORY 0x%016llx", total_size);
-                if (!i_sysAttrs.iv_enhancedNoMirrorMode)
-                {
-                    FAPI_DBG("mss_eff_grouping: MIRRORING SIZE: 0x%016llx & %d",
-                             l_mirror_sizes[j - 1], j);
-                    FAPI_DBG("mss_eff_grouping: Required MIRRORING SIZE: 0x%016llx ",
-                             non_mirroring_size);
-                }
-                FAPI_DBG("mss_eff_grouping: HTM_BASE : 0x%016llx", htm_bar_base);
-                FAPI_DBG("mss_eff_grouping: OCC_BASE : 0x%016llx",
-                         occ_sandbox_base);
-            }
-            else if ((total_size >=
-                     (io_procAttrs.iv_htmBarSize +
-                      io_procAttrs.iv_occSandboxSize)) &&
-                     ((io_procAttrs.iv_htmBarSize +
-                       io_procAttrs.iv_occSandboxSize) == 0))
-            {
-            }
-            else
-            {
-                FAPI_ERR("mss_eff_grouping: Required memory space for the HTM "
-                         "and OCC SANDBOX BARS is not available (normal). "
-                         "Total Size 0x%016llx", total_size);
-                const uint64_t TOTAL_SIZE = total_size;
-                const uint64_t & HTM_BAR_SIZE = io_procAttrs.iv_htmBarSize;
-                const uint64_t & OCC_SANDBOX_BAR_SIZE =
-                    io_procAttrs.iv_occSandboxSize;
-                const uint8_t & MIRROR_PLACEMENT_POLICY =
-                    i_sysAttrs.iv_selectiveMode;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_MSS_EFF_GROUPING_NO_SPACE_FOR_HTM_OCC_BAR);
-                break;
-            }
-        }
-        else if ((i_sysAttrs.iv_selectiveMode ==
-                 fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED) ||
-                 (i_sysAttrs.iv_selectiveMode ==
-                 fapi::ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED_DRAWER))
-        {
-            uint64_t total_size = 0;
-            uint8_t memhole = 0;
-            uint8_t j = 0;
-            for (uint8_t i = 0; i < 4; i++)
-            {
-                total_size += l_mirror_sizes[i];
-                if (i_groupData.iv_data[i][ALT_VALID])
-                {
-                    memhole++;
-                }
-            }
-
-            if ((total_size >=
-                 (io_procAttrs.iv_htmBarSize + io_procAttrs.iv_occSandboxSize)) &&
-                ((io_procAttrs.iv_htmBarSize + io_procAttrs.iv_occSandboxSize) >
-                 0))
-            {
-                uint64_t other_bar_size = 0;
-                other_bar_size = io_procAttrs.iv_htmBarSize +
-                    io_procAttrs.iv_occSandboxSize;
-                uint64_t non_mirroring_size = total_size - other_bar_size;
-                uint64_t temp_size = 0;
-                uint8_t done = 0;
-                uint8_t i = 0;
-                while (!done)
-                {
-                    if ((temp_size <= non_mirroring_size)
-                        && (non_mirroring_size <= (temp_size
-                            += l_mirror_sizes[i++])))
-                    {
-                        done = 1;
-                    }
-                }
-                j = i;
-                if (memhole)
-                {
-                    if (l_mirror_sizes[j - 1] < other_bar_size)
-                    {
-                        FAPI_ERR("mss_eff_grouping: Memory HTM/OCC BAR not "
-                                 "possible (flipped), Total Memory 0x%016llx",
-                                 l_memory_sizes[j - 1]);
-                        const uint64_t TOTAL_SIZE = l_memory_sizes[j - 1];
-                        const uint64_t & HTM_BAR_SIZE =
-                            io_procAttrs.iv_htmBarSize;
-                        const uint64_t & OCC_SANDBOX_BAR_SIZE =
-                            io_procAttrs.iv_occSandboxSize;
-                        const uint8_t & MIRROR_PLACEMENT_POLICY =
-                            i_sysAttrs.iv_selectiveMode;
-                        FAPI_SET_HWP_ERROR(rc,
-                            RC_MSS_EFF_GROUPING_HTM_OCC_BAR_NOT_POSSIBLE);
-                        break;
-                    }
-                    else
-                    {
-                        l_mirror_sizes[i - 1] = l_mirror_sizes[i - 1]
-                            - (temp_size - non_mirroring_size);
-                    }
-                }
-                else
-                {
-                    l_mirror_sizes[i - 1] = l_mirror_sizes[i - 1] - (temp_size
-                        - non_mirroring_size);
-                    for (; i < 8; i++)
-                    {
-                        if (l_memory_sizes[i])
-                            l_memory_sizes[i] = 0;
-                    }
-                }
-                if (io_procAttrs.iv_htmBarSize < io_procAttrs.iv_occSandboxSize)
-                {
-                    occ_sandbox_base = mirror_bases[j - 1] +
-                        l_mirror_sizes[j - 1];
-                    io_procAttrs.iv_htmBarSize =
-                        occ_sandbox_base + io_procAttrs.iv_occSandboxSize;
-                }
-                else
-                {
-                    htm_bar_base = mirror_bases[j - 1] + l_mirror_sizes[j - 1];
-                    occ_sandbox_base = htm_bar_base + io_procAttrs.iv_htmBarSize;
-                }
-                FAPI_DBG(" TOTAL MEMORY 0x%016llx", total_size);
-                FAPI_DBG("  MIRRORING SIZE: 0x%016llx & %d",
-                         l_mirror_sizes[j - 1], j);
-                FAPI_DBG("  Required MIRRORING SIZE: 0x%016llx ",
-                         non_mirroring_size);
-                FAPI_DBG("  HTM_BASE : 0x%016llx", htm_bar_base);
-                FAPI_DBG("  OCC_BASE : 0x%016llx", occ_sandbox_base);
-            }
-            else if ((total_size >=
-                (io_procAttrs.iv_htmBarSize + io_procAttrs.iv_occSandboxSize)) &&
-                ((io_procAttrs.iv_htmBarSize + io_procAttrs.iv_occSandboxSize) == 0))
-            {
-            }
-            else
-            {
-                FAPI_ERR("mss_eff_grouping: Required memory space for the HTM "
-                         "and OCC SANDBOX BARS is not available (flipped). "
-                         "Total Size 0x%016llx", total_size);
-                const uint64_t TOTAL_SIZE = total_size;
-                const uint64_t & HTM_BAR_SIZE = io_procAttrs.iv_htmBarSize;
-                const uint64_t & OCC_SANDBOX_BAR_SIZE =
-                    io_procAttrs.iv_occSandboxSize;
-                const uint8_t & MIRROR_PLACEMENT_POLICY =
-                    i_sysAttrs.iv_selectiveMode;
-                FAPI_SET_HWP_ERROR(rc,
-                    RC_MSS_EFF_GROUPING_NO_SPACE_FOR_HTM_OCC_BAR);
-                break;
-            }
-        }
-
-        //----------------------------------------------------------------------
-        //  Setting up Calculated Attributes
-        //----------------------------------------------------------------------
-        for (uint8_t i = 0; i < 8; i++)
-        {
-            FAPI_INF("mss_eff_grouping: ATTR_PROC_MEM_BASES[%u]: 0x%016llx",
-                     i, mem_bases[i]);
-        }
-        rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES, &i_target, mem_bases);
-        if (rc)
-        {
-            FAPI_ERR("Error writing ATTR_PROC_MEM_BASES");
-            break;
-        }
-
-        for (uint8_t i = 0; i < 8; i++)
-        {
-            FAPI_INF("mss_eff_grouping: ATTR_PROC_MEM_BASES_ACK[%u]: 0x%016llx",
-                     i, mem_bases_ack[i]);
-        }
-        rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASES_ACK, &i_target, mem_bases_ack);
-        if (rc)
-        {
-            FAPI_ERR("Error writing ATTR_PROC_MEM_BASES_ACK");
-            break;
-        }
-
-        for (uint8_t i = 0; i < 8; i++)
-        {
-            FAPI_INF("mss_eff_grouping: ATTR_PROC_MEM_SIZES[%u]: 0x%016llx",
-                     i, l_memory_sizes[i]);
-        }
-        rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES, &i_target, l_memory_sizes);
-        if (rc)
-        {
-            FAPI_ERR("Error writing ATTR_PROC_MEM_SIZES");
-            break;
-        }
-
-        for (uint8_t i = 0; i < 8; i++)
-        {
-            FAPI_INF("mss_eff_grouping: ATTR_PROC_MEM_SIZES_ACK[%u]: 0x%016llx",
-                     i, l_memory_sizes_ack[i]);
-        }
-        rc = FAPI_ATTR_SET(ATTR_PROC_MEM_SIZES_ACK, &i_target,
-                           l_memory_sizes_ack);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error writing ATTR_PROC_MEM_SIZES_ACK");
-            break;
-        }
-
-        rc = FAPI_ATTR_SET(ATTR_MSS_MCS_GROUP_32, &i_target,
-                           i_groupData.iv_data);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error writing ATTR_MSS_MCS_GROUP");
-            break;
-        }
-
-        if (!i_sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            for (uint8_t i = 0; i < 4; i++)
-            {
-                FAPI_INF("mss_eff_grouping: ATTR_PROC_MIRROR_BASES[%u]: "
-                         "0x%016llx", i, mirror_bases[i]);
-            }
-            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES, &i_target, mirror_bases);
-            if (rc)
-            {
-                FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES");
-                break;
-            }
-
-            for (uint8_t i = 0; i < 4; i++)
-            {
-                FAPI_INF("mss_eff_grouping: ATTR_PROC_MIRROR_BASES_ACK[%u]: "
-                         "0x%016llx", i, mirror_bases_ack[i]);
-            }
-            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASES_ACK, &i_target,
-                               mirror_bases_ack);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing ATTR_PROC_MIRROR_BASES_ACK");
-                break;
-            }
-
-            for (uint8_t i = 0; i < 4; i++)
-            {
-                FAPI_INF("mss_eff_grouping: ATTR_PROC_MIRROR_SIZES[%u]: "
-                         "0x%016llx", i, l_mirror_sizes[i]);
-            }
-            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES, &i_target,
-                               l_mirror_sizes);
-            if (rc)
-            {
-                FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES");
-                break;
-            }
-
-            for (uint8_t i = 0; i < 4; i++)
-            {
-                FAPI_INF("mss_eff_grouping: ATTR_PROC_MIRROR_SIZES_ACK[%u]: "
-                         "0x%016llx", i, l_mirror_sizes_ack[i]);
-            }
-            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_SIZES_ACK, &i_target,
-                               l_mirror_sizes_ack);
-            if (rc)
-            {
-                FAPI_ERR("Error writing ATTR_PROC_MIRROR_SIZES_ACK");
-                break;
-            }
-        }
-
-        FAPI_INF("mss_eff_grouping: ATTR_PROC_HTM_BAR_BASE_ADDR: 0x%016llx",
-                 htm_bar_base);
-        rc = FAPI_ATTR_SET(ATTR_PROC_HTM_BAR_BASE_ADDR, &i_target,
-                            htm_bar_base);
-        if (rc)
-        {
-            FAPI_ERR("Error writing ATTR_PROC_HTM_BAR_BASE_ADDR");
-            break;
-        }
-
-        FAPI_INF("mss_eff_grouping: ATTR_PROC_OCC_SANDBOX_BASE_ADDR: 0x%016llx",
-                 occ_sandbox_base);
-        rc = FAPI_ATTR_SET(ATTR_PROC_OCC_SANDBOX_BASE_ADDR, &i_target,
-                           occ_sandbox_base);
-        if (rc)
-        {
-            FAPI_ERR("Error writing  ATTR_PROC_OCC_SANDBOX_BASE_ADDR");
-            break;
-        }
-    } while (0);
-
-    return rc;
-}
-
-//------------------------------------------------------------------------------
-// mss_eff_grouping HW Procedure
-//------------------------------------------------------------------------------
-fapi::ReturnCode mss_eff_grouping(const fapi::Target & i_target,
-    std::vector<fapi::Target> &i_associated_centaurs)
-{
-    fapi::ReturnCode rc;
-    FAPI_INF("mss_eff_grouping: Start, chip %s", i_target.toEcmdString());
-
-    do
-    {
-        // Fill in the EffGroupingMemInfo structure with memory information
-        EffGroupingMemInfo memInfo;
-        rc = memInfo.getMemInfo(i_associated_centaurs);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error getting mem info");
-            break;
-        }
-
-        // Get the necessary system attributes
-        EffGroupingSysAttrs sysAttrs;
-        rc = sysAttrs.getAttrs();
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error getting system attributes");
-            break;
-        }
-
-        // Get the necessary processor chip attributes
-        EffGroupingProcAttrs procAttrs;
-        rc = procAttrs.getAttrs(i_target);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error getting proc chip attributes");
-            break;
-        }
-
-        // Check that the system and processor chip attributes are valid
-        rc = grouping_checkValidAttributes(sysAttrs, procAttrs);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error validating sys/proc attributes");
-            break;
-        }
-
-        // Create a EffGroupingData structure
-        EffGroupingData groupData;
-
-        // Attempt to Group the MCSs. All of the grouping functions are called
-        // if allowed, if MCSs cannot be grouped by one function they may be
-        // grouped by the subsequent functions
-        if (procAttrs.iv_groupsAllowed & MCS_GROUP_8)
-        {
-            grouping_group8McsPerGroup(memInfo, groupData);
-        }
-        if (procAttrs.iv_groupsAllowed & MCS_GROUP_4)
-        {
-            grouping_group4McsPerGroup(memInfo, groupData);
-        }
-        if (procAttrs.iv_groupsAllowed & MCS_GROUP_2)
-        {
-            grouping_group2McsPerGroup(memInfo, groupData);
-        }
-        if (procAttrs.iv_groupsAllowed & MCS_GROUP_1)
-        {
-            // Note that grouping_checkValidAttributes() ensures that this is
-            // only in checkerboard mode
-            grouping_group1McsPerGroup(memInfo, groupData);
-        }
-
-        // Find the ungrouped MCSs and deconfigure their associated membuf chips
-        rc = grouping_findUngroupedMCSs(memInfo, groupData);
-        if (rc)
-        {
-            // Ungrouped MCSs were found, return the error
-            FAPI_ERR("mss_eff_grouping: Error from grouping_findUngroupedMCSs");
-            break;
-        }
-
-        // Calculate Alt Memory
-        grouping_calcAltMemory(groupData);
-
-        // Sort Groups from high memory size to low
-        grouping_sortGroups(groupData);
-
-        // Calculate the total non mirrored size
-        for (uint8_t pos = 0; pos < groupData.iv_numGroups; pos++)
-        {
-            groupData.iv_totalSizeNonMirr += groupData.iv_data[pos][GROUP_SIZE];
-        }
-        FAPI_INF("mss_eff_grouping: Total non-mirrored size %u GB",
-                 groupData.iv_totalSizeNonMirr);
-
-        if (!sysAttrs.iv_enhancedNoMirrorMode)
-        {
-            // Calculate base and alt-base addresses
-            rc = grouping_calcMirrorMemory(i_target, procAttrs, groupData);
-            if (rc)
-            {
-                FAPI_ERR("mss_eff_grouping: Error from grouping_calcMirrorMemory");
-                break;
-            }
-        }
-        else
-        {
-            // ATTR_MRW_ENHANCED_GROUPING_NO_MIRRORING is true
-            // Calculate base and alt-base addresses
-            grouping_calcNonMirrorMemory(procAttrs, groupData);
-        }
-
-        // Set the ATTR_MSS_MEM_MC_IN_GROUP attribute
-        rc = grouping_setATTR_MSS_MEM_MC_IN_GROUP(i_target, groupData);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error from grouping_setATTR_MSS_MEM_MC_IN_GROUP");
-            break;
-        }
-
-        // Trace a summary of the Grouping Data
-        grouping_traceData(sysAttrs, groupData);
-
-        // Set Memory Base and Size FAPI Attributes
-        rc = grouping_setBaseSizeAttrs(i_target, sysAttrs, procAttrs,
-                                       groupData);
-        if (rc)
-        {
-            FAPI_ERR("mss_eff_grouping: Error from grouping_setBaseSizeAttrs");
-            break;
-        }
-    } while (0);
-
-    FAPI_INF("mss_eff_grouping: End");
-    return rc;
-}
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H
deleted file mode 100644
index bd71b9775..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H
+++ /dev/null
@@ -1,80 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_eff_grouping.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_grouping.H,v 1.8 2014/04/10 18:45:31 jdsloat Exp $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_grouping.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Girisankar Paulraj     Email: gpaulraj@in.ibm.com
-// *! BACKUP NAME : Mark Bellows      Email: bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_eff_grouping
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.8    | jdsloat  | 04/10/14| Mike Jones's rewrite.  
-//  1.7    | gpaulraj | 08/12/13| moved constants to C file
-//  1.6    | gpaulraj | 05/22/13| added constants for debugging purpose
-//  1.5    | bellows  | 09/25/12| review updates made
-//  1.4    | bellows  | 08/31/12| object updated, call updated
-//  1.3    | bellows  | 07/27/12| updated for setup_bars full function
-//  1.2    | bellows  | 07/16/12| added in Id tag
-//  1.1    | gpaulraj | 03/19/12| Updated
-
-#ifndef MSS_EFF_GROUPINGHWPB_H_
-#define MSS_EFF_GROUPINGHWPB_H_
-
-#include <fapi.H>
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*mss_eff_grouping_FP_t)(const fapi::Target &,
-                                                  std::vector<fapi::Target> &);
-
-extern "C"
-{
-
-/**
- * @brief mss_eff_grouping HW Procedure
- *
- * @param[in] i_target              Processor Chip Target
- * @param[in] i_associated_centaurs Memory Buffer Targets associated with the
- *                                  Processor Chip Target
- * @return fapi::ReturnCode
- */
-fapi::ReturnCode mss_eff_grouping(const fapi::Target & i_target,
-    std::vector<fapi::Target> & i_associated_centaurs);
-
-}
-
-#endif // MSS_EFF_GROUPINGHWPB_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C
deleted file mode 100644
index 4893c17d1..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C
+++ /dev/null
@@ -1,250 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_error_support.C,v 1.3 2014/02/19 13:41:28 bellows Exp $
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_error_support.C
-// *! DESCRIPTION : common and hwp error collecting programs
-// *! OWNER NAME : bellows@us.ibm.com
-// *! BACKUP NAME :
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.3    | bellows  |19-FEB-14| RAS Review Updates
-//  1.2    | bellows  | 05/08/13| Fixed error return code checking
-//  1.1    | bellows  | 03/08/13| Initial Version
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-
-#include <fapi.H>
-#include <mss_error_support.H>
-#include <cen_scom_addresses.H>
-using namespace fapi;
-
-// This is the FFDC HWP specially written to collect the data specified by RC_ERROR_MEM_GROUPING
-fapi::ReturnCode hwpCollectMemGrouping(const fapi::Target & i_target,fapi::ReturnCode & o_rc)
-{
-  fapi::ReturnCode l_rc = fapi::FAPI_RC_SUCCESS;
-
-  uint32_t _ATTR_PROC_POS;
-  uint32_t _ATTR_CEN_POS;
-  uint8_t _ATTR_CHIP_UNIT_POS_MBA0;
-  uint8_t _ATTR_CHIP_UNIT_POS_MBA1;
-  uint8_t _ATTR_EFF_DIMM_SIZE0[2][2];
-  uint8_t _ATTR_EFF_DIMM_SIZE1[2][2];
-  uint8_t _ATTR_MSS_INTERLEAVE_ENABLE;
-  uint8_t _ATTR_ALL_MCS_IN_INTERLEAVING_GROUP;
-  uint64_t _ATTR_PROC_MEM_BASE;
-  uint64_t _ATTR_PROC_MIRROR_BASE;
-  uint8_t _ATTR_MSS_MEM_MC_IN_GROUP[8];
-  uint64_t _ATTR_PROC_MEM_BASES[8];
-  uint64_t _ATTR_PROC_MEM_SIZES[8];
-  uint32_t _ATTR_MSS_MCS_GROUP_32[16][16];
-  uint64_t _ATTR_PROC_MIRROR_BASES[4];
-  uint64_t _ATTR_PROC_MIRROR_SIZES[4];
-
-  std::vector<fapi::Target> l_mba_chiplets;
-  std::vector<fapi::Target> l_memb;
-
-  unsigned i;
-
-  do
-  {
-    l_rc = FAPI_ATTR_GET(ATTR_POS, &i_target, _ATTR_PROC_POS);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_POS (Proc)");
-      break;
-    }
-
-    l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MEMBUF_CHIP, l_memb);
-    if (l_rc)
-    {
-      FAPI_ERR("Error fapiGetChildChiplets");
-      break;
-    }
-
-    for(i=0;i<l_memb.size();i++)
-    {
-      l_rc = FAPI_ATTR_GET(ATTR_POS, &l_memb[i], _ATTR_CEN_POS);
-      if (l_rc)
-      {
-        FAPI_ERR("Error reading ATTR_POS (cen)");
-        break;
-      }
-
-      l_rc = fapiGetChildChiplets(l_memb[i], fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets);
-      if (l_rc)
-      {
-        FAPI_ERR("Error fapiGetChildChiplets");
-        break;
-      }
-
-
-      l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[0], _ATTR_CHIP_UNIT_POS_MBA0);
-      if (l_rc)
-      {
-        FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS (0)");
-        break;
-      }
-
-      l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_mba_chiplets[1], _ATTR_CHIP_UNIT_POS_MBA1);
-      if (l_rc)
-      {
-        FAPI_ERR("Error reading ATTR_CHIP_UNIT_POS (1)");
-        break;
-      }
-
-      l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[0], _ATTR_EFF_DIMM_SIZE0);
-      if (l_rc)
-      {
-        FAPI_ERR("Error reading ATTR_EFF_DIMM_SIZE (0)");
-        break;
-      }
-
-      l_rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_SIZE, &l_mba_chiplets[1], _ATTR_EFF_DIMM_SIZE1);
-      if (l_rc)
-      {
-        FAPI_ERR("Error reading ATTR_EFF_DIMM_SIZE (1)");
-        break;
-      }
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_INTERLEAVE_ENABLE,&i_target, _ATTR_MSS_INTERLEAVE_ENABLE);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_MSS_INTERLEAVE_ENABLE");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_ALL_MCS_IN_INTERLEAVING_GROUP, NULL,_ATTR_ALL_MCS_IN_INTERLEAVING_GROUP); // system level attribute
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_ALL_MCS_IN_INTERLEAVING_GROUP");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,&i_target,_ATTR_PROC_MEM_BASE);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_PROC_MEM_BASE");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,&i_target,_ATTR_PROC_MIRROR_BASE);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASE");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_MEM_MC_IN_GROUP, &i_target, _ATTR_MSS_MEM_MC_IN_GROUP);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_MSS_MEM_MC_IN_GROUP");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES, &i_target, _ATTR_PROC_MEM_BASES);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_PROC_MEM_BASES");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES, &i_target, _ATTR_PROC_MEM_SIZES);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_PROC_MEM_SIZES");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_MSS_MCS_GROUP_32,&i_target, _ATTR_MSS_MCS_GROUP_32);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_MSS_MCS_GROUP_32");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES, &i_target, _ATTR_PROC_MIRROR_BASES);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_PROC_MIRROR_BASES");
-      break;
-    }
-
-    l_rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES, &i_target, _ATTR_PROC_MIRROR_SIZES);
-    if (l_rc)
-    {
-      FAPI_ERR("Error reading ATTR_PROC_MIRROR_SIZES");
-      break;
-    }
-
-    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MSS_GROUPING_ATTRS);
-
-  }while(0);
-
-  return l_rc;
-}
-
-fapi::ReturnCode hwpCollectMemFIRs(const fapi::Target & i_target,fapi::ReturnCode & o_rc)
-{
-  fapi::ReturnCode l_rc;
-
-  const fapi::Target & CENCHIP = i_target;
-
-  FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MSS_FIRS);
-
-
-  std::vector<fapi::Target> l_mba_chiplets;
-  unsigned i;
-  l_rc = fapiGetChildChiplets(i_target, fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets);
-  if (l_rc)
-  {
-    FAPI_ERR("Error fapiGetChildChiplets");
-    return l_rc;
-  }
-
-  for(i=0;i<l_mba_chiplets.size(); i++)
-  {
-    const fapi::Target & CENCHIP_MBA = l_mba_chiplets[i];
-    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_ERROR_MBA_FIRS);
-
-  }
-  return fapi::FAPI_RC_SUCCESS;
-}
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H
deleted file mode 100644
index 1e0c3ff0c..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H
+++ /dev/null
@@ -1,67 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_error_support.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_error_support.H,v 1.1 2013/03/21 19:04:22 bellows Exp $
-
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE : mss_error_support.H
-// *! DESCRIPTION : Tools
-// *! OWNER NAME : bellows@us.ibm.com
-// *! BACKUP NAME :
-// #! ADDITIONAL COMMENTS :
-//
-
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.0    | 03/08/13 | bellows | First version
-
-#ifndef _MSS_ERROR_SUPPORT_H
-#define _MSS_ERROR_SUPPORT_H
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*hwpCollectMemGrouping_FP_t)(const fapi::Target&,  fapi::ReturnCode &);
-
-extern "C"
-{
-
-
-fapi::ReturnCode hwpCollectMemGrouping(const fapi::Target & i_target,fapi::ReturnCode & o_rc);
-fapi::ReturnCode hwpCollectMemFIRs(const fapi::Target & i_target,fapi::ReturnCode & o_rc);
-
-
-
-} // extern "C"
-
-#endif /* _MSS_ERROR_SUPPORT_H */
-
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
deleted file mode 100644
index 382cc23ee..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C
+++ /dev/null
@@ -1,475 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_throttle_to_power.C,v 1.18 2014/11/06 21:07:04 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_throttle_to_power.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_throttle_to_power
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Jacob Sloat       Email: jdsloat@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// applicable CQ component memory_screen
-//
-// DESCRIPTION:
-// The purpose of this procedure is to set the power attributes for each dimm
-// and channel pair
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.18  | pardeik  |06-NOV-14| removed string in trace statement
-//         |          |         | changed FAPI_IMP to FAPI_INF
-//   1.17  | pardeik  |16-OCT-14| removed l_dimm_power_array_integer to fix
-//         |          |         |  cronus 64bit compile error
-//   1.16  | pardeik  |15-OCT-14| remove attr writing for ATTR_MSS_DIMM_MAXPOWER
-//   1.15  | pardeik  |27-AUG-14| use new power curve uplift attribute for idle 
-//   1.14  | pardeik  |21-MAY-14| Fixed power calculations
-//   1.13  | jdsloat  |10-MAR-14| Edited comments
-//   1.12  | pardeik  |06-JAN-14| added dimm power curve uplift from MRW
-//         |          |         | use max utiliation from MRW for MAX_UTIL
-//   1.11  | pardeik  |13-NOV-13| changed MAX_UTIL from 75 to 56.25
-//   1.10  | bellows  |19-SEP-13| fixed possible buffer overrun found by stradale
-//   1.9   | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
-//         |          |         | added FAPI_ERR before return code lines
-//         |          |         | made trace statements for procedures FAPI_IMP
-//   1.8   | pardeik  |25-OCT-12| updated FAPI_ERR sections, added CQ component
-//         |          |         | comment line
-//   1.7   | pardeik  |19-OCT-12| use ATTR_MSS_CHANNEL_PAIR_MAXPOWER instead of
-//         |          |         | ATTR_MSS_CHANNEL_MAXPOWER
-//         | pardeik  |19-OCT-12| multiple throttle N values by 4 to get dram
-//         |          |         | utilization
-//   1.6   | pardeik  |11-OCT-12| updated to use new throttle attributes, made
-//         |          |         | function mss_throttle_to_power_calc
-//   1.5   | pardeik  |10-APR-12| power calculation updates and fixes
-//   1.5   | pardeik  |10-APR-12| power calculation updates and fixes
-//   1.4   | pardeik  |04-APR-12| moved cdimm power calculation to end of
-//         |          |         | section instead of having it in multiple
-//         |          |         | places
-//   1.3   | pardeik  |04-APR-12| use else if instead of if after checking
-//         |          |         | throttle denominator to zero
-//   1.2   | pardeik  |03-APR-12| use mba target intead of mbs, added cdimm
-//         |          |         | power calculation for half of cdimm
-//   1.1   | pardeik  |01-APR-11| Updated to use attributes and fapi functions
-//         |          |         | to loop through ports/dimms
-//         | pardeik  |01-DEC-11| First Draft.
-
-
-//------------------------------------------------------------------------------
-//  My Includes
-//------------------------------------------------------------------------------
-#include <mss_throttle_to_power.H>
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-extern "C" {
-
-    using namespace fapi;
-
-
-//------------------------------------------------------------------------------
-// Funtions in this file
-//------------------------------------------------------------------------------
-    fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba);
-
-    fapi::ReturnCode mss_throttle_to_power_calc
-      (
-       const fapi::Target &i_target_mba,
-       uint32_t i_throttle_n_per_mba,
-       uint32_t i_throttle_n_per_chip,
-       uint32_t i_throttle_d,
-       float &channel_pair_power
-       );
-
-
-//------------------------------------------------------------------------------
-// @brief mss_throttle_to_power(): This function will get the throttle
-// attributes and call another function to determine the dimm and channel pair
-// power based on those throttles
-//
-// @param[in]	const fapi::Target &i_target_mba:  MBA Target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba)
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_throttle_to_power ***");
-
-	uint32_t throttle_n_per_mba;
-	uint32_t throttle_n_per_chip;
-	uint32_t throttle_d;
-	float channel_pair_power;
-
-// Get input attributes
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA,
-			   &i_target_mba, throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP,
-			   &i_target_mba, throttle_n_per_chip);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_MEM_THROTTLE_DENOMINATOR,
-			   &i_target_mba, throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-
-// Call function mss_throttle_to_power_calc
-	rc = mss_throttle_to_power_calc(
-					i_target_mba,
-					throttle_n_per_mba,
-					throttle_n_per_chip,
-					throttle_d,
-					channel_pair_power
-					);
-	if (rc)
-	{
-	    FAPI_ERR("Error (0x%x) calling mss_throttle_to_power_calc", static_cast<uint32_t>(rc));
-	    return rc;
-	}
-
-	FAPI_INF("*** mss_throttle_to_power COMPLETE ***");
-	return rc;
-
-    }
-
-
-
-//------------------------------------------------------------------------------
-// @brief mss_throttle_to_power_calc(): This function will calculate the dimm
-// and channel pair power and update attributes with the power values
-//
-// @param[in]   const fapi::Target &i_target_mba:  MBA Target
-// @param[in]   uint32_t i_throttle_n_per_mba:  Throttle value for
-//              cfg_nm_n_per_mba
-// @param[in]   uint32_t i_throttle_n_per_chip:  Throttle value for
-//              cfg_nm_n_per_chip
-// @param[in]	uint32_t i_throttle_d:  Throttle value for cfg_nm_m
-// @param[out]  float &o_channel_pair_power:  channel pair power at these
-//              throttle settings
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_throttle_to_power_calc
-      (
-       const fapi::Target &i_target_mba,
-       uint32_t i_throttle_n_per_mba,
-       uint32_t i_throttle_n_per_chip,
-       uint32_t i_throttle_d,
-       float &o_channel_pair_power
-       )
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_throttle_to_power_calc ***");
-
-	const uint8_t MAX_NUM_PORTS = 2;
-	const uint8_t MAX_NUM_DIMMS = 2;
-
-	uint32_t l_power_slope_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	uint32_t l_power_int_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	uint8_t l_dimm_ranks_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	uint8_t l_port;
-	uint8_t l_dimm;
-	float l_dimm_power_array[MAX_NUM_PORTS][MAX_NUM_DIMMS];
-	float l_utilization;
-	float l_channel_power_array[MAX_NUM_PORTS];
-	uint32_t l_channel_power_array_integer[MAX_NUM_PORTS];
-	uint32_t l_channel_pair_power_integer;
-	float l_uplift;
-	uint8_t l_power_curve_percent_uplift;
-	uint8_t l_power_curve_percent_uplift_idle;
-	uint32_t l_max_dram_databus_util;
-	uint8_t num_mba_with_dimms;
-	uint8_t custom_dimm;
-	fapi::Target target_chip;
-	std::vector<fapi::Target> target_mba_array;
-	std::vector<fapi::Target> target_dimm_array;
-	uint8_t mba_index;
-	uint8_t l_utilization_idle = 0;
-
-
-// get input attributes
-	rc = FAPI_ATTR_GET(ATTR_MRW_MAX_DRAM_DATABUS_UTIL,
-			   NULL, l_max_dram_databus_util);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MAX_DRAM_DATABUS_UTIL");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT,
-			   NULL, l_power_curve_percent_uplift);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE,
-			   NULL, l_power_curve_percent_uplift_idle);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_DIMM_POWER_CURVE_PERCENT_UPLIFT_IDLE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_SLOPE,
-			   &i_target_mba, l_power_slope_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_SLOPE");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MSS_POWER_INT,
-			   &i_target_mba, l_power_int_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_POWER_INT");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM,
-			   &i_target_mba, l_dimm_ranks_array);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_NUM_RANKS_PER_DIMM");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, custom_dimm);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_EFF_CUSTOM_DIMM");
-	    return rc;
-	}
-
-// Maximum theoretical data bus utilization (percent of max) (for ceiling)
-// Comes from MRW value in c% - convert to %
-	float MAX_UTIL = (float) l_max_dram_databus_util / 100;
-
-// get number of mba's  with dimms for a CDIMM
-	if (custom_dimm == fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES)
-	{
-// Get Centaur target for the given MBA
-	    rc = fapiGetParentChip(i_target_mba, target_chip);
-	    if (rc) {
-		FAPI_ERR("Error calling fapiGetParentChip");
-		return rc;
-	    }
-// Get MBA targets from the parent chip centaur
-	    rc = fapiGetChildChiplets(target_chip,
-				      fapi::TARGET_TYPE_MBA_CHIPLET,
-				      target_mba_array,
-				      fapi::TARGET_STATE_PRESENT);
-	    if (rc) {
-		FAPI_ERR("Error calling fapiGetChildChiplets");
-		return rc;
-	    }
-	    num_mba_with_dimms = 0;
-	    for (mba_index=0; mba_index < target_mba_array.size(); mba_index++)
-	    {
-		rc = fapiGetAssociatedDimms(target_mba_array[mba_index],
-					    target_dimm_array,
-					    fapi::TARGET_STATE_PRESENT);
-		if (rc) {
-		    FAPI_ERR("Error calling fapiGetAssociatedDimms");
-		    return rc;
-		}
-		if (target_dimm_array.size() > 0)
-		{
-		    num_mba_with_dimms++;
-		}
-	    }
-
-	}
-	else
-	{
-// ISDIMMs, set to a value of one since they are handled on a per MBA basis
-	    num_mba_with_dimms = 1;
-	}
-
-// add up the power from all dimms for this MBA (across both channels) using the
-// throttle values
-	o_channel_pair_power = 0;
-	l_channel_pair_power_integer = 0;
-	for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
-	{
-	    l_channel_power_array[l_port] = 0;
-	    l_channel_power_array_integer[l_port] = 0;
-	    for (l_dimm=0; l_dimm < MAX_NUM_DIMMS; l_dimm++)
-	    {
-// default dimm power is zero (used for dimms that are not physically present)
-		l_dimm_power_array[l_port][l_dimm] = 0;
-		l_utilization = 0;
-// See if there are any ranks present on the dimm (configured or deconfigured)
-		if (l_dimm_ranks_array[l_port][l_dimm] > 0)
-		{
-// N/M throttling has the dimm0 and dimm1 throttles the same for DIMM level
-// throttling, which we plan to use
-// MBA or chip level throttling could limit the commands to a dimm (used along
-// with the dimm level throttling)
-// If MBA/chip throttle is less than dimm throttle, then use MBA/chip throttle
-// If MBA/chip throttle is greater than dimm throttle, then use the dimm
-// throttle
-// If either of these are above the MAX_UTIL, then use MAX_UTIL
-// Get power from each dimm here
-// Note that the MAX_UTIL effectively is the percent of maximum bandwidth for
-// that dimm
-
-		    if (i_throttle_d == 0)
-		    {
-// throttle denominator is zero (N/M throttling disabled), set dimm power to the
-// maximum
-			FAPI_DBG("N/M Throttling is disabled (M=0).  Use Max DIMM Power");
-			l_dimm_power_array[l_port][l_dimm] =
-			  (l_power_slope_array[l_port][l_dimm] *
-			   ((float)MAX_UTIL / 100) +
-			   l_power_int_array[l_port][l_dimm]);
-			l_utilization = (float)MAX_UTIL;
-		    }
-		    else if (
-			     (
-			      ((float)i_throttle_n_per_mba * 100 * 4) /
-			      i_throttle_d)
-			     >
-			     (((float)i_throttle_n_per_chip / num_mba_with_dimms * 100 * 4) /
-			      i_throttle_d)
-			     )
-		    {
-// limited by the mba/chip throttles (ie.  cfg_nm_n_per_chip)
-			if ((((float)i_throttle_n_per_chip / num_mba_with_dimms * 100 * 4) /
-			     i_throttle_d) > MAX_UTIL)
-			{
-// limited by the maximum utilization
-			    l_dimm_power_array[l_port][l_dimm] =
-			      (l_power_slope_array[l_port][l_dimm] *
-			       ((float)MAX_UTIL / 100) +
-			       l_power_int_array[l_port][l_dimm]);
-			    l_utilization = (float)MAX_UTIL;
-			}
-			else
-			{
-// limited by the per chip throttles
-			    l_dimm_power_array[l_port][l_dimm] =
-			      (l_power_slope_array[l_port][l_dimm] *
-			       (((float)i_throttle_n_per_chip / num_mba_with_dimms * 4)
-				/ i_throttle_d) +
-			       l_power_int_array[l_port][l_dimm]);
-			    l_utilization = (((float)i_throttle_n_per_chip / num_mba_with_dimms *
-					      100 * 4) / i_throttle_d);
-			}
-		    }
-		    else
-		    {
-// limited by the per mba throttles (ie.  cfg_nm_n_per_mba)
-			if ((((float)i_throttle_n_per_mba * 100 * 4) /
-			     i_throttle_d) > MAX_UTIL)
-			{
-// limited by the maximum utilization
-			    l_dimm_power_array[l_port][l_dimm] =
-			      (l_power_slope_array[l_port][l_dimm] *
-			       ((float)MAX_UTIL / 100) +
-			       l_power_int_array[l_port][l_dimm]);
-			    l_utilization = (float)MAX_UTIL;
-			}
-			else
-			{
-// limited by the per mba throttles
-// multiply by number of dimms on port since other dimm has same throttle value
-			    l_dimm_power_array[l_port][l_dimm] =
-			      (l_power_slope_array[l_port][l_dimm] *
-			       (((float)i_throttle_n_per_mba * 4) /
-				i_throttle_d) +
-			       l_power_int_array[l_port][l_dimm]);
-			    l_utilization =
-			      (((float)i_throttle_n_per_mba * 100 * 4) /
-			       i_throttle_d);
-			}
-		    }
-		}
-// Get dimm power in integer format (add on 1 since value will get truncated)
-// Include any system uplift here too
-		l_uplift = ( (l_power_curve_percent_uplift - l_power_curve_percent_uplift_idle) / (MAX_UTIL - l_utilization_idle) ) * l_utilization + l_power_curve_percent_uplift_idle;
-		if (l_dimm_power_array[l_port][l_dimm] > 0)
-		{
-		    l_dimm_power_array[l_port][l_dimm] =
-		      l_dimm_power_array[l_port][l_dimm]
-		      * (1 + l_uplift / 100);
-		}
-// calculate channel power by adding up the power of each dimm
-		l_channel_power_array[l_port] = l_channel_power_array[l_port] +
-		  l_dimm_power_array[l_port][l_dimm];
-		FAPI_DBG("[P%d:D%d][CH Util %4.2f/%4.2f][Slope:Int %d:%d][UpliftPercent %4.2f (min/max %d/%d)][Power %4.2f cW]", l_port, l_dimm, l_utilization, MAX_UTIL, l_power_slope_array[l_port][l_dimm], l_power_int_array[l_port][l_dimm], l_uplift, l_power_curve_percent_uplift_idle, l_power_curve_percent_uplift, l_dimm_power_array[l_port][l_dimm]);
-	    }
-	    FAPI_DBG("[P%d][Power %4.2f cW]", l_port, l_channel_power_array[l_port]);
-	}
-// get the channel pair power for this MBA (add on 1 since value will get
-// truncated)
-	for (l_port = 0; l_port < MAX_NUM_PORTS; l_port++)
-	{
-	    o_channel_pair_power = o_channel_pair_power +
-	      l_channel_power_array[l_port];
-	    if (l_channel_power_array_integer[l_port] > 0)
-	    {
-		l_channel_power_array_integer[l_port] =
-		  (int)l_channel_power_array[l_port] + 1;
-	    }
-	}
-	FAPI_DBG("Channel Pair Power %4.2f cW]", o_channel_pair_power);
-
-	if (o_channel_pair_power > 0)
-	{
-	    l_channel_pair_power_integer = (int)o_channel_pair_power + 1;
-	}
-//------------------------------------------------------------------------------
-// Update output attributes
-
-// Removed updating ATTR_MSS_DIMM_MAXPOWER for SW282712
-
-	rc = FAPI_ATTR_SET(ATTR_MSS_CHANNEL_PAIR_MAXPOWER,
-			   &i_target_mba, l_channel_pair_power_integer);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_CHANNEL_PAIR_MAXPOWER");
-	    return rc;
-	}
-
-	FAPI_INF("*** mss_throttle_to_power_calc COMPLETE ***");
-	return rc;
-    }
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
deleted file mode 100644
index e43ac2f2e..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H
+++ /dev/null
@@ -1,117 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_throttle_to_power.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_throttle_to_power.H,v 1.4 2012/12/12 20:10:50 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_throttle_to_power.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_throttle_to_power.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Joab Henderson    Email: joabhend@us.ibm.com
-// *! BACKUP NAME : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_throttle_to_power.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.4   | pardeik  |04-DEC-12| update lines to have a max width of 80 chars
-//         |          |         | removed variable names in typedef's
-//   1.3   | pardeik  |11-OCT-12| change i_target to i_target_mba
-//   1.2   | pardeik  |03-APR-12| use mba target instead of mbs
-//   1.1   | pardeik  |01-DEC-11| First Draft.
-
-
-
-#ifndef MSS_THROTTLE_TO_POWER_H_
-#define MSS_THROTTLE_TO_POWER_H_
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_throttle_to_power_FP_t)(const fapi::Target &);
-
-typedef fapi::ReturnCode (*mss_throttle_to_power_calc_FP_t)
-(
- const fapi::Target &,
- uint32_t,
- uint32_t,
- uint32_t,
- float &
- );
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// @brief mss_throttle_to_power(): This function will get the throttle
-// attributes and call another function to determine the dimm and channel pair
-// power based on those throttles
-//
-// @param[in]	const fapi::Target &i_target_mba:  MBA Target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_throttle_to_power(const fapi::Target & i_target_mba);
-
-//------------------------------------------------------------------------------
-// @brief mss_throttle_to_power_calc(): This function will calculate the dimm
-// and channel pair power and update attributes with the power values
-//
-// @param[in]   const fapi::Target &i_target_mba:  MBA Target
-// @param[in]   uint32_t i_throttle_n_per_mba:  Throttle value for
-//              cfg_nm_n_per_mba
-// @param[in]   uint32_t i_throttle_n_per_chip:  Throttle value for
-//              cfg_nm_n_per_chip
-// @param[in]   uint32_t i_throttle_d:  Throttle value for cfg_nm_m
-// @param[out]	float &o_channel_pair_power:  channel pair power at these
-//              throttle settings
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_throttle_to_power_calc
-      (
-       const fapi::Target &i_target_mba,
-       uint32_t i_throttle_n_per_mba,
-       uint32_t i_throttle_n_per_chip,
-       uint32_t i_throttle_d,
-       float &channel_pair_power
-       );
-
-} // extern "C"
-
-#endif // MSS_THROTTLE_TO_POWER_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.C
deleted file mode 100755
index 7b6102c43..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.C
+++ /dev/null
@@ -1,138 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_util_to_throttle.C,v 1.7 2014/11/06 21:07:06 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_util_to_throttle.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_util_to_throttle
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Mark Bellows Email:  bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// applicable CQ component memory_screen
-//
-// DESCRIPTION:
-// The purpose of this procedure is to set the N throttle attributes for a
-// given dram data bus utilization.  TMGT will call this to determine a
-// minimum N_MBA setting for the minimum MBA utilization allowed for that system
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.7    | pardeik  |06-NOV-14| removed string in trace statement
-//         |          |         | changed FAPI_IMP to FAPI_INF
-//  1.6    | pardeik  |11-FEB-14| RAS review fix:  change %% to percent
-//  1.5    | pardeik  |13-JAN-14| Fixed calculation to not include x2 factor for
-//         |          |         |  other MBA for custom DIMMs
-//  1.4    | pardeik  |06-JAN-14| Use ATTR_MRW_MEM_THROTTLE_DENOMINATOR instead
-//         |          |         |  of ATTR_MRW_SAFEMODE_MEM_THROTTLE_DENOMINATOR
-//  1.3    | pardeik  |07-NOV-13| gerrit review updates
-//  1.2    | pardeik  |07-NOV-13| gerrit review updates
-//  1.1    | pardeik  |06-OCT-13| First Draft.
-
-
-//------------------------------------------------------------------------------
-//  My Includes
-//------------------------------------------------------------------------------
-#include <mss_util_to_throttle.H>
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-extern "C" {
-
-    using namespace fapi;
-
-
-//------------------------------------------------------------------------------
-// @brief mss_util_to_throttle(): This function will determine the minimum
-// N throttle settings for N/M throttling given a dram data bus utilization
-//
-// @param[in]	const fapi::Target &i_target_mba:  MBA Target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_util_to_throttle(const fapi::Target & i_target_mba)
-    {
-	fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-
-	FAPI_INF("*** Running mss_util_to_throttle ***");
-
-	uint32_t throttle_d;
-	uint8_t data_bus_util;
-	uint32_t min_throttle_n_per_mba;
-
-// Get input attributes
-	rc = FAPI_ATTR_GET(ATTR_MSS_DATABUS_UTIL_PER_MBA,
-			   &i_target_mba, data_bus_util);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MSS_DATABUS_UTIL_PER_MBA");
-	    return rc;
-	}
-	rc = FAPI_ATTR_GET(ATTR_MRW_MEM_THROTTLE_DENOMINATOR,
-			   NULL, throttle_d);
-	if (rc) {
-	    FAPI_ERR("Error getting attribute ATTR_MRW_MEM_THROTTLE_DENOMINATOR");
-	    return rc;
-	}
-
-// Calculate out the minimum N_MBA throttle number for the given utilization
-//   Uses N/M Throttling.   Equation:  (DRAM data bus utilization Percent / 100 ) = ((N * 4) / M)
-//   The 4 is a constant since dram data bus utilization is 4X the address bus utilization
-//   Add one since integer will truncate floating point number, so we we do not end up with a
-//   lower than intended setting
-	min_throttle_n_per_mba =((data_bus_util * throttle_d) / 4 / 100) + 1;
-	FAPI_INF("MIN N_MBA Throttle for %d percent DRAM data bus util = %d", data_bus_util, min_throttle_n_per_mba);
-
-
-// Update output attributes
-	rc = FAPI_ATTR_SET(ATTR_MSS_UTIL_N_PER_MBA,
-			   &i_target_mba, min_throttle_n_per_mba);
-	if (rc) {
-	    FAPI_ERR("Error writing attribute ATTR_MSS_UTIL_N_PER_MBA");
-	    return rc;
-	}
-
-	FAPI_INF("*** mss_util_to_throttle COMPLETE ***");
-	return rc;
-
-    }
-
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.H
deleted file mode 100755
index 691e56e5e..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.H
+++ /dev/null
@@ -1,76 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/mss_util_to_throttle.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_util_to_throttle.H,v 1.2 2013/11/07 20:39:38 pardeik Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/
-//          centaur/working/procedures/ipl/fapi/mss_util_to_throttle.H,v $
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_util_to_throttle.H
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Mark Bellows Email:  bellows@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// Header file for mss_util_to_throttle.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.2   | pardeik  |07-NOV-13| gerrit review updates
-//   1.1   | pardeik  |06-OCT-13| First Draft.
-
-
-
-#ifndef MSS_UTIL_TO_THROTTLE_H_
-#define MSS_UTIL_TO_THROTTLE_H_
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*mss_util_to_throttle_FP_t)(const fapi::Target &);
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// @brief mss_util_to_throttle(): This function will determine the minimum
-// N throttle settings for N/M throttling given a dram data bus utilization
-// and update the attribute ATTR_MSS_UTIL_N_PER_MBA with the result
-//
-// @param[in]	const fapi::Target &i_target_mba:  MBA Target
-//
-// @return fapi::ReturnCode
-//------------------------------------------------------------------------------
-
-    fapi::ReturnCode mss_util_to_throttle(const fapi::Target & i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_UTIL_TO_THROTTLE_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C
deleted file mode 100644
index b7b170db3..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C
+++ /dev/null
@@ -1,865 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.C $      */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: opt_memmap.C,v 1.21 2015/01/23 01:54:26 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/opt_memmap.C,v $
-
-
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : opt_memmap.C
-// *! DESCRIPTION : Layout non-mirrored/mirrored address map (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Design flow:
-//
-// opt_memmap() interacts with mss_eff_grouping() to define the assignment
-// of non-mirrored/mirrored real address space on each chip in the drawer:
-// - mss_eff_grouping() is responsible for the address assignment/layout
-//   of regions on a chip basis
-// - opt_memmap() determines the final position of each chip's address
-//   space within the drawer
-// 
-// Sequence:
-//
-// opt_memmap() will be called twice in the IPL flow, once before and once
-// after mss_eff_grouping().  
-//
-// 1) Call opt_memmap() with i_init = true
-//
-//    opt_memmap() writes ATTR_PROC_[MEM|MIRROR]_BASE attributes to
-//    provide a basis for mss_eff_grouping() to stack all on-chip
-//    groups.  Initially all chips are set to common values to provide
-//    a simple basis for size comparison.
-//
-//                                          non-mirrored              mirrored
-//         mirror       eff. stacking        stacking                 stacking
-//         policy       sort criteria         origin                   origin
-//        --------      -------------   ---------------------  -----------------------
-//         NORMAL            nm                0 TB                    X TB
-//         DRAWER            nm           32 TB * drawer       X TB+(32 TB * drawer)/2
-//         FLIPPED           m                 X TB                    0 TB
-//      FLIPPED_DRAWER       m          X TB+(32 TB * drawer)      32TB * drawer
-//    
-// 2) mss_eff_grouping() call
-//    - The HWP updates each proc's ATTR_PROC_[MEM|MIRROR]_[BASES|SIZES]
-//      attributes based on the address regions allocated for installed memory
-//      behind each proc
-//    - ATTR_PROC_[MEM|MIRROR]_[BASES|SIZES]_ACK are updated to reflect
-//      the stackable size of each on chip memory region
-//
-// 3) Call opt_memmap() with i_init = false
-//    - Consume mss_eff_grouping() *_ACK attributes for each proc to determine
-//      "effective stackable" size of non-mirrored/mirrored regions
-//      on each proc
-//    - Stack procs based on their effective size and desired placement
-//      policy
-//    - Write ATTR_PROC_[MEM|MIRROR]_BASE attributes to their final
-//      value
-//
-// 4) mss_eff_grouping() call
-//    - Second run will produce properly aligned output attributes based
-//      on final per-chip base address attributes determined in prior step
-//
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-
-#include <opt_memmap.H>
-#include <algorithm>
-
-//------------------------------------------------------------------------------
-//  Constant definitions
-//------------------------------------------------------------------------------
-
-extern "C" {
-
-using namespace fapi;
-
-
-//------------------------------------------------------------------------------
-//  Function definitions
-//------------------------------------------------------------------------------
-
-
-// class to represent memory region
-class MemRegion
-{
-public:
-    // region type (mirrored/non-mirrored)
-    enum type { nm = 0, m = 1 };
-
-    // constructors
-    MemRegion(MemRegion::type type) :
-        iv_group_type(type), iv_base(0), iv_size(0) {}
-
-    MemRegion(MemRegion::type type, uint64_t base, uint64_t size) :
-        iv_group_type(type), iv_base(base), iv_size(size) {}
-
-    // comparison operators for sorting
-    bool operator < (MemRegion rhs) const
-    {
-        bool l_lt = true;
-        if (iv_base > rhs.iv_base ||
-            ((iv_base == rhs.iv_base) && (iv_size > rhs.iv_size)))
-        {
-            l_lt = false;
-        }
-        return l_lt;
-    }
-
-    bool operator == (MemRegion rhs) const
-    {
-        return((iv_base == rhs.iv_base) &&
-               (iv_size == rhs.iv_size));
-    }
-
-    bool operator > (MemRegion rhs) const
-    {
-        return (!(*this == rhs) && !(*this < rhs));
-    }
-
-    uint64_t getBase() const { return iv_base; }
-    uint64_t getSize() const { return iv_size; }
-    void setBase(uint64_t base) { iv_base = base; }
-    void setSize(uint64_t size) { iv_size = size; }
-
-    // determine if region size is power of 2 aligned
-    bool isPowerOf2() const
-    {
-        return ((iv_size != 0) && !(iv_size & (iv_size - 1)));
-    }
-
-    // round region size to next largest power of 2
-    void roundNextPowerOf2()
-    {
-        iv_size = iv_size - 1;
-        iv_size = iv_size | (iv_size >> 1);
-        iv_size = iv_size | (iv_size >> 2);
-        iv_size = iv_size | (iv_size >> 4);
-        iv_size = iv_size | (iv_size >> 8);
-        iv_size = iv_size | (iv_size >> 16);
-        iv_size = iv_size | (iv_size >> 32);
-        iv_size = iv_size + 1;
-    }
-
-    // debug function
-    void dump() const
-    {
-        FAPI_DBG("Region [ %s ]", (iv_group_type == nm)?("nm"):("m"));
-        FAPI_DBG("  Base: 0x%016llX", iv_base);
-        FAPI_DBG("  Size: 0x%016llX", iv_size);
-    }
-
-private:
-    // region type
-    type iv_group_type;
-
-    // region parameters
-    uint64_t iv_base;
-    uint64_t iv_size;
-
-};
-
-
-// class to represent memory map (non-mirrored/mirrored regions) on one processor chip
-class ProcChipMemmap
-{
-public:
-    // constructor
-    ProcChipMemmap(Target* t, MemRegion::type sort, bool chip_as_group) :
-        iv_target(t), iv_sort(sort), iv_chip_as_group(chip_as_group), iv_node_id(0), iv_chip_id(0), iv_nm(MemRegion::nm), iv_m(MemRegion::m) {}
-
-    // comparison operator for sort
-    // sort in increasing effective size, and decreasing proc position
-    // e.g. proc0 and proc2 have same size, then the order will be
-    // proc2 then proc0
-    bool operator < (ProcChipMemmap rhs) const
-    {
-        uint8_t l_pos = ((4*iv_node_id)+iv_chip_id);
-        uint8_t r_pos = ((4*rhs.iv_node_id)+rhs.iv_chip_id);
-
-        bool l_lt = true;
-        // perform sort comparison
-        MemRegion l = ((iv_sort == MemRegion::nm)?(iv_nm):(iv_m));
-        MemRegion r = ((iv_sort == MemRegion::nm)?(rhs.iv_nm):(rhs.iv_m));
-        if ((l > r) ||
-            ((l == r) && (l_pos < r_pos)))
-        {
-            l_lt = false;
-        }
-        return l_lt;
-    }
-
-    // process chip data from attributes
-    ReturnCode processAttributes()
-    {
-        ReturnCode rc;
-        uint64_t l_nm_base;
-        uint64_t l_m_base;
-        uint64_t l_nm_bases[OPT_MEMMAP_MAX_NM_REGIONS] = { 0 };
-        uint64_t l_nm_sizes[OPT_MEMMAP_MAX_NM_REGIONS] = { 0 };
-        uint64_t l_m_bases[OPT_MEMMAP_MAX_M_REGIONS] = { 0 };
-        uint64_t l_m_sizes[OPT_MEMMAP_MAX_M_REGIONS] = { 0 };
-        std::vector<MemRegion> l_nm_regions;
-        std::vector<MemRegion> l_m_regions;
-
-        do
-        {
-            // obtain node/chip ID
-            rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID,
-                               iv_target,
-                               iv_node_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_FABRIC_NODE)");
-                break;
-            }
-
-            rc = FAPI_ATTR_GET(ATTR_FABRIC_CHIP_ID,
-                               iv_target,
-                               iv_chip_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_FABRIC_CHIP)");
-                break;
-            }
-
-            // retrieve base address attributes (computed by prior opt_memmap call)
-            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASE,
-                               iv_target,
-                               l_nm_base);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASE)");
-                break;
-            }
-            iv_nm.setBase(l_nm_base);
-
-            rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASE,
-                               iv_target,
-                               l_m_base);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASE)");
-                break;
-            }
-            iv_m.setBase(l_m_base);
-
-            // retrieve regions (bases and sizes) computed by mss_eff_grouping
-            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_BASES_ACK,
-                               iv_target,
-                               l_nm_bases);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_BASES_ACK)");
-                break;
-            }
-            
-            rc = FAPI_ATTR_GET(ATTR_PROC_MEM_SIZES_ACK,
-                               iv_target,
-                               l_nm_sizes);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MEM_SIZES_ACK)");
-                break;
-            }
-            rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_BASES_ACK,
-                               iv_target,
-                               l_m_bases);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_BASES_ACK)");
-                break;
-            }
-            
-            rc = FAPI_ATTR_GET(ATTR_PROC_MIRROR_SIZES_ACK,
-                               iv_target,
-                               l_m_sizes);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_PROC_MIRROR_SIZES_ACK)");
-                break;
-            }
-
-            // populate non-mirrored regions
-            FAPI_INF("Process Chip n%d:p%d: Begin", iv_node_id, iv_chip_id);
-            for (uint8_t i = 0; i < OPT_MEMMAP_MAX_NM_REGIONS; i++)
-            {
-                if (l_nm_sizes[i] != 0)
-                {
-                    FAPI_INF("  nm_bases[%d] = 0x%016llX", i, l_nm_bases[i]);
-                    FAPI_INF("  nm_sizes[%d] = 0x%016llX", i, l_nm_sizes[i]);
-                    MemRegion r(MemRegion::nm, l_nm_bases[i], l_nm_sizes[i]);
-                    l_nm_regions.push_back(r);
-                }
-            }
-
-            // populate mirrored regions
-            for (uint8_t i = 0; i < OPT_MEMMAP_MAX_M_REGIONS; i++)
-            {
-                if (l_m_sizes[i] != 0)
-                {
-                    // align to common origin
-                    FAPI_INF("   m_bases[%d] = 0x%016llX", i, l_m_bases[i]);
-                    FAPI_INF("   m_sizes[%d] = 0x%016llX", i, l_m_sizes[i]);
-                    MemRegion r(MemRegion::m, l_m_bases[i], l_m_sizes[i]);
-                    l_m_regions.push_back(r);
-                }
-            }
-
-            // sort regions for effective size calculations
-            std::sort(l_nm_regions.begin(), l_nm_regions.end());
-            std::sort(l_m_regions.begin(), l_m_regions.end());
-
-            // compute effective size of chip address space associated with
-            // each stack (rounded up to a power of 2)
-            if (l_nm_regions.size() != 0)
-            {
-//                if (iv_nm.getBase() != l_nm_regions[0].getBase())
-//                {
-//                    const uint64_t& ADDR = iv_nm.getBase();
-//                    FAPI_ERR("Unexpected value returned for ATTR_PROC_MEM_BASE (='0x%016llX')",
-//                             iv_nm.getBase());
-//                    FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MEM_BASE_ERR);
-//                    break;
-//                }
-
-                iv_nm.setSize(l_nm_regions[l_nm_regions.size()-1].getBase() -
-                              l_nm_regions[0].getBase() +
-                              l_nm_regions[l_nm_regions.size()-1].getSize());
-                if (!iv_nm.isPowerOf2())
-                {
-                    iv_nm.roundNextPowerOf2();
-                }
-            }
-            else
-            {
-                iv_nm.setSize(0);
-            }
-            FAPI_INF("  nm_eff_size = 0x%016llX", iv_nm.getSize());
-
-            if (l_m_regions.size() != 0)
-            {
-//                if (iv_m.getBase() != l_m_regions[0].getBase())
-//                {
-//                    const uint64_t& ADDR = iv_m.getBase();
-//                    FAPI_ERR("Unexpected value returned for ATTR_PROC_MIRROR_BASE (='0x%016llX')",
-//                             iv_m.getBase());
-//                    FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_MIRROR_BASE_ERR);
-//                    break;
-//                }
-
-                iv_m.setSize(l_m_regions[l_m_regions.size()-1].getBase() -
-                             l_m_regions[0].getBase() +
-                             l_m_regions[l_m_regions.size()-1].getSize());
-                if (!iv_m.isPowerOf2())
-                {
-                    iv_m.roundNextPowerOf2();
-                }
-            }
-            else
-            {
-                iv_m.setSize(0);
-            }
-            FAPI_INF("   m_eff_size = 0x%016llX", iv_m.getSize());
-            FAPI_INF("Process Chip: End");
-
-        } while(0);
-
-        return rc;
-    }
-
-    // return group ID
-    uint8_t getGroupID() const
-    {
-        uint8_t pos = ((4*iv_node_id)+iv_chip_id);
-        return((iv_chip_as_group)?(pos):(iv_node_id));
-    }
-
-    // return specified region size
-    uint64_t getSize(const MemRegion::type type) const
-    {
-        return((type == MemRegion::nm)?(iv_nm.getSize()):(iv_m.getSize()));
-    }
-
-    // establish new base address for this chip
-    void setBase(const MemRegion::type type, const uint64_t& base)
-    {
-        if (type == MemRegion::nm)
-        {
-            iv_nm.setBase(base);
-        }
-        else
-        {
-            iv_m.setBase(base);
-        }
-    }
-
-    // flush state back to attributes
-    ReturnCode flushAttributes()
-    {
-        ReturnCode rc;
-        uint64_t nm_base = iv_nm.getBase();
-        uint64_t m_base = iv_m.getBase();
-
-        FAPI_INF("Stack Chip n%d:p%d: Begin", iv_node_id, iv_chip_id);
-        FAPI_INF("  nm_base: 0x%016llX", nm_base);
-        FAPI_INF("   m_base: 0x%016llX", m_base);
-        do
-        {
-            // set base addresses
-            rc = FAPI_ATTR_SET(ATTR_PROC_MEM_BASE,
-                               iv_target,
-                               nm_base);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MEM_BASE)");
-                break;
-            }
-
-            rc = FAPI_ATTR_SET(ATTR_PROC_MIRROR_BASE,
-                               iv_target,
-                               m_base);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_SET (ATTR_PROC_MIRROR_BASE)");
-                break;
-            }
-
-        } while(0);
-        FAPI_INF("Stack Chip: End");
-        return rc;
-    }
-
-private:
-    // pointer to processor chip target
-    Target *iv_target;
-    // sort criteria
-    MemRegion::type iv_sort;
-    // chip position information
-    bool iv_chip_as_group;
-    uint8_t iv_node_id;
-    uint8_t iv_chip_id;
-    // chip effective non-mirrored region
-    MemRegion iv_nm;
-    // chip effective mirrored region
-    MemRegion iv_m;
-};
-
-
-// class to represent group in drawer memory map
-class ProcGroupMemmap
-{
-public:
-    // constructor
-    ProcGroupMemmap(uint8_t group_id, uint8_t mirror_policy, MemRegion::type sort) :
-        iv_group_id(group_id), iv_mirror_policy(mirror_policy), iv_sort(sort), iv_nm(MemRegion::nm), iv_m(MemRegion::m) {}
-
-    // comparison operator for sort
-    // sort in increasing size, and decreasing node ID
-    // e.g. group2 and group0 have same size, then the order will be
-    // group2 then group0
-    bool operator < (const ProcGroupMemmap & rhs) const
-    {
-        bool l_lt = true;
-        // perform sort comparison
-        MemRegion l = ((iv_sort == MemRegion::nm)?(iv_nm):(iv_m));
-        MemRegion r = ((iv_sort == MemRegion::nm)?(rhs.iv_nm):(rhs.iv_m));
-        if ((l > r) ||
-            ((l == r) && (iv_group_id < rhs.iv_group_id)))
-        {
-            l_lt = false;
-        }
-        return l_lt;
-    }
-
-    // retreive group ID
-    uint8_t getGroupID() const { return iv_group_id; }
-
-    // add chip to group
-    void addChip(const ProcChipMemmap & chip)
-    {
-        iv_nm.setSize(iv_nm.getSize() + chip.getSize(MemRegion::nm));
-        iv_m.setSize(iv_m.getSize() + chip.getSize(MemRegion::m));
-        iv_chips.push_back(chip);
-    }
-    
-    // finalize effective group size
-    void processGroup()
-    {
-        FAPI_INF("Process Group %d: Begin", iv_group_id);
-        // sort member chips based on their effective stackable sizes
-        // individual chip sizes should already be power-of-2 aligned
-        std::sort(iv_chips.begin(), iv_chips.end());
-
-        // ensure size is rounded to power-of-2
-        if (!iv_nm.isPowerOf2())
-        {
-            iv_nm.roundNextPowerOf2();
-        }
-        if (!iv_m.isPowerOf2())
-        {
-            iv_m.roundNextPowerOf2();
-        }
-        FAPI_INF("  nm_eff_size = 0x%016llX", iv_nm.getSize());
-        FAPI_INF("   m_eff_size = 0x%016llX", iv_m.getSize());
-        FAPI_INF("Process Group: End");
-    }
-
-    // return specified region size
-    uint64_t getSize(const MemRegion::type type) const
-    {
-        return((type == MemRegion::nm)?(iv_nm.getSize()):(iv_m.getSize()));
-    }
-
-    // walk through member chips, from largest->smallest effective size
-    // assign base addresses for each
-    ReturnCode stackChips(uint64_t nm_base, uint64_t m_base)
-    {
-        ReturnCode rc;
-        uint64_t l_nm_base_curr = nm_base;
-        uint64_t l_m_base_curr = m_base;
-
-        iv_nm.setBase(nm_base);
-        iv_m.setBase(m_base);
-
-        FAPI_INF("Stack Group %d: Begin", iv_group_id);
-        for (uint8_t i = iv_chips.size();
-             i != 0;
-             --i)
-        {
-            // establish base addresses for each chip & realign
-            // all groups on this chip to reflect this
-            iv_chips[i-1].setBase(MemRegion::nm, l_nm_base_curr);
-            iv_chips[i-1].setBase(MemRegion::m, l_m_base_curr);
-            l_nm_base_curr += iv_chips[i-1].getSize(MemRegion::nm);
-
-            if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) ||
-                (iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_DRAWER))
-            {
-                l_m_base_curr += iv_chips[i-1].getSize(MemRegion::nm) / 2;
-            }
-            else
-            {
-                l_m_base_curr += iv_chips[i-1].getSize(MemRegion::m);
-            }
-
-            // flush attributes for this chip
-            rc = iv_chips[i-1].flushAttributes();
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from flushAttributes");
-                break;
-            }
-        }
-
-        FAPI_INF("Stack Group: End");
-        return rc;
-    }
-
-private:
-    // collection of member chips
-    std::vector<ProcChipMemmap> iv_chips;
-    // group ID
-    uint8_t iv_group_id;
-    // mirroring policy/sort criteria
-    uint8_t iv_mirror_policy;
-    MemRegion::type iv_sort;
-    // effective sizes
-    MemRegion iv_nm;
-    MemRegion iv_m;
-
-};
-
-
-// class to represent memory map at drawer scope
-class ProcDrawerMemmap
-{
-
-public:
-    // constructor
-    ProcDrawerMemmap(uint8_t mirror_policy, uint8_t group_policy, uint64_t alt_origin, uint8_t drawer_id) :
-        iv_mirror_policy(mirror_policy), iv_group_policy(group_policy), iv_alt_origin(alt_origin), iv_drawer_id(drawer_id)
-    {
-        // establish base address values based on memory map policy
-        if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) ||
-            (iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_DRAWER))
-        {
-            iv_sort_policy = MemRegion::nm;
-            iv_nm_base = OPT_MEMMAP_BASE_ORIGIN + (iv_drawer_id * 32 * OPT_MEMMAP_TB);
-            iv_m_base = iv_alt_origin + (iv_nm_base / 2);
-        }
-        else if ((iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED) ||
-                 (iv_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED_DRAWER))
-        {
-            iv_sort_policy = MemRegion::m;
-            iv_m_base = OPT_MEMMAP_BASE_ORIGIN + (iv_drawer_id * 32 * OPT_MEMMAP_TB);
-            iv_nm_base = iv_alt_origin + iv_m_base;
-
-        }
-    }
-
-    // return drawer sort/ordering policies
-    MemRegion::type getSortPolicy() const { return iv_sort_policy; }
-    bool getGroupPolicy() const { return (iv_group_policy == ENUM_ATTR_OPT_MEMMAP_GROUP_POLICY_CHIP_AS_GROUP); }
-
-    uint64_t getBase(MemRegion::type type)
-    {
-        if (type == MemRegion::nm) { return iv_nm_base; }
-        else { return iv_m_base; }
-    }
-
-    // chip processing function
-    ReturnCode insertChip(ProcChipMemmap chip)
-    {
-        ReturnCode rc;
-
-        // search for matching group
-        uint8_t group_match_count = 0;
-        for (std::vector<ProcGroupMemmap>::iterator g = iv_groups.begin();
-             g != iv_groups.end();
-             g++)
-        {
-            // add to existing group
-            if (chip.getGroupID() == g->getGroupID())
-            {
-                g->addChip(chip);
-                group_match_count++;
-            }
-        }
-        // create group if no matches found
-        if (group_match_count == 0)
-        {
-            ProcGroupMemmap new_group(chip.getGroupID(), iv_mirror_policy, iv_sort_policy);
-            new_group.addChip(chip);
-            iv_groups.push_back(new_group);
-        }
-        // multiple group matches were found, error
-        else if (group_match_count != 1)
-        {
-            const uint8_t& GROUP_ID = chip.getGroupID();
-            const uint8_t& MATCH_COUNT = group_match_count;
-            FAPI_ERR("Internal error, chip matched multiple group IDs (=%d)",
-                     chip.getGroupID());
-            FAPI_SET_HWP_ERROR(rc, RC_OPT_MEMMAP_GROUP_ERR);
-        }
-        return rc;
-    }
-
-    // drawer processing function
-    ReturnCode processDrawer()
-    {
-        ReturnCode rc;
-        FAPI_INF("Process Drawer: Begin");
-
-        // determine effective size of each group
-        for (std::vector<ProcGroupMemmap>::iterator g = iv_groups.begin();
-             g != iv_groups.end();
-             g++)
-        {
-            g->processGroup();
-        }
-
-        // order groups by effective size
-        std::sort(iv_groups.begin(), iv_groups.end());
-
-        FAPI_INF("Stack Drawer: Begin");
-        // walk through groups, from largest->smallest effective size
-        for (uint8_t i = iv_groups.size();
-             i != 0;
-             --i)
-        {
-            // establish base addresses for group
-            rc = iv_groups[i-1].stackChips(iv_nm_base, iv_m_base);
-            if (!rc.ok())
-            {
-                break;
-            }
-
-            // establish base addresses for next group
-            iv_nm_base += iv_groups[i-1].getSize(MemRegion::nm);
-            if ((iv_mirror_policy ==
-                 ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_NORMAL) ||
-                (iv_mirror_policy ==
-                 ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_DRAWER))
-            {
-                iv_m_base += iv_groups[i-1].getSize(MemRegion::nm) / 2;
-            }
-            else
-            {
-                iv_m_base += iv_groups[i-1].getSize(MemRegion::m);
-            }
-        }
-
-        FAPI_INF("Stack Drawer: End");
-        FAPI_INF("Process Drawer: End");
-        return rc;
-    }
-
-private:
-    // collection of member groups
-    std::vector<ProcGroupMemmap> iv_groups;
-
-    // mirror policy
-    uint8_t iv_mirror_policy;
-    uint8_t iv_group_policy;
-    MemRegion::type iv_sort_policy;
-    uint64_t iv_alt_origin;
-    uint8_t iv_drawer_id;
-
-    // current base address values
-    uint64_t iv_nm_base;
-    uint64_t iv_m_base;
-
-};
-
-
-// HWP entry point
-ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init)
-{
-    ReturnCode rc;
-    uint8_t l_mirror_policy;
-    uint8_t l_group_policy;
-    uint64_t l_alt_origin;
-    uint8_t l_drawer_id = 0;
-
-    do
-    {
-        // retrieve mirroring policy/placement attributes
-        rc = FAPI_ATTR_GET(ATTR_MEM_MIRROR_PLACEMENT_POLICY,
-                           NULL,
-                           l_mirror_policy);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying ATTR_MEM_MIRROR_PLACEMENT_POLICY");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_OPT_MEMMAP_GROUP_POLICY,
-                           NULL,
-                           l_group_policy);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying ATTR_OPT_MEMMAP_GROUP_POLICY");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_MIRROR_BASE_ADDRESS,
-                           NULL,
-                           l_alt_origin);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying ATTR_MIRROR_BASE_ADDRESS");
-            break;
-        }
-
-        // all chips in input vector must lie in same drawer
-        // if required by placement policy, determine drawer number
-        // (equivalent to the fabric node ID)
-        if ((l_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_DRAWER) ||
-            (l_mirror_policy == ENUM_ATTR_MEM_MIRROR_PLACEMENT_POLICY_FLIPPED_DRAWER))
-        {
-            rc = FAPI_ATTR_GET(ATTR_FABRIC_NODE_ID,
-                               &(*(i_procs.begin())),
-                               l_drawer_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from FAPI_ATTR_GET (ATTR_FABRIC_NODE_ID)");
-                break;
-            }
-        }
-
-        FAPI_INF("opt_memmap called with i_init: %d, mirror_policy: %d, group_policy: %d, alternate_origin: 0x%016llX",
-                 (i_init)?(1):(0), l_mirror_policy, l_group_policy, l_alt_origin);
-
-        // construct drawer memory map object
-        ProcDrawerMemmap l_drawer(l_mirror_policy, l_group_policy, l_alt_origin, l_drawer_id);
-
-        // process all chips in scope of drawer
-        for (std::vector<fapi::Target>::iterator l_iter = i_procs.begin();
-             l_iter != i_procs.end();
-             l_iter++)
-        {
-            ProcChipMemmap l_chip(&(*l_iter), l_drawer.getSortPolicy(), l_drawer.getGroupPolicy());
-
-            if (i_init)
-            {
-                l_chip.setBase(MemRegion::nm, l_drawer.getBase(MemRegion::nm));
-                l_chip.setBase(MemRegion::m, l_drawer.getBase(MemRegion::m));
-                rc = l_chip.flushAttributes();
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from flushAttributes");
-                    break;
-                }
-            }
-            else
-            {
-                rc = l_chip.processAttributes();
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from processAttributes");
-                    break;
-                }
-                rc = l_drawer.insertChip(l_chip);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from insertChip");
-                    break;
-                }
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-        // process drawer to align each group & its member chips
-        if (!i_init)
-        {
-            rc = l_drawer.processDrawer();
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from processDrawer");
-                break;
-            }
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-} //end extern C
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H b/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H
deleted file mode 100644
index 37a56ff71..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H
+++ /dev/null
@@ -1,108 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_config/opt_memmap.H $      */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: opt_memmap.H,v 1.9 2014/06/19 14:06:35 dcrowell Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/opt_memmap.H,v $      */
-
-
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : opt_memmap.H
-// *! DESCRIPTION : Layout non-mirrored/mirrored address map (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : ???           Email: ???@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//  1.9    | dcrowell | 06/19/14| Remove OPT_MEMMAP_OFFSET_ORIGIN
-//  1.7    | jmcgill  | 07/10/13| Update to match new attributes, selective
-//         |          |         | aligment policy changes
-//  1.6    | jmcgill  | 05/24/13| Correct index name
-//  1.5    | jmcgill  | 05/23/13| Address FW review issues
-//  1.4    | jmcgill  | 04/28/13| Shift constant definitions
-//  1.3    | vanlee   | 02/20/13| Added i_init parameter
-//  1.2    | vanlee   | 01/04/13| Added version string
-//  1.1    | vanlee   | 12/01/12| Initial version
-
-#ifndef MSS_OPT_MEMMAP_H_
-#define MSS_OPT_MEMMAP_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// conversion factor definitions
-const uint64_t OPT_MEMMAP_GB = 0x0000000040000000ULL;
-const uint64_t OPT_MEMMAP_TB = 0x0000010000000000ULL;
-
-// default origin for non-mirrored/mirrored address regions
-const uint64_t OPT_MEMMAP_BASE_ORIGIN      = 0;                     // 0
-const uint64_t OPT_MEMMAP_SELECTIVE_ORIGIN = 0x0000080000000000LL;  // 8TB
-
-// maximum non-mirrored/mirrored regions supported
-const uint8_t OPT_MEMMAP_MAX_NM_REGIONS = 8;
-const uint8_t OPT_MEMMAP_MAX_M_REGIONS  = 4;
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*opt_memmap_FP_t)(std::vector<fapi::Target> & i_procs,
-                                            bool i_init);
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// i_init = true  : initialize all ATTR_PROC_MEM_BASE attributes to 0
-//        = false : perform memory map optimization
-fapi::ReturnCode opt_memmap(std::vector<fapi::Target> & i_procs, bool i_init);
-
-
-} // extern "C"
-
-#endif // MSS_OPT_MEMMAP_H_
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.C b/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.C
deleted file mode 100644
index 8625b5068..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.C
+++ /dev/null
@@ -1,159 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_pre_config.C,v 1.1 2013/08/06 23:30:21 asaetow Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_pre_config.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_pre_config
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-// This procedure puts in required attributes for mss_eff_config_thermal which are based on "worst case" config in case these attributes were not able to be setup by mss_eff_config.
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.2   |          |         |
-//   1.1   | asaetow  |02-AUG-13| First Draft.
-
-
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-
-//----------------------------------------------------------------------
-// ENUMs
-//----------------------------------------------------------------------
-
-
-
-extern "C" {
-
-
-
-//******************************************************************************
-//* name=mss_eff_pre_config, param=i_target_mba, return=ReturnCode
-//******************************************************************************
-fapi::ReturnCode mss_eff_pre_config(const fapi::Target i_target_mba) {
-   fapi::ReturnCode rc = fapi::FAPI_RC_SUCCESS;
-   const char * const PROCEDURE_NAME = "mss_eff_pre_config";
-   FAPI_INF("*** Running %s on %s ... ***", PROCEDURE_NAME, i_target_mba.toEcmdString());
-
-   
-   const uint32_t MSS_EFF_EMPTY = 0;
-   const uint32_t MSS_EFF_VALID = 255;
-   const uint8_t PORT_SIZE = 2;
-   const uint8_t DIMM_SIZE = 2;
-
-   // Grab DIMM/SPD data.
-   uint8_t cur_dimm_spd_valid_u8array[PORT_SIZE][DIMM_SIZE]; 
-   uint8_t spd_custom[PORT_SIZE][DIMM_SIZE];
-   for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) {
-      for (uint8_t cur_dimm = 0; cur_dimm < DIMM_SIZE; cur_dimm += 1) {
-         cur_dimm_spd_valid_u8array[cur_port][cur_dimm] = MSS_EFF_EMPTY;
-         spd_custom[cur_port][cur_dimm] = 0;
-      }
-   }
-   uint8_t cur_mba_port = 0;
-   uint8_t cur_mba_dimm = 0;
-   std::vector<fapi::Target> l_target_dimm_array;
-   rc = fapiGetAssociatedDimms(i_target_mba, l_target_dimm_array); if(rc) return rc;
-   for (uint8_t dimm_index = 0; dimm_index < l_target_dimm_array.size(); dimm_index += 1) {
-      rc = FAPI_ATTR_GET(ATTR_MBA_PORT, &l_target_dimm_array[dimm_index], cur_mba_port); if(rc) return rc;
-      rc = FAPI_ATTR_GET(ATTR_MBA_DIMM, &l_target_dimm_array[dimm_index], cur_mba_dimm); if(rc) return rc;
-      cur_dimm_spd_valid_u8array[cur_mba_port][cur_mba_dimm] = MSS_EFF_VALID;
-      rc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM, &l_target_dimm_array[dimm_index], spd_custom[cur_mba_port][cur_mba_dimm]); if(rc) return rc;
-   }
-
-   uint32_t eff_cen_rcv_imp_dq_dqs_schmoo[PORT_SIZE];
-   uint32_t eff_cen_drv_imp_dq_dqs_schmoo[PORT_SIZE];
-   uint8_t eff_dram_gen = fapi::ENUM_ATTR_EFF_DRAM_GEN_DDR3;
-   uint8_t eff_dimm_type = fapi::ENUM_ATTR_EFF_DIMM_TYPE_LRDIMM;
-   uint8_t eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES;
-   uint8_t eff_dram_width = fapi::ENUM_ATTR_EFF_DRAM_WIDTH_X4;
-   uint8_t eff_dram_tdqs = fapi::ENUM_ATTR_EFF_DRAM_TDQS_DISABLE;
-   uint8_t eff_num_ranks_per_dimm[PORT_SIZE][DIMM_SIZE];
-   uint8_t eff_num_master_ranks_per_dimm[PORT_SIZE][DIMM_SIZE];
-   uint8_t eff_dimm_ranks_configed[PORT_SIZE][DIMM_SIZE]; 
-   uint8_t eff_num_drops_per_port = fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_SINGLE;
-
-   if (cur_dimm_spd_valid_u8array[0][0] == MSS_EFF_VALID) {
-      if (spd_custom[0][0] == fapi::ENUM_ATTR_SPD_CUSTOM_YES) {
-         eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_YES;
-      } else {
-         eff_custom_dimm = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO;
-      }
-   } else {
-      FAPI_INF("WARNING: Plug rule violation at %s!", i_target_mba.toEcmdString());
-      FAPI_INF("WARNING: Do NOT trust ATTR_EFF_CUSTOM_DIMM for %s!", i_target_mba.toEcmdString());
-   }
-
-   for (uint8_t cur_port = 0; cur_port < PORT_SIZE; cur_port += 1) {
-      eff_cen_rcv_imp_dq_dqs_schmoo[cur_port] = 0;
-      eff_cen_drv_imp_dq_dqs_schmoo[cur_port] = 0;
-      for (uint8_t cur_dimm = 0; cur_dimm < DIMM_SIZE; cur_dimm += 1) {
-         eff_num_ranks_per_dimm[cur_port][cur_dimm] = 8;
-         eff_num_master_ranks_per_dimm[cur_port][cur_dimm] = 8;
-         eff_dimm_ranks_configed[cur_port][cur_dimm] = 0xFF;
-      }
-   }
-
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, eff_cen_rcv_imp_dq_dqs_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, eff_cen_drv_imp_dq_dqs_schmoo); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_GEN, &i_target_mba, eff_dram_gen); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_TYPE, &i_target_mba, eff_dimm_type); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_CUSTOM_DIMM, &i_target_mba, eff_custom_dimm); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WIDTH, &i_target_mba, eff_dram_width); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_TDQS, &i_target_mba, eff_dram_tdqs); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, eff_num_ranks_per_dimm); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM, &i_target_mba, eff_num_master_ranks_per_dimm); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_DIMM_RANKS_CONFIGED, &i_target_mba, eff_dimm_ranks_configed); if(rc) return rc;
-   rc = FAPI_ATTR_SET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, eff_num_drops_per_port); if(rc) return rc;
-
-   return rc;
-}
-
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.H b/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.H
deleted file mode 100755
index 42e82e6d1..000000000
--- a/src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.H
+++ /dev/null
@@ -1,76 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mc_config/mss_eff_pre_config/mss_eff_pre_config.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_eff_pre_config.H,v 1.2 2014/02/20 20:52:11 bellows Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_eff_pre_config.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : mss_eff_pre_config.H
-// *! DESCRIPTION : Header file for mss_eff_pre_config.
-// *! OWNER NAME  : Michael Pardeik   Email: pardeik@us.ibm.com
-// *! BACKUP NAME : Anuwat Saetow     Email: asaetow@us.ibm.com
-// *! ADDITIONAL COMMENTS :
-//
-//
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.2   |          |         |
-//   1.1   | asaetow  |02-AUG-13| First Draft.
-
-
-#ifndef MSS_EFF_PRE_CONFIG_H_
-#define MSS_EFF_PRE_CONFIG_H_
-
-//----------------------------------------------------------------------
-//  My Includes
-//----------------------------------------------------------------------
-
-
-//----------------------------------------------------------------------
-//  Includes
-//----------------------------------------------------------------------
-#include <fapi.H>
-
-
-typedef fapi::ReturnCode (*mss_eff_pre_config_FP_t)(const fapi::Target i_target_mba);
-
-extern "C" {
-
-  //******************************************************************************
-    //* name=mss_eff_pre_config, param=i_target_mba, return=ReturnCode
-      //******************************************************************************
-        fapi::ReturnCode mss_eff_pre_config(const fapi::Target i_target_mba);
-
-} // extern "C"
-
-#endif // MSS_EFF_PRE_CONFIG_H_
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.C b/src/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.C
deleted file mode 100644
index d7aee6a7f..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.C
+++ /dev/null
@@ -1,128 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/accessMBvpdL4BankDelete.C $   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: accessMBvpdL4BankDelete.C,v 1.5 2015/02/24 19:23:31 whs Exp $
-/**
- *  @file accessMBvpdL4BankDelete.C
- *
- *  @brief get the L4 Bank Delete data from MBvpd record VSPD keyword MX
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <accessMBvpdL4BankDelete.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-fapi::ReturnCode accessMBvpdL4BankDelete(
-                              const fapi::Target  &i_mbTarget,
-                              uint32_t  & io_val,
-                              const fapi::MBvpdL4BankDeleteMode i_mode )
-{
-    fapi::ReturnCode l_fapirc;
-    uint16_t l_l4BankDelete = 0;
-    uint32_t l_bufSize = sizeof(l_l4BankDelete);
-
-    FAPI_DBG("accessMBvpdL4BankDelete: entry ");
-
-    do {
-        // check for get/set mode
-        if (GET_L4_BANK_DELETE_MODE == i_mode) // retrieve value from vpd
-        {
-            // get vpd version from record VSPD keyword MX
-            l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                 fapi::MBVPD_KEYWORD_MX,
-                                 i_mbTarget,
-                                 reinterpret_cast<uint8_t *>(&l_l4BankDelete),
-                                 l_bufSize);
-            if (l_fapirc)
-            {
-                FAPI_ERR("accessMBvpdL4BankDelete: Read of MX keyword failed");
-                break;  //  break out with fapirc
-            }
-
-            // Check that sufficient size was returned.
-            if (l_bufSize < sizeof(l_l4BankDelete) )
-            {
-                FAPI_ERR("accessMBvpdL4BankDelete:"
-                     " less keyword data returned than expected %d < %zd",
-                       l_bufSize, sizeof(l_l4BankDelete));
-                const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_MX;
-                const uint32_t & RETURNED_SIZE = l_bufSize;
-                const fapi::Target & CHIP_TARGET = i_mbTarget;
-                FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-                break;  //  break out with fapirc
-            }
-            // return value
-            io_val = static_cast<uint32_t>(FAPI_BE16TOH(l_l4BankDelete));
-
-            FAPI_DBG("accessMBvpdL4BankDelete: get L4 Bank Delete = 0x%08x",
-                io_val);
-        }
-        else if (SET_L4_BANK_DELETE_MODE == i_mode) // update vpd value
-        {
-
-            uint16_t l_val = static_cast<uint16_t>(io_val);
-            l_l4BankDelete = FAPI_HTOBE16(l_val);
-
-            // update vpd record VSPD keyword MX
-            l_fapirc = fapiSetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                 fapi::MBVPD_KEYWORD_MX,
-                                 i_mbTarget,
-                                 reinterpret_cast<uint8_t *>(&l_l4BankDelete),
-                                 l_bufSize);
-            if (l_fapirc)
-            {
-                FAPI_ERR("accessMBvpdL4BankDelete: Set of MX keyword failed");
-                break;  //  break out with fapirc
-            }
-
-            FAPI_DBG("accessMBvpdL4BankDelete: set L4 Bank Delete = 0x%04x",
-                l_l4BankDelete);
-
-        }
-        else  // unlikely invalid mode
-        {
-            FAPI_ERR("accessMBvpdL4BankDelete:"
-                     " invalid mode = 0x%02x", i_mode);
-            const uint32_t & MODE = i_mode;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INVALID_MODE_PARAMETER);
-            break;  //  break out with fapirc
-        }
-
-    } while (0);
-
-    FAPI_DBG("accessMBvpdL4BankDelete: exit rc=0x%08x)",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionConsts.H b/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionConsts.H
deleted file mode 100644
index 6eafef167..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionConsts.H
+++ /dev/null
@@ -1,48 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/hwpf/working/hwp/mvpd_accessors/compressionTool/DQCompressionConsts.H,v $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: DQCompressionConsts.H,v 1.1 2014/11/12 19:55:07 pragupta Exp $
-#ifndef _DQCOMPRESSIONCONSTS_H_
-#define _DQCOMPRESSIONCONSTS_H_
-
-namespace DQCompression
-{
-/* Constants to be used by compression and decompression */
-    const uint32_t DQarray_size         = 80;
-    const uint32_t DQSarray_size        = 20;
-    const uint32_t BYTE_LENGTH          =  8;
-    const uint32_t BYTE_CODE_LENGTH     =  3; //bytes
-    const uint32_t NIBBLE_SWAP_LENGTH   =  2; //bytes
-    const uint32_t NIBBLE_PERM_LENGTH   =  5; //bits
-    const uint32_t DQ_CODE_LENGTH       =  17;//bytes
-    const uint32_t DQS_CODE_LENGTH      =  2; //bytes
-    const uint32_t SIX_BIT_ZERO_PADDING =  6;
-
-    const uint32_t DQ_GROUP_SIZE        =  8;
-    const uint32_t DQS_GROUP_SIZE       =  2;
-    //DQ and DQS Flag - to determine the input type
-    const uint8_t DQ = 1;
-    const uint8_t DQS= 2;
-}
-#endif
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionLib.C b/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionLib.C
deleted file mode 100644
index e4f7f81e0..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionLib.C
+++ /dev/null
@@ -1,392 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/hwpf/working/hwp/mvpd_accessors/compressionTool/DQCompressionLib.C,v $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-//$Id: DQCompressionLib.C,v 1.6 2014/11/12 19:53:08 pragupta Exp $
-/**
- * @file  DQCompressionLib.C
- * @brief Defines utility functions which calculates the encoding for DQ
- *        or DQS arrays
- *
- * Wiring Rules:
- * - On a port any byte may be wired to any byte on the DIMM connector
- *   i.e. bytes must remain whole and undivided
- *
- * - In a Byte the Upper and Lower Nibble my be swapped.
- *   This includes the DQ and the DQS
- *
- * - In a Nibble any connection of the DQ is allowed.
- *    i.e. Nibbles must remain whole and undivided
- *
- * - The DQS may be swapped from the upper and lower nibbles
- *   in a byte without swapping the DQ.
- */
-#include <DQCompressionLib.H>
-#include "DQCompressionConsts.H"
-
-using namespace DQCompression;
-/**
- * @brief  Checks whether the input follows the wiring rules or not
- * @param  i_data DQ or DQS array as a vector
- * @param  i_arrayType DQ = 1 and DQS = 2
- */
-int validateInputData (const std::vector<uint8_t>& i_data,
-                uint32_t i_arrayType)
-{
-    int  l_rc = NO_ERR;
-    do
-    {
-        l_rc = ((i_data.size() == 80) || (i_data.size() == 20)) ?
-                NO_ERR : INVALID_INPUT;
-        if (l_rc != NO_ERR)
-        {
-                DQ_TRAC("Input data size is: %d. Size should be 80 or 20\n",
-                                (int)i_data.size());
-                break;
-        }
-        uint32_t l_grpSize = (i_arrayType == DQS) ? 2: BYTE_LENGTH;
-
-        //Check that the bytes are whole and undivided
-        //Check that the nibbles are whole and undivided
-        std::vector<uint8_t> l_data (i_data);
-
-        std::vector<uint8_t>::iterator l_itBegin  = l_data.begin();
-        std::vector<uint8_t>::iterator l_itMiddle = l_itBegin + (l_grpSize/2);
-        std::vector<uint8_t>::iterator l_itEnd    = l_itBegin + l_grpSize;
-
-        uint32_t l_loopCnts = l_data.size()-l_grpSize;
-        for(uint32_t i = 0; (i < l_loopCnts); i += l_grpSize)
-        {
-            //Sort nibbles at a time
-            std::sort(l_itBegin, l_itMiddle);
-            std::sort(l_itMiddle,l_itEnd);
-
-            //Check the first nibble
-            for (std::vector<uint8_t>::iterator j = l_itBegin;
-                                j < l_itMiddle-1; j++)
-            {
-                if (*(j+1) != (*j)+1)
-                {
-                    l_rc = INVALID_INPUT;
-                    DQ_TRAC("First nibble of byte %d is not together\n",i);
-                    break;
-                }
-            }
-            if (l_rc)
-            {
-                break;
-            }
-
-            //Check the second nibble
-            for (std::vector<uint8_t>::iterator j = l_itMiddle;
-                                (j < l_itEnd-1); j++)
-            {
-                if (*(j+1) != (*j)+1)
-                {
-                    l_rc = INVALID_INPUT;
-                    DQ_TRAC("Second nibble of byte %d is not together\n",i);
-                    break;
-                }
-            }
-            if (l_rc)
-            {
-                break;
-            }
-
-            //Check that first and second nibble are part of the same byte
-            uint8_t l_inc = l_grpSize/2;
-            if (((*l_itBegin+l_inc) != *l_itMiddle) &&
-                                ((*l_itBegin-l_inc) != *l_itMiddle))
-            {
-                l_rc = INVALID_INPUT;
-                DQ_TRAC("Byte %d is not together\n", i);
-                break;
-            }
-
-            l_itBegin += l_grpSize;
-            l_itMiddle+= l_grpSize;
-            l_itEnd   += l_grpSize;
-       } //end for loop
-    } while (0);
-    return l_rc;
-}
-
-
-/**
- * @brief  Calculates the byte-to-byte mapping for ISDIMM to Centaur
- * @param  i_data DQ or DQS array as a vector
- * @param  o_byteMap: vector that will hold the byte-to-byte mapping
- */
-void byte_mapping (std::vector<uint8_t>& i_data,
-                std::vector<uint8_t>& o_byteMap)
-{
-    uint32_t l_size = i_data.size() - BYTE_LENGTH;
-
-    for(uint32_t i = 0; i < l_size; i += BYTE_LENGTH)
-    {
-        o_byteMap.push_back(i_data[i]/BYTE_LENGTH);
-    }
-}
-
-/**
- * @brief  Calculates the permutation of a sequence between two iterators
- * @param  i_itBegin iterator to the beginning of the sequence
- * @param  i_itEnd   iterator to the end of the sequence
- * @retval uint32_t code: 24 bits of code for byte permuatation
- *         and 5 bits of code for nibble permutation
- */
-uint32_t permutation (const std::vector<uint8_t>::iterator i_itBegin,
-                const std::vector<uint8_t>::iterator i_itEnd)
-{
-    std::vector<uint8_t> l_sequence (i_itBegin, i_itEnd);
-    std::vector<uint8_t> l_permutation;
-    std::vector<uint8_t> l_index (l_sequence);
-    size_t l_seqSize = l_sequence.size();
-
-    //We want the sorted list of sequence to determine
-    //the index for lehmer's code
-    std::sort(l_index.begin(), l_index.end());
-
-    for(uint32_t i = 0; i < l_seqSize; i++)
-    {
-        //find the index of the value in sequence in the index array
-        std::vector<uint8_t> ::iterator it = std::find (l_index.begin(),
-                        l_index.end(), l_sequence.at(i));
-
-        //Add that index to another array
-        uint8_t l_idx = it-l_index.begin();
-        l_permutation.push_back(l_idx);
-
-        //Delete that value from the array and shift
-        //This will change the indices for the rest of
-        //the values each iteration
-        l_index.erase(l_index.begin() + l_idx);
-    }
-
-    //Skip the last element as it is always zero
-    l_permutation.pop_back();
-
-    uint32_t l_code = 0;
-    uint32_t l_factorial = 1;
-
-    //Generate the variable base code
-    //Since, the last element will always be zero.
-    //we start multiplying by 1!
-    for (uint32_t i = 1; i < l_seqSize; i++)
-    {
-        l_factorial *= i;
-        l_code += l_factorial * l_permutation.back();
-        l_permutation.pop_back();
-    }
-    return l_code;
-}
-
-/**
- * @brief  Figures out if the nibbles within a byte are swapped or not
- * @param  i_data DQ or DQS array as a vector
- * @param  l_grpSize: 8 for DQ and 2 for DQS
- * @retval uint32_t which has 1 for the byte whose nibble is swapped
- *         or 0 if the nibbles are not swapped
- */
-uint32_t nibble_swap (std::vector<uint8_t>& i_data, uint32_t l_grpSize)
-{
-    uint32_t o_swap = 0;
-    //Skip the last one as it is unused
-    for(uint32_t i = 0; i < i_data.size() - l_grpSize; i+= l_grpSize)
-    {
-        if (i_data.at(i) > i_data.at(i+(l_grpSize/2)))
-        {
-            o_swap |= 1;
-        }
-        o_swap <<= 1;
-    }
-    return (o_swap>>1);
-}
-
-/**
- * @brief  Insert data in ecmdDataBuffer one byte at a time to preserve
- *         endianess
- * @param  o_encodedData: buffer to insert the data into
- * @param  i_data:        value to be inserted in ecmdDataBuffer
- * @param  i_size:        number of bytes to insert
- * @param  i_startBit:    Bit to start inserting the data from
- * @retval errl:          NULL for no-err and BUFFER_OVERFLOW
- *                        if error inserting in ecmdDataBuffer
- */
-int insertEncodedData (ecmdDataBufferBase& o_encodedData, uint32_t i_data,
-                uint32_t i_size, uint32_t i_startBit)
-{
-    DQ_TRAC("Entering insertEncodedData i_data:%X, i_size:%d, i_startBit:%d\n",
-                i_data, i_size, i_startBit);
-    int  l_rc = NO_ERR;
-    //Insert one byte at a time to take care of endianess
-    for(int i = i_size; i > 0; i--)
-    {
-        uint32_t l_datatobeinserted = (i_data>>((i-1)*BYTE_LENGTH))&0xFF;
-        l_rc = o_encodedData.insertFromRight(l_datatobeinserted,
-                        i_startBit, BYTE_LENGTH);
-        if (l_rc)
-        {
-            l_rc = ECMD_OPER_ERROR;
-            DQ_TRAC("ECMD errored while writing %d data ;startbit=%d\n",
-                                l_datatobeinserted, i_startBit);
-            break;
-        }
-        i_startBit += BYTE_LENGTH;
-    }
-    return l_rc;
-}
-
-/**
- * @brief  Calculates the encoding for ISDIMM to C4DQ or C4DQS
- * @param  i_data    DQ or DQS array as a vector
- * @param  i_arrayType DQ = 1 and DQS = 2
- * @param  o_encodedData buffer to insert the encoded data into
- * @retval error codes
- */
-int DQCompression::encodeDQ (std::vector<uint8_t>& i_data,
-                uint32_t i_arrayType, ecmdDataBufferBase& o_encodedData)
-{
-    int l_rc = NO_ERR;
-    uint8_t l_grpSize;
-
-    DQ_TRAC("Entering encodeDQ\n");
-    do
-    {
-        l_rc = validateInputData (i_data, i_arrayType);
-        if(l_rc)
-        {
-            DQ_TRAC ("validateInputData errored\n");
-            break;
-        }
-        if (i_arrayType == DQ)
-        {
-            l_grpSize = DQ_GROUP_SIZE;
-            //allocate the buffers with right length
-            o_encodedData.setByteLength(DQ_CODE_LENGTH);
-
-            //Determine the byte-to-byte mapping
-            std::vector<uint8_t> l_byteMap;
-            byte_mapping(i_data, l_byteMap);
-
-            //Determine the permutation for byte mapping
-            uint32_t l_byteCode = permutation(l_byteMap.begin(),
-                        l_byteMap.end());
-
-            //Check if the nibbles are swapped within a byte
-            uint32_t l_nibbleSwap = nibble_swap(i_data, l_grpSize);
-
-            //Copy everything into the o_encodedData buffer
-            //Copy encoded data for byte-to-byte mapping
-            uint32_t l_startBit = 0;
-            DQ_TRAC("Writing byte-to-byte mapping to ecmdBuffer\n");
-            l_rc = insertEncodedData (o_encodedData, l_byteCode,
-                        BYTE_CODE_LENGTH,l_startBit);
-            if (l_rc)
-            {
-                DQ_TRAC("Error writing byte-to-byte mapping to ecmdBuffer\n");
-                break;
-            }
-
-            //Copy the data for nibbleSwap
-            DQ_TRAC("Writing nibbleSwap data to ecmdBuffer\n");
-            l_startBit += (BYTE_CODE_LENGTH * BYTE_LENGTH);
-            l_rc = insertEncodedData (o_encodedData, l_nibbleSwap,
-                            NIBBLE_SWAP_LENGTH,l_startBit);
-            if (l_rc)
-            {
-                DQ_TRAC("Error writing nibbleSwap data to ecmdBuffer\n");
-                break;
-            }
-
-            //Nibble Permutations - setup
-            std::vector<uint8_t>::iterator l_itBegin = i_data.begin();
-            std::vector<uint8_t>::iterator l_itEnd = l_itBegin +
-                (l_grpSize/2);
-
-            int l_numNibbles = ((i_data.size()/l_grpSize) - 1)*2;
-            l_startBit += NIBBLE_SWAP_LENGTH*BYTE_LENGTH;
-
-            //Add 0 padding - to round up the nibble perms to next byte
-            DQ_TRAC("Writing the 0 padding\n");
-            uint32_t l_temp = 0;
-            l_rc = o_encodedData.insertFromRight(l_temp,l_startBit,
-                        SIX_BIT_ZERO_PADDING);
-            if (l_rc)
-            {
-                DQ_TRAC("Error writing 6-bit 0 padding to ecmdDataBuffer\n");
-                break;
-            }
-            l_startBit += SIX_BIT_ZERO_PADDING;
-
-            DQ_TRAC("Starting nibble permutations\n");
-            for(int i = 0; i < l_numNibbles; i++)
-            {
-                //Find the permutation of the nibble
-                uint32_t l_nibblePerm = permutation(l_itBegin, l_itEnd);
-                //Store it in the encode data buffer
-                l_rc = o_encodedData.insertFromRight(l_nibblePerm,
-                                l_startBit,NIBBLE_PERM_LENGTH);
-                if (l_rc)
-                {
-                    DQ_TRAC("Error writing nibblePerm data to ecmdBuffer\n",
-                            i);
-                    break;
-                }
-                l_startBit += NIBBLE_PERM_LENGTH;
-
-                //Setup iterators for the next iteration
-                l_itBegin  += (l_grpSize/2);
-                l_itEnd    += (l_grpSize/2);
-            }
-
-            if (l_rc)
-            {
-                break;
-            }
-        }
-        else if (i_arrayType == DQS)
-        {
-            l_grpSize = DQS_GROUP_SIZE;
-
-            o_encodedData.setByteLength(DQS_CODE_LENGTH);
-            uint32_t l_nibbleSwap = nibble_swap(i_data, l_grpSize);
-            l_rc = insertEncodedData (o_encodedData, l_nibbleSwap,
-                        NIBBLE_SWAP_LENGTH,0);
-            if (l_rc)
-            {
-                DQ_TRAC("Error writing DQS data to ecmdDataBuffer\n");
-                break;
-            }
-        }
-        else
-        {
-            l_rc = INVALID_ARRAY_TYPE;
-            DQ_TRAC("Data type does not match DQ or DQS\n");
-            break;
-        }
-    } while (0);
-
-    DQ_TRAC("Exiting encodeDQ\n");
-    return l_rc;
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionReasonCodes.H b/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionReasonCodes.H
deleted file mode 100644
index ce519624f..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/DQCompressionReasonCodes.H
+++ /dev/null
@@ -1,39 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/hwpf/working/hwp/mvpd_accessors/compressionTool/DQCompressionReasonCodes.H,v $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-//$Id: DQCompressionReasonCodes.H,v 1.4 2014/11/12 19:53:08 pragupta Exp $
-/* @file DQCompressionReasonCodes.H
- *
- * @brief Reason Codes files for DQCompressionLib
- */
-#ifndef __DQCOMPRESSIONREASONCODES_H
-#define __DQCOMPRESSIONREASONCODES_H
-    const char* ReasonCodes [] =
-    {
-        "NO_ERR",
-        "ECMD_OPER_ERROR",
-        "INVALID_INPUT",
-        "INVALID_ARRAY_TYPE"
-    };
-#endif
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/EncodeDQMapping.C b/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/EncodeDQMapping.C
deleted file mode 100644
index d2d861308..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/EncodeDQMapping.C
+++ /dev/null
@@ -1,292 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/hwpf/working/hwp/mvpd_accessors/compressionTool/EncodeDQMapping.C,v $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-//$Id: EncodeDQMapping.C,v 1.5 2014/11/12 19:53:08 pragupta Exp $
-
-/*
- *  @file  EncodeDQMapping.C
- *  @brief computes the encoding for ISDIMM to DQ or DQS mapping
- *
- *
- *  @param first input is a csv file that has the contents of DQ or DQS array
- *         It can have upto 4 ports. If there are less than 4 ports passed in,
- *         the algorithm will assume one-to-one mapping for the rest of the
- *         ports, meaning zeros for encoded data.
- *
- *
- *  @param second input is a file that will hold the encoded data
- *         (one byte of hex data separated with a space)
- *
- *
- */
-#include <DQCompressionLib.H>
-#include "DQCompressionReasonCodes.H"
-#include "DQCompressionConsts.H"
-#include <stdio.h>
-
-using namespace DQCompression;
-
-void parseInput (FILE* i_ptrFile, std::vector <std::vector<uint8_t> >& i_dqData,
-                 std::vector<std::vector<uint8_t> >& i_dqsData)
-{
-    const uint32_t l_MAX_STR_LENGTH = 300;
-    char l_inputStr [l_MAX_STR_LENGTH];
-    char* l_splitStr;
-
-    int l_dqRowNum  = 0;
-    int l_dqsRowNum = 0;
-    uint8_t l_arrayType = 0;
-
-    //Read the file
-    while (fgets(l_inputStr,l_MAX_STR_LENGTH,i_ptrFile))
-    {
-        //convert l_inputStr to a vector of uint8_t
-        l_splitStr = strtok (l_inputStr, ",");
-        //# means it is a comment: the comment can say whether it is DQ or DQS
-        if (*l_splitStr == '#')
-        {
-            //Look for DQ or DQS in the comment
-            char* l_dqPos = strstr(l_splitStr, "DQ");
-            if (l_dqPos != NULL)
-            {
-                l_arrayType = (*(l_dqPos+2) == 'S') ? DQS : DQ;
-            }
-        }
-        //Skip empty lines
-        else if (*l_splitStr != '\n')
-        {
-            std::vector <uint8_t> l_col;
-            //Add DQ arrays to the i_dqData vector
-            if(l_arrayType == DQ)
-            {
-                i_dqData.push_back (l_col);
-                while (l_splitStr != NULL)
-                {
-                    i_dqData.at(l_dqRowNum).push_back(atoi(l_splitStr));
-                    l_splitStr = strtok (NULL, ",");
-                }
-                l_dqRowNum += 1;
-            }
-
-            else if(l_arrayType == DQS)
-            {
-                //Add DQS arrays to the i_dqsData vector
-                i_dqsData.push_back (l_col);
-                while (l_splitStr != NULL)
-                {
-                    i_dqsData.at(l_dqsRowNum).push_back(atoi(l_splitStr));
-                    l_splitStr = strtok (NULL, ",");
-                }
-                l_dqsRowNum += 1;
-            }
-            else
-            {
-                fprintf(stderr,"Couldn't determixe DQ or DQS from comment\n");
-                exit(1);
-            }
-        } // end outer else if
-    } //end while
-}
-int writeEncodedData (FILE* i_ptrFile,
-        std::vector <std::vector<uint8_t> >& i_data, uint8_t i_arrayType)
-{
-    size_t l_numPorts = i_data.size();
-    uint32_t l_dataSize;
-    int  l_rc = 0;
-    for (uint32_t i = 0; i < l_numPorts; i++)
-    {
-        DQ_TRAC ("Input Data: \n");
-        for (uint32_t j = 0; j < i_data.at(i).size(); j++)
-        {
-           DQ_TRAC("%d ", i_data.at(i).at(j));
-        }
-        DQ_TRAC ("\n");
-
-
-        ecmdDataBufferBase l_encodedData;
-        l_rc = encodeDQ (i_data.at(i), i_arrayType,
-                        l_encodedData);
-        if(l_rc)
-        {
-            //Check l_rc and print meaningful msgs
-            fprintf(stderr, "Error Encoding Data %s \n", ReasonCodes[l_rc]);
-            exit(1);
-        }
-
-        l_dataSize = l_encodedData.getByteLength();
-        char l_buffer [4];
-        //Write the data to a text file
-        for (uint32_t j = 0; j < l_dataSize; j++)
-        {
-            if (j == 0)
-            {
-                sprintf(l_buffer,"%02X", l_encodedData.getByte(j));
-            }
-            else
-            {
-                sprintf(l_buffer," %02X", l_encodedData.getByte(j));
-            }
-            l_rc = fputs(l_buffer, i_ptrFile);
-            if (l_rc == EOF)
-            {
-                DQ_TRAC("Unable to write data to the output file.\n");
-                break;
-            }
-        }
-        if (l_rc == EOF)
-        {
-            break;
-        }
-        l_rc = fputs("\n", i_ptrFile);
-        if (l_rc == EOF)
-        {
-            DQ_TRAC("Unable to write newline char to the output file\n");
-            break;
-        }
-    }
-
-    //If less than 4 ports are passed in as an input, we assume
-    //that the rest of the ports have one to one mapping, which
-    //leads to all zeros for the encoded data.
-    if (l_numPorts < 4)
-    {
-        for (uint32_t i = 0; i < (4 - l_numPorts); i++)
-        {
-            for (uint32_t j = 0; j < l_dataSize; j++)
-            {
-                if(j == 0)
-                {
-                    l_rc = fputs("00", i_ptrFile);
-                    if (l_rc == EOF)
-                    {
-                        DQ_TRAC("Unable to write data '00' to the output file");
-                        break;
-                    }
-                }
-                else
-                {
-                    l_rc = fputs(" 00", i_ptrFile);
-                    if (l_rc == EOF)
-                    {
-                        DQ_TRAC("Unable to write data '00' to the output file");
-                        break;
-                    }
-                }
-            } //end inner for loop
-            if (l_rc == EOF)
-            {
-                break;
-            }
-            l_rc = fputs("\n", i_ptrFile);
-            if (l_rc == EOF)
-            {
-                DQ_TRAC("Unable to write newline char to the output file");
-                break;
-            }
-        } //end for loop
-    } // end if statement
-}
-
-
-
-int main (int argc, char* argv [])
-{
-    int l_rc = 0;
-    do {
-        if (argc > 3)
-        {
-            fprintf(stderr, "There should only be two parameters\n");
-            exit(1);
-        }
-        //Open the input file
-        FILE* l_prInFile = fopen (argv[1], "r");
-        if (l_prInFile == NULL)
-        {
-            fprintf(stderr, "Can't open the input file for reading\n");
-            exit(1);
-        }
-
-        //parse the inputs
-        std::vector <std::vector<uint8_t> > l_dqData;
-        std::vector <std::vector<uint8_t> > l_dqsData;
-        parseInput(l_prInFile, l_dqData, l_dqsData);
-        fclose(l_prInFile);
-
-        //Open the output file
-        FILE* l_prOutFile = fopen (argv[2], "w");
-        if (l_prOutFile == NULL)
-        {
-            fprintf(stderr, "Can't open the output file for writing\n");
-            exit(1);
-        }
-
-        //process DQ arrays
-        if (!(l_dqData.empty()))
-        {
-            l_rc = fputs("DQ\n", l_prOutFile);
-            if (l_rc == EOF)
-            {
-                DQ_TRAC("Unable to write DQ to the file\n");
-                break;
-            }
-            if(l_dqData.at(0).size() != DQarray_size)
-            {
-                fprintf(stderr, "DQ arrays must have 80 elements\n");
-             exit(1);
-            }
-            l_rc =  writeEncodedData (l_prOutFile, l_dqData, DQ);
-            if (l_rc == EOF)
-            {
-                DQ_TRAC ("writeEncodedData for DQ failed l_rc: %d\n", l_rc);
-                break;
-            }
-        }
-
-        //process DQS arrays
-         if (!(l_dqsData.empty()))
-        {
-            l_rc = fputs("DQS\n", l_prOutFile);
-            if (l_rc == EOF)
-            {
-                DQ_TRAC("Unable to write DQS to the file\n");
-                break;
-            }
-            if(l_dqsData.at(0).size() != DQSarray_size)
-            {
-                fprintf(stderr, "DQS arrays must have 20 elements\n");
-                exit(1);
-            }
-            l_rc = writeEncodedData (l_prOutFile, l_dqsData, DQS);
-            if (l_rc == EOF)
-            {
-                DQ_TRAC("writeEncodedData for DQS failed\n");
-                break;
-            }
-        }
-
-        fclose(l_prOutFile);
-    } while (0);
-
-    return ((l_rc == EOF) ? EOF : 0);
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/makefile b/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/makefile
deleted file mode 100644
index fa6b04766..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/compressionTool/makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/mvpd_accessors/compressionTool/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2014,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../../..
-
-OUT_FILE += $(GENDIR)/compression
-
-GEN_PASS_BODY += $(OUT_FILE)
-CLEAN_TARGETS += $(OUT_FILE) compression.o
-
-INC_DIRS += $(ROOTPATH)/src/include/usr/ecmddatabuffer
-INC_DIRS += $(ROOTPATH)/src/include/usr/hwpf/hwp/mvpd_accessors
-INC_DIRS += $(ROOTPATH)/src/usr/hwpf/hwp/mvpd_accessors/compressionTool
-vpath %.C $(ROOTPATH)/src/usr/ecmddatabuffer
-
-HCFLAGS += -DPRDF_COMPRESSBUFFER_COMPRESS_FUNCTIONS=1
-HCFLAGS += -DPRDF_COMPRESSBUFFER_UNCOMPRESS_FUNCTIONS=1
-HCFLAGS += -lz
-HCFLAGS += -Di386=1
-
-include $(ROOTPATH)/config.mk
-
-$(OUT_FILE): ecmdDataBufferBase.C DQCompressionLib.C EncodeDQMapping.C
-	$(C2) "    CC         $(notdir $@)"
-	$(C1)$(CCACHE) $(HOST_PREFIX)g++ -O3 -g $^ -o $(OUT_FILE)\
-			$(foreach dir,$(INC_DIRS), -I $(dir)) $(HCFLAGS)
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C b/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C
deleted file mode 100644
index 491e0c19c..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C
+++ /dev/null
@@ -1,77 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C $     */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $ID: getControlCapableData.C, v 1.1 2014/9/4 09:05:00 eliner Exp $
-/**
- *  @file getControlCapable.C
- *
- *  @brief MBvpd accessor for the ATTR_VPD_POWER_CONTROL_CAPABLE attributes
- */
-
-#include    <stdint.h>
-#include    <fapi.H>
-#include    <getControlCapableData.H>
-
-extern "C"
-{
-using namespace fapi;
-fapi::ReturnCode getControlCapableData(
-                const fapi::Target &i_mbTarget,
-                uint8_t & o_val)
-{
-    fapi::ReturnCode l_rc;
-
-    FAPI_DBG("getControlCapableData: start");
-    do {
-        // ATTR_VPD_POWER_CONTROL_CAPABLE is at the membuf level, but the
-        //  getMBvpdAttr() function takes a mba, so need to do a
-        //  conversion
-        std::vector<fapi::Target> l_mbas;
-        l_rc = fapiGetChildChiplets( i_mbTarget,
-                                     fapi::TARGET_TYPE_MBA_CHIPLET,
-                                     l_mbas );
-        if( l_rc )
-        {
-            FAPI_ERR("getControlCapableData: fapiGetChildChiplets failed");
-            break;
-        }
-
-        // If we don't have any functional MBAs then we will fail in
-        //  the other function so just return a default value here
-        if( l_mbas.empty() )
-        {
-            o_val = fapi::ENUM_ATTR_VPD_POWER_CONTROL_CAPABLE_NONE;
-            break;
-        }
-
-        // Call a VPD Accessor HWP to get the data
-        FAPI_EXEC_HWP(l_rc, getMBvpdAttr,
-                      l_mbas[0], ATTR_VPD_POWER_CONTROL_CAPABLE,
-                      &o_val, sizeof(ATTR_VPD_POWER_CONTROL_CAPABLE_Type));
-    } while(0);
-    FAPI_DBG("getControlCapableData: end");
-
-    return l_rc;
-}
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.C b/src/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.C
deleted file mode 100644
index 95062bb6f..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.C
+++ /dev/null
@@ -1,128 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getDQAttrISDIMM.C $           */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getDQAttrISDIMM.C,v 1.1 2015/04/09 13:36:12 janssens Exp $
-/**
- * @file getDQAttrISDIMM.C
- *
- * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQ attribute
- */
-
-#include <stdint.h>
-#include <fapi.H>
-#include <getISDIMMTOC4DAttrs.H>
-#include <getDecompressedISDIMMAttrs.H>
-#include <getDQAttrISDIMM.H>
-
-extern "C"
-{
-
-using namespace fapi;
-
-fapi::ReturnCode getDQAttrISDIMM(
-                const fapi::Target &i_mbTarget,
-                uint8_t (&o_val)[4][80])
-{
-
-    const uint32_t l_Q0_KEYWORD_SIZE = 32;
-    //Record:SPDX, Keyword Q1, offset:0, 96 bytes.
-    uint8_t l_q0_keyword[l_Q0_KEYWORD_SIZE];
-    uint32_t l_Q0Bufsize = l_Q0_KEYWORD_SIZE;
-    uint8_t l_DQ_keyword[DQ_KEYWORD_SIZE];
-
-    fapi::ReturnCode l_fapirc;
-    do{
-
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_SPDX,
-                        fapi::MBVPD_KEYWORD_Q0,
-                        i_mbTarget,
-                        (uint8_t *) (&l_q0_keyword),
-                        l_Q0Bufsize);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getDQAttrISDIMM: Read of Q0 Keyword failed");
-            break;
-        }
-
-        uint8_t l_dimmPos = 0;
-        l_fapirc = FAPI_ATTR_GET(ATTR_ISDIMM_MBVPD_INDEX,&i_mbTarget,l_dimmPos);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getDQAttrISDIMM: read of ATTR_POS failed");
-            break;
-        }
-
-        l_fapirc = getDQAttribute(i_mbTarget,l_q0_keyword[l_dimmPos],
-                                  l_DQ_keyword);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getDQAttrISDIMM: read of DQ Keyword failed");
-            break;
-        }
-    }while(0);
-
-    //end actual data
-
-    ecmdDataBufferBase l_data_buffer_DQ1(136); //17 bytes
-    ecmdDataBufferBase l_data_buffer_DQ2(136);
-    ecmdDataBufferBase l_data_buffer_DQ3(136);
-    ecmdDataBufferBase l_data_buffer_DQ4(136);
-    ecmdDataBufferBase l_data_buffer_DQS(16); //2 bytes
-    uint8_t l_finalDQ1Array[80];
-    uint8_t l_finalDQ2Array[80];
-    uint8_t l_finalDQ3Array[80];
-    uint8_t l_finalDQ4Array[80];
-    uint8_t l_finalDQSArray[20];
-
-    for(int l_dataIndex=0;l_dataIndex<17;l_dataIndex++)
-    {
-        l_data_buffer_DQ1.insertFromRight(l_DQ_keyword[l_dataIndex],
-                        l_dataIndex*8,8);
-        l_data_buffer_DQ2.insertFromRight(l_DQ_keyword[l_dataIndex+17],
-                        l_dataIndex*8,8);
-        l_data_buffer_DQ3.insertFromRight(l_DQ_keyword[l_dataIndex+34],
-                        l_dataIndex*8,8);
-        l_data_buffer_DQ4.insertFromRight(l_DQ_keyword[l_dataIndex+51],
-                        l_dataIndex*8,8);
-    }
-    decodeISDIMMAttrs(l_data_buffer_DQ1,l_data_buffer_DQS,
-                    l_finalDQ1Array,l_finalDQSArray);
-    decodeISDIMMAttrs(l_data_buffer_DQ2,l_data_buffer_DQS,
-                    l_finalDQ2Array,l_finalDQSArray);
-    decodeISDIMMAttrs(l_data_buffer_DQ3,l_data_buffer_DQS,
-                    l_finalDQ3Array,l_finalDQSArray);
-    decodeISDIMMAttrs(l_data_buffer_DQ4,l_data_buffer_DQS,
-                    l_finalDQ4Array,l_finalDQSArray);
-
-    for(int l_finalIndex=0;l_finalIndex<80;l_finalIndex++)
-    {
-        o_val[0][l_finalIndex] = l_finalDQ1Array[l_finalIndex];
-        o_val[1][l_finalIndex] = l_finalDQ2Array[l_finalIndex];
-        o_val[2][l_finalIndex] = l_finalDQ3Array[l_finalIndex];
-        o_val[3][l_finalIndex] = l_finalDQ4Array[l_finalIndex];
-    }
-    return FAPI_RC_SUCCESS;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.C b/src/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.C
deleted file mode 100644
index 408250931..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.C
+++ /dev/null
@@ -1,222 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getDQSAttrISDIMM.C $          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getDQSAttrISDIMM.C,v 1.1 2015/04/09 13:36:16 janssens Exp $
-/**
- * @file getDQSAttrISDIMM.C
- *
- * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQS attribute
- */
-
-#include <stdint.h>
-#include <fapi.H>
-#include <getISDIMMTOC4DAttrs.H>
-#include <getDecompressedISDIMMAttrs.H>
-#include <getDQSAttrISDIMM.H>
-
-extern "C"
-{
-
-using namespace fapi;
-
-fapi::ReturnCode getDQSAttrISDIMM(
-                const fapi::Target &i_mbTarget,
-                uint8_t (&o_val)[4][20])
-{
-    //Record:SPDX, Keyword K1, offset:0,32 bytes
-    const uint32_t l_Q0_KEYWORD_SIZE = 32;
-    const uint32_t l_K0_KEYWORD_SIZE = 32;
-    const uint32_t l_DQS_KEYWORD_SIZE = 32;
-    uint8_t l_k0_keyword[l_K0_KEYWORD_SIZE];
-    uint8_t l_q0_keyword[l_Q0_KEYWORD_SIZE];
-    uint8_t l_DQS_keyword[l_DQS_KEYWORD_SIZE];
-    uint8_t l_DQ_keyword[DQ_KEYWORD_SIZE];
-    uint32_t l_K0Bufsize = l_K0_KEYWORD_SIZE;
-    uint32_t l_Q0Bufsize = l_Q0_KEYWORD_SIZE;
-    uint32_t l_DQSBufsize = l_DQS_KEYWORD_SIZE;
-
-
-    fapi::ReturnCode l_fapirc;
-    do{
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_SPDX,
-                       fapi::MBVPD_KEYWORD_K0,
-                       i_mbTarget,
-                       (uint8_t *) (&l_k0_keyword),
-                       l_K0Bufsize);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getDQSAttrISDIMM: Read of K0 Keyword failed");
-            break;
-        }
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_SPDX,
-                       fapi::MBVPD_KEYWORD_Q0,
-                       i_mbTarget,
-                       (uint8_t *) (&l_q0_keyword),
-                       l_Q0Bufsize);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getDQSAttrISDIMM: Read of Q0 Keyword failed");
-            break;
-        }
-
-        uint8_t l_dimmPos = 0;
-        l_fapirc = FAPI_ATTR_GET(ATTR_ISDIMM_MBVPD_INDEX,&i_mbTarget,l_dimmPos);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getDQAttrISDIMM: read of ATTR_POS failed");
-            break;
-        }
-
-        fapi::MBvpdKeyword l_DQS_Keyword = fapi::MBVPD_KEYWORD_K1;
-        uint8_t l_actualK0Data = l_k0_keyword[l_dimmPos];
-        switch(l_actualK0Data)
-        {
-            case 1:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K1;
-                break;
-            case 2:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K2;
-                break;
-            case 3:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K3;
-                break;
-            case 4:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K4;
-                break;
-            case 5:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K5;
-                break;
-            case 6:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K6;
-                break;
-            case 7:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K7;
-                break;
-            case 8:
-                l_DQS_Keyword = fapi::MBVPD_KEYWORD_K8;
-                break;
-            default:
-                FAPI_ERR("getISDIMMTOC4DAttrs: Incorrect Data to read DQS keyword, tried to read copy 0x%02x",l_actualK0Data);
-                const uint8_t & DQS_COPY = l_actualK0Data;
-                FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_DQS_DATA);
-                break;
-        }
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_SPDX,
-                                     l_DQS_Keyword,
-                                     i_mbTarget,
-                                     (uint8_t *) (&l_DQS_keyword),
-                                     l_DQSBufsize);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getISDIMMTOC4DAttrs: Read of DQS keyword failed");
-            break;
-        }
-
-        l_fapirc = getDQAttribute(i_mbTarget,l_q0_keyword[l_dimmPos],
-                                  l_DQ_keyword);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getISDIMMTOC4DAttrs: Read of DQ keyword failed");
-            break;
-        }
-
-        uint32_t rc_num = 0;
-
-        if(!l_fapirc)
-        {
-            ecmdDataBufferBase l_data_buffer_DQ1(136); //17 bytes
-            ecmdDataBufferBase l_data_buffer_DQ2(136);
-            ecmdDataBufferBase l_data_buffer_DQ3(136);
-            ecmdDataBufferBase l_data_buffer_DQ4(136);
-            ecmdDataBufferBase l_data_buffer_DQS1(16); //2 bytes
-            ecmdDataBufferBase l_data_buffer_DQS2(16);
-            ecmdDataBufferBase l_data_buffer_DQS3(16);
-            ecmdDataBufferBase l_data_buffer_DQS4(16);
-
-            uint8_t l_finalDQArray[80];
-            uint8_t l_finalDQS1Array[20];
-            uint8_t l_finalDQS2Array[20];
-            uint8_t l_finalDQS3Array[20];
-            uint8_t l_finalDQS4Array[20];
-
-            for(int l_dqsDataIndex=0;l_dqsDataIndex<2;l_dqsDataIndex++)
-            {
-                rc_num |= l_data_buffer_DQS1.
-                        insertFromRight(l_DQS_keyword[l_dqsDataIndex],
-                                        l_dqsDataIndex*8,8);
-                rc_num |= l_data_buffer_DQS2.
-                        insertFromRight(l_DQS_keyword[l_dqsDataIndex+2],
-                                        l_dqsDataIndex*8,8);
-                rc_num |= l_data_buffer_DQS3.
-                        insertFromRight(l_DQS_keyword[l_dqsDataIndex+4],
-                                        l_dqsDataIndex*8,8);
-                rc_num |= l_data_buffer_DQS4.
-                        insertFromRight(l_DQS_keyword[l_dqsDataIndex+8],
-                                        l_dqsDataIndex*8,8);
-            }
-            for(int l_dqDataIndex=0;l_dqDataIndex<17;l_dqDataIndex++)
-            {
-                rc_num |= l_data_buffer_DQ1.
-                        insertFromRight(l_DQ_keyword[l_dqDataIndex],
-                                        l_dqDataIndex*8,8);
-                rc_num |= l_data_buffer_DQ2.
-                        insertFromRight(l_DQ_keyword[l_dqDataIndex+17],
-                                        l_dqDataIndex*8,8);
-                rc_num |= l_data_buffer_DQ3.
-                        insertFromRight(l_DQ_keyword[l_dqDataIndex+34],
-                                        l_dqDataIndex*8,8);
-                rc_num |= l_data_buffer_DQ4.
-                        insertFromRight(l_DQ_keyword[l_dqDataIndex+51],
-                                        l_dqDataIndex*8,8);
-            }
-
-            l_fapirc.setEcmdError(rc_num);
-            if(l_fapirc)
-            {
-                FAPI_ERR("getISDIMMTOC4DAttrs.C: ecmdDataBufferBase inserted wrong");
-                break;
-            }
-
-            decodeISDIMMAttrs(l_data_buffer_DQ1,l_data_buffer_DQS1,
-                            l_finalDQArray,l_finalDQS1Array);
-            decodeISDIMMAttrs(l_data_buffer_DQ2,l_data_buffer_DQS2,
-                            l_finalDQArray,l_finalDQS2Array);
-            decodeISDIMMAttrs(l_data_buffer_DQ3,l_data_buffer_DQS3,
-                            l_finalDQArray,l_finalDQS3Array);
-            decodeISDIMMAttrs(l_data_buffer_DQ4,l_data_buffer_DQS4,
-                            l_finalDQArray,l_finalDQS4Array);
-
-            for(int l_finalIndex=0;l_finalIndex<20;l_finalIndex++)
-            {
-                o_val[0][l_finalIndex] = l_finalDQS1Array[l_finalIndex];
-                o_val[1][l_finalIndex] = l_finalDQS2Array[l_finalIndex];
-                o_val[2][l_finalIndex] = l_finalDQS3Array[l_finalIndex];
-                o_val[3][l_finalIndex] = l_finalDQS4Array[l_finalIndex];
-            }
-        }
-    }while(0);
-    return l_fapirc;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.C b/src/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.C
deleted file mode 100644
index a5dbd47b7..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.C
+++ /dev/null
@@ -1,263 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getDecompressedISDIMMAttrs.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $ID: getDecompressedISDIMMAttrs.C, v 1.1 2014/9/26 09:22:00 eliner Exp $
-
-/**
- *  @file getDecompressedISDIMMAttrs.C
- *
- *  @brief Decompresses the ISDIMMToC4DQ and DQS Attributes for proper use
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <vector>
-#include <ecmdDataBufferBase.H>
-#include <getDecompressedISDIMMAttrs.H>
-
-void antiPermutation(int i_permNum, int* o_array,int i_finalSize)
-{
-    int l_factorialIndex = 1;
-    int l_factorialNum = 1;
-    int l_permNum = i_permNum;
-    int l_size;
-
-    //find the largest factorial needed to represent this number
-    //(need to find whether we're antiPermuting an array with length 4 or 9)
-
-    while(i_permNum > l_factorialNum)
-    {
-        l_factorialIndex = l_factorialIndex + 1;
-        l_factorialNum = l_factorialNum * l_factorialIndex;
-    }
-
-    if(i_permNum != l_factorialNum && i_permNum != 0)
-    {
-        l_factorialNum = l_factorialNum/l_factorialIndex;
-        l_factorialIndex = l_factorialIndex - 1;
-    }
-
-    //now make the array to match the size
-    l_size = i_finalSize -1;
-
-    //fill the array
-    //first with 0's
-    for(int l_arrayIndex = 0; l_arrayIndex<i_finalSize;l_arrayIndex++)
-    {
-        o_array[l_arrayIndex] = 0;
-    }
-
-    while(l_permNum >= l_factorialNum || l_factorialIndex > 0)
-    {
-        if(l_permNum < l_factorialNum){
-            l_factorialNum = l_factorialNum/l_factorialIndex;
-            l_factorialIndex = l_factorialIndex - 1;
-        }else{
-            o_array[l_size-l_factorialIndex] =
-                    o_array[l_size-l_factorialIndex]+1;
-            l_permNum = l_permNum - l_factorialNum;
-        }
-    }
-}
-
-void unPermeateToVector(int* i_array, int i_size,std::vector<int>& o_result)
-{
-    std::vector<int> l_allNumbers;
-    for(int l_allNumIndex=0;l_allNumIndex<i_size;l_allNumIndex++)
-    {
-        l_allNumbers.push_back(l_allNumIndex);
-    }
-
-    o_result.clear();
-    for(int l_arrayIndex = 0; l_arrayIndex<i_size;l_arrayIndex++)
-    {
-        o_result.push_back(l_allNumbers.at(i_array[l_arrayIndex]));
-        l_allNumbers.erase(l_allNumbers.begin()+i_array[l_arrayIndex]);
-    }
-}
-
-int getSeparatedInformation(ecmdDataBufferBase& i_toSeparateDQ,
-                            ecmdDataBufferBase& i_separateDQS,
-                            int* o_nibSwap,int* o_nibToNib,int* o_nibSwapDQS)
-{
-    uint32_t o_byteToByte = 0;
-
-    for(int l_nibSwapIndex=0;l_nibSwapIndex<9;l_nibSwapIndex++)
-    {
-        //the nibble bits are bits 31 to 39
-        uint32_t l_DQ_index_bit = l_nibSwapIndex+31;
-        uint32_t l_DQS_index_bit = l_nibSwapIndex+7;
-        o_nibSwap[l_nibSwapIndex] = i_toSeparateDQ.getBit(l_DQ_index_bit);
-        o_nibSwapDQS[l_nibSwapIndex] = i_separateDQS.getBit(l_DQS_index_bit);
-
-    }
-    uint32_t l_toAdd = 1;
-    //@todo-RTC:117985
-    for(int l_byteIndex=23;l_byteIndex>=2;l_byteIndex--)
-    {
-        //byte to byte is bits 2-23
-        uint32_t l_currentBit = i_toSeparateDQ.getBit(l_byteIndex);
-        if(l_currentBit == 1)
-        {
-            o_byteToByte = o_byteToByte + l_toAdd;
-        }
-        l_toAdd = l_toAdd * 2;
-    }
-    for(int l_nibbleIndex=0;l_nibbleIndex<18;l_nibbleIndex++)
-    {
-        uint32_t l_currentSum = 0;
-        uint32_t l_toAddNibble = 1;
-        //nibble to Nibble is 46-135
-        for(int l_bitIndex=4;l_bitIndex>=0;l_bitIndex--)
-        {
-            uint32_t l_currentBit = i_toSeparateDQ.getBit((l_nibbleIndex*5)+
-                            46+l_bitIndex);
-            if(l_currentBit == 1)
-            {
-                l_currentSum = l_currentSum + l_toAddNibble;
-            }
-            l_toAddNibble = l_toAddNibble * 2;
-        }
-        o_nibToNib[l_nibbleIndex] = l_currentSum;
-    }
-    return o_byteToByte;
-
-}
-
-void convertToFinal80Array(uint8_t* o_final80Array,
-                std::vector<int>& i_byteNums,int* i_nibbleSwap,
-                std::vector<std::vector<int> >& i_nibbleToNibNums)
-{
-    int l_byteIndex;
-    int l_zeroSeven;
-
-    for(l_byteIndex = 0; l_byteIndex < 9; l_byteIndex++)
-    {
-        for(l_zeroSeven = 0; l_zeroSeven<8; l_zeroSeven++)
-        {
-            o_final80Array[(l_byteIndex*8)+l_zeroSeven] =
-                    (i_byteNums.at(l_byteIndex)*8) + l_zeroSeven;
-        }
-    }
-    //nibble switch now.
-    for(int l_nibIndex = 0; l_nibIndex<9;l_nibIndex++)
-    {
-        if(i_nibbleSwap[l_nibIndex] == 1)
-        {
-            for(int l_bitIndex = 0; l_bitIndex<4;l_bitIndex++)
-            {
-                char l_placeHolder = o_final80Array[(l_nibIndex*8) +
-                        l_bitIndex];
-                o_final80Array[(l_nibIndex*8) + l_bitIndex] =
-                        o_final80Array[(l_nibIndex*8) + l_bitIndex + 4];
-                o_final80Array[(l_nibIndex*8) + l_bitIndex + 4] =
-                        l_placeHolder;
-            }
-        }
-    }
-    //nibble order now.
-    for(int l_nibOrderIndex = 0; l_nibOrderIndex<18; l_nibOrderIndex++)
-    {
-        std::vector<int> l_currentNibSet =
-                i_nibbleToNibNums.at(l_nibOrderIndex);
-        o_final80Array[(l_nibOrderIndex*4)+1] =
-                o_final80Array[(l_nibOrderIndex*4)] + l_currentNibSet.at(1);
-        o_final80Array[(l_nibOrderIndex*4)+2] =
-                o_final80Array[(l_nibOrderIndex*4)] + l_currentNibSet.at(2);
-        o_final80Array[(l_nibOrderIndex*4)+3] =
-                o_final80Array[(l_nibOrderIndex*4)] + l_currentNibSet.at(3);
-        o_final80Array[(l_nibOrderIndex*4)] =
-                o_final80Array[(l_nibOrderIndex*4)] + l_currentNibSet.at(0);
-    }
-    for(int l_finalIndex = 72; l_finalIndex<80;l_finalIndex++)
-    {
-        o_final80Array[l_finalIndex] = 255;
-    }
-}
-
-void convertToFinal20Array(uint8_t* o_final20Array,
-                std::vector<int>& i_byteNums,int* i_nibbleSwap)
-{
-    int l_byteIndex;
-    int l_zeroOne;
-
-    for(l_byteIndex = 0; l_byteIndex < 9; l_byteIndex++)
-    {
-        for(l_zeroOne = 0; l_zeroOne < 2; l_zeroOne++)
-        {
-            o_final20Array[(l_byteIndex*2)+l_zeroOne] =
-                    (i_byteNums.at(l_byteIndex)*2) + l_zeroOne;
-        }
-    }
-    //nibble switch now
-    for(int l_nibIndex = 0;l_nibIndex<9;l_nibIndex++)
-    {
-        if(i_nibbleSwap[l_nibIndex] == 1)
-        {
-            char l_placeHolder = o_final20Array[(l_nibIndex*2)];
-            o_final20Array[(l_nibIndex*2)] = o_final20Array[(l_nibIndex*2)+1];
-            o_final20Array[(l_nibIndex*2) + 1] = l_placeHolder;
-        }
-    }
-
-    o_final20Array[18] = 255;
-    o_final20Array[19] = 255;
-}
-
-void decodeISDIMMAttrs(ecmdDataBufferBase& i_dataDQ,
-                ecmdDataBufferBase& i_dataDQS,uint8_t* o_finalArray,
-                uint8_t* o_finalDQSArray)
-{
-    int l_byteArray[9];
-    int l_nibbleSwap[9];
-    int l_nibOrder[18];
-    int l_nibbleSwapDQS[9];
-    int l_byteOrder = getSeparatedInformation(i_dataDQ,i_dataDQS,l_nibbleSwap,
-                    l_nibOrder,l_nibbleSwapDQS);
-    int l_sizeByte = 9;
-    int l_sizeNibble = 4;
-
-    antiPermutation(l_byteOrder,l_byteArray,l_sizeByte);
-    std::vector<int> l_byteAllNumbers;
-    unPermeateToVector(l_byteArray,l_sizeByte,l_byteAllNumbers);
-
-    int l_nibOrderArray[18][4];
-
-    std::vector<std::vector<int> > l_nibToNibAllNums;
-    for(int l_eachNibble=0;l_eachNibble<18;l_eachNibble++)
-    {
-        antiPermutation(l_nibOrder[l_eachNibble],
-                        l_nibOrderArray[l_eachNibble],l_sizeNibble);
-        std::vector<int> l_currentNibToNib;
-        unPermeateToVector(l_nibOrderArray[l_eachNibble],
-                           l_sizeNibble,l_currentNibToNib);
-        l_nibToNibAllNums.push_back(l_currentNibToNib);
-    }
-
-    convertToFinal80Array(o_finalArray,l_byteAllNumbers,
-                    l_nibbleSwap,l_nibToNibAllNums);
-    convertToFinal20Array(o_finalDQSArray,l_byteAllNumbers,l_nibbleSwapDQS);
-}
-
-
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.C b/src/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.C
deleted file mode 100644
index bc33d4578..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.C
+++ /dev/null
@@ -1,98 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getISDIMMTOC4DAttrs.C $       */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getISDIMMTOC4DAttrs.C,v 1.4 2015/04/09 13:36:21 janssens Exp $
-/**
- * @file getISDIMMTOC4DAttrs.C
- *
- * @brief MBvpd accessor for the ATTR_VPD_ISDIMMTOC4DQ and DQS attributes
- */
-
-#include <stdint.h>
-#include <fapi.H>
-#include <getISDIMMTOC4DAttrs.H>
-#include <getDecompressedISDIMMAttrs.H>
-
-extern "C"
-{
-
-using namespace fapi;
-
-fapi::ReturnCode getDQAttribute(const fapi::Target &i_mbTarget,
-                uint32_t i_whichCopy, uint8_t (&o_DQKeyword)[DQ_KEYWORD_SIZE])
-{
-    uint32_t l_DQBufsize = DQ_KEYWORD_SIZE;
-
-    fapi::ReturnCode l_fapirc;
-    fapi::MBvpdKeyword l_DQKey = fapi::MBVPD_KEYWORD_Q1;
-    do{
-        switch(i_whichCopy)
-        {
-            case 1:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q1;
-                break;
-            case 2:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q2;
-                break;
-            case 3:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q3;
-                break;
-            case 4:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q4;
-                break;
-            case 5:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q5;
-                break;
-            case 6:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q6;
-                break;
-            case 7:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q7;
-                break;
-            case 8:
-                l_DQKey = fapi::MBVPD_KEYWORD_Q8;
-                break;
-            default:
-                FAPI_ERR("getISDIMMTOC4DAttrs: Incorrect Data to read DQ keyword, tried to read copy 0x%02x",i_whichCopy);
-                const uint8_t & DQ_COPY = i_whichCopy;
-                FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_DQ_DATA);
-                break;
-        }
-
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_SPDX,
-                                     l_DQKey,
-                                     i_mbTarget,
-                                     (uint8_t *) (&o_DQKeyword),
-                                     l_DQBufsize);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getISDIMMTOC4DAttrs: Read of DQ keyword failed");
-            break;
-        }
-    }while(0);
-    return l_fapirc;
-
-}
-
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.C
deleted file mode 100644
index 41b5c1240..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.C
+++ /dev/null
@@ -1,170 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAddrMirrorData.C $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdAddrMirrorData.C,v 1.5 2014/10/23 22:01:31 dcrowell Exp $
-/**
- *  @file getMBvpdAddrMirrorData.C
- *
- *  @brief get Address Mirroring Data from MBvpd AM keyword
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdAddrMirrorData.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-fapi::ReturnCode getMBvpdAddrMirrorData(
-                              const fapi::Target   &i_mbaTarget,
-                              uint8_t (& o_val)[2][2])
-{
-    //AM keyword layout
-    //The following constants are for readibility. They need to stay in sync
-    //  with the vpd layout.
-    const uint8_t NUM_MBAS =  2;   //There are 2 MBAs per Centaur memory buffer
-    const uint8_t NUM_PORTS = 2;   //Each MBA has 2 ports
-    struct port_attributes
-    {
-       uint8_t iv_dimm ; // bits 0:3 DIMM 0 bits 4:7 DIMM 1
-    };
-    struct mba_attributes
-    {
-        port_attributes mba_port[NUM_PORTS];
-    };
-    struct am_keyword
-    {
-        mba_attributes mb_mba[NUM_MBAS];
-        uint8_t        spare[8]; //VPD data CCIN_31E1_v.5.3.ods
-    };
-    const uint32_t AM_KEYWORD_SIZE = sizeof(am_keyword);  // keyword size
-
-    fapi::ReturnCode l_fapirc;
-    fapi::Target l_mbTarget;
-    uint8_t l_mbaPos = NUM_MBAS; //initialize to out of range value (+1)
-    am_keyword * l_pMaBuffer = NULL; // MBvpd MT keyword buffer
-    uint32_t  l_MaBufsize = sizeof(am_keyword);
-
-    FAPI_DBG("getMBvpdAddrMirrorData: entry ");
-
-    do {
-        // Determine which VPD format we are using
-        uint8_t l_customDimm = 0;
-        l_fapirc=FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM,&i_mbaTarget,l_customDimm);
-        if(l_fapirc)
-        {
-            FAPI_ERR("getMBvpdAddrMirrorData: Read of Custom Dimm failed");
-            break;
-        }
-
-        //if not a custom_dimm then assume ISDIMM
-        if(fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO == l_customDimm)
-        {
-            // Planar CVPD (==ISDIMM) has no AM keyword, by default there is
-            // no mirrored data
-            for (uint8_t l_port=0; l_port<NUM_PORTS; l_port++)
-            {
-                o_val[l_port][0] = 0;
-                o_val[l_port][1] = 0;
-            }
-            break;
-        }
-
-        // find the position of the passed mba on the centuar
-        l_fapirc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,&i_mbaTarget,l_mbaPos);
-        if (l_fapirc)
-        {
-            FAPI_ERR(" getMBvpdAddrMirrorData: Get MBA position failed ");
-            break;  //  break out with fapirc
-        }
-        FAPI_DBG("getMBvpdAddrMirrorData: mba %s position=%d",
-             i_mbaTarget.toEcmdString(),
-             l_mbaPos);
-
-        // find the Centaur memmory buffer from the passed MBA
-        l_fapirc = fapiGetParentChip (i_mbaTarget,l_mbTarget);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdAddrMirrorData: Finding the parent mb failed ");
-            break;  //  break out with fapirc
-        }
-        FAPI_DBG("getMBvpdAddrMirrorData: parent mb path=%s ",
-             l_mbTarget.toEcmdString()  );
-
-        // Read the AM keyword field
-        l_pMaBuffer = new am_keyword;
-
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_AM,
-                                     l_mbTarget,
-                                     reinterpret_cast<uint8_t *>(l_pMaBuffer),
-                                     l_MaBufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdAddrMirrorData: Read of AM keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient AM was returned.
-        if (l_MaBufsize < AM_KEYWORD_SIZE )
-        {
-            FAPI_ERR("getMBvpdAddrMirrorData:"
-                     " less AM keyword returned than expected %d < %d",
-                       l_MaBufsize, AM_KEYWORD_SIZE);
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_AM;
-            const uint32_t & RETURNED_SIZE = l_MaBufsize;
-            const fapi::Target & CHIP_TARGET = l_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-            break;  //  break out with fapirc
-        }
-
-        // Return the 4 bits of address mirroring data for each
-        // of the 4 DIMMs for the requested mba from the AM keyword buffer
-        for (uint8_t l_port=0; l_port<NUM_PORTS; l_port++)
-        {
-            uint8_t l_dimm = l_pMaBuffer->
-                                mb_mba[l_mbaPos].mba_port[l_port].iv_dimm;
-            o_val[l_port][0]= ((l_dimm & 0xF0)>>4);
-            o_val[l_port][1]= l_dimm & 0x0F;
-        }
-
-    } while (0);
-
-    if( l_pMaBuffer )
-    {
-        delete l_pMaBuffer;
-        l_pMaBuffer = NULL;
-    }
-
-    FAPI_DBG("getMBvpdAddrMirrorData: exit rc=0x%08x",
-               static_cast<uint32_t>(l_fapirc));
-    return  l_fapirc;
-}
-
-}   // extern "C"
\ No newline at end of file
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C
deleted file mode 100644
index 499f225af..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C
+++ /dev/null
@@ -1,2045 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdAttr.C,v 1.9 2015/10/06 15:17:45 dcrowell Exp $
-/**
- *  @file getMBvpdAttr.C
- *
- *  @brief get Attribute Data from MBvpd
- *
- */
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <getMBvpdAttr.H>
-#include    <getMBvpdVersion.H>
-
-// Used to ensure attribute enums are equal at compile time
-class Error_ConstantsDoNotMatch;
-template<const bool MATCH> void checkConstantsMatch()
-{
-    Error_ConstantsDoNotMatch();
-}
-template <> inline void checkConstantsMatch<true>() {}
-
-extern "C"
-{
-using   namespace   fapi;
-using   namespace   getAttrData;
-
-// ----------------------------------------------------------------------------
-// local functions
-// ----------------------------------------------------------------------------
-/**
- *  @brief Find attribute definition in global table
- */
-fapi::ReturnCode findAttrDef (const fapi::Target    & i_mbaTarget,
-                              const DimmType        & i_dimmType,
-                              const fapi::AttributeId & i_attr,
-                              const MBvpdAttrDef*   & o_pAttrDef,
-                              const VpdVersion      & i_version);
-/**
- *  @brief Read the attribute keyword
- */
-fapi::ReturnCode readKeyword (const fapi::Target   & i_mbTarget,
-                              const fapi::Target   & i_mbaTarget,
-                              const MBvpdAttrDef   * i_pAttrDef,
-                              const DimmType       & i_dimmType,
-                                    uint8_t        * i_pBuffer,
-                              const uint32_t       & i_bufsize,
-                              const VpdVersion     & i_version);
-/**
- *  @brief return default output value
- */
-fapi::ReturnCode returnDefault (const MBvpdAttrDef    * i_pAttrDef,
-                                        void          * o_pVal,
-                                const size_t          & i_valSize);
-
-/**
- *  @brief Return the output value
- */
-fapi::ReturnCode returnValue (const MBvpdAttrDef    * i_pAttrDef,
-                              const uint8_t         & i_pos,
-                                    void            * o_pVal,
-                              const size_t          & i_valSize,
-                                    uint8_t         * i_pBuffer,
-                              const VpdVersion      & i_version);
-
-// return version from keyword VM or VZ or VD
-fapi::ReturnCode getVersion  (const fapi::Target    & i_mbaTarget,
-                              const DimmType        & i_dimmType,
-                              VpdVersion            & o_version);
-
-
-/**
- *  @brief Translation functions
- */
-fapi::ReturnCode xlate_DRAM_RON (const fapi::AttributeId i_attr,
-                                     uint8_t & io_value);
-fapi::ReturnCode xlate_RTT_NOM  (const fapi::AttributeId i_attr,
-                                     uint8_t & io_value);
-fapi::ReturnCode xlate_RTT_WR   (const fapi::AttributeId i_attr,
-                                     uint8_t & io_value);
-fapi::ReturnCode xlate_WR_VREF  (const fapi::AttributeId i_attr,
-                                     uint32_t & io_value);
-fapi::ReturnCode xlate_RD_VREF  (const fapi::AttributeId i_attr,
-                                     uint32_t & io_value);
-fapi::ReturnCode xlate_SLEW_RATE (const fapi::AttributeId i_attr,
-                                     uint8_t & io_value);
-
-/**
- *  @brief Find the ISDIMM MR keyword
- */
-fapi::ReturnCode FindMRkeyword (const fapi::Target       & i_mbTarget,
-                                      fapi::MBvpdKeyword & o_keyword);
-/**
- *  @brief Find the ISDIMM MT keyword
- */
-fapi::ReturnCode FindMTkeyword (const fapi::Target       & i_mbTarget,
-                                const fapi::Target       & i_mbaTarget,
-                                      fapi::MBvpdKeyword & o_keyword,
-                                const VpdVersion         & i_version);
-
-keywordLayout * layoutFactory :: getLayout(const uint32_t & i_keyword,
-                                           const uint32_t & i_ver)
-{
-    switch(i_ver)
-    {
-        case VM_01:
-        {
-            switch(i_keyword)
-            {
-                case MBVPD_KEYWORD_MT:
-                case MBVPD_KEYWORD_PD1:
-                case MBVPD_KEYWORD_PDZ:
-                case MBVPD_KEYWORD_PD4:
-                case MBVPD_KEYWORD_PD5:
-                case MBVPD_KEYWORD_PD6:
-                case MBVPD_KEYWORD_PD8:
-                case MBVPD_KEYWORD_PDY: { return ( new VM_01_MT_layout());}
-        
-                case MBVPD_KEYWORD_M1:
-                case MBVPD_KEYWORD_M2:
-                case MBVPD_KEYWORD_M3:
-                case MBVPD_KEYWORD_M4:
-                case MBVPD_KEYWORD_M5:
-                case MBVPD_KEYWORD_M6:
-                case MBVPD_KEYWORD_M7:
-                case MBVPD_KEYWORD_M8:
-                case MBVPD_KEYWORD_MR: { return ( new VM_01_MR_layout());}
-                default: return NULL;
-            }
-        }
-        default:
-        {
-            switch(i_keyword)
-            {
-                case MBVPD_KEYWORD_MT:
-                case MBVPD_KEYWORD_T1:
-                case MBVPD_KEYWORD_T2:
-                case MBVPD_KEYWORD_T4:
-                case MBVPD_KEYWORD_T5:
-                case MBVPD_KEYWORD_T6:
-                case MBVPD_KEYWORD_T8:{ return ( new VM_00_MT_layout());}
-                
-                case MBVPD_KEYWORD_M1:
-                case MBVPD_KEYWORD_M2:
-                case MBVPD_KEYWORD_M3:
-                case MBVPD_KEYWORD_M4:
-                case MBVPD_KEYWORD_M5:
-                case MBVPD_KEYWORD_M6:
-                case MBVPD_KEYWORD_M7:
-                case MBVPD_KEYWORD_M8:
-                case MBVPD_KEYWORD_MR: { return ( new VM_00_MR_layout());}
-                default: return NULL;
-            }
-        }
-    }
-}
-
-
-// ----------------------------------------------------------------------------
-// HWP accessor to get MBvpd Attribute Data
-// ----------------------------------------------------------------------------
-fapi::ReturnCode getMBvpdAttr(const fapi::Target   &i_mbaTarget,
-                              const fapi::AttributeId i_attr,
-                              void  * o_pVal,
-                              const size_t i_valSize)
-{
-    fapi::ReturnCode l_fapirc;
-    uint8_t *   l_pBuffer = NULL;
-    uint32_t    l_bufsize = 0;
-
-    FAPI_DBG("getMBvpdAttr: entry attr=0x%02x, size=%d ",
-             i_attr,i_valSize  );
-
-    do
-    {
-        fapi::Target l_mbTarget;
-        uint8_t  l_pos = NUM_PORTS;     //initialize to out of range value (+1)
-        DimmType l_dimmType = ALL_DIMM;
-        const MBvpdAttrDef * l_pAttrDef = NULL;
-        VpdVersion l_version = INVALID_VER; // invalid vpd value
-
-        // find DIMM Info; parent, position, dimm type
-        l_fapirc = findDimmInfo (i_mbaTarget, l_mbTarget, l_pos, l_dimmType);
-        if (l_fapirc)
-        {
-            break; // return with error
-        }
-
-        //read VPD version
-        l_fapirc = getVersion (i_mbaTarget,
-                                   l_dimmType,
-                                   l_version);
-        if (l_fapirc)
-        {
-            FAPI_ERR("findAttrDef: getVersion failed");
-            break;  //  break out with fapirc
-        }
-        // find Attribute definition
-        l_fapirc = findAttrDef (i_mbaTarget, 
-                                l_dimmType, 
-                                i_attr, 
-                                l_pAttrDef, 
-                                l_version);
-        if (l_fapirc)
-        {
-            break; // return with error
-        }
-
-        FAPI_DBG("getMBvpdAttr: attr=0x%08x, dimmType=%d "
-                 "keyword=%d offset=%d outType=0x%04x default=%d ",
-             i_attr,l_dimmType,l_pAttrDef->iv_keyword,l_pAttrDef->iv_offset,
-             l_pAttrDef->iv_outputType,l_pAttrDef->iv_defaultValue  );
-
-        // Either just return defaults or read keyword and return vpd data
-        // Mask off the special processing flags from the output type.
-        if (DEFAULT_VALUE ==
-                        ((l_pAttrDef->iv_outputType) & SPECIAL_PROCESSING_MASK))
-        {
-            l_fapirc = returnDefault (l_pAttrDef,
-                                      o_pVal,
-                                      i_valSize);
-            if (l_fapirc) break; // return with error
-
-        }
-        else
-        {
-            fapi::MBvpdKeyword l_keyword = l_pAttrDef->iv_keyword;
-            uint32_t l_keywordsize =0;
-            keywordLayout * l_kwLayout = layoutFactory::getLayout( l_keyword,
-                                                               l_version);
-            if( l_kwLayout != NULL)
-            {
-                l_keywordsize = l_kwLayout->getKeywordSize();
-            }
-            else
-            {
-                FAPI_ERR("layoutFactory::getLayout:"
-                     " returned NULL pointer for Keyword: 0x%x ,Version :0x%x",
-                       l_keyword, l_version);
-                const fapi::AttributeId & ATTR_ID = i_attr;
-                const uint32_t & KEYWORD = l_keyword;
-                const uint32_t & VERSION = l_version;
-                const uint32_t & DIMM_TYPE = l_dimmType;
-                FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_UNEXPECTED_KEYWORD);
-                break;  //  break out with fapirc
-            }               
-
-            l_pBuffer = new uint8_t[l_keywordsize];
-            l_bufsize = l_keywordsize;
-
-            l_fapirc = readKeyword (l_mbTarget,
-                                    i_mbaTarget,
-                                    l_pAttrDef,
-                                    l_dimmType,
-                                    l_pBuffer,
-                                    l_bufsize,
-                                    l_version);
-            if (l_fapirc) break; // return with error
-            
-            // retrun the output value
-            l_fapirc = returnValue (l_pAttrDef,
-                                    l_pos,
-                                    o_pVal,
-                                    i_valSize,
-                                    l_pBuffer,
-                                    l_version);
-            if (l_fapirc) break; // return with error
-        }
-    }
-    while (0);
-
-    delete l_pBuffer;
-    l_pBuffer = NULL;
-
-    FAPI_DBG("getMBvpdAttr: exit rc=0x%08x",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-
-}
-
-// ----------------------------------------------------------------------------
-// local functions
-// ----------------------------------------------------------------------------
-
-
-// find dimm info; parent, type, position
-fapi::ReturnCode findDimmInfo (const fapi::Target & i_mbaTarget,
-                                     fapi::Target & o_mbTarget,
-                                     uint8_t      & o_pos,
-                                     DimmType     & o_dimmType)
-{
-    fapi::ReturnCode l_fapirc;
-
-    do
-    {
-        // find the position of the passed mba on the centuar
-        l_fapirc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS,&i_mbaTarget,o_pos);
-        if (l_fapirc)
-        {
-            FAPI_ERR(" getMBvpdAttr: Get MBA position failed ");
-            break;  //  break out with fapirc
-        }
-        FAPI_DBG("findDimmInfo: mba %s position=%d",
-             i_mbaTarget.toEcmdString(),
-             o_pos);
-
-        // find the Centaur memmory buffer from the passed MBA
-        l_fapirc = fapiGetParentChip (i_mbaTarget,o_mbTarget);
-        if (l_fapirc)
-        {
-            FAPI_ERR("findDimmInfo: Finding the parent mb failed ");
-            break;  //  break out with fapirc
-        }
-        FAPI_DBG("findDimmInfo: parent path=%s ",
-             o_mbTarget.toEcmdString()  );
-
-        // Determine if ISDIMM or CDIMM
-        std::vector<fapi::Target> l_target_dimm_array;
-
-        l_fapirc = fapiGetAssociatedDimms(i_mbaTarget, l_target_dimm_array);
-        if(l_fapirc)
-        {
-           FAPI_ERR("findDimmInfo: Problem getting DIMMs of MBA");
-           break;   //return error
-        }
-        if(l_target_dimm_array.size() != 0)
-        {
-            uint8_t l_customDimm=0;
-            l_fapirc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM,&l_target_dimm_array[0],
-                          l_customDimm);
-            if(l_fapirc) {
-               FAPI_ERR("findDimmInfo: ATTR_SPD_CUSTOM failed ");
-               break;   //return error
-            }
-
-            if (l_customDimm == fapi::ENUM_ATTR_SPD_CUSTOM_YES)
-            {
-                o_dimmType = CDIMM;
-                FAPI_DBG("findDimmInfo: CDIMM TYPE!!!");
-            }
-            else
-            {
-                o_dimmType = ISDIMM;
-                FAPI_DBG("findDimmInfo: ISDIMM TYPE!!!");
-            }
-        }
-        else
-        {
-           o_dimmType = ISDIMM;
-           FAPI_DBG("findDimmInfo: ISDIMM TYPE (dimm array size = 0)");
-        }
-    }
-    while (0);
-
-    return l_fapirc;
-}
-
-// return version from keyword VM or VZ or VD
-fapi::ReturnCode getVersion  (const fapi::Target    & i_mbaTarget,
-                              const DimmType        & i_dimmType,
-                              VpdVersion            & o_version)
-{
-    fapi::ReturnCode l_fapirc;
-    fapi::Target l_mbTarget;
-    fapi::MBvpdKeyword l_keyword = fapi::MBVPD_KEYWORD_VM;  // try VM first
-    fapi::MBvpdRecord  l_record  = fapi::MBVPD_RECORD_SPDX; // default to SPDX
-    MBvpdVMKeyword l_vmVersionBuf={};
-    uint32_t l_vmBufSize = sizeof(MBvpdVMKeyword); // VM keyword is of 4 bytes.
-    uint16_t l_versionBuf = 0;
-    uint32_t l_bufSize = sizeof(l_versionBuf);
-    bool     l_sizeMismatch = false;  // to track returned size vs expected size
-
-    do
-    {
-        // find the Centaur memory buffer from the passed MBA
-        l_fapirc = fapiGetParentChip (i_mbaTarget,l_mbTarget);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getVersion: Finding the parent mb failed ");
-            break;  //  break out with fapirc
-        }
-
-        if (CDIMM == i_dimmType)
-        {
-            l_record = fapi::MBVPD_RECORD_VSPD;
-        }
-
-        o_version = VM_VER;    // initialize to finding VM keyword
-
-        // try to get VM keyword from SPDX or VSPD
-        l_fapirc = fapiGetMBvpdField(l_record,
-                                     l_keyword,
-                                     l_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_vmVersionBuf),
-                                     l_vmBufSize);
-        if (l_vmBufSize < sizeof(MBvpdVMKeyword))
-        {
-            l_sizeMismatch = true;
-        }
-
-        if((l_fapirc == 0) && (!l_sizeMismatch))
-        {
-            FAPI_DBG("getVersion:"
-                     " returned vm data : 0x%x ",
-                     l_vmVersionBuf.iv_version);
-
-            // Get the first byte from VM keyword which has version value.
-            l_versionBuf = l_vmVersionBuf.iv_version;
-            if(l_versionBuf > VM_SUPPORTED_HIGH_VER)
-            {
-                FAPI_ERR("getVersion:"
-                         " un-supported vm version returned : 0x%x ",
-                         l_versionBuf);
-                const uint32_t & KEYWORD = l_keyword;
-                const uint32_t & RETURNED_VALUE = l_versionBuf;
-                const uint32_t & RECORD_NAME = l_record;
-                const uint32_t & DIMM_TYPE = i_dimmType;
-                const fapi::Target & CHIP_TARGET = l_mbTarget;
-                FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INVALID_VM_VERSION_RETURNED);
-                break;  //  break out with fapirc
-            }
-            else if(l_versionBuf != VM_NOT_SUPPORTED)
-            {
-                o_version = static_cast<VpdVersion>(o_version |
-                                 static_cast<VpdVersion>(l_versionBuf));
-            }
-        }
-        
-        // Get the VD in case of VM read error or 
-        // VM returned size is fine but with  value 0, then the Version is in
-        // VD format.
-        if((l_fapirc) || 
-           ((!l_sizeMismatch) && (l_versionBuf == VM_NOT_SUPPORTED)))    
-        {
-            fapi::ReturnCode l_fapirc2;
-            o_version = VD_VER;    // initialize to finding VD keyword
-            l_keyword = fapi::MBVPD_KEYWORD_VD;
-            l_bufSize = sizeof(l_versionBuf);
-
-            // try to get VD keyword from SPDX or VSPD
-            l_fapirc2 = fapiGetMBvpdField(l_record,
-                                     l_keyword,
-                                     l_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_versionBuf),
-                                     l_bufSize);
-            l_fapirc  = l_fapirc2;   //explicitly free previous error infor
-            if (l_bufSize < sizeof(l_versionBuf))
-            {
-                l_sizeMismatch = true;
-            }
-            else if(l_fapirc == 0)
-            {
-                o_version = static_cast<VpdVersion>(o_version |
-                           static_cast<VpdVersion>(FAPI_BE16TOH(l_versionBuf)));
-            }
-        }
-
-        // try record VINI keyword VZ (should work)
-        if (l_fapirc)
-        {
-            fapi::ReturnCode l_fapirc3;
-
-            o_version = VZ_VER;    // VZ keyword
-            l_record  = fapi::MBVPD_RECORD_VINI;
-            l_keyword = fapi::MBVPD_KEYWORD_VZ;
-            l_bufSize = sizeof(l_versionBuf);
-
-            l_fapirc3 = fapiGetMBvpdField(l_record,
-                                     l_keyword,
-                                     l_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_versionBuf),
-                                     l_bufSize);
-            l_fapirc  = l_fapirc3;   //explicitly free previous error infor
-            if (l_bufSize < sizeof(l_versionBuf))
-            {
-                l_sizeMismatch = true;
-            }
-            else if(l_fapirc == 0)
-            {
-                o_version = static_cast<VpdVersion>(o_version |
-                           static_cast<VpdVersion>(FAPI_BE16TOH(l_versionBuf)));
-            }
-        }
-
-        if (l_fapirc)
-        {
-            FAPI_ERR("getVersion: Read of VM,VD and VZ keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        if (l_sizeMismatch)
-        {
-            FAPI_ERR("getVersion:"
-                     " less keyword data returned than expected %d < %d",
-                       l_bufSize, sizeof(l_versionBuf));
-            const uint32_t & KEYWORD = l_keyword;
-            const uint32_t & RETURNED_SIZE = l_bufSize;
-            const fapi::Target & CHIP_TARGET = l_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-            break;  //  break out with fapirc
-        }
-
-        FAPI_DBG("getVersion: vpd version=0x%x keyword=%d",
-                o_version,l_keyword);
-
-    }
-    while (0);
-
-    return l_fapirc;
-}
-
-// find attribute definition
-// table rules:
-//     Vesions must be in decreasing order (highest first...)
-//        for a specific Dimm Type. The first match found, searching
-//        from row index 0 to the end, will be used.
-fapi::ReturnCode findAttrDef (const fapi::Target    & i_mbaTarget,
-                              const DimmType        & i_dimmType,
-                              const AttributeId     & i_attr,
-                              const MBvpdAttrDef*   & o_pAttrDef,
-                              const VpdVersion      & i_version)
-{
-
-fapi::ReturnCode l_fapirc;
-    o_pAttrDef = NULL;
-
-    // find first row in the attribute defintion table for this attribute
-
-    uint32_t i=0; //at this scope for the debug message at end
-    for (; i < g_MBVPD_ATTR_DEF_array_size; i++)
-    {
-        if ( (g_MBVPD_ATTR_DEF_array[i].iv_attrId == i_attr) &&
-             ((ALL_DIMM   == g_MBVPD_ATTR_DEF_array[i].iv_dimmType) ||
-              (i_dimmType == g_MBVPD_ATTR_DEF_array[i].iv_dimmType)) )
-        {
-
-            // Some of them are expected to be the same for all Dimm Types and versions
-            if (ALL_VER  == g_MBVPD_ATTR_DEF_array[i].iv_version)
-            {
-                o_pAttrDef = &g_MBVPD_ATTR_DEF_array[i];
-                break; //use this row
-            }
-            // If this row is for this version type (VM or VD or VZ)
-            // and is equal or less than the version, then use it
-            if ((g_MBVPD_ATTR_DEF_array[i].iv_version &
-                        (VpdVersion)(ALL_VER & i_version)) &&
-                ((g_MBVPD_ATTR_DEF_array[i].iv_version & VER_MASK) <=
-                 (i_version & VER_MASK)) )
-            {
-                o_pAttrDef = &g_MBVPD_ATTR_DEF_array[i];
-                break; //use this row
-            }
-        }
-    }
-
-    // return an error if definition was not found
-    if (NULL == o_pAttrDef)
-    {
-        if (!l_fapirc) // if no other error found
-        {
-            // Could be due to a table error, which shouldn't happen because
-            // every attribute has an ALL_DIMM ALL_VER entry.
-            // More likely due to an invalid attribute ID being passed.
-            FAPI_ERR("findAttrDef:"
-                     " attr ID 0x%x not in table  dimmType=%d version=%x",
-                      i_attr,
-                      i_dimmType,
-                      i_version);
-            const fapi::AttributeId & ATTR_ID   = i_attr;
-            const DimmType          & DIMM_TYPE = i_dimmType;
-            const VpdVersion        & VERSION   = i_version;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_ATTRIBUTE_NOT_FOUND);
-        }
-    }
-    else
-    {
-        FAPI_DBG("findAttrDef: use attribute definition row=%d",i );
-    }
-
-    return l_fapirc;
-}
-
-// read the attribute keyword
-// note: i_pAttrDef->iv_dimmType is likely ALL_DIMM were as
-//       l_dimmType will be either CDIMM or ISDIMM
-fapi::ReturnCode readKeyword (const fapi::Target   & i_mbTarget,
-                              const fapi::Target   & i_mbaTarget,
-                              const MBvpdAttrDef   * i_pAttrDef,
-                              const DimmType       & i_dimmType,
-                                    uint8_t        * i_pBuffer,
-                              const uint32_t       & i_bufsize,
-                              const VpdVersion     & i_version)
-{
-    fapi::ReturnCode l_fapirc;
-    uint32_t l_bufsize = i_bufsize;
-    uint32_t l_keywordsize = 0;
-    fapi::MBvpdKeyword l_keyword = i_pAttrDef->iv_keyword; //default for CDIMMs
-    fapi::MBvpdRecord  l_record  = MBVPD_RECORD_VSPD;      //default for CDIMMs
-
-    FAPI_DBG("readKeyword: Read keyword %d ",l_keyword);
-    do
-    {
-        if (CDIMM != i_dimmType)
-        {
-            if (MBVPD_KEYWORD_MT == l_keyword)
-            {
-                l_fapirc = FindMTkeyword (i_mbTarget,
-                                          i_mbaTarget,
-                                          l_keyword,
-                                          i_version);
-                if (l_fapirc) break; //return with error
-            }
-            else if (MBVPD_KEYWORD_MR == l_keyword)
-            {
-                l_fapirc = FindMRkeyword (i_mbTarget,
-                                          l_keyword);
-                if (l_fapirc) break; //return with error
-            }
-            else //table error, shouldn't happen
-            {
-                FAPI_ERR("readKeyword: invalid keyword %d for dimmType=%d",
-                      l_keyword,
-                      i_dimmType);
-                const fapi::AttributeId & ATTR_ID = i_pAttrDef->iv_attrId;
-                const fapi::MBvpdKeyword & KEYWORD =  l_keyword;
-                FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_UNEXPECTED_ISDIMM_KEYWORD);
-                break; // return error
-            }
-            l_record  = fapi::MBVPD_RECORD_SPDX;      // for ISDIMMs
-            
-        }
-        else
-        {
-            if(( i_version == VM_01 ) && (MBVPD_KEYWORD_MT == l_keyword))
-            {
-                l_keyword = MBVPD_KEYWORD_PDY;
-            }
-        }
-
-        // Retrieve attribute keyword
-        l_fapirc = fapiGetMBvpdField(l_record,
-                             l_keyword,
-                             i_mbTarget,
-                             reinterpret_cast<uint8_t *>(i_pBuffer),
-                             l_bufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("readKeyword: Read of attr keyword failed");
-            FAPI_ERR("readKeyword:Attribute : 0x%x ,version : 0x%x",
-                     i_pAttrDef->iv_attrId, i_version);
-            FAPI_ERR("readKeyword : Keyword : 0x%x , record 0x%x",
-                           l_keyword , l_record);
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient keyword was returned.
-        if (l_bufsize < i_bufsize )
-        {
-            FAPI_ERR("readKeyword:"
-                     " less keyword returned than expected %d < %d",
-                       l_bufsize, l_keywordsize);
-            const uint32_t & KEYWORD = l_keyword;
-            const uint32_t & RETURNED_SIZE = l_bufsize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-            break;  //  break out with fapirc
-        }
-    }
-    while (0);
-
-    return l_fapirc;
-}
-
-// used by returnValue to consolidate setting invalid size error
-fapi::ReturnCode sizeMismatch (const size_t   i_correctSize,
-                               const size_t   i_inputSize,
-                               const fapi::AttributeId i_attr)
-{
-    fapi::ReturnCode l_fapirc;
-    do
-    {
-        FAPI_ERR("sizeMismatch:"
-                 " output variable size does not match expected %d != %d"
-                 " for attr id=0x%08x",
-                   i_correctSize, i_inputSize, i_attr);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint32_t & EXPECTED_SIZE = i_correctSize;
-        const uint32_t & PASSED_SIZE = i_inputSize;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_OUTPUT_VARIABLE_SIZE);
-    }
-    while (0);
-    return l_fapirc;
-}
-
-
-// return default output value
-fapi::ReturnCode returnDefault (const MBvpdAttrDef  * i_pAttrDef,
-                                void                * o_pVal,
-                                const size_t        & i_valSize)
-{
-    fapi::ReturnCode l_fapirc;
-    uint16_t  l_outputType = i_pAttrDef->iv_outputType & OUTPUT_TYPE_MASK;
-
-    FAPI_DBG("returnDefault: default value outputType=0x%04x ",
-              l_outputType);
-
-    // return default according to the attribute varible type
-    switch (l_outputType)
-    {
-        case UINT8_BY2:        // uint8_t [2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint8_t l_value = (uint8_t)i_pAttrDef->iv_defaultValue;
-
-            (*(UINT8_BY2_t*)o_pVal)[0] = l_value;
-            (*(UINT8_BY2_t*)o_pVal)[1] = l_value;
-            break;
-        }
-
-        case  UINT8_BY2_BY2:     // uint8_t  [2][2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_BY2_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_BY2_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint8_t l_value =  (uint8_t)i_pAttrDef->iv_defaultValue;
-            for (uint8_t l_port=0; l_port<NUM_PORTS;l_port++)
-            {
-                for (uint8_t l_j=0; l_j<NUM_DIMMS; l_j++)
-                {
-                    (*(UINT8_BY2_BY2_t*)o_pVal)[l_port][l_j] = l_value;
-                }
-           }
-           break;
-        }
-
-        case  UINT8_BY2_BY2_BY4: // uint8_t  [2][2][4]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_BY2_BY2_BY4_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_BY2_BY2_BY4_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint8_t l_value = (uint8_t)i_pAttrDef->iv_defaultValue;
-            for (uint8_t l_port=0; l_port<NUM_PORTS;l_port++)
-            {
-                for (uint8_t l_j=0; l_j<NUM_DIMMS; l_j++)
-                {
-                    for (uint8_t l_k=0; l_k<NUM_RANKS; l_k++)
-                    {
-                        (*(UINT8_BY2_BY2_BY4_t*)o_pVal)[l_port][l_j][l_k] =
-                                                                        l_value;
-                    }
-                }
-           }
-           break;
-        }
-
-        case  UINT32_BY2:        // uint32_t [2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT32_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT32_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint32_t l_value = (uint32_t)i_pAttrDef->iv_defaultValue;
-
-            for (uint8_t l_port=0; l_port<2;l_port++)
-            {
-                (*(UINT32_BY2_t*)o_pVal)[l_port] = l_value;
-            }
-            break;
-        }
-
-        case  UINT32_BY2_BY2:        // uint32_t [2][2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT32_BY2_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT32_BY2_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint32_t l_value = (uint32_t)i_pAttrDef->iv_defaultValue;
-
-            for (uint8_t l_port=0; l_port<NUM_PORTS;l_port++)
-            {
-                for (uint8_t l_j=0; l_j<NUM_DIMMS; l_j++)
-                {
-                    (*(UINT32_BY2_BY2_t*)o_pVal)[l_port][l_j] = l_value;
-                }
-            }
-            break;
-        }
-
-        case  UINT64:            // uint64_t
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT64_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT64_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint64_t l_value = (uint64_t)i_pAttrDef->iv_defaultValue;
-            (*(UINT64_t*)o_pVal) = l_value;
-            break ;
-        }
-        default: // Hard to do, but needs to be caught
-            FAPI_ERR("returnDefault: invalid output type 0x%04x for"
-                       " attribute ID 0x%08x",
-                       i_pAttrDef->iv_outputType,
-                       i_pAttrDef->iv_attrId);
-            const fapi::AttributeId & ATTR_ID = i_pAttrDef->iv_attrId;
-            const DimmType & DIMM_TYPE =  i_pAttrDef->iv_dimmType;
-            const uint16_t & OUTPUT_TYPE = i_pAttrDef->iv_outputType;
-            FAPI_SET_HWP_ERROR(l_fapirc,
-                                       RC_MBVPD_DEFAULT_UNEXPECTED_OUTPUT_TYPE);
-            break;  //  break out with fapirc
-    }
-
-    return l_fapirc;
-}
-
-// used by returnValue to consolidate pulling an uint32_t value from vpd based
-// on the size of the data in the vpd layout (uint8_t, uint16_t, or uint32_t).
-uint32_t getUint32 (const uint16_t & i_dataSpecial,
-                          uint8_t *  i_pBuffer)
-{
-    uint32_t o_val = 0;
-
-    if (UINT8_DATA == i_dataSpecial)
-    {
-        o_val = *i_pBuffer;
-    }
-    else if (UINT16_DATA == i_dataSpecial)
-    {
-        o_val = *(i_pBuffer+1);      // LSB
-        o_val |= ((*i_pBuffer)<<8);  // MSB
-    }
-    else
-    {
-        memcpy(&o_val, i_pBuffer, sizeof(o_val));
-        o_val = FAPI_BE32TOH(o_val);
-    }
-
-    return o_val;
-}
-
-// return the output value
-// i_pBuffer will be NULL if the default value is to be used.
-fapi::ReturnCode returnValue (const MBvpdAttrDef*   i_pAttrDef,
-                              const uint8_t         & i_pos,
-                                    void            * o_pVal,
-                              const size_t          & i_valSize,
-                                    uint8_t         * i_pBuffer,
-                              const VpdVersion      & i_version)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t     l_attrOffset = i_pAttrDef->iv_offset;
-    uint32_t l_port_spec_sec_size = 0;
-    uint32_t l_mba_sec_size = 0;
-    fapi::MBvpdKeyword l_keyword = i_pAttrDef->iv_keyword;
-    uint16_t  l_outputType= i_pAttrDef->iv_outputType & OUTPUT_TYPE_MASK;
-    uint16_t  l_special   = i_pAttrDef->iv_outputType & SPECIAL_PROCESSING_MASK;
-
-    FAPI_DBG("returnValue: output offset=0%02x pos=%d outputType=0x%04x"
-              " special=0x%04x ",
-              l_attrOffset,i_pos,l_outputType,l_special);
-   
-    // UINT8 : only 1 value is present, it isn't stored per mba/port
-    if( l_outputType != UINT8 )
-    {
-        keywordLayout * l_kwLayout = layoutFactory::getLayout( l_keyword, 
-                                                           i_version);
-        if( l_kwLayout != NULL)
-        {
-            // Move the pointer to port specific section data
-            i_pBuffer += l_kwLayout->getNonPortHeadSize();
-            l_port_spec_sec_size = l_kwLayout->getPortSectionSize();
-            l_mba_sec_size       = l_port_spec_sec_size * NUM_PORTS;
-        }
-    }
-       
-    // return data according to the attribute varible type
-    switch (l_outputType)
-    {
-        case UINT8_BY2:        // uint8_t [2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-            // pull data from keyword buffer
-            uint8_t l_port0 = *( i_pBuffer + ( i_pos * l_mba_sec_size)
-                                + (0 *  l_port_spec_sec_size) + l_attrOffset);
-            uint8_t l_port1 = *( i_pBuffer + ( i_pos * l_mba_sec_size)
-                                + (1 *  l_port_spec_sec_size) + l_attrOffset);
-
-            switch (l_special)
-            {
-                case LOW_NIBBLE: // return low nibble
-                    l_port0 = l_port0 & 0x0F;
-                    l_port1 = l_port1 & 0x0F;
-                    break;
-
-                case HIGH_NIBBLE: // return high nibble
-                    l_port0 = ((l_port0 & 0xF0)>>4);
-                    l_port1 = ((l_port1 & 0xF0)>>4);
-                    break;
-
-                case PORT00: // return port 0 for both ports 0 and 1
-                    l_port1=l_port0;
-                    break;
-
-                case PORT11: // return port 1 for both ports 0 and 1
-                    l_port0=l_port1;
-                    break;
-
-                case XLATE_SLEW:
-                    l_fapirc = xlate_SLEW_RATE( i_pAttrDef->iv_attrId,l_port0);
-                    if (l_fapirc) break;
-                    l_fapirc = xlate_SLEW_RATE( i_pAttrDef->iv_attrId,l_port1);
-                    if (l_fapirc) break;
-
-                default:
-                     ;      // use data  directly from  keyword buffer
-            }
-            if (l_fapirc) break;
-
-            (*(UINT8_BY2_t*)o_pVal)[0] = l_port0;
-            (*(UINT8_BY2_t*)o_pVal)[1] = l_port1;
-            break;
-        }
-
-        case  UINT8_BY2_BY2:     // uint8_t  [2][2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_BY2_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_BY2_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            for (uint8_t l_port=0; l_port<NUM_PORTS;l_port++)
-            {
-
-                uint8_t l_dimm0 = *( i_pBuffer + ( i_pos * l_mba_sec_size)
-                                  + (l_port *  l_port_spec_sec_size) + l_attrOffset);
-                uint8_t l_dimm1 = 0;
-                if (BOTH_DIMMS == l_special)
-                {
-                    l_dimm1 = l_dimm0; //use vpd value for both DIMMs
-                }
-                else
-                {
-                    l_dimm1 = *( i_pBuffer + ( i_pos * l_mba_sec_size)
-                               + (l_port *  l_port_spec_sec_size) + l_attrOffset+ 1);
-                    switch (l_special)
-                    {
-                        case XLATE_DRAM_RON: // translate
-                            l_fapirc =
-                                  xlate_DRAM_RON(i_pAttrDef->iv_attrId,l_dimm0);
-                            if (l_fapirc) break; //break with error
-                            l_fapirc =
-                                  xlate_DRAM_RON(i_pAttrDef->iv_attrId,l_dimm1);
-                        default:
-                            ;      // use data  directly from  keyword buffer
-                    }
-                }
-                if (l_fapirc)  break; // break with error
-                (*(UINT8_BY2_BY2_t*)o_pVal)[l_port][0] = l_dimm0;
-                (*(UINT8_BY2_BY2_t*)o_pVal)[l_port][1] = l_dimm1;
-           }
-           break;
-        }
-
-        case  UINT8_BY2_BY2_BY4: // uint8_t  [2][2][4]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_BY2_BY2_BY4_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_BY2_BY2_BY4_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint8_t l_value = 0;
-            for (uint8_t l_port=0; l_port<NUM_PORTS;l_port++)
-            {
-                for (uint8_t l_j=0; l_j<NUM_DIMMS; l_j++)
-                {
-                    for (uint8_t l_k=0; l_k<NUM_RANKS; l_k++)
-                    {
-                        l_value = *( i_pBuffer + ( i_pos * l_mba_sec_size)
-                                  + (l_port *  l_port_spec_sec_size) 
-                                  + ( l_attrOffset +(l_j)*NUM_RANKS+l_k));
-                        switch (l_special)
-                        {
-                            case XLATE_RTT_NOM: // translate
-                                l_fapirc=xlate_RTT_NOM(i_pAttrDef->iv_attrId,
-                                                                       l_value);
-                                break;
-                            case XLATE_RTT_WR: // translate
-                                l_fapirc=xlate_RTT_WR(i_pAttrDef->iv_attrId,
-                                                                       l_value);
-                            default:
-                                ;     // use data  directly from  keyword buffer
-                        }
-                        if (l_fapirc)  break; // break with error
-                        (*(UINT8_BY2_BY2_BY4_t*)o_pVal)[l_port][l_j][l_k] =
-                                                                        l_value;
-                    }
-                    if (l_fapirc)  break; // break with error
-                }
-                if (l_fapirc) break; // break with error
-           }
-           break;
-
-        }
-        case  UINT32_BY2:        // uint32_t [2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT32_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT32_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint16_t l_xlateSpecial = SPECIAL_XLATE_MASK & l_special;
-            uint16_t l_dataSpecial  = SPECIAL_DATA_MASK  & l_special;
-            for (uint8_t l_port=0; l_port<2;l_port++)
-            {
-                uint32_t l_value = getUint32 (l_dataSpecial, 
-                        ( i_pBuffer + ( i_pos * l_mba_sec_size) + 
-                          + (l_port *  l_port_spec_sec_size) + l_attrOffset));
-                switch (l_xlateSpecial)
-                {
-                    case XLATE_RD_VREF: // translate
-                        l_fapirc=xlate_RD_VREF(i_pAttrDef->iv_attrId,
-                                                               l_value);
-                        break;
-                    case XLATE_WR_VREF: // translate
-                        l_fapirc=xlate_WR_VREF(i_pAttrDef->iv_attrId,
-                                                               l_value);
-                    default:
-                        ;     // use data  directly from  keyword buffer
-                }
-                if (l_fapirc)  break; // break with error
-                (*(UINT32_BY2_t*)o_pVal)[l_port] = l_value;
-            }
-            break;
-        }
-        case  UINT32_BY2_BY2:        // uint32_t [2][2]
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT32_BY2_BY2_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT32_BY2_BY2_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint16_t l_dataSpecial  = SPECIAL_DATA_MASK  & l_special;
-            uint8_t  l_vpdIncrement = 4; //default to 4 byte vpd field
-            if  (UINT8_DATA == l_dataSpecial)
-            {
-                l_vpdIncrement = 1;     // vpd is only 1 byte
-            }
-            else if  (UINT16_DATA == l_dataSpecial)
-            {
-                l_vpdIncrement = 2;     // vpd is 2 bytes
-            }
-
-            for (uint8_t l_port=0; l_port<2;l_port++)
-            {
-                uint8_t l_vpdOffset = 0;
-                for (uint8_t l_j=0; l_j<NUM_DIMMS; l_j++)
-                {
-                    uint32_t l_value = getUint32 (l_dataSpecial, 
-                          ( i_pBuffer + ( i_pos * l_mba_sec_size) +
-                          + (l_port *  l_port_spec_sec_size) 
-                          + (l_attrOffset+l_vpdOffset)));
-
-                    (*(UINT32_BY2_BY2_t*)o_pVal)[l_port][l_j] = l_value;
-                    l_vpdOffset += l_vpdIncrement;
-                }
-            }
-            break;
-        }
-        case  UINT64:            // uint64_t
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT64_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT64_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            uint64_t l_value = 0;
-            if (MERGE == l_special)
-            {
-                uint32_t l_port0 = getUint32 (UINT32_DATA,
-                         ( i_pBuffer + ( i_pos * l_mba_sec_size) +
-                         + (0 *  l_port_spec_sec_size)+ l_attrOffset));
-                uint32_t l_port1 = getUint32 (UINT32_DATA, 
-                         ( i_pBuffer + ( i_pos * l_mba_sec_size) +
-                         + (1 *  l_port_spec_sec_size)+ l_attrOffset));
-
-                l_value = ( ((static_cast<uint64_t>(l_port0))<<32) |
-                               (static_cast<uint64_t>(l_port1)) );
-            }
-            else
-            {
-                FAPI_ERR("returnValue: invalid output type 0x%04x for"
-                       " attribute ID 0x%08x UINT64_T",
-                       i_pAttrDef->iv_outputType,
-                       i_pAttrDef->iv_attrId);
-                const fapi::AttributeId & ATTR_ID = i_pAttrDef->iv_attrId;
-                const DimmType & DIMM_TYPE =  i_pAttrDef->iv_dimmType;
-                const uint16_t & OUTPUT_TYPE = i_pAttrDef->iv_outputType;
-                FAPI_SET_HWP_ERROR(l_fapirc,
-                                        RC_MBVPD_UINT64_UNEXPECTED_OUTPUT_TYPE);
-                break;  //  break out with fapirc
-            }
-            (*(UINT64_t*)o_pVal) = l_value;
-            break ;
-        }
-        case  UINT8:            // uint8_t
-        {
-            // make sure return value size is correct
-            if (sizeof(UINT8_t) != i_valSize)
-            {
-                l_fapirc = sizeMismatch(sizeof(UINT8_t),
-                                        i_valSize,
-                                        i_pAttrDef->iv_attrId);
-                break; //return with error
-            }
-
-            // only 1 value is present, it isn't stored per mba/port
-            uint8_t l_value = (reinterpret_cast<uint8_t*>(i_pBuffer))[l_attrOffset];
-            (*(UINT8_t*)o_pVal) = l_value;
-            break ;
-        }
-        default: // Hard to do, but needs to be caught
-            FAPI_ERR("returnValue: invalid output type 0x%04x for"
-                       " attribute ID 0x%08x",
-                       i_pAttrDef->iv_outputType,
-                       i_pAttrDef->iv_attrId);
-            const fapi::AttributeId & ATTR_ID = i_pAttrDef->iv_attrId;
-            const DimmType & DIMM_TYPE =  i_pAttrDef->iv_dimmType;
-            const uint16_t & OUTPUT_TYPE = i_pAttrDef->iv_outputType;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_UNEXPECTED_OUTPUT_TYPE);
-            break;  //  break out with fapirc
-    }
-    return l_fapirc;
-}
-
-// ----------------------------------------------------------------------------
-// Translate vpd values to attribute enumeration for ATTR_VPD_DRAM_RON
-// ----------------------------------------------------------------------------
-fapi::ReturnCode xlate_DRAM_RON (const fapi::AttributeId i_attr,
-                                     uint8_t & io_value)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t VPD_DRAM_RON_INVALID = 0x00;
-    const uint8_t VPD_DRAM_RON_OHM34 = 0x07;
-    const uint8_t VPD_DRAM_RON_OHM40 = 0x03;
-
-    switch (io_value)
-    {
-    case VPD_DRAM_RON_INVALID:
-        io_value=fapi::ENUM_ATTR_VPD_DRAM_RON_INVALID;
-        break;
-    case VPD_DRAM_RON_OHM34:
-        io_value=fapi::ENUM_ATTR_VPD_DRAM_RON_OHM34;
-        break;
-    case VPD_DRAM_RON_OHM40:
-        io_value=fapi::ENUM_ATTR_VPD_DRAM_RON_OHM40;
-        break;
-    default:
-        FAPI_ERR("Unsupported VPD encode for ATTR_VPD_DRAM_RON 0x%02x",
-                 io_value);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint8_t  & VPD_VALUE = io_value;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_TERM_DATA_UNSUPPORTED_VPD_ENCODE);
-        break;
-    }
-
-    return  l_fapirc;
-}
-
-// ----------------------------------------------------------------------------
-// Translate vpd values to attribute enumeration for ATTR_VPD_DRAM_RTT_NOM
-// ----------------------------------------------------------------------------
-fapi::ReturnCode xlate_RTT_NOM (const fapi::AttributeId i_attr,
-                                         uint8_t & io_value)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t DRAM_RTT_NOM_DISABLE = 0x00;
-    const uint8_t DRAM_RTT_NOM_OHM20 = 0x04;
-    const uint8_t DRAM_RTT_NOM_OHM30 = 0x05;
-    const uint8_t DRAM_RTT_NOM_OHM34 = 0x07;
-    const uint8_t DRAM_RTT_NOM_OHM40 = 0x03;
-    const uint8_t DRAM_RTT_NOM_OHM48 = 0x85;
-    const uint8_t DRAM_RTT_NOM_OHM60 = 0x01;
-    const uint8_t DRAM_RTT_NOM_OHM80 = 0x06;
-    const uint8_t DRAM_RTT_NOM_OHM120 = 0x02;
-    const uint8_t DRAM_RTT_NOM_OHM240 = 0x84;
-
-    switch(io_value)
-    {
-    case DRAM_RTT_NOM_DISABLE:
-        io_value=fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_DISABLE;
-        break;
-    case DRAM_RTT_NOM_OHM20:
-        io_value= fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM20;
-        break;
-    case DRAM_RTT_NOM_OHM30:
-        io_value= fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM30;
-        break;
-    case DRAM_RTT_NOM_OHM34:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM34;
-        break;
-    case DRAM_RTT_NOM_OHM40:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM40;
-        break;
-    case DRAM_RTT_NOM_OHM48:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM48;
-        break;
-    case DRAM_RTT_NOM_OHM60:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM60;
-        break;
-    case DRAM_RTT_NOM_OHM80:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM80;
-        break;
-    case DRAM_RTT_NOM_OHM120:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM120;
-        break;
-    case DRAM_RTT_NOM_OHM240:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_RTT_NOM_OHM240;
-        break;
-    default:
-        FAPI_ERR("Unsupported VPD encode for ATTR_VPD_DRAM_RTT_NOM 0x%02x",
-                    io_value);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint8_t  & VPD_VALUE = io_value;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_TERM_DATA_UNSUPPORTED_VPD_ENCODE);
-        break;
-    }
-
-    return  l_fapirc;
-}
-
-// ----------------------------------------------------------------------------
-// Translate vpd values to attribute enumeration for ATTR_VPD_DRAM_RTT_WR
-// ----------------------------------------------------------------------------
-fapi::ReturnCode xlate_RTT_WR (const fapi::AttributeId i_attr,
-                                        uint8_t & io_value)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t DRAM_RTT_WR_DISABLE = 0x00;
-    const uint8_t DRAM_RTT_WR_OHM60   = 0x01;
-    const uint8_t DRAM_RTT_WR_OHM120  = 0x02;
-
-    switch(io_value)
-    {
-    case DRAM_RTT_WR_DISABLE:
-        io_value=fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_DISABLE;
-        break;
-    case DRAM_RTT_WR_OHM60:
-        io_value= fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM60;
-        break;
-    case DRAM_RTT_WR_OHM120:
-        io_value= fapi::ENUM_ATTR_VPD_DRAM_RTT_WR_OHM120;
-        break;
-    default:
-        FAPI_ERR("Unsupported VPD encode for ATTR_VPD_DRAM_RTT_WR 0x%02x",
-                    io_value);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint8_t  & VPD_VALUE = io_value;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_TERM_DATA_UNSUPPORTED_VPD_ENCODE);
-        break;
-    }
-
-    return  l_fapirc;
-}
-
-// ----------------------------------------------------------------------------
-// Translate vpd values to attribute enumeration for ATTR_VPD_DRAM_WR_VREF
-// ----------------------------------------------------------------------------
-fapi::ReturnCode xlate_WR_VREF (const fapi::AttributeId i_attr,
-                                         uint32_t & io_value)
-{
-    fapi::ReturnCode l_fapirc;
-    // The following intentionally skips 0x0a..0x0f, 0x1a..0x1f, and 0x2a..0x2f
-    const uint8_t WR_VREF_VDD420 = 0x00;
-    const uint8_t WR_VREF_VDD425 = 0x01;
-    const uint8_t WR_VREF_VDD430 = 0x02;
-    const uint8_t WR_VREF_VDD435 = 0x03;
-    const uint8_t WR_VREF_VDD440 = 0x04;
-    const uint8_t WR_VREF_VDD445 = 0x05;
-    const uint8_t WR_VREF_VDD450 = 0x06;
-    const uint8_t WR_VREF_VDD455 = 0x07;
-    const uint8_t WR_VREF_VDD460 = 0x08;
-    const uint8_t WR_VREF_VDD465 = 0x09;
-    const uint8_t WR_VREF_VDD470 = 0x10;
-    const uint8_t WR_VREF_VDD475 = 0x11;
-    const uint8_t WR_VREF_VDD480 = 0x12;
-    const uint8_t WR_VREF_VDD485 = 0x13;
-    const uint8_t WR_VREF_VDD490 = 0x14;
-    const uint8_t WR_VREF_VDD495 = 0x15;
-    const uint8_t WR_VREF_VDD500 = 0x16;
-    const uint8_t WR_VREF_VDD505 = 0x17;
-    const uint8_t WR_VREF_VDD510 = 0x18;
-    const uint8_t WR_VREF_VDD515 = 0x19;
-    const uint8_t WR_VREF_VDD520 = 0x20;
-    const uint8_t WR_VREF_VDD525 = 0x21;
-    const uint8_t WR_VREF_VDD530 = 0x22;
-    const uint8_t WR_VREF_VDD535 = 0x23;
-    const uint8_t WR_VREF_VDD540 = 0x24;
-    const uint8_t WR_VREF_VDD545 = 0x25;
-    const uint8_t WR_VREF_VDD550 = 0x26;
-    const uint8_t WR_VREF_VDD555 = 0x27;
-    const uint8_t WR_VREF_VDD560 = 0x28;
-    const uint8_t WR_VREF_VDD565 = 0x29;
-    const uint8_t WR_VREF_VDD570 = 0x30;
-    const uint8_t WR_VREF_VDD575 = 0x31;
-
-    switch(io_value)
-    {
-    case WR_VREF_VDD420:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD420;
-        break;
-    case WR_VREF_VDD425:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD425;
-        break;
-    case WR_VREF_VDD430:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD430;
-        break;
-    case WR_VREF_VDD435:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD435;
-        break;
-    case WR_VREF_VDD440:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD440;
-        break;
-    case WR_VREF_VDD445:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD445;
-        break;
-    case WR_VREF_VDD450:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD450;
-        break;
-    case WR_VREF_VDD455:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD455;
-        break;
-    case WR_VREF_VDD460:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD460;
-        break;
-    case WR_VREF_VDD465:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD465;
-        break;
-    case WR_VREF_VDD470:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD470;
-        break;
-    case WR_VREF_VDD475:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD475;
-        break;
-    case WR_VREF_VDD480:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD480;
-        break;
-    case WR_VREF_VDD485:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD485;
-        break;
-    case WR_VREF_VDD490:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD490;
-        break;
-    case WR_VREF_VDD495:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD495;
-        break;
-    case WR_VREF_VDD500:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD500;
-        break;
-    case WR_VREF_VDD505:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD505;
-        break;
-    case WR_VREF_VDD510:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD510;
-        break;
-    case WR_VREF_VDD515:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD515;
-        break;
-    case WR_VREF_VDD520:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD520;
-        break;
-    case WR_VREF_VDD525:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD525;
-        break;
-    case WR_VREF_VDD530:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD530;
-        break;
-    case WR_VREF_VDD535:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD535;
-        break;
-    case WR_VREF_VDD540:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD540;
-        break;
-    case WR_VREF_VDD545:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD545;
-        break;
-    case WR_VREF_VDD550:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD550;
-        break;
-    case WR_VREF_VDD555:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD555;
-        break;
-    case WR_VREF_VDD560:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD560;
-        break;
-    case WR_VREF_VDD565:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD565;
-        break;
-    case WR_VREF_VDD570:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD570;
-        break;
-    case WR_VREF_VDD575:
-        io_value = fapi::ENUM_ATTR_VPD_DRAM_WR_VREF_VDD575;
-        break;
-    default:
-        FAPI_ERR("Unsupported VPD encode for ATTR_VPD_DRAM_WR_VREF 0x%08x",
-                    io_value);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint32_t  & VPD_VALUE = io_value;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_TERM_DATA_UNSUPPORTED_VPD_ENCODE);
-        break;
-    }
-    return  l_fapirc;
-}
-
-// ----------------------------------------------------------------------------
-// Translate vpd values to attribute enumeration for ATTR_VPD_CEN_RD_VREF
-// ----------------------------------------------------------------------------
-fapi::ReturnCode xlate_RD_VREF (const fapi::AttributeId i_attr,
-                                        uint32_t & io_value)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t RD_VREF_VDD61000 = 0x15;
-    const uint8_t RD_VREF_VDD59625 = 0x14;
-    const uint8_t RD_VREF_VDD58250 = 0x13;
-    const uint8_t RD_VREF_VDD56875 = 0x12;
-    const uint8_t RD_VREF_VDD55500 = 0x11;
-    const uint8_t RD_VREF_VDD54125 = 0x10;
-    const uint8_t RD_VREF_VDD52750 = 0x09;
-    const uint8_t RD_VREF_VDD51375 = 0x08;
-    const uint8_t RD_VREF_VDD50000 = 0x07;
-    const uint8_t RD_VREF_VDD48625 = 0x06;
-    const uint8_t RD_VREF_VDD47250 = 0x05;
-    const uint8_t RD_VREF_VDD45875 = 0x04;
-    const uint8_t RD_VREF_VDD44500 = 0x03;
-    const uint8_t RD_VREF_VDD43125 = 0x02;
-    const uint8_t RD_VREF_VDD41750 = 0x01;
-    const uint8_t RD_VREF_VDD40375 = 0x00;
-    const uint8_t RD_VREF_VDD81000 = 0x31;
-    const uint8_t RD_VREF_VDD79625 = 0x30;
-    const uint8_t RD_VREF_VDD78250 = 0x29;
-    const uint8_t RD_VREF_VDD76875 = 0x28;
-    const uint8_t RD_VREF_VDD75500 = 0x27;
-    const uint8_t RD_VREF_VDD74125 = 0x26;
-    const uint8_t RD_VREF_VDD72750 = 0x25;
-    const uint8_t RD_VREF_VDD71375 = 0x24;
-    const uint8_t RD_VREF_VDD70000 = 0x23;
-    const uint8_t RD_VREF_VDD68625 = 0x22;
-    const uint8_t RD_VREF_VDD67250 = 0x21;
-    const uint8_t RD_VREF_VDD65875 = 0x20;
-    const uint8_t RD_VREF_VDD64500 = 0x19;
-    const uint8_t RD_VREF_VDD63125 = 0x18;
-    const uint8_t RD_VREF_VDD61750 = 0x17;
-    const uint8_t RD_VREF_VDD60375 = 0x16;
-
-    switch(io_value)
-    {
-    case RD_VREF_VDD61000:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD61000;
-        break;
-    case RD_VREF_VDD59625:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD59625;
-        break;
-    case RD_VREF_VDD58250:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD58250;
-        break;
-    case RD_VREF_VDD56875:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD56875;
-        break;
-    case RD_VREF_VDD55500:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD55500;
-        break;
-    case RD_VREF_VDD54125:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD54125;
-        break;
-    case RD_VREF_VDD52750:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD52750;
-        break;
-    case RD_VREF_VDD51375:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD51375;
-        break;
-    case RD_VREF_VDD50000:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD50000;
-        break;
-    case RD_VREF_VDD48625:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD48625;
-        break;
-    case RD_VREF_VDD47250:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD47250;
-        break;
-    case RD_VREF_VDD45875:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD45875;
-        break;
-    case RD_VREF_VDD44500:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD44500;
-        break;
-    case RD_VREF_VDD43125:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD43125;
-        break;
-    case RD_VREF_VDD41750:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD41750;
-        break;
-    case RD_VREF_VDD40375:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD40375;
-        break;
-    case RD_VREF_VDD81000:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD81000;
-        break;
-    case RD_VREF_VDD79625:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD79625;
-        break;
-    case RD_VREF_VDD78250:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD78250;
-        break;
-    case RD_VREF_VDD76875:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD76875;
-        break;
-    case RD_VREF_VDD75500:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD75500;
-        break;
-    case RD_VREF_VDD74125:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD74125;
-        break;
-    case RD_VREF_VDD72750:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD72750;
-        break;
-    case RD_VREF_VDD71375:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD71375;
-        break;
-    case RD_VREF_VDD70000:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD70000;
-        break;
-    case RD_VREF_VDD68625:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD68625;
-        break;
-    case RD_VREF_VDD67250:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD67250;
-        break;
-    case RD_VREF_VDD65875:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD65875;
-        break;
-    case RD_VREF_VDD64500:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD64500;
-        break;
-    case RD_VREF_VDD63125:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD63125;
-        break;
-    case RD_VREF_VDD61750:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD61750;
-        break;
-    case RD_VREF_VDD60375:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_RD_VREF_VDD60375;
-        break;
-    default:
-        FAPI_ERR("Unsupported VPD encode for ATTR_VPD_CEN_RD_VREF 0x%08x",
-                    io_value);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint32_t  & VPD_VALUE = io_value;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_TERM_DATA_UNSUPPORTED_VPD_ENCODE);
-        break;
-    }
-    return  l_fapirc;
-}
-
-// ----------------------------------------------------------------------------
-// Translate vpd values to attribute enumeration for
-//   ATTR_VPD_CEN_SLEW_RATE_DQ_DQS
-//   ATTR_VPD_CEN_SLEW_RATE_ADDR
-//   ATTR_VPD_CEN_SLEW_RATE_CLK
-//   ATTR_VPD_CEN_SLEW_RATE_SPCKE
-//   ATTR_VPD_CEN_SLEW_RATE_CNTL
-// They all have the same mapping and can share a translation procedure
-// ----------------------------------------------------------------------------
-fapi::ReturnCode xlate_SLEW_RATE (const fapi::AttributeId i_attr,
-                                     uint8_t & io_value)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t SLEW_RATE_3V_NS = 0x03;
-    const uint8_t SLEW_RATE_4V_NS = 0x04;
-    const uint8_t SLEW_RATE_5V_NS = 0x05;
-    const uint8_t SLEW_RATE_6V_NS = 0x06;
-    const uint8_t SLEW_RATE_MAXV_NS = 0x0F;
-
-//  Ensure that the enums are equal so that one routine can be shared
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_3V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_3V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS==
-                       (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_3V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_3V_NS>();
-
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_4V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_4V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS==
-                       (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_4V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_4V_NS>();
-
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_5V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_5V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_5V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_5V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_5V_NS==
-                       (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_5V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_5V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_5V_NS>();
-
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_6V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_6V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_6V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_6V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_6V_NS==
-                       (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_6V_NS>();
-    checkConstantsMatch<(uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_6V_NS==
-                        (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_6V_NS>();
-
-    checkConstantsMatch<
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_MAXV_NS==
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_ADDR_SLEW_MAXV_NS>();
-    checkConstantsMatch<
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_MAXV_NS==
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CLK_SLEW_MAXV_NS>();
-    checkConstantsMatch<
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_MAXV_NS==
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_SPCKE_SLEW_MAXV_NS>();
-    checkConstantsMatch<
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_MAXV_NS==
-                     (uint8_t)ENUM_ATTR_VPD_CEN_SLEW_RATE_CNTL_SLEW_MAXV_NS>();
-
-    switch(io_value)
-    {
-    case SLEW_RATE_3V_NS:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_3V_NS;
-        break;
-    case SLEW_RATE_4V_NS:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_4V_NS;
-        break;
-    case SLEW_RATE_5V_NS:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_5V_NS;
-        break;
-    case SLEW_RATE_6V_NS:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_6V_NS;
-        break;
-    case SLEW_RATE_MAXV_NS:
-        io_value = fapi::ENUM_ATTR_VPD_CEN_SLEW_RATE_DQ_DQS_SLEW_MAXV_NS;
-        break;
-    default:
-         FAPI_ERR("Unsupported VPD encode for ATTR_VPD_CEN_SLEW_RATE 0x%02x",
-                    io_value);
-        const fapi::AttributeId & ATTR_ID = i_attr;
-        const uint8_t  & VPD_VALUE = io_value;
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_TERM_DATA_UNSUPPORTED_VPD_ENCODE);
-        break;
-    }
-
-    return  l_fapirc;
-}
-
-// Determine ISDMM MR keyword to use
-fapi::ReturnCode FindMRkeyword (const fapi::Target       & i_mbTarget,
-                                      fapi::MBvpdKeyword & o_keyword)
-{
-    fapi::ReturnCode l_fapirc;
-    const uint8_t l_M0_KEYWORD_SIZE = 32;
-    uint8_t l_m0_keyword[l_M0_KEYWORD_SIZE];
-    uint32_t l_M0Bufsize = l_M0_KEYWORD_SIZE;
-
-    do
-    {
-
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_SPDX,
-                                     fapi::MBVPD_KEYWORD_M0,
-                                     i_mbTarget,
-                                     (uint8_t *)(&l_m0_keyword),
-                                     l_M0Bufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("FindMRkeyword: Read of M0 keyword failed");
-            break;  //  break out with fapirc
-        }
-        if (l_M0_KEYWORD_SIZE > l_M0Bufsize)
-        {
-            FAPI_ERR("FindMRkeyword:"
-                     " less M0 keyword returned than expected %d < %d",
-                       l_M0Bufsize, l_M0_KEYWORD_SIZE);
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_M0;
-            const uint32_t & RETURNED_SIZE = l_M0Bufsize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-            break;  //  break out with fapirc
-        }
-
-        uint8_t l_index = 0;
-        l_fapirc = FAPI_ATTR_GET(ATTR_ISDIMM_MBVPD_INDEX,&i_mbTarget,
-                                    l_index);
-        if(l_fapirc)
-        {
-            FAPI_ERR("FindMRkeyword: read of ISDIMM MBVPD Index failed");
-            break;
-        }
-        if (l_M0_KEYWORD_SIZE < l_index)
-        {
-            FAPI_ERR("unsupported MBVPD index : 0x%02x",l_index);
-            const uint8_t & M0_DATA = l_index;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_M0_DATA);
-            break;
-        }
-
-        o_keyword = fapi::MBVPD_KEYWORD_M1;
-
-        uint8_t l_actualM0Data = l_m0_keyword[l_index];
-
-        switch (l_actualM0Data)
-        {
-            case 1:
-                o_keyword = fapi::MBVPD_KEYWORD_M1;
-                break;
-            case 2:
-                o_keyword = fapi::MBVPD_KEYWORD_M2;
-                break;
-            case 3:
-                o_keyword = fapi::MBVPD_KEYWORD_M3;
-                break;
-            case 4:
-                o_keyword = fapi::MBVPD_KEYWORD_M4;
-                break;
-            case 5:
-                o_keyword = fapi::MBVPD_KEYWORD_M5;
-                break;
-            case 6:
-                o_keyword = fapi::MBVPD_KEYWORD_M6;
-                break;
-            case 7:
-                o_keyword = fapi::MBVPD_KEYWORD_M7;
-                break;
-            case 8:
-                o_keyword = fapi::MBVPD_KEYWORD_M8;
-                break;
-            default:
-                FAPI_ERR("Incorrect M0 data : 0x%02x",l_actualM0Data);
-                const uint8_t & M0_DATA = l_actualM0Data;
-                FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_M0_DATA);
-                break;
-        }
-
-    }
-    while (0);
-    if (!l_fapirc)
-    {
-        FAPI_DBG ("FindMRkeyword: use MR keyword %d",o_keyword);
-    }
-
-    return  l_fapirc;
-}
-
-// Determine ISDMM MT keyword to use
-fapi::ReturnCode FindMTkeyword (const fapi::Target       & i_mbTarget,
-                                const fapi::Target       & i_mbaTarget,
-                                      fapi::MBvpdKeyword & o_keyword,
-                                const VpdVersion         & i_version)
-{
-    fapi::ReturnCode l_fapirc;
-    do
-    {
-        //MT keyword is located in the SPDX record,
-        //and found by using ATTR_SPD_NUM_RANKS
-        //T1: one dimm, rank 1  T2: one dimm, rank 2   T3: one dimm, rank 4
-        //T5: two dimm, rank 1  T6: two dimm, rank 2   T8: two dimm, rank 4
-        fapi::ATTR_SPD_NUM_RANKS_Type l_spd_dimm_ranks[2][2] = {
-                {fapi::ENUM_ATTR_SPD_NUM_RANKS_RX,
-                fapi::ENUM_ATTR_SPD_NUM_RANKS_RX},
-                {fapi::ENUM_ATTR_SPD_NUM_RANKS_RX,
-                fapi::ENUM_ATTR_SPD_NUM_RANKS_RX}
-        };
-        uint8_t l_mba_port;
-        uint8_t l_mba_dimm;
-
-        std::vector<fapi::Target> l_target_dimm_array;
-        l_fapirc = fapiGetAssociatedDimms(i_mbaTarget, l_target_dimm_array,
-                                              fapi::TARGET_STATE_PRESENT);
-        if(l_fapirc)
-        {
-            FAPI_ERR("FindMTkeyword: read of Associated Dimms failed");
-            break;
-        }
-
-        for(uint8_t l_dimm_index=0; l_dimm_index<l_target_dimm_array.size();
-                    l_dimm_index+=1)
-        {
-            l_fapirc = FAPI_ATTR_GET(ATTR_MBA_PORT,
-                            &l_target_dimm_array[l_dimm_index],
-                            l_mba_port);
-            if(l_fapirc)
-            {
-                FAPI_ERR("FindMTkeyword: read of ATTR_MBA_PORT failed");
-                break;
-            }
-            l_fapirc = FAPI_ATTR_GET(ATTR_MBA_DIMM,
-                            &l_target_dimm_array[l_dimm_index],
-                            l_mba_dimm);
-            if(l_fapirc)
-            {
-                FAPI_ERR("FindMTkeyword: read of ATTR_MBA_DIMM failed");
-                break;
-            }
-
-            l_fapirc = FAPI_ATTR_GET(ATTR_SPD_NUM_RANKS,
-                            &l_target_dimm_array[l_dimm_index],
-                            l_spd_dimm_ranks[l_mba_port][l_mba_dimm]);
-            if(l_fapirc)
-            {
-                FAPI_ERR("FindMTkeyword: read of ATTR_SPD_NUM_RANKS failed");
-                break;
-            }
-        }
-        if(l_fapirc)
-        {
-            break;
-        }
-
-        fapi::ATTR_SPD_NUM_RANKS_Type l_rankCopy =
-          fapi::ENUM_ATTR_SPD_NUM_RANKS_RX;
-        uint8_t l_dimmInvalid = 0;
-        bool l_double_drop = false;
-        /* Mismatched rank numbers between the paired ports is an error
-         * that should deconfigure the parent MBA so the data for that
-         * MBA should never be fetched. The same is for mismatched slot 1
-         * and slot 0 on the same port
-         */
-
-        //single or double drop
-        if( (l_spd_dimm_ranks[0][1] == fapi::ENUM_ATTR_SPD_NUM_RANKS_RX)
-          && (l_spd_dimm_ranks[1][1] == fapi::ENUM_ATTR_SPD_NUM_RANKS_RX) )
-        {
-            //if the two match, it's a valid case.
-            if(l_spd_dimm_ranks[0][0] == l_spd_dimm_ranks[1][0])
-            {
-                //0000, set to 1
-                if(l_spd_dimm_ranks[0][0]
-                   == fapi::ENUM_ATTR_SPD_NUM_RANKS_RX)
-                {
-                    l_rankCopy = 1;
-                    //throwing error for all empty
-                    FAPI_ERR("FindMTkeyword: No dimm's found");
-                    const uint8_t DIMM_P0S0 = l_spd_dimm_ranks[0][0];
-                    const uint8_t DIMM_P0S1 = l_spd_dimm_ranks[0][1];
-                    const uint8_t DIMM_P1S0 = l_spd_dimm_ranks[1][0];
-                    const uint8_t DIMM_P1S1 = l_spd_dimm_ranks[1][1];
-                    FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_DIMMS_NOT_FOUND);
-                    break;
-
-                //either 0101,0202,0404.
-                }
-                else
-                {
-                    l_rankCopy = l_spd_dimm_ranks[0][0];
-                }
-            }
-            else
-            {
-                //throwing error for invalid dimm combination
-                l_dimmInvalid = 1;
-            }
-        //if all 4 are the same, its double ranked
-        } else if(l_spd_dimm_ranks[0][1] == l_spd_dimm_ranks[0][0] &&
-                    l_spd_dimm_ranks[1][1] == l_spd_dimm_ranks[1][0] &&
-                    l_spd_dimm_ranks[0][1] == l_spd_dimm_ranks[1][1])
-        {
-            //either 1111,2222,4444
-            l_rankCopy = l_spd_dimm_ranks[0][0];
-            l_double_drop = true;
-        }
-        else
-        {
-            //throwing error for invalid dimm combination
-            l_dimmInvalid = 1;
-        }
-
-        if(l_dimmInvalid)
-        {
-            FAPI_ERR("There is an invalid combination of dimm's found");
-            const uint8_t INVALID_DIMM_P0S0 = l_spd_dimm_ranks[0][0];
-            const uint8_t INVALID_DIMM_P0S1 = l_spd_dimm_ranks[0][1];
-            const uint8_t INVALID_DIMM_P1S0 = l_spd_dimm_ranks[1][0];
-            const uint8_t INVALID_DIMM_P1S1 = l_spd_dimm_ranks[1][1];
-            const fapi::Target & MBA = i_mbaTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_DIMM_FOUND);
-            break;
-        }
-
-        switch (l_rankCopy)
-        {
-            case fapi::ENUM_ATTR_SPD_NUM_RANKS_R1:
-                if( l_double_drop ) {
-                    if(i_version == VM_01){
-                        o_keyword = fapi::MBVPD_KEYWORD_PD5;
-                    } else {
-                        o_keyword = fapi::MBVPD_KEYWORD_T5;
-                    }
-                } else {
-                    if(i_version == VM_01){
-                        o_keyword = fapi::MBVPD_KEYWORD_PD1;
-                    } else {
-                        o_keyword = fapi::MBVPD_KEYWORD_T1;
-                    }
-                }
-                break;
-            case fapi::ENUM_ATTR_SPD_NUM_RANKS_R2:
-                if( l_double_drop ) {
-                    if(i_version == VM_01){
-                        o_keyword = fapi::MBVPD_KEYWORD_PD6;
-                    } else {
-                        o_keyword = fapi::MBVPD_KEYWORD_T6;
-                    }
-                } else {
-                    if(i_version == VM_01){
-                        o_keyword = fapi::MBVPD_KEYWORD_PDZ;
-                    } else {
-                        o_keyword = fapi::MBVPD_KEYWORD_T2;
-                    }
-                }
-                break;
-            case fapi::ENUM_ATTR_SPD_NUM_RANKS_R4:
-                if( l_double_drop ) {
-                    if(i_version == VM_01){
-                        o_keyword = fapi::MBVPD_KEYWORD_PD8;
-                    } else {
-                        o_keyword = fapi::MBVPD_KEYWORD_T8;
-                    }
-                } else {
-                    if(i_version == VM_01){
-                        o_keyword = fapi::MBVPD_KEYWORD_PD4;
-                    } else {
-                        o_keyword = fapi::MBVPD_KEYWORD_T4;
-                    }
-                }
-                break;
-            default:
-                FAPI_ERR("Invalid dimm rank : 0x%02x",l_rankCopy);
-                const uint8_t & RANK_NUM = l_rankCopy;
-                FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_MT_DATA);
-                break;
-        }
-
-    }
-    while (0);
-       
-    if (!l_fapirc)
-    {
-        FAPI_DBG ("FindMTkeyword: use MT keyword %d",o_keyword);
-    }
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C
deleted file mode 100644
index 27fd1d821..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C
+++ /dev/null
@@ -1,227 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C $          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdAttrData.C,v 1.7 2015/09/30 20:44:12 janssens Exp $
-/**
- *  @file getMBvpdAttrData.C
- *
- *  @brief get Attribute Data from MBvpd
- *
- */
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdAttr.H>
-
-using   namespace   fapi;
-using   namespace   getAttrData;
-
-namespace fapi
-{
-namespace getAttrData
-{
-
-// ----------------------------------------------------------------------------
-// Attribute definition table
-// ----------------------------------------------------------------------------
-
-const MBvpdAttrDef g_MBVPD_ATTR_DEF_array [] =
-{
-
-//----------------------------------------------------------------------------------
-// Attribute exceptions to use with SPDX or VSPD VM keyword
-// Note: Ideally, all new exception will be in this section and be for both
-//       ISDIMMs and CDIMMMs
-//----------------------------------------------------------------------------------
-    {ATTR_VPD_MR_VERSION_BYTE,ALL_DIMM,VM_01,MBVPD_KEYWORD_MR,0,UINT8,0},
-    {ATTR_VPD_MR_DATA_CONTROL_BYTE,ALL_DIMM,VM_01,MBVPD_KEYWORD_MR,1,UINT8,0},
-    {ATTR_VPD_MT_VERSION_BYTE,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,0,UINT8,0},
-    {ATTR_VPD_MT_DATA_CONTROL_BYTE,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,1,UINT8,0},
-    {ATTR_VPD_PERIODIC_MEMCAL_MODE_OPTIONS,ALL_DIMM,VM_01,MBVPD_KEYWORD_MR,50,UINT32_BY2|UINT16_DATA,0},
-    {ATTR_VPD_DRAM_RTT_PARK,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,10,UINT8_BY2_BY2_BY4|XLATE_RTT_WR,0},
-    {ATTR_VPD_RD_CTR_WINDAGE_OFFSET,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,64,UINT32_BY2|UINT16_DATA,0},
-
-    {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,68,UINT8_BY2_BY2|DEFAULT_VALUE,0},
-    {ATTR_VPD_DIMM_RCD_IBT,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,66,UINT32_BY2_BY2|DEFAULT_VALUE,0},
-    {ATTR_VPD_CEN_RD_VREF,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,34,UINT32_BY2|UINT8_DATA|XLATE_RD_VREF,0},
-    {ATTR_VPD_DRAM_WR_VREF,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,35,UINT32_BY2|UINT8_DATA|XLATE_WR_VREF,0},
-    {ATTR_VPD_DRAM_WRDDR4_VREF,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,36,UINT8_BY2,0},
-    {ATTR_VPD_CEN_RCV_IMP_DQ_DQS,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,37,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_DQ_DQS,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,38,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_CNTL,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,39,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_ADDR,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,40,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_CLK,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,41,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_SPCKE,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,42,UINT8_BY2,0},
-    {ATTR_VPD_CEN_SLEW_RATE_DQ_DQS,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,43,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_CNTL,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,44,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_ADDR,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,45,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_CLK,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,46,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_SPCKE,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,47,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CKE_PRI_MAP,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,48,UINT32_BY2|UINT16_DATA,0},
-    {ATTR_VPD_CKE_PWR_MAP,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,50,UINT64|MERGE,0},
-    {ATTR_VPD_RLO,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,54,UINT8_BY2|LOW_NIBBLE,0},
-    {ATTR_VPD_WLO,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,54,UINT8_BY2|HIGH_NIBBLE,0},
-    {ATTR_VPD_GPO,ALL_DIMM,VM_01,MBVPD_KEYWORD_MT,55,UINT8_BY2,0},
-
-//----------------------------------------------------------------------------------
-// Attribute exceptions to use with SPDX or VSPD VD keyword
-// Note: Ideally, all new exception will be in this section and be for both
-//       ISDIMMs and CDIMMMs
-//----------------------------------------------------------------------------------
-    {ATTR_VPD_DIMM_RCD_IBT,ALL_DIMM,VD_01,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|UINT8_DATA,0},
-    {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ALL_DIMM,VD_01,MBVPD_KEYWORD_MT,36,UINT8_BY2_BY2|BOTH_DIMMS,0},
-    {ATTR_VPD_DRAM_WR_VREF,ALL_DIMM,VD_01,MBVPD_KEYWORD_MT,38,UINT32_BY2|UINT8_DATA|XLATE_WR_VREF,0},
-
-//----------------------------------------------------------------------------------
-// Attribute exceptions to use with VINI VZ keyword
-// All entries should select either ISDIMM or CDIMM since both used the VZ keyword
-// Note: Ideally, there will be no more additions in this section as all future
-//       DIMMs will use the VD keword
-//----------------------------------------------------------------------------------
-
-// Planar ISDIMM changes
-// Need to include these exceptions to support early Palmetto and Habanero without the VD keyword & VZ=13
-    {ATTR_VPD_DIMM_RCD_IBT,ISDIMM,VZ_13,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|UINT8_DATA,0},
-    {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ISDIMM,VZ_13,MBVPD_KEYWORD_MT,36,UINT8_BY2_BY2|BOTH_DIMMS,0},
-    // Create 3 reserved bytes in V13
-    {ATTR_VPD_DRAM_WR_VREF,ISDIMM,VZ_13,MBVPD_KEYWORD_MT,38,UINT32_BY2|UINT8_DATA|XLATE_WR_VREF,0},
-// Need to include these exceptions to support early Palmetto and Habanero with VZ=11 and 10
-    {ATTR_VPD_DIMM_RCD_IBT,ISDIMM,ALL_VZ,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|DEFAULT_VALUE,0x64},
-    {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ISDIMM,ALL_VZ,MBVPD_KEYWORD_MT,35,UINT8_BY2_BY2|DEFAULT_VALUE,1},
-
-// CDIMM changes in V60 (ascii 10)
-// Need to include these exceptions to support pre DD 2.0 centaurs
-    {ATTR_VPD_TSYS_ADR,CDIMM,VZ_10,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT00,0},
-    {ATTR_VPD_TSYS_ADR,CDIMM,ALL_VZ,MBVPD_KEYWORD_MR,51,UINT8_BY2|PORT00,0},
-
-    {ATTR_VPD_TSYS_DP18,CDIMM,VZ_10,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT11,0},
-    {ATTR_VPD_TSYS_DP18,CDIMM,ALL_VZ,MBVPD_KEYWORD_MR,51,UINT8_BY2|PORT11,0},
-
-    {ATTR_VPD_RLO,CDIMM,VZ_10,MBVPD_KEYWORD_MT,60,UINT8_BY2|LOW_NIBBLE,0},
-    {ATTR_VPD_RLO,CDIMM,ALL_VZ,MBVPD_KEYWORD_MR,49,UINT8_BY2|LOW_NIBBLE,0},
-
-    {ATTR_VPD_WLO,CDIMM,VZ_10,MBVPD_KEYWORD_MT,60,UINT8_BY2|HIGH_NIBBLE,0},
-    {ATTR_VPD_WLO,CDIMM,ALL_VZ,MBVPD_KEYWORD_MR,49,UINT8_BY2|HIGH_NIBBLE,0},
-
-    {ATTR_VPD_GPO,CDIMM,VZ_10,MBVPD_KEYWORD_MT,61,UINT8_BY2,0},
-    {ATTR_VPD_GPO,CDIMM,ALL_VZ,MBVPD_KEYWORD_MR,50,UINT8_BY2,0},
-
-//----------------------------------------------------------------------------------
-// Base Term Data definitions to be used if no other version exceptions
-// All entries to be ALL_DIMM ALL_VER
-// Note: No changes are expected in this section
-//----------------------------------------------------------------------------------
-// Base Term Data definitions to be used if no version exceptions
-    {ATTR_VPD_DRAM_RON,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,0,UINT8_BY2_BY2|XLATE_DRAM_RON,0},
-    {ATTR_VPD_DRAM_RTT_NOM,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,2,UINT8_BY2_BY2_BY4|XLATE_RTT_NOM,0},
-    {ATTR_VPD_DRAM_RTT_WR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,10,UINT8_BY2_BY2_BY4|XLATE_RTT_WR,0},
-    {ATTR_VPD_ODT_RD,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,18,UINT8_BY2_BY2_BY4,0},
-    {ATTR_VPD_ODT_WR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,26,UINT8_BY2_BY2_BY4,0},
-    {ATTR_VPD_DIMM_RCD_OUTPUT_TIMING,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,36,UINT8_BY2_BY2|DEFAULT_VALUE,0},
-    {ATTR_VPD_DIMM_RCD_IBT,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,34,UINT32_BY2_BY2|DEFAULT_VALUE,0},
-    {ATTR_VPD_CEN_RD_VREF,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,37,UINT32_BY2|UINT8_DATA|XLATE_RD_VREF,0},
-    {ATTR_VPD_DRAM_WR_VREF,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,38,UINT32_BY2|XLATE_WR_VREF,0},
-    {ATTR_VPD_DRAM_WRDDR4_VREF,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,42,UINT8_BY2,0},
-    {ATTR_VPD_CEN_RCV_IMP_DQ_DQS,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,43,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_DQ_DQS,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,44,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_CNTL,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,45,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_ADDR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,46,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_CLK,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,47,UINT8_BY2,0},
-    {ATTR_VPD_CEN_DRV_IMP_SPCKE,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,48,UINT8_BY2,0},
-    {ATTR_VPD_CEN_SLEW_RATE_DQ_DQS,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,49,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_CNTL,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,50,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_ADDR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,51,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_CLK,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,52,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CEN_SLEW_RATE_SPCKE,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,53,UINT8_BY2|XLATE_SLEW,0},
-    {ATTR_VPD_CKE_PRI_MAP,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,54,UINT32_BY2|UINT16_DATA,0},
-    {ATTR_VPD_CKE_PWR_MAP,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,56,UINT64|MERGE,0},
-    {ATTR_VPD_RLO,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,60,UINT8_BY2|LOW_NIBBLE,0},
-    {ATTR_VPD_WLO,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,60,UINT8_BY2|HIGH_NIBBLE,0},
-    {ATTR_VPD_GPO,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MT,61,UINT8_BY2,0},
-
-// Base Phase Rotator definitions to be used if no version exceptions
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,0,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CLK_P1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,1,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,2,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CLK_P1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,3,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,4,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,5,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,6,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,7,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A4,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,8,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A5,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,9,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A6,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,10,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A7,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,11,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A8,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,12,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A9,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,13,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A10,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,14,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A11,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,15,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A12,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,16,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A13,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,17,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A14,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,18,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_A15,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,19,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,20,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,21,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_BA2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,22,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_CASN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,23,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_RASN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,24,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_CMD_WEN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,25,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_PAR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,26,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M_ACTN,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,27,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,28,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,29,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,30,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CKE3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,31,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,32,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,33,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,34,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_CSN3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,35,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,36,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M0_CNTL_ODT1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,37,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,38,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,39,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,40,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CKE3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,41,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,42,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,43,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN2,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,44,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_CSN3,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,45,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT0,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,46,UINT8_BY2,0},
-    {ATTR_VPD_CEN_PHASE_ROT_M1_CNTL_ODT1,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,47,UINT8_BY2,0},
-    {ATTR_VPD_DRAM_2N_MODE_ENABLED,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,48,UINT8_BY2,0},
-    {ATTR_VPD_TSYS_ADR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT00,0},
-    {ATTR_VPD_TSYS_DP18,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT11,0},
-
-// Membuf-level data that is stored within MR
-    {ATTR_VPD_POWER_CONTROL_CAPABLE,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,253,UINT8,0},
-};
-
-const uint32_t g_MBVPD_ATTR_DEF_array_size =
-    sizeof(g_MBVPD_ATTR_DEF_array) /
-    sizeof(MBvpdAttrDef);
-
-}   // namespace getAttrData
-}   // namespace fapi
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.C
deleted file mode 100644
index b5b4b95ad..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.C
+++ /dev/null
@@ -1,98 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdDram2NModeEnabled.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdDram2NModeEnabled.C,v 1.4 2014/12/11 13:35:35 whs Exp $
-/**
- *  @file getMBvpdDram2NModeEnabled.C
- *
- *  @brief get the Dram 2N Mode value from MBvpd keyword MR
- *         and return whether 2N mode is enabled
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdDram2NModeEnabled.H>
-#include    <getMBvpdAttr.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-fapi::ReturnCode getMBvpdDram2NModeEnabled(
-                              const fapi::Target   &i_mbaTarget,
-                              uint8_t  & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-    uint8_t l_dram2NMode [2] = {0,0};
-
-    FAPI_DBG("getMBvpdDram2NModeEnabled: entry ");
-
-    do {
-        // Retrieve the Dram 2N Mode from the MR keyword
-        FAPI_EXEC_HWP(l_fapirc,
-                      getMBvpdAttr,
-                      i_mbaTarget,
-                      fapi::ATTR_VPD_DRAM_2N_MODE_ENABLED,
-                      &l_dram2NMode,
-                      sizeof(l_dram2NMode));
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdDram2NModeEnabled: Read of VZ keyword failed");
-            break;  //  break out with fapirc
-        }
-        // ensure values match
-        if (l_dram2NMode[0] != l_dram2NMode[1]) {
-            FAPI_ERR("getMBvpdDram2NModeEnabled:"
-                     " ports should have same value 0x%02x != 0x%02x",
-                     l_dram2NMode[0],l_dram2NMode[1]);
-            const uint32_t & PORT0 = l_dram2NMode[0];
-            const uint32_t & PORT1 = l_dram2NMode[1];
-            const fapi::Target & MBA_TARGET = i_mbaTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_DRAM_2N_MODE_NOT_EQUAL);
-            break;  //  break out with fapirc
-        }
-        // return value
-        const uint8_t DRAM_2N_MODE  = 0x02;
-        if (DRAM_2N_MODE == l_dram2NMode[0] )
-        {
-            o_val=fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_TRUE;
-        }
-        else
-        {
-            o_val=fapi::ENUM_ATTR_VPD_DRAM_2N_MODE_ENABLED_FALSE;
-        }
-
-    } while (0);
-
-    FAPI_DBG("getMBvpdDram2NModeEnabled: exit rc=0x%08x)",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.C
deleted file mode 100644
index 2f83fa234..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.C
+++ /dev/null
@@ -1,172 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdMemoryDataVersion.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdMemoryDataVersion.C,v 1.3 2015/10/06 15:18:04 dcrowell Exp $
-/**
- *  @file getMBvpdMemoryDataVersion.C
- *
- *  @brief get the Memory Data version from MBvpd record SPDX keyword VM
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdMemoryDataVersion.H>
-#include    <fapiSystemConfig.H>
-#include    <getMBvpdAttr.H>
-extern "C"
-{
-using   namespace   fapi;
-using   namespace   getAttrData;
-
-fapi::ReturnCode getMBvpdMemoryDataVersion(
-                              const fapi::Target   &i_mbTarget,
-                              uint32_t  & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-    DimmType l_dimmType = ISDIMM;
-    fapi::MBvpdRecord  l_record  = fapi::MBVPD_RECORD_SPDX;
-    uint32_t l_vpdMemoryDataVersion = VM_KEYWORD_DEFAULT_VALUE;   
-    uint32_t l_bufSize = sizeof(l_vpdMemoryDataVersion);
-
-    FAPI_DBG("getMBvpdMemoryDataVersion: entry ");
-
-    do {
-        
-        FAPI_DBG("getMBvpdMemoryDataVersion: Membuff path=%s ",
-             i_mbTarget.toEcmdString()  );
-
-        // Find the dimm type 
-        // Determine if ISDIMM or CDIMM
-
-        // Find one mba target for passing it to fapiGetAssociatedDimms
-        std::vector<fapi::Target> l_mba_chiplets;
-        l_fapirc = fapiGetChildChiplets( i_mbTarget ,
-                        fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets );
-        if((l_fapirc) || (l_mba_chiplets.size() == 0))
-        {
-           FAPI_ERR("getMBvpdMemoryDataVersion: Problem getting MBA's of Membuff");
-           break;   //return error
-        }
-        
-        std::vector<fapi::Target> l_target_dimm_array;
-        l_fapirc = fapiGetAssociatedDimms(l_mba_chiplets[0], l_target_dimm_array);
-        if(l_fapirc)
-        {
-           FAPI_ERR("getMBvpdMemoryDataVersion: Problem getting DIMMs of Membuff");
-           break;   //return error
-        }
-        if(l_target_dimm_array.size() != 0)
-        {
-            uint8_t l_customDimm=0;
-            l_fapirc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM,&l_target_dimm_array[0],
-                          l_customDimm);
-            if(l_fapirc) {
-               FAPI_ERR("getMBvpdMemoryDataVersion: ATTR_SPD_CUSTOM failed ");
-               break;   //return error
-            }
-
-            if (l_customDimm == fapi::ENUM_ATTR_SPD_CUSTOM_YES)
-            {
-                l_dimmType = CDIMM;
-                FAPI_DBG("getMBvpdMemoryDataVersion: CDIMM TYPE!!!");
-            }
-            else
-            {
-                l_dimmType = ISDIMM;
-                FAPI_DBG("getMBvpdMemoryDataVersion: ISDIMM TYPE!!!");
-            }
-        }
-        else
-        {
-           l_dimmType = ISDIMM;
-           FAPI_DBG("getMBvpdMemoryDataVersion: ISDIMM TYPE (dimm array size = 0)");
-        }
-       
-        if( l_dimmType == CDIMM)
-        {
-            l_record = fapi::MBVPD_RECORD_VSPD;
-        }
-
-        // get Memory Data  version from record VSPD/SPDX keyword VM
-        l_fapirc = fapiGetMBvpdField(l_record,
-                                     fapi::MBVPD_KEYWORD_VM,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_vpdMemoryDataVersion),
-                                     l_bufSize);
-        if (l_fapirc)
-        {
-            FAPI_DBG("getMBvpdMemoryDataVersion: Returning default"
-                        " as VM keyword read failed.");
-            l_fapirc = FAPI_RC_SUCCESS;  // Lets make it success and return default
-            break;  //  break out and return
-        }
-
-        // Check that sufficient size was returned.
-        if (l_bufSize < sizeof(l_vpdMemoryDataVersion) )
-        {
-            FAPI_ERR("getMBvpdMemoryDataVersion:"
-                     " less keyword data returned than expected %d < %d",
-                       l_bufSize, sizeof(l_vpdMemoryDataVersion));
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_VM;
-            const uint32_t & RETURNED_SIZE = l_bufSize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-            break;  //  break out with fapirc
-        }
-                    
-        // Check if the format byte in the value returned is in between valid range
-        if (( ((MBvpdVMKeyword *)(&l_vpdMemoryDataVersion))->iv_version >  VM_SUPPORTED_HIGH_VER )||
-            ( ((MBvpdVMKeyword *)(&l_vpdMemoryDataVersion))->iv_version == VM_NOT_SUPPORTED ))
-        {
-            FAPI_ERR("getMBvpdMemoryDataVersion:"
-                     " keyword data returned is invalid : %d ",
-                       l_vpdMemoryDataVersion);
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_VM;
-            const uint32_t & RETURNED_VALUE = l_vpdMemoryDataVersion;
-            const uint32_t & RECORD_NAME = l_record;
-            const uint32_t & DIMM_TYPE = l_dimmType;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INVALID_VM_DATA_RETURNED);
-            break;  //  break out with fapirc
-        }
-        // return value
-        o_val = static_cast<uint32_t>(FAPI_BE16TOH(l_vpdMemoryDataVersion));
-
-        FAPI_DBG("getMBvpdMemoryDataVersion: Memory Data version=0x%08x",
-                o_val);
-
-
-    } while (0);
-
-    FAPI_DBG("getMBvpdMemoryDataVersion: exit rc=0x%08x)",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.C
deleted file mode 100644
index b5b8b2b92..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.C
+++ /dev/null
@@ -1,69 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.C $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdRing.C,v 1.1 2013/10/09 20:52:37 mjjones Exp $
-/**
- *  @file getMBvpdRing.C
- *
- *  @brief function to fetch repair rings from MBVPD  records
- *
- */
-
-#include    <stdint.h>
-#include    <fapi.H> //  fapi support
-#include    <getMBvpdRing.H>
-#include    <mvpdRingFuncs.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-// getMBvpdRing: Wrapper to call common function mbvpdRingFunc
-fapi::ReturnCode getMBvpdRing(fapi::MBvpdRecord   i_record,
-                              fapi::MBvpdKeyword  i_keyword,
-                              const fapi::Target &i_fapiTarget,
-                              const uint8_t       i_chipletId,
-                              const uint8_t       i_ringId,
-                              uint8_t             *i_pRingBuf,
-                              uint32_t            &io_rRingBufsize)
-{
-    fapi::ReturnCode  l_fapirc;
-
-    FAPI_INF("getMBvpdRing: entry ringId=0x%x, chipletId=0x%x, size=0x%x",
-             i_ringId, i_chipletId, io_rRingBufsize );
-
-    // Pass the parameters into mbvpdRingFunc
-    l_fapirc = mbvpdRingFunc(MBVPD_RING_GET,
-                            i_record,
-                            i_keyword,
-                            i_fapiTarget,
-                            i_chipletId,
-                            i_ringId,
-                            i_pRingBuf,
-                            io_rRingBufsize );
-
-    FAPI_INF("getMBvpdRing: exit rc=0x%x", static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.H b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.H
deleted file mode 100644
index abde02fde..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.H
+++ /dev/null
@@ -1,93 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdRing.H $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdRing.H,v 1.1 2013/10/09 20:53:03 mjjones Exp $
-/**
- *  @file getMBvpdRing.H
- *
- *  @brief Prototype for getMBvpdRing() -
- *          get a repair ring from a MBVPD record
- */
-
- #ifndef    _HWP_GETMBVPDRING_
- #define    _HWP_GETMBVPDRING_
-
- #include   <fapi.H>
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*getMBvpdRing_FP_t)
-     (fapi::MBvpdRecord,fapi::MBvpdKeyword,const fapi::Target &,
-      const uint8_t, const uint8_t, uint8_t *, uint32_t &);
-
-
-extern "C"
-{
-/**
- * @brief  get specified ring from MBVPD for the specified memory buffer target.
- *
- * A Ring Id Chiplet Id should be unique in the mbvpd record.
- * The code does not validate. No assumption should be made on which would
- * be returned if there are multiple.
- *
- * @param i_record          -   Record enumerator
- * @param i_keyword         -   Keyword enumerator
- * Supported Rings are:
- *                   MBVPD_RECORD_VSPD - MBVPD_KEYWORD_PDD
- * @param i_fapiTarget      -   memory buffer target
- * @param i_chipletId       -   Chiplet ID
- * @param i_ringId          -   Ring ID
- * @param i_pRingBuf        -   pointer to a buffer allocated by the caller
- *                              to receive the ring header and data.
- *                              if NULL, the size of the min buffer required
- *                              buffer will be returned in io_rRingBufsize
- *                              with rc FAPI_RC_SUCCESS.
- * @param io_rRingBufsize   -   in:     size of ring buffer that caller has
- *                                      allocated
- *                              out:    number of BYTES that were copied to the
- *                                      output buffer.
- *                                      If the ring was not found, an error
- *                                      will be returned and this will be 0.
- *                                      If the output buffer is not big enough,
- *                                      an error will be returned and this will
- *                                      be the minimum size required.
- *                              The buffer contains the CompressedScanData
- *                              structure followed by compressed data. The
- *                              caller does compression and decompression.
- *  Buffer:   io_rRingBufsize returns xNN.
- *    byte x0  CompressedScanData structure (rs4 header)
- *    byte x18 compressed data (sizeof CompressedScanData is 0x18)
- *    byte xNN last byte of compressed data
- *
- * @return fapi::ReturnCode -   FAPI_RC_SUCCESS if success,
- *                              relevant error code for failure.
- */
-fapi::ReturnCode getMBvpdRing(  fapi::MBvpdRecord   i_record,
-                                fapi::MBvpdKeyword  i_keyword,
-                                const fapi::Target  &i_fapiTarget,
-                                const uint8_t       i_chipletId,
-                                const uint8_t       i_ringId,
-                                uint8_t             *io_pRingBuf,
-                                uint32_t            &io_rRingBufsize );
-
-}
-
-#endif
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.C
deleted file mode 100644
index 0dace4805..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.C
+++ /dev/null
@@ -1,157 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSPDXRecordVersion.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdSPDXRecordVersion.C,v 1.2 2015/09/29 20:55:54 janssens Exp $
-/**
- *  @file getMBvpdSPDXRecordVersion.C
- *
- *  @brief get the SPDX record version from MBvpd record SPDX keyword VD
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdSPDXRecordVersion.H>
-#include    <fapiSystemConfig.H>
-#include    <getMBvpdAttr.H>
-
-extern "C"
-{
-using   namespace   fapi;
-using   namespace   getAttrData;
-
-fapi::ReturnCode getMBvpdSPDXRecordVersion(
-                              const fapi::Target   &i_mbTarget,
-                              uint32_t  & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-    DimmType l_dimmType = ISDIMM;
-    fapi::MBvpdRecord  l_record  = fapi::MBVPD_RECORD_SPDX;
-    uint16_t l_vpdSPDXRecordVersion = VD_KEYWORD_DEFAULT_VALUE;
-    uint32_t l_bufSize = sizeof(l_vpdSPDXRecordVersion);
-
-    FAPI_DBG("getMBvpdSPDXRecordVersion: entry ");
-
-    do {
-
-        FAPI_DBG("getMBvpdSPDXRecordVersion: Membuff  path=%s ",
-             i_mbTarget.toEcmdString()  );
-
-        // Find the dimm type
-        // Determine if ISDIMM or CDIMM
-
-        // Find one mba target for passing it to fapiGetAssociatedDimms
-        std::vector<fapi::Target> l_mba_chiplets;
-        l_fapirc = fapiGetChildChiplets( i_mbTarget ,
-                        fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets );
-        if((l_fapirc) || (l_mba_chiplets.size() == 0))
-        {
-           FAPI_ERR("getMBvpdSPDXRecordVersion: Problem getting MBA's of Membuff");
-           break;   //return error
-        }
-
-        std::vector<fapi::Target> l_target_dimm_array;
-        l_fapirc = fapiGetAssociatedDimms(l_mba_chiplets[0], l_target_dimm_array);
-        if(l_fapirc)
-        {
-           FAPI_ERR("getMBvpdSPDXRecordVersion: Problem getting DIMMs of Membuff");
-           break;   //return error
-        }
-        if(l_target_dimm_array.size() != 0)
-        {
-            uint8_t l_customDimm=0;
-            l_fapirc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM,&l_target_dimm_array[0],
-                          l_customDimm);
-            if(l_fapirc) {
-               FAPI_ERR("getMBvpdSPDXRecordVersion: ATTR_SPD_CUSTOM failed ");
-               break;   //return error
-            }
-
-            if (l_customDimm == fapi::ENUM_ATTR_SPD_CUSTOM_YES)
-            {
-                l_dimmType = CDIMM;
-                FAPI_DBG("getMBvpdSPDXRecordVersion: CDIMM TYPE!!!");
-            }
-            else
-            {
-                l_dimmType = ISDIMM;
-                FAPI_DBG("getMBvpdSPDXRecordVersion: ISDIMM TYPE!!!");
-            }
-        }
-        else
-        {
-           l_dimmType = ISDIMM;
-           FAPI_DBG("getMBvpdSPDXRecordVersion: ISDIMM TYPE (dimm array size = 0)");
-        }
-
-        if(l_dimmType == CDIMM)
-        {
-            l_record = fapi::MBVPD_RECORD_VSPD;
-        }
-
-        // get version from record SPDX/VSPD keyword VD
-        l_fapirc = fapiGetMBvpdField(l_record,
-                                     fapi::MBVPD_KEYWORD_VD,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_vpdSPDXRecordVersion),
-                                     l_bufSize);
-        if (l_fapirc)
-        {
-            FAPI_DBG("getMBvpdSPDXRecordVersion: Returning default "
-                                  "as VD keyword read failed");
-            l_fapirc = FAPI_RC_SUCCESS;  // Lets make it success and return default
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient size was returned.
-        if (l_bufSize < sizeof(l_vpdSPDXRecordVersion) )
-        {
-            FAPI_ERR("getMBvpdSPDXRecordVersion:"
-                     " less keyword data returned than expected %d < %d",
-                       l_bufSize, sizeof(l_vpdSPDXRecordVersion));
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_VD;
-            const uint32_t & RETURNED_SIZE = l_bufSize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-            break;  //  break out with fapirc
-        }
-        // return value
-        o_val = static_cast<uint32_t>(FAPI_BE16TOH(l_vpdSPDXRecordVersion));
-
-        FAPI_DBG("getMBvpdSPDXRecordVersion: SPDX Record version=0x%08x",
-                o_val);
-
-
-    } while (0);
-
-    FAPI_DBG("getMBvpdSPDXRecordVersion: exit rc=0x%08x)",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.C
deleted file mode 100644
index 020b3e281..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.C
+++ /dev/null
@@ -1,129 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSensorMap.C $         */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdSensorMap.C,v 1.2 2014/02/12 22:11:52 mjjones Exp $
-
-/**
- * @file getMBvpdSensorMap.C
- *
- * @brief Return primary and secondary sensor map from cvpd record VSPD
- *        keyword MW for attributes:
- *
- *        ATTR_VPD_CDIMM_SENSOR_MAP_PRIMARY
- *        ATTR_VPD_CDIMM_SENSOR_MAP_SECONDARY
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <getMBvpdSensorMap.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-fapi::ReturnCode getMBvpdSensorMap(
-                    const        fapi::Target &i_mbTarget,
-                    const        fapi::MBvpdSensorMap i_attr,
-                    uint8_t      &o_val)
-
-{
-    fapi::ReturnCode l_fapirc;
-
-    //MW keyword layout
-    struct mw_keyword
-    {
-        uint8_t     MWKeywordVersion;
-        uint8_t     masterPowerSlope_MSB;     //big endian order
-        uint8_t     masterPowerSlope_LSB;
-        uint8_t     masterPowerIntercept_MSB; //big endian order
-        uint8_t     masterPowerIntercept_LSB;
-        uint8_t     reserved[4];
-        uint8_t     tempSensorPrimaryLayout;
-        uint8_t     tempSensorSecondaryLayout;
-    };
-    const uint32_t MW_KEYWORD_SIZE = sizeof(mw_keyword);  // keyword size
-
-    mw_keyword * l_pMwBuffer = NULL; // MBvpd MW keyword buffer
-    uint32_t  l_MwBufsize = sizeof(mw_keyword);
-
-    FAPI_DBG("getMBvpdSensorMap: entry ");
-
-    do {
-
-        l_pMwBuffer = new mw_keyword;
-
-        // Read the MW keyword field
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_MW,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(l_pMwBuffer),
-                                     l_MwBufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdSensorMap: Read of MV keyword failed");
-            break;  //  break out with fapirc
-        }
-        // Check that sufficient MW keyword was returned.
-        if (l_MwBufsize < MW_KEYWORD_SIZE )
-        {
-            FAPI_ERR("getMBvpdSensorMap:"
-                     " less MW keyword returned than expected %d < %d",
-                       l_MwBufsize, MW_KEYWORD_SIZE);
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_MW;
-            const uint32_t & RETURNED_SIZE = l_MwBufsize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-            break;  //  break out with fapirc
-        }
-
-        // Return requested value
-        switch (i_attr)
-        {
-           case SENSOR_MAP_PRIMARY:
-               o_val = l_pMwBuffer->tempSensorPrimaryLayout;
-               break;
-           case SENSOR_MAP_SECONDARY:
-               o_val = l_pMwBuffer->tempSensorSecondaryLayout;
-               break;
-           default: // Hard to do, but needs to be caught
-               FAPI_ERR("getMBvpdSensorMap: invalid attribute ID 0x%02x",
-                       i_attr);
-               const fapi::MBvpdSensorMap & ATTR_ID = i_attr;
-               FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_ATTRIBUTE_ID);
-               break;
-       }
-
-    } while (0);
-
-    delete l_pMwBuffer;
-    l_pMwBuffer = NULL;
-
-    FAPI_DBG("getMBvpdSensorMap: exit rc=0x%08x",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.C
deleted file mode 100644
index e53e406cf..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.C
+++ /dev/null
@@ -1,492 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSlopeInterceptData.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdSlopeInterceptData.C,v 1.5 2015/09/29 15:59:42 dcrowell Exp $
-/**
- *  @file getMBvpdSlopeInterceptData.C
- *
- *  @brief get master and supplier power slope and intercept data
- *         from MBvpd MV and MW keywords
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <getMBvpdSlopeInterceptData.H>
-
-extern "C"
-{
-using namespace fapi;
-
-// local function to get master power slope and intercept data
-fapi::ReturnCode getMBvpdMasterData(
-                              const fapi::Target   &i_mbTarget,
-                              const fapi::MBvpdSlopeIntercept i_attr,
-                              uint32_t & o_val);
-
-// local function to get supplier power slope and intercept data
-fapi::ReturnCode getMBvpdSupplierData(
-                              const fapi::Target   &i_mbTarget,
-                              const fapi::MBvpdSlopeIntercept i_attr,
-                              uint32_t & o_val);
-
-/**
- * @brief get power slope and intercept data from cvpd record VSPD
- *        keyword MW and MV
- * @param[in]  i_mbTarget   -   mb target
- * @param[in]  i_attr       -   enumerator to select requested value
- * @param[out] o_val        -   master/supplier slope/intercept value
- *
- * @return fapi::ReturnCode -   FAPI_RC_SUCCESS if success,
- *                              relevant error code for failure.
- */
-
-fapi::ReturnCode getMBvpdSlopeInterceptData(
-                              const fapi::Target   &i_mbTarget,
-                              const fapi::MBvpdSlopeIntercept i_attr,
-                              uint32_t & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-
-    FAPI_DBG("getMBvpdSlopeInterceptData: entry ");
-
-    // get master values from MW keyword or supplier values from MV keyword
-    switch (i_attr)
-    {
-       case MASTER_POWER_SLOPE:
-       case MASTER_POWER_INTERCEPT:
-       case MASTER_TOTAL_POWER_SLOPE:
-       case MASTER_TOTAL_POWER_INTERCEPT:
-           l_fapirc = getMBvpdMasterData(i_mbTarget, i_attr, o_val);
-           break;
-       case SUPPLIER_POWER_SLOPE:
-       case SUPPLIER_POWER_INTERCEPT:
-       case SUPPLIER_TOTAL_POWER_SLOPE:
-       case SUPPLIER_TOTAL_POWER_INTERCEPT:
-           l_fapirc = getMBvpdSupplierData(i_mbTarget, i_attr, o_val);
-           break;
-       default: // Unlikely, but needs to be caught
-           FAPI_ERR("getMBvpdSlopeInterceptData: invalid attribute ID 0x%02x",
-                       i_attr);
-           const fapi::MBvpdSlopeIntercept & ATTR_ID = i_attr;
-           FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INVALID_ATTRIBUTE_ID);
-    }
-
-    FAPI_DBG("getMBvpdSlopeInterceptData: exit rc=0x%08x",
-               static_cast<uint32_t>(l_fapirc));
-    return  l_fapirc;
-}
-
-// local function to get master power slope and intercept data
-//
-// the master power slope and intercept are in the MW keyword
-//
-fapi::ReturnCode getMBvpdMasterData(
-                              const fapi::Target   &i_mbTarget,
-                              const fapi::MBvpdSlopeIntercept i_attr,
-                              uint32_t & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-
-    //MW keyword layout
-    struct mw_keyword
-    {
-        uint8_t     MWKeywordVersion;
-        uint8_t     masterPowerSlope_MSB;     //big endian order
-        uint8_t     masterPowerSlope_LSB;
-        uint8_t     masterPowerIntercept_MSB; //big endian order
-        uint8_t     masterPowerIntercept_LSB;
-        uint8_t     masterTotalPowerSlope_MSB;     //big endian order
-        uint8_t     masterTotalPowerSlope_LSB;
-        uint8_t     masterTotalPowerIntercept_MSB; //big endian order
-        uint8_t     masterTotalPowerIntercept_LSB;
-        uint8_t     tempSensorPrimaryLayout;
-        uint8_t     tempSensorSecondaryLayout;
-    };
-    const uint32_t MW_KEYWORD_SIZE = sizeof(mw_keyword);  // keyword size
-
-    mw_keyword * l_pMwBuffer = NULL; // MBvpd MW keyword buffer
-    uint32_t  l_MwBufsize = sizeof(mw_keyword);
-
-    FAPI_DBG("getMBvpdMasterData: entry ");
-
-    do {
-
-        l_pMwBuffer = new mw_keyword;
-
-        // Read the MW keyword field
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_MW,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(l_pMwBuffer),
-                                     l_MwBufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdMasterData: Read of MV keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient MW keyword was returned.
-        if (l_MwBufsize < MW_KEYWORD_SIZE )
-        {
-            FAPI_ERR("getMBvpdMasterData:"
-                     " less MW keyword returned than expected %d < %d",
-                       l_MwBufsize, MW_KEYWORD_SIZE);
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_MW;
-            const uint32_t & RETURNED_SIZE = l_MwBufsize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-            break;  //  break out with fapirc
-        }
-
-        // Return requested value
-        switch (i_attr)
-        {
-           case MASTER_POWER_SLOPE:  //get each byte to perserve endian
-               o_val = l_pMwBuffer->masterPowerSlope_LSB;
-               o_val |= (l_pMwBuffer->masterPowerSlope_MSB << 8);
-               break;
-           case MASTER_POWER_INTERCEPT:  //get each byte to perserve endian
-               o_val = l_pMwBuffer->masterPowerIntercept_LSB;
-               o_val |= (l_pMwBuffer->masterPowerIntercept_MSB << 8);
-               break;
-           case MASTER_TOTAL_POWER_SLOPE:  //get each byte to perserve endian
-               o_val = l_pMwBuffer->masterTotalPowerSlope_LSB;
-               o_val |= (l_pMwBuffer->masterTotalPowerSlope_MSB << 8);
-               break;
-           case MASTER_TOTAL_POWER_INTERCEPT:  //get each byte to perserve endian
-               o_val = l_pMwBuffer->masterTotalPowerIntercept_LSB;
-               o_val |= (l_pMwBuffer->masterTotalPowerIntercept_MSB << 8);
-               break;
-       default: //i_attr value was checked before call so should not get here
-               break;
-       }
-
-    } while (0);
-
-    delete l_pMwBuffer;
-    l_pMwBuffer = NULL;
-
-    FAPI_DBG("getMBvpdMasterData: exit rc=0x%08x",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-// local function to get supplier power slope and intercept data
-//
-// Read the #I keyword to get the module ID of this CDIMM
-// Then read the #MV keyword which has all the vendor supplied info
-// and search the list for the module ID found in the #I keyword
-//
-fapi::ReturnCode getMBvpdSupplierData(
-                              const fapi::Target   &i_mbTarget,
-                              const fapi::MBvpdSlopeIntercept i_attr,
-                              uint32_t & o_val)
-{
-
-    //#I keyword layout
-    const uint32_t  PDI_DDR3_KEYWORD_SIZE = 256;
-    const uint32_t  PDI_DDR4_KEYWORD_SIZE = 384; // assumed size for DDR4
-    const uint8_t   SPD_DDR3 = 0xB;
-    const uint8_t   SPD_DDR4 = 0xC;
-    struct pdI_keyword
-    {
-        union
-        {
-            struct // common
-            {
-                uint8_t   filler1[2];
-                uint8_t   mem_type;
-            } common;
-            struct // DDR3 layout of #I
-            {
-                uint8_t   filler1[117]; // other fields and reserved bytes
-                uint8_t   moduleID_MSB; // at offset 117. Big endian order
-                uint8_t   moduleID_LSB; // VPD data CCIN_31E1_v.5.3.ods
-                uint8_t   filler2[PDI_DDR3_KEYWORD_SIZE-117-2]; //trailing space
-            } ddr3;
-            struct // DDR4 layout of #I
-            {
-                uint8_t   filler1[350]; // other fields and reserved bytes
-                uint8_t   moduleID_MSB; // at offset 320. Big endian order
-                uint8_t   moduleID_LSB; //
-                uint8_t   filler2[PDI_DDR4_KEYWORD_SIZE-350-2]; //trailing space
-            } ddr4;
-        } pdI;
-    };
-
-    //MV keyword layout
-    struct mv_vendorInfo
-    {
-        uint8_t   supplierID_MSB;              // Big endian order
-        uint8_t   supplierID_LSB;
-        uint8_t   supplierPowerSlope_MSB;      // Big endian order
-        uint8_t   supplierPowerSlope_LSB;
-        uint8_t   supplierPowerIntercept_MSB;  // Big endian order
-        uint8_t   supplierPowerIntercept_LSB;
-        uint8_t   supplierTotalPowerSlope_MSB;      // Big endian order
-        uint8_t   supplierTotalPowerSlope_LSB;
-        uint8_t   supplierTotalPowerIntercept_MSB;  // Big endian order
-        uint8_t   supplierTotalPowerIntercept_LSB;
-
-    };
-    struct mv_keyword //variable length. Structure is size of 1 entry.
-    {
-        uint8_t   version;
-        uint8_t   numEntries;
-        mv_vendorInfo firstVendorInfo;
-       // variable number of vendor supplied entries
-    };
-
-    fapi::ReturnCode l_fapirc;
-    pdI_keyword  *  l_pPdIBuffer = NULL;   // MBvpd #I keyword buffer
-    uint32_t        l_pdIBufsize = sizeof(pdI_keyword);
-    uint8_t         l_moduleID_LSB = 0;    // module ID to look for
-    uint8_t         l_moduleID_MSB = 0;
-    mv_keyword   *  l_pMvBuffer = NULL;    // MBvpd MV keyword buffer
-    uint32_t        l_mvBufsize = 0;       // variable length
-    mv_vendorInfo * l_pVendorInfo = NULL;
-    uint32_t        l_offset = 0;
-    bool            l_found = false;
-
-    do {
-
-        l_pPdIBuffer = new pdI_keyword;
-
-        // Read the #I keyword field to get the Module ID
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_PDI,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(l_pPdIBuffer),
-                                     l_pdIBufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdSupplierData: Read of pdI keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        FAPI_DBG("getMBvpdSupplierData: #I mem type=0x%02x ",
-            l_pPdIBuffer->pdI.common.mem_type);
-
-        // check for DDR3 or DDR4
-        if (SPD_DDR3 == l_pPdIBuffer->pdI.common.mem_type )
-        {
-            // Check that sufficient #I was returned.
-            if (l_pdIBufsize < PDI_DDR3_KEYWORD_SIZE )
-            {
-                FAPI_ERR("getMBvpdSupplierData:"
-                         " less DDR3 #I keyword returned than expected %d < %d",
-                           l_pdIBufsize, PDI_DDR3_KEYWORD_SIZE);
-                const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_PDI;
-                const uint32_t & RETURNED_SIZE = l_pdIBufsize;
-                const fapi::Target & CHIP_TARGET = i_mbTarget;
-                FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-                break;  //  break out with fapirc
-            }
-
-            // grab module ID
-            l_moduleID_LSB = l_pPdIBuffer->pdI.ddr3.moduleID_LSB;
-            l_moduleID_MSB = l_pPdIBuffer->pdI.ddr3.moduleID_MSB;
-        }
-        else if (SPD_DDR4 == l_pPdIBuffer->pdI.common.mem_type )
-        {
-            // Check that sufficient #I was returned.
-            if (l_pdIBufsize < PDI_DDR4_KEYWORD_SIZE )
-            {
-                FAPI_ERR("getMBvpdSupplierData:"
-                         " less DDR4 #I keyword returned than expected %d < %d",
-                           l_pdIBufsize, PDI_DDR4_KEYWORD_SIZE);
-                const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_PDI;
-                const uint32_t & RETURNED_SIZE = l_pdIBufsize;
-                const fapi::Target & CHIP_TARGET = i_mbTarget;
-                FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-                break;  //  break out with fapirc
-            }
-
-            // grab module ID
-            l_moduleID_LSB = l_pPdIBuffer->pdI.ddr4.moduleID_LSB;
-            l_moduleID_MSB = l_pPdIBuffer->pdI.ddr4.moduleID_MSB;
-        }
-        else
-        {
-            FAPI_ERR("getMBvpdSupplierData:"
-                     " unexpected memory type in #I");
-            const uint8_t & MEM_TYPE = l_pPdIBuffer->pdI.common.mem_type;
-            const fapi::Target & MEMBUF_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_UNEXPECTED_MEM_TYPE);
-            break;  //  break out with fapirc
-        }
-
-        // Done with #I buffer. Error paths free buffer at end.
-        delete l_pPdIBuffer;
-        l_pPdIBuffer = NULL;
-
-        FAPI_DBG("getMBvpdSupplierData: #I moduleID=0x%08x ",
-            l_moduleID_LSB+(l_moduleID_MSB<<8));
-
-        // see how big the MV keyword is as it is variable length
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_MV,
-                                     i_mbTarget,
-                                     NULL, //pass NULL buff pointer to get size
-                                     l_mvBufsize);
-        if (l_fapirc)
-        {
-             FAPI_ERR("getMBvpdSupplierData: Read of MV keyword failed");
-             break;  //  break out with fapirc
-        }
-
-        // read MV keyword
-        l_pMvBuffer = (mv_keyword *)new uint8_t[l_mvBufsize];
-
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_MV,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(l_pMvBuffer),
-                                     l_mvBufsize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdSupplierData: Read of MV keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient MV was returned to get at least the count.
-        l_pVendorInfo = &(l_pMvBuffer->firstVendorInfo);
-        l_offset = (uint8_t *)l_pVendorInfo - (uint8_t *)l_pMvBuffer;
-
-        if (l_mvBufsize < l_offset )
-        {
-            FAPI_ERR("getMBvpdSupplierData:"
-                     " less MV keyword returned than expected %d < %d",
-                       l_mvBufsize, l_offset);
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_MV;
-            const uint32_t & RETURNED_SIZE = l_mvBufsize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-            break;  //  break out with fapirc
-        }
-
-        // look for matching module ID
-        for (uint32_t l_count=0;l_count < l_pMvBuffer->numEntries;l_count++)
-        {
-            // shouldn't run past end of buffer, checking to be sure
-            if (l_offset + sizeof (mv_vendorInfo) > l_mvBufsize)
-            {
-                break;
-            }
-
-            FAPI_DBG("getMBvpdSupplierData: cnt=%d this supplier ID= 0x%08x ",
-              l_count,
-              l_pVendorInfo->supplierID_LSB+(l_pVendorInfo->supplierID_MSB<<8));
-
-            if ((l_pVendorInfo->supplierID_LSB == l_moduleID_LSB ) &&
-                (l_pVendorInfo->supplierID_MSB == l_moduleID_MSB ))
-            {
-                l_found = true;
-                break;
-            }
-            l_offset += sizeof (mv_vendorInfo);
-            l_pVendorInfo++;
-        }
-
-        // If not found, see if first supplier should be used
-        // and there is one (unlikely that there is not one).
-        if ( ! l_found &&
-             0 < l_pMvBuffer->numEntries &&
-             sizeof (mv_keyword) <= l_mvBufsize)
-        {
-            uint8_t l_checkUseFirstSupplier = 0;
-            l_fapirc = FAPI_ATTR_GET(
-                       ATTR_CENTAUR_EC_USE_FIRST_SUPPLIER_FOR_INVALID_MODULE_ID,
-                       &i_mbTarget,
-                       l_checkUseFirstSupplier);
-            if (l_fapirc)
-            {
-                FAPI_ERR("getMBvpdSupplierData:"
-                         " get attr use first supplier failed");
-                break;  //  break out with fapirc
-            }
-            FAPI_DBG("getMBvpdSupplierData: attr use first supplier = 0x%02x",
-                      l_checkUseFirstSupplier);
-            if ( l_checkUseFirstSupplier)
-            {
-                l_pVendorInfo = &(l_pMvBuffer->firstVendorInfo);
-                l_found = true;
-            }
-        }
-
-        // Return requested value if found
-        if ( l_found )
-        {
-            switch (i_attr)
-            {
-               case SUPPLIER_POWER_SLOPE:  //get each byte to perserve endian
-                   o_val = l_pVendorInfo->supplierPowerSlope_LSB;
-                   o_val |= (l_pVendorInfo->supplierPowerSlope_MSB << 8);
-                   break;
-               case SUPPLIER_POWER_INTERCEPT: //get each byte to perserve endian
-                   o_val = l_pVendorInfo->supplierPowerIntercept_LSB;
-                   o_val |= (l_pVendorInfo->supplierPowerIntercept_MSB << 8);
-                   break;
-               case SUPPLIER_TOTAL_POWER_SLOPE:  //get each byte to perserve endian
-                   o_val = l_pVendorInfo->supplierTotalPowerSlope_LSB;
-                   o_val |= (l_pVendorInfo->supplierTotalPowerSlope_MSB << 8);
-                   break;
-               case SUPPLIER_TOTAL_POWER_INTERCEPT: //get each byte to perserve endian
-                   o_val = l_pVendorInfo->supplierTotalPowerIntercept_LSB;
-                   o_val |= (l_pVendorInfo->supplierTotalPowerIntercept_MSB << 8);
-                   break;
-
-           default: //i_attr value was checked already so should not get here
-                   break;
-            }
-       }
-       else
-       {
-           FAPI_ERR("getMBvpdSupplierData:"
-                    " supplier ID not found 0x%04x",
-                      l_moduleID_LSB+(l_moduleID_MSB<<8));
-           const uint32_t & MODULE_ID = l_moduleID_LSB+(l_moduleID_MSB<<8);
-           const fapi::Target & MEMBUF_TARGET = i_mbTarget;
-           FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_SUPPLIER_ID_NOT_IN_MV_VPD );
-       }
-
-    } while (0);
-
-    delete l_pPdIBuffer;
-    l_pPdIBuffer = NULL;
-    delete l_pMvBuffer;
-    l_pMvBuffer = NULL;
-
-    FAPI_DBG("getMBvpdSupplierData: exit rc=0x%08x",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.C
deleted file mode 100644
index 3e05baffc..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.C
+++ /dev/null
@@ -1,189 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdSpareDramData.C $     */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdSpareDramData.C,v 1.7 2014/10/23 21:00:12 eliner Exp $
-#include  <stdint.h>
-
-//  fapi support
-#include  <fapi.H>
-#include  <dimmConsts.H>
-#include  <getMBvpdSpareDramData.H>
-
-extern "C"
-{
-using namespace fapi;
-
-fapi::ReturnCode getMBvpdSpareDramData(const fapi::Target &i_mba,
-                                       uint8_t (&o_data)[DIMM_DQ_MAX_MBA_PORTS]
-                                                    [DIMM_DQ_MAX_MBAPORT_DIMMS]
-                                                    [DIMM_DQ_MAX_DIMM_RANKS])
-{
-    // AM keyword layout
-    const uint8_t NUM_MBAS =  2; // Two MBAs per Centaur
-    const uint8_t NUM_MIRR_BYTES = 4; // Size of address mirror data
-
-    // Struct for AM Keyword buffer
-    // Contains a 1D array for the address mirror data and
-    // a 2D array for the spare DRAM data.
-    struct MirrorData
-    {
-        uint8_t iv_mirrorData[NUM_MIRR_BYTES];
-    };
-    struct DimmSpareData
-    {
-        // This contains information for all ranks and is returned in o_data
-        uint8_t iv_dimmSpareData;
-    };
-    struct PortSpareData
-    {
-        DimmSpareData iv_dimmSpareData[DIMM_DQ_MAX_MBAPORT_DIMMS];
-    };
-    struct MbaSpareData
-    {
-        PortSpareData iv_portSpareData[DIMM_DQ_MAX_MBA_PORTS];
-    };
-    struct AmKeyword
-    {
-        MirrorData mirrorData;
-        MbaSpareData iv_mbaSpareData[NUM_MBAS];
-    };
-
-    // AM keyword size
-    const uint32_t AM_KEYWORD_SIZE = sizeof(AmKeyword);
-    fapi::ReturnCode l_rc;
-    // Centaur memory buffer target
-    fapi::Target l_mbTarget;
-    // MBvpd AM keyword buffer
-    AmKeyword * l_pAmBuffer = NULL;
-    uint32_t  l_AmBufSize = sizeof(AmKeyword);
-
-    do
-    {
-        uint8_t l_customDimm = 0;
-
-        l_rc = FAPI_ATTR_GET(ATTR_EFF_CUSTOM_DIMM,&i_mba,l_customDimm);
-        if(l_rc)
-        {
-            FAPI_ERR("getMBvpdSpareDramData: Read of Custom Dimm failed");
-            break;
-        }
-
-        //if custom_dimm = 0, use isdimm
-        if(fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO == l_customDimm)
-        {
-            //ISDIMMs do not have any spare drams,
-            //return 0 for all ports and ranks.
-            for (uint8_t i = 0; i < DIMM_DQ_MAX_MBA_PORTS; i++)
-            {
-                for (uint8_t j = 0; j < DIMM_DQ_MAX_MBAPORT_DIMMS; j++)
-                {
-                    for (uint8_t k = 0; k < DIMM_DQ_MAX_DIMM_RANKS; k++)
-                    {
-                        o_data[i][j][k] = 0;
-                    }
-                }
-            }
-        //if custom_dimm = 1, use cdimm
-        }else
-        {
-            // find the Centaur memory buffer from the passed MBA
-            l_rc = fapiGetParentChip (i_mba, l_mbTarget);
-            if (l_rc)
-            {
-                FAPI_ERR("getMBvpdSpareDramData: Finding the parent mb failed ");
-                break;
-            }
-
-            // Read AM keyword field
-            l_pAmBuffer = new AmKeyword();
-            l_rc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
-                                     fapi::MBVPD_KEYWORD_AM,
-                                     l_mbTarget,
-                                     reinterpret_cast<uint8_t *>(l_pAmBuffer),
-                                     l_AmBufSize);
-            if (l_rc)
-            {
-                FAPI_ERR("getMBvpdSpareDramData: "
-                         "Read of AM Keyword failed");
-                break;
-            }
-
-            // Check for error or incorrect amount of data returned
-            if (l_AmBufSize < AM_KEYWORD_SIZE)
-            {
-                FAPI_ERR("getMBvpdSpareDramData:"
-                         " less AM keyword returned than expected %d < %d",
-                           l_AmBufSize, AM_KEYWORD_SIZE);
-                const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_AM;
-                const uint32_t & RETURNED_SIZE = l_AmBufSize;
-                const fapi::Target & CHIP_TARGET = l_mbTarget;
-                FAPI_SET_HWP_ERROR(l_rc, RC_MBVPD_INSUFFICIENT_VPD_RETURNED );
-                break;
-            }
-
-            // Find the position of the passed mba on the centuar
-            uint8_t l_mba = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_mba, l_mba);
-
-            if (l_rc)
-            {
-                FAPI_ERR("getMBvpdSpareDramData: Get MBA position failed ");
-                break;
-            }
-            // Data in the AM Keyword contains information for both MBAs and
-            // is stored in [mba][port][dimm] ([2][2][2]) format, where the
-            // third (dimm) dimension contains a byte where each two bits of
-            // that byte are the spare status for a particular rank.
-            // The caller expects data returned for a particular MBA,
-            // and where the ranks for each dimm are separately indexed,
-            // so conversion to a [port][dimm][rank] ([2][2][4]) format
-            // is necessary.
-            for (uint8_t i = 0; i < DIMM_DQ_MAX_MBA_PORTS; i++)
-            {
-                for (uint8_t j = 0; j < DIMM_DQ_MAX_MBAPORT_DIMMS; j++)
-                {
-                    // Mask to pull of two bits at a time from iv_dimmSpareData
-                    uint8_t l_dimmMask = 0xC0;
-                    // Shift amount decrements each time as l_dimmMask
-                    // is shifted to the right
-                    uint8_t l_rankBitShift = 6;
-                    for (uint8_t k = 0; k < DIMM_DQ_MAX_DIMM_RANKS; k++)
-                    {
-                        o_data[i][j][k] =((l_pAmBuffer->iv_mbaSpareData[l_mba].
-                                       iv_portSpareData[i].iv_dimmSpareData[j].
-                                       iv_dimmSpareData & l_dimmMask) >>
-                                       l_rankBitShift);
-                        l_dimmMask >>= 2;
-                        l_rankBitShift -= 2;
-                    }
-                }
-            }
-        }
-    }while(0);
-    delete l_pAmBuffer;
-    l_pAmBuffer = NULL;
-    return l_rc;
-}
-
-}  // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.C
deleted file mode 100644
index fda938c95..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.C
+++ /dev/null
@@ -1,105 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVersion.C $           */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdVersion.C,v 1.3 2015/02/24 19:23:56 whs Exp $
-/**
- *  @file getMBvpdVersion.C
- *
- *  @brief get the vpd version from MBvpd record VINI keyword VZ
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdVersion.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-fapi::ReturnCode getMBvpdVersion(
-                              const fapi::Target   &i_mbaTarget,
-                              uint32_t  & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-    fapi::Target l_mbTarget;
-    uint16_t l_vpdVersion = 0;
-    uint32_t l_bufSize = sizeof(l_vpdVersion);
-
-    FAPI_DBG("getMBvpdVersion: entry ");
-
-    do {
-        // find the Centaur memory buffer from the passed MBA
-        l_fapirc = fapiGetParentChip (i_mbaTarget,l_mbTarget);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdVersion: Finding the parent mb failed ");
-            break;  //  break out with fapirc
-        }
-        FAPI_DBG("getMBvpdVersion: parent path=%s ",
-             l_mbTarget.toEcmdString()  );
-
-        // get vpd version from record VINI keyword VZ
-        l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VINI,
-                                     fapi::MBVPD_KEYWORD_VZ,
-                                     l_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_vpdVersion),
-                                     l_bufSize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdVersion: Read of VZ keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient size was returned.
-        if (l_bufSize < sizeof(l_vpdVersion) )
-        {
-            FAPI_ERR("getMBvpdVersion:"
-                     " less keyword data returned than expected %d < %d",
-                       l_bufSize, sizeof(l_vpdVersion));
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_VZ;
-            const uint32_t & RETURNED_SIZE = l_bufSize;
-            const fapi::Target & CHIP_TARGET = l_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-            break;  //  break out with fapirc
-        }
-        // return value
-        o_val = static_cast<uint32_t>(FAPI_BE16TOH(l_vpdVersion));
-
-        FAPI_DBG("getMBvpdVersion: vpd version=0x%08x",
-                o_val);
-
-
-    } while (0);
-
-    FAPI_DBG("getMBvpdVersion: exit rc=0x%08x)",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.C
deleted file mode 100644
index 3985a403b..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.C
+++ /dev/null
@@ -1,154 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMBvpdVoltageSettingData.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMBvpdVoltageSettingData.C,v 1.2 2015/09/29 20:55:55 janssens Exp $
-/**
- *  @file getMBvpdVoltageSettingData.C
- *
- *  @brief get the Voltage Setting Data from DW keyword of MBVPD SPDX record
- *  *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <getMBvpdVoltageSettingData.H>
-#include    <fapiSystemConfig.H>
-#include    <getMBvpdAttr.H>
-
-extern "C"
-{
-using   namespace   fapi;
-using   namespace   getAttrData;
-
-fapi::ReturnCode getMBvpdVoltageSettingData(const fapi::Target   &i_mbTarget,
-                                            uint32_t & o_val)
-{
-    fapi::ReturnCode l_fapirc;
-    DimmType l_dimmType = ISDIMM;
-    fapi::MBvpdRecord  l_record  = fapi::MBVPD_RECORD_SPDX;
-    uint16_t l_vpdVoltageSettingData = DW_KEYWORD_DEFAULT_VALUE;
-    uint32_t l_bufSize = sizeof(l_vpdVoltageSettingData);
-
-    FAPI_DBG("getMBvpdVoltageSettingData: entry ");
-
-    do {
-
-        FAPI_DBG("getMBvpdVoltageSettingData: Membuff path=%s ",
-             i_mbTarget.toEcmdString()  );
-
-        // Find the dimm type
-        // Determine if ISDIMM or CDIMM
-
-        // Find one mba target for passing it to fapiGetAssociatedDimms
-        std::vector<fapi::Target> l_mba_chiplets;
-        l_fapirc = fapiGetChildChiplets( i_mbTarget ,
-                        fapi::TARGET_TYPE_MBA_CHIPLET, l_mba_chiplets );
-        if((l_fapirc) || (l_mba_chiplets.size() == 0))
-        { 
-           FAPI_ERR("getMBvpdVoltageSettingData: Problem getting MBA's of Membuff");
-           break;   //return error
-        }
-
-        std::vector<fapi::Target> l_target_dimm_array;
-        l_fapirc = fapiGetAssociatedDimms(l_mba_chiplets[0], l_target_dimm_array);
-        if(l_fapirc)
-        {
-           FAPI_ERR("getMBvpdVoltageSettingData: Problem getting DIMMs of Membuf");
-           break;   //return error
-        }
-        if(l_target_dimm_array.size() != 0)
-        {
-            uint8_t l_customDimm=0;
-            l_fapirc = FAPI_ATTR_GET(ATTR_SPD_CUSTOM,&l_target_dimm_array[0],
-                          l_customDimm);
-            if(l_fapirc) {
-               FAPI_ERR("getMBvpdVoltageSettingData: ATTR_SPD_CUSTOM failed ");
-               break;   //return error
-            }
-
-            if (l_customDimm == fapi::ENUM_ATTR_SPD_CUSTOM_YES)
-            {
-                l_dimmType = CDIMM;
-                FAPI_DBG("getMBvpdVoltageSettingData: CDIMM TYPE!!!");
-            }
-            else
-            {
-                l_dimmType = ISDIMM;
-                FAPI_DBG("getMBvpdVoltageSettingData: ISDIMM TYPE!!!");
-            }
-        }
-        else
-        {
-           l_dimmType = ISDIMM;
-           FAPI_DBG("getMBvpdVoltageSettingData: ISDIMM TYPE (dimm array size = 0)");
-        }
-
-       
-        if(l_dimmType == CDIMM)
-        {
-            l_record = fapi::MBVPD_RECORD_VSPD;
-        }
-        // get voltage setting data from record SPDX keyword DW
-        l_fapirc = fapiGetMBvpdField(l_record,
-                                     fapi::MBVPD_KEYWORD_DW,
-                                     i_mbTarget,
-                                     reinterpret_cast<uint8_t *>(&l_vpdVoltageSettingData),
-                                     l_bufSize);
-        if (l_fapirc)
-        {
-            FAPI_ERR("getMBvpdVersion: Read of DW keyword failed");
-            break;  //  break out with fapirc
-        }
-
-        // Check that sufficient size was returned.
-        if (l_bufSize < sizeof(l_vpdVoltageSettingData) )
-        {
-            FAPI_ERR("getMBvpdVoltageSettingData:"
-                     " less keyword data returned than expected %d < %d",
-                       l_bufSize, sizeof(l_vpdVoltageSettingData));
-            const uint32_t & KEYWORD = fapi::MBVPD_KEYWORD_DW;
-            const uint32_t & RETURNED_SIZE = l_bufSize;
-            const fapi::Target & CHIP_TARGET = i_mbTarget;
-            FAPI_SET_HWP_ERROR(l_fapirc,RC_MBVPD_INSUFFICIENT_VPD_RETURNED);
-            break;  //  break out with fapirc
-        }
-        // return value
-        o_val = static_cast<uint32_t>(FAPI_BE16TOH(l_vpdVoltageSettingData));
-
-        FAPI_DBG("getMBvpdVoltageSettingData: voltage setting Data=0x%08x",
-                o_val);
-
-
-    } while (0);
-
-    FAPI_DBG("getMBvpdVoltageSettingData: exit rc=0x%08x)",
-               static_cast<uint32_t>(l_fapirc));
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.C b/src/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.C
deleted file mode 100644
index 790731ec2..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.C
+++ /dev/null
@@ -1,124 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMvpdExL2SingleMemberEnable.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMvpdExL2SingleMemberEnable.C,v 1.1 2013/04/10 22:02:33 mjjones Exp $
-/**
- *  @file getMvpdExL2SingleMemberEnable.C
- *
- *  @brief MVPD Accessor for providing the ATTR_EX_L2_SINGLE_MEMBER_ENABLE
- *         attribute
- */
-
-/*
- * Change Log ******************************************************************
- * Flag     Defect/Feature  User        Date        Description
- * ------   --------------  ----------  ----------- ----------------------------
- *                          mjjones     04/10/2013  Created.
- */
-
-#include <getMvpdExL2SingleMemberEnable.H>
-
-extern "C"
-{
-
-fapi::ReturnCode getMvpdExL2SingleMemberEnable(
-    const fapi::Target & i_procTarget,
-    uint32_t & o_val)
-{
-    /**
-     *  @brief Structure of the LWP4 record, IN keyword MVPD field
-     *         for the retrieval of the Single Member Enable data
-     *
-     *  This could move to a common header file if multiple VPD Accessors need
-     *  to get data from the LWP4 record, IN keyword MVPD field
-     */
-    struct MVPD_LWP4_IN
-    {
-        uint8_t iv_reserved0;
-        uint8_t iv_reserved1;
-        uint8_t iv_singleMemberEnable0_7;
-        uint8_t iv_singleMemberEnable8_15;
-    };
-
-    fapi::ReturnCode l_rc;
-    uint8_t * l_pField = NULL;
-    uint32_t l_fieldSize = 0;
-
-    FAPI_INF("getMvpdExL2SingleMemberEnable: entry");
-
-    // Call fapiGetMvpdField with a NULL pointer to get the field size
-    l_rc = fapiGetMvpdField(fapi::MVPD_RECORD_LWP4,
-                            fapi::MVPD_KEYWORD_IN,
-                            i_procTarget,
-                            l_pField,
-                            l_fieldSize);
-
-    if (l_rc)
-    {
-        FAPI_ERR("getMvpdExL2SingleMemberEnable: Error getting MVPD field size");
-    }
-    else
-    {
-        if (l_fieldSize < sizeof(MVPD_LWP4_IN))
-        {
-            FAPI_ERR("getMvpdExL2SingleMemberEnable: MVPD field too small (%d)",
-                     l_fieldSize);
-            uint32_t & FIELD_SIZE = l_fieldSize;
-            FAPI_SET_HWP_ERROR(l_rc,
-                RC_MVPD_EX_L2_SINGLE_MEMBER_ENABLE_BAD_FIELD_SIZE);
-        }
-        else
-        {
-            // Allocate memory and call fapiGetMvpdField to get the field
-            l_pField = new uint8_t[l_fieldSize];
-
-            l_rc = fapiGetMvpdField(fapi::MVPD_RECORD_LWP4,
-                                    fapi::MVPD_KEYWORD_IN,
-                                    i_procTarget,
-                                    l_pField,
-                                    l_fieldSize);
-
-            if (l_rc)
-            {
-                FAPI_ERR(
-                    "getMvpdExL2SingleMemberEnable: Error getting MVPD field");
-            }
-            else
-            {
-                MVPD_LWP4_IN * l_pData =
-                    reinterpret_cast<MVPD_LWP4_IN *>(l_pField);
-
-                o_val = l_pData->iv_singleMemberEnable0_7;
-                o_val <<= 8;
-                o_val += l_pData->iv_singleMemberEnable8_15;
-
-                FAPI_INF("getMvpdExL2SingleMemberEnable: 0x%08x", o_val);
-            }
-
-            delete [] l_pField;
-        }
-    }
-
-    return l_rc;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.C b/src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.C
deleted file mode 100644
index c3ccbdc1d..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.C
+++ /dev/null
@@ -1,76 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.C $               */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getMvpdRing.C,v 1.1 2012/07/19 22:00:40 mjjones Exp $
-/**
- *  @file getMvpdRing.C
- *
- *  @brief fetch repair rings from MVPD  records
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-
-#include    <getMvpdRing.H>
-#include    <mvpdRingFuncs.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-// getMvpdRing: Wrapper to call common function mvpdRingFunc
-fapi::ReturnCode getMvpdRing( fapi::MvpdRecord i_record,
-                              fapi::MvpdKeyword i_keyword, 
-                              const fapi::Target &i_fapiTarget,
-                              const uint8_t       i_chipletId,
-                              const uint8_t       i_ringId,
-                              uint8_t             *i_pRingBuf,
-                              uint32_t            &io_rRingBufsize)
-{
-    fapi::ReturnCode        l_fapirc;
-
-    FAPI_DBG("getMvpdRing: entry ringId=0x%x, chipletId=0x%x, size=0x%x ",
-             i_ringId,
-             i_chipletId,
-             io_rRingBufsize  );
-
-    // common get and set processing
-    l_fapirc = mvpdRingFunc(MVPD_RING_GET,
-                            i_record,
-                            i_keyword,
-                            i_fapiTarget,
-                            i_chipletId,
-                            i_ringId,
-                            i_pRingBuf,
-                            io_rRingBufsize);
-
-
-    FAPI_DBG("getMvpdRing: exit rc=0x%x",
-               static_cast<uint32_t>(l_fapirc) );
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.H b/src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.H
deleted file mode 100644
index e89a9f051..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.H
+++ /dev/null
@@ -1,94 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/getMvpdRing.H $               */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: RepairRingFunc.H,v 1.1 2012/07/19 22:00:38 mjjones Exp $
-/**
- *  @file getMvpdRing.H
- *
- *  @brief Prototype for getMvpdRing() -
- *          get a repair ring from a MVPD record
- */
-
- #ifndef    _HWP_GETMVPDRING_
- #define    _HWP_GETMVPDRING_
-
- #include   <fapi.H>
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*getMvpdRing_FP_t)
-     (fapi::MvpdRecord,fapi::MvpdKeyword,const fapi::Target &,
-      const uint8_t, const uint8_t, uint8_t *, uint32_t &);
-
-
-extern "C"
-{
-/**
- * @brief   get specified ring from MVPD for the specified target CPU.
- *
- * A Ring Id Chiplet Id should be unique in the mvpd Record.
- * The code does not validate. No assumption should be made on which would
- * be returned if there are multiple.
- *
- * @param i_record          -   Record enumerator 
- * @param i_keyword         -   Keyword enumerator 
- * Supported Rings are: 
- *                   MVPD_RECORD_CP00 - MVPD_KEYWORD_PDR
- *                   MVPD_RECORD_CP00 - MVPD_KEYWORD_PDG
- * @param i_fapiTarget      -   cpu target
- * @param i_chipletId       -   Chiplet ID
- * @param i_ringId          -   Ring ID
- * @param i_pRingBuf        -   pointer to a buffer allocated by the caller 
- *                              to receive the ring header and data.
- *                              if NULL, the size of the min buffer required
- *                              buffer will be returned in io_rRingBufsize 
- *                              with rc FAPI_RC_SUCCESS.
- * @param io_rRingBufsize   -   in:     size of ring buffer that caller has
- *                                      allocated
- *                              out:    number of BYTES that were copied to the
- *                                      output buffer.
- *                                      If the ring was not found, an error
- *                                      will be returned and this will be 0.
- *                                      If the output buffer is not big enough,
- *                                      an error will be returned and this will
- *                                      be the minimum size required.
- *                              The buffer contains the CompressedScanData
- *                              structure followed by compressed data. The 
- *                              caller does compression and decompression.
- *  Buffer:   io_rRingBufsize returns xNN. 
- *    byte x0  CompressedScanData structure (rs4 header)
- *    byte x18 compressed data (sizeof CompressedScanData is 0x18)
- *    byte xNN last byte of compressed data
- *
- * @return fapi::ReturnCode -   FAPI_RC_SUCCESS if success,
- *                              relevant error code for failure.
- */
-fapi::ReturnCode getMvpdRing( fapi::MvpdRecord i_record,
-                              fapi::MvpdKeyword i_keyword,
-                              const fapi::Target  &i_fapiTarget,
-                              const uint8_t       i_chipletId,
-                              const uint8_t       i_ringId,
-                              uint8_t             *io_pRingBuf,
-                              uint32_t            &io_rRingBufsize );
-
-}
-
-#endif
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/makefile b/src/usr/hwpf/hwp/mvpd_accessors/makefile
deleted file mode 100644
index 34bb8da52..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/makefile
+++ /dev/null
@@ -1,29 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/mvpd_accessors/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-SUBDIRS += compressionTool.d
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/mvpd.mk b/src/usr/hwpf/hwp/mvpd_accessors/mvpd.mk
deleted file mode 100644
index e90063cc6..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/mvpd.mk
+++ /dev/null
@@ -1,55 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/mvpd_accessors/mvpd.mk $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-CFLAGS += -DDQCOMPRESSION_TEST=1
-
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mvpd_accessors
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/mvpd_accessors
-
-VPATH += ${HWPPATH}/mvpd_accessors
-VPATH += ${HWPPATH}/mvpd_accessors/compressionTool
-OBJS += getMvpdRing.o
-OBJS += getMBvpdRing.o
-OBJS += setMvpdRing.o
-OBJS += mvpdRingFuncs.o
-OBJS += getMvpdExL2SingleMemberEnable.o
-OBJS += getMBvpdAddrMirrorData.o
-OBJS += getMBvpdSlopeInterceptData.o
-OBJS += getMBvpdSpareDramData.o
-OBJS += getMBvpdVersion.o
-OBJS += getMBvpdMemoryDataVersion.o
-OBJS += getMBvpdSPDXRecordVersion.o
-OBJS += getMBvpdVoltageSettingData.o
-OBJS += getMBvpdDram2NModeEnabled.o
-OBJS += getMBvpdSensorMap.o
-OBJS += getControlCapableData.o
-OBJS += accessMBvpdL4BankDelete.o
-OBJS += getDecompressedISDIMMAttrs.o
-OBJS += getDQAttrISDIMM.o
-OBJS += getDQSAttrISDIMM.o
-OBJS += getISDIMMTOC4DAttrs.o
-OBJS += DQCompressionLib.o
-OBJS += getMBvpdAttr.o
-OBJS += getMBvpdAttrData.o
-
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.C b/src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.C
deleted file mode 100644
index 3a532a1dc..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.C
+++ /dev/null
@@ -1,831 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.C $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mvpdRingFuncs.C,v 1.12 2014/07/16 19:06:49 cswenson Exp $
-/**
- *  @file mvpdRingFuncs.C
- *
- *  @brief common routines
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiUtil.H>
-#include    <mvpdRingFuncs.H>
-
-//      pull in CompressedScanData def from proc_slw_build HWP
-#include <p8_scan_compression.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-// functions internal to this file
-// these functions are common for both mvpdRingFunc and mbvpdRingFunc
-fapi::ReturnCode mvpdValidateRingHeader( CompressedScanData * i_pRing,
-                                     uint8_t              i_chipletId,
-                                     uint8_t              i_ringId,
-                                     uint32_t             i_ringBufsize);
-
-fapi::ReturnCode mvpdRingFuncFind( const uint8_t   i_chipletId,
-                               const uint8_t       i_ringId,
-                               uint8_t           * i_pRecordBuf,
-                               uint32_t            i_recordBufLen,
-                               uint8_t           * &o_rRingBuf,
-                               uint32_t            &o_rRingBufsize);
-
-fapi::ReturnCode mvpdRingFuncGet ( uint8_t *i_pRing,
-                               uint32_t     i_ringLen,
-                               uint8_t     *i_pCallerRingBuf,
-                               uint32_t    &io_rCallerRingBufLen);
-
-fapi::ReturnCode mvpdRingFuncSet ( uint8_t *i_pRecordBuf,
-                               uint32_t     i_recordLen,
-                               uint8_t     *i_pRing,
-                               uint32_t     i_ringLen,
-                               uint8_t     *i_pCallerRingBuf,
-                               uint32_t     i_callerRingBufLen);
-
-//******************************************************************************
-// mvpdValidateRecordKeyword & mbvpdValidateRecordKeyword
-// Check for supported combinations of Record and Keyword.
-// The record needs to contain rings of RS4 header (CompressedScanData) format
-//  note: "getting" data not in RS4 header format would likely just fail to find
-//  the ring harmlessly.  "Setting" data could make a mess looking for the end
-//  to append a new ring. The result could be invalid vpd.
-//  note: place first in the file to make finding the supported list easier.
-//******************************************************************************
-fapi::ReturnCode mvpdValidateRecordKeyword( fapi::MvpdRecord i_record,
-                                            fapi::MvpdKeyword i_keyword)
-{
-    // add record/keywords with rings with RS4 header here.
-    struct _supportedRecordKeywords {
-                                fapi::MvpdRecord record;
-                                fapi::MvpdKeyword keyword;
-    } supportedRecordKeywords [] = {
-        { MVPD_RECORD_CP00, MVPD_KEYWORD_PDR },
-        { MVPD_RECORD_CP00, MVPD_KEYWORD_PDG },
-    };
-    fapi::ReturnCode        l_fapirc;
-    bool l_validPair = false;
-    const uint32_t numPairs =
-             sizeof(supportedRecordKeywords)/sizeof(supportedRecordKeywords[0]);
-
-    for (uint32_t curPair = 0; curPair < numPairs; curPair++ )
-    {
-        if (supportedRecordKeywords[curPair].record == i_record &&
-            supportedRecordKeywords[curPair].keyword == i_keyword)
-        {
-            l_validPair = true;
-            break;
-        }
-    }
-    if ( !l_validPair ) {
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MVPD_RING_FUNC_INVALID_PARAMETER );
-     }
-    return l_fapirc;
-
-};
-
-
-#ifndef FAPI_NO_MBVPD
-fapi::ReturnCode mbvpdValidateRecordKeyword(fapi::MBvpdRecord i_record,
-                                            fapi::MBvpdKeyword i_keyword)
-{
-    // add record/keywords with rings with RS4 header here.
-    struct _supportedRecordKeywords {
-                                fapi::MBvpdRecord record;
-                                fapi::MBvpdKeyword keyword;
-    } supportedRecordKeywords [] = {
-        { MBVPD_RECORD_VSPD, MBVPD_KEYWORD_PDD },
-    };
-
-    fapi::ReturnCode l_fapirc;
-    bool l_validPair = false;
-
-    const uint32_t numPairs =
-             sizeof(supportedRecordKeywords)/sizeof(supportedRecordKeywords[0]);
-
-    for (uint32_t curPair = 0; curPair < numPairs; curPair++ )
-    {
-        if (supportedRecordKeywords[curPair].record == i_record &&
-            supportedRecordKeywords[curPair].keyword == i_keyword)
-        {
-            l_validPair = true;
-            break;
-        }
-    }
-    if (!l_validPair)
-    {
-        FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_RING_FUNC_INVALID_PARAMETER );
-    }
-    return l_fapirc;
-
-};
-#endif
-
-
-//******************************************************************************
-// mvpdRingFunc: the getMvpdRing and setMvpdRing wrappers call this function
-//               to do all the processing.
-// note: io_rRingBufsize is only 'output' for get.
-//******************************************************************************
-fapi::ReturnCode mvpdRingFunc(  const mvpdRingFuncOp i_mvpdRingFuncOp,
-                                fapi::MvpdRecord i_record,
-                                fapi::MvpdKeyword i_keyword,
-                                const fapi::Target   &i_fapiTarget,
-                                const uint8_t        i_chipletId,
-                                const uint8_t        i_ringId,
-                                uint8_t              *i_pRingBuf,
-                                uint32_t             &io_rRingBufsize)
-{
-    fapi::ReturnCode        l_fapirc;
-    uint32_t                l_recordLen  = 0;
-    uint8_t                 *l_recordBuf = NULL;
-    uint8_t                 *l_pRing     = NULL;
-    uint32_t                l_ringLen    = 0;
-
-   FAPI_DBG("mvpdRingFunc:entry op=0x%x ringId=0x%x chipletId=0x%x size=0x%x ",
-             i_mvpdRingFuncOp,
-             i_ringId,
-             i_chipletId,
-             io_rRingBufsize  );
-
-    do {
-        // do common get and set input parameter error checks
-        // check for supported combination of Record and Keyword
-        l_fapirc = mvpdValidateRecordKeyword( i_record,
-                                              i_keyword);
-        if ( l_fapirc )
-        {
-             FAPI_ERR(" mvpdRingFunc: unsupported record keyword pair ");
-
-            //  break out with fapirc
-            break;
-        }
-
-        // do set specific input parameter checks
-        if (i_mvpdRingFuncOp == MVPD_RING_SET )
-        {
-            // passing NULL pointer to receive needed size is only for get.
-            if (i_pRingBuf == NULL )
-            {
-                FAPI_SET_HWP_ERROR(l_fapirc,
-                                    RC_MVPD_RING_FUNC_INVALID_PARAMETER );
-                //  break out with fapirc
-                break;
-            }
-
-            // Validate ring header to protect vpd
-            l_fapirc =  mvpdValidateRingHeader(
-                         reinterpret_cast<CompressedScanData *>(i_pRingBuf),
-                         i_chipletId,
-                         i_ringId,
-                         io_rRingBufsize);
-            if ( l_fapirc )
-            {
-                FAPI_ERR(" mvpdRingFunc: invalid ring header ");
-                //  break out with fapirc
-                break;
-            }
-
-        }
-
-        //  call fapiGetMvpdField once with a NULL pointer to get the buffer
-        //  size no error should be returned.
-        l_fapirc = fapiGetMvpdField(  i_record,
-                                      i_keyword,
-                                      i_fapiTarget,
-                                      NULL,
-                                      l_recordLen );
-        if ( l_fapirc )
-        {
-            FAPI_ERR("mvpdRingFunc:fapiGetMvpdField failed to get buffer size");
-
-            //  break out with fapirc
-            break;
-        }
-
-        FAPI_DBG( "mvpdRingFunc: fapiGetMvpdField returned record len=0x%x",
-                  l_recordLen );
-
-        //  allocate buffer for the record. Always works
-        l_recordBuf =  static_cast<uint8_t*>(fapiMalloc((size_t)l_recordLen));
-
-        //  load ring from MVPD for this target
-        l_fapirc = fapiGetMvpdField(  i_record,
-                                      i_keyword,
-                                      i_fapiTarget,
-                                      l_recordBuf,
-                                      l_recordLen );
-        if ( l_fapirc )
-        {
-            FAPI_ERR("mvpdRingFunc: fapiGetMvpdField failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-            //  break out with fapirc
-            break;
-        }
-
-        // find ring in the record. It is an error if not there for a "get".
-        // Its ok if not there for a "set". The ring will be added.
-        // l_ringLen set to 0 if not there with l_pRing at the start of padding.
-        l_fapirc = mvpdRingFuncFind (i_chipletId,
-                                     i_ringId,
-                                     l_recordBuf,
-                                     l_recordLen,
-                                     l_pRing,
-                                     l_ringLen);
-        if ( l_fapirc )
-        {
-            FAPI_ERR("mvpdRingFunc: mvpdRingFuncFind failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-            //  break out with fapirc
-            break;
-        }
-        // do the get or set specific operations
-        if (i_mvpdRingFuncOp == MVPD_RING_GET ) // do the get operation
-        {
-            // ensure ring was found. Must be there for "get"
-            if (l_ringLen == 0)  //not found
-            {
-                const   uint8_t    & RING_MODIFIER =   i_ringId;
-                const   uint8_t    & CHIPLET_ID =   i_chipletId;
-                const fapi::Target & CHIP_TARGET = i_fapiTarget;
-                FAPI_SET_HWP_ERROR(l_fapirc, RC_REPAIR_RING_NOT_FOUND );
-                //  break out with fapirc
-                break;
-            }
-
-            // copy ring back to caller's buffer
-            l_fapirc = mvpdRingFuncGet ( l_pRing,
-                                         l_ringLen,
-                                         i_pRingBuf,
-                                         io_rRingBufsize);
-            if ( l_fapirc )
-            {
-                FAPI_ERR("mvpdRingFunc: mvpdRingFuncGet failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-                //  break out with fapirc
-                break;
-            }
-
-        } else {     // set operation
-
-            // update record with caller's ring
-            l_fapirc = mvpdRingFuncSet ( l_recordBuf,
-                                         l_recordLen,
-                                         l_pRing,
-                                         l_ringLen,
-                                         i_pRingBuf,
-                                         io_rRingBufsize);
-            if ( l_fapirc )
-            {
-                FAPI_ERR("mvpdRingFunc: mvpdRingFuncSet failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-                //  break out with fapirc
-                break;
-            }
-            // update record back to the mvpd
-            l_fapirc = fapiSetMvpdField(i_record,
-                                      i_keyword,
-                                      i_fapiTarget,
-                                      l_recordBuf,
-                                      l_recordLen );
-            if ( l_fapirc )
-            {
-                FAPI_ERR("mvpdRingFunc: fapiSetMvpdField failed");
-
-                io_rRingBufsize =   0;
-                //  break out with fapirc
-               break;
-            }
-        }
-
-
-    } while ( 0 );
-
-    //  unload the repair ring
-    fapiFree((void*)l_recordBuf);
-    l_recordBuf =   NULL;
-
-    FAPI_DBG( "mvpdRingFunc: exit bufsize= 0x%x rc= 0x%x",
-                          io_rRingBufsize,
-                          static_cast<uint32_t>(l_fapirc) );
-    return  l_fapirc;
-}
-
-
-#ifndef FAPI_NO_MBVPD
-//******************************************************************************
-// mbvpdRingFunc: getMBvpdRing calls this function to get repair ring
-// note: io_rRingBufsize is only 'output' for get.
-//******************************************************************************
-fapi::ReturnCode mbvpdRingFunc( const mbvpdRingFuncOp i_mbvpdRingFuncOp,
-                                fapi::MBvpdRecord i_record,
-                                fapi::MBvpdKeyword i_keyword,
-                                const fapi::Target &i_fapiTarget,
-                                const uint8_t i_chipletId,
-                                const uint8_t i_ringId,
-                                uint8_t *i_pRingBuf,
-                                uint32_t &io_rRingBufsize)
-{
-    fapi::ReturnCode l_fapirc;
-    uint32_t l_recordLen = 0;
-    uint8_t *l_recordBuf = NULL;
-    uint8_t *l_pRing = NULL;
-    uint32_t l_ringLen = 0;
-
-   FAPI_DBG("mbvpdRingFunc:entry op=0x%x ringId=0x%x chipletId=0x%x size=0x%x ",
-             i_mbvpdRingFuncOp, i_ringId, i_chipletId, io_rRingBufsize  );
-
-    do {
-        // do input parameter error checks
-        // check for supported combination of Record and Keyword
-        l_fapirc = mbvpdValidateRecordKeyword( i_record, i_keyword);
-
-        if (l_fapirc)
-        {
-             FAPI_ERR(" mbvpdRingFunc: unsupported record keyword pair ");
-            //  break out with fapirc
-            break;
-        }
-
-        //  call fapiGetMBvpdField once with a NULL pointer to get the buffer
-        //  size no error should be returned.
-        l_fapirc = fapiGetMBvpdField( i_record,
-                                      i_keyword,
-                                      i_fapiTarget,
-                                      NULL,
-                                      l_recordLen );
-        if (l_fapirc)
-        {
-            FAPI_ERR("mbvpdRingFunc:fapiGetMBvpdField failed"
-                         " to get buffer size");
-            //  break out with fapirc
-            break;
-        }
-
-        FAPI_DBG("mbvpdRingFunc: fapiGetMBvpdField returned record len=0x%x",
-                  l_recordLen );
-
-        //  allocate buffer for the record. Always works
-        l_recordBuf = static_cast<uint8_t*>(fapiMalloc((size_t)l_recordLen));
-
-        //  load ring from MBVPD for this target
-        l_fapirc = fapiGetMBvpdField( i_record,
-                                      i_keyword,
-                                      i_fapiTarget,
-                                      l_recordBuf,
-                                      l_recordLen );
-        if (l_fapirc)
-        {
-            FAPI_ERR("mbvpdRingFunc: fapiGetMBvpdField failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-            //  break out with fapirc
-            break;
-        }
-
-        // find ring in the record. It is an error if not there for a "get".
-        l_fapirc = mvpdRingFuncFind ( i_chipletId,
-                                  i_ringId,
-                                  l_recordBuf,
-                                  l_recordLen,
-                                  l_pRing,
-                                  l_ringLen);
-        if (l_fapirc)
-        {
-            FAPI_ERR("mbvpdRingFunc: mvpdRingFuncFind failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-            //  break out with fapirc
-            break;
-        }
-        // do the get operations
-        if (i_mbvpdRingFuncOp == MBVPD_RING_GET) // do the get operation
-        {
-            // ensure ring was found. Must be there for "get"
-            if (l_ringLen == 0)  //not found
-            {
-                const uint8_t & RING_MODIFIER = i_ringId;
-                const uint8_t & CHIPLET_ID = i_chipletId;
-                const fapi::Target & CHIP_TARGET = i_fapiTarget;
-                FAPI_SET_HWP_ERROR(l_fapirc, RC_REPAIR_RING_NOT_FOUND );
-                //  break out with fapirc
-                break;
-            }
-
-            // copy ring back to caller's buffer
-            l_fapirc = mvpdRingFuncGet ( l_pRing,
-                                     l_ringLen,
-                                     i_pRingBuf,
-                                     io_rRingBufsize);
-            if (l_fapirc)
-            {
-                FAPI_ERR("mbvpdRingFunc: mvpdRingFuncGet failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-                //  break out with fapirc
-                break;
-            }
-        }
-        else
-        {
-            // Set operation has been removed, if need to be implemented
-            //copy over from mvpdRingFuncs
-            FAPI_ERR("mbvpdRingFunc: Invalid parameter function");
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_MBVPD_RING_FUNC_INVALID_PARAMETER);
-        }
-
-    } while ( 0 );
-
-    //  unload the repair ring
-    fapiFree((void*)l_recordBuf);
-    l_recordBuf =   NULL;
-
-    FAPI_DBG( "mbvpdRingFunc: exit bufsize= 0x%x rc= 0x%x",
-                          io_rRingBufsize,
-                          static_cast<uint32_t>(l_fapirc) );
-    return  l_fapirc;
-}
-#endif
-
-
-//******************************************************************************
-// mvpdRingFuncFind: step through the record looking at rings for a match.
-// o_rpRing returns a pointer to the ring if it is there in the record
-//          if not there, returns a pointer to the start of the padding after
-//          the last ring.
-// o_rRingLen returns the number of bytes in the ring (header and data)
-//          Will be 0 if ring not found.
-//******************************************************************************
-fapi::ReturnCode mvpdRingFuncFind( const uint8_t    i_chipletId,
-                                const uint8_t       i_ringId,
-                                uint8_t           * i_pRecordBuf,
-                                uint32_t            i_recordBufLen,
-                                uint8_t           * &o_rpRing,
-                                uint32_t            &o_rRingLen)
-{
-    fapi::ReturnCode        l_fapirc;
-    uint8_t                 *l_pRing        =   NULL;
-    uint32_t                l_offset        =   0;
-    CompressedScanData      *l_pScanData    =   NULL;
-    bool                    l_foundflag     =   false;
-
-    // initialize return fields in case of an error.
-    o_rpRing=NULL;
-    o_rRingLen=0;
-
-    FAPI_DBG("mvpdRingFuncFind: entry chipletId=0x%x, ringId=0x%x ",
-             i_chipletId,
-             i_ringId  );
-
-    do  {
-        //  point to #R record
-        l_pRing =   i_pRecordBuf;
-
-        //  Find first RSA data block in ring (fixed offset defined by
-        //      MVPD spec)
-        //
-        //  First byte in record should be the version number, skip
-        //      over this.
-        //
-        FAPI_DBG( "mvpdRingFuncFind: record version = 0x%x", *l_pRing );
-        l_pRing++;
-        l_offset    =   0;
-
-        l_foundflag =   false;
-        // be sure that data we will look at is within the passed buffer
-        while ( l_offset+sizeof(CompressedScanData) < i_recordBufLen )
-        {
-            //  point to header
-            l_pScanData =
-                reinterpret_cast<CompressedScanData *>( l_pRing+l_offset );
-
-            //  Check magic key to make sure this is a valid record.
-            if ( FAPI_BE32TOH(l_pScanData->iv_magic) != RS4_MAGIC )
-            {
-                FAPI_DBG("mvpdRingFuncFind:Header 0x%x offset 0x%x,end of list",
-                            FAPI_BE32TOH(l_pScanData->iv_magic),
-                            l_offset  );
-                break;
-            }
-            //  dump record info for debug
-            FAPI_DBG("mvpdRingFuncFind:%d ringId=0x%x chipletId=0x%x"
-                        " ringlen=0x%x size=0x%x",
-                        l_offset,
-                        l_pScanData->iv_ringId,
-                        l_pScanData->iv_chipletId,
-                        FAPI_BE32TOH(l_pScanData->iv_length),
-                        FAPI_BE32TOH(l_pScanData->iv_size)  );
-
-
-            if (    (l_pScanData->iv_ringId == i_ringId)
-                 && (l_pScanData->iv_chipletId == i_chipletId) )
-            {
-                FAPI_DBG( "mvpdRingFuncFind: Found it: ring=0x%x, chiplet=0x%x,"
-                          " ringlen=0x%x",
-                          i_ringId,
-                          i_chipletId,
-                          FAPI_BE32TOH(l_pScanData->iv_length) );
-
-                if (l_offset+FAPI_BE32TOH(l_pScanData->iv_size)>i_recordBufLen)
-                {
-                    // shouldn't happen, but does not all fit
-                    FAPI_SET_HWP_ERROR(l_fapirc, RC_REPAIR_RING_INVALID_SIZE );
-                    break;
-                }
-                l_foundflag =   true;
-                o_rpRing = l_pRing+l_offset;
-                o_rRingLen=FAPI_BE32TOH(l_pScanData->iv_size);
-                // got it, break out of scan loop
-                break;
-            }
-
-            // being defensive.
-            if (FAPI_BE32TOH(l_pScanData->iv_size) == 0)
-            {
-                // size of 0 is invalid, would loop forever.
-                break;
-            }
-            // bump to next ring
-            l_offset +=  FAPI_BE32TOH(l_pScanData->iv_size) ;
-
-        }   // end while scan loop
-
-        //  if no other error and not found, indicate with 0 size.
-        if ( !l_fapirc && ! l_foundflag )
-        {
-            o_rpRing = l_pRing+l_offset; //return pointer to end of list
-                                           //incase needed for appending
-            o_rRingLen=0;              //indicate not found
-        }
-
-    }  while ( 0 );
-
-
-    FAPI_DBG("mvpdRingFuncFind: exit *ring= 0x%p", o_rpRing);
-    FAPI_IMP("mvpdRingFuncFind: exit chipletId=0x%x, ringId=0x%x size=0x%x"
-                          " rc=0x%x",
-                          i_chipletId,
-                          i_ringId,
-                          o_rRingLen,
-                          static_cast<uint32_t>(l_fapirc) );
-
-    return  l_fapirc;
-}
-
-//******************************************************************************
-// mvpdValidateRingHeader
-//******************************************************************************
-fapi::ReturnCode mvpdValidateRingHeader( CompressedScanData * i_pRingBuf,
-                                     uint8_t              i_chipletId,
-                                     uint8_t              i_ringId,
-                                     uint32_t             i_ringBufsize)
-{
-    fapi::ReturnCode        l_fapirc;
-
-    if ( i_ringBufsize <= sizeof(CompressedScanData) ||
-                FAPI_BE32TOH(i_pRingBuf->iv_magic) != RS4_MAGIC ||
-                i_pRingBuf->iv_ringId != i_ringId ||
-                i_pRingBuf->iv_chipletId != i_chipletId ||
-                FAPI_BE32TOH(i_pRingBuf->iv_size) != i_ringBufsize)
-   {
-       FAPI_SET_HWP_ERROR(l_fapirc, RC_MVPD_RING_FUNC_INVALID_PARAMETER );
-   }
-   return l_fapirc;
-}
-
-//******************************************************************************
-// mvpdRingFuncGet: copy the ring back to the caller
-//******************************************************************************
-fapi::ReturnCode mvpdRingFuncGet ( uint8_t     *i_pRing,
-                               uint32_t     i_ringLen,
-                               uint8_t     *i_pCallerRingBuf,
-                               uint32_t    &io_rCallerRingBufLen)
-{
-    fapi::ReturnCode        l_fapirc;
-
-    do {
-        //  return buffer pointer is NULL if just looking for the size
-        if  (   i_pCallerRingBuf == NULL )
-        {
-            io_rCallerRingBufLen = i_ringLen;
-            //  break out of do block with success rc
-            break;
-        }
-        //  check if we have enough space
-        if ( io_rCallerRingBufLen < i_ringLen )
-        {
-            FAPI_ERR( "mvpdRingFuncGet: output buffer too small:  0x%x < 0x%x",
-                          io_rCallerRingBufLen,
-                          i_ringLen
-                          );
-
-            //  return actual size of data, so caller can re-try with
-            //  the correct value
-            io_rCallerRingBufLen =   i_ringLen;
-            FAPI_SET_HWP_ERROR(l_fapirc, RC_REPAIR_RING_INVALID_SIZE );
-
-            //  break out of do block with fapi rc set
-            break;
-        }
-       //  we're good, copy data into the passed-in buffer
-       FAPI_DBG( "mvpdRingFuncGet: memcpy 0x%p 0x%p 0x%x",
-                    i_pCallerRingBuf,
-                    i_pRing,
-                    i_ringLen );
-       memcpy( i_pCallerRingBuf, i_pRing, i_ringLen );
-       io_rCallerRingBufLen =   i_ringLen;
-
-   }  while (0);
-
-   FAPI_DBG( "mvpdRingFuncGet: exit bufsize= 0x%x rc= 0x%x",
-                          io_rCallerRingBufLen,
-                          static_cast<uint32_t>(l_fapirc) );
-
-   return l_fapirc;
-}
-
-//******************************************************************************
-// mvpdRingFuncSet: update the record with the caller's ring.
-//******************************************************************************
-fapi::ReturnCode mvpdRingFuncSet ( uint8_t     *i_pRecordBuf,
-                               uint32_t     i_recordLen,
-                               uint8_t     *i_pRing,
-                               uint32_t     i_ringLen,
-                               uint8_t     *i_pCallerRingBuf,
-                               uint32_t     i_callerRingBufLen)
-{
-    fapi::ReturnCode l_fapirc;
-    uint8_t          *l_to = NULL;
-    uint8_t          *l_fr = NULL;
-    uint32_t         l_len = 0;
-    uint8_t          *l_pRingEnd; // pointer into record to start of pad at end
-
-    FAPI_DBG( "mvpdRingFuncSet: pRing=0x%p rLen=0x%x pCaller=0x%p cLen=0x%x",
-                       i_pRing,
-                       i_ringLen,
-                       i_pCallerRingBuf,
-                       i_callerRingBufLen);
-
-    do {
-        // if exact fit, update in place
-        if (i_callerRingBufLen == i_ringLen)
-        {
-            l_to = i_pRing;
-            l_fr = i_pCallerRingBuf;
-            l_len = i_callerRingBufLen;
-            FAPI_DBG( "mvpdRingFuncSet: update in place-memcpy 0x%p 0x%p 0x%x",
-                       l_to,
-                       l_fr,
-                       l_len);
-            memcpy (l_to, l_fr, l_len);
-
-            // break out successful
-            break;
-        }
-
-        // will need the end for shifting... look for something invalid
-        l_fapirc = mvpdRingFuncFind (0x00,
-                                     0x00,
-                                     i_pRecordBuf,
-                                     i_recordLen,
-                                     l_pRingEnd, // find start of padding
-                                     l_len);
-        if ( l_fapirc )
-        {
-            FAPI_ERR("mvpdRingFuncSet: mvpdRingFuncFind failed rc=0x%x",
-                     static_cast<uint32_t>(l_fapirc));
-            //  break out with fapirc
-            break;
-        }
-        FAPI_DBG( "mvpdRingFuncSet: end= 0x%p",
-                                 l_pRingEnd);
-
-        // if not there, then append if it fits
-        if (i_ringLen == 0 ) //is not currently in record (0 len from find)
-        {
-            if (l_pRingEnd+i_callerRingBufLen > i_pRecordBuf+i_recordLen)
-            {
-          FAPI_ERR( "mvpdRingFuncSet: not enough room to append ");
-                FAPI_SET_HWP_ERROR(l_fapirc,
-                                 RC_MVPD_RING_FUNC_INSUFFICIENT_RECORD_SPACE );
-                //  break out of do block with fapi rc set
-                break;
-            }
-            l_to = i_pRing;
-            l_fr = i_pCallerRingBuf;
-            l_len = i_callerRingBufLen;
-            FAPI_DBG( "mvpdRingFuncSet: append-memcpy 0x%p 0x%p 0x%x",
-                       l_to,
-                       l_fr,
-                       l_len);
-            memcpy (l_to, l_fr, l_len);
-
-            // break out successful
-            break;
-        }
-
-        // if smaller, then shift left and zero fill
-        if (i_callerRingBufLen < i_ringLen)
-        {
-            l_to = i_pRing;
-            l_fr = i_pCallerRingBuf;
-            l_len = i_callerRingBufLen;
-            FAPI_DBG( "mvpdRingFuncSet: shrink-memcpy 0x%p 0x%p 0x%x",
-                       l_to,
-                       l_fr,
-                       l_len);
-            memcpy (l_to, l_fr, l_len);
-
-            l_to = i_pRing+i_callerRingBufLen;
-            l_fr = i_pRing+i_ringLen;
-            l_len = (l_pRingEnd)-(i_pRing+i_ringLen);
-            FAPI_DBG( "mvpdRingFuncSet: shrink-memmove 0x%p 0x%p 0x%x",
-                       l_to,
-                       l_fr,
-                       l_len);
-            memmove (l_to, l_fr, l_len); //use memmove, always overlaps.
-
-            l_to = (l_pRingEnd)-(i_ringLen-i_callerRingBufLen);
-            l_len = i_ringLen-i_callerRingBufLen;
-            FAPI_DBG( "mvpdRingFuncSet: shrink-memset 0x%p 0x%x 0x%x",
-                       l_to,
-                       0x00,
-                       l_len);
-            memset (l_to, 0x00, l_len);
-
-            // break out successful
-            break;
-
-        }
-
-        // if larger, then shift right, if it fits
-        if (i_callerRingBufLen > i_ringLen)
-        {
-            // ensure the padding can contain the growth
-            if ((l_pRingEnd + (i_callerRingBufLen - i_ringLen))  >
-                (i_pRecordBuf + i_recordLen))
-            {
-                FAPI_ERR( "mvpdRingFuncSet: not enough room to insert ");
-                FAPI_SET_HWP_ERROR(l_fapirc,
-                                 RC_MVPD_RING_FUNC_INSUFFICIENT_RECORD_SPACE );
-                //  break out of do block with fapi rc set
-                break;
-            }
-
-            l_to = i_pRing+i_callerRingBufLen;
-            l_fr = i_pRing+i_ringLen;
-            l_len = l_pRingEnd-(i_pRing+i_ringLen);
-            FAPI_DBG( "mvpdRingFuncSet: insert-memmove 0x%p 0x%p 0x%x",
-                       l_to,
-                       l_fr,
-                       l_len);
-            memmove (l_to, l_fr, l_len);
-
-            l_to = i_pRing;
-            l_fr = i_pCallerRingBuf;
-            l_len = i_callerRingBufLen;
-            FAPI_DBG( "mvpdRingFuncSet: insert-memcpy 0x%p 0x%p 0x%x",
-                       l_to,
-                       l_fr,
-                       l_len);
-            memcpy (l_to, l_fr, l_len);
-
-            // break out successful
-            break;
-        }
-        FAPI_ERR( "mvpdRingFuncSet: shouldn't get to here" );
-
-    } while (0);
-
-    FAPI_DBG( "mvpdRingFuncSet: exit  rc= 0x%x",
-                          static_cast<uint32_t>(l_fapirc) );
-
-   return l_fapirc;
-}
-
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.H b/src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.H
deleted file mode 100644
index 8c3d6bc1e..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.H
+++ /dev/null
@@ -1,115 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/mvpdRingFuncs.H $             */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: mvpdRingFuncs.H,v 1.4 2014/07/16 19:07:08 cswenson Exp $
-/**
- *  @file mvpdRingFuncs.H
- *
- *  @brief Prototype for mvpdRingFuncs()
- */
-
- #ifndef    _HWP_MVPDRINGFUNCS_
- #define    _HWP_MVPDRINGFUNCS_
-
- #include   <fapi.H>
-
-// mvpdRingFunc can be used for get and set
-enum mvpdRingFuncOp
-{
-    MVPD_RING_GET,
-    MVPD_RING_SET,
-};
-
-#ifndef FAPI_NO_MBVPD
-// Only get operation for mbvpd Rings
-enum mbvpdRingFuncOp
-{
-    MBVPD_RING_GET,
-};
-#endif
-
-extern "C"
-{
-
-/**
- * @brief   get or set the requested ring for the record and keyword
- *          for the specified target CPU.
- *
- *          detailed comments on get and set are in the
- *          getMvpdRing.H and setMvpdRing.H and apply here as well.
- *
- * @param i_mvpdRingFuncOp  -   indicate get or set via enum mvpdRingFuncOp
- * @param i_record          -   Record enumerator
- * @param i_keyword         -   Keyword enumerator
- * @param i_fapiTarget      -   cpu target
- * @param i_chipletId       -   Chiplet ID
- * @param i_ringId          -   Ring ID
- * @param i_pRingBuf        -   The buffer to receive or send the ring
- * @param io_rRingBufsize   -   Size of ring / ring buffer
- *
- * @return fapi::ReturnCode -   FAPI_RC_SUCCESS if success,
- *                              relevant error code for failure.
- */
-fapi::ReturnCode mvpdRingFunc(  mvpdRingFuncOp       i_mvpdRingFuncOp,
-                                fapi::MvpdRecord     i_record,
-                                fapi::MvpdKeyword    i_keyword,
-                                const fapi::Target   &i_fapiTarget,
-                                const uint8_t        i_chipletId,
-                                const uint8_t        i_ringId,
-                                uint8_t              *i_pRingBuf,
-                                uint32_t             &io_rRingBufsize);
-
-#ifndef FAPI_NO_MBVPD
-/**
- * @brief   get the requested ring for the record and keyword
- *          for the specified target CPU.
- *
- *          detailed comments on get are in getMbvpdRing.H
- *          and apply here as well.
- *
- * @param i_mbvpdRingFuncOp  -  indicate get or set via enum mbvpdRingFuncOp
- * @param i_record          -   Record enumerator
- * @param i_keyword         -   Keyword enumerator
- * @param i_fapiTarget      -   cpu target
- * @param i_chipletId       -   Chiplet ID
- * @param i_ringId          -   Ring ID
- * @param i_pRingBuf        -   The buffer to receive or send the ring
- * @param io_rRingBufsize   -   Size of ring / ring buffer
- *
- * @return fapi::ReturnCode -   FAPI_RC_SUCCESS if success,
- *                              relevant error code for failure.
- */
-fapi::ReturnCode mbvpdRingFunc( mbvpdRingFuncOp i_mbvpdRingFuncOp,
-                                fapi::MBvpdRecord i_record,
-                                fapi::MBvpdKeyword i_keyword,
-                                const fapi::Target &i_fapiTarget,
-                                const uint8_t i_chipletId,
-                                const uint8_t i_ringId,
-                                uint8_t *i_pRingBuf,
-                                uint32_t &io_rRingBufsize);
-#endif
-
-} // extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.C b/src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.C
deleted file mode 100644
index d28a810c8..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.C
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.C $               */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: setMvpdRing.C,v 1.2 2014/06/27 19:24:02 thi Exp $
-/**
- *  @file setMvpdRing.C
- *
- *  @brief update rings in MVPD records
- *
- */
-
-#include    <stdint.h>
-
-//  fapi support
-#include    <fapi.H>
-
-#include    <setMvpdRing.H>
-#include    <mvpdRingFuncs.H>
-
-extern "C"
-{
-using   namespace   fapi;
-
-// setMvpdRing: Wrapper to call common function mvpdRingFunc
-fapi::ReturnCode setMvpdRing( fapi::MvpdRecord i_record,
-                                fapi::MvpdKeyword i_keyword,
-                                const fapi::Target &i_fapiTarget,
-                                const uint8_t       i_chipletId,
-                                const uint8_t       i_ringId,
-                                uint8_t             *i_pRingBuf,
-                                uint32_t            i_rRingBufsize)
-{
-    fapi::ReturnCode        l_fapirc;
-
-    FAPI_DBG("setMvpdRing: entry ringId=0x%x, chipletId=0x%x, size=0x%x ",
-             i_ringId,
-             i_chipletId,
-             i_rRingBufsize  );
-
-    // common get and set processing
-    l_fapirc = mvpdRingFunc(MVPD_RING_SET,
-                            i_record,
-                            i_keyword,
-                            i_fapiTarget,
-                            i_chipletId,
-                            i_ringId,
-                            i_pRingBuf,
-                            i_rRingBufsize); //in and out for common code.
-                                             //in only for set. 
-
-    FAPI_DBG("setMvpdRing: exit rc=0x%x",
-               static_cast<uint32_t>(l_fapirc) );
-
-    return  l_fapirc;
-}
-
-}   // extern "C"
diff --git a/src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.H b/src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.H
deleted file mode 100644
index 8e69d0b7b..000000000
--- a/src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.H
+++ /dev/null
@@ -1,94 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/mvpd_accessors/setMvpdRing.H $               */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: setMvpdRing.H,v 1.2 2013/01/25 21:12:40 whs Exp $
-/**
- *  @file setMvpdRing.H
- *
- *  @brief Prototype for setMvpdRing() -
- *          get a repair ring from a MVPD record
- */
-
- #ifndef    _HWP_SETMVPDRING_
- #define    _HWP_SETMVPDRING_
-
- #include   <fapi.H>
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*setMvpdRing_FP_t) 
-        (fapi::MvpdRecord,fapi::MvpdKeyword, const fapi::Target &,
-         const uint8_t, const uint8_t, uint8_t *, uint32_t);
-
-extern "C"
-{
-
-/**
- * @brief   set specified ring from MVPD for the specified target CPU.
- *
- * A Ring Id Chiplet Id should be unique in the mvpd Record.
- * The code does not validate. No assumption should be made on which would
- * be updated if there are multiple.
- *
- * The set ring can be the same size or smaller than an existing ring.
- * The ring can be larger than the existing ring or can be added (was
- * not there before) if there is room in the record. 
- *
- * @param i_record          -   Record enumerator
- * @param i_keyword         -   Keyword enumerator
- * Supported Rings are:
- *                   MVPD_RECORD_CP00 - MVPD_KEYWORD_PDR
- *                   MVPD_RECORD_CP00 - MVPD_KEYWORD_PDG
- * @param i_fapiTarget      -   cpu target
- * @param i_chipletId       -   Chiplet ID
- * @param i_ringId          -   Ring ID
- * @param i_pRingBuf        -   pointer to a buffer allocated by the caller
- *                              to with the ring header and data to set.
- *                              Can not be NULL. 
- * @param i_rRingBufsize    -   size of ring buffer that the caller has
- *                              allocated.
- *                              The buffer contains the CompressedScanData
- *                              structure followed by compressed data. The 
- *                              caller does compression and decompression.
- *                              The header needs to include the RS4 magic 
- *                              number. The ring ID and chiplet ID must match
- *                              the passed parameters. The size must match the
- *                              parameter size. 
- *
- *  Buffer:   io_rRingBufsize returns xNN.
- *    byte x0  CompressedScanData structure (rs4 header)
- *    byte x18 compressed data (sizeof CompressedScanData is 0x18)
- *    byte xNN last byte of compressed data*
- *
- * @return fapi::ReturnCode -   FAPI_RC_SUCCESS if success,
- *                              relevant error code for failure.
- */
-fapi::ReturnCode setMvpdRing(   fapi::MvpdRecord i_record,
-                                fapi::MvpdKeyword i_keyword,
-                                const fapi::Target  &i_fapiTarget,
-                                const uint8_t       i_chipletId,
-                                const uint8_t       i_ringId,
-                                uint8_t             *i_pRingBuf,
-                                uint32_t            i_rRingBufsize );
-
-}
-
-#endif
diff --git a/src/usr/hwpf/hwp/nest_chiplets/makefile b/src/usr/hwpf/hwp/nest_chiplets/makefile
deleted file mode 100644
index c300c808e..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/makefile
+++ /dev/null
@@ -1,61 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/nest_chiplets/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-MODULE = nest_chiplets
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/secure_boot
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += proc_start_clocks_chiplets.o
-OBJS += proc_a_x_pci_dmi_pll_initf.o
-OBJS += proc_a_x_pci_dmi_pll_setup.o
-OBJS += proc_a_x_pci_dmi_pll_utils.o
-OBJS += proc_pcie_slot_power.o
-
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
deleted file mode 100644
index b58d55429..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C
+++ /dev/null
@@ -1,422 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_initf.C,v 1.20 2015/05/14 21:03:40 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_a_x_pci_dmi_pll_initf.C
-// *! DESCRIPTION : Scan PLL settings for A/X/PCI/DMI PLLs
-// *!
-// *! OWNER NAME  : Ralph Koester            Email: rkoester@de.ibm.com
-// *!
-// *! The purpose of this procedure is to scan in runtime PLL settings
-// *! for the X/A/PCIE/DMI PLLs
-// *!
-// *! - prerequisite is that the PLLs are in bypass mode
-// *! - setup the PLLs by a ring load of PLL config bits
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_a_x_pci_dmi_pll_initf.H>
-#include <proc_a_x_pci_dmi_pll_utils.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitons
-//------------------------------------------------------------------------------
-const uint32_t DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ = 4800;
-
-
-//------------------------------------------------------------------------------
-// Function definition
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Scan PLL settings for A/X/PCI/DMI PLLs
-//
-// parameters: i_target    => chip target
-//             i_startX    => True to start X BUS PLL, else false
-//             i_startA    => True to start A BUS PLL, else false
-//             i_startPCIE => True to start PCIE PLL, else false
-//             i_startDMI  => True to start DMI PLL, else false
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(
-    const fapi::Target & i_target,
-    const bool i_startX,
-    const bool i_startA,
-    const bool i_startPCIE,
-    const bool i_startDMI)
-{
-    // attribute data
-    uint8_t pcie_enable_attr;
-    uint8_t abus_enable_attr;
-    uint8_t is_simulation;
-    uint8_t lctank_pll_vco_workaround = 0;
-
-    // return codes
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_INF("\n   Parameter1, start_XBUS=%s\n   Parameter2, start_ABUS=%s\n   Parameter3, start_PCIE=%s\n   Parameter4, start_DMI=%s \n" ,
-             i_startX ? "true":"false",
-             i_startA ? "true":"false",
-             i_startPCIE ? "true":"false",
-             i_startDMI ? "true":"false");
-    do
-    {
-        //------------//
-        // Workaround //
-        //------------//
-        rc = FAPI_ATTR_GET(ATTR_IS_SIMULATION,
-                           NULL,
-                           is_simulation);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying ATTR_IS_SIMULATION");
-            break;
-        }
-
-        if (!is_simulation)
-        {
-            rc = FAPI_ATTR_GET(ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG,
-                               &i_target,
-                               lctank_pll_vco_workaround);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error querying Chip EC feature: ATTR_CHIP_EC_FEATURE_LCTANK_PLL_VCO_BUG");
-                break;
-            }
-        }
-
-        FAPI_DBG("lctank PLL VCO bug circumvention is %s",
-                 (lctank_pll_vco_workaround ? "enabled" : "disabled"));
-
-
-        //------------//
-        // X Bus PLL  //
-        //------------//
-        if (!i_startX)
-        {
-            FAPI_DBG("X BUS PLL not selected for setup in this routine.");
-        }
-        else
-        {
-            FAPI_INF("This routine does not do X-BUS PLL setup at this time!.");
-            FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic.");
-        }
-        // end X-bus PLL setup
-
-
-        //------------//
-        // A Bus PLL  //
-        //------------//
-
-        // query ABUS partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
-                           &i_target,
-                           abus_enable_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying ATTR_PROC_A_ENABLE");
-            break;
-        }
-
-        if (!i_startA)
-        {
-            FAPI_DBG("A BUS PLL not selected for setup in this routine.");
-        }
-        else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE)
-        {
-            FAPI_DBG("A BUS PLL setup skipped (partial good).");
-        }
-        else
-        {
-            // apply workaround for A PLL for all frequencies
-            bool a_lctank_pll_vco_workaround = (lctank_pll_vco_workaround != 0);
-            FAPI_DBG("A-Bus PLL VCO bug circumvention is %s",
-                     (a_lctank_pll_vco_workaround ? "enabled" : "disabled"));
-
-            // establish base ring state
-            rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                RING_ADDRESS_PROC_AB_BNDY_PLL,
-                                                RING_OP_BASE,
-                                                RING_BUS_ID_0,
-                                                false);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                break;
-            }
-
-            if (a_lctank_pll_vco_workaround)
-            {
-                rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                    RING_ADDRESS_PROC_AB_BNDY_PLL,
-                                                    RING_OP_MOD_VCO_S1,
-                                                    RING_BUS_ID_0,
-                                                    false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                    break;
-                }
-
-                // release PLL (skip lock check) & re-scan
-                rc = proc_a_x_pci_dmi_pll_release_pll(i_target,
-                                                      A_BUS_CHIPLET_0x08000000,
-                                                      false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll");
-                    break;
-                }
-
-                rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                    RING_ADDRESS_PROC_AB_BNDY_PLL,
-                                                    RING_OP_MOD_VCO_S2,
-                                                    RING_BUS_ID_0,
-                                                    false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                    break;
-                }
-            }
-            FAPI_INF("Done setting up A-Bus PLL. ");
-        }  // end A PLL
-
-
-        //----------//
-        // DMI PLL  //
-        //----------//
-        if (!i_startDMI)
-        {
-            FAPI_DBG("DMI PLL not selected for setup in this routine.");
-        }
-        else
-        {
-            // only apply DMI workaround if needed when frequency < 4800 MHz,
-            bool dmi_lctank_pll_vco_workaround = (lctank_pll_vco_workaround != 0);
-            uint32_t dmi_freq;
-            if (dmi_lctank_pll_vco_workaround)
-            {
-                // frequency reported via X attribute should be equivalent to DMI freq
-                // given that we are running NEST off of X-bus PLL (NEST=X/2) and
-                // DMI=NEST*2
-                rc = FAPI_ATTR_GET(ATTR_FREQ_X, NULL, dmi_freq);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Failed to get attribute: ATTR_FREQ_X");
-                    break;
-                }
-
-                if (dmi_freq >= DMI_PLL_VCO_WORKAROUND_THRESHOLD_FREQ)
-                {
-                    dmi_lctank_pll_vco_workaround = false;
-                }
-            }
-            FAPI_DBG("DMI PLL VCO bug circumvention is %s",
-                     (dmi_lctank_pll_vco_workaround ? "enabled" : "disabled"));
-
-            // establish base ring state
-            rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                RING_ADDRESS_PROC_PB_BNDY_DMIPLL,
-                                                RING_OP_BASE,
-                                                RING_BUS_ID_0,
-                                                true);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                break;
-            }
-
-            if (dmi_lctank_pll_vco_workaround)
-            {
-                rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                    RING_ADDRESS_PROC_PB_BNDY_DMIPLL,
-                                                    RING_OP_MOD_VCO_S1,
-                                                    RING_BUS_ID_0,
-                                                    true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                    break;
-                }
-
-                // release PLL (skip lock check) & re-scan
-                rc = proc_a_x_pci_dmi_pll_release_pll(i_target,
-                                                      NEST_CHIPLET_0x02000000,
-                                                      false);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll");
-                    break;
-                }
-
-                rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                    RING_ADDRESS_PROC_PB_BNDY_DMIPLL,
-                                                    RING_OP_MOD_VCO_S2,
-                                                    RING_BUS_ID_0,
-                                                    true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                    break;
-                }
-            }
-
-            FAPI_INF("Done setting up DMI PLL. ");
-        }  // end DMI PLL
-
-
-        //-----------//
-        // PCIE PLL  //
-        //-----------//
-
-        // query PCIE partial good attribute
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
-                           &i_target,
-                           pcie_enable_attr);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE");
-            break;
-        }
-
-        if (!i_startPCIE)
-        {
-            FAPI_DBG("PCIE PLL not selected for setup in this routine.");
-        }
-        else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
-        {
-            FAPI_DBG("PCIE PLL setup skipped (partial good).");
-        }
-        else
-        {
-            // establish base ring state
-            rc = proc_a_x_pci_dmi_pll_scan_bndy(i_target,
-                                                RING_ADDRESS_PROC_PCI_BNDY_PLL,
-                                                RING_OP_BASE,
-                                                RING_BUS_ID_0,
-                                                false);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_a_x_pci_dmi_pll_scan_bndy");
-                break;
-            }
-
-            FAPI_INF("Done setting up PCIE PLL.");
-        }  // end PCIE PLL
-
-    } while (0); // end do
-
-    // mark function exit
-    FAPI_INF("Exit");
-    return rc;
-}  // end FAPI procedure proc_a_x_pci_dmi_pll_initf
-
-
-} // extern "C"
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: proc_a_x_pci_dmi_pll_initf.C,v $
-Revision 1.20  2015/05/14 21:03:40  jmcgill
-Update to use modified proc_a_x_pci_dmi_pll_utils API
-
-Revision 1.19  2014/12/02 00:17:23  szhong
-remove hardcoded bndy pll length in code
-
-Revision 1.18  2014/11/13 20:17:22  szhong
-adjust pb_bndy_dmi_pll length to 240
-
-Revision 1.17  2014/11/11 22:10:35  szhong
-increased attribute data length to support Naples
-
-Revision 1.16  2014/01/07 14:43:23  mfred
-Checking in updates from Andrea Ma:  Include statements fixed and one fapi dbg statement changed.
-
-Revision 1.15  2013/09/30 16:09:56  jmcgill
-fix HW268965
-
-Revision 1.14  2013/04/29 16:38:51  jmcgill
-add constants for Murano DD1 ccalload/ccalfmin ring offsets used in workaround
-
-Revision 1.13  2013/04/18 17:33:35  jmcgill
-qualify workaround for DMI bus based on frequency
-
-Revision 1.12  2013/04/17 22:38:38  jmcgill
-implement A/DMI PLL workaround for SW194943, reorganize code to use common subroutines for PLL scan/setup
-
-Revision 1.11  2013/01/24 16:34:45  jmcgill
-fix comment as well...
-
-Revision 1.10  2013/01/24 16:33:40  jmcgill
-adjust for DMI attribute change
-
-Revision 1.9  2013/01/20 19:21:03  jmcgill
-update for A chiplet partial good support
-
-Revision 1.8  2013/01/10 14:42:53  jmcgill
-add partial good support
-
-Revision 1.6  2012/12/07 17:09:39  mfred
-fix to add DMI PLL settings for MC1 for Venice.
-
-Revision 1.5  2012/12/06 22:59:18  mfred
-adjust DMI PLL settings based on chip type.
-
-Revision 1.4  2012/08/27 15:29:03  mfred
-Fixed some findings from the latest FW code review.
-
-Revision 1.3  2012/08/20 16:00:09  jmcgill
-adjust ring offsets for 39 model
-
-Revision 1.2  2012/08/14 18:32:42  mfred
-Changed input parms from bool & to const bool.
-
-Revision 1.1  2012/08/14 14:18:02  mfred
-Separating proc_a_x_pci_dmi_pll_setup into two hwp.  And update code to use real scanning instead of sim cheats.
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H
deleted file mode 100644
index c7f14c671..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H
+++ /dev/null
@@ -1,87 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_initf.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_initf.H,v 1.5 2015/05/14 21:03:42 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_initf.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_a_x_pci_dmi_pll_initf.H
-// *! DESCRIPTION : Scan PLL settings for A/X/PCI/DMI PLLs
-// *!
-// *! OWNER NAME  : Ralph Koester            Email: rkoester@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_A_X_PCI_DMI_PLL_INITF_H_
-#define _PROC_A_X_PCI_DMI_PLL_INITF_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_a_x_pci_dmi_pll_initf_FP_t)(const fapi::Target &,
-                                                            const bool,
-                                                            const bool,
-                                                            const bool,
-                                                            const bool);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-/**
- * @brief Scan PLL settings for A/X/PCI/DMI PLLs
- *
- * @param[in] i_target     Reference to target
- * @param[in] i_startX     True if X PLL should be initalized, else false
- * @param[in] i_startA     True if A PLL should be initalized, else false
- * @param[in] i_startPCIE  True if PCIE PLL should be initalized, else false
- * @param[in] i_startDMI   True if DMI PLL should be initalized, else false
- *
- * @return ReturnCode
- */
-fapi::ReturnCode proc_a_x_pci_dmi_pll_initf(const fapi::Target & i_target,
-                                            const bool i_startX,
-                                            const bool i_startA,
-                                            const bool i_startPCIE,
-                                            const bool i_startDMI);
-
-} // extern "C"
-
-#endif // _PROC_A_X_PCI_DMI_PLL_INITF_H_
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C
deleted file mode 100644
index 004ed3b44..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C
+++ /dev/null
@@ -1,383 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_setup.C,v 1.16 2014/08/27 14:53:40 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_a_x_pci_dmi_pll_setup.C
-// *! DESCRIPTION : Initialize and lock A/X/PCI/DMI PLLs
-// *!
-// *! OWNER NAME  : Ralph Koester            Email: rkoester@de.ibm.com
-// *!
-// *! The purpose of this procedure is to initialize (remove from reset/bypass)
-// *! and lock the X/A/PCIE/DMI PLLs
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_a_x_pci_dmi_pll_setup.H>
-#include <proc_a_x_pci_dmi_pll_utils.H>
-
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-const uint64_t GENERIC_PCB_CONFIG_0x000F001E = 0x000F001EULL;
-
-
-//------------------------------------------------------------------------------
-// Function definition
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Clear and unmask chiplet PLL lock indication
-//
-// parameters: i_target                 => chip target
-//             i_chiplet_base_scom_addr => aligned base address of chiplet SCOM
-//                                         address space
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_target,
-                                                        const uint32_t i_chiplet_base_scom_addr)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // data buffer to hold register values
-    ecmdDataBufferBase data(64);
-
-    do
-    {
-        rc = fapiGetScom(i_target,
-                         i_chiplet_base_scom_addr | GENERIC_PCB_ERR_0x000F001F,
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading PCB Slave PLL Lock Indication");
-            break;
-        }
-        
-        rc_ecmd |= data.setBit(25);  // set bit to clear previous lock errors 
-        rc_ecmd |= data.setBit(26);  // set bit to clear previous lock errors 
-        rc_ecmd |= data.setBit(27);  // set bit to clear previous lock errors
-        rc_ecmd |= data.setBit(28);  // set bit to clear previous lock errors
-        
-        if (rc_ecmd)
-        {
-        	FAPI_ERR("Error (0x%x) setting up PLL Lock Indication ecmdDataBufferBase", rc_ecmd);
-        	rc.setEcmdError(rc_ecmd);
-        	break;		
-        }
-        
-        FAPI_INF("Clearing PCB Slave Lock Indication Bit 25,26,27,28");
-        rc = fapiPutScom(i_target,
-                         i_chiplet_base_scom_addr | GENERIC_PCB_ERR_0x000F001F,
-                         data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error writing PCB Slave PLL Lock Indication");
-            break;
-        }
-        
-        rc = fapiGetScom(i_target,
-                         i_chiplet_base_scom_addr | GENERIC_PCB_CONFIG_0x000F001E,
-                         data);
-        if (!rc.ok())
-        {
-           FAPI_ERR("Error reading PCB Slave PLL Lock Mask");
-           break;
-        }
-        
-        rc_ecmd |= data.clearBit(12);  // set bit to clear PLL Lock Mask 
-        
-        if (rc_ecmd)
-        {
-        	FAPI_ERR("Error (0x%x) setting up PLL Lock Mask ecmdDataBufferBase", rc_ecmd);
-        	rc.setEcmdError(rc_ecmd);
-        	break;		
-        }
-        
-        FAPI_INF("Clearing PCB Slave Lock Mask Bit 12");
-        rc = fapiPutScom(i_target, 
-                         i_chiplet_base_scom_addr | GENERIC_PCB_CONFIG_0x000F001E,
-                         data);
-        if (!rc.ok())
-        {
-           FAPI_ERR("Error writing PCB Slave Lock Mask");
-           break;
-        }
-    } while(0);
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Initialize and lock A/X/PCI/DMI PLLs
-//
-// parameters: i_target       =>   chip target
-//             i_startX       =>   True to start X BUS PLL, else false
-//             i_startA       =>   True to start A BUS PLL, else false
-//             i_startPCIE    =>   True to start PCIE PLL, else false
-//             i_startDMI     =>   True to start DMI PLL, else false
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-    fapi::ReturnCode proc_a_x_pci_dmi_pll_setup(const fapi::Target & i_target,
-                                     const bool i_startX,
-                                     const bool i_startA,
-                                     const bool i_startPCIE,
-                                     const bool i_startDMI)
-    {
-        // data buffer to hold register values
-        ecmdDataBufferBase gp_data(64);
-		ecmdDataBufferBase scom_data(64);
-	
-
-        // return codes
-        fapi::ReturnCode rc;
-		
-        // locals
-        uint8_t pcie_enable_attr;
-        uint8_t abus_enable_attr;
-
-        // mark function entry
-        FAPI_INF("Entry1, start_XBUS=%s\n, Entry2, start_ABUS=%s\n, Entry3, start_PCIE=%s\n, Entry4, start_DMI=%s \n" ,
-                 i_startX? "true":"false",
-                 i_startA? "true":"false",
-                 i_startPCIE? "true":"false",
-                 i_startDMI? "true":"false");
-
-        do
-        {
-            //------------//
-            // X Bus PLL  //
-            //------------//
-            if (!i_startX)
-            {
-                FAPI_DBG("X BUS PLL not selected for setup in this routine.");
-            }
-            else
-            {
-                FAPI_INF("This routine does not do X-BUS PLL setup at this time!.");
-                FAPI_INF("It is assumed that the X-BUS PLL is already set up in synchronous mode for use with the NEST logic.");
-
-                rc = proc_a_x_pci_dmi_pll_setup_unmask_lock(
-                    i_target,
-                    TP_CHIPLET_0x01000000);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock");
-                    break;
-                }
-            }
-            // end X-bus PLL setup
-
-
-
-            //------------//
-            // A Bus PLL  //
-            //------------//
-
-            // query ABUS partial good attribute
-            rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
-                               &i_target,
-                               abus_enable_attr);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error querying ATTR_PROC_A_ENABLE");
-                break;
-            }
-
-            if (!i_startA)
-            {
-                FAPI_DBG("A BUS PLL not selected for setup in this routine.");
-            }
-            else if (abus_enable_attr != fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE)
-            {
-                FAPI_DBG("A BUS PLL setup skipped (partial good).");
-            }
-            else
-            {
-                FAPI_DBG("Starting PLL setup for A BUS PLL ...");
-                rc = proc_a_x_pci_dmi_pll_release_pll(
-                        i_target,
-                        A_BUS_CHIPLET_0x08000000,
-                        true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll");
-                    break;
-                }
-
-                rc = proc_a_x_pci_dmi_pll_setup_unmask_lock(
-                    i_target,
-                    A_BUS_CHIPLET_0x08000000);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock");
-                    break;
-                }
-
-                FAPI_INF("Done setting up A-Bus PLL. ");
-            }  // end A PLL
-
-
-            //----------//
-            // DMI PLL  //
-            //----------//
-            if (!i_startDMI)
-            {
-                FAPI_DBG("DMI PLL not selected for setup in this routine.");
-            }
-            else
-            {
-                FAPI_DBG("Starting PLL setup for DMI PLL ...");
-                rc = proc_a_x_pci_dmi_pll_release_pll(
-                        i_target,
-                        NEST_CHIPLET_0x02000000,
-                        true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll");
-                    break;
-                }
-                rc = proc_a_x_pci_dmi_pll_setup_unmask_lock(
-                    i_target,
-                    NEST_CHIPLET_0x02000000);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_setup_unmask_lock");
-                    break;
-                }
-
-                FAPI_INF("Done setting up DMI PLL. ");
-            }  // end DMI PLL
-
-
-            //-----------//
-            // PCIE PLL  //
-            //-----------//
-
-            // query PCIE partial good attribute
-            rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
-                               &i_target,
-                               pcie_enable_attr);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error querying ATTR_PROC_PCIE_ENABLE");
-                break;
-            }
-
-            if (!i_startPCIE)
-            {
-                FAPI_DBG("PCIE PLL not selected for setup in this routine.");
-            }
-            else if (pcie_enable_attr != fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
-            {
-                FAPI_DBG("PCIE PLL setup skipped (partial good).");
-            }
-            else
-            {
-                FAPI_DBG("Starting PLL setup for PCIE PLL ...");
-                rc = proc_a_x_pci_dmi_pll_release_pll(
-                        i_target,
-                        PCIE_CHIPLET_0x09000000,
-                        true);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_a_x_pci_dmi_pll_release_pll");
-                    break;
-                }
-
-                FAPI_INF("Done setting up PCIE PLL. ");
-
-            }  // end PCIE PLL
-
-        } while (0); // end do
-
-        // mark function exit
-        FAPI_INF("Exit");
-        return rc;
-    }  // end FAPI procedure proc_a_x_pci_dmi_pll_setup
-
-} // extern "C"
-
-/*
-*************** Do not edit this area ***************
-This section is automatically updated by CVS when you check in this file.
-Be sure to create CVS comments when you commit so that they can be included here.
-$Log: proc_a_x_pci_dmi_pll_setup.C,v $
-Revision 1.16  2014/08/27 14:53:40  jmcgill
-shift PCI PLL unlock reporting from istep 7 -> 14 (SW273877)
-
-Revision 1.15  2014/04/02 14:02:33  jmcgill
-respect function input parameters/partial good in unlock error clear/unmask logic (SW252901)
-
-Revision 1.14  2014/03/28 15:25:39  bgeukes
-updates for SW252901 after RAS review
-
-Revision 1.13  2014/03/27 17:58:08  bgeukes
-fix for the scominit updates
-
-Revision 1.12  2014/01/07 14:43:34  mfred
-Checking in updates from Andrea Ma:  Include statements fixed and one fapi dbg statement changed.
-
-Revision 1.11  2013/04/17 22:38:42  jmcgill
-implement A/DMI PLL workaround for SW194943, reorganize code to use common subroutines for PLL scan/setup
-
-Revision 1.10  2013/01/25 19:30:22  mfred
-Release PLLs from bypass before checking for PLL lock.  Also, check for two lock bits on DMI PLL to support Venice.
-
-Revision 1.9  2013/01/20 19:22:44  jmcgill
-update for A chiplet partial good support
-
-Revision 1.8  2013/01/10 14:40:13  jmcgill
-add partial good support
-
-Revision 1.7  2012/08/14 18:32:45  mfred
-Changed input parms from bool & to const bool.
-
-Revision 1.6  2012/08/14 14:18:06  mfred
-Separating proc_a_x_pci_dmi_pll_setup into two hwp.  And update code to use real scanning instead of sim cheats.
-
-
-*/
-
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H
deleted file mode 100644
index ce3df4d2e..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H
+++ /dev/null
@@ -1,94 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_setup.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_setup.H,v 1.8 2014/08/27 14:53:48 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_setup.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_a_x_pci_dmi_pll_setup.H
-// *! DESCRIPTION : Initialize and lock A/X/PCI/DMI PLLs
-// *!
-// *! OWNER NAME  : Ralph Koester            Email: rkoester@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_A_X_PCI_DMI_PLL_SETUP_H_
-#define _PROC_A_X_PCI_DMI_PLL_SETUP_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_a_x_pci_dmi_pll_setup_FP_t)(const fapi::Target &,
-                           const bool, const bool, const bool, const bool);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-/*
- * @brief Clear and unmask chiplet PLL lock indication
- * @param[in] i_target                 Reference to target
- * @param[in] i_chiplet_base_scom_addr Aligned base address of chiplet SCOM
- *                                     address space
- * @return ReturnCode
- */
-  fapi::ReturnCode proc_a_x_pci_dmi_pll_setup_unmask_lock(const fapi::Target & i_target,
-                                                          const uint32_t i_chiplet_base_scom_addr);
-
-/**
- * @brief Initialize and lock A/X/PCI/DMI PLLs
- *
- * @param[in] i_target     Reference to target
- * @param[in] i_startX     True if x_bus PLL should be started, else false
- * @param[in] i_startA     True if A PLL should be started, else false
- * @param[in] i_startPCIE  True if PCIE PLL should be started, else false
- * @param[in] i_startDMI   True if DMI PLL should be started, else false
- *
- * @return ReturnCode
- */
-  fapi::ReturnCode proc_a_x_pci_dmi_pll_setup(const fapi::Target & i_target,
-                                   const bool i_startX,
-                                   const bool i_startA,
-                                   const bool i_startPCIE,
-                                   const bool i_startDMI);
-
-} // extern "C"
-
-#endif // _PROC_A_X_PCI_DMI_PLL_SETUP_H_
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
deleted file mode 100644
index de733a395..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C
+++ /dev/null
@@ -1,1432 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_utils.C,v 1.9 2015/08/14 16:31:17 thi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_a_x_pci_dmi_pll_utils.C
-// *! DESCRIPTION : PLL configuration utility functions
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_a_x_pci_dmi_pll_utils.H>
-#include <p8_istep_num.H>
-#include <proc_sbe_scan_service.H>
-#include <proc_use_sbe_scan_service.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// SBE polling constants
-const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_SBE_MAX_POLLS = 100;
-const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_HW = 2000000;
-const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_SIM = 0;
-
-// SBE Control Register field/bit definitions
-const uint32_t SBE_CONTROL_REG_CTL_NO_LB_BIT = 0;
-
-// SBE Mailbox0 Register scan request format constants
-const uint32_t MBOX0_REQUEST_VALID_BIT = 0;
-const uint32_t MBOX0_RING_SELECT_START_BIT = 6;
-const uint32_t MBOX0_RING_SELECT_END_BIT = 7;
-const uint32_t MBOX0_RING_OP_START_BIT = 9;
-const uint32_t MBOX0_RING_OP_END_BIT = 11;
-const uint32_t MBOX0_RING_BUS_ID_START_BIT = 13;
-const uint32_t MBOX0_RING_BUS_ID_END_BIT = 15;
-
-// SBE MBOX1 Scratch Register scan reply format constants
-const uint32_t MBOX1_SCAN_REPLY_SUCCESS_BIT = 0;
-
-// VCO PLL workaround ring offsets
-const uint32_t PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET = 580;
-const uint32_t PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET = 581;
-
-const uint32_t AB_BNDY_PLL_RING_CCALLOAD_OFFSET = 278;
-const uint32_t AB_BNDY_PLL_RING_CCALFMIN_OFFSET = 279;
-
-// PLL lock polling constants
-const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS = 50;
-const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW = 2000000;
-const uint32_t PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM = 1;
-
-// Pervasive LFIR Register field/bit definitions
-const uint8_t PERV_LFIR_SCAN_COLLISION_BIT = 3;
-
-// OPCG/Clock Region Register values
-const uint64_t OPCG_REG0_FOR_SETPULSE  = 0x818C000000000000ull;
-const uint64_t OPCG_REG2_FOR_SETPULSE  = 0x0000000000002000ull;
-const uint64_t OPCG_REG3_FOR_SETPULSE  = 0x6000000000000000ull;
-const uint64_t CLK_REGION_FOR_SETPULSE = 0x0010040000000000ull;
-
-// GP3 Register field/bit definitions
-const uint8_t GP3_PLL_TEST_ENABLE_BIT = 3;
-const uint8_t GP3_PLL_RESET_BIT = 4;
-const uint8_t GP3_PLL_BYPASS_BIT = 5;
-
-// PLL Lock Register field/bit definitions
-const uint8_t PLL_LOCK_REG_LOCK_START_BIT = 0;
-const uint8_t PLL_LOCK_REG_LOCK_END_BIT = 3;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-using namespace fapi;
-
-//------------------------------------------------------------------------------
-// function:
-//      Calculate state to apply to Centaur tp_bndy_pll ring
-//
-// parameters: i_target      => chip target
-//             i_pll_ring_op => modification to be made to PLL content
-//             o_ring_data   => data buffer containing ring state to apply
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_calc_memb_tp_bndy_pll(
-    const fapi::Target & i_target,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    ecmdDataBufferBase & o_ring_data)
-{
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // determine ring length
-        fapi::ATTR_MEMB_TP_BNDY_PLL_LENGTH_Type ring_length;
-        rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH, &i_target, ring_length);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_MEMB_TP_BNDY_PLL_LENGTH.");
-            break;
-        }
-        rc_ecmd |= o_ring_data.setBitLength(ring_length);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // determine starting ring state
-        if (i_pll_ring_op == RING_OP_BASE)
-        {
-            // start from attribute data
-            fapi::ATTR_MEMB_TP_BNDY_PLL_DATA_Type ring_data_attr = {0};
-            rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_DATA, &i_target, ring_data_attr);
-            if (rc)
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_MEMB_TP_BNDY_PLL_DATA.");
-                break;
-            }
-            rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else
-        {
-            // start from data currently in ring
-            rc = fapiGetRing(i_target, RING_ADDRESS_MEMB_TP_BNDY_PLL, o_ring_data, fapi::RING_MODE_SET_PULSE);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from fapiGetRing (ring ID: 0x08%x)", RING_ADDRESS_MEMB_TP_BNDY_PLL);
-                break;
-            }
-        }
-
-        // modify ring data
-        if (i_pll_ring_op == RING_OP_MOD_REFCLK_SEL)
-        {
-            fapi::ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset;
-            rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_MEMB_DMI_CUPLL_REFCLKSEL_OFFSET");
-                break;
-            }
-
-            if (o_ring_data.isBitClear(refclksel_offset))
-            {
-                rc_ecmd |= o_ring_data.setBit(refclksel_offset);
-            }
-            else
-            {
-                rc_ecmd |= o_ring_data.clearBit(refclksel_offset);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading refclock select attribute data into buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_PFD360)
-        {
-            fapi::ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET_Type pfd360_offset;
-            rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_MEMB_DMI_CUPLL_PFD360_OFFSET");
-                break;
-            }
-
-            if (o_ring_data.isBitClear(pfd360_offset))
-            {
-                rc_ecmd |= o_ring_data.setBit(pfd360_offset);
-            }
-            else
-            {
-                rc_ecmd |= o_ring_data.clearBit(pfd360_offset);
-            }
-
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading pfd360 attribute data into buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Calculate state to apply to processor pci_bndy_pll ring
-//
-// parameters: i_target     => chip target
-//             o_ring_data  => data buffer containing ring state to apply
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_calc_proc_pci_bndy_pll(
-    const fapi::Target & i_target,
-    ecmdDataBufferBase & o_ring_data)
-{
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // determine ring length
-        fapi::ATTR_PROC_PCI_BNDY_PLL_LENGTH_Type ring_length;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_LENGTH, &i_target, ring_length);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_LENGTH.");
-            break;
-        }
-        rc_ecmd |= o_ring_data.setBitLength(ring_length);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // determine starting ring state
-        fapi::ATTR_PROC_PCI_BNDY_PLL_DATA_Type ring_data_attr = {0};
-        rc = FAPI_ATTR_GET(ATTR_PROC_PCI_BNDY_PLL_DATA, &i_target, ring_data_attr);
-        if (rc)
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_PROC_PCI_BNDY_PLL_DATA.");
-            break;
-        }
-        rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Calculate state to apply to processor pb_bndy_dmipll ring
-//
-// parameters: i_target      => chip target
-//             i_pll_ring_op => modification to be made to base PLL content
-//             i_pll_bus_id  => bus instance to target for modification
-//             o_ring_data   => data buffer containing ring state to apply
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_calc_proc_pb_bndy_dmipll(
-    const fapi::Target & i_target,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    const p8_pll_utils_bus_id i_pll_bus_id,
-    ecmdDataBufferBase & o_ring_data)
-{
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // determine ring length
-        fapi::ATTR_PROC_PB_BNDY_DMIPLL_LENGTH_Type ring_length;
-        rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_LENGTH, &i_target, ring_length);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_LENGTH.");
-            break;
-        }
-        rc_ecmd |= o_ring_data.setBitLength(ring_length);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // determine starting ring state
-        if (i_pll_ring_op == RING_OP_BASE)
-        {
-            // start from attribute data
-            fapi::ATTR_PROC_PB_BNDY_DMIPLL_DATA_Type ring_data_attr = {0};
-            rc = FAPI_ATTR_GET(ATTR_PROC_PB_BNDY_DMIPLL_DATA, &i_target, ring_data_attr);
-            if (rc)
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_PROC_PB_BNDY_DMIPLL_DATA.");
-                break;
-            }
-            rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else
-        {
-            // start from data currently in ring
-            rc = fapiGetRing(i_target, RING_ADDRESS_PROC_PB_BNDY_DMIPLL, o_ring_data, fapi::RING_MODE_SET_PULSE);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from fapiGetRing (ring ID: 0x08%x)", RING_ADDRESS_PROC_PB_BNDY_DMIPLL);
-                break;
-            }
-        }
-
-        // modify ring data
-        if (i_pll_ring_op == RING_OP_MOD_VCO_S1)
-        {
-            rc_ecmd |= o_ring_data.setBit(PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET);
-            rc_ecmd |= o_ring_data.setBit(PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan1)", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_VCO_S2)
-        {
-            rc_ecmd |= o_ring_data.setBit(PB_BNDY_DMIPLL_RING_CCALLOAD_OFFSET);
-            rc_ecmd |= o_ring_data.clearBit(PB_BNDY_DMIPLL_RING_CCALFMIN_OFFSET);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan2)", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_REFCLK_SEL)
-        {
-            fapi::ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset = {0};
-            rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_PROC_DMI_CUPLL_REFCLKSEL_OFFSET");
-                break;
-            }
-
-            if (o_ring_data.isBitSet(refclksel_offset[i_pll_bus_id]))
-            {
-                rc_ecmd |= o_ring_data.clearBit(refclksel_offset[i_pll_bus_id]);
-            }
-            else
-            {
-                rc_ecmd |= o_ring_data.setBit(refclksel_offset[i_pll_bus_id]);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading refclock select attribute data into buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_PFD360)
-        {
-            fapi::ATTR_PROC_DMI_CUPLL_PFD360_OFFSET_Type pfd360_offset;
-            rc = FAPI_ATTR_GET(ATTR_PROC_DMI_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_PROC_DMI_CUPLL_PFD360_OFFSET");
-                break;
-            }
-
-            if (o_ring_data.isBitSet(pfd360_offset[i_pll_bus_id]))
-            {
-                rc_ecmd |= o_ring_data.clearBit(pfd360_offset[i_pll_bus_id]);
-            }
-            else
-            {
-                rc_ecmd |= o_ring_data.setBit(pfd360_offset[i_pll_bus_id]);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading pfd360 attribute data into buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Calculate state to apply to processor ab_bndy_pll ring
-//
-// parameters: i_target      => chip target
-//             i_pll_ring_op => modification to be made to base PLL content
-//             i_pll_bus_id  => bus instance to target for modification
-//             o_ring_data   => data buffer containing ring state to apply
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_calc_proc_ab_bndy_pll(
-    const fapi::Target & i_target,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    const p8_pll_utils_bus_id i_pll_bus_id,
-    ecmdDataBufferBase & o_ring_data)
-{
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // determine ring length
-        fapi::ATTR_PROC_AB_BNDY_PLL_LENGTH_Type ring_length;
-        rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_LENGTH, &i_target, ring_length);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_LENGTH.");
-            break;
-        }
-        rc_ecmd |= o_ring_data.setBitLength(ring_length);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting ecmd data buffer length. Buffer must be set to length of scan chain.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // determine starting ring state
-        if (i_pll_ring_op == RING_OP_BASE)
-        {
-            // start from attribute data
-            fapi::ATTR_PROC_AB_BNDY_PLL_DATA_Type ring_data_attr = {0};
-            rc = FAPI_ATTR_GET(ATTR_PROC_AB_BNDY_PLL_DATA, &i_target, ring_data_attr);
-            if (rc)
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_PROC_AB_BNDY_PLL_DATA.");
-                break;
-            }
-            rc_ecmd |= o_ring_data.insert(ring_data_attr, 0, ring_length, 0);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading scan chain attribute data into buffer.",  rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else
-        {
-            // start from data currently in ring
-            rc = fapiGetRing(i_target, RING_ADDRESS_PROC_AB_BNDY_PLL, o_ring_data, fapi::RING_MODE_SET_PULSE);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from fapiGetRing (ring ID: 0x08%x)", RING_ADDRESS_PROC_AB_BNDY_PLL);
-                break;
-            }
-        }
-
-        // modify ring data
-        if (i_pll_ring_op == RING_OP_MOD_VCO_S1)
-        {
-            rc_ecmd |= o_ring_data.setBit(AB_BNDY_PLL_RING_CCALLOAD_OFFSET);
-            rc_ecmd |= o_ring_data.setBit(AB_BNDY_PLL_RING_CCALFMIN_OFFSET);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan1)", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_VCO_S2)
-        {
-            rc_ecmd |= o_ring_data.setBit(AB_BNDY_PLL_RING_CCALLOAD_OFFSET);
-            rc_ecmd |= o_ring_data.clearBit(AB_BNDY_PLL_RING_CCALFMIN_OFFSET);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up data buffer to enable lctank PLL vco workaround (scan2)", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_REFCLK_SEL)
-        {
-            fapi::ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET_Type refclksel_offset = {0};
-            rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET, &i_target, refclksel_offset);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_PROC_ABUS_CUPLL_REFCLKSEL_OFFSET");
-                break;
-            }
-
-            if (o_ring_data.isBitSet(refclksel_offset[i_pll_bus_id]))
-            {
-                rc_ecmd |= o_ring_data.clearBit(refclksel_offset[i_pll_bus_id]);
-            }
-            else
-            {
-                rc_ecmd |= o_ring_data.setBit(refclksel_offset[i_pll_bus_id]);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading refclock select attribute data into buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else if (i_pll_ring_op == RING_OP_MOD_PFD360)
-        {
-            fapi::ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET_Type pfd360_offset;
-            rc = FAPI_ATTR_GET(ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET, &i_target, pfd360_offset);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Failed to get attribute: ATTR_PROC_ABUS_CUPLL_PFD360_OFFSET");
-                break;
-            }
-
-            if (o_ring_data.isBitSet(pfd360_offset[i_pll_bus_id]))
-            {
-                rc_ecmd |= o_ring_data.clearBit(pfd360_offset[i_pll_bus_id]);
-            }
-            else
-            {
-                rc_ecmd |= o_ring_data.setBit(pfd360_offset[i_pll_bus_id]);
-            }
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x loading pfd360 attribute data into buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Poll for SBE to reach designated state (interlocked with scan requests)
-//
-// parameters: i_target     => chip target
-//             i_poll_limit => number of polls permitted before timeout
-//
-// returns: FAPI_RC_SUCCESS if desired state was reached, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_poll_sbe(
-    const fapi::Target & i_target,
-    const uint32_t i_num_polls)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    uint32_t poll_num = 0;
-    bool poll_timeout = false;
-    bool sbe_running = true;
-    bool sbe_ready = false;
-
-    ecmdDataBufferBase sbe_control_data(64);
-    ecmdDataBufferBase sbe_vital_data(64);
-    uint32_t istep_num;
-    uint8_t substep_num;
-    ecmdDataBufferBase mbox_data(64);
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        do
-        {
-            // delay between poll attempts
-            if (poll_num)
-            {
-                FAPI_DBG("Pausing prior to next poll...");
-                rc = fapiDelay(PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_HW,
-                               PROC_A_X_PCI_DMI_PLL_UTILS_SBE_POLL_DELAY_SIM);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from fapiDelay");
-                    break;
-                }
-            }
-
-            // increment poll count, timeout if threshold exceeded
-            poll_num++;
-            if (poll_num > i_num_polls)
-            {
-                poll_timeout = true;
-                break;
-            }
-
-            // determine SBE run state
-            FAPI_DBG("Reading SBE state (poll %d / %d)", poll_num, i_num_polls);
-            rc = fapiGetScom(i_target, PORE_SBE_CONTROL_0x000E0001, sbe_control_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error reading SBE Control Register");
-                break;
-            }
-            sbe_running = sbe_control_data.isBitClear(SBE_CONTROL_REG_CTL_NO_LB_BIT);
-            FAPI_DBG("Run state: %s", ((sbe_running)?("run"):("halted")));
-
-            // get SBE istep/substep information
-            rc = fapiGetScom(i_target, MBOX_SBEVITAL_0x0005001C, sbe_vital_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error reading SBE Vital Register");
-                break;
-            }
-
-            rc_ecmd |= sbe_vital_data.extractToRight(&istep_num,
-                                                     ISTEP_NUM_BIT_POSITION,
-                                                     ISTEP_NUM_BIT_LENGTH);
-            rc_ecmd |= sbe_vital_data.extractToRight(&substep_num,
-                                                     SUBSTEP_NUM_BIT_POSITION,
-                                                     SUBSTEP_NUM_BIT_LENGTH);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            // get HB->SBE request mailbox, check that it is clear
-            rc = fapiGetScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Scom error reading SBE MBOX0 Register");
-                break;
-            }
-
-            sbe_ready = (istep_num == PROC_SBE_SCAN_SERVICE_ISTEP_NUM) &&
-                        (substep_num == SUBSTEP_SBE_READY) &&
-                        (mbox_data.getDoubleWord(0) == 0);
-
-            FAPI_DBG("Istep: 0x%03X, Substep: %X, MBOX: %016llX", istep_num, substep_num, mbox_data.getDoubleWord(0));
-
-        } while (!poll_timeout &&
-                 sbe_running &&
-                 !sbe_ready);
-
-        if (!rc.ok())
-        {
-            break;
-        }
-        if (!sbe_running)
-        {
-            FAPI_ERR("SBE is NOT running!");
-            const fapi::Target & TARGET = i_target;
-            ecmdDataBufferBase & SBE_CONTROL = sbe_control_data;
-            FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_SBE_STOPPED);
-            break;
-        }
-        if (poll_timeout || !sbe_ready)
-        {
-            FAPI_ERR("Poll limit reached waiting for SBE to attain expected state");
-            FAPI_ERR("Expected istep 0x%03llX, substep 0x%X but found istep 0x%03X, substep 0x%X",
-                     PROC_SBE_SCAN_SERVICE_ISTEP_NUM, SUBSTEP_SBE_READY,
-                     istep_num, substep_num);
-            const fapi::Target & TARGET = i_target;
-            const uint32_t & POLL_COUNT = i_num_polls;
-            const ecmdDataBufferBase & SBE_VITAL = sbe_vital_data;
-            FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_SBE_TIMEOUT_ERROR);
-            break;
-        }
-
-        FAPI_DBG("SBE reached expected state");
-
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Scan PLL boundary ring with setpulse (scan executed by SBE)
-//
-// parameters: i_target              => chip target
-//             i_pll_ring_addr       => PLL ring address
-//             i_pll_ring_op         => modification to be made to base PLL content
-//             i_pll_bus_id          => bus instance to target for modification
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_scan_bndy_sbe(
-    const fapi::Target & i_target,
-    const p8_pll_utils_ring_address i_pll_ring_addr,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    const p8_pll_utils_bus_id i_pll_bus_id)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // check request content
-        p8_pll_utils_ring_id pll_ring_id;
-        if (i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL)
-        {
-            pll_ring_id = RING_ID_ABUS;
-        }
-        else if (i_pll_ring_addr == RING_ADDRESS_PROC_PCI_BNDY_PLL)
-        {
-            pll_ring_id = RING_ID_PCI;
-        }
-        else if (i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL)
-        {
-            pll_ring_id = RING_ID_DMI;
-        }
-        else
-        {
-            FAPI_ERR("Invalid/unsupported SBE ring operation requested");
-            const fapi::Target & TARGET = i_target;
-            const p8_pll_utils_ring_address & PLL_RING_ADDR = i_pll_ring_addr;
-            const p8_pll_utils_ring_op & PLL_RING_OP = i_pll_ring_op;
-            const p8_pll_utils_bus_id & PLL_BUS_ID = i_pll_bus_id;
-            const bool & INVALID_RING_ADDRESS = true;
-            const bool & INVALID_RING_OP = false;
-            const bool & INVALID_BUS_ID = false;
-            FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_INVALID_OPERATION);
-            break;
-        }
-
-        // verify that SBE is ready to service scan operation
-        // (it should be waiting for our request)
-        FAPI_DBG("Checking SBE is ready to receive scan request");
-        rc = p8_pll_utils_poll_sbe(i_target, 1);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from p8_pll_utils_poll_sbe");
-            break;
-        }
-
-        // construct scan request format
-        ecmdDataBufferBase mbox_data(64);
-        rc_ecmd |= mbox_data.setBit(MBOX0_REQUEST_VALID_BIT);
-        rc_ecmd |= mbox_data.insertFromRight(static_cast<uint32_t>(pll_ring_id),
-                                             MBOX0_RING_SELECT_START_BIT,
-                                             (MBOX0_RING_SELECT_END_BIT-
-                                              MBOX0_RING_SELECT_START_BIT+1));
-        rc_ecmd |= mbox_data.insertFromRight(static_cast<uint32_t>(i_pll_ring_op),
-                                             MBOX0_RING_OP_START_BIT,
-                                             (MBOX0_RING_OP_END_BIT-
-                                              MBOX0_RING_OP_START_BIT+1));
-        rc_ecmd |= mbox_data.insertFromRight(static_cast<uint32_t>(i_pll_bus_id),
-                                             MBOX0_RING_BUS_ID_START_BIT,
-                                             (MBOX0_RING_BUS_ID_END_BIT-
-                                              MBOX0_RING_BUS_ID_START_BIT+1));
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up SBE MBOX0 data buffer.", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // submit request to SBE
-        FAPI_DBG("Submitting scan request to SBE");
-        rc = fapiPutScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error writing SBE MBOX0 Register");
-            break;
-        }
-
-        // poll until SBE drops response SBE indicates scan is finished (back to 'ready' state)
-        // or until maximum poll count is reached
-        FAPI_DBG("Polling for SBE completion...");
-        rc = p8_pll_utils_poll_sbe(i_target,
-                                   PROC_A_X_PCI_DMI_PLL_UTILS_SBE_MAX_POLLS);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from p8_pll_utils_poll_sbe");
-            break;
-        }
-
-        // check result of scan operation
-        FAPI_DBG("SBE reached ready state, checking result of scan operation");
-        rc = fapiGetScom(i_target, MBOX_SCRATCH_REG1_0x00050039, mbox_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading SBE MBOX1 Register");
-            break;
-        }
-
-        if (mbox_data.isBitClear(MBOX1_SCAN_REPLY_SUCCESS_BIT))
-        {
-            FAPI_ERR("SBE indicated scan operation failure!");
-            const fapi::Target & TARGET = i_target;
-            const p8_pll_utils_ring_address & PLL_RING_ADDR = i_pll_ring_addr;
-            const p8_pll_utils_ring_op & PLL_RING_OP = i_pll_ring_op;
-            const p8_pll_utils_bus_id & PLL_BUS_ID = i_pll_bus_id;
-            const ecmdDataBufferBase & MBOX1_DATA = mbox_data;
-            FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_SBE_SCAN_ERROR);
-            break;
-        }
-
-        FAPI_DBG("SBE reply indicates scan was successful!");
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Scan PLL boundary ring with setpulse (scan executed by HB/FSP platform)
-//
-// parameters: i_target              => chip target
-//             i_pll_ring_addr       => PLL ring address
-//             i_pll_ring_op         => modification to be made to base PLL content
-//             i_pll_bus_id          => bus instance to target for modification
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode p8_pll_utils_scan_bndy_non_sbe(
-    const fapi::Target & i_target,
-    const p8_pll_utils_ring_address i_pll_ring_addr,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    const p8_pll_utils_bus_id i_pll_bus_id)
-{
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // form base chiplet ID / ring data to scan
-        uint32_t chiplet_base_scom_addr;
-        ecmdDataBufferBase ring_data;
-        if (i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL)
-        {
-            chiplet_base_scom_addr = TP_CHIPLET_0x01000000;
-            rc = p8_pll_utils_calc_memb_tp_bndy_pll(i_target,
-                                                    i_pll_ring_op,
-                                                    ring_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from p8_pll_utils_calc_memb_tp_bndy_pll");
-                break;
-            }
-        }
-        else if (i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL)
-        {
-            chiplet_base_scom_addr = NEST_CHIPLET_0x02000000;
-            rc = p8_pll_utils_calc_proc_pb_bndy_dmipll(i_target,
-                                                       i_pll_ring_op,
-                                                       i_pll_bus_id,
-                                                       ring_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from p8_pll_utils_calc_proc_pb_bndy_dmipll");
-                break;
-            }
-        }
-        else if (i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL)
-        {
-            chiplet_base_scom_addr = A_BUS_CHIPLET_0x08000000;
-            rc = p8_pll_utils_calc_proc_ab_bndy_pll(i_target,
-                                                    i_pll_ring_op,
-                                                    i_pll_bus_id,
-                                                    ring_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from p8_pll_utils_calc_proc_ab_bndy_pll");
-                break;
-            }
-        }
-        else
-        {
-            chiplet_base_scom_addr = PCIE_CHIPLET_0x09000000;
-            rc = p8_pll_utils_calc_proc_pci_bndy_pll(i_target,
-                                                     ring_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from p8_pll_utils_calc_proc_pci_bndy_pll");
-                break;
-            }
-        }
-
-        // configure OPCG to generate setpulse
-        ecmdDataBufferBase scom_data(64);
-        FAPI_DBG("Writing OPCG Register 0 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG0_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 0.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL0_0x00030002, scom_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error writing OPCG Register0 to generate setpulse.");
-            break;
-        }
-
-        FAPI_DBG("Writing OPCG Register 2 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG2_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 2.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL2_0x00030004, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing OPCG Register2 to generate setpulse.");
-            break;
-        }
-
-        FAPI_DBG("Writing OPCG Register 3 to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, OPCG_REG3_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write OPCG Register 3.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL3_0x00030005, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing OPCG Register3 to generate setpulse.");
-            break;
-        }
-
-        FAPI_DBG("Writing OPCG Clock Region Register to generate setpulse ...");
-        rc_ecmd |= scom_data.setDoubleWord(0, CLK_REGION_FOR_SETPULSE);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to write Clock Region Register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_CLK_REGION_0x00030006, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing Clock Region Register to generate setpulse.");
-            break;
-        }
-
-        // scan new ring data into PLL boundary scan ring
-        rc = fapiPutRing(i_target, i_pll_ring_addr, ring_data, fapi::RING_MODE_SET_PULSE);
-        if (rc)
-        {
-            FAPI_ERR("fapiPutRing failed with rc = 0x%x", (uint32_t) rc);
-            break;
-        }
-        FAPI_DBG("Loading of the config bits for PLL is done.");
-
-
-        // set the OPCG back to a good state
-        FAPI_DBG("Writing OPCG Register 3 to clear setpulse ...");
-        rc_ecmd |= scom_data.flushTo0();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear OPCG Register 3.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_OPCG_CNTL3_0x00030005, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing OPCG Register3 to clear setpulse.");
-            break;
-        }
-
-        FAPI_DBG("Writing OPCG Clock Region Register to clear setpulse ...");
-        rc_ecmd |= scom_data.flushTo0();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Clock Region Register.",  rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_CLK_REGION_0x00030006, scom_data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing Clock Region Register to clear setpulse.");
-            break;
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Scan PLL boundary ring with setpulse
-//
-// parameters: i_target              => chip target
-//             i_pll_ring_addr       => PLL ring address
-//             i_pll_ring_op         => modification to be made to base PLL content
-//             i_pll_bus_id          => bus instance to target for modification
-//             i_mask_scan_collision => mask scan collision bit in chiplet
-//                                      pervasive LFIR
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy(
-    const fapi::Target& i_target,
-    const p8_pll_utils_ring_address i_pll_ring_addr,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    const p8_pll_utils_bus_id i_pll_bus_id,
-    const bool i_mask_scan_collision)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // check validity of arguments
-        bool invalid_ring_address = ((i_pll_ring_addr != RING_ADDRESS_MEMB_TP_BNDY_PLL) &&
-                                     (i_pll_ring_addr != RING_ADDRESS_PROC_PB_BNDY_DMIPLL) &&
-                                     (i_pll_ring_addr != RING_ADDRESS_PROC_AB_BNDY_PLL) &&
-                                     (i_pll_ring_addr != RING_ADDRESS_PROC_PCI_BNDY_PLL));
-        bool invalid_ring_op = (((i_pll_ring_op != RING_OP_BASE) &&
-                                 (i_pll_ring_op != RING_OP_MOD_VCO_S1) &&
-                                 (i_pll_ring_op != RING_OP_MOD_VCO_S2) &&
-                                 (i_pll_ring_op != RING_OP_MOD_REFCLK_SEL) &&
-                                 (i_pll_ring_op != RING_OP_MOD_PFD360)) ||
-                                ((i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL) &&
-                                 ((i_pll_ring_op == RING_OP_MOD_VCO_S1) ||
-                                  (i_pll_ring_op == RING_OP_MOD_VCO_S2))) ||
-                                ((i_pll_ring_addr == RING_ADDRESS_PROC_PCI_BNDY_PLL) &&
-                                 (i_pll_ring_op != RING_OP_BASE)));
-        bool invalid_bus_id = ((((i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL) ||
-                                 (i_pll_ring_addr == RING_ADDRESS_PROC_PCI_BNDY_PLL)) &&
-                                (i_pll_bus_id != RING_BUS_ID_0)) ||
-                               (((i_pll_ring_op == RING_OP_BASE) ||
-                                 (i_pll_ring_op == RING_OP_MOD_VCO_S1) ||
-                                 (i_pll_ring_op == RING_OP_MOD_VCO_S2)) &&
-                                (i_pll_bus_id != RING_BUS_ID_0)) ||
-                               ((i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL) &&
-                                (i_pll_bus_id != RING_BUS_ID_0) &&
-                                (i_pll_bus_id != RING_BUS_ID_1) &&
-                                (i_pll_bus_id != RING_BUS_ID_2) &&
-                                (i_pll_bus_id != RING_BUS_ID_3)) ||
-                               ((i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL) &&
-                                (i_pll_bus_id != RING_BUS_ID_0) &&
-                                (i_pll_bus_id != RING_BUS_ID_1) &&
-                                (i_pll_bus_id != RING_BUS_ID_2) &&
-                                (i_pll_bus_id != RING_BUS_ID_3) &&
-                                (i_pll_bus_id != RING_BUS_ID_4) &&
-                                (i_pll_bus_id != RING_BUS_ID_5) &&
-                                (i_pll_bus_id != RING_BUS_ID_6) &&
-                                (i_pll_bus_id != RING_BUS_ID_7)));
-
-        if (invalid_ring_address ||
-            invalid_ring_op ||
-            invalid_bus_id)
-        {
-            FAPI_ERR("Invalid/unsupported ring operation requested");
-            FAPI_ERR("  ring address: %x (invalid = %d)", i_pll_ring_addr, invalid_ring_address);
-            FAPI_ERR("  ring op: %x (invalid = %d)", i_pll_ring_op, invalid_ring_op);
-            FAPI_ERR("  bus id: %x (invalid = %d)", i_pll_bus_id, invalid_bus_id);
-
-            const fapi::Target & TARGET = i_target;
-            const p8_pll_utils_ring_address & PLL_RING_ADDR = i_pll_ring_addr;
-            const p8_pll_utils_ring_op & PLL_RING_OP = i_pll_ring_op;
-            const p8_pll_utils_bus_id & PLL_BUS_ID = i_pll_bus_id;
-            const bool & INVALID_RING_ADDRESS = invalid_ring_address;
-            const bool & INVALID_RING_OP = invalid_ring_op;
-            const bool & INVALID_BUS_ID = invalid_bus_id;
-            FAPI_SET_HWP_ERROR(rc, RC_P8_PLL_UTILS_INVALID_OPERATION);
-            break;
-        }
-
-        // optionally mask pervasive LFIR prior to scan operation
-        bool unmask_scan_collision = false;
-        uint32_t chiplet_base_scom_addr;
-        ecmdDataBufferBase scom_data(64);
-        if (i_pll_ring_addr == RING_ADDRESS_MEMB_TP_BNDY_PLL)
-        {
-            chiplet_base_scom_addr = TP_CHIPLET_0x01000000;
-        }
-        else if (i_pll_ring_addr == RING_ADDRESS_PROC_PB_BNDY_DMIPLL)
-        {
-            chiplet_base_scom_addr = NEST_CHIPLET_0x02000000;
-        }
-        else if (i_pll_ring_addr == RING_ADDRESS_PROC_AB_BNDY_PLL)
-        {
-            chiplet_base_scom_addr = A_BUS_CHIPLET_0x08000000;
-        }
-        else
-        {
-            chiplet_base_scom_addr = PCIE_CHIPLET_0x09000000;
-        }
-
-        if (i_mask_scan_collision)
-        {
-            FAPI_DBG("Reading value of Pervasive LFIR scan collision mask bit ...");
-            rc = fapiGetScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_0x0004000D, scom_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error reading Pervasive LFIR Mask OR Register.");
-                break;
-            }
-            unmask_scan_collision = scom_data.isBitClear(PERV_LFIR_SCAN_COLLISION_BIT);
-
-            FAPI_DBG("Masking Pervasive LFIR scan collision bit ...");
-            rc_ecmd |= scom_data.flushTo0();
-            rc_ecmd |= scom_data.setBit(PERV_LFIR_SCAN_COLLISION_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to set Pervasive LFIR Mask Register.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_OR_0x0004000F, scom_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing Pervasive LFIR Mask OR Register.");
-                break;
-            }
-        }
-
-        // make determination of scan path to use
-        bool use_sbe;
-        FAPI_EXEC_HWP(rc, proc_use_sbe_scan_service, i_target, use_sbe);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from proc_use_sbe_scan_service");
-            break;
-        }
-
-        // scan path determined
-        // request SCAN via SBE (SBE holds data)
-        if (use_sbe)
-        {
-            rc = p8_pll_utils_scan_bndy_sbe(i_target,
-                                            i_pll_ring_addr,
-                                            i_pll_ring_op,
-                                            i_pll_bus_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from p8_pll_utils_scan_bndy_sbe");
-                break;
-            }
-        }
-        // construct ring content to scan via attributes, invoke FAPI API
-        else
-        {
-            rc = p8_pll_utils_scan_bndy_non_sbe(i_target,
-                                                i_pll_ring_addr,
-                                                i_pll_ring_op,
-                                                i_pll_bus_id);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from p8_pll_utils_scan_bndy_non_sbe");
-                break;
-            }
-        }
-
-        // clear & Unmask Pervasive LFIR
-        if (i_mask_scan_collision)
-        {
-            FAPI_DBG("Clearing Pervasive LFIR scan collision bit ...");
-            rc_ecmd |= scom_data.flushTo1();
-            rc_ecmd |= scom_data.clearBit(PERV_LFIR_SCAN_COLLISION_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up ecmd data buffer to clear Pervasive LFIR Register.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_AND_0x0004000B, scom_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing Pervasive LFIR AND Register.");
-                break;
-            }
-
-            if (unmask_scan_collision)
-            {
-                FAPI_DBG("Unmasking Pervasive LFIR scan collision bit ...");
-                rc = fapiPutScom(i_target, chiplet_base_scom_addr | GENERIC_PERV_LFIR_MASK_AND_0x0004000E, scom_data);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error writing Pervasive LFIR Mask And Register.");
-                    break;
-                }
-            }
-        }
-
-    } while(0);
-
-    // mark function exit
-    FAPI_DBG("End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Release PLL from test mode/bypass/reset and optionally check for lock
-//
-// parameters: i_target                 => chip target
-//             i_chiplet_base_scom_addr => aligned base address of chiplet SCOM
-//                                         address space
-//             i_check_lock             => check for PLL lock?
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_scom_addr,
-    const bool i_check_lock)
-{
-    // data buffer to hold SCOM data
-    ecmdDataBufferBase data(64);
-
-    // return codes
-    uint32_t rc_ecmd = 0;
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        FAPI_DBG("Release PLL test enable");
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP3_PLL_TEST_ENABLE_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL test enable", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP3 to clear PLL test enable");
-            break;
-        }
-
-        FAPI_DBG("Release PLL reset");
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP3_PLL_RESET_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL reset", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP3 to clear PLL reset");
-            break;
-        }
-
-        FAPI_DBG("Release PLL bypass");
-        // 24july2012  mfred moved this before checking PLL lock as this is required for analog PLLs.
-        rc_ecmd |= data.flushTo1();
-        rc_ecmd |= data.clearBit(GP3_PLL_BYPASS_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("Error 0x%x setting up data buffer to clear GP3 PLL bypass", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        rc = fapiPutScom(i_target, i_chiplet_base_scom_addr | GENERIC_GP3_AND_0x000F0013, data);
-        if (rc)
-        {
-            FAPI_ERR("Error writing GP3 to clear PLL bypass");
-            break;
-        }
-
-        if (i_check_lock)
-        {
-            FAPI_DBG("Checking for PLL lock...");
-            uint32_t num = 0;
-            bool timeout = false;
-
-            // poll until PLL is locked or max count is reached
-            do
-            {
-                num++;
-                if (num > PROC_A_X_PCI_DMI_PLL_UTILS_MAX_LOCK_POLLS)
-                {
-                    timeout = 1;
-                    break;
-                }
-                rc = fapiGetScom(i_target, i_chiplet_base_scom_addr | GENERIC_PLLLOCKREG_0x000F0019, data);
-                if (rc)
-                {
-                    FAPI_ERR("Error reading PLL lock register");
-                    break;
-                }
-                rc = fapiDelay(PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_HW,
-                               PROC_A_X_PCI_DMI_PLL_UTILS_POLL_DELAY_SIM);
-                if (rc)
-                {
-                    FAPI_ERR("Error from fapiDelay");
-                    break;
-                }
-            } while (!timeout &&
-                     !data.isBitSet(PLL_LOCK_REG_LOCK_START_BIT,
-                                    (PLL_LOCK_REG_LOCK_END_BIT-
-                                     PLL_LOCK_REG_LOCK_START_BIT+1)));
-
-            if (rc)
-            {
-                break;
-            }
-            if (timeout)
-            {
-                FAPI_ERR("Timed out polling for PLL lock");
-                const uint8_t LOCK_STATUS = data.getByte(0);
-                const fapi::Target & CHIP_IN_ERROR = i_target;
-                if (i_chiplet_base_scom_addr == NEST_CHIPLET_0x02000000)
-                {
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_DMI_PLL_NO_LOCK);
-                }
-                else if (i_chiplet_base_scom_addr == A_BUS_CHIPLET_0x08000000)
-                {
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_ABUS_PLL_NO_LOCK);
-                }
-                else if (i_chiplet_base_scom_addr == PCIE_CHIPLET_0x09000000)
-                {
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_A_X_PCI_DMI_PLL_SETUP_PCIE_PLL_NO_LOCK);
-                }
-                break;
-            }
-            else
-            {
-                FAPI_DBG("PLL is locked.");
-            }
-        }
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H b/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
deleted file mode 100644
index c1a16c4de..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H
+++ /dev/null
@@ -1,136 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_a_x_pci_dmi_pll_setup/proc_a_x_pci_dmi_pll_utils.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_a_x_pci_dmi_pll_utils.H,v 1.4 2015/05/14 21:18:32 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_a_x_pci_dmi_pll_utils.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_a_x_pci_dmi_pll_utils.H
-// *! DESCRIPTION : PLL configuration utility functions
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_A_X_PCI_DMI_PLL_UTILS_H_
-#define _PROC_A_X_PCI_DMI_PLL_UTILS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-enum p8_pll_utils_ring_address
-{
-    RING_ADDRESS_MEMB_TP_BNDY_PLL = 0x01030088,
-    RING_ADDRESS_PROC_AB_BNDY_PLL = 0x08030088,
-    RING_ADDRESS_PROC_PCI_BNDY_PLL = 0x09030088,
-    RING_ADDRESS_PROC_PB_BNDY_DMIPLL = 0x02030088
-};
-
-enum p8_pll_utils_ring_id
-{
-    RING_ID_ABUS = 1,
-    RING_ID_PCI = 2,
-    RING_ID_DMI = 3
-};
-
-enum p8_pll_utils_ring_op
-{
-    RING_OP_BASE = 0,
-    RING_OP_MOD_VCO_S1 = 1,
-    RING_OP_MOD_VCO_S2 = 2,
-    RING_OP_MOD_REFCLK_SEL = 3,
-    RING_OP_MOD_PFD360 = 4
-};
-
-enum p8_pll_utils_bus_id
-{
-    RING_BUS_ID_0 = 0,
-    RING_BUS_ID_1 = 1,
-    RING_BUS_ID_2 = 2,
-    RING_BUS_ID_3 = 3,
-    RING_BUS_ID_4 = 4,
-    RING_BUS_ID_5 = 5,
-    RING_BUS_ID_6 = 6,
-    RING_BUS_ID_7 = 7
-};
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Scan PLL boundary ring with setpulse
-//
-// parameters: i_target              => chip target
-//             i_pll_ring_addr       => PLL ring address
-//             i_pll_ring_op         => modification to be made to base PLL content
-//             i_pll_bus_id          => bus instance to target for modification
-//             i_mask_scan_collision => mask scan collision bit in chiplet
-//                                      pervasive LFIR
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_a_x_pci_dmi_pll_scan_bndy(
-    const fapi::Target& i_target,
-    const p8_pll_utils_ring_address i_pll_ring_addr,
-    const p8_pll_utils_ring_op i_pll_ring_op,
-    const p8_pll_utils_bus_id i_pll_bus_id,
-    const bool i_mask_scan_collision);
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Release chiplet PLL from test mode/bypass/reset and optionally check
-//      for lock
-//
-// parameters: i_target                 => chip target
-//
-//             i_chiplet_base_scom_addr => aligned base address of chiplet SCOM
-//                                         address space
-//             i_check_lock             => check for PLL lock?
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_a_x_pci_dmi_pll_release_pll(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_scom_addr,
-    const bool i_check_lock);
-
-
-} // extern "C"
-
-#endif // _PROC_A_X_PCI_DMI_PLL_UTILS_H_
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.C b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.C
deleted file mode 100644
index 92069c833..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.C
+++ /dev/null
@@ -1,685 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_pcie_slot_power/proc_pcie_slot_power.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_slot_power.C,v 1.3 2014/07/28 21:40:12 ricmata Exp $
-//$Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_slot_power.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_pcie_slot_power.C
-// *! DESCRIPTION : Disable/Enable slot power on hot-plug controlled slots.
-// *!
-// *! OWNER NAME  : Rick Mata         Email: ricmata@us.ibm.com
-// *! BACKUP NAME : Rick Mata	      Email: ricmata@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-//  Version     Date        Owner       Description
-//------------------------------------------------------------------------------
-//    1.0       7/22/14     ricmata     Initial release: Brazos support only.
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include "proc_pcie_slot_power.H"
-
-
-extern "C" 
-{
-
-  //---------------------------//
-  // Function protoptypes      //
-  //---------------------------//
-
-  /**
-  * @brief Issues i2c write command of 1-Byte length.
-  *
-  * @param[in] i_target		Reference to chip target.
-  * @param[in] i_i2c_sel_dev	The i2c slave address to the hotplug controller.
-  * @param[in] i_i2c_addr	The Register offset to load into the FIFO.
-  * @param[in] i_i2c_data 	The Register data to load into the FIFO.
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode proc_perv_i2cms_write(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, const uint8_t i_i2c_data);
-
-
-  /**
-  * @brief Issues i2c read command of 1-Byte length.
-  *
-  * @param[in] i_target		Reference to chip target.
-  * @param[in] i_i2c_sel_dev	The i2c slave address to the hotplug controller.
-  * @param[in] i_i2c_addr	The Register offset to load into the FIFO.
-  * @param[in] 0_i2c_data 	The Register data to read from the FIFO.
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode proc_perv_i2cms_read(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, uint8_t *o_i2c_data);
-
-
-  /**
-  * @brief Checks P8 I2C Master Status register for command complete and errors.
-  *
-  * @param[in] i_target		Reference to chip target
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode check_not_ready_bits(const fapi::Target &i_target);
-
-
-  /**
-  * @brief Checks P8 I2C Master Status register for the FIFO to be flushed.
-  *
-  * @param[in] i_target		Reference to chip target
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode check_fifo_entry_bits(const fapi::Target &i_target);
-
-
-//------------------------------------------------------------------------------
-//
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-  //------------------------------------------------------------------------------
-  // name: proc_pcie_slot_power
-  //------------------------------------------------------------------------------
-  // purpose: 
-  // Enables/Disables slot power to hot-plug controlled pcie slots.
-  //      
-  // parameters: 
-  // 'i_target' is reference to chip target.
-  // 'i_enable_slot_power' TRUE to enable slot power, else FALSE to disable slot power.
-  //
-  //
-  // returns:
-  // FAPI_RC_SUCCESS (success)
-  //
-  // getscom/putscom fapi errors
-  // fapi error assigned from eCMD function failure
-  //
-  // RC_UNKNOWN_PCIE_SLOT_POWER_RC
-  // ekb/eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode proc_pcie_slot_power(const fapi::Target &i_target, const bool i_enable_slot_power) {
-
-    fapi::ReturnCode rc; //fapi return code value
-    ecmdDataBufferBase fsi_data(64);
-    //const uint8_t led9551_reg_pgood = 0x00; // Register to read pgood state on LED9551 Controller.
-    const int MAX_PORTS = 2; // Max number of ports for LED9551 Controller.
-    const uint8_t ary_led9551_reg_en[MAX_PORTS] = {0x05, 0x06}; // Port target on LED9551 register to enable and disable power.
-    const uint8_t led9551_data_slot_off = 0x54;	//Data to disable power on LED9551 controller.
-    const uint8_t led9551_data_slot_on = 0x55; 	//Data to enable power on LED9551 controller.
-    const uint8_t led9551_dev_addr = 0xC4; 	//I2C address to target i2c device.
-    //uint8_t pgood_data;	//Data contents to store the read for the PGOOD register access.
-    //uint64_t nano_sec_delay = 250000000; //(250000000 ns = 250 ms) to wait
-    //uint64_t sim_cyc_delay = 2500000; //2,500,000 simulation cycles to wait
-
-    // mark function entry
-    FAPI_INF("proc_pcie_slot_power: Start");
-
-    fapi::ATTR_NAME_Type chip_type;
-    rc = FAPI_ATTR_GET_PRIVILEGED(ATTR_NAME, &i_target, chip_type);
-    if (rc)  {
-      FAPI_ERR("fapiGetAttribute (Privildged) of ATTR_NAME failed");
-      return rc;
-    }
-
-    if (chip_type == fapi::ENUM_ATTR_NAME_VENICE) { // This is a Venice-based system, Brazos.
-      FAPI_INF("%s: ATTR_NAME retrieve is %x", i_target.toEcmdString(), chip_type);
-
-      for (int counter = 0; counter < MAX_PORTS; counter++) {
-        //DISABLE_SLOT_POWER
-        if(!i_enable_slot_power) {
-          rc = proc_perv_i2cms_write(i_target, led9551_dev_addr, ary_led9551_reg_en[counter], led9551_data_slot_off);
-          if (rc) {
-            FAPI_ERR("Error occurred while disabling slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString());
-            return rc;
-          }
-          FAPI_INF("Disabled slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString());
-        }
-        
-        //ENABLE_SLOT_POWER
-        else { // (i_enable_slot_power)
-          rc = proc_perv_i2cms_write(i_target, led9551_dev_addr, ary_led9551_reg_en[counter], led9551_data_slot_on);
-          if (rc) {
-            FAPI_ERR("Error occurred while enabling slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString());
-            return rc;
-          }
-          FAPI_INF("Enabled slot power on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString());
-        }
-      }
-
-
-/*      //Removing this section as we decussed in a broader meeting that we don't need to check for PGOOD. We will let PHYP or Sapphire do the checking.
-      //Wait before checking PGOOD state.
-      rc = fapiDelay(nano_sec_delay, sim_cyc_delay);
-      if (rc) {
-        FAPI_ERR("%s: fapiDelay error");
-        return rc;
-      }
-      
-      //Read PGOOD State
-      rc = proc_perv_i2cms_read(i_target, led9551_dev_addr, led9551_reg_pgood, &pgood_data);
-      if (rc) {
-        FAPI_ERR("Error occurred while reading pgood register on I2C addr=%X, target=%s", led9551_dev_addr, i_target.toEcmdString());
-        return rc;
-      }
-      FAPI_INF("PGOOD register read on I2C addr=%X, value=%x, target=%s", led9551_dev_addr, pgood_data, i_target.toEcmdString());
-*/
-    }
-    else {
-      FAPI_INF("%s: This chip type is not supported. ATTR_NAME retrieve is %x", i_target.toEcmdString(), chip_type);
-    }
-
-    // mark function entry
-    FAPI_INF("proc_pcie_slot_power: End");
-    return rc;
-  }
-
-
-
-  //------------------------------------------------------------------------------
-  // name: proc_perv_i2cms_write
-  //------------------------------------------------------------------------------
-  // purpose: 
-  // Set up of P8 I2C Master engine for I2C write operations.
-  //      
-  // parameters: 
-  // 'i_target' is reference to chip target
-  // 'i_i2c_sel_dev' is reference to i2c device target
-  // 'i_i2c_addr' is reference to the address entered into the FIFO
-  // 'i_i2c_data' is reference to data for write operation
-  //
-  // returns:
-  //
-  // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml)
-  // 
-  // getscom/putscom fapi errors
-  // fapi error assigned from eCMD function failure
-  // 
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode proc_perv_i2cms_write(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, const uint8_t i_i2c_data) {
-
-    fapi::ReturnCode rc; //fapi return code value
-    uint32_t rc_ecmd;    //ecmd return code value
-    const uint32_t data_size = 64; //Size of data buffer
-    ecmdDataBufferBase fsi_data(data_size);
-
-    // mark function entry
-    FAPI_INF("proc_perv_i2cms_write: Start");
-
-    //1. Check I2C Status for I2C errors or complete bit not set
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_not_ready_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-
-    //2. Initialize I2C Mode register
-    rc_ecmd = fsi_data.insertFromRight(I2C_MODE_DATA, 0, 32);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Load I2C Mode register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_MODE_0x000A0026, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_MODE_0x000A0026, i_target.toEcmdString());
-      return rc;
-    }
-
-    //3. Initialize I2C Command register
-    rc_ecmd = fsi_data.setWord(0, I2C_CMD_DATA_2B);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd = fsi_data.insertFromRight(i_i2c_sel_dev, 8, 8);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd = fsi_data.clearBit(15);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) setting bit on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Load I2C Command register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_COMMAND_0x000A0025, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_COMMAND_0x000A0025, i_target.toEcmdString());
-      return rc;
-    }
-
-    //4. Write address offset into the I2C FIFO
-    rc_ecmd = fsi_data.insertFromRight(i_i2c_addr, 0, 8);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Write the I2C FIFO with the address to slave device on target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data );
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString());
-      return rc;
-    }
-
-    //5. Poll for the FIFO Entry count in the status to ensure all data was checked in.
-
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_fifo_entry_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-
-    //6. Write data into the I2C FIFO 
-    rc_ecmd = fsi_data.insertFromRight(i_i2c_data, 0, 8);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Write the I2C FIFO with data to slave device on target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString());
-      return rc;
-    }
-
-     //TODO: Step 7. is not required for 1-byte length transfers. Instead, will go straight to check for complete bit and errors. Leaving it here for possible future enhancements.
-    //7. Repeat 5. and 6. above until all data is transferred. 
-
-    //8. Poll for complete bit to be set and check for errors.
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_not_ready_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-
-    // mark function entry
-    FAPI_INF("proc_perv_i2cms_write: End");
-    return rc;
-  }
-
-
-  //------------------------------------------------------------------------------
-  // name: proc_perv_i2cms_read
-  //------------------------------------------------------------------------------
-  // purpose: 
-  // Set up of P8 I2C Master engine for I2C write operations.
-  //      
-  // parameters: 
-  // 'i_target' is reference to chip target
-  // 'i_i2c_sel_dev' is reference to i2c device target
-  // 'i_i2c_addr' is reference to the address entered into the FIFO
-  // 'o_i2c_data' is reference to the data read from the FIFO
-  //
-  // returns:
-  //
-  // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml)
-  // 
-  // getscom/putscom fapi errors
-  // fapi error assigned from eCMD function failure
-  // 
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode proc_perv_i2cms_read(const fapi::Target &i_target, const uint8_t i_i2c_sel_dev, const uint8_t i_i2c_addr, uint8_t  *o_i2c_data) {
-
-    fapi::ReturnCode rc; //fapi return code value
-    uint32_t rc_ecmd;    //ecmd return code value
-    const uint32_t data_size = 64; //Size of data buffer
-    ecmdDataBufferBase fsi_data(data_size);
-
-    // mark function entry
-    FAPI_INF("proc_perv_i2cms_read: Start");
-
-    //1. Check I2C Status for I2C errors or complete bit not set
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_not_ready_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-
-    //2. Initialize I2C Mode register
-    rc_ecmd = fsi_data.insertFromRight(I2C_MODE_DATA, 0, 32);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Load I2C Mode register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_MODE_0x000A0026, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_MODE_0x000A0026, i_target.toEcmdString());
-      return rc;
-    }
-
-    //3. Initialize I2C Command register
-    rc_ecmd = fsi_data.setWord(0, I2C_CMD_DATA_1B);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd = fsi_data.insertFromRight(i_i2c_sel_dev, 8, 8);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd = fsi_data.clearBit(15);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) clearing bit on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Load I2C Command register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_COMMAND_0x000A0025, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_COMMAND_0x000A0025, i_target.toEcmdString());
-      return rc;
-    }
-
-    //4. Write address offset into the I2C FIFO
-    rc_ecmd = fsi_data.insertFromRight(i_i2c_addr, 0, 8);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Write the I2C FIFO with the address to slave device on target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data );
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString());
-      return rc;
-    }
-
-    //5. Poll for complete bit to be set and check for errors.
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_not_ready_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-    
-    //6. Initialize I2C Command register
-    rc_ecmd = fsi_data.setWord(0, I2C_CMD_DATA_1B);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) setting first word on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd = fsi_data.insertFromRight(i_i2c_sel_dev, 8, 8);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) inserting data on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    rc_ecmd = fsi_data.setBit(15);
-    if(rc_ecmd) {
-      FAPI_ERR("Error (%u) setting bit on %s", rc_ecmd, i_target.toEcmdString());
-      rc.setEcmdError(rc_ecmd);
-      return rc;
-    }
-    FAPI_DBG("Load I2C Command register target=%s, value=0x%016llX", i_target.toEcmdString(), fsi_data.getDoubleWord(0));
-    rc = fapiPutScom(i_target, I2CMS_COMMAND_0x000A0025, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiPutScom error (addr: 0x%08llX), target=%s", I2CMS_COMMAND_0x000A0025, i_target.toEcmdString());
-      return rc;
-    }
-
-    //7. Read data from the I2C FIFO
-    FAPI_DBG("Read I2C data from the FIFO");
-    rc = fapiGetScom(i_target, I2CMS_FIFO1_READ_0x000A0024, fsi_data );
-    if (rc) {
-      FAPI_ERR("fapiGetScom error (addr: 0x%08llX), target=%s", I2CMS_FIFO1_READ_0x000A0024, i_target.toEcmdString());
-      return rc;
-    }
-    FAPI_DBG("Read data from the I2C FIFO to slave device on target=%s, value=0x%X", i_target.toEcmdString(), fsi_data.getByte(0));
-    *o_i2c_data = fsi_data.getByte(0);
-
-    //8. Poll status register's FIFO_ENTRY_COUNT to know if entire FIFO has been read.
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX)", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_fifo_entry_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-
-    //TODO: Step 9. is not required for 1-byte length transfers. Instead, will go straight to check for complete bit and errors. Leaving it here for possible future enhancements.
-
-    //9. Repeat 7. and 8. above until all data is read from the FIFO.
-    
-    //10. Poll for complete bit and check for any errors. 
-    FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX)", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-    rc = check_not_ready_bits(i_target);
-    if(rc) {
-      FAPI_ERR("Error occurred while checking target=%s P8 I2C regster (addr: 0x%08llX) for a error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-
-  // mark function entry
-  FAPI_INF("proc_perv_i2cms_read: End");
-  return rc;
-  }
-
-    
-  //------------------------------------------------------------------------------
-  //------------------------------------------------------------------------------
-  // name: check_not_ready_bits
-  //------------------------------------------------------------------------------
-  // purpose: 
-  // Checks P8 I2C Status register for complete bit and errors.
-  //      
-  // Bits that indicate P8 I2C Master engine is not ready for operation.
-  // bit 0	Invalid Command.
-  // bit 1	Local Bus Parity Error.
-  // bit 2	Back End Overrun Error.
-  // bit 3	Back End Access Error.
-  // bit 4	Arbitration Lost Error.
-  // bit 5	NACK Recieved Error.
-  // bit 6	Data Request.     
-  // bit 8	Stop Error.
-  //
-  // parameters: 
-  // 'i_target' is reference to chip target
-  //
-  // returns:
-  //
-  // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml)
-  // 
-  // getscom/putscom fapi errors
-  // fapi error assigned from eCMD function failure
-  // 
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode check_not_ready_bits(const fapi::Target &i_target) {
-
-    fapi::ReturnCode rc;
-    const uint32_t data_size = 64; //Size of data buffer
-    ecmdDataBufferBase fsi_data(data_size);
-    const int MAX_NUM_NOT_RDY_BITS = 8; //Maximum number of bits that indicate P8 I2C Master engine is not ready.
-    const uint32_t ARY_NOT_RDY_BITS[MAX_NUM_NOT_RDY_BITS] = {0, 1, 2, 3, 4, 5, 6, 8}; //Array of bits that indicate P8 I2C Master engine is not ready.
-    uint64_t nano_sec_delay = 1000000; //(1000000 ns = 1 ms ) to wait
-    uint64_t sim_cyc_delay = 10000; //10,000 simulation cycles to wait
-    int poll_counter; //Number of iterations while polling
-    const int MAX_NUM_POLLS = 100; //Maximum number of iterations (So, 1ms * 100 = 100ms before timeout)
-
-    // mark function entry
-    FAPI_INF("check_not_ready_bits: Start");
-
-    //1. Read I2C Status register and poll for complete bit to be set then check for errors.
-    rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-    poll_counter = 0;
-    while (!fsi_data.isBitSet(7)) {
-      poll_counter++;
-
-      //Exceed max number of polls
-      if(poll_counter > MAX_NUM_POLLS) {
-        FAPI_ERR("Exceeded max number of polls (%d) for target=%s", MAX_NUM_POLLS, i_target.toEcmdString());
-        const fapi::Target & CHIP_TARGET = i_target;
-        const uint64_t & ADDRESS_VAL = I2CMS_STATUS_0x000A002B;
-        ecmdDataBufferBase & DATA_REG = fsi_data;
-        FAPI_SET_HWP_ERROR(rc, RC_I2C_COMPLETE_BIT_TIMEOUT_RC);
-        return rc;
-      }
-      FAPI_DBG("target=%s, Poll Iter: %d", i_target.toEcmdString(), poll_counter);
-
-      //Wait before checking again
-      rc = fapiDelay(nano_sec_delay, sim_cyc_delay);
-      if (rc) {
-        FAPI_ERR("fapiDelay error");
-        return rc;
-      }
-
-      //Get data from I2C Status register
-      FAPI_DBG("Checking I2C Status on target=%s (addr: 0x%08llX) for at least 1 error bit", i_target.toEcmdString(), I2CMS_STATUS_0x000A002B);
-      rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data);
-      if (rc) {
-        FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B);
-        return rc;
-      }
-    }
-
-    //2. Check P8 I2C Master engine is ready for new operation.
-    for(int counter = 0; counter < MAX_NUM_NOT_RDY_BITS; counter++) {
-      if( fsi_data.isBitSet(ARY_NOT_RDY_BITS[counter] )) {
-        FAPI_ERR("Error in bit pos %u of I2CMS_STATUS_0x000A002B, (addr: 0x%08llX) ",ARY_NOT_RDY_BITS[counter], I2CMS_STATUS_0x000A002B);
-        const fapi::Target & CHIP_TARGET = i_target;
-        const uint64_t & ADDRESS_VAL = I2CMS_STATUS_0x000A002B;
-        ecmdDataBufferBase & DATA_REG = fsi_data;
-        FAPI_SET_HWP_ERROR(rc, RC_I2C_ERROR_BIT_PRESENT_RC);
-        return rc;
-      }
-    }
-
-    // mark function exit
-    FAPI_INF("check_not_ready_bits: End");
-    return rc;
-  }
-
-
-  //------------------------------------------------------------------------------
-  //------------------------------------------------------------------------------
-  // name: check_fifo_entry_bits
-  //------------------------------------------------------------------------------
-  // purpose: 
-  // Checks P8 I2C Status register for FIFO entry to read 00 indicating FIFO has been flushed..
-  //      
-  // Bits that indicate P8 I2C Master engine is not ready for operation.
-  // bit[28:31] - FIFO Entry Count
-  //
-  // parameters: 
-  // 'i_target' is reference to chip target
-  //
-  // returns:
-  //
-  // (Note: refer to file eclipz/chips/p8/working/procedures/xml/error_info/proc_pcie_slot_power_errors.xml)
-  // 
-  // getscom/putscom fapi errors
-  // fapi error assigned from eCMD function failure
-  // 
-  //------------------------------------------------------------------------------
-  fapi::ReturnCode check_fifo_entry_bits(const fapi::Target &i_target) {
-
-    fapi::ReturnCode rc;
-    const uint32_t data_size = 64; //Size of data buffer
-    ecmdDataBufferBase fsi_data(data_size);
-    uint64_t nano_sec_delay = 1000000; //(1000000 ns = 1 ms ) to wait
-    uint64_t sim_cyc_delay = 10000; //10,000 simulation cycles to wait
-    int poll_counter; //Number of iterations while polling
-    const int MAX_NUM_POLLS = 100; //Maximum number of iterations (So, 1ms * 100 = 100ms before timeout)
-
-    // mark function entry
-    FAPI_INF("check_fifo_entry_bits: Start");
-
-    //Read I2C Status register and poll for FIFO entry count to reach 00.
-    rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data);
-    if (rc) {
-      FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B);
-      return rc;
-    }
-    poll_counter = 0;
-    while (!fsi_data.isBitClear(28, 4)) {
-      poll_counter++;
-
-      //Exceed max number of polls
-      if(poll_counter > MAX_NUM_POLLS) {
-        FAPI_ERR("Exceeded max number of polls (%d) for target=%s", MAX_NUM_POLLS, i_target.toEcmdString());
-        const fapi::Target & CHIP_TARGET = i_target;
-        const uint64_t & ADDRESS_VAL = I2CMS_STATUS_0x000A002B;
-        ecmdDataBufferBase & DATA_REG = fsi_data;
-        FAPI_SET_HWP_ERROR(rc, RC_I2C_FIFO_INCOMPLETE_RC);
-        return rc;
-      }
-      FAPI_DBG("target=%s, Poll Iter: %d", i_target.toEcmdString(), poll_counter);
-
-
-      //Wait before checking again
-      rc = fapiDelay(nano_sec_delay, sim_cyc_delay);
-      if (rc) {
-        FAPI_ERR("fapiDelay error");
-        return rc;
-      }
-
-      //Get data from I2C Status register
-      rc = fapiGetScom(i_target, I2CMS_STATUS_0x000A002B, fsi_data);
-      if (rc) {
-        FAPI_ERR("fapiGetScom error (addr: 0x%08llX)", I2CMS_STATUS_0x000A002B);
-        return rc;
-      }
-    }
-
-    // mark function exit
-    FAPI_INF("check_fifio_entry_bits: End");
-    return rc;
-  }
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.H b/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.H
deleted file mode 100644
index 6795dc883..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_pcie_slot_power/proc_pcie_slot_power.H
+++ /dev/null
@@ -1,90 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/activate_powerbus/proc_pcie_slot_power/proc_pcie_slot_power.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_pcie_slot_power.H,v 1.3 2014/07/28 21:40:41 ricmata Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_pcie_slot_power.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_pcie_slot_power.C
-// *! DESCRIPTION : Disable/Enable slot power on hot-plug controlled slots.
-// *!
-// *! OWNER NAME  : Rick Mata         Email: ricmata@us.ibm.com
-// */ BACKUP NAME : Rick Mata	      Email: ricmata@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-//------------------------------------------------------------------------------
-//  Version     Date        Owner       Description
-//------------------------------------------------------------------------------
-//    1.0       7/22/14     ricmata     Initial release: Brazos support only.
-//------------------------------------------------------------------------------
-#ifndef _PROC_PCIE_SLOT_POWER_H_
-#define _PROC_PCIE_SLOT_POWER_H_
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include "fapi.H"
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-const uint32_t I2C_MODE_DATA		   = 0x01760000;
-const uint32_t I2C_CMD_DATA_2B		   = 0xD0000002;
-const uint32_t I2C_CMD_DATA_1B		   = 0xD0000001;
-const uint64_t I2CMS_FIFO1_READ_0x000A0024 = 0x00000000000A0024ULL;
-const uint64_t I2CMS_COMMAND_0x000A0025    = 0x00000000000A0025ULL;
-const uint64_t I2CMS_MODE_0x000A0026       = 0x00000000000A0026ULL;
-const uint64_t I2CMS_STATUS_0x000A002B     = 0x00000000000A002BULL;
-const uint64_t I2CMS_EXT_STATUS_0x000A002C = 0x00000000000A002CULL;
-
-//------------------------------------------------------------------------------
-// Structure Definition(s)
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_pcie_slot_power_FP_t)(const fapi::Target &i_target, const bool);
-
-extern "C"
-{
-  /**
-  * @brief Disable/enable slot power to hot-plug controlled slots.
-  *
-  * @param[in] (1) 'i_target' is reference to chip target
-  *            (2) 'i_enable_slot_power' is reference to boolean object: True = ON, False = OFF.
-  *
-  * @return ReturnCode
-  *
-  *
-  */
-  fapi::ReturnCode proc_pcie_slot_power(const fapi::Target &i_target, const bool i_enable_slot_power);
-
-} //extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
deleted file mode 100644
index 025c3d0c9..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C
+++ /dev/null
@@ -1,890 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_start_clocks_chiplets.C,v 1.19 2015/05/14 21:21:34 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ****
-// *|
-// *! TITLE       : proc_start_clocks_chiplets.H
-// *! DESCRIPTION : Start X/A/PCIE chiplet clocks (FAPI)
-// *!
-// *! OWNER NAME  : Ralph Koester           Email: rkoester@de.ibm.com
-// *! BACKUP NAME : Gebhard Weber           Email: gweber@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_start_clocks_chiplets.H"
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear chiplet fence in GP3 register
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_clear_chiplet_fence(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase mask_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_GP3_AND_0x000F0013;
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_chiplet_fence: Start");
-
-    do
-    {
-        // form AND mask to clear chiplet fence bit
-        rc_ecmd |= mask_data.flushTo1();
-        rc_ecmd |= mask_data.clearBit(GP3_FENCE_EN_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_chiplet_fence: Error 0x%x setting up data buffer to clear chiplet fence",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write chiplet GP3 AND mask register to clear fence bit
-        rc = fapiPutScom(i_target, scom_addr, mask_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_chiplet_fence: fapiPutScom error (GP3_AND_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_chiplet_fence: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear pervasive fence in GP0 register
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_clear_perv_fence(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase mask_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_GP0_AND_0x00000004;
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_perv_fence: Start");
-
-    do
-    {
-        // form AND mask to clear pervasive fence bit
-        rc_ecmd |= mask_data.flushTo1();
-        rc_ecmd |= mask_data.clearBit(GP0_PERV_FENCE_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_perv_fence: Error 0x%x setting up data buffer to clear pervasive fence",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write chiplet GP0 AND mask register to clear pervasive fence bit
-        rc = fapiPutScom(i_target, scom_addr, mask_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_perv_fence: fapiPutScom error (GP0_AND_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_perv_fence: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set functional mode clock mux selects
-//           in GP0 register
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_set_mux_selects(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase mask_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_GP0_AND_0x00000004;
-
-    FAPI_DBG("proc_start_clocks_chiplet_set_mux_selects: Start");
-
-    do
-    {
-        // form AND mask to clear mux selects
-        rc_ecmd |= mask_data.flushTo1();
-        rc_ecmd |= mask_data.clearBit(GP0_ABSTCLK_MUXSEL_BIT);
-        rc_ecmd |= mask_data.clearBit(GP0_SYNCCLK_MUXSEL_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_set_mux_selects: Error 0x%x setting up data buffer to clear chiplet mux selects",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write chiplet GP0 AND mask register to clear mux selects
-        rc = fapiPutScom(i_target, scom_addr, mask_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_set_mux_selects: fapiPutScom error (GP0_AND_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_set_mux_selects: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to get partial good vector from SEEPROM
-// parameters: i_target                 => chip target
-//             i_chiplet_base_addr      => base SCOM address for chiplet
-//             o_chiplet_reg_vec        => output vector
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-
-// note:
-// expected value out of SEEPROM (in case of "all good", the "Partial Good Region"-Pattern are:
-// XBUS = 0xF00, ABUS = 0xE100, PCIE = 0xF700
-
-fapi::ReturnCode proc_start_clocks_get_partial_good_vector(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr,
-    uint64_t * o_chiplet_reg_vec
-    )
-{
-    fapi::ReturnCode rc;
-    uint64_t partial_good_regions[32];
-
-    FAPI_DBG("proc_start_clocks_get_partial_good_vector: Start");
-
-    do
-    {
-
-        FAPI_DBG("proc_start_clocks_get_partial_good_vector: Get attribute ATTR_CHIP_REGIONS_TO_ENABLE (partial good region data) " );
-        rc = FAPI_ATTR_GET( ATTR_CHIP_REGIONS_TO_ENABLE, &i_target, partial_good_regions);
-        if (rc) {
-            FAPI_ERR("fapi_attr_get( ATTR_CHIP_REGIONS_TO_ENABLE ) failed. With rc = 0x%x",
-                     (uint32_t) rc );
-            break;
-        }
-
-
-        FAPI_DBG("proc_start_clocks_get_partial_good_vector: start assignment of the partial good vector per chiplet");
-
-        switch (i_chiplet_base_addr)
-        {
-
-          case X_BUS_CHIPLET_0x04000000:
-              FAPI_DBG("proc_start_clocks_get_partial_good_vector: XBUS, attribute for XBUS (%016llX)", partial_good_regions[4]);
-              *o_chiplet_reg_vec = partial_good_regions[4];
-              break;
-
-
-          case A_BUS_CHIPLET_0x08000000:
-              FAPI_DBG("proc_start_clocks_get_partial_good_vector: ABUS, attribute for ABUS (%016llX)", partial_good_regions[8]);
-              *o_chiplet_reg_vec = partial_good_regions[8];
-              break;
-
-          case PCIE_CHIPLET_0x09000000:
-              FAPI_DBG("proc_start_clocks_get_partial_good_vector: PCIE, attribute for PCIE (%016llX)", partial_good_regions[9]);
-              *o_chiplet_reg_vec = partial_good_regions[9];
-              break;
-
-          default:
-
-               FAPI_ERR("proc_start_clocks_get_partial_good_vector: invalid chiplet base address selected when selecting par. good vector (0x%08X)",
-                        i_chiplet_base_addr);
-               uint32_t CHIPLET_BASE_SCOM_ADDR = i_chiplet_base_addr;
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_CHIPLETS_PARTIAL_GOOD_ERR);
-               break;
-
-        }
-
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_get_partial_good_vector: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to set clock region register (starts clocks)
-// parameters: i_target              => chip target
-//             i_chiplet_base_addr   => base SCOM address for chiplet
-//             i_chiplet_reg_vec     => vector from SEEPROM with partial good
-//                                      clock regions
-//             o_chiplet_clkreg_vec  => output vector which contains
-//                                      the masked vector -> used to set the
-//					clock region register	
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_set_clk_region_reg(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr,
-    const uint64_t i_chiplet_reg_vec,
-    uint64_t * o_chiplet_clkreg_vec
-    )
-
-
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_CLK_REGION_0x00030006;
-    uint64_t extracted_rec_vec;
-    uint64_t clk_region_start_nsl_ary_masked;
-    uint64_t clk_region_start_all_masked;
-
-    FAPI_DBG("proc_start_clocks_chiplet_set_clk_region_reg: Start");
-
-    do
-    {
-
-
-        // bitwise ORing of input vector
-        extracted_rec_vec = PROC_START_CLOCKS_CHIPLETS_CLOCK_REGION_MANIPULATION | i_chiplet_reg_vec;
-
-        // start NSL/array clocks
-
-        clk_region_start_nsl_ary_masked = PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY & extracted_rec_vec;
-
-        rc_ecmd |= data.setDoubleWord(0, clk_region_start_nsl_ary_masked);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: Error 0x%x setting up data buffer for NSL/ARY clock start",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutScom(i_target, scom_addr, data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: fapiPutScom error (CLK_REGION_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-        // start all clocks
-
-        clk_region_start_all_masked = PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL & extracted_rec_vec;
-
-        // output: value written into clk_region register, reused for status register checking
-
-        *o_chiplet_clkreg_vec = clk_region_start_all_masked;
-
-        rc_ecmd |= data.setDoubleWord(0, clk_region_start_all_masked);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: Error 0x%x setting up data buffer for SL/NSL/ARY clock start",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutScom(i_target, scom_addr, data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_set_clk_region_reg: fapiPutScom error (CLK_REGION_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_set_clk_region_reg: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to check clock status register to ensure
-//           all desired clock domains have been started
-// parameters: i_target             => chip target
-//             i_chiplet_base_addr  => base SCOM address for chiplet
-//             i_chiplet_clkreg_vec => region vector of SEEPROM for clock regions
-//                                     need to be turned on
-// returns: FAPI_RC_SUCCESS if operation was successful, else
-//          RC_PROC_START_CLOCKS_CHIPLETS_CLK_STATUS_ERR if status register
-//          data does not match expected pattern
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_check_clk_status_reg(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr,
-    const uint64_t i_chiplet_clkreg_vec)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase vec_data(64);
-    ecmdDataBufferBase status_data(64);
-    ecmdDataBufferBase exp_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_CLK_STATUS_0x00030008;
-    const uint32_t xbus = X_BUS_CHIPLET_0x04000000;
-    const uint32_t abus = A_BUS_CHIPLET_0x08000000;
-    const uint32_t pcie = PCIE_CHIPLET_0x09000000;
-
-    FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: Start");
-
-    do
-    {
-
-        // read clock status register
-        rc = fapiGetScom(i_target, scom_addr, status_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: fapiGetScom error (CLK_STATUS_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-        // load it with reference data
-        rc_ecmd |= vec_data.setDoubleWord(0, i_chiplet_clkreg_vec);
-        // generate expected value databuffer
-        rc_ecmd |= exp_data.flushTo1();
-
-        if ( i_chiplet_base_addr == xbus)
-        {
-
-           if ( vec_data.isBitSet(4)) { rc_ecmd |= exp_data.clearBit(0,3); }
-           if ( vec_data.isBitSet(5)) { rc_ecmd |= exp_data.clearBit(3,6); }
-           if ( vec_data.isBitSet(6)) { rc_ecmd |= exp_data.clearBit(9,6); }
-           if ( vec_data.isBitSet(7)) { rc_ecmd |= exp_data.clearBit(15,3);}
-
-        }
-
-        else
-        {
-
-           if ( vec_data.isBitSet(4))  { rc_ecmd |= exp_data.clearBit(0,3); }
-           if ( vec_data.isBitSet(5))  { rc_ecmd |= exp_data.clearBit(3,3); }
-           if ( vec_data.isBitSet(6))  { rc_ecmd |= exp_data.clearBit(6,3); }
-           if ( vec_data.isBitSet(7))  { rc_ecmd |= exp_data.clearBit(9,3); }
-           if ( vec_data.isBitSet(9))  { rc_ecmd |= exp_data.clearBit(15,3);}
-           if ( vec_data.isBitSet(10)) { rc_ecmd |= exp_data.clearBit(18,3);}
-           if ( vec_data.isBitSet(11)) { rc_ecmd |= exp_data.clearBit(21,3);}
-
-        }
-
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Error 0x%x setting up data buffer to set clock status",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-
-        // check that value matches expected pattern
-        // set a unique HWP_ERROR
-        if (status_data.getDoubleWord(0) != exp_data.getDoubleWord(0))
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_check_clk_status_reg: Clock status register actual value (%016llX) does not match expected value (%016llX)",
-                     status_data.getDoubleWord(0), exp_data.getDoubleWord(0));
-            ecmdDataBufferBase & STATUS_REG = status_data;
-            ecmdDataBufferBase & EXPECTED_REG = exp_data;
-
-            if ( i_chiplet_base_addr == xbus)
-            {
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_CLK_STATUS_ERR);
-               break;
-            }
-            if ( i_chiplet_base_addr == abus)
-            {
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_CLK_STATUS_ERR);
-               break;
-            }
-            if ( i_chiplet_base_addr == pcie)
-            {
-               const fapi::Target & CHIP_IN_ERROR  = i_target;
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_CLK_STATUS_ERR);
-               break;
-            }
-
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_check_clk_status_reg: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear force align in GP0 register
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_clear_force_align(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase mask_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_GP0_AND_0x00000004;
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_force_align: Start");
-
-    do
-    {
-        // form AND mask to clear force align bit
-        rc_ecmd |= mask_data.flushTo1();
-        rc_ecmd |= mask_data.clearBit(GP0_FORCE_ALIGN_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_force_align: Error 0x%x setting up data buffer to clear force align",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write chiplet GP0 AND mask register to clear force align bit
-        rc = fapiPutScom(i_target, scom_addr, mask_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_force_align: fapiPutScom error (GP0_AND_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_force_align: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to clear flushmode inhibit in GP0 register
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_clear_flushmode_inhibit(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase mask_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_GP0_AND_0x00000004;
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_flushmode_inhibit: Start");
-
-    do
-    {
-        // form AND mask to clear force align bit
-        rc_ecmd |= mask_data.flushTo1();
-        rc_ecmd |= mask_data.clearBit(GP0_FLUSHMODE_INHIBIT_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_flushmode_inhibit: Error 0x%x setting up data buffer to clear flushmode inhibit",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write chiplet GP0 AND mask register to clear force align bit
-        rc = fapiPutScom(i_target, scom_addr, mask_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_clear_flushmode_inhibit: fapiPutScom error (GP0_AND_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_clear_flushmode_inhibit: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to check chiplet FIR register for errors
-//           after clocks have been started
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else
-//          RC_PROC_START_CLOCKS_CHIPLETS_FIR_ERR if FIR register data doesn't
-//          match expected pattern
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplet_check_fir(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-{
-    fapi::ReturnCode rc;
-    ecmdDataBufferBase fir_data(64);
-    uint32_t scom_addr = i_chiplet_base_addr |
-                         GENERIC_XSTOP_0x00040000;
-    const uint32_t xbus = X_BUS_CHIPLET_0x04000000;
-    const uint32_t abus = A_BUS_CHIPLET_0x08000000;
-    const uint32_t pcie = PCIE_CHIPLET_0x09000000;
-
-
-    FAPI_DBG("proc_start_clocks_chiplet_check_fir: Start");
-
-    do
-    {
-        // read chiplet FIR register
-        rc = fapiGetScom(i_target, scom_addr, fir_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_check_fir: fapiGetScom error (XSTOP_0x%08X)",
-                     scom_addr);
-            break;
-        }
-
-        // check that value matches expected pattern
-        // set a unique HWP_ERROR
-        if (fir_data.getDoubleWord(0) !=
-            PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP)
-        {
-            FAPI_ERR("proc_start_clocks_chiplet_check_fir: FIR register actual value (%016llX) does not match expected value (%016llX)",
-                     fir_data.getDoubleWord(0), PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP);
-            ecmdDataBufferBase & FIR_REG = fir_data;
-            const uint64_t & FIR_EXP_REG = PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP;
-
-
-            if ( i_chiplet_base_addr == xbus)
-            {
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_XBUS_CHIPLET_FIR_ERR);
-               break;
-            }
-            if ( i_chiplet_base_addr == abus)
-            {
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_ABUS_CHIPLET_FIR_ERR);
-               break;
-            }
-            if ( i_chiplet_base_addr == pcie)
-            {
-
-               const fapi::Target & CHIP_IN_ERROR  = i_target;
-               FAPI_SET_HWP_ERROR(rc, RC_PROC_START_CLOCKS_PCIE_CHIPLET_FIR_ERR);
-               break;
-            }
-
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_chiplet_check_fir: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// function: utility subroutine to run clock start sequence on a generic chiplet
-// parameters: i_target            => chip target
-//             i_chiplet_base_addr => base SCOM address for chiplet
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_generic_chiplet(
-    const fapi::Target& i_target,
-    const uint32_t i_chiplet_base_addr)
-
-{
-    fapi::ReturnCode rc;
-    uint64_t chiplet_reg_vec;
-    uint64_t chiplet_clkreg_vec;
-
-    FAPI_DBG("proc_start_clocks_generic_chiplet: Start");
-
-    do
-    {
-
-
-        // clear chiplet fence in GP3 register
-        FAPI_DBG("Writing GP3 AND mask to clear chiplet fence ...");
-        rc = proc_start_clocks_chiplet_clear_chiplet_fence(i_target,
-                                                           i_chiplet_base_addr);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP3 AND mask to clear chiplet fence");
-            break;
-        }
-
-        // clear pervasive fence in GP0 register
-        FAPI_DBG("Writing GP0 AND mask to clear pervasive fence ...");
-        rc = proc_start_clocks_chiplet_clear_perv_fence(i_target,
-                                                        i_chiplet_base_addr);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to clear pervasive fence");
-            break;
-        }
-
-        // set functional clock mux selects in GP0 register
-        FAPI_DBG("Writing GP0 AND mask to set functional clock mux selects ...");
-        rc = proc_start_clocks_chiplet_set_mux_selects(i_target,
-                                                       i_chiplet_base_addr);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to set functional clock mux selects");
-            break;
-        }
-
-        // pick partial good region vector from SEEPROM
-        FAPI_DBG("Get partial good region vector ...");
-        rc = proc_start_clocks_get_partial_good_vector(i_target,
-                                                       i_chiplet_base_addr,
-                                                       & chiplet_reg_vec
-                                                       );
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error getting partial good region vector");
-            break;
-        }
-
-
-        // write clock region register to start clocks
-        FAPI_DBG("Writing clock region register to start clocks ...");
-        rc = proc_start_clocks_chiplet_set_clk_region_reg(i_target,
-                                                          i_chiplet_base_addr,
-                                                          chiplet_reg_vec,
-                                                          & chiplet_clkreg_vec
-                                                          );
-
-
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing clock region register");
-            break;
-        }
-
-        // check clock status register to ensure that all clocks are started
-        FAPI_DBG("Checking clock status register ...");
-        rc = proc_start_clocks_chiplet_check_clk_status_reg(i_target,
-                                                            i_chiplet_base_addr,
-                                                            chiplet_clkreg_vec);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error checking clock status register");
-            break;
-        }
-
-        // clear force align bit in GP0 register
-        FAPI_DBG("Writing GP0 AND mask to clear force align ...");
-        rc = proc_start_clocks_chiplet_clear_force_align(i_target,
-                                                         i_chiplet_base_addr);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to clear force align");
-            break;
-        }
-
-        // clear flushmode inhibit bit in GP0 register
-        FAPI_DBG("Writing GP0 AND mask to clear flushmode inhibit ...");
-        rc = proc_start_clocks_chiplet_clear_flushmode_inhibit(i_target,
-                                                               i_chiplet_base_addr);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error writing GP0 AND mask to clear flushmode inhibit");
-            break;
-        }
-
-        // check chiplet FIR register
-        FAPI_DBG("Checking chiplet FIR register for errors after clock start ...");
-        rc = proc_start_clocks_chiplet_check_fir(i_target,
-                                                 i_chiplet_base_addr);
-        if (rc)
-        {
-            FAPI_ERR("proc_start_clocks_generic_chiplet: Error checking chiplet FIR register after clock start");
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_start_clocks_generic_chiplet: End");
-
-    return rc;
-}
-
-
-//------------------------------------------------------------------------------
-// Hardware Procedure
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
-                                            bool xbus, bool abus, bool pcie)
-{
-    fapi::ReturnCode rc;
-    uint8_t xbus_enable_attr;
-    uint8_t abus_enable_attr;
-    uint8_t pcie_enable_attr;
-
-    // mark HWP entry
-    FAPI_IMP("proc_start_clocks_chiplets: Entering ...");
-
-    do
-    {
-        if (xbus)
-        {
-            // query XBUS partial good attribute
-            rc = FAPI_ATTR_GET(ATTR_PROC_X_ENABLE,
-                               &i_target,
-                               xbus_enable_attr);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_X_ENABLE");
-                break;
-            }
-
-            if (xbus_enable_attr == fapi::ENUM_ATTR_PROC_X_ENABLE_ENABLE)
-            {
-                FAPI_DBG("Starting X bus chiplet clocks ...");
-                rc = proc_start_clocks_generic_chiplet(
-                    i_target,
-                    X_BUS_CHIPLET_0x04000000);
-                if (rc)
-                {
-                    FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (X)");
-                    break;
-                }
-            }
-            else
-            {
-                FAPI_DBG("Skipping XBUS chiplet clock start (partial good).");
-            }
-        }
-
-        if (abus)
-        {
-            // query ABUS partial good attribute
-            rc = FAPI_ATTR_GET(ATTR_PROC_A_ENABLE,
-                               &i_target,
-                               abus_enable_attr);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_A_ENABLE");
-                break;
-            }
-
-            if (abus_enable_attr == fapi::ENUM_ATTR_PROC_A_ENABLE_ENABLE)
-            {
-                FAPI_DBG("Starting A bus chiplet clocks ...");
-                rc = proc_start_clocks_generic_chiplet(
-                    i_target,
-                    A_BUS_CHIPLET_0x08000000);
-                if (rc)
-                {
-                    FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (A)");
-                    break;
-                }
-            }
-            else
-            {
-                FAPI_DBG("Skipping ABUS chiplet clock start (partial good).");
-            }
-        }
-
-        if (pcie)
-        {
-            // query PCIE partial good attribute
-            rc = FAPI_ATTR_GET(ATTR_PROC_PCIE_ENABLE,
-                               &i_target,
-                               pcie_enable_attr);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_start_clocks_chiplets: Error querying ATTR_PROC_PCIE_ENABLE");
-                break;
-            }
-
-            if (pcie_enable_attr == fapi::ENUM_ATTR_PROC_PCIE_ENABLE_ENABLE)
-            {
-                FAPI_DBG("Starting PCIE chiplet clocks ...");
-                rc = proc_start_clocks_generic_chiplet(
-                    i_target,
-                    PCIE_CHIPLET_0x09000000);
-                if (rc)
-                {
-                    FAPI_ERR("proc_start_clocks_chiplets: Error from proc_start_clocks_generic_chiplet (PCIE)");
-                    break;
-                }
-            }
-            else
-            {
-                FAPI_DBG("Skipping PCIE chiplet clock start (partial good).");
-            }
-        }
-
-    } while (0);
-
-    // mark HWP exit
-    FAPI_IMP("proc_start_clocks_chiplets: Exiting ...");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H b/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H
deleted file mode 100644
index 3a0a52e47..000000000
--- a/src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H
+++ /dev/null
@@ -1,115 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_start_clocks_chiplets.H,v 1.7 2014/09/26 19:01:22 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_start_clocks_chiplets.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ****
-// *|
-// *! TITLE       : proc_start_clocks_chiplets.H
-// *! DESCRIPTION : Start X/A/PCIE chiplet clocks (FAPI)
-// *!
-// *! OWNER NAME  : Ralph Koester           Email: rkoester@de.ibm.com
-// *! BACKUP NAME : Gebhard Weber           Email: gweber@de.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-// *! The purpose of this procedure is to start the clocks for X/A/PCIe chiplets
-// *! Reference: FW specification: 7.3, PRV POR specification spreadsheet
-// *!    - Start Xbus, ABus, PCIe clocks
-// *!    - Drop fences
-// *!
-// *! Prerequisites: proc_a_x_pci_pll_setup
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_START_CLOCKS_CHIPLETS_H_
-#define _PROC_START_CLOCKS_CHIPLETS_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_start_clocks_chiplets_FP_t)(const fapi::Target&, bool, bool, bool);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// GP3 register bit/field definitions
-const uint8_t GP3_FENCE_EN_BIT = 18;
-
-// GP0 register bit/field definitions
-const uint8_t GP0_ABSTCLK_MUXSEL_BIT    = 0;
-const uint8_t GP0_SYNCCLK_MUXSEL_BIT    = 1;
-const uint8_t GP0_FLUSHMODE_INHIBIT_BIT = 2;
-const uint8_t GP0_FORCE_ALIGN_BIT       = 3;
-const uint8_t GP0_PERV_FENCE_BIT        = 63;
-
-// Clock Region Register clock start data patterns
-const uint64_t PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_NSL_ARY = 0x4FE0060000000000ull;
-const uint64_t PROC_START_CLOCKS_CHIPLETS_CLK_REGION_REG_START_ALL = 0x4FE00E0000000000ull;
-
-// Chiplet FIR register expected pattern
-const uint64_t PROC_START_CLOCKS_CHIPLETS_CHIPLET_FIR_REG_EXP = 0x0000000000000000ull;
-
-
-// Input clock region vector mask (for bit manipulation of clock regions)
-const uint64_t PROC_START_CLOCKS_CHIPLETS_CLOCK_REGION_MANIPULATION = 0xF0000FFFFFFFFFFFull;
-
-
-//------------------------------------------------------------------------------
-// Function prototype
-//------------------------------------------------------------------------------
-
-// function: FAPI proc_start_clocks_chiplets  HWP entry point
-//           start clocks for X/A/PCIE chiplets
-// parameters: i_target => P8 chip target
-//             i_xbus   => start X chiplet clocks?
-//             i_abus   => start A chiplet clocks?
-//             i_pcie   => start PCIE chiplet clocks?
-// returns: FAPI_RC_SUCCESS if clock start sequence completes successfully
-//          else FAPI getscom/putscom return code for failing operation
-fapi::ReturnCode proc_start_clocks_chiplets(const fapi::Target& i_target,
-                                            bool i_xbus,
-                                            bool i_abus,
-                                            bool i_pcie);
-
-} // extern "C"
-
-#endif // _PROC_START_CLOCKS_CHIPLETS_H_
diff --git a/src/usr/hwpf/hwp/proc_hwreconfig/makefile b/src/usr/hwpf/hwp/proc_hwreconfig/makefile
deleted file mode 100644
index 65b6f1889..000000000
--- a/src/usr/hwpf/hwp/proc_hwreconfig/makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/proc_hwreconfig/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2012,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = proc_hwreconfig
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/bus_training
-
-##  NOTE: add the base istep dir here. 
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/proc_hwreconfig
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += proc_enable_reconfig.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/edi_ei_initialization/<HWP_dir>
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C
deleted file mode 100644
index 025373fb0..000000000
--- a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C
+++ /dev/null
@@ -1,394 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_enable_reconfig.C,v 1.15 2014/06/20 18:58:18 steffen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_enable_reconfig.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *!  Licensed material - Program property of IBM
-// *!  Refer to copyright instructions form no. G120-2083
-// *! Created on Thu Oct 31 2013 at 10:28:49
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_enable_reconfig
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  :  Jacob Sloat   Email: jdsloat@us.ibm.com
-// *! BACKUP NAME :                 Email: ______@us.ibm.com
-
-// *! ADDITIONAL COMMENTS :
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.12  | jdsloat  |14-MAY-14| Fixed target name l_target_pu_mcs to i_target_pu_mcs
-//   1.11  | jdsloat  |13-MAY-14| Removed unused attribute l_attr_feature_venice
-//   1.10  | jdsloat  |08-MAY-14| Changed  MC1_BUSCNTL_FIR_0x02011E00 to IOMC0_BUSCNTL_FIR_0x02011A00 chiplet address to cover MC0 for venice.
-///  1.9   | dcrowell |02-MAY-14| Corrected comment in previous commit
-//   1.8   | jdsloat  |02-MAY-14| Added initializing of MCS_MCFGPR_0x02011802 to all 0s according to SW259625 by Dan Crowell
-//   1.7   | jdsloat  |25-MAR-14| Added return rc to the end of the code
-//   1.6   | jdsloat  |14-MAR-14| Commented out INIT_STATE set at the end of procedure.  SW245901
-//   1.5   | bellows  |17-FEB-14| Deconfig a proc if error found - SW246059
-//   1.4   | bellows  |13-NOV-13| Fixed up rc_ecmd problems from review
-//   1.3   | bellows  |11-NOV-13| Firmware review updates
-//   1.2   | bellows  |08-NOV-13| Simpified + added attributes
-//   1.1   | bellows  |07-NOV-13| Created from proc_prep_for_reconfig.C
-#include <fapi.H>
-#include "proc_enable_reconfig.H"
-#include <p8_scom_addresses.H>
-#include <cen_scom_addresses.H>
-#include "gcr_funcs.H"
-
-extern "C" {
-
-	using namespace fapi;
-
-// For clearing the FIR mask , used by io run training
-// As per Irving , it should be ok to clear all FIRs here since we will scom init , also we dont touch mask values
-fapi::ReturnCode clear_fir_reg(const fapi::Target &i_target,fir_io_interface_t i_chip_interface){
-	ReturnCode rc;
-	ecmdDataBufferBase data(64);
-	FAPI_INF("Clear Fir Reg:In the Clear FIR RW register function on %s", i_target.toEcmdString());
-	rc = fapiPutScom(i_target, fir_rw_reg_addr[i_chip_interface], data);
-	if (!rc.ok()){FAPI_ERR("Error writing FIR mask register (=%08X)!",fir_rw_reg_addr[i_chip_interface]);}
-	return(rc);
-}
-
-// Cleans up for Centaur Reconfig
-ReturnCode proc_enable_reconfig_cleanup(const Target &master_target){
-	ReturnCode rc;
-	io_interface_t master_interface;
-	master_interface                             = CP_IOMC0_P0; // base scom for MC bus
-	uint32_t master_group                        = 3;  // Design requires us to do this as per scom map and layout
-	uint32_t rc_ecmd                             = 0;
-	ecmdDataBufferBase   set_bits(16);
-	ecmdDataBufferBase clear_bits(16);
-	ecmdDataBufferBase mask_buffer_64(64);
-	ecmdDataBufferBase data_buffer_64(64);
-	ecmdDataBufferBase rx_set_bits(16);
-	ecmdDataBufferBase tx_set_bits(16);
-	bool memory_attached                         = false;
-	bool reset_required                          = false;
-	uint8_t l_attr_mss_init_state                = 0x0;
-	uint8_t l_attr_proc_ec_mss_reconfig_possible = 0x0;
-	uint8_t mcs_unit_id                          = 0x0;
-	uint8_t mcs_unit_lower_limit                 = 0;
-	uint8_t mcs_unit_upper_limit                 = 3;
-	io_interface_t slave_interface               = CEN_DMI; // Centaur scom base
-	uint32_t slave_group                         = 0x0;
-	// vector to hold MCS chiplet targets
-	std::vector<fapi::Target> mcs_chiplets;
-	fapi::Target master_parent_target;
-	fapi::Target attached_cen_target;
-
-	// Verify MCS Chiplet Type
-	if(master_target.getType() != fapi::TARGET_TYPE_MCS_CHIPLET){
-		const Target &MASTER_TARGET = master_target;
-		FAPI_ERR("Invalid io_cleanup HWP invocation . Pair of targets dont belong to DMI bus instances");
-		FAPI_SET_HWP_ERROR(rc, PROC_ENABLE_RECONFIG_CLEANUP_INVALID_MCS_RC);
-		return(rc);
-	}
-
-	// Find DMI0 or DMI1 controller limits based on passed in target.
-	rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &master_target, mcs_unit_id);   // read chip unit number
-	if(rc){return rc;}
-	if(mcs_unit_id == 0){        // DMI0, not on Tuleta, on Brazos
-		mcs_unit_lower_limit = 0;
-		mcs_unit_upper_limit = 3;
-	}else if(mcs_unit_id == 4){  // DMI1, on Tuleta and Brazos
-		mcs_unit_lower_limit = 4;
-		mcs_unit_upper_limit = 7;
-	}else{
-		return rc;
-	}
-
-	// Get Master Parent Target
-	rc = fapiGetParentChip(master_target, master_parent_target); if(rc){return rc;}
-	// Get mcs_chiplets list on processor
-	rc = fapiGetChildChiplets(master_parent_target,fapi::TARGET_TYPE_MCS_CHIPLET,mcs_chiplets, fapi::TARGET_STATE_PRESENT); if(rc){return rc;}
-
-	// Loop over all present MCS chiplets in the controller, to see if a reset is required
-	for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){
-		rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id);   // read chip unit number
-		if(rc){return rc;}
-		if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){    //To limit these actions to a single DMI controller
-			rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT);
-			if(!rc){     // An error from this means that there is no centaur attached.
-				rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state);  if(rc) return rc;
-				if(l_attr_mss_init_state != ENUM_ATTR_MSS_INIT_STATE_COLD){
-					reset_required = true;
-					break;
-				}
-			}else{
-				rc = FAPI_RC_SUCCESS;
-			}
-		}
-	}
-	if(!reset_required){
-		return(rc);
-	}
-
-	FAPI_INF("CleanUp: Global Reset Required");
-
-	// Get l_attr_proc_ec_mss_reconfig_possible, an attribute that states whether the part is DD1(0) or DD2(1)
-	rc = FAPI_ATTR_GET(ATTR_PROC_EC_MSS_RECONFIG_POSSIBLE, &master_parent_target, l_attr_proc_ec_mss_reconfig_possible); if(rc){return rc;}
-	if(!l_attr_proc_ec_mss_reconfig_possible){
-		FAPI_ERR("This processor cannot go through a reconfig loop. Please upgrade to > DD1\n");
-		const fapi::Target & PROC =  master_parent_target;
-		FAPI_SET_HWP_ERROR(rc, RC_PROC_ENABLE_RECONFIG_CLEANUP_UNSUPPORTED);
-		return rc;
-	}
-
-	// Loop over all present MCS chiplets in the controller
-	// Turn off FIR propagator, Mask FIRs, and force channel fail
-	for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){
-		rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id);   // read chip unit number
-		if(rc){return rc;}
-		if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){    //To limit these actions to a single DMI controller
-			memory_attached = true;
-			rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT);
-			if(rc){    // An error from this means that there is no centaur attached.
-				memory_attached = false;
-			}else{
-				rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state);  if(rc) return rc;
-			}
-			// turn off the FIR propagator
-			rc_ecmd = data_buffer_64.setBit(42);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = mask_buffer_64.setBit(42);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc = fapiPutScomUnderMask(*i, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64);  if(rc) return rc;
-
-			// Mask firs in the MCS, We do not mask firs on Centaur as they should not matter
-			rc_ecmd = data_buffer_64.setBit(0,64);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc = fapiPutScom(*i, MCS_MCIFIRMASK_0x02011843, data_buffer_64); if(rc) return rc;
-
-			// Force a channel fail on mcs and on Centaur if possible
-			// ***
-			// *** Causes too many bus errors on Centaur side.  This is okay as long as the function makes it to clearing the firs after reset.
-			// *** If GCR hang after reset happens, the function will exit early before clearing firs and cause too many bus errors
-			// *** GCR hang is fixed by doing global reset! Since global reset also does a GCR reset.
-			rc_ecmd = data_buffer_64.clearBit(0,64);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = data_buffer_64.setBit(0);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = mask_buffer_64.clearBit(0,64);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = mask_buffer_64.setBit(0);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc = fapiPutScomUnderMask(master_target, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64); if(rc) return rc;
-			if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){
-				rc_ecmd = data_buffer_64.clearBit(0,64);
-				if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-				rc_ecmd = data_buffer_64.setBit(0);
-				if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-				rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64);
-				if(rc) return rc;
-			}
-
-			// Set fence bits on mcs and on Centaur if possible
-			rc_ecmd = set_bits.setBit(0);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc = GCR_write(*i, master_interface,  rx_fence_pg, master_group, 0, set_bits, set_bits, 1, 1);
-			if(rc) return rc;
-			if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){
-				rc=GCR_write(attached_cen_target, slave_interface, rx_fence_pg, slave_group, 0, set_bits, set_bits, 1, 1);
-				if(rc) return rc;
-			}
-		}
-	}
-
-	/// reset start
-	// pu
-	rc = fapiGetScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data_buffer_64);
-	if (!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on master side(%08X)!",scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); return rc;}
-	rc_ecmd = data_buffer_64.setBit(2,6);  // Scom_mode_pb ,ioreset starts at bit 2, will reset every mcs on the memory controller
-	if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);}
-	rc = fapiPutScom(master_target, scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0], data_buffer_64);
-	if (!rc.ok()){FAPI_ERR("Error Writing SCOM mode PB register for ioreset_hard_bus0 on master side(%08X)!",scom_mode_pb_reg_addr[FIR_CP_IOMC0_P0]); return rc;}
-
-	// cen
-	for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){
-		rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id);   // read chip unit number
-		if (!rc.ok()){FAPI_ERR("Error retreiving MCS chiplet number, while resetting Centaurs.");return rc;}
-		if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){    //To limit these actions to a single DMI controller
-			rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT);
-			if(!rc){   // An error from this means that there is no centaur attached.
-				rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state);  if(rc) return rc;
-				if((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE) ){
-					rc_ecmd = data_buffer_64.flushTo0();
-					if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);}
-					rc = fapiGetScom(attached_cen_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data_buffer_64);
-					if(!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",scom_mode_pb_reg_addr[FIR_CEN_DMI]); return rc;}
-					rc_ecmd = data_buffer_64.setBit(2,1);  // Scom_mode_pb ,ioreset starts at bit 2
-					if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);}
-					rc = fapiPutScom(attached_cen_target, scom_mode_pb_reg_addr[FIR_CEN_DMI], data_buffer_64);
-					if(!rc.ok()){FAPI_ERR("Error Reading SCOM mode PB register for ioreset_hard_bus0 on Slave side(=%08X)!",scom_mode_pb_reg_addr[FIR_CEN_DMI]); return rc;}
-				}
-			}
-		}
-	}
-	FAPI_INF("CleanUp: Global Reset Done");
-	/// reset end
-
-	// Set Bus IDs, Clear FIRs, Turn on FIR Propagator
-	for (std::vector<fapi::Target>::iterator i = mcs_chiplets.begin(); i != mcs_chiplets.end(); i++){
-		rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &(*i), mcs_unit_id);   // read chip unit number
-		if (!rc.ok()){FAPI_ERR("Error retreiving MCS chiplet number, while setting bus id.");return rc;}
-		if((mcs_unit_lower_limit <= mcs_unit_id) && (mcs_unit_id <= mcs_unit_upper_limit)){    //To limit these actions to a single DMI controller
-			// Set Bus IDs -- Must rewrite bus ids after reset since reset sets all bus ids to 0 and there would be contention on the GCR ring
-			clear_bits.flushTo0();
-			uint32_t rxbits = 0;
-			uint32_t txbits = 0;
-			// Tuleta has MCS4-7 corresponding to port DMI1
-			// Brazos has MCS0-7 corresponding to port DMI0 and DMI1
-			if(mcs_unit_id == 0){
-				rxbits = 0x0000;    //bus_id: 0 group_id: 0
-				txbits = 0x0100;    //bus_id: 0 group_id: 32
-			}else if(mcs_unit_id == 1){
-				rxbits = 0x0400;    //bus_id: 1 group_id: 0
-				txbits = 0x0500;    //bus_id: 1 group_id: 32
-			}else if(mcs_unit_id == 2){
-				rxbits = 0x0800;    //bus_id: 2 group_id: 0
-				txbits = 0x0900;    //bus_id: 2 group_id: 32
-			}else if(mcs_unit_id == 3){
-				rxbits = 0x0C00;    //bus_id: 3 group_id: 0
-				txbits = 0x0D00;    //bus_id: 3 group_id: 32
-			}else if(mcs_unit_id == 4){
-				rxbits = 0x0000;    //bus_id: 0 group_id: 0
-				txbits = 0x0100;    //bus_id: 0 group_id: 32
-			}else if(mcs_unit_id == 5){
-				rxbits = 0x0400;    //bus_id: 1 group_id: 0
-				txbits = 0x0500;    //bus_id: 1 group_id: 32
-			}else if(mcs_unit_id == 6){
-				rxbits = 0x0800;    //bus_id: 2 group_id: 0
-				txbits = 0x0900;    //bus_id: 2 group_id: 32
-			}else if(mcs_unit_id == 7){
-				rxbits = 0x0C00;    //bus_id: 3 group_id: 0
-				txbits = 0x0D00;    //bus_id: 3 group_id: 32
-			}else{      //If chip_unit is unkown, set return error
-				FAPI_ERR("Invalid io_cleanup HWP. MCS chiplet number is unknown while setting the bus id.");
-				const fapi::Target & TARGET = *i;
-				FAPI_SET_HWP_ERROR(rc, PROC_ENABLE_RECONFIG_CLEANUP_POST_RESET_MCS_UNIT_ID_FAIL);
-				return rc;
-			}
-			rc_ecmd |= rx_set_bits.insertFromRight(rxbits, 0, 16);
-			rc_ecmd |= tx_set_bits.insertFromRight(txbits, 0, 16);
-			if(rc_ecmd){rc.setEcmdError(rc_ecmd);return(rc);}
-			// We do not need to rewrite bus ids for Centaur.
-			// Write RX bus id on MCS
-			rc = GCR_write(*i, master_interface, rx_id1_pg, master_group, 0, rx_set_bits, clear_bits,1,1);
-			if(rc){
-				FAPI_INF("io_cleanup rx putscom fail");
-				return(rc);
-			}
-			// Write TX bus id on MCS
-			rc = GCR_write(*i, master_interface, tx_id1_pg, master_group, 0, tx_set_bits, clear_bits,1,1);
-			if(rc){
-				FAPI_INF("in_cleanup tx putscom fail");
-				return(rc);
-			}
-			memory_attached = true;
-			rc = fapiGetOtherSideOfMemChannel( *i, attached_cen_target, fapi::TARGET_STATE_PRESENT);
-			if(rc){     // An error from this means that there is no centaur attached.
-				memory_attached = false;
-			}else{
-				rc = FAPI_ATTR_GET(ATTR_MSS_INIT_STATE, &attached_cen_target, l_attr_mss_init_state);  if(rc) return rc;
-			}
-			// Clear FIR on MCS and CEN (DMI FIR)
-			if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){
-				rc = clear_fir_reg(attached_cen_target,FIR_CEN_DMI);
-				if(rc){return(rc);}
-			}
-			rc = clear_fir_reg(*i,FIR_CP_IOMC0_P0);
-			if(rc){return(rc);}
-			rc_ecmd = data_buffer_64.clearBit(0,64);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			// # cen mbi fir
-			if((memory_attached) && ((l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_CLOCKS_ON) || (l_attr_mss_init_state == ENUM_ATTR_MSS_INIT_STATE_DMI_ACTIVE)) ){
-				rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_FIR_0x02010800, data_buffer_64);
-				if(rc) return rc;
-				// # cen mbicrc syndromes
-				rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CRCSYN_0x0201080C, data_buffer_64);
-				if(rc) return rc;
-				// # cen mbicfg configuration register
-				rc = fapiPutScom(attached_cen_target, CENTAUR_MBI_CFG_0x0201080A, data_buffer_64);
-				if(rc) return rc;
-				// # cen dmi fir
-				rc = fapiPutScom(attached_cen_target, CENTAUR_CEN_DMIFIR_0x02010400, data_buffer_64);
-				if(rc) return rc;
-			}
-			rc = fapiPutScom(*i, MCS_MCIFIR_0x02011840, data_buffer_64);
-			if(rc) return rc;
-			// # pu mcicrcsyn
-			rc = fapiPutScom(*i, MCS_MCICRCSYN_0x0201184C, data_buffer_64);
-			if(rc) return rc;
-			// # pu mcicfg
-			rc = fapiPutScom(*i, MCS_MCICFG_0x0201184A, data_buffer_64);
-			if(rc) return rc;
-			// # dmi fir
-			rc = fapiPutScom(*i, IOMC0_BUSCNTL_FIR_0x02011A00, data_buffer_64);
-			if(rc) return rc;
-			//Turn off indication of valid MCS for OCC
-			rc = fapiPutScom(*i, MCS_MCFGPR_0x02011802, data_buffer_64);
-			if(rc) return rc;
-
-			// Turn on the FIR propagator so FIR bits shut down the DMI
-			rc_ecmd = data_buffer_64.clearBit(0,64);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = mask_buffer_64.clearBit(0,64);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = data_buffer_64.clearBit(42);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc_ecmd = mask_buffer_64.setBit(42);
-			if(rc_ecmd){ rc.setEcmdError(rc_ecmd); return(rc);}
-			rc = fapiPutScomUnderMask(*i, MCS_MCICFG_0x0201184A, data_buffer_64, mask_buffer_64);
-			if(rc) return rc;
-		}
-	}
-	FAPI_INF("CleanUp: Done");
-	return rc;
-}
-
-
-ReturnCode proc_enable_reconfig(fapi::Target & i_target_pu_mcs) {
-	ReturnCode rc;
-	uint8_t mcs_unit_id = 0x0;     // Valid values for DMI0 (0-3) and DMI1 (4-7)
-	rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target_pu_mcs, mcs_unit_id);   // read mcs unit id value
-	if(rc){return rc;}
-	if((mcs_unit_id == 0) || (mcs_unit_id == 4) ){     // calls proc_enable_reconfig_cleanup only if mcs unit id is 0 or 4 (beginning of each memory controller)
-		FAPI_INF("mcs %s : type %d\n", i_target_pu_mcs.toEcmdString(), i_target_pu_mcs.getType() );
-		rc = proc_enable_reconfig_cleanup(i_target_pu_mcs);
-		if(rc) return rc;
-	}
-	return rc;
-}
-
-} // extern C
-
diff --git a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H b/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H
deleted file mode 100644
index d3f288098..000000000
--- a/src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H
+++ /dev/null
@@ -1,83 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/proc_hwreconfig/proc_enable_reconfig/proc_enable_reconfig.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_enable_reconfig.H,v 1.6 2014/06/20 18:58:18 steffen Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_enable_reconfig.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *!  Licensed material - Program property of IBM
-// *!  Refer to copyright instructions form no. G120-2083
-// *! Created on Thu Oct 31 2013 at 15:39:28
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_enable_reconfig
-// *! DESCRIPTION : see additional comments below
-// *! OWNER NAME  :  Bellows Mark   Email: bellows@us.ibm.com
-// *! BACKUP NAME :                 Email: ______@us.ibm.com
-
-// *! ADDITIONAL COMMENTS :
-//
-//------------------------------------------------------------------------------
-// Don't forget to create CVS comments when you check in your changes!
-//------------------------------------------------------------------------------
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|  Author: |  Date:  | Comment:
-//---------|----------|---------|-----------------------------------------------
-//   1.3   | bellows  |11-NOV-13| Fixed obsolete comment from when it was part of proc_prep_for_reconfig
-//   1.2   | bellows  |08-NOV-13| Simplified
-//   1.1   | bellows  |07-NOV-13| Created from proc_prep_for_reconfig
-#ifndef __proc_enable_reconfig_H
-#define __proc_enable_reconfig_H
-
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-#include "io_clear_firs.H"
-
-  using namespace fapi;
-
-	CONST_UINT64_T( CENTAUR_MBI_CFG_0x0201080A                     , ULL(0x0201080A) );
-	CONST_UINT64_T( CENTAUR_MBI_FIR_0x02010800                     , ULL(0x02010800) );
-	CONST_UINT64_T( CENTAUR_MBI_CRCSYN_0x0201080C                  , ULL(0x0201080C) );
-	CONST_UINT64_T( CENTAUR_CEN_DMIFIR_0x02010400                  , ULL(0x02010400) );
-
-typedef fapi::ReturnCode (*proc_enable_reconfig_FP_t)(fapi::Target & i_target_pu_mcs);
-
-extern "C"
-{
-
-/**
- * @brief proc_enable_reconfig procedure. Reset memory controller to known state which includes masking/clearing FIRs, causing a channel fails, and global resetting the memory controller and gcr ring.
- *
- * @param[in]   fapi::Target i_target_mcs,  // an MCS with an attached centaur
- *
- * @return ReturnCode
- */
-
-  ReturnCode proc_enable_reconfig(fapi::Target & i_target_pu_mcs);
-
-} // extern "C"
-
-#endif
diff --git a/src/usr/hwpf/hwp/runtime/makefile b/src/usr/hwpf/hwp/runtime/makefile
deleted file mode 100644
index 750a00244..000000000
--- a/src/usr/hwpf/hwp/runtime/makefile
+++ /dev/null
@@ -1,32 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/runtime/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2011,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-HWPPATH = ../
-MODULE = hwp_rt
-HOSTBOOT_RUNTIME = 1
-
-VPATH += ../
-
-include ../hwp.mk
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C b/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C
deleted file mode 100644
index 2e87f36c4..000000000
--- a/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C
+++ /dev/null
@@ -1,379 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C $       */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_xip_customize.C,v 1.15 2014/09/12 21:29:23 mklight Exp $
-/*------------------------------------------------------------------------------*/
-/* *! TITLE : cen_xip_customize.C                                               */
-/* *! DESCRIPTION : Customizes Centaur images from a Centaur reference image.   */
-/* *! OWNER NAME : Michael Olsen                  cmolsen@us.ibm.com            */
-//
-/* *! EXTENDED DESCRIPTION :                                                    */
-//
-/* *! USAGE : 
-              To build (for Hostboot) -
-              buildfapiprcd   -c "sbe_xip_image.c,pore_inline_assembler.c,p8_ring_identification.c"   -C "p8_image_help.C,p8_image_help_base.C,p8_pore_table_gen_api_fixed.C,p8_scan_compression.C"   -e "../../xml/error_info/cen_xip_customize_errors.xml,../../xml/error_info/proc_sbe_decompress_scan_halt_codes.xml,../../../../../../hwpf/hwp/xml/error_info/mvpd_errors.xml"   cen_xip_customize.C                                               */
-//
-/* *! ASSUMPTIONS :                                                             */
-//
-/* *! COMMENTS :                                                                */
-//
-/*------------------------------------------------------------------------------*/
-#define __CEN_XIP_CUSTOMIZE_C
-#include <cen_xip_customize.H>
-#include <p8_delta_scan_rw.h>
-#include <p8_pore_table_gen_api.H>
-
-extern "C"  {
-
-using namespace fapi;
-
-
-const uint32_t FSI_GP4_DMI_REFCLOCK_TERM_START_BIT = 8;
-const uint32_t FSI_GP4_DMI_REFCLOCK_TERM_END_BIT = 9;
-
-const uint32_t FSI_GP4_DDR_REFCLOCK_TERM_START_BIT = 10;
-const uint32_t FSI_GP4_DDR_REFCLOCK_TERM_END_BIT = 11;
-
-
-//  Parameter list:
-//  const fapi::Target &i_target:  Processor chip target.
-//  void      *i_imageIn:      Ptr to input image.
-//  void      *i_imageOut:     Ptr to output img.
-//  uint32_t  io_sizeImageOut: In: Max size of img. Out: Final size.
-//  void      *i_buf1:         Temp buffer 1 for dexed RS4 ring. Caller allocs/frees.
-//  uint32_t  i_sizeBuf1:      Size of buf1.
-//  void      *i_buf2:         Temp buffer 2 for WF ring. Caller allocs/frees.
-//  uint32_t  i_sizeBuf22      Size of buf2.
-//
-ReturnCode cen_xip_customize(const fapi::Target &i_target,
-                             void            *i_imageIn,
-                             void            *i_imageOut,
-                             uint32_t        &io_sizeImageOut,
-                             void            *i_buf1,
-                             const uint32_t  i_sizeBuf1,
-                             void            *i_buf2,
-                             const uint32_t  i_sizeBuf2 )
-{
-  fapi::ReturnCode rc;
-  uint32_t  rcLoc=0;
-  uint32_t  sizeImage, sizeImageIn, sizeImageOutMax;
-
-  sizeImageOutMax = io_sizeImageOut;
-  
-  // ==========================================================================
-  // Check and copy input image.
-  // ==========================================================================
-  //
-  // First, check supplied size and validation of input image.
-  //
-  sbe_xip_image_size(i_imageIn, &sizeImageIn);
-  rcLoc = sbe_xip_validate(i_imageIn, sizeImageIn);
-  if (rcLoc)  {
-    FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_UNSPECIFIED_IMAGE_ERR);
-    return rc;
-  }
-  
-  // Second, copy input image to supplied output image location.
-  //    
-  memcpy( i_imageOut, i_imageIn, sizeImageIn);
-  sbe_xip_image_size(i_imageOut, &sizeImage);
-  rcLoc = sbe_xip_validate(i_imageOut, sizeImage);
-  if (rcLoc)  {
-    FAPI_ERR("xip_validate() failed w/rcLoc=%i",rcLoc);
-    uint32_t & RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_UNSPECIFIED_IMAGE_ERR);
-    return rc;
-  }
-  if (sizeImage!=sizeImageIn)  {
-    FAPI_ERR("Size obtained from image's header (=%i) differs from supplied size (=%i).",
-      sizeImage,sizeImageIn);
-    uint32_t & DATA_IMG_SIZE_INP = sizeImageIn;
-    uint32_t & DATA_IMG_SIZE = sizeImage;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_IMAGE_SIZE_MISMATCH);
-    return rc;
-  }
-  FAPI_DBG("Input image (w/location=0x%016llx) copied to output image and validated w/size=%i bytes and location=0x%016llx",
-    (uint64_t)i_imageIn, sizeImageIn, (uint64_t)i_imageOut);
-
-  // --------------------------------------------------------------------------
-  // CUSTOMIZE item:    Update PLL ring (tp_pll_bndy_ring_alt).
-  // Retrieval method:  Attribute.
-  // --------------------------------------------------------------------------
-  uint32_t  tmp32Const1, tmp32Const2;
-  uint8_t   attrRingFlush[MAX_CEN_PLL_RING_SIZE]={0};
-  uint8_t   attrRingData[MAX_CEN_PLL_RING_SIZE]={0};
-  uint8_t   attrChipletId=0xff;
-  uint32_t  attrScanSelect=0;
-  uint32_t  attrRingDataSize=0; // Ring bit size
-  uint32_t  sizeDeltaPllRingAlt=0;
-  uint8_t   *bufDeltaPllRingAlt;
-  uint64_t  scanMaxRotate=SCAN_ROTATE_DEFAULT;
-  uint32_t  *wfInline=NULL;
-  uint32_t  wfInlineLenInWords;
-  uint32_t  bufLC=0;
-
-  //
-  // Retrieve the raw PLL rings state from attributes.
-  //
-  FAPI_INF("PLL update: Retrieve the raw PLL ring state from attributes.");
-  // Get ring size.
-  rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH, &i_target, attrRingDataSize); // This better be in bits.
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH) returned error.");
-    return rc;
-  }
-  FAPI_DBG("PLL update: PLL ring length (bits) = %i",attrRingDataSize);
-  FAPI_DBG("PLL update: Size of buf1, i_sizeBuf1 (bytes) = %i",i_sizeBuf1);
-  if (attrRingDataSize>MAX_CEN_PLL_RING_SIZE*8 || attrRingDataSize>i_sizeBuf1*8)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_LENGTH) returned ring size =%i bits.\n",
-              attrRingDataSize);
-    FAPI_ERR("But that exceeds either:\n");
-    FAPI_ERR("  the max pll ring size =%i bits, or\n",MAX_CEN_PLL_RING_SIZE*8);
-    FAPI_ERR("  the size of the pre-allocated buf1 =%i bits.", i_sizeBuf1*8);
-    uint32_t &DATA_ATTRIBUTE_RING_SIZE=attrRingDataSize;
-    tmp32Const1=8*MAX_CEN_PLL_RING_SIZE;
-    tmp32Const2=8*(uint32_t)i_sizeBuf1;
-    uint32_t &DATA_MAX_PLL_RING_SIZE=tmp32Const1;
-    uint32_t &DATA_SIZE_OF_BUF1=tmp32Const2;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_PLL_RING_SIZE_TOO_LARGE);
-    return rc;
-  }
-  sizeDeltaPllRingAlt = attrRingDataSize; // We've already checked it'll fit into buf1.
-  // Get flush and alter (desired) ring state data.
-  rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_FLUSH, &i_target, attrRingFlush);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_FLUSH) returned error.");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_DATA, &i_target, attrRingData);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_DATA) returned error.");
-    return rc;
-  }
-  rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_SCAN_SELECT, &i_target, attrScanSelect);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_SCAN_SELECT) returned error.");
-    return rc;
-  }
-/*
-  rc = FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_CHIPLET_ID, &i_target, attrChipletId);
-  if (rc)  {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_TP_BNDY_PLL_CHIPLET_ID) returned error.");
-    return rc;
-  }
-*/
-
-  //
-  // Calculate the delta scan ring.
-  //
-  FAPI_INF("PLL update: Calculate the delta scan ring.");
-  bufDeltaPllRingAlt = (uint8_t*)i_buf1;
-  rcLoc = calc_ring_delta_state( (uint32_t*)attrRingFlush,
-                                  (uint32_t*)attrRingData,
-                                  (uint32_t*)bufDeltaPllRingAlt, // Pre-allocated buffer.
-                                  sizeDeltaPllRingAlt );
-  if (rcLoc)  {
-    FAPI_ERR("calc_ring_delta_state() returned error w/rcLoc=%i",rcLoc);
-    FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-    uint32_t &RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_IMGBUILD_ERROR);
-    return rc;
-  }
-
-  //
-	// Create wiggle-flip (WF) program.
-	//
-  //scanMaxRotate = SCAN_MAX_ROTATE; // Max out on rotate length. P8 PLL running.
-  scanMaxRotate = SCAN_ROTATE_DEFAULT; // Max out on rotate length. P8 PLL running.
-/*
-  rcLoc = sbe_xip_get_scalar( i_imageOut, SCAN_MAX_ROTATE_38XXX_NAME, &scanMaxRotate);
-	if (rcLoc)  {
-	  FAPI_ERR("Strange error from sbe_xip_get_scalar(SCAN_MAX_ROTATE_38XXX_NAME) w/rcLoc=%i; ",rcLoc);
-	  FAPI_ERR("Already retrieved SCAN_MAX_ROTATE_38XXX_NAME in slw_build() w/o trouble; ");
-	  uint32_t &RC_LOCAL=rcLoc;
-	  FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_UNSPECIFIED_IMAGE_ERR);
-	  return rc;
-	}
-	if (scanMaxRotate<0x20 || scanMaxRotate>SCAN_MAX_ROTATE)  {
-	  FAPI_INF("WARNING: Value of key word SCAN_MAX_ROTATE_38XXX_NAME=0x%llx is not permitted; ",scanMaxRotate);
-    scanMaxRotate = SCAN_ROTATE_DEFAULT;
-		FAPI_INF("scanMaxRotate set to 0x%llx; ", scanMaxRotate);
-		FAPI_INF("Continuing...; ");
-	}
-*/
-	wfInline = (uint32_t*)i_buf2;  // Use HB buf2 for wiggle-flip prg.
-	wfInlineLenInWords = i_sizeBuf2/4;
-	rcLoc = create_wiggle_flip_prg((uint32_t*)bufDeltaPllRingAlt,
-	                            sizeDeltaPllRingAlt,
-	                            attrScanSelect, //=0x00100008,  // addr=0x00030088 ?
-	                            attrChipletId, //=0xff,
-	                            &wfInline,
-	                            &wfInlineLenInWords, // Is 8-byte aligned on return.
-                              1,  // Always do flush optimization.
-	                            (uint32_t)scanMaxRotate,
-                              0,  // No need to use waits for Centaur.
-                              0); // Centaur doesn't support scan polling.
-	if (rcLoc)  {
-	  FAPI_ERR("create_wiggle_flip_prg() failed w/rcLoc=%i",rcLoc);
-	  uint32_t &RC_LOCAL=rcLoc;
-	  FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_IMGBUILD_ERROR);
-	  return rc;
-	}
-
-  //
-  // Populate ring header and put ring header and Wf ring into 
-  // proper spots in pre-allocated bufWfRingBlock buffer (HB buf1).
-  //
-  DeltaRingLayout *bufWfRingBlock;
-  uint64_t entryOffsetWfRingBlock;
-  uint32_t sizeWfRingBlock, sizeWfRingBlockMax;
-
-  bufWfRingBlock = (DeltaRingLayout*)i_buf1; // Reuse HB buf1 for WF ring block.
-  sizeWfRingBlockMax = i_sizeBuf1;
-  entryOffsetWfRingBlock      = calc_ring_layout_entry_offset( 1, 0);
-  bufWfRingBlock->entryOffset = myRev64(entryOffsetWfRingBlock);
-  bufWfRingBlock->backItemPtr	= 0; // Will be updated below, as we don't know yet.
-	sizeWfRingBlock     	      =	entryOffsetWfRingBlock +  // Must be 8-byte aligned.
-  												      wfInlineLenInWords*4;     // Must be 8-byte aligned.
-	// Quick check to see if final ring block size will fit in HB buffer.
-	if (sizeWfRingBlock>sizeWfRingBlockMax)  {
-    FAPI_ERR("WF PLL _alt ring block size (=%i) exceeds pre-allocated buf1 size (=%i).",
-      sizeWfRingBlock, sizeWfRingBlockMax);
-    uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeWfRingBlock;
-    uint32_t &DATA_SIZE_OF_BUF1=sizeWfRingBlock;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_PLL_RING_BLOCK_TOO_LARGE);
-    return rc;
-	}
-	bufWfRingBlock->sizeOfThis  = myRev32(sizeWfRingBlock);
-	bufWfRingBlock->sizeOfMeta	=	0;
-	bufLC = (uint32_t)entryOffsetWfRingBlock;
-	// Copy over meta data which is zero, so nothing to do in this case!
-	// Copy over WF ring prg which is already 8-byte aligned.
-	memcpy( (uint8_t*)bufWfRingBlock+bufLC, wfInline, (size_t)wfInlineLenInWords*4);
-
-  // Now, some post-sanity checks on alignments.
-	if ( entryOffsetWfRingBlock%8 || 
-	     sizeWfRingBlock%8)  {
-		FAPI_ERR("Member(s) of WF ring block are not 8-byte aligned:");
-    FAPI_ERR("  Entry offset            = %i", (uint32_t)entryOffsetWfRingBlock);
-		FAPI_ERR("  Size of ring block      = %i", sizeWfRingBlock);
-    tmp32Const1=(uint32_t)entryOffsetWfRingBlock;
-    uint32_t &DATA_RING_BLOCK_ENTRYOFFSET=tmp32Const1;
-    uint32_t &DATA_RING_BLOCK_SIZEOFTHIS=sizeWfRingBlock;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_RING_BLOCK_ALIGN_ERROR);
-    return rc;
-	}
-
-  //
-  // Append PLL _alt ring to image.
-  //
-  FAPI_INF("PLL update: Appending WF PLL ring block to .rings section.");
-  rcLoc = write_ring_block_to_image( i_imageOut,
-                                     TP_PLL_BNDY_RING_ALT_TOC_NAME,
-                                     bufWfRingBlock,
-                                     0,
-                                     0,
-                                     0,
-                                     sizeImageOutMax,
-                                     SBE_XIP_SECTION_RINGS,
-                                     i_buf2,      // Use buf2 as temp buf.
-                                     i_sizeBuf2 );
-  if (rcLoc)  {
-    FAPI_ERR("write_ring_block_to_image() failed w/rc=%i",rcLoc);
-    FAPI_ERR("Check p8_delta_scan_rw.h for meaning of IMGBUILD_xyz rc code.");
-    uint32_t &RC_LOCAL=rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_IMGBUILD_ERROR);
-    return rc;
-  }
-
-  // ==========================================================================
-  // CUSTOMIZE item:    Centaur reference clock termination
-  // Retrieval method:  Attribute.
-  // ==========================================================================
-
-  uint8_t attrDMIRefclockTerm;
-  uint8_t attrDDRRefclockTerm;
-  SbeXipItem xipTocItem;
-  void *xipTocItemPtr;
-  uint64_t *refclockTermPtr;
-  ecmdDataBufferBase refclockTerm(64);
-  SBE_XIP_ERROR_STRINGS(errorStrings);
-
-  rc = FAPI_ATTR_GET(ATTR_MEMB_DMI_REFCLOCK_RCVR_TERM, NULL, attrDMIRefclockTerm);
-  if (rc) {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_DMI_REFCLOCK_RCVR_TERM) returned error.\n");
-    return rc;
-  }
-
-  rc = FAPI_ATTR_GET(ATTR_MEMB_DDR_REFCLOCK_RCVR_TERM, NULL, attrDDRRefclockTerm);
-  if (rc) {
-    FAPI_ERR("FAPI_ATTR_GET(ATTR_MEMB_DDR_REFCLOCK_RCVR_TERM) returned error.\n");
-    return rc;
-  }
-
-  // form customization data
-  rcLoc |= refclockTerm.insertFromRight(attrDMIRefclockTerm,
-                                        FSI_GP4_DMI_REFCLOCK_TERM_START_BIT,
-                                        (FSI_GP4_DMI_REFCLOCK_TERM_END_BIT-
-                                         FSI_GP4_DMI_REFCLOCK_TERM_START_BIT+1));
-  rcLoc |= refclockTerm.insertFromRight(attrDDRRefclockTerm,
-                                        FSI_GP4_DDR_REFCLOCK_TERM_START_BIT,
-                                        (FSI_GP4_DDR_REFCLOCK_TERM_END_BIT-
-                                         FSI_GP4_DDR_REFCLOCK_TERM_START_BIT+1));
-
-  if (rcLoc) {
-    FAPI_ERR("Error 0x%x forming refclock termination data buffer", rcLoc);
-    rc.setEcmdError(rcLoc);
-    return rc;
-  }
-
-  // look up customization location
-  rcLoc = sbe_xip_find(i_imageOut, REFCLOCK_TERM_TOC_NAME, &xipTocItem);
-  if (rcLoc) {
-    FAPI_ERR("sbe_xip_find() failed w/rc=%i and %s", rcLoc, SBE_XIP_ERROR_STRING(errorStrings, rcLoc));
-    FAPI_ERR("Probable cause:");
-    FAPI_ERR("\tThe keyword (=%s) was not found.", REFCLOCK_TERM_TOC_NAME);
-    uint32_t & RC_LOCAL = rcLoc;
-    FAPI_SET_HWP_ERROR(rc, RC_CEN_XIPC_KEYWORD_NOT_FOUND_ERROR);
-    return rc;
-  }
-
-  sbe_xip_pore2host(i_imageOut, xipTocItem.iv_address, &xipTocItemPtr);
-  refclockTermPtr = (uint64_t*)xipTocItemPtr;
-  *(refclockTermPtr + 0) = myRev64(refclockTerm.getDoubleWord(0));
-
-  //
-  // Done
-  //  
-
-  sbe_xip_image_size( i_imageOut, &io_sizeImageOut);
-  
-  return rc;
-  
-}
-
-
-} // End of extern C
diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.H b/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.H
deleted file mode 100644
index 2cb218885..000000000
--- a/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.H
+++ /dev/null
@@ -1,64 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.H $       */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2013,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_xip_customize.H,v 1.1 2013/01/24 14:07:39 cmolsen Exp $
-
-#include <fapi.H>
-
-typedef fapi::ReturnCode (*cen_xip_customize_FP_t) (	const fapi::Target&, 
-																					    			void*,
-																										void*,
-																							    	uint32_t&,
-																										void*,
-																										const uint32_t,
-																										void*,
-																								    const uint32_t );
-
-extern "C"
-{
-
-//
-// Function declares.
-//
-
-	// Description: 
-	// FAPI HWP entry point for cen_xip_customize().
-	// cen_xip_customize() customizes the Centaur image.
-	//
-	// Parameters:  
-	// fapi::Target &i_target:        Processor chip target.
-  // void         *i_imageIn:       Ptr to input IPL or SLW image.
-  // void         *i_imageOut:      Ptr to output IPL img. (Ignored for SLW/RAM imgs.)
-  // uint32_t     &io_sizeImageOut: In: Max size of IPL/SRAM img. Out: Final size.
-  // void         *i_buf1:          Temp buffer1 for dexed RS4 ring. Caller allocs/frees.
-  // uint32_t     i_sizeBuf1:       Size of buf1.
-  // void         *i_buf2:          Temp buffer2 for WF ring. Caller allocs/frees.
-  // uint32_t     i_sizeBuf22       Size of buf2.
-	fapi::ReturnCode cen_xip_customize( const fapi::Target &i_target,
-                                     void  *i_imageIn,
-														         void  *i_imageOut,
-																		 uint32_t    &io_sizeImageOut,
-																		 void  *i_buf1,
-																		 const uint32_t    i_sizeBuf1,
-																		 void  *i_buf2,
-																		 const uint32_t    i_sizeBuf2 );
-}
diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/makefile b/src/usr/hwpf/hwp/sbe_centaur_init/makefile
deleted file mode 100644
index 3973e1e9b..000000000
--- a/src/usr/hwpf/hwp/sbe_centaur_init/makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/sbe_centaur_init/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2011,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = sbe_centaur_init
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-## pointer to fapiporeve files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/fapiporeve
-EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/model
-EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/porevesrc
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/sbe_centaur_init
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/mvpd_accessors
-
-
-OBJS += sbe_centaur_init.o
-OBJS += cen_xip_customize.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-## VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/sbe_centaur_init/????
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C b/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C
deleted file mode 100644
index 632ac48d2..000000000
--- a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C
+++ /dev/null
@@ -1,328 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.C $        */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file sbe_centaur_init.C
- *
- *  Support file for IStep:
- *      sbe_centaur_init
- *
- *
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-#include <trace/interface.H>
-#include <initservice/taskargs.H>
-#include <errl/errlentry.H>
-#include <initservice/isteps_trace.H>
-#include <targeting/common/commontargeting.H>
-#include <targeting/common/utilFilter.H>
-#include <fapi.H>
-#include <fapiPoreVeArg.H>
-#include <fapiTarget.H>
-#include <fapi.H>
-#include <fapiPlatHwpInvoker.H>
-#include <vfs/vfs.H>
-#include "sbe_centaur_init.H"
-#include <isteps/hwpisteperror.H>
-#include <errl/errludtarget.H>
-#include <sbe/sbeif.H>
-#include "cen_xip_customize.H"
-#include <util/align.H>
-
-extern fapi::ReturnCode fapiPoreVe(const fapi::Target i_target,
-           std::list<uint64_t> & io_sharedObjectArgs);
-
-const uint64_t REPAIR_LOADER_RETRY_CTR_MASK = 0x000007FC00000000ull;
-
-// Constants
-// Memory Relocation Register for Centaur SBE image
-const uint64_t CENTAUR_SBE_PNOR_MRR = 0;
-
-// Max SBE image buffer size
-const uint32_t MAX_SBE_IMG_SIZE = 48 * 1024;
-
-// Low MSS freq for 32x32 machines
-const uint32_t MSS_FREQ_32x32_CONFIG = 1066;
-
-// Low Nest Freq
-const uint32_t LOW_NEST_FREQ = 2000;
-
-namespace   SBE_CENTAUR_INIT
-{
-
-using   namespace   ISTEP;
-using   namespace   ISTEP_ERROR;
-using   namespace   ERRORLOG;
-using   namespace   TARGETING;
-using   namespace   fapi;
-using   namespace   vsbe;
-
-
-//
-//  Wrapper function to call step 10
-//
-void*    call_sbe_centaur_init( void *io_pArgs )
-{
-
-    TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-              "call_sbe_centaur_init entry");
-
-    // Get target list to pass in procedure
-    TARGETING::TargetHandleList l_membufTargetList;
-    getAllChips(l_membufTargetList, TYPE_MEMBUF);
-
-    // Get sys target to check capable nest frequencies
-    TARGETING::Target* l_sys = NULL;
-    targetService().getTopLevelTarget(l_sys);
-    assert(l_sys != NULL, "sbe_centaur_init: sys target is NULL");
-
-    size_t l_sbePnorSize = 0;
-    void* l_sbePnorAddr = NULL;
-    errlHndl_t  l_errl = NULL;
-    uint32_t l_booted_nest_freq = 0;
-    MRW_NEST_CAPABLE_FREQUENCIES_SYS l_mrw_nest_capable;
-
-    IStepError  l_StepError;
-
-    // Loop thru all Centaurs in list
-    for (TargetHandleList::const_iterator
-         l_membuf_iter = l_membufTargetList.begin();
-         l_membuf_iter != l_membufTargetList.end();
-         ++l_membuf_iter)
-    {
-
-        TARGETING::Target* l_membuf_target = *l_membuf_iter;
-        HwasState l_hwasState = l_membuf_target->getAttr<ATTR_HWAS_STATE>();
-
-        TARGETING::ATTR_MSS_INIT_STATE_type  l_attr_mss_init_state=
-                l_membuf_target->getAttr<TARGETING::ATTR_MSS_INIT_STATE>();
-
-        //run SBE init on functional OR previously functional centaurs
-        if ( l_hwasState.functional ||
-            (l_hwasState.present &&
-            (l_attr_mss_init_state != ENUM_ATTR_MSS_INIT_STATE_COLD)) )
-        {
-            l_membuf_target->setAttr<TARGETING::ATTR_MSS_INIT_STATE>(
-                                 ENUM_ATTR_MSS_INIT_STATE_COLD);
-        }
-        else
-        {
-            //go to the next membuf in the list because this present  membuf is
-            //not functional or has not gone through an IPL once
-            continue;
-        }
-        //find SBE image in PNOR
-        uint8_t cur_ec = (*l_membuf_iter)->getAttr<TARGETING::ATTR_EC>();
-
-
-        TRACDCOMP( ISTEPS_TRACE::g_trac_isteps_trace, INFO_MRK,
-                   "call_sbe_centaur_init() - Find SBE image in PNOR");
-
-        l_errl = SBE::findSBEInPnor(l_membuf_target,
-                                 l_sbePnorAddr,
-                                 l_sbePnorSize,
-                                 NULL);
-        if (l_errl)
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace, ERR_MRK,
-           "call_sbe_centaur_init() - Error getting image from PNOR. "
-           "Target 0x%.8X, EC=0x%.2X",
-           TARGETING::get_huid(l_membuf_target), cur_ec );
-
-            // capture the target data in the elog
-            ErrlUserDetailsTarget(l_membuf_target).addToLog( l_errl );
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_errl );
-
-            // Commit Error
-            errlCommit( l_errl, HWPF_COMP_ID );
-            continue;
-        }
-
-        char l_header[10];
-        memcpy (l_header, l_sbePnorAddr, 9);
-        l_header[9] = '\0';
-
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                     "call_sbe_centaur_init - Loading "
-                     "centaur sbe from pnor, Addr 0x%llX, Size %d, Header %s",
-                     l_sbePnorAddr, l_sbePnorSize, l_header);
-
-        // Create a FAPI Target
-        const fapi::Target l_fapiTarget( fapi::TARGET_TYPE_MEMBUF_CHIP,
-                     (const_cast<TARGETING::Target*>(l_membuf_target)));
-
-        // Expand buffer for new image size
-        const uint32_t l_customizedMaxSize = ALIGN_POW2(MAX_SBE_IMG_SIZE);
-        const uint32_t l_buf1Size = ALIGN_POW2(MAX_SBE_IMG_SIZE);
-        const uint32_t l_buf2Size = ALIGN_POW2(MAX_SBE_IMG_SIZE);
-
-        uint32_t l_customizedSize = l_customizedMaxSize;
-        char * l_pCustomizedImage = (char *)malloc(l_customizedMaxSize);
-        void * l_pBuf1 = malloc(l_buf1Size);
-        void * l_pBuf2 = malloc(l_buf2Size);
-
-        // Setup args
-        std::list<uint64_t> myArgs;
-
-        // Set FapiPoreVeOtherArg: run unlimited instructions
-        FapiPoreVeOtherArg *l_otherArg =
-                new FapiPoreVeOtherArg(vsbe::RUN_UNLIMITED, vsbe::PORE_SBE);
-        // Entry point
-        l_otherArg->iv_entryPoint = const_cast<char*>("pnor::_sbe_pnor_start");
-        l_otherArg->iv_mrr = CENTAUR_SBE_PNOR_MRR;
-        myArgs.push_back(reinterpret_cast<uint64_t>(l_otherArg));
-
-        // Set FapiPoreVeMemArg for pnor option, base address = 0
-        uint32_t base_addr = 0;
-        char* l_dataPnor = const_cast<char*>(l_pCustomizedImage);
-        FapiPoreVeMemArg* l_memArg = new FapiPoreVeMemArg(ARG_PNOR,
-                                               base_addr, l_customizedSize,
-                                               static_cast<void*>(l_dataPnor));
-        myArgs.push_back(reinterpret_cast<uint64_t>(l_memArg));
-
-        // Create state argument to dump out state for debugging purpose
-        FapiPoreVeStateArg *l_stateArg = new FapiPoreVeStateArg(NULL);
-        l_stateArg->iv_installState = false;
-        l_stateArg->iv_extractState = true;
-        myArgs.push_back(reinterpret_cast<uint64_t>(l_stateArg));
-
-        //  Put out info on target
-        TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-            "Running call_sbe_centaur_init on Centaur "
-            " target HUID %.8X", TARGETING::get_huid(l_membuf_target));
-
-        // XIP customize is going to look for a PLL ring with a "stub"
-        // mem freq -- so set to a default, then clear it (so as not
-        // to mess up MSS HWP later
-
-        // Grab capable frequencies
-        l_mrw_nest_capable =
-                   l_sys->getAttr<ATTR_MRW_NEST_CAPABLE_FREQUENCIES_SYS>();
-
-        // Get the nest freq we booted with
-        l_booted_nest_freq = l_sys->getAttr<TARGETING::ATTR_NEST_FREQ_MHZ>();
-
-        // If we are running nest at 2.0, and we support 2.0 and 2.4, we
-        // need to drop MSS freq to 1066
-        if ((l_mrw_nest_capable ==
-                   MRW_NEST_CAPABLE_FREQUENCIES_SYS_2000_MHZ_OR_2400_MHZ) &&
-            (l_booted_nest_freq == LOW_NEST_FREQ))
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                "Reducing MSS frequency in sbe_centaur_init to %d based on "
-                "nest frequency", MSS_FREQ_32x32_CONFIG);
-
-            l_membuf_target->setAttr
-                <TARGETING::ATTR_MSS_FREQ>(MSS_FREQ_32x32_CONFIG);
-        }
-        else //boot as normal
-        {
-            l_membuf_target->setAttr<TARGETING::ATTR_MSS_FREQ>(1600);
-        }
-
-        FAPI_INVOKE_HWP( l_errl, cen_xip_customize,
-                         l_fapiTarget, l_sbePnorAddr,
-                         l_pCustomizedImage, l_customizedSize,
-                         l_pBuf1, l_buf1Size,
-                         l_pBuf2, l_buf2Size );
-
-        l_membuf_target->setAttr<TARGETING::ATTR_MSS_FREQ>(0);
-
-        if (l_errl)
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-               "ERROR 0x%.8X call_sbe_centaur_init - Error returned from"
-               " cen_xip_customize, l_rc 0x%llX", l_errl->reasonCode());
-        }
-        else
-        {
-            // Run the engine
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "call_sbe_centaur_init - Start VSBE engine...");
-
-            FAPI_INVOKE_HWP(l_errl, fapiPoreVe, l_fapiTarget, myArgs);
-
-            if (l_errl)
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                   "ERROR 0x%.8X call_sbe_centaur_init - Error returned from"
-                   " VSBE engine on this Centaur, l_rc 0x%llX",
-                   l_errl->reasonCode());
-                l_errl->collectTrace(FAPI_IMP_TRACE_NAME, 1024);
-                l_errl->collectTrace("ISTEPS_TRACE", 512);
-            }
-       
-            // Remove 0x0104000A reading, per Joe, the IPL procedures are no
-            // longer writing information related to the repair loader into
-            // this register
-
-        }
-
-        // Freeing memory
-        delete l_otherArg;
-        delete l_memArg;
-        delete l_stateArg;
-        free( l_pCustomizedImage );
-        free( l_pBuf1 );
-        free( l_pBuf2 );
-
-        if (l_errl )
-        {
-            // capture the target data in the elog
-            ErrlUserDetailsTarget(l_membuf_target).addToLog( l_errl );
-
-            // Create IStep error log and cross reference error that occurred
-            l_StepError.addErrorDetails( l_errl );
-
-            // Commit Error
-            errlCommit( l_errl, HWPF_COMP_ID );
-        }
-        else
-        {
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                 "call_sbe_centaur_init - VSBE engine runs successfully "
-                 "on this Centaur");
-        }
-
-    }   // end for
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "call_sbe_centaur_init exit" );
-
-    return l_StepError.getErrorHandle();
-}
-
-};   // end namespace
-
diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.H b/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.H
deleted file mode 100644
index 80fec7084..000000000
--- a/src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.H
+++ /dev/null
@@ -1,82 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/sbe_centaur_init/sbe_centaur_init.H $        */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-#ifndef __SBE_CENTAUR_INIT_SBE_CENTAUR_INIT_H
-#define __SBE_CENTAUR_INIT_SBE_CENTAUR_INIT_H
-/**
- *  @file sbe_centaur_init.H
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *
- *  HWP_IGNORE_VERSION_CHECK
- */
-
-/*  @tag isteplist
- *  @docversion     v1.28 (12/03/12)
- *  @istepname      sbe_centaur_init
- *  @istepnum       10
- *  @istepdesc      Step 10 Hostboot SBE Centaur Init
- *
- *  @{
- *      @substepnum     1
- *      @substepname    host_prd_hwreconfig
- *      @substepdesc    : Hook for PRD to handle reconfig
- *      @param  target 
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    cen_sbe_tp_chiplet_init1
- *      @substepdesc    : Execute all steps in ISTEP 10
- *      @param  target 
- *          @target_sched   serial
- *  @}
-
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-
-namespace   SBE_CENTAUR_INIT
-{
-
-    /**
-     *  @brief   sbe_centaur_init
-     *
-     *           Execute alll steps in step 10
-     *
-     *  param[in,out] io_pArgs  -   (normally) a pointer to args,
-     *                              or NULL.
-     *  return  any errlors to istep
-     *
-     */
-    void*    call_sbe_centaur_init( void * io_pArgs );
-
-};   // end namespace
-
-#endif
diff --git a/src/usr/hwpf/hwp/secure_boot/makefile b/src/usr/hwpf/hwp/secure_boot/makefile
deleted file mode 100644
index f010e90c7..000000000
--- a/src/usr/hwpf/hwp/secure_boot/makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/secure_boot/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = secure_boot
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/secure_boot
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
-
-OBJS += proc_check_security.o
-OBJS += proc_stop_sbe_scan_service.o
-OBJS += proc_use_sbe_scan_service.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/secure_boot
-
-include ${ROOTPATH}/config.mk
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_check_security.C b/src/usr/hwpf/hwp/secure_boot/proc_check_security.C
deleted file mode 100644
index 9514ef4b7..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_check_security.C
+++ /dev/null
@@ -1,100 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_check_security.C $          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_check_security.C,v 1.2 2015/08/03 14:04:43 thi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_security.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_check_security.C
-// *! DESCRIPTION : Determine state of processor security controls
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_check_security.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// Security Switch register field/bit definitions
-const uint32_t OTPC_M_SECURITY_SWITCH_TRUSTED_BOOT_BIT = 1;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Determine state of processor security controls
-//
-// parameters: i_target => chip target
-//             o_secure => true if security enabled, else false
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_check_security(
-    const fapi::Target& i_target,
-    bool & o_secure)
-{
-    // return codes
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        ecmdDataBufferBase security_switch_data(64);
-        rc = fapiGetScom(i_target, OTPC_M_SECURITY_SWITCH_0x00010005, security_switch_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error reading Security Switch Register");
-            break;
-        }
-        o_secure = security_switch_data.isBitSet(OTPC_M_SECURITY_SWITCH_TRUSTED_BOOT_BIT);
-
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_check_security.H b/src/usr/hwpf/hwp/secure_boot/proc_check_security.H
deleted file mode 100644
index 8cad2b975..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_check_security.H
+++ /dev/null
@@ -1,79 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_check_security.H $          */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_check_security.H,v 1.1 2015/05/14 21:16:40 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_security.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_check_security.H
-// *! DESCRIPTION : Determine state of processor security controls
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_CHECK_SECURITY_H_
-#define _PROC_CHECK_SECURITY_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_check_security_FP_t)(const fapi::Target &, bool &);
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Determine state of processor security controls
-//
-// parameters: i_target => chip target
-//             o_secure => true if security enabled, else false
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_check_security(
-    const fapi::Target& i_target,
-    bool & o_secure);
-
-
-} // extern "C"
-
-#endif // _PROC_CHECK_SECURITY_H_
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_sbe_scan_service.H b/src/usr/hwpf/hwp/secure_boot/proc_sbe_scan_service.H
deleted file mode 100644
index cb5a88027..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_sbe_scan_service.H
+++ /dev/null
@@ -1,49 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_sbe_scan_service.H $        */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_scan_service.H,v 1.1 2015/05/14 22:23:55 jmcgill Exp $
-
-/// Substep numbers for the proc_sbe_scan_service procedure
-
-#ifndef __PROC_SBE_SCAN_SERVICE_H
-#define __PROC_SBE_SCAN_SERVICE_H
-
-#include "fapi_sbe_common.H"
-#include "sbe_vital.H"
-
-//NOTE: The following values must stay constant as HB looks for them
-CONST_UINT8_T(SUBSTEP_PROC_ENTRY,                   ULL(0x0));
-CONST_UINT8_T(SUBSTEP_SBE_READY,                    ULL(0x1));
-CONST_UINT8_T(SUBSTEP_DECODE_REQ,                   ULL(0x2));
-CONST_UINT8_T(SUBSTEP_SCAN_IP,                      ULL(0x3));
-CONST_UINT8_T(SUBSTEP_SCAN_PRE_BRANCH,              ULL(0x4));
-CONST_UINT8_T(SUBSTEP_SCAN_IN_BRANCH,               ULL(0x5));
-CONST_UINT8_T(SUBSTEP_SCAN_DONE,                    ULL(0x6));
-CONST_UINT8_T(SUBSTEP_SCAN_POST_BRANCH,             ULL(0x7));
-CONST_UINT8_T(SUBSTEP_RESCAN_IP,                    ULL(0x8));
-CONST_UINT8_T(SUBSTEP_RESCAN_CHECKWORD_ERR,         ULL(0xD));
-CONST_UINT8_T(SUBSTEP_ARG_ERR,                      ULL(0xE));
-CONST_UINT8_T(SUBSTEP_HALT_SUCCESS,                 ULL(0xF));
-
-#endif  // __PROC_SBE_SCAN_SERVICE_H
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.C b/src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.C
deleted file mode 100644
index bedad0b7e..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.C
+++ /dev/null
@@ -1,295 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.C $   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_stop_sbe_scan_service.C,v 1.2 2015/07/27 00:48:38 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_sbe_scan_service.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_stop_sbe_scan_service.C
-// *! DESCRIPTION : Stop SBE runtime scan service
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_stop_sbe_scan_service.H>
-#include <p8_scom_addresses.H>
-#include <p8_istep_num.H>
-#include <proc_sbe_scan_service.H>
-#include <proc_use_sbe_scan_service.H>
-#include <proc_extract_sbe_rc.H>
-#include <proc_reset_i2cm_bus_fence.H>
-#include <proc_sbe_utils.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// SBE progress constants
-const uint8_t  SBE_EXIT_SUCCESS_0xF = 0xF;
-
-// SBE polling constants
-const uint32_t SBE_HALT_POLL_MAX_LOOPS = 10;
-const uint32_t SBE_HALT_POLL_DELAY_HW = 2000000;
-const uint32_t SBE_HALT_POLL_DELAY_SIM = 10000000;
-
-// SBE Mailbox0 Register scan request format constants
-const uint32_t MBOX0_REQUEST_VALID_BIT = 0;
-const uint32_t MBOX0_HALT_PATTERN_START_BIT = 16;
-const uint32_t MBOX0_HALT_PATTERN_END_BIT = 31;
-const uint32_t MBOX0_HALT_PATTERN = 0xD05E;
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Stop SBE runtime scan service
-//
-// parameters: i_target => chip target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_stop_sbe_scan_service(
-    const fapi::Target& i_target,
-    const void* i_pSEEPROM)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    // track if procedure has cleared I2C master bus fence
-    bool i2cm_bus_fence_cleared = false;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // check SBE progress
-        bool sbe_running = true;
-        size_t loop_time = 0;
-        uint8_t halt_code = 0;
-        uint16_t istep_num = 0;
-        uint8_t substep_num = 0;
-        bool scan_service_loop_reached = false;
-
-        // retrieve status
-        rc = proc_sbe_utils_check_status(
-            i_target,
-            sbe_running,
-            halt_code,
-            istep_num,
-            substep_num);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from proc_check_sbe_state_check_status");
-            break;
-        }
-
-        // get HB->SBE request mailbox, check that it is clear
-        ecmdDataBufferBase mbox_data(64);
-        bool sbe_ready = false;
-        rc = fapiGetScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Scom error reading SBE MBOX0 Register");
-            break;
-        }
-        sbe_ready = (mbox_data.getDoubleWord(0) == 0);
-
-        scan_service_loop_reached =
-            sbe_running &&
-            sbe_ready &&
-            !halt_code &&
-            (istep_num == PROC_SBE_SCAN_SERVICE_ISTEP_NUM) &&
-            (substep_num == SUBSTEP_SBE_READY);
-
-        FAPI_INF("SBE is running [%d], loop time [%zd], scan service loop reached [%d]",
-                 sbe_running, loop_time, scan_service_loop_reached);
-
-        if (!sbe_running)
-        {
-            FAPI_INF("SBE is stopped, exiting!");
-            break;
-        }
-        else if (scan_service_loop_reached)
-        {
-            // format stop request
-            rc_ecmd |= mbox_data.setBit(MBOX0_REQUEST_VALID_BIT);
-            rc_ecmd |= mbox_data.insertFromRight(MBOX0_HALT_PATTERN,
-                                                 MBOX0_HALT_PATTERN_START_BIT,
-                                                 (MBOX0_HALT_PATTERN_END_BIT-
-                                                  MBOX0_HALT_PATTERN_START_BIT)+1);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("Error 0x%x setting up SBE MBOX0 data buffer.", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            // submit stop request to SBE
-            FAPI_DBG("Submitting stop request to SBE");
-            rc = fapiPutScom(i_target, MBOX_SCRATCH_REG0_0x00050038, mbox_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error writing SBE MBOX0 Register");
-                break;
-            }
-
-            // pause to allow request to be processed
-            uint32_t loop_num = 0;
-            while (sbe_running && (loop_num < SBE_HALT_POLL_MAX_LOOPS))
-            {
-                loop_num++;
-                rc = fapiDelay(SBE_HALT_POLL_DELAY_HW, SBE_HALT_POLL_DELAY_SIM);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from fapiDelay");
-                    break;
-                }
-
-                // retrieve status
-                rc = proc_sbe_utils_check_status(
-                    i_target,
-                    sbe_running,
-                    halt_code,
-                    istep_num,
-                    substep_num);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error from proc_check_sbe_state_check_status");
-                    break;
-                }
-            }
-            if (rc)
-            {
-                break;
-            }
-            if (sbe_running)
-            {
-                FAPI_ERR("SBE is STILL running!");
-                const fapi::Target & TARGET = i_target;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_SBE_SCAN_SERVICE_SBE_NOT_STOPPED);
-                break;
-            }
-
-            // before analysis proceeds, make sure that I2C master bus fence is cleared
-            FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_reset_i2cm_bus_fence");
-                break;
-            }
-            // mark that fence has been cleared
-            i2cm_bus_fence_cleared = true;
-
-            //  ensure correct halt code is captured
-            rc = proc_sbe_utils_check_status(
-                i_target,
-                sbe_running,
-                halt_code,
-                istep_num,
-                substep_num);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_check_sbe_state_check_status");
-                break;
-            }
-
-            // confirm that expected halt point was reached
-            if (halt_code != SBE_EXIT_SUCCESS_0xF)
-            {
-                FAPI_ERR("SBE halted with error 0x%X (istep 0x%03X, substep 0x%X)",
-                         halt_code, istep_num, substep_num);
-                // extract & return error code from analyzing SBE state
-                FAPI_EXEC_HWP(rc, proc_extract_sbe_rc, i_target, NULL, i_pSEEPROM, SBE);
-                break;
-            }
-
-            if ((istep_num != PROC_SBE_SCAN_SERVICE_ISTEP_NUM) ||
-                (substep_num != SUBSTEP_HALT_SUCCESS))
-            {
-                FAPI_ERR("Expected SBE istep 0x%03llX, substep 0x%X but found istep 0x%03X, substep 0x%X",
-                         PROC_SBE_SCAN_SERVICE_ISTEP_NUM, SUBSTEP_HALT_SUCCESS,
-                         istep_num, substep_num);
-                const fapi::Target & TARGET = i_target;
-                const uint32_t & ISTEP_NUM = istep_num;
-                const uint32_t & SUBSTEP_NUM = substep_num;
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_SBE_SCAN_SERVICE_SBE_BAD_HALT);
-                break;
-            }
-
-            // Reset the SBE so it can be used for MPIPL if needed
-            ecmdDataBufferBase sbe_reset_data(64);
-            rc = fapiPutScom(i_target, PORE_SBE_RESET_0x000E0002, sbe_reset_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Scom error resetting SBE\n");
-                break;
-            }
-        }
-        // error
-        else
-        {
-            FAPI_ERR("SBE did not reach acceptable final state!");
-            const fapi::Target & TARGET = i_target;
-            const bool & SBE_RUNNING = sbe_running;
-            const uint8_t & HALT_CODE = halt_code;
-            const uint16_t & ISTEP_NUM = istep_num;
-            const uint8_t & SUBSTEP_NUM = substep_num;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_STOP_SBE_SCAN_SERVICE_UNEXPECTED_FINAL_STATE);
-            break;
-        }
-
-    } while(0);
-
-    // if an error occurred prior to the I2C master bus fence
-    // being cleared, attempt to clear it prior to exit
-    if (!rc.ok() && !i2cm_bus_fence_cleared)
-    {
-        // discard rc, return that of original fail
-        fapi::ReturnCode rc_unused;
-        FAPI_EXEC_HWP(rc_unused, proc_reset_i2cm_bus_fence, i_target);
-    }
-
-    // mark function entry
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.H b/src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.H
deleted file mode 100644
index 4ee6d97f6..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.H
+++ /dev/null
@@ -1,79 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_stop_sbe_scan_service.H $   */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_stop_sbe_scan_service.H,v 1.1 2015/05/14 21:25:17 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_stop_sbe_scan_service.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_stop_sbe_scan_service.H
-// *! DESCRIPTION : Stop SBE runtime scan service
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_STOP_SBE_SCAN_SERVICE_H_
-#define _PROC_STOP_SBE_SCAN_SERVICE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_stop_sbe_scan_service_FP_t)(const fapi::Target &,
-                                                            const void *);
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Stop SBE runtime scan service
-//
-// parameters: i_target => chip target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_stop_sbe_scan_service(
-    const fapi::Target& i_target,
-    const void *);
-
-
-} // extern "C"
-
-#endif // _PROC_STOP_SBE_SCAN_SERVICE_H_
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.C b/src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.C
deleted file mode 100644
index b24bc416e..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.C
+++ /dev/null
@@ -1,148 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.C $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_use_sbe_scan_service.C,v 1.1 2015/05/14 21:49:17 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_use_sbe_scan_service.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_use_sbe_scan_service.C
-// *! DESCRIPTION : Shared routine used to determine use of SBE runtime scan
-// *!               service
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_use_sbe_scan_service.H>
-#include <proc_check_master_sbe_seeprom.H>
-#include <proc_check_security.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Use SBE runtime scan service?
-//
-// parameters: i_target => chip target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_use_sbe_scan_service(
-    const fapi::Target& i_target,
-    bool& o_use_sbe_scan_service)
-{
-    // return codes
-    fapi::ReturnCode rc;
-
-    // mark function entry
-    FAPI_DBG("Start");
-
-    do
-    {
-        // make determination of scan path to use
-        // use SBE scan service if:
-        //   processor chip target AND
-        //   slave chip AND
-        //   ((secure boot enabled OR ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE) AND !ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE)
-
-        // check for processor chip target
-        o_use_sbe_scan_service = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP);
-        // check for slave chip
-        if (o_use_sbe_scan_service)
-        {
-            bool is_master;
-            FAPI_EXEC_HWP(rc, proc_check_master_sbe_seeprom, i_target, is_master);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_check_master_sbe_seeprom");
-                break;
-            }
-            o_use_sbe_scan_service = !is_master;
-        }
-        // check for security state/attribute direction
-        if (o_use_sbe_scan_service)
-        {
-            bool is_secure;
-            FAPI_EXEC_HWP(rc, proc_check_security, i_target, is_secure);
-            if (!rc.ok())
-            {
-                FAPI_ERR("Error from proc_check_security");
-                break;
-            }
-            o_use_sbe_scan_service = is_secure;
-
-            // force use of SBE scan service by attribute
-            if (!o_use_sbe_scan_service)
-            {
-                fapi::ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE_Type force_use_sbe_attr;
-                rc = FAPI_ATTR_GET(ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE, NULL, force_use_sbe_attr);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error reading ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE");
-                    break;
-                }
-
-                o_use_sbe_scan_service = (force_use_sbe_attr == fapi::ENUM_ATTR_FORCE_USE_SBE_SLAVE_SCAN_SERVICE_TRUE);
-            }
-
-            // discontinue use of SBE scan service once trusted scan path is available
-            if (o_use_sbe_scan_service)
-            {
-                fapi::ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE_Type trusted_slave_scan_path_active;
-                rc = FAPI_ATTR_GET(ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE, NULL, trusted_slave_scan_path_active);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("Error reading ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE");
-                    break;
-                }
-
-                o_use_sbe_scan_service = (trusted_slave_scan_path_active == fapi::ENUM_ATTR_TRUSTED_SLAVE_SCAN_PATH_ACTIVE_FALSE);
-            }
-        }
-    } while(0);
-
-    // mark function entry
-    FAPI_DBG("End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.H b/src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.H
deleted file mode 100644
index 69532ee63..000000000
--- a/src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.H
+++ /dev/null
@@ -1,80 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/secure_boot/proc_use_sbe_scan_service.H $    */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2015                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_use_sbe_scan_service.H,v 1.1 2015/05/14 21:49:21 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_use_sbe_scan_service.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2015
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_use_sbe_scan_service.H
-// *! DESCRIPTION : Shared routine used to determine use of SBE runtime scan
-// *!               service
-// *!
-// *! OWNER NAME  : Joe McGill               Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_USE_SBE_SCAN_SERVICE_H_
-#define _PROC_USE_SBE_SCAN_SERVICE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_use_sbe_scan_service_FP_t)(const fapi::Target &,
-                                                           bool &);
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// function:
-//      Use SBE runtime scan service?
-//
-// parameters: i_target => chip target
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_use_sbe_scan_service(
-    const fapi::Target& i_target,
-    bool& o_use_sbe_scan_service);
-
-
-} // extern "C"
-
-#endif // _PROC_USE_SBE_SCAN_SERVICE_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/makefile b/src/usr/hwpf/hwp/slave_sbe/makefile
deleted file mode 100644
index c7543213d..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/makefile
+++ /dev/null
@@ -1,73 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/slave_sbe/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2015
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-ROOTPATH = ../../../../..
-
-MODULE = slave_sbe
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_getecid
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/proc_mailbox_utils
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/pstates/pstates
-EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/porevesrc
-EXTRAINCDIR += ${ROOTPATH}/src/usr/pore/poreve/model/
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/secure_boot
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/core_activate/proc_stop_deadman_timer
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += proc_extract_sbe_rc.o
-OBJS += proc_read_seeprom.o
-OBJS += proc_getecid.o
-OBJS += proc_spless_sbe_startWA.o
-OBJS += proc_reset_i2cm_bus_fence.o
-OBJS += proc_check_master_sbe_seeprom.o
-OBJS += proc_tp_collect_dbg_data.o
-OBJS += proc_extract_pore_engine_state.o
-OBJS += proc_extract_pore_base_ffdc.o
-OBJS += proc_extract_pore_halt_ffdc.o
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_getecid
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.C b/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.C
deleted file mode 100644
index c8c4f4e38..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.C
+++ /dev/null
@@ -1,129 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_check_master_sbe_seeprom.C,v 1.1 2013/09/23 22:04:00 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_master_sbe_seeprom.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_check_master_sbe_seeprom.C
-// *! DESCRIPTION : Determine if given chip is the drawer master (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill    Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_check_master_sbe_seeprom.H"
-#include "p8_scom_addresses.H"
-
-
-extern "C"
-{
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-fapi::ReturnCode proc_check_master_sbe_seeprom(
-    const fapi::Target & i_target,
-    bool & o_is_master)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    ecmdDataBufferBase data;
-
-    bool pri_master = false;
-    uint8_t chip_id;
-
-    FAPI_DBG("proc_check_master_sbe_seeprom: Start");
-
-    do
-    {
-        // read SBE vital to determine primary/secondary master bit state
-        rc = fapiGetScom(i_target,
-                         MBOX_SBEVITAL_0x0005001C,
-                         data);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_check_master_sbe_seeprom: Error from fapiGetScom (MBOX_SBEVITAL_0x005001C)");
-            break;
-        }
-
-        // extract primary/secondary master bit
-        pri_master = data.isBitClear(MBOX_SBEVITAL_SBE_SELECT_MODE_MASTER_BIT);
-
-        // read device ID register to determine chip position
-        rc = fapiGetScom(i_target,
-                         PCBMS_DEVICE_ID_0x000F000F,
-                         data);
-
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_check_master_sbe_seeprom: Error from fapiGetScom (PCBMS_DEVICE_ID_0x000F000F)");
-            break;
-        }
-
-        // extract socketID and chip position fields
-        rc_ecmd |= data.extractToRight(
-            &chip_id,
-            PCBMS_DEVICE_ID_CHIP_ID_START_BIT,
-            (PCBMS_DEVICE_ID_CHIP_ID_END_BIT-
-             PCBMS_DEVICE_ID_CHIP_ID_START_BIT)+1);
-
-        // check data buffer manipulation return code
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_check_master_sbe_seeprom: Error 0x%X extracting socket/chip position",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // compare SBE Vital/Device ID fields with expected values
-        // for master chip
-        if ((pri_master && (chip_id == PCBMS_DEVICE_ID_PRIMARY_MASTER)) ||
-            (!pri_master && (chip_id == PCBMS_DEVICE_ID_ALTERNATE_MASTER)))
-        {
-            o_is_master = true;
-        }
-        else
-        {
-            o_is_master = false;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_check_master_sbe_seeprom: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.H b/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.H
deleted file mode 100644
index e579b8005..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.H
+++ /dev/null
@@ -1,94 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_cen_ref_clk_enable/proc_check_master_sbe_seeprom.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_check_master_sbe_seeprom.H,v 1.1 2013/09/23 22:04:00 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_check_master_sbe_seeprom.H,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_check_master_sbe_seeprom.H
-// *! DESCRIPTION : Determine if given chip is the drawer master (FAPI)
-// *!
-// *! OWNER NAME  : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef PROC_CHECK_MASTER_SBE_SEEPROM_H_
-#define PROC_CHECK_MASTER_SBE_SEEPROM_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// SBE Vital register bit/field definitions
-const uint32_t MBOX_SBEVITAL_SBE_SELECT_MODE_MASTER_BIT = 10;
-
-// Device ID register bit/field definitions
-const uint32_t PCBMS_DEVICE_ID_CHIP_ID_START_BIT = 36;
-const uint32_t PCBMS_DEVICE_ID_CHIP_ID_END_BIT = 39;
-
-const uint32_t PCBMS_DEVICE_ID_PRIMARY_MASTER = 0x00;
-const uint32_t PCBMS_DEVICE_ID_ALTERNATE_MASTER = 0x02;
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_check_master_sbe_seeprom_FP_t)(const fapi::Target &,
-                                      bool &);
-
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-/**
- * @brief HWP which determines if a given chip is the drawer master
- *
- * @param[in]  i_target    Processor target
- * @param[out] o_is_master Master state
- *
- * @return ReturnCode
- */
-fapi::ReturnCode proc_check_master_sbe_seeprom(
-    const fapi::Target & i_target,
-    bool & o_is_master);
-
-
-} // extern "C"
-
-#endif // PROC_CHECK_MASTER_SBE_SEEPROM_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C
deleted file mode 100644
index 1f2a38ccf..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C
+++ /dev/null
@@ -1,166 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_pore_base_ffdc.C,v 1.4 2015/04/22 14:14:25 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_base_ffdc.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_pore_base_ffdc.C
-// *! DESCRIPTION : Log base FFDC for SBE/SLW errors
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Johannes Koesters       Email: koesters@de.ibm.com
-// *!
-// *! Overview:
-// *!   - Dump state of SBE/SLW engine
-// *!   - Extract additional FFDC based on engine type
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_extract_pore_base_ffdc.H>
-#include <proc_tp_collect_dbg_data.H>
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-/**
- * proc_extract_pore_engine_state - HWP entry point, log PORE engine state
- *
- * @param[in]   i_pore_state     - struct holding PORE state
- * @param[in]   i_pore_sbe_state - struct holding PORE SBE specific state
- * @param[out]  o_rc             - target return code for extra FFDC
- *
- * @retval      fapi::ReturnCode = SUCCESS
- */
-fapi::ReturnCode proc_extract_pore_base_ffdc(const por_base_state & i_pore_state,
-                                             const por_sbe_base_state & i_pore_sbe_state,
-                                             fapi::ReturnCode & o_rc)
-
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    FAPI_INF("proc_extract_pore_base_ffdc: Start");
-
-    do
-    {
-        // append to return code
-        const fapi::Target & CHIP = i_pore_state.target;
-        const por_engine_t & ENGINE = i_pore_state.engine;
-        const bool & VIRTUAL = i_pore_state.is_virtual;
-        const uint64_t & PORE_VITAL_REG = i_pore_state.vital_state.getDoubleWord(0);
-        const uint64_t & PORE_STATUS_REG = i_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET);
-        const uint64_t & PORE_CONTROL_REG = i_pore_state.engine_state.getDoubleWord(PORE_CONTROL_OFFSET);
-        const uint64_t & PORE_RESET_REG = i_pore_state.engine_state.getDoubleWord(PORE_RESET_OFFSET);
-        const uint64_t & PORE_ERR_MASK_REG = i_pore_state.engine_state.getDoubleWord(PORE_ERR_MASK_OFFSET);
-        const uint64_t & PORE_P0_REG = i_pore_state.engine_state.getDoubleWord(PORE_P0_OFFSET);
-        const uint64_t & PORE_P1_REG = i_pore_state.engine_state.getDoubleWord(PORE_P1_OFFSET);
-        const uint64_t & PORE_A0_REG = i_pore_state.engine_state.getDoubleWord(PORE_A0_OFFSET);
-        const uint64_t & PORE_A1_REG = i_pore_state.engine_state.getDoubleWord(PORE_A1_OFFSET);
-        const uint64_t & PORE_TBL_BASE_REG = i_pore_state.engine_state.getDoubleWord(PORE_TBL_BASE_OFFSET);
-        const uint64_t & PORE_EXE_TRIGGER_REG = i_pore_state.engine_state.getDoubleWord(PORE_EXE_TRIGGER_OFFSET);
-        const uint64_t & PORE_CTR_REG = i_pore_state.engine_state.getDoubleWord(PORE_CTR_OFFSET);
-        const uint64_t & PORE_D0_REG = i_pore_state.engine_state.getDoubleWord(PORE_D0_OFFSET);
-        const uint64_t & PORE_D1_REG = i_pore_state.engine_state.getDoubleWord(PORE_D1_OFFSET);
-        const uint64_t & PORE_IBUF0_REG = i_pore_state.engine_state.getDoubleWord(PORE_IBUF0_OFFSET);
-        const uint64_t & PORE_IBUF1_REG = i_pore_state.engine_state.getDoubleWord(PORE_IBUF1_OFFSET);
-        const uint64_t & PORE_DEBUG0_REG = i_pore_state.engine_state.getDoubleWord(PORE_DEBUG0_OFFSET);
-        const uint64_t & PORE_DEBUG1_REG = i_pore_state.engine_state.getDoubleWord(PORE_DEBUG1_OFFSET);
-        const uint64_t & PORE_STACK0_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK0_OFFSET);
-        const uint64_t & PORE_STACK1_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK1_OFFSET);
-        const uint64_t & PORE_STACK2_REG = i_pore_state.engine_state.getDoubleWord(PORE_STACK2_OFFSET);
-        const uint64_t & PORE_IDFLAGS_REG = i_pore_state.engine_state.getDoubleWord(PORE_IDFLAGS_OFFSET);
-        const uint64_t & PORE_SPRG0_REG = i_pore_state.engine_state.getDoubleWord(PORE_SPRG0_OFFSET);
-        const uint64_t & PORE_MRR_REG = i_pore_state.engine_state.getDoubleWord(PORE_MRR_OFFSET);
-        const uint64_t & PORE_I2CE0_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE0_OFFSET);
-        const uint64_t & PORE_I2CE1_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE1_OFFSET);
-        const uint64_t & PORE_I2CE2_REG = i_pore_state.engine_state.getDoubleWord(PORE_I2CE2_OFFSET);
-        const uint64_t & PORE_PC = i_pore_state.pc;
-        const uint64_t & PORE_RC = i_pore_state.rc;
-        FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_ENGINE_STATE);
-
-
-        //
-        // collect additional FFDC based on engine type
-        //
-
-        if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP)
-        {
-            if (i_pore_state.engine == SBE)
-            {
-                uint8_t is_mpipl;
-                rc = FAPI_ATTR_GET(ATTR_IS_MPIPL, NULL, is_mpipl);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_extract_pore_base_ffdc: Error reading ATTR_IS_MPIPL");
-                    break;
-                }
-
-                const uint64_t & PNOR_ECCB_STATUS = i_pore_sbe_state.pnor_eccb_status.getDoubleWord(0);
-                const uint64_t & SEEPROM_ECCB_STATUS = i_pore_sbe_state.i2cm_eccb_status.getDoubleWord(0);
-                const uint8_t & SOFT_ERROR_STATUS = i_pore_sbe_state.soft_err;
-                const bool & ATTN_REPORTED = i_pore_sbe_state.reported_attn;
-                if ((o_rc == fapi::RC_SBE_TRIGGER_WINKLE_HOSTBOOT_DID_NOT_RESPOND) ||
-                    (o_rc == fapi::RC_SBE_TRIGGER_WINKLE_EX_DID_NOT_ENTER_WINKLE) ||
-                    (o_rc == fapi::RC_SBE_TRIGGER_WINKLE_EX_WAKEUP_DID_NOT_HIT_GOTO) ||
-                    (o_rc == fapi::RC_SBE_TRIGGER_WINKLE_EX_WAKEUP_DID_NOT_FINISH) ||
-		    (is_mpipl))
-                {
-                    FAPI_ERR("proc_extract_pore_base_ffdc: Collecting base FFDC for SBE fail (exclude TP ring)...");
-                    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE_WO_TP_DATA);
-                }
-                else
-                {
-                    FAPI_ERR("proc_extract_pore_base_ffdc: Collecting base FFDC for SBE fail (include TP ring)...");
-                    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SBE_W_TP_DATA);
-                }
-            }
-            else
-            {
-                FAPI_ERR("proc_extract_pore_base_ffdc: Collecting base FFDC for SLW fail...");
-                FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_BASE_FFDC_SLW);
-            }
-        }
-    } while(0);
-
-    FAPI_INF("proc_extract_pore_base_ffdc: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H
deleted file mode 100644
index 10424d9f8..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H
+++ /dev/null
@@ -1,86 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_base_ffdc.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_pore_base_ffdc.H,v 1.1 2014/07/23 19:38:05 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_base_ffdc.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_pore_base_ffdc.C
-// *! DESCRIPTION : Log base FFDC for SBE/SLW errors
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Johannes Koesters       Email: koesters@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_EXTRACT_PORE_BASE_FFDC_H_
-#define _PROC_EXTRACT_PORE_BASE_FFDC_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <proc_extract_sbe_rc.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_extract_pore_base_ffdc_FP_t)(const por_base_state &,
-                                                             const por_sbe_base_state &,
-                                                             fapi::ReturnCode &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * proc_extract_pore_engine_state - HWP entry point, log PORE engine state
- *
- * @param[in]   i_pore_state     - struct holding PORE state
- * @param[in]   i_pore_sbe_state - struct holding PORE SBE specific state
- * @param[out]  o_rc             - target return code for extra FFDC
- *
- * @retval      fapi::ReturnCode = SUCCESS
- */
-fapi::ReturnCode proc_extract_pore_base_ffdc(const por_base_state & i_pore_state,
-                                             const por_sbe_base_state & i_pore_sbe_state,
-                                             fapi::ReturnCode & o_rc);
-
-
-
-} // extern "C"
-
-#endif // _PROC_EXTRACT_PORE_BASE_FFDC_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C
deleted file mode 100644
index 7ca0ad37d..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C
+++ /dev/null
@@ -1,558 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_pore_engine_state.C,v 1.3 2014/08/07 15:04:41 thi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_engine_state.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_pore_engine_state.C
-// *! DESCRIPTION : Extract PORE (SBE/SLW) engine state
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Johannes Koesters       Email: koesters@de.ibm.com
-// *!
-// *! Overview:
-// *!   - Dump state of SBE/SLW engine
-// *!
-//------------------------------------------------------------------------------
-
-
-#ifdef FAPIECMD
-  #if FAPIECMD == 1
-    #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 0
-  #else
-    #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 1
-  #endif
-#else
-  #ifdef __HOSTBOOT_MODULE
-    #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 1
-  #else
-    #define PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE 0
-  #endif
-#endif
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_extract_pore_engine_state.H>
-#include <p8_scom_addresses.H>
-#include <proc_extract_sbe_rc.H>
-
-#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
-  #include <poreve.H>
-#endif
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-const uint32_t SLW_VITAL_PIBMEM_OFFSET = 0x12;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-/**
- * proc_extract_pore_engine_state_sbe_ffdc - Extract SBE-specific engine state
- *
- * @param[in]   i_target         - target of chip with failed SBE
- * @param[out]  o_pore_sbe_state - PORE SBE-specific state/FFDC content
- *
- * @retval      fapi::ReturnCode = SUCCESS
- * @retval      fapi::ReturnCode = results of cfam/SCOM access
- */
-fapi::ReturnCode proc_extract_pore_engine_state_sbe_ffdc(
-    const fapi::Target & i_target,
-    por_sbe_base_state & o_pore_sbe_state)
-{
-    // return codes
-    fapi::ReturnCode rc;
-
-    FAPI_DBG("proc_extract_pore_engine_state_sbe_ffdc: Start");
-
-    do
-    {
-        // check cfam status register for any PIB errors
-        ecmdDataBufferBase cfam_status(32);
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_STATUS_0x00001007, cfam_status);
-        if (rc)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetCfamRegister (CFAM_FSI_STATUS_0x00001007)");
-            break;
-        }
-
-        // bit 30 indicates SBE reported attention
-        if (cfam_status.isBitSet(30))
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: SBE reported attention to CFAM Status register");
-            o_pore_sbe_state.reported_attn = true;
-        }
-
-        // check ECCB engines (I2C/LPC) for UE/CE conditions
-        // SLW does not use these engines to access main memory, so no need to check
-        rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, o_pore_sbe_state.i2cm_eccb_status);
-        if (rc)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetScom (PORE_ECCB_STATUS_REGISTER_READ_0x000C00002)");
-            break;
-        }
-
-        rc = fapiGetScom(i_target, LPC_STATUS_0x000B0002, o_pore_sbe_state.pnor_eccb_status);
-        if (rc)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_sbe_ffdc: Error from fapiGetScom (LPC_STATUS_0x000B0002)");
-            break;
-        }
-
-        // determine if either engine has reached threshold of > 128 CEs
-        if (o_pore_sbe_state.i2cm_eccb_status.isBitSet(57))
-        {
-            o_pore_sbe_state.soft_err = eSOFT_ERR_I2CM;
-        }
-
-        if (o_pore_sbe_state.pnor_eccb_status.isBitSet(57))
-        {
-            if (o_pore_sbe_state.soft_err == eSOFT_ERR_I2CM)
-            {
-                o_pore_sbe_state.soft_err = eSOFT_ERR_BOTH;
-            }
-            else
-            {
-                o_pore_sbe_state.soft_err = eSOFT_ERR_PNOR;
-            }
-        }
-    } while(0);
-
-    FAPI_DBG("proc_extract_pore_engine_state_sbe_ffdc: End");
-    return rc;
-}
-
-
-/**
- * proc_extract_pore_engine_state_hw - Extract PORE engine state from HW
- *
- * @param[in]   i_target       - target of chip with failed SBE/SLW engine
- * @param[in]   i_engine       - engine type (SBE/SLW)
- * @param[out]  o_vital_state  - data buffer to hold SBE/SLW vital state
- * @param[out]  o_engine_state - data buffer to hold engine FFDC state
- *
- * @retval      fapi::ReturnCode = SUCCESS
- * @retval      fapi::ReturnCode = results of cfam/SCOM access
- */
-fapi::ReturnCode proc_extract_pore_engine_state_hw(
-    const fapi::Target & i_target,
-    const por_engine_t i_engine,
-    ecmdDataBufferBase & o_vital_state,
-    ecmdDataBufferBase & o_engine_state)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-
-    FAPI_DBG("proc_extract_pore_engine_state_hw: Start");
-
-    do
-    {
-        // collect SBE/SLW vital register value
-        if (i_engine == SBE)
-        {
-            ecmdDataBufferBase cfam_vital_data(32);
-
-            // collect from SBE vital HW register
-            rc = fapiGetCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, cfam_vital_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetCfamRegister (CFAM_FSI_SBE_VITAL_0x0000281C)");
-                break;
-            }
-
-            rc_ecmd |= o_vital_state.setWord(0, cfam_vital_data.getWord(0));
-            rc_ecmd |= o_vital_state.setWord(1, 0x0);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_extract_pore_engine_state_hw: Error %x forming SBE Vital FFDC data buffers",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        else
-        {
-            // collect from PIBMEM (virtual SLW vital state)
-            rc = fapiGetScom(i_target,
-                             PIBMEM0_0x00080000 + SLW_VITAL_PIBMEM_OFFSET,
-                             o_vital_state);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetCfamRegister (CFAM_FSI_SBE_VITAL_0x0000281C)");
-                break;
-            }
-        }
-
-        // collect SBE/SLW engine state
-        for (uint8_t offset = PORE_STATUS_OFFSET;
-             offset < PORE_NUM_REGS;
-             offset++)
-        {
-            ecmdDataBufferBase reg(64);
-        
-            rc = fapiGetScom(i_target,
-                             (uint32_t) i_engine + offset,
-                             reg);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_pore_engine_state_hw: Error from fapiGetScom (0x%08X)",
-                         (uint32_t) i_engine + offset);
-                break;
-            }
-
-            rc_ecmd |= o_engine_state.setDoubleWord(offset, reg.getDoubleWord(0));
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_extract_pore_engine_state_hw: Error %x inserting engine FFDC data value (DW=%d)",
-                         rc_ecmd, offset);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-    } while(0);
-
-    FAPI_DBG("proc_extract_pore_engine_state_hw: End");
-    return rc;
-}
-
-
-/**
- * proc_extract_pore_engine_state_virtual - Extract PORE engine state from virtual engine
- *
- * @param[in]   i_target       - target of chip with failed SBE engine
- * @param[in]   i_poreve       - pointer to PoreVe object
- * @param[out]  o_vital_state  - data buffer to hold SBE vital state
- * @param[out]  o_engine_state - data buffer to hold engine FFDC state
- *
- * @retval      fapi::ReturnCode = SUCCESS
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR
- */
-#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
-fapi::ReturnCode proc_extract_pore_engine_state_virtual(
-    const fapi::Target & i_target,
-    vsbe::PoreVe * i_poreve,
-    ecmdDataBufferBase & o_vital_state,
-    ecmdDataBufferBase & o_engine_state)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-    vsbe::ModelError me;
-
-    FAPI_DBG("proc_extract_pore_engine_state_virtual: Start");
-
-    do
-    {
-        // extract SBE vital state
-        // - for processor chips, this should resolve to a getscom
-        // - for Centaur, the state should be extracted from the virtual model
-        uint64_t vital_data;
-        int pib_rc;
-        me = i_poreve->getscom(MBOX_SBEVITAL_0x0005001C, vital_data, pib_rc);
-        if (me != vsbe::ME_SUCCESS)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_virtual: Model error %x extracting SBE vital state",
-                     (int) me);
-            const fapi::Target & CHIP = i_target;
-            const uint32_t & MODEL_ERROR = (uint32_t) me;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR);
-            break;
-        }
-        else if (pib_rc)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_virtual: PIB error getting SBE vital state (error code %d)",
-                     pib_rc);
-            const fapi::Target & CHIP = i_target;
-            const int & PIB_ERROR = pib_rc;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR);
-            break;
-        }
-        rc_ecmd = o_vital_state.setDoubleWord(0, vital_data);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_virtual: Error %x inserting SBE vital FFDC data value",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // extract engine state from model
-        vsbe::PoreState ve_state;
-        me = i_poreve->iv_pore.extractState(ve_state);
-        if (me != vsbe::ME_SUCCESS)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_virtual: Model error %x extracting virtual engine state",
-                     (int) me);
-            const fapi::Target & CHIP = i_target;
-            const uint32_t & MODEL_ERROR = (uint32_t) me;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR);
-            break;
-        }
-
-        uint64_t status;
-        ve_state.get(vsbe::PORE_STATUS, status);
-        uint64_t control;
-        ve_state.get(vsbe::PORE_CONTROL, control);
-        uint64_t reset;
-        ve_state.get(vsbe::PORE_RESET, reset);
-        uint64_t table_base;
-        ve_state.get(vsbe::PORE_TABLE_BASE_ADDR, table_base);
-        uint64_t ibuf0, ibuf1;
-        ve_state.get(vsbe::PORE_IBUF_01, ibuf0);
-        ve_state.get(vsbe::PORE_IBUF_2, ibuf1);
-        uint64_t dbg0, dbg1;
-        ve_state.get(vsbe::PORE_DBG0, dbg0);
-        ve_state.get(vsbe::PORE_DBG1, dbg1);
-        uint64_t stack0, stack1, stack2;
-        ve_state.get(vsbe::PORE_PC_STACK0, stack0);
-        ve_state.get(vsbe::PORE_PC_STACK1, stack1);
-        ve_state.get(vsbe::PORE_PC_STACK2, stack2);
-        uint64_t mrr;
-        ve_state.get(vsbe::PORE_MEM_RELOC, mrr);
-        uint64_t i2c_e0, i2c_e1, i2c_e2;
-        ve_state.get(vsbe::PORE_I2C_E0_PARAM, i2c_e0);
-        ve_state.get(vsbe::PORE_I2C_E1_PARAM, i2c_e1);
-        ve_state.get(vsbe::PORE_I2C_E2_PARAM, i2c_e2);
-
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_STATUS_OFFSET, status);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_CONTROL_OFFSET, control);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_RESET_OFFSET, reset);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_ERR_MASK_OFFSET, i_poreve->iv_pore.emr.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_P0_OFFSET, (i_poreve->iv_pore.p0.read() << 32));
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_P1_OFFSET, (i_poreve->iv_pore.p1.read() << 32));
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_A0_OFFSET, i_poreve->iv_pore.a0.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_A1_OFFSET, i_poreve->iv_pore.a1.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_TBL_BASE_OFFSET, table_base);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_EXE_TRIGGER_OFFSET, i_poreve->iv_pore.etr.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_CTR_OFFSET, i_poreve->iv_pore.ctr.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_D0_OFFSET, i_poreve->iv_pore.d0.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_D1_OFFSET, i_poreve->iv_pore.d1.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_IBUF0_OFFSET, ibuf0);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_IBUF1_OFFSET, ibuf1);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_DEBUG0_OFFSET, dbg0);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_DEBUG1_OFFSET, dbg1);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK0_OFFSET, stack0);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK1_OFFSET, stack1);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_STACK2_OFFSET, stack2);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_IDFLAGS_OFFSET, i_poreve->iv_pore.ifr.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_SPRG0_OFFSET, i_poreve->iv_pore.sprg0.read());
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_MRR_OFFSET, mrr);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE0_OFFSET, i2c_e0);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE1_OFFSET, i2c_e1);
-        rc_ecmd |= o_engine_state.setDoubleWord(PORE_I2CE2_OFFSET, i2c_e2);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_pore_engine_state_virtual: Error %x inserting engine FFDC data value",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-    } while(0);
-
-    FAPI_DBG("proc_extract_pore_engine_state_virtual: End");
-    return rc;
-}
-#endif
-
-/**
- * proc_extract_pore_engine_state - HWP entry point, extract PORE engine state
- *
- * @param[in]   i_target         - chip target, used to collect engine state if
- *                                 i_poreve is NULL
- * @param[in]   i_poreve         - pointer to PoreVe object, used to collect engine
- *                                 state if non NULL
- * @param[in]   i_engine         - engine type to analyze (SBE/SLW)
- * @param[out]  o_pore_state     - PORE state/FFDC content
- * @param[out]  o_pore_sbe_state - PORE SBE-specific state/FFDC content (filled
- *                                 only if i_engine=SBE)
- *
- * @retval      fapi::ReturnCode = SUCCESS
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION
- */
-fapi::ReturnCode proc_extract_pore_engine_state(const fapi::Target & i_target,
-                                                void * i_poreve,
-                                                const por_engine_t i_engine,
-                                                por_base_state & o_pore_state,
-                                                por_sbe_base_state & o_pore_sbe_state)
-{
-    // return code
-    fapi::ReturnCode rc;
-
-    do
-    {
-        //
-        // check arguments
-        //
-
-        // virtual SBE for processor or Centaur OR
-        // real SBE/SLW for processor
-        bool is_virtual = (i_poreve != NULL);
-#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
-        bool is_virtual_supported = true;
-        vsbe::PoreVe * ve = reinterpret_cast<vsbe::PoreVe *>(i_poreve);
-#else
-        bool is_virtual_supported = false;
-#endif
-        bool is_processor = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP);
-        bool is_centaur = (i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP);
-        bool is_sbe = (i_engine == SBE);
-        bool is_slw = (i_engine == SLW);
-
-        o_pore_state.target = i_target;
-        o_pore_state.engine = i_engine;
-        o_pore_state.is_virtual = is_virtual;
-
-        if (!((is_virtual && is_virtual_supported && (is_processor || is_centaur) && is_sbe) ||
-              (!is_virtual && is_processor && (is_sbe || is_slw))))
-        {
-            FAPI_ERR("proc_extract_pore_engine_state: Unsupported invocation for target: %s, engine type: %s, virtual: %d",
-                     i_target.toEcmdString(), ((i_engine == SBE)?("SBE"):("SLW")), is_virtual);
-            const fapi::Target & CHIP = i_target;
-            const por_engine_t & ENGINE = i_engine;
-            const bool & VIRTUAL = is_virtual;
-            const bool & VIRTUAL_IS_SUPPORTED = is_virtual_supported;
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION);
-            break;
-        }
-
-
-        //
-        // extract engine state
-        //
-
-        FAPI_INF("proc_extract_pore_engine_state: Extracting PORE engine FFDC for target: %s, engine type: %s, virtual: %d",
-                 i_target.toEcmdString(), ((i_engine == SBE)?("SBE"):("SLW")), is_virtual);
-
-        // collect engine state from virtual PORE engine
-        if (is_virtual)
-        {
-#if PROC_EXTRACT_PORE_ENGINE_STATE_BUILD_POREVE == 1
-            rc = proc_extract_pore_engine_state_virtual(i_target,
-                                                        ve,
-                                                        o_pore_state.vital_state,
-                                                        o_pore_state.engine_state);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_virtual");
-                break;
-            }
-#endif
-        }
-        // HW
-        else
-        {
-            rc = proc_extract_pore_engine_state_hw(i_target,
-                                                   i_engine,
-                                                   o_pore_state.vital_state,
-                                                   o_pore_state.engine_state);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_hw");
-                break;
-            }
-        }
-
-        FAPI_INF("proc_extract_pore_engine_state: PORE_VITAL = 0x%016llX", o_pore_state.vital_state.getDoubleWord(0));
-        FAPI_INF("proc_extract_pore_engine_state: PORE_STATUS = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET));     
-        FAPI_INF("proc_extract_pore_engine_state: PORE_CONTROL = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_CONTROL_OFFSET));    
-        FAPI_INF("proc_extract_pore_engine_state: PORE_RESET = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_RESET_OFFSET));      
-        FAPI_INF("proc_extract_pore_engine_state: PORE_ERR_MASK = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_ERR_MASK_OFFSET));   
-        FAPI_INF("proc_extract_pore_engine_state: PORE_P0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_P0_OFFSET));         
-        FAPI_INF("proc_extract_pore_engine_state: PORE_P1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_P1_OFFSET));         
-        FAPI_INF("proc_extract_pore_engine_state: PORE_A0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_A0_OFFSET));         
-        FAPI_INF("proc_extract_pore_engine_state: PORE_A1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_A1_OFFSET));         
-        FAPI_INF("proc_extract_pore_engine_state: PORE_TBL_BASE = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_TBL_BASE_OFFSET));   
-        FAPI_INF("proc_extract_pore_engine_state: PORE_EXE_TRIGGER = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_EXE_TRIGGER_OFFSET));
-        FAPI_INF("proc_extract_pore_engine_state: PORE_CTR = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_CTR_OFFSET));        
-        FAPI_INF("proc_extract_pore_engine_state: PORE_D0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_D0_OFFSET));         
-        FAPI_INF("proc_extract_pore_engine_state: PORE_D1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_D1_OFFSET));         
-        FAPI_INF("proc_extract_pore_engine_state: PORE_IBUF0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IBUF0_OFFSET));      
-        FAPI_INF("proc_extract_pore_engine_state: PORE_IBUF1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IBUF1_OFFSET));      
-        FAPI_INF("proc_extract_pore_engine_state: PORE_DEBUG0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_DEBUG0_OFFSET));     
-        FAPI_INF("proc_extract_pore_engine_state: PORE_DEBUG1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_DEBUG1_OFFSET));     
-        FAPI_INF("proc_extract_pore_engine_state: PORE_STACK0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK0_OFFSET));     
-        FAPI_INF("proc_extract_pore_engine_state: PORE_STACK1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK1_OFFSET));     
-        FAPI_INF("proc_extract_pore_engine_state: PORE_STACK2 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_STACK2_OFFSET));     
-        FAPI_INF("proc_extract_pore_engine_state: PORE_IDFLAGS = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_IDFLAGS_OFFSET));    
-        FAPI_INF("proc_extract_pore_engine_state: PORE_SPRG0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_SPRG0_OFFSET));      
-        FAPI_INF("proc_extract_pore_engine_state: PORE_MRR = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_MRR_OFFSET));        
-        FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE0 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE0_OFFSET));      
-        FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE1 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE1_OFFSET));      
-        FAPI_INF("proc_extract_pore_engine_state: PORE_I2CE2 = 0x%016llX", o_pore_state.engine_state.getDoubleWord(PORE_I2CE2_OFFSET));      
-
-        o_pore_state.pc = (o_pore_state.engine_state.getDoubleWord(PORE_STATUS_OFFSET) & 0x0000FFFFFFFFFFFFULL);
-        FAPI_INF("proc_extract_pore_engine_state: PORE_PC = 0x%016llX", o_pore_state.pc);
-
-        //
-        // processor SBE specific state collection
-        //
-
-        if (is_processor && is_sbe)
-        {
-            rc = proc_extract_pore_engine_state_sbe_ffdc(i_target,
-                                                         o_pore_sbe_state);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_pore_engine_state: Error from proc_extract_pore_engine_state_sbe_ffdc");
-                break;
-            }
-
-            FAPI_INF("proc_extract_pore_engine_state: SBE SEEPROM ECCB = %016llX", o_pore_sbe_state.i2cm_eccb_status.getDoubleWord(0));
-            FAPI_INF("proc_extract_pore_engine_state: SBE PNOR ECCB = %016llX", o_pore_sbe_state.pnor_eccb_status.getDoubleWord(0));
-            FAPI_INF("proc_extract_pore_engine_state: SBE soft error = %d", o_pore_sbe_state.soft_err);
-            FAPI_INF("proc_extract_pore_engine_state: SBE attn = %d", o_pore_sbe_state.reported_attn);
-        }
-    } while(0);
-
-    FAPI_INF("proc_extract_pore_engine_state: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H
deleted file mode 100644
index 6a2b7fc42..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H
+++ /dev/null
@@ -1,97 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_engine_state.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_pore_engine_state.H,v 1.2 2014/07/24 03:16:22 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_engine_state.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_pore_engine_state.H
-// *! DESCRIPTION : Extract PORE (SBE/SLW) engine state
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Johannes Koesters       Email: koesters@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_EXTRACT_PORE_ENGINE_STATE_H_
-#define _PROC_EXTRACT_PORE_ENGINE_STATE_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <proc_extract_sbe_rc.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_extract_pore_engine_state_FP_t)(const fapi::Target &,
-                                                                void *,
-                                                                const por_engine_t,
-                                                                por_base_state &,
-                                                                por_sbe_base_state &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-
-/**
- * proc_extract_pore_engine_state - HWP entry point, extract PORE engine state
- *
- * @param[in]   i_target         - chip target, used to collect engine state if
- *                                 i_poreve is NULL
- * @param[in]   i_poreve         - pointer to PoreVe object, used to collect engine
- *                                 state if non NULL
- * @param[in]   i_engine         - engine type to analyze (SBE/SLW)
- * @param[out]  o_pore_state     - PORE state/FFDC content
- * @param[out]  o_pore_sbe_state - PORE SBE-specific state/FFDC content (filled
- *                                 only if i_engine=SBE)
- *
- * @retval      fapi::ReturnCode = SUCCESS
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_MODEL_ERROR
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_VSBE_PIB_ERROR
- * @retval      fapi::ReturnCode = RC_PROC_EXTRACT_PORE_ENGINE_STATE_UNSUPPORTED_INVOCATION
- */
-fapi::ReturnCode proc_extract_pore_engine_state(const fapi::Target & i_target,
-                                                void *,
-                                                const por_engine_t i_engine,
-                                                por_base_state & o_pore_state,
-                                                por_sbe_base_state & o_pore_sbe_state);
-
-
-} // extern "C"
-
-#endif // _PROC_EXTRACT_PORE_ENGINE_STATE_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C
deleted file mode 100644
index aaf28f372..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C
+++ /dev/null
@@ -1,550 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_pore_halt_ffdc.C,v 1.2 2014/08/07 13:32:17 thi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_halt_ffdc.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_pore_halt_ffdc.C
-// *! DESCRIPTION : Extract halt-fail related FFDC for selected SBE/SLW errors
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <p8_scom_addresses.H>
-#include <proc_extract_pore_halt_ffdc.H>
-
-
-// -----------------------------------------------------------------------------
-// Constant definitions
-// -----------------------------------------------------------------------------
-
-// X Clock Adjust Set register bit/field definitions
-const uint32_t X_CLK_ADJ_SET_REG_SYNC_BIT = 2;
-const uint32_t X_CLK_ADJ_SET_REG_RLM_SELECT_BIT = 5;
-const uint32_t X_CLK_ADJ_SET_REG_CMD_START_BIT = 6;
-const uint32_t X_CLK_ADJ_SET_REG_CMD_END_BIT = 9;
-const uint32_t X_CLK_ADJ_SET_REG_DATA_START_BIT = 21;
-const uint32_t X_CLK_ADJ_SET_REG_DATA_END_BIT = 28;
-
-const uint8_t X_CLK_ADJ_CMD_TYPE_READ = 0xE;
-
-
-const uint64_t scan_ffdc_addr_arr[] =
-{
-    GENERIC_CLK_SYNC_CONFIG_0x00030000,
-    GENERIC_OPCG_CNTL0_0x00030002,
-    GENERIC_OPCG_CNTL1_0x00030003,
-    GENERIC_OPCG_CNTL2_0x00030004,
-    GENERIC_OPCG_CNTL3_0x00030005,
-    GENERIC_CLK_REGION_0x00030006,
-    GENERIC_CLK_SCANSEL_0x00030007,
-    GENERIC_CLK_STATUS_0x00030008,
-    GENERIC_CLK_ERROR_0x00030009,
-    GENERIC_CLK_SCANDATA0_0x00038000
-};
-
-const uint64_t instruct_start_ffdc_addr_arr[] =
-{
-    EX_PERV_TCTL0_R_MODE_0x10013001,
-    EX_PERV_TCTL0_R_STAT_0x10013002,
-    EX_PERV_TCTL0_POW_STAT_0x10013004,
-    EX_PCNE_REG0_HOLD_OUT_0x1001300D,
-    EX_PERV_THREAD_ACTIVE_0x1001310E,
-    EX_CORE_FIR_0x10013100,
-    EX_SPATTN_0x10040004,
-    PM_SPECIAL_WKUP_FSP_0x100F010B,
-    PM_SPECIAL_WKUP_OCC_0x100F010C,
-    PM_SPECIAL_WKUP_PHYP_0x100F010D,
-    EX_OHA_RO_STATUS_REG_0x1002000B,
-    EX_OHA_MODE_REG_RWx1002000D,
-    EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011,
-    EX_OHA_RO_STATUS_REG_0x1002000B,
-    EX_OHA_AISS_IO_REG_0x10020014,   
-    EX_GP3_0x100F0012,
-    EX_PMGP0_0x100F0100,
-    EX_PMGP1_0x100F0103,
-    EX_PFET_CTL_REG_0x100F0106,
-    EX_PFET_STAT_REG_0x100F0107,
-    EX_PFET_CTL_REG_0x100F010E,
-    EX_PMSTATEHISTPERF_REG_0x100F0113,
-    EX_PCBS_FSM_MONITOR1_REG_0x100F0170,
-    EX_PCBS_FSM_MONITOR2_REG_0x100F0171,   
-    EX_PMErr_REG_0x100F0109,   
-    EX_PCBS_DPLL_STATUS_REG_100F0161,   
-    EX_DPLL_CPM_PARM_REG_0x100F0152        
-};
-
-const uint64_t dpll_lock_ffdc_addr_arr[] =
-{
-    EX_DPLL_CPM_PARM_REG_0x100F0152,
-    EX_PMGP0_0x100F0100,
-    EX_GP3_0x100F0012
-};
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-/**
- * proc_extract_pore_halt_ffdc_unicast - collect FFDC data for one chiplet
- *
- * @param[in]   i_target         - target for FFDC collection
- * @param[in]   i_halt_type      - FFDC type, for logging
- * @param[in]   i_ffdc_addrs     - FFDC addresses to log
- * @param[in]   i_base_scom_addr - base SCOM address (XX000000) to apply
- *                                 to entries of i_ffdc_addrs_log
- * @param[out]  o_rc             - target return code for extra FFDC
- *
- * @retval      fapi::ReturnCode = SUCCESS
- */
-fapi::ReturnCode proc_extract_pore_halt_ffdc_unicast(const fapi::Target & i_target,
-                                                     const por_halt_type_t i_halt_type,
-                                                     const std::vector<uint64_t> * i_ffdc_addrs,
-                                                     const uint32_t i_base_scom_addr,
-                                                     fapi::ReturnCode & o_rc)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-
-    // FFDC collection
-    ecmdDataBufferBase ffdc_reg_addrs(64*(i_ffdc_addrs->size()));
-    ecmdDataBufferBase ffdc_reg_data(64*(i_ffdc_addrs->size()));
-    uint8_t dw_index = 0;
-
-    FAPI_INF("proc_extract_pore_halt_ffdc_unicast: Start (target = %s, base = 0x%08X)",
-             i_target.toEcmdString(), i_base_scom_addr);
-
-    do
-    {
-        rc_ecmd |= ffdc_reg_addrs.flushTo1();
-        rc_ecmd |= ffdc_reg_data.flushTo1();
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_unicast: Error %x flushing FFDC data buffers", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        for (std::vector<uint64_t>::const_iterator i = i_ffdc_addrs->begin();
-             i != i_ffdc_addrs->end();
-             i++)
-        {
-            ecmdDataBufferBase data(64);
-            uint32_t scom_addr = (uint32_t) (*i);
-            scom_addr &= 0x0FFFFFFF;
-            scom_addr += i_base_scom_addr;
-
-            FAPI_DBG("proc_extract_pore_halt_ffdc_unicast: Dumping 0x%08X on %s",
-                     scom_addr, i_target.toEcmdString());
-
-            // explicitly ignore return code, attempt to collect all FFDC registers
-            rc = fapiGetScom(i_target, scom_addr, data);
-            rc_ecmd |= ffdc_reg_addrs.setDoubleWord(dw_index, scom_addr);
-            if (rc.ok())
-            {
-                rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, data.getDoubleWord(0));
-            }
-            else
-            {
-                rc = fapi::FAPI_RC_SUCCESS;
-            }
-
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_extract_pore_halt_ffdc_unicast: Error %x forming FFDC data buffers", rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-            dw_index++;
-        }
-        if (!rc.ok())
-        {
-            break;
-        }
-
-    } while(0);
-
-    const fapi::Target & TARGET = i_target;
-    const por_halt_type_t & PORE_HALT_TYPE = i_halt_type;
-    const ecmdDataBufferBase & FFDC_ADDRESSES = ffdc_reg_addrs;
-    const ecmdDataBufferBase & FFDC_DATA = ffdc_reg_data;
-    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_HALT_FFDC);
-
-    FAPI_INF("proc_extract_pore_halt_ffdc_unicast: End");
-    return rc;
-}
-
-
-/**
- * proc_extract_pore_halt_ffdc_skew_adjust - collect FFDC data for XBUS skew adjust halt
- *
- * @param[in]   i_target         - target for FFDC collection
- * @param[in]   i_halt_type      - FFDC type, for logging
- * @param[out]  o_rc             - target return code for extra FFDC
- *
- * @retval      fapi::ReturnCode = SUCCESS
- */
-fapi::ReturnCode proc_extract_pore_halt_ffdc_skew_adjust(const fapi::Target & i_target,
-                                                         const por_halt_type_t i_halt_type,
-                                                         fapi::ReturnCode & o_rc)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-
-    // FFDC collection
-    const uint8_t READ_REGS = 16;
-    ecmdDataBufferBase ffdc_reg_addrs(64*READ_REGS);
-    ecmdDataBufferBase ffdc_reg_data(64*READ_REGS);
-
-    FAPI_INF("proc_extract_pore_halt_ffdc_skew_adjust: Start (target = %s)",
-             i_target.toEcmdString());
-
-    for (uint8_t dw_index = 0; dw_index < READ_REGS; dw_index++)
-    {
-        ecmdDataBufferBase data(64);
-        bool iter_valid = true;
-
-        // write set register with sync bit asserted
-        rc_ecmd |= data.setBit(X_CLK_ADJ_SET_REG_SYNC_BIT);
-        rc_ecmd |= data.setBit(X_CLK_ADJ_SET_REG_RLM_SELECT_BIT);
-        rc_ecmd |= data.insertFromRight(
-            X_CLK_ADJ_CMD_TYPE_READ,
-            X_CLK_ADJ_SET_REG_CMD_START_BIT,
-            (X_CLK_ADJ_SET_REG_CMD_END_BIT-
-             X_CLK_ADJ_SET_REG_CMD_START_BIT+1));
-        rc_ecmd |= data.insertFromRight(
-            dw_index,
-            X_CLK_ADJ_SET_REG_DATA_START_BIT,
-            (X_CLK_ADJ_SET_REG_DATA_END_BIT-
-             X_CLK_ADJ_SET_REG_DATA_START_BIT+1));
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming X CLK Adjust Set register data buffer (set)",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        
-        rc = fapiPutScom(i_target, X_CLK_ADJ_SET_0x040F0016, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiPutScom (X_CLK_ADJ_SET_0x040F0016)");
-            iter_valid = false;
-        }
-
-        // write set register with sync bit cleared
-        rc_ecmd |= data.clearBit(X_CLK_ADJ_SET_REG_SYNC_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming X CLK Adjust Set register data buffer (clear)",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutScom(i_target, X_CLK_ADJ_SET_0x040F0016, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiPutScom (X_CLK_ADJ_SET_0x040F0016)");
-            iter_valid = false;
-        }
-
-        rc = fapiGetScom(i_target, X_CLK_ADJ_DAT_REG_0x040F0015, data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error from fapiGetScom (X_CLK_ADJ_DAT_REG_0x040F0015)");
-            iter_valid = false;
-        }
-
-        rc_ecmd |= ffdc_reg_addrs.setDoubleWord(dw_index, dw_index);
-        if (iter_valid)
-        {
-            rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, data.getDoubleWord(0));
-        }
-        else
-        {
-            rc_ecmd |= ffdc_reg_data.setDoubleWord(dw_index, 0xFFFFFFFFFFFFFFFFULL);
-            rc = fapi::FAPI_RC_SUCCESS;
-        }
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_pore_halt_ffdc_skew_adjust: Error %x forming FFDC data buffers", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-    }
-
-    const fapi::Target & TARGET = i_target;
-    const por_halt_type_t & PORE_HALT_TYPE = i_halt_type;
-    const ecmdDataBufferBase & FFDC_ADDRESSES = ffdc_reg_addrs;
-    const ecmdDataBufferBase & FFDC_DATA = ffdc_reg_data;
-    FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_EXTRACT_PORE_HALT_FFDC);
-
-    FAPI_INF("proc_extract_pore_halt_ffdc_skew_adjust: End");
-    return rc;
-}
-
-
-
-/**
- * proc_extract_pore_halt_ffdc - HWP entry point, log PORE fail FFDC
- *
- * @param[in]   i_pore_state - struct holding PORE state
- * @param[in]   i_halt_type  - FFDC type to collect
- * @param[in]   i_offset     - offset to apply to FFDC registers for
- *                             i_halt_type (constant/value of PORE
- *                             pervasive base registers/none)
- * @param[out]  o_rc         - target return code for extra FFDC
- *
- * @retval      fapi::ReturnCode = SUCCESS
- */
-fapi::ReturnCode proc_extract_pore_halt_ffdc(const por_base_state & i_pore_state,
-                                             const por_halt_type_t i_halt_type,
-                                             const por_ffdc_offset_t i_offset,
-                                             fapi::ReturnCode & o_rc)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-
-    // FFDC register collection pointer
-    const std::vector<uint64_t> *p = NULL;
-    std::vector<uint64_t> scan_ffdc_addr(scan_ffdc_addr_arr, scan_ffdc_addr_arr + (sizeof(scan_ffdc_addr_arr) / sizeof(scan_ffdc_addr_arr[0])));
-    std::vector<uint64_t> instruct_start_ffdc_addr(instruct_start_ffdc_addr_arr, instruct_start_ffdc_addr_arr + (sizeof(instruct_start_ffdc_addr_arr) / sizeof(instruct_start_ffdc_addr_arr[0])));
-    std::vector<uint64_t> dpll_lock_ffdc_addr(dpll_lock_ffdc_addr_arr, dpll_lock_ffdc_addr_arr + (sizeof(dpll_lock_ffdc_addr_arr) / sizeof(dpll_lock_ffdc_addr_arr[0])));
-
-    FAPI_INF("proc_extract_pore_halt_ffdc: Start");
-
-    do
-    {
-        const fapi::Target & TARGET = i_pore_state.target;
-        const por_halt_type_t & PORE_HALT_TYPE = i_halt_type;
-
-        if (i_halt_type == PORE_HALT_SKEW_ADJUST_FAIL)
-        {
-            FAPI_DBG("proc_extract_pore_halt_ffdc: Collecting skew adjust FFDC");
-            if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP)
-            {
-                rc = proc_extract_pore_halt_ffdc_skew_adjust(i_pore_state.target,
-                                                             i_halt_type,
-                                                             o_rc);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_skew_adjust");
-                    break;
-                }
-            }
-            else
-            {
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE);
-                break;
-            }
-        }
-        else if (i_halt_type == PORE_HALT_FIR_FAIL)
-        {
-            FAPI_DBG("proc_extract_pore_halt_ffdc: Collecting FIR FFDC");
-            if (i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP)
-            {
-                FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_PROC_FIR_FFDC);
-                break;
-            }
-            else if (i_pore_state.target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)
-            {
-                FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_CEN_FIR_FFDC);
-                break;
-            }
-            else
-            {
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE);
-                break;
-            }
-        }
-        else
-        {
-            // set pointer based on halt type
-            switch (i_halt_type)
-            {
-                case PORE_HALT_SCAN_FAIL:
-                case PORE_HALT_SCAN_FLUSH_FAIL:
-                case PORE_HALT_ARRAYINIT_FAIL:
-                    p = &(scan_ffdc_addr);
-                    FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to scan FFDC array");
-                    break;
-                case PORE_HALT_INSTRUCT_FAIL:
-                    p = &(instruct_start_ffdc_addr);
-                    FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to instruction start FFDC array");
-                    break;
-                case PORE_HALT_DPLL_LOCK_FAIL:
-                    p = &(dpll_lock_ffdc_addr);
-                    FAPI_DBG("proc_extract_pore_halt_ffdc: Pointer set to DPLL lock FFDC array");
-                    break;
-                default:
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_TYPE);
-                    break;
-            }
-            if (!rc.ok())
-            {
-                break;
-            }
-            
-            // determine chiplet ID offset to apply to FFDC registers collected
-            // for this halt type
-            uint32_t chiplet_id = i_offset;
-            if ((i_offset == POR_FFDC_OFFSET_USE_P0) ||
-                (i_offset == POR_FFDC_OFFSET_USE_P1))
-            {
-                chiplet_id = 0x0;
-                // chiplet addressed is stored in one of the PORE pervasive base registers
-                // use the value of that register to form the chiplet portion of the FFDC
-                // SCOM addresses
-                rc_ecmd |= i_pore_state.engine_state.extractPreserve(
-                    &chiplet_id,
-                    (64*(i_offset)) + 24,
-                    8,
-                    0);
-                
-                if (rc_ecmd)
-                {
-                    FAPI_ERR("proc_extract_pore_halt_ffdc: Error %x extracting P%d pervasive base content",
-                             rc_ecmd, (i_offset == POR_FFDC_OFFSET_USE_P0)?(0):(1));
-                    rc.setEcmdError(rc_ecmd);
-                    break;
-                }
-            }
-            
-            // multicast address
-            // only support EX multicast unrolling for processor chip targets
-            if (chiplet_id & 0x40000000)
-            {
-                uint8_t mc_group = (chiplet_id >> 24) & 0x3;
-                std::vector<fapi::Target> ex_chiplets;
-            
-                if ((i_pore_state.target.getType() == fapi::TARGET_TYPE_PROC_CHIP) &&
-                    ((mc_group == 1) || (mc_group == 2)))
-                {
-                    // determine set of EX chiplets
-                    rc = fapiGetChildChiplets(i_pore_state.target,
-                                              fapi::TARGET_TYPE_EX_CHIPLET,
-                                              ex_chiplets,
-                                              fapi::TARGET_STATE_FUNCTIONAL);
-                    if (!rc.ok())
-                    {
-                        FAPI_ERR("proc_extract_pore_halt_ffdc: Error from fapiGetChildChiplets");
-                        break;
-                    }
-            
-                    // collect FFDC for chiplets which are part of the multicast group
-                    for (std::vector<fapi::Target>::iterator i = ex_chiplets.begin();
-                         i != ex_chiplets.end();
-                         i++)
-                    {
-                        ecmdDataBufferBase mc_config_data(64);
-                        uint64_t mc_group_addr = (mc_group == 1)?(EX_MCGR2_0x100F0002):(EX_MCGR3_0x100F0003);
-                        uint8_t mc_group_listen;
-            
-                        rc = fapiGetScom(*i, mc_group_addr, mc_config_data);
-                        if (!rc.ok())
-                        {
-                            FAPI_ERR("proc_extract_pore_halt_ffdc: Error from fapiGetScom (EX_MCGR%d_0x%08llX)",
-                                     mc_group+1, mc_group_addr);
-                            break;
-                        }
-            
-                        rc_ecmd |= mc_config_data.extractToRight(&mc_group_listen, 3, 3);
-                        if (rc_ecmd)
-                        {
-                            FAPI_ERR("proc_extract_pore_halt_ffdc: Error %x extracting multicast group listen configuration", rc_ecmd);
-                            rc.setEcmdError(rc_ecmd);
-                            break;
-                        }
-            
-                        if (mc_group_listen == mc_group)
-                        {
-                            rc = proc_extract_pore_halt_ffdc_unicast(*i, i_halt_type, p, 0x10000000, o_rc);
-                            if (!rc.ok())
-                            {
-                                if (!rc.ok())
-                                {
-                                    FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_unicast");
-                                    break;
-                                }
-                            }
-                        }
-                        else
-                        {
-                            FAPI_INF("proc_extract_pore_halt_ffdc: Skipping %s, not part of multicast group",
-                                     i->toEcmdString());
-                        }
-                    }
-                    if (!rc.ok())
-                    {
-                        break;
-                    }
-                }
-                else
-                {
-                    FAPI_ERR("proc_extract_halt_ffdc: Unsupported multicast extraction for target: %s, group: %d",
-                             i_pore_state.target.toEcmdString(), mc_group);
-                    const uint8_t & CHIPLET_ID = chiplet_id;
-                    const uint8_t & MC_GROUP = mc_group;
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_HALT_FFDC_BAD_MULTICAST);
-                    break;
-                }
-            }
-            // unicast address
-            else
-            {
-                rc = proc_extract_pore_halt_ffdc_unicast(i_pore_state.target, i_halt_type, p, chiplet_id, o_rc);
-                if (!rc.ok())
-                {
-                    FAPI_ERR("proc_extract_pore_halt_ffdc: Error from proc_extract_pore_halt_ffdc_unicast");
-                    break;
-                }
-            }
-        }
-    } while(0);
-
-    FAPI_INF("proc_extract_pore_halt_ffdc: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H
deleted file mode 100644
index 1e9d4e2d3..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H
+++ /dev/null
@@ -1,88 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_pore_halt_ffdc.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_pore_halt_ffdc.H,v 1.1 2014/07/23 19:38:06 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_pore_halt_ffdc.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_pore_halt_ffdc.C
-// *! DESCRIPTION : Extract SBE/SLW halt-fail related FFDC
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_EXTRACT_PORE_HALT_FFDC_H_
-#define _PROC_EXTRACT_PORE_HALT_FFDC_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <proc_extract_sbe_rc.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_extract_pore_halt_ffdc_FP_t)(const por_base_state &,
-                                                             const por_halt_type_t,
-                                                             const por_ffdc_offset_t,
-                                                             fapi::ReturnCode &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * proc_extract_pore_halt_ffdc - HWP entry point, log PORE fail FFDC
- *
- * @param[in]   i_pore_state - struct holding PORE state
- * @param[in]   i_halt_type  - FFDC type to collect
- * @param[in]   i_offset     - offset to apply to FFDC registers for
- *                             i_halt_type (constant/value of PORE
- *                             pervasive base registers/none)
- * @param[out]  o_rc         - target return code for extra FFDC
- *
- * @retval      fapi::ReturnCode = SUCCESS
- */
-fapi::ReturnCode proc_extract_pore_halt_ffdc(const por_base_state & i_pore_state,
-                                             const por_halt_type_t i_halt_type,
-                                             const por_ffdc_offset_t i_offset,
-                                             fapi::ReturnCode & o_rc);
-
-} // extern "C"
-
-#endif // _PROC_EXTRACT_PORE_HALT_FFDC_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
deleted file mode 100644
index 2bf1bc810..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C
+++ /dev/null
@@ -1,580 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_sbe_rc.C,v 1.25 2015/09/22 13:47:24 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_sbe_rc.C
-// *! DESCRIPTION : Create return code for PORE (SBE/SLW) error
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Johannes Koesters       Email: koesters@de.ibm.com
-// *!
-// *! Overview:
-// *!   - Analyze error state of SBE/SLW engine
-// *!     - Examine SBE/SLW engine state to determine if a HW error occurred.
-// *!       Return RC for HW error if present
-// *!     - For 'halt' due to SBE/SLW code generated failure:
-// *!         - Determine PC at point for failure
-// *!         - Lookup PC in appropriate code space (SEEPROM/PIBMEM/OTPROM),
-// *!           extract & return RC for its associated error
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_extract_sbe_rc.H>
-#include <proc_reset_i2cm_bus_fence.H>
-#include <proc_extract_pore_engine_state.H>
-#include <proc_extract_pore_base_ffdc.H>
-#include <proc_extract_pore_halt_ffdc.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// address space masks
-const uint64_t PORE_ADDR_MASK              = 0x0000FFFFFFFFFFFFULL;
-const uint64_t INTERNAL_ADDR_MASK          = 0x000000007FFFFFFFULL;
-const uint64_t ADDR_TYPE_MASK              = 0x0000FFFF80000000ULL;
-const uint64_t OTPROM_ADDR_TYPE            = 0x0000000100000000ULL;
-const uint64_t PIBMEM_ADDR_TYPE            = 0x0000000800000000ULL;
-const uint64_t SEEPROM_ADDR_TYPE           = 0x0000800C80000000ULL;
-const uint64_t SLW_ADDR_TYPE               = 0x0000800080000000ULL;
-
-// illegal instruction encoding for SW detected halt
-const uint32_t PORE_HALT_WITH_ERROR_INSTRUCTION = (('h' << 24) | ('a' << 16) | ('l' << 8) | ('t'));
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-/**
- * proc_extract_sbe_rc - HWP entry point, return RC indicating SBE/SLW error
- *
- * @param[in]   i_target - target of chip with failed SBE/SLW engine
- * @param[in]   i_poreve - pointer to PoreVe object, used to collect engine
- *                         state if non NULL
- * @param[in]   i_image  - pointer to memory-mapped PORE image
- * @param[in]   i_engine - type of engine that failed (SBE/SLW)
- *
- * @retval      fapi::ReturnCode  - The error code the SBE hit, or the error hit
- *                                  while trying to get the error code
- */
-fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
-                                     void * i_poreve,
-                                     const void * i_image,
-                                     const por_engine_t i_engine)
-{
-    // return codes
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0x0;
-
-    // common state for analysis/FFDC
-    const fapi::Target & CHIP = i_target;
-    por_base_state pore_state;
-    // SBE specific state for analysis/FFDC
-    por_sbe_base_state pore_sbe_state;
-    // multicast error regs
-    ecmdDataBufferBase mc_err_reg0(64);
-
-    // process arguments
-    bool is_processor = (i_target.getType() == fapi::TARGET_TYPE_PROC_CHIP);
-    bool is_sbe = (i_engine == SBE);
-    bool is_slw = (i_engine == SLW);
-
-    do
-    {
-        // 
-        // SBE - capture multicast error reg
-        // 
-        rc = fapiGetScom(i_target, PCBMS_REC_ERR_REG0_0x000F0011, mc_err_reg0);
-        if (!rc.ok())
-        {
-            FAPI_INF("proc_extract_sbe_rc: Error from fapiGetScom (PCBMS_REC_ERR_REG0_0x000F0011)");
-            rc = fapi::FAPI_RC_SUCCESS;
-        }
-
-        //
-        // all engine types -- extract engine state
-        //
-
-        FAPI_INF("proc_extract_sbe_rc: Processing PORE engine for target: %s, engine type: %s, virtual: %d", 
-                 i_target.toEcmdString(),
-                 ((i_engine == SBE)?("SBE"):("SLW")),
-                 (i_poreve == NULL)?(0):(1));
-
-        FAPI_EXEC_HWP(rc, proc_extract_pore_engine_state,
-                      i_target, i_poreve, i_engine, pore_state, pore_sbe_state);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_extract_sbe_rc: Error from proc_extract_pore_engine_state");
-            break;
-        }
-
-
-        //
-        // processor SBE -- return SEEPROM/PNOR UE as highest priority callouts
-        //
-
-        if (is_processor && is_sbe)
-        {
-            // ensure I2C master bus fence is released before proceeding
-            FAPI_EXEC_HWP(rc, proc_reset_i2cm_bus_fence, i_target);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_extract_sbe_rc: Error from proc_reset_i2cm_bus_fence");
-                break;
-            }
-
-            // return error if either ECCB engine reports an unrecoverable ECC error
-            if (pore_sbe_state.i2cm_eccb_status.isBitClear(41,2) && pore_sbe_state.i2cm_eccb_status.isBitSet(43))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SBE encountered Unrecoverable ECC error on I2C Access");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_SEEPROM);
-                break;
-            }
-
-            if (pore_sbe_state.pnor_eccb_status.isBitClear(41,2) && pore_sbe_state.pnor_eccb_status.isBitSet(43))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SBE encountered Unrecoverable ECC error on PNOR Access");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNRECOVERABLE_ECC_PNOR);
-                break;
-            }
-        }
-
-
-        //
-        // all engine types -- process PORE Debug0/Debug1 registers for HW detected/SW generated errors
-        // 
-
-        ecmdDataBufferBase pore_debug0_reg;
-        ecmdDataBufferBase pore_debug1_reg;
-
-        rc_ecmd |= pore_state.engine_state.extractToRight(pore_debug0_reg, 64*PORE_DEBUG0_OFFSET, 64);
-        rc_ecmd |= pore_state.engine_state.extractToRight(pore_debug1_reg, 64*PORE_DEBUG1_OFFSET, 64);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_extract_sbe_rc: Error %x extracting PORE engine debug register state", rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // any HW error will cause DBG_LOCK bit to be set
-        if (pore_debug1_reg.isBitSet(63))
-        {
-            FAPI_ERR("proc_extract_sbe_rc: PIBMS_DBG_LOCK - error set");
-
-            // print bitwise messages for error log, unique errors will be grouped/combined into callouts below
-            // grouping is done per guidance provided by Andreas Koenig
-            if (pore_debug1_reg.isBitSet(48))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: ERR_DATA_READ_P_ERR - Parity error in read data from OCI");
-            }
-            uint8_t oci_rc = (pore_debug0_reg.getByte(7) >> 5) & 0x7;
-            if (oci_rc)
-            {
-                FAPI_ERR("proc_extract_sbe_rc: Last return code from OCI received return code %i", oci_rc);
-            }
-            if (pore_debug1_reg.isBitSet(52))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: BAD_PAR - bad instruction parity");
-            }
-            if (pore_debug1_reg.isBitSet(53))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: BAD_INSTRUCTION - invalid instruction");
-            }
-            if (pore_debug1_reg.isBitSet(54))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: BAD_PC - PC overflow/underflow");
-            }
-            if (pore_debug1_reg.isBitSet(55))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SCAN_DATA_CRC - Scan data CRC error");
-            }
-            if (pore_debug1_reg.isBitSet(56))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: PC_STACK_ERR - PC stack PUSH error or POP error");
-            }
-            if (pore_debug1_reg.isBitSet(57))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: INSTR_FETCH_ERROR - Non-zero return code or read DEBUG1 parity error was received when during fetch phase");
-            }
-            if (pore_debug1_reg.isBitSet(58))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: BAD_OPERAND - Invalid Instruction Operand");
-            }
-            if (pore_debug1_reg.isBitSet(59))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: BAD_INSTRUCTION_PATH - Invalid Instruction Path (e.g. FI2C parameter miss)");
-            }
-            if (pore_debug1_reg.isBitSet(60))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: BAD_START_VECTOR_TRIGGER - Invalid Start Vector triggered");
-            }
-            if (pore_debug1_reg.isBitSet(61))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: FI2C_PROTOCOL_HANG - Fast I2C protocol hang detected - exceeded poll limit for FI2C engine");
-            }
-            if (pore_debug1_reg.isBitSet(62))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: ROL_INVALID - rotate invalid");
-            }
-            if (pore_debug0_reg.isBitSet(32))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: PIB_DATA_READ_P_ERR - Parity error in read data from PRV PIB");
-            }
-            uint8_t pcb_error = (pore_debug0_reg.getByte(4) >> 4) & 0x7;
-            uint32_t scom_address = pore_debug0_reg.getWord(0);
-            if (pcb_error)
-            {
-                FAPI_ERR("proc_extract_sbe_rc: PORE engine got PCB error %i accessing scom address 0x%08X", pcb_error, scom_address);
-            }
-            if (pore_debug0_reg.isBitSet(36))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_0 - I2CM internal errors including parity errors");
-            }
-            if (pore_debug0_reg.isBitSet(37))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_1 - bad PIB response code error for ECCAX to I2CM communication");
-            }
-            if (pore_debug0_reg.isBitSet(38))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_2 - ECCAX internal errors (UCE or PIB master resets)");
-            }
-            if (pore_debug0_reg.isBitSet(39))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: I2C_BAD_STATUS_3 - I2C bus issues (I2C bus busy, NACK, stop bit error)");
-            }
-            if (pore_debug0_reg.isBitSet(40))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_0 - parity error from DEBUG or STATUS or ERROR MASK or PC STACK regs");
-            }
-            if (pore_debug0_reg.isBitSet(41))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_1 - parity error from CONTROL or EXE TRIGGER or EXE T_MASK or I2C PARAM regs");
-            }
-            if (pore_debug0_reg.isBitSet(42))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_2 - parity error from PERV/OCI BASE ADDR or TABLE BASE ADDR or MEMORY RELOC regs");
-            }
-            if (pore_debug0_reg.isBitSet(43))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_3 - parity error from SCR0 or SCR1 or SCR2 or DEBUG0 SCR0 reg");
-            }
-            if (pore_debug0_reg.isBitSet(44))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: GROUP_PARITY_ERROR_4 - parity error from IBUF regs");
-            }
-
-            //
-            // Bucketize callouts based on combination of error bits
-            //
-
-            // "Internal Error" bucket (Error Event 3)
-            if ((pore_debug0_reg.getNumBitsSet(40,5) != 0) || pore_debug1_reg.isBitSet(55))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: Internal Error (Event 3)");
-                const uint8_t & GROUP_PARITY_ERROR_0_4 = (pore_debug0_reg.getByte(5) >> 3) & 0x1F;
-                const bool & SCAN_DATA_CRC_ERROR = pore_debug1_reg.isBitSet(55);
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INTERNAL_ERROR);
-                break;
-            }
-
-            // "I2C Error" bucket (Error Event 0)
-            if ((pore_debug0_reg.getNumBitsSet(36,4) != 0) || (pore_debug1_reg.isBitSet(61)))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: I2C Error (Event 0)");
-                const uint8_t & I2C_BAD_STATUS_0_3 = (pore_debug0_reg.getByte(4) & 0x0F);
-                const bool & FI2C_HANG = pore_debug1_reg.isBitSet(61);
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_I2C_ERROR);
-                break;
-            }
-
-            // "SCOM Error" bucket (Error Event 0), raise only if no instruction execution error is present
-            if ((pore_debug0_reg.getNumBitsSet(32,4) != 0) && (pore_debug1_reg.getNumBitsSet(52,9) == 0) && (pore_debug1_reg.isBitClear(62)))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SCOM operation failed (Event 0)");
-                const uint32_t & SCOM_ADDRESS = scom_address;
-                const uint8_t & PIB_ERROR_CODE = pcb_error;
-                const bool & PIB_DATA_READ_PARITY_ERROR = pore_debug0_reg.isBitSet(32);
-
-
-                if (is_sbe &&
-                    (scom_address == (uint32_t) TP_GP0_OR_0x01000005) &&
-                    (pore_state.vital_state.getHalfWord(1) == 0x2031))
-                {
-                    FAPI_INF("proc_extract_sbe_rc: Reconfig loop should be attempted");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ENGINE_RETRY);
-                }
-                // SW285387
-                else if (is_sbe &&
-                         (scom_address == (uint32_t) PCIE_OPCG_CNTL0_0x09030002) &&
-                         (pore_state.vital_state.getHalfWord(1) == 0x2100))
-                {
-                    FAPI_INF("proc_extract_sbe_rc: PCI OPCG SCOM failure encountered");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_PCI_CLOCK_ERROR);
-                }
-                // SW310202
-                else if (is_sbe &&
-                         (scom_address == (uint32_t) WRITE_ALL_GP0_OR_0x68000005) &&
-                         (pore_state.vital_state.getHalfWord(1) == 0x2120) &&
-                         (mc_err_reg0.isBitSet(36) &&                                 // slave9 response
-                          mc_err_reg0.isBitClear(37) && mc_err_reg0.isBitSet(38,2)))  // slave9 error code = 0b011
-                {
-                    FAPI_INF("proc_extract_sbe_rc: PCI multicast SCOM failure encountered");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_PCI_CLOCK_ERROR);
-                }
-                else
-                {
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SCOM_ERROR);
-                }
-                break;
-            }
-
-            // "OCI Error" bucket (Error Event 1)
-            if (is_slw && (pore_debug1_reg.getNumBitsSet(48,4) != 0))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: OCI Master operation failed (Event 1)");
-                const uint8_t & OCI_ERROR_CODE = oci_rc;
-                const bool & OCI_DATA_READ_PARITY_ERROR = pore_debug1_reg.isBitSet(48);
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_OCI_ERROR);
-                break;
-            }
-
-            // check for PORE code generated halt
-            // code detected errors will result in the the execution of an invalid instruction -> ASCII 'halt'
-            if (pore_debug1_reg.isBitSet(53) || pore_debug1_reg.isBitSet(62))
-            {
-                // check alignment of PC value
-                if (pore_state.pc & 0x3ULL)
-                {
-                    FAPI_ERR("proc_extract_sbe_rc: Unexpected address alignment");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_UNALIGNED);
-                    break;
-                }
-
-                // examine first word of IBUF register
-                uint32_t instruction = pore_state.engine_state.getWord(2*PORE_IBUF0_OFFSET);
-                if (instruction == PORE_HALT_WITH_ERROR_INSTRUCTION)
-                {
-                     // halt encountered
-                     // RC indicating unique exit point will be contained in next word
-                     // retrieve RC from appropriate memory space
-                     uint64_t rc_addr = (pore_state.pc & INTERNAL_ADDR_MASK)+4;
-                     
-                     if ((is_processor && 
-                         (((pore_state.pc & ADDR_TYPE_MASK) == SEEPROM_ADDR_TYPE) ||
-                          ((pore_state.pc & ADDR_TYPE_MASK) == SLW_ADDR_TYPE))) ||
-                         (!is_processor))
-                     {
-                         if (i_image == NULL)
-                         {
-                             FAPI_ERR("proc_extract_sbe_rc: PORE image pointer is NULL");
-                             FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_IMAGE_POINTER_NULL);
-                             break;
-                         }
-
-                         FAPI_INF("proc_extract_sbe_rc: Extracting the error code from address 0x%llX in PORE image", rc_addr);
-                         uint8_t * p_errorCode = (uint8_t *) i_image + rc_addr;
-                         pore_state.rc =
-                             (p_errorCode[0] << 3*8) |
-                             (p_errorCode[1] << 2*8) |
-                             (p_errorCode[2] << 1*8) |
-                             (p_errorCode[3]);
-                     }
-                     else if (is_processor && ((pore_state.pc & ADDR_TYPE_MASK) == PIBMEM_ADDR_TYPE))
-                     {
-                         FAPI_INF("proc_extract_sbe_rc: Extracting the error code from address 0x%llX in the PIBMEM", rc_addr);
-                         ecmdDataBufferBase pibmem_data(64);
-                         rc = fapiGetScom(i_target, PIBMEM0_0x00080000 + (rc_addr >>3), pibmem_data);
-                         if (rc)
-                         {
-                             FAPI_ERR("proc_extract_sbe_rc: Error from fapiGetScom (PIBMEM address 0x%08X)", (uint32_t) (PIBMEM0_0x00080000 + (rc_addr >>3)));
-                             break;
-                         }
-                         pore_state.rc = pibmem_data.getWord((rc_addr & 0x04)?1:0);
-                     }
-                     else
-                     {
-                         FAPI_ERR("proc_extract_sbe_rc: Address (0x%012llX) isn't in a known memory address space", pore_state.pc);
-                         FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_ADDR_NOT_RECOGNIZED);
-                         break;
-                     }
-
-                     // invoke platform function to return XML defined RC associated with PORE state
-                     FAPI_ERR("proc_extract_sbe_rc: PORE got error code 0x%06X", pore_state.rc);
-                     FAPI_SET_SBE_ERROR(rc, pore_state.rc);
-
-                     // ensure that error is generated in this code path
-                     if (rc.ok())
-                     {
-                         FAPI_ERR("proc_extract_sbe_rc: PORE got error code 0x%06X, but this did not resolve to any return code!", pore_state.rc);
-                         FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_FROM_ADDR_CODE_BUG);
-                     }
-                     break;
-                }
-            }
-
-            // "Instruction Execution Error" bucket (Error Event 2)
-            if ((pore_debug1_reg.getNumBitsSet(52,9) != 0) || (pore_debug1_reg.isBitSet(62)))
-            {
-                FAPI_ERR("proc_extract_sbe_rc: Instruction execution error (Event 2)");
-                const bool & INSTRUCTION_PARITY_ERROR = pore_debug1_reg.isBitSet(52);
-                const bool & INVALID_INSTRUCTION_NON_ROTATE = pore_debug1_reg.isBitSet(53);
-                const bool & PC_OVERFLOW_UNDERFLOW = pore_debug1_reg.isBitSet(54);
-                // bit 55 covered by Internal Error check
-                const bool & PC_STACK_ERROR = pore_debug1_reg.isBitSet(56);
-                const bool & INSTRUCTION_FETCH_ERROR = pore_debug1_reg.isBitSet(57);
-                const bool & INVALID_OPERAND = pore_debug1_reg.isBitSet(58);
-                const bool & I2C_ENGINE_MISS = pore_debug1_reg.isBitSet(59);
-                const bool & INVALID_START_VECTOR = pore_debug1_reg.isBitSet(60);
-                const bool & INVALID_INSTRUCTION_ROTATE = pore_debug1_reg.isBitSet(62);
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_INSTRUCTION_ERROR);
-                break;
-            }
-        }
-
-
-        //
-        // processor SBE -- check for real halt in OTPROM
-        // 
-
-        // for processor SBE only, check for real halt (wait 0) instruction in OTPROM
-        if (is_processor && is_sbe && ((pore_state.pc & ADDR_TYPE_MASK) == OTPROM_ADDR_TYPE))
-        {
-            // Note: OTPROM halts are actual halt instructions, which means the
-            //       SBE updated the PC before the halt.
-            //       Thus we have to subtract 4 to get back to the address of the halt
-            uint32_t pc_m4 = (uint32_t)(pore_state.pc & INTERNAL_ADDR_MASK)-4;
-
-            // map the OTPROM address to the known error at that location
-            // the OTPROM is write-once at mfg test, so addresses should remain fixed in this code
-            FAPI_INF("proc_extract_sbe_rc: Determining OTPROM error at address 0x%X", pc_m4);
-            switch (pc_m4)
-            {
-                case (0x400fc):
-                case (0x40118):
-                case (0x40124):
-                    FAPI_ERR("proc_extract_sbe_rc: Chip was not identified as Murano or Venice");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BAD_CHIP_TYPE);
-                    break;
-                case (0x401c0):
-                case (0x401cc):
-                    FAPI_ERR("proc_extract_sbe_rc: SEEPROM magic number didn't match \"XIP SEPM\"");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SEEPROM_MAGIC_NUMBER_MISMATCH);
-                    break;
-                case (0x401ec):
-                case (0x401f8):
-                    FAPI_ERR("proc_extract_sbe_rc: Branch to SEEPROM didn't happen");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_BRANCH_TO_SEEPROM_FAIL);
-                    break;
-                default:
-                    FAPI_ERR("proc_extract_sbe_rc: Halted in OTPROM, but not at an expected halt location");
-                    FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_UNEXPECTED_OTPROM_HALT);
-                    break;
-            }
-        }
-
-
-        //
-        // all engine types -- validate execution progress of PC
-        //
-
-        // determine if engine was ever started
-        if (((pore_state.pc & PORE_ADDR_MASK) == 0x0000800000000000ULL) ||
-            ((pore_state.pc & PORE_ADDR_MASK) == 0x0000000000000000ULL))
-        {
-            FAPI_ERR("proc_extract_sbe_rc: PC is all zeros, which means PORE engine was probably never started");
-            FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_NEVER_STARTED);
-            break;
-        }
-
-
-        //
-        // processor SBE -- return soft error with lowest priority
-        //
-
-        if (is_processor && is_sbe && (pore_sbe_state.soft_err != eNO_ERROR))
-        {
-            if (pore_sbe_state.soft_err == eSOFT_ERR_I2CM)
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on I2C Access");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM);
-                break;
-            }
-            else if (pore_sbe_state.soft_err == eSOFT_ERR_PNOR)
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on PNOR Access");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_PNOR);
-                break;
-            }
-            else // (soft_err == eSOFT_ERR_BOTH)
-            {
-                FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on I2C Access");
-                FAPI_ERR("proc_extract_sbe_rc: SBE encountered Recoverable ECC Error on PNOR Access");
-                FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_SOFT_ECC_ERROR_SEEPROM_AND_PNOR);
-                break;
-            }
-        }
-
-    } while(0);
-
-    //
-    // processor SBE -- ensure HWP doesn't return FAPI_RC_SUCCESS if the engine reported attn
-    // 
-    if (rc.ok() && is_processor && is_sbe && pore_sbe_state.reported_attn)
-    {
-        FAPI_ERR("proc_extract_sbe_rc: SBE reported attention, but proc_extract_sbe_rc tried to return SUCCESS!");
-        FAPI_SET_HWP_ERROR(rc, RC_PROC_EXTRACT_SBE_RC_CODE_BUG);
-    }
-
-    //
-    // all engine types -- append engine specific base FFDC to any non-zero return code
-    // 
-
-    if (!rc.ok())
-    {
-        FAPI_ADD_INFO_TO_HWP_ERROR(rc, RC_PROC_EXTRACT_PORE_BASE_FFDC);
-    }
-
-    FAPI_INF("proc_extract_sbe_rc: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
deleted file mode 100644
index 3e2114749..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H
+++ /dev/null
@@ -1,203 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_extract_sbe_rc.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_extract_sbe_rc.H,v 1.9 2014/07/24 03:13:59 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_extract_sbe_rc.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_extract_sbe_rc.H
-// *! DESCRIPTION : Create return code for PORE (SBE/SLW) error
-// *!
-// *! OWNER NAME  : Joe McGill              Email: jmcgill@us.ibm.com
-// *! BACKUP NAME : Johannes Koesters       Email: koesters@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_EXTRACT_SBE_RC_H_
-#define _PROC_EXTRACT_SBE_RC_H_
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-#include <cen_scom_addresses.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// engine types
-enum por_engine_t {
-    SBE = PORE_SBE_0x000E0000,
-    SLW = PORE_SLW_0x00068000
-};
-
-// common SCOM register offsets for SBE/SLW engines
-enum por_reg_offset_t {
-    PORE_STATUS_OFFSET      = 0x00,
-    PORE_CONTROL_OFFSET     = 0x01,
-    PORE_RESET_OFFSET       = 0x02,
-    PORE_ERR_MASK_OFFSET    = 0x03,
-    PORE_P0_OFFSET          = 0x04,
-    PORE_P1_OFFSET          = 0x05,
-    PORE_A0_OFFSET          = 0x06,
-    PORE_A1_OFFSET          = 0x07,
-    PORE_TBL_BASE_OFFSET    = 0x08,
-    PORE_EXE_TRIGGER_OFFSET = 0x09,
-    PORE_CTR_OFFSET         = 0x0A,
-    PORE_D0_OFFSET          = 0x0B,
-    PORE_D1_OFFSET          = 0x0C,
-    PORE_IBUF0_OFFSET       = 0x0D,
-    PORE_IBUF1_OFFSET       = 0x0E,
-    PORE_DEBUG0_OFFSET      = 0x0F,
-    PORE_DEBUG1_OFFSET      = 0x10,
-    PORE_STACK0_OFFSET      = 0x11,
-    PORE_STACK1_OFFSET      = 0x12,
-    PORE_STACK2_OFFSET      = 0x13,
-    PORE_IDFLAGS_OFFSET     = 0x14,
-    PORE_SPRG0_OFFSET       = 0x15,
-    PORE_MRR_OFFSET         = 0x16,
-    PORE_I2CE0_OFFSET       = 0x17,
-    PORE_I2CE1_OFFSET       = 0x18,
-    PORE_I2CE2_OFFSET       = 0x19,
-    PORE_NUM_REGS           = 0x1A
-};
-
-// SBE soft error types
-enum por_sbe_soft_error_t
-{
-    eNO_ERROR = 0,
-    eSOFT_ERR_I2CM=1, 
-    eSOFT_ERR_PNOR=2,
-    eSOFT_ERR_BOTH=3
-};
-
-enum por_halt_type_t
-{
-    PORE_HALT_SCAN_FAIL = 0,
-    PORE_HALT_SCAN_FLUSH_FAIL = 1,
-    PORE_HALT_ARRAYINIT_FAIL = 2,
-    PORE_HALT_SKEW_ADJUST_FAIL = 3,
-    PORE_HALT_FIR_FAIL = 4,
-    PORE_HALT_INSTRUCT_FAIL = 5,
-    PORE_HALT_DPLL_LOCK_FAIL = 6
-};
-
-enum por_ffdc_offset_t
-{
-    POR_FFDC_OFFSET_NONE = 0x0,
-    POR_FFDC_OFFSET_TP_CHIPLET = TP_CHIPLET_0x01000000,
-    POR_FFDC_OFFSET_NEST_CHIPLET = NEST_CHIPLET_0x02000000,
-    POR_FFDC_OFFSET_MEM_CHIPLET = MEM_CHIPLET_0x03000000,
-    POR_FFDC_OFFSET_XBUS_CHIPLET = X_BUS_CHIPLET_0x04000000,
-    POR_FFDC_OFFSET_ABUS_CHIPLET = A_BUS_CHIPLET_0x08000000,
-    POR_FFDC_OFFSET_PCIE_CHIPLET = PCIE_CHIPLET_0x09000000,
-    POR_FFDC_OFFSET_EX_CHIPLET = EX00_CHIPLET_0x10000000,
-    POR_FFDC_OFFSET_USE_P0 = PORE_P0_OFFSET,
-    POR_FFDC_OFFSET_USE_P1 = PORE_P1_OFFSET
-};
-
-
-// structure to encapsulate PORE state/FFDC content
-struct por_base_state
-{
-    fapi::Target target;               // chip target associated with failed engine
-    por_engine_t engine;               // engine type (SBE/SLW)
-    bool is_virtual;                   // virtual engine?
-    ecmdDataBufferBase vital_state;    // SBE/SLW vital state
-    ecmdDataBufferBase engine_state;   // SBE/SLW engine state
-    uint64_t pc;                       // SBE/SLW engine PC
-    uint32_t rc;                       // RC associated with SBE/SLW halt point
-
-    por_base_state()
-    {
-        vital_state.setDoubleWordLength(1);
-        vital_state.flushTo1();
-        engine_state.setDoubleWordLength(PORE_NUM_REGS);
-        engine_state.flushTo1();
-        pc = 0xFFFFFFFFFFFFFFFFULL;
-        rc = 0x0;
-    }
-};
-
-// structure to encapsulate PORE SBE-specific base FFDC content
-struct por_sbe_base_state
-{
-    ecmdDataBufferBase pnor_eccb_status;  // PNOR ECCB status register state
-    ecmdDataBufferBase i2cm_eccb_status;  // SEEPROM ECCB status register state
-    por_sbe_soft_error_t soft_err;        // PNOR/SEEPROM soft error state
-    bool reported_attn;                   // SBE generated attention?
-
-    por_sbe_base_state()
-    {
-        pnor_eccb_status.setDoubleWordLength(1);
-        pnor_eccb_status.flushTo1();
-        i2cm_eccb_status.setDoubleWordLength(1);
-        i2cm_eccb_status.flushTo1();
-        soft_err = eNO_ERROR;
-        reported_attn = false;
-    }
-};
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_extract_sbe_rc_FP_t)(const fapi::Target &,
-                                                     void *,
-                                                     const void *,
-                                                     const por_engine_t);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * proc_extract_sbe_rc - HWP entry point, return RC indicating SBE/SLW error
- *
- * @param[in]   i_target - target of chip with failed SBE/SLW engine
- * @param[in]   i_poreve - pointer to PoreVe object, used to collect engine
- *                         state if non NULL
- * @param[in]   i_image  - pointer to memory-mapped PORE image
- * @param[in]   i_engine - type of engine that failed (SBE/SLW)
- *
- * @retval      fapi::ReturnCode  - The error code the SBE hit, or the error hit
- *                                  while trying to get the error code
- */
-fapi::ReturnCode proc_extract_sbe_rc(const fapi::Target & i_target,
-                                     void * i_poreve,
-                                     const void * i_image,
-                                     const por_engine_t i_engine);
-
-} // extern "C"
-
-#endif // _PROC_EXTRACT_SBE_RC_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C
deleted file mode 100644
index 85470056e..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C
+++ /dev/null
@@ -1,557 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-// -*- mode: C++; c-file-style: "linux";  -*-
-// $Id: proc_read_seeprom.C,v 1.11 2013/09/18 18:48:38 szhong Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_read_seeprom.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_read_seeprom.C
-// *! DESCRIPTION : Read the value of seeprom given a starting address and read length 
-// *!
-// *! OWNER NAME  : Christina Kuhfal            Email: ckuhfal@us.ibm.com
-// *! MODIFIED BY : William Zhong               Email: szhong@us.ibm.com
-// *!
-// *! Overview:
-// *!   Set the address that is going to be read
-// *!	Read from that address
-// *!	Send the data that was read back to the user 
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_read_seeprom.H"
-#include <fapi.H>
-
-//*******************************************************
-//Experiments on s1_e8052 wafer model shows first read takes 29*200000 cycles
-//other normal reads takes 19*200000 cycles.
-//*******************************************************
-
-#define TIMEOUT_LIMIT 40         //total time_out: TIMEOUT_LIMIT*LOOP_DELAY_CYCLE or TIMEOUT_LIMIT*LOOP_DELAY_TIME
-#define LOOP_DELAY_CYCLE 200000
-#define LOOP_DELAY_TIME  200000  //!!!this number should be rechecked!!!
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// function:
-//      Set the address that is going to be read
-//	Read from that address
-//	Send the data that was read back to the user 
-//
-// parameters:  i_target  => chip target
-//		i_start_addr => start address
-//		i_length => length to read in bytes
-//              o_data => The data that is read is sent back to the user
-// returns: FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-   
-
-    fapi::ReturnCode check_status_register_errors(ecmdDataBufferBase is_ready)
-    {
-	fapi::ReturnCode rc;
-	////////////////////////////////////////////////////////////////////
-	//*****************Check if any errorbits are set*****************//
-	do{
-	    if(is_ready.isBitSet(0))
-		{
-		    FAPI_ERR("ERROR:PIB_BUS_ADDR_NVLD_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_BUS_ADDR_NVLD_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(1))
-		{
-		    FAPI_ERR("ERROR: PIB_BUS_WRITE_NVLD_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_BUS_WRITE_NVLD_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(2))
-		{
-		    FAPI_ERR("ERROR:PIB_BUS_READ_NVLD_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_BUS_READ_NVLD_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(3))
-		{
-		    FAPI_ERR("ERROR:PIB_BUS_ADDR_PAR_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_BUS_ADDR_PAR_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(4))
-		{
-		    FAPI_ERR("ERROR:PIB_BUS_PAR_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_BUS_PAR_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(5))
-		{
-		    FAPI_ERR("ERROR:LOCAL_BUS_PAR_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_LOCAL_BUS_PAR_ERR_BIT_SET);
-		    break;
-		}
-	    //38:40 
-	    if(is_ready.isBitSet(45))
-		{
-		    FAPI_ERR("ERROR:PIB_INVALID_COMMAND");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_INVALID_COMMAND_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(46))
-		{
-		    FAPI_ERR("ERROR:PIB_PARITY_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_PARITY_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(47))
-		{
-		    FAPI_ERR("ERROR:I2C_BACK_END_OVERRUN_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_BACK_END_OVERRUN_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(48))
-		{
-		    FAPI_ERR("ERROR:I2C_BACK_END_ACCESS_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_BACK_END_ACCESS_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(49))
-		{
-		    FAPI_ERR("ERROR:I2C_ARBITRATION_LOST_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_ARBITRATION_LOST_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(50))
-		{
-		    FAPI_ERR("ERROR:I2C_NACK_RECIEVED_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_NACK_RECIEVED_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(53))
-		{
-		    FAPI_ERR("ERROR:I2C_STOP_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_STOP_ERR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(56))
-		{
-		    FAPI_ERR("ERROR:I2C_STOP_ERR");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PARITY_ERROR_BIT_SET);
-		    break;
-		}
-	    if(is_ready.isBitSet(57))
-		{
-		    FAPI_ERR("ERROR:CE_COUNTER_OVERFLOW_BIT_SET");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_CE_COUNTER_OVERFLOW_BIT_SET);
-		    break;
-		}
-
-	    //38:40
-	    uint16_t err32to47=is_ready.getHalfWord(2);
-	    uint16_t e_38_40=(err32to47 & 0x0380)>>7;
-	    if(e_38_40!=0)
-		{
-		    FAPI_ERR("ERROR:PIB_MASTER_RESP_INFO is not zero");
-		    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_MASTER_RESP_INFO_BITS_SET);
-		    break; 
-		}
-
-	    uint16_t e_41_43=(err32to47 & 0x0070)>>4;
-	    if(e_41_43!=0)
-		{
-		    if(e_41_43==4)//0b100
-			{
-			    FAPI_ERR("ERROR:PIB_CONTROL_REG_DATA_LGT_ERR, pib control reg data length error");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_CONTROL_REG_DATA_LGT_ERR);
-			    break;
-			}
-		    else if(e_41_43==5)//0b101
-			{
-			    FAPI_ERR("ERROR:PIB_CONTROL_REG_ADD LENGTH ERROR");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_CONTROL_REG_ADD_LGT_ERR);
-			    break;
-			}
-		    else if(e_41_43==6)//0b110)
-			{
-			    FAPI_ERR("ERROR:PIB_CONTROL_REG_ADDR_BDY_ERR, address boundary error");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_CONTROL_REG_ADDR_BDY_ERR);
-			    break;
-			}
-		    else if(e_41_43==7)//0b111)
-			{
-			    FAPI_ERR("ERROR:PIB_ECCADDR_REG_ERR");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_ECCADDR_REG_ERR);
-			    break;
-			}
-		    else if(e_41_43==2)//0b010)
-			{
-			    FAPI_ERR("ERROR:EFF_PIBM_RESET, pib master reset");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_EFF_PIBM_RESET);
-			    break;
-			}
-		    else if(e_41_43==1)//0b001)
-			{
-			    FAPI_ERR("ERROR:UCE_Q, uncorrectable ecc error");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_UEC_Q);
-			    break;
-			}
-		    else //0b011, 3
-			{
-			    FAPI_ERR("ERROR:reset from pib slave");
-			    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_PIB_SLAVE_RESET);
-			    break;
-			}
-
-		}
-	    
-	    //41:43 (100:data length error, 110:address boundary error,
-	    //010 pibmaster reset,  001 uncorrectable ecc error. 
-	}while(0);
-	return rc;
-	//*********************************************************************
-	///////////////////////////////////////////////////////////////////////
-
-    }
-
-
-
-
-    fapi::ReturnCode proc_read_seeprom(const fapi::Target & i_target,
-				       uint32_t & i_start_addr, uint32_t & i_length, bool & i_ecc_disable, uint64_t * return_data, bool & use_secondary)
-    {
-	fapi::ReturnCode rc;
-	uint32_t rc_ecmd=0;
-	//----------------------------Buffers-----------------------------------------------
-	//The buffer that set 000A0006 which we need to do before anything else 
-	ecmdDataBufferBase beginning_buff    = ecmdDataBufferBase (64);
-	//The buffer that will tell whether or not the data is ready to be read
-	ecmdDataBufferBase is_ready          = ecmdDataBufferBase (64);
-	//The buffer that will hold the data to be returned
-	ecmdDataBufferBase data              = ecmdDataBufferBase (64);
-	//The buffer that contains the value of the first time we call the control register
-	ecmdDataBufferBase control_reg_buff1 = ecmdDataBufferBase (64);
-	//The device_id buffer
-	ecmdDataBufferBase device_id_buff    = ecmdDataBufferBase (64);
-	//The port number buffer
-	ecmdDataBufferBase port_buff         = ecmdDataBufferBase (64);
-	//The address buffer
-	ecmdDataBufferBase address_buff      = ecmdDataBufferBase (64); 
-	//ECC Buffer
-	ecmdDataBufferBase ecc_buff          = ecmdDataBufferBase (64);
-	ecmdDataBufferBase vital_reg_buff    = ecmdDataBufferBase (64);
-
-
-	uint64_t clearallbits = 0x0000000000000000LLU;
-	uint64_t ecc_value; 
-	rc_ecmd|=data.setDoubleWord(0,clearallbits);
-	rc.setEcmdError(rc_ecmd);
-	if(!rc.ok())
-	    {
-		FAPI_ERR("proc_read_seeprom: Error 0x%x failed clearing data bits",rc_ecmd);
-		return rc;
-	    }
-
-	do 
-	{
-	    //Putting the value of the 000A0006 into the buffer 
-	    uint64_t beginning = 0x0003000100000000LLU; //bit_rate_devisor: 0x0003, wrap_mode bit31is 1
-	    beginning_buff.setDoubleWord(0, beginning);
-
-	    //Whether ecc is disabled(1) or not(0)
-	    if(i_ecc_disable){
-		ecc_value = 0x0000000000000000LLU;
-		FAPI_DBG("ecc disabled\n");
-	    }
-	    else{
-		ecc_value = 0x0000FFFF00001C78LLU; 
-		FAPI_DBG("ecc enabled\n");
-	    }
-	    
-	    //Put the ecc value into the ecc buffer
-	    rc_ecmd|=ecc_buff.setDoubleWord(0, ecc_value); 
-	    rc.setEcmdError(rc_ecmd);
-	    if(!rc.ok())
-		{
-		    FAPI_ERR("proc_read_seeprom: Error 0x%x failed clearing data bits",rc_ecmd);
-		    break;
-		}
-
-	    //Figure out how many times we will need to get data
-	    int num_times = i_length / 8 ; 
-    
-            uint64_t device_id =0; //seeprom device id
-            uint8_t di[2]={0,0}; //device id array to be filled by attribute
-            uint8_t pi[2]={0,0}; //port id array to be filled by attribute
-            rc=FAPI_ATTR_GET (ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS,&i_target,di);
-            if(rc)
-                {
-                    FAPI_ERR ("Problem doing fapi_attr_get on ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS");
-                }
-            rc=FAPI_ATTR_GET (ATTR_SBE_SEEPROM_I2C_PORT,&i_target,pi);
-            if(rc)
-                {
-                    FAPI_ERR ("Problem doing fapi_attr_get on ATTR_SBE_SEEPROM_I2C_PORT");
-                }
-            device_id= di[0]; //seeprom 1
-            if(use_secondary)
-                {
-                    device_id=di[1]; //secondary
-                }
-            FAPI_DBG ("Device ID: %llu\n",device_id);
-            device_id = device_id << 49; 
-	    rc_ecmd|=device_id_buff.setDoubleWord(0, device_id);
-	    rc.setEcmdError(rc_ecmd);
-	    if(!rc.ok())
-		{
-		    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting device_id_buff",rc_ecmd);
-		    break;
-		}
-	    //Put the value of the port number into the port buffer
-	    uint64_t port = pi[0]; // default port id;
-            if(use_secondary)
-            {
-                port=pi[1];
-            }
-            
-            FAPI_DBG ("Port: %llu\n", port);
-            port = port << 41;//41 (bit 18 to 22 is the port number);
-	    rc_ecmd|=port_buff.setDoubleWord(0, port);
-	    rc.setEcmdError(rc_ecmd);
-	    if(!rc.ok())
-		{
-		    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting port_buff",rc_ecmd);
-		    break;
-		}
-
-	    //Put the value of the address into the address buffer
-	    FAPI_DBG("i_start_addr: %08x\n",i_start_addr);
-	    uint64_t start_addr = i_start_addr << 16;
-	    rc_ecmd|=address_buff.setDoubleWord(0, start_addr); 
-	    rc.setEcmdError(rc_ecmd);
-	    if(!rc.ok())
-		{
-		    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting address_buff",rc_ecmd);
-		    break;
-		}
-	    
-	    //The base value of the first time that the control register is used 
-	    uint64_t control_reg_data1 = 0xD801008000000000LLU;
-	    //11011000<device ID>100<port number>010000000<register address> 
-         
-	    //Put the initial value of the control registers
-	    rc_ecmd|=control_reg_buff1.setDoubleWord (0, control_reg_data1);
-
-	    //Include the device id in the control registers
-	    rc_ecmd|=control_reg_buff1.merge(device_id_buff);
-
-	    //Include the port number in the control registers
-	    rc_ecmd|=control_reg_buff1.merge(port_buff);
-	
-	    //Include the starting address in the control registers
-	    rc_ecmd|=control_reg_buff1.merge(address_buff);
-
-	    rc.setEcmdError(rc_ecmd);
-	    if(!rc.ok())
-		{
-		    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting merging control_reg_buff1",rc_ecmd);
-		    break;
-		}
-	    
-
-
-	    //Set the ECC write or no ECC write
-	    rc = fapiPutScom(i_target, 0x000C0004, ecc_buff);
-	    if(rc)
-	    {
-		FAPI_ERR("Failed to perform fapiPutScom on ECC Address register 0x000C0004");
-		break;
-	    }
-	    //This is the Instruction Sequence to I2CM for Data Write
-	    //I got this from page 307 of the PervasiveWorkbook_P8.pdf
-	    rc = fapiPutScom(i_target, I2CM_MODE_REGISTER_0_0x000A0006, beginning_buff);
-	    if(rc)
-	    {
-		FAPI_ERR("Failed to perform fapiPutScom on MODE_REGISTER_0 0x000A0006");
-		break;
-	    }
-    
-            //Read Status Register
-	    int i = 0;
-	    for(i = 0; i < num_times; i++)
-		{
-		    if(i==0)//first read
-			{
-			    if(num_times==1)
-				{
-				    //printf("first time only\n");//add read conti if multiple read needed
-				    rc = fapiPutScom(i_target, PORE_ECCB_CONTROL_REGISTER_0x000C0000, control_reg_buff1); 
-				    if(rc)
-					{
-					    FAPI_ERR("Failed to perform fapiPutScom on PORE_ECCB_CONTROL_REGISTER 0x000C0000");
-					    break;
-					}
-				}
-			    else
-				{
-				    rc_ecmd|=control_reg_buff1.clearBit(3);//clear the withstop
-				    rc_ecmd|=control_reg_buff1.setBit(2);//set read cont
-				    
-				    rc.setEcmdError(rc_ecmd);
-				    if(!rc.ok())
-					{
-					    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting bit2/clearing bit3 of control_reg_buff1",rc_ecmd);
-					    break;
-					}
-				    FAPI_DBG("control: %016llx\n",control_reg_buff1.getDoubleWord(0));
-				    rc = fapiPutScom(i_target, PORE_ECCB_CONTROL_REGISTER_0x000C0000, control_reg_buff1); 
-				    if(rc)
-					{
-					    FAPI_ERR("Failed to perform fapiPutScom on PORE_ECCB_CONTROL_REGISTER 0x000C0000");
-					    break;
-					}
-				}
-			    
-			}
-		    else if(i==num_times-1)//last read, wstart=0, wa=0, wrc=0,wstop=1, 0  for 23:25, 0 for 32:63
-			{
-			    rc_ecmd|=control_reg_buff1.clearBit(0);
-			    rc_ecmd|=control_reg_buff1.clearBit(1);
-			    rc_ecmd|=control_reg_buff1.clearBit(2);
-			    rc_ecmd|=control_reg_buff1.setBit(3);
-			    rc_ecmd|=control_reg_buff1.setAnd((uint32_t)0,23,3);//clearbit(,)
-			    rc_ecmd|=control_reg_buff1.setAnd((uint32_t)0,32,32);
-			    rc.setEcmdError(rc_ecmd);
-			    if(!rc.ok())
-				{
-				    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting/clearing bits",rc_ecmd);
-				    break;
-				}
-			    FAPI_DBG("control: %016llx\n",control_reg_buff1.getDoubleWord(0));
-							    
-			    rc = fapiPutScom(i_target, PORE_ECCB_CONTROL_REGISTER_0x000C0000, control_reg_buff1);
-			    if(rc)
-				{
-				    FAPI_ERR("Failed to perform fapiPutScom on PORE_ECCB_CONTROL_REGISTER 0x000C0000");
-				    break;
-				}
-			}
-		    else //other
-			{
-			    rc_ecmd|=control_reg_buff1.clearBit(0);
-			    rc_ecmd|=control_reg_buff1.clearBit(1);
-			    rc_ecmd|=control_reg_buff1.setBit(2);
-			    rc_ecmd|=control_reg_buff1.clearBit(3);
-			    rc_ecmd|=control_reg_buff1.setAnd((uint32_t)0,23,3);
-			    rc_ecmd|=control_reg_buff1.setAnd((uint32_t)0,32,32);
-			    rc.setEcmdError(rc_ecmd);
-			    if(!rc.ok())
-				{
-				    FAPI_ERR("proc_read_seeprom: Error 0x%x failed setting/clearing bits",rc_ecmd);
-				    break;
-				}
-			    FAPI_DBG("control: %016llx\n",control_reg_buff1.getDoubleWord(0));
-
-			    rc = fapiPutScom(i_target, PORE_ECCB_CONTROL_REGISTER_0x000C0000, control_reg_buff1); 
-			    if(rc)
-				{
-				    FAPI_ERR("Failed to perform fapiPutScom on PORE_ECCB_CONTROL_REGISTER 0x000C0000");
-				    break;
-				}
-				   
-			}			    
-		    //Wait until the value is ready to be collected 
-		    bool is_not_complete = true; 
-		    uint16_t counter=0;
-		    while(is_not_complete)
-			{
-			    counter++;
-			    //printf( "counter: %d\n",counter);
-			    rc = fapiGetScom(i_target, PORE_ECCB_STATUS_REGISTER_READ_0x000C0002, is_ready);
-			    if(rc)
-				{
-				    FAPI_ERR("Failed to perform fapiGetScom on PORE_ECCB_STATUS_REGISTER 0x000C0002");
-				    break;
-				}
-			    rc=check_status_register_errors(is_ready);
-			    if(rc) break;
-			    if(!is_ready.isBitSet(44))
-				{
-				    is_not_complete = false;
-				    if(is_ready.isBitClear(52))
-					{
-					    FAPI_ERR("ERROR:I2C_COMMAND_COMPLETE is not set after bit 44 is cleared");
-					    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_COMMAND_COMPLETE_NOT_SET);
-					    break;  
-					}
-				}
-			    rc=fapiDelay(LOOP_DELAY_TIME,LOOP_DELAY_CYCLE);
-			    if (rc) break;
-
-			    if(counter>TIMEOUT_LIMIT)
-				{
-				    FAPI_SET_HWP_ERROR(rc,RC_PROC_READ_SEEPROM_I2C_COMMAND_COMPLETE_TIME_OUT);
-				    FAPI_ERR("ERROR: I2C_COMMAND_COMPLETE not set, TIME OUT");
-				    break;
-				}
-			}
-		    if(rc)
-			{
-			    FAPI_ERR("ECCB Status Register reported an error");
-			    break;
-			}
-		    //Read Data Register
-		    rc = fapiGetScom(i_target, PORE_ECCB_DATA_REGISTER_0x000C0003, data);
-		    if(rc)
-			{
-			    FAPI_ERR("Failed to perform fapiGetScom on PORE_ECCB_DATA_REGISTER 0x000C0003");
-			    break;
-			}
-		    uint64_t data_temp = data.getDoubleWord (0);
-		    FAPI_INF ("Byte - 0x%4x, data: %016llx\n",i*8,data_temp);
-		    *return_data = data_temp;
-		    //Increment the array pointer that will get passed back
-		    return_data++;
-		}
-	}while(0);
-	return rc; 
-	
-    }
-} // extern "C"
-/* Local Variables: */
-/* c-basic-offset: 4 */
-/* End: */
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.H
deleted file mode 100644
index cf96592cf..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.H
+++ /dev/null
@@ -1,84 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_read_seeprom.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_read_seeprom.H,v 1.4 2013/06/06 20:45:13 cswenson Exp $
-/* File proc_read_seeprom.H created by KUHFAL, CHRISTINA L. (CHRISTY) on Thu Jun 21 2012. */
-
-/* Change Activity: */
-/* End Change Activity */
-
-#ifndef _PROC_READ_SEEPROM_H
-#define _PROC_READ_SEEPROM_H
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_read_seeprom_FP_t)(const fapi::Target &,
-						   uint32_t &, uint32_t &, bool &, uint64_t *, bool &);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * @Read seeprom_0 or seeprom_1
- *
- * @param[in] i_target      Reference to processor chip target
- * @param[in] i_start_addr  The starting address to begin reading the seeprom
- * @param[in] i_length The  Length that is to be read from seeprom
- * @param[in] i_ecc_disable True if ecc is to be disabled false otherwise
- * @param[in] return_data   Data returned to the wrapper
- * @param[in] use_secondary True if secondary seeprom is to used, false otherwise
- * @return ReturnCode
- */
-   fapi::ReturnCode proc_read_seeprom(const fapi::Target & i_target,
-				      uint32_t & i_start_addr, uint32_t & i_length, bool & i_ecc_disable, uint64_t * return_data, bool & use_secondary);  
-
-} // extern "C"
-
-#endif /* _PROC_READ_SEEPROM_H */
-
-/* Change Log
-<@log@>
-
-Fri Jul 27 2012  08:29:15  by KUHFAL, CHRISTINA L. (CHRISTY)
-<reason><version><Brief description and why change was made.>
-
-Fri Jun 22 2012  14:22:35  by KUHFAL, CHRISTINA L. (CHRISTY)
-<reason><version><Brief description and why change was made.>
-
-Thu Jun 21 2012  10:02:20  by KUHFAL, CHRISTINA L. (CHRISTY)
-<reason><version><Brief description and why change was made.>
-*/
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.C b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.C
deleted file mode 100644
index 7bba17e1b..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.C
+++ /dev/null
@@ -1,107 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_reset_i2cm_bus_fence.C,v 1.1 2014/02/18 19:53:44 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_reset_i2cm_bus_fence.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_reset_i2cm_bus_fence.C
-// *! DESCRIPTION : Clear i2cm bus fence to restore FSP access (FAPI)
-// *!
-// *! OWNER NAME : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <proc_reset_i2cm_bus_fence.H>
-#include <p8_scom_addresses.H>
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-const uint32_t CFAM_FSI_GP4_I2CM_BUS_FENCE_BIT = 20;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C" {
-
-// HWP entry point, comments in header
-fapi::ReturnCode proc_reset_i2cm_bus_fence(const fapi::Target & i_target)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-    ecmdDataBufferBase cfam_data(32);
-
-    // mark HWP entry
-    FAPI_INF("proc_reset_i2cm_bus_fence: Start");
-
-    do
-    {
-        // read FSI GP4
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP4_0x00002813, cfam_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_reset_i2cm_bus_fence: Error from fapiGetCfamRegister (CFAM_FSI_GP4_0x00002813)");
-            break;
-        }
-
-        // clear fence bit
-        rc_ecmd |= cfam_data.clearBit(CFAM_FSI_GP4_I2CM_BUS_FENCE_BIT);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_reset_i2cm_bus_fence: Error 0x%x forming FSI GP4 register write data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // write back modified data
-        rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP4_0x00002813, cfam_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_reset_i2cm_bus_fence: Error from fapiGetCfamRegister (CFAM_FSI_GP4_0x00002813)");
-            break;
-        }
-
-    } while(0);
-
-    // mark HWP exit
-    FAPI_INF("proc_reset_i2cm_bus_fence: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.H
deleted file mode 100644
index 54ac54ad1..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.H
+++ /dev/null
@@ -1,77 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_reset_i2cm_bus_fence.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014                             */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_reset_i2cm_bus_fence.H,v 1.1 2014/02/18 19:53:45 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_reset_i2cm_bus_fence.H,v $
-///------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_reset_i2cm_bus_fence.C
-// *! DESCRIPTION : Clear i2cm bus fence to restore FSP access (FAPI)
-// *!
-// *! OWNER NAME : Joe McGill        Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef PROC_RESET_I2CM_BUS_FENCE_H_
-#define PROC_RESET_I2CM_BUS_FENCE_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_reset_i2cm_bus_fence_FP_t)(const fapi::Target & i_target);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-/**
- * @brief HWP which clears i2cm bus fence to restore FSP access in the case of
- *        an SBE engine failure
- *
- * @param[in] i_target Reference to processor chip target
- *
- * @return ReturnCode
- */
-fapi::ReturnCode proc_reset_i2cm_bus_fence(const fapi::Target & i_target);
-
-
-} // extern "C"
-
-#endif // PROC_RESET_I2CM_BUS_FENCE_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H
deleted file mode 100644
index 1df4169d9..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H
+++ /dev/null
@@ -1,39 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_check_master.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_check_master.H,v 1.3 2013/10/03 20:53:15 jeshua Exp $
-
-/// Substep numbers for proc_sbe_check_master
-
-#ifndef __PROC_SBE_CHECK_MASTER_H
-#define __PROC_SBE_CHECK_MASTER_H
-
-#include "fapi_sbe_common.H"
-#include "sbe_vital.H"
-
-CONST_UINT8_T(SUBSTEP_CHECK_MASTER_PROC_ENTRY,           ULL(0x0));
-//NOTE: The slave chip substep value can never change, because HB checks for it
-CONST_UINT8_T(SUBSTEP_CHECK_MASTER_SLAVE_CHIP,           ULL(0x1));
-CONST_UINT8_T(SUBSTEP_CHECK_MASTER_MASTER_CHIP,          ULL(0x2));
-
-
-#endif  // __PROC_SBE_CHECK_MASTER_H
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_enable_pnor.H b/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_enable_pnor.H
deleted file mode 100644
index 80c23c18d..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_enable_pnor.H
+++ /dev/null
@@ -1,38 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_check_slave_sbe_seeprom_complete/proc_sbe_enable_pnor.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_sbe_enable_pnor.H,v 1.2 2014/06/08 19:18:37 jmcgill Exp $
-
-/// Substep numbers for proc_sbe_enable_pnor
-
-#ifndef __PROC_SBE_ENABLE_PNOR_H
-#define __PROC_SBE_ENABLE_PNOR_H
-
-#include "fapi_sbe_common.H"
-#include "sbe_vital.H"
-
-CONST_UINT8_T(SUBSTEP_ENABLE_PNOR_PROC_ENTRY,    ULL(0x0));
-CONST_UINT8_T(SUBSTEP_ENABLE_PNOR_SLAVE_CHIP,    ULL(0x1));
-CONST_UINT8_T(SUBSTEP_ENABLE_PNOR_MASTER_CHIP,   ULL(0x2));
-
-
-#endif  // __PROC_SBE_ENABLE_PNOR_H
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C b/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C
deleted file mode 100644
index bafa8aa55..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C
+++ /dev/null
@@ -1,219 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.C $      */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_getecid.C,v 1.11 2015/05/14 21:14:31 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_getecid.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_getecid.C
-// *! DESCRIPTION : Get ECID string from target using SCOM
-// *!
-// *! OWNER NAME  : Joe McGill     Email: jmcgill@us.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <proc_getecid.H>
-#include <proc_check_security.H>
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-// OTPROM mode register field/bit definitions
-const uint32_t OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT = 1;
-
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-
-// HWP entry point
-fapi::ReturnCode proc_getecid(
-    const fapi::Target& i_target,
-    ecmdDataBufferBase& io_fuseString)
-{
-    // return code
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-    uint64_t attr_data[2];
-    bool secure_mode = false;
-
-    // mark HWP entry
-    FAPI_DBG("proc_getecid: Start");
-
-    // data buffers
-    io_fuseString.setBitLength(112); // sets size and zeros out buffer
-    ecmdDataBufferBase security_switch_data(64);
-    ecmdDataBufferBase otprom_mode_data(64);
-    ecmdDataBufferBase ecid_data(64);
-
-    do
-    {
-        //
-        // determine if security is enabled
-        //
-
-        FAPI_EXEC_HWP(rc, proc_check_security, i_target, secure_mode);
-        if (!rc.ok())
-        {
-            FAPI_ERR("Error from proc_check_security");
-            break;
-        }
-
-        //
-        // clear ECC enable before reading ECID data (read-modify-write OTPROM Mode register), insecure mode only
-        //
-
-        if (!secure_mode)
-        {
-
-            rc = fapiGetScom(i_target, OTPC_M_MODE_REGISTER_0x00010008, otprom_mode_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_getecid: fapiGetScom error (OTPC_M_MODE_REGISTER_0x00010008) for %s",
-                         i_target.toEcmdString());
-                break;
-            }
-
-            rc_ecmd |= otprom_mode_data.clearBit(OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_getecid: Error 0x%X setting up OTPROM Mode register data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            rc = fapiPutScom(i_target, OTPC_M_MODE_REGISTER_0x00010008, otprom_mode_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_getecid: fapiPutScom error (OTPC_M_MODE_REGISTER_0x00010008) for %s",
-                         i_target.toEcmdString());
-                break;
-            }
-        }
-
-        //
-        // extract and manipulate ECID data
-        //
-
-        rc = fapiGetScom(i_target, ECID_PART_0_0x00018000, ecid_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_getecid: fapiGetScom error (ECID_PART_0_0x00018000) for %s",
-                     i_target.toEcmdString());
-            break;
-        }
-
-        // 0:63 become 63:0
-        rc_ecmd |= ecid_data.reverse();
-        // copy bits 0:63 from the scom into 0:63 of the fuseString/attribute data
-        rc_ecmd |= io_fuseString.insert(ecid_data,  0, 64);
-        attr_data[0] = ecid_data.getDoubleWord(0);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_getecid: Error 0x%X processing ECID (part 0) data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiGetScom(i_target, ECID_PART_1_0x00018001, ecid_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_getecid: fapiGetScom error (ECID_PART_1_0x00018001) for %s",
-                     i_target.toEcmdString());
-            break;
-        }
-
-        // 0:63 become 63:0
-        rc_ecmd |= ecid_data.reverse();
-        // copy bits 0:47 from the scom into 64:111 of the fuseString
-        // all bits into attribute data
-        rc_ecmd |= io_fuseString.insert(ecid_data, 64, 48);
-        attr_data[1] = ecid_data.getDoubleWord(0);
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_getecid: Error 0x%X processing ECID (part 1) data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        // push fuse string into attribute
-        rc = FAPI_ATTR_SET(ATTR_ECID,
-                           &i_target,
-                           attr_data);
-        if (!rc.ok())
-        {
-            FAPI_ERR("proc_getecid: Error from FAPI_ATTR_SET (ATTR_ECID) for %s (attr_data[0] = %016llX, attr_data[1] = %016llX",
-                     i_target.toEcmdString(), attr_data[0], attr_data[1]);
-            break;
-        }
-
-        //
-        // restore ECC enable setting (insecure mode only)
-        //
-
-        if (!secure_mode)
-        {
-            rc_ecmd |= otprom_mode_data.setBit(OTPC_M_MODE_REGISTER_ECC_ENABLE_BIT);
-            if (rc_ecmd)
-            {
-                FAPI_ERR("proc_getecid: Error 0x%X setting up OTPROM Mode register data buffer",
-                         rc_ecmd);
-                rc.setEcmdError(rc_ecmd);
-                break;
-            }
-
-            rc = fapiPutScom(i_target, OTPC_M_MODE_REGISTER_0x00010008, otprom_mode_data);
-            if (!rc.ok())
-            {
-                FAPI_ERR("proc_getecid: fapiPutScom error (OTPC_M_MODE_REGISTER_0x00010008) for %s",
-                         i_target.toEcmdString());
-                break;
-            }
-        }
-
-    } while(0);
-
-    // mark HWP exit
-    FAPI_DBG("proc_getecid: End");
-    return rc;
-}
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H b/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H
deleted file mode 100644
index 5f849269c..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H
+++ /dev/null
@@ -1,79 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_getecid/proc_getecid.H $      */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_getecid.H,v 1.8 2014/10/03 21:56:49 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/utils/proc_getecid.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2011
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_getecid.H
-// *! DESCRIPTION : Get ECID string from target using SCOM
-// *!
-// *! OWNER NAME  : Joe McGill     Email: jmcgill@us.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS:
-// *!
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_GETECID_H_
-#define _PROC_GETECID_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-#include "p8_scom_addresses.H"
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_getecid_FP_t)(const fapi::Target&, ecmdDataBufferBase& fuseString);
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-// function: FAPI proc_getecid HWP entry point
-// parameters: i_target      => P8 chip target
-//             io_fuseString => ecmdDataBuffer which will return ECID data
-//                              (also written to ATTR_ECID)
-// returns: FAPI_RC_SUCCESS if successful, else error
-fapi::ReturnCode proc_getecid(
-    const fapi::Target& i_target,
-    ecmdDataBufferBase& io_fuseString);
-
-} // extern "C"
-
-#endif // _PROC_GETECID_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.C b/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.C
deleted file mode 100644
index 9ead7810e..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.C
+++ /dev/null
@@ -1,216 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_spless_sbe_startWA.C,v 1.2 2015/08/05 14:19:34 baiocchi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_spless_sbe_startWA.C,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_spless_sbe_startWA.C
-// *! DESCRIPTION : Issue workaround for CFAM Reset SBE start (FAPI)
-// *!
-// *! OWNER  NAME  : Benedikt Geukes         Email: benedikt.geukes@de.ibm.com
-// *! BACKUP NAME  : Ralph Koester           Email: rkoester@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include "proc_spless_sbe_startWA.H"
-#include "p8_scom_addresses.H"
-#include "p8_mailbox_utils.H"
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C"
-{
-
-
-//------------------------------------------------------------------------------
-// Hardware Procedure
-//------------------------------------------------------------------------------
-// parameters: i_target            => chip target (S1/P8)
-//             i_sbeSeepromSelect  => SBE Seeprom Select Bit
-// returns:    FAPI_RC_SUCCESS if operation was successful, else error
-//------------------------------------------------------------------------------
-fapi::ReturnCode proc_spless_sbe_startWA(const fapi::Target & i_target,
-                                         const bool  i_sbeSeepromSelect)
-{
-
-    uint32_t           rc_ecmd = 0;
-    fapi::ReturnCode   rc;
-    uint32_t           l_set_data;
-    ecmdDataBufferBase  set_data(32);
-
-    // mark start of function
-    FAPI_INF("proc_spless_sbe_startWA: Enter: i_sbeSeepromSelect=%d", i_sbeSeepromSelect);
-
-    do {
-
-        // -----------------------------------------------------------
-        //Need to set the I2C speed based in the mailbox reg
-        //Since not all 1.x part have the correctly programmed OTPROM
-        rc = p8_mailbox_utils_get_mbox2( i_target, l_set_data );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: get_mbox2 = 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-        rc_ecmd |= set_data.setWord( 0, l_set_data );
-
-        FAPI_INF(   "Write 0x%08x to mbox scratch 2",
-                    set_data.getWord(0)   );
-
-        // write it to mbox scratch2
-        rc = fapiPutCfamRegister( i_target,
-                                  MBOX_SCRATCH_REG1_0x00002839,
-                                  set_data    );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: write MBOX_SCRATCH_REG1_0x00002839= 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-
-        // ------------------------------------------------
-        // Enable output to ATTN pin to monitor for checkstops (3 commands)
-        // - putcfam pu 0x081C 20000000
-        FAPI_INF(   "Enable output to ATTN pin to monitor for checkstops");
-
-        rc_ecmd |= set_data.setWord( 0, 0x20000000 );
-
-        rc = fapiPutCfamRegister( i_target,
-                                  CFAM_FSI_INTR_MASK_0x0000081C,
-                                  set_data    );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: write CFAM_FSI_INTR_MASK_0x0000081C= 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-        // - putcfam pu 0x100D 40000000
-        rc_ecmd |= set_data.setWord( 0, 0x40000000 );
-
-        rc = fapiPutCfamRegister( i_target,
-                                  CFAM_FSI_TRUE_MASK_0x0000100D,
-                                  set_data    );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: write CFAM_FSI_TRUE_MASK_0x0000100D= 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-
-        // - putcfam pu  0x100B FFFFFFFF
-        rc_ecmd |= set_data.setWord( 0, 0xFFFFFFFF );
-
-        rc = fapiPutCfamRegister( i_target,
-                                  CFAM_FSI_INTR_STATUS_0x0000100B,
-                                  set_data    );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: write CFAM_FSI_INTR_STATUS_0x0000100B= 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-
-
-        // -----------------------------------------------
-        // Now toggle Warmstart bit to circumvent HW254584
-        // -- set bit 8 to select SBE Image to boot from
-        if (i_sbeSeepromSelect == true)
-        {
-            rc_ecmd |= set_data.setWord( 0, 0x30800000 );
-        }
-        else
-        {
-            rc_ecmd |= set_data.setWord( 0, 0x30000000 );
-        }
-        FAPI_INF(   "Write 0x%08x to SBE VITAL to toggle Warmstart bit",
-                    set_data.getWord(0)   );
-
-        rc = fapiPutCfamRegister( i_target,
-                                  CFAM_FSI_SBE_VITAL_0x0000281C,
-                                  set_data    );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: write CFAM_FSI_SBE_VITAL_0x0000281C= 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-        // -----------------------------------------------
-        // Now start SBE
-        // -- set bit 8 to select SBE Image to boot from
-        if (i_sbeSeepromSelect == true)
-        {
-            rc_ecmd |= set_data.setWord( 0, 0xB0800000 );
-        }
-        else
-        {
-            rc_ecmd |= set_data.setWord( 0, 0xB0000000 );
-        }
-
-        FAPI_INF(   "Write 0x%08x to SBE VITAL start SBE",
-                    set_data.getWord(0)   );
-
-        rc = fapiPutCfamRegister( i_target,
-                                  CFAM_FSI_SBE_VITAL_0x0000281C,
-                                  set_data    );
-        if (rc)
-        {
-            FAPI_ERR("ERROR: write CFAM_FSI_SBE_VITAL_0x0000281C= 0x%08x",
-                     static_cast<uint32_t>(rc) );
-            break;
-        }
-
-        if(rc_ecmd)
-        {
-            FAPI_ERR( "Error (0x%08x) writing value to set_data",
-                      rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-    } while(0);  // end do
-
-    // mark function exit
-    FAPI_INF("proc_spless_sbe_startWA: Exit");
-    return rc;
-}  // end FAPI procedure proc_spless_sbe_startWA
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.H b/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.H
deleted file mode 100644
index 29552ff54..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.H
+++ /dev/null
@@ -1,89 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_spless_sbe_startWA/proc_spless_sbe_startWA.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_spless_sbe_startWA.H,v 1.1 2015/08/04 22:04:52 baiocchi Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_spless_sbe_startWA.H,v $
-//------------------------------------------------------------------------------
-// *|
-// *! (C) Copyright International Business Machines Corp. 2013
-// *! All Rights Reserved -- Property of IBM
-// *! ***  ***
-// *|
-// *! TITLE       : proc_spless_sbe_startWA.C
-// *! DESCRIPTION : Issue workaround for CFAM Reset SBE start (FAPI)
-// *!
-// *! OWNER  NAME  : Benedikt Geukes         Email: benedikt.geukes@de.ibm.com
-// *! BACKUP NAME  : Ralph Koester           Email: rkoester@de.ibm.com
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef _PROC_SPLESS_SBE_STARTWA_H_
-#define _PROC_SPLESS_SBE_STARTWA_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-
-#include <fapi.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode (*proc_spless_sbe_startWA_FP_t)(const fapi::Target &,
-                                                         const bool );
-
-
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-
-extern "C"
-{
-
-/**
- * @brief Issue workaround for SPless slave chips (ie started by CFAM Reset)
- *        Note this only applies to DD1.x parts (both murano/venice)
- *        The master chip is started by the FPGA, but the slaves need to be
- *        started by Hostboot
- *
- * @param[in] i_target            chip target
- * @param[in] i_sbeSeepromSelect  SBE Seeprom Select Bit:
- *                                if false then first image; otherwise 2nd image
- *
- * @return ReturnCode
- */
-  fapi::ReturnCode proc_spless_sbe_startWA(const fapi::Target & i_target,
-                                           const bool  i_sbeSeepromSelect);
-
-} // extern "C"
-
-#endif // _PROC_SPLESS_SBE_STARTWA_H_
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C b/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C
deleted file mode 100644
index 4ff333420..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C
+++ /dev/null
@@ -1,285 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.C $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_tp_collect_dbg_data.C,v 1.7 2014/10/03 20:25:36 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_tp_collect_dbg_data.C,v $
-//------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_tp_collect_dbg_data.C
-// *! DESCRIPTION : Procedure to collect TP debug data
-// *!
-// *! OWNER NAME : Benedikt Geukes        Email: bgeukes@de.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-
-//------------------------------------------------------------------------------
-//  Includes
-//------------------------------------------------------------------------------
-#include <proc_tp_collect_dbg_data.H>
-#include <utility>
-//------------------------------------------------------------------------------
-// Constant definitions
-//------------------------------------------------------------------------------
-
-const uint32_t PROC_TP_COLLECT_DBG_DATA_FSI_SHIFT_CTRL 	= 0x00000043;
-const uint32_t PERV_VITL_CHAIN_RING_ADDRESS = 0x0103800C;
-const uint32_t TP_VITL_SPY_MAX_SPY_RANGES = 24;
-
-
-//------------------------------------------------------------------------------
-// Function definitions
-//------------------------------------------------------------------------------
-
-extern "C" {
-
-// HWP entry point, comments in header
-fapi::ReturnCode proc_tp_collect_dbg_data(const fapi::Target & i_target,
-                                          fapi::ReturnCode & o_rc)
-{
-    fapi::ReturnCode rc;
-    uint32_t rc_ecmd = 0;
-
-	ecmdDataBufferBase ring_data;
-    ecmdDataBufferBase spy_data;
-    uint32_t ring_length;
-    uint32_t spy_length;
-    uint32_t spy_offsets[TP_VITL_SPY_MAX_SPY_RANGES];
-	ecmdDataBufferBase fsi_data(32);
-	ecmdDataBufferBase scom_data(64);
-
-    // mark HWP entry
-    FAPI_INF("proc_tp_collect_dbg_data: Start");
-
-    do
-    {
-		// Setting Prevent AutoStart Bit to avoid scan chain corruption
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_SBE_VITAL_0x0000281c)");
-            break;
-        }
-        
-        rc_ecmd |= fsi_data.setBit(1);
-        rc_ecmd |= fsi_data.setBit(3);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI SBE Vital Register",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutCfamRegister(i_target, CFAM_FSI_SBE_VITAL_0x0000281C, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_SBE_VITAL_0x0000281C)");
-            break;
-        }
-		
-		
-        // Setting FSI Shift Speed
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, fsi_data);
-        if (rc)
-        {
-        	FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_SHIFT_CTRL_0x00000C10)");
-            break;
-        }
-        
-        rc_ecmd |= fsi_data.setWord(0,PROC_TP_COLLECT_DBG_DATA_FSI_SHIFT_CTRL);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI SHIFT CTRL register data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        rc = fapiPutCfamRegister(i_target, CFAM_FSI_SHIFT_CTRL_0x00000C10, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_SHIFT_CTRL_0x00000C10)");
-            break;
-        }
-        
-        // Changing Fences for Vital scan
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_0x00002812, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_GP3_0x00002812)");
-            break;
-        }
-        
-        rc_ecmd |= fsi_data.clearBit(23);
-        rc_ecmd |= fsi_data.setBit(24);
-        rc_ecmd |= fsi_data.setBit(25);
-        rc_ecmd |= fsi_data.setBit(26);
-        rc_ecmd |= fsi_data.clearBit(27);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI GP3 data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        
-        rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_0x00002812, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_GP3_0x00002812)");
-            break;
-        }
-        
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
-            break;
-        }
-        
-        rc_ecmd |= fsi_data.setBit(16);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI GP3 MIRROR data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        
-        rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
-            break;
-        }
-        
-        rc = fapiGetCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiGetCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
-            break;
-        }
-        
-        rc_ecmd |= fsi_data.setBit(26);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x setting up FSI GP3 MIRROR data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        
-        rc = fapiPutCfamRegister(i_target, CFAM_FSI_GP3_MIRROR_0x0000281B, fsi_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: fapiPutCfamRegister error (CFAM_FSI_GP3_MIRROR_0x0000281B)");
-            break;
-        }
-
-        // obtain ring/spy attribute data
-        rc = FAPI_ATTR_GET(ATTR_PROC_PERV_VITL_LENGTH, &i_target, ring_length);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error from FAPI_ATTR_GET (ATTR_PROC_PERV_VITL_LENGTH)");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_TP_VITL_SPY_LENGTH, &i_target, spy_length);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error from FAPI_ATTR_GET (ATTR_PROC_TP_VITL_SPY_LENGTH)");
-            break;
-        }
-
-        rc = FAPI_ATTR_GET(ATTR_PROC_TP_VITL_SPY_OFFSETS, &i_target, spy_offsets);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error from FAPI_ATTR_GET (ATTR_PROC_TP_VITL_SPY_OFFSETS)");
-            break;
-        }
-
-        rc_ecmd |= ring_data.setBitLength(ring_length);
-        rc_ecmd |= spy_data.setBitLength(spy_length);
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x sizing FFDC data buffers",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-        
-        // collect data from ring
-        rc = fapiGetRing(i_target, PERV_VITL_CHAIN_RING_ADDRESS, ring_data);
-        if (rc)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error from fapiGetRing (PERV_VITL_CHAIN)");
-            break;
-        }
-
-        // extract spy data from ring image
-        uint32_t spy_offset_curr = 0;
-        for (uint32_t spy_offset_index = 0;
-             spy_offset_index < TP_VITL_SPY_MAX_SPY_RANGES;
-             spy_offset_index++)
-        {
-            if (spy_offsets[spy_offset_index] == 0xFFFFFFFF)
-            {
-                break;
-            }
-
-            uint32_t first = ((spy_offsets[spy_offset_index] >> 16) & 0xFFFF);
-            uint32_t second = (spy_offsets[spy_offset_index] & 0xFFFF);
-
-            uint32_t chunk_size = (second - first + 1);
-            rc_ecmd |= spy_data.insert(ring_data,
-                                       spy_offset_curr,
-                                       chunk_size,
-                                       first);
-            spy_offset_curr += chunk_size;
-        }
-
-        if (rc_ecmd)
-        {
-            FAPI_ERR("proc_tp_collect_dbg_data: Error 0x%x forming FFDC spy data buffer",
-                     rc_ecmd);
-            rc.setEcmdError(rc_ecmd);
-            break;
-        }
-
-        ecmdDataBufferBase & VITL_DATA = spy_data;
-        FAPI_ADD_INFO_TO_HWP_ERROR(o_rc, RC_TP_COLLECT_DBG_DATA);
-
-    } while(0);
-
-    // mark HWP exit
-    FAPI_INF("proc_tp_collect_dbg_data: End");
-    return rc;
-}
-
-
-} // extern "C"
diff --git a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H b/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H
deleted file mode 100644
index a9b0092a4..000000000
--- a/src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H
+++ /dev/null
@@ -1,78 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/slave_sbe/proc_tp_collect_dbg_data/proc_tp_collect_dbg_data.H $ */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: proc_tp_collect_dbg_data.H,v 1.3 2014/03/10 16:09:15 jmcgill Exp $
-// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_tp_collect_dbg_data.H,v $
-///------------------------------------------------------------------------------
-// *! (C) Copyright International Business Machines Corp. 2012
-// *! All Rights Reserved -- Property of IBM
-//------------------------------------------------------------------------------
-// *! TITLE       : proc_tp_collect_dbg_data.C
-// *! DESCRIPTION : Header file for procedure to collect TP debug data
-// *!
-// *! OWNER NAME : Benedikt Geukes        Email: bgeukes@de.ibm.com
-// *!
-// *! ADDITIONAL COMMENTS :
-// *!
-//------------------------------------------------------------------------------
-
-#ifndef PROC_TP_COLLECT_DBG_DATA_H_
-#define PROC_TP_COLLECT_DBG_DATA_H_
-
-//------------------------------------------------------------------------------
-// Includes
-//------------------------------------------------------------------------------
-#include <fapi.H>
-#include <p8_scom_addresses.H>
-#include <common_scom_addresses.H>
-
-//------------------------------------------------------------------------------
-// Structure definitions
-//------------------------------------------------------------------------------
-
-// function pointer typedef definition for HWP call support
-typedef fapi::ReturnCode
-(*proc_tp_collect_dbg_data_FP_t)(const fapi::Target &, fapi::ReturnCode &);
-
-extern "C" {
-
-//------------------------------------------------------------------------------
-// Function prototypes
-//------------------------------------------------------------------------------
-
-/**
- * @brief HWP to collect TP debug data for fails during various IPL steps 
- *        
- *
- * @param[in]  i_target Reference to processor chip target
- * @param[out] o_rc     Reference to return code (for appending of FFDC)
- *
- * @return ReturnCode
- */
-fapi::ReturnCode proc_tp_collect_dbg_data(const fapi::Target & i_target, fapi::ReturnCode & o_rc);
-
-
-} // extern "C"
-
-#endif // PROC_TP_COLLECT_DBG_DATA_H_
diff --git a/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C b/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C
deleted file mode 100644
index 998941e2e..000000000
--- a/src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C
+++ /dev/null
@@ -1,590 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/spd_accessors/getSpdAttrAccessor.C $         */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2013,2014                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-// $Id: getSpdAttrAccessor.C,v 1.3 2014/08/05 15:04:52 kahnevan Exp $
-/**
- *  @file getSpdAttrAccessor.C
- *
- *  @brief Accessor HWP that gets DDR neutral DIMM SPD FAPI Attribute data
- *
- */
-
-#include <stdint.h>
-#include <fapi.H>
-#include <getSpdAttrAccessor.H>
-
-namespace fapi
-{
-    namespace getSpdAttr
-    {
-        enum DdrType
-        {
-            DDR3 = 1,
-            DDR4 = 2,
-        };
-    }
-}
-
-extern "C"
-{
-
-/**
- * @brief Checks the user's buffer size
- *
- * @param[in] i_attr         Attribute ID (just used for tracing)
- * @param[in] i_actualSize   Actual buffer size
- * @param[in] i_expectedSize Expected buffer size
- *
- * @return fapi::ReturnCode Indicating success or error
- */
-fapi::ReturnCode checkSize(const fapi::getSpdAttr::Attr i_attr,
-                           const size_t i_actualSize,
-                           const size_t i_expectedSize)
-{
-    fapi::ReturnCode l_rc;
-
-    if (i_actualSize != i_expectedSize)
-    {
-        FAPI_ERR("getSpdAttrAccessor: Incorrect Attribute output buffer size %d:%zd:%zd",
-                 i_attr, i_actualSize, i_expectedSize);
-        const fapi::getSpdAttr::Attr & ATTR_ID = i_attr;
-        const size_t & ACTUAL_SIZE = i_actualSize;
-        const size_t & EXPECTED_SIZE = i_expectedSize;
-        FAPI_SET_HWP_ERROR(l_rc, RC_GET_SPD_ACCESSOR_INVALID_OUTPUT_SIZE);
-    }
-
-    return l_rc;
-}
-
-/**
- * @brief Returns the DIMM DDR Type
- *
- * This function only supports DDR3 and DDR4
- *
- * @param[in]  i_dimm Reference to DIMM fapi target.
- * @param[out] o_type Filled in with the DIMM DDR Type.
- *
- * @return fapi::ReturnCode Indicating success or error
- */
-fapi::ReturnCode getDdrType(const fapi::Target & i_dimm,
-                            fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type & o_type)
-{
-    fapi::ReturnCode l_rc = FAPI_ATTR_GET(ATTR_SPD_DRAM_DEVICE_TYPE, &i_dimm,
-                                          o_type);
-    if (l_rc)
-    {
-        FAPI_ERR("getSpdAttrAccessor: Error querying DDR type");
-    }
-    else if ((o_type != fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3) &&
-             (o_type != fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR4))
-    {
-        FAPI_ERR("getSpdAttrAccessor: Invalid DIMM DDR Type 0x%02x", o_type);
-        const fapi::Target & DIMM = i_dimm;
-        const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type & TYPE = o_type;
-        FAPI_SET_HWP_ERROR(l_rc, RC_GET_SPD_ACCESSOR_INVALID_DDR_TYPE);
-    }
-
-    return l_rc;
-}
-
-/**
- * @brief Returns SPD_SDRAM_BANKS data
- *
- * The raw data has different meanings for DDR3 and DDR4, this HWP translates
- * each to the enumeration in the common FAPI Attribute
- *
- * @param[in]  i_dimm Reference to DIMM fapi target
- * @param[in]  i_attr The Attribute to get
- * @param[out] o_pVal Pointer to data buffer filled in with attribute data
- * @param[in]  i_len  Size of o_pVal
- * @param[in]  i_type DDR Type
- *
- * @return fapi::ReturnCode Indicating success or error
- */
-fapi::ReturnCode get_SPD_SDRAM_BANKS(const fapi::Target & i_dimm,
-    const fapi::getSpdAttr::Attr i_attr,
-    void * o_pVal,
-    const size_t i_len,
-    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
-{
-    fapi::ATTR_SPD_SDRAM_BANKS_Type & o_val =
-        *(reinterpret_cast<fapi::ATTR_SPD_SDRAM_BANKS_Type *>(o_pVal));
-    o_val = 0;
-
-    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
-
-    if (!l_rc)
-    {
-        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
-        {
-            fapi::ATTR_SPD_SDRAM_BANKS_DDR3_Type l_banks = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS_DDR3, &i_dimm, l_banks);
-
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_SDRAM_BANKS: Error getting DDR3 attr");
-            }
-            else
-            {
-                switch (l_banks)
-                {
-                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B8:
-                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8;
-                    break;
-                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B16:
-                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B16;
-                    break;
-                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B32:
-                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B32;
-                    break;
-                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR3_B64:
-                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B64;
-                    break;
-                default:
-                   FAPI_ERR("get_SPD_SDRAM_BANKS: Unrecognized DDR3 attr 0x%x",
-                            l_banks);
-                   o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_UNKNOWN;
-                }
-            }
-        }
-        else
-        {
-            fapi::ATTR_SPD_SDRAM_BANKS_DDR4_Type l_banks = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_SDRAM_BANKS_DDR4, &i_dimm, l_banks);
-
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_SDRAM_BANKS: Error getting DDR4 attr");
-            }
-            else
-            {
-                switch (l_banks)
-                {
-                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR4_B4:
-                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B4;
-                    break;
-                case fapi::ENUM_ATTR_SPD_SDRAM_BANKS_DDR4_B8:
-                    o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_B8;
-                    break;
-                   FAPI_ERR("get_SPD_SDRAM_BANKS: Unrecognized DDR4 attr 0x%x",
-                            l_banks);
-                   o_val = fapi::ENUM_ATTR_SPD_SDRAM_BANKS_UNKNOWN;
-                }
-            }
-        }
-    }
-
-    return l_rc;
-}
-
-/**
- * @brief Returns SPD_MODULE_NOMINAL_VOLTAGE data
- *
- * The raw data has different meanings for DDR3 and DDR4, this HWP translates
- * each to the enumeration in the common FAPI Attribute
- *
- * @param[in]  i_dimm Reference to DIMM fapi target
- * @param[in]  i_attr The Attribute to get
- * @param[out] o_pVal Pointer to data buffer filled in with attribute data
- * @param[in]  i_len  Size of o_pVal
- * @param[in]  i_type DDR Type
- *
- * @return fapi::ReturnCode Indicating success or error
- */
-fapi::ReturnCode get_SPD_MODULE_NOMINAL_VOLTAGE(const fapi::Target & i_dimm,
-    const fapi::getSpdAttr::Attr i_attr,
-    void * o_pVal,
-    const size_t i_len,
-    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
-{
-    fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_Type & o_val =
-        *(reinterpret_cast<fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_Type *>(
-            o_pVal));
-    o_val = 0;
-
-    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
-
-    if (!l_rc)
-    {
-        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
-        {
-            fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_Type l_voltage = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3, &i_dimm,
-                                 l_voltage);
-
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_MODULE_NOMINAL_VOLTAGE: Error getting DDR3 attr");
-            }
-            else
-            {
-                if (l_voltage &
-                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_NOTOP1_5)
-                {
-                    o_val |=
-                        fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_NOTOP1_5;
-                }
-                if (l_voltage &
-                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_OP1_35)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_35;
-                }
-                if (l_voltage &
-                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR3_OP1_2X)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2X;
-                }
-            }
-        }
-        else
-        {
-            fapi::ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4_Type l_voltage = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4, &i_dimm,
-                                 l_voltage);
-
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_MODULE_NOMINAL_VOLTAGE: Error getting DDR4 attr");
-            }
-            else
-            {
-                if (l_voltage &
-                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4_OP1_2V)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_OP1_2V;
-                }
-                if (l_voltage &
-                    fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_DDR4_END1_2V)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_MODULE_NOMINAL_VOLTAGE_END1_2V;
-                }
-            }
-        }
-    }
-
-    return l_rc;
-}
-
-/**
- * @brief Returns SPD_CAS_LATENCIES_SUPPORTED data
- *
- * The raw data has different meanings for DDR3 and DDR4, this HWP translates
- * each to the enumeration in the common FAPI Attribute
- *
- * @param[in]  i_dimm Reference to DIMM fapi target
- * @param[in]  i_attr The Attribute to get
- * @param[out] o_pVal Pointer to data buffer filled in with attribute data
- * @param[in]  i_len  Size of o_pVal
- * @param[in]  i_type DDR Type
- *
- * @return fapi::ReturnCode Indicating success or error
- */
-fapi::ReturnCode get_SPD_CAS_LATENCIES_SUPPORTED(const fapi::Target & i_dimm,
-    const fapi::getSpdAttr::Attr i_attr,
-    void * o_pVal,
-    const size_t i_len,
-    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
-{
-    fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_Type & o_val =
-        *(reinterpret_cast<fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_Type *>(
-            o_pVal));
-    o_val = 0;
-
-    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
-
-    if (!l_rc)
-    {
-        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
-        {
-            fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_Type cl = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3, &i_dimm,
-                                 cl);
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_CAS_LATENCIES_SUPPORTED: Error getting DDR3 attr");
-            }
-            else
-            {
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_4)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_4;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_5)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_5;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_6)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_6;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_7)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_7;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_8)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_8;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_9)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_9;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_10)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_10;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_11)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_11;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_12)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_12;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_13)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_13;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_14)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_14;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_15)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_15;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_16)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_16;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_17)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_17;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR3_CL_18)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_18;
-                }
-            }
-        }
-        else
-        {
-            fapi::ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_Type cl = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4, &i_dimm,
-                                 cl);
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_CAS_LATENCIES_SUPPORTED: Error getting DDR4 attr");
-            }
-            else
-            {
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_7)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_7;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_8)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_8;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_9)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_9;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_10)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_10;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_11)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_11;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_12)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_12;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_13)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_13;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_14)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_14;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_15)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_15;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_16)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_16;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_17)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_17;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_18)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_18;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_19)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_19;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_20)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_20;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_21)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_21;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_22)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_22;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_23)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_23;
-                }
-                if (cl & fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_DDR4_CL_24)
-                {
-                    o_val |= fapi::ENUM_ATTR_SPD_CAS_LATENCIES_SUPPORTED_CL_24;
-                }
-            }
-        }
-    }
-
-    return l_rc;
-}
-
-/**
- * @brief Returns SPD_MODULE_REVISION_CODE data
- *
- * The fields are different sizes for DDR3 and DDR4, this HWP copies the value
- * to the attribute size in the common FAPI Attribute
- *
- * @param[in]  i_dimm Reference to DIMM fapi target
- * @param[in]  i_attr The Attribute to get
- * @param[out] o_pVal Pointer to data buffer filled in with attribute data
- * @param[in]  i_len  Size of o_pVal
- * @param[in]  i_type DDR Type
- *
- * @return fapi::ReturnCode Indicating success or error
- */
-fapi::ReturnCode get_SPD_MODULE_REVISION_CODE(const fapi::Target & i_dimm,
-    const fapi::getSpdAttr::Attr i_attr,
-    void * o_pVal,
-    const size_t i_len,
-    const fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type i_type)
-{
-    fapi::ATTR_SPD_MODULE_REVISION_CODE_Type & o_val =
-        *(reinterpret_cast<fapi::ATTR_SPD_MODULE_REVISION_CODE_Type *>(o_pVal));
-    o_val = 0;
-
-    fapi::ReturnCode l_rc = checkSize(i_attr, i_len, sizeof(o_val));
-
-    if (!l_rc)
-    {
-        if (i_type == fapi::ENUM_ATTR_SPD_DRAM_DEVICE_TYPE_DDR3)
-        {
-            // Size of DDR3 data matches DDR neutral attribute (uint32_t)
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_REVISION_CODE_DDR3, &i_dimm,
-                                 o_val);
-
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_MODULE_REVISION_CODE: Error getting DDR3 attr");
-            }
-        }
-        else
-        {
-            // Size of DDR4 data (uint8_t) is smaller than the DDR neutral
-            // attribute (uint32_t)
-            fapi::ATTR_SPD_MODULE_REVISION_CODE_DDR4_Type l_code = 0;
-            l_rc = FAPI_ATTR_GET(ATTR_SPD_MODULE_REVISION_CODE_DDR4, &i_dimm,
-                                 l_code);
-
-            if (l_rc)
-            {
-                FAPI_ERR("get_SPD_MODULE_NOMINAL_VOLTAGE: Error getting DDR4 attr");
-            }
-            else
-            {
-                o_val = static_cast<fapi::ATTR_SPD_MODULE_REVISION_CODE_Type>(
-                    l_code);
-            }
-        }
-    }
-
-    return l_rc;
-}
-
-//-----------------------------------------------------------------------------
-// getSpdAttrAccessor HWP - See header file for details
-//-----------------------------------------------------------------------------
-fapi::ReturnCode getSpdAttrAccessor(const fapi::Target & i_dimm,
-                                    const fapi::getSpdAttr::Attr i_attr,
-                                    void * o_pVal,
-                                    const size_t i_len)
-{
-    fapi::ReturnCode l_rc;
-
-    fapi::ATTR_SPD_DRAM_DEVICE_TYPE_Type l_type = 0;
-    l_rc = getDdrType(i_dimm, l_type);
-
-    if (l_rc)
-    {
-        FAPI_ERR("getSpdAttrAccessor: Error from getDdrType for Attr ID 0x%02x",
-                 i_attr);
-    }
-    else
-    {
-        switch (i_attr)
-        {
-        case fapi::getSpdAttr::SPD_SDRAM_BANKS:
-            l_rc = get_SPD_SDRAM_BANKS(i_dimm, i_attr, o_pVal, i_len, l_type);
-            break;
-        case fapi::getSpdAttr::SPD_MODULE_NOMINAL_VOLTAGE:
-            l_rc = get_SPD_MODULE_NOMINAL_VOLTAGE(i_dimm,  i_attr,o_pVal, i_len,
-                                                  l_type);
-            break;
-        case fapi::getSpdAttr::SPD_CAS_LATENCIES_SUPPORTED:
-            l_rc = get_SPD_CAS_LATENCIES_SUPPORTED(i_dimm, i_attr, o_pVal,
-                                                   i_len, l_type);
-            break;
-        case fapi::getSpdAttr::SPD_MODULE_REVISION_CODE:
-            l_rc = get_SPD_MODULE_REVISION_CODE(i_dimm,  i_attr, o_pVal, i_len,
-                                                l_type);
-            break;
-        default:
-            FAPI_ERR("getSpdAttrAccessor: Invalid Attribute ID 0x%02x", i_attr);
-            const fapi::getSpdAttr::Attr & ATTR_ID = i_attr;
-            FAPI_SET_HWP_ERROR(l_rc, RC_GET_SPD_ACCESSOR_INVALID_ATTRIBUTE_ID);
-        }
-    }
-
-    return l_rc;
-}
-
-}
diff --git a/src/usr/hwpf/hwp/spd_accessors/spd.mk b/src/usr/hwpf/hwp/spd_accessors/spd.mk
deleted file mode 100644
index 0857f09f8..000000000
--- a/src/usr/hwpf/hwp/spd_accessors/spd.mk
+++ /dev/null
@@ -1,29 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/spd_accessors/spd.mk $
-#
-# OpenPOWER HostBoot Project
-#
-# COPYRIGHT International Business Machines Corp. 2013,2014
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/spd_accessors
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/spd_accessors
-
-VPATH += ${HWPPATH}/spd_accessors
-
-OBJS += getSpdAttrAccessor.o
-
diff --git a/src/usr/hwpf/hwp/start_payload/HBconfig b/src/usr/hwpf/hwp/start_payload/HBconfig
deleted file mode 100644
index 3cc6ed127..000000000
--- a/src/usr/hwpf/hwp/start_payload/HBconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-config SET_NOMINAL_PSTATE
-    default n
-    depends on !HTMGT
-    help
-        Set the PState to Nominal just before starting the payload.
-config START_OCC_DURING_BOOT
-    default n
-    help
-        Activates all the OCCs during IPL
diff --git a/src/usr/hwpf/hwp/start_payload/makefile b/src/usr/hwpf/hwp/start_payload/makefile
deleted file mode 100644
index 4c284afa2..000000000
--- a/src/usr/hwpf/hwp/start_payload/makefile
+++ /dev/null
@@ -1,61 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/usr/hwpf/hwp/start_payload/makefile $
-#
-# OpenPOWER HostBoot Project
-#
-# Contributors Listed Below - COPYRIGHT 2012,2016
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-#     http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-ROOTPATH = ../../../../..
-
-MODULE = start_payload
-
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-##  NOTE: add the base istep dir here. 
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/start_payload
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/start_payload/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/pstates/pstates
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += start_payload.o
-
-
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/start_payload/<HWP_dir>
-
-include ${ROOTPATH}/config.mk
-
diff --git a/src/usr/hwpf/hwp/start_payload/start_payload.C b/src/usr/hwpf/hwp/start_payload/start_payload.C
deleted file mode 100644
index e51f5428e..000000000
--- a/src/usr/hwpf/hwp/start_payload/start_payload.C
+++ /dev/null
@@ -1,234 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/start_payload/start_payload.C $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2012,2016                        */
-/* [+] Google Inc.                                                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-/**
- *  @file start_payload.C
- *
- *  Support file for IStep: start_payload
- *   Start Payload
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-#include    <kernel/console.H>              //  printk status
-#include    <sys/misc.h>
-#include    <trace/interface.H>
-#include    <initservice/taskargs.H>
-#include    <errl/errlentry.H>
-#include    <vfs/vfs.H>
-#include    <initservice/initserviceif.H>
-#include    <initservice/extinitserviceif.H>
-#include    <initservice/istepdispatcherif.H>
-#include    <usr/cxxtest/TestSuite.H>
-#include    <hwpf/istepreasoncodes.H>
-#include    <errl/errludtarget.H>
-#include    <sys/time.h>
-#include    <sys/mmio.h>
-#include    <mbox/mbox_queues.H>
-#include    <mbox/mboxif.H>
-#include    <i2c/i2cif.H>
-#include    <hwpf/hwp/occ/occ.H>
-#include    <sys/mm.h>
-#include    <devicefw/userif.H>
-#include    <util/misc.H>
-
-#include    <initservice/isteps_trace.H>
-#include    <isteps/hwpisteperror.H>
-
-//  targeting support
-#include    <targeting/common/commontargeting.H>
-
-//  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-#include    "p8_set_pore_bar.H"
-#include    "p8_cpu_special_wakeup.H"
-#include    "p8_pore_table_gen_api.H"
-#include    <p8_scom_addresses.H>
-#include    "proc_set_max_pstate.H"
-
-#include    "start_payload.H"
-#include    <runtime/runtime.H>
-#include    <devtree/devtreeif.H>
-#include    <sys/task.h>
-#include    <intr/interrupt.H>
-#include    <kernel/ipc.H> // for internode data areas
-#include    <mbox/ipc_msg_types.H>
-#include    <pnor/pnorif.H>
-#include    <sys/mm.h>
-#include    <algorithm>
-#include    <config.h>
-#include    <ipmi/ipmiwatchdog.H>
-#include    <vpd/vpd_if.H>
-
-//  Uncomment these files as they become available:
-// #include    "host_start_payload/host_start_payload.H"
-
-namespace   START_PAYLOAD
-{
-
-using   namespace   TARGETING;
-using   namespace   fapi;
-using   namespace   ISTEP;
-using   namespace   ISTEP_ERROR;
-
-/**
- * @brief This function disables the special wakeup that allows scom
- *        operations on napped cores
- *
- * @return errlHndl_t error handle
- */
-errlHndl_t disableSpecialWakeup();
-
-
-#ifdef CONFIG_SET_NOMINAL_PSTATE
-errlHndl_t setMaxPstate ( void )
-{
-    errlHndl_t l_errl = NULL;
-
-    TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-               "Speed up to max P-state" );
-
-    TARGETING::TargetHandleList l_procTargetList;
-    getAllChips(l_procTargetList, TYPE_PROC);
-
-    // loop thru all the cpus
-    for (TargetHandleList::const_iterator
-         l_proc_iter = l_procTargetList.begin();
-         l_proc_iter != l_procTargetList.end();
-         ++l_proc_iter)
-    {
-        //  make a local copy of the CPU target
-        const TARGETING::Target* l_proc_target = *l_proc_iter;
-
-        //  trace HUID
-        TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                  "target HUID %.8X", TARGETING::get_huid(l_proc_target));
-
-        // cast OUR type of target to a FAPI type of target.
-        fapi::Target l_fapi_proc_target( TARGET_TYPE_PROC_CHIP,
-                                         (const_cast<TARGETING::Target*>(
-                                                         l_proc_target)) );
-
-        //  call the HWP with each fapi::Target
-        FAPI_INVOKE_HWP( l_errl,
-                         proc_set_max_pstate,
-                         l_fapi_proc_target);
-        if ( l_errl )
-        {
-            // capture the target data in the elog
-            ERRORLOG::ErrlUserDetailsTarget(l_proc_target).addToLog( l_errl );
-
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "ERROR : setMaxPstate, PLID=0x%x",
-                      l_errl->plid()  );
-            break;
-        }
-        else
-        {
-            TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                       "SUCCESS : setMaxPstate" );
-        }
-    }   // end for
-
-    return l_errl;
-}
-#endif
-
-errlHndl_t disableSpecialWakeup()
-{
-    errlHndl_t l_errl = NULL;
-
-    // loop thru all proc and find all functional ex units
-    TARGETING::TargetHandleList l_procTargetList;
-    getAllChips(l_procTargetList, TYPE_PROC);
-    for (TargetHandleList::const_iterator l_procIter =
-         l_procTargetList.begin();
-         l_procIter != l_procTargetList.end();
-         ++l_procIter)
-    {
-        const TARGETING::Target* l_pChipTarget = *l_procIter;
-
-        // Get EX list under this proc
-        TARGETING::TargetHandleList l_exList;
-        getChildChiplets( l_exList, l_pChipTarget, TYPE_EX );
-
-        for (TargetHandleList::const_iterator
-             l_exIter = l_exList.begin();
-             l_exIter != l_exList.end();
-             ++l_exIter)
-        {
-            const TARGETING::Target * l_exTarget = *l_exIter;
-
-            fapi::Target l_fapi_ex_target
-                ( TARGET_TYPE_EX_CHIPLET,
-                  (const_cast<TARGETING::Target*>(l_exTarget)) );
-
-            TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                      "Running p8_cpu_special_wakeup(DISABLE) "
-                      "on EX target HUID %.8X",
-                      TARGETING::get_huid(l_exTarget));
-
-            FAPI_INVOKE_HWP(l_errl,
-                            p8_cpu_special_wakeup,
-                            l_fapi_ex_target,
-                            SPCWKUP_DISABLE,
-                            HOST);
-
-            if(l_errl)
-            {
-                TRACFCOMP( ISTEPS_TRACE::g_trac_isteps_trace,
-                           "Disable p8_cpu_special_wakeup ERROR :"
-                           " Returning errorlog, reason=0x%x",
-                           l_errl->reasonCode() );
-
-                // capture the target data in the elog
-                ERRORLOG::ErrlUserDetailsTarget(l_exTarget).addToLog( l_errl );
-
-                break;
-            }
-            else
-            {
-                TRACFCOMP(ISTEPS_TRACE::g_trac_isteps_trace,
-                          "SUCCESS: Disable special wakeup");
-            }
-        }
-        if(l_errl)
-        {
-            break;
-        }
-    }
-
-    return l_errl;
-}
-
-
-};   // end namespace
diff --git a/src/usr/hwpf/hwp/start_payload/start_payload.H b/src/usr/hwpf/hwp/start_payload/start_payload.H
deleted file mode 100644
index 54ca19f76..000000000
--- a/src/usr/hwpf/hwp/start_payload/start_payload.H
+++ /dev/null
@@ -1,113 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/usr/hwpf/hwp/start_payload/start_payload.H $              */
-/*                                                                        */
-/* OpenPOWER HostBoot Project                                             */
-/*                                                                        */
-/* COPYRIGHT International Business Machines Corp. 2012,2014              */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-#ifndef  __START_PAYLOAD_START_PAYLOAD_H
-#define  __START_PAYLOAD_START_PAYLOAD_H
-
-/**
- *  @file start_payload.H
- *
- *  Start Payload
- *
- *  All of the following routines are "named isteps" - they are invoked as
- *  tasks by the @ref IStepDispatcher.
- *
- *  HWP_IGNORE_VERSION_CHECK
- *
- */
-
- /*  @tag isteplist
- *  @docversion     v1.28 (12/03/12)
- *  @istepname      start_payload
- *  @istepnum       21
- *  @istepdesc      Start Payload
- *
- *  @{
- *      @substepnum     1
- *      @substepname    host_runtime_setup
- *      @substepdesc    :
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     2
- *      @substepname    host_verify_hdat
- *      @substepdesc    :  Start Payload
- *          @target_sched   serial
- *  @}
- *  @{
- *      @substepnum     3
- *      @substepname    host_start_payload
- *      @substepdesc    :  Start Payload
- *          @target_sched   serial
- *  @}
- *
- */
-
-/******************************************************************************/
-// Includes
-/******************************************************************************/
-#include    <stdint.h>
-
-namespace   START_PAYLOAD
-{
-
-/**
- *  @brief   host_runtime_setup
- *
- *           Host Runtime Setup
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*    call_host_runtime_setup( void    *io_pArgs );
-
-/**
- *  @brief   host_verify_hdat
- *
- *           Secureboot verification of PHYP/AVP image load
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*    call_host_verify_hdat( void    *io_pArgs );
-
-/**
- *  @brief   host_start_payload
- *
- *           Start Payload
- *
- *  param[in,out]   -   pointer to any arguments, usually NULL
- *
- *  return  any error logs to istep
- *
- */
-void*    call_host_start_payload( void    *io_pArgs );
-
-};   // end namespace
-
-#endif
-
diff --git a/src/usr/initservice/istepdispatcher/makefile b/src/usr/initservice/istepdispatcher/makefile
index a478d6c51..71fa00f14 100644
--- a/src/usr/initservice/istepdispatcher/makefile
+++ b/src/usr/initservice/istepdispatcher/makefile
@@ -25,7 +25,6 @@
 ROOTPATH = ../../../..
 MODULE = istepdisp
 
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/establish_system_smp
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
 
 # Next includes required for attribute override support
diff --git a/src/usr/isteps/istep18/makefile b/src/usr/isteps/istep18/makefile
index d411bdcec..a7c9806b3 100644
--- a/src/usr/isteps/istep18/makefile
+++ b/src/usr/isteps/istep18/makefile
@@ -28,45 +28,22 @@ MODULE = tod_init
 
 ##      support for Targeting and fapi
 EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 
 ## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
 
-##  NOTE: add the base istep dir here.
-##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/@istepname
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init
+#@TODO-RTC:149253-Add TOD support
+#OBJS += tod_init.o
+#OBJS += TodControls.o
+#OBJS += TodDrawer.o
+#OBJS += TodProc.o
+#OBJS += TodSvc.o
+#OBJS += TodSvcUtil.o
+#OBJS += TodHwpIntf.o
+#OBJS += TodTopologyManager.o
 
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##@ EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/???
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_setup
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_save_config
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_utils
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_init
-
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += tod_init.o
-OBJS += TodControls.o
-OBJS += TodDrawer.o
-OBJS += TodProc.o
-OBJS += TodSvc.o
-OBJS += TodSvcUtil.o
-OBJS += TodHwpIntf.o
-OBJS += TodTopologyManager.o
 OBJS += proc_tod_setup.o
 OBJS += proc_tod_save_config.o
 OBJS += proc_tod_init.o
 OBJS += proc_tod_utils.o
 
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##@ VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/???
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_setup
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_save_config
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_utils
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/tod_init/proc_tod_init
-
 include ${ROOTPATH}/config.mk
diff --git a/src/usr/occ/occ.C b/src/usr/occ/occ.C
index c13f09e70..3572abec9 100644
--- a/src/usr/occ/occ.C
+++ b/src/usr/occ/occ.C
@@ -26,8 +26,8 @@
 #include    <stdint.h>
 #include    <config.h>
 
-#include    <hwpf/hwp/occ/occ.H>
-#include    <hwpf/hwp/occ/occ_common.H>
+#include    <occ/occ.H>
+#include    <occ/occ_common.H>
 
 #include    <initservice/taskargs.H>
 #include    <errl/errlentry.H>
@@ -46,9 +46,6 @@
 #include    <targeting/common/util.H>
 
 //  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-#include    <hwpf/plat/fapiPlatTrace.H>
 #include    <isteps/hwpf_reasoncodes.H>
 
 #include    <vfs/vfs.H>
diff --git a/src/usr/occ/occ.mk b/src/usr/occ/occ.mk
index a64a2f2e3..321c67e95 100644
--- a/src/usr/occ/occ.mk
+++ b/src/usr/occ/occ.mk
@@ -22,63 +22,13 @@
 # permissions and limitations under the License.
 #
 # IBM_PROLOG_END_TAG
-##      support for Targeting and fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
 
-## pointer to common HWP files
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/include
-
-## pointer to already consumed procedures.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar
-
-##  NOTE: add the base istep dir here.
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ
-
-##  Include sub dirs
-##  NOTE: add a new EXTRAINCDIR when you add a new HWP
-##  EXAMPLE:
-##  EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ/<HWP_dir>
-EXTRAINCDIR += ${ROOTPATH}/src/usr/hwpf/hwp/occ/occ_procedures
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures
-
-##  NOTE: add new object files when you add a new HWP
-OBJS += p8_pba_init.o
-OBJS += p8_pm_init.o
-OBJS += p8_pcbs_init.o
-OBJS += p8_pmc_init.o
-OBJS += p8_poregpe_init.o
-OBJS += p8_oha_init.o
-OBJS += p8_ocb_init.o
-OBJS += p8_pss_init.o
-OBJS += p8_occ_control.o
-OBJS += p8_occ_sram_init.o
-OBJS += p8_pm_firinit.o
-OBJS += p8_pm_oha_firinit.o
-OBJS += p8_pm_pcbs_firinit.o
-OBJS += p8_pm_occ_firinit.o
-OBJS += p8_pm_pba_firinit.o
-OBJS += p8_pm_pmc_firinit.o
-OBJS += p8_pm_utils.o
-
-
-#These procedures are included per Stradale's request so
-#they can implement OCC Reset.
-OBJS += p8_pm_prep_for_reset.o
-OBJS += p8_pmc_force_vsafe.o
-OBJS += p8_ocb_indir_access.o
-OBJS += p8_ocb_indir_setup_linear.o
+#@TODO-RTC:159930-Enable OCC support for HTMGT
 
 #common occ functions between ipl and runtime
 OBJS += occ_common.o
 OBJS += occ.o
 OBJS += $(if $(CONFIG_HTMGT),occAccess.o)
 
-##  NOTE: add a new directory onto the vpaths when you add a new HWP
-##  EXAMPLE:
-#   VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/occ/<HWP_dir>
-VPATH += ${ROOTPATH}/src/usr/hwpf/hwp/occ/occ_procedures
 
 
diff --git a/src/usr/occ/occ_common.C b/src/usr/occ/occ_common.C
index a6c7e73f5..81c5d7ccc 100644
--- a/src/usr/occ/occ_common.C
+++ b/src/usr/occ/occ_common.C
@@ -45,9 +45,6 @@
 #include    <targeting/common/util.H>
 
 //  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-#include    <hwpf/plat/fapiPlatTrace.H>
 #include    <isteps/hwpf_reasoncodes.H>
 
 #include    <vfs/vfs.H>
diff --git a/src/usr/occ/runtime/rt_occ.C b/src/usr/occ/runtime/rt_occ.C
index a5a2126b0..e36cef3d0 100644
--- a/src/usr/occ/runtime/rt_occ.C
+++ b/src/usr/occ/runtime/rt_occ.C
@@ -25,7 +25,7 @@
 #include <runtime/interface.h>
 #include <kernel/console.H>
 
-#include <hwpf/hwp/occ/occ_common.H>
+#include <occ/occ_common.H>
 
 #include <vmmconst.h>
 #include <sys/misc.h>
@@ -44,16 +44,8 @@
 #include    <runtime/rt_targeting.H>
 
 //  fapi support
-#include    <fapi.H>
-#include    <fapiPlatHwpInvoker.H>
-#include    <hwpf/plat/fapiPlatTrace.H>
 #include    <isteps/hwpf_reasoncodes.H>
 
-// Procedures
-#include <p8_occ_control.H>
-#include <p8_pba_bar_config.H>
-#include <p8_pm_init.H>
-#include <p8_pm_prep_for_reset.H>
 
 using namespace TARGETING;
 // Trace
diff --git a/src/usr/runtime/occ/test/rt_occtest.H b/src/usr/runtime/occ/test/rt_occtest.H
index 0b827ca9a..5d9a67ca6 100644
--- a/src/usr/runtime/occ/test/rt_occtest.H
+++ b/src/usr/runtime/occ/test/rt_occtest.H
@@ -27,7 +27,7 @@
 
 #include <cxxtest/TestSuite.H>
 #include <runtime/interface.h>
-#include <hwpf/hwp/occ/occ_common.H>
+//#include <hwpf/hwp/occ/occ_common.H>
 #include <fapi.H>
 #include <targeting/common/commontargeting.H>
 #include <vmmconst.h>
diff --git a/src/usr/runtime/test/runtimeattrstest.H b/src/usr/runtime/test/runtimeattrstest.H
index 0eb628cf3..2cf2f389e 100644
--- a/src/usr/runtime/test/runtimeattrstest.H
+++ b/src/usr/runtime/test/runtimeattrstest.H
@@ -40,7 +40,7 @@
 #include <arch/ppc.H> //for MAGIC
 #include <attributeenums.H>
 #include <errl/errlmanager.H>
-#include <hwpf/plat/fapiPlatHwpInvoker.H>
+//#include <hwpf/plat/fapiPlatHwpInvoker.H>
 #include "../common/hsvc_attribute_structs.H"
 
 extern trace_desc_t* g_trac_runtime;
diff --git a/src/usr/scom/runtime/makefile b/src/usr/scom/runtime/makefile
index 60f86d7d4..3397a82d8 100644
--- a/src/usr/scom/runtime/makefile
+++ b/src/usr/scom/runtime/makefile
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2013,2015
+# Contributors Listed Below - COPYRIGHT 2013,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -30,13 +30,6 @@ MODULE = scom_rt
 include ../scom.mk
 
 #include unique object modules - currently none
-# OBJS +=
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/ecmddatabuffer
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/plat
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/hwp/utility_procedures/
-
 OBJS += handleSpecialWakeup.o
 
 SUBDIRS += test.d
diff --git a/src/usr/targeting/runtime/test/makefile b/src/usr/targeting/runtime/test/makefile
index 2e0ba3552..987655384 100644
--- a/src/usr/targeting/runtime/test/makefile
+++ b/src/usr/targeting/runtime/test/makefile
@@ -5,7 +5,7 @@
 #
 # OpenPOWER HostBoot Project
 #
-# Contributors Listed Below - COPYRIGHT 2013,2015
+# Contributors Listed Below - COPYRIGHT 2013,2016
 # [+] International Business Machines Corp.
 #
 #
@@ -25,7 +25,6 @@
 HOSTBOOT_RUNTIME = 1
 ROOTPATH = ../../../../..
 
-EXTRAINCDIR += ${ROOTPATH}/src/include/usr/hwpf/fapi
 MODULE = testtargeting_rt
 TESTS = *.H