HWP: Update HWPs with latest good versions

The selection of HWPs to pull into Hostboot was due to either:
1/ Thi needed to pull into Hostboot build for VPO to match Cronus level.
2/ Mike saw that latest code in eKB is a trivial update to current reviewed
version (usually just adding the cvs version number)
These changes have all passed the "HWP Review"

RTC: 46573
Change-Id: I50031a19e5b4f7ad0531cd58df9ec24034207664
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1499
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

8 files changed, 226 insertions, 187 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/edi_regs.h b/src/usr/hwpf/hwp/bus_training/edi_regs.h
index 313b14b83..7dfdf3206 100644
--- a/src/usr/hwpf/hwp/bus_training/edi_regs.h
+++ b/src/usr/hwpf/hwp/bus_training/edi_regs.h
@@ -42,7 +42,7 @@
 //----------------------------------------------------- 
 // Constant file for edi_reg_attribute.txt_fixed
 // File generated at 16:23 on 8/31/2011 using system_pervasive/common/tools/CreateConstantsH.pl
-// $Id: edi_regs.h,v 1.8 2012/05/21 12:22:01 varkeykv Exp $
+// $Id: edi_regs.h,v 1.9 2012/07/28 04:03:12 jmcgill Exp $
 // $URL: $
 //
 // *!**************************************************************************
@@ -479,8 +479,8 @@ NUM_REGS
 
 
 // merged ei4 and edi ext addresses
-const uint32_t  GCR_sub_reg_ext_addr[] =     { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3,
-0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3
+const uint32_t  GCR_sub_reg_ext_addr[] =     { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF,
+											   0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF
 };
 //merged ei4 and edi 
 const char* const GCR_sub_reg_names[] = {
@@ -700,7 +700,8 @@ const char* const GCR_sub_reg_names[] = {
 	"Per-Bus BUSCTL FIR Error Reset Reg",
 	"Per-Bus FIR Error Source-Isolation Reg",
 	"Per-Bus FIR Error Source-Isolation Mask Reg",
-	"Per-Bus FIR Error Injection Reg"
+	"Per-Bus FIR Error Injection Reg",
+    "Per-Bus FIR Register Write Alias",
 	"TX Lane Mode Reg",
 	"TX Cntl and Status Reg",
 	"TX Per-Lane Spare Mode Reg",
@@ -893,7 +894,8 @@ const char* const GCR_sub_reg_names[] = {
 	"Per-Bus BUSCTL FIR Error Reset Reg",
 	"Per-Bus FIR Error Source-Isolation Reg",
 	"Per-Bus FIR Error Source-Isolation Mask Reg",
-	"Per-Bus FIR Error Injection Reg"
+	"Per-Bus FIR Error Injection Reg",
+	"Per-Bus FIR Register Write Alias"
 };
 
 // tx_mode_pl Register field name                                       data value   Description
diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
index 3b5c01e27..6764b00b7 100644
--- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
@@ -68,7 +68,7 @@ ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,GCR_sub
 //------------------------------------------------------------------------------------------------------------------------------------

 // GCR SCOM WRITE  - main api for write - do not use doGCRop directly

 //------------------------------------------------------------------------------------------------------------------------------------

-ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, int skipCheck)

+ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, int skipCheck,int bypass_rmw)

 {

    ReturnCode rc;

    uint32_t rc_ecmd=0;

@@ -79,7 +79,7 @@ ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_s
       rc.setEcmdError(rc_ecmd);

    }

    else{

-        rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck);

+        rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck,bypass_rmw);

         if(!rc.ok())

         {

           FAPI_ERR("Unexpected error while performing GCR OP \n");

@@ -125,7 +125,7 @@ uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) {
 /* gcr2        readvalid 39        1       # read data valid bit                                                         */

 /*************************************************************************************************************************/

 

-ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck) {

+ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck,int bypass_rmw) {

     ReturnCode rc;

     uint32_t rc_ecmd=0;

     uint64_t  scom_address64=0;

@@ -163,7 +163,12 @@ ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op
     {

         FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]);

         scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0));

-        rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+        if(!bypass_rmw){

+           rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+        }

+        else{

+         getscom_data64.flushTo0();

+        }

         if(!rc.ok())

         {

             FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n");

@@ -219,7 +224,9 @@ ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op
                    else

                    {

                        // check the write

-                       rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+                       if(!skipCheck){

+                        rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+                       }

                        if(!rc.ok()){

                        FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n");

                        return(rc);

diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
index 6fc15eaec..08d6eb355 100644
--- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
@@ -21,126 +21,126 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   *** IBM Confidential ***
-// *!***************************************************************************
-// *! FILENAME             : gcr_funcs.H
-// *! TITLE                : 
-// *! DESCRIPTION          : 
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkeykv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |jaswamin|09/13/11|
-//   2.0   |varkeykv|01/12/12| Post GFW review changes
-//------------------------------------------------------------------------------
-
-#ifndef GCR_FUNCS
-#define GCR_FUNCS
-
-/* Include some system headers */
-#include <list>
-#include <stdint.h>
-#include <fapi.H>
-using namespace fapi;
-
-#include "edi_regs.h"
-
-
-enum io_interface_t {     CP_PSI,
-           CP_FABRIC_X0,
-           CP_FABRIC_A0, 
-           CP_IOMC0_P0,  
-           CP_IOMC1_P0,  
-           S1_FABRIC_SX0,
-           S1_FABRIC_SA0,
-           CEN_DMI,
-           };
-
-// P8 chip interfaces
-const uint32_t NUM_INTERFACES=21;
-const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",
-                                            "CP_FABRIC_X0", 
-                                            "CP_FABRIC_A0",
-                                            "CP_IOMC0_P0",  
-                                            "CP_IOMC1_P0",  
-                                            "S1_FABRIC_SX0",
-                                            "S1_FABRIC_SA0", 
-                                            "CEN_DMI" };
-// EDI register addresses for CP
-const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,
-                                                  0x0401103F,
-                                                  0x08010c3f, 
-                                                  0x02011a3F, 
-                                                  0x02011e3F,
-                                                  0x03010c3f,
-                                                  0x08010c3f, 
-                                                  0x0201043F  };
-const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,
-                                                  0x04011020, 
-                                                  0x08010c20, 
-                                                  0x02011a20, 
-                                                  0x02011e20,
-                                                  0x03010c20,
-                                                  0x08010c20, 
-                                                  0x02010420  };
-
-
-// Register type
-typedef enum { tx_per_lane,  tx_per_group,  tx_per_pack, tx_per_bus,  rx_per_lane,  rx_per_group,  rx_per_pack, rx_per_bus, num_register_type } register_type;
-
-typedef enum { gcr_op_read,  gcr_op_write }  gcr_op;
-
-
-// Lane Bit Defintions
-// 0x00  (lane 0),   0x01  (lane 1) , etc
-const uint8_t SELECT_ALL_LANES=0x1F;          // The lane address is a 5 bit value  0b 11111  selects all lanes
-
-// Group Bit Definitions 0x00 group 0 ,  0x01 group1 , etc
-const uint8_t  RX_GROUP_BROADCAST =0x0F ;       // (Write Only) The group address is a 6 bit value to select all groups ,
-const uint8_t  TX_GROUP_BROADCAST =0x2F  ;      // (Write Only) The group address is a 6 bit value to select all groups ,
-
-// ROUTINES
-//------------------------------------------------------------------------------------------------------------------------------------
-// generate the 64 bit scom address for the GCR
-//------------------------------------------------------------------------------------------------------------------------------------
-uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// handle GCR operations - do not use directly!
-// use GCR_read and GCR_write for reg access - not this function!!!!
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,
-                   gcr_op read_or_write, GCR_sub_registers target_io_reg,
-                   uint32_t group_address,  uint32_t lane_address,
-                   ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits,
-                   ecmdDataBufferBase &databuf_16bit, int skipCheck=0);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM READ  - main api for read - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,
-                     GCR_sub_registers target_io_reg, uint32_t group_address,
-                     uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM WRITE  - main api for write - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface,
-                      GCR_sub_registers target_io_reg, uint32_t group_address,
-                      uint32_t lane_address,  ecmdDataBufferBase set_bits,
-                      ecmdDataBufferBase clear_bits, int skipCheck=0);
-
-
-
-
-#endif
-
+// *!***************************************************************************

+// *! (C) Copyright International Business Machines Corp. 1997, 1998

+// *!           All Rights Reserved -- Property of IBM

+// *!                   *** IBM Confidential ***

+// *!***************************************************************************

+// *! FILENAME             : gcr_funcs.H

+// *! TITLE                : 

+// *! DESCRIPTION          : 

+// *! CONTEXT              : 

+// *!

+// *! OWNER  NAME          : Varghese, Varkey         Email: varkeykv@in.ibm.com

+// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com

+// *!

+// *!***************************************************************************

+// CHANGE HISTORY:

+//------------------------------------------------------------------------------

+// Version:|Author: | Date:  | Comment:

+// --------|--------|--------|--------------------------------------------------

+//   1.0   |jaswamin|09/13/11|

+//   2.0   |varkeykv|01/12/12| Post GFW review changes

+//------------------------------------------------------------------------------

+

+#ifndef GCR_FUNCS

+#define GCR_FUNCS

+

+/* Include some system headers */

+#include <list>

+#include <stdint.h>

+#include <fapi.H>

+using namespace fapi;

+

+#include "edi_regs.h"

+

+

+enum io_interface_t {     CP_PSI,

+           CP_FABRIC_X0,

+           CP_FABRIC_A0, 

+           CP_IOMC0_P0,  

+           CP_IOMC1_P0,  

+           S1_FABRIC_SX0,

+           S1_FABRIC_SA0,

+           CEN_DMI,

+           };

+

+// P8 chip interfaces

+const uint32_t NUM_INTERFACES=21;

+const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",

+                                            "CP_FABRIC_X0", 

+                                            "CP_FABRIC_A0",

+                                            "CP_IOMC0_P0",  

+                                            "CP_IOMC1_P0",  

+                                            "S1_FABRIC_SX0",

+                                            "S1_FABRIC_SA0", 

+                                            "CEN_DMI" };

+// EDI register addresses for CP

+const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,

+                                                  0x0401103F,

+                                                  0x08010c3f, 

+                                                  0x02011a3F, 

+                                                  0x02011e3F,

+                                                  0x03010c3f,

+                                                  0x08010c3f, 

+                                                  0x0201043F  };

+const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,

+                                                  0x04011020, 

+                                                  0x08010c20, 

+                                                  0x02011a20, 

+                                                  0x02011e20,

+                                                  0x03010c20,

+                                                  0x08010c20, 

+                                                  0x02010420  };

+

+

+// Register type

+typedef enum { tx_per_lane,  tx_per_group,  tx_per_pack, tx_per_bus,  rx_per_lane,  rx_per_group,  rx_per_pack, rx_per_bus, num_register_type } register_type;

+

+typedef enum { gcr_op_read,  gcr_op_write }  gcr_op;

+

+

+// Lane Bit Defintions

+// 0x00  (lane 0),   0x01  (lane 1) , etc

+const uint8_t SELECT_ALL_LANES=0x1F;          // The lane address is a 5 bit value  0b 11111  selects all lanes

+

+// Group Bit Definitions 0x00 group 0 ,  0x01 group1 , etc

+const uint8_t  RX_GROUP_BROADCAST =0x0F ;       // (Write Only) The group address is a 6 bit value to select all groups ,

+const uint8_t  TX_GROUP_BROADCAST =0x2F  ;      // (Write Only) The group address is a 6 bit value to select all groups ,

+

+// ROUTINES

+//------------------------------------------------------------------------------------------------------------------------------------

+// generate the 64 bit scom address for the GCR

+//------------------------------------------------------------------------------------------------------------------------------------

+uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );

+

+//------------------------------------------------------------------------------------------------------------------------------------

+// handle GCR operations - do not use directly!

+// use GCR_read and GCR_write for reg access - not this function!!!!

+//------------------------------------------------------------------------------------------------------------------------------------

+ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,

+                   gcr_op read_or_write, GCR_sub_registers target_io_reg,

+                   uint32_t group_address,  uint32_t lane_address,

+                   ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits,

+                   ecmdDataBufferBase &databuf_16bit, int skipCheck=0,int bypass_rmw=0);

+

+//------------------------------------------------------------------------------------------------------------------------------------

+// GCR SCOM READ  - main api for read - do not use doGCRop directly

+//------------------------------------------------------------------------------------------------------------------------------------

+ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,

+                     GCR_sub_registers target_io_reg, uint32_t group_address,

+                     uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);

+

+//------------------------------------------------------------------------------------------------------------------------------------

+// GCR SCOM WRITE  - main api for write - do not use doGCRop directly

+//------------------------------------------------------------------------------------------------------------------------------------

+ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface,

+                      GCR_sub_registers target_io_reg, uint32_t group_address,

+                      uint32_t lane_address,  ecmdDataBufferBase set_bits,

+                      ecmdDataBufferBase clear_bits, int skipCheck=0,int bypass_rmw=0);

+

+

+

+

+#endif

+

diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml b/src/usr/hwpf/hwp/bus_training/io_errors.xml
index 3aba85739..db1d0e266 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml
+++ b/src/usr/hwpf/hwp/bus_training/io_errors.xml
@@ -1,7 +1,7 @@
 <!--  IBM_PROLOG_BEGIN_TAG
      This is an automatically generated prolog.
    
-     $Source: src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml $
+     $Source: src/usr/hwpf/hwp/bus_training/io_errors.xml $
    
      IBM CONFIDENTIAL
    
@@ -20,7 +20,7 @@
      Origin: 30
    
      IBM_PROLOG_END_TAG -->
-<!-- Error definitions for io_run_training procedure -->
+<!-- Error definitions for IO HWPS  -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
@@ -99,4 +99,29 @@
     <rc>IO_RUN_TRAINING_INVALID_INVOCATION_RC</rc>
     <description>io run training invoked with wrong pair of targets</description>
   </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_OFFCAL_TIMEOUT_RC</rc>
+    <description>io offset cal timedout</description>
+  </hwpError>
+   <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_OFFCAL_ERROR_RC</rc>
+    <description>io offset cal errored out</description>
+  </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_INVALID_INVOCATION_RC</rc>
+    <description>io dc cal invoked with wrong pair of targets</description>
+  </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_ERROR_RC</rc>
+    <description>io impedance cal errored out</description>
+  </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_TIMEOUT_RC</rc>
+    <description>io impedance cal timed out</description>
+  </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
index fc5d352d7..29ffde61f 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C
@@ -73,11 +73,23 @@ ReturnCode  edi_training::run_training(const Target& master_target,  io_interfac
             }
             else{
                  // Get training function  status for Master Chip  (poll on the master chip's rx_wderf_done)
-                rc=training_function_status(master_target  ,  master_interface,master_group,   slave_target  ,  slave_interface,slave_group);
-                if(!rc.ok()){
-                    FAPI_ERR("io_run_training : Failed Training");
-                }
-            }
+		 if(master_interface==CP_FABRIC_X0){
+		    for (int current_group = 0 ; current_group < 4; current_group++)
+		    {
+		    rc=training_function_status(master_target  ,  master_interface,current_group,   slave_target  ,  slave_interface,current_group);
+			if(!rc.ok()){
+			    FAPI_ERR("io_run_training : Failed Training");
+			}
+		    }
+		 }
+		 else{
+		     rc=training_function_status(master_target  ,  master_interface,master_group,   slave_target  ,  slave_interface,slave_group);
+			if(!rc.ok()){
+			    FAPI_ERR("io_run_training : Failed Training");
+			}
+		    }
+		 }
+
         }
     return(rc);
 }
@@ -159,14 +171,16 @@ ReturnCode  edi_training::run_training_functions(const Target& target, io_interf
 		}
 		else
 		{
-			FAPI_DBG("io_run_training:Setting Training start bit on intereface %d group=%d\n",interface,current_group);
+
 			if(interface==CP_FABRIC_X0)
 			{
-			 rc=GCR_write(target ,  interface,  ei4_rx_training_start_pg, current_group,0,   set_bits, clear_bits);
+	      		       FAPI_DBG("io_run_training:Setting Training start bit via broadcast on interface %d group=%d\n",interface,current_group);
+   			       rc=GCR_write(target ,  interface,  ei4_rx_training_start_pg, 15,0,   set_bits, clear_bits,1,1);
 			}
 			else
 			{
-			 rc=GCR_write(target ,  interface,  rx_training_start_pg, current_group,0,   set_bits, clear_bits);
+  	           FAPI_DBG("io_run_training:Setting Training start bit on interface %d group=%d\n",interface,current_group);
+			   rc=GCR_write(target ,  interface,  rx_training_start_pg, current_group,0,   set_bits, clear_bits);
 			}
 			if (rc) {
 				 FAPI_ERR("io_run_training: Failed to write training start bits \n");
@@ -232,6 +246,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                       // Run First FAILED Data Capture for Wire Test for FAILED bus
                                        dump_ffdc_wiretest(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
 				       break;
+				    
                                     }
                                     else
                                     {
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H
index 41b8dccc7..aa2e79a3a 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H
@@ -49,7 +49,6 @@
 #define IO_funcs
 #include <fapi.H>
 #include "gcr_funcs.H"
-//#include "ei4_regs.h"
 
 using namespace fapi;
 
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C
index 55d79fe9c..222a4b818 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.C
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C
@@ -77,28 +77,20 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
           rc=init.isChipMaster(master_target,master_interface,master_group,is_master);
           if(rc.ok()){
                if(!is_master){
-                    //Swap master and slave targets !!
-                    FAPI_DBG("X Bus ..target swap performed");
-                    for(int i=0;i<5;++i){
-                     master_group=slave_group=i;
-                       FAPI_DBG("X Bus training for group %d",i);
+                     //Swap master and slave targets !!
+                     FAPI_DBG("X Bus ..target swap performed");
                      rc=init.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
                      //If one clock group cannot be trained.. bus cannot be used..so return rc to plat
                      if(!rc.ok()){
                          return(rc);
                      }
-                    }
-               }
+			   }
                else{
-                    for(int i=0;i<5;++i){
-                     master_group=slave_group=i;
-                     FAPI_DBG("X Bus training for group %d",i);
                      rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
                      //If one clock group cannot be trained.. bus cannot be used..so return rc to plat
                      if(!rc.ok()){
                          return(rc);
                      }
-                    }
                }
           }
      }
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.H b/src/usr/hwpf/hwp/bus_training/io_run_training.H
index 3692fbd0f..adc8e83f1 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.H
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.H
@@ -21,35 +21,34 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-#ifndef IO_RUN_TRAINING_H_
-#define IO_RUN_TRAINING_H_
-
-#include <fapi.H>
-#include "io_funcs.H"
-
-using namespace fapi;
-
-/**
- * io_run_training func pointer Typedef for hostboot 
- *
- */
-typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &);
-
-extern "C"
-{
-
-/**
- * io_run_training 
- *
- * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric 
- * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric
- * while these are called master or slave... I actually do a check in the code to see 
- * whether these are actually master chips by reading a GCR master_mode bit
- * and accordingly will perform a target swap if required 
- * @return ReturnCode
- */
-fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);
-
-} // extern "C"
-
-#endif // IO_RUN_TRAINING_H
+#ifndef IO_RUN_TRAINING_H_

+#define IO_RUN_TRAINING_H_

+

+#include <fapi.H>

+

+using namespace fapi;

+

+/**

+ * io_run_training func pointer Typedef for hostboot 

+ *

+ */

+typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &);

+

+extern "C"

+{

+

+/**

+ * io_run_training 

+ *

+ * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric 

+ * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric

+ * while these are called master or slave... I actually do a check in the code to see 

+ * whether these are actually master chips by reading a GCR master_mode bit

+ * and accordingly will perform a target swap if required 

+ * @return ReturnCode

+ */

+fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);

+

+} // extern "C"

+

+#endif // IO_RUN_TRAINING_H