HWP: Update HWPs with latest good versions

The selection of HWPs to pull into Hostboot was due to either:
1/ Thi needed to pull into Hostboot build for VPO to match Cronus level.
2/ Mike saw that latest code in eKB is a trivial update to current reviewed
version (usually just adding the cvs version number)
These changes have all passed the "HWP Review"

RTC: 46573
Change-Id: I50031a19e5b4f7ad0531cd58df9ec24034207664
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1499
Tested-by: Jenkins Server
Reviewed-by: Van H. Lee <vanlee@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

32 files changed, 582 insertions, 429 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/edi_regs.h b/src/usr/hwpf/hwp/bus_training/edi_regs.h
index 313b14b83..7dfdf3206 100644
--- a/src/usr/hwpf/hwp/bus_training/edi_regs.h
+++ b/src/usr/hwpf/hwp/bus_training/edi_regs.h
@@ -42,7 +42,7 @@
 //----------------------------------------------------- 
 // Constant file for edi_reg_attribute.txt_fixed
 // File generated at 16:23 on 8/31/2011 using system_pervasive/common/tools/CreateConstantsH.pl
-// $Id: edi_regs.h,v 1.8 2012/05/21 12:22:01 varkeykv Exp $
+// $Id: edi_regs.h,v 1.9 2012/07/28 04:03:12 jmcgill Exp $
 // $URL: $
 //
 // *!**************************************************************************
@@ -479,8 +479,8 @@ NUM_REGS
 
 
 // merged ei4 and edi ext addresses
-const uint32_t  GCR_sub_reg_ext_addr[] =     { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3,
-0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3
+const uint32_t  GCR_sub_reg_ext_addr[] =     { 0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x08E, 0x08F, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x199, 0x19A, 0x19B, 0x19C, 0x19D, 0x19F, 0x1A0, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D5, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DA, 0x1DB, 0x1DC, 0x1E0, 0x1E1, 0x1E2, 0x1E3, 0x1E4, 0x1E5, 0x1E6, 0x1E7, 0x1E8, 0x1E9, 0x000, 0x001, 0x002, 0x003, 0x005, 0x008, 0x009, 0x00A, 0x00B, 0x00C, 0x00D, 0x00E, 0x00F, 0x010, 0x011, 0x012, 0x013, 0x014, 0x016, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02A, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10D, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x137, 0x138, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x141, 0x142, 0x143, 0x145, 0x146, 0x147, 0x148, 0x149, 0x14A, 0x14B, 0x14C, 0x14D, 0x14E, 0x14F, 0x150, 0x151, 0x152, 0x153, 0x154, 0x155, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15E, 0x15F, 0x160, 0x161, 0x162, 0x168, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x16E, 0x16F, 0x170, 0x171, 0x172, 0x173, 0x174, 0x175, 0x176, 0x177, 0x178, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF,
+											   0x080, 0x081, 0x082, 0x085, 0x086, 0x087, 0x088, 0x08A, 0x08B, 0x08C, 0x08D, 0x180, 0x181, 0x182, 0x183, 0x184, 0x185, 0x186, 0x188, 0x189, 0x18A, 0x18B, 0x18C, 0x192, 0x193, 0x194, 0x198, 0x19D, 0x19F, 0x1A0, 0x1A1, 0x1A2, 0x1A3, 0x1A4, 0x1A5, 0x1A6, 0x1A7, 0x1A8, 0x1C7, 0x1C8, 0x1C9, 0x1CA, 0x1CB, 0x1CC, 0x1CD, 0x1CE, 0x1CF, 0x1D0, 0x1D1, 0x1D2, 0x1D3, 0x1D4, 0x1D6, 0x1D7, 0x1D8, 0x1D9, 0x1DB, 0x1DC, 0x000, 0x001, 0x002, 0x005, 0x008, 0x009, 0x00A, 0x00C, 0x00D, 0x00E, 0x00F, 0x016, 0x017, 0x018, 0x019, 0x01A, 0x01B, 0x01C, 0x01D, 0x01E, 0x01F, 0x020, 0x021, 0x022, 0x023, 0x024, 0x025, 0x026, 0x027, 0x028, 0x029, 0x02B, 0x02C, 0x02D, 0x100, 0x101, 0x102, 0x103, 0x104, 0x105, 0x106, 0x107, 0x108, 0x109, 0x10A, 0x10B, 0x10C, 0x10F, 0x110, 0x111, 0x112, 0x113, 0x114, 0x117, 0x11A, 0x11B, 0x11C, 0x11D, 0x11E, 0x11F, 0x120, 0x121, 0x122, 0x123, 0x124, 0x125, 0x126, 0x127, 0x128, 0x129, 0x12A, 0x12B, 0x12C, 0x12D, 0x12E, 0x12F, 0x130, 0x131, 0x132, 0x133, 0x134, 0x135, 0x136, 0x137, 0x139, 0x13A, 0x13B, 0x13C, 0x13D, 0x13E, 0x13F, 0x140, 0x142, 0x146, 0x147, 0x148, 0x149, 0x14E, 0x151, 0x152, 0x153, 0x154, 0x155, 0x156, 0x157, 0x158, 0x159, 0x15A, 0x15B, 0x15C, 0x15D, 0x15F, 0x160, 0x161, 0x162, 0x163, 0x164, 0x165, 0x166, 0x167, 0x169, 0x16A, 0x16B, 0x16C, 0x16D, 0x171, 0x172, 0x173, 0x175, 0x176, 0x177, 0x1F0, 0x1F1, 0x1F2, 0x1F3, 0x1FF
 };
 //merged ei4 and edi 
 const char* const GCR_sub_reg_names[] = {
@@ -700,7 +700,8 @@ const char* const GCR_sub_reg_names[] = {
 	"Per-Bus BUSCTL FIR Error Reset Reg",
 	"Per-Bus FIR Error Source-Isolation Reg",
 	"Per-Bus FIR Error Source-Isolation Mask Reg",
-	"Per-Bus FIR Error Injection Reg"
+	"Per-Bus FIR Error Injection Reg",
+    "Per-Bus FIR Register Write Alias",
 	"TX Lane Mode Reg",
 	"TX Cntl and Status Reg",
 	"TX Per-Lane Spare Mode Reg",
@@ -893,7 +894,8 @@ const char* const GCR_sub_reg_names[] = {
 	"Per-Bus BUSCTL FIR Error Reset Reg",
 	"Per-Bus FIR Error Source-Isolation Reg",
 	"Per-Bus FIR Error Source-Isolation Mask Reg",
-	"Per-Bus FIR Error Injection Reg"
+	"Per-Bus FIR Error Injection Reg",
+	"Per-Bus FIR Register Write Alias"
 };
 
 // tx_mode_pl Register field name                                       data value   Description
diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
index 3b5c01e27..6764b00b7 100644
--- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.C
@@ -68,7 +68,7 @@ ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,GCR_sub
 //------------------------------------------------------------------------------------------------------------------------------------

 // GCR SCOM WRITE  - main api for write - do not use doGCRop directly

 //------------------------------------------------------------------------------------------------------------------------------------

-ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, int skipCheck)

+ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, int skipCheck,int bypass_rmw)

 {

    ReturnCode rc;

    uint32_t rc_ecmd=0;

@@ -79,7 +79,7 @@ ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface, GCR_s
       rc.setEcmdError(rc_ecmd);

    }

    else{

-        rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck);

+        rc=doGCRop(chip_target, interface, gcr_op_write, target_io_reg, group_address, lane_address, set_bits, clear_bits, databuf_16bit, skipCheck,bypass_rmw);

         if(!rc.ok())

         {

           FAPI_ERR("Unexpected error while performing GCR OP \n");

@@ -125,7 +125,7 @@ uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data) {
 /* gcr2        readvalid 39        1       # read data valid bit                                                         */

 /*************************************************************************************************************************/

 

-ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck) {

+ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op read_or_write, GCR_sub_registers target_io_reg, uint32_t group_address,  uint32_t lane_address,  ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits, ecmdDataBufferBase &databuf_16bit, int skipCheck,int bypass_rmw) {

     ReturnCode rc;

     uint32_t rc_ecmd=0;

     uint64_t  scom_address64=0;

@@ -163,7 +163,12 @@ ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op
     {

         FAPI_DBG("ei_reg_addr_GCR_scom[interface]=%x\n",ei_reg_addr_GCR_scom[interface]);

         scom_address64 =scom_address_64bit(ei_reg_addr_GCR_scom[interface], getscom_data64.getDoubleWord(0));

-        rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+        if(!bypass_rmw){

+           rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+        }

+        else{

+         getscom_data64.flushTo0();

+        }

         if(!rc.ok())

         {

             FAPI_ERR("IO gcr_funcs:GETSCOM error occurred ********\n");

@@ -219,7 +224,9 @@ ReturnCode  doGCRop(const Target& chip_target, io_interface_t interface, gcr_op
                    else

                    {

                        // check the write

-                       rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+                       if(!skipCheck){

+                        rc = fapiGetScom( chip_target, scom_address64, getscom_data64 );

+                       }

                        if(!rc.ok()){

                        FAPI_ERR("IO gcr_funcs: GETSCOM error occurred\n");

                        return(rc);

diff --git a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
index 6fc15eaec..08d6eb355 100644
--- a/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/gcr_funcs.H
@@ -21,126 +21,126 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// *!***************************************************************************
-// *! (C) Copyright International Business Machines Corp. 1997, 1998
-// *!           All Rights Reserved -- Property of IBM
-// *!                   *** IBM Confidential ***
-// *!***************************************************************************
-// *! FILENAME             : gcr_funcs.H
-// *! TITLE                : 
-// *! DESCRIPTION          : 
-// *! CONTEXT              : 
-// *!
-// *! OWNER  NAME          : Varghese, Varkey         Email: varkeykv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
-// *!
-// *!***************************************************************************
-// CHANGE HISTORY:
-//------------------------------------------------------------------------------
-// Version:|Author: | Date:  | Comment:
-// --------|--------|--------|--------------------------------------------------
-//   1.0   |jaswamin|09/13/11|
-//   2.0   |varkeykv|01/12/12| Post GFW review changes
-//------------------------------------------------------------------------------
-
-#ifndef GCR_FUNCS
-#define GCR_FUNCS
-
-/* Include some system headers */
-#include <list>
-#include <stdint.h>
-#include <fapi.H>
-using namespace fapi;
-
-#include "edi_regs.h"
-
-
-enum io_interface_t {     CP_PSI,
-           CP_FABRIC_X0,
-           CP_FABRIC_A0, 
-           CP_IOMC0_P0,  
-           CP_IOMC1_P0,  
-           S1_FABRIC_SX0,
-           S1_FABRIC_SA0,
-           CEN_DMI,
-           };
-
-// P8 chip interfaces
-const uint32_t NUM_INTERFACES=21;
-const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",
-                                            "CP_FABRIC_X0", 
-                                            "CP_FABRIC_A0",
-                                            "CP_IOMC0_P0",  
-                                            "CP_IOMC1_P0",  
-                                            "S1_FABRIC_SX0",
-                                            "S1_FABRIC_SA0", 
-                                            "CEN_DMI" };
-// EDI register addresses for CP
-const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,
-                                                  0x0401103F,
-                                                  0x08010c3f, 
-                                                  0x02011a3F, 
-                                                  0x02011e3F,
-                                                  0x03010c3f,
-                                                  0x08010c3f, 
-                                                  0x0201043F  };
-const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,
-                                                  0x04011020, 
-                                                  0x08010c20, 
-                                                  0x02011a20, 
-                                                  0x02011e20,
-                                                  0x03010c20,
-                                                  0x08010c20, 
-                                                  0x02010420  };
-
-
-// Register type
-typedef enum { tx_per_lane,  tx_per_group,  tx_per_pack, tx_per_bus,  rx_per_lane,  rx_per_group,  rx_per_pack, rx_per_bus, num_register_type } register_type;
-
-typedef enum { gcr_op_read,  gcr_op_write }  gcr_op;
-
-
-// Lane Bit Defintions
-// 0x00  (lane 0),   0x01  (lane 1) , etc
-const uint8_t SELECT_ALL_LANES=0x1F;          // The lane address is a 5 bit value  0b 11111  selects all lanes
-
-// Group Bit Definitions 0x00 group 0 ,  0x01 group1 , etc
-const uint8_t  RX_GROUP_BROADCAST =0x0F ;       // (Write Only) The group address is a 6 bit value to select all groups ,
-const uint8_t  TX_GROUP_BROADCAST =0x2F  ;      // (Write Only) The group address is a 6 bit value to select all groups ,
-
-// ROUTINES
-//------------------------------------------------------------------------------------------------------------------------------------
-// generate the 64 bit scom address for the GCR
-//------------------------------------------------------------------------------------------------------------------------------------
-uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// handle GCR operations - do not use directly!
-// use GCR_read and GCR_write for reg access - not this function!!!!
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,
-                   gcr_op read_or_write, GCR_sub_registers target_io_reg,
-                   uint32_t group_address,  uint32_t lane_address,
-                   ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits,
-                   ecmdDataBufferBase &databuf_16bit, int skipCheck=0);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM READ  - main api for read - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,
-                     GCR_sub_registers target_io_reg, uint32_t group_address,
-                     uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);
-
-//------------------------------------------------------------------------------------------------------------------------------------
-// GCR SCOM WRITE  - main api for write - do not use doGCRop directly
-//------------------------------------------------------------------------------------------------------------------------------------
-ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface,
-                      GCR_sub_registers target_io_reg, uint32_t group_address,
-                      uint32_t lane_address,  ecmdDataBufferBase set_bits,
-                      ecmdDataBufferBase clear_bits, int skipCheck=0);
-
-
-
-
-#endif
-
+// *!***************************************************************************

+// *! (C) Copyright International Business Machines Corp. 1997, 1998

+// *!           All Rights Reserved -- Property of IBM

+// *!                   *** IBM Confidential ***

+// *!***************************************************************************

+// *! FILENAME             : gcr_funcs.H

+// *! TITLE                : 

+// *! DESCRIPTION          : 

+// *! CONTEXT              : 

+// *!

+// *! OWNER  NAME          : Varghese, Varkey         Email: varkeykv@in.ibm.com

+// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com

+// *!

+// *!***************************************************************************

+// CHANGE HISTORY:

+//------------------------------------------------------------------------------

+// Version:|Author: | Date:  | Comment:

+// --------|--------|--------|--------------------------------------------------

+//   1.0   |jaswamin|09/13/11|

+//   2.0   |varkeykv|01/12/12| Post GFW review changes

+//------------------------------------------------------------------------------

+

+#ifndef GCR_FUNCS

+#define GCR_FUNCS

+

+/* Include some system headers */

+#include <list>

+#include <stdint.h>

+#include <fapi.H>

+using namespace fapi;

+

+#include "edi_regs.h"

+

+

+enum io_interface_t {     CP_PSI,

+           CP_FABRIC_X0,

+           CP_FABRIC_A0, 

+           CP_IOMC0_P0,  

+           CP_IOMC1_P0,  

+           S1_FABRIC_SX0,

+           S1_FABRIC_SA0,

+           CEN_DMI,

+           };

+

+// P8 chip interfaces

+const uint32_t NUM_INTERFACES=21;

+const char * const io_interface_name[NUM_INTERFACES] = { "CP_PSI",

+                                            "CP_FABRIC_X0", 

+                                            "CP_FABRIC_A0",

+                                            "CP_IOMC0_P0",  

+                                            "CP_IOMC1_P0",  

+                                            "S1_FABRIC_SX0",

+                                            "S1_FABRIC_SA0", 

+                                            "CEN_DMI" };

+// EDI register addresses for CP

+const uint32_t ei_reg_addr_GCR_scom[NUM_INTERFACES] = { 0x00000000,

+                                                  0x0401103F,

+                                                  0x08010c3f, 

+                                                  0x02011a3F, 

+                                                  0x02011e3F,

+                                                  0x03010c3f,

+                                                  0x08010c3f, 

+                                                  0x0201043F  };

+const uint32_t ei_reg_addr_Mode_scom[NUM_INTERFACES]= { 0x00000000,

+                                                  0x04011020, 

+                                                  0x08010c20, 

+                                                  0x02011a20, 

+                                                  0x02011e20,

+                                                  0x03010c20,

+                                                  0x08010c20, 

+                                                  0x02010420  };

+

+

+// Register type

+typedef enum { tx_per_lane,  tx_per_group,  tx_per_pack, tx_per_bus,  rx_per_lane,  rx_per_group,  rx_per_pack, rx_per_bus, num_register_type } register_type;

+

+typedef enum { gcr_op_read,  gcr_op_write }  gcr_op;

+

+

+// Lane Bit Defintions

+// 0x00  (lane 0),   0x01  (lane 1) , etc

+const uint8_t SELECT_ALL_LANES=0x1F;          // The lane address is a 5 bit value  0b 11111  selects all lanes

+

+// Group Bit Definitions 0x00 group 0 ,  0x01 group1 , etc

+const uint8_t  RX_GROUP_BROADCAST =0x0F ;       // (Write Only) The group address is a 6 bit value to select all groups ,

+const uint8_t  TX_GROUP_BROADCAST =0x2F  ;      // (Write Only) The group address is a 6 bit value to select all groups ,

+

+// ROUTINES

+//------------------------------------------------------------------------------------------------------------------------------------

+// generate the 64 bit scom address for the GCR

+//------------------------------------------------------------------------------------------------------------------------------------

+uint64_t scom_address_64bit(uint32_t gcr_addr, uint64_t gcr_data );

+

+//------------------------------------------------------------------------------------------------------------------------------------

+// handle GCR operations - do not use directly!

+// use GCR_read and GCR_write for reg access - not this function!!!!

+//------------------------------------------------------------------------------------------------------------------------------------

+ReturnCode doGCRop(const Target& chip_target, io_interface_t interface,

+                   gcr_op read_or_write, GCR_sub_registers target_io_reg,

+                   uint32_t group_address,  uint32_t lane_address,

+                   ecmdDataBufferBase set_bits,  ecmdDataBufferBase clear_bits,

+                   ecmdDataBufferBase &databuf_16bit, int skipCheck=0,int bypass_rmw=0);

+

+//------------------------------------------------------------------------------------------------------------------------------------

+// GCR SCOM READ  - main api for read - do not use doGCRop directly

+//------------------------------------------------------------------------------------------------------------------------------------

+ReturnCode  GCR_read(const Target& chip_target, io_interface_t interface,

+                     GCR_sub_registers target_io_reg, uint32_t group_address,

+                     uint32_t lane_address, ecmdDataBufferBase &databuf_16bit);

+

+//------------------------------------------------------------------------------------------------------------------------------------

+// GCR SCOM WRITE  - main api for write - do not use doGCRop directly

+//------------------------------------------------------------------------------------------------------------------------------------

+ReturnCode  GCR_write(const Target& chip_target, io_interface_t interface,

+                      GCR_sub_registers target_io_reg, uint32_t group_address,

+                      uint32_t lane_address,  ecmdDataBufferBase set_bits,

+                      ecmdDataBufferBase clear_bits, int skipCheck=0,int bypass_rmw=0);

+

+

+

+

+#endif

+

diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml b/src/usr/hwpf/hwp/bus_training/io_errors.xml
index 3aba85739..db1d0e266 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml
+++ b/src/usr/hwpf/hwp/bus_training/io_errors.xml
@@ -1,7 +1,7 @@
 <!--  IBM_PROLOG_BEGIN_TAG
      This is an automatically generated prolog.
    
-     $Source: src/usr/hwpf/hwp/bus_training/io_run_training_errors.xml $
+     $Source: src/usr/hwpf/hwp/bus_training/io_errors.xml $
    
      IBM CONFIDENTIAL
    
@@ -20,7 +20,7 @@
      Origin: 30
    
      IBM_PROLOG_END_TAG -->
-<!-- Error definitions for io_run_training procedure -->
+<!-- Error definitions for IO HWPS  -->
 <hwpErrors>
   <!-- *********************************************************************** -->
   <hwpError>
@@ -99,4 +99,29 @@
     <rc>IO_RUN_TRAINING_INVALID_INVOCATION_RC</rc>
     <description>io run training invoked with wrong pair of targets</description>
   </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_OFFCAL_TIMEOUT_RC</rc>
+    <description>io offset cal timedout</description>
+  </hwpError>
+   <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_OFFCAL_ERROR_RC</rc>
+    <description>io offset cal errored out</description>
+  </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_INVALID_INVOCATION_RC</rc>
+    <description>io dc cal invoked with wrong pair of targets</description>
+  </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_ERROR_RC</rc>
+    <description>io impedance cal errored out</description>
+  </hwpError>
+     <!-- *********************************************************************** -->
+  <hwpError>
+    <rc>IO_DCCAL_ZCAL_TIMEOUT_RC</rc>
+    <description>io impedance cal timed out</description>
+  </hwpError>
 </hwpErrors>
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.C b/src/usr/hwpf/hwp/bus_training/io_funcs.C
index fc5d352d7..29ffde61f 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.C
@@ -73,11 +73,23 @@ ReturnCode  edi_training::run_training(const Target& master_target,  io_interfac
             }
             else{
                  // Get training function  status for Master Chip  (poll on the master chip's rx_wderf_done)
-                rc=training_function_status(master_target  ,  master_interface,master_group,   slave_target  ,  slave_interface,slave_group);
-                if(!rc.ok()){
-                    FAPI_ERR("io_run_training : Failed Training");
-                }
-            }
+		 if(master_interface==CP_FABRIC_X0){
+		    for (int current_group = 0 ; current_group < 4; current_group++)
+		    {
+		    rc=training_function_status(master_target  ,  master_interface,current_group,   slave_target  ,  slave_interface,current_group);
+			if(!rc.ok()){
+			    FAPI_ERR("io_run_training : Failed Training");
+			}
+		    }
+		 }
+		 else{
+		     rc=training_function_status(master_target  ,  master_interface,master_group,   slave_target  ,  slave_interface,slave_group);
+			if(!rc.ok()){
+			    FAPI_ERR("io_run_training : Failed Training");
+			}
+		    }
+		 }
+
         }
     return(rc);
 }
@@ -159,14 +171,16 @@ ReturnCode  edi_training::run_training_functions(const Target& target, io_interf
 		}
 		else
 		{
-			FAPI_DBG("io_run_training:Setting Training start bit on intereface %d group=%d\n",interface,current_group);
+
 			if(interface==CP_FABRIC_X0)
 			{
-			 rc=GCR_write(target ,  interface,  ei4_rx_training_start_pg, current_group,0,   set_bits, clear_bits);
+	      		       FAPI_DBG("io_run_training:Setting Training start bit via broadcast on interface %d group=%d\n",interface,current_group);
+   			       rc=GCR_write(target ,  interface,  ei4_rx_training_start_pg, 15,0,   set_bits, clear_bits,1,1);
 			}
 			else
 			{
-			 rc=GCR_write(target ,  interface,  rx_training_start_pg, current_group,0,   set_bits, clear_bits);
+  	           FAPI_DBG("io_run_training:Setting Training start bit on interface %d group=%d\n",interface,current_group);
+			   rc=GCR_write(target ,  interface,  rx_training_start_pg, current_group,0,   set_bits, clear_bits);
 			}
 			if (rc) {
 				 FAPI_ERR("io_run_training: Failed to write training start bits \n");
@@ -232,6 +246,7 @@ ReturnCode  edi_training::training_function_status(const Target&  master_chip_ta
                                       // Run First FAILED Data Capture for Wire Test for FAILED bus
                                        dump_ffdc_wiretest(master_chip_target, master_chip_interface , master_group, slave_chip_target ,  slave_chip_interface,slave_group);
 				       break;
+				    
                                     }
                                     else
                                     {
diff --git a/src/usr/hwpf/hwp/bus_training/io_funcs.H b/src/usr/hwpf/hwp/bus_training/io_funcs.H
index 41b8dccc7..aa2e79a3a 100644
--- a/src/usr/hwpf/hwp/bus_training/io_funcs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_funcs.H
@@ -49,7 +49,6 @@
 #define IO_funcs
 #include <fapi.H>
 #include "gcr_funcs.H"
-//#include "ei4_regs.h"
 
 using namespace fapi;
 
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.C b/src/usr/hwpf/hwp/bus_training/io_run_training.C
index 55d79fe9c..222a4b818 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.C
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.C
@@ -77,28 +77,20 @@ ReturnCode io_run_training(const Target &master_target,const Target &slave_targe
           rc=init.isChipMaster(master_target,master_interface,master_group,is_master);
           if(rc.ok()){
                if(!is_master){
-                    //Swap master and slave targets !!
-                    FAPI_DBG("X Bus ..target swap performed");
-                    for(int i=0;i<5;++i){
-                     master_group=slave_group=i;
-                       FAPI_DBG("X Bus training for group %d",i);
+                     //Swap master and slave targets !!
+                     FAPI_DBG("X Bus ..target swap performed");
                      rc=init.run_training(slave_target,slave_interface,slave_group,master_target,master_interface,master_group);
                      //If one clock group cannot be trained.. bus cannot be used..so return rc to plat
                      if(!rc.ok()){
                          return(rc);
                      }
-                    }
-               }
+			   }
                else{
-                    for(int i=0;i<5;++i){
-                     master_group=slave_group=i;
-                     FAPI_DBG("X Bus training for group %d",i);
                      rc=init.run_training(master_target,master_interface,master_group,slave_target,slave_interface,slave_group);
                      //If one clock group cannot be trained.. bus cannot be used..so return rc to plat
                      if(!rc.ok()){
                          return(rc);
                      }
-                    }
                }
           }
      }
diff --git a/src/usr/hwpf/hwp/bus_training/io_run_training.H b/src/usr/hwpf/hwp/bus_training/io_run_training.H
index 3692fbd0f..adc8e83f1 100644
--- a/src/usr/hwpf/hwp/bus_training/io_run_training.H
+++ b/src/usr/hwpf/hwp/bus_training/io_run_training.H
@@ -21,35 +21,34 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-#ifndef IO_RUN_TRAINING_H_
-#define IO_RUN_TRAINING_H_
-
-#include <fapi.H>
-#include "io_funcs.H"
-
-using namespace fapi;
-
-/**
- * io_run_training func pointer Typedef for hostboot 
- *
- */
-typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &);
-
-extern "C"
-{
-
-/**
- * io_run_training 
- *
- * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric 
- * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric
- * while these are called master or slave... I actually do a check in the code to see 
- * whether these are actually master chips by reading a GCR master_mode bit
- * and accordingly will perform a target swap if required 
- * @return ReturnCode
- */
-fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);
-
-} // extern "C"
-
-#endif // IO_RUN_TRAINING_H
+#ifndef IO_RUN_TRAINING_H_

+#define IO_RUN_TRAINING_H_

+

+#include <fapi.H>

+

+using namespace fapi;

+

+/**

+ * io_run_training func pointer Typedef for hostboot 

+ *

+ */

+typedef fapi::ReturnCode (*io_run_training_FP_t)(const fapi::Target &,const fapi::Target &);

+

+extern "C"

+{

+

+/**

+ * io_run_training 

+ *

+ * master_target is the master side of a bus ..p8.mcs in a DMI .. or a p8.abus/p8.xbus in fabric 

+ * slave_target - slave side of the bus .. Centaur in DMI , p8.xbus or p8.abus for fabric

+ * while these are called master or slave... I actually do a check in the code to see 

+ * whether these are actually master chips by reading a GCR master_mode bit

+ * and accordingly will perform a target swap if required 

+ * @return ReturnCode

+ */

+fapi::ReturnCode io_run_training(const fapi::Target &master_target,const fapi::Target & slave_target);

+

+} // extern "C"

+

+#endif // IO_RUN_TRAINING_H

diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
index e81be6161..29712d68a 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.C
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_cen_framelock.C,v 1.6 2012/06/01 02:47:07 jmcgill Exp $
+// $Id: proc_cen_framelock.C,v 1.7 2012/07/23 14:15:46 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -40,6 +40,8 @@
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
+#include "p8_scom_addresses.H"
+#include "cen_scom_addresses.H"
 #include "proc_cen_framelock.H"
 
 extern "C"
diff --git a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
index 43b038840..78c20c35b 100644
--- a/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
+++ b/src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H
@@ -1,26 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
-// $Id: proc_cen_framelock.H,v 1.5 2012/04/11 06:24:13 jmcgill Exp $
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dmi_training/proc_cen_framelock/proc_cen_framelock.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: proc_cen_framelock.H,v 1.6 2012/07/23 14:15:49 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_cen_framelock.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -52,8 +53,6 @@
 //------------------------------------------------------------------------------
 
 #include <fapi.H>
-#include "p8_scom_addresses.H"
-#include "cen_scom_addresses.H"
 
 //------------------------------------------------------------------------------
 // Structure definitions
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
index 08c817a92..30cc399b8 100644
--- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_extent_setup.C,v 1.8 2012/07/17 13:24:10 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -31,6 +32,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.8    | bellows  |16-Jul-12| added in Id tag
 //  1.7    | bellows  |15-Jun-12| Updated for Firmware
 //  1.3    | gpaulraj |11-Nov-11| modified according HWPF format
 //  1.2    | gpaulraj |02-oct-11| supported for MCS loop - SIM model. compiled in the ecmd & FAPI calls included.
diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
index a2a131174..be03117f0 100755
--- a/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
+++ b/src/usr/hwpf/hwp/dram_initialization/mss_extent_setup/mss_extent_setup.H
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_extent_setup.H,v 1.8 2012/07/17 13:22:51 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -41,6 +42,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.8    | bellows  |16-Jul-12| added in Id tag
 //  1.7    | bellows  |15-Jun-12| Updated for Firmware
 //   1.2   |          |         |
 //   1.1   | gpaulraj |11-NOV-11| First Draft.
@@ -54,6 +56,7 @@ typedef fapi::ReturnCode (*mss_extent_setup_FP_t)();
 
 extern "C"
 {
+
 /**
  * @brief extent setup  procedure -- currently an open shell until extent functions are found t obe needed 
  *
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
index e64236331..8e3db1748 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.C
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_setup_bars.C,v 1.3 2012/06/12 02:44:04 jmcgill Exp $
+// $Id: proc_setup_bars.C,v 1.5 2012/07/23 17:47:05 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -75,6 +75,7 @@ extern "C" {
 // Function definitions
 //------------------------------------------------------------------------------
 
+
 //------------------------------------------------------------------------------
 // function: utility function to display address range/BAR information and
 //           check properties
@@ -154,9 +155,9 @@ bool proc_setup_bars_common_do_ranges_overlap(
     // check that ranges are non-overlapping
     if (i_ranges.size() > 1)
     {
-        for (uint8_t r = 0; (r < i_ranges.size()-1) && !overlap; r++)
+        for (size_t r = 0; (r < i_ranges.size()-1) && !overlap; r++)
         {
-            for (uint8_t x = r+1; x < i_ranges.size(); x++)
+            for (size_t x = r+1; x < i_ranges.size(); x++)
             {
                 if (i_ranges[r]->overlaps(*(i_ranges[x])))
                 {
diff --git a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
index 439bfe21d..df3acb937 100644
--- a/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
+++ b/src/usr/hwpf/hwp/dram_initialization/proc_setup_bars/proc_setup_bars.H
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_setup_bars.H,v 1.2 2012/06/12 02:44:02 jmcgill Exp $
+// $Id: proc_setup_bars.H,v 1.3 2012/07/23 17:47:41 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_setup_bars.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -211,19 +211,14 @@ struct proc_setup_bars_addr_range
     // round region size to next largest power of 2
     void round_next_power_of_2()
     {
-        uint64_t size_round;
-        // if size is zero/one, leave as is
-        if ((size != 0) && (size != 1))
-        {
-            // shift until new size is greater than or
-            // equal to existing size
-            for (size_round = 0x1ULL;
-                 size_round < size;
-                 size_round = (size_round << 1))
-            {
-            }
-            size = size_round;
-        }
+        size = size - 1;
+        size = size | (size >> 1);
+        size = size | (size >> 2);
+        size = size | (size >> 4);
+        size = size | (size >> 8);
+        size = size | (size >> 16);
+        size = size | (size >> 32);
+        size = size + 1;
     }
 
     // return ending address of range
@@ -236,10 +231,10 @@ struct proc_setup_bars_addr_range
     bool overlaps(const proc_setup_bars_addr_range& range_compare) const
     {
         // if either range is disabled, consider them non-overlapping
-        return(!(!enabled ||
-                 !range_compare.enabled ||
-                 ((end_addr() < range_compare.base_addr) ||
-                  (base_addr > range_compare.end_addr()))));
+        return(enabled &&
+               range_compare.enabled &&
+               (base_addr <= range_compare.end_addr()) &&
+               (end_addr() >= range_compare.base_addr));
     }
 
     // merge two ranges (span breadth of both ranges)
diff --git a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
index 2322a5a1b..4032787f5 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_ddr_phy_reset/mss_ddr_phy_reset.C
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: mss_ddr_phy_reset.C,v 1.9 2012/07/18 16:27:39 mfred Exp $
+// $Id: mss_ddr_phy_reset.C,v 1.11 2012/07/27 16:43:25 bellows Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_ddr_phy_reset.C,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -64,6 +64,10 @@ extern "C" {
 
 using namespace fapi;
 
+   // prototype of function called in phy reset
+ReturnCode mss_deassert_force_mclk_low (const Target& i_target); 
+
+
 fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
 {
     // Target is centaur.mba
@@ -98,7 +102,6 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
         //
         // Run cen_ddr_phy_reset.C prepares the DDR PLLs. These PLLs were previously configured via scan init, but have
         // been held in reset. At this point the PLL GP bit is deasserted to take the PLLs out of reset.
-        // Note - this is done in the cen_startclocks.C procedure.
         //
         // The cen_ddr_phy_reset.C now resets the DDR PHY logic. This process will NOT destroy any configuration values
         // previously loaded via the init file. The intent is for the initialized phase rotator configuration to remain valid after the
@@ -107,7 +110,18 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
         //
         // The following steps must be performed as part of the PHY reset procedure.
   
-  
+
+         // PLL Lock cannot happen if mclk low is asserted
+        // this procedure was moved from draminit to:
+        // Deassert Force_mclk_low signal
+        // see CQ 216395
+        rc = mss_deassert_force_mclk_low(i_target);
+        if(rc)
+        {
+            FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            return rc;
+        }
+
   
         //
         // 1. Drive all control signals to the PHY to their inactive state, idle state, or inactive value.
@@ -827,6 +841,28 @@ fapi::ReturnCode mss_ddr_phy_reset(const fapi::Target & i_target)
     return rc;
 }
 
+// function moved from draminit because we need mclk low not asserted for pll locking
+ReturnCode mss_deassert_force_mclk_low (const Target& i_target)
+{ 
+    ReturnCode rc;
+    uint32_t rc_num = 0;
+    ecmdDataBufferBase data_buffer(64);
+
+    FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++");
+
+
+    rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
+    if(rc) return rc;
+    rc_num = data_buffer.setBit(63);
+    rc.setEcmdError( rc_num);
+    if(rc) return rc;
+    rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
+    if(rc) return rc;
+
+    return rc;
+}
+
+
 } //end extern C
 
 
@@ -839,6 +875,12 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: mss_ddr_phy_reset.C,v $
+Revision 1.11  2012/07/27 16:43:25  bellows
+CQ216395 hardware needs force mclk low in phy reset procedure
+
+Revision 1.10  2012/07/24 17:11:02  mfred
+Removed confusing comment.
+
 Revision 1.9  2012/07/18 16:27:39  mfred
 Check for ATTR_IS_SIMULATION attribute instead of use compiler switch.
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index f3400b38b..718a52bad 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_draminit.C,v 1.35 2012/07/27 16:44:38 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +29,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.35   | bellows  | 7/25/12 | CQ 216395 (move force mclk low deassert to phyreset, resetn toggle)
+//  1.34   | bellows  | 7/16/12 | added in Id tag
 //  1.33   | jdsloat  | 6/26/12 | Added rtt_nom rank by rank value.
 //  1.32   | jdsloat  | 6/11/12 | Fixed Attributes: RTT_NOM, CL, DRAM_WR within the MRS load.
 //  1.31   | bellows  | 5/24/12 | Removed GP Bit 
@@ -99,7 +102,14 @@ ReturnCode mss_rcd_load( Target& i_target, uint32_t i_port_number, uint32_t& io_
 ReturnCode mss_mrs_load( Target& i_target, uint32_t i_port_number, uint32_t& io_ccs_inst_cnt);
 ReturnCode mss_assert_resetn_drive_mem_clks( Target& i_target);
 ReturnCode mss_deassert_force_mclk_low( Target& i_target);
+ReturnCode mss_assert_resetn ( Target& i_target, uint8_t value);
 
+const uint64_t  DELAY_100NS             = 100;      // general purpose 100 ns delay for HW mode   (2000 sim cycles if simclk = 20ghz)
+const uint64_t  DELAY_1US               = 1000;     // general purpose 1 usec delay for HW mode   (20000 sim cycles if simclk = 20ghz)
+const uint64_t  DELAY_100US             = 100000;   // general purpose 100 usec delay for HW mode (2000000 sim cycles if simclk = 20ghz)
+const uint64_t  DELAY_2000SIMCYCLES     = 2000;     // general purpose 2000 sim cycle delay for sim mode     (100 ns if simclk = 20Ghz)
+const uint64_t  DELAY_20000SIMCYCLES    = 20000;    // general purpose 20000 sim cycle delay for sim mode    (1 usec if simclk = 20Ghz)
+const uint64_t  DELAY_2000000SIMCYCLES  = 2000000;  // general purpose 2000000 sim cycle delay for sim mode  (100 usec if simclk = 20Ghz)
 
 ReturnCode mss_draminit(Target& i_target)
 {
@@ -125,22 +135,30 @@ ReturnCode mss_draminit(Target& i_target)
         //MASTER_ATTENTION_REG_CHECK();
 
         // Step one: Deassert Force_mclk_low signal     
-        rc = mss_deassert_force_mclk_low(i_target);
+      // this action needs to be done in ddr_phy_reset so that the plls can actually lock
+
+        // Step two: Assert Resetn signal, Begin driving mem clks
+        rc = mss_assert_resetn_drive_mem_clks(i_target);
         if(rc)
         {
-            FAPI_ERR(" deassert_force_mclk_low Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            FAPI_ERR(" assert_resetn_drive_mem_clks Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
             return rc;
         }
 
-
-        // Step two: Assert Resetn signal, Begin driving mem clks
-        rc = mss_assert_resetn_drive_mem_clks(i_target);
+        rc = mss_assert_resetn(i_target, 0 ); // assert a reset
         if(rc)
         {
-            FAPI_ERR(" assert_resetn_drive_mem_clks Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
             return rc;
         }
+        rc = fapiDelay(DELAY_100US, DELAY_2000SIMCYCLES); // wait 2000 simcycles (in sim mode) OR 100 uS (in hw mode)
 
+        rc = mss_assert_resetn(i_target, 1 ); // de-assert a reset
+        if(rc)
+        {
+            FAPI_ERR(" assert_resetn Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator());
+            return rc;
+        }
         // Cycle through Ports...
         // Ports 0-1
         for ( port_number = 0; port_number < MAX_NUM_PORTS; port_number++)
@@ -222,26 +240,6 @@ ReturnCode mss_draminit(Target& i_target)
 
 
 
-ReturnCode mss_deassert_force_mclk_low (Target& i_target)
-{ 
-    ReturnCode rc;
-    uint32_t rc_num = 0;
-    ecmdDataBufferBase data_buffer(64);
-
-    FAPI_INF( "+++++++++++++++++++++ DEASSERTING FORCE MCLK LOW +++++++++++++++++++++");
-
-
-    rc = fapiGetScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
-    if(rc) return rc;
-    rc_num = data_buffer.setBit(63);
-    rc.setEcmdError( rc_num);
-    if(rc) return rc;
-    rc = fapiPutScom(i_target, MEM_MBA01_CCS_MODEQ_0x030106A7, data_buffer);
-    if(rc) return rc;
-
-    return rc;
-}
-
 ReturnCode mss_assert_resetn_drive_mem_clks(
             Target& i_target
             )
@@ -1035,5 +1033,39 @@ ReturnCode mss_mrs_load(
     return rc;
 }
 
+ReturnCode mss_assert_resetn (
+            Target& i_target,
+            uint8_t value
+            )
+{    
+// value of 1 deasserts reset
+
+    ReturnCode rc;
+    ReturnCode rc_buff;
+    uint32_t rc_num = 0;
+    ecmdDataBufferBase data_buffer(64);
+
+    FAPI_INF( "+++++++++++++++++++++ ASSERTING RESETN to the value of %d +++++++++++++++++++++", value);
+
+    rc = fapiGetScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
+    if(rc) return rc;
+
+    //Setting up CCS mode
+    rc_num = rc_num | data_buffer.insert( value, 24, 1, 7); // use bit 7
+
+    if (rc_num)
+    {
+        FAPI_ERR( "mss_ccs_mode: Error setting up buffers");
+        rc_buff.setEcmdError(rc_num);
+        return rc_buff;
+    }
+
+    rc = fapiPutScom(i_target, CCS_MODEQ_AB_REG_0x030106A7, data_buffer);
+    if(rc) return rc;
+
+    return rc;
+}
+
+
 } //end extern C
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
index 49f7a8772..f08e71da8 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_draminit_mc.C,v 1.24 2012/07/17 13:23:51 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -44,6 +45,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.24   | bellows  |16-JUL-12| added in Id tag
+//  1.22   | bellows  |13-JUL-12| Fixed periodic cal bit 61 being set. HW214829
 //  1.20   | jdsloat  |21-MAY-12| Typo fix, addresses moved to cen_scom_addresses.H, moved per cal settings to initfile
 //  1.19   | jdsloat  |08-MAY-12| All Refresh controls moved to initfile, changed to just enable refresh
 //  1.18   | jdsloat  |07-MAY-12| Fixed refresh interval, trfc, ref check interval bit ordering
@@ -165,14 +168,13 @@ ReturnCode mss_draminit_mc (Target& i_target)
 	}
 
         // Step Four: Setup Periodic Cals
-        FAPI_INF( "+++ Skipping Periodic Cals +++");
-        // FAPI_INF( "+++ Setting Up Periodic Cals +++");
-        // rc = mss_enable_periodic_cal(l_mbaChiplets[i]);
-        // if(rc)
-        // {
-        //    FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-        //    return rc;
-        // }
+        FAPI_INF( "+++ Setting Up Periodic Cals +++");
+        rc = mss_enable_periodic_cal(l_mbaChiplets[i]);
+        if(rc)
+        {
+           FAPI_ERR("---Error During Periodic Cal Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+           return rc;
+        }
 
         // Step Five: Setup Power Management
         FAPI_INF( "+++ Setting Up Power Management +++");
@@ -280,7 +282,8 @@ ReturnCode mss_enable_periodic_cal (Target& i_target)
     }
 
     //Start the periodic Cal
-     rc_num = rc_num | mba01_data_buffer_64_p1.setBit(61);
+    // do not set bit 61 - HW214829
+    // rc_num = rc_num | mba01_data_buffer_64_p1.setBit(61);
 
     //Write the mba_p01_PER_CAL_CFG_REG
     rc = fapiPutScom(i_target, DPHY01_DDRPHY_PC_PER_CAL_CONFIG_P0_0x8000C00B0301143F, mba01_data_buffer_64_p0);
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
index c99d5c910..f296353e8 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H
@@ -1,25 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: mss_draminit_mc.H,v 1.5 2012/07/17 13:22:39 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -27,6 +29,7 @@
 //------------------------------------------------------------------------------
 // Version:|   Date:  | Author:  | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.5    | 07/16/12 | bellows  | added in Id tag
 //  1.4    | 03/07/12 | jdsloat  | changed target to centaur
 //  1.3    | 02/17/12 | jdsloat  | Added the other &
 //  1.1    | 02/02/12 | jdsloat  | Added & and description of target type
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
index c07e9edc1..59ef4df63 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_draminit_training.C,v 1.29 2012/07/17 13:23:56 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +29,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|------------------------------------------------
+//  1.29   | bellows  |16-Jul-12| bellows | added in Id tag
 //  1.28   | bellows  |02-May-12| cal ranks are 4 bits, this needed to be adjusted
 //  1.26   | asaetow  |12-Apr-12| Added "if(rc) return rc;" at line 180.
 //  1.25   | asaetow  |06-Apr-12| Added "if(rc) return rc;" at line 165.
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
index d00e1d0a4..392f9a525 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H
@@ -1,25 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_draminit_training/mss_draminit_training.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: mss_draminit_training.H,v 1.3 2012/07/17 13:22:42 bellows Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -27,6 +29,7 @@
 //------------------------------------------------------------------------------
 // Version:|   Date:  | Author:  | Comment:
 //---------|----------|----------|-----------------------------------------------
+//  1.3    | 07/16/12 | bellows | added in Id tag
 //  1.1    | 02/20/12 | divyakum | Added target description
 //  1.0    | 11/14/11 | divyakum | First draft.
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.C b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
index 0a05cb6f7..5395b5cd8 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.C
@@ -1,25 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.C $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: mss_funcs.C,v 1.28 2012/07/17 13:24:16 bellows Exp $
 /* File mss_funcs.C created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
 
 //------------------------------------------------------------------------------
@@ -42,7 +44,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//  1.26   | divyakum | 3/22/12 | Fixed warnings from mss_execute_zq_cal function
+//  1.28   | bellows  | 07/16/12|added in Id tag
+//  1.27   | divyakum | 3/22/12 | Fixed warnings from mss_execute_zq_cal function
 //  1.26   | divyakum | 3/22/12 | Fixed mss_execute_zq_cal function variable name mismatch
 //  1.25   | divyakum | 3/21/12 | Added mss_execute_zq_cal function
 //  1.24   | jdsloat  | 3/20/12 | ccs_inst_arry0 bank fields reverse function removed
@@ -324,7 +327,7 @@ ReturnCode mss_ccs_start_stop(
         rc_buff.setEcmdError(rc_num);
         return rc_buff;
     }
-    
+
     rc = fapiPutScom(i_target, CCS_CNTLQ_AB_REG_0x030106A5, data_buffer);
 
     return rc;
diff --git a/src/usr/hwpf/hwp/dram_training/mss_funcs.H b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
index 6046e10aa..d87c4d9b8 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_funcs.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_funcs.H
@@ -1,25 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/dram_training/mss_funcs.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: mss_funcs.H,v 1.12 2012/07/17 13:22:58 bellows Exp $
 /* File mss_funcs.H created by SLOAT JACOB D. (JAKE),2D3970 on Fri Apr 22 2011. */
 
 //------------------------------------------------------------------------------
@@ -42,6 +44,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.12   | 07/16/12 | bellows | added in Id tag
 //  1.11   | 3/21/12  | divyakum| Added mss_execute_zq_cal function 
 //  1.10   | 2/14/12  | jdsloat | Comment section filled in, elimated unnecessary constant, added enums
 //  1.9    | 2/08/12  | jdsloat | Target to Target&
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
index a79ce3cea..7750001dd 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_scominit.C,v 1.8 2012/07/17 13:24:42 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -41,7 +42,8 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//	 1.7   | menlowuu |14-JUN-12| Added fixes suggested by Mike,
+//   1.8   | bellows  |16-JUL-12| added in Id tag
+//   1.7   | menlowuu |14-JUN-12| Added fixes suggested by Mike,
 //	 					replace rc_num with ReturnCode, created RC for when
 //	 					MBAs != 2, and return on all errors 
 //   1.6   | menlowuu |08-JUN-12| Fixed inserting centaur vector & return code.
diff --git a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
index 6e1865528..8c3b03aa5 100644
--- a/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
+++ b/src/usr/hwpf/hwp/dram_training/mss_scominit/mss_scominit.H
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_scominit.H,v 1.5 2012/07/17 13:23:28 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -41,8 +42,9 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
-//	 1.4   | menlowuu |20-JUN-12| added type to the typedef
-//	 1.3   | menlowuu |13-JUN-12| added & to reference i_target in FP_t function
+//   1.5   |bellows   |16-JUL-12| added in Id tag
+//   1.4   | menlowuu |20-JUN-12| added type to the typedef
+//   1.3   | menlowuu |13-JUN-12| added & to reference i_target in FP_t function
 //	 							  added comment expecting centaur target
 //   1.2   | menlowuu |06-JUN-12| Removed char* parameter for function
 //   0.1   | menlowuu |01-DEC-11| First Draft.
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C
index e25250f13..32bd122a1 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C
+++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.C
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_fab_iovalid.C,v 1.7 2012/05/18 18:03:06 jmcgill Exp $
+// $Id: proc_fab_iovalid.C,v 1.8 2012/07/23 14:15:51 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.C,v $
 //------------------------------------------------------------------------------
 // *|
@@ -40,6 +40,7 @@
 //------------------------------------------------------------------------------
 // Includes
 //------------------------------------------------------------------------------
+#include "p8_scom_addresses.H"
 #include "proc_fab_iovalid.H"
 
 extern "C"
diff --git a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H
index 490774fe8..bcc195a31 100644
--- a/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H
+++ b/src/usr/hwpf/hwp/edi_ei_initialization/proc_fab_iovalid/proc_fab_iovalid.H
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: proc_fab_iovalid.H,v 1.7 2012/05/18 18:03:09 jmcgill Exp $
+// $Id: proc_fab_iovalid.H,v 1.8 2012/07/23 14:15:54 jmcgill Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ipl/fapi/proc_fab_iovalid.H,v $
 //------------------------------------------------------------------------------
 // *|
@@ -57,7 +57,6 @@
 //------------------------------------------------------------------------------
 
 #include <fapi.H>
-#include "p8_scom_addresses.H"
 
 
 //------------------------------------------------------------------------------
diff --git a/src/usr/hwpf/hwp/include/common_scom_addresses.H b/src/usr/hwpf/hwp/include/common_scom_addresses.H
index 7edeb8da2..e264dc53c 100755
--- a/src/usr/hwpf/hwp/include/common_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/common_scom_addresses.H
@@ -21,7 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
-// $Id: common_scom_addresses.H,v 1.18 2012/06/25 17:52:34 bcbrock Exp $
+// $Id: common_scom_addresses.H,v 1.22 2012/07/24 15:52:06 koenig Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/common_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -448,6 +448,10 @@ CONST_UINT64_T( WRITE_ALL_GP0_OR_0x6B000005           , ULL(0x6B000005) );
 CONST_UINT64_T( READ_ALL_GP1_AND_0x4B000001           , ULL(0x4B000001) );       // and all GP1 but not PRV
 
 CONST_UINT64_T( WRITE_EX_GP3_AND_0x690F0013           , ULL(0x690F0013) );       // and all EX GP3
+CONST_UINT64_T( WRITE_EX_GP3_OR_0x690F0014            , ULL(0x690F0014) );       // or all EX GP3
+
+
+CONST_UINT64_T( WRITE_EX_PMGP0_OR_0x690F0102          , ULL(0x690F0102) );       // or all EX PMGP0
 
 CONST_UINT64_T( WRITE_ALL_CLK_REGION_0x6B030006       , ULL(0x6B030006) );       // all GP3 but not PRV
 
@@ -523,6 +527,7 @@ CONST_UINT64_T( WRITE_ALL_PCB_SLAVE_ERRREG_0x6B0F001F    , ULL(0x6B0F001F) ); //
 CONST_UINT64_T( SCAN_ALLREGIONEXVITAL,              ULL(0x0FF00E0000000000) );
 CONST_UINT64_T( SCAN_CLK_ALL,                       ULL(0x0FF00E0000000000) );
 CONST_UINT64_T( SCAN_CLK_ALLEXDPLL,                 ULL(0x0FE00E0000000000) );
+CONST_UINT64_T( SCAN_CLK_ALL_BUT_PLL,               ULL(0x0FE00E0000000000) );
 CONST_UINT64_T( SCAN_CLK_CORE_ONLY,                 ULL(0x06000E0000000000) );
 
 
@@ -530,6 +535,7 @@ CONST_UINT64_T( SCAN_ALLSCANEXVITAL,                ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALLSCANEXPRV,                  ULL(0x0FF00DCE00000000) );  // Looking to be deprecated
 CONST_UINT64_T( SCAN_ALL_BUT_GPTRTIMEREP,           ULL(0x0FF00DCE00000000) );
 CONST_UINT64_T( SCAN_ALL_BUT_VITALDPLLGPTRTIME,     ULL(0x0FE00DCE00000000) );
+CONST_UINT64_T( SCAN_ALL_BUT_VITALPLLGPTRTIME,      ULL(0x0FE00DCE00000000) );
 CONST_UINT64_T( SCAN_GPTR_TIME_REP,                 ULL(0x0FF0023000000000) );
 CONST_UINT64_T( SCAN_TIME_REP,                      ULL(0x0CF0003000000000) );
 
@@ -538,9 +544,11 @@ CONST_UINT64_T( SCAN_CORE_ALL_BUT_GPTRTIMEREP,      ULL(0x06000DCE00000000) );
 CONST_UINT64_T( SCAN_CORE_GPTR_TIME_REP,            ULL(0x0600023000000000) );
 CONST_UINT64_T( SCAN_CORE_TIME_REP,                 ULL(0x0600003000000000) );
 
+CONST_UINT64_T( SCAN_TP_ARRAY_INIT_REGIONS,         ULL(0x09000e0000000000) );
+CONST_UINT64_T( SCAN_TP_REGIONS_EXCEPT_PIB_PCB,     ULL(0x09e00e0000000000) );
+CONST_UINT64_T( SCAN_TP_SCAN_SELECTS,               ULL(0x09e00dce00000000) );
 
-
-
+CONST_UINT8_T( SCAN_CHIPLET_STBY,                   ULL(0x00) );
 CONST_UINT8_T( SCAN_CHIPLET_TP,                     ULL(0x01) );
 CONST_UINT8_T( SCAN_CHIPLET_NEST,                   ULL(0x02) );
 CONST_UINT8_T( SCAN_CHIPLET_MEM,                    ULL(0x03) );
@@ -548,18 +556,6 @@ CONST_UINT8_T( SCAN_CHIPLET_ALL,                    ULL(0x68) );
 CONST_UINT8_T( SCAN_CHIPLET_GROUP1,                 ULL(0x69) );
 CONST_UINT8_T( SCAN_CHIPLET_GROUP3,                 ULL(0x6B) );
 
-/*  This content is old but will let R. Koester remove it formally
-CONST_UINT64_T( SCAN_ALLREGIONEXVITAL,            ULL(0x0FF00E0000000000) );
-// next line was wrong based on a documentation error, do we need this option at all?
-// use OPTION 3 instead rkoester 05/23/12
-// CONST_UINT64_T( SCAN_ALLSCANEXVITAL,              ULL(0x0FF00FFE00000000) );
-CONST_UINT64_T( SCAN_ALLSCANEXVITAL,              ULL(0x0FF00DCE00000000) );
-CONST_UINT64_T( SCAN_ALLSCANEXPRV,                ULL(0x0FF00DCE00000000) );
-// next line is a suggestion from Johannes, I need to discuss this with PRV design first:
-// this would exclude a scan region for PRV, which probably does not serve chiplet init correctly
-// rkoester 05/23/12
-// CONST_UINT64_T( SCAN_ALLSCANEXPRV,             ULL(0x07F00DCE00000000) );
-*/
 
 CONST_UINT8_T( READ_OR_ALL_CHIPLETS,                ULL(0x40) );   // group 0: all chiplets
 CONST_UINT8_T( READ_OR_ALL_FUNC_CHIPLETS,           ULL(0x43) );   // group 3: all functional chiplets
@@ -577,6 +573,18 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: common_scom_addresses.H,v $
+Revision 1.22  2012/07/24 15:52:06  koenig
+Added EX GP3 OR codepoint - AK
+
+Revision 1.21  2012/07/06 09:49:48  rkoester
+add clock region / scan region for tp_arrayinit, make this common
+
+Revision 1.20  2012/07/03 09:38:25  rkoester
+add address for Centaur Scan0
+
+Revision 1.19  2012/07/02 16:43:47  rkoester
+add vector for scan_no_pll
+
 Revision 1.18  2012/06/25 17:52:34  bcbrock
 Modified proc_sbe_decompress_scan.S: 1) Removed comments and code related to
 the "polling" protocol. 2) Added a final SCOM to always issue a "setpulse"
diff --git a/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.C b/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.C
index d652c9b52..63162d0d7 100644
--- a/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.C
+++ b/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_freq.C,v 1.17 2012/07/17 13:24:13 bellows Exp $
 /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */
 
 //------------------------------------------------------------------------------
@@ -56,6 +57,7 @@
 //  1.14   | jdsloat  | 05/10/12 | Fixed per Firmware Request, RC checks, 0 checks
 //  1.15   | jdsloat  | 06/04/12 | Added a Configuration check
 //  1.16   | jdsloat  | 06/08/12 | Updates per Firware request
+//  1.17   | bellows  | 07/16/12 | added in Id tag
 //
 // This procedure takes CENTAUR as argument.  for each DIMM (under each MBA)
 // DIMM SPD attributes are read to determine optimal DRAM frequency
diff --git a/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.H b/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.H
index bcd6ae2a0..74f8de4ab 100644
--- a/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.H
+++ b/src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.H
@@ -1,25 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/mc_init/mss_freq/mss_freq.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: mss_freq.H,v 1.5 2012/07/17 13:22:54 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -43,6 +45,7 @@
 //  1.0    | jsabrow  | 11/30/11 | initial drop
 //  1.2    | jsabrow  | 02/14/12 | Updates for initial code review
 //  1.3    | jdsloat  | 04/26/12 | Code review updates
+//  1.5    | bellows  | 07/16/12 | added in Id tag
 
 #ifndef MSS_FREQHWPB_H_
 #define MSS_FREQHWPB_H_
diff --git a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C
index ff09263c3..8aa152e37 100644
--- a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C
+++ b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.C
@@ -21,6 +21,7 @@
  *
  *  IBM_PROLOG_END_TAG
  */
+// $Id: mss_volt.C,v 1.11 2012/07/17 13:24:49 bellows Exp $
 /* File mss_volt.C created by JEFF SABROWSKI on Fri 21 Oct 2011. */
 
 //------------------------------------------------------------------------------
@@ -51,6 +52,7 @@
 //  1.8    | jdsloat  | 04/26/12 | fixed 1.5V issue
 //  1.9    | jdsloat  | 05/08/12 | Removed debug message
 //  1.10   | jdsloat  | 05/09/12 | Fixed typo
+//  1.11   | bellows  | 07/16/12 | added in Id tag
 
 // This procedure takes a vector of Centaurs behind a voltage domain,
 // reads in supported DIMM voltages from SPD and determines optimal
diff --git a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.H b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.H
index 11f220630..a37a3a225 100644
--- a/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.H
+++ b/src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.H
@@ -1,25 +1,27 @@
-//  IBM_PROLOG_BEGIN_TAG
-//  This is an automatically generated prolog.
-//
-//  $Source: src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.H $
-//
-//  IBM CONFIDENTIAL
-//
-//  COPYRIGHT International Business Machines Corp. 2012
-//
-//  p1
-//
-//  Object Code Only (OCO) source materials
-//  Licensed Internal Code Source Materials
-//  IBM HostBoot Licensed Internal Code
-//
-//  The source code for this program is not published or other-
-//  wise divested of its trade secrets, irrespective of what has
-//  been deposited with the U.S. Copyright Office.
-//
-//  Origin: 30
-//
-//  IBM_PROLOG_END
+/*  IBM_PROLOG_BEGIN_TAG
+ *  This is an automatically generated prolog.
+ *
+ *  $Source: src/usr/hwpf/hwp/mc_init/mss_volt/mss_volt.H $
+ *
+ *  IBM CONFIDENTIAL
+ *
+ *  COPYRIGHT International Business Machines Corp. 2012
+ *
+ *  p1
+ *
+ *  Object Code Only (OCO) source materials
+ *  Licensed Internal Code Source Materials
+ *  IBM HostBoot Licensed Internal Code
+ *
+ *  The source code for this program is not published or other-
+ *  wise divested of its trade secrets, irrespective of what has
+ *  been deposited with the U.S. Copyright Office.
+ *
+ *  Origin: 30
+ *
+ *  IBM_PROLOG_END_TAG
+ */
+// $Id: mss_volt.H,v 1.5 2012/07/17 13:23:39 bellows Exp $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
 // *! All Rights Reserved -- Property of IBM
@@ -43,7 +45,7 @@
 //  1.0    | jsabrow  | 11/30/11 | initial drop
 //  1.2    | bellows  | 12/21/11 | fixed missing ;
 //  1.4    | jsabrow  | 02/14/12 | Updates for code review
-
+//  1.5    | bellows  | 07/16/12 | added $Id tag
 #ifndef MSS_VOLTHWPB_H_
 #define MSS_VOLTHWPB_H_
 
diff --git a/src/usr/hwpf/makefile b/src/usr/hwpf/makefile
index 99b51dd3f..6cb4ed8c8 100644
--- a/src/usr/hwpf/makefile
+++ b/src/usr/hwpf/makefile
@@ -32,7 +32,7 @@ SUBDIRS = fapi.d hwp.d plat.d test.d
 #------------------------------------------------------------------------------
 HWP_ERROR_XML_FILES = hwp/fapiHwpErrorInfo.xml   \
     hwp/dmi_training/proc_cen_framelock/proc_cen_framelock_errors.xml \
-    hwp/bus_training/io_run_training_errors.xml \
+    hwp/bus_training/io_errors.xml \
     hwp/dimm_errors.xml	\
     hwp/dram_training/memory_errors.xml \
     hwp/nest_chiplets/proc_start_clocks_chiplets/proc_start_clocks_chiplets_errors.xml \