HWP hacks for unused variables.

Change-Id: Iaa5d80be87e3f5753750325479ecbf3c946f719a
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4041
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 43 insertions, 43 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
index a34f347bc..ede8687c2 100644
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
+++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C
@@ -27,9 +27,9 @@
 // *!                   *** IBM Confidential ***
 // *!***************************************************************************
 // *! FILENAME             : io_clear_firs.C
-// *! TITLE                : 
+// *! TITLE                :
 // *! DESCRIPTION          : To clear summary fir registers
-// *! CONTEXT              : 
+// *! CONTEXT              :
 // *!
 // *! OWNER  NAME          : Swaminathan, Janani         Email: jaswamin@in.ibm.com
 // *! BACKUP NAME          : Varghese, Varkey            Email: varkey.kv@in.ibm.com
@@ -63,15 +63,15 @@ using namespace fapi;
 
 // for toggling the rx and tx fir reset.
 ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_interface,uint32_t i_group){
-    
+
     ReturnCode rc;
     uint32_t rc_ecmd=0;
     uint16_t bits = 0;
     ecmdDataBufferBase data_buffer;
- 
+
     ecmdDataBufferBase set_bits(16);
     ecmdDataBufferBase clear_bits(16);
-    
+
     //set the rx_fir_reset bit
     bits=rx_fir_reset;
     rc_ecmd|=set_bits.insert(bits,0,16);
@@ -83,7 +83,7 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter
         return(rc);
     }
     rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
+
     //clear the rx_fir_reset bit
     bits=0x0000;
     rc_ecmd|=set_bits.insert(bits,0,16);
@@ -95,7 +95,7 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter
         return(rc);
     }
     rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
+
     //set the tx_fir_reset bit
     bits=tx_fir_reset;
     rc_ecmd|=set_bits.insert(bits,0,16);
@@ -107,7 +107,7 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter
         return(rc);
     }
     rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
+
     //clear the tx_fir_reset
     bits=0x0000;
     rc_ecmd|=set_bits.insert(bits,0,16);
@@ -119,76 +119,76 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter
         return(rc);
     }
     rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);}
-    
+
     return(rc);
 
-    
+
 }
 
 
 ReturnCode read_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface,ecmdDataBufferBase &o_databuf_64bit){
-    
+
     ReturnCode rc;
     uint32_t rc_ecmd=0;
     uint64_t scom_address64=0;
     ecmdDataBufferBase temp(64);
     rc_ecmd |=o_databuf_64bit.flushTo0();
-    
+
     //get the 64 bit scom address.
     temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]);
     scom_address64=temp.getDoubleWord(0);
-    
+
     //read the 64 bit fir register
     rc=fapiGetScom(i_target,scom_address64,o_databuf_64bit);
-    
+
     return(rc);
 }
 
 ReturnCode io_clear_firs(const fapi::Target &i_target){
-    
+
     ReturnCode rc;
-    fir_io_interface_t interface;
+    fir_io_interface_t __attribute__((unused)) interface; // HACK
     io_interface_t gcr_interface; // requires different base address for gcr scoms
     uint32_t group;
-    
+
     //on dmi
     if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){
           FAPI_DBG("This is a Processor DMI bus using base DMI scom address");
           interface=FIR_CP_IOMC0_P0; // base scom for MC bus
           gcr_interface=CP_IOMC0_P0;
           group=3; // design requires us to swap
-          
+
      }
      else if((i_target.getType() ==  fapi::TARGET_TYPE_MEMBUF_CHIP)){
             FAPI_DBG("This is a Centaur DMI bus using base DMI scom address");
             interface=FIR_CEN_DMI;
             gcr_interface=CEN_DMI;
             group=0;
-           
+
      }
      else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){
             FAPI_DBG("This is a X Bus invocation");
             interface=FIR_CP_FABRIC_X0;
             gcr_interface=CP_FABRIC_X0;
             group=0;
-            
+
      }
-     
+
      else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){
             FAPI_DBG("This is an A Bus invocation");
             interface=FIR_CP_FABRIC_A0;
             gcr_interface=CP_FABRIC_A0;
             group=0;
-            
+
      }
      else{
         FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances");
         FAPI_SET_HWP_ERROR(rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC);
         return(rc);
      }
-     
+
     rc=clear_fir_err_regs(i_target,gcr_interface,group);
-    
+
     return(rc);
 }
 
diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
index 8b012fda9..993daf49a 100644
--- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
+++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C
@@ -27,19 +27,19 @@
 // *!                   *** IBM Confidential ***
 // *!***************************************************************************
 // *! FILENAME             : io_read_erepair.C
-// *! TITLE                : 
+// *! TITLE                :
 // *! DESCRIPTION          : Power down bad lanes
-// *! CONTEXT              : 
+// *! CONTEXT              :
 // *!
 // *! OWNER  NAME          : Varghese, Varkey         Email: varkey.kv@in.ibm.com
-// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com      
+// *! BACKUP NAME          : Swaminathan, Janani      Email: jaswamin@in.ibm.com
 // *!
 // *!***************************************************************************
 // CHANGE HISTORY:
 //------------------------------------------------------------------------------
 // Version:|Author: | Date:  | Comment:
 // --------|--------|--------|--------------------------------------------------
-//   1.0   |varkeykv||Initial check in 
+//   1.0   |varkeykv||Initial check in
 //------------------------------------------------------------------------------
 
 #include <fapi.H>
@@ -55,7 +55,7 @@ using namespace fapi;
 /*
  This function will perform power down of lanes on any IO target MEMBUF,MCS , XBUS or ABUS
  * Bad lanes are powered down , but caller is expected to logically disable lanes by calling restore_repair prior
- * to calling this HWP 
+ * to calling this HWP
 */
 
 ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &tx_lanes,const std::vector<uint8_t> &rx_lanes)
@@ -69,28 +69,28 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &
   io_interface_t interface=CP_IOMC0_P0; // Since G
   uint32_t rc_ecmd=0;
   uint8_t clock_group=0;
-  uint8_t start_group=0;
-  uint8_t end_group=0;
-  
+  uint8_t __attribute__((unused)) start_group=0; // HACK
+  uint8_t __attribute__((unused)) end_group=0; // HACK
+
     rc_ecmd=mask.flushTo1();
     if(rc_ecmd)
     {
         rc.setEcmdError(rc_ecmd);
         return(rc);
     }
-    // Both TX and RX power down bits are on bit 0 
+    // Both TX and RX power down bits are on bit 0
     rc_ecmd=mask.clearBit(0);
     if(rc_ecmd)
     {
         rc.setEcmdError(rc_ecmd);
         return(rc);
     }
-  
-  // Check which type of bus this is and do setup needed 
+
+  // Check which type of bus this is and do setup needed
   if(target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) {
     start_group=0;
     end_group=0;
-    interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT 
+    interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT
   }
   else if(target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT ) {
     start_group=0;
@@ -112,7 +112,7 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &
       FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC);
       return(rc);
   }
-  
+
    FAPI_INF("Power down IO lanes\n");
 
       rc_ecmd|=data.flushTo0();
@@ -123,26 +123,26 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &
           rc.setEcmdError(rc_ecmd);
           return(rc);
       }
-      
-    //TX Lanes power down 
+
+    //TX Lanes power down
       for(uint8_t i=0;i<tx_lanes.size();++i){
         clock_group=0;
         lane=tx_lanes[i];
-        //For Xbus figure out the clock group number 
+        //For Xbus figure out the clock group number
         if(interface==CP_FABRIC_X0){
           while(lane>(xbus_lanes_per_group-1)){
             lane=lane-xbus_lanes_per_group;
             clock_group++;
           }
         }
-        //Power down this lane 
+        //Power down this lane
         rc = GCR_write( target, interface, tx_mode_pl, clock_group,  lane,  data,mask );
         if(rc){return rc;}
 
       }
 
 
-      // Process RX lane powerdown 
+      // Process RX lane powerdown
       for(uint8_t i=0;i<rx_lanes.size();++i){
         clock_group=0;
         lane=rx_lanes[i];
@@ -153,7 +153,7 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &
             clock_group++;
           }
         }
-        //Power down this lane 
+        //Power down this lane
         rc = GCR_write( target, interface, rx_mode_pl, clock_group,  lane,  data,mask );
         if(rc){return rc;}
       }