diff options
| author | Patrick Williams <iawillia@us.ibm.com> | 2013-04-10 22:46:44 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2013-04-17 15:38:07 -0500 |
| commit | 24677286a33ea478fd5c2db959e894dd3a5f0e85 (patch) | |
| tree | 385b8732e6bdde1874c0889ff284e935a95232f2 | |
| parent | 9bc120bbd4bdd9aecf2ef2f3f491654dc1ba5ea3 (diff) | |
| download | talos-hostboot-24677286a33ea478fd5c2db959e894dd3a5f0e85.tar.gz talos-hostboot-24677286a33ea478fd5c2db959e894dd3a5f0e85.zip | |
HWP hacks for unused variables.
Change-Id: Iaa5d80be87e3f5753750325479ecbf3c946f719a
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/4041
Reviewed-by: MIKE J. JONES <mjjones@us.ibm.com>
Tested-by: Jenkins Server
Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
Reviewed-by: Zane Shelley <zshelle@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
11 files changed, 1341 insertions, 1341 deletions
diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C index a3eeb412d..20ef82d5b 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_pfet_init.C @@ -30,7 +30,7 @@ // *! OWNER NAME: Greg Still Email: stillgs@us.ibm.com // *! /// \file p8_pfet_init.C -/// \brief Configure and initialize the EX PFET controllers based on +/// \brief Configure and initialize the EX PFET controllers based on /// attribute information and removes the override function. /// /// High-level procedure flow: @@ -39,9 +39,9 @@ /// Check for valid parameters /// if PM_CONFIG { /// Nop (all the work is done in PM_INIT as this procedure is not run -/// for the PM Reset path (eg, only done at IPL) +/// for the PM Reset path (eg, only done at IPL) /// else if PM_INIT { -/// Get the delay setting held in platform attributes +/// Get the delay setting held in platform attributes /// Convert these to hardware values /// for each EX chiplet { /// Store the Core VDD delay and VRET/VOFF values @@ -149,7 +149,7 @@ p8_pfet_init(const Target& i_target, uint32_t mode) /// ------------------------------- /// Unsupported Mode - else + else { FAPI_ERR("Unknown mode passed to p8_pfet_init. Mode %x ....", mode); @@ -173,10 +173,10 @@ pfet_init(const Target& i_target) std::vector<fapi::Target> l_exChiplets; uint8_t l_functional = 0; uint8_t l_ex_number = 0; - bool error_flag = false; - + bool __attribute__((unused)) error_flag = false; // HACK + uint64_t address; - + uint8_t core_vret_voff_value; uint8_t eco_vret_voff_value; @@ -214,7 +214,7 @@ pfet_init(const Target& i_target) /// ATTR_PM_PFET_POWERUP_ECO_DELAY0 /// ATTR_PM_PFET_POWERUP_ECO_DELAY1 /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY0 - /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 + /// ATTR_PM_PFET_POWERDOWN_CORE_DELAY1 /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY0 /// ATTR_PM_PFET_POWERDOWN_ECO_DELAY1 /// Output feature attributes @@ -235,11 +235,11 @@ pfet_init(const Target& i_target) { FAPI_INF("Executing pfet_config..."); - + // Harcoded defaults that don't come via attribute // Vret (not supported) = "off" (stage 0 = 0xB) for bits 0:3 // Voff = "off" (stage 01 = 0xB) for bits 4:7 - // \todo The scan0 values are zeros which indicate that the + // \todo The scan0 values are zeros which indicate that the // power won't go off. Double check the setting below!!! core_vret_voff_value = 0xBB; eco_vret_voff_value = 0xBB; @@ -269,7 +269,7 @@ pfet_init(const Target& i_target) // FAPI_SET_HWP_ERROR(l_rc, RC_PROCPM_PFET_GET_ATTR); break; } - + /// ---------------------------------------------------------- l_rc = FAPI_ATTR_GET( ATTR_PM_PFET_POWERUP_CORE_DELAY0, &i_target, @@ -422,9 +422,9 @@ pfet_init(const Target& i_target) attr_pm_pfet_powerdown_eco_delay1_value = convert_delay_to_value( attr_pm_pfet_powerdown_eco_delay1 , attr_proc_refclk_frequency); - + // Choosing always delay0 - attr_pm_pfet_powerup_core_sequence_delay_select = 0; + attr_pm_pfet_powerup_core_sequence_delay_select = 0; attr_pm_pfet_powerdown_core_sequence_delay_select = 0; attr_pm_pfet_powerup_eco_sequence_delay_select = 0; attr_pm_pfet_powerdown_eco_sequence_delay_select = 0; @@ -449,8 +449,8 @@ pfet_init(const Target& i_target) // Loop through all the functional chiplets // ****************************************************************** - l_rc = fapiGetChildChiplets(i_target, - TARGET_TYPE_EX_CHIPLET, + l_rc = fapiGetChildChiplets(i_target, + TARGET_TYPE_EX_CHIPLET, l_exChiplets, TARGET_STATE_PRESENT); if (l_rc) @@ -575,7 +575,7 @@ pfet_init(const Target& i_target) // ------------------------------------------------------------- FAPI_DBG("\tSetting ECO Voff Settings"); e_rc |= data.setBitLength(64); - e_rc |= data.insertFromRight(eco_vret_voff_value, 0, 8); + e_rc |= data.insertFromRight(eco_vret_voff_value, 0, 8); if (e_rc) { FAPI_ERR("Error (0x%x) setting up ecmdDataBufferBase", e_rc); @@ -650,12 +650,12 @@ pfet_set_delay( const fapi::Target& i_target, // convert_delay_to_value // Helper function to convert time values (binary in ns)to hardware delays //------------------------------------------------------------------------------ -uint8_t -convert_delay_to_value (uint32_t i_delay, +uint8_t +convert_delay_to_value (uint32_t i_delay, uint32_t i_attr_proc_nest_frequency) { uint8_t pfet_delay_value; - float dly; + float dly; // attr_proc_nest_frequency [MHz] // delay [ns] // pfet_delay_value = 15 - log2( i_delay * i_attr_proc_nest_frequency/1000); diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C index 806c7d475..7f0cb94e6 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_set_pore_bar/p8_poreslw_init.C @@ -190,7 +190,7 @@ poreslw_init(const Target& i_target) FAPI_ERR("Scom error writing PMC_MODE"); break; } - + FAPI_DBG("Activate the PMC Idle seequencer by making sure the Halt bit is clear"); // Setup up each of the EX chiplets @@ -330,8 +330,8 @@ poreslw_ex_setup(const Target& i_target) uint8_t l_functional = 0; uint8_t l_ex_number = 0; uint64_t address; - bool core_flag = false; - bool error_flag = false; + bool __attribute__((unused)) core_flag = false; // HACK + bool __attribute__((unused)) error_flag = false; // HACK //@thi - fixed compiler error - Greg will fix this in next version //uint32_t fsierror = 0; @@ -349,7 +349,7 @@ poreslw_ex_setup(const Target& i_target) const uint32_t PM_SLEEP_POWER_OFF_SEL_BIT = 2; const uint32_t PM_WINKLE_POWER_DOWN_EN_BIT = 3; const uint32_t PM_WINKLE_POWER_UP_EN_BIT = 4; - const uint32_t PM_WINKLE_POWER_OFF_SEL_BIT = 5; + const uint32_t PM_WINKLE_POWER_OFF_SEL_BIT = 5; //@thi - fixed compiler error - Greg will fix this in next version //const uint32_t IDLE_STATE_OVERRIDE_EN = 6; @@ -517,7 +517,7 @@ poreslw_ex_setup(const Target& i_target) // If sleep entry = 1 (hardware), sleep power down enable = 1 // else sleep entry = 0 (assisted), sleep power down enable = 0 if (pm_sleep_entry) - { + { e_rc |= set_data.setBit(PM_SLEEP_POWER_DOWN_EN_BIT); } else @@ -552,7 +552,7 @@ poreslw_ex_setup(const Target& i_target) // else winkle entry = 0 (assisted), winkle power down enable = 0 if (pm_winkle_entry) { - e_rc |= set_data.setBit(PM_WINKLE_POWER_DOWN_EN_BIT); + e_rc |= set_data.setBit(PM_WINKLE_POWER_DOWN_EN_BIT); } else { @@ -563,7 +563,7 @@ poreslw_ex_setup(const Target& i_target) // else winkle exit = 0 (assisted), winkle power up enable = 0 if (pm_winkle_exit) { - e_rc |= set_data.setBit(PM_WINKLE_POWER_UP_EN_BIT); + e_rc |= set_data.setBit(PM_WINKLE_POWER_UP_EN_BIT); } else { @@ -637,16 +637,16 @@ poreslw_ex_setup(const Target& i_target) // -------------------------------------- // Check if SBE code has already cleared the OHA override. // As chiplets may be enabled but offline (eg in Winkle) - // treat SCOM errors as off-line (eg skip it). If online - // and set, clear the override. - + // treat SCOM errors as off-line (eg skip it). If online + // and set, clear the override. + /* GSS: removed as Cronus always puts a message out of (PCB_OFFLINE) even though this code is meant to handle it. As this messge can cause confusion in the lab, the check is being removed. - bool oha_accessible = true; + bool oha_accessible = true; l_rc = fapiGetScom(l_exChiplets[j], EX_OHA_MODE_REG_RWx1002000D, data); if(!l_rc.ok()) - { + { l_rc = fapiGetCfamRegister( i_target, CFAM_FSI_STATUS_0x00001007, data ); if(!l_rc.ok()) { @@ -655,14 +655,14 @@ poreslw_ex_setup(const Target& i_target) } FAPI_INF( "CFAM_FSI_STATUS_0x00001007: 0x%X", data.getWord(0)); e_rc |= data.extractToRight( &fsierror, 17, 3 ); - if ( e_rc ) - { - l_rc.setEcmdError(e_rc); + if ( e_rc ) + { + l_rc.setEcmdError(e_rc); break; } - if (fsierror == PIB_OFFLINE_ERROR) + if (fsierror == PIB_OFFLINE_ERROR) { - FAPI_INF( "Chiplet offline error detected. Skipping OHA Override clearing"); + FAPI_INF( "Chiplet offline error detected. Skipping OHA Override clearing"); oha_accessible = false; } else @@ -695,8 +695,8 @@ poreslw_ex_setup(const Target& i_target) } } End of check removal - */ - + */ + // -------------------------------------- // Check that PM function is enabled (eg not disabled). // If not, remove the disable @@ -708,10 +708,10 @@ poreslw_ex_setup(const Target& i_target) FAPI_ERR("Scom error reading PMGP0"); break; } - + if (data.isBitSet(PM_DISABLE)) { - + // Activate the PCBS-PM macro by clearing the PM_DISABLE bit FAPI_INF("\tActivate the PCBS-PM for EX %x", l_ex_number); @@ -742,7 +742,7 @@ poreslw_ex_setup(const Target& i_target) FAPI_ERR("Scom error clearing EX_OCC_SPWKUP"); break; } - + if (data.isBitSet(0)) { FAPI_INF("\tClear OCC Special Wake-up for EX %x", l_ex_number); diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C index e24b52f1d..8ad158544 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_image_help.C @@ -54,8 +54,8 @@ extern "C" { // i_alter - altered (desired) ring state // o_delta - ring delta state, caller allocates buffer // i_ringLen - length of ring in bits -int calc_ring_delta_state( const uint32_t *i_init, - const uint32_t *i_alter, +int calc_ring_delta_state( const uint32_t *i_init, + const uint32_t *i_alter, uint32_t *o_delta, const uint32_t i_ringLen ) { @@ -102,7 +102,7 @@ int calc_ring_delta_state( const uint32_t *i_init, alter = alter & mask; remainingBits = 0; } - + // Do the XORing. o_delta[i] = init ^ alter; } @@ -130,7 +130,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s uint32_t rc=0; uint32_t i=0; uint32_t scanSelectAddr=0; - uint32_t scanRing_baseAddr=0, scanRing_baseAddr_long=0; + uint32_t scanRing_baseAddr=0, __attribute__((unused)) scanRing_baseAddr_long=0; // HACK uint32_t scanRing_poreAddr=0; uint32_t scanRingCheckWord=0; uint32_t bitShift=0; @@ -143,28 +143,28 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s PoreInlineContext ctx; maxWfInlineLenInWords = *o_wfInlineLenInWords; - + pore_inline_context_create(&ctx, *o_wfInline, maxWfInlineLenInWords * 4, 0, 0); - + // // Set Default scanselq addr and scanring addr vars // // 0x00030007: port 3 - clock cotrol endpt, x07- scanselq (regin & types) - scanSelectAddr = P8_PORE_CLOCK_CONTROLLER_REG; - + scanSelectAddr = P8_PORE_CLOCK_CONTROLLER_REG; + // Addr of clock control SCOM register(s) for short and long rotates. // // Short: 0x00038000: port 3, addr bit 16 must be set to 1 and bit 19 to 0. - scanRing_baseAddr = P8_PORE_SHIFT_REG; + scanRing_baseAddr = P8_PORE_SHIFT_REG; scanRing_poreAddr = scanRing_baseAddr; // Long (poll): 0x00039000: port 3, addr bit 16 must be set to 1 and bit 19 to 1. scanRing_baseAddr_long = P8_PORE_SHIFT_REG | 0x00001000; - + // Header check word for checking ring write was successful scanRingCheckWord = P8_SCAN_CHECK_WORD; - - // This fix is a direct copy of the setp1_mcreadand macro in ./ipl/sbe/p8_slw.H + + // This fix is a direct copy of the setp1_mcreadand macro in ./ipl/sbe/p8_slw.H uint64_t CLEAR_MC_TYPE_MASK=0x47; PoreInlineLocation src1=0, src2=0, tgt1=0, tgt2=0; pore_MR( &ctx, D1, P0); @@ -194,7 +194,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s MY_ERR("***inline_branch_fixup error (2) rc = %d", ctx.error); return ctx.error; } - + // We can assume that atomic lock is already in effect prior to WF calls. // It can probably also be assumed that functional clocks are stopped, but // let's do it and check for it anyway. @@ -237,7 +237,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s MY_ERR("***STI(1) rc = %d", ctx.error); return ctx.error; } - + // Check how many 32-bit shift ops are needed and if we need final shift of remaining bit. count = i_ringBitLen/32; remainder = i_ringBitLen%32; @@ -250,13 +250,13 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s // CMO: I changed the following to not skip the first 32-bit. //remainingBits = i_ringBitLen-32; //Yong impl. remainingBits = i_ringBitLen; //Mike impl. - + MY_DBG("count=%i rem=%i remBits=%i",count,remainder,remainingBits); - // Read and compare init and flush values 32 bits at a time. Store delta in + // Read and compare init and flush values 32 bits at a time. Store delta in // o_delta buffer. for (i=0; i<count; i++) { - + if (i==(count-1)) { // Cleanup any leftover bits in dirty buffer. (Only applies to last word.) MY_DBG("Clearing any dirty bits in last WF word:\n"); @@ -270,7 +270,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s //==================================================================================== // If flush & init values are identical, increase the read count, no code needed. - // When the discrepancy is found, read (rotate the ring) up to current address + // When the discrepancy is found, read (rotate the ring) up to current address // then scan/write in the last 32 bits //==================================================================================== if (i_deltaRing[i] > 0) { @@ -280,12 +280,12 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s #ifdef IMGBUILD_PPD_WF_POLLING_PROT uint32_t nwait1=0; PoreInlineLocation srcp1=0,tgtp1=0; - + pore_imm64b = uint64_t(rotateLen)<<32; // pore_LI(&ctx, D0, pore_imm64b); // pore_STD(&ctx, D0, scanRing_baseAddr_long, P0); pore_STI(&ctx, scanRing_baseAddr_long, P0, pore_imm64b); - + nwait1 = rotateLen / 20 + 1; // 20x over sampling. PORE_LOCATION(&ctx, tgtp1); pore_WAITS(&ctx, nwait1); @@ -305,7 +305,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s if (ctx.error > 0) { MY_ERR("***LD D0 rc = %d", ctx.error); return ctx.error; - } + } #endif } // End of if (rotateLen>0) @@ -336,7 +336,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s pore_LI(&ctx, D0, pore_imm64b ); // Cleanup shift register snapshot and put in D1. pore_AND(&ctx, D1, D0, D1); - // Put ring data in D0. + // Put ring data in D0. // Note, any dirty content was removed earlier. pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; pore_LI(&ctx, D0, pore_imm64b ); @@ -346,7 +346,7 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s } else { pore_LD(&ctx, D1, scanRing_baseAddr, P1); - // Bring ring data in as an immediate. + // Bring ring data in as an immediate. // Note, any dirty content was removed earlier. pore_imm64b = ((uint64_t)myRev32(i_deltaRing[i])) << 32; pore_XORI(&ctx, D0, D1, pore_imm64b); @@ -387,12 +387,12 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s rotateLen = rotateLen + 32; else rotateLen = rotateLen + remainingBits; - + #ifdef IMGBUILD_PPD_WF_POLLING_PROT uint32_t nwait2=0; PoreInlineLocation srcp2=0,tgtp2=0; - - // Max rotate length is 2^20-1, i.e., data BITS(12-31)=>0x000FFFFF + + // Max rotate length is 2^20-1, i.e., data BITS(12-31)=>0x000FFFFF if (rotateLen>=SCAN_MAX_ROTATE_LONG) { MY_INF("Scanning should never be here since max possible ring length is\n"); MY_INF("480,000 bits but MAX_LONG_ROTATE=0x%0x and rotateLen=0x%0x\n", @@ -438,19 +438,19 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s remainingBits = 0; } // End of for loop - + // If the scan ring has not been rotated to the original position // shift the ring by remaining shift bit length. if (rotateLen>0) { #ifdef IMGBUILD_PPD_WF_POLLING_PROT uint32_t nwait3=0; PoreInlineLocation srcp3=0,tgtp3=0; - + pore_imm64b = uint64_t(rotateLen)<<32; // pore_LI(&ctx, D0, pore_imm64b); // pore_STD(&ctx, D0, scanRing_baseAddr_long, P0); pore_STI(&ctx, scanRing_baseAddr_long, P0, pore_imm64b); - + nwait3 = rotateLen / 20 + 1; // 20x over sampling. PORE_LOCATION(&ctx, tgtp3); pore_WAITS(&ctx, nwait3); @@ -494,8 +494,8 @@ int create_wiggle_flip_prg( uint32_t *i_deltaRing, // scan ring delta s pore_MR( &ctx, D1, P0); pore_ANDI( &ctx, D1, D1, CLEAR_MC_TYPE_MASK); pore_ORI( &ctx, D1, D1, BIT(60)); - pore_MR( &ctx, P1, D1); - if (ctx.error > 0) { + pore_MR( &ctx, P1, D1); + if (ctx.error > 0) { MY_ERR("***setp1_mcreadand rc = %d", ctx.error); return ctx.error; } @@ -596,7 +596,7 @@ int get_ring_layout_from_image( const void *i_imageIn, uint32_t sizeInitf; SbeXipSection hostSection; void *initfHostAddress0; - + SBE_XIP_ERROR_STRINGS(errorStrings); // Always first get the .initf stats from the TOC: @@ -614,7 +614,7 @@ int get_ring_layout_from_image( const void *i_imageIn, MY_INF("INFO : No ring data exists for the section ID = SBE_XIP_SECTION_RINGS (ID=%i).",SBE_XIP_SECTION_RINGS); return DSLWB_RING_SEARCH_NO_MATCH; // Implies exhaust search as well. } - initfHostAddress0 = (void*)((uintptr_t)i_imageIn + hostSection.iv_offset); + initfHostAddress0 = (void*)((uintptr_t)i_imageIn + hostSection.iv_offset); sizeInitf = hostSection.iv_size; // On first call, get the base offset to the .initf section. @@ -625,16 +625,16 @@ int get_ring_layout_from_image( const void *i_imageIn, else nextRingLayout = (DeltaRingLayout*)*nextRing; - MY_DBG("initfHostAddress0 = 0x%016llx",(uint64_t)initfHostAddress0); + MY_DBG("initfHostAddress0 = 0x%016llx",(uint64_t)initfHostAddress0); MY_DBG("sizeInitf = %i", sizeInitf); MY_DBG("nextRingLayout = 0x%016llx",(uint64_t)nextRingLayout); - + // Populate the output RS4 ring BE layout structure as well as local structure in host LE format where needed. // Note! Entire memory content is in BE format. So we do LE conversions where needed. // bRingFound = 0; bRingEOS = 0; - + // SEARCH loop: Parse ring blocks successively until we find a ring that matches: // ddLevel == i_ddLevel // sysPhase == i_sysPhase @@ -647,7 +647,7 @@ int get_ring_layout_from_image( const void *i_imageIn, MY_DBG("Next override = %i",thisRingLayout->override); MY_DBG("Next reserved1 = %i",thisRingLayout->reserved1); MY_DBG("Next reserved2 = %i",thisRingLayout->reserved2); - + if (myRev32(thisRingLayout->ddLevel)==i_ddLevel) { // Is there a non-specific DD level, like for sys phase? if ((thisRingLayout->sysPhase==0 && i_sysPhase==0) || (thisRingLayout->sysPhase==1 && i_sysPhase==1) || @@ -663,7 +663,7 @@ int get_ring_layout_from_image( const void *i_imageIn, *nextRing = NULL; MY_DBG("\tRing search exhausted!"); } - + } // End of SEARCH. if (bRingFound) { @@ -671,7 +671,7 @@ int get_ring_layout_from_image( const void *i_imageIn, rcLoc = DSLWB_RING_SEARCH_EXHAUST_MATCH; else rcLoc = DSLWB_RING_SEARCH_MATCH; - } + } else { *nextRing = NULL; if (bRingEOS) @@ -691,29 +691,29 @@ int get_ring_layout_from_image( const void *i_imageIn, o_rs4RingLayout->override = thisRingLayout->override; o_rs4RingLayout->reserved1 = thisRingLayout->reserved1; o_rs4RingLayout->reserved2 = thisRingLayout->reserved2; - o_rs4RingLayout->metaData = (char*)(&thisRingLayout->reserved2 + + o_rs4RingLayout->metaData = (char*)(&thisRingLayout->reserved2 + sizeof(thisRingLayout->reserved2)); - o_rs4RingLayout->rs4Launch = (uint32_t*)((uintptr_t)thisRingLayout + + o_rs4RingLayout->rs4Launch = (uint32_t*)((uintptr_t)thisRingLayout + myRev64(thisRingLayout->entryOffset)); // entryOffset, rs4Launch and ASM_RS4_LAUNCH_BUF_SIZE should already be 8-byte aligned. - o_rs4RingLayout->rs4Delta = (uint32_t*)( (uintptr_t)thisRingLayout + + o_rs4RingLayout->rs4Delta = (uint32_t*)( (uintptr_t)thisRingLayout + myRev64(thisRingLayout->entryOffset) + ASM_RS4_LAUNCH_BUF_SIZE ); - // Check that the ring layout structure in the memory is 8-byte aligned. This must + // Check that the ring layout structure in the memory is 8-byte aligned. This must // be so because: - // - The entryOffset address must be on an 8-byte boundary because the start of the - // .rings section must be 8-byte aligned AND because the rs4Delta member is the + // - The entryOffset address must be on an 8-byte boundary because the start of the + // .rings section must be 8-byte aligned AND because the rs4Delta member is the // last member and which must itself be 8-byte aligned. - // - These two things together means that both the beginning and end of the delta - // ring layout must be 8-byte aligned, and thus the whole block, i.e. sizeOfThis, + // - These two things together means that both the beginning and end of the delta + // ring layout must be 8-byte aligned, and thus the whole block, i.e. sizeOfThis, // must therefore automatically be 8-byte aligned. // Also check that the RS4 delta ring is 8-byte aligned. // Also check that the RS4 launcher is 8-byte aligned. // - if (((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)%8 || - myRev32(o_rs4RingLayout->sizeOfThis)%8 || - myRev64(o_rs4RingLayout->entryOffset)%8 || + if (((uintptr_t)thisRingLayout-(uintptr_t)i_imageIn)%8 || + myRev32(o_rs4RingLayout->sizeOfThis)%8 || + myRev64(o_rs4RingLayout->entryOffset)%8 || ASM_RS4_LAUNCH_BUF_SIZE%8) { MY_ERR("Ring block or layout structure is not 8-byte aligned:"); MY_ERR(" thisRingLayout-imageIn = %i",(uintptr_t)thisRingLayout-(uintptr_t)i_imageIn); @@ -749,37 +749,37 @@ int write_wiggle_flip_to_image( void *io_imageOut, void *ringsBuffer=NULL; uint32_t ringRingsOffset=0; uint64_t ringPoreAddress=0,backPtr=0,fwdPtr=0,fwdPtrCheck; - + SBE_XIP_ERROR_STRINGS(errorStrings); - MY_DBG("wfInlineLenInWords=%i", i_wfInlineLenInWords); - + MY_DBG("wfInlineLenInWords=%i", i_wfInlineLenInWords); + // Modify the input ring layout content - // - Remove the qualifier section: ddLevel, sysPhase, override and reserved1+2. + // - Remove the qualifier section: ddLevel, sysPhase, override and reserved1+2. // This means reducing the entryOffset by the size of these qualifiers. - // - The new WF ring block and start of WF code must both be 8-byte aligned. + // - The new WF ring block and start of WF code must both be 8-byte aligned. // - RS4 entryOffset is already 8-byte aligned. // - The WF code section, i.e. wfInlineLenInWords, is already 8-byte aligned. // - i_ringLayout->entryOffset = + i_ringLayout->entryOffset = myRev64( myByteAlign(8, myRev64(i_ringLayout->entryOffset) - sizeof(i_ringLayout->ddLevel) - sizeof(i_ringLayout->sysPhase) - sizeof(i_ringLayout->override) - sizeof(i_ringLayout->reserved1) - sizeof(i_ringLayout->reserved2) ) ); - i_ringLayout->sizeOfThis = + i_ringLayout->sizeOfThis = myRev32( myRev64(i_ringLayout->entryOffset) + i_wfInlineLenInWords*4 ); - + // Not really any need for this. Just being consistent. Once we have transitioned completely to new - // headers, then ditch i_wfInline from parm list and assign wfInline to layout in main program. + // headers, then ditch i_wfInline from parm list and assign wfInline to layout in main program. i_ringLayout->wfInline = i_wfInline; - + if (myRev64(i_ringLayout->entryOffset)%8 || myRev32(i_ringLayout->sizeOfThis)%8) { MY_ERR("Ring block or WF code origin not 8-byte aligned."); return IMGBUILD_ERR_MISALIGNED_RING_LAYOUT; } - + // Calc the size of the data section we're adding and the resulting output image. // rc = sbe_xip_image_size( io_imageOut, &sizeImageIn); @@ -789,7 +789,7 @@ int write_wiggle_flip_to_image( void *io_imageOut, } sizeNewDataBlock = myRev32(i_ringLayout->sizeOfThis); // ...estimate max size of new image - sizeImageOutThisEst = sizeImageIn + sizeNewDataBlock + SBE_XIP_MAX_SECTION_ALIGNMENT; // + sizeImageOutThisEst = sizeImageIn + sizeNewDataBlock + SBE_XIP_MAX_SECTION_ALIGNMENT; // if (sizeImageOutThisEst>*i_sizeImageMaxNew) { MY_ERR("Estimated new image size (=%i) would exceed max allowed size (=%i).", @@ -797,7 +797,7 @@ int write_wiggle_flip_to_image( void *io_imageOut, *i_sizeImageMaxNew = sizeImageOutThisEst; return IMGBUILD_ERR_IMAGE_TOO_LARGE; } - + MY_DBG("Input image size\t\t= %6i\n\tNew rings data block size\t= %6i\n\tOutput image size (max)\t\t<=%6i", sizeImageIn, sizeNewDataBlock, sizeImageOutThisEst); MY_DBG("entryOffset = %i\n\tsizeOfThis = %i\n\tMeta data size = %i", @@ -841,12 +841,12 @@ int write_wiggle_flip_to_image( void *io_imageOut, } deltaLC = i_wfInlineLenInWords*4; memcpy( (uint8_t*)ringsBuffer+bufLC, i_wfInline, deltaLC); - + // Append WF ring layout to .rings section of in-memory input image. // Note! All layout members should already be 8-byte aligned. // - rc = sbe_xip_append( io_imageOut, - SBE_XIP_SECTION_RINGS, + rc = sbe_xip_append( io_imageOut, + SBE_XIP_SECTION_RINGS, (void*)ringsBuffer, sizeNewDataBlock, sizeImageOutThisEst, @@ -868,7 +868,7 @@ int write_wiggle_flip_to_image( void *io_imageOut, return IMGBUILD_ERR_XIP_MISC; } MY_DBG("Successful append of RS4 ring to .rings. Next, update forward ptr..."); - + // Update forward pointer associated with the ring/var name + any override offset. // // Convert the ring offset (wrt .rings address) to an PORE address @@ -881,12 +881,12 @@ int write_wiggle_flip_to_image( void *io_imageOut, return IMGBUILD_ERR_XIP_MISC; } // ...then update the forward pointer, i.e. the old "variable/ring name's" pointer. - // DO NOT add any 8-byte offset if override ring. The backItemPtr already has this + // DO NOT add any 8-byte offset if override ring. The backItemPtr already has this // from p8_delta_scan. // backPtr = myRev64(i_ringLayout->backItemPtr); MY_DBG("backPtr = 0x%016llx", backPtr); - rc = sbe_xip_write_uint64( io_imageOut, + rc = sbe_xip_write_uint64( io_imageOut, backPtr, fwdPtr); rc = rc+sbe_xip_read_uint64(io_imageOut, @@ -898,7 +898,7 @@ int write_wiggle_flip_to_image( void *io_imageOut, return IMGBUILD_ERR_XIP_MISC; } if (fwdPtrCheck!=ringPoreAddress || backPtr!=myRev64(i_ringLayout->backItemPtr)) { - MY_ERR("Forward or backward pointer mess. Check code."); + MY_ERR("Forward or backward pointer mess. Check code."); MY_ERR("fwdPtr =0x%016llx",fwdPtr); MY_ERR("fwdPtrCheck =0x%016llx",fwdPtrCheck); MY_ERR("layout bckPtr=0x%016llx",myRev64(i_ringLayout->backItemPtr)); @@ -916,9 +916,9 @@ int write_wiggle_flip_to_image( void *io_imageOut, if (ringsBuffer) free(ringsBuffer); return IMGBUILD_ERR_XIP_MISC; } - + if (ringsBuffer) free(ringsBuffer); - + return rc; } @@ -940,12 +940,12 @@ int append_empty_section( void *io_image, SBE_XIP_ERROR_STRINGS(errorStrings); rc = 0; - + if (*i_sizeSection==0) { MY_INF("INFO : Requested append size = 0. Nothing to do."); return rc; } - + // Check if there is enough room in the new image to add section. // sbe_xip_image_size( io_image, &sizeImageIn); @@ -960,11 +960,11 @@ int append_empty_section( void *io_image, *i_sizeImageMaxNew = sizeImageOutThisEst; return IMGBUILD_ERR_IMAGE_TOO_LARGE; } - + // Add the NULL buffer as a section append. sbe_xip_append() initializes with 0s. // - rc = sbe_xip_append( io_image, - i_sectionId, + rc = sbe_xip_append( io_image, + i_sectionId, NULL, *i_sizeSection, sizeImageOutThisEst, @@ -984,7 +984,7 @@ int append_empty_section( void *io_image, MY_ERR("xip_validate() of output image failed: %s", SBE_XIP_ERROR_STRING(errorStrings, rc)); return IMGBUILD_ERR_XIP_MISC; } - + // Return final section size. // rc = sbe_xip_get_section( io_image, i_sectionId, &xipSection); @@ -1047,7 +1047,7 @@ int initialize_slw_section( void *io_image, MY_ERR("***_RET or _NOP generated rc = %d", ctx.error); return IMGBUILD_ERR_PORE_INLINE_ASM; } - + // ... get host and pore location of Scom table in .slw section. // Note that we will assume, further down, that the NC section goes first, // then the L2 section and then the L3 section. @@ -1068,7 +1068,7 @@ int initialize_slw_section( void *io_image, hostScomTableL2 = (void*)((uintptr_t)hostScomTableNC + SLW_SCOM_TABLE_SIZE_NC); hostScomTableL3 = (void*)((uintptr_t)hostScomTableL2 + SLW_SCOM_TABLE_SIZE_L2); - + // ... get location of ----> Scom NC <---- vector from TOC. rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem); if (rc) { @@ -1161,8 +1161,8 @@ int create_and_initialize_fixed_image( void *io_image) // Ensure, to play it safe, that last two sections (.slw & .ffdc) are both on // 128-byte boundaries. The max [fixed] image size must itself already be // 128-byte aligned. - sizeSectionFit = (int) ( FIXED_SLW_IMAGE_SIZE - - sizeImageIn - + sizeSectionFit = (int) ( FIXED_SLW_IMAGE_SIZE - + sizeImageIn - FIXED_SLW_SECTION_SIZE - FIXED_FFDC_SECTION_SIZE ); if (sizeSectionFit<0) { @@ -1173,7 +1173,7 @@ int create_and_initialize_fixed_image( void *io_image) MY_ERR("Size of .ffdc section = %i\n",FIXED_FFDC_SECTION_SIZE); return IMGBUILD_ERR_SECTION_SIZING; } - + // Append .fit // sizeImageChk = FIXED_SLW_IMAGE_SIZE; @@ -1192,7 +1192,7 @@ int create_and_initialize_fixed_image( void *io_image) sizeSectionChk, sizeSectionReq); return IMGBUILD_ERR_SECTION_SIZING; } - + // Append .slw // sizeImageChk = FIXED_SLW_IMAGE_SIZE; @@ -1211,10 +1211,10 @@ int create_and_initialize_fixed_image( void *io_image) sizeSectionChk, sizeSectionReq); return IMGBUILD_ERR_SECTION_SIZING; } - + // Append .ffdc - // + // sizeImageChk = FIXED_SLW_IMAGE_SIZE; sizeSectionReq = FIXED_FFDC_SECTION_SIZE; sizeSectionChk = sizeSectionReq; @@ -1245,7 +1245,7 @@ int create_and_initialize_fixed_image( void *io_image) return IMGBUILD_ERR_KEYWORD_NOT_FOUND; } hostRamTable = (void*)((uintptr_t)io_image + xipSection.iv_offset); - + // ... get location of Ram vector. rc = sbe_xip_find( io_image, SLW_HOST_REG_VECTOR_TOC_NAME, &xipTocItem); if (rc) { @@ -1278,7 +1278,7 @@ int create_and_initialize_fixed_image( void *io_image) MY_ERR("***_RET or _NOP generated rc = %d", ctx.error); return IMGBUILD_ERR_PORE_INLINE_ASM; } - + // ... calc host ptr to Scom NC subsection. // Note that we will assume, further down, that the NC section goes first, // then the L2 section and then the L3 section. @@ -1299,7 +1299,7 @@ int create_and_initialize_fixed_image( void *io_image) hostScomTableL2 = (void*)((uintptr_t)hostScomTableNC + SLW_SCOM_TABLE_SIZE_NC); hostScomTableL3 = (void*)((uintptr_t)hostScomTableL2 + SLW_SCOM_TABLE_SIZE_L2); - + // ... get location of ----> Scom NC <---- vector from TOC. rc = sbe_xip_find( io_image, SLW_HOST_SCOM_NC_VECTOR_TOC_NAME, &xipTocItem); if (rc) { @@ -1379,7 +1379,7 @@ int update_runtime_scom_pointer( void *io_image) MY_ERR("\tThe keyword (=%s) was not found.",SLW_RUNTIME_SCOM_TOC_NAME); return IMGBUILD_ERR_KEYWORD_NOT_FOUND; } - + // Update host_runtime_scom with sub_slw_runtime_scom's address. // rc = sbe_xip_set_scalar( io_image, HOST_RUNTIME_SCOM_TOC_NAME, xipSlwRuntimeAddr); @@ -1447,7 +1447,7 @@ int write_vpd_ring_to_ipl_image(void *io_image, uint32_t asmInitLC=0; uint32_t asmBuffer[ASM_RS4_LAUNCH_BUF_SIZE/4]; uint64_t scanChipletAddress=0; - + SBE_XIP_ERROR_STRINGS(errorStrings); MY_INF("i_ringName=%s; \n", i_ringName); @@ -1458,7 +1458,7 @@ int write_vpd_ring_to_ipl_image(void *io_image, } sbe_xip_image_size( io_image, &sizeImageIn); - + chipletId = i_bufRs4Ring->iv_chipletId; // Create RS4 launcher and store in asmBuffer. @@ -1470,13 +1470,13 @@ int write_vpd_ring_to_ipl_image(void *io_image, MY_ERR("\tProbable cause:\n"); MY_ERR("\t\tThe key word (=proc_sbe_decompress_scan_chiplet_address) does not exist in the image. (No TOC record.)\n"); return IMGBUILD_ERR_KEYWORD_NOT_FOUND; - } + } else if (rc==SBE_XIP_BUG) { MY_ERR("\tProbable cause:\n"); MY_ERR("\t\tIllegal keyword, maybe?\n"); return IMGBUILD_ERR_XIP_MISC; - } + } else { MY_ERR("\tUnknown cause.\n"); return IMGBUILD_ERR_XIP_UNKNOWN; @@ -1521,7 +1521,7 @@ int write_vpd_ring_to_ipl_image(void *io_image, DeltaRingLayout *bufRs4RingBlock; uint64_t entryOffsetRs4RingBlock; uint32_t sizeRs4RingBlock, sizeRs4RingBlockMax; - + bufRs4RingBlock = (DeltaRingLayout*)i_bufTmp; //HB buf2. sizeRs4RingBlockMax = i_sizeBufTmp; entryOffsetRs4RingBlock = calc_ring_layout_entry_offset( 0, 0); @@ -1554,7 +1554,7 @@ int write_vpd_ring_to_ipl_image(void *io_image, memcpy( (uint8_t*)bufRs4RingBlock+bufLC, (uint8_t*)i_bufRs4Ring, (size_t)sizeRs4Ring); // Now, some post-sanity checks on alignments. - if ( entryOffsetRs4RingBlock%8 || + if ( entryOffsetRs4RingBlock%8 || sizeRs4RingBlock%8) { MY_ERR("Member(s) of RS4 ring block are not 8-byte aligned; \n"); MY_ERR(" Entry offset = %i; \n", (uint32_t)entryOffsetRs4RingBlock); @@ -1625,7 +1625,7 @@ int write_vpd_ring_to_slw_image(void *io_image, uint64_t waitsScanDelay=0; uint64_t twinHaltOpCodes; uint32_t iFill; - + MY_INF("i_ringName=%s; \n", i_ringName); if (i_bufTmp == NULL) { @@ -1634,9 +1634,9 @@ int write_vpd_ring_to_slw_image(void *io_image, } sbe_xip_image_size( io_image, &sizeImageIn); - + chipletId = i_bufRs4Ring->iv_chipletId; - + // Decompress RS4 VPD ring. // sizeRingRaw = myRev32(i_bufRs4Ring->iv_length); @@ -1698,7 +1698,7 @@ int write_vpd_ring_to_slw_image(void *io_image, return IMGBUILD_ERR_WF_CREATE; } - // Populate ring header and put ring header and Wf ring into + // Populate ring header and put ring header and Wf ring into // proper spots in pre-allocated bufWfRingBlock buffer (HB buf2). // DeltaRingLayout *bufWfRingBlock; @@ -1710,17 +1710,17 @@ int write_vpd_ring_to_slw_image(void *io_image, entryOffsetWfRingBlock = calc_ring_layout_entry_offset( 1, 0); bufWfRingBlock->entryOffset = myRev64(entryOffsetWfRingBlock); bufWfRingBlock->backItemPtr = 0; // Will be updated below, as we don't know yet. - - // Allocate either fitted or worst-case space for the ring. For example, the + + // Allocate either fitted or worst-case space for the ring. For example, the // rings, ex_repr_core/eco, need worst-case space allocation. if (i_bWcSpace==0) { // Fitted space sizing. sizeWfRingBlock = entryOffsetWfRingBlock + // Must be 8-byte aligned. wfInlineLenInWords*4; // Must be 8-byte aligned. } - else { + else { // Worst-case space sizing. - sizeWfRingBlock = ((sizeRingRaw-1)/32 + 1) * 4 * WF_WORST_CASE_SIZE_FAC + + sizeWfRingBlock = ((sizeRingRaw-1)/32 + 1) * 4 * WF_WORST_CASE_SIZE_FAC + WF_ENCAP_SIZE; sizeWfRingBlock = (uint32_t)myByteAlign(8, sizeWfRingBlock); // Fill void with "halt" instructions, 0x02000000 (LE). Note, void is whole multiple of 8x. @@ -1743,7 +1743,7 @@ int write_vpd_ring_to_slw_image(void *io_image, memcpy( (uint8_t*)bufWfRingBlock+bufLC, wfInline, (size_t)wfInlineLenInWords*4); // Now, some post-sanity checks on alignments. - if ( entryOffsetWfRingBlock%8 || + if ( entryOffsetWfRingBlock%8 || sizeWfRingBlock%8) { MY_ERR("Member(s) of WF ring block are not 8-byte aligned:"); MY_ERR(" Entry offset = %i", (uint32_t)entryOffsetWfRingBlock); @@ -1788,7 +1788,7 @@ int write_vpd_ring_to_slw_image(void *io_image, // check_and_perform_ring_datacare() // // Checks if the Mvpd ring passed has a datacare ring in the .dcrings image section. If it does, -// the Mvpd's ring bits corresponding to the care bits in the 1st half of the dc cring will be +// the Mvpd's ring bits corresponding to the care bits in the 1st half of the dc cring will be // overwritten by the data bits in the 2nd half of the dc ring. int check_and_perform_ring_datacare( void *i_imageRef, void *io_buf1, // Mvpd ring in/out. BE format. @@ -1807,14 +1807,14 @@ int check_and_perform_ring_datacare( void *i_imageRef, SbeXipItem xipTocItem; uint8_t bMatch=0; uint32_t sizeRs4Container; - - + + bitLength = myRev32(((CompressedScanData*)io_buf1)->iv_length); scanSelect = myRev32(((CompressedScanData*)io_buf1)->iv_scanSelect); ringId = ((CompressedScanData*)io_buf1)->iv_ringId; chipletId = ((CompressedScanData*)io_buf1)->iv_chipletId; flushOpt = ((CompressedScanData*)io_buf1)->iv_flushOptimization; - + MY_INF("In check_and_perform_ring_datacare()...\n"); MY_DBG("Mvpd ring characteristics:\n"); @@ -1823,14 +1823,14 @@ int check_and_perform_ring_datacare( void *i_imageRef, MY_DBG("Chiplet ID: 0x%02x\n",chipletId); MY_DBG("Flush Opt: %i\n",flushOpt); MY_DBG("Scan select: 0x%08x\n",scanSelect); - + rc = sbe_xip_find( i_imageRef, i_ringName, &xipTocItem); if (rc) { MY_ERR("_find() failed w/rc=%i\n",rc); return IMGBUILD_ERR_KEYWORD_NOT_FOUND; } MY_DBG("xipTocItem.iv_address=0x%016llx\n",xipTocItem.iv_address); - + // Now look for datacare match in .dcrings section. nextRing = NULL; rs4Datacare = NULL; @@ -1865,7 +1865,7 @@ int check_and_perform_ring_datacare( void *i_imageRef, else MY_DBG("rs4Datacare=NULL (no ring matched search criteria, or empty ring section.)\n"); } while (nextRing!=NULL && !bMatch); - + if (bMatch) { // Decompress Mvpd ring. @@ -1884,14 +1884,14 @@ int check_and_perform_ring_datacare( void *i_imageRef, rc = _rs4_decompress( (uint8_t*)io_buf1, i_sizeBuf2, // Assumption is that sizeBuf2=sizeBuf1 &ringBitLenDc, - (CompressedScanData*)( (uintptr_t)rs4Datacare + + (CompressedScanData*)( (uintptr_t)rs4Datacare + myRev64(rs4Datacare->entryOffset) + ASM_RS4_LAUNCH_BUF_SIZE) ); if (rc) { MY_ERR("_rs4_decompress(datacare...) failed: rc=%i\n",rc); return IMGBUILD_ERR_RS4_DECOMPRESS; } - + MY_DBG("bitLength=%i\n",bitLength); MY_DBG("ringBitLen=%i\n",ringBitLen); MY_DBG("ringBitLenDc=%i\n",ringBitLenDc); @@ -1900,11 +1900,11 @@ int check_and_perform_ring_datacare( void *i_imageRef, ringBitLen, ringBitLenDc); return IMGBUILD_ERR_DATACARE_RING_MESS; } - + // Overlay io_buf2 bits according to care and data bits in io_buf1 uint32_t iWord, remBits32; uint32_t dataVpd, dataDc, careDc, careDc1, careDc2; - + // Split apart the raw datacare ring into data (1st part) and care (2nd part). // Note that the order is already in BE for both Datacare and Mvpd rings. // Further note that the care part is fractured into two words that need to @@ -1932,7 +1932,7 @@ int check_and_perform_ring_datacare( void *i_imageRef, return IMGBUILD_ERR_DATACARE_RING_MESS; } } - + // Compress overlayed Mvpd ring. rc = _rs4_compress( (CompressedScanData*)io_buf1, i_sizeBuf2, @@ -1946,12 +1946,12 @@ int check_and_perform_ring_datacare( void *i_imageRef, if (rc) { MY_ERR("\t_rs4_compress() failed: rc=%i ",rc); return IMGBUILD_ERR_RS4_DECOMPRESS; - } - + } + } - + MY_INF("Leaving check_and_perform_ring_datacare()...\n"); - + return rc; } @@ -1967,8 +1967,8 @@ int check_and_perform_ring_datacare( void *i_imageRef, // - p8_delta_scan_w // - p8_delta_scan_r // - ??? -void cleanup( void *buf1, - void *buf2, +void cleanup( void *buf1, + void *buf2, void *buf3, void *buf4, void *buf5) diff --git a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C index abb08f456..470c76d07 100644 --- a/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C +++ b/src/usr/hwpf/hwp/build_winkle_images/p8_slw_build/p8_pore_table_gen_api.C @@ -61,8 +61,8 @@ */ uint32_t p8_pore_gen_cpureg( void *io_image, uint32_t i_sizeImage, - uint32_t i_regName, - uint64_t i_regData, + uint32_t i_regName, + uint64_t i_regData, uint32_t i_coreId, // [0:15] uint32_t i_threadId) { @@ -83,12 +83,12 @@ uint32_t p8_pore_gen_cpureg( void *io_image, uint32_t sprSwiz=0; #ifdef DYNAMIC_RAM_TABLE uint32_t iCore=0, sizeTableThis=0, sizeTableAll=0; - void *hostRamEntryFirstAll; // First entry of all Ram tables. - void *hostRamEntryLastAll; // Last entry of all Ram tables. + void *hostRamEntryFirstAll; // First entry of all Ram tables. + void *hostRamEntryLastAll; // Last entry of all Ram tables. uint64_t xipRamTableNext; void *hostRamTableNext; #endif - + // ------------------------------------------------------------------------- // Validate Ramming parameters. // @@ -121,7 +121,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, if (rcLoc) return IMGBUILD_ERR_RAM_INVALID_PARM; rcLoc = 0; - + // ------------------------------------------------------------------------- // Validate image and get pointer to SLW section. // @@ -146,7 +146,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, } hostSlwRamSection = (void*)((uint8_t*)io_image + xipSection.iv_offset); sbe_xip_host2pore( io_image, hostSlwRamSection, &xipSlwRamSection); - + // ------------------------------------------------------------------------- // Cross check SPR register and table defines // @@ -155,7 +155,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED; } if (xipSection.iv_size!=SLW_RAM_TABLE_SIZE+SLW_SCOM_TABLE_SIZE_ALL) { - MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); + MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); MY_ERR("Check code or image version.\n"); return IMGBUILD_ERR_RAM_HDRS_NOT_SYNCED; } @@ -169,7 +169,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, MY_INF("Image validation and size checks - OK\n"); MY_INF("\tImage size = %i\n",i_sizeImage); MY_INF("\tSLW section size= %i\n",xipSection.iv_size); - + // ------------------------------------------------------------------------- // Locate RAM vector and locate RAM table associated with "This" core ID. // @@ -188,13 +188,13 @@ uint32_t p8_pore_gen_cpureg( void *io_image, hostRamTableThis = NULL; bNewTable = 1; } - + #ifdef DYNAMIC_RAM_TABLE hostRamEntryFirstAll = hostSlwRamSection; hostRamEntryLastAll = hostRamEntryFirstAll; // ------------------------------------------------------------------------- - // Walk the RAM vector and RAM tables to + // Walk the RAM vector and RAM tables to // - determine size of present tables, sizeTableAll - we'll need it when/if shifting entries forward // - check for RAM table overflow. // @@ -237,14 +237,14 @@ uint32_t p8_pore_gen_cpureg( void *io_image, } #else // ------------------------------------------------------------------------- - // We don't need to walk the "this" RAM table to check for RAM table + // We don't need to walk the "this" RAM table to check for RAM table // as this is done further down during insertion of the entry. // #endif - - + + // ------------------------------------------------------------------------- - // Walk the "This" core ID's RAM table to + // Walk the "This" core ID's RAM table to // - determine insertion point, hostRamEntryThis, of new RAM entry // if (bNewTable) { @@ -258,11 +258,11 @@ uint32_t p8_pore_gen_cpureg( void *io_image, bEntryEnd = 1; #else // Append to beginning of agreed upon static position for this coreId. - hostRamTableThis = (void*)((uint8_t*)hostSlwRamSection + + hostRamTableThis = (void*)((uint8_t*)hostSlwRamSection + (uint32_t)(SLW_RAM_TABLE_SIZE/SLW_MAX_CORES)*i_coreId ); hostRamEntryThis = hostRamTableThis; // ...update RAM vector (since it is currently NULL) - *((uint64_t*)hostRamVector + i_coreId) = myRev64( xipSlwRamSection + + *((uint64_t*)hostRamVector + i_coreId) = myRev64( xipSlwRamSection + (uint32_t)(SLW_RAM_TABLE_SIZE/SLW_MAX_CORES)*i_coreId ); bEntryEnd = 1; #endif @@ -308,8 +308,8 @@ uint32_t p8_pore_gen_cpureg( void *io_image, // (Need to do this before inserting new RAM entry at hostRamEntryThis.) // if (!bNewTable) - for ( ramEntryNext=(RamTableEntry*)hostRamEntryLastAll; - ramEntryNext>=(RamTableEntry*)hostRamEntryThis; + for ( ramEntryNext=(RamTableEntry*)hostRamEntryLastAll; + ramEntryNext>=(RamTableEntry*)hostRamEntryThis; ramEntryNext-- ) { *(ramEntryNext+1) = *ramEntryNext; if ((ramEntryNext+1)->instr!=ramEntryNext->instr) { @@ -337,7 +337,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, ( ((uint32_t)headerType) << RAM_HEADER_TYPE_START_C & RAM_HEADER_TYPE_MASK_C ) | ( i_regName << RAM_HEADER_SPRN_START_C & RAM_HEADER_SPRN_MASK_C ) | ( i_threadId << RAM_HEADER_THREAD_START_C & RAM_HEADER_THREAD_MASK_C ); - // ...do the SPR instr + // ...do the SPR instr sprSwiz = i_regName>>5 | (i_regName & 0x0000001f)<<5; if (sprSwiz!=SLW_SPR_REGS[iReg].swizzled) { MY_ERR("Inconsistent swizzle rules implemented. Check code. Dumping data.\n"); @@ -389,7 +389,7 @@ uint32_t p8_pore_gen_cpureg( void *io_image, uint32_t p8_pore_gen_scom( void *io_image, uint32_t i_sizeImage, uint32_t i_scomAddr, - uint32_t i_coreId, // [0:15] + uint32_t i_coreId, // [0:15] uint64_t i_scomData, uint32_t i_operation, // [0:5] uint32_t i_section) // [0,2,3] @@ -399,7 +399,7 @@ uint32_t p8_pore_gen_scom( void *io_image, uint32_t operation=0; uint32_t entriesCount=0, entriesMatch=0, entriesNOP=0; uint32_t sizeImageIn=0; - void *hostSlwSection; + void __attribute__((unused)) *hostSlwSection; // HACK uint64_t xipScomTableThis; void *hostScomVector, *hostScomTableThis; void *hostScomEntryNext; // running entry pointer @@ -410,7 +410,7 @@ uint32_t p8_pore_gen_scom( void *io_image, SbeXipSection xipSection; SbeXipItem xipTocItem; PoreInlineContext ctx; - + // ------------------------------------------------------------------------- // Validate Scom parameters. // @@ -433,7 +433,7 @@ uint32_t p8_pore_gen_scom( void *io_image, if (rcLoc) return IMGBUILD_ERR_SCOM_INVALID_PARM; rcLoc = 0; - + // ------------------------------------------------------------------------- // Validate image and get pointer to SLW section. // @@ -459,7 +459,7 @@ uint32_t p8_pore_gen_scom( void *io_image, hostSlwSection = (void*)((uint8_t*)io_image + xipSection.iv_offset); // ...check .slw section size if (xipSection.iv_size!=SLW_RAM_TABLE_SIZE+SLW_SCOM_TABLE_SIZE_ALL) { - MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); + MY_ERR("SLW table size in *.H header file differs from SLW section size in image.\n"); MY_ERR("Check code or image version.\n"); return IMGBUILD_ERR_SCOM_HDRS_NOT_SYNCD; } @@ -475,9 +475,9 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_INF("Image validation and size checks - OK\n"); MY_INF("\tImage size = %i\n",i_sizeImage); MY_INF("\tSLW section size= %i\n",xipSection.iv_size); - + // ------------------------------------------------------------------------- - // Locate Scom vector according to i_section and then locate Scom table + // Locate Scom vector according to i_section and then locate Scom table // associated with "This" core ID. // switch (i_section) { @@ -528,7 +528,7 @@ uint32_t p8_pore_gen_scom( void *io_image, // doesn't include NOP entries.) // - If no NOP found, insert at first RET. // - + // First, create search strings for addr, nop and ret. // Note, the following IIS will also be used in case of // - i_operation==append @@ -552,7 +552,7 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_ERR("pore_NOP generated rc = %d", ctx.error); return IMGBUILD_ERR_PORE_INLINE_ASM; } - + // Second, search for addr and nop in relevant coreId table until first RET. // Note: // - We go through ALL entries until first RET instr. We MUST find a RET instr, @@ -560,7 +560,7 @@ uint32_t p8_pore_gen_scom( void *io_image, // - Count number of entries and check for overrun, though we'll continue // searching until we find an RET. (Should be improved.) // - The STI(+SCOM_addr) opcode is in the 2nd word of the Scom entry. - // - For an append operation, if a NOP is found (before a RET obviously), the + // - For an append operation, if a NOP is found (before a RET obviously), the // SCOM is replacing that NNNN sequence. hostScomEntryNext = hostScomTableThis; while (memcmp(hostScomEntryNext, bufRET, sizeof(uint32_t))) { @@ -576,7 +576,7 @@ uint32_t p8_pore_gen_scom( void *io_image, hostScomEntryNext = (void*)((uintptr_t)hostScomEntryNext + XIPSIZE_SCOM_ENTRY); } hostScomEntryRET = hostScomEntryNext; // The last EntryNext will always be the first RET. - + switch (i_section) { case 0: if (entriesCount>=SLW_MAX_SCOMS_NC) { @@ -651,7 +651,7 @@ uint32_t p8_pore_gen_scom( void *io_image, i_operation, P8_PORE_SCOM_FIRST_OP, P8_PORE_SCOM_LAST_OP); return IMGBUILD_ERR_SCOM_INVALID_PARM; } - + // ------------------------------------------------------------------------- // Assuming pre-allocated Scom table (after pre-allocated Ram table): // - Table is pre-filled with RNNN ISS. @@ -660,7 +660,7 @@ uint32_t p8_pore_gen_scom( void *io_image, // - Remember to check for more than SLW_MAX_SCOMS_NC entries! switch (operation) { - case P8_PORE_SCOM_APPEND: // Append a Scom at first occurring NNNN or RNNN, + case P8_PORE_SCOM_APPEND: // Append a Scom at first occurring NNNN or RNNN, if (hostScomEntryNOP) { // ... replace the NNNN MY_INF("Append at NOP\n"); @@ -695,7 +695,7 @@ uint32_t p8_pore_gen_scom( void *io_image, MY_INF("Replace existing Scom w/NOPs\n"); memcpy(hostScomEntryMatch,(void*)bufIIS,XIPSIZE_SCOM_ENTRY); } - else { + else { // do nothing, and assume everything is fine, since we did no damage. } break; @@ -703,10 +703,10 @@ uint32_t p8_pore_gen_scom( void *io_image, if (hostScomEntryMatch) { // ... do an OR on the data (which is the 2nd DWord in the entry) MY_INF("Overlay existing Scom - OR case\n"); - *((uint64_t*)hostScomEntryMatch+1) = + *((uint64_t*)hostScomEntryMatch+1) = *((uint64_t*)hostScomEntryMatch+1) | myRev64(i_scomData); } - else { + else { MY_ERR("No Scom entry found to do OR operation with.\n"); return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND; } @@ -715,10 +715,10 @@ uint32_t p8_pore_gen_scom( void *io_image, if (hostScomEntryMatch) { // ... do an AND on the data (which is the 2nd DWord in the entry) MY_INF("Overlay existing Scom - AND case\n"); - *((uint64_t*)hostScomEntryMatch+1) = + *((uint64_t*)hostScomEntryMatch+1) = *((uint64_t*)hostScomEntryMatch+1) & myRev64(i_scomData); } - else { + else { MY_ERR("No Scom entry found to do AND operation with.\n"); return IMGBUILD_ERR_SCOM_ENTRY_NOT_FOUND; } @@ -734,7 +734,7 @@ uint32_t p8_pore_gen_scom( void *io_image, default: MY_ERR("Impossible value of operation (=%i). Check code.\n",operation); return IMGBUILD_ERR_CHECK_CODE; - + } // End of switch(operation) return rc; diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C index a34f347bc..ede8687c2 100644 --- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.C +++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.C @@ -27,9 +27,9 @@ // *! *** IBM Confidential *** // *!*************************************************************************** // *! FILENAME : io_clear_firs.C -// *! TITLE : +// *! TITLE : // *! DESCRIPTION : To clear summary fir registers -// *! CONTEXT : +// *! CONTEXT : // *! // *! OWNER NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com // *! BACKUP NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com @@ -63,15 +63,15 @@ using namespace fapi; // for toggling the rx and tx fir reset. ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_interface,uint32_t i_group){ - + ReturnCode rc; uint32_t rc_ecmd=0; uint16_t bits = 0; ecmdDataBufferBase data_buffer; - + ecmdDataBufferBase set_bits(16); ecmdDataBufferBase clear_bits(16); - + //set the rx_fir_reset bit bits=rx_fir_reset; rc_ecmd|=set_bits.insert(bits,0,16); @@ -83,7 +83,7 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter return(rc); } rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + //clear the rx_fir_reset bit bits=0x0000; rc_ecmd|=set_bits.insert(bits,0,16); @@ -95,7 +95,7 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter return(rc); } rc=GCR_write(i_target,i_chip_interface,rx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + //set the tx_fir_reset bit bits=tx_fir_reset; rc_ecmd|=set_bits.insert(bits,0,16); @@ -107,7 +107,7 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter return(rc); } rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + //clear the tx_fir_reset bits=0x0000; rc_ecmd|=set_bits.insert(bits,0,16); @@ -119,76 +119,76 @@ ReturnCode clear_fir_err_regs(const Target &i_target,io_interface_t i_chip_inter return(rc); } rc=GCR_write(i_target,i_chip_interface,tx_reset_act_pg,i_group,0,set_bits ,clear_bits);if (rc) {return(rc);} - + return(rc); - + } ReturnCode read_fir_reg(const Target &i_target,fir_io_interface_t i_chip_interface,ecmdDataBufferBase &o_databuf_64bit){ - + ReturnCode rc; uint32_t rc_ecmd=0; uint64_t scom_address64=0; ecmdDataBufferBase temp(64); rc_ecmd |=o_databuf_64bit.flushTo0(); - + //get the 64 bit scom address. temp.setDoubleWord(0,fir_rw_reg_addr[i_chip_interface]); scom_address64=temp.getDoubleWord(0); - + //read the 64 bit fir register rc=fapiGetScom(i_target,scom_address64,o_databuf_64bit); - + return(rc); } ReturnCode io_clear_firs(const fapi::Target &i_target){ - + ReturnCode rc; - fir_io_interface_t interface; + fir_io_interface_t __attribute__((unused)) interface; // HACK io_interface_t gcr_interface; // requires different base address for gcr scoms uint32_t group; - + //on dmi if( (i_target.getType() == fapi::TARGET_TYPE_MCS_CHIPLET )){ FAPI_DBG("This is a Processor DMI bus using base DMI scom address"); interface=FIR_CP_IOMC0_P0; // base scom for MC bus gcr_interface=CP_IOMC0_P0; group=3; // design requires us to swap - + } else if((i_target.getType() == fapi::TARGET_TYPE_MEMBUF_CHIP)){ FAPI_DBG("This is a Centaur DMI bus using base DMI scom address"); interface=FIR_CEN_DMI; gcr_interface=CEN_DMI; group=0; - + } else if((i_target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT)){ FAPI_DBG("This is a X Bus invocation"); interface=FIR_CP_FABRIC_X0; gcr_interface=CP_FABRIC_X0; group=0; - + } - + else if((i_target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT)){ FAPI_DBG("This is an A Bus invocation"); interface=FIR_CP_FABRIC_A0; gcr_interface=CP_FABRIC_A0; group=0; - + } else{ FAPI_ERR("Invalid io_clear_firs HWP invocation . Target doesnt belong to DMI/X/A instances"); FAPI_SET_HWP_ERROR(rc, IO_CLEAR_FIRS_INVALID_INVOCATION_RC); return(rc); } - + rc=clear_fir_err_regs(i_target,gcr_interface,group); - + return(rc); } diff --git a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C index 8b012fda9..993daf49a 100644 --- a/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C +++ b/src/usr/hwpf/hwp/bus_training/io_power_down_lanes.C @@ -27,19 +27,19 @@ // *! *** IBM Confidential *** // *!*************************************************************************** // *! FILENAME : io_read_erepair.C -// *! TITLE : +// *! TITLE : // *! DESCRIPTION : Power down bad lanes -// *! CONTEXT : +// *! CONTEXT : // *! // *! OWNER NAME : Varghese, Varkey Email: varkey.kv@in.ibm.com -// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com +// *! BACKUP NAME : Swaminathan, Janani Email: jaswamin@in.ibm.com // *! // *!*************************************************************************** // CHANGE HISTORY: //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|--------|-------------------------------------------------- -// 1.0 |varkeykv||Initial check in +// 1.0 |varkeykv||Initial check in //------------------------------------------------------------------------------ #include <fapi.H> @@ -55,7 +55,7 @@ using namespace fapi; /* This function will perform power down of lanes on any IO target MEMBUF,MCS , XBUS or ABUS * Bad lanes are powered down , but caller is expected to logically disable lanes by calling restore_repair prior - * to calling this HWP + * to calling this HWP */ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> &tx_lanes,const std::vector<uint8_t> &rx_lanes) @@ -69,28 +69,28 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> & io_interface_t interface=CP_IOMC0_P0; // Since G uint32_t rc_ecmd=0; uint8_t clock_group=0; - uint8_t start_group=0; - uint8_t end_group=0; - + uint8_t __attribute__((unused)) start_group=0; // HACK + uint8_t __attribute__((unused)) end_group=0; // HACK + rc_ecmd=mask.flushTo1(); if(rc_ecmd) { rc.setEcmdError(rc_ecmd); return(rc); } - // Both TX and RX power down bits are on bit 0 + // Both TX and RX power down bits are on bit 0 rc_ecmd=mask.clearBit(0); if(rc_ecmd) { rc.setEcmdError(rc_ecmd); return(rc); } - - // Check which type of bus this is and do setup needed + + // Check which type of bus this is and do setup needed if(target.getType() == fapi::TARGET_TYPE_ABUS_ENDPOINT) { start_group=0; end_group=0; - interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT + interface=CP_FABRIC_A0; // base scom for A bus , assume translation to A1 by PLAT } else if(target.getType() == fapi::TARGET_TYPE_XBUS_ENDPOINT ) { start_group=0; @@ -112,7 +112,7 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> & FAPI_SET_HWP_ERROR(rc, IO_RUN_TRAINING_INVALID_INVOCATION_RC); return(rc); } - + FAPI_INF("Power down IO lanes\n"); rc_ecmd|=data.flushTo0(); @@ -123,26 +123,26 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> & rc.setEcmdError(rc_ecmd); return(rc); } - - //TX Lanes power down + + //TX Lanes power down for(uint8_t i=0;i<tx_lanes.size();++i){ clock_group=0; lane=tx_lanes[i]; - //For Xbus figure out the clock group number + //For Xbus figure out the clock group number if(interface==CP_FABRIC_X0){ while(lane>(xbus_lanes_per_group-1)){ lane=lane-xbus_lanes_per_group; clock_group++; } } - //Power down this lane + //Power down this lane rc = GCR_write( target, interface, tx_mode_pl, clock_group, lane, data,mask ); if(rc){return rc;} } - // Process RX lane powerdown + // Process RX lane powerdown for(uint8_t i=0;i<rx_lanes.size();++i){ clock_group=0; lane=rx_lanes[i]; @@ -153,7 +153,7 @@ ReturnCode io_power_down_lanes(const Target& target,const std::vector<uint8_t> & clock_group++; } } - //Power down this lane + //Power down this lane rc = GCR_write( target, interface, rx_mode_pl, clock_group, lane, data,mask ); if(rc){return rc;} } diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C index e8ca570f0..0a1a2f7f9 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_draminit_training_advanced.C @@ -44,7 +44,7 @@ // Version:| Author: | Date: | Comment: //---------|----------|---------|----------------------------------------------- // 1.1 | sasethur |30-Sep-11| Initial draft. -// 1.2 | sasethur |18-Nov-11| Changed function names +// 1.2 | sasethur |18-Nov-11| Changed function names // 1.3 | sasethur |01-Dec-11| Added details on Vref shmoo, reg addresses // 1.4 | sasethur |29-Jan-12| Updated wr&rd vref, removed ecmd workarounds // 1.5 | sasethur |13-Feb-12| Updated register naming conventions @@ -62,10 +62,10 @@ // 1.20 | bellows |13-Nov-12| Updated for new SI attributes // 1.21 | sasethur |11-Nov-12| Updated for new SI attribute change, fw review comments // 1.22 | sasethur |07-Dec-12| Updated for FW review comments - multiple changes -// 1.23 | sasethur |14-Dec-12| Updated for FW review comments -// 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file -// 1.25 | abhijsau |31-Jan-13| removed mss_mcbist_common.C include file , needs to be included while compiling -// 1.26 | abhijsau |06-Mar-13| fixed fw comment +// 1.23 | sasethur |14-Dec-12| Updated for FW review comments +// 1.24 | sasethur |17-Jan-13| Updated for mss_mcbist_common.C include file +// 1.25 | abhijsau |31-Jan-13| removed mss_mcbist_common.C include file , needs to be included while compiling +// 1.26 | abhijsau |06-Mar-13| fixed fw comment // This procedure Schmoo's DRV_IMP, SLEW, VREF (DDR, CEN), RCV_IMP based on attribute from effective config procedure @@ -74,7 +74,7 @@ // Internal Vref controlled by this function & external vref platform to provide function we return value // Not supported -// DDR4, DIMM Types +// DDR4, DIMM Types //---------------------------------------------------------------------- // Includes - FAPI //---------------------------------------------------------------------- @@ -100,15 +100,15 @@ enum shmoo_param { PARAM_NONE = 0x00, DELAY_REG = 0x01, - DRV_IMP = 0x02, + DRV_IMP = 0x02, SLEW_RATE = 0x04, WR_VREF = 0x08, RD_VREF = 0x10, - RCV_IMP = 0x20 + RCV_IMP = 0x20 }; -extern "C" +extern "C" { using namespace fapi; @@ -117,66 +117,66 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, - uint8_t i_pattern, uint8_t i_test_type); + shmoo_type_t i_shmoo_type_valid, + uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, uint8_t i_test_type); fapi::ReturnCode delay_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, - shmoo_type_t i_shmoo_type_valid, + shmoo_type_t i_shmoo_type_valid, uint32_t *o_left_margin, uint32_t *o_right_margin, uint8_t i_pattern, uint8_t i_test_type); -void find_best_margin(shmoo_param i_shmoo_param_valid,uint32_t i_left[], - uint32_t i_right[], const uint8_t i_max, +void find_best_margin(shmoo_param i_shmoo_param_valid,uint32_t i_left[], + uint32_t i_right[], const uint8_t i_max, uint32_t i_param_nom, uint8_t& o_index); //----------------------------------------------------------------------------------- //Function name: mss_draminit_training_advanced() //Description: This function varies driver impedance, receiver impedance, slew, wr & rd vref //based on attribute definition and runs either mcbist/delay shmoo based on attribute -//Also calls unmask function mss_unmask_draminit_training_advanced_errors() -//Input : const fapi::Target MBA, i_pattern = pattern selection during mcbist @ lab, -// l_test type = test type selection during mcbist @ lab +//Also calls unmask function mss_unmask_draminit_training_advanced_errors() +//Input : const fapi::Target MBA, i_pattern = pattern selection during mcbist @ lab, +// l_test type = test type selection during mcbist @ lab // Default vlaues are Zero //----------------------------------------------------------------------------------- -fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba, - uint8_t i_pattern, +fapi::ReturnCode mss_draminit_training_advanced(const fapi::Target & i_target_mba, + uint8_t i_pattern, uint8_t i_test_type) { // const fapi::Target is centaur.mba - + fapi::ReturnCode rc; - FAPI_INF(" pattern bit is %d and test_type_bit is %d",i_pattern,i_test_type); - + FAPI_INF(" pattern bit is %d and test_type_bit is %d",i_pattern,i_test_type); + rc = mss_draminit_training_advanced_cloned(i_target_mba,i_pattern,i_test_type); - if (rc) + if (rc) { FAPI_ERR("Advanced DRAM Init training procedure is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); } - + // If mss_unmask_draminit_training_advanced_errors gets it's own bad rc, // it will commit the passed in rc (if non-zero), and return it's own bad rc. - // Else if mss_unmask_draminit_training_advanced_errors runs clean, + // Else if mss_unmask_draminit_training_advanced_errors runs clean, // it will just return the passed in rc. - + rc = mss_unmask_draminit_training_advanced_errors(i_target_mba, rc); - if (rc) + if (rc) { FAPI_ERR("Unmask Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); return rc; @@ -200,42 +200,42 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta { //const fapi::Target is centaur.mba fapi::ReturnCode rc; - char procedure_name[32]; + char procedure_name[32]; sprintf(procedure_name, "mss_draminit_training_advanced"); FAPI_INF("+++++++ Executing %s +++++++", procedure_name); - + // Define attribute variables uint32_t l_attr_mss_freq_u32 = 0; - uint32_t l_attr_mss_volt_u32 = 0; + uint32_t l_attr_mss_volt_u32 = 0; uint8_t l_num_drops_per_port_u8 = 2; uint8_t l_num_ranks_per_dimm_u8array[MAX_PORT][MAX_DIMM] = {{0}}; - uint8_t l_actual_dimm_size_u8 = 0; + uint8_t __attribute__((unused) l_actual_dimm_size_u8 = 0; // HACK uint8_t l_port = 0; uint8_t l_dimm_type_u8 = 0; //default is set to CDIMM - uint32_t l_left_margin=0; - uint32_t l_right_margin=0; - + uint32_t l_left_margin=0; + uint32_t l_right_margin=0; + // Define local variables uint8_t l_shmoo_type_valid_t=0; uint8_t l_shmoo_param_valid_t=0; - + //const fapi::Target is centaur fapi::Target l_target_centaur; - rc = fapiGetParentChip(i_target_mba, l_target_centaur); + rc = fapiGetParentChip(i_target_mba, l_target_centaur); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); + rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); + rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc; - - //const fapi::Target is centaur.mba - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); + + //const fapi::Target is centaur.mba + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target_mba, l_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target_mba, l_num_drops_per_port_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target_mba, l_num_ranks_per_dimm_u8array); if(rc) return rc; - + FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); FAPI_INF("freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); @@ -244,49 +244,49 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta FAPI_INF("num_ranks_per_dimm = [%02d][%02d][%02d][%02d] on %s.", l_num_ranks_per_dimm_u8array[0][0],l_num_ranks_per_dimm_u8array[0][1], l_num_ranks_per_dimm_u8array[1][0],l_num_ranks_per_dimm_u8array[1][1], i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) + if ( l_num_drops_per_port_u8 == fapi::ENUM_ATTR_EFF_NUM_DROPS_PER_PORT_DUAL ) { l_actual_dimm_size_u8 = 2; } - else + else { l_actual_dimm_size_u8 = 1; } - - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t); - if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, l_shmoo_param_valid_t); + + rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target_mba, l_shmoo_type_valid_t); if(rc) return rc; - + rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_PARAM_VALID, &i_target_mba, l_shmoo_param_valid_t); + if(rc) return rc; + shmoo_type_t l_shmoo_type_valid; shmoo_param l_shmoo_param_valid; l_shmoo_type_valid=(shmoo_type_t)l_shmoo_type_valid_t; l_shmoo_param_valid=(shmoo_param)l_shmoo_param_valid_t; - + FAPI_INF("+++++++++++++++++++++++++ Read Schmoo Attributes ++++++++++++++++++++++++++"); FAPI_INF("Schmoo param valid = 0x%x on %s", l_shmoo_param_valid, i_target_mba.toEcmdString()); FAPI_INF("Schmoo test valid = 0x%x on %s", l_shmoo_type_valid, i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - //Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit + //Check for Shmoo Parameter, if anyof them is enabled then go into the loop else the procedure exit - for ( l_port = 0; l_port < MAX_PORT; l_port += 1 ) + for ( l_port = 0; l_port < MAX_PORT; l_port += 1 ) { if (( l_num_ranks_per_dimm_u8array[l_port][0] > 0 ) || (l_num_ranks_per_dimm_u8array[l_port][1] > 0)) { - if((l_shmoo_param_valid != PARAM_NONE) || (l_shmoo_type_valid != TEST_NONE)) + if((l_shmoo_param_valid != PARAM_NONE) || (l_shmoo_type_valid != TEST_NONE)) { if((l_shmoo_param_valid & DRV_IMP) != 0) - { - rc = drv_imped_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); + { + rc = drv_imped_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) { FAPI_ERR("Driver Impedance Schmoo function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); return rc; } } - if((l_shmoo_param_valid & SLEW_RATE) !=0) + if((l_shmoo_param_valid & SLEW_RATE) !=0) { rc = slew_rate_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) @@ -295,7 +295,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta return rc; } } - if((l_shmoo_param_valid & WR_VREF) != 0) + if((l_shmoo_param_valid & WR_VREF) != 0) { rc = wr_vref_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) @@ -314,7 +314,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta } } if ((l_shmoo_param_valid & RCV_IMP) !=0) - { + { rc = rcv_imp_shmoo(i_target_mba, l_port, l_shmoo_type_valid, i_pattern,i_test_type); if (rc) { @@ -324,7 +324,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta } if (((l_shmoo_param_valid & DELAY_REG) != 0) || (l_shmoo_type_valid != TEST_NONE)) { - rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type); + rc = delay_shmoo(i_target_mba, l_port, l_shmoo_type_valid, &l_left_margin, &l_right_margin,i_pattern,i_test_type); if (rc) { FAPI_ERR("Delay Schmoo Function is Failed rc = 0x%08X (creator = %d)", uint32_t(rc), rc.getCreator()); @@ -332,7 +332,7 @@ fapi::ReturnCode mss_draminit_training_advanced_cloned(const fapi::Target & i_ta } } } - } + } } return rc; } @@ -366,7 +366,7 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint8_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0}; uint32_t l_drv_imp_dq_dqs_schmoo[MAX_PORT] = {0}; uint8_t l_drv_imp_dq_dqs_nom_fc = 0; - //Temporary + //Temporary i_shmoo_type_valid = WR_EYE; //Hard coded, since no other schmoo is applicable for this parameter uint32_t l_left_margin_drv_imp_array[MAX_DRV_IMP] = {0}; uint32_t l_right_margin_drv_imp_array[MAX_DRV_IMP] = {0}; @@ -374,44 +374,44 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, uint32_t l_right_margin = 0; uint8_t count = 0; uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address - - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); + + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs); + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_drv_imp_dq_dqs_schmoo); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++Read DRIVER IMP Attributes values++++++++++++++++"); FAPI_INF("CEN_DRV_IMP_DQ_DQS[%d] = [%02d] Ohms, on %s", i_port, l_drv_imp_dq_dqs_nom[i_port], i_target_mba.toEcmdString()); FAPI_INF("CEN_DRV_IMP_DQ_DQS_SCHMOO[0] = [0x%x], CEN_DRV_IMP_DQ_DQS_SCHMOO[1] = [0x%x] on %s", l_drv_imp_dq_dqs_schmoo[0],l_drv_imp_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s", l_slew_rate_dq_dqs[0],l_slew_rate_dq_dqs[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s", l_slew_rate_dq_dqs_schmoo[0],l_slew_rate_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - + if(l_drv_imp_dq_dqs_schmoo[i_port] == 0) //Check for any of the bits enabled in the shmoo { FAPI_INF("DRIVER IMP Shmoo set to FAST Mode and won't do anything"); } else - { - for(index = 0; index< MAX_DRV_IMP; index+=1) + { + for(index = 0; index< MAX_DRV_IMP; index+=1) { - if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK) + if (l_drv_imp_dq_dqs_schmoo[i_port] & MASK) { l_drv_imp_dq_dqs[i_port] = drv_imp_array[index]; FAPI_INF("Current Driver Impedance Value = %d Ohms", drv_imp_array[index]); FAPI_INF("Configuring Driver Impedance Registers:"); - rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs[i_port]); + rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs[i_port]); if (rc) return rc; FAPI_INF("Configuring Slew Rate Registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; FAPI_INF("Calling Shmoo for finding Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type); if (rc) return rc; l_left_margin_drv_imp_array[index]= l_left_margin; l_right_margin_drv_imp_array[index]= l_right_margin; @@ -426,7 +426,7 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, l_drv_imp_dq_dqs_nom_fc = l_drv_imp_dq_dqs_nom[i_port]; find_best_margin(DRV_IMP, l_left_margin_drv_imp_array, l_right_margin_drv_imp_array, MAX_DRV_IMP, l_drv_imp_dq_dqs_nom_fc, count); - + if (count >= MAX_DRV_IMP) { FAPI_ERR("Driver Imp new input(%d) out of bounds, (>= %d)", @@ -436,7 +436,7 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_drv_imp_dq_dqs_new[0] = drv_imp_array[count]; @@ -447,28 +447,28 @@ fapi::ReturnCode drv_imped_shmoo(const fapi::Target & i_target_mba, l_drv_imp_dq_dqs_new[1] = drv_imp_array[count]; l_drv_imp_dq_dqs_new[0] = l_drv_imp_dq_dqs_nom[0]; } - + if (l_drv_imp_dq_dqs_new[i_port] != l_drv_imp_dq_dqs_nom[i_port]) { FAPI_INF("Better Margin found on %d Ohms on %s", l_drv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_new); if (rc) return rc; FAPI_INF("Configuring New Driver Impedance Value to Registers:"); rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs_new[i_port]); if (rc) return rc; - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_new[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_new[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed - Restoring the original values!"); + FAPI_INF("Nominal value will not be changed - Restoring the original values!"); rc = config_drv_imp(i_target_mba, i_port, l_drv_imp_dq_dqs_nom[i_port]); if (rc) return rc; - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; - } + } } - + FAPI_INF("++++ Driver impedance shmoo function executed successfully ++++"); } return rc; @@ -500,7 +500,7 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint32_t l_slew_rate_dq_dqs_schmoo[MAX_PORT] = {0}; uint8_t l_drv_imp_dq_dqs_nom[MAX_PORT] = {0}; i_shmoo_type_valid = WR_EYE; // Hard coded - Other shmoo type is not valid - Temporary - + uint8_t index = 0; uint8_t count = 0; uint32_t l_left_margin_slew_array[MAX_NUM_SLEW_RATES] = {0}; @@ -508,21 +508,21 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint8_t l_slew_type = 0; // Hard coded since this procedure will touch only DQ_DQS and not address - + //Read Attributes - DRV IMP, SLEW, SLEW RATES values to be Schmoo'ed - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS, &i_target_mba, l_drv_imp_dq_dqs_nom); if (rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_nom); + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_DRV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_slew_rate_dq_dqs_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++Read Slew Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_DRV_IMP_DQ_DQS[0] = [%02d] Ohms, CEN_DRV_IMP_DQ_DQS[1] = [%02d] Ohms on %s", l_drv_imp_dq_dqs_nom[0],l_drv_imp_dq_dqs_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS[0] = [%02d]V/ns , CEN_SLEW_RATE_DQ_DQS[1] = [%02d]V/ns on %s", l_slew_rate_dq_dqs_nom[0],l_slew_rate_dq_dqs_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_SLEW_RATE_DQ_DQS_SCHMOO[0] = [0x%x], CEN_SLEW_RATE_DQ_DQS_SCHMOO[1] = [0x%x] on %s", l_slew_rate_dq_dqs_schmoo[0],l_slew_rate_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - + if(l_slew_rate_dq_dqs_schmoo == 0) //Check for any of the bits enabled in the shmoo { FAPI_INF("Slew Rate Shmoo set to FAST Mode and won't do anything"); @@ -531,16 +531,16 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, { for(index = 0; index < MAX_NUM_SLEW_RATES; index+=1) { - if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK ) + if (l_slew_rate_dq_dqs_schmoo[i_port] & MASK ) { l_slew_rate_dq_dqs[i_port] = slew_rate_array[index]; FAPI_INF("Current Slew rate value is %d V/ns", slew_rate_array[index]); FAPI_INF("Configuring Slew registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs[i_port]); if (rc) return rc; FAPI_INF("Calling Shmoo for finding Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type); if (rc) return rc; l_left_margin_slew_array[index]= l_left_margin; l_right_margin_slew_array[index]= l_right_margin; @@ -564,38 +564,38 @@ fapi::ReturnCode slew_rate_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_slew_rate_dq_dqs_new[0] = slew_rate_array[count]; - l_slew_rate_dq_dqs_new[1] = l_slew_rate_dq_dqs_nom[1]; + l_slew_rate_dq_dqs_new[1] = l_slew_rate_dq_dqs_nom[1]; } else { l_slew_rate_dq_dqs_new[1] = slew_rate_array[count]; - l_slew_rate_dq_dqs_new[0] = l_slew_rate_dq_dqs_nom[0]; + l_slew_rate_dq_dqs_new[0] = l_slew_rate_dq_dqs_nom[0]; } - - - + + + if (l_slew_rate_dq_dqs_new[i_port] != l_slew_rate_dq_dqs_nom[i_port]) { FAPI_INF("Better Margin found on Slew Rate: %d V/ns on %s", l_slew_rate_dq_dqs_new[i_port], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_SLEW_RATE_DQ_DQS, &i_target_mba, l_slew_rate_dq_dqs_new); if (rc) return rc; FAPI_INF("Configuring New Slew Rate Value to Registers:"); - rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs_new[i_port]); + rc = config_slew_rate(i_target_mba, i_port, l_slew_type, l_drv_imp_dq_dqs_nom[i_port], l_slew_rate_dq_dqs_new[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!"); + FAPI_INF("Nominal value will not be changed!"); FAPI_INF("Slew Rate: %d V/ns on %s", l_slew_rate_dq_dqs_nom[i_port], i_target_mba.toEcmdString()); } } FAPI_INF("++++ Slew Rate shmoo function executed successfully ++++"); } -return rc; +return rc; } //---------------------------------------------------------------------------------------------- @@ -620,19 +620,19 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, uint32_t l_wr_dram_vref[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_nom[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_new[MAX_PORT] = {0}; - uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; + uint32_t l_wr_dram_vref_schmoo[MAX_PORT] = {0}; uint32_t l_wr_dram_vref_nom_fc = 0; i_shmoo_type_valid = WR_EYE; // Hard coded - Temporary - + uint8_t index = 0; uint8_t count = 0; uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_wr_vref_array[MAX_WR_VREF]= {0}; uint32_t l_right_margin_wr_vref_array[MAX_WR_VREF]= {0}; - + //Read the write vref attributes - rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_nom); + rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WR_VREF_SCHMOO, &i_target_mba, l_wr_dram_vref_schmoo); if (rc) return rc; @@ -640,8 +640,8 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, FAPI_INF("DRAM_WR_VREF[0] = %d , DRAM_WR_VREF[0] = %d on %s", l_wr_dram_vref_nom[0], l_wr_dram_vref_nom[1],i_target_mba.toEcmdString()); FAPI_INF("DRAM_WR_VREF_SCHMOO[0] = [%x],DRAM_WR_VREF_SCHMOO[0] = [%x] on %s", l_wr_dram_vref_schmoo[0], l_wr_dram_vref_schmoo[1],i_target_mba.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - - + + if(l_wr_dram_vref_schmoo[i_port] == 0) { FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings"); @@ -650,15 +650,15 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, { for(index = 0; index < MAX_WR_VREF; index+=1) { - if (l_wr_dram_vref_schmoo[i_port] & MASK) + if (l_wr_dram_vref_schmoo[i_port] & MASK) { FAPI_INF("Current Vref value is %dmV", wr_vref_array[index]); l_wr_dram_vref[i_port] = wr_vref_array[index]; - rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref[i_port]); + rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref[i_port]); if (rc) return rc; FAPI_INF(" Calling Shmoo for finding Timing Margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, - &l_left_margin, &l_right_margin, i_pattern, i_test_type); + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + &l_left_margin, &l_right_margin, i_pattern, i_test_type); if (rc) return rc; l_left_margin_wr_vref_array[index]= l_left_margin; l_right_margin_wr_vref_array[index]= l_right_margin; @@ -683,7 +683,7 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_wr_dram_vref_new[0] = wr_vref_array_fitness[count]; @@ -694,21 +694,21 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, l_wr_dram_vref_new[1] = wr_vref_array_fitness[count]; l_wr_dram_vref_new[0] = l_wr_dram_vref_nom[0]; } - + if(l_wr_dram_vref_new[i_port] != l_wr_dram_vref_nom[i_port]) { FAPI_INF("Best Margin Found on Vref : %d , %d mV on %s", count, wr_vref_array_fitness[count], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_new); + rc = FAPI_ATTR_SET(ATTR_EFF_DRAM_WR_VREF, &i_target_mba, l_wr_dram_vref_new); if (rc) return rc; FAPI_INF("Configuring New Vref Value to registers:"); - rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_new[i_port]); - if (rc) return rc; + rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_new[i_port]); + if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_nom[i_port]); - if (rc) return rc; + FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); + rc = config_wr_dram_vref(i_target_mba, i_port, l_wr_dram_vref_nom[i_port]); + if (rc) return rc; } } FAPI_INF("++++ Write Vref Shmoo function executed successfully ++++"); @@ -719,21 +719,21 @@ fapi::ReturnCode wr_vref_shmoo(const fapi::Target & i_target_mba, //---------------------------------------------------------------------------------------------- -// Function name: rd_vref_shmoo() -// Description: This function varies the Centaur IO vref in 16 steps -// Calls write eye shmoo function +// Function name: rd_vref_shmoo() +// Description: This function varies the Centaur IO vref in 16 steps +// Calls write eye shmoo function // Input param: const fapi::Target MBA, port = 0,1 // Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS // Shmoo param: PARAM_NONE, DRV_IMP, SLEW_RATE, WR_VREF, RD_VREF, RCV_IMP // Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR // i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg //---------------------------------------------------------------------------------------------- - + fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t i_port, shmoo_type_t i_shmoo_type_valid, uint8_t i_pattern, - uint8_t i_test_type) + uint8_t i_test_type) { fapi::ReturnCode rc; uint32_t l_rd_cen_vref[MAX_PORT] = {0}; @@ -744,23 +744,23 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, uint8_t index = 0; uint8_t count = 0; i_shmoo_type_valid = RD_EYE; // Hard coded - Temporary - + uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_rd_vref_array[MAX_RD_VREF] = {0}; uint32_t l_right_margin_rd_vref_array[MAX_RD_VREF] = {0}; - - + + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RD_VREF_SCHMOO, &i_target_mba, l_rd_cen_vref_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++CENTAUR VREF Read Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_RD_VREF[0] = %d CEN_RD_VREF[1] = %d on %s", l_rd_cen_vref_nom[0],l_rd_cen_vref_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_RD_VREF_SCHMOO[0] = [%d], CEN_RD_VREF_SCHMOO[1] = [%d] on %s", l_rd_cen_vref_schmoo[0], l_rd_cen_vref_schmoo[1],i_target_mba.toEcmdString()); FAPI_INF("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); - + if(l_rd_cen_vref_schmoo[i_port] == 0) { FAPI_INF("FAST Shmoo Mode: This function will not change any Write DRAM VREF settings"); @@ -800,7 +800,7 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_rd_cen_vref_new[0] = rd_cen_vref_array_fitness[count]; @@ -811,20 +811,20 @@ fapi::ReturnCode rd_vref_shmoo(const fapi::Target & i_target_mba, l_rd_cen_vref_new[1] = rd_cen_vref_array_fitness[count]; l_rd_cen_vref_new[0] = l_rd_cen_vref_nom[0]; } - + if(l_rd_cen_vref_new[i_port] != l_rd_cen_vref_nom[i_port]) { FAPI_INF("Best Margin Found on Vref : %dmv , %dmV on %s", l_rd_cen_vref_new[i_port], rd_cen_vref_array_fitness[count], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RD_VREF, &i_target_mba, l_rd_cen_vref_new); if (rc) return rc; FAPI_INF("Configuring New Read Vref Value to Registers:"); - rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_new[i_port]); + rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_new[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); - rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_nom[i_port]); + FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); + rc = config_rd_cen_vref(i_target_mba, i_port, l_rd_cen_vref_nom[i_port]); if (rc) return rc; } } @@ -857,18 +857,18 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, uint8_t index = 0; uint8_t count = 0; i_shmoo_type_valid = RD_EYE; //Hard coded since no other shmoo is applicable - Temporary - + uint32_t l_left_margin = 0; uint32_t l_right_margin = 0; uint32_t l_left_margin_rcv_imp_array[MAX_RCV_IMP] = {0}; uint32_t l_right_margin_rcv_imp_array[MAX_RCV_IMP] = {0}; - - + + rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_nom); if (rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS_SCHMOO, &i_target_mba, l_rcv_imp_dq_dqs_schmoo); if (rc) return rc; - + FAPI_INF("+++++++++++++++++RECIVER IMP Read Shmoo Attributes values+++++++++++++++"); FAPI_INF("CEN_RCV_IMP_DQ_DQS[0] = %d , CEN_RCV_IMP_DQ_DQS[1] = %d on %s", l_rcv_imp_dq_dqs_nom[0],l_rcv_imp_dq_dqs_nom[1], i_target_mba.toEcmdString()); FAPI_INF("CEN_RCV_IMP_DQ_DQS_SCHMOO[0] = [%d], CEN_RCV_IMP_DQ_DQS_SCHMOO[1] = [%d], on %s", l_rcv_imp_dq_dqs_schmoo[0],l_rcv_imp_dq_dqs_schmoo[1], i_target_mba.toEcmdString()); @@ -889,7 +889,7 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, FAPI_INF("Configuring Receiver impedance registers:"); rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs[i_port]); if (rc) return rc; FAPI_INF("Calling Shmoo function to find out timing margin:"); - rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, + rc = delay_shmoo(i_target_mba, i_port, i_shmoo_type_valid, &l_left_margin, &l_right_margin, i_pattern, i_test_type); if (rc) return rc; l_left_margin_rcv_imp_array[index]= l_left_margin; @@ -914,7 +914,7 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, } else { - + if(i_port == 0) { l_rcv_imp_dq_dqs_new[0] = rcv_imp_array[count]; @@ -925,25 +925,25 @@ fapi::ReturnCode rcv_imp_shmoo(const fapi::Target & i_target_mba, l_rcv_imp_dq_dqs_new[1] = rcv_imp_array[count]; l_rcv_imp_dq_dqs_new[0] = l_rcv_imp_dq_dqs_nom[0]; } - + if (l_rcv_imp_dq_dqs_new[i_port] != l_rcv_imp_dq_dqs_nom[i_port]) { FAPI_INF("Better Margin found on %d on %s", l_rcv_imp_dq_dqs_new[i_port], i_target_mba.toEcmdString()); - rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_new); + rc = FAPI_ATTR_SET(ATTR_EFF_CEN_RCV_IMP_DQ_DQS, &i_target_mba, l_rcv_imp_dq_dqs_new); if (rc) return rc; rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs_new[i_port]); if (rc) return rc; } else { - FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); + FAPI_INF("Nominal value will not be changed!- Restoring the original values!"); rc = config_rcv_imp(i_target_mba, i_port, l_rcv_imp_dq_dqs_nom[i_port]); if (rc) return rc; } } FAPI_INF("++++ Receiver Impdeance Shmoo function executed successfully ++++"); } -return rc; +return rc; } //------------------------------------------------------------------------------ @@ -953,7 +953,7 @@ return rc; // Shmoo type: MCBIST, WR_EYE, RD_EYE, WR_DQS, RD_DQS // Shmoo Mode: FEW_ADDR, QUARTER_ADDR, HALF_ADDR, FULL_ADDR // i_pattern, i_test_type : Default = 0, mcbist lab function would use this arg -// Output param: l_left_margin = Left Margin(Setup time), +// Output param: l_left_margin = Left Margin(Setup time), // l_right_margin = Right Margin (Hold time) in ps //------------------------------------------------------------------------------ @@ -1001,12 +1001,12 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, uint32_t left_margin_nom = 0; uint32_t right_margin_nom = 0; uint32_t diff_margin_nom = 0; - uint32_t total_margin = 0; + uint32_t __attribute__((unused)) total_margin = 0; // HACK uint32_t diff_margin = 0; uint8_t index = 0; uint8_t index2 = 0; - - + + for(index = 0; index < i_max; index+=1) //send max from top function { if(i_shmoo_param_valid & DRV_IMP) @@ -1032,7 +1032,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, } } else if(i_shmoo_param_valid & WR_VREF) - { + { if (wr_vref_array_fitness[index] == i_param_nom) { left_margin_nom = i_left[index]; @@ -1043,7 +1043,7 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, } } else if(i_shmoo_param_valid & RD_VREF) - { + { if (rd_cen_vref_array_fitness[index] == i_param_nom) { left_margin_nom = i_left[index]; @@ -1054,17 +1054,17 @@ void find_best_margin(shmoo_param i_shmoo_param_valid, } } else if(i_shmoo_param_valid & RCV_IMP) - { + { if (rcv_imp_array[index] == i_param_nom) { left_margin_nom = i_left[index]; right_margin_nom = i_right[index]; diff_margin_nom = (i_left[index] >= i_right[index]) ? (i_left[index] - i_right[index]) : (i_right[index] - i_left[index]); FAPI_INF("Receiver Impedance value (NOM): %d Ohms Setup Margin: %d Hold Margin: %d", i_param_nom, i_left[index], i_right[index]); - break; + break; } } - + } for(index2 = 0; index2 < i_max; index2+=1) { diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C index c576bec61..ddbb0108f 100644 --- a/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C +++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_trainadv/mss_generic_shmoo.C @@ -27,7 +27,7 @@ // *! *** IBM Confidential *** // *!*************************************************************************** // *! FILENAME : mss_generic_shmoo.C -// *! TITLE : MSS Generic Shmoo Implementation +// *! TITLE : MSS Generic Shmoo Implementation // *! DESCRIPTION : Memory Subsystem Generic Shmoo -- abstraction for HB // *! CONTEXT : To make all shmoos share a common abstraction layer // *! @@ -39,19 +39,19 @@ //------------------------------------------------------------------------------ // Version:|Author: | Date: | Comment: // --------|--------|---------|-------------------------------------------------- -// 1.26 |abhijit |01/21/13 | fixed fw comments -// 1.25 |abhijit |01/21/13 | fixed the constructor definition +// 1.26 |abhijit |01/21/13 | fixed fw comments +// 1.25 |abhijit |01/21/13 | fixed the constructor definition // 1.21 |sasethur|01/17/13 | Updated for sanity mcbist function // 1.20 |abhijit |01/11/13 | Updated for change in setup_mcbist function // 1.19 |aditya |01/07/13 | Updated for change in setup_mcbist function -// 1.18 |sasethur|14-DEC-12| Updated for change in access delay function -// 1.16 |sasethur|14-DEC-12| Updated for Warning -// 1.15 |abhijit |13-DEC-12| Updated for FW review comments +// 1.18 |sasethur|14-DEC-12| Updated for change in access delay function +// 1.16 |sasethur|14-DEC-12| Updated for Warning +// 1.15 |abhijit |13-DEC-12| Updated for FW review comments // 1.14 |abhijit |06-DEC-12| Fixed more FW review comments // 1.12 |abhijit |15-Nov-12| Fixed FW review comments // 1.11 |abhijit |29-Oct-12| added change for ISDIMM checker DQS. -// 1.9 |abhijit |22-Oct-12| added Write and read DQS. -// 1.8 |abhijit |15-Oct-12|Updated multiple changes +// 1.9 |abhijit |22-Oct-12| added Write and read DQS. +// 1.8 |abhijit |15-Oct-12|Updated multiple changes // 1.0 |varkeykv|27-Sep-11|Initial check in //------------------------------------------------------------------------------ #include <fapi.H> @@ -66,11 +66,11 @@ extern "C" { using namespace fapi; -// START IMPLEMENTATION OF generic_shmoo CLASS METHODS +// START IMPLEMENTATION OF generic_shmoo CLASS METHODS //! shmoo_mask - What shmoos do you want to run ... encoded as Hex 0x2,0x4,0x8,0x16 /*------------------------------------------------------------------------------ * constructor: generic_shmoo - * Description :Constructor used to initialize variables and do the initial settings + * Description :Constructor used to initialize variables and do the initial settings * * Parameters: i_target: mba; iv_port: 0, 1 * ---------------------------------------------------------------------------*/ @@ -79,40 +79,40 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith //this->shmoo_mask=shmoo_mask; //! Sets what Shmoos the caller wants to run this->algorithm=shmoo_algorithm ; this->iv_port=prt ; - - + + iv_MAX_RANKS=8; iv_MAX_BYTES=10; iv_DQS_ON=0; iv_pattern=0; iv_test_type=0; iv_dmm_type=0; - + for(int i=0;i<iv_MAX_RANKS;++i) { valid_rank[i]=0; } - + FAPI_DBG("mss_generic_shmoo : constructor running for shmoo type %d",shmoo_mask); iv_shmoo_type = 0; SHMOO[iv_shmoo_type].static_knob.min_val=0; - SHMOO[iv_shmoo_type].static_knob.max_val=512; - - + SHMOO[iv_shmoo_type].static_knob.max_val=512; + + if(shmoo_mask & TEST_NONE) { FAPI_DBG("mss_generic_shmoo : WR_EYE selected %d",shmoo_mask); iv_shmoo_type = 0; SHMOO[0].static_knob.min_val=0; - SHMOO[0].static_knob.max_val=512; + SHMOO[0].static_knob.max_val=512; } - + if(shmoo_mask & WR_EYE) { FAPI_DBG("mss_generic_shmoo : WR_EYE selected %d",shmoo_mask); iv_shmoo_type = 0; SHMOO[0].static_knob.min_val=0; - SHMOO[0].static_knob.max_val=512; + SHMOO[0].static_knob.max_val=512; } if(shmoo_mask & RD_EYE) { @@ -121,7 +121,7 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith SHMOO[2].static_knob.min_val=0; SHMOO[2].static_knob.max_val=128; } - + if(shmoo_mask & WRT_DQS) //preet { FAPI_DBG("mss_generic_shmoo : WRT_DQS selected %d",shmoo_mask); @@ -130,17 +130,17 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith SHMOO[1].static_knob.min_val=0; SHMOO[1].static_knob.max_val=512; } - + if(shmoo_mask & RD_GATE) //preet { FAPI_DBG("mss_generic_shmoo : RD_EYE selected %d",shmoo_mask); - + iv_shmoo_type = 3; iv_DQS_ON = 1; SHMOO[3].static_knob.min_val=0; SHMOO[3].static_knob.max_val=128; } - + for(int j=0;j<iv_MAX_RANKS;++j) { init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.nom_val,0); @@ -150,7 +150,7 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.right_margin_val,0); init_multi_array(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[j].K.left_margin_val,0); } - + if(iv_DQS_ON == 1) { for(int j=0;j<iv_MAX_RANKS;++j) //initialize values for DQS @@ -172,7 +172,7 @@ generic_shmoo:: generic_shmoo(uint8_t prt,shmoo_type_t shmoo_mask,shmoo_algorith * Parameters: i_target: mba; iv_port: 0, 1 * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin,uint8_t i_pattern,uint8_t i_test_type){ - fapi::ReturnCode rc; + fapi::ReturnCode rc; uint8_t num_ranks_per_dimm[2][2]; uint8_t l_attr_eff_dimm_type_u8=0; uint8_t l_attr_schmoo_test_type_u8=0; @@ -180,14 +180,14 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri uint16_t l_sp_mask=0x00ff; ecmdDataBufferBase l_data_buffer1_64(64); uint32_t rc_num = 0; - + rc = FAPI_ATTR_GET(ATTR_EFF_NUM_RANKS_PER_DIMM, &i_target, num_ranks_per_dimm); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; - rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; + rc = FAPI_ATTR_GET(ATTR_EFF_SCHMOO_TEST_VALID, &i_target, l_attr_schmoo_test_type_u8); if(rc) return rc; iv_MAX_RANKS=num_ranks_per_dimm[iv_port][0]+num_ranks_per_dimm[iv_port][1]; iv_pattern=i_pattern; iv_test_type=i_test_type; - + if ( l_attr_eff_dimm_type_u8 == 0 ) { iv_MAX_BYTES=8; @@ -199,26 +199,26 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri rc_num = rc_num | l_data_buffer1_64.insertFromRight(l_sp_mask,0,16); if(rc_num) { - FAPI_ERR( "mss_generic_shmoo: Error in run !"); - rc.setEcmdError(rc_num); + FAPI_ERR( "mss_generic_shmoo: Error in run !"); + rc.setEcmdError(rc_num); return rc; - } + } } else { rc_num = rc_num | l_data_buffer1_64.insertFromRight(l_sp_mask,16,16); if(rc_num) { - FAPI_ERR( "mss_generic_shmoo:"); - rc.setEcmdError(rc_num); + FAPI_ERR( "mss_generic_shmoo:"); + rc.setEcmdError(rc_num); return rc; - } + } } rc = fapiPutScom(i_target,MBS_MCBIST01_MCBCMABQ_0x02011674,l_data_buffer1_64); if(rc) return rc; iv_dmm_type=1; iv_MAX_BYTES=9; } - rc = mss_getrankpair(i_target,iv_port,0,&rank_pair,valid_rank);if(rc) return rc; + rc = mss_getrankpair(i_target,iv_port,0,&rank_pair,valid_rank);if(rc) return rc; FAPI_DBG("mss_generic_shmoo : run() for shmoo type %d",shmoo_mask); // Check if all bytes/bits are in a pass condition initially .Otherwise quit if(l_attr_schmoo_test_type_u8 == 0){ @@ -226,19 +226,19 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri return rc; } if(l_attr_schmoo_test_type_u8 == 1){ - rc=sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only + rc=sanity_check(i_target); // Run MCBIST only when ATTR_EFF_SCHMOO_TEST_VALID is mcbist only if(!rc.ok()) { FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition"); - return rc; + return rc; } }else{ - // rc=sanity_check(i_target); // Run MCBIST by default before for every schmoo to check if memory is in good condition. + // rc=sanity_check(i_target); // Run MCBIST by default before for every schmoo to check if memory is in good condition. // if(!rc.ok()) // { // FAPI_ERR("generic_shmoo::run MSS Generic Shmoo failed initial Sanity Check. Memory not in an all pass Condition"); - // return rc; + // return rc; // } // If memory is OK then we continue to gather nominals and config values // Now Read nominal values for all knobs configured @@ -248,7 +248,7 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri rc=find_bound(i_target,RIGHT);if(rc) return rc; //Find LEFT BOUND OR HOLD BOUND rc=find_bound(i_target,LEFT);if(rc) return rc; - //Find the margins in Ps i.e setup margin ,hold margin,Eye width + //Find the margins in Ps i.e setup margin ,hold margin,Eye width rc=get_margin(i_target);if(rc) return rc; //It is used to find the lowest of setup and hold margin rc=get_min_margin(i_target,o_right_min_margin,o_left_min_margin);if(rc) return rc; @@ -261,7 +261,7 @@ fapi::ReturnCode generic_shmoo::run(const fapi::Target & i_target,uint32_t *o_ri * Function: sanity_check * Description : do intial mcbist check in nominal and report spd if any bad bit found * - * Parameters: i_target: mba; + * Parameters: i_target: mba; * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ fapi:: ReturnCode rc; @@ -271,24 +271,24 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ uint8_t l_rank_valid = 0; uint8_t l_byte = 0; uint8_t l_nibble = 0; - uint8_t l_socket =0; + uint8_t __attribute__((unused)) l_socket =0; // HACK uint32_t rc_num = 0; - uint8_t l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; + uint8_t __attribute__((unused)) l_dqBitmap[DIMM_DQ_RANK_BITMAP_SIZE]; // HACK uint64_t l_original_start_address1 = 0x0000000000000000; uint64_t l_original_end_address1 = 0x0000000000000000; uint64_t l_original_start_address2 = 0x0000000000000000; uint64_t l_original_end_address2 = 0x0000000000000000; - uint64_t l_start =0x0000000000000000ull; - uint64_t l_end = 0x0000000000000000ull; + uint64_t l_start =0x0000000000000000ull; + uint64_t l_end = 0x0000000000000000ull; uint64_t l_time = 0x0000000000000000ull; - ecmdDataBufferBase l_data_bufferx1_64(64); + ecmdDataBufferBase l_data_bufferx1_64(64); ecmdDataBufferBase l_data_bufferx2_64(64); - ecmdDataBufferBase l_data_bufferx3_64(64); + ecmdDataBufferBase l_data_bufferx3_64(64); ecmdDataBufferBase l_data_bufferx4_64(64); - + rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_bufferx1_64); if(rc) return rc; rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; + rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; l_original_start_address1 = l_data_bufferx1_64.getDoubleWord (0); l_original_end_address1 = l_data_bufferx2_64.getDoubleWord (0); @@ -297,17 +297,17 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ for(l_rank = 0; l_rank < iv_MAX_RANKS; l_rank++) { l_rank_valid=valid_rank[l_rank]; - + if(l_rank_valid<MAX_RANK_DIMM) - { + { l_socket=0; } else { l_socket=1; - } + } FAPI_INF(" entering set_up mcbist now and rank %d",l_rank_valid); - + rc = setup_mcbist(i_target, iv_port, MCBIST_2D_CUP_PAT8, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,l_rank_valid,0,l_start,l_end);if(rc) return rc; //send shmoo mode to vary the address range FAPI_INF(" starting mcbist now"); @@ -329,10 +329,10 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ else { l_dqBitmap[l_byte] = 0x0f; - } + } //rc = dimmSetBadDqBitmap(i_target,iv_port,l_socket, l_rank_valid, l_dqBitmap);if(rc) return rc; } - } + } } rc_num = l_data_bufferx1_64.setDoubleWord(0,l_original_start_address1);if (rc_num){FAPI_ERR( "Error in function sanity_check:");rc.setEcmdError(rc_num);return rc;} rc_num = l_data_bufferx2_64.setDoubleWord(0,l_original_end_address1);if (rc_num){FAPI_ERR( "Error in function sanity_check:");rc.setEcmdError(rc_num);return rc;} @@ -342,13 +342,13 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; - + } - + if(l_mcb_status) { FAPI_ERR("generic_shmoo:sanity_check failed !! MCBIST failed on intial run , memory is not in good state aborting shmoo"); - FAPI_SET_HWP_ERROR(rc,RC_MSS_MCBIST_ERROR); + FAPI_SET_HWP_ERROR(rc,RC_MSS_MCBIST_ERROR); return rc; } @@ -358,12 +358,12 @@ fapi::ReturnCode generic_shmoo::sanity_check(const fapi::Target & i_target){ * Function: do_mcbist_test * Description : do mcbist check for error on particular nibble * - * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; + * Parameters: i_target: mba,iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uint8_t i_rank,uint8_t i_byte,uint8_t i_nibble,uint8_t &pass) { mcbist_mode=QUARTER_SLOW; - uint8_t l_socket=0; + uint8_t __attribute__((unused)) l_socket=0; // HACK uint8_t l_mcb_status=0; input_type l_input_type_e = ISDIMM_DQ; uint8_t i_input_index_u8=0; @@ -374,54 +374,54 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uin uint64_t l_original_end_address1 = 0x0000000000000000; uint64_t l_original_start_address2 = 0x0000000000000000; uint64_t l_original_end_address2 = 0x0000000000000000; - ecmdDataBufferBase l_data_bufferx1_64(64); + ecmdDataBufferBase l_data_bufferx1_64(64); ecmdDataBufferBase l_data_bufferx2_64(64); - ecmdDataBufferBase l_data_bufferx3_64(64); + ecmdDataBufferBase l_data_bufferx3_64(64); ecmdDataBufferBase l_data_bufferx4_64(64); - uint64_t l_start =0x0000000000000000ull; - uint64_t l_end = 0x0000000000000000ull; + uint64_t l_start =0x0000000000000000ull; + uint64_t l_end = 0x0000000000000000ull; uint64_t l_time = 0x0000000000000000ull; rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA0Q_0x030106d0,l_data_bufferx1_64); if(rc) return rc; rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; - rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; + rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; rc = fapiGetScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; l_original_start_address1 = l_data_bufferx1_64.getDoubleWord (0); l_original_end_address1 = l_data_bufferx2_64.getDoubleWord (0); l_original_start_address2 = l_data_bufferx3_64.getDoubleWord (0); l_original_end_address2 = l_data_bufferx4_64.getDoubleWord (0); - + if(i_rank<4) - { + { l_socket=0; } else { l_socket=1; - } - - - + } + + + rc = setup_mcbist(i_target, iv_port, ABLE_FIVE, CENSHMOO, UNMASK_ALL, 0,iv_pattern,iv_test_type,i_rank,0,l_start,l_end);if(rc) return rc; //send shmoo mode to vary the address range - + rc = start_mcb(i_target); if(rc) { - FAPI_ERR("generic_shmoo::do_mcbist_test: Start MCBIST failed !!"); - + FAPI_ERR("generic_shmoo::do_mcbist_test: Start MCBIST failed !!"); + return rc; } rc=poll_mcb(i_target,false,&l_mcb_status,l_time); if(rc) { - FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); - + FAPI_ERR("generic_shmoo::do_mcbist_test: POLL MCBIST failed !!"); + return rc; } rc=mcb_error_map(i_target,mcbist_error_map,iv_port,i_rank); if(rc) { - FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); - + FAPI_ERR("generic_shmoo::do_mcbist_test: mcb_error_map failed!!"); + return rc; } rc_num = l_data_bufferx1_64.setDoubleWord(0,l_original_start_address1);if (rc_num){FAPI_ERR( "Error in function do_mcbist_test:");rc.setEcmdError(rc_num);return rc;} @@ -432,7 +432,7 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uin rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA0Q_0x030106d2,l_data_bufferx2_64); if(rc) return rc; rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSSARA1Q_0x030106d1,l_data_bufferx3_64); if(rc) return rc; rc = fapiPutScom(i_target,MBA01_MCBIST_MCBSEARA1Q_0x030106d3,l_data_bufferx4_64); if(rc) return rc; - + if(iv_dmm_type==1) { i_input_index_u8=8*i_byte+4*i_nibble; @@ -440,12 +440,12 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uin i_byte=l_val/8; i_nibble=l_val%4; check_error_map(i_rank,i_byte,i_nibble,pass); - + } else { check_error_map(i_rank,i_byte,i_nibble,pass); - + } return rc; } @@ -453,11 +453,11 @@ fapi::ReturnCode generic_shmoo::do_mcbist_test(const fapi::Target & i_target,uin * Function: check_error_map * Description : used by do_mcbist_test to check the error map for particular nibble * - * Parameters: iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; + * Parameters: iv_port 0/1 , rank 0-7 , byte 0-7, nibble 0/1, pass; * ---------------------------------------------------------------------------*/ void generic_shmoo::check_error_map(uint8_t i_rank,uint8_t i_byte,uint8_t i_nibble,uint8_t &pass) { - + if( mcbist_error_map [iv_port][i_rank][i_byte][i_nibble] == 1){ pass=0; // FAPI_INF("We are in error1"); @@ -467,7 +467,7 @@ void generic_shmoo::check_error_map(uint8_t i_rank,uint8_t i_byte,uint8_t i_nib pass=1; //FAPI_INF("We are in error2"); } - + } /*------------------------------------------------------------------------------ * Function: init_multi_array @@ -477,22 +477,22 @@ void generic_shmoo::check_error_map(uint8_t i_rank,uint8_t i_byte,uint8_t i_nib * ---------------------------------------------------------------------------*/ void generic_shmoo::init_multi_array(uint32_t (&array)[MAX_DQ][MAX_RPS],uint32_t init_val) { - + uint8_t l_byte,l_nibble,l_bit,l_rp; uint8_t l_dq=0; for (l_rp=0;l_rp<MAX_RPS;++l_rp) {// Byte loop - + for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { + { //Bit loop for(l_bit=0;l_bit<MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; array[l_dq][l_rp]=init_val; - } + } } } } @@ -511,17 +511,17 @@ fapi::ReturnCode generic_shmoo::init_multi_array_dqs(uint32_t (&array)[MAX_DQ][M uint8_t l_dq=0; for (l_rp=0;l_rp<MAX_RPS;++l_rp) {// Byte loop - + for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { + { //Bit loop for(l_bit=0;l_bit<MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; array[l_dq][l_rp]=init_val; - } + } } } } @@ -529,65 +529,65 @@ return rc; } /*------------------------------------------------------------------------------ * Function: get_all_noms - * Description : This function gets the nominal values for each DQ + * Description : This function gets the nominal values for each DQ * - * Parameters: Target:MBA + * Parameters: Target:MBA * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target) { fapi::ReturnCode rc; - + uint8_t l_rnk,l_byte,l_nibble,l_bit; uint8_t i_rnk=0; uint8_t i_rp=0; uint32_t val=0; uint8_t l_dq=0; - + input_type_t l_input_type_e = WR_DQ; access_type_t l_access_type_e = READ ; FAPI_DBG("mss_generic_shmoo : get_all_noms : Reading in all nominal values"); - - + + if(iv_shmoo_type == 1) - { + { l_input_type_e = WR_DQS; - + } else if(iv_shmoo_type == 2) - { - + { + l_input_type_e = RD_DQ; - + } else if(iv_shmoo_type == 3) - { - + { + l_input_type_e = RD_DQS; - + } - - + + for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) {// Byte loop i_rnk=valid_rank[l_rnk]; - rc = mss_getrankpair(i_target,iv_port,i_rnk,&i_rp,valid_rank);if(rc) return rc; + rc = mss_getrankpair(i_target,iv_port,i_rnk,&i_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) - { + { //Bit loop for(l_bit=0;l_bit<MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; - - rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,i_rnk,l_input_type_e,l_dq,0,val);if(rc) return rc; + + rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,i_rnk,l_input_type_e,l_dq,0,val);if(rc) return rc; SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rnk].K.nom_val[l_dq][i_rp]=val; FAPI_INF("Nominal Value for rank=%d and rank pair=%d and dq=%d is %d",i_rnk,i_rp,l_dq,val); - + } } } - } + } return rc; } @@ -598,7 +598,7 @@ fapi::ReturnCode generic_shmoo::get_all_noms(const fapi::Target & i_target) * Parameters: Target:MBA,bound:RIGHT/LEFT,scenario:type of schmoo,iv_port:0/1,rank:0-7,byte:0-7,nibble:0/1,bit:0-3,pass, * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_t bound,uint8_t scenario,uint8_t rank,uint8_t byte,uint8_t nibble,uint8_t bit,uint8_t pass,bool &flag) -{ +{ fapi::ReturnCode rc; ecmdDataBufferBase data_buffer_64(64); ecmdDataBufferBase data_buffer_64_1(64); @@ -621,21 +621,21 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ uint8_t l_dq=0; access_type_t l_access_type_e = WRITE; - - + + l_dq=8*byte+4*nibble+bit; - - rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; - - + + rc = mss_getrankpair(i_target,iv_port,rank,&l_rp,valid_rank);if(rc) return rc; + + if(scenario == 2) { l_input_type_e = RD_DQ; } - - + + if(bound==LEFT) { - + if(algorithm==SEQ_LIN) { l_min_value=SHMOO[scenario].static_knob.min_val; @@ -645,7 +645,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,1,l_current_val);if(rc) return rc; rc=do_mcbist_test(i_target,rank,byte,nibble,pass); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } @@ -654,7 +654,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ { pass=1; for(l_current_val=l_current_val+10;((l_current_val>l_min_value)&&(pass==1));l_current_val--) - { + { rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; rc = fapiGetScom(i_target,MBA01_MBA_PMU0Q_0x03010437,data_buffer_64); if(rc) return rc; l_rd_cnt_A = data_buffer_64.getDoubleWord(0); @@ -714,23 +714,23 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ { pass=1; } - } + } }while(l_delta<read_counter_threshold); if(!pass) { SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val; } - } + } } - + SHMOO[scenario].MBA.P[iv_port].S[rank].K.lb_regval[l_dq][l_rp]=l_current_val+l_left_del; - - + + l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; FAPI_INF(" the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val); rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; } - } + } if(bound==RIGHT) { if(algorithm==SEQ_LIN) @@ -742,12 +742,12 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,1,l_current_val);if(rc) return rc; rc=do_mcbist_test(i_target,rank,byte,nibble,pass); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } } - + if(flag) { pass=1; @@ -812,7 +812,7 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ { pass=1; } - } + } }while(l_delta<read_counter_threshold); if(!pass) { @@ -824,17 +824,17 @@ fapi::ReturnCode generic_shmoo::knob_update(const fapi::Target & i_target,bound_ } } } - + SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val-l_right_del; - + FAPI_INF(" the right bound for dq=%d is %d ",l_dq,SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]); l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; FAPI_INF(" the restoring nominal value for rank=%d dq=%d and rp=%d is %d",rank,l_dq,l_rp,l_current_val); rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,rank,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + } } - return rc; + return rc; } /*------------------------------------------------------------------------------ * Function: knob_update_dqs @@ -851,38 +851,38 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo data_buffer_64_1.flushTo0(); uint32_t l_current_val=0; uint32_t l_max_value=0; - uint32_t l_min_value=0; - + uint32_t __attribute__((unused)) l_min_value=0; // HACK + uint8_t l_rp=0; input_type_t l_input_type_e = WR_DQS; uint8_t l_dq=0; access_type_t l_access_type_e = WRITE; - - if(scenario == 1) + + if(scenario == 1) { l_input_type_e = WR_DQS; } - else if(scenario == 3) + else if(scenario == 3) { l_input_type_e = RD_DQS; } - + if(bound==LEFT) { - + if(algorithm==SEQ_LIN) { l_min_value=SHMOO[scenario].static_knob.min_val; FAPI_INF(" curr val in left above = %d and pass=%d ",l_current_val,pass); for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val >= 20)&&(pass==1));l_current_val-=20) { - //use saurabh function for writing here + //use saurabh function for writing here FAPI_INF(" curr val in left = %d and pass=%d ",l_current_val,pass); rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + rc=do_mcbist_test(i_target,rank,byte,nibble,pass); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } @@ -894,25 +894,25 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo FAPI_INF(" left bound = %d ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]); l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + } } - + else if(bound==RIGHT) { - + if(algorithm==SEQ_LIN) { l_max_value=SHMOO[scenario].static_knob.max_val; for(l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp];((l_current_val<l_max_value)&&(pass==1));l_current_val+=100) { - //use saurabh function for writing here + //use saurabh function for writing here FAPI_INF(" curr val = %d ",l_current_val); rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; - + rc=do_mcbist_test(i_target,rank,byte,nibble,pass); if(rc) - { + { FAPI_ERR("generic_shmoo::find_bound do_mcbist_test failed"); return rc; } @@ -922,11 +922,11 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]=l_current_val; } l_current_val=SHMOO[scenario].MBA.P[iv_port].S[rank].K.nom_val[l_dq][l_rp]; - + rc=mss_access_delay_reg(i_target,l_access_type_e,iv_port,0,l_input_type_e,l_dq,0,l_current_val);if(rc) return rc; FAPI_INF(" right bound = %d ",SHMOO[scenario].MBA.P[iv_port].S[rank].K.rb_regval[l_dq][l_rp]); } - + } return rc; } @@ -940,34 +940,34 @@ fapi::ReturnCode generic_shmoo::knob_update_dqs(const fapi::Target & i_target,bo fapi::ReturnCode generic_shmoo::find_bound(const fapi::Target & i_target,bound_t bound){ uint8_t l_rnk,l_byte,l_nibble,l_bit; fapi::ReturnCode rc; - + uint8_t i_rank=0; bool flag=false; - - - + + + FAPI_INF("generic_shmoo::find_bound running find_bound function "); - - + + for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) {// Byte loop i_rank=valid_rank[l_rnk]; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { //Nibble loop - + for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { - + //Bit loop for(l_bit=0;l_bit< MAX_BITS;++l_bit) { // preetham function here - - + + if(iv_DQS_ON==1) rc=knob_update_dqs(i_target,bound,iv_shmoo_type,i_rank,l_byte,l_nibble,l_bit,1);if(rc) return rc; else - rc=knob_update(i_target,bound,iv_shmoo_type,i_rank,l_byte,l_nibble,l_bit,1,flag); if(rc) return rc; + rc=knob_update(i_target,bound,iv_shmoo_type,i_rank,l_byte,l_nibble,l_bit,1,flag); if(rc) return rc; } } } @@ -977,14 +977,14 @@ fapi::ReturnCode generic_shmoo::find_bound(const fapi::Target & i_target,bound_t //#ifdef char /*------------------------------------------------------------------------------ * Function: print_report - * Description : This function is used to print the information needed such as freq,voltage etc, and also the right,left and total margin + * Description : This function is used to print the information needed such as freq,voltage etc, and also the right,left and total margin * * Parameters: Target:MBA * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target) { fapi::ReturnCode rc; - + uint8_t l_rnk,l_byte,l_nibble,l_bit; uint8_t l_dq=0; uint8_t l_rp=0; @@ -996,48 +996,48 @@ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target) uint8_t l_attr_eff_num_drops_per_port_u8 = 0; uint8_t l_attr_eff_dram_width_u8 = 0; fapi::Target l_target_centaur; - - + + rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc; - + rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_u32); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_MSS_VOLT, &l_target_centaur, l_attr_mss_volt_u32); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DIMM_TYPE, &i_target, l_attr_eff_dimm_type_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_NUM_DROPS_PER_PORT, &i_target, l_attr_eff_num_drops_per_port_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_EFF_DRAM_WIDTH, &i_target, l_attr_eff_dram_width_u8); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &i_target, l_mbapos);if(rc) return rc; - + FAPI_INF(" freq = %d on %s.", l_attr_mss_freq_u32, l_target_centaur.toEcmdString()); FAPI_INF("volt = %d on %s.", l_attr_mss_volt_u32, l_target_centaur.toEcmdString()); FAPI_INF("dimm_type = %d on %s.", l_attr_eff_dimm_type_u8, i_target.toEcmdString()); if ( l_attr_eff_dimm_type_u8 == fapi::ENUM_ATTR_EFF_DIMM_TYPE_CDIMM ) { - FAPI_INF("It is a CDIMM"); + FAPI_INF("It is a CDIMM"); } else { - FAPI_INF("It is an ISDIMM"); + FAPI_INF("It is an ISDIMM"); } FAPI_INF("num_drops_per_port = %d on %s.", l_attr_eff_num_drops_per_port_u8, i_target.toEcmdString()); FAPI_INF("num_ranks = %d on %s.", iv_MAX_RANKS,i_target.toEcmdString()); FAPI_INF("dram_width = %d on %s. \n\n", l_attr_eff_dram_width_u8, i_target.toEcmdString()); FAPI_INF("+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++"); FAPI_INF("Schmoo POS\tPort\tRank\tByte\tnibble\tbit\tNominal\t\tSetup_Limit\tHold_Limit\tWrD_Setup(ps)\tWrD_Hold(ps)\tEye_Width(ps)\tBitRate "); - - - + + + for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) {// Byte loop i_rank=valid_rank[l_rnk]; rc = mss_getrankpair(i_target,iv_port,i_rank,&l_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { - + //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { for(l_bit=0;l_bit< MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; if(iv_shmoo_type==0) @@ -1048,19 +1048,19 @@ fapi::ReturnCode generic_shmoo::print_report(const fapi::Target & i_target) { FAPI_INF("RD_EYE\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\t%d\n ",iv_port,l_mbapos,i_rank,l_byte,l_nibble,l_bit,SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.nom_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.rb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.lb_regval[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.right_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.left_margin_val[l_dq][l_rp],SHMOO[iv_shmoo_type].MBA.P[iv_port].S[i_rank].K.total_margin[l_dq][l_rp],l_attr_mss_freq_u32); } - + } } } } - - + + return rc; } //#endif /*------------------------------------------------------------------------------ * Function: get_margin - * Description : This function is used to get margin for setup,hold and total eye width in Ps by using frequency + * Description : This function is used to get margin for setup,hold and total eye width in Ps by using frequency * * Parameters: Target:MBA * ---------------------------------------------------------------------------*/ @@ -1076,26 +1076,26 @@ fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target) uint8_t i_rank=0; uint64_t l_factor=0; uint64_t l_factor_ps=1000000000; - + //FAPI_INF(" the factor is % llu ",l_cyc); - + fapi::Target l_target_centaur; rc = fapiGetParentChip(i_target, l_target_centaur); if(rc) return rc; rc = FAPI_ATTR_GET(ATTR_MSS_FREQ, &l_target_centaur, l_attr_mss_freq_margin_u32); if(rc) return rc; l_freq=l_attr_mss_freq_margin_u32/2; - l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data + l_cyc=l_cyc/l_freq;// converting to zepto to get more accurate data l_factor=l_cyc/128; //FAPI_INF("l_factor is % llu ",l_factor); - - - + + + for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) {// Byte loop i_rank=valid_rank[l_rnk]; - rc = mss_getrankpair(i_target,iv_port,i_rank,&l_rp,valid_rank);if(rc) return rc; + rc = mss_getrankpair(i_target,iv_port,i_rank,&l_rp,valid_rank);if(rc) return rc; for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { - + //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { @@ -1110,16 +1110,16 @@ fapi::ReturnCode generic_shmoo::get_margin(const fapi::Target & i_target) } } } - - + + return rc; } /*------------------------------------------------------------------------------ * Function: get_min_margin - * Description : This function is used to get the minimum margin of all the schmoo margins + * Description : This function is used to get the minimum margin of all the schmoo margins * - * Parameters: Target:MBA,right minimum margin , left minimum margin, pass fail + * Parameters: Target:MBA,right minimum margin , left minimum margin, pass fail * ---------------------------------------------------------------------------*/ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uint32_t *o_right_min_margin,uint32_t *o_left_min_margin) { @@ -1130,19 +1130,19 @@ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uin uint8_t l_dq=0; uint8_t l_rp=0; - - - + + + for (l_rnk=0;l_rnk<iv_MAX_RANKS;++l_rnk) {// Byte loop for(l_byte=0;l_byte<iv_MAX_BYTES;++l_byte) { - + //Nibble loop for(l_nibble=0;l_nibble< MAX_NIBBLES;++l_nibble) { for(l_bit=0;l_bit< MAX_BITS;++l_bit) - { + { l_dq=8*l_byte+4*l_nibble+l_bit; if(SHMOO[iv_shmoo_type].MBA.P[iv_port].S[l_rnk].K.right_margin_val[l_dq][l_rp]<l_temp_right) { @@ -1156,12 +1156,12 @@ fapi::ReturnCode generic_shmoo::get_min_margin(const fapi::Target & i_target,uin } } } - - - // hacked for now till schmoo is running + + + // hacked for now till schmoo is running *o_right_min_margin=l_temp_right; *o_left_min_margin=l_temp_left; return rc; } - + }//Extern C diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C index c57e9a717..303aef3d4 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_oha_init.C @@ -23,7 +23,7 @@ /* begin_generated_IBM_copyright_prolog */ /* */ /* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ +/* After initializing, DO NOT MODIFY OR MOVE */ /* --------------------------------------------------------------- */ /* IBM Confidential */ /* */ @@ -47,7 +47,7 @@ // *! OWNER NAME: Ralf Maier Email: ralf.maier@de.ibm.com // *! // *! General Description: -// *! +// *! // *! The purpose of this procedure is to do a initial setup of OHA // *! // *! Procedure Prereq: @@ -86,7 +86,7 @@ /// \version -------------------------------------------------------------------------- /// \version 1.4 rmaier 03/13/12 Added modes-structure /// \version -------------------------------------------------------------------------- -/// \version 1.0 rmaier 12/01/11 Initial Version +/// \version 1.0 rmaier 12/01/11 Initial Version /// \version --------------------------------------------------------------------------- /// /// @@ -122,20 +122,20 @@ /// -- select precounter for ppt timer ( 0=0.25us, 1=0.5us, 2=1us, 3=2us ) /// /// if PM_CONFIG { -/// -/// convert_ppt_time() - Convert Power Proxy Trace Time to Power Proxy Trace Time Select and Match feature attributes +/// +/// convert_ppt_time() - Convert Power Proxy Trace Time to Power Proxy Trace Time Select and Match feature attributes /// With ATTR_PM_POWER_PROXY_TRACE_TIMER (binary in nanoseconds) to produce ATTR_PM_PPT_TIMER_MATCH_VALUE and ATTR_PM_PPT_TIMER_TICK /// 0=0.25us , 1=0.5us, 2=1us, and 3=2us /// /// else if PM_INIT { -/// +/// /// Timer settings if not able to be done in the init file /// - PPT timer -/// - AISS hang timer +/// - AISS hang timer /// /// } else if PM_RESET { /// -/// AISS reset +/// AISS reset /// /// } //end PM_RESET -mode /// @@ -161,7 +161,7 @@ extern "C" { - + using namespace fapi; @@ -189,12 +189,12 @@ typedef struct { // Function definitions // ---------------------------------------------------------------------- -// Reset function +// Reset function fapi::ReturnCode p8_oha_init_reset (const Target &i_target, uint32_t i_mode); // Config function fapi::ReturnCode p8_oha_init_config (const fapi::Target& i_target) ; -// INIT -fapi::ReturnCode p8_oha_init_init (const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) ; +// INIT +fapi::ReturnCode p8_oha_init_init (const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) ; // ---------------------------------------------------------------------- @@ -207,9 +207,9 @@ p8_oha_init(const fapi::Target &i_target, uint32_t i_mode) fapi::ReturnCode rc; - - - + + + if ( i_mode == PM_CONFIG ) { FAPI_DBG("*************************************"); @@ -218,187 +218,187 @@ p8_oha_init(const fapi::Target &i_target, uint32_t i_mode) rc=p8_oha_init_config(i_target); if (rc) { - FAPI_ERR(" p8_oha_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - } else if ( i_mode == PM_INIT ) { + FAPI_ERR(" p8_oha_init_config failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } else if ( i_mode == PM_INIT ) { + - FAPI_DBG("*************************************"); FAPI_INF("MODE: INIT , Calling: p8_oha_init_init"); FAPI_DBG("*************************************"); - + // ****************************************************************** /// \todo should this values be attributes?? The get those attributes here //#ifndef ATTRIBUTES_AVAIL - - //Declare parms struct + + //Declare parms struct struct_i_oha_val_init_type i_oha_val_init; - + //Assign values to parms in struct // should come from MRWB i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us i_oha_val_init.LAD_ENTRY = 16; i_oha_val_init.LAD_EXIT = 17; - - + + //#else // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); //VENICE or SALERNO - + //#endif - + // ****************************************************************** - - - + + + rc=p8_oha_init_init(i_target, i_oha_val_init); - + if (rc) { - FAPI_ERR(" p8_oha_init_init failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - + FAPI_ERR(" p8_oha_init_init failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } else if ( i_mode == PM_RESET ) { FAPI_DBG("*************************************"); FAPI_INF("MODE: RESET"); FAPI_DBG("*************************************"); - - - - - //Declare parms struct - struct_i_oha_val_init_type i_oha_val_init; - + + + + + //Declare parms struct + struct_i_oha_val_init_type __attribute__((unused)) i_oha_val_init; // HACK + //Assign values to parms in struct // should come from MRWB i_oha_val_init.AISS_HANG_DETECT_TIMER_SEL = 9; // oha_mode_reg (11:14) - 0=1ms, 1=2ms, 3=4ms, ...9=512ms. others illegal i_oha_val_init.PPT_TIMER_SELECT = 3; // activity_sample_mode_reg (36:37) 0=0.25us, 1=0.5us, 2=1us, and 3=2us i_oha_val_init.LAD_ENTRY = 16; i_oha_val_init.LAD_EXIT = 17; - + // ****************************************************************** /// \todo should this values be attributes?? The get those attributes here - + #ifndef ATTRIBUTES_AVAIL - - + + #else // FAPI_ATTR_GET("IVRMS_ENABLED", i_target,(unit8_t) ivrms_enabled); //VENICE or SALERNO - + #endif - + // ****************************************************************** - - - - + + + + //FAPI_DBG("*************************************"); FAPI_INF("Calling: p8_oha_init_reset"); //FAPI_DBG("*************************************"); - rc = p8_oha_init_reset( i_target, i_mode); - + rc = p8_oha_init_reset( i_target, i_mode); + if (rc) { - FAPI_ERR(" p8_oha_init_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - + FAPI_ERR(" p8_oha_init_reset failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + } else { //FAPI_DBG("*************************************"); FAPI_ERR("Unknown mode passed to p8_oha_init. Mode %x ....\n", i_mode); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BAD_MODE); //FAPI_DBG("*************************************"); - }; - - - - return rc; - -} + }; + + + + return rc; + +} fapi::ReturnCode -p8_oha_init_config(const fapi::Target& i_target) +p8_oha_init_config(const fapi::Target& i_target) { fapi::ReturnCode rc; - + uint8_t attr_pm_aiss_timeout; uint32_t attr_pm_power_proxy_trace_timer; uint32_t attr_pm_ppt_timer_tick; uint32_t attr_pm_ppt_timer_match_value; - - + + // ****************************************************************** - // Get Attributes for OHA Timers Delay - // ****************************************************************** - // set defaults if not available + // Get Attributes for OHA Timers Delay + // ****************************************************************** + // set defaults if not available attr_pm_ppt_timer_tick = 2; // Default 2: 1us - - + + /// \todo PLAT attr ... not there yet - attr_pm_aiss_timeout = 5; // Default 5: 32ms - // rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + attr_pm_aiss_timeout = 5; // Default 5: 32ms + // rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } - // + // /// \todo PLAT attr ... not there yet attr_pm_power_proxy_trace_timer = 64000; // Default 1us,,, 32us...64ms - // rc = FAPI_ATTR_GET(ATTR_PM_POWER_PROXY_TRACE_TIMER, &i_target, attr_pm_power_proxy_trace_timer); + // rc = FAPI_ATTR_GET(ATTR_PM_POWER_PROXY_TRACE_TIMER, &i_target, attr_pm_power_proxy_trace_timer); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_POWER_PROXY_TRACE_TIMER with rc = 0x%x", (uint32_t)rc); return rc; } - - - + + + + // ****************************************************************** + // Calculate OHA timer settings // ****************************************************************** - // Calculate OHA timer settings - // ****************************************************************** //FAPI_DBG("*************************************"); FAPI_DBG("Calculate OHA timer settings"); - //FAPI_DBG("*************************************"); + //FAPI_DBG("*************************************"); //FAPI_DBG("*************************************"); FAPI_DBG("Calculate:"); FAPI_DBG(" ATTR_PM_PPT_TIMER_MATCH_VALUE"); FAPI_DBG(" ATTR_PM_PPT_TIMER_TICK"); FAPI_DBG("using:"); FAPI_DBG(" ATTR_PM_POWER_PROXY_TRACE_TIMER"); - //FAPI_DBG("**************************************************************************"); + //FAPI_DBG("**************************************************************************"); FAPI_DBG(" Set ATTR_PM_AISS_TIMEOUT to 5 (32ms)"); - //FAPI_DBG("**************************************************************************"); - - - - + //FAPI_DBG("**************************************************************************"); + + + + // - attr_pm_ppt_timer_match_value = attr_pm_power_proxy_trace_timer / 32 ; //time in us / 32us - - - - - + attr_pm_ppt_timer_match_value = attr_pm_power_proxy_trace_timer / 32 ; //time in us / 32us + + + + + FAPI_DBG("*************************************"); FAPI_DBG("attr_pm_aiss_timeout : %X", attr_pm_aiss_timeout); - FAPI_DBG("attr_pm_ppt_timer_match_value : %X", attr_pm_ppt_timer_match_value); + FAPI_DBG("attr_pm_ppt_timer_match_value : %X", attr_pm_ppt_timer_match_value); FAPI_DBG("*************************************"); - + + // ****************************************************************** + // Set Attributes for OHA timers // ****************************************************************** - // Set Attributes for OHA timers - // ****************************************************************** - - // rc = FAPI_ATTR_SET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + + // rc = FAPI_ATTR_SET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return; } - - rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); + + rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); + rc = FAPI_ATTR_SET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); return rc; } - - - + + + return rc; - + } //end CONFIG @@ -407,113 +407,113 @@ p8_oha_init_config(const fapi::Target& i_target) fapi::ReturnCode -p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) +p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_val_init) { fapi::ReturnCode rc; - + ecmdDataBufferBase data(64); ecmdDataBufferBase mask(64); - + std::vector<fapi::Target> l_chiplets; std::vector<Target>::iterator itr; - - + + // Variables //TODO RTC: 68461 - refresh procedures uint32_t c = 0 ; uint32_t l_rc; - + uint8_t attr_pm_aiss_timeout; uint32_t attr_pm_ppt_timer_tick; uint32_t attr_pm_ppt_timer_match_value; - + FAPI_INF(""); //FAPI_DBG("********* ******************* *********"); FAPI_INF("Executing ....p8_oha_init"); //FAPI_DBG("********* ******************* *********"); FAPI_INF(""); - - - - + + + + rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); - - - - + + + + //FAPI_DBG("***********************************************"); FAPI_INF(" Welcome to p8_oha_init INIT-mode "); //FAPI_DBG("***********************************************"); - - - + + + // ****************************************************************** - // Get Attributes for OHA Timers Delay - // ****************************************************************** - #ifndef ATTRIBUTES_AVAIL + // Get Attributes for OHA Timers Delay + // ****************************************************************** + #ifndef ATTRIBUTES_AVAIL // ****************************************************************** - // set defaults if not available + // set defaults if not available attr_pm_ppt_timer_tick = 2; // Default 2: 1us attr_pm_ppt_timer_match_value = 0x7FF; // Default 0x7FF: 64ms - attr_pm_aiss_timeout = 5; // Default 5: 32ms - #else + attr_pm_aiss_timeout = 5; // Default 5: 32ms + #else /// \todo PLAT attr ... not there yet - //rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); - //if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); + //rc = FAPI_ATTR_GET(ATTR_PM_AISS_TIMEOUT, &i_target, attr_pm_aiss_timeout); + //if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_AISS_TIMEOUT with rc = 0x%x", (uint32_t)rc); return rc; } + rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_TICK, &i_target, attr_pm_ppt_timer_tick); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_TICK with rc = 0x%x", (uint32_t)rc); return rc; } - rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); + rc = FAPI_ATTR_GET(ATTR_PM_PPT_TIMER_MATCH_VALUE, &i_target, attr_pm_ppt_timer_match_value); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_PPT_TIMER_MATCH_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } - #endif - - - + #endif + + + // ****************************************************************** // initialize all oha_reg with scan-zero values upfront // ****************************************************************** - - - + + + for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ - - - FAPI_DBG("Content Loop Variable C : %d ", c); - - - + + + // HACK - FAPI_DBG("Content Loop Variable C : %d ", c); + + + // ****************************************************************** // AISS hang timer setup // ****************************************************************** // ****************************************************************** - + // - set aiss_timeout to max time // ****************************************************************** //FAPI_DBG("**********************************************"); FAPI_INF(" Setup aiss hang time in oha_mode_reg 1002000D"); //FAPI_DBG("**********************************************"); - + // Read register content rc = fapiGetScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); if (rc) {FAPI_ERR("fapiGetScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - + FAPI_DBG ("Content of EX_OHA_MODE_REG_0x1002000D : %016llX", data.getDoubleWord(0)); - - - + + + //data.flushTo0(); - l_rc = data.insertFromRight(attr_pm_aiss_timeout ,11,4); + l_rc = data.insertFromRight(attr_pm_aiss_timeout ,11,4); if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - + rc = fapiPutScom( (*itr), EX_OHA_MODE_REG_RWx1002000D , data ); if (rc) { - FAPI_ERR("fapiPutScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - - - + FAPI_ERR("fapiPutScom(EX_OHA_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + + + // ****************************************************************** // Low Activity Detect (LAD) setup // ****************************************************************** @@ -525,40 +525,40 @@ p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_ //FAPI_DBG("**********************************************************************************************"); FAPI_INF(" Setup Low Activity Detect (LAD) in oha_low_activity_detect_mode_reg 10020003, but NOT ENABLED"); //FAPI_DBG("**********************************************************************************************"); - + // Read register content //if (VERBOSE) { rc = fapiGetScom( (*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); if (rc) { FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003) failed. With rc = 0x%x", (uint32_t)rc); return rc; } FAPI_DBG(" Pre write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); //} - + // - l_rc = data.setByte(0, i_oha_val_init.LAD_ENTRY); // 16 + l_rc = data.setByte(0, i_oha_val_init.LAD_ENTRY); // 16 l_rc |= data.setByte(1, i_oha_val_init.LAD_EXIT); // 17 - l_rc |= data.shiftRight(1); // LAD entry/exit starts at bit 1 + l_rc |= data.shiftRight(1); // LAD entry/exit starts at bit 1 l_rc |= data.clearBit(0); if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } //FAPI_DBG(" !!!!!!!!!!!!!!!!!!!!!!returncode : %d", rc); - - - - - + + + + + rc = fapiPutScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 , data ); if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + FAPI_ERR("fapiGetScom(EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - + // if debug mode read back //if (VERBOSE) { // rc = fapiGetScom((*itr), EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003, data); if (rc) return rc; // FAPI_DBG(" Post write content of EX_OHA_LOW_ACTIVITY_DETECT_MODE_REG_RWx10020003 : %016llX", data.getDoubleWord(0)); //} FAPI_INF ("Done LAD setup. LAD Disabled " ); - - - + + + // ****************************************************************** // Power Proxy Trace (PPT) setup // ****************************************************************** @@ -569,32 +569,32 @@ p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_ //FAPI_DBG("********************************************************************************"); FAPI_INF(" Setup Power Proxy Trace (PPT) in oha_activity_sample_mode_reg 10020000"); //FAPI_DBG("********************************************************************************"); - - // Read register content + + // Read register content rc = fapiGetScom( (*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } FAPI_DBG(" Pre write content of EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 : %016llX", data.getDoubleWord(0)); - - - // set ppt_int_timer_select to longest interval "11" = 2us + + + // set ppt_int_timer_select to longest interval "11" = 2us //l_rc = data.setBit(36); - //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } + //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } //l_rc = data.setBit(37); - //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } - - l_rc = data.insertFromRight(attr_pm_ppt_timer_match_value ,24,11); - l_rc |= data.insertFromRight(attr_pm_ppt_timer_tick ,36,2); + //if (l_rc) { FAPI_ERR("Bit operation failed."); FAPI_SET_HWP_ERROR(rc, RC_PROC_OHA_CODE_BITOP_FAILED); } + + l_rc = data.insertFromRight(attr_pm_ppt_timer_match_value ,24,11); + l_rc |= data.insertFromRight(attr_pm_ppt_timer_tick ,36,2); if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - - - + + + rc = fapiPutScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000 , data ); if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + FAPI_ERR("fapiGetScom(EX_OHA_ACTIVITY_SAMPLE_MODE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - + // if debug mode read back //if (VERBOSE) { rc = fapiGetScom((*itr), EX_OHA_ACTIVITY_SAMPLE_MODE_REG_RWx10020000, data); if (rc) return rc; @@ -602,11 +602,11 @@ p8_oha_init_init(const fapi::Target& i_target, struct_i_oha_val_init_type i_oha_ //} FAPI_INF ("Done PPT timer setup." ); } - - - + + + return rc; - + } //end INIT @@ -631,7 +631,7 @@ p8_oha_init_reset(const Target &i_target, uint32_t i_mode) // Variables //TODO RTC: 68461 - refresh procedures uint32_t c = 0 ; uint32_t l_rc; - + FAPI_DBG(""); //FAPI_DBG("********* ******************* *********"); FAPI_INF("Executing p8_oha_init..."); @@ -647,10 +647,10 @@ p8_oha_init_reset(const Target &i_target, uint32_t i_mode) rc = fapiGetChildChiplets (i_target, TARGET_TYPE_EX_CHIPLET, l_chiplets); if (rc) return rc; FAPI_DBG(" chiplet vector size => %u", l_chiplets.size()); - - + + //FAPI_DBG("***********************************************"); FAPI_INF(" Welcome to p8_oha_init_reset "); @@ -660,50 +660,50 @@ p8_oha_init_reset(const Target &i_target, uint32_t i_mode) for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ - FAPI_DBG("Content Loop Variable C : %d ", c); + // HACK - FAPI_DBG("Content Loop Variable C : %d ", c); + + + + - - - - //FAPI_DBG("*************************************"); FAPI_INF("Reset AISS "); FAPI_INF("Write to register OHA_ARCH_IDLE_STATE_REG "); //FAPI_DBG("*************************************"); - - - - rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); + + + + rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - FAPI_DBG(" Pre write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); - + FAPI_DBG(" Pre write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); + l_rc = data.setBit(9); //reset_idle_state_sequencer_in ... reset pulse gets generated. Not unsetting required if (l_rc) { FAPI_ERR("Bit operation failed. With rc = 0x%x", (uint32_t)l_rc); rc.setEcmdError(l_rc); return rc; } - + rc = fapiPutScom((*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 , data ); if (rc) { - FAPI_ERR("fapiPutScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + FAPI_ERR("fapiPutScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; } - + // if debug mode read back //if (VERBOSE) { rc = fapiGetScom( (*itr), EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011, data); if (rc) return rc; - FAPI_DBG(" Post write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); + FAPI_DBG(" Post write content of EX_OHA_ARCH_IDLE_STATE_REG_RWx10020011 : %016llX", data.getDoubleWord(0) ); //} if (rc) { - FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; - } - - + FAPI_ERR("fapiGetScom(EX_OHA_ARCH_IDLE_STATE_REG) failed. With rc = 0x%x", (uint32_t)rc); return rc; + } + + } - - + + FAPI_INF(""); FAPI_INF("Executing proc_OHA_init ....\n"); @@ -721,4 +721,4 @@ for (itr = l_chiplets.begin(); itr != l_chiplets.end(); itr++){ } //end extern C - + diff --git a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C index 62432c68a..0d52fd94d 100755 --- a/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C +++ b/src/usr/hwpf/hwp/occ/occ_procedures/p8_pmc_init.C @@ -23,7 +23,7 @@ /* begin_generated_IBM_copyright_prolog */ /* */ /* This is an automatically generated copyright prolog. */ -/* After initializing, DO NOT MODIFY OR MOVE */ +/* After initializing, DO NOT MODIFY OR MOVE */ /* --------------------------------------------------------------- */ /* IBM Confidential */ /* */ @@ -47,15 +47,15 @@ // *! OWNER NAME: Joe Procwriter Email: asmartpersion@xx.ibm.com // *! // *! General Description: -// *! +// *! // *! The purpose of this procedure is to ...... -// *! +// *! // *! High-level procedure flow: // *! o Do thing 1 // *! o Do thing 2 // *! o Do thing 3 // *! o Check if all went well -// *! o If so celebrate +// *! o If so celebrate // *! o Else write logs, set bad return code // *! // *! Procedure Prereq: @@ -63,7 +63,7 @@ // *! //------------------------------------------------------------------------------ - + // ---------------------------------------------------------------------- // Includes // ---------------------------------------------------------------------- @@ -71,7 +71,7 @@ #include "p8_pm.H" #include "p8_pmc_init.H" -//---------------------------------------------------------------------- +//---------------------------------------------------------------------- // eCMD Includes //---------------------------------------------------------------------- // #include <ecmdClientCapi.H> @@ -91,8 +91,8 @@ //#ifdef FAPIECMD extern "C" { - // #endif - + // #endif + using namespace fapi; @@ -112,45 +112,45 @@ using namespace fapi; // fapi::ReturnCode -// pmc_create_spivid_settings(const Target& l_pTarget) +// pmc_create_spivid_settings(const Target& l_pTarget) // { // fapi::ReturnCode rc; - + // return rc ; -// } +// } //------------------------------------------------------------------------- - /// Locally computed variables to put into the feature attributes -//------------------------------------------------------------------------- + /// Locally computed variables to put into the feature attributes +//------------------------------------------------------------------------- fapi::ReturnCode -pmc_config_spivid_settings(const Target& l_pTarget) +pmc_config_spivid_settings(const Target& l_pTarget) { fapi::ReturnCode rc; - + uint32_t attr_pm_spivid_clock_divider; uint32_t attr_pm_spivid_frequency = 10; uint32_t attr_proc_nest_frequency = 2400; FAPI_INF("entering the config function"); - + rc = FAPI_ATTR_GET(ATTR_FREQ_PB, NULL, attr_proc_nest_frequency); if (rc) return rc; //TODO RTC: 68461 - refresh procedures - hacked target in the line below. - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FREQUENCY, &l_pTarget, attr_pm_spivid_frequency); if (rc) return rc; - - + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FREQUENCY, &l_pTarget, attr_pm_spivid_frequency); if (rc) return rc; + + // calculation of clock divider - attr_pm_spivid_clock_divider = (attr_proc_nest_frequency/(attr_pm_spivid_frequency*8)-1 ); + attr_pm_spivid_clock_divider = (attr_proc_nest_frequency/(attr_pm_spivid_frequency*8)-1 ); rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); if (rc) return rc; - + FAPI_INF("exiting the config function"); return rc ; } @@ -158,13 +158,13 @@ pmc_config_spivid_settings(const Target& l_pTarget) fapi::ReturnCode -pmc_reset_function(const Target& i_target) +pmc_reset_function(const Target& i_target) { fapi::ReturnCode rc; ecmdDataBufferBase data(64); // ecmdDataBufferBase mask(64); uint32_t e_rc = 0; - uint32_t count = 0 ; + uint32_t count = 0 ; bool is_stopped ; bool is_spivid_stopped ; bool is_not_ongoing ; @@ -173,7 +173,7 @@ pmc_reset_function(const Target& i_target) bool is_pstate_error_stopped ; bool is_intchp_error_stopped; bool is_MasterPMC; - bool enable_fw_pstate_mode; + bool __attribute__((unused)) enable_fw_pstate_mode; // HACK //////////////////////////////////////////////////////////////////////////// @@ -234,7 +234,7 @@ pmc_reset_function(const Target& i_target) //////////////////////////////////////////////////////////////////////////// -// 3. cRQ_TD_DisableMPS: Write PMC_MODE_REG to halt things Which register bits should be written with what to make this below halts ? +// 3. cRQ_TD_DisableMPS: Write PMC_MODE_REG to halt things Which register bits should be written with what to make this below halts ? // halt_pstate_master_fsm<-1 <-1 indicates to write the bit with the value 1 // halt_idle_state_master_fsm<-1 <-1 indicates to write the bit with the value 1 // Note: Other bits are left as setup so the configuration remains as things halt, and new @@ -270,8 +270,8 @@ pmc_reset_function(const Target& i_target) //////////////////////////////////////////////////////////////////////////// // 4. if enable_interchip_interface==1 // cRQ_TD_HaltInterchip_On: Write PMC_INTCHP_COMMAND_REG.interchip_halt_msg_fsm<-1 Should we write the command register here ? That's why I specified the command register, PMC_INTCHP_COMMAND_REG. -// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG -// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG +// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG +// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG // is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error // is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? // is_stopped = (interchip_ga_ongoing == 0) || is_pstate_error_stopped || is_intchp_error_stopped @@ -291,10 +291,10 @@ pmc_reset_function(const Target& i_target) if (rc) { FAPI_ERR("fapiGetScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); return rc; } - + e_rc = data.setBit(01); if(e_rc){rc.setEcmdError(e_rc); return rc; } - - + + rc = fapiPutScom(i_target, PMC_INTCHP_COMMAND_REG_0x00062014 , data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_INTCHP_COMMAND_REG_0x00062014) failed."); return rc; @@ -307,19 +307,19 @@ pmc_reset_function(const Target& i_target) for (count = 0 , is_stopped = 0 ; count <= 256 && is_stopped == 0; count++) { -// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG +// cRQ_TD_HaltInterchip_Wait1: Read PMC_STATUS_REG // is_pstate_error_stopped = pstate_processing_is_suspended || gpsa_bdcst_error || gpsa_vchg_error || gpsa_timeout_error || pstate_interchip_error rc = fapiGetScom(i_target, PMC_STATUS_REG_0x00062009 , data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); return rc; } - + is_pstate_error_stopped = data.isBitSet(0) | data.isBitSet(1) | data.isBitSet(5)| data.isBitSet(6) | data.isBitSet(11) ; - -// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG + +// cRQ_TD_HaltInterchip_Wait2: Read PMC_INTCHP_STATUS_REG // is_intchp_error_stopped = interchip_ecc_ue_err || interchip_fsm_err || (is_MasterPMC && interchip_slave_error_code != 0) is_MasterPMC where is this bit ? rc = fapiGetScom(i_target, PMC_INTCHP_STATUS_REG_0x00062013 , data ); @@ -341,7 +341,7 @@ pmc_reset_function(const Target& i_target) FAPI_ERR("Timed out in polling interchip ongoing ... "); FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); return rc; - + } @@ -364,7 +364,7 @@ pmc_reset_function(const Target& i_target) } // end if - + //////////////////////////////////////////////////////////////////////////// @@ -385,30 +385,30 @@ pmc_reset_function(const Target& i_target) if (rc) { FAPI_ERR("fapiGetScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); return rc; } - + e_rc = data.setBit(15); if(e_rc){rc.setEcmdError(e_rc); return rc; } - + rc = fapiPutScom(i_target, PMC_SPIV_COMMAND_REG_0x00062047 , data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_COMMAND_REG_0x00062047) failed."); return rc; } - - + + // cRQ_TD_Spivid_HaltWait: Read PMC_SPIV_STATUS_REG // if spivid_ongoing && !is_spivid_error Then -->cRQ_TD_Spivid_HaltWait (Wait limit is parm TD_Spivid_HaltWait_max=100) for (count = 0 , is_spivid_stopped=0; count <= 100 && is_spivid_stopped==0 ; count++) - { + { rc = fapiGetScom(i_target, PMC_SPIV_STATUS_REG_0x00062046 , data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_SPIV_STATUS_REG_0x00062046) failed."); return rc; } - is_spivid_stopped = data.isBitClear(0) | data.isBitSet(1) | data.isBitSet(2) | data.isBitSet(3) | data.isBitSet(4) ; - - } // end for + is_spivid_stopped = data.isBitClear(0) | data.isBitSet(1) | data.isBitSet(2) | data.isBitSet(3) | data.isBitSet(4) ; + + } // end for @@ -417,7 +417,7 @@ pmc_reset_function(const Target& i_target) FAPI_ERR("Timed out in polling spiv ongoing ... "); FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMCINIT_TIMEOUT); return rc; - + } } // end if @@ -425,7 +425,7 @@ pmc_reset_function(const Target& i_target) //////////////////////////////////////////////////////////////////////////// // 6. cRQ_TD_MPS_HaltWait: Read PMC_STATUS_REG -// +// // if (fw_pstate_mode) // is_not_ongoing = (enable_pstate_voltage_changes==0 || volt_chg_ongoing==0) && (brd_cst_ongoing == 0) // else @@ -449,12 +449,12 @@ pmc_reset_function(const Target& i_target) FAPI_ERR("fapiGetScom(PMC_STATUS_REG_0x00062009) failed."); return rc; } - + if (fw_pstate_mode) { - + is_not_ongoing = (enable_pstate_voltage_changes==0 || data.isBitClear(8)) && data.isBitClear(9); - + } else { @@ -493,24 +493,24 @@ p8_pmc_init(const Target& i_target, uint32_t mode) FAPI_INF(""); FAPI_INF("Executing p8_pmc_init ...."); - + // ------------------------------------------------ // CONFIG mode // ------------------------------------------------ - if (mode == PM_CONFIG) + if (mode == PM_CONFIG) { - + FAPI_INF("PMC configuration..."); rc=pmc_config_spivid_settings(i_target); - - } - + + } + // ------------------------------------------------ // INIT mode // ------------------------------------------------ else if (mode == PM_INIT) { - + uint8_t attr_pm_spivid_frame_size; uint8_t attr_pm_spivid_in_delay_frame1; uint8_t attr_pm_spivid_in_delay_frame2; @@ -526,109 +526,109 @@ p8_pmc_init(const Target& i_target, uint32_t mode) uint8_t attr_pm_spivid_crc_check_enable; uint8_t attr_pm_spivid_majority_vote_enable; uint8_t attr_pm_spivid_max_retries; - uint8_t attr_pm_spivid_crc_polynomial_enables; + uint8_t attr_pm_spivid_crc_polynomial_enables; - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &i_target, attr_pm_spivid_frame_size); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &i_target, attr_pm_spivid_frame_size); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_frame_size = 0x%x", attr_pm_spivid_frame_size );} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &i_target, attr_pm_spivid_in_delay_frame1); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &i_target, attr_pm_spivid_in_delay_frame1); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame1 = 0x%x", attr_pm_spivid_in_delay_frame1);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &i_target, attr_pm_spivid_in_delay_frame2); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &i_target, attr_pm_spivid_in_delay_frame2); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame2 = 0x%x", attr_pm_spivid_in_delay_frame2);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &i_target, attr_pm_spivid_clock_polarity); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &i_target, attr_pm_spivid_clock_polarity); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_polarity = 0x%x", attr_pm_spivid_clock_polarity);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &i_target, attr_pm_spivid_clock_phase); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &i_target, attr_pm_spivid_clock_phase); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_phase = 0x%x", attr_pm_spivid_clock_phase);} - //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &i_target, attr_pm_spivid_interframe_delay_write_status); + //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &i_target, attr_pm_spivid_interframe_delay_write_status); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status = 0x%x", attr_pm_spivid_interframe_delay_write_status);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &i_target, attr_pm_spivid_interframe_delay_write_status_value); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &i_target, attr_pm_spivid_interframe_delay_write_status_value); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status_value = 0x%x", attr_pm_spivid_interframe_delay_write_status_value);} - //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &i_target, attr_pm_spivid_inter_retry_delay_value); + //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &i_target, attr_pm_spivid_inter_retry_delay_value); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay_value = 0x%x", attr_pm_spivid_inter_retry_delay_value);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &i_target, attr_pm_spivid_inter_retry_delay); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &i_target, attr_pm_spivid_inter_retry_delay); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay = 0x%x", attr_pm_spivid_inter_retry_delay);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &i_target, attr_pm_spivid_crc_gen_enable); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &i_target, attr_pm_spivid_crc_gen_enable); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_gen_enable = 0x%x", attr_pm_spivid_crc_gen_enable);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &i_target, attr_pm_spivid_crc_check_enable); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &i_target, attr_pm_spivid_crc_check_enable); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_check_enable = 0x%x", attr_pm_spivid_crc_check_enable);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &i_target, attr_pm_spivid_majority_vote_enable); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &i_target, attr_pm_spivid_majority_vote_enable); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_majority_vote_enable = 0x%x", attr_pm_spivid_majority_vote_enable);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &i_target, attr_pm_spivid_max_retries); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &i_target, attr_pm_spivid_max_retries); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_max_retries = 0x%x", attr_pm_spivid_max_retries);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &i_target, attr_pm_spivid_crc_polynomial_enables); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &i_target, attr_pm_spivid_crc_polynomial_enables); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_polynomial_enables = 0x%x", attr_pm_spivid_crc_polynomial_enables);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &i_target, attr_pm_spivid_clock_divider); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &i_target, attr_pm_spivid_clock_divider); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_divider = 0x%x", attr_pm_spivid_clock_divider);} - //---------------------------------------------------------- - rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &i_target, attr_pm_spivid_port_enable); + //---------------------------------------------------------- + rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &i_target, attr_pm_spivid_port_enable); if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } else { FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable = 0x%x", attr_pm_spivid_port_enable);} - //---------------------------------------------------------- + //---------------------------------------------------------- @@ -641,29 +641,29 @@ p8_pmc_init(const Target& i_target, uint32_t mode) // rc=pmc_create_spivid_settings(i_target); above lines replaced this functions - + FAPI_INF("PMC initialization..."); - uint8_t o2s_frame_size = attr_pm_spivid_frame_size; - uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; - uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; - uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; - uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; - uint8_t o2s_port_enable = attr_pm_spivid_port_enable; - uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; - uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; - uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; - uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; - uint8_t o2s_max_retries = attr_pm_spivid_max_retries; - uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; - uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; - //spivid_freq = attr_pm_spivid_frequency; - uint8_t o2s_in_count2 = 0 ; - uint8_t o2s_out_count2 = 0 ; - uint8_t o2s_bridge_enable = 0x1 ; - uint8_t o2s_nr_of_frames = 1 ; //(uint8_t) args.front(); args.pop_front(); // for pmc o2s operations it is usually 1 - uint8_t o2s_in_count1 = 0 ; - uint8_t o2s_out_count1 = 32 ; + uint8_t o2s_frame_size = attr_pm_spivid_frame_size; + uint8_t o2s_in_delay1 = attr_pm_spivid_in_delay_frame1; + uint8_t o2s_in_delay2 = attr_pm_spivid_in_delay_frame2; + uint8_t o2s_clk_pol = attr_pm_spivid_clock_polarity; + uint8_t o2s_clk_pha = attr_pm_spivid_clock_phase; + uint8_t o2s_port_enable = attr_pm_spivid_port_enable; + uint32_t o2s_inter_frame_delay = attr_pm_spivid_interframe_delay_write_status_value; + uint8_t o2s_crc_gen_en = attr_pm_spivid_crc_gen_enable; + uint8_t o2s_crc_check_en = attr_pm_spivid_crc_check_enable; + uint8_t o2s_majority_vote_en = attr_pm_spivid_majority_vote_enable; + uint8_t o2s_max_retries = attr_pm_spivid_max_retries; + uint8_t o2s_crc_polynomial_enables = attr_pm_spivid_crc_polynomial_enables; + uint16_t o2s_clk_divider = attr_pm_spivid_clock_divider; + //spivid_freq = attr_pm_spivid_frequency; + uint8_t o2s_in_count2 = 0 ; + uint8_t o2s_out_count2 = 0 ; + uint8_t o2s_bridge_enable = 0x1 ; + uint8_t o2s_nr_of_frames = 1 ; //(uint8_t) args.front(); args.pop_front(); // for pmc o2s operations it is usually 1 + uint8_t o2s_in_count1 = 0 ; + uint8_t o2s_out_count1 = 32 ; uint32_t dummy = 0 ; @@ -671,36 +671,36 @@ p8_pmc_init(const Target& i_target, uint32_t mode) - - + + // Here to bypass feature attribute passing until these as moved into proc.pm.pmc.scom.initfile - -// o2s_frame_size = 0x10 ; -// o2s_clk_pol = 0; -// o2s_clk_pha = 0; -// o2s_clk_divider= 0x1D; + +// o2s_frame_size = 0x10 ; +// o2s_clk_pol = 0; +// o2s_clk_pha = 0; +// o2s_clk_divider= 0x1D; // o2s_inter_frame_delay = 0x0; // nest_freq = 600; // spivid_freq = 10; -// o2s_in_count1=0; -// o2s_out_count1=0; -// o2s_in_delay1=0; -// o2s_in_count2=0; -// o2s_out_count2=0; -// o2s_in_delay2=0; +// o2s_in_count1=0; +// o2s_out_count1=0; +// o2s_in_delay1=0; +// o2s_in_count2=0; +// o2s_out_count2=0; +// o2s_in_delay2=0; // o2s_wdata = 0x11223344; - - + + // ****************************************************************** - // - set PMC_o2s_CTRL_REG0A (24b) + // - set PMC_o2s_CTRL_REG0A (24b) // ****************************************************************** rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0A_0x00062050, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0A) failed."); return rc; } - + e_rc = data.insertFromRight( o2s_frame_size ,0,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} e_rc = data.insertFromRight( o2s_in_count1 ,6,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} e_rc = data.insertFromRight( o2s_out_count1 ,12,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} @@ -710,7 +710,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" PMC O2S CTRL_REG_0A Configuration "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); e_rc = data.extractToRight(&dummy,0,6); FAPI_INF(" frame size => %x ", dummy); e_rc |= data.extractToRight(&dummy,6,6); @@ -728,24 +728,24 @@ p8_pmc_init(const Target& i_target, uint32_t mode) if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG0A_0x00062050) failed."); return rc; } - + // ****************************************************************** - // - set PMC_O2S_CTRL_REG0B (24b) + // - set PMC_O2S_CTRL_REG0B (24b) // ****************************************************************** rc = fapiGetScom(i_target, PMC_O2S_CTRL_REG0B_0x00062051, data ); if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG0B) failed."); return rc; } - + e_rc = data.insertFromRight(o2s_out_count2,00,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} e_rc = data.insertFromRight(o2s_in_delay2 ,06,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} e_rc = data.insertFromRight(o2s_in_count2 ,12,6); if(e_rc){rc.setEcmdError(e_rc); return rc;} // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" PMC O2S CTRL_REG_0B Configuration "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" o2s_out_count2 => %d ", o2s_out_count2); FAPI_INF(" o2s_in_delay2 => %d ", o2s_in_delay2 ); FAPI_INF(" o2s_in_count2 => %d ", o2s_in_count2 ); @@ -766,7 +766,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) if (rc) { FAPI_ERR("fapiGetScom(PMC_O2S_CTRL_REG1) failed."); return rc; } - + o2s_nr_of_frames--; e_rc = data.insertFromRight( o2s_bridge_enable ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} e_rc = data.insertFromRight( o2s_clk_pol ,2,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} @@ -775,11 +775,11 @@ p8_pmc_init(const Target& i_target, uint32_t mode) e_rc = data.insertFromRight( o2s_nr_of_frames ,17,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} e_rc = data.insertFromRight( o2s_port_enable ,18,3); if(e_rc){rc.setEcmdError(e_rc); return rc;} o2s_nr_of_frames++; - + // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" PMC O2S CTRL_REG_1 Configuration "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" o2s_bridge_enable => %d ", o2s_bridge_enable ); FAPI_INF(" o2s_clk_pol => %d ", o2s_clk_pol ); FAPI_INF(" o2s_clk_pha => %d ", o2s_clk_pha ); @@ -794,7 +794,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG1_0x00062052) failed."); return rc; } - + // ****************************************************************** // - set PMC_O2S_CTRL_REG2 @@ -810,7 +810,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" PMC O2S CTRL_REG_2 Configuration "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" o2s_inter_frame_delay => %d ", o2s_inter_frame_delay ); FAPI_INF(" " ); FAPI_INF(" " ); @@ -822,7 +822,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_CTRL_REG2_0x00062053) failed."); return rc; } - + // ****************************************************************** // - set PMC_O2S_CTRL_REG4 // ****************************************************************** @@ -840,7 +840,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" PMC O2S CTRL_REG_4 Configuration "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" o2s_crc_gen_en => %d ", o2s_crc_gen_en ); FAPI_INF(" o2s_crc_check_en => %d ", o2s_crc_check_en ); FAPI_INF(" o2s_majority_vote_en => %d ", o2s_majority_vote_en ); @@ -874,7 +874,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" PMC O2S CTRL_REG_3Configuration "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" spiv_crc_gen_en => %d ", o2s_crc_gen_en ); FAPI_INF(" spiv_crc_check_en => %d ", o2s_crc_check_en ); FAPI_INF(" spiv_majority_vote_en => %d ", o2s_majority_vote_en ); @@ -889,62 +889,62 @@ p8_pmc_init(const Target& i_target, uint32_t mode) if (rc) { FAPI_ERR("fapiPutScom(PMC_SPIV_CTRL_REG4_0x00062045) failed."); return rc; } - - + + // ****************************************************************** // - write PMC_O2S_command_reg to clear any latent errors // ****************************************************************** e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.insertFromRight(one ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // halt retries - e_rc = data.insertFromRight(one ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // reset sticky errors + e_rc = data.insertFromRight(one ,0,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // halt retries + e_rc = data.insertFromRight(one ,1,1); if(e_rc){rc.setEcmdError(e_rc); return rc;} // reset sticky errors // FAPI_INF(" -----------------------------------------------------"); FAPI_INF(" clearing errors "); - // FAPI_INF(" -----------------------------------------------------"); + // FAPI_INF(" -----------------------------------------------------"); rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG_0x00062057) failed."); return rc; } - + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - + rc = fapiPutScom(i_target, PMC_O2S_COMMAND_REG_0x00062057, data ); if (rc) { FAPI_ERR("fapiPutScom(PMC_O2S_COMMAND_REG_0x00062057) failed."); return rc; } FAPI_INF ("I m done with the init " ); - + } - + /// ------------------------------- /// Reset: perform reset of PMC - else if (mode == PM_RESET) + else if (mode == PM_RESET) { FAPI_INF("PMC reset..."); - + // Reset PMC. However, the bit used means the entire PMC must be reconfigured! - + e_rc = data.flushTo0(); if(e_rc){rc.setEcmdError(e_rc); return rc;} - e_rc = data.setBit(12); if(e_rc){rc.setEcmdError(e_rc); return rc; } // RESET_ALL_PMC_REGISTERS - - rc=fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data); if(rc) return rc; + e_rc = data.setBit(12); if(e_rc){rc.setEcmdError(e_rc); return rc; } // RESET_ALL_PMC_REGISTERS + + rc=fapiPutScom(i_target, PMC_MODE_REG_0x00062000 , data); if(rc) return rc; // This function is not yet verified rc=pmc_reset_function(i_target); - - } - + } + + /// ------------------------------- /// Unsupported Mode - + else { FAPI_ERR("Unknown mode passed to p8_pmc_init. Mode %x ", mode); uint32_t & MODE = mode; - FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); + FAPI_SET_HWP_ERROR(rc, RC_PROCPM_PMC_CODE_BAD_MODE); } - + return rc; } @@ -953,7 +953,7 @@ p8_pmc_init(const Target& i_target, uint32_t mode) //#ifdef FAPIECMD } //end extern C -// #endif +// #endif @@ -986,15 +986,15 @@ p8_pmc_init(const Target& i_target, uint32_t mode) CONST_UINT64_T( PMC_SPIV_COMMAND_REG_0x00072047 , ULL(0x00072047) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 ,ULL(0x00062051) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 ,ULL(0x00062052) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 ,ULL(0x00062053) ); - CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 ,ULL(0x00062055) ); - CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 ,ULL(0x00062056) ); - CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 ,ULL(0x00062057) ); - CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 ,ULL(0x00062058) ); - CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 ,ULL(0x00062059) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG0A_0x00062050 , ULL(0x00062050) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG0B_0x00062051 ,ULL(0x00062051) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG1_0x00062052 ,ULL(0x00062052) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG2_0x00062053 ,ULL(0x00062053) ); + CONST_UINT64_T( PMC_O2S_CTRL_REG4_0x00062055 ,ULL(0x00062055) ); + CONST_UINT64_T( PMC_O2S_STATUS_REG_0x00062056 ,ULL(0x00062056) ); + CONST_UINT64_T( PMC_O2S_COMMAND_REG_0x00062057 ,ULL(0x00062057) ); + CONST_UINT64_T( PMC_O2S_WDATA_REG_0x00062058 ,ULL(0x00062058) ); + CONST_UINT64_T( PMC_O2S_RDATA_REG_0x00062059 ,ULL(0x00062059) ); // OCI Space Addresses CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); @@ -1085,7 +1085,7 @@ CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); // uint8_t attr_pm_spivid_crc_check_enable_set = 1 ; // uint8_t attr_pm_spivid_majority_vote_enable_set = 1; // uint8_t attr_pm_spivid_max_retries_set = 5 ; -// uint8_t attr_pm_spivid_crc_polynomial_enables_set = 0xD5; +// uint8_t attr_pm_spivid_crc_polynomial_enables_set = 0xD5; // // uint32_t attr_pm_spivid_frequency_set = 20; // // uint32_t attr_p8_nest_frequency_set = 3000; @@ -1093,76 +1093,76 @@ CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size_set); +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size_set); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } - - -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1_set); + + +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } // // rc = FAPI_ATTR_SET(ATTR_FREQ_PB, &l_pTarget, attr_p8_nest_frequency_set); if (rc) return rc; // // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_FREQUENCY, &l_pTarget, attr_pm_spivid_frequency_set); if (rc) return rc; - -// //---------------------------------------------------------- -// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider_set); + +// //---------------------------------------------------------- +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider_set); // // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } -// //---------------------------------------------------------- -// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable_set); +// //---------------------------------------------------------- +// // rc = FAPI_ATTR_SET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable_set); // // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } @@ -1174,38 +1174,38 @@ CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); - - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_STEPSIZE, &l_pTarget, attr_pm_pstate_stepsize_set); + + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_STEPSIZE, &l_pTarget, attr_pm_pstate_stepsize_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_STEPSIZE with rc = 0x%x", (uint32_t)rc); break; } - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE, &l_pTarget, attr_pm_external_vrm_stepdelay_range_set); + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE, &l_pTarget, attr_pm_external_vrm_stepdelay_range_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_EXTERNAL_VRM_STEPDELAY_RANGE with rc = 0x%x", (uint32_t)rc); break; } - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE, &l_pTarget, attr_pm_external_vrm_stepdelay_value_set); + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE, &l_pTarget, attr_pm_external_vrm_stepdelay_value_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_EXTERNAL_VRM_STEPDELAY_VALUE with rc = 0x%x", (uint32_t)rc); break; } - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PMC_HANGPULSE_DIVIDER, &l_pTarget, attr_pm_pmc_hangpulse_divider_set); + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PMC_HANGPULSE_DIVIDER, &l_pTarget, attr_pm_pmc_hangpulse_divider_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PMC_HANGPULSE_DIVIDER with rc = 0x%x", (uint32_t)rc); break; } - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PVSAFE_PSTATE, &l_pTarget, attr_pm_pvsafe_pstate_set); + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PVSAFE_PSTATE, &l_pTarget, attr_pm_pvsafe_pstate_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PVSAFE_PSTATE with rc = 0x%x", (uint32_t)rc); break; } - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, &l_pTarget, attr_pm_pstate_undervolting_minimum_set); + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM, &l_pTarget, attr_pm_pstate_undervolting_minimum_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MINIMUM with rc = 0x%x", (uint32_t)rc); break; } - /// //---------------------------------------------------------- - /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, &l_pTarget, attr_pm_pstate_undervolting_maximum_set); + /// //---------------------------------------------------------- + /// rc = FAPI_ATTR_SET(ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM, &l_pTarget, attr_pm_pstate_undervolting_maximum_set); /// if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_PSTATE_UNDERVOLTING_MAXIMUM with rc = 0x%x", (uint32_t)rc); break; } -// //---------------------------------------------------------- -// rc = FAPI_ATTR_SET(ATTR_PM_OCC_HEARTBEAT_TIME, &l_pTarget, attr_pm_occ_heartbeat_time_set); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_SET(ATTR_PM_OCC_HEARTBEAT_TIME, &l_pTarget, attr_pm_occ_heartbeat_time_set); // if (rc) { FAPI_ERR("fapiSetAttribute of ATTR_PM_OCC_HEARTBEAT_TIME with rc = 0x%x", (uint32_t)rc); break; } // ------------------------------------------------------------------------------------------------------------------------------------------------ @@ -1213,111 +1213,111 @@ CONST_UINT32_T( OCI_PMC_MODE_REG_0x40010000 , ULL(0x40010000) ); // Enable the get functions -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_FRAME_SIZE, &l_pTarget, attr_pm_spivid_frame_size); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_FRAME_SIZE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_frame_size = 0x%x", attr_pm_spivid_frame_size );} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME1, &l_pTarget, attr_pm_spivid_in_delay_frame1); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME1 with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame1 = 0x%x", attr_pm_spivid_in_delay_frame1);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_IN_DELAY_FRAME2, &l_pTarget, attr_pm_spivid_in_delay_frame2); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_IN_DELAY_FRAME2 with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_in_delay_frame2 = 0x%x", attr_pm_spivid_in_delay_frame2);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_POLARITY, &l_pTarget, attr_pm_spivid_clock_polarity); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_POLARITY with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_polarity = 0x%x", attr_pm_spivid_clock_polarity);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_PHASE, &l_pTarget, attr_pm_spivid_clock_phase); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_PHASE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_phase = 0x%x", attr_pm_spivid_clock_phase);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS, &l_pTarget, attr_pm_spivid_interframe_delay_write_status); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status = 0x%x", attr_pm_spivid_interframe_delay_write_status);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE, &l_pTarget, attr_pm_spivid_interframe_delay_write_status_value); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTERFRAME_DELAY_WRITE_STATUS_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_interframe_delay_write_status_value = 0x%x", attr_pm_spivid_interframe_delay_write_status_value);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE, &l_pTarget, attr_pm_spivid_inter_retry_delay_value); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY_VALUE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay_value = 0x%x", attr_pm_spivid_inter_retry_delay_value);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_INTER_RETRY_DELAY, &l_pTarget, attr_pm_spivid_inter_retry_delay); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_INTER_RETRY_DELAY with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_inter_retry_delay = 0x%x", attr_pm_spivid_inter_retry_delay);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_GEN_ENABLE, &l_pTarget, attr_pm_spivid_crc_gen_enable); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_GEN_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_gen_enable = 0x%x", attr_pm_spivid_crc_gen_enable);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_CHECK_ENABLE, &l_pTarget, attr_pm_spivid_crc_check_enable); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_CHECK_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_check_enable = 0x%x", attr_pm_spivid_crc_check_enable);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE, &l_pTarget, attr_pm_spivid_majority_vote_enable); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAJORITY_VOTE_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_majority_vote_enable = 0x%x", attr_pm_spivid_majority_vote_enable);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_MAX_RETRIES, &l_pTarget, attr_pm_spivid_max_retries); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_MAX_RETRIES with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_max_retries = 0x%x", attr_pm_spivid_max_retries);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES, &l_pTarget, attr_pm_spivid_crc_polynomial_enables); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CRC_POLYNOMIAL_ENABLES with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_crc_polynomial_enables = 0x%x", attr_pm_spivid_crc_polynomial_enables);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_CLOCK_DIVIDER, &l_pTarget, attr_pm_spivid_clock_divider); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_CLOCK_DIVIDER with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_clock_divider = 0x%x", attr_pm_spivid_clock_divider);} -// //---------------------------------------------------------- -// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable); +// //---------------------------------------------------------- +// rc = FAPI_ATTR_GET(ATTR_PM_SPIVID_PORT_ENABLE, &l_pTarget, attr_pm_spivid_port_enable); // if (rc) { FAPI_ERR("fapiGetAttribute of ATTR_PM_SPIVID_PORT_ENABLE with rc = 0x%x", (uint32_t)rc); return rc; } // else { FAPI_INF (" value read from the attribute attr_pm_spivid_port_enable = 0x%x", attr_pm_spivid_port_enable);} -// //---------------------------------------------------------- +// //---------------------------------------------------------- + - //-------------------------------------------------------------------- - //- >>> SCOM.INITFILE elements + //- >>> SCOM.INITFILE elements //-------------------------------------------------------------------- diff --git a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C index fbab62fb9..e2f6f4a73 100644 --- a/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C +++ b/src/usr/hwpf/hwp/utility_procedures/mss_maint_cmds.C @@ -44,7 +44,7 @@ // | | | Added stop condition enums // | | | STOP_IMMEDIATE // | | | ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR -// | | | Now require cleanupCmd() for super fast read +// | | | Now require cleanupCmd() for super fast read // | | | to disable rrq fifo mode when done. // 1.11 | 09/07/12 | gollub | Updates from review. // | | | Support for more patterns. @@ -55,9 +55,9 @@ // | | | Updates to traces. // 1.16 | 11/21/12 | gollub | Updates from review. // 1.17 | 12/19/12 | gollub | Added UE isolation -// 1.18 | 01/15/13 | gollub | Added check for valid dimm before calling +// 1.18 | 01/15/13 | gollub | Added check for valid dimm before calling // | | | dimmGetBadDqBitmap -// 1.19 | 01/31/13 | gollub | Updated MDI bits for random pattern so +// 1.19 | 01/31/13 | gollub | Updated MDI bits for random pattern so // | | | don't get SUEs // | | | Added mss_check_steering // | | | Added mss_do_steering @@ -82,40 +82,40 @@ using namespace fapi; /** * @brief Max 8 master ranks per MB - */ + */ const uint8_t MSS_MAX_RANKS = 8; /** * @brief The number of symbols per rank - */ + */ const uint8_t MSS_SYMBOLS_PER_RANK = 72; /** * @brief 9 x8 DRAMs we can steer, plus one for no steer option - */ + */ const uint8_t MSS_X8_STEER_OPTIONS_PER_PORT = 10; /** * @brief 18 x4 DRAMs we can steer on port0, plus one for no steer option - */ + */ const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT0 = 19; /** * @brief 17 x4 DRAMs we can steer on port1, plus one no steer option - * NOTE: Only 17 DRAMs we can steer since one DRAM is used for the + * NOTE: Only 17 DRAMs we can steer since one DRAM is used for the * ECC spare. - */ + */ const uint8_t MSS_X4_STEER_OPTIONS_PER_PORT1 = 18; /** * @brief 18 on port0, 17 on port1, plus one no steer option * NOTE: Can's use ECC spare to fix bad spare DRAMs - */ + */ const uint8_t MSS_X4_ECC_STEER_OPTIONS = 36; /** * @brief Max 8 patterns - */ + */ const uint8_t MSS_MAX_PATTERNS = 9; @@ -123,14 +123,14 @@ namespace mss_MemConfig { /** * @brief DRAM size in gigabits, used to determine address range for maint cmds - */ + */ enum DramSize { GBIT_2 = 0, GBIT_4 = 1, GBIT_8 = 2, }; - + /** * @brief DRAM width, used to determine address range for maint cmds */ @@ -153,7 +153,7 @@ namespace mss_MemConfig COL_12 = 0x00000FF8, // c2, c1, c0 always 0 BANK_3 = 0x00000007, }; - + /** * @brief Spare DRAM config, used to identify what spares exist */ @@ -164,7 +164,7 @@ namespace mss_MemConfig HIGH_NIBBLE = 2, // x4 spare (high nibble: no plan to use) FULL_BYTE = 3 // x8 dpare }; - + }; @@ -200,7 +200,7 @@ static const uint32_t mss_mbstr[2]={ static const uint32_t mss_mbmmr[2]={ // port0/1 port2/3 MBS_ECC0_MBMMRQ_0x0201145B, MBS_ECC1_MBMMRQ_0x0201149B}; - + static const uint32_t mss_readMuxRegs[8][2]={ // port0/1 port2/3 {MBS_ECC0_MBSBS0_0x0201145E, MBS_ECC1_MBSBS0_0x0201149E}, @@ -211,7 +211,7 @@ static const uint32_t mss_readMuxRegs[8][2]={ {MBS_ECC0_MBSBS5_0x02011463, MBS_ECC1_MBSBS5_0x020114A3}, {MBS_ECC0_MBSBS6_0x02011464, MBS_ECC1_MBSBS6_0x020114A4}, {MBS_ECC0_MBSBS7_0x02011465, MBS_ECC1_MBSBS7_0x020114A5}}; - + static const uint32_t mss_writeMuxRegs[8]={ MBA01_MBABS0_0x03010440, @@ -226,7 +226,7 @@ static const uint32_t mss_writeMuxRegs[8]={ //------------------------------------------------------------------------------ // Conversion from symbol index to galois field stored in markstore //------------------------------------------------------------------------------ -static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = +static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = { 0x80, 0xa0, 0x90, 0xf0, 0x08, 0x0a, 0x09, 0x0f, // symbols 0- 7 0x98, 0xda, 0xb9, 0x7f, 0x91, 0xd7, 0xb2, 0x78, // symbols 8-15 @@ -239,7 +239,7 @@ static const uint8_t mss_symbol2Galois[MSS_SYMBOLS_PER_RANK] = 0xfe, 0x61, 0x75, 0x5d, 0x51, 0x27, 0xa2, 0x38, // symbols 64-71 }; - + static const uint8_t mss_x8dramSparePort0Index_to_symbol[MSS_X8_STEER_OPTIONS_PER_PORT]={ // symbol @@ -646,19 +646,19 @@ static const uint32_t mss_ECC[MSS_MAX_PATTERNS][4]={ 0x04F3D0DA, // 1st 64B of cachline 0x019764DA, // 2nd 64B of cachline 0x0DC751A1}, // 2nd 64B of cachline - + // PATTERN_6 - verified {0x0CF6B55C, // 1st 64B of cachline 0x08CCE671, // 1st 64B of cachline 0x02D94BBB, // 2nd 64B of cachline 0x030C31B6}, // 2nd 64B of cachline - + // PATTERN_7 - verified {0x09150CD1, // 1st 64B of cachline 0x0F9D48C9, // 1st 64B of cachline 0x073AF236, // 2nd 64B of cachline 0x045D9F0E}, // 2nd 64B of cachline - + // PATTERN_8: random {0x00000000, // 1st 64B of cachline 0x00000000, // 1st 64B of cachline @@ -696,17 +696,17 @@ mss_MaintCmd::mss_MaintCmd(const fapi::Target & i_target, fapi::ReturnCode mss_MaintCmd::stopCmd() { fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; + uint32_t l_ecmd_rc = 0; ecmdDataBufferBase l_mbmsrq(64); ecmdDataBufferBase l_mbmccq(64); - ecmdDataBufferBase l_mbmacaq(64); - + ecmdDataBufferBase l_mbmacaq(64); + FAPI_INF("ENTER mss_MaintCmd::stopCmd()"); - + // Read MBMSRQ l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); if(l_rc) return l_rc; - + // If MBMSRQ[0], maint_cmd_in_progress, stop the cmd if (l_mbmsrq.isBitSet(0)) { @@ -725,16 +725,16 @@ fapi::ReturnCode mss_MaintCmd::stopCmd() // Write MBMCCQ l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_mbmccq); if(l_rc) return l_rc; - + // Read MBMSRQ l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_mbmsrq); if(l_rc) return l_rc; - + // If cmd didn't stop as expected if (l_mbmsrq.isBitSet(0)) { FAPI_ERR("MBMSRQ[0] = 1, unsuccessful forced maint cmd stop."); - + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we used to stop cmd @@ -743,13 +743,13 @@ fapi::ReturnCode mss_MaintCmd::stopCmd() ecmdDataBufferBase & MBMSR = l_mbmsrq; // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_UNSUCCESSFUL_FORCED_MAINT_CMD_STOP); - return l_rc; - } + return l_rc; + } } - + // Store the address we stopped at in iv_startAddr l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, iv_startAddr); if(l_rc) return l_rc; @@ -761,8 +761,8 @@ fapi::ReturnCode mss_MaintCmd::stopCmd() l_rc.setEcmdError(l_ecmd_rc); return l_rc; } - - + + FAPI_INF("EXIT mss_MaintCmd::stopCmd()"); return l_rc; } @@ -775,9 +775,9 @@ fapi::ReturnCode mss_MaintCmd::cleanupCmd() { fapi::ReturnCode l_rc; FAPI_INF("ENTER mss_MaintCmd::cleanupCmd()"); - - + + FAPI_INF("EXIT mss_MaintCmd::cleanupCmd()"); return l_rc; } @@ -833,18 +833,18 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // Read MBSECC l_rc = fapiGetScom(iv_targetCentaur, mss_mbsecc[iv_mbaPosition], l_mbsecc); if(l_rc) return l_rc; - + // Read MBMCT[0:4], cmd type, for FFDC l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); if(l_rc) return l_rc; - + // Check for MBMCCQ[0], maint_cmd_start, to be reset by hw. if (l_mbmccq.isBitSet(0)) { FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw."); - + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we are checking @@ -852,8 +852,8 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - + ecmdDataBufferBase & MBMCT = l_mbmct; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET); } @@ -865,7 +865,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() if (l_rc) fapiLogError(l_rc); FAPI_ERR("MBMCCQ[1]: maint_cmd_stop not reset by hw."); - + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we are checking @@ -873,8 +873,8 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; - + ecmdDataBufferBase & MBMCT = l_mbmct; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_STOP_NOT_RESET); } @@ -895,7 +895,7 @@ fapi::ReturnCode mss_MaintCmd::preConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type previously run - ecmdDataBufferBase & MBMCT = l_mbmct; + ecmdDataBufferBase & MBMCT = l_mbmct; // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_IN_PROGRESS); @@ -1040,7 +1040,7 @@ fapi::ReturnCode mss_MaintCmd::loadEndAddress() ecmdDataBufferBase l_data(64); FAPI_INF("ENTER mss_MaintCmd::loadEndAddress()"); - + l_rc = fapiGetScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); if(l_rc) return l_rc; @@ -1049,7 +1049,7 @@ fapi::ReturnCode mss_MaintCmd::loadEndAddress() { l_rc.setEcmdError(l_ecmd_rc); return l_rc; - } + } l_rc = fapiPutScom(iv_target, MBA01_MBMEAQ_0x0301060E, l_data); if(l_rc) return l_rc; @@ -1081,7 +1081,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() if ( 0 != (iv_stopCondition & STOP_IMMEDIATE) ) l_ecmd_rc |= l_mbasctlq.setBit(0); - // Enable stop end of rank + // Enable stop end of rank if ( 0 != (iv_stopCondition & STOP_END_OF_RANK) ) l_ecmd_rc |= l_mbasctlq.setBit(1); @@ -1111,7 +1111,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() // Stop on MPE if ( 0 != (iv_stopCondition & STOP_ON_MPE) ) - l_ecmd_rc |= l_mbasctlq.setBit(8); + l_ecmd_rc |= l_mbasctlq.setBit(8); // Stop on UE if ( 0 != (iv_stopCondition & STOP_ON_UE) ) @@ -1126,9 +1126,9 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() l_ecmd_rc |= l_mbasctlq.setBit(11); // Stop on SUE - if ( 0 != (iv_stopCondition & STOP_ON_SUE) ) + if ( 0 != (iv_stopCondition & STOP_ON_SUE) ) l_ecmd_rc |= l_mbasctlq.setBit(12); - + // Enable command complete attention on clean and error if ( 0 != (iv_stopCondition & ENABLE_CMD_COMPLETE_ATTENTION_ON_CLEAN_AND_ERROR) ) l_ecmd_rc |= l_mbasctlq.setBit(16); @@ -1144,7 +1144,7 @@ fapi::ReturnCode mss_MaintCmd::loadStopCondMask() if(l_rc) return l_rc; FAPI_INF("EXIT mss_MaintCmd::loadStopCondMask()"); - + return l_rc; } @@ -1168,7 +1168,7 @@ fapi::ReturnCode mss_MaintCmd::startMaintCmd() { l_rc.setEcmdError(l_ecmd_rc); return l_rc; - } + } l_rc = fapiPutScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); if(l_rc) return l_rc; @@ -1185,7 +1185,7 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() ecmdDataBufferBase l_mbmccq(64); ecmdDataBufferBase l_mbafirq(64); ecmdDataBufferBase l_mbmct(64); - + FAPI_INF("ENTER mss_MaintCmd::postConditionCheck()"); // Read MBMCCQ @@ -1195,16 +1195,16 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // Read MBAFIRQ l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_mbafirq); if(l_rc) return l_rc; - + // Read MBMCT[0:4], cmd type, for FFDC l_rc = fapiGetScom(iv_target, MBA01_MBMCTQ_0x0301060A, l_mbmct); - if(l_rc) return l_rc; - + if(l_rc) return l_rc; + // Check for MBMCCQ[0], maint_cmd_start, to be reset by hw. if (l_mbmccq.isBitSet(0)) { FAPI_ERR("MBMCCQ[0]: maint_cmd_start not reset by hw."); - + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = iv_target; // FFDC: Capture register we are checking @@ -1212,8 +1212,8 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; - + ecmdDataBufferBase & MBMCT = l_mbmct; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_START_NOT_RESET); } @@ -1225,7 +1225,7 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() if (l_rc) fapiLogError(l_rc); FAPI_ERR("MBAFIRQ[0], invalid_maint_cmd."); - + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = iv_target; @@ -1234,9 +1234,9 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type set in hw - ecmdDataBufferBase & MBMCT = l_mbmct; - - // Create new log + ecmdDataBufferBase & MBMCT = l_mbmct; + + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_CMD); } @@ -1257,8 +1257,8 @@ fapi::ReturnCode mss_MaintCmd::postConditionCheck() const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // FFDC: MBMCT[0:4] contains the cmd type set in hw ecmdDataBufferBase & MBMCT = l_mbmct; - // NOTE: List of additional FFDC regs specified in memory_errors.xml - + // NOTE: List of additional FFDC regs specified in memory_errors.xml + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_ADDR); } @@ -1298,12 +1298,12 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() FAPI_DBG("MBSPAQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); // Read MBMACAQ just to see if it's incrementing - l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMACAQ_0x0301060D, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMACAQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); // Waiting for MBMSRQ[0] maint cmd in progress bit to turn off - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMSRQ = 0x%.8X 0x%.8X",l_data.getWord(0), l_data.getWord(1)); @@ -1316,7 +1316,7 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() if (count == loop_limit) { FAPI_ERR("Maint cmd timeout."); - + // TODO: Calling out FW high // Calling out MBA target low, deconfig, gard const fapi::Target & MBA = iv_target; @@ -1324,10 +1324,10 @@ fapi::ReturnCode mss_MaintCmd::pollForMaintCmdComplete() const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; // Specify CENTAUR target so we can read some FFDC regs from MBS const fapi::Target & CENTAUR = iv_targetCentaur; - // NOTE: List of additional FFDC regs specified in memory_errors.xml + // NOTE: List of additional FFDC regs specified in memory_errors.xml // Create new log - FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT); + FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_CMD_TIMEOUT); } else { @@ -1349,7 +1349,7 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; uint8_t l_symbol_mark = MSS_INVALID_SYMBOL; - uint8_t l_chip_mark = MSS_INVALID_SYMBOL; + uint8_t l_chip_mark = MSS_INVALID_SYMBOL; FAPI_INF("ENTER mss_MaintCmd::collectFFDC()"); @@ -1378,19 +1378,19 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() if(l_rc) return l_rc; FAPI_DBG("MBASCTLQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMCCQ_0x0301060B, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMCCQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBMSRQ_0x0301060C, l_data); if(l_rc) return l_rc; FAPI_DBG("MBMSRQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBAFIRQ_0x03010600, l_data); if(l_rc) return l_rc; FAPI_DBG("MBAFIRQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); - l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); + l_rc = fapiGetScom(iv_target, MBA01_MBSPAQ_0x03010611, l_data); if(l_rc) return l_rc; FAPI_DBG("MBSPAQ = 0x%.8X 0x%.8X", l_data.getWord(0), l_data.getWord(1)); @@ -1446,7 +1446,7 @@ fapi::ReturnCode mss_MaintCmd::collectFFDC() l_eccSpareSymbol); if(l_rc) return l_rc; } - + FAPI_INF("EXIT mss_MaintCmd::collectFFDC()"); return l_rc; } @@ -1540,7 +1540,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) for(loop=0; loop<16; loop++ ) { - // A write to MAINT_BUFFx_DATAy will not update until the corresponding + // A write to MAINT_BUFFx_DATAy will not update until the corresponding // MAINT_BUFFx_DATA_ECCy is written to. l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][0], 0, 32, 0); l_ecmd_rc |= l_data.insert(mss_maintBufferData[i_initPattern][loop][1], 32, 32, 0); @@ -1550,7 +1550,7 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) return l_rc; } l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][0], l_data); - if(l_rc) return l_rc; + if(l_rc) return l_rc; l_rc = fapiPutScom(iv_targetCentaur, maintBufferDataRegs[iv_mbaPosition][loop][1], l_ecc); if(l_rc) return l_rc; @@ -1583,11 +1583,11 @@ fapi::ReturnCode mss_MaintCmd::loadPattern(PatternIndex i_initPattern) l_rc = fapiPutScom(iv_targetCentaur, maintBuffer65thRegs[loop][iv_mbaPosition], l_65th); if(l_rc) return l_rc; - } + } //---------------------------------------------------- // Save i_initPattern in unused maint mark reg - // so we know what pattern was used when we do + // so we know what pattern was used when we do // UE isolation //---------------------------------------------------- @@ -1695,8 +1695,8 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) { // Get l_ddr_freq from ATTR_MSS_FREQ // Possible frequencies are 800, 1066, 1333, 1600, 1866, and 2133 MHz - // NOTE: Max 32 address bits using 800 and 1066 result in scrub - // taking longer than 12h, but these is no plan to actually use + // NOTE: Max 32 address bits using 800 and 1066 result in scrub + // taking longer than 12h, but these is no plan to actually use // those frequencies. l_rc = FAPI_ATTR_GET( ATTR_MSS_FREQ, &iv_targetCentaur, l_ddr_freq); if (l_rc) @@ -1709,7 +1709,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) if (l_ddr_freq == 0) { FAPI_ERR("ATTR_MSS_FREQ set to zero so can't calculate scrub rate."); - + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = iv_target; @@ -1718,11 +1718,11 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) // FFDC: Capture command type we are trying to run const mss_MaintCmd::CmdType & CMD_TYPE = iv_cmdType; - // Create new log + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_ZERO_DDR_FREQ); return l_rc; } - + // l_timebase_sel // MBMCTQ[9:10]: 00 = 1 * Maint Clk // 01 = 8192 * Maint Clk @@ -1756,7 +1756,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) } // NOTE: Assumption is max 32 address bits, which can be done - // in 12h (+/- 2h). More than 32 address bits would + // in 12h (+/- 2h). More than 32 address bits would // double scrub time for every extra address bit. if (l_num_address_bits > 32) { @@ -1800,7 +1800,7 @@ fapi::ReturnCode mss_MaintCmd::loadSpeed(TimeBaseSpeed i_speed) l_timebase_burst_sel = 0; // Disable burst mode l_burst_window_sel = 0; // Don't care since burst mode disabled l_burst_window = 0; // Don't care since burst mode disabled - l_burst_interval = 0; // Don't care since burst mode disabled + l_burst_interval = 0; // Don't care since burst mode disabled return l_rc; @@ -1878,7 +1878,7 @@ mss_SuperFastInit::mss_SuperFastInit( const fapi::Target & i_target, i_stopCondition, i_poll, cv_cmdType), - iv_initPattern( i_initPattern ) // NOTE: iv_initPattern is instance + iv_initPattern( i_initPattern ) // NOTE: iv_initPattern is instance // variable of SuperFastInit, since not // needed in parent class {} @@ -1899,7 +1899,7 @@ fapi::ReturnCode mss_SuperFastInit::setupAndExecuteCmd() fapi::ReturnCode l_rc; ecmdDataBufferBase l_data(64); - + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -1908,7 +1908,7 @@ fapi::ReturnCode mss_SuperFastInit::setupAndExecuteCmd() // Make sure maint logic in valid state to run new cmd l_rc = preConditionCheck(); if(l_rc) return l_rc; - + // Load pattern l_rc = loadPattern(iv_initPattern); if(l_rc) return l_rc; @@ -1993,7 +1993,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() fapi::ReturnCode l_rc; uint32_t l_ecmd_rc = 0; - + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -2008,7 +2008,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() // Load cmd type: MBMCTQ l_rc = loadCmdType(); if(l_rc) return l_rc; - + // Load start address: MBMACAQ l_rc = loadStartAddress(); if(l_rc) return l_rc; @@ -2055,7 +2055,7 @@ fapi::ReturnCode mss_SuperFastRandomInit::setupAndExecuteCmd() l_rc = collectFFDC(); if(l_rc) return l_rc; FAPI_INF("EXIT mss_SuperFastRandomInit::setupAndExecuteCmd()"); - + return l_rc; } @@ -2175,7 +2175,7 @@ fapi::ReturnCode mss_SuperFastRead::setupAndExecuteCmd() // Start the command: MBMCCQ l_rc = startMaintCmd(); if(l_rc) return l_rc; - + // Check for early problems with maint cmd instead of waiting for // cmd timeout l_rc = postConditionCheck(); if(l_rc) return l_rc; @@ -2287,7 +2287,7 @@ fapi::ReturnCode mss_SuperFastRead::cleanupCmd() FAPI_INF("EXIT mss_SuperFastRead::cleanupCmd()"); - + return l_rc; } @@ -2328,7 +2328,7 @@ fapi::ReturnCode mss_AtomicInject::setupAndExecuteCmd() FAPI_INF("ENTER mss_AtomicInject::setupAndExecuteCmd()"); fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; + uint32_t l_ecmd_rc = 0; // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. @@ -2555,20 +2555,20 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() fapi::ReturnCode l_rc; - uint32_t l_ecmd_rc = 0; + uint32_t l_ecmd_rc = 0; ecmdDataBufferBase l_mbspa_mask(64); ecmdDataBufferBase l_mbspa_mask_original(64); - ecmdDataBufferBase l_mbspa_and(64); - + ecmdDataBufferBase l_mbspa_and(64); + // Read MBSPA MASK l_rc = fapiGetScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); if(l_rc) return l_rc; - + // Save original mask value so we can restore it when done - l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); + l_ecmd_rc |= l_mbspa_mask_original.insert(l_mbspa_mask, 0, 64, 0); // Mask bits 0 and 8, to hide the special attentions when the cmd completes - l_ecmd_rc |= l_mbspa_mask.setBit(0); + l_ecmd_rc |= l_mbspa_mask.setBit(0); l_ecmd_rc |= l_mbspa_mask.setBit(8); if(l_ecmd_rc) { @@ -2579,7 +2579,7 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() // Write MBSPA MASK l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask); if(l_rc) return l_rc; - + // Make sure maint logic in valid state to run new cmd l_rc = preConditionCheck(); if(l_rc) return l_rc; @@ -2622,11 +2622,11 @@ fapi::ReturnCode mss_IncrementAddress::setupAndExecuteCmd() // Write MPSPA AND register l_rc = fapiPutScom(iv_target, MBA01_MBSPAQ_AND_0x03010612, l_mbspa_and); if(l_rc) return l_rc; - - // Restore MBSPA MASK + + // Restore MBSPA MASK l_rc = fapiPutScom(iv_target, MBA01_MBSPAMSKQ_0x03010614, l_mbspa_mask_original); if(l_rc) return l_rc; - + FAPI_INF("EXIT mss_IncrementAddress::setupAndExecuteCmd()"); @@ -2702,12 +2702,12 @@ fapi::ReturnCode mss_TimeBaseScrub::setupAndExecuteCmd() FAPI_INF("\nDEBUG. Set hard CE threshold to 1: MBSTRQ"); ecmdDataBufferBase l_data(64); uint32_t l_hardCEThreshold = 1; - l_rc = fapiGetScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); + l_rc = fapiGetScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); if(l_rc) return l_rc; l_data.insert( l_hardCEThreshold, 28, 12, 32-12 ); // 28:39 hard ce threshold l_data.setBit(2); // Enable hard ce ETE special attention l_data.setBit(57); // Enable per-symbol counters to count hard ces - l_rc = fapiPutScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); + l_rc = fapiPutScom(iv_target, MBS01_MBSTRQ_0x02011655, l_data); if(l_rc) return l_rc; */ @@ -2726,7 +2726,7 @@ fapi::ReturnCode mss_TimeBaseScrub::setupAndExecuteCmd() // Poll for command complete: MBMSRQ l_rc = pollForMaintCmdComplete(); if(l_rc) return l_rc; - + // Collect FFDC l_rc = collectFFDC(); if(l_rc) return l_rc; @@ -2776,7 +2776,7 @@ fapi::ReturnCode mss_TimeBaseSteerCleanup::setupAndExecuteCmd() FAPI_INF("ENTER mss_TimeBaseSteerCleanup::setupAndExecuteCmd()"); fapi::ReturnCode l_rc; - + // Gather data that needs to be stored. For testing purposes we will just // set an abitrary number. //l_rc = setSavedData( 0xdeadbeef ); if(l_rc) return l_rc; @@ -2849,7 +2849,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, static const uint8_t memConfigType[9][4][2]={ // Refer to Centaur Workbook: 5.2 Master and Slave Rank Usage - // + // // SUBTYPE_A SUBTYPE_B SUBTYPE_C SUBTYPE_D // //SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 SLOT_0_ONLY SLOT_0_AND_1 @@ -3004,8 +3004,8 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, const fapi::Target & MBA = i_target; // FFDC: Capture register we are checking ecmdDataBufferBase & MBAXCR = l_data; - - // Create new log. + + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_DRAM_SIZE_WIDTH); return l_rc; } @@ -3021,7 +3021,7 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, // (4:5) Configuration subtype (A, B, C, D) l_ecmd_rc |= l_data.extractPreserve(&l_configSubType, 4, 2, 8-2); - // (8) Slot Configuration + // (8) Slot Configuration // 0 = Centaur DIMM or IS DIMM, slot0 only, 1 = IS DIMM slots 0 and 1 l_ecmd_rc |= l_data.extractPreserve(&l_slotConfig, 8, 1, 8-1); if(l_ecmd_rc) @@ -3085,12 +3085,12 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, l_ecmd_rc |= o_endAddr.insert( l_end_slave_rank, 4, 3, 8-3 ); // BANK = 7:10 - l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); + l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_bank, 7, 4, 32-4 ); // ROW = 11:27 l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_row_zero, 11, 17, 32-17 ); - // COL = 28:39, note: c2, c1, c0 always 0 + // COL = 28:39, note: c2, c1, c0 always 0 l_ecmd_rc |= o_endAddr.insert( (uint32_t)l_col, 28, 12, 32-12 ); @@ -3134,9 +3134,9 @@ fapi::ReturnCode mss_get_address_range( const fapi::Target & i_target, // FFDC: Capture i_rank; uint8_t RANK = i_rank; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_ADDRESS_RANGE_BAD_INPUT); - return l_rc; + return l_rc; } // NOTE: If this rank is not valid, we should see MBAFIR[1]: invalid @@ -3289,9 +3289,9 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, // FFDC: Capture i_rank; uint8_t RANK = i_rank; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_MARK_STORE_BAD_INPUT); - return l_rc; + return l_rc; } // Read markstore register for the given rank @@ -3318,7 +3318,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, if (l_symbolMarkGalois == 0x00) // No symbol mark { - o_symbolMark = MSS_INVALID_SYMBOL; + o_symbolMark = MSS_INVALID_SYMBOL; } else if (l_dramWidth == mss_MemConfig::X4) { @@ -3364,7 +3364,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, // FFDC: Capture markstore ecmdDataBufferBase & MARKSTORE = l_markstore; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE); return l_rc; } @@ -3381,7 +3381,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, if (l_chipMarkGalois == 0x00) // No chip mark { - o_chipMark = MSS_INVALID_SYMBOL; + o_chipMark = MSS_INVALID_SYMBOL; } else // Converted from galois field to chip index { @@ -3419,7 +3419,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, // FFDC: Capture markstore ecmdDataBufferBase & MARKSTORE = l_markstore; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_MARKSTORE); return l_rc; } @@ -3427,7 +3427,7 @@ fapi::ReturnCode mss_get_mark_store( const fapi::Target & i_target, FAPI_INF("mss_get_mark_store(): rank%d, chip mark = %d, symbol mark = %d", i_rank, o_chipMark, o_symbolMark ); - + return l_rc; } @@ -3481,7 +3481,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, FAPI_ERR("Error getting DRAM width"); return l_rc; } - + // Check for i_rank out of range if (i_rank>=8) { @@ -3492,10 +3492,10 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, // FFDC: Capture i_rank; uint8_t RANK = i_rank; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_MARK_STORE_BAD_INPUT); - return l_rc; - } + return l_rc; + } // Get l_symbolMarkGalois if (i_symbolMark == MSS_INVALID_SYMBOL) // No symbol mark @@ -3570,7 +3570,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, // FFDC: Capure i_chipMark; uint8_t CHIP_MARK = i_chipMark; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_INDEX); return l_rc; } @@ -3639,7 +3639,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, { // TODO: Can FW distingish this rc from all the others // so they know they just need to retry after clearing MPR FIR? - + FAPI_ERR("Markstore write may have been blocked due to MPE FIR set."); // FFDC: MBA target @@ -3654,7 +3654,7 @@ fapi::ReturnCode mss_put_mark_store( const fapi::Target & i_target, uint8_t CHIP_MARK = i_chipMark; // FFDC: Capture MBECCFIR ecmdDataBufferBase & MBECCFIR = l_mbeccfir; - + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_MARKSTORE_WRITE_BLOCKED); return l_rc; @@ -3692,7 +3692,7 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, o_dramSparePort0Symbol = MSS_INVALID_SYMBOL; o_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - o_eccSpareSymbol = MSS_INVALID_SYMBOL; + o_eccSpareSymbol = MSS_INVALID_SYMBOL; // Get Centaur target for the given MBA l_rc = fapiGetParentChip(i_target, l_targetCentaur); @@ -3721,21 +3721,21 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // Check for i_rank or i_muxType out of range - if ((i_rank>=8) || + if ((i_rank>=8) || !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX))) { - FAPI_ERR("i_rank or i_muxType input to mss_get_steer_mux out of range"); + FAPI_ERR("i_rank or i_muxType input to mss_get_steer_mux out of range"); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_GET_STEER_MUX_BAD_INPUT); - return l_rc; + return l_rc; } @@ -3774,7 +3774,7 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, else { FAPI_ERR("Steer mux l_dramSparePort0Index out of range."); - + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3783,13 +3783,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capture steer mux ecmdDataBufferBase & STEER_MUX = l_steerMux; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; + return l_rc; } @@ -3814,7 +3814,7 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, else { FAPI_ERR("Steer mux l_dramSparePort1Index out of range."); - + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3823,13 +3823,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capture steer mux ecmdDataBufferBase & STEER_MUX = l_steerMux; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; + return l_rc; } @@ -3850,7 +3850,7 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, else { FAPI_ERR("o_eccSpareSymbol out of range."); - + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -3859,13 +3859,13 @@ fapi::ReturnCode mss_get_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capture steer mux ecmdDataBufferBase & STEER_MUX = l_steerMux; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_STEER_MUX); - return l_rc; + return l_rc; } FAPI_INF("mss_get_steer_mux(): rank%d, port0 steer = %d, port1 steer = %d, ecc steer = %d", @@ -3934,27 +3934,27 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // Check for i_rank or i_muxType or i_steerType or i_symbol out of range - if ((i_rank>=8) || + if ((i_rank>=8) || !((i_muxType==mss_SteerMux::READ_MUX) || (i_muxType==mss_SteerMux::WRITE_MUX)) || !((i_steerType == mss_SteerMux::DRAM_SPARE_PORT0) || (i_steerType == mss_SteerMux::DRAM_SPARE_PORT1) || (i_steerType == mss_SteerMux::ECC_SPARE)) || (i_symbol >= 72)) { - FAPI_ERR("i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range"); + FAPI_ERR("i_rank or i_muxType or i_steerType or i_symbol input to mss_get_steer_mux out of range"); // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; // FFDC: Capture i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_PUT_STEER_MUX_BAD_INPUT); - return l_rc; + return l_rc; } @@ -3991,7 +3991,7 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, if ( MSS_X8_STEER_OPTIONS_PER_PORT <= l_dramSparePort0Index ) { FAPI_ERR("No match for i_symbol = %d in mss_x8dramSparePort0Index_to_symbol[].", i_symbol); - + // TODO: Calling out FW high // FFDC: MBA target const fapi::Target & MBA = i_target; @@ -4000,13 +4000,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4036,13 +4036,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4079,13 +4079,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4115,13 +4115,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4159,13 +4159,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_INVALID_SYMBOL_TO_STEER); return l_rc; } @@ -4182,13 +4182,13 @@ fapi::ReturnCode mss_put_steer_mux( const fapi::Target & i_target, // FFDC: Capure i_rank; uint8_t RANK = i_rank; // FFDC: Capure i_muxType - uint8_t MUX_TYPE = i_muxType; + uint8_t MUX_TYPE = i_muxType; // FFDC: Capure i_steerType - uint8_t STEER_TYPE = i_steerType; + uint8_t STEER_TYPE = i_steerType; // FFDC: Capure i_symbol - uint8_t SYMBOL = i_symbol; + uint8_t SYMBOL = i_symbol; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_X8_ECC_SPARE); return l_rc; } @@ -4263,7 +4263,7 @@ fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, uint8_t l_steerType = 0; // 0 = DRAM_SPARE_PORT0, Spare DRAM on port0 // 1 = DRAM_SPARE_PORT1, Spare DRAM on port1 // 2 = ECC_SPARE, ECC spare (used in x4 mode only) - + // Check for i_rank or i_symbol out of range if ((i_rank>=8) || (i_symbol>=72)) @@ -4277,45 +4277,45 @@ fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, // FFDC: Capture i_symbol; uint8_t SYMBOL = i_symbol; // FFDC: Capture i_x4EccSpare - uint8_t X4ECCSPARE = i_x4EccSpare; + uint8_t X4ECCSPARE = i_x4EccSpare; - // Create new log. + // Create new log. FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_DO_STEER_INPUT_OUT_OF_RANGE); - return l_rc; + return l_rc; } //------------------------------------------------------ // Determine l_steerType - //------------------------------------------------------ + //------------------------------------------------------ if (i_x4EccSpare) { l_steerType = mss_SteerMux::ECC_SPARE; } else { - // Symbols 71-40, 7-4 come from port0 + // Symbols 71-40, 7-4 come from port0 if (((i_symbol<=71)&&(i_symbol>=40)) || ((i_symbol<=7)&&(i_symbol>=4))) { l_steerType = mss_SteerMux::DRAM_SPARE_PORT0; } - // Symbols 39-8, 3-0 come from port1 + // Symbols 39-8, 3-0 come from port1 else { - l_steerType = mss_SteerMux::DRAM_SPARE_PORT1; - } + l_steerType = mss_SteerMux::DRAM_SPARE_PORT1; + } } //------------------------------------------------------ // Update write mux //------------------------------------------------------ l_rc = mss_put_steer_mux( - + i_target, // MBA i_rank, // Master rank: 0-7 mss_SteerMux::WRITE_MUX,// write mux l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE i_symbol); // First symbol index of DRAM to steer around - + if (l_rc) { FAPI_ERR("Error updating write mux"); @@ -4324,31 +4324,31 @@ fapi::ReturnCode mss_do_steering(const fapi::Target & i_target, //------------------------------------------------------ // Wait for a periodic cal. - //------------------------------------------------------ + //------------------------------------------------------ // 250 ms delay for HW mode const uint64_t HW_MODE_DELAY = 250000000; - - // 200000 sim cycle delay for SIM mode - const uint64_t SIM_MODE_DELAY = 200000; - + + // 200000 sim cycle delay for SIM mode + const uint64_t SIM_MODE_DELAY = 200000; + fapiDelay(HW_MODE_DELAY, SIM_MODE_DELAY); - + // TODO: Could be precise and find cal interval from: // ATTR_EFF_ZQCAL_INTERVAL (in clocks... so still have to know freq) - // ATTR_EFF_MEMCAL_INTERVAL (in clocks... so still have to know freq) + // ATTR_EFF_MEMCAL_INTERVAL (in clocks... so still have to know freq) //------------------------------------------------------ // Update read mux - //------------------------------------------------------ + //------------------------------------------------------ l_rc = mss_put_steer_mux( - + i_target, // MBA i_rank, // Master rank: 0-7 mss_SteerMux::READ_MUX, // read mux l_steerType, // DRAM_SPARE_PORT0/DRAM_SPARE_PORT1/ECC_SPARE i_symbol); // First symbol index of DRAM to steer around - + if (l_rc) { FAPI_ERR("Error updating read mux"); @@ -4386,7 +4386,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, uint8_t l_dq_pair_index = 0; uint8_t l_bad_dq_pair_index = 0; uint8_t l_bad_dq_pair_count=0; - uint8_t l_bad_dq_pair = 0xff; + uint8_t __attribute__((unused)) l_bad_dq_pair = 0xff; // HACK. uint8_t l_dq_pair_mask = 0xC0; uint8_t l_byte_being_steered = 0xff; uint8_t l_bad_symbol = MSS_INVALID_SYMBOL; @@ -4478,7 +4478,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, { // For each DIMM select on the given port:0,1 for(l_dimm=0; l_dimm<DIMM_DQ_MAX_MBAPORT_DIMMS; l_dimm++ ) - { + { if (l_valid_dimm[l_port][l_dimm]) { // For each rank select on the given DIMM select:0,1,2,3 @@ -4573,7 +4573,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, l_dq_pair_mask = l_dq_pair_mask >> 2; } - // If spare is bad but not used, not valid to try repair + // If spare is bad but not used, not valid to try repair if ( l_spare_exists && (l_byte==9) && (l_bad_dq_pair_count > 0) && !l_spare_used) { FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, Bad unused spare - no valid repair", @@ -4627,7 +4627,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Remember which byte is being steered // so we know where to apply chip or symbol mark - // if spare turns out to be bad + // if spare turns out to be bad l_byte_being_steered = l_byte; // Update which rank 0-7 has had repairs applied @@ -4715,13 +4715,13 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte, 8*l_byte+7,l_chip_mark, l_chip_mark+3 ); } - + // Else, more bad bits than we can repair so update o_repairs_exceeded else { - o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; + o_repairs_exceeded |= l_repairs_exceeded_translation[l_port][l_dimm]; - l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; + l_repair_status[l_port][l_dimm][l_rank]=MSS_REPAIRS_EXCEEDED; // If port1 repairs exceeded and port0 had a repair, say port0 repairs exceeded too if ((l_repair_status[1][l_dimm][l_rank] == MSS_REPAIRS_EXCEEDED) && (l_repair_status[0][l_dimm][l_rank] == MSS_REPAIRS_APPLIED)) @@ -4736,7 +4736,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Break out of loop on bytes break; } - } // End If bad symbol count > 1 + } // End If bad symbol count > 1 //Else if bad symbol count = 1 @@ -4746,7 +4746,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, if (!l_symbol_mark_used) { - // NOTE: Have to do a read/modify/write so we + // NOTE: Have to do a read/modify/write so we // only update symbol mark, and don't overwrite // chip mark. @@ -4808,7 +4808,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, } FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbol %d, FIXED SYMBOL WITH X2 SYMBOL MARK", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], + l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_symbol_mark ); @@ -4857,7 +4857,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, // Remember which byte is being steered // so we where to apply chip or symbol mark - // if spare turns out to be bad + // if spare turns out to be bad l_byte_being_steered = l_byte; // Update which rank 0-7 has had repairs applied @@ -4872,7 +4872,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, } FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 STEER", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], + l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_bad_symbol, l_bad_symbol + 3); @@ -4883,7 +4883,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, else if (!l_chip_mark_used) { - // NOTE: Have to do a read/modify/write so we + // NOTE: Have to do a read/modify/write so we // only update chip mark, and don't overwrite // symbol mark. @@ -4945,7 +4945,7 @@ fapi::ReturnCode mss_restore_DRAM_repairs( const fapi::Target & i_target, } FAPI_ERR("WARNING: port=%d, dimm=%d, rank=%d, l_dqBitmap[%d] = %02x, dq %d-%d, symbols %d-%d, FIXED SYMBOL WITH X8 CHIP MARK", - l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], + l_port, l_dimm, l_rank, l_byte, l_dqBitmap[l_byte], 8*l_byte + 2*l_bad_dq_pair_index, 8*l_byte + 2*l_bad_dq_pair_index + 1, l_chip_mark, l_chip_mark + 3); @@ -5066,7 +5066,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, MAINT0_MBA_MAINT_BUFF3_DATA2_0x03010687, // 5 DW11 MAINT0_MBA_MAINT_BUFF1_DATA3_0x03010668, // 6 DW13 MAINT0_MBA_MAINT_BUFF3_DATA3_0x03010688}},//7 DW15 - + // UE trap 1: // Port0 {{MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, // 0 DW0 @@ -5106,13 +5106,13 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, uint8_t l_port = 0; // 0,1 uint8_t l_beat = 0; // 0-7 uint8_t l_byte = 0; // 0-9 - uint8_t l_loop = 0; + uint8_t l_loop = 0; ecmdDataBufferBase l_data(64); ecmdDataBufferBase l_UE_trap0_signature(64); ecmdDataBufferBase l_UE_trap1_signature(64); ecmdDataBufferBase l_mbmmr(64); ecmdDataBufferBase l_mbmct(64); - ecmdDataBufferBase l_mbstr(64); + ecmdDataBufferBase l_mbstr(64); uint8_t l_initPattern = 0; uint8_t l_cmd_type = 0; fapi::Target l_targetCentaur; @@ -5130,7 +5130,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, uint8_t l_ECC_c3_c2_c1_c0_23 = 0; uint8_t l_dramSparePort0Symbol = MSS_INVALID_SYMBOL; uint8_t l_dramSparePort1Symbol = MSS_INVALID_SYMBOL; - uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; + uint8_t l_eccSpareSymbol = MSS_INVALID_SYMBOL; //---------------------------------------------------- // Initialize o_bad_bits @@ -5167,7 +5167,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, // MBMMR[4:7] contains the pattern index l_rc = fapiGetScom(l_targetCentaur, mss_mbmmr[l_mbaPosition], l_mbmmr); - if(l_rc) return l_rc; + if(l_rc) return l_rc; l_ecmd_rc |= l_mbmmr.extractPreserve(&l_initPattern, 4, 4, 8-4); if(l_ecmd_rc) { @@ -5212,7 +5212,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA0_0x03010655, l_UE_trap0_signature); if(l_rc) return l_rc; - + l_rc = fapiGetScom(i_target, MAINT0_MBA_MAINT_BUFF0_DATA4_0x03010659, l_UE_trap1_signature); if(l_rc) return l_rc; @@ -5233,27 +5233,27 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, else { FAPI_ERR("IPL UE trapping didn't work."); - + // Read for FFDC: MBSTR[59]: UE trap enable bit l_rc = fapiGetScom(l_targetCentaur, mss_mbstr[l_mbaPosition], l_mbstr); if(l_rc) return l_rc; - + // Calling out MBA target high, deconfig, gard const fapi::Target & MBA = i_target; // FFDC: Capture UE trap contents ecmdDataBufferBase & UE_TRAP0 = l_UE_trap0_signature; - ecmdDataBufferBase & UE_TRAP1 = l_UE_trap1_signature; + ecmdDataBufferBase & UE_TRAP1 = l_UE_trap1_signature; // FFDC: MBMCT[0:4] contains the cmd type - ecmdDataBufferBase & MBMCT = l_mbmct; + ecmdDataBufferBase & MBMCT = l_mbmct; // FFDC: MBMMR[4:7] contains the pattern index - ecmdDataBufferBase & MBMMR = l_mbmmr; + ecmdDataBufferBase & MBMMR = l_mbmmr; // FFDC: MBSTR[59]: UE trap enable bit - ecmdDataBufferBase & MBSTR = l_mbstr; - + ecmdDataBufferBase & MBSTR = l_mbstr; + // Create new log FAPI_SET_HWP_ERROR(l_rc, RC_MSS_MAINT_NO_UE_TRAP); - + return l_rc; } @@ -5267,7 +5267,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, { l_tmp_data_diff[0] = 0; l_tmp_data_diff[1] = 0; - + FAPI_INF("port%d", l_port); for(l_beat=0; l_beat<8; l_beat++ ) { @@ -5287,7 +5287,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, FAPI_INF("***************************************** l_tmp_diff: 0x%.8X 0x%.8X", l_tmp_data_diff[0], l_tmp_data_diff[1]); } - // Put l_tmp_diff into a ecmdDataBufferBase to make it easier + // Put l_tmp_diff into a ecmdDataBufferBase to make it easier // to get into o_bad_bits l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[0], 0, 32, 0); l_ecmd_rc |= l_diff.insert(l_tmp_data_diff[1], 32, 32, 0); @@ -5316,7 +5316,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- for(l_loop=0; l_loop<4; l_loop++ ) - { + { l_tag_MDI = 0; l_tmp_65th_byte_diff = 0; @@ -5348,7 +5348,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, { // Checkbit0_1 maps to port0 bit 64, which is on byte8 o_bad_bits[0][8] |= 0x80; - } + } // Check for mismatch in bit 1: Tag0_2 if (l_tmp_65th_byte_diff & 0x40) @@ -5378,7 +5378,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, //---------------------------------------------------- for(l_loop=0; l_loop<4; l_loop++ ) - { + { l_ECC = 0; l_rc = fapiGetScom(i_target, maintBufferRead65thByteRegs[l_UE_trap][l_loop], l_data); @@ -5424,7 +5424,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, o_bad_bits[0][8] |= l_ECC_c6_c5_c4_01 | l_ECC_c6_c5_c4_23; // The 8 bits of ECC_c3_c2_c1_c0 maps to byte8 byte on port1 o_bad_bits[1][8] |= l_ECC_c3_c2_c1_c0_01 | l_ECC_c3_c2_c1_c0_23; - + //---------------------------------------------------- // Spare: Mark byte9 bad if bad bits found in position being steered @@ -5471,7 +5471,7 @@ fapi::ReturnCode mss_IPL_UE_isolation( const fapi::Target & i_target, } //---------------------------------------------------- - // Show results + // Show results //---------------------------------------------------- FAPI_ERR("WARNING: IPL UE isolation results for rank = %d.", i_rank); |
