Hostboot - Updated HWPs from defect SW219606 (week 8/13)

SW219606

Change-Id: I9eee6d20610412764a0ad3ed406633426f154b2f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5971
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

2 files changed, 92 insertions, 53 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
index 4821e2a31..e3aea2740 100644
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_clear_firs.H,v 1.7 2013/03/26 14:45:18 jaswamin Exp $
+// $Id: io_clear_firs.H,v 1.8 2013/08/01 12:57:19 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 2012, 2013
 // *!           All Rights Reserved -- Property of IBM
@@ -110,6 +110,18 @@ const uint32_t fir_clear_mask_reg_addr[FIR_INTERFACES]={0x04011004,
                                                   0x02011a04, 
                                                   0x02011e04, 
                                                   0x02010404  };
+// This is for Centaur Reconfig loop IO_CLEANUP  procedure
+const uint32_t scom_mode_pb_reg_addr[FIR_INTERFACES] ={ 0x04011020,
+                                                       0x04011420,
+                                                       0x04011C20,
+                                                       0x04011820,
+                                                       0x08010C20,
+                                                       0x02011A20,
+                                                       0x02011E20,
+                                                       0x02010420};
+    
+    
+    
                                                   
 
 enum fir_error_type{
diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
index 7ded82f58..42d327273 100644
--- a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
+++ b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_restore_erepair.C,v 1.13 2013/06/11 12:25:18 varkeykv Exp $
+// $Id: io_restore_erepair.C,v 1.15 2013/08/06 14:15:48 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -65,7 +65,9 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
 {
   ReturnCode rc;
   ecmdDataBufferBase data_one(16);
-  ecmdDataBufferBase data_two(16);
+  ecmdDataBufferBase data_two(16);

+  ecmdDataBufferBase data_one1(16);

+  ecmdDataBufferBase data_two2(16);
   ecmdDataBufferBase mode_reg(16);
   ecmdDataBufferBase mask(16);
   bool msbswap=false;
@@ -119,7 +121,7 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
   
   // This is specially for Cronus/Lab 
   if(tx_lanes.size()==0 && rx_lanes.size()==0){
-    rc=erepairGetFailedLanes(target,tx_lanes,rx_lanes); 
+   // rc=erepairGetFailedLanes(target,tx_lanes,rx_lanes); 
     //FAPI_EXEC_HWP(rc,erepairGetFailedLanesHwp,target,tx_lanes,rx_lanes);
     if(!rc.ok()){
       FAPI_ERR("Accessor HWP has returned a fail");
@@ -132,7 +134,15 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
     for(uint8_t clock_group=start_group;clock_group<=end_group;++clock_group){
       //Collect the TX bad lanes into a single buffer
       rc_ecmd|=data_one.flushTo0();
-      rc_ecmd|=data_two.flushTo0();
+      rc_ecmd|=data_two.flushTo0();

+      

+      // Read in values for RMW 

+      rc = GCR_read( target,interface,tx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one);

+      if(rc){return rc;}

+      rc = GCR_read( target,interface,tx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two);

+      if(rc){return rc;}

+      

+

       
       if(rc_ecmd)
       {
@@ -163,30 +173,28 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
       for(uint8_t i=0;i<tx_lanes.size();++i){
         if(msbswap){

           //assume that MSB-LSB swap exists only on A or MC bus 
-                  lane=end_lane-tx_lanes[i];
+                  lane=end_lane-tx_lanes[i];

+                  FAPI_DBG("Corrected lane is  %d\n",lane);
         }
         else{

-          // Do lane number shifting for X bus

-        if(interface==CP_FABRIC_X0){

-              if(clock_group==0){

-                lane=0;

-              }

-              else if(clock_group==1){

-                lane=20;

-              }

-              else if(clock_group==2){

-                lane=40;

-              }

-              else if(clock_group==3){

-                lane=60;

-              }

-        }

-          if(interface==CP_FABRIC_X0){
-              lane-=tx_lanes[i];

-          }

-          else{

-            lane=tx_lanes[i];

-          }
+              // Do lane number shifting for X bus

+            if(interface==CP_FABRIC_X0){

+                  if(clock_group==0 && tx_lanes[i]<20){

+                    lane=tx_lanes[i];

+                  }

+                  else if(clock_group==1 && (tx_lanes[i]>19 && tx_lanes[i]<40)){

+                    lane=tx_lanes[i]-20;

+                  }

+                  else if(clock_group==2 && (tx_lanes[i]>39 && tx_lanes[i]<60)){

+                    lane=tx_lanes[i]-40;

+                  }

+                  else if(clock_group==3 && (tx_lanes[i]>59 && tx_lanes[i]<80) ){

+                    lane=tx_lanes[i]-60;

+                  }

+            }

+            else{

+              lane=tx_lanes[i];

+            }
         }
           if (lane < 16) {
              data_one.setBit(lane);
@@ -195,12 +203,15 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
              data_two.setBit(lane-16);
           }
       }
-      //Now write the bad lanes on TX side on this target
+      //Now write the bad lanes on TX side on this target

+      FAPI_DBG("#2 Corrected TX lane is  %d\n",lane);

+
       rc = GCR_write( target, interface, tx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one,mask );
       if(rc){return rc;}
       rc = GCR_write( target, interface, tx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two,mask);
       if(rc){return rc;}
-
+

+      
       rc_ecmd|=data_one.flushTo0();
       rc_ecmd|=data_two.flushTo0();
       
@@ -208,45 +219,61 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
       {
           rc.setEcmdError(rc_ecmd);
           return(rc);
-      }
+      }

+      

+      // Read in original data

+      

+      rc = GCR_read( target,interface,rx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one);

+      if(rc){return rc;}

+      rc = GCR_read( target,interface,rx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two);

+      if(rc){return rc;}

+      

+      // Read in values for RMW 

+      rc = GCR_read( target,interface,rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one1);

+      if(rc){return rc;}

+      rc = GCR_read( target,interface,rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two2);

+      if(rc){return rc;}

+      
       // RX lane records 
       // Set the RX bad lanes in the buffer 
       for(uint8_t i=0;i<rx_lanes.size();++i){

         

-        if(interface==CP_FABRIC_X0){

-              if(clock_group==0){

-                lane=0;

-              }

-              else if(clock_group==1){

-                lane=20;

-              }

-              else if(clock_group==2){

-                lane=40;

-              }

-              else if(clock_group==3){

-                lane=60;

-              }

-              lane-=rx_lanes[i];

-        }

-        else{

-          lane=rx_lanes[i];

-        }
+            if(interface==CP_FABRIC_X0){

+                  if(clock_group==0 && rx_lanes[i]<20){

+                    lane=rx_lanes[i];

+                  }

+                  else if(clock_group==1 && (rx_lanes[i]>19 && rx_lanes[i]<40)){

+                    lane=rx_lanes[i]-20;

+                  }

+                  else if(clock_group==2 && (rx_lanes[i]>39 && rx_lanes[i]<60)){

+                    lane=rx_lanes[i]-40;

+                  }

+                  else if(clock_group==3 && (rx_lanes[i]>59 && rx_lanes[i]<80) ){

+                    lane=rx_lanes[i]-60;

+                  }

+            }

+            else{

+              lane=rx_lanes[i];

+            }
           if (lane < 16) {
-             data_one.setBit(lane);
+             data_one.setBit(lane);

+             data_one1.setBit(lane);
           }
           else {
-             data_two.setBit(lane-16);
+             data_two.setBit(lane-16);

+             data_two2.setBit(lane-16);
           }
-      }
+      }

+       FAPI_DBG("#2 Corrected RX lane is  %d\n",lane);
       //Now write the bad lanes in one shot on the slave side RX
       rc = GCR_write( target, interface, rx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one,mask );
       if(rc){return rc;}
       rc = GCR_write( target, interface, rx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two,mask);
       if(rc){return rc;}
       //Now write the bad lanes in one shot on the slave side RX
-      rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one,mask );
+      rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one1,mask );
       if(rc){return rc;}
-      rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two,mask);
+      rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two2,mask);
       if(rc){return rc;}