Hostboot - Updated HWPs from defect SW219606 (week 8/13)

SW219606

Change-Id: I9eee6d20610412764a0ad3ed406633426f154b2f
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/5971
Tested-by: Jenkins Server
Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

6 files changed, 139 insertions, 72 deletions

diff --git a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
index 4821e2a31..e3aea2740 100644
--- a/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
+++ b/src/usr/hwpf/hwp/bus_training/io_clear_firs.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_clear_firs.H,v 1.7 2013/03/26 14:45:18 jaswamin Exp $
+// $Id: io_clear_firs.H,v 1.8 2013/08/01 12:57:19 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 2012, 2013
 // *!           All Rights Reserved -- Property of IBM
@@ -110,6 +110,18 @@ const uint32_t fir_clear_mask_reg_addr[FIR_INTERFACES]={0x04011004,
                                                   0x02011a04, 
                                                   0x02011e04, 
                                                   0x02010404  };
+// This is for Centaur Reconfig loop IO_CLEANUP  procedure
+const uint32_t scom_mode_pb_reg_addr[FIR_INTERFACES] ={ 0x04011020,
+                                                       0x04011420,
+                                                       0x04011C20,
+                                                       0x04011820,
+                                                       0x08010C20,
+                                                       0x02011A20,
+                                                       0x02011E20,
+                                                       0x02010420};
+    
+    
+    
                                                   
 
 enum fir_error_type{
diff --git a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
index 7ded82f58..42d327273 100644
--- a/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
+++ b/src/usr/hwpf/hwp/bus_training/io_restore_erepair.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: io_restore_erepair.C,v 1.13 2013/06/11 12:25:18 varkeykv Exp $
+// $Id: io_restore_erepair.C,v 1.15 2013/08/06 14:15:48 varkeykv Exp $
 // *!***************************************************************************
 // *! (C) Copyright International Business Machines Corp. 1997, 1998
 // *!           All Rights Reserved -- Property of IBM
@@ -65,7 +65,9 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
 {
   ReturnCode rc;
   ecmdDataBufferBase data_one(16);
-  ecmdDataBufferBase data_two(16);
+  ecmdDataBufferBase data_two(16);

+  ecmdDataBufferBase data_one1(16);

+  ecmdDataBufferBase data_two2(16);
   ecmdDataBufferBase mode_reg(16);
   ecmdDataBufferBase mask(16);
   bool msbswap=false;
@@ -119,7 +121,7 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
   
   // This is specially for Cronus/Lab 
   if(tx_lanes.size()==0 && rx_lanes.size()==0){
-    rc=erepairGetFailedLanes(target,tx_lanes,rx_lanes); 
+   // rc=erepairGetFailedLanes(target,tx_lanes,rx_lanes); 
     //FAPI_EXEC_HWP(rc,erepairGetFailedLanesHwp,target,tx_lanes,rx_lanes);
     if(!rc.ok()){
       FAPI_ERR("Accessor HWP has returned a fail");
@@ -132,7 +134,15 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
     for(uint8_t clock_group=start_group;clock_group<=end_group;++clock_group){
       //Collect the TX bad lanes into a single buffer
       rc_ecmd|=data_one.flushTo0();
-      rc_ecmd|=data_two.flushTo0();
+      rc_ecmd|=data_two.flushTo0();

+      

+      // Read in values for RMW 

+      rc = GCR_read( target,interface,tx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one);

+      if(rc){return rc;}

+      rc = GCR_read( target,interface,tx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two);

+      if(rc){return rc;}

+      

+

       
       if(rc_ecmd)
       {
@@ -163,30 +173,28 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
       for(uint8_t i=0;i<tx_lanes.size();++i){
         if(msbswap){

           //assume that MSB-LSB swap exists only on A or MC bus 
-                  lane=end_lane-tx_lanes[i];
+                  lane=end_lane-tx_lanes[i];

+                  FAPI_DBG("Corrected lane is  %d\n",lane);
         }
         else{

-          // Do lane number shifting for X bus

-        if(interface==CP_FABRIC_X0){

-              if(clock_group==0){

-                lane=0;

-              }

-              else if(clock_group==1){

-                lane=20;

-              }

-              else if(clock_group==2){

-                lane=40;

-              }

-              else if(clock_group==3){

-                lane=60;

-              }

-        }

-          if(interface==CP_FABRIC_X0){
-              lane-=tx_lanes[i];

-          }

-          else{

-            lane=tx_lanes[i];

-          }
+              // Do lane number shifting for X bus

+            if(interface==CP_FABRIC_X0){

+                  if(clock_group==0 && tx_lanes[i]<20){

+                    lane=tx_lanes[i];

+                  }

+                  else if(clock_group==1 && (tx_lanes[i]>19 && tx_lanes[i]<40)){

+                    lane=tx_lanes[i]-20;

+                  }

+                  else if(clock_group==2 && (tx_lanes[i]>39 && tx_lanes[i]<60)){

+                    lane=tx_lanes[i]-40;

+                  }

+                  else if(clock_group==3 && (tx_lanes[i]>59 && tx_lanes[i]<80) ){

+                    lane=tx_lanes[i]-60;

+                  }

+            }

+            else{

+              lane=tx_lanes[i];

+            }
         }
           if (lane < 16) {
              data_one.setBit(lane);
@@ -195,12 +203,15 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
              data_two.setBit(lane-16);
           }
       }
-      //Now write the bad lanes on TX side on this target
+      //Now write the bad lanes on TX side on this target

+      FAPI_DBG("#2 Corrected TX lane is  %d\n",lane);

+
       rc = GCR_write( target, interface, tx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one,mask );
       if(rc){return rc;}
       rc = GCR_write( target, interface, tx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two,mask);
       if(rc){return rc;}
-
+

+      
       rc_ecmd|=data_one.flushTo0();
       rc_ecmd|=data_two.flushTo0();
       
@@ -208,45 +219,61 @@ ReturnCode io_restore_erepair(const Target& target,std::vector<uint8_t> &tx_lane
       {
           rc.setEcmdError(rc_ecmd);
           return(rc);
-      }
+      }

+      

+      // Read in original data

+      

+      rc = GCR_read( target,interface,rx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one);

+      if(rc){return rc;}

+      rc = GCR_read( target,interface,rx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two);

+      if(rc){return rc;}

+      

+      // Read in values for RMW 

+      rc = GCR_read( target,interface,rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one1);

+      if(rc){return rc;}

+      rc = GCR_read( target,interface,rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two2);

+      if(rc){return rc;}

+      
       // RX lane records 
       // Set the RX bad lanes in the buffer 
       for(uint8_t i=0;i<rx_lanes.size();++i){

         

-        if(interface==CP_FABRIC_X0){

-              if(clock_group==0){

-                lane=0;

-              }

-              else if(clock_group==1){

-                lane=20;

-              }

-              else if(clock_group==2){

-                lane=40;

-              }

-              else if(clock_group==3){

-                lane=60;

-              }

-              lane-=rx_lanes[i];

-        }

-        else{

-          lane=rx_lanes[i];

-        }
+            if(interface==CP_FABRIC_X0){

+                  if(clock_group==0 && rx_lanes[i]<20){

+                    lane=rx_lanes[i];

+                  }

+                  else if(clock_group==1 && (rx_lanes[i]>19 && rx_lanes[i]<40)){

+                    lane=rx_lanes[i]-20;

+                  }

+                  else if(clock_group==2 && (rx_lanes[i]>39 && rx_lanes[i]<60)){

+                    lane=rx_lanes[i]-40;

+                  }

+                  else if(clock_group==3 && (rx_lanes[i]>59 && rx_lanes[i]<80) ){

+                    lane=rx_lanes[i]-60;

+                  }

+            }

+            else{

+              lane=rx_lanes[i];

+            }
           if (lane < 16) {
-             data_one.setBit(lane);
+             data_one.setBit(lane);

+             data_one1.setBit(lane);
           }
           else {
-             data_two.setBit(lane-16);
+             data_two.setBit(lane-16);

+             data_two2.setBit(lane-16);
           }
-      }
+      }

+       FAPI_DBG("#2 Corrected RX lane is  %d\n",lane);
       //Now write the bad lanes in one shot on the slave side RX
       rc = GCR_write( target, interface, rx_lane_disabled_vec_0_15_pg, clock_group,  0,  data_one,mask );
       if(rc){return rc;}
       rc = GCR_write( target, interface, rx_lane_disabled_vec_16_31_pg, clock_group,  0,  data_two,mask);
       if(rc){return rc;}
       //Now write the bad lanes in one shot on the slave side RX
-      rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one,mask );
+      rc = GCR_write( target, interface, rx_lane_bad_vec_0_15_pg, clock_group,  0,  data_one1,mask );
       if(rc){return rc;}
-      rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two,mask);
+      rc = GCR_write( target, interface, rx_lane_bad_vec_16_31_pg, clock_group,  0,  data_two2,mask);
       if(rc){return rc;}
 
 
diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
index 85c64f1e0..843c6fc59 100755
--- a/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit/mss_draminit.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: mss_draminit.C,v 1.51 2013/08/01 18:36:52 jdsloat Exp $
+// $Id: mss_draminit.C,v 1.52 2013/08/07 14:31:53 jdsloat Exp $
 //------------------------------------------------------------------------------
 // Don't forget to create CVS comments when you check in your changes!
 //------------------------------------------------------------------------------
@@ -28,6 +28,7 @@
 //------------------------------------------------------------------------------
 // Version:|  Author: |  Date:  | Comment:
 //---------|----------|---------|-----------------------------------------------
+//  1.52   | jdsloat  | 08/07/13| Added a single rc_num check and edited a debug/error message to make firmware happy.
 //  1.51   | jdsloat  | 08/01/13| Fixed dimm/rank conversion in address mirroring phy setting for a 4 rank dimm scenario
 //  1.50   | mwuu     | 07/17/13| Fixed CS when accessing RCD words on 1 rank RDIMMs
 //         |          |         | Added checks for invalid RTT_NOM, RTT_WR
@@ -981,6 +982,14 @@ ReturnCode mss_rcd_load(
 
                 // Send out to the CCS array
                 rc_num = rc_num | num_idles_16.insertFromRight((uint32_t) 12, 0, 16);
+
+	        if (rc_num)
+	        {
+	           FAPI_ERR( "mss_rcd_load: Error setting up buffers");
+	           rc_buff.setEcmdError(rc_num);
+	           return rc_buff;
+	        }
+
                 rc = mss_ccs_inst_arry_0( i_target,
                                           io_ccs_inst_cnt,
                                           address_16,
@@ -1464,7 +1473,7 @@ ReturnCode mss_mrs_load(
                     }
                     else
                     {
-                        FAPI_ERR( "mss_mrs_load: Error determining ATTR_EFF_DRAM_RTT_NOM value from attribute");
+                        FAPI_ERR( "mss_mrs_load: Error determining ATTR_EFF_DRAM_RTT_NOM value: %d from attribute", dram_rtt_nom[i_port_number][dimm_number][rank_number]);
                         FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
                         return rc;
                     }
@@ -1507,9 +1516,9 @@ ReturnCode mss_mrs_load(
                     {
                         dram_rtt_wr[i_port_number][dimm_number][rank_number] = 0x40;
                     }
-					else
-					{
-                        FAPI_ERR( "mss_mrs_load: Error determining ATTR_EFF_DRAM_RTT_WR value from attribute");
+		    else
+		    {
+                        FAPI_ERR( "mss_mrs_load: Error determining ATTR_EFF_DRAM_RTT_WR value: %d from attribute", dram_rtt_wr[i_port_number][dimm_number][rank_number]);
                         FAPI_SET_HWP_ERROR(rc, RC_MSS_IMP_INPUT_ERROR);
                         return rc;
                     }
diff --git a/src/usr/hwpf/hwp/include/p8_scom_addresses.H b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
index b7cdba757..4f55a0c05 100755
--- a/src/usr/hwpf/hwp/include/p8_scom_addresses.H
+++ b/src/usr/hwpf/hwp/include/p8_scom_addresses.H
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: p8_scom_addresses.H,v 1.159 2013/06/28 16:50:17 stillgs Exp $
+// $Id: p8_scom_addresses.H,v 1.161 2013/08/21 15:11:23 gweber Exp $
 // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/p8_scom_addresses.H,v $
 //------------------------------------------------------------------------------
 // *! (C) Copyright International Business Machines Corp. 2011
@@ -148,11 +148,11 @@ CONST_UINT64_T( DEVICE_ID_REG_0x000F000F            , ULL(0x000F000F) );
  //------------------------------------------------------------------------------
  //      MULTICAST REGISTER DEFINITION
  //------------------------------------------------------------------------------
- CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_RWx690F0103                             , ULL(0x690F0103) );       
- CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_WANDx690F0104                           , ULL(0x690F0104) );       
- CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105                            , ULL(0x690F0105) );       
- CONST_UINT64_T( WRITE_ALL_PCBSPM_MODE_REG_0x690F0156                             , ULL(0x690F0156) );       
- CONST_UINT64_T( WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D            , ULL(0x690F015D) );       
+ CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_RWx690F0103                             , ULL(0x690F0103) );
+ CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_WANDx690F0104                           , ULL(0x690F0104) );
+ CONST_UINT64_T( WRITE_ALL_EX_PMGP1_REG_0_WORx690F0105                            , ULL(0x690F0105) );
+ CONST_UINT64_T( WRITE_ALL_PCBSPM_MODE_REG_0x690F0156                             , ULL(0x690F0156) );
+ CONST_UINT64_T( WRITE_ALL_PCBS_Power_Management_Bounds_Reg_0x690F015D            , ULL(0x690F015D) );
 
 
 //------------------------------------------------------------------------------
@@ -165,6 +165,8 @@ CONST_UINT32_T( CFAM_FSI_GP6_0x00002815               , ULL(0x00002815) );
 CONST_UINT32_T( CFAM_FSI_GP7_0x00002816               , ULL(0x00002816) );
 CONST_UINT32_T( CFAM_FSI_GP8_0x00002817               , ULL(0x00002817) );
 CONST_UINT32_T( CFAM_FSI_WRITE_PROTECT_0x00002818     , ULL(0x00002818) );
+CONST_UINT32_T( CFAM_OSCSW_SENSE1_0x00002819          , ULL(0x00002819) );
+CONST_UINT32_T( CFAM_OSCSW_SENSE2_0x0000281A          , ULL(0x0000281A) );
 CONST_UINT32_T( CFAM_FSI_GP3_MIRROR_0x0000281B        , ULL(0x0000281B) );
 CONST_UINT32_T( CFAM_FSI_SBE_VITAL_0x0000281C         , ULL(0x0000281C) );
 
@@ -1556,6 +1558,10 @@ CONST_UINT64_T( EX_NCU_FIR_OR_REG_0x10010C02           , ULL(0x10010C02) );
 CONST_UINT64_T( EX_NCU_FIR_MASK_REG_0x10010C03         , ULL(0x10010C03) );
 CONST_UINT64_T( EX_NCU_FIR_ACTION0_REG_0x10010C06      , ULL(0x10010C06) );
 CONST_UINT64_T( EX_NCU_FIR_ACTION1_REG_0x10010C07      , ULL(0x10010C07) );
+CONST_UINT64_T( EX_NCU_MODE_REG_0x10010C0A             , ULL(0x10010C0A) );
+
+//CHTM
+CONST_UINT64_T( EX_CHTM_MODE_REG_0x10011000            , ULL(0x10011000) );
 
 //L2
 CONST_UINT64_T( EX_L2_FIR_REG_0x10012800              , ULL(0x10012800) );
@@ -1729,11 +1735,11 @@ CONST_UINT64_T( EX_PERV_LFIR_ACT1_0x10040011          , ULL(0x10040011) );
 //      EX THERMAL
 //------------------------------------------------------------------------------
 CONST_UINT64_T( EX_THERM_0x10050000                   , ULL(0x10050000) );
-CONST_UINT64_T( EX_THERM_DTS_RESULT0_0x10050000       , ULL(0x10050000) ); 
-CONST_UINT64_T( EX_THERM_DTS_RESULT1_0x10050001       , ULL(0x10050001) ); 
-CONST_UINT64_T( EX_THERM_MODE_REG_0x1005000F          , ULL(0x1005000F) ); 
-CONST_UINT64_T( EX_THERM_CONTROL_REG_0x10050012       , ULL(0x10050012) ); 
-CONST_UINT64_T( EX_THERM_ERR_STATUS_REG_0x10050013    , ULL(0x10050013) ); 
+CONST_UINT64_T( EX_THERM_DTS_RESULT0_0x10050000       , ULL(0x10050000) );
+CONST_UINT64_T( EX_THERM_DTS_RESULT1_0x10050001       , ULL(0x10050001) );
+CONST_UINT64_T( EX_THERM_MODE_REG_0x1005000F          , ULL(0x1005000F) );
+CONST_UINT64_T( EX_THERM_CONTROL_REG_0x10050012       , ULL(0x10050012) );
+CONST_UINT64_T( EX_THERM_ERR_STATUS_REG_0x10050013    , ULL(0x10050013) );
 CONST_UINT64_T( EX_CPM_CONFIG_WRITE_REG0_0x10050000   , ULL(0x10050000) );
 CONST_UINT64_T( EX_CPM_CONFIG_WRITE_REG1_0x10050001   , ULL(0x10050001) );
 CONST_UINT64_T( EX_CPM_RAW_RESULT0_10050005           , ULL(0x10050005) );
@@ -1960,6 +1966,13 @@ This section is automatically updated by CVS when you check in this file.
 Be sure to create CVS comments when you commit so that they can be included here.
 
 $Log: p8_scom_addresses.H,v $
+Revision 1.161  2013/08/21 15:11:23  gweber
+added CFAM_OSCSW_SENSE1,2
+
+Revision 1.160  2013/08/08 02:48:33  stillgs
+
+Add NCU and CHTM mode registers
+
 Revision 1.159  2013/06/28 16:50:17  stillgs
 
 Adde PBAX Push Control/Status 1 registers for pba_init -reset
diff --git a/src/usr/hwpf/hwp/memory_attributes.xml b/src/usr/hwpf/hwp/memory_attributes.xml
index 9d07533f3..1f140743a 100644
--- a/src/usr/hwpf/hwp/memory_attributes.xml
+++ b/src/usr/hwpf/hwp/memory_attributes.xml
@@ -21,7 +21,7 @@
 <!--                                                                        -->
 <!-- IBM_PROLOG_END_TAG                                                     -->
 <attributes>
-<!-- $Id: memory_attributes.xml,v 1.82 2013/08/05 21:40:04 bellows Exp $ -->
+<!-- $Id: memory_attributes.xml,v 1.83 2013/08/12 20:40:29 bellows Exp $ -->
 <!-- DO NOT EDIT THIS FILE DIRECTLY PLEASE UPDATE THE ODS FILE AND FOLLOW THE INSTRUCTION TAB -->
 <!-- PLEASE SEE MARK BELLOWS (BELLOWS.IBM.COM) OR OTHERS ON MEMORY TEAM FOR HELP -->
 <!-- *********************************************************************** -->
@@ -3562,6 +3562,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint32</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 
 <attribute>
@@ -3571,6 +3572,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint32</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 
 <attribute>
@@ -3580,6 +3582,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint8</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 
 <attribute>
@@ -3589,6 +3592,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint8</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 
 <attribute>
@@ -3598,6 +3602,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint8</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 
 <attribute>
@@ -3607,6 +3612,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint8</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 
 <attribute>
@@ -3616,6 +3622,7 @@ will originates from VPD for custom DIMMs in the MW keyword byte 5 (MSB is on th
     <valueType>uint8</valueType>
     <platInit/>
     <odmVisable/>
+    <array>2</array>
 </attribute>
 -->
 
diff --git a/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C b/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C
index e44dd3f86..d3ce8f475 100644
--- a/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C
+++ b/src/usr/hwpf/hwp/sbe_centaur_init/cen_xip_customize.C
@@ -20,7 +20,7 @@
 /* Origin: 30                                                             */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
-// $Id: cen_xip_customize.C,v 1.10 2013/03/28 00:21:54 cmolsen Exp $
+// $Id: cen_xip_customize.C,v 1.11 2013/08/12 20:05:18 dcrowell Exp $
 /*------------------------------------------------------------------------------*/
 /* *! TITLE : cen_xip_customize.C                                               */
 /* *! DESCRIPTION : Customizes Centaur images from a Centaur reference image.   */
@@ -37,7 +37,6 @@
 //
 /*------------------------------------------------------------------------------*/
 #define __CEN_XIP_CUSTOMIZE_C
-#include <HvPlicModule.H>
 #include <cen_xip_customize.H>
 #include <p8_delta_scan_rw.h>
 #include <p8_pore_table_gen_api.H>