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author | Christian Geddes <crgeddes@us.ibm.com> | 2019-04-25 13:04:51 -0500 |
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committer | Daniel M. Crowell <dcrowell@us.ibm.com> | 2019-05-14 14:54:03 -0500 |
commit | b95951684667a2d77a76e589505e4250a0f02751 (patch) | |
tree | 45117e7be05d6b04787717bcb95b818d0f3d8a75 /src/usr/hwas/common/hwas.C | |
parent | 7ddeb4b85db8f85f1ddffcda0943efeba58e20f9 (diff) | |
download | talos-hostboot-b95951684667a2d77a76e589505e4250a0f02751.tar.gz talos-hostboot-b95951684667a2d77a76e589505e4250a0f02751.zip |
Force Axone simics to read all VPD from HW with config flags
This commit will set the config flags to always read from HW
rather than the old VPD cache in PNOR. Until this point in Axone
we were still using an old copy of MVPD that we write into PNOR
during the startup simics scripts. From this commit onward we will
use the actual VPD simics provides. To handle this, some updates
we needed to the PG rules for Axone.
Change-Id: Ie06cefe1aec37edfc4c379ee1173bc51fc6bbe1f
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/76519
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Matt Derksen <mderkse1@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Diffstat (limited to 'src/usr/hwas/common/hwas.C')
-rw-r--r-- | src/usr/hwas/common/hwas.C | 15 |
1 files changed, 11 insertions, 4 deletions
diff --git a/src/usr/hwas/common/hwas.C b/src/usr/hwas/common/hwas.C index f0ce3ed04..580d6ef60 100644 --- a/src/usr/hwas/common/hwas.C +++ b/src/usr/hwas/common/hwas.C @@ -970,6 +970,13 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, uint16_t l_xbus = (l_model == MODEL_NIMBUS) ? VPD_CP00_PG_XBUS_GOOD_NIMBUS : VPD_CP00_PG_XBUS_GOOD_CUMULUS; + uint16_t l_perv = (l_model == MODEL_AXONE) ? + VPD_CP00_PG_PERVASIVE_GOOD_AXONE : VPD_CP00_PG_PERVASIVE_GOOD; + + uint16_t l_n2 = (l_model == MODEL_AXONE) ? + VPD_CP00_PG_N2_GOOD_AXONE : VPD_CP00_PG_N2_GOOD; + + // Check all bits in FSI entry if (i_pgData[VPD_CP00_PG_FSI_INDEX] != VPD_CP00_PG_FSI_GOOD) @@ -985,14 +992,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, else // Check all bits in PRV entry if (i_pgData[VPD_CP00_PG_PERVASIVE_INDEX] != - VPD_CP00_PG_PERVASIVE_GOOD) + l_perv) { HWAS_INF("pTarget %.8X - Pervasive pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_target->getAttr<ATTR_HUID>(), VPD_CP00_PG_PERVASIVE_INDEX, i_pgData[VPD_CP00_PG_PERVASIVE_INDEX], - VPD_CP00_PG_PERVASIVE_GOOD); + l_perv); l_chipFunctional = false; } else @@ -1022,14 +1029,14 @@ bool isChipFunctional(const TARGETING::TargetHandle_t &i_target, } else // Check all bits in N2 entry - if (i_pgData[VPD_CP00_PG_N2_INDEX] != VPD_CP00_PG_N2_GOOD) + if (i_pgData[VPD_CP00_PG_N2_INDEX] != l_n2) { HWAS_INF("pTarget %.8X - N2 pgData[%d]: " "actual 0x%04X, expected 0x%04X - bad", i_target->getAttr<ATTR_HUID>(), VPD_CP00_PG_N2_INDEX, i_pgData[VPD_CP00_PG_N2_INDEX], - VPD_CP00_PG_N2_GOOD); + l_n2); l_chipFunctional = false; } else |