Initial port of PRD to Hostboot

Change-Id: I7ee2673131d4891d482e99a403a36300b79e547e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1853
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>

1 files changed, 458 insertions, 0 deletions

diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule
new file mode 100644
index 000000000..baf284fd8
--- /dev/null
+++ b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule
@@ -0,0 +1,458 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+# 
+# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule $
+# 
+# IBM CONFIDENTIAL
+# 
+# COPYRIGHT International Business Machines Corp. 2012
+# 
+# p1
+# 
+# Object Code Only (OCO) source materials
+# Licensed Internal Code Source Materials
+# IBM HostBoot Licensed Internal Code
+# 
+# The source code for this program is not published or otherwise
+# divested of its trade secrets, irrespective of what has been
+# deposited with the U.S. Copyright Office.
+# 
+# Origin: 30
+# 
+# IBM_PROLOG_END_TAG 
+
+    ############################################################################
+    # NEST Chiplet Registers
+    ############################################################################
+
+    register NEST_CHIPLET_CS_FIR
+    {
+        name        "TCN.XFIR";
+        scomaddr    0x02040000;
+        capture     group default;
+    };
+
+    register NEST_CHIPLET_RE_FIR
+    {
+        name        "TCN.RFIR";
+        scomaddr    0x02040001;
+        capture     group default;
+    };
+
+    register NEST_CHIPLET_FIR_MASK
+    {
+        name        "TCN.FIR_MASK";
+        scomaddr    0x02040002;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet LFIR
+    ############################################################################
+
+    register NEST_LFIR
+    {
+        name        "TCN.LOCAL_FIR";
+        scomaddr    0x0204000a;
+        reset       (&, 0x0204000b);
+        mask        (|, 0x0204000f);
+        capture     group default;
+    };
+
+    register NEST_LFIR_MASK
+    {
+        name        "TCN.EPS.FIR.LOCAL_FIR_MASK";
+        scomaddr    0x0204000d;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register NEST_LFIR_ACT0
+    {
+        name        "TCN.EPS.FIR.LOCAL_FIR_ACTION0";
+        scomaddr    0x02040010;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register NEST_LFIR_ACT1
+    {
+        name        "TCN.EPS.FIR.LOCAL_FIR_ACTION1";
+        scomaddr    0x02040011;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet DMIFIR
+    ############################################################################
+
+    register DMIFIR
+    {
+        name        "DMI.BUSCTL.SCOM.FIR_REG";
+        scomaddr    0x02010400;
+        reset       (&, 0x02010401);
+        mask        (|, 0x02010405);
+        capture     group default;
+    };
+
+    register DMIFIR_MASK
+    {
+        name        "DMI.BUSCTL.SCOM.FIR_MASK_REG";
+        scomaddr    0x02010403;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register DMIFIR_ACT0
+    {
+        name        "DMI.BUSCTL.SCOM.FIR_ACTION0_REG";
+        scomaddr    0x02010406;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register DMIFIR_ACT1
+    {
+        name        "DMI.BUSCTL.SCOM.FIR_ACTION1_REG";
+        scomaddr    0x02010407;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MBIFIR
+    ############################################################################
+
+    register MBIFIR
+    {
+        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRQ";
+        scomaddr    0x02010800;
+        reset       (&, 0x02010801);
+        mask        (|, 0x02010805);
+        capture     group default;
+    };
+
+    register MBIFIR_MASK
+    {
+        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRMASK";
+        scomaddr    0x02010803;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBIFIR_ACT0
+    {
+        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRACT0";
+        scomaddr    0x02010806;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBIFIR_ACT1
+    {
+        name        "MBU.MBI.MBI.SCOMFIR.MBIFIRACT1";
+        scomaddr    0x02010807;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MBSFIR
+    ############################################################################
+
+    register MBSFIR
+    {
+        name        "MBU.MBS.MBS_FIR_REG";
+        scomaddr    0x02011400;
+        reset       (&, 02011401);
+        mask        (|, 02011405);
+        capture     group default;
+    };
+
+    register MBSFIR_MASK
+    {
+        name        "MBU.MBS.MBS_FIR_MASK_REG";
+        scomaddr    0x02011403;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSFIR_ACT0
+    {
+        name        "MBU.MBS.MBS_FIR_ACTION0_REG";
+        scomaddr    0x02011406;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSFIR_ACT1
+    {
+        name        "MBU.MBS.MBS_FIR_ACTION1_REG";
+        scomaddr    0x02011407;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MBSECC01FIR
+    ############################################################################
+
+    register MBSECC01FIR
+    {
+        name        "MBU.MBS.ECC01.MBECCFIR";
+        scomaddr    0x02011440;
+        reset       (&, 02011441);
+        mask        (|, 02011445);
+        capture     group default;
+    };
+
+    register MBSECC01FIR_MASK
+    {
+        name        "MBU.MBS.ECC01.MBECCFIR_MASK";
+        scomaddr    0x02011443;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSECC01FIR_ACT0
+    {
+        name        "MBU.MBS.ECC01.MBECCFIR_ACTION0";
+        scomaddr    0x02011446;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSECC01FIR_ACT1
+    {
+        name        "MBU.MBS.ECC01.MBECCFIR_ACTION1";
+        scomaddr    0x02011447;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MBSECC23FIR
+    ############################################################################
+
+    register MBSECC23FIR
+    {
+        name        "MBU.MBS.ECC23.MBECCFIR";
+        scomaddr    0x02011480;
+        reset       (&, 02011481);
+        mask        (|, 02011485);
+        capture     group default;
+    };
+
+    register MBSECC23FIR_MASK
+    {
+        name        "MBU.MBS.ECC23.MBECCFIR_MASK";
+        scomaddr    0x02011483;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSECC23FIR_ACT0
+    {
+        name        "MBU.MBS.ECC23.MBECCFIR_ACTION0";
+        scomaddr    0x02011486;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSECC23FIR_ACT1
+    {
+        name        "MBU.MBS.ECC23.MBECCFIR_ACTION0";
+        scomaddr    0x02011487;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MCBIST01FIR
+    ############################################################################
+
+    register MCBIST01FIR
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRQ";
+        scomaddr    0x02011600;
+        reset       (&, 0x02011601);
+        mask        (|, 0x02011605);
+        capture     group default;
+    };
+
+    register MCBIST01FIR_MASK
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRMASK";
+        scomaddr    0x02011603;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MCBIST01FIR_ACT0
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION0";
+        scomaddr    0x02011606;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MCBIST01FIR_ACT1
+    {
+        name        "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION1";
+        scomaddr    0x02011607;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MCBIST23FIR
+    ############################################################################
+
+    register MCBIST23FIR
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRQ";
+        scomaddr    0x02011700;
+        reset       (&, 0x02011701);
+        mask        (|, 0x02011705);
+        capture     group default;
+    };
+
+    register MCBIST23FIR_MASK
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRMASK";
+        scomaddr    0x02011703;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MCBIST23FIR_ACT0
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION0";
+        scomaddr    0x02011706;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MCBIST23FIR_ACT1
+    {
+        name        "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION1";
+        scomaddr    0x02011707;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet NESTFBISTFIR
+    ############################################################################
+
+    register NESTFBISTFIR
+    {
+        name        "FBIST.FBN.FBN_FIR_REG";
+        scomaddr    0x02010880;
+        reset       (&, 0x02010881);
+        mask        (|, 0x02010885);
+        capture     group default;
+    };
+
+    register NESTFBISTFIR_MASK
+    {
+        name        "FBIST.FBN.FBN_FIR_MASK_REG";
+        scomaddr    0x02010883;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register NESTFBISTFIR_ACT0
+    {
+        name        "FBIST.FBN.FBN_FIR_ACTION0_REG";
+        scomaddr    0x02010886;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register NESTFBISTFIR_ACT1
+    {
+        name        "FBIST.FBN.FBN_FIR_ACTION1_REG";
+        scomaddr    0x02010887;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet SENSORCACHEFIR
+    ############################################################################
+
+    register SENSORCACHEFIR
+    {
+        name        "SCAC.SCAC_LFIR";
+        scomaddr    0x020115c0;
+        reset       (&, 0x020115c1);
+        mask        (|, 0x020115c5);
+        capture     group default;
+    };
+
+    register SENSORCACHEFIR_MASK
+    {
+        name        "SCAC.SCAC_FIRMASK";
+        scomaddr    0x020115c3;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register SENSORCACHEFIR_ACT0
+    {
+        name        "SCAC.SCAC_FIRACTION0";
+        scomaddr    0x020115c6;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register SENSORCACHEFIR_ACT1
+    {
+        name        "SCAC.SCAC_FIRACTION1";
+        scomaddr    0x020115c7;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    ############################################################################
+    # NEST Chiplet MBSSECUREFIR
+    ############################################################################
+
+    register MBSSECUREFIR
+    {
+        name        "MBU.MBS.ARB.RXLT.MBSSIRQ";
+        scomaddr    0x0201141e;
+        reset       (&, 0x0201141f);
+        # This is a special register in which we are not able to mask. All bits
+        # in this register should be set to checkstop so we will not need to
+        # mask anyway.
+        capture     group default;
+    };
+
+    register MBSSECUREFIR_MASK
+    {
+        name        "MBU.MBS.ARB.RXLT.MBSSIRMASK";
+        scomaddr    0x02011421;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSSECUREFIR_ACT0
+    {
+        name        "MBU.MBS.ARB.RXLT.MBSSIRACT0";
+        scomaddr    0x02011424;
+        capture     type secondary;
+        capture     group default;
+    };
+
+    register MBSSECUREFIR_ACT1
+    {
+        name        "MBU.MBS.ARB.RXLT.MBSSIRACT1";
+        scomaddr    0x02011425;
+        capture     type secondary;
+        capture     group default;
+    };
+