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| author | Zane Shelley <zshelle@us.ibm.com> | 2012-09-20 12:18:46 -0500 |
|---|---|---|
| committer | A. Patrick Williams III <iawillia@us.ibm.com> | 2012-11-07 16:13:29 -0600 |
| commit | 63aca27a47a3b60ca107c12cad8d132a0cfeb64c (patch) | |
| tree | e3e38fb25b6986223f8ba8f617f04697f4801b2d /src/usr/diag/prdf/plat/pegasus | |
| parent | 1190a8872faeac22924a4528c9fbeabdafe9fad6 (diff) | |
| download | talos-hostboot-63aca27a47a3b60ca107c12cad8d132a0cfeb64c.tar.gz talos-hostboot-63aca27a47a3b60ca107c12cad8d132a0cfeb64c.zip | |
Initial port of PRD to Hostboot
Change-Id: I7ee2673131d4891d482e99a403a36300b79e547e
Reviewed-on: http://gfw160.austin.ibm.com:8080/gerrit/1853
Tested-by: Jenkins Server
Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/plat/pegasus')
34 files changed, 13197 insertions, 0 deletions
diff --git a/src/usr/diag/prdf/plat/pegasus/CommonActions.rule b/src/usr/diag/prdf/plat/pegasus/CommonActions.rule new file mode 100644 index 000000000..028bb8fa7 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/CommonActions.rule @@ -0,0 +1,111 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/CommonActions.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# This file is intended to create a common set of actionclasses for all rule +# files. Simply add the following line at the top the actionclass section of +# each rule file. +# +# .include "CommonActions.rule" +# +# Note that no indentation can be used for the .include keyword. +################################################################################ + +################################################################################ +# Thresholds and Flags # +################################################################################ +# FIXME These thresholds are just for demo purpose. +# Its new format. Once team is comfortable with new format we can remove them +# The syntax for new format is +# threshold ( field (errorFrequency[ time_units, time_base ] ), mfg|mfg_file (errorFrequency[........])) +# time_base can have sec|min|hour|day +# NOTE : Time finally will be changed the seconds.Maximum value supported is 0xffffffff (around 49710 days) +# If more then this value is specified, it will be truncated +/** Threshold of 1 */ +actionclass threshold1 +{ +# Field threshold 1 + threshold( field(1 / 0xffffffff sec) ); +}; + +/** Threshold of 2 per month */ +actionclass threshold2pmonth +{ +# Field threshold 2 per 30 days + threshold( field(2 / 30 day) ); +}; + +/** Threshold of 1 , mfg 2 per min*/ +actionclass threshold1mfg2pmin +{ +# Field threshold 1, mfg 2 per min +# if in time base ( sec|min|hour|day) nothing is specified , by defaut it is sec + threshold( field(1), mfg (2/min) ); +}; + +#FIXME: comment out so I can compile in Hostboot +##/** Threshold of 1 per second , mfg threshold P7CORE_L2_CACHE_CES (from mnfg file) */ +#actionclass threshold1per1SecwithField +#{ +# Field threshold 1 per second, mfg threshold will be taken from file +# threshold( field(1 / sec), mfg_file(P7CORE_L2_CACHE_CES) ); +#}; + +################################################################################ +# Simple Callouts # +################################################################################ + +/** Callout 2nd Level Support, priority medium */ +actionclass callout2ndLvlMed +{ + callout(procedure(NextLevelSupport_ENUM), MRU_MED); +}; + +################################################################################ +# Dump Types # +################################################################################ + +/** Dump SH */ +actionclass dumpSH +{ + dump(DUMP_CONTENT_SH); +}; + +################################################################################ +# Default callouts # +################################################################################ + +/** Default action for an unexpected unmasked bit */ +actionclass defaultMaskedError +{ + dumpSH; + callout2ndLvlMed; + threshold1; +}; + +/** Default TBD action */ +actionclass TBDDefaultCallout +{ + defaultMaskedError; +}; + diff --git a/src/usr/diag/prdf/plat/pegasus/Ex.rule b/src/usr/diag/prdf/plat/pegasus/Ex.rule new file mode 100644 index 000000000..d51ced0dd --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Ex.rule @@ -0,0 +1,1306 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Ex.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Scope: +# Registers and actions for the following chiplets: +# Note that only addresses for EX0 will be used. +# +# Chiplet Register Addresses Description +# ======= ======================= ============================================ +# EX0 0x10000000 - 0x10FFFFFF EX0 pervasive logic +# EX1 0x11000000 - 0x11FFFFFF EX1 pervasive logic +# EX2 0x12000000 - 0x12FFFFFF EX2 pervasive logic +# EX3 0x13000000 - 0x13FFFFFF EX3 pervasive logic +# EX4 0x14000000 - 0x14FFFFFF EX4 pervasive logic +# EX5 0x15000000 - 0x15FFFFFF EX5 pervasive logic +# EX6 0x16000000 - 0x16FFFFFF EX6 pervasive logic +# EX7 0x17000000 - 0x17FFFFFF EX7 pervasive logic +# EX8 0x18000000 - 0x18FFFFFF EX8 pervasive logic +# EX9 0x19000000 - 0x19FFFFFF EX9 pervasive logic +# EX10 0x1A000000 - 0x1AFFFFFF EX10 pervasive logic +# EX11 0x1B000000 - 0x1BFFFFFF EX11 pervasive logic +# EX12 0x1C000000 - 0x1CFFFFFF EX12 pervasive logic +# EX13 0x1D000000 - 0x1DFFFFFF EX13 pervasive logic +# EX14 0x1E000000 - 0x1EFFFFFF EX14 pervasive logic +# EX15 0x1F000000 - 0x1FFFFFFF EX15 pervasive logic +# +################################################################################ + +chip Ex +{ + name "Power8 EX Chiplet"; + targettype TYPE_EX; + sigoff 0x8000; +# FIXME May need to update dump type + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # EX Chiplet Registers + ############################################################################ + + register EX_CHIPLET_CS_FIR + { + name "EX00.TP.ECO_DOM.XFIR"; + scomaddr 0x10040000; + capture group default; + }; + + register EX_CHIPLET_RE_FIR + { + name "EX00.TP.ECO_DOM.RFIR"; + scomaddr 0x10040001; + capture group default; + }; + + register EX_CHIPLET_FIR_MASK + { + name "EX00.TP.ECO_DOM.FIR_MASK"; + scomaddr 0x10040002; + capture type secondary; + capture group default; + }; + + # EX special attention registers - Used for FFDC only + # Currently, all analysis of these registers is done by ATTN. + + register EX_CHIPLET_SPA + { + name "EX00.TP.ECO_DOM.EPS.FIR.SPATTN"; + scomaddr 0x10040004; + capture group default; + }; + + ############################################################################ + # EX Chiplet LFIR + ############################################################################ + + register EX_LFIR + { + name "EX00.TP.ECO_DOM.LOCAL_FIR"; + scomaddr 0x1004000a; + reset (&, 0x1004000b); + mask (|, 0x1004000f); + capture group default; + }; + + register EX_LFIR_MASK + { + name "EX00.TP.ECO_DOM.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x1004000d; + capture type secondary; + capture group default; + }; + + register EX_LFIR_ACT0 + { + name "EX00.TP.ECO_DOM.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x10040010; + capture type secondary; + capture group default; + }; + + register EX_LFIR_ACT1 + { + name "EX00.TP.ECO_DOM.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x10040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # EX Chiplet COREFIR + ############################################################################ + + register COREFIR + { + name "EX00.EC.PC.PC_NE.FIR.CORE_FIR"; + scomaddr 0x10013100; + reset (&, 0x10013101); + mask (|, 0x10013108); + capture group default; + }; + + register COREFIR_MASK + { + name "EX00.EC.PC.PC_NE.FIR.CORE_FIRMASK"; + scomaddr 0x10013106; + capture type secondary; + capture group default; + }; + + register COREFIR_ACT0 + { + name "EX00.EC.PC.PC_NE.FIR.CORE_ACTION0"; + scomaddr 0x10013103; + capture type secondary; + capture group default; + }; + + register COREFIR_ACT1 + { + name "EX00.EC.PC.PC_NE.FIR.CORE_ACTION1"; + scomaddr 0x10013104; + capture type secondary; + capture group default; + }; + + ############################################################################ + # EX Chiplet L2FIR + ############################################################################ + + register L2FIR + { + name "EX00.L2.L2MISC.L2CERRS.FIR_REG"; + scomaddr 0x10012800; + reset (&, 0x10012801); + mask (|, 0x10012805); + capture group default; + }; + + register L2FIR_MASK + { + name "EX00.L2.L2MISC.L2CERRS.FIR_MASK_REG"; + scomaddr 0x10012803; + capture type secondary; + capture group default; + }; + + register L2FIR_ACT0 + { + name "EX00.L2.L2MISC.L2CERRS.FIR_ACTION0_REG"; + scomaddr 0x10012806; + capture type secondary; + capture group default; + }; + + register L2FIR_ACT1 + { + name "EX00.L2.L2MISC.L2CERRS.FIR_ACTION1_REG"; + scomaddr 0x10012807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # EX Chiplet L3FIR + ############################################################################ + + register L3FIR + { + name "EX00.L3.L3_MISC.L3CERRS.FIR_REG"; + scomaddr 0x10010800; + reset (&, 0x10010801); + mask (|, 0x10010805); + capture group default; + }; + + register L3FIR_MASK + { + name "EX00.L3.L3_MISC.L3CERRS.FIR_MASK_REG"; + scomaddr 0x10010803; + capture type secondary; + capture group default; + }; + + register L3FIR_ACT0 + { + name "EX00.L3.L3_MISC.L3CERRS.FIR_ACTION0_REG"; + scomaddr 0x10010806; + capture type secondary; + capture group default; + }; + + register L3FIR_ACT1 + { + name "EX00.L3.L3_MISC.L3CERRS.FIR_ACTION1_REG"; + scomaddr 0x10010807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # EX Chiplet NCUFIR + ############################################################################ + + register NCUFIR + { + name "EX00.NC.NCMISC.NCSCOMS.FIR_REG"; + scomaddr 0x10010c00; + reset (&, 0x10010c01); + mask (|, 0x10010c05); + capture group default; + }; + + register NCUFIR_MASK + { + name "EX00.NC.NCMISC.NCSCOMS.FIR_MASK_REG"; + scomaddr 0x10010c03; + capture type secondary; + capture group default; + }; + + register NCUFIR_ACT0 + { + name "EX00.NC.NCMISC.NCSCOMS.FIR_ACTION0_REG"; + scomaddr 0x10010c06; + capture type secondary; + capture group default; + }; + + register NCUFIR_ACT1 + { + name "EX00.NC.NCMISC.NCSCOMS.FIR_ACTION1_REG"; + scomaddr 0x10010c07; + capture type secondary; + capture group default; + }; + + ############################################################################ + # EX Chiplet SPATTNs + ############################################################################ + + # EX special attention registers - Used for FFDC only + # Currently, all analysis of these registers is done by ATTN. + + register SPATTN_0 + { + name "EX00.EC.PC.PC_NE.TCTL0.SPATTN"; + scomaddr 0x10013007; + capture group default; + }; + + register SPATTN_1 + { + name "EX00.EC.PC.PC_NE.TCTL1.SPATTN"; + scomaddr 0x10013017; + capture group default; + }; + + register SPATTN_2 + { + name "EX00.EC.PC.PC_NE.TCTL2.SPATTN"; + scomaddr 0x10013027; + capture group default; + }; + register SPATTN_3 + { + name "EX00.EC.PC.PC_NE.TCTL3.SPATTN"; + scomaddr 0x10013037; + capture group default; + }; + + register SPATTN_4 + { + name "EX00.EC.PC.PC_NE.TCTL4.SPATTN"; + scomaddr 0x10013047; + capture group default; + }; + + register SPATTN_5 + { + name "EX00.EC.PC.PC_NE.TCTL5.SPATTN"; + scomaddr 0x10013057; + capture group default; + }; + + register SPATTN_6 + { + name "EX00.EC.PC.PC_NE.TCTL6.SPATTN"; + scomaddr 0x10013067; + capture group default; + }; + + register SPATTN_7 + { + name "EX00.EC.PC.PC_NE.TCTL7.SPATTN"; + scomaddr 0x10013077; + capture group default; + }; + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# EX Chiplet Registers +################################################################################ + +rule ExChipetFir +{ + CHECK_STOP: + (EX_CHIPLET_CS_FIR & `1F00000000000000`) & ~EX_CHIPLET_FIR_MASK; + RECOVERABLE: + ((EX_CHIPLET_RE_FIR >> 2) & `1F00000000000000`) & ~EX_CHIPLET_FIR_MASK; +}; + +group gExChipetFir attntype CHECK_STOP, RECOVERABLE filter singlebit +{ + /** EX_CHIPLET_FIR[3] + * Attention from LFIR + */ + (ExChipetFir, bit(3))? analyze(gExLFir); + + /** EX_CHIPLET_FIR[4] + * Attention from COREFIR + */ + (ExChipetFir, bit(4)) ? analyze(gCoreFir); + + /** EX_CHIPLET_FIR[5] + * Attention from L2FIR + */ + (ExChipetFir, bit(5)) ? analyze(gL2Fir); + + /** EX_CHIPLET_FIR[6] + * Attention from L3FIR + */ + (ExChipetFir, bit(6)) ? analyze(gL3Fir); + + /** EX_CHIPLET_FIR[7] + * Attention from NCUFIR + */ + (ExChipetFir, bit(7)) ? analyze(gNcuFir); +}; + +################################################################################ +# EX Chiplet LFIR +################################################################################ + +rule ExLFir +{ + CHECK_STOP: EX_LFIR & ~EX_LFIR_MASK & ~EX_LFIR_ACT0 & ~EX_LFIR_ACT1; + RECOVERABLE: EX_LFIR & ~EX_LFIR_MASK & ~EX_LFIR_ACT0 & EX_LFIR_ACT1; +}; + +group gExLFir filter singlebit +{ + /** EX_LFIR[0] + * CFIR internal parity error + */ + (ExLFir, bit(0)) ? TBDDefaultCallout; + + /** EX_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (ExLFir, bit(1)) ? TBDDefaultCallout; + + /** EX_LFIR[2] + * Local errors from CC (PCB error) + */ + (ExLFir, bit(2)) ? TBDDefaultCallout; + + /** EX_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (ExLFir, bit(3)) ? TBDDefaultCallout; + + /** EX_LFIR[4] + * Local errors from PSC (PCB error) + */ + (ExLFir, bit(4)) ? TBDDefaultCallout; + + /** EX_LFIR[5] + * Local errors from PSC (parity error) + */ + (ExLFir, bit(5)) ? TBDDefaultCallout; + + /** EX_LFIR[6] + * Local errors from Thermal (parity error) + */ + (ExLFir, bit(6)) ? TBDDefaultCallout; + + /** EX_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (ExLFir, bit(7)) ? TBDDefaultCallout; + + /** EX_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (ExLFir, bit(8|9)) ? TBDDefaultCallout; + + /** EX_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (ExLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# EX Chiplet COREFIR +################################################################################ + +rule CoreFir +{ + CHECK_STOP: COREFIR & ~COREFIR_MASK & ~COREFIR_ACT0 & ~COREFIR_ACT1; + RECOVERABLE: COREFIR & ~COREFIR_MASK & ~COREFIR_ACT0 & COREFIR_ACT1; +}; + +group gCoreFir filter singlebit +{ + /** COREFIR[0] + * IFU_SRAM_PARITY_ERR: SRAM recoverable error (ICACHE parity error, etc.) + */ + (CoreFir, bit(0)) ? TBDDefaultCallout; + + /** COREFIR[1] + * IF_SETDELETE_ERR: set deleted + */ + (CoreFir, bit(1)) ? TBDDefaultCallout; + + /** COREFIR[2] + * IF_RFILE_REC_ERR: RegFile recoverable error + */ + (CoreFir, bit(2)) ? TBDDefaultCallout; + + /** COREFIR[3] + * IF_RFILE_CHKSTOP_ERR: RegFile core check stop + */ + (CoreFir, bit(3)) ? TBDDefaultCallout; + + /** COREFIR[4] + * IF_LOG_REC_ERR: logic recoverable error + */ + (CoreFir, bit(4)) ? TBDDefaultCallout; + + /** COREFIR[5] + * IF_LOG_CHKSTOP_ERR: logic core check stop + */ + (CoreFir, bit(5)) ? TBDDefaultCallout; + + /** COREFIR[6] + * IF_NOT_MT_REC_ERR: recoverable if not in MT window + */ + (CoreFir, bit(6)) ? TBDDefaultCallout; + + /** COREFIR[7] + * IF_CHKSTOP_ERR: system check stop + */ + (CoreFir, bit(7)) ? TBDDefaultCallout; + + /** COREFIR[8] + * RECOV_FIR_CHKSTOP_ERR: recovery core check stop + */ + (CoreFir, bit(8)) ? TBDDefaultCallout; + + /** COREFIR[9] + * SD_RFILE_REC_ERR: RegFile recoverable error + */ + (CoreFir, bit(9)) ? TBDDefaultCallout; + + /** COREFIR[10] + * SD_RFILE_CHKSTOP_ERR: RegFile core check stop (mapper error) + */ + (CoreFir, bit(10)) ? TBDDefaultCallout; + + /** COREFIR[11] + * SD_LOG_REC_ERR: logic recoverable error + */ + (CoreFir, bit(11)) ? TBDDefaultCallout; + + /** COREFIR[12] + * SD_LOG_CHKSTOP_ERR: logic core check stop + */ + (CoreFir, bit(12)) ? TBDDefaultCallout; + + /** COREFIR[13] + * SD_NOT_MT_REC_ERR: recoverable if not in MT window + */ + (CoreFir, bit(13)) ? TBDDefaultCallout; + + /** COREFIR[14] + * SD_MCHK_AND_ME_EQ_0: MCHK received while ME=0 non recoverable + */ + (CoreFir, bit(14)) ? TBDDefaultCallout; + + /** COREFIR[15] + * SD_PC_L2_UE_ERR: UE from L2 + */ + (CoreFir, bit(15)) ? TBDDefaultCallout; + + /** COREFIR[16] + * ISU_L2_UE_OVER_TH_ERR: Number of UEs from L2 above threshold + */ + (CoreFir, bit(16)) ? TBDDefaultCallout; + + /** COREFIR[17] + * SD_PC_CI_UE: UE on CI load + */ + (CoreFir, bit(17)) ? TBDDefaultCallout; + + /** COREFIR[19] + * FX_GPR_REC_ERR: GPR recoverable error + */ + (CoreFir, bit(19)) ? TBDDefaultCallout; + + /** COREFIR[21] + * FX_LOG_CHKSTOP_ERR: logic core check stop + */ + (CoreFir, bit(21)) ? TBDDefaultCallout; + + /** COREFIR[22] + * FX_NOT_MT_REC_ERR: recoverable if not in MT window + */ + (CoreFir, bit(22)) ? TBDDefaultCallout; + + /** COREFIR[23] + * VS_VRF_REC_ERR: VRF recoverable error + */ + (CoreFir, bit(23)) ? TBDDefaultCallout; + + /** COREFIR[24] + * VS_LOG_REC_ERR: logic recoverable error + */ + (CoreFir, bit(24)) ? TBDDefaultCallout; + + /** COREFIR[25] + * VS_LOG_CHKSTOP_ERR: logic core check stop + */ + (CoreFir, bit(25)) ? TBDDefaultCallout; + + /** COREFIR[26] + * RECOV_IN_MAINT_ERR: 26 = recov_in_maint + */ + (CoreFir, bit(26)) ? TBDDefaultCallout; + + /** COREFIR[27] + * DU_LOG_REC_ERR: logic recoverable error + */ + (CoreFir, bit(27)) ? TBDDefaultCallout; + + /** COREFIR[28] + * DU_LOG_CHKSTOP_ERR: logic core check stop + */ + (CoreFir, bit(28)) ? TBDDefaultCallout; + + /** COREFIR[29] + * LSU_SRAM_PARITY_ERR: SRAM recoverable error (DCACHE parity error, etc.) + */ + (CoreFir, bit(29)) ? TBDDefaultCallout; + + /** COREFIR[30] + * LS_SETDELETE_ERR: set deleted + */ + (CoreFir, bit(30)) ? TBDDefaultCallout; + + /** COREFIR[31] + * LS_RFILE_REC_ERR: RegFile recoverable error + */ + (CoreFir, bit(31)) ? TBDDefaultCallout; + + /** COREFIR[32] + * LS_RFILE_CHKSTOP_ERR: RegFile core check stop + */ + (CoreFir, bit(32)) ? TBDDefaultCallout; + + /** COREFIR[33] + * LS_TLB_MULTIHIT_ERR: special recovery error TLB multi hit error occurred + */ + (CoreFir, bit(33)) ? TBDDefaultCallout; + + /** COREFIR[34] + * LS_SLB_MULTIHIT_ERR: special recovery error SLBFEE multi hit error occurred + */ + (CoreFir, bit(34)) ? TBDDefaultCallout; + + /** COREFIR[35] + * LS_DERAT_MULTIHIT_ERR: special recovery error ERAT multi hit error occurred + */ + (CoreFir, bit(35)) ? TBDDefaultCallout; + + /** COREFIR[36] + * FORWARD_PROGRESS_ERR: forward progress error + */ + (CoreFir, bit(36)) ? TBDDefaultCallout; + + /** COREFIR[37] + * LS_LOG_REC_ERR: logic recoverable error + */ + (CoreFir, bit(37)) ? TBDDefaultCallout; + + /** COREFIR[38] + * LS_LOG_CHKSTOP_ERR: logic core check stop + */ + (CoreFir, bit(38)) ? TBDDefaultCallout; + + /** COREFIR[39] + * LS_NOT_MT_REC_ERR: recoverable if not in MT window + */ + (CoreFir, bit(39)) ? TBDDefaultCallout; + + /** COREFIR[40] + * LS_NOT_CI_REC_ERR: recoverable if not in CI window + */ + (CoreFir, bit(40)) ? TBDDefaultCallout; + + /** COREFIR[41] + * LS_CHKSTOP_ERR: system check stop + */ + (CoreFir, bit(41)) ? TBDDefaultCallout; + + /** COREFIR[42] + * LS_GPR_RCV_CHKSTOP_ERR: UE from GPR/VRF recovery process + */ + (CoreFir, bit(42)) ? TBDDefaultCallout; + + /** COREFIR[43] + * THREAD_HANG_REC_ERR: thread hang recoverable error + */ + (CoreFir, bit(43)) ? TBDDefaultCallout; + + /** COREFIR[44] + * FIR_LOG_RECOV_ERR: logic recoverable error + */ + (CoreFir, bit(44)) ? TBDDefaultCallout; + + /** COREFIR[45] + * PC_LOG_CHKSTOP_ERR: PC logic core check stop + */ + (CoreFir, bit(45)) ? TBDDefaultCallout; + + /** COREFIR[47] + * TFC_FIR_TFMR_P_ERR: TFMR Parity Error (timing facility may be corrupt) + */ + (CoreFir, bit(47)) ? TBDDefaultCallout; + + /** COREFIR[48] + * SPRD_FIR_HYP_RES_P_ERR: Hypervisor Resource error - core check stop + */ + (CoreFir, bit(48)) ? TBDDefaultCallout; + + /** COREFIR[49] + * TFC_FIR_P_ERR: TFAC parity error + */ + (CoreFir, bit(49)) ? TBDDefaultCallout; + + /** COREFIR[50] + * TFC_FIR_CONTROL_ERR: TFAC control error + */ + (CoreFir, bit(50)) ? TBDDefaultCallout; + + /** COREFIR[51] + * PC_FIRM_AND_SEL_ERR: TFAC firmware error and select error + */ + (CoreFir, bit(51)) ? TBDDefaultCallout; + + /** COREFIR[52] + * CORE_HUNG: Hang recovery failed (core check stop) + */ + (CoreFir, bit(52)) ? TBDDefaultCallout; + + /** COREFIR[53] + * CORE_HANG_DETECT: Internal hang detected (core hang) + */ + (CoreFir, bit(53)) ? TBDDefaultCallout; + + /** COREFIR[54] + * AMBI_HANG_DETECT: Hang detected unknown source + */ + (CoreFir, bit(54)) ? TBDDefaultCallout; + + /** COREFIR[55] + * NEST_HANG_DETECT: External Hang detected + */ + (CoreFir, bit(55)) ? TBDDefaultCallout; + + /** COREFIR[59] + * PC_SOM_ERR: SCOM satellite error detected + */ + (CoreFir, bit(59)) ? TBDDefaultCallout; + + /** COREFIR[60] + * DBG_FIR_CHECKSTOP_ON_TRIGGER: debug Trigger Error inject + */ + (CoreFir, bit(60)) ? TBDDefaultCallout; + + /** COREFIR[61] + * SP_INJ_REC_ERR: SCOM or Firmware recoverable Error Inject + */ + (CoreFir, bit(61)) ? TBDDefaultCallout; + + /** COREFIR[62] + * SP_INJ_XSTOP_ERR: Firmware Xstop Error Inject + */ + (CoreFir, bit(62)) ? TBDDefaultCallout; + + /** COREFIR[63] + * SPRD_PHYP_ERR_INJ: Phyp Xstop via SPRC / SPRD + */ + (CoreFir, bit(63)) ? TBDDefaultCallout; +}; + +################################################################################ +# EX Chiplet L2FIR +################################################################################ + +rule L2Fir +{ + CHECK_STOP: L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & ~L2FIR_ACT1; + RECOVERABLE: L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & L2FIR_ACT1; +}; + +group gL2Fir filter singlebit +{ + /** L2FIR[0] + * CACHE_RD_CE + */ + (L2Fir, bit(0)) ? TBDDefaultCallout; + + /** L2FIR[1] + * CACHE_RD_UE + */ + (L2Fir, bit(1)) ? TBDDefaultCallout; + + /** L2FIR[2] + * CACHE_RD_SUE + */ + (L2Fir, bit(2)) ? TBDDefaultCallout; + + /** L2FIR[3] + * HW_DIR_INTIATED_LINE_DELETE_OCCURRED + */ + (L2Fir, bit(3)) ? TBDDefaultCallout; + + /** L2FIR[4] + * CACHE_UE_SUE_DETECTED_ON_MODIFIED_LINE_BY_CO + */ + (L2Fir, bit(4)) ? TBDDefaultCallout; + + /** L2FIR[5] + * CACHE_UE_SUE_DETECTED_ON_NON_MODIFIED_LINE_BY_CO + */ + (L2Fir, bit(5)) ? TBDDefaultCallout; + + /** L2FIR[6] + * DIR_CE_DETECTED + */ + (L2Fir, bit(6)) ? TBDDefaultCallout; + + /** L2FIR[7] + * DIR_UE_DETECTED + */ + (L2Fir, bit(7)) ? TBDDefaultCallout; + + /** L2FIR[8] + * DIR_STUCK_BIT_CE + */ + (L2Fir, bit(8)) ? TBDDefaultCallout; + + /** L2FIR[9] + * DIR_SBCE_REPAIR_FAILED + */ + (L2Fir, bit(9)) ? TBDDefaultCallout; + + /** L2FIR[10] + * MULTIPLE_DIR_ERRORS_DETECTED + */ + (L2Fir, bit(10)) ? TBDDefaultCallout; + + /** L2FIR[11] + * LRU_READ_ERROR_DETECTED + */ + (L2Fir, bit(11)) ? TBDDefaultCallout; + + /** L2FIR[12] + * RC_POWERBUS_DATA_TIMEOUT + */ + (L2Fir, bit(12)) ? TBDDefaultCallout; + + /** L2FIR[13] + * NCU_POWERBUS_DATA_TIMEOUT + */ + (L2Fir, bit(13)) ? TBDDefaultCallout; + + /** L2FIR[14] + * HW_CONTROL_ERROR + */ + (L2Fir, bit(14)) ? TBDDefaultCallout; + + /** L2FIR[15] + * LRU_ALL_MEMBERS_IN_CGC_ARE_LINE_DELETED + */ + (L2Fir, bit(15)) ? TBDDefaultCallout; + + /** L2FIR[16] + * CACHE_INHIBITED_HIT_CACHEABLE_ERROR + */ + (L2Fir, bit(16)) ? TBDDefaultCallout; + + /** L2FIR[17] + * RC_LOAD_RECIVED_PB_CRESP_ADR_ERR + */ + (L2Fir, bit(17)) ? TBDDefaultCallout; + + /** L2FIR[18] + * RC_STORE_RECIVED_PB_CRESP_ADR_ERR + */ + (L2Fir, bit(18)) ? TBDDefaultCallout; + + /** L2FIR[19] + * RC_POWBUS_DATA_CE_ERR_FROM_F2CHK + */ + (L2Fir, bit(19)) ? TBDDefaultCallout; + + /** L2FIR[20] + * RC_POWBUS_DATA_UE_ERR_FROM_F2CHK + */ + (L2Fir, bit(20)) ? TBDDefaultCallout; + + /** L2FIR[21] + * RC_POWBUS_DATA_SUE_ERR_FROM_F2CHK + */ + (L2Fir, bit(21)) ? TBDDefaultCallout; + + /** L2FIR[22] + * CO_ICSW_UE_SUE_DATA_ERR_FROM_F2CHK + */ + (L2Fir, bit(22)) ? TBDDefaultCallout; + + /** L2FIR[23] + * RC_LOAD_RECIVED_PB_CRESP_ADR_ERR_FOR_HYP + */ + (L2Fir, bit(23)) ? TBDDefaultCallout; + + /** L2FIR[24] + * RCDAT_RD_PARITY_ERR + */ + (L2Fir, bit(24)) ? TBDDefaultCallout; + + /** L2FIR[25] + * CO_ICSW_RTY_BUSY_ABT_ERR + */ + (L2Fir, bit(25)) ? TBDDefaultCallout; + + /** L2FIR[26] + * HA_LOG_STOP_SW_ERR + */ + (L2Fir, bit(26)) ? TBDDefaultCallout; + + /** L2FIR[27] + * RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN0 + */ + (L2Fir, bit(27)) ? TBDDefaultCallout; + + /** L2FIR[28] + * RC_LOAD_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN1 + */ + (L2Fir, bit(28)) ? TBDDefaultCallout; + + /** L2FIR[29] + * RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN0 + */ + (L2Fir, bit(29)) ? TBDDefaultCallout; + + /** L2FIR[30] + * RC_STORE_RECEIVED_PB_ACK_DEAD_FROM_FOREIGN1 + */ + (L2Fir, bit(30)) ? TBDDefaultCallout; + + /** L2FIR[31] + * ILLEGAL_MPALOG_TPID_SW_ERR + */ + (L2Fir, bit(31)) ? TBDDefaultCallout; + + /** L2FIR[32] + * UNEXP_HA_ST_ERR + */ + (L2Fir, bit(32)) ? TBDDefaultCallout; + + /** L2FIR[33] + * HA_LINE_IN_CONS_CACHE_ERR + */ + (L2Fir, bit(33)) ? TBDDefaultCallout; + + /** L2FIR[34] + * HA_TABLE_IN_PROD_CACHE_ERR + */ + (L2Fir, bit(34)) ? TBDDefaultCallout; + + /** L2FIR[35] + * ILLEGAL_LOG_STOP_SW_ERR + */ + (L2Fir, bit(35)) ? TBDDefaultCallout; + + /** L2FIR[48] + * SCOM_ERR1: scom error + */ + (L2Fir, bit(48)) ? TBDDefaultCallout; + + /** L2FIR[49] + * SCOM_ERR2: scom error + */ + (L2Fir, bit(49)) ? TBDDefaultCallout; +}; + +################################################################################ +# EX Chiplet L3FIR +################################################################################ + +rule L3Fir +{ + CHECK_STOP: L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & ~L3FIR_ACT1; + RECOVERABLE: L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & L3FIR_ACT1; +}; + +group gL3Fir filter singlebit +{ + /** L3FIR[0] + * Reserved field (Access type is pb_cmd_err) + */ + (L3Fir, bit(0)) ? TBDDefaultCallout; + + /** L3FIR[1] + * Reserved field (Access type is pb_data_err) + */ + (L3Fir, bit(1)) ? TBDDefaultCallout; + + /** L3FIR[2] + * Reserved field (Access type is l3_spare_error1) + */ + (L3Fir, bit(2)) ? TBDDefaultCallout; + + /** L3FIR[3] + * Reserved field (Access type is l3_spare_error1) + */ + (L3Fir, bit(3)) ? TBDDefaultCallout; + + /** L3FIR[4] + * Reserved field (Access type is l3_cac_rd_ce_det_not_lindel_req) + */ + (L3Fir, bit(4)) ? TBDDefaultCallout; + + /** L3FIR[5] + * Reserved field (Access type is l3_cac_rd_ue_det) + */ + (L3Fir, bit(5)) ? TBDDefaultCallout; + + /** L3FIR[6] + * Reserved field (Access type is l3_cac_rd_sue_det) + */ + (L3Fir, bit(6)) ? TBDDefaultCallout; + + /** L3FIR[7] + * Reserved field (Access type is l3_cac_wr_data_ce_from_pb) + */ + (L3Fir, bit(7)) ? TBDDefaultCallout; + + /** L3FIR[8] + * Reserved field (Access type is l3_cac_wr_data_ue_from_pb) + */ + (L3Fir, bit(8)) ? TBDDefaultCallout; + + /** L3FIR[9] + * Reserved field (Access type is l3_cac_wr_data_sue_from_pb) + */ + (L3Fir, bit(9)) ? TBDDefaultCallout; + + /** L3FIR[10] + * Reserved field (Access type is l3_cac_wr_data_ce_from_l2) + */ + (L3Fir, bit(10)) ? TBDDefaultCallout; + + /** L3FIR[11] + * Reserved field (Access type is l3_cac_wr_data_ue_from_l2) + */ + (L3Fir, bit(11)) ? TBDDefaultCallout; + + /** L3FIR[12] + * Reserved field (Access type is l3_cac_wr_data_sue_from_l2) + */ + (L3Fir, bit(12)) ? TBDDefaultCallout; + + /** L3FIR[13] + * Reserved field (Access type is l3_dir_rd_ce_det) + */ + (L3Fir, bit(13)) ? TBDDefaultCallout; + + /** L3FIR[14] + * Reserved field (Access type is l3_dir_rd_ue_det) + */ + (L3Fir, bit(14)) ? TBDDefaultCallout; + + /** L3FIR[15] + * Reserved field (Access type is l3_dir_rd_phantom_error) + */ + (L3Fir, bit(15)) ? TBDDefaultCallout; + + /** L3FIR[16] + * Reserved field (Access type is l3_co_sn_cresp_addr_err) + */ + (L3Fir, bit(16)) ? TBDDefaultCallout; + + /** L3FIR[17] + * Reserved field (Access type is l3_pf_cresp_addr_err) + */ + (L3Fir, bit(17)) ? TBDDefaultCallout; + + /** L3FIR[18] + * Reserved field (Access type is l3_addr_hang_detected) + */ + (L3Fir, bit(18)) ? TBDDefaultCallout; + + /** L3FIR[19] + * Reserved field (Access type is l3_flink_0_load_ack_dead) + */ + (L3Fir, bit(19)) ? TBDDefaultCallout; + + /** L3FIR[20] + * Reserved field (Access type is l3_flink_0_store_ack_dead) + */ + (L3Fir, bit(20)) ? TBDDefaultCallout; + + /** L3FIR[21] + * Reserved field (Access type is l3_flink_1_load_ack_dead) + */ + (L3Fir, bit(21)) ? TBDDefaultCallout; + + /** L3FIR[22] + * Reserved field (Access type is l3_flink_1_store_ack_dead) + */ + (L3Fir, bit(22)) ? TBDDefaultCallout; + + /** L3FIR[23] + * Reserved field (Access type is l3_mach_hang_detected) + */ + (L3Fir, bit(23)) ? TBDDefaultCallout; + + /** L3FIR[24] + * Reserved field (Access type is l3_hw_control_err) + */ + (L3Fir, bit(24)) ? TBDDefaultCallout; + + /** L3FIR[25] + * Reserved field (Access type is l3_snoop_sw_err_detected) + */ + (L3Fir, bit(25)) ? TBDDefaultCallout; + + /** L3FIR[26] + * Reserved field (Access type is l3_line_del_ce_done) + */ + (L3Fir, bit(26)) ? TBDDefaultCallout; + + /** L3FIR[27] + * Reserved field (Access type is l3_dram_error) + */ + (L3Fir, bit(27)) ? TBDDefaultCallout; + + /** L3FIR[28] + * Reserved field (Access type is l3_lru_error) + */ + (L3Fir, bit(28)) ? TBDDefaultCallout; + + /** L3FIR[29] + * Reserved field (Access type is l3_all_members_deleted_error) + */ + (L3Fir, bit(29)) ? TBDDefaultCallout; + + /** L3FIR[30] + * Reserved field (Access type is l3_refresh_timer_error) + */ + (L3Fir, bit(30)) ? TBDDefaultCallout; + + /** L3FIR[31] + * Reserved field (Access type is l3_ha_consumer_sw_access_err) + */ + (L3Fir, bit(31)) ? TBDDefaultCallout; + + /** L3FIR[32] + * Reserved field (Access type is l3_ha_producer_sw_access_err) + */ + (L3Fir, bit(32)) ? TBDDefaultCallout; + + /** L3FIR[33] + * Reserved field (Access type is l3_ha_line_in_consumer_cac_err) + */ + (L3Fir, bit(33)) ? TBDDefaultCallout; + + /** L3FIR[34] + * Reserved field (Access type is l3_ha_table_in_producer_cac_err) + */ + (L3Fir, bit(34)) ? TBDDefaultCallout; + + /** L3FIR[35] + * Reserved field (Access type is l3_ha_log_overflow_err) + */ + (L3Fir, bit(35)) ? TBDDefaultCallout; + + /** L3FIR[36] + * Reserved field (Access type is scom_err) + */ + (L3Fir, bit(36)) ? TBDDefaultCallout; +}; + +################################################################################ +# EX Chiplet NCUFIR +################################################################################ + +rule NcuFir +{ + CHECK_STOP: NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & ~NCUFIR_ACT1; + RECOVERABLE: NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & NCUFIR_ACT1; +}; + +group gNcuFir filter singlebit +{ + /** NCUFIR[0] + * CONTROL_ERR: H/W control error. + */ + (NcuFir, bit(0)) ? TBDDefaultCallout; + + /** NCUFIR[1] + * TLBIE_SW_ERR: TLBIE received illegal AP/LP field from core. + */ + (NcuFir, bit(1)) ? TBDDefaultCallout; + + /** NCUFIR[2] + * ST_ADDR_ERR: Store address machine or TLBIE/sync machine received addr_err cresp. + */ + (NcuFir, bit(2)) ? TBDDefaultCallout; + + /** NCUFIR[3] + * LD_ADDR_ERR: Load address machine received addr_err cresp. + */ + (NcuFir, bit(3)) ? TBDDefaultCallout; + + /** NCUFIR[4] + * ST_FOREIGN0_ACK_DEAD: Store received ack_dead on foreign link0. + */ + (NcuFir, bit(4)) ? TBDDefaultCallout; + + /** NCUFIR[5] + * ST_FOREIGN1_ACK_DEAD: Store received ack_dead on foreign link1. + */ + (NcuFir, bit(5)) ? TBDDefaultCallout; + + /** NCUFIR[6] + * LD_FOREIGN0_ACK_DEAD: Load received ack_dead on foreign link0. + */ + (NcuFir, bit(6)) ? TBDDefaultCallout; + + /** NCUFIR[7] + * LD_FOREIGN1_ACK_DEAD: Load received ack_dead on foreign link1. + */ + (NcuFir, bit(7)) ? TBDDefaultCallout; + + /** NCUFIR[8] + * STQ_DATA_PARITY_ERR: Store data parity error from regfile detected. + */ + (NcuFir, bit(8)) ? TBDDefaultCallout; + + /** NCUFIR[9] + * STORE_TIMEOUT: Store timed out on PB. + */ + (NcuFir, bit(9)) ? TBDDefaultCallout; + + /** NCUFIR[10] + * TLBIE_MASTER_TIMEOUT: TLBIE master timed out on PB. + */ + (NcuFir, bit(10)) ? TBDDefaultCallout; + + /** NCUFIR[11] + * TLBIE_SNOOP_TIMEOUT: TLBIE snooper timed out waiting for core. + */ + (NcuFir, bit(11)) ? TBDDefaultCallout; + + /** NCUFIR[12] + * HTM_IMA_TIMEOUT: HTM/IMA address machine timed out on PB. + */ + (NcuFir, bit(12)) ? TBDDefaultCallout; + + /** NCUFIR[13] + * IMA_CRESP_ADDR_ERR: IMA received addr_err cresp. + */ + (NcuFir, bit(13)) ? TBDDefaultCallout; + + /** NCUFIR[14] + * IMA_FOREIGN0_ACK_DEAD: IMA received ack_dead on foreign link0. + */ + (NcuFir, bit(14)) ? TBDDefaultCallout; + + /** NCUFIR[15] + * IMA_FOREIGN1_ACK_DEAD: IMA received ack_dead on foreign link1. + */ + (NcuFir, bit(15)) ? TBDDefaultCallout; + + /** NCUFIR[16] + * HTM_GOT_ACK_DEAD: HTM received ack_dead on any foreign link. + */ + (NcuFir, bit(16)) ? TBDDefaultCallout; + + /** NCUFIR[17] + * PMISC_CRESP_ADDR_ERR: PMISC received address error cresp. + */ + (NcuFir, bit(17)) ? TBDDefaultCallout; + + /** NCUFIR[18] + * TLBIE_CONTROL_ERR: TLBIE control error. + */ + (NcuFir, bit(28)) ? TBDDefaultCallout; + + /** NCUFIR[24] + * SCOM_ERR1: scom erro + */ + (NcuFir, bit(24)) ? TBDDefaultCallout; + + /** NCUFIR[25] + * SCOM_ERR2: scom error + */ + (NcuFir, bit(25)) ? TBDDefaultCallout; +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule" + diff --git a/src/usr/diag/prdf/plat/pegasus/Mba.rule b/src/usr/diag/prdf/plat/pegasus/Mba.rule new file mode 100644 index 000000000..75a0c414c --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Mba.rule @@ -0,0 +1,716 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Mba.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Scope: +# Registers and actions for the following chiplets: +# +# Chiplet Register Addresses Description +# ======= ======================= ============================================ +# MEM 0x03010400 - 0x0301043F MBA 01 +# MEM 0x03010600 - 0x0301063F MBA 01 MCBIST +# MEM 0x03010C00 - 0x03010C3F MBA 23 +# MEM 0x03010E00 - 0x03010E3F MBA 23 MCBIST +# +################################################################################ + +chip Mba +{ + name "Centaur MBA Chiplet"; + targettype TYPE_MBA; + sigoff 0x8000; +# FIXME May need to update dump type + dump DUMP_CONTENT_HWSUPERNOVA; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # MEM Chiplet MBAFIR + ############################################################################ + + register MBAFIR + { + name "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRQ"; + scomaddr 0x03010600; + reset (&, 0x03010601); + mask (|, 0x03010605); + capture group default; + }; + + register MBAFIR_MASK + { + name "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRMASK"; + scomaddr 0x03010603; + capture type secondary; + capture group default; + }; + + register MBAFIR_ACT0 + { + name "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRACT0"; + scomaddr 0x03010606; + capture type secondary; + capture group default; + }; + + register MBAFIR_ACT1 + { + name "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBAFIRACT1"; + scomaddr 0x03010607; + capture type secondary; + capture group default; + }; + + ############################################################################ + # MEM Chiplet MBASECUREFIR + ############################################################################ + + register MBASECUREFIR + { + name "MBU.MBA01.MBA_SRQ.MBASIRQ"; + scomaddr 0x0301041b; + reset (&, 0x0301041c); + # This is a special register in which we are not able to mask. All bits + # in this register should be set to checkstop so we will not need to + # mask anyway. + capture group default; + }; + + register MBASECUREFIR_MASK + { + name "MBU.MBA01.MBA_SRQ.MBASIRMASK"; + scomaddr 0x0301041e; + capture type secondary; + capture group default; + }; + + register MBASECUREFIR_ACT0 + { + name "MBU.MBA01.MBA_SRQ.MBASIRACT0"; + scomaddr 0x03010421; + capture type secondary; + capture group default; + }; + + register MBASECUREFIR_ACT1 + { + name "MBU.MBA01.MBA_SRQ.MBASIRACT1"; + scomaddr 0x03010422; + capture type secondary; + capture group default; + }; + + ############################################################################ + # MEM Chiplet DDRPHYFIR + ############################################################################ + + register MBADDRPHYFIR + { + name "DPHY01.PHY01_DDRPHY_FIR_REG"; + scomaddr 0x800200900301143F; + reset (&, 0x800200910301143F); + mask (|, 0x800200950301143F); + capture group default; + }; + + register MBADDRPHYFIR_MASK + { + name "DPHY01.PHY01_DDRPHY_FIR_MASK_REG"; + scomaddr 0x800200930301143F; + capture type secondary; + capture group default; + }; + + register MBADDRPHYFIR_ACT0 + { + name "DPHY01.PHY01_DDRPHY_FIR_ACTION0_REG"; + scomaddr 0x800200960301143F; + capture type secondary; + capture group default; + }; + + register MBADDRPHYFIR_ACT1 + { + name "DPHY01.PHY01_DDRPHY_FIR_ACTION1_REG"; + scomaddr 0x800200970301143F; + capture type secondary; + capture group default; + }; + + ############################################################################ + # MEM Chiplet MBACALFIR + ############################################################################ + + register MBACALFIR + { + name "MBU.MBA01.MBA_SRQ.MBACALFIRQ"; + scomaddr 0x03010400; + reset (&, 0x03010401); + mask (|, 0x03010405); + capture group default; + }; + + register MBACALFIR_MASK + { + name "MBU.MBA01.MBA_SRQ.MBACALFIR_MASK"; + scomaddr 0x03010403; + capture type secondary; + capture group default; + }; + + register MBACALFIR_ACT0 + { + name "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION0"; + scomaddr 0x03010406; + capture type secondary; + capture group default; + }; + + register MBACALFIR_ACT1 + { + name "MBU.MBA01.MBA_SRQ.MBACALFIR_ACTION1"; + scomaddr 0x03010407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # MEM Chiplet MBASPA + ############################################################################ + + register MBASPA + { + name "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBSPAQ"; + scomaddr 0x03010611; + reset (&, 0x03010612); + #FIXME : There is no OR register for mask. Is it right to use mask register value + mask (|, 0x03010614); + capture group default; + }; + + register MBASPA_MASK + { + name "MBU.MBA01.MBA_MCBIST.SCOMFIR.MBSPAMSKQ"; + scomaddr 0x03010614; + capture type secondary; + capture group default; + }; +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +# This group is a layer of indirection. Normally, each rule file will have a +# single global or chiplet FIR which will have group that defines which lower +# level FIRs to analyze. Unfortunately, the MBA target contains only a subset of +# the FIRs in the Centaur's MEM chiplet. So the MEM chiplet FIR's group +# definition must remain in Membuf.rule. This group will serve as a psuedo +# chiplet FIR. This group could contain the bit definitions for all of the MBA +# registers, however, we could not utilize the filter for each register. +# Instead, the bit definitions will simply analyze the respective FIR groups. +# The FIRs in this group will be analyzed in order so if a FIR should be +# analyzed before another then simply change the order of the FIRs in this +# group. + +# NOTE: The rule definition for this group must be different than that of the +# individual FIR groups. Otherwise, it causes hashing collisions in the +# signatures. In this case, we will add the SPECIAL attention line even +# though none of these registers will trigger a special attention. This +# should change the hash enough to make a unique signature. + +rule tmpMbaFir +{ + CHECK_STOP: MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1; + RECOVERABLE: MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & MBAFIR_ACT1; + SPECIAL: MBAFIR; # See note above. +}; + +rule tmpMbaSecureFir +{ + CHECK_STOP: + MBASECUREFIR & ~MBASECUREFIR_MASK & ~MBASECUREFIR_ACT0 & ~MBASECUREFIR_ACT1; + # NOTE: This secure FIR will only report checkstop attentions. + SPECIAL: + MBASECUREFIR; # See note above. +}; + +rule tmpMbaCalFir +{ + CHECK_STOP: MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1; + RECOVERABLE: MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & MBACALFIR_ACT1; + SPECIAL: MBACALFIR; # See note above. +}; + +rule tmpMbaDdrPhyFir +{ + CHECK_STOP: + MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1; + RECOVERABLE: + MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & MBADDRPHYFIR_ACT1; + SPECIAL: + MBADDRPHYFIR; # See note above. +}; + +group gMBA attntype CHECK_STOP, RECOVERABLE filter singlebit +{ + (tmpMbaFir, bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| + 10|11|12|13|14|15|16|17|18|19| + 20|21|22|23|24|25|26|27|28|29| + 30|31|32|33|34|35|36|37|38|39| + 40|41|42|43|44|45|46|47|48|49| + 50|51|52|53|54|55|56|57|58|59| + 60|61|62|63 )) ? analyze(gMbaFir); + + (tmpMbaSecureFir, bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| + 10|11|12|13|14|15|16|17|18|19| + 20|21|22|23|24|25|26|27|28|29| + 30|31|32|33|34|35|36|37|38|39| + 40|41|42|43|44|45|46|47|48|49| + 50|51|52|53|54|55|56|57|58|59| + 60|61|62|63 )) ? analyze(gMbaSecureFir); + + (tmpMbaDdrPhyFir, bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| + 10|11|12|13|14|15|16|17|18|19| + 20|21|22|23|24|25|26|27|28|29| + 30|31|32|33|34|35|36|37|38|39| + 40|41|42|43|44|45|46|47|48|49| + 50|51|52|53|54|55|56|57|58|59| + 60|61|62|63 )) ? analyze(gMbaDdrPhyFir); + + (tmpMbaCalFir, bit( 0| 1| 2| 3| 4| 5| 6| 7| 8| 9| + 10|11|12|13|14|15|16|17|18|19| + 20|21|22|23|24|25|26|27|28|29| + 30|31|32|33|34|35|36|37|38|39| + 40|41|42|43|44|45|46|47|48|49| + 50|51|52|53|54|55|56|57|58|59| + 60|61|62|63 )) ? analyze(gMbaCalFir); +}; + +################################################################################ +# MEM Chiplet MBAFIR +################################################################################ + +rule MbaFir +{ + CHECK_STOP: MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & ~MBAFIR_ACT1; + RECOVERABLE: MBAFIR & ~MBAFIR_MASK & ~MBAFIR_ACT0 & MBAFIR_ACT1; +}; + +group gMbaFir filter singlebit +{ + /** MBAFIR[0] + * MBAFIRQ_INVALID_MAINT_CMD + */ + (MbaFir, bit(0)) ? TBDDefaultCallout; + + /** MBAFIR[1] + * MBAFIRQ_INVALID_MAINT_ADDRESS + */ + (MbaFir, bit(1)) ? TBDDefaultCallout; + + /** MBAFIR[2] + * MBAFIRQ_MULTI_ADDRESS_MAINT_TIMEOU + */ + (MbaFir, bit(2)) ? TBDDefaultCallout; + + /** MBAFIR[3] + * MBAFIRQ_INTERNAL_FSM_ERROR + */ + (MbaFir, bit(3)) ? TBDDefaultCallout; + + /** MBAFIR[4] + * MBAFIRQ_MCBIST_ERROR + */ + (MbaFir, bit(4)) ? TBDDefaultCallout; + + /** MBAFIR[5] + * MBAFIRQ_SCOM_CMD_REG_PE + */ + (MbaFir, bit(5)) ? TBDDefaultCallout; + + /** MBAFIR[6] + * MBAFIRQ_CHANNEL_CHKSTP_ERR + */ + (MbaFir, bit(6)) ? TBDDefaultCallout; + + /** MBAFIR[7] + * MBAFIRQ_WRD_CAW2_DATA_CE_UE_ERR + */ + (MbaFir, bit(7)) ? TBDDefaultCallout; + + /** MBAFIR[15] + * MBAFIRQ_INTERNAL_SCOM_ERROR + */ + (MbaFir, bit(15)) ? TBDDefaultCallout; + + /** MBAFIR[16] + * MBAFIRQ_INTERNAL_SCOM_ERROR_CLONE + */ + (MbaFir, bit(16)) ? TBDDefaultCallout; +}; + +################################################################################ +# MEM Chiplet MBASECUREFIR +################################################################################ + +rule MbaSecureFir +{ + CHECK_STOP: + MBASECUREFIR & ~MBASECUREFIR_MASK & ~MBASECUREFIR_ACT0 & ~MBASECUREFIR_ACT1; + # NOTE: This secure FIR will only report checkstop attentions. +}; + +group gMbaSecureFir filter singlebit +{ + /** MBASECUREFIR[0] + * MBASIRQ_INVALID_MBA_CAL0Q_ACCESS + */ + (MbaSecureFir, bit(0)) ? TBDDefaultCallout; + + /** MBASECUREFIR[1] + * MBASIRQ_INVALID_MBA_CAL1Q_ACCESS + */ + (MbaSecureFir, bit(1)) ? TBDDefaultCallout; + + /** MBASECUREFIR[2] + * MBASIRQ_INVALID_MBA_CAL2Q_ACCESS + */ + (MbaSecureFir, bit(2)) ? TBDDefaultCallout; + + /** MBASECUREFIR[3] + * MBASIRQ_INVALID_MBA_CAL3Q_ACCESS + */ + (MbaSecureFir, bit(3)) ? TBDDefaultCallout; + + /** MBASECUREFIR[4] + * MBASIRQ_INVALID_DDR_CONFIG_REG_ACCESS + */ + (MbaSecureFir, bit(4)) ? TBDDefaultCallout; + + /** MBASECUREFIR[5] + * MBASIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS + */ + (MbaSecureFir, bit(5)) ? TBDDefaultCallout; +}; + +################################################################################ +# MEM Chiplet DDRPHYFIR +################################################################################ + +rule MbaDdrPhyFir +{ + CHECK_STOP: + MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & ~MBADDRPHYFIR_ACT1; + RECOVERABLE: + MBADDRPHYFIR & ~MBADDRPHYFIR_MASK & ~MBADDRPHYFIR_ACT0 & MBADDRPHYFIR_ACT1; +}; + +group gMbaDdrPhyFir filter singlebit +{ + /** MBADDRPHYFIR[48] + * PHY01_DDRPHY_FIR_REG_DDR0_FSM_CKSTP + */ + (MbaDdrPhyFir, bit(48)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[49] + * PHY01_DDRPHY_FIR_REG_DDR0_PARITY_CKSTP + */ + (MbaDdrPhyFir, bit(49)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[50] + * PHY01_DDRPHY_FIR_REG_DDR0_CALIBRATION_ERROR + */ + (MbaDdrPhyFir, bit(50)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[51] + * PHY01_DDRPHY_FIR_REG_DDR0_FSM_ERR + */ + (MbaDdrPhyFir, bit(51)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[52] + * PHY01_DDRPHY_FIR_REG_DDR0_PARITY_ERR + */ + (MbaDdrPhyFir, bit(52)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[53] + * PHY01_DDRPHY_FIR_REG_DDR01_FIR_PARITY_ERR + */ + (MbaDdrPhyFir, bit(53)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[56] + * PHY01_DDRPHY_FIR_REG_DDR1_FSM_CKSTP + */ + (MbaDdrPhyFir, bit(56)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[57] + * PHY01_DDRPHY_FIR_REG_DDR1_PARITY_CKSTP + */ + (MbaDdrPhyFir, bit(57)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[58] + * PHY01_DDRPHY_FIR_REG_DDR1_CALIBRATION_ERROR + */ + (MbaDdrPhyFir, bit(58)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[59] + * PHY01_DDRPHY_FIR_REG_DDR1_FSM_ERR + */ + (MbaDdrPhyFir, bit(59)) ? TBDDefaultCallout; + + /** MBADDRPHYFIR[60] + * PHY01_DDRPHY_FIR_REG_DDR1_PARITY_ERR + */ + (MbaDdrPhyFir, bit(60)) ? TBDDefaultCallout; +}; + +################################################################################ +# MEM Chiplet MBACALFIR +################################################################################ + +rule MbaCalFir +{ + CHECK_STOP: MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & ~MBACALFIR_ACT1; + RECOVERABLE: MBACALFIR & ~MBACALFIR_MASK & ~MBACALFIR_ACT0 & MBACALFIR_ACT1; +}; + +group gMbaCalFir filter singlebit +{ + /** MBACALFIR[0] + * MBACALFIRQ_MBA_RECOVERABLE_ERROR + */ + (MbaCalFir, bit(0)) ? TBDDefaultCallout; + + /** MBACALFIR[1] + * MBACALFIRQ_MBA_NONRECOVERABLE_ERROR + */ + (MbaCalFir, bit(1)) ? TBDDefaultCallout; + + /** MBACALFIR[2] + * MBACALFIRQ_REFRESH_OVERRUN + */ + (MbaCalFir, bit(2)) ? TBDDefaultCallout; + + /** MBACALFIR[3] + * MBACALFIRQ_WAT_ERROR + */ + (MbaCalFir, bit(3)) ? TBDDefaultCallout; + + /** MBACALFIR[4] + * MBACALFIRQ_RCD_PARITY_ERROR_0 + */ + (MbaCalFir, bit(4)) ? TBDDefaultCallout; + + /** MBACALFIR[5] + * MBACALFIRQ_DDR0_CAL_TIMEOUT_ERR + */ + (MbaCalFir, bit(5)) ? TBDDefaultCallout; + + /** MBACALFIR[6] + * MBACALFIRQ_DDR1_CAL_TIMEOUT_ERR + */ + (MbaCalFir, bit(6)) ? TBDDefaultCallout; + + /** MBACALFIR[7] + * MBACALFIRQ_RCD_PARITY_ERROR_1 + */ + (MbaCalFir, bit(7)) ? TBDDefaultCallout; + + /** MBACALFIR[8] + * MBACALFIRQ_MBX_TO_MBA_PAR_ERROR + */ + (MbaCalFir, bit(8)) ? TBDDefaultCallout; + + /** MBACALFIR[9] + * MBACALFIRQ_MBA_WRD_UE + */ + (MbaCalFir, bit(9)) ? TBDDefaultCallout; + + /** MBACALFIR[10] + * MBACALFIRQ_MBA_WRD_CE + */ + (MbaCalFir, bit(10)) ? TBDDefaultCallout; + + /** MBACALFIR[11] + * MBACALFIRQ_MBA_MAINT_UE + */ + (MbaCalFir, bit(11)) ? TBDDefaultCallout; + + /** MBACALFIR[12] + * MBACALFIRQ_MBA_MAINT_CE + */ + (MbaCalFir, bit(12)) ? TBDDefaultCallout; + + /** MBACALFIR[13] + * MBACALFIRQ_DDR_CAL_RESET_TIMEOUT + */ + (MbaCalFir, bit(13)) ? TBDDefaultCallout; + + /** MBACALFIR[14] + * MBACALFIRQ_WRQ_DATA_CE + */ + (MbaCalFir, bit(14)) ? TBDDefaultCallout; + + /** MBACALFIR[15] + * MBACALFIRQ_WRQ_DATA_UE + */ + (MbaCalFir, bit(15)) ? TBDDefaultCallout; + + /** MBACALFIR[16] + * MBACALFIRQ_WRQ_DATA_SUE + */ + (MbaCalFir, bit(16)) ? TBDDefaultCallout; + + /** MBACALFIR[17] + * MBACALFIRQ_WRQ_RRQ_HANG_ERR + */ + (MbaCalFir, bit(17)) ? TBDDefaultCallout; + + /** MBACALFIR[18] + * MBACALFIRQ_SM_1HOT_ERR + */ + (MbaCalFir, bit(18)) ? TBDDefaultCallout; + + /** MBACALFIR[19] + * MBACALFIRQ_WRD_SCOM_ERROR + */ + (MbaCalFir, bit(19)) ? TBDDefaultCallout; + + /** MBACALFIR[20] + * MBACALFIRQ_INTERNAL_SCOM_ERROR + */ + (MbaCalFir, bit(20)) ? TBDDefaultCallout; + + /** MBACALFIR[21] + * MBACALFIRQ_INTERNAL_SCOM_ERROR_COPY + */ + (MbaCalFir, bit(21)) ? TBDDefaultCallout; +}; + +############################################################################### +# MEM Chiplet MBASPA +################################################################################ + +rule MbaSpa +{ + SPECIAL: MBASPA & ~MBASPA_MASK; +}; + +group gMbaSpa attntype SPECIAL filter singlebit +{ + /** MBASPA[0] + * MBSPAQ_COMMAND_COMPLETE_WO_ENA_ERR_ATTN + */ + (MbaSpa, bit(0)) ? analyzeMaintCmdComplete; + + /** MBASPA[1] + * MBSPAQ_HARD_CE_ETE_ATTN + */ + (MbaSpa, bit(1)) ? TBDDefaultCallout; + + /** MBASPA[2] + * MBSPAQ_SOFT_CE_ETE_ATTN + */ + (MbaSpa, bit(2)) ? TBDDefaultCallout; + + /** MBASPA[3] + * MBSPAQ_INTERMITTENT_ETE_ATTN + */ + (MbaSpa, bit(3)) ? TBDDefaultCallout; + + /** MBASPA[4] + * MBSPAQ_RCE_ETE_ATTN + */ + (MbaSpa, bit(4)) ? TBDDefaultCallout; + + /** MBASPA[5] + * MBSPAQ_EMERGENCY_THROTTLE_ATTN + */ + (MbaSpa, bit(5)) ? TBDDefaultCallout; + + /** MBASPA[6] + * MBSPAQ_FIRMWARE_ATTN0 + */ + (MbaSpa, bit(6)) ? TBDDefaultCallout; + + /** MBASPA[7] + * MBSPAQ_FIRMWARE_ATTN1 + */ + (MbaSpa, bit(7)) ? TBDDefaultCallout; + + /** MBASPA[8] + * MBSPAQ_WAT_DEBUG_ATTN + */ + (MbaSpa, bit(8)) ? TBDDefaultCallout; + + /** MBASPA[9] + * MBSPAQ_SPARE_ATTN1 + */ + (MbaSpa, bit(9)) ? TBDDefaultCallout; + + /** MBASPA[10] + * MBSPAQ_MCBIST_DONE + */ + (MbaSpa, bit(10)) ? TBDDefaultCallout; +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule"; + +################################################################################ +# Higher level actions +################################################################################ + +/** Analyze maintenance command complete */ +actionclass analyzeMaintCmdComplete { funccall("MaintCmdComplete"); }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Mcs.rule b/src/usr/diag/prdf/plat/pegasus/Mcs.rule new file mode 100644 index 000000000..19c99e96b --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Mcs.rule @@ -0,0 +1,329 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Mcs.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Scope: +# Registers and actions for the following chiplets: +# Note that only addresses for MC0/MCS0 will be used. +# +# Chiplet Register Addresses Description +# ======= ======================= ============================================ +# MCS 0x02011800 - 0x0201187F MC0/MCS0 +# MCS 0x02011880 - 0x020118FF MC0/MCS1 +# MCS 0x02011900 - 0x0201197F MC1/MCS0 +# MCS 0x02011980 - 0x020119FF MC1/MCS1 +# MCS 0x02011A00 - 0x02011A3E DMI0 - DMI3 +# MCS 0x02011C00 - 0x02011C7F MC2/MCS0 +# MCS 0x02011C80 - 0x02011CFF MC2/MCS1 +# MCS 0x02011D00 - 0x02011D7F MC3/MCS0 +# MCS 0x02011D80 - 0x02011DFF MC3/MCS1 +# MCS 0x02011E00 - 0x02011E3E DMI4 - DMI7 +# +################################################################################ + +chip Mcs +{ + name "Power8 MCS Chiplet"; + targettype TYPE_MCS; + sigoff 0x8000; +# FIXME May need to update dump type + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # PB Chiplet MCIFIR + ############################################################################ + + register MCIFIR + { + name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRQ"; + scomaddr 0x02011840; + reset (&, 0x02011841); + mask (|, 0x02011845); + capture group default; + }; + + register MCIFIR_AND + { + name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRQ AND"; + scomaddr 0x02011841; + capture group never; + }; + + register MCIFIR_MASK + { + name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRMASK"; + scomaddr 0x02011843; + capture type secondary; + capture group default; + }; + + register MCIFIR_ACT0 + { + name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRACT0"; + scomaddr 0x02011846; + capture type secondary; + capture group default; + }; + + register MCIFIR_ACT1 + { + name "MC0.MCS0.RIGHT.MCI.SCOMFIR.MCIFIRACT1"; + scomaddr 0x02011847; + capture type secondary; + capture group default; + }; +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# PB Chiplet MCIFIR +################################################################################ + +rule MciFir +{ + CHECK_STOP: MCIFIR & ~MCIFIR_MASK & ~MCIFIR_ACT0 & ~MCIFIR_ACT1; + RECOVERABLE: MCIFIR & ~MCIFIR_MASK & ~MCIFIR_ACT0 & MCIFIR_ACT1; + SPECIAL: MCIFIR & ~MCIFIR_MASK & MCIFIR_ACT0 & ~MCIFIR_ACT1; +}; + +group gMciFir attntype CHECK_STOP, RECOVERABLE, SPECIAL filter singlebit +{ + /** MCIFIR[0] + * MCIFIRQ_REPLAY_TIMEOUT + */ + (MciFir, bit(0)) ? TBDDefaultCallout; + + /** MCIFIR[1] + * MCIFIRQ_CHANNEL_FAIL + */ + (MciFir, bit(1)) ? TBDDefaultCallout; + + /** MCIFIR[2] + * MCIFIRQ_CRC_ERROR + */ + (MciFir, bit(2)) ? TBDDefaultCallout; + + /** MCIFIR[3] + * MCIFIRQ_FRAME_NOACK + */ + (MciFir, bit(3)) ? TBDDefaultCallout; + + /** MCIFIR[4] + * MCIFIRQ_SEQID_OUT_OF_ORDER + */ + (MciFir, bit(4)) ? TBDDefaultCallout; + + /** MCIFIR[5] + * MCIFIRQ_REPLAY_BUFFER_ECC_CE + */ + (MciFir, bit(5)) ? TBDDefaultCallout; + + /** MCIFIR[6] + * MCIFIRQ_REPLAY_BUFFER_ECC_UE + */ + (MciFir, bit(6)) ? TBDDefaultCallout; + + /** MCIFIR[7] + * MCIFIRQ_MCI_CHINIT_STATE_MACHINE_TIMEOUT + */ + (MciFir, bit(7)) ? TBDDefaultCallout; + + /** MCIFIR[8] + * MCIFIRQ_MCI_INTERNAL_CONTROL_PARITY_ERROR + */ + (MciFir, bit(8)) ? TBDDefaultCallout; + + /** MCIFIR[9] + * MCIFIRQ_MCI_DATA_FLOW_PARITY_ERROR + */ + (MciFir, bit(9)) ? TBDDefaultCallout; + + /** MCIFIR[10] + * MCIFIRQ_CRC_PERFORMANCE_DEGRADATION + */ + (MciFir, bit(10)) ? TBDDefaultCallout; + + /** MCIFIR[11] + * MCIFIRQ_CHANNEL_INTERLOCK_FAIL + */ + (MciFir, bit(11)) ? TBDDefaultCallout; + + /** MCIFIR[12] + * MCIFIRQ_CENTAUR_CHECKSTOP + */ + (MciFir, bit(12)) ? TBDDefaultCallout; + + /** MCIFIR[13] + * MCIFIRQ_CENTAUR_TRACESTOP + */ + (MciFir, bit(13)) ? TBDDefaultCallout; + + /** MCIFIR[14] + * MCIFIRQ_FPGA_INTERRUPT + */ + (MciFir, bit(14)) ? TBDDefaultCallout; + + /** MCIFIR[15] + * MCIFIRQ_CENTAUR_RECOVERABLE_ERROR + */ + (MciFir, bit(15)) ? TBDDefaultCallout; + + /** MCIFIR[16] + * MCIFIRQ_CENTAUR_SPECIAL_ATTENTION + */ + (MciFir, bit(16)) ? TBDDefaultCallout; + + /** MCIFIR[17] + * MCIFIRQ_CENTAUR_MAINTENANCE_COMPLETE + */ + (MciFir, bit(17)) ? TBDDefaultCallout; + + /** MCIFIR[18] + * MCIFIRQ_CENTAUR_INBAND_PIB_ERROR + */ + (MciFir, bit(18)) ? TBDDefaultCallout; + + /** MCIFIR[24] + * MCIFIRQ_MCS_RECOVERABLE_ERROR + */ + (MciFir, bit(24)) ? TBDDefaultCallout; + + /** MCIFIR[25] + * MCIFIRQ_MCS_INTERNAL_NONRECOVERABLE_ERROR + */ + (MciFir, bit(25)) ? TBDDefaultCallout; + + /** MCIFIR[26] + * MCIFIRQ_POWERBUS_PROTOCOL_ERROR + */ + (MciFir, bit(26)) ? TBDDefaultCallout; + + /** MCIFIR[27] + * MCIFIRQ_MCS_COMMAND_LIST_TIMEOUT_DUE_TO_POWERBUS + */ + (MciFir, bit(27)) ? TBDDefaultCallout; + + /** MCIFIR[28] + * MCIFIRQ_MCS_COMMAND_LIST_TIMEOUT_DUE_TO_EDI_CHANNEL + */ + (MciFir, bit(28)) ? TBDDefaultCallout; + + /** MCIFIR[29] + * MCIFIRQ_INBAND_BAR_HIT_WITH_INCORRECT_TTYPE + */ + (MciFir, bit(29)) ? TBDDefaultCallout; + + /** MCIFIR[30] + * MCIFIRQ_MULTIPLE_BAR_HIT + */ + (MciFir, bit(30)) ? TBDDefaultCallout; + + /** MCIFIR[31] + * MCIFIRQ_CHANNEL_FAIL_SIGNAL_ACTIVE + */ + (MciFir, bit(31)) ? TBDDefaultCallout; + + /** MCIFIR[32] + * MCIFIRQ_MIRROR_ACTION_OCCURRED + */ + (MciFir, bit(32)) ? TBDDefaultCallout; + + /** MCIFIR[33] + * MCIFIRQ_NONFOREIGN_ACCESS_TO_FOREIGN_BAR + */ + (MciFir, bit(33)) ? TBDDefaultCallout; + + /** MCIFIR[34] + * MCIFIRQ_CENTAUR_SYNC_COMMAND_DETECTED + */ + (MciFir, bit(34)) ? TBDDefaultCallout; + + /** MCIFIR[35] + * MCIFIRQ_POWERBUS_WRITE_DATA_BUFFER_CE + */ + (MciFir, bit(35)) ? TBDDefaultCallout; + + /** MCIFIR[36] + * MCIFIRQ_POWERBUS_WRITE_DATA_BUFFER_UE + */ + (MciFir, bit(36)) ? TBDDefaultCallout; + + /** MCIFIR[37] + * MCIFIRQ_POWERBUS_WRITE_DATA_BUFFER_SUE + */ + (MciFir, bit(37)) ? TBDDefaultCallout; + + /** MCIFIR[38] + * MCIFIRQ_HA_ILLEGAL_CONSUMER_ACCESS_ERROR + */ + (MciFir, bit(38)) ? TBDDefaultCallout; + + /** MCIFIR[48] + * MCIFIRQ_INTERNAL_SCOM_ERROR + */ + (MciFir, bit(48)) ? TBDDefaultCallout; + + /** MCIFIR[49] + * MCIFIRQ_INTERNAL_SCOM_ERROR_CLONE + */ + (MciFir, bit(49)) ? TBDDefaultCallout; +}; + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule" + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf.rule b/src/usr/diag/prdf/plat/pegasus/Membuf.rule new file mode 100644 index 000000000..549f2eac6 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf.rule @@ -0,0 +1,163 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Scope: +# Registers and actions for the following chiplets: +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# TP 0x01000000 - 0x01FFFFFF TP pervasive logic +# NEST 0x02000000 - 0x02FFFFFF NEST pervasive logic +# MEM 0x03000000 - 0x03FFFFFF MEM pervasive logic, note that this does +# include the SCOM addresses characterized by +# the MBA target. See Mba.rule for those +# address ranges. +# +################################################################################ + +chip Membuf +{ + name "Centaur Chip"; + targettype TYPE_MEMBUF; + sigoff 0x8000; +# FIXME May need to update dump type + dump DUMP_CONTENT_HWSUPERNOVA; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # Global Broadcast Registers + ############################################################################ + + register GLOBAL_CS_FIR + { + name "Global Checkstop Attention FIR"; + scomaddr 0x570F001C; + capture group default; + }; + + register GLOBAL_RE_FIR + { + name "Global Recoverable Attention FIR"; + scomaddr 0x570F001B; + capture group default; + }; + + register GLOBAL_SPA + { + name "Global Special Attention FIR"; + scomaddr 0x570F001A; + capture group default; + }; + +# Import all of the chiplet registers +.include "Membuf_regs_TP.rule" +.include "Membuf_regs_NEST.rule" +.include "Membuf_regs_MEM.rule" + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Global Broadcast Registers +################################################################################ + +rule GlobalFir +{ + CHECK_STOP: GLOBAL_CS_FIR; + RECOVERABLE: GLOBAL_RE_FIR; +}; + +group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit +{ + /** GLOBAL_FIR[1] + * Attention from TP chiplet + */ + (GlobalFir, bit(1)) ? analyze(gTpChipletFir); + + /** GLOBAL_FIR[2] + * Attention from NEST chiplet + */ + (GlobalFir, bit(2)) ? analyze(gNestChipletFir); + + /** GLOBAL_FIR[3] + * Attention from MEM chiplet + */ + (GlobalFir, bit(3)) ? analyze(gMemChipletFir); +}; + +rule GlobalSpa +{ + SPECIAL: GLOBAL_SPA; +}; + +group gGlobalSpa attntype SPECIAL filter singlebit +{ + /** GLOBAL_SPA[3] + * Attention from MEM chiplet + */ + (GlobalSpa, bit(3)) ? analyze(gMemChipletSpa); +}; + +# Import all of the chiplet rules and actions +.include "Membuf_acts_TP.rule" +.include "Membuf_acts_NEST.rule" +.include "Membuf_acts_MEM.rule" + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule" + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_acts_MEM.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_acts_MEM.rule new file mode 100644 index 000000000..69b85f7b8 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf_acts_MEM.rule @@ -0,0 +1,229 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_acts_MEM.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# MEM Chiplet Registers +################################################################################ + +rule MemChipletFir +{ + CHECK_STOP: + (MEM_CHIPLET_CS_FIR & `17f6000000000000`) & ~MEM_CHIPLET_FIR_MASK; + RECOVERABLE: + ((MEM_CHIPLET_RE_FIR >> 2) & `17f6000000000000`) & ~MEM_CHIPLET_FIR_MASK; +}; + +group gMemChipletFir filter singlebit +{ + /** MEM_CHIPLET_FIR[3] + * Attention from LFIR + */ + (MemChipletFir, bit(3)) ? analyze(gMemLFir); + + /** MEM_CHIPLET_FIR[5] + * Attention from MBAFIR (MBA 01) + */ + (MemChipletFir, bit(5)) ? analyzeMba0; + + /** MEM_CHIPLET_FIR[6] + * Attention from MBAFIR (MBA 23) + */ + (MemChipletFir, bit(6)) ? analyzeMba1; + + /** MEM_CHIPLET_FIR[7] + * Attention from MBACALFIR (MBA 01) + */ + (MemChipletFir, bit(7)) ? analyzeMba0; + + /** MEM_CHIPLET_FIR[8] + * Attention from MBACALFIR (MBA 23) + */ + (MemChipletFir, bit(8)) ? analyzeMba1; + + /** MEM_CHIPLET_FIR[9] + * Attention from DDRPHYFIR (MBA 01) + */ + (MemChipletFir, bit(9)) ? analyzeMba0; + + /** MEM_CHIPLET_FIR[10] + * Attention from DDRPHYFIR (MBA 23) + */ + (MemChipletFir, bit(10)) ? analyzeMba1; + + /** MEM_CHIPLET_FIR[11] + * Attention from MEMFBISTFIR + */ + (MemChipletFir, bit(11)) ? analyze(gMemFbistFir); + + /** MEM_CHIPLET_FIR[12] + * Attention from MBASECUREFIR (MBA 01) + */ + (MemChipletFir, bit(12)) ? analyzeMba0; + + /** MEM_CHIPLET_FIR[13] + * Attention from MBASECUREFIR (MBA 23) + */ + (MemChipletFir, bit(13)) ? analyzeMba1; +}; + +rule MemChipletSpa +{ + SPECIAL: MEM_CHIPLET_SPA & ~MEM_CHIPLET_SPA_MASK; +}; + +group gMemChipletSpa filter singlebit +{ + /** MEM_CHIPLET_SPA[0] + * Attention from Mba 01 + */ + (MemChipletSpa, bit(0)) ? analyzeMba0; + + /** MEM_CHIPLET_SPA[1] + * Attention from Mba 1 + */ + (MemChipletSpa, bit(1)) ? analyzeMba1; +}; + +################################################################################ +# MEM Chiplet LFIR +################################################################################ + +rule MemLFir +{ + CHECK_STOP: MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & ~MEM_LFIR_ACT1; + RECOVERABLE: MEM_LFIR & ~MEM_LFIR_MASK & ~MEM_LFIR_ACT0 & MEM_LFIR_ACT1; +}; + +group gMemLFir filter singlebit +{ + /** MEM_LFIR[0] + * CFIR internal parity error + */ + (MemLFir, bit(0)) ? TBDDefaultCallout; + + /** MEM_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (MemLFir, bit(1)) ? TBDDefaultCallout; + + /** MEM_LFIR[2] + * Local errors from CC (PCB error) + */ + (MemLFir, bit(2)) ? TBDDefaultCallout; + + /** MEM_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (MemLFir, bit(3)) ? TBDDefaultCallout; + + /** MEM_LFIR[4] + * Local errors from PSC (PCB error) + */ + (MemLFir, bit(4)) ? TBDDefaultCallout; + + /** MEM_LFIR[5] + * Local errors from PSC (parity error) + */ + (MemLFir, bit(5)) ? TBDDefaultCallout; + + /** MEM_LFIR[6] + * Local errors from Thermal (parity error) + */ + (MemLFir, bit(6)) ? TBDDefaultCallout; + + /** MEM_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (MemLFir, bit(7)) ? TBDDefaultCallout; + + /** MEM_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (MemLFir, bit(8|9)) ? TBDDefaultCallout; + + /** MEM_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (MemLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# MEM Chiplet MEMFBISTFIR +################################################################################ + +rule MemFbistFir +{ + CHECK_STOP: + MEMFBISTFIR & ~MEMFBISTFIR_MASK & ~MEMFBISTFIR_ACT0 & ~MEMFBISTFIR_ACT1; + RECOVERABLE: + MEMFBISTFIR & ~MEMFBISTFIR_MASK & ~MEMFBISTFIR_ACT0 & MEMFBISTFIR_ACT1; +}; + +group gMemFbistFir filter singlebit +{ + /** MBAFBISTFIR[0] + * FBM_FIR_REG_FBM_SCOM_UE + */ + (MemFbistFir, bit(0)) ? TBDDefaultCallout; + + /** MBAFBISTFIR[1] + * FBM_FIR_REG_FBM_CMD_CHK_1HOT + */ + (MemFbistFir, bit(1)) ? TBDDefaultCallout; + + /** MBAFBISTFIR[2] + * FBM_FIR_REG_FBM_DS_DATA_DROP + */ + (MemFbistFir, bit(2)) ? TBDDefaultCallout; + + /** MBAFBISTFIR[3] + * FBM_FIR_REG_FBM_DGEN_1HOT + */ + (MemFbistFir, bit(3)) ? TBDDefaultCallout; + + /** MBAFBISTFIR[4] + * FBM_FIR_REG_FBM_DGEN_RD_DATA_DROP + */ + (MemFbistFir, bit(4)) ? TBDDefaultCallout; + + /** MBAFBISTFIR[15] + * FBM_FIR_REG_INTERNAL_SCOM_ERROR + */ + (MemFbistFir, bit(15)) ? TBDDefaultCallout; + + /** MBAFBISTFIR[16] + * FBM_FIR_REG_INTERNAL_SCOM_ERROR_CLONE + */ + (MemFbistFir, bit(16)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to MEM chiplet +################################################################################ + +/** Analyze connected MBA0 */ +actionclass analyzeMba0 { analyze(connected(TYPE_MBA, 0)); }; + +/** Analyze connected MBA1 */ +actionclass analyzeMba1 { analyze(connected(TYPE_MBA, 1)); }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_acts_NEST.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_acts_NEST.rule new file mode 100644 index 000000000..f94002527 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf_acts_NEST.rule @@ -0,0 +1,1172 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_acts_NEST.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# NEST Chiplet Registers +################################################################################ + +rule NestChipletFir +{ + CHECK_STOP: + (NEST_CHIPLET_CS_FIR & `17fe000000000000`) & ~NEST_CHIPLET_FIR_MASK; + RECOVERABLE: + ((NEST_CHIPLET_RE_FIR >> 2) & `17fe000000000000`) & ~NEST_CHIPLET_FIR_MASK; +}; + +group gNestChipletFir filter singlebit +{ + /** NEST_CHIPLET_FIR[3] + * Attention from LFIR + */ + (NestChipletFir, bit(3)) ? analyze(gNestLFir); + + /** NEST_CHIPLET_FIR[5] + * Attention from DMIFIR + */ + (NestChipletFir, bit(5)) ? analyze(gDmiFir); + + /** NEST_CHIPLET_FIR[6] + * Attention from MBIFIR + */ + (NestChipletFir, bit(6)) ? analyze(gMbiFir); + + /** NEST_CHIPLET_FIR[7] + * Attention from MBSFIR + */ + (NestChipletFir, bit(7)) ? analyze(gMbsFir); + + /** NEST_CHIPLET_FIR[8|9] + * Attention from MBSECCFIRs + */ + (NestChipletFir, bit(8|9)) ? analyze(gMbsEccFir); + + /** NEST_CHIPLET_FIR[10|11] + * Attention from MCBISTFIRs + */ + (NestChipletFir, bit(10|11)) ? analyze(gMcbistFir); + + /** NEST_CHIPLET_FIR[12] + * Attention from NESTFBISTFIR + */ + (NestChipletFir, bit(12))? analyze(gNestFbistFir); + + /** NEST_CHIPLET_FIR[13] + * Attention from SENSORCACHEFIR + */ + (NestChipletFir, bit(13)) ? analyze(gSensorCacheFir); + + /** NEST_CHIPLET_FIR[14] + * Attention from MBS secure FIR + */ + (NestChipletFir, bit(14))? analyze(gMbsSecureFir); +}; + +################################################################################ +# NEST Chiplet LFIR +################################################################################ + +rule NestLFir +{ + CHECK_STOP: NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & ~NEST_LFIR_ACT1; + RECOVERABLE: NEST_LFIR & ~NEST_LFIR_MASK & ~NEST_LFIR_ACT0 & NEST_LFIR_ACT1; +}; + +group gNestLFir filter singlebit +{ + /** NEST_LFIR[0] + * CFIR internal parity error + */ + (NestLFir, bit(0)) ? TBDDefaultCallout; + + /** NEST_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (NestLFir, bit(1)) ? TBDDefaultCallout; + + /** NEST_LFIR[2] + * Local errors from CC (PCB error) + */ + (NestLFir, bit(2)) ? TBDDefaultCallout; + + /** NEST_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (NestLFir, bit(3)) ? TBDDefaultCallout; + + /** NEST_LFIR[4] + * Local errors from PSC (PCB error) + */ + (NestLFir, bit(4)) ? TBDDefaultCallout; + + /** NEST_LFIR[5] + * Local errors from PSC (parity error) + */ + (NestLFir, bit(5)) ? TBDDefaultCallout; + + /** NEST_LFIR[6] + * Local errors from Thermal (parity error) + */ + (NestLFir, bit(6)) ? TBDDefaultCallout; + + /** NEST_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (NestLFir, bit(7)) ? TBDDefaultCallout; + + /** NEST_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (NestLFir, bit(8|9)) ? TBDDefaultCallout; + + /** NEST_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (NestLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet DMIFIR +################################################################################ + +rule DmiFir +{ + CHECK_STOP: DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & ~DMIFIR_ACT1; + RECOVERABLE: DMIFIR & ~DMIFIR_MASK & ~DMIFIR_ACT0 & DMIFIR_ACT1; +}; + +group gDmiFir filter singlebit +{ + /** DMIFIR[0] + * FIR_RX_INVALID_STATE_OR_PARITY_ERROR + */ + (DmiFir, bit(0)) ? TBDDefaultCallout; + + /** DMIFIR[1] + * FIR_TX_INVALID_STATE_OR_PARITY_ERROR + */ + (DmiFir, bit(1)) ? TBDDefaultCallout; + + /** DMIFIR[2] + * FIR_GCR_HANG_ERROR + */ + (DmiFir, bit(2)) ? TBDDefaultCallout; + + /** DMIFIR[8] + * FIR_RX_BUS0_TRAINING_ERROR + */ + (DmiFir, bit(8)) ? TBDDefaultCallout; + + /** DMIFIR[9] + * FIR_RX_BUS0_SPARE_DEPLOYED + */ + (DmiFir, bit(9)) ? TBDDefaultCallout; + + /** DMIFIR[10] + * FIR_RX_BUS0_MAX_SPARES_EXCEEDED + */ + (DmiFir, bit(10)) ? TBDDefaultCallout; + + /** DMIFIR[11] + * FIR_RX_BUS0_RECAL_OR_DYN_REPAIR_ERROR + */ + (DmiFir, bit(11)) ? TBDDefaultCallout; + + /** DMIFIR[12] + * FIR_RX_BUS0_TOO_MANY_BUS_ERRORS + */ + (DmiFir, bit(12)) ? TBDDefaultCallout; + + /** DMIFIR[16] + * FIR_RX_BUS1_TRAINING_ERROR + */ + (DmiFir, bit(16)) ? TBDDefaultCallout; + + /** DMIFIR[17] + * FIR_RX_BUS1_SPARE_DEPLOYED + */ + (DmiFir, bit(17)) ? TBDDefaultCallout; + + /** DMIFIR[18] + * FIR_RX_BUS1_MAX_SPARES_EXCEEDED + */ + (DmiFir, bit(18)) ? TBDDefaultCallout; + + /** DMIFIR[19] + * FIR_RX_BUS1_RECAL_OR_DYN_REPAIR_ERROR + */ + (DmiFir, bit(19)) ? TBDDefaultCallout; + + /** DMIFIR[20] + * FIR_RX_BUS1_TOO_MANY_BUS_ERRORS + */ + (DmiFir, bit(20)) ? TBDDefaultCallout; + + /** DMIFIR[24] + * FIR_RX_BUS2_TRAINING_ERROR + */ + (DmiFir, bit(24)) ? TBDDefaultCallout; + + /** DMIFIR[25] + * FIR_RX_BUS2_SPARE_DEPLOYED + */ + (DmiFir, bit(25)) ? TBDDefaultCallout; + + /** DMIFIR[26] + * FIR_RX_BUS2_MAX_SPARES_EXCEEDED + */ + (DmiFir, bit(26)) ? TBDDefaultCallout; + + /** DMIFIR[27] + * FIR_RX_BUS2_RECAL_OR_DYN_REPAIR_ERROR + */ + (DmiFir, bit(27)) ? TBDDefaultCallout; + + /** DMIFIR[28] + * FIR_RX_BUS2_TOO_MANY_BUS_ERRORS + */ + (DmiFir, bit(28)) ? TBDDefaultCallout; + + /** DMIFIR[32] + * FIR_RX_BUS3_TRAINING_ERROR + */ + (DmiFir, bit(32)) ? TBDDefaultCallout; + + /** DMIFIR[33] + * FIR_RX_BUS3_SPARE_DEPLOYED + */ + (DmiFir, bit(33)) ? TBDDefaultCallout; + + /** DMIFIR[34] + * FIR_RX_BUS3_MAX_SPARES_EXCEEDED + */ + (DmiFir, bit(34)) ? TBDDefaultCallout; + + /** DMIFIR[35] + * FIR_RX_BUS3_RECAL_OR_DYN_REPAIR_ERROR + */ + (DmiFir, bit(35)) ? TBDDefaultCallout; + + /** DMIFIR[36] + * FIR_RX_BUS3_TOO_MANY_BUS_ERRORS + */ + (DmiFir, bit(36)) ? TBDDefaultCallout; + + /** DMIFIR[40] + * FIR_RX_BUS4_TRAINING_ERROR + */ + (DmiFir, bit(40)) ? TBDDefaultCallout; + + /** DMIFIR[41] + * FIR_RX_BUS4_SPARE_DEPLOYED + */ + (DmiFir, bit(41)) ? TBDDefaultCallout; + + /** DMIFIR[42] + * FIR_RX_BUS4_MAX_SPARES_EXCEEDED + */ + (DmiFir, bit(42)) ? TBDDefaultCallout; + + /** DMIFIR[43] + * FIR_RX_BUS4_RECAL_OR_DYN_REPAIR_ERROR + */ + (DmiFir, bit(43)) ? TBDDefaultCallout; + + /** DMIFIR[44] + * FIR_RX_BUS4_TOO_MANY_BUS_ERRORS + */ + (DmiFir, bit(44)) ? TBDDefaultCallout; + + /** DMIFIR[48] + * FIR_SCOMFIR_ERROR + */ + (DmiFir, bit(48)) ? TBDDefaultCallout; + + /** DMIFIR[49] + * FIR_SCOMFIR_ERROR_CLONE + */ + (DmiFir, bit(49)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet DMIFIR +################################################################################ + +rule SensorCacheFir +{ + CHECK_STOP: SENSORCACHEFIR & ~SENSORCACHEFIR_MASK & ~SENSORCACHEFIR_ACT0 & ~SENSORCACHEFIR_ACT1; + RECOVERABLE: SENSORCACHEFIR & ~SENSORCACHEFIR_MASK & ~SENSORCACHEFIR_ACT0 & SENSORCACHEFIR_ACT1; +}; + +group gSensorCacheFir filter singlebit +{ + /** SENSORCACHEFIR[0] + * SCAC_LFIR_I2CMINVADDR + */ + (SensorCacheFir, bit(0)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[1] + * SCAC_LFIR_I2CMINVWRITE + */ + (SensorCacheFir, bit(1)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[2] + * SCAC_LFIR_I2CMINVREAD + */ + (SensorCacheFir, bit(2)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[3] + * SCAC_LFIR_I2CMAPAR + */ + (SensorCacheFir, bit(3)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[4] + * SCAC_LFIR_I2CMPAR + */ + (SensorCacheFir, bit(4)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[5] + * SCAC_LFIR_I2CMLBPAR + */ + (SensorCacheFir, bit(5)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[10] + * SCAC_LFIR_I2CMINVCMD + */ + (SensorCacheFir, bit(10)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[11] + * SCAC_LFIR_I2CMPERR + */ + (SensorCacheFir, bit(11)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[12] + * SCAC_LFIR_I2CMOVERRUN + */ + (SensorCacheFir, bit(12)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[13] + * SCAC_LFIR_I2CMACCESS + */ + (SensorCacheFir, bit(13)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[14] + * SCAC_LFIR_I2CMARB + */ + (SensorCacheFir, bit(14)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[15] + * SCAC_LFIR_I2CMNACK + */ + (SensorCacheFir, bit(15)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[16] + * SCAC_LFIR_I2CMSTOP + */ + (SensorCacheFir, bit(16)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[17] + * SCAC_LFIR_LOCALPIB1 + */ + (SensorCacheFir, bit(17)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[18] + * SCAC_LFIR_LOCALPIB2 + */ + (SensorCacheFir, bit(18)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[19] + * SCAC_LFIR_LOCALPIB3 + */ + (SensorCacheFir, bit(19)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[20] + * SCAC_LFIR_LOCALPIB4 + */ + (SensorCacheFir, bit(20)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[21] + * SCAC_LFIR_LOCALPIB5 + */ + (SensorCacheFir, bit(21)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[22] + * SCAC_LFIR_LOCALPIB6 + */ + (SensorCacheFir, bit(22)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[23] + * SCAC_LFIR_LOCALPIB7 + */ + (SensorCacheFir, bit(23)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[24] + * SCAC_LFIR_STALLERROR + */ + (SensorCacheFir, bit(24)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[25] + * SCAC_LFIR_REGPARERR + */ + (SensorCacheFir, bit(25)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[26] + * SCAC_LFIR_REGPARERRX + */ + (SensorCacheFir, bit(26)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[32] + * SCAC_LFIR_SMERR + */ + (SensorCacheFir, bit(32)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[33] + * SCAC_LFIR_REGACCERR + */ + (SensorCacheFir, bit(33)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[34] + * SCAC_LFIR_RESETERR + */ + (SensorCacheFir, bit(34)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[35] + * SCAC_LFIR_INTERNAL_SCOM_ERROR + */ + (SensorCacheFir, bit(35)) ? TBDDefaultCallout; + + /** SENSORCACHEFIR[36] + * SCAC_LFIR_INTERNAL_SCOM_ERROR_CLONE + */ + (SensorCacheFir, bit(36)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet MBIFIR +################################################################################ + +rule MbiFir +{ + CHECK_STOP: MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & ~MBIFIR_ACT1; + RECOVERABLE: MBIFIR & ~MBIFIR_MASK & ~MBIFIR_ACT0 & MBIFIR_ACT1; +}; + +group gMbiFir filter singlebit +{ + /** MbiFir[0] + * MBIFIRQ_REPLAY_TIMEOUT + */ + (MbiFir, bit(0)) ? TBDDefaultCallout; + + /** MbiFir[1] + * MBIFIRQ_CHANNEL_FAIL + */ + (MbiFir, bit(1)) ? TBDDefaultCallout; + + /** MbiFir[2] + * MBIFIRQ_CRC_ERROR + */ + (MbiFir, bit(2)) ? TBDDefaultCallout; + + /** MbiFir[3] + * MBIFIRQ_FRAME_NOACK + */ + (MbiFir, bit(3)) ? TBDDefaultCallout; + + /** MbiFir[4] + * MBIFIRQ_SEQID_OUT_OF_ORDER + */ + (MbiFir, bit(4)) ? TBDDefaultCallout; + + /** MbiFir[5] + * MBIFIRQ_REPLAY_BUFFER_ECC_CE + */ + (MbiFir, bit(5)) ? TBDDefaultCallout; + + /** MbiFir[6] + * MBIFIRQ_REPLAY_BUFFER_ECC_UE + */ + (MbiFir, bit(6)) ? TBDDefaultCallout; + + /** MbiFir[7] + * MBIFIRQ_MBI_STATE_MACHINE_TIMEOUT + */ + (MbiFir, bit(7)) ? TBDDefaultCallout; + + /** MbiFir[8] + * MBIFIRQ_MBI_INTERNAL_CONTROL_PARITY_ERROR + */ + (MbiFir, bit(8)) ? TBDDefaultCallout; + + /** MbiFir[9] + * MBIFIRQ_MBI_DATA_FLOW_PARITY_ERROR + */ + (MbiFir, bit(9)) ? TBDDefaultCallout; + + /** MbiFir[10] + * MBIFIRQ_CRC_PERFORMANCE_DEGRADATION + */ + (MbiFir, bit(10)) ? TBDDefaultCallout; + + /** MbiFir[11] + * MBIFIRQ_HOST_MC_GLOBAL_CHECKSTOP + */ + (MbiFir, bit(11)) ? TBDDefaultCallout; + + /** MbiFir[12] + * MBIFIRQ_HOST_MC_TRACESTOP + */ + (MbiFir, bit(12)) ? TBDDefaultCallout; + + /** MbiFir[13] + * MBIFIRQ_CHANNEL_INTERLOCK_FAIL + */ + (MbiFir, bit(13)) ? TBDDefaultCallout; + + /** MbiFir[14] + * MBIFIRQ_HOST_MC_LOCAL_CHECKSTOP + */ + (MbiFir, bit(14)) ? TBDDefaultCallout; + + /** MbiFir[15] + * MBIFIRQ_FRTL_CONTER_OVERFLOW + */ + (MbiFir, bit(15)) ? TBDDefaultCallout; + + /** MbiFir[16] + * MBIFIRQ_SCOM_REGISTER_PARITY_ERROR + */ + (MbiFir, bit(16)) ? TBDDefaultCallout; + + /** MbiFir[17] + * MBIFIRQ_IO_FAULT: IO to MBI + */ + (MbiFir, bit(17)) ? TBDDefaultCallout; + + /** MbiFir[18] + * MBIFIRQ_MULTIPLE_REPLAY + */ + (MbiFir, bit(18)) ? TBDDefaultCallout; + + /** MbiFir[19] + * MBIFIRQ_MBICFG_PARITY_SCOM_ERROR + */ + (MbiFir, bit(19)) ? TBDDefaultCallout; + + /** MbiFir[20] + * MBIFIRQ_BUFFER_OVERRUN_ERROR + */ + (MbiFir, bit(20)) ? TBDDefaultCallout; + + /** MbiFir[25] + * MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE + */ + (MbiFir, bit(25)) ? TBDDefaultCallout; + + /** MbiFir[26] + * MBIFIRQ_INTERNAL_SCOM_ERROR_CLONE_COPY + */ + (MbiFir, bit(26)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet MBSFIR +################################################################################ + +rule MbsFir +{ + CHECK_STOP: MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & ~MBSFIR_ACT1; + RECOVERABLE: MBSFIR & ~MBSFIR_MASK & ~MBSFIR_ACT0 & MBSFIR_ACT1; +}; + +group gMbsFir filter singlebit +{ + /** MBSFIR[0] + * MBS_FIR_REG_HOST_PROTOCOL_ERROR + */ + (MbsFir, bit(0)) ? TBDDefaultCallout; + + /** MBSFIR[1] + * MBS_FIR_REG_INT_PROTOCOL_ERROR + */ + (MbsFir, bit(1)) ? TBDDefaultCallout; + + /** MBSFIR[2] + * MBS_FIR_REG_INVALID_ADDRESS_ERROR + */ + (MbsFir, bit(2)) ? TBDDefaultCallout; + + /** MBSFIR[3] + * MBS_FIR_REG_EXTERNAL_TIMEOUT + */ + (MbsFir, bit(3)) ? TBDDefaultCallout; + + /** MBSFIR[4] + * MBS_FIR_REG_INTERNAL_TIMEOUT + */ + (MbsFir, bit(4)) ? TBDDefaultCallout; + + /** MBSFIR[5] + * MBS_FIR_REG_INT_BUFFER_CE + */ + (MbsFir, bit(5)) ? TBDDefaultCallout; + + /** MBSFIR[6] + * MBS_FIR_REG_INT_BUFFER_UE + */ + (MbsFir, bit(6)) ? TBDDefaultCallout; + + /** MBSFIR[7] + * MBS_FIR_REG_INT_BUFFER_SUE + */ + (MbsFir, bit(7)) ? TBDDefaultCallout; + + /** MBSFIR[8] + * MBS_FIR_REG_INT_PARITY_ERROR + */ + (MbsFir, bit(8)) ? TBDDefaultCallout; + + /** MBSFIR[9] + * MBS_FIR_REG_CACHE_SRW_CE + */ + (MbsFir, bit(9)) ? TBDDefaultCallout; + + /** MBSFIR[10] + * MBS_FIR_REG_CACHE_SRW_UE + */ + (MbsFir, bit(10)) ? TBDDefaultCallout; + + /** MBSFIR[11] + * MBS_FIR_REG_CACHE_SRW_SUE + */ + (MbsFir, bit(11)) ? TBDDefaultCallout; + + /** MBSFIR[12] + * MBS_FIR_REG_CACHE_CO_CE + */ + (MbsFir, bit(12)) ? TBDDefaultCallout; + + /** MBSFIR[13] + * MBS_FIR_REG_CACHE_CO_UE + */ + (MbsFir, bit(13)) ? TBDDefaultCallout; + + /** MBSFIR[14] + * MBS_FIR_REG_CACHE_CO_SUE + */ + (MbsFir, bit(14)) ? TBDDefaultCallout; + + /** MBSFIR[15] + * MBS_FIR_REG_DIR_CE + */ + (MbsFir, bit(15)) ? TBDDefaultCallout; + + /** MBSFIR[16] + * MBS_FIR_REG_DIR_UE + */ + (MbsFir, bit(16)) ? TBDDefaultCallout; + + /** MBSFIR[17] + * MBS_FIR_REG_DIR_MEMBER_DELETED + */ + (MbsFir, bit(17)) ? TBDDefaultCallout; + + /** MBSFIR[18] + * MBS_FIR_REG_DIR_ALL_MEMBERS_DELETED + */ + (MbsFir, bit(18)) ? TBDDefaultCallout; + + /** MBSFIR[19] + * MBS_FIR_REG_LRU_ERROR + */ + (MbsFir, bit(19)) ? TBDDefaultCallout; + + /** MBSFIR[20] + * MBS_FIR_REG_EDRAM_ERROR + */ + (MbsFir, bit(20)) ? TBDDefaultCallout; + + /** MBSFIR[21] + * MBS_FIR_REG_EMERGENCY_THROTTLE_SET + */ + (MbsFir, bit(21)) ? TBDDefaultCallout; + + /** MBSFIR[22] + * MBS_FIR_REG_HOST_INBAND_READ_ERROR + */ + (MbsFir, bit(22)) ? TBDDefaultCallout; + + /** MBSFIR[23] + * MBS_FIR_REG_HOST_INBAND_WRITE_ERROR + */ + (MbsFir, bit(23)) ? TBDDefaultCallout; + + /** MBSFIR[24] + * MBS_FIR_REG_OCC_INBAND_READ_ERROR + */ + (MbsFir, bit(24)) ? TBDDefaultCallout; + + /** MBSFIR[25] + * MBS_FIR_REG_OCC_INBAND_WRITE_ERROR + */ + (MbsFir, bit(25)) ? TBDDefaultCallout; + + /** MBSFIR[26] + * MBS_FIR_REG_SRB_BUFFER_CE + */ + (MbsFir, bit(26)) ? TBDDefaultCallout; + + /** MBSFIR[27] + * MBS_FIR_REG_SRB_BUFFER_UE + */ + (MbsFir, bit(27)) ? TBDDefaultCallout; + + /** MBSFIR[28] + * MBS_FIR_REG_SRB_BUFFER_SUE + */ + (MbsFir, bit(28)) ? TBDDefaultCallout; + + /** MBSFIR[29] + * MBS_FIR_REG_INTERNAL_SCOM_ERROR + */ + (MbsFir, bit(29)) ? TBDDefaultCallout; + + /** MBSFIR[30] + * MBS_FIR_REG_INTERNAL_SCOM_ERROR_COPY + */ + (MbsFir, bit(30)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet MBSECC01FIR and MBSECC23FIR +################################################################################ + +rule MbsEcc01Fir +{ + CHECK_STOP: + MBSECC01FIR & ~MBSECC01FIR_MASK & ~MBSECC01FIR_ACT0 & ~MBSECC01FIR_ACT1; + RECOVERABLE: + MBSECC01FIR & ~MBSECC01FIR_MASK & ~MBSECC01FIR_ACT0 & MBSECC01FIR_ACT1; +}; + +rule MbsEcc23Fir +{ + CHECK_STOP: + MBSECC23FIR & ~MBSECC23FIR_MASK & ~MBSECC23FIR_ACT0 & ~MBSECC23FIR_ACT1; + RECOVERABLE: + MBSECC23FIR & ~MBSECC23FIR_MASK & ~MBSECC23FIR_ACT0 & MBSECC23FIR_ACT1; +}; + +group gMbsEccFir filter singlebit +{ + /** MBSECCFIR01[0:7] + * MBECCFIR_MEMORY_MPE_RANK_0_7 + */ + (MbsEcc01Fir, bit(0|1|2|3|4|5|6|7)) ? TBDDefaultCallout; + + /** MBSECCFIR23[0:7] + * MBECCFIR_MEMORY_MPE_RANK_0_7 + */ + (MbsEcc23Fir, bit(0|1|2|3|4|5|6|7)) ? TBDDefaultCallout; + + /** MBSECCFIR01[16] + * MBECCFIR_MEMORY_NCE + */ + (MbsEcc01Fir, bit(16)) ? TBDDefaultCallout; + + /** MBSECCFIR23[16] + * MBECCFIR_MEMORY_NCE + */ + (MbsEcc23Fir, bit(16)) ? TBDDefaultCallout; + + /** MBSECCFIR01[17] + * MBECCFIR_MEMORY_RCE + */ + (MbsEcc01Fir, bit(17)) ? TBDDefaultCallout; + + /** MBSECCFIR23[17] + * MBECCFIR_MEMORY_RCE + */ + (MbsEcc23Fir, bit(17)) ? TBDDefaultCallout; + + /** MBSECCFIR01[18] + * MBECCFIR_MEMORY_SUE + */ + (MbsEcc01Fir, bit(18)) ? TBDDefaultCallout; + + /** MBSECCFIR23[18] + * MBECCFIR_MEMORY_SUE + */ + (MbsEcc23Fir, bit(18)) ? TBDDefaultCallout; + + /** MBSECCFIR01[19] + * MBECCFIR_MEMORY_UE + */ + (MbsEcc01Fir, bit(19)) ? TBDDefaultCallout; + + /** MBSECCFIR23[19] + * MBECCFIR_MEMORY_UE + */ + (MbsEcc23Fir, bit(19)) ? TBDDefaultCallout; + + /** MBSECCFIR01[20:27] + * MBECCFIR_MAINT_MPE_RANK_0_7 + */ + (MbsEcc01Fir, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout; + + /** MBSECCFIR23[20:27] + * MBECCFIR_MAINT_MPE_RANK_0_7 + */ + (MbsEcc23Fir, bit(20|21|22|23|24|25|26|27)) ? TBDDefaultCallout; + + /** MBSECCFIR01[36] + * MBECCFIR_MAINTENANCE_NCE + */ + (MbsEcc01Fir, bit(36)) ? TBDDefaultCallout; + + /** MBSECCFIR23[36] + * MBECCFIR_MAINTENANCE_NCE + */ + (MbsEcc23Fir, bit(36)) ? TBDDefaultCallout; + + /** MBSECCFIR01[37] + * MBECCFIR_MAINTENANCE_SCE + */ + (MbsEcc01Fir, bit(37)) ? TBDDefaultCallout; + + /** MBSECCFIR23[37] + * MBECCFIR_MAINTENANCE_SCE + */ + (MbsEcc23Fir, bit(37)) ? TBDDefaultCallout; + + /** MBSECCFIR01[38] + * MBECCFIR_MAINTENANCE_MCE + */ + (MbsEcc01Fir, bit(38)) ? TBDDefaultCallout; + + /** MBSECCFIR23[38] + * MBECCFIR_MAINTENANCE_MCE + */ + (MbsEcc23Fir, bit(38)) ? TBDDefaultCallout; + + /** MBSECCFIR01[39] + * MBECCFIR_MAINTENANCE_RCE + */ + (MbsEcc01Fir, bit(39)) ? TBDDefaultCallout; + + /** MBSECCFIR23[39] + * MBECCFIR_MAINTENANCE_RCE + */ + (MbsEcc23Fir, bit(39)) ? TBDDefaultCallout; + + /** MBSECCFIR01[40] + * MBECCFIR_MAINTENANCE_SUE + */ + (MbsEcc01Fir, bit(40)) ? TBDDefaultCallout; + + /** MBSECCFIR23[40] + * MBECCFIR_MAINTENANCE_SUE + */ + (MbsEcc23Fir, bit(40)) ? TBDDefaultCallout; + + /** MBSECCFIR01[41] + * MBECCFIR_MAINTENANCE_UE + */ + (MbsEcc01Fir, bit(41)) ? TBDDefaultCallout; + + /** MBSECCFIR23[41] + * MBECCFIR_MAINTENANCE_UE + */ + (MbsEcc23Fir, bit(41)) ? TBDDefaultCallout; + + /** MBSECCFIR01[42] + * MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE + */ + (MbsEcc01Fir, bit(42)) ? TBDDefaultCallout; + + /** MBSECCFIR23[42] + * MBECCFIR_MPE_DURING_USE_MAINTENANCE_MARK_MODE + */ + (MbsEcc23Fir, bit(42)) ? TBDDefaultCallout; + + /** MBSECCFIR01[43] + * MBECCFIR_PREFETCH_MEMORY_UE + */ + (MbsEcc01Fir, bit(43)) ? TBDDefaultCallout; + + /** MBSECCFIR23[43] + * MBECCFIR_PREFETCH_MEMORY_UE + */ + (MbsEcc23Fir, bit(43)) ? TBDDefaultCallout; + + /** MBSECCFIR01[44] + * MBECCFIR_MEMORY_RCD_PARITY_ERROR + */ + (MbsEcc01Fir, bit(44)) ? TBDDefaultCallout; + + /** MBSECCFIR23[44] + * MBECCFIR_MEMORY_RCD_PARITY_ERROR + */ + (MbsEcc23Fir, bit(44)) ? TBDDefaultCallout; + + /** MBSECCFIR01[45] + * MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR + */ + (MbsEcc01Fir, bit(45)) ? TBDDefaultCallout; + + /** MBSECCFIR23[45] + * MBECCFIR_MAINTENANCE_RCD_PARITY_ERROR + */ + (MbsEcc23Fir, bit(45)) ? TBDDefaultCallout; + + /** MBSECCFIR01[46] + * MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR + */ + (MbsEcc01Fir, bit(46)) ? TBDDefaultCallout; + + /** MBSECCFIR23[46] + * MBECCFIR_RECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR + */ + (MbsEcc23Fir, bit(46)) ? TBDDefaultCallout; + + /** MBSECCFIR01[47] + * MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR + */ + (MbsEcc01Fir, bit(47)) ? TBDDefaultCallout; + + /** MBSECCFIR23[47] + * MBECCFIR_UNRECOVERABLE_CONFIGURATION_REGISTER_PARITY_ERROR + */ + (MbsEcc23Fir, bit(47)) ? TBDDefaultCallout; + + /** MBSECCFIR01[48] + * MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR + */ + (MbsEcc01Fir, bit(48)) ? TBDDefaultCallout; + + /** MBSECCFIR23[48] + * MBECCFIR_MASKABLE_CONFIGURATION_REGISTER_PARITY_ERROR + */ + (MbsEcc23Fir, bit(48)) ? TBDDefaultCallout; + + /** MBSECCFIR01[49] + * MBECCFIR_ECC_DATAPATH_PARITY_ERROR + */ + (MbsEcc01Fir, bit(49)) ? TBDDefaultCallout; + + /** MBSECCFIR23[49] + * MBECCFIR_ECC_DATAPATH_PARITY_ERROR + */ + (MbsEcc23Fir, bit(49)) ? TBDDefaultCallout; + + /** MBSECCFIR01[50] + * MBECCFIR_INTERNAL_SCOM_ERROR + */ + (MbsEcc01Fir, bit(50)) ? TBDDefaultCallout; + + /** MBSECCFIR23[50] + * MBECCFIR_INTERNAL_SCOM_ERROR + */ + (MbsEcc23Fir, bit(50)) ? TBDDefaultCallout; + + /** MBSECCFIR01[51] + * MBECCFIR_INTERNAL_SCOM_ERROR_COPY + */ + (MbsEcc01Fir, bit(51)) ? TBDDefaultCallout; + + /** MBSECCFIR23[51] + * MBECCFIR_INTERNAL_SCOM_ERROR_COPY + */ + (MbsEcc23Fir, bit(51)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet MCBIST01FIR and MCBIST23FIR +################################################################################ + +rule Mcbist01Fir +{ + CHECK_STOP: + MCBIST01FIR & ~MCBIST01FIR_MASK & ~MCBIST01FIR_ACT0 & ~MCBIST01FIR_ACT1; + RECOVERABLE: + MCBIST01FIR & ~MCBIST01FIR_MASK & ~MCBIST01FIR_ACT0 & MCBIST01FIR_ACT1; +}; + +rule Mcbist23Fir +{ + CHECK_STOP: + MCBIST23FIR & ~MCBIST23FIR_MASK & ~MCBIST23FIR_ACT0 & ~MCBIST23FIR_ACT1; + RECOVERABLE: + MCBIST23FIR & ~MCBIST23FIR_MASK & ~MCBIST23FIR_ACT0 & MCBIST23FIR_ACT1; +}; + +group gMcbistFir filter singlebit +{ + /** MCBISTFIR01[0] + * MBSFIRQ_SCOM_PAR_ERRORS + */ + (Mcbist01Fir, bit(0)) ? TBDDefaultCallout; + + /** MCBISTFIR23[0] + * MBSFIRQ_SCOM_PAR_ERRORS + */ + (Mcbist23Fir, bit(0)) ? TBDDefaultCallout; + + /** MCBISTFIR01[1] + * MBSFIRQ_MBX_PAR_ERRORS + */ + (Mcbist01Fir, bit(1)) ? TBDDefaultCallout; + + /** MCBISTFIR23[1] + * MBSFIRQ_MBX_PAR_ERRORS + */ + (Mcbist23Fir, bit(1)) ? TBDDefaultCallout; + + /** MCBISTFIR01[15] + * MBSFIRQ_INTERNAL_SCOM_ERROR + */ + (Mcbist01Fir, bit(15)) ? TBDDefaultCallout; + + /** MCBISTFIR23[15] + * MBSFIRQ_INTERNAL_SCOM_ERROR + */ + (Mcbist23Fir, bit(15)) ? TBDDefaultCallout; + + /** MCBISTFIR01[16] + * MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE + */ + (Mcbist01Fir, bit(16)) ? TBDDefaultCallout; + + /** MCBISTFIR23[16] + * MBSFIRQ_INTERNAL_SCOM_ERROR_CLONE + */ + (Mcbist23Fir, bit(16)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet NESTFBISTFIR +################################################################################ + +rule NestFbistFir +{ + CHECK_STOP: + NESTFBISTFIR & ~NESTFBISTFIR_MASK & ~NESTFBISTFIR_ACT0 & ~NESTFBISTFIR_ACT1; + RECOVERABLE: + NESTFBISTFIR & ~NESTFBISTFIR_MASK & ~NESTFBISTFIR_ACT0 & NESTFBISTFIR_ACT1; +}; + +group gNestFbistFir filter singlebit +{ + /** NESTFBISTFIR[0] + * FBN_FIR_REG_FBN_SCOM_UE + */ + (NestFbistFir, bit(0)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[1] + * FBN_FIR_REG_FBN_USCHK_1HOT + */ + (NestFbistFir, bit(1)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[2] + * FBN_FIR_REG_FBN_USCHK_DATA_DROP + */ + (NestFbistFir, bit(2)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[3] + * FBN_FIR_REG_FBN_DGEN_1HOT + */ + (NestFbistFir, bit(3)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[4] + * FBN_FIR_REG_FBN_CMD_1HOT + */ + (NestFbistFir, bit(4)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[5] + * FBN_FIR_REG_FBN_CMD_EARLY_RESPONSE + */ + (NestFbistFir, bit(5)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[6] + * FBN_FIR_REG_FBN_FBIST_FAIL + */ + (NestFbistFir, bit(6)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[7] + * FBN_FIR_REG_FBN_US_CRC_ERR + */ + (NestFbistFir, bit(7)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[15] + * FBN_FIR_REG_INTERNAL_SCOM_ERROR + */ + (NestFbistFir, bit(15)) ? TBDDefaultCallout; + + /** NESTFBISTFIR[16] + * FBN_FIR_REG_INTERNAL_SCOM_ERROR_CLONE + */ + (NestFbistFir, bit(16)) ? TBDDefaultCallout; +}; + +################################################################################ +# NEST Chiplet MBSSECUREFIR +################################################################################ + +rule MbsSecureFir +{ + CHECK_STOP: + MBSSECUREFIR & ~MBSSECUREFIR_MASK & ~MBSSECUREFIR_ACT0 & ~MBSSECUREFIR_ACT1; + # NOTE: This secure FIR will only report checkstop attentions. +}; + +group gMbsSecureFir filter singlebit +{ + /** MBSSECUREFIR[0] + * MBSSIRQ_INVALID_MBSXCR_ACCESS + */ + (MbsSecureFir, bit(0)) ? TBDDefaultCallout; + + /** MBSSECUREFIR[1] + * MBSSIRQ_INVALID_MBAXCR01_ACCESS + */ + (MbsSecureFir, bit(1)) ? TBDDefaultCallout; + + /** MBSSECUREFIR[2] + * MBSSIRQ_INVALID_MBAXCR23_ACCESS + */ + (MbsSecureFir, bit(2)) ? TBDDefaultCallout; + + /** MBSSECUREFIR[3] + * MBSSIRQ_INVALID_MBAXCRMS_ACCRESS + */ + (MbsSecureFir, bit(3)) ? TBDDefaultCallout; + + /** MBSSECUREFIR[5] + * MBSSIRQ_INVALID_SIR_MASK_OR_ACTION_REGISTER_ACCESS + */ + (MbsSecureFir, bit(5)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to NEST chiplet +################################################################################ + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_acts_TP.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_acts_TP.rule new file mode 100644 index 000000000..84d097c0c --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf_acts_TP.rule @@ -0,0 +1,110 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_acts_TP.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# TP Chiplet Registers +################################################################################ + +rule TpChipletFir +{ + CHECK_STOP: + (TP_CHIPLET_CS_FIR & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK; + RECOVERABLE: + ((TP_CHIPLET_RE_FIR >> 2) & `1000000000000000`) & ~TP_CHIPLET_FIR_MASK; +}; + +group gTpChipletFir filter singlebit +{ + /** TP_CHIPLET_FIR[3] + * Attention from LFIR + */ + (TpChipletFir, bit(3)) ? analyze(gTpLFir); +}; + +################################################################################ +# TP Chiplet LFIR +################################################################################ + +rule TpLFir +{ + CHECK_STOP: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; + RECOVERABLE: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; +}; + +group gTpLFir filter singlebit +{ + /** TP_LFIR[0] + * CFIR internal parity error + */ + (TpLFir, bit(0)) ? TBDDefaultCallout; + + /** TP_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (TpLFir, bit(1)) ? TBDDefaultCallout; + + /** TP_LFIR[2] + * Local errors from CC (PCB error) + */ + (TpLFir, bit(2)) ? TBDDefaultCallout; + + /** TP_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (TpLFir, bit(3)) ? TBDDefaultCallout; + + /** TP_LFIR[4] + * Local errors from PSC (PCB error) + */ + (TpLFir, bit(4)) ? TBDDefaultCallout; + + /** TP_LFIR[5] + * Local errors from PSC (parity error) + */ + (TpLFir, bit(5)) ? TBDDefaultCallout; + + /** TP_LFIR[6] + * Local errors from Thermal (parity error) + */ + (TpLFir, bit(6)) ? TBDDefaultCallout; + + /** TP_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (TpLFir, bit(7)) ? TBDDefaultCallout; + + /** TP_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (TpLFir, bit(8|9)) ? TBDDefaultCallout; + + /** TP_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (TpLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to TP chiplet +################################################################################ + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule new file mode 100644 index 000000000..5de564fe3 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule @@ -0,0 +1,138 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_regs_MEM.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # MEM Chiplet Registers + ############################################################################ + + register MEM_CHIPLET_CS_FIR + { + name "TCM.XFIR"; + scomaddr 0x03040000; + capture group default; + }; + + register MEM_CHIPLET_RE_FIR + { + name "TCM.RFIR"; + scomaddr 0x03040001; + capture group default; + }; + + register MEM_CHIPLET_FIR_MASK + { + name "TCM.FIR_MASK"; + scomaddr 0x03040002; + capture type secondary; + capture group default; + }; + + register MEM_CHIPLET_SPA + { + name "TCM.EPS.FIR.SPATTN"; + scomaddr 0x03040004; + capture group default; + }; + + register MEM_CHIPLET_SPA_MASK + { + name "TCM.EPS.FIR.SPA_MASK"; + scomaddr 0x03040007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # MEM Chiplet LFIR + ############################################################################ + + register MEM_LFIR + { + name "TCM.LOCAL_FIR"; + scomaddr 0x0304000a; + reset (&, 0x0304000b); + mask (|, 0x0304000f); + capture group default; + }; + + register MEM_LFIR_MASK + { + name "TCM.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0304000d; + capture type secondary; + capture group default; + }; + + register MEM_LFIR_ACT0 + { + name "TCM.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x03040010; + capture type secondary; + capture group default; + }; + + register MEM_LFIR_ACT1 + { + name "TCM.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x03040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # MEM Chiplet MEMFBISTFIR + ############################################################################ + + register MEMFBISTFIR + { + name "FBIST.FBM.FBM_FIR_REG"; + scomaddr 0x03010480; + reset (&, 0x03010481); + mask (|, 0x03010485); + capture group default; + }; + + register MEMFBISTFIR_MASK + { + name "FBIST.FBM.FBM_FIR_MASK_REG"; + scomaddr 0x03010483; + capture type secondary; + capture group default; + }; + + register MEMFBISTFIR_ACT0 + { + name "FBIST.FBM.FBM_FIR_ACTION0_REG"; + scomaddr 0x03010486; + capture type secondary; + capture group default; + }; + + register MEMFBISTFIR_ACT1 + { + name "FBIST.FBM.FBM_FIR_ACTION1_REG"; + scomaddr 0x03010487; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule new file mode 100644 index 000000000..baf284fd8 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule @@ -0,0 +1,458 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_regs_NEST.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # NEST Chiplet Registers + ############################################################################ + + register NEST_CHIPLET_CS_FIR + { + name "TCN.XFIR"; + scomaddr 0x02040000; + capture group default; + }; + + register NEST_CHIPLET_RE_FIR + { + name "TCN.RFIR"; + scomaddr 0x02040001; + capture group default; + }; + + register NEST_CHIPLET_FIR_MASK + { + name "TCN.FIR_MASK"; + scomaddr 0x02040002; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet LFIR + ############################################################################ + + register NEST_LFIR + { + name "TCN.LOCAL_FIR"; + scomaddr 0x0204000a; + reset (&, 0x0204000b); + mask (|, 0x0204000f); + capture group default; + }; + + register NEST_LFIR_MASK + { + name "TCN.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0204000d; + capture type secondary; + capture group default; + }; + + register NEST_LFIR_ACT0 + { + name "TCN.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x02040010; + capture type secondary; + capture group default; + }; + + register NEST_LFIR_ACT1 + { + name "TCN.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x02040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet DMIFIR + ############################################################################ + + register DMIFIR + { + name "DMI.BUSCTL.SCOM.FIR_REG"; + scomaddr 0x02010400; + reset (&, 0x02010401); + mask (|, 0x02010405); + capture group default; + }; + + register DMIFIR_MASK + { + name "DMI.BUSCTL.SCOM.FIR_MASK_REG"; + scomaddr 0x02010403; + capture type secondary; + capture group default; + }; + + register DMIFIR_ACT0 + { + name "DMI.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x02010406; + capture type secondary; + capture group default; + }; + + register DMIFIR_ACT1 + { + name "DMI.BUSCTL.SCOM.FIR_ACTION1_REG"; + scomaddr 0x02010407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MBIFIR + ############################################################################ + + register MBIFIR + { + name "MBU.MBI.MBI.SCOMFIR.MBIFIRQ"; + scomaddr 0x02010800; + reset (&, 0x02010801); + mask (|, 0x02010805); + capture group default; + }; + + register MBIFIR_MASK + { + name "MBU.MBI.MBI.SCOMFIR.MBIFIRMASK"; + scomaddr 0x02010803; + capture type secondary; + capture group default; + }; + + register MBIFIR_ACT0 + { + name "MBU.MBI.MBI.SCOMFIR.MBIFIRACT0"; + scomaddr 0x02010806; + capture type secondary; + capture group default; + }; + + register MBIFIR_ACT1 + { + name "MBU.MBI.MBI.SCOMFIR.MBIFIRACT1"; + scomaddr 0x02010807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MBSFIR + ############################################################################ + + register MBSFIR + { + name "MBU.MBS.MBS_FIR_REG"; + scomaddr 0x02011400; + reset (&, 02011401); + mask (|, 02011405); + capture group default; + }; + + register MBSFIR_MASK + { + name "MBU.MBS.MBS_FIR_MASK_REG"; + scomaddr 0x02011403; + capture type secondary; + capture group default; + }; + + register MBSFIR_ACT0 + { + name "MBU.MBS.MBS_FIR_ACTION0_REG"; + scomaddr 0x02011406; + capture type secondary; + capture group default; + }; + + register MBSFIR_ACT1 + { + name "MBU.MBS.MBS_FIR_ACTION1_REG"; + scomaddr 0x02011407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MBSECC01FIR + ############################################################################ + + register MBSECC01FIR + { + name "MBU.MBS.ECC01.MBECCFIR"; + scomaddr 0x02011440; + reset (&, 02011441); + mask (|, 02011445); + capture group default; + }; + + register MBSECC01FIR_MASK + { + name "MBU.MBS.ECC01.MBECCFIR_MASK"; + scomaddr 0x02011443; + capture type secondary; + capture group default; + }; + + register MBSECC01FIR_ACT0 + { + name "MBU.MBS.ECC01.MBECCFIR_ACTION0"; + scomaddr 0x02011446; + capture type secondary; + capture group default; + }; + + register MBSECC01FIR_ACT1 + { + name "MBU.MBS.ECC01.MBECCFIR_ACTION1"; + scomaddr 0x02011447; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MBSECC23FIR + ############################################################################ + + register MBSECC23FIR + { + name "MBU.MBS.ECC23.MBECCFIR"; + scomaddr 0x02011480; + reset (&, 02011481); + mask (|, 02011485); + capture group default; + }; + + register MBSECC23FIR_MASK + { + name "MBU.MBS.ECC23.MBECCFIR_MASK"; + scomaddr 0x02011483; + capture type secondary; + capture group default; + }; + + register MBSECC23FIR_ACT0 + { + name "MBU.MBS.ECC23.MBECCFIR_ACTION0"; + scomaddr 0x02011486; + capture type secondary; + capture group default; + }; + + register MBSECC23FIR_ACT1 + { + name "MBU.MBS.ECC23.MBECCFIR_ACTION0"; + scomaddr 0x02011487; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MCBIST01FIR + ############################################################################ + + register MCBIST01FIR + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRQ"; + scomaddr 0x02011600; + reset (&, 0x02011601); + mask (|, 0x02011605); + capture group default; + }; + + register MCBIST01FIR_MASK + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRMASK"; + scomaddr 0x02011603; + capture type secondary; + capture group default; + }; + + register MCBIST01FIR_ACT0 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION0"; + scomaddr 0x02011606; + capture type secondary; + capture group default; + }; + + register MCBIST01FIR_ACT1 + { + name "MBU.MBS.MCBISTS01.SCOMFIR.MBSFIRACTION1"; + scomaddr 0x02011607; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MCBIST23FIR + ############################################################################ + + register MCBIST23FIR + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRQ"; + scomaddr 0x02011700; + reset (&, 0x02011701); + mask (|, 0x02011705); + capture group default; + }; + + register MCBIST23FIR_MASK + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRMASK"; + scomaddr 0x02011703; + capture type secondary; + capture group default; + }; + + register MCBIST23FIR_ACT0 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION0"; + scomaddr 0x02011706; + capture type secondary; + capture group default; + }; + + register MCBIST23FIR_ACT1 + { + name "MBU.MBS.MCBISTS23.SCOMFIR.MBSFIRACTION1"; + scomaddr 0x02011707; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet NESTFBISTFIR + ############################################################################ + + register NESTFBISTFIR + { + name "FBIST.FBN.FBN_FIR_REG"; + scomaddr 0x02010880; + reset (&, 0x02010881); + mask (|, 0x02010885); + capture group default; + }; + + register NESTFBISTFIR_MASK + { + name "FBIST.FBN.FBN_FIR_MASK_REG"; + scomaddr 0x02010883; + capture type secondary; + capture group default; + }; + + register NESTFBISTFIR_ACT0 + { + name "FBIST.FBN.FBN_FIR_ACTION0_REG"; + scomaddr 0x02010886; + capture type secondary; + capture group default; + }; + + register NESTFBISTFIR_ACT1 + { + name "FBIST.FBN.FBN_FIR_ACTION1_REG"; + scomaddr 0x02010887; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet SENSORCACHEFIR + ############################################################################ + + register SENSORCACHEFIR + { + name "SCAC.SCAC_LFIR"; + scomaddr 0x020115c0; + reset (&, 0x020115c1); + mask (|, 0x020115c5); + capture group default; + }; + + register SENSORCACHEFIR_MASK + { + name "SCAC.SCAC_FIRMASK"; + scomaddr 0x020115c3; + capture type secondary; + capture group default; + }; + + register SENSORCACHEFIR_ACT0 + { + name "SCAC.SCAC_FIRACTION0"; + scomaddr 0x020115c6; + capture type secondary; + capture group default; + }; + + register SENSORCACHEFIR_ACT1 + { + name "SCAC.SCAC_FIRACTION1"; + scomaddr 0x020115c7; + capture type secondary; + capture group default; + }; + + ############################################################################ + # NEST Chiplet MBSSECUREFIR + ############################################################################ + + register MBSSECUREFIR + { + name "MBU.MBS.ARB.RXLT.MBSSIRQ"; + scomaddr 0x0201141e; + reset (&, 0x0201141f); + # This is a special register in which we are not able to mask. All bits + # in this register should be set to checkstop so we will not need to + # mask anyway. + capture group default; + }; + + register MBSSECUREFIR_MASK + { + name "MBU.MBS.ARB.RXLT.MBSSIRMASK"; + scomaddr 0x02011421; + capture type secondary; + capture group default; + }; + + register MBSSECUREFIR_ACT0 + { + name "MBU.MBS.ARB.RXLT.MBSSIRACT0"; + scomaddr 0x02011424; + capture type secondary; + capture group default; + }; + + register MBSSECUREFIR_ACT1 + { + name "MBU.MBS.ARB.RXLT.MBSSIRACT1"; + scomaddr 0x02011425; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Membuf_regs_TP.rule b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_TP.rule new file mode 100644 index 000000000..7ea4535d6 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Membuf_regs_TP.rule @@ -0,0 +1,86 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Membuf_regs_TP.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # TP Chiplet Registers + ############################################################################ + + register TP_CHIPLET_CS_FIR + { + name "TPTOP.TPC.XFIR"; + scomaddr 0x01040000; + capture group default; + }; + + register TP_CHIPLET_RE_FIR + { + name "TPTOP.TPC.RFIR"; + scomaddr 0x01040001; + capture group default; + }; + + register TP_CHIPLET_FIR_MASK + { + name "TPTOP.TPC.FIR_MASK"; + scomaddr 0x01040002; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet LFIR + ############################################################################ + + register TP_LFIR + { + name "TPTOP.TPC.LOCAL_FIR"; + scomaddr 0x0104000a; + reset (&, 0x0104000b); + mask (|, 0x0104000f); + capture group default; + }; + + register TP_LFIR_MASK + { + name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0104000d; + capture type secondary; + capture group default; + }; + + register TP_LFIR_ACT0 + { + name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x01040010; + capture type secondary; + capture group default; + }; + + register TP_LFIR_ACT1 + { + name "TPTOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x01040011; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc.rule b/src/usr/diag/prdf/plat/pegasus/Proc.rule new file mode 100644 index 000000000..39e9a469b --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc.rule @@ -0,0 +1,332 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# +# Scope: +# Registers and actions for the following chiplets: +# +# Chiplet Register Adddresses Description +# ======= ======================= ============================================ +# TP 0x01000000 - 0x01FFFFFF TP pervasive logic +# PB 0x02000000 - 0x02FFFFFF PB pervasive logic, note that this does +# include the SCOM addresses characterized by +# the MCS target. See Mcs.rule for those +# address ranges. +# XBUS 0x04000000 - 0x0400FFFF XBUS pervasive logic +# ABUS 0x08000000 - 0x0800FFFF ABUS pervasive logic +# PCIE 0x09000000 - 0x09FFFFFF PCIE pervasive logic +# +################################################################################ + +chip Proc +{ + name "Power8 Chip"; + targettype TYPE_PROC; + sigoff 0x8000; +# FIXME May need to update dump type + dump DUMP_CONTENT_HW; + scomlen 64; + + ############################################################################# + # # + # ###### # + # # # ###### #### ### #### ##### ###### ##### #### # + # # # # # # # # # # # # # # + # ###### ##### # # #### # ##### # # #### # + # # # # # ### # # # # ##### # # + # # # # # # # # # # # # # # # # + # # # ###### #### ### #### # ###### # # #### # + # # + ############################################################################# + + ############################################################################ + # Global Broadcast Registers + ############################################################################ + + register GLOBAL_CS_FIR + { + name "Global Checkstop Attention FIR"; + scomaddr 0x570F001C; + capture group default; + }; + + register GLOBAL_RE_FIR + { + name "Global Recoverable Attention FIR"; + scomaddr 0x570F001B; + capture group default; + }; + + register GLOBAL_SPA + { + name "Global Special Attention FIR"; + scomaddr 0x570F001A; + capture group default; + }; + +# Import all of the chiplet registers +.include "Proc_regs_TP.rule" +.include "Proc_regs_PB.rule" +.include "Proc_regs_XBUS.rule" +.include "Proc_regs_ABUS.rule" +.include "Proc_regs_PCIE.rule" + +}; + + ############################################################################## + # # + # #### # # + # # # # # # ##### ### # # # ## ##### ### ### # # ### # + # # # # # # # # # # # # # # # # # ## # # # + # #### # # # #### ### # ####### # # # # # # # # ### # + # # # # # # # # # # # # # # # # # # ## # # + # # # ### #### ##### ### # # # ## # ### ### # # ### # + # # + ############################################################################## + +################################################################################ +# Global Broadcast Registers +################################################################################ + +rule GlobalFir +{ + CHECK_STOP: GLOBAL_CS_FIR; + RECOVERABLE: GLOBAL_RE_FIR; +}; + +group gGlobalFir attntype CHECK_STOP, RECOVERABLE filter singlebit +{ + /** GLOBAL_FIR[1] + * Attention from TP chiplet + */ + (GlobalFir, bit(1)) ? analyze(gTpChipletFir); + + /** GLOBAL_FIR[2] + * Attention from PB chiplet + */ + (GlobalFir, bit(2)) ? analyze(gPbChipletFir); + + /** GLOBAL_FIR[4] + * Attention from XBUS chiplet + */ + (GlobalFir, bit(4)) ? analyze(gXbusChipletFir); + + /** GLOBAL_FIR[8] + * Attention from ABUS chiplet + */ + (GlobalFir, bit(8)) ? analyze(gAbusChipletFir); + + /** GLOBAL_FIR[9] + * Attention from PCIE + */ + (GlobalFir, bit(9)) ? analyze(gPcieChipletFir); + + /** GLOBAL_FIR[11] + * Attention from EX1 (Venice only) + */ + (GlobalFir, bit(11)) ? defaultMaskedError; + + /** GLOBAL_FIR[12] + * Attention from EX2 (Venice only) + */ + (GlobalFir, bit(12)) ? defaultMaskedError; + + /** GLOBAL_FIR[13] + * Attention from EX3 (Venice only) + */ + (GlobalFir, bit(13)) ? defaultMaskedError; + + /** GLOBAL_FIR[14] + * Attention from EX4 + */ + (GlobalFir, bit(14)) ? analyzeEx4; + + /** GLOBAL_FIR[15] + * Attention from EX5 + */ + (GlobalFir, bit(15)) ? analyzeEx5; + + /** GLOBAL_FIR[16] + * Attention from EX6 + */ + (GlobalFir, bit(16)) ? analyzeEx6; + + /** GLOBAL_FIR[19] + * Attention from EX9 (Venice only) + */ + (GlobalFir, bit(19)) ? defaultMaskedError; + + /** GLOBAL_FIR[20] + * Attention from EX10 (Venice only) + */ + (GlobalFir, bit(20)) ? defaultMaskedError; + + /** GLOBAL_FIR[21] + * Attention from EX11 (Venice only) + */ + (GlobalFir, bit(21)) ? defaultMaskedError; + + /** GLOBAL_FIR[22] + * Attention from EX12 + */ + (GlobalFir, bit(22)) ? analyzeEx12; + + /** GLOBAL_FIR[23] + * Attention from EX13 + */ + (GlobalFir, bit(23)) ? analyzeEx13; + + /** GLOBAL_FIR[24] + * Attention from EX14 + */ + (GlobalFir, bit(24)) ? analyzeEx14; +}; + +rule GlobalSpa +{ + SPECIAL: GLOBAL_SPA; +}; + +group gGlobalSpa attntype SPECIAL filter singlebit +{ + /** GLOBAL_SPA[1] + * Attention from TP chiplet + */ + (GlobalSpa, bit(1)) ? analyze(gTpChipletSpa); + + /** GLOBAL_SPA[2] + * Attention from PB chiplet + */ + (GlobalSpa, bit(2)) ? analyze(gPbChipletSpa); + + /** GLOBAL_SPA[9] + * Attention from PCIE + */ + (GlobalSpa, bit(9)) ? analyze(gPcieChipletSpa); + + /** GLOBAL_SPA[11] + * Attention from EX1 (Venice only) + */ + (GlobalSpa, bit(11)) ? defaultMaskedError; + + /** GLOBAL_SPA[12] + * Attention from EX2 (Venice only) + */ + (GlobalSpa, bit(12)) ? defaultMaskedError; + + /** GLOBAL_SPA[13] + * Attention from EX3 (Venice only) + */ + (GlobalSpa, bit(13)) ? defaultMaskedError; + + /** GLOBAL_SPA[14] + * Attention from EX4 + */ + (GlobalSpa, bit(14)) ? analyzeEx4; + + /** GLOBAL_SPA[15] + * Attention from EX5 + */ + (GlobalSpa, bit(15)) ? analyzeEx5; + + /** GLOBAL_SPA[16] + * Attention from EX6 + */ + (GlobalSpa, bit(16)) ? analyzeEx6; + + /** GLOBAL_SPA[19] + * Attention from EX9 (Venice only) + */ + (GlobalSpa, bit(19)) ? defaultMaskedError; + + /** GLOBAL_SPA[20] + * Attention from EX10 (Venice only) + */ + (GlobalSpa, bit(20)) ? defaultMaskedError; + + /** GLOBAL_SPA[21] + * Attention from EX11 (Venice only) + */ + (GlobalSpa, bit(21)) ? defaultMaskedError; + + /** GLOBAL_SPA[22] + * Attention from EX12 + */ + (GlobalSpa, bit(22)) ? analyzeEx12; + + /** GLOBAL_SPA[23] + * Attention from EX13 + */ + (GlobalSpa, bit(23)) ? analyzeEx13; + + /** GLOBAL_SPA[24] + * Attention from EX14 + */ + (GlobalSpa, bit(24)) ? analyzeEx14; +}; + +# Import all of the chiplet rules and actions +# NOTE: Some of PB local FIRs are handled through the TP chiplet FIRs +.include "Proc_acts_TP.rule" +.include "Proc_acts_PB.rule" +.include "Proc_acts_XBUS.rule" +.include "Proc_acts_ABUS.rule" +.include "Proc_acts_PCIE.rule" + + ############################################################################## + # # + # # ### # + # # # ## ##### ### ### # # # # # # ### ### ### ### # + # # # # # # # # # ## # # # # # # # # # # + # ####### # # # # # # # # # # ##### ### ### ## ### # + # # # # # # # # # # ## # # # # # # # # # # + # # # ## # ### ### # # ### ### # # ### ### ### ### # + # # + ############################################################################## + +# Include the common action set. +.include "CommonActions.rule" + +################################################################################ +# Analyze Connected Parts # +################################################################################ + +/** Analyze connected EX4 */ +actionclass analyzeEx4 { analyze(connected(TYPE_EX, 4)); }; + +/** Analyze connected EX5 */ +actionclass analyzeEx5 { analyze(connected(TYPE_EX, 5)); }; + +/** Analyze connected EX6 */ +actionclass analyzeEx6 { analyze(connected(TYPE_EX, 6)); }; + +/** Analyze connected EX12 */ +actionclass analyzeEx12 { analyze(connected(TYPE_EX, 12)); }; + +/** Analyze connected EX13 */ +actionclass analyzeEx13 { analyze(connected(TYPE_EX, 13)); }; + +/** Analyze connected EX14 */ +actionclass analyzeEx14 { analyze(connected(TYPE_EX, 14)); }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_acts_ABUS.rule b/src/usr/diag/prdf/plat/pegasus/Proc_acts_ABUS.rule new file mode 100644 index 000000000..5f3b423d9 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_acts_ABUS.rule @@ -0,0 +1,344 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_acts_ABUS.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# ABUS Chiplet Registers +################################################################################ + +rule AbusChipletFir +{ + CHECK_STOP: + (ABUS_CHIPLET_CS_FIR & `1C00000000000000`) & ~ABUS_CHIPLET_FIR_MASK; + RECOVERABLE: + ((ABUS_CHIPLET_RE_FIR >> 2) & `1C00000000000000`) & ~ABUS_CHIPLET_FIR_MASK; +}; + +group gAbusChipletFir filter singlebit +{ + /** ABUS_CHIPLET_FIR[3] + * Attention from LFIR + */ + (AbusChipletFir, bit(3)) ? analyze(gAbusLFir); + + /** ABUS_CHIPLET_FIR[4] + * Attention from PBESFIR + */ + (AbusChipletFir, bit(4)) ? analyze(gPbesFir); + + /** ABUS_CHIPLET_FIR[5] + * Attention from IOAFIR + */ + (AbusChipletFir, bit(5)) ? analyze(gIoaFir); +}; + +################################################################################ +# ABUS Chiplet LFIR +################################################################################ + +rule AbusLFir +{ + CHECK_STOP: ABUS_LFIR & ~ABUS_LFIR_MASK & ~ABUS_LFIR_ACT0 & ~ABUS_LFIR_ACT1; + RECOVERABLE: ABUS_LFIR & ~ABUS_LFIR_MASK & ~ABUS_LFIR_ACT0 & ABUS_LFIR_ACT1; +}; + +group gAbusLFir filter singlebit +{ + /** ABUS_LFIR[0] + * CFIR internal parity error + */ + (AbusLFir, bit(0)) ? TBDDefaultCallout; + + /** ABUS_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (AbusLFir, bit(1)) ? TBDDefaultCallout; + + /** ABUS_LFIR[2] + * Local errors from CC (PCB error) + */ + (AbusLFir, bit(2)) ? TBDDefaultCallout; + + /** ABUS_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (AbusLFir, bit(3)) ? TBDDefaultCallout; + + /** ABUS_LFIR[4] + * Local errors from PSC (PCB error) + */ + (AbusLFir, bit(4)) ? TBDDefaultCallout; + + /** ABUS_LFIR[5] + * Local errors from PSC (parity error) + */ + (AbusLFir, bit(5)) ? TBDDefaultCallout; + + /** ABUS_LFIR[6] + * Local errors from Thermal (parity error) + */ + (AbusLFir, bit(6)) ? TBDDefaultCallout; + + /** ABUS_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (AbusLFir, bit(7)) ? TBDDefaultCallout; + + /** ABUS_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (AbusLFir, bit(8|9)) ? TBDDefaultCallout; + + /** ABUS_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (AbusLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# ABUS Chiplet PBESFIR +################################################################################ + +rule PbesFir +{ + CHECK_STOP: + PBESFIR & ~PBESFIR_MASK & ~PBESFIR_ACT0 & ~PBESFIR_ACT1; + RECOVERABLE: + PBESFIR & ~PBESFIR_MASK & ~PBESFIR_ACT0 & PBESFIR_ACT1; +}; + +group gPbesFir filter singlebit +{ + /** PBESFIR[0] + * A0LINK_FMR_ERROR: a0link_fmr_error + */ + (PbesFir, bit(0)) ? TBDDefaultCallout; + + /** PBESFIR[1] + * A1LINK_FMR_ERROR: a1link_fmr_error + */ + (PbesFir, bit(1)) ? TBDDefaultCallout; + + /** PBESFIR[2] + * A2LINK_FMR_ERROR: a2link_fmr_error + */ + (PbesFir, bit(2)) ? TBDDefaultCallout; + + /** PBESFIR[3] + * A0LINK_PSR_ERR: a0link_psr_err + */ + (PbesFir, bit(3)) ? TBDDefaultCallout; + + /** PBESFIR[4] + * A1LINK_PSR_ERR: a1link_psr_err + */ + (PbesFir, bit(4)) ? TBDDefaultCallout; + + /** PBESFIR[5] + * A2LINK_PSR_ERR: a2link_psr_err + */ + (PbesFir, bit(5)) ? TBDDefaultCallout; + + /** PBESFIR[6] + * A0LINK_PSR_COR_ERR + */ + (PbesFir, bit(6)) ? TBDDefaultCallout; + + /** PBESFIR[7] + * A0LINK_PSR_DERR_ERR + */ + (PbesFir, bit(7)) ? TBDDefaultCallout; + + /** PBESFIR[8] + * A0LINK_PSR_UNC_ERR + */ + (PbesFir, bit(8)) ? TBDDefaultCallout; + + /** PBESFIR[9] + * A1LINK_PSR_COR_ERR + */ + (PbesFir, bit(9)) ? TBDDefaultCallout; + + /** PBESFIR[10] + * A1LINK_PSR_DERR_ERR + */ + (PbesFir, bit(10)) ? TBDDefaultCallout; + + /** PBESFIR[11] + * A1LINK_PSR_UNC_ERR + */ + (PbesFir, bit(11)) ? TBDDefaultCallout; + + /** PBESFIR[12] + * A2LINK_PSR_COR_ERR + */ + (PbesFir, bit(12)) ? TBDDefaultCallout; + + /** PBESFIR[13] + * A2LINK_PSR_DERR_ERR + */ + (PbesFir, bit(13)) ? TBDDefaultCallout; + + /** PBESFIR[14] + * NK_PSR_UNC_ERR + */ + (PbesFir, bit(14)) ? TBDDefaultCallout; + + /** PBESFIR[15] + * A0LINK_FMR_COR_ERR_HI + */ + (PbesFir, bit(15)) ? TBDDefaultCallout; + + /** PBESFIR[16] + * A0LINK_FMR_COR_ERR_LO + */ + (PbesFir, bit(16)) ? TBDDefaultCallout; + + /** PBESFIR[17] + * A0LINK_FMR_SUE_ERR_HI + */ + (PbesFir, bit(17)) ? TBDDefaultCallout; + + /** PBESFIR[18] + * A0LINK_FMR_SUE_ERR_LO + */ + (PbesFir, bit(18)) ? TBDDefaultCallout; + + /** PBESFIR[19] + * A0LINK_FMR_UNC_ERR_HI + */ + (PbesFir, bit(19)) ? TBDDefaultCallout; + + /** PBESFIR[20] + * A0LINK_FMR_UNC_ERR_LO + */ + (PbesFir, bit(20)) ? TBDDefaultCallout; + + /** PBESFIR[21] + * A1LINK_FMR_COR_ERR_HI + */ + (PbesFir, bit(21)) ? TBDDefaultCallout; + + /** PBESFIR[22] + * A1LINK_FMR_COR_ERR_LO + */ + (PbesFir, bit(22)) ? TBDDefaultCallout; + + /** PBESFIR[23] + * A1LINK_FMR_SUE_ERR_HI + */ + (PbesFir, bit(23)) ? TBDDefaultCallout; + + /** PBESFIR[24] + * A1LINK_FMR_SUE_ERR_LO + */ + (PbesFir, bit(24)) ? TBDDefaultCallout; + + /** PBESFIR[25] + * A1LINK_FMR_UNC_ERR_HI + */ + (PbesFir, bit(25)) ? TBDDefaultCallout; + + /** PBESFIR[26] + * A1LINK_FMR_UNC_ERR_LO + */ + (PbesFir, bit(26)) ? TBDDefaultCallout; + + /** PBESFIR[27] + * A2LINK_FMR_COR_ERR_HI + */ + (PbesFir, bit(27)) ? TBDDefaultCallout; + + /** PBESFIR[28] + * A2LINK_FMR_COR_ERR_LO + */ + (PbesFir, bit(28)) ? TBDDefaultCallout; + + /** PBESFIR[29] + * A2LINK_FMR_SUE_ERR_HI + */ + (PbesFir, bit(29)) ? TBDDefaultCallout; + + /** PBESFIR[30] + * A2LINK_FMR_SUE_ERR_LO + */ + (PbesFir, bit(30)) ? TBDDefaultCallout; + + /** PBESFIR[31] + * A2LINK_FMR_UNC_ERR_HI + */ + (PbesFir, bit(31)) ? TBDDefaultCallout; + + /** PBESFIR[32] + * A2LINK_FMR_UNC_ERR_LO + */ + (PbesFir, bit(32)) ? TBDDefaultCallout; + + /** PBESFIR[33] + * A0_OBS_CR_OVERFLOW_FIR_ERR + */ + (PbesFir, bit(33)) ? TBDDefaultCallout; + + /** PBESFIR[34] + * A1_OBS_CR_OVERFLOW_FIR_ERR + */ + (PbesFir, bit(34)) ? TBDDefaultCallout; + + /** PBESFIR[35] + * A2_OBS_CR_OVERFLOW_FIR_ERR + */ + (PbesFir, bit(35)) ? TBDDefaultCallout; + + /** PBESFIR[36] + * FIR_SCOM_ERR_DUP + */ + (PbesFir, bit(36)) ? TBDDefaultCallout; + + /** PBESFIR[37] + * FIR_SCOM_ERR + */ + (PbesFir, bit(37)) ? TBDDefaultCallout; +}; + +################################################################################ +# ABUS Chiplet IOAFIR +################################################################################ + +rule IoaFir +{ + CHECK_STOP: IOAFIR & ~IOAFIR_MASK & ~IOAFIR_ACT0 & ~IOAFIR_ACT1; + RECOVERABLE: IOAFIR & ~IOAFIR_MASK & ~IOAFIR_ACT0 & IOAFIR_ACT1; +}; + +group gIoaFir filter singlebit +{ +#FIXME:A temp fix to generate error signature by setting bit 0 + /** IOAFIR[0] + * ERROR + */ + (IoaFir, bit(0)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to ABUS chiplet +################################################################################ + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_acts_PB.rule b/src/usr/diag/prdf/plat/pegasus/Proc_acts_PB.rule new file mode 100644 index 000000000..580bc7c5b --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_acts_PB.rule @@ -0,0 +1,2454 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_acts_PB.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# PB Chiplet Registers +################################################################################ + +rule PbChipletFir +{ + CHECK_STOP: + (PB_CHIPLET_CS_FIR & `1FDFF80000000000`) & ~PB_CHIPLET_FIR_MASK; + RECOVERABLE: + ((PB_CHIPLET_RE_FIR >> 2 ) & `1FDFF80000000000`) & ~PB_CHIPLET_FIR_MASK; +}; + +group gPbChipletFir filter singlebit +{ + /** PB_CHIPLET_FIR[3] + * Attention from LFIR + */ + (PbChipletFir, bit(3)) ? analyze(gPbLFir); + + /** PB_CHIPLET_FIR[4] + * Attention from NXDMAENGFIR + */ + (PbChipletFir, bit(4)) ? analyze(gNxDmaEngFir); + + /** PB_CHIPLET_FIR[5] + * Attention from NXCQFIR + */ + (PbChipletFir, bit(5)) ? analyze(gNxCqFir); + + /** PB_CHIPLET_FIR[6] + * Attention from MCDFIR + */ + (PbChipletFir, bit(6)) ? analyze(gMcdFir); + + /** PB_CHIPLET_FIR[7|9] + * Attention from PBWESTFIR or PBEASTFIR + */ + (PbChipletFir, bit(7|9)) ? analyze(gPbWestEastFir); + + /** PB_CHIPLET_FIR[8] + * Attention from PBCENTFIR + */ + (PbChipletFir, bit(8)) ? analyze(gPbCentFir); + + /** PB_CHIPLET_FIR[11] + * Attention from PSIFIR + */ + (PbChipletFir, bit(11)) ? analyze(gPsiFir); + + /** PB_CHIPLET_FIR[12] + * Attention from ICPFIR + */ + (PbChipletFir, bit(12)) ? analyze(gIcpFir); + + /** PB_CHIPLET_FIR[13] + * Attention from PBAFIR + */ + (PbChipletFir, bit(13)) ? analyze(gPbaFir); + + /** PB_CHIPLET_FIR[14] + * Attention from EHHCAFIR + */ + (PbChipletFir, bit(14)) ? analyze(gEhHcaFir); + + /** PB_CHIPLET_FIR[15] + * Attention from NXASFIR + */ + (PbChipletFir, bit(15)) ? analyze(gNxAsFir); + + /** PB_CHIPLET_FIR[16] + * Attention from ENHCAFIR + */ + (PbChipletFir, bit(16)) ? analyze(gEnHcaFir); + + /** PB_CHIPLET_FIR[17|18|19] + * Attention from PCINESTFIRs + */ + (PbChipletFir, bit(17|18|19)) ? analyze(gPciNestFir); + + /** PB_CHIPLET_FIR[20] + * Attention from NXCXAFIR + */ + (PbChipletFir, bit(20)) ? analyze(gNxCxaFir); +}; + +rule PbChipletSpa +{ + SPECIAL: PB_CHIPLET_SPA & ~PB_CHIPLET_SPA_MASK; +}; + +group gPbChipletSpa filter singlebit +{ + /** PB_CHIPLET_SPA[0] + * Attention from PBCENTFIR + */ + (PbChipletSpa, bit(0)) ? analyze(gPbCentFir); +}; + +################################################################################ +# PB Chiplet LFIR +################################################################################ + +rule PbLFir +{ + CHECK_STOP: PB_LFIR & ~PB_LFIR_MASK & ~PB_LFIR_ACT0 & ~PB_LFIR_ACT1; + RECOVERABLE: PB_LFIR & ~PB_LFIR_MASK & ~PB_LFIR_ACT0 & PB_LFIR_ACT1; +}; + +group gPbLFir filter singlebit +{ + /** PB_LFIR[0] + * CFIR internal parity error + */ + (PbLFir, bit(0)) ? TBDDefaultCallout; + + /** PB_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (PbLFir, bit(1)) ? TBDDefaultCallout; + + /** PB_LFIR[2] + * Local errors from CC (PCB error) + */ + (PbLFir, bit(2)) ? TBDDefaultCallout; + + /** PB_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (PbLFir, bit(3)) ? TBDDefaultCallout; + + /** PB_LFIR[4] + * Local errors from PSC (PCB error) + */ + (PbLFir, bit(4)) ? TBDDefaultCallout; + + /** PB_LFIR[5] + * Local errors from PSC (parity error) + */ + (PbLFir, bit(5)) ? TBDDefaultCallout; + + /** PB_LFIR[6] + * Local errors from Thermal (parity error) + */ + (PbLFir, bit(6)) ? TBDDefaultCallout; + + /** PB_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (PbLFir, bit(7)) ? TBDDefaultCallout; + + /** PB_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (PbLFir, bit(8|9)) ? TBDDefaultCallout; + + /** PB_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (PbLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet NXDMAENGFIR +################################################################################ + +rule NxDmaEngFir +{ + CHECK_STOP: + NXDMAENGFIR & ~NXDMAENGFIR_MASK & ~NXDMAENGFIR_ACT0 & ~NXDMAENGFIR_ACT1; + RECOVERABLE: + NXDMAENGFIR & ~NXDMAENGFIR_MASK & ~NXDMAENGFIR_ACT0 & NXDMAENGFIR_ACT1; +}; + +group gNxDmaEngFir filter singlebit +{ +# FIXME - Get confirmation from HW team to see how this FIR is wired. +# Also, a temp fix to generate error signature by setting bit 0 + /** NXDMAENGFIR[0] + * ERROR + */ + (NxDmaEngFir, bit(0)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet NXCQFIR +################################################################################ + +rule NxCqFir +{ + CHECK_STOP: NXCQFIR & ~NXCQFIR_MASK & ~NXCQFIR_ACT0 & ~NXCQFIR_ACT1; + RECOVERABLE: NXCQFIR & ~NXCQFIR_MASK & ~NXCQFIR_ACT0 & NXCQFIR_ACT1; +}; + +group gNxCqFir filter singlebit +{ +# FIXME - Get confirmation from HW team to see how this FIR is wired. +# Also, a temp fix to generate error signature by setting bit 0 + /** NXCQFIR[0] + * ERROR + */ + (NxCqFir, bit(0)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet NXASFIR +################################################################################ + +rule NxAsFir +{ + CHECK_STOP: NXASFIR & ~NXASFIR_MASK & ~NXASFIR_ACT0 & ~NXASFIR_ACT1; + RECOVERABLE: NXASFIR & ~NXASFIR_MASK & ~NXASFIR_ACT0 & NXASFIR_ACT1; +}; + +group gNxAsFir filter singlebit +{ + /** NXASFIR[0] + * SND_ARY_UE + */ + (NxAsFir, bit(0)) ? TBDDefaultCallout; + + /** NXASFIR[1] + * MMIO_DAT_UE + */ + (NxAsFir, bit(1)) ? TBDDefaultCallout; + + /** NXASFIR[2] + * COPREQ_DAT_UE + */ + (NxAsFir, bit(2)) ? TBDDefaultCallout; + + /** NXASFIR[3] + * PBCQ_Q_INFO_PE + */ + (NxAsFir, bit(3)) ? TBDDefaultCallout; + + /** NXASFIR[4] + * RCMD0_ADDR_PE + */ + (NxAsFir, bit(4)) ? TBDDefaultCallout; + + /** NXASFIR[5] + * RCMD0_TTAG_PE + */ + (NxAsFir, bit(5)) ? TBDDefaultCallout; + + /** NXASFIR[6] + * RCMD1_ADDR_PE + */ + (NxAsFir, bit(6)) ? TBDDefaultCallout; + + /** NXASFIR[7] + * RCMD1_TTAG_PE + */ + (NxAsFir, bit(7)) ? TBDDefaultCallout; + + /** NXASFIR[8] + * MAL_FMD_MMIO_ST + */ + (NxAsFir, bit(8)) ? TBDDefaultCallout; + + /** NXASFIR[9] + * DATA_HANG + */ + (NxAsFir, bit(9)) ? TBDDefaultCallout; + + /** NXASFIR[10] + * CANNOT_RTY_ERR + */ + (NxAsFir, bit(10)) ? TBDDefaultCallout; + + /** NXASFIR[11] + * CMPL_CNT_ERR + */ + (NxAsFir, bit(11)) ? TBDDefaultCallout; + + /** NXASFIR[12] + * MULT_CAM_HIT_ERR + */ + (NxAsFir, bit(12)) ? TBDDefaultCallout; + + /** NXASFIR[13] + * FUTURE_ERR_1 + */ + (NxAsFir, bit(13)) ? TBDDefaultCallout; + + /** NXASFIR[14] + * FL_FIFO_OVFLW + */ + (NxAsFir, bit(14)) ? TBDDefaultCallout; + + /** NXASFIR[15] + * CMD_TO_INVALID_RW + */ + (NxAsFir, bit(15)) ? TBDDefaultCallout; + + /** NXASFIR[16] + * DMA_WL_UE + */ + (NxAsFir, bit(16)) ? TBDDefaultCallout; + + /** NXASFIR[17] + * CREDWT_RTY_ERR + */ + (NxAsFir, bit(17)) ? TBDDefaultCallout; + + /** NXASFIR[18] + * NOTIFY_RTY_ERR + */ + (NxAsFir, bit(18)) ? TBDDefaultCallout; + + /** NXASFIR[19] + * RCV_TAB_UE + */ + (NxAsFir, bit(19)) ? TBDDefaultCallout; + + /** NXASFIR[20] + * FIFO_ADR_TAB_UE + */ + (NxAsFir, bit(20)) ? TBDDefaultCallout; + + /** NXASFIR[21] + * MMIO_CR_DARY_UE + */ + (NxAsFir, bit(21)) ? TBDDefaultCallout; + + /** NXASFIR[22] + * NOTIF_ARY_UE + */ + (NxAsFir, bit(22)) ? TBDDefaultCallout; + + /** NXASFIR[23] + * INTR_ARY_UE + */ + (NxAsFir, bit(23)) ? TBDDefaultCallout; + + /** NXASFIR[24] + * CR0_ATAG_PE + */ + (NxAsFir, bit(24)) ? TBDDefaultCallout; + + /** NXASFIR[25] + * CR0_TTAG_PE + */ + (NxAsFir, bit(25)) ? TBDDefaultCallout; + + /** NXASFIR[26] + * CR1_ATAG_PE + */ + (NxAsFir, bit(26)) ? TBDDefaultCallout; + + /** NXASFIR[27] + * CR1_TTAG_PE + */ + (NxAsFir, bit(27)) ? TBDDefaultCallout; + + /** NXASFIR[28] + * CW_ADR_ERR + */ + (NxAsFir, bit(28)) ? TBDDefaultCallout; + + /** NXASFIR[29] + * INTR_RTY_CNT_EXP + */ + (NxAsFir, bit(29)) ? TBDDefaultCallout; + + /** NXASFIR[30] + * EG_OVFLW + */ + (NxAsFir, bit(30)) ? TBDDefaultCallout; + + /** NXASFIR[31] + * MULT_PM_HIT + */ + (NxAsFir, bit(31)) ? TBDDefaultCallout; + + /** NXASFIR[32] + * EG_SCOM_ERR + */ + (NxAsFir, bit(32)) ? TBDDefaultCallout; + + /** NXASFIR[33] + * UNUSUAL_EG_SCENARIO + */ + (NxAsFir, bit(33)) ? TBDDefaultCallout; + + /** NXASFIR[34] + * DSLC_INTF_PE + */ + (NxAsFir, bit(34)) ? TBDDefaultCallout; + + /** NXASFIR[35] + * AS_IN_CE + */ + (NxAsFir, bit(35)) ? TBDDefaultCallout; + + /** NXASFIR[36] + * AS_IN_UNSUP_CFG + */ + (NxAsFir, bit(36)) ? TBDDefaultCallout; + + /** NXASFIR[37] + * COPREQ_CRESP_ERR + */ + (NxAsFir, bit(37)) ? TBDDefaultCallout; + + /** NXASFIR[38] + * CREDWT_CRESP_ERR + */ + (NxAsFir, bit(38)) ? TBDDefaultCallout; + + /** NXASFIR[39] + * AS_IN_SP_FIR + */ + (NxAsFir, bit(39)) ? TBDDefaultCallout; + + /** NXASFIR[40] + * AS_EG_CE + */ + (NxAsFir, bit(40)) ? TBDDefaultCallout; + + /** NXASFIR[41] + * SCOM_ERR + */ + (NxAsFir, bit(41)) ? TBDDefaultCallout; + + /** NXASFIR[42] + * SCOM_ERR_DUP + */ + (NxAsFir, bit(42)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet NXCXAFIR +################################################################################ + +rule NxCxaFir +{ + CHECK_STOP: NXCXAFIR & ~NXCXAFIR_MASK & ~NXCXAFIR_ACT0 & ~NXCXAFIR_ACT1; + RECOVERABLE: NXCXAFIR & ~NXCXAFIR_MASK & ~NXCXAFIR_ACT0 & NXCXAFIR_ACT1; +}; + +group gNxCxaFir filter singlebit +{ + /** NXCXAFIR[0] + * BAR_PE + */ + (NxCxaFir, bit(0)) ? TBDDefaultCallout; + + /** NXCXAFIR[1] + * REGISTER_PE + */ + (NxCxaFir, bit(1)) ? TBDDefaultCallout; + + /** NXCXAFIR[2] + * MASTER_ARRAY_CE + */ + (NxCxaFir, bit(2)) ? TBDDefaultCallout; + + /** NXCXAFIR[3] + * MASTER_ARRAY_UE + */ + (NxCxaFir, bit(3)) ? TBDDefaultCallout; + + /** NXCXAFIR[4] + * TIMER_EXPIRED_RECOV_ERROR + */ + (NxCxaFir, bit(4)) ? TBDDefaultCallout; + + /** NXCXAFIR[5] + * TIMER_EXPIRED_XSTOP_ERROR + */ + (NxCxaFir, bit(5)) ? TBDDefaultCallout; + + /** NXCXAFIR[6] + * PSL_CMD_UE + */ + (NxCxaFir, bit(6)) ? TBDDefaultCallout; + + /** NXCXAFIR[7] + * PSL_CMD_SUE + */ + (NxCxaFir, bit(7)) ? TBDDefaultCallout; + + /** NXCXAFIR[8] + * SNOOP_ARRAY_CE + */ + (NxCxaFir, bit(8)) ? TBDDefaultCallout; + + /** NXCXAFIR[9] + * SNOOP_ARRAY_UE + */ + (NxCxaFir, bit(9)) ? TBDDefaultCallout; + + /** NXCXAFIR[10] + * RECOVERY_FAILED + */ + (NxCxaFir, bit(10)) ? TBDDefaultCallout; + + /** NXCXAFIR[13] + * MASTER_RECOVERABLE_ERROR + */ + (NxCxaFir, bit(13)) ? TBDDefaultCallout; + + /** NXCXAFIR[14] + * SNOOPER_RECOVERABLE_ERROR + */ + (NxCxaFir, bit(14)) ? TBDDefaultCallout; + + /** NXCXAFIR[15] + * XPT_RECOVERABLE_ERROR + */ + (NxCxaFir, bit(15)) ? TBDDefaultCallout; + + /** NXCXAFIR[16] + * MASTER_SYS_XSTOP_ERROR + */ + (NxCxaFir, bit(16)) ? TBDDefaultCallout; + + /** NXCXAFIR[17] + * SNOOPER_SYS_XSTOP_ERROR + */ + (NxCxaFir, bit(17)) ? TBDDefaultCallout; + + /** NXCXAFIR[18] + * XPT_SYS_XSTOP_ERROR + */ + (NxCxaFir, bit(18)) ? TBDDefaultCallout; + + /** NXCXAFIR[19] + * MUOP_ERROR_1 + */ + (NxCxaFir, bit(19)) ? TBDDefaultCallout; + + /** NXCXAFIR[20] + * MUOP_ERROR_2 + */ + (NxCxaFir, bit(20)) ? TBDDefaultCallout; + + /** NXCXAFIR[21] + * MUOP_ERROR_3 + */ + (NxCxaFir, bit(21)) ? TBDDefaultCallout; + + /** NXCXAFIR[22] + * SUOP_ERROR_1 + */ + (NxCxaFir, bit(22)) ? TBDDefaultCallout; + + /** NXCXAFIR[23] + * SUOP_ERROR_2 + */ + (NxCxaFir, bit(23)) ? TBDDefaultCallout; + + /** NXCXAFIR[24] + * SUOP_ERROR_3 + */ + (NxCxaFir, bit(24)) ? TBDDefaultCallout; + + /** NXCXAFIR[25] + * POWERBUS_MISC_ERROR + */ + (NxCxaFir, bit(25)) ? TBDDefaultCallout; + + /** NXCXAFIR[26] + * POWERBUS_INTERFACE_PE + */ + (NxCxaFir, bit(26)) ? TBDDefaultCallout; + + /** NXCXAFIR[27] + *POWERBUS_DATA_HANG_ERROR + */ + (NxCxaFir, bit(27)) ? TBDDefaultCallout; + + /** NXCXAFIR[28] + * POWERBUS_HANG_ERROR + */ + (NxCxaFir, bit(28)) ? TBDDefaultCallout; + + /** NXCXAFIR[29] + * LD_CLASS_CMD_ADDR_ERR + */ + (NxCxaFir, bit(29)) ? TBDDefaultCallout; + + /** NXCXAFIR[30] + * ST_CLASS_CMD_ADDR_ERR + */ + (NxCxaFir, bit(30)) ? TBDDefaultCallout; + + /** NXCXAFIR[31] + * PHB_LINK_DOWN + */ + (NxCxaFir, bit(31)) ? TBDDefaultCallout; + + /** NXCXAFIR[32] + * LD_CLASS_CMD_FOREIGN_LINK_FAIL + */ + (NxCxaFir, bit(32)) ? TBDDefaultCallout; + + /** NXCXAFIR[33] + * FOREIGN_LINK_HANG_ERROR + */ + (NxCxaFir, bit(33)) ? TBDDefaultCallout; + + /** NXCXAFIR[34] + * XPT_POWERBUS_CE + */ + (NxCxaFir, bit(34)) ? TBDDefaultCallout; + + /** NXCXAFIR[35] + * XPT_POWERBUS_UE + */ + (NxCxaFir, bit(35)) ? TBDDefaultCallout; + + /** NXCXAFIR[36] + * XPT_POWERBUS_SUE + */ + (NxCxaFir, bit(36)) ? TBDDefaultCallout; + + /** NXCXAFIR[37] + * TLBI_TIMEOUT + */ + (NxCxaFir, bit(37)) ? TBDDefaultCallout; + + /** NXCXAFIR[38] + * TLBI_SEQ_ERR + */ + (NxCxaFir, bit(38)) ? TBDDefaultCallout; + + /** NXCXAFIR[39] + * TLBI_BAD_OP_ERR + */ + (NxCxaFir, bit(39)) ? TBDDefaultCallout; + + /** NXCXAFIR[40] + * TLBI_SEQ_NUM_PARITY_ERR + */ + (NxCxaFir, bit(40)) ? TBDDefaultCallout; + + /** NXCXAFIR[41] + * ST_CLASS_CMD_FOREIGN_LINK_FAIL + */ + (NxCxaFir, bit(41)) ? TBDDefaultCallout; + + /** NXCXAFIR[47] + * SCOM_ERR2 + */ + (NxCxaFir, bit(47)) ? TBDDefaultCallout; + + /** NXCXAFIR[48] + * SCOM_ERR + */ + (NxCxaFir, bit(48)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet MCDFIR +################################################################################ + +rule McdFir +{ + CHECK_STOP: MCDFIR & ~MCDFIR_MASK & ~MCDFIR_ACT0 & ~MCDFIR_ACT1; + RECOVERABLE: MCDFIR & ~MCDFIR_MASK & ~MCDFIR_ACT0 & MCDFIR_ACT1; +}; + +group gMcdFir filter singlebit +{ + /** MCDFIR[0] + * MCD_ARRAY_ECC_UE_ERR + */ + (McdFir, bit(0)) ? TBDDefaultCallout; + + /** MCDFIR[1] + * MCD_ARRAY_ECC_CE_ERR + */ + (McdFir, bit(1)) ? TBDDefaultCallout; + + /** MCDFIR[2] + * MCD_REG_PARITY_ERR + */ + (McdFir, bit(2)) ? TBDDefaultCallout; + + /** MCDFIR[3] + * MCD_SM_ERR + */ + (McdFir, bit(3)) ? TBDDefaultCallout; + + /** MCDFIR[4] + * MCD_REC_HANG_ERR + */ + (McdFir, bit(4)) ? TBDDefaultCallout; + + /** MCDFIR[5] + * MCD_PB_PARITY_ERR + */ + (McdFir, bit(5)) ? TBDDefaultCallout; + + /** MCDFIR[6] + * MCD_UNSOLICITED_CRESP_ERR + */ + (McdFir, bit(6)) ? TBDDefaultCallout; + + /** MCDFIR[7] + * MCD_ACK_DEAD_ERR + */ + (McdFir, bit(7)) ? TBDDefaultCallout; + + /** MCDFIR[8] + * FIR_PARITY_ERR2 + */ + (McdFir, bit(8)) ? TBDDefaultCallout; + + /** MCDFIR[9] + * FIR_PARITY_ERR + */ + (McdFir, bit(9)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet PBEASTFIR and PBWESTFIR +################################################################################ + +# TODO - All these FIRs should have the same bit definition. Idealy, we will +# only want to have one copy of the bit definition. Unfortuately, the +# rule code parser does not have the support for something like this. +# Maybe we can add this as a later feature. + +rule PbEastFir +{ + CHECK_STOP: PBEASTFIR & ~PBEASTFIR_MASK & ~PBEASTFIR_ACT0 & ~PBEASTFIR_ACT1; + RECOVERABLE: PBEASTFIR & ~PBEASTFIR_MASK & ~PBEASTFIR_ACT0 & PBEASTFIR_ACT1; +}; + +rule PbWestFir +{ + CHECK_STOP: PBWESTFIR & ~PBWESTFIR_MASK & ~PBWESTFIR_ACT0 & ~PBWESTFIR_ACT1; + RECOVERABLE: PBWESTFIR & ~PBWESTFIR_MASK & ~PBWESTFIR_ACT0 & PBWESTFIR_ACT1; +}; + +group gPbWestEastFir filter singlebit +{ + /** PBWESTFIR[0] + * PB_WEST_PBIEX01_PBH_HW_ERROR + */ + (PbWestFir, bit(0)) ? TBDDefaultCallout; + + /** PBEASTFIR[0] + * PB_EAST_PBIEX04_PBH_HW_ERROR + */ + (PbEastFir, bit(0)) ? TBDDefaultCallout; + + /** PBWESTFIR[1] + * PB_WEST_PBIEX01_PBH_RECOV_ERROR + */ + (PbWestFir, bit(1)) ? TBDDefaultCallout; + + /** PBEASTFIR[1] + * PB_EAST_PBIEX04_PBH_RECOV_ERROR + */ + (PbEastFir, bit(1)) ? TBDDefaultCallout; + + /** PBWESTFIR[2] + * PB_WEST_PBIEX01_PBH_PROTOCOL_ERROR + */ + (PbWestFir, bit(2)) ? TBDDefaultCallout; + + /** PBEASTFIR[2] + * PB_EAST_PBIEX04_PBH_PROTOCOL_ERROR + */ + (PbEastFir, bit(2)) ? TBDDefaultCallout; + + /** PBWESTFIR[3] + * PB_WEST_PBIEX01_PBH_OVERFLOW_ERROR + */ + (PbWestFir, bit(3)) ? TBDDefaultCallout; + + /** PBEASTFIR[3] + * PB_EAST_PBIEX04_PBH_OVERFLOW_ERROR + */ + (PbEastFir, bit(3)) ? TBDDefaultCallout; + + /** PBWESTFIR[4] + * PB_WEST_PBIEX02_PBH_HW_ERROR + */ + (PbWestFir, bit(4)) ? TBDDefaultCallout; + + /** PBEASTFIR[4] + * PB_EAST_PBIEX05_PBH_HW_ERROR + */ + (PbEastFir, bit(4)) ? TBDDefaultCallout; + + /** PBWESTFIR[5] + * PB_WEST_PBIEX02_PBH_RECOV_ERROR + */ + (PbWestFir, bit(5)) ? TBDDefaultCallout; + + /** PBEASTFIR[5] + * PB_EAST_PBIEX05_PBH_RECOV_ERROR + */ + (PbEastFir, bit(5)) ? TBDDefaultCallout; + + /** PBWESTFIR[6] + * PB_WEST_PBIEX02_PBH_PROTOCOL_ERROR + */ + (PbWestFir, bit(6)) ? TBDDefaultCallout; + + /** PBEASTFIR[6] + * PB_EAST_PBIEX05_PBH_PROTOCOL_ERROR + */ + (PbEastFir, bit(6)) ? TBDDefaultCallout; + + /** PBWESTFIR[7] + * PB_WEST_PBIEX02_PBH_OVERFLOW_ERROR + */ + (PbWestFir, bit(7)) ? TBDDefaultCallout; + + /** PBEASTFIR[7] + * PB_EAST_PBIEX05_PBH_OVERFLOW_ERROR + */ + (PbEastFir, bit(7)) ? TBDDefaultCallout; + + /** PBWESTFIR[8] + * PB_WEST_PBIEX03_PBH_HW_ERROR + */ + (PbWestFir, bit(8)) ? TBDDefaultCallout; + + /** PBEASTFIR[8] + * PB_EAST_PBIEX06_PBH_HW_ERROR + */ + (PbEastFir, bit(8)) ? TBDDefaultCallout; + + /** PBWESTFIR[9] + * PB_WEST_PBIEX03_PBH_RECOV_ERROR + */ + (PbWestFir, bit(9)) ? TBDDefaultCallout; + + /** PBEASTFIR[9] + * PB_EAST_PBIEX06_PBH_RECOV_ERROR + */ + (PbEastFir, bit(9)) ? TBDDefaultCallout; + + /** PBWESTFIR[10] + * PB_WEST_PBIEX03_PBH_PROTOCOL_ERROR + */ + (PbWestFir, bit(10)) ? TBDDefaultCallout; + + /** PBEASTFIR[10] + * PB_EAST_PBIEX06_PBH_PROTOCOL_ERROR + */ + (PbEastFir, bit(10)) ? TBDDefaultCallout; + + /** PBWESTFIR[11] + * PB_WEST_PBIEX03_PBH_OVERFLOW_ERROR + */ + (PbWestFir, bit(11)) ? TBDDefaultCallout; + + /** PBEASTFIR[11] + * PB_EAST_PBIEX06_PBH_OVERFLOW_ERROR + */ + (PbEastFir, bit(11)) ? TBDDefaultCallout; + + /** PBWESTFIR[12] + * PB_WEST_PBIEX09_PBH_HW_ERROR + */ + (PbWestFir, bit(12)) ? TBDDefaultCallout; + + /** PBEASTFIR[12] + * PB_EAST_PBIEX12_PBH_HW_ERROR + */ + (PbEastFir, bit(12)) ? TBDDefaultCallout; + + /** PBWESTFIR[13] + * PB_WEST_PBIEX09_PBH_RECOV_ERROR + */ + (PbWestFir, bit(13)) ? TBDDefaultCallout; + + /** PBEASTFIR[13] + * PB_EAST_PBIEX12_PBH_RECOV_ERROR + */ + (PbEastFir, bit(13)) ? TBDDefaultCallout; + + /** PBWESTFIR[14] + * PB_WEST_PBIEX09_PBH_PROTOCOL_ERROR + */ + (PbWestFir, bit(14)) ? TBDDefaultCallout; + + /** PBEASTFIR[14] + * PB_EAST_PBIEX12_PBH_PROTOCOL_ERROR + */ + (PbEastFir, bit(14)) ? TBDDefaultCallout; + + /** PBWESTFIR[15] + * PB_WEST_PBIEX09_PBH_OVERFLOW_ERROR + */ + (PbWestFir, bit(15)) ? TBDDefaultCallout; + + /** PBEASTFIR[15] + * PB_EAST_PBIEX12_PBH_OVERFLOW_ERROR + */ + (PbEastFir, bit(15)) ? TBDDefaultCallout; + + /** PBWESTFIR[16] + * PB_WEST_PBIEX10_PBH_HW_ERROR + */ + (PbWestFir, bit(16)) ? TBDDefaultCallout; + + /** PBEASTFIR[16] + * PB_EAST_PBIEX13_PBH_HW_ERROR + */ + (PbEastFir, bit(16)) ? TBDDefaultCallout; + + /** PBWESTFIR[17] + * PB_WEST_PBIEX10_PBH_RECOV_ERROR + */ + (PbWestFir, bit(17)) ? TBDDefaultCallout; + + /** PBEASTFIR[17] + * PB_EAST_PBIEX13_PBH_RECOV_ERROR + */ + (PbEastFir, bit(17)) ? TBDDefaultCallout; + + /** PBWESTFIR[18] + * PB_WEST_PBIEX10_PBH_PROTOCOL_ERROR + */ + (PbWestFir, bit(18)) ? TBDDefaultCallout; + + /** PBEASTFIR[18] + * PB_EAST_PBIEX13_PBH_PROTOCOL_ERROR + */ + (PbEastFir, bit(18)) ? TBDDefaultCallout; + + /** PBWESTFIR[19] + * PB_WEST_PBIEX10_PBH_OVERFLOW_ERROR + */ + (PbWestFir, bit(19)) ? TBDDefaultCallout; + + /** PBEASTFIR[19] + * PB_EAST_PBIEX13_PBH_OVERFLOW_ERROR + */ + (PbEastFir, bit(19)) ? TBDDefaultCallout; + + /** PBWESTFIR[20] + * PB_WEST_PBIEX11_PBH_HW_ERROR + */ + (PbWestFir, bit(20)) ? TBDDefaultCallout; + + /** PBEASTFIR[20] + * PB_EAST_PBIEX14_PBH_HW_ERROR + */ + (PbEastFir, bit(20)) ? TBDDefaultCallout; + + /** PBWESTFIR[21] + * PB_WEST_PBIEX11_PBH_RECOV_ERROR + */ + (PbWestFir, bit(21)) ? TBDDefaultCallout; + + /** PBEASTFIR[21] + * PB_EAST_PBIEX14_PBH_RECOV_ERROR + */ + (PbEastFir, bit(21)) ? TBDDefaultCallout; + + /** PBWESTFIR[22] + * PB_WEST_PBIEX11_PBH_PROTOCOL_ERROR + */ + (PbWestFir, bit(22)) ? TBDDefaultCallout; + + /** PBEASTFIR[22] + * PB_EAST_PBIEX14_PBH_PROTOCOL_ERROR + */ + (PbEastFir, bit(22)) ? TBDDefaultCallout; + + /** PBWESTFIR[23] + * PB_WEST_PBIEX11_PBH_OVERFLOW_ERROR + */ + (PbWestFir, bit(23)) ? TBDDefaultCallout; + + /** PBEASTFIR[23] + * PB_EAST_PBIEX14_PBH_OVERFLOW_ERROR + */ + (PbEastFir, bit(23)) ? TBDDefaultCallout; + + /** PBWESTFIR[24] + * PB_WEST_DATA_OVERFLOW_ERROR + */ + (PbWestFir, bit(24)) ? TBDDefaultCallout; + + /** PBEASTFIR[24] + * PB_EAST_DATA_OVERFLOW_ERROR + */ + (PbEastFir, bit(24)) ? TBDDefaultCallout; + + /** PBWESTFIR[25] + * PB_WEST_DATA_PROTOCOL_ERROR + */ + (PbWestFir, bit(25)) ? TBDDefaultCallout; + + /** PBEASTFIR[25] + * PB_EAST_DATA_PROTOCOL_ERROR + */ + (PbEastFir, bit(25)) ? TBDDefaultCallout; + + /** PBWESTFIR[26] + * PB_WEST_DATA_ROUTE_ERROR + */ + (PbWestFir, bit(26)) ? TBDDefaultCallout; + + /** PBEASTFIR[26] + * PB_EAST_DATA_ROUTE_ERROR + */ + (PbEastFir, bit(26)) ? TBDDefaultCallout; + + /** PBWESTFIR[27] + * PB_WEST_CMD_OVERFLOW_ERROR + */ + (PbWestFir, bit(27)) ? TBDDefaultCallout; + + /** PBEASTFIR[27] + * PB_EAST_CMD_OVERFLOW_ERROR + */ + (PbEastFir, bit(27)) ? TBDDefaultCallout; + + /** PBWESTFIR[32] + * FIR_SCOM_WEST_ERR + */ + (PbWestFir, bit(32)) ? TBDDefaultCallout; + + /** PBEASTFIR[32] + * FIR_SCOM_EAST_ERR + */ + (PbEastFir, bit(32)) ? TBDDefaultCallout; + + /** PBWESTFIR[33] + * FIR_SCOM_WEST_ERR_DUP + */ + (PbWestFir, bit(33)) ? TBDDefaultCallout; + + /** PBEASTFIR[33] + * FIR_SCOM_EAST_ERR_DUP + */ + (PbEastFir, bit(33)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet PBCENTFIR +################################################################################ + +rule PbCentFir +{ + CHECK_STOP: PBCENTFIR & ~PBCENTFIR_MASK & ~PBCENTFIR_ACT0 & ~PBCENTFIR_ACT1; + RECOVERABLE: PBCENTFIR & ~PBCENTFIR_MASK & ~PBCENTFIR_ACT0 & PBCENTFIR_ACT1; + SPECIAL: PBCENTFIR & ~PBCENTFIR_MASK & PBCENTFIR_ACT0 & ~PBCENTFIR_ACT1; +}; + +group gPbCentFir filter singlebit +{ + /** PBCENTFIR[0] + * PB_CENT_PROTOCOL_ERROR + */ + (PbCentFir, bit(0)) ? TBDDefaultCallout; + + /** PBCENTFIR[1] + * PB_CENT_OVERFLOW_ERROR + */ + (PbCentFir, bit(1)) ? TBDDefaultCallout; + + /** PBCENTFIR[2] + * PB_CENT_HW_PARITY_ERROR + */ + (PbCentFir, bit(2)) ? TBDDefaultCallout; + + /** PBCENTFIR[3] + * PB_CENT_TLBIE_TM_TIMEOUT_ERROR + */ + (PbCentFir, bit(3)) ? TBDDefaultCallout; + + /** PBCENTFIR[4] + * PB_CENT_COHERENCY_ERROR + */ + (PbCentFir, bit(4)) ? TBDDefaultCallout; + + /** PBCENTFIR[5] + * PB_CENT_CRESP_ADDR_ERROR + */ + (PbCentFir, bit(5)) ? TBDDefaultCallout; + + /** PBCENTFIR[6] + * PB_CENT_CRESP_ERROR + */ + (PbCentFir, bit(6)) ? TBDDefaultCallout; + + /** PBCENTFIR[7] + * PB_CENT_HANG_RECOVERY_LIMIT_ERROR + */ + (PbCentFir, bit(7)) ? TBDDefaultCallout; + + /** PBCENTFIR[8] + * PB_CENT_DATA_ROUTE_ERROR + */ + (PbCentFir, bit(8)) ? TBDDefaultCallout; + + /** PBCENTFIR[9] + * PB_CENT_HANG_RECOVERY_GTE_LEVEL1 + */ + (PbCentFir, bit(9)) ? TBDDefaultCallout; + + /** PBCENTFIR[10] + * PB_CENT_FORCE_MP_IPL + */ + (PbCentFir, bit(10)) ? TBDDefaultCallout; + + /** PBCENTFIR[11] + * PB_CENT_FIR_SPARE_0 + */ + (PbCentFir, bit(11)) ? TBDDefaultCallout; + + /** PBCENTFIR[12] + * PB_CENT_F0LINK_ERROR + */ + (PbCentFir, bit(12)) ? TBDDefaultCallout; + + /** PBCENTFIR[13] + * PB_CENT_F1LINK_ERROR + */ + (PbCentFir, bit(13)) ? TBDDefaultCallout; + + /** PBCENTFIR[14] + * PB_CENT_F0_OVERFLOW + */ + (PbCentFir, bit(14)) ? TBDDefaultCallout; + + /** PBCENTFIR[15] + * PB_CENT_F1_OVERFLOW + */ + (PbCentFir, bit(15)) ? TBDDefaultCallout; + + /** PBCENTFIR[16] + * FIR_SCOM_CENT_ERR + */ + (PbCentFir, bit(16)) ? TBDDefaultCallout; + + /** PBCENTFIR[17] + * FIR_SCOM_CENT_ERR_DUP + */ + (PbCentFir, bit(17)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet PSIFIR +################################################################################ + +rule PsiFir +{ + CHECK_STOP: PSIFIR & ~PSIFIR_MASK & ~PSIFIR_ACT0 & ~PSIFIR_ACT1; + RECOVERABLE: PSIFIR & ~PSIFIR_MASK & ~PSIFIR_ACT0 & PSIFIR_ACT1; +}; + +group gPsiFir filter singlebit +{ + /** PSIFIR[0] + * PB_ECC_ERR_CE + */ + (PsiFir, bit(0)) ? TBDDefaultCallout; + + /** PSIFIR[1] + * PB_ECC_ERR_UE + */ + (PsiFir, bit(1)) ? TBDDefaultCallout; + + /** PSIFIR[2] + * PB_ECC_ERR_SUE + */ + (PsiFir, bit(3)) ? TBDDefaultCallout; + + /** PSIFIR[4] + * INTERRUPT_FROM_FSP + */ + (PsiFir, bit(4)) ? TBDDefaultCallout; + + /** PSIFIR[5] + * FSP_ECC_ERR_CE + */ + (PsiFir, bit(5)) ? TBDDefaultCallout; + + /** PSIFIR[6] + * FSP_ECC_ERR_UE + */ + (PsiFir, bit(6)) ? TBDDefaultCallout; + + /** PSIFIR[7] + * ERROR_STATE + */ + (PsiFir, bit(7)) ? TBDDefaultCallout; + + /** PSIFIR[8] + * INVALID_TTYPE + */ + (PsiFir, bit(8)) ? TBDDefaultCallout; + + /** PSIFIR[9] + * INVALID_CRESP + */ + (PsiFir, bit(9)) ? TBDDefaultCallout; + + /** PSIFIR[10] + * PB_DATA_TIME_OUT + */ + (PsiFir, bit(10)) ? TBDDefaultCallout; + + /** PSIFIR[11] + * PB_PARITY_ERROR + */ + (PsiFir, bit(11)) ? TBDDefaultCallout; + + /** PSIFIR[12] + * FSP_ACCESS_TRUSTED_SPACE + */ + (PsiFir, bit(12)) ? TBDDefaultCallout; + + /** PSIFIR[13] + * UNEXPECTED_PB + */ + (PsiFir, bit(13)) ? TBDDefaultCallout; + + /** PSIFIR[14] + * INTERRUPT_REG_CHANGE_WHILE_ACTIVE + */ + (PsiFir, bit(14)) ? TBDDefaultCallout; + + /** PSIFIR[15] + * INTERRUPT0_ADDRESS_ERROR + */ + (PsiFir, bit(15)) ? TBDDefaultCallout; + + /** PSIFIR[16] + * INTERRUPT1_ADDRESS_ERROR + */ + (PsiFir, bit(16)) ? TBDDefaultCallout; + + /** PSIFIR[17] + * INTERRUPT2_ADDRESS_ERROR + */ + (PsiFir, bit(17)) ? TBDDefaultCallout; + + /** PSIFIR[18] + * INTERRUPT3_ADDRESS_ERROR + */ + (PsiFir, bit(18)) ? TBDDefaultCallout; + + /** PSIFIR[19] + * INTERRUPT4_ADDRESS_ERROR + */ + (PsiFir, bit(19)) ? TBDDefaultCallout; + + /** PSIFIR[20] + * INTERRUPT5_ADDRESS_ERROR + */ + (PsiFir, bit(20)) ? TBDDefaultCallout; + + /** PSIFIR[21] + * TCBR_TP_PSI_GLB_ERR_0 + */ + (PsiFir, bit(21)) ? TBDDefaultCallout; + + /** PSIFIR[22] + * TCBR_TP_PSI_GLB_ERR_1 + */ + (PsiFir, bit(22)) ? TBDDefaultCallout; + + /** PSIFIR[23] + * SCOM_ERROR + */ + (PsiFir, bit(23)) ? TBDDefaultCallout; + + /** PSIFIR[24] + * FIR_PARITY_ERROR + */ + (PsiFir, bit(24)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet ICPFIR +################################################################################ + +rule IcpFir +{ + CHECK_STOP: ICPFIR & ~ICPFIR_MASK & ~ICPFIR_ACT0 & ~ICPFIR_ACT1; + RECOVERABLE: ICPFIR & ~ICPFIR_MASK & ~ICPFIR_ACT0 & ICPFIR_ACT1; +}; + +group gIcpFir filter singlebit +{ + /** ICPFIR[0] + * INT_HW_ERROR_EOI_Q + */ + (IcpFir, bit(0)) ? TBDDefaultCallout; + + /** ICPFIR[1] + * INT_HW_ERROR_FWD_Q + */ + (IcpFir, bit(1)) ? TBDDefaultCallout; + + /** ICPFIR[2] + * INT_HW_ERROR_IR_QU + */ + (IcpFir, bit(2)) ? TBDDefaultCallout; + + /** ICPFIR[3] + * INT_HW_ERROR_RET_Q + */ + (IcpFir, bit(3)) ? TBDDefaultCallout; + + /** ICPFIR[4] + * INT_HW_ERROR_ADDRI + */ + (IcpFir, bit(4)) ? TBDDefaultCallout; + + /** ICPFIR[5] + * INT_HW_ERROR_DATAI + */ + (IcpFir, bit(5)) ? TBDDefaultCallout; + + /** ICPFIR[6] + * INT_HW_ERROR_ADDRO + */ + (IcpFir, bit(7)) ? TBDDefaultCallout; + + /** ICPFIR[8] + * INT_HW_ERROR_LDSTQ + */ + (IcpFir, bit(8)) ? TBDDefaultCallout; + + /** ICPFIR[9] + * INT_HW_ERROR_REQQ + */ + (IcpFir, bit(9)) ? TBDDefaultCallout; + + /** ICPFIR[10] + * SCOM_REG_CHECK + */ + (IcpFir, bit(10)) ? TBDDefaultCallout; + + /** ICPFIR[11] + * INVALID_FORWARD_SETUP + */ + (IcpFir, bit(11)) ? TBDDefaultCallout; + + /** ICPFIR[12] + * ADDRESS_CORE_FIELD + */ + (IcpFir, bit(12)) ? TBDDefaultCallout; + + /** ICPFIR[13] + * ADDRESS_CORE_FIELD_MMIO + */ + (IcpFir, bit(13)) ? TBDDefaultCallout; + + /** ICPFIR[14] + * UNSOLICITED_CRESP + */ + (IcpFir, bit(14)) ? TBDDefaultCallout; + + /** ICPFIR[15] + * UNSOLICITED_DATA + */ + (IcpFir, bit(15)) ? TBDDefaultCallout; + + /** ICPFIR[16] + * INVALID_CMD + */ + (IcpFir, bit(16)) ? TBDDefaultCallout; + + /** ICPFIR[17] + * INVALID_CRESPZ + */ + (IcpFir, bit(17)) ? TBDDefaultCallout; + + /** ICPFIR[18] + * INVALID_CRESP + */ + (IcpFir, bit(18)) ? TBDDefaultCallout; + + /** ICPFIR[19] + * Reserved field (Access type is reserved) + */ + (IcpFir, bit(19)) ? TBDDefaultCallout; + + /** ICPFIR[20] + * ECC_CE_ON_DATA + */ + (IcpFir, bit(20)) ? TBDDefaultCallout; + + /** ICPFIR[21] + * ECC_UE_ON_DATA + */ + (IcpFir, bit(21)) ? TBDDefaultCallout; + + /** ICPFIR[22] + * ECC_SUE_ON_DATA + */ + (IcpFir, bit(22)) ? TBDDefaultCallout; + + /** ICPFIR[23] + * PARITY_CHK_ADDRESS + */ + (IcpFir, bit(23)) ? TBDDefaultCallout; + + /** ICPFIR[24] + * PARITY_CHK_TAG + */ + (IcpFir, bit(24)) ? TBDDefaultCallout; + + /** ICPFIR[25] + * TIMEOUT_LD_STQ + */ + (IcpFir, bit(25)) ? TBDDefaultCallout; + + /** ICPFIR[26] + * TIMEOUT_RETURNQ + */ + (IcpFir, bit(26)) ? TBDDefaultCallout; + + /** ICPFIR[27] + * TIMEOUT_FWDQ + */ + (IcpFir, bit(27)) ? TBDDefaultCallout; + + /** ICPFIR[28] + * TIMEOUT_EOIQ + */ + (IcpFir, bit(28)) ? TBDDefaultCallout; + + /** ICPFIR[32] + * EXT_TRACE_0 + */ + (IcpFir, bit(32)) ? TBDDefaultCallout; + + /** ICPFIR[33] + * EXT_TRACE_1 + */ + (IcpFir, bit(33)) ? TBDDefaultCallout; + + /** ICPFIR[34] + * ADU_RECOV + */ + (IcpFir, bit(34)) ? TBDDefaultCallout; + + /** ICPFIR[35] + * EXT_XSTOP + */ + (IcpFir, bit(35)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet PBAFIR +################################################################################ + +rule PbaFir +{ + CHECK_STOP: PBAFIR & ~PBAFIR_MASK & ~PBAFIR_ACT0 & ~PBAFIR_ACT1; + RECOVERABLE: PBAFIR & ~PBAFIR_MASK & ~PBAFIR_ACT0 & PBAFIR_ACT1; +}; + +group gPbaFir filter singlebit +{ + /** PBAFIR[0] + * PBAFIR_OCI_APAR_ERR + */ + (PbaFir, bit(0)) ? TBDDefaultCallout; + + /** PBAFIR[1] + * PBAFIR_PB_RDADRERR_FW + */ + (PbaFir, bit(1)) ? TBDDefaultCallout; + + /** PBAFIR[2] + * PBAFIR_PB_RDDATATO_FW + */ + (PbaFir, bit(2)) ? TBDDefaultCallout; + + /** PBAFIR[3] + * PBAFIR_PB_SUE_FW + */ + (PbaFir, bit(3)) ? TBDDefaultCallout; + + /** PBAFIR[4] + * PBAFIR_PB_UE_FW + */ + (PbaFir, bit(4)) ? TBDDefaultCallout; + + /** PBAFIR[5] + * PBAFIR_PB_CE_FW + */ + (PbaFir, bit(5)) ? TBDDefaultCallout; + + /** PBAFIR[6] + * PBAFIR_OCI_SLAVE_INIT + */ + (PbaFir, bit(6)) ? TBDDefaultCallout; + + /** PBAFIR[7] + * PBAFIR_OCI_WRPAR_ERR + */ + (PbaFir, bit(7)) ? TBDDefaultCallout; + + /** PBAFIR[8] + * PBAFIR_OCI_REREQTO + */ + (PbaFir, bit(8)) ? TBDDefaultCallout; + + /** PBAFIR[9] + * PBAFIR_PB_UNEXPCRESP + */ + (PbaFir, bit(9)) ? TBDDefaultCallout; + + /** PBAFIR[10] + * PBAFIR_PB_UNEXPDATA + */ + (PbaFir, bit(10)) ? TBDDefaultCallout; + + /** PBAFIR[11] + * PBAFIR_PB_PARITY_ERR + */ + (PbaFir, bit(11)) ? TBDDefaultCallout; + + /** PBAFIR[12] + * PBAFIR_PB_WRADRERR_FW + */ + (PbaFir, bit(12)) ? TBDDefaultCallout; + + /** PBAFIR[13] + * PBAFIR_PB_BADCRESP + */ + (PbaFir, bit(13)) ? TBDDefaultCallout; + + /** PBAFIR[14] + * PBAFIR_PB_ACKDEAD_FW + */ + (PbaFir, bit(14)) ? TBDDefaultCallout; + + /** PBAFIR[15] + * PBAFIR_PB_CRESPTO + */ + (PbaFir, bit(15)) ? TBDDefaultCallout; + + /** PBAFIR[16] + * PBAFIR_BCUE_SETUP_ERR + */ + (PbaFir, bit(16)) ? TBDDefaultCallout; + + /** PBAFIR[17] + * PBAFIR_BCUE_PB_ACK_DEAD + */ + (PbaFir, bit(17)) ? TBDDefaultCallout; + + /** PBAFIR[18] + * PBAFIR_BCUE_PB_ADRERR + */ + (PbaFir, bit(18)) ? TBDDefaultCallout; + + /** PBAFIR[19] + * PBAFIR_BCUE_OCI_DATERR + */ + (PbaFir, bit(19)) ? TBDDefaultCallout; + + /** PBAFIR[20] + * PBAFIR_BCDE_SETUP_ERR + */ + (PbaFir, bit(20)) ? TBDDefaultCallout; + + /** PBAFIR[21] + * PBAFIR_BCDE_PB_ACK_DEAD + */ + (PbaFir, bit(21)) ? TBDDefaultCallout; + + /** PBAFIR[22] + * PBAFIR_BCDE_PB_ADRERR + */ + (PbaFir, bit(22)) ? TBDDefaultCallout; + + /** PBAFIR[23] + * PBAFIR_BCDE_RDDATATO_ERR + */ + (PbaFir, bit(23)) ? TBDDefaultCallout; + + /** PBAFIR[24] + * PBAFIR_BCDE_SUE_ERR + */ + (PbaFir, bit(24)) ? TBDDefaultCallout; + + /** PBAFIR[25] + * PBAFIR_BCDE_UE_ERR + */ + (PbaFir, bit(25)) ? TBDDefaultCallout; + + /** PBAFIR[26] + * PBAFIR_BCDE_CE + */ + (PbaFir, bit(26)) ? TBDDefaultCallout; + + /** PBAFIR[27] + * PBAFIR_BCDE_OCI_DATERR + */ + (PbaFir, bit(27)) ? TBDDefaultCallout; + + /** PBAFIR[28] + * PBAFIR_INTERNAL_ERR + */ + (PbaFir, bit(28)) ? TBDDefaultCallout; + + /** PBAFIR[29] + * PBAFIR_ILLEGAL_CACHE_OP + */ + (PbaFir, bit(29)) ? TBDDefaultCallout; + + /** PBAFIR[30] + * PBAFIR_OCI_BAD_REG_ADDR + */ + (PbaFir, bit(30)) ? TBDDefaultCallout; + + /** PBAFIR[31] + * PBAFIR_AXPUSH_WRERR + */ + (PbaFir, bit(31)) ? TBDDefaultCallout; + + /** PBAFIR[32] + * PBAFIR_AXRCV_DLO_ERR + */ + (PbaFir, bit(32)) ? TBDDefaultCallout; + + /** PBAFIR[33] + * PBAFIR_AXRCV_DLO_TO + */ + (PbaFir, bit(33)) ? TBDDefaultCallout; + + /** PBAFIR[34] + * PBAFIR_AXRCV_RSVDATA_TO + */ + (PbaFir, bit(34)) ? TBDDefaultCallout; + + /** PBAFIR[35] + * PBAFIR_AXFLOW_ERR + */ + (PbaFir, bit(35)) ? TBDDefaultCallout; + + /** PBAFIR[36] + * PBAFIR_AXSND_DHI_RTYTO + */ + (PbaFir, bit(36)) ? TBDDefaultCallout; + + /** PBAFIR[37] + * PBAFIR_AXSND_DLO_RTYTO + */ + (PbaFir, bit(37)) ? TBDDefaultCallout; + + /** PBAFIR[38] + * PBAFIR_AXSND_RSVTO + */ + (PbaFir, bit(38)) ? TBDDefaultCallout; + + /** PBAFIR[39] + * PBAFIR_AXSND_RSVERR + */ + (PbaFir, bit(39)) ? TBDDefaultCallout; + + /** PBAFIR[40] + * PBAFIR_PB_ACKDEAD_FW_WR + */ + (PbaFir, bit(40)) ? TBDDefaultCallout; + + /** PBAFIR[44|45] + * PBAFIR_FIR_PARITY_ERR + */ + (PbaFir, bit(44|45)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet EHHCAFIR +################################################################################ + +rule EhHcaFir +{ + CHECK_STOP: EHHCAFIR & ~EHHCAFIR_MASK & ~EHHCAFIR_ACT0 & ~EHHCAFIR_ACT1; + RECOVERABLE: EHHCAFIR & ~EHHCAFIR_MASK & ~EHHCAFIR_ACT0 & EHHCAFIR_ACT1; +}; + +group gEhHcaFir filter singlebit +{ + /** EHHCAFIR[0] + * CE1_0_OUT: array0_a CE + */ + (EhHcaFir, bit(0)) ? TBDDefaultCallout; + + /** EHHCAFIR[1] + * CE2_0_OUT: array0_b CE + */ + (EhHcaFir, bit(1)) ? TBDDefaultCallout; + + /** EHHCAFIR[2 + * UE1_0_OUT: array0_a ue + */ + (EhHcaFir, bit(2)) ? TBDDefaultCallout; + + /** EHHCAFIR[3] + * UE2_0_OUT: array0_b ue + */ + (EhHcaFir, bit(3)) ? TBDDefaultCallout; + + /** EHHCAFIR[4] + * CE1_1_OUT: array1_a CE + */ + (EhHcaFir, bit(4)) ? TBDDefaultCallout; + + /** EHHCAFIR[5] + * CE2_1_OUT: array1_b CE + */ + (EhHcaFir, bit(5)) ? TBDDefaultCallout; + + /** EHHCAFIR[6] + * UE1_1_OUT: array1_a ue + */ + (EhHcaFir, bit(6)) ? TBDDefaultCallout; + + /** EHHCAFIR[7] + * UE2_1_OUT: array1_b ue + */ + (EhHcaFir, bit(7)) ? TBDDefaultCallout; + + /** EHHCAFIR[8] + * CE1_2_OUT: array2_a CE + */ + (EhHcaFir, bit(8)) ? TBDDefaultCallout; + + /** EHHCAFIR[9] + * CE2_2_OUT: array2_b CE + */ + (EhHcaFir, bit(9)) ? TBDDefaultCallout; + + /** EHHCAFIR[10] + * UE1_2_OUT: array2_a ue + */ + (EhHcaFir, bit(10)) ? TBDDefaultCallout; + + /** EHHCAFIR[11] + * UE2_2_OUT: array2_b ue + */ + (EhHcaFir, bit(11)) ? TBDDefaultCallout; + + /** EHHCAFIR[12] + * CE1_3_OUT: array3_a CE + */ + (EhHcaFir, bit(12)) ? TBDDefaultCallout; + + /** EHHCAFIR[13] + * CE2_3_OUT: array3_b CE + */ + (EhHcaFir, bit(13)) ? TBDDefaultCallout; + + /** EHHCAFIR[14] + * UE1_3_OUT: array3_a ue + */ + (EhHcaFir, bit(14)) ? TBDDefaultCallout; + + /** EHHCAFIR[15] + * UE2_3_OUT: array3_b ue + */ + (EhHcaFir, bit(15)) ? TBDDefaultCallout; + + /** EHHCAFIR[16] + * CE1_4_OUT: array4_a CE + */ + (EhHcaFir, bit(16)) ? TBDDefaultCallout; + + /** EHHCAFIR[17] + * CE2_4_OUT: array4_b CE + */ + (EhHcaFir, bit(17)) ? TBDDefaultCallout; + + /** EHHCAFIR[18] + * UE1_4_OUT: array4_a ue + */ + (EhHcaFir, bit(18)) ? TBDDefaultCallout; + + /** EHHCAFIR[19] + * UE2_4_OUT: array4_b ue + */ + (EhHcaFir, bit(19)) ? TBDDefaultCallout; + + /** EHHCAFIR[20] + * CE1_5_OUT: array5_a CE + */ + (EhHcaFir, bit(20)) ? TBDDefaultCallout; + + /** EHHCAFIR[21] + * CE2_5_OUT: array5_b CE + */ + (EhHcaFir, bit(21)) ? TBDDefaultCallout; + + /** EHHCAFIR[22] + * UE1_5_OUT: array5_a ue + */ + (EhHcaFir, bit(22)) ? TBDDefaultCallout; + + /** EHHCAFIR[23] + * UE2_5_OUT: array5_b ue + */ + (EhHcaFir, bit(23)) ? TBDDefaultCallout; + + /** EHHCAFIR[24] + * CE1_6_OUT: array6_a CE + */ + (EhHcaFir, bit(24)) ? TBDDefaultCallout; + + /** EHHCAFIR[25] + * CE2_6_OUT: array6_b CE + */ + (EhHcaFir, bit(25)) ? TBDDefaultCallout; + + /** EHHCAFIR[26] + * UE1_6_OUT: array6_a ue + */ + (EhHcaFir, bit(26)) ? TBDDefaultCallout; + + /** EHHCAFIR[27] + * UE2_6_OUT: array6_b ue + */ + (EhHcaFir, bit(27)) ? TBDDefaultCallout; + + /** EHHCAFIR[28] + * CE1_7_OUT: array7_a CE + */ + (EhHcaFir, bit(28)) ? TBDDefaultCallout; + + /** EHHCAFIR[29] + * CE2_7_OUT: array7_b CE + */ + (EhHcaFir, bit(29)) ? TBDDefaultCallout; + + /** EHHCAFIR[30] + * UE1_7_OUT: array7_a ue + */ + (EhHcaFir, bit(30)) ? TBDDefaultCallout; + + /** EHHCAFIR[31] + * UE2_7_OUT: array7_b ue + */ + (EhHcaFir, bit(31)) ? TBDDefaultCallout; + + /** EHHCAFIR[32] + * DROP_COUNTER_FULL: Drop Counter Full + */ + (EhHcaFir, bit(32)) ? TBDDefaultCallout; + + /** EHHCAFIR[33] + * INTERNAL_ERROR: Internal Error + */ + (EhHcaFir, bit(33)) ? TBDDefaultCallout; + + /** EHHCAFIR[34] + * SCOM_ERROR + */ + (EhHcaFir, bit(34)) ? TBDDefaultCallout; + + /** EHHCAFIR[35] + * FIR_PARITY_ERROR + */ + (EhHcaFir, bit(35)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet ENHCAFIR +################################################################################ + +rule EnHcaFir +{ + CHECK_STOP: ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ~ENHCAFIR_ACT1; + RECOVERABLE: ENHCAFIR & ~ENHCAFIR_MASK & ~ENHCAFIR_ACT0 & ENHCAFIR_ACT1; +}; + +group gEnHcaFir filter singlebit +{ + /** ENHCAFIR[0] + * DPX0_DAT_UE: PB0 data UE + */ + (EnHcaFir, bit(0)) ? TBDDefaultCallout; + + /** ENHCAFIR[1] + * DPX0_DAT_SUE: PB0 data UE + */ + (EnHcaFir, bit(1)) ? TBDDefaultCallout; + + /** ENHCAFIR[2] + * DPX0_DAT_CE: PB0 data ue + */ + (EnHcaFir, bit(2)) ? TBDDefaultCallout; + + /** ENHCAFIR[3] + * + */ + (EnHcaFir, bit(3)) ? TBDDefaultCallout; + + /** ENHCAFIR[4] + * CO_DROP_COUNTER_FULL: Castout Drop Counter Full + */ + (EnHcaFir, bit(4)) ? TBDDefaultCallout; + + /** ENHCAFIR[5] + * DATA_HANG_DETECT: Castout Drop Counter Full + */ + (EnHcaFir, bit(5)) ? TBDDefaultCallout; + + /** ENHCAFIR[6] + * UNEXPECTED_DATA_OR_CRESP: Castout Drop Counter Full + */ + (EnHcaFir, bit(6)) ? TBDDefaultCallout; + + /** ENHCAFIR[7] + * INTERNAL_ERROR: Castout Drop Counter Full + */ + (EnHcaFir, bit(7)) ? TBDDefaultCallout; + + /** ENHCAFIR[8] + * SCOM_ERROR + */ + (EnHcaFir, bit(8)) ? TBDDefaultCallout; + + /** ENHCAFIR[9] + * FIR_PARITY_ERROR + */ + (EnHcaFir, bit(9)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet PCINESTFIRs +################################################################################ + +# TODO - All these FIRs should have the same bit definition. Idealy, we will +# only want to have one copy of the bit definition. Unfortuately, the +# rule code parser does not have the support for something like this. +# Maybe we can add this as a later feature. + +rule PciNestFir_0 +{ + CHECK_STOP: + PCINESTFIR_0 & ~PCINESTFIR_0_MASK & ~PCINESTFIR_0_ACT0 & ~PCINESTFIR_0_ACT1; + RECOVERABLE: + PCINESTFIR_0 & ~PCINESTFIR_0_MASK & ~PCINESTFIR_0_ACT0 & PCINESTFIR_0_ACT1; +}; + +rule PciNestFir_1 +{ + CHECK_STOP: + PCINESTFIR_1 & ~PCINESTFIR_1_MASK & ~PCINESTFIR_1_ACT0 & ~PCINESTFIR_1_ACT1; + RECOVERABLE: + PCINESTFIR_1 & ~PCINESTFIR_1_MASK & ~PCINESTFIR_1_ACT0 & PCINESTFIR_1_ACT1; +}; + +rule PciNestFir_2 +{ + CHECK_STOP: + PCINESTFIR_2 & ~PCINESTFIR_2_MASK & ~PCINESTFIR_2_ACT0 & ~PCINESTFIR_2_ACT1; + RECOVERABLE: + PCINESTFIR_2 & ~PCINESTFIR_2_MASK & ~PCINESTFIR_2_ACT0 & PCINESTFIR_2_ACT1; +}; + +group gPciNestFir filter singlebit +{ + /** PCINESTFIR_0[0] + * BAR_PE + */ + (PciNestFir_0, bit(0)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[0] + * BAR_PE + */ + (PciNestFir_1, bit(0)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[0] + * BAR_PE + */ + (PciNestFir_2, bit(0)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[1] + * NONBAR_PE + */ + (PciNestFir_0, bit(1)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[1] + * NONBAR_PE + */ + (PciNestFir_1, bit(1)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[1] + * NONBAR_PE + */ + (PciNestFir_2, bit(1)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[2] + * PB_TO_PEC_CE + */ + (PciNestFir_0, bit(2)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[2] + * PB_TO_PEC_CE + */ + (PciNestFir_1, bit(2)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[2] + * PB_TO_PEC_CE + */ + (PciNestFir_2, bit(2)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[3] + * PB_TO_PEC_UE + */ + (PciNestFir_0, bit(3)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[3] + * PB_TO_PEC_UE + */ + (PciNestFir_1, bit(3)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[3] + * PB_TO_PEC_UE + */ + (PciNestFir_2, bit(3)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[4] + * PB_TO_PEC_SUE + */ + (PciNestFir_0, bit(4)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[4] + * PB_TO_PEC_SUE + */ + (PciNestFir_1, bit(4)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[4] + * PB_TO_PEC_SUE + */ + (PciNestFir_2, bit(4)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[5] + * ARY_ECC_CE + */ + (PciNestFir_0, bit(5)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[5] + * ARY_ECC_CE + */ + (PciNestFir_1, bit(5)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[5] + * ARY_ECC_CE + */ + (PciNestFir_2, bit(5)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[6] + * ARY_ECC_UE + */ + (PciNestFir_0, bit(6)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[6] + * ARY_ECC_UE + */ + (PciNestFir_1, bit(6)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[6] + * ARY_ECC_UE + */ + (PciNestFir_2, bit(6)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[7] + * ARY_ECC_SUE + */ + (PciNestFir_0, bit(7)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[7] + * ARY_ECC_SUE + */ + (PciNestFir_1, bit(7)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[7] + * ARY_ECC_SUE + */ + (PciNestFir_2, bit(7)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[8] + * REGISTER_ARRAY_PE + */ + (PciNestFir_0, bit(8)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[8] + * REGISTER_ARRAY_PE + */ + (PciNestFir_1, bit(8)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[8] + * REGISTER_ARRAY_PE + */ + (PciNestFir_2, bit(8)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[9] + * PB_INTERFACE_PE + */ + (PciNestFir_0, bit(9)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[9] + * PB_INTERFACE_PE + */ + (PciNestFir_1, bit(9)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[9] + * PB_INTERFACE_PE + */ + (PciNestFir_2, bit(9)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[10] + * PB_DATA_HANG_ERRORS + */ + (PciNestFir_0, bit(10)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[10] + * PB_DATA_HANG_ERRORS + */ + (PciNestFir_1, bit(10)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[10] + * PB_DATA_HANG_ERRORS + */ + (PciNestFir_2, bit(10)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[11] + * PB_HANG_ERRORS + */ + (PciNestFir_0, bit(11)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[11] + * PB_HANG_ERRORS + */ + (PciNestFir_1, bit(11)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[11] + * PB_HANG_ERRORS + */ + (PciNestFir_2, bit(11)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[12] + * RD_ARE_ERRORS + */ + (PciNestFir_0, bit(12)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[12] + * RD_ARE_ERRORS + */ + (PciNestFir_1, bit(12)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[12] + * RD_ARE_ERRORS + */ + (PciNestFir_2, bit(12)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[13] + * NONRD_ARE_ERRORS + */ + (PciNestFir_0, bit(13)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[13] + * NONRD_ARE_ERRORS + */ + (PciNestFir_1, bit(13)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[13] + * NONRD_ARE_ERRORS + */ + (PciNestFir_2, bit(13)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[14] + * PCI_HANG_ERROR + */ + (PciNestFir_0, bit(14)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[14] + * PCI_HANG_ERROR + */ + (PciNestFir_1, bit(14)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[14] + * PCI_HANG_ERROR + */ + (PciNestFir_2, bit(14)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[15] + * PCI_CLOCK_ERROR + */ + (PciNestFir_0, bit(15)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[15] + * PCI_CLOCK_ERROR + */ + (PciNestFir_1, bit(15)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[15] + * PCI_CLOCK_ERROR + */ + (PciNestFir_2, bit(15)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[16] + * AIB_FENCE + */ + (PciNestFir_0, bit(16)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[16] + * AIB_FENCE + */ + (PciNestFir_1, bit(16)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[16] + * AIB_FENCE + */ + (PciNestFir_2, bit(16)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[17] + * HW_ERRORS + */ + (PciNestFir_0, bit(17)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[17] + * HW_ERRORS + */ + (PciNestFir_1, bit(17)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[17] + * HW_ERRORS + */ + (PciNestFir_2, bit(17)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[18] + * UNSOLICITIEDPBDATA + */ + (PciNestFir_0, bit(18)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[18] + * UNSOLICITIEDPBDATA + */ + (PciNestFir_1, bit(18)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[18] + * UNSOLICITIEDPBDATA + */ + (PciNestFir_2, bit(18)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[19] + * UNEXPECTEDCRESP + */ + (PciNestFir_0, bit(19)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[19] + * UNEXPECTEDCRESP + */ + (PciNestFir_1, bit(19)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[19] + * UNEXPECTEDCRESP + */ + (PciNestFir_2, bit(19)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[20] + * INVALIDCRESP + */ + (PciNestFir_0, bit(20)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[20] + * INVALIDCRESP + */ + (PciNestFir_1, bit(20)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[20] + * INVALIDCRESP + */ + (PciNestFir_2, bit(20)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[21] + * PBUNSUPPORTEDSIZE + */ + (PciNestFir_0, bit(21)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[21] + * PBUNSUPPORTEDSIZE + */ + (PciNestFir_1, bit(21)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[21] + * PBUNSUPPORTEDSIZE + */ + (PciNestFir_2, bit(21)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[22] + * PBUNSUPPORTEDCMD + */ + (PciNestFir_0, bit(22)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[22] + * PBUNSUPPORTEDCMD + */ + (PciNestFir_1, bit(22)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[22] + * PBUNSUPPORTEDCMD + */ + (PciNestFir_2, bit(22)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[23] + * AIB_PE + */ + (PciNestFir_0, bit(23)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[23] + * AIB_PE + */ + (PciNestFir_1, bit(23)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[23] + * AIB_PE + */ + (PciNestFir_2, bit(23)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[24] + * ASB_ERROR + */ + (PciNestFir_0, bit(24)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[24] + * ASB_ERROR + */ + (PciNestFir_1, bit(24)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[24] + * ASB_ERROR + */ + (PciNestFir_2, bit(24)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[25] + * FOREIGN_LINK_FAIL + */ + (PciNestFir_0, bit(25)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[25] + * FOREIGN_LINK_FAIL + */ + (PciNestFir_1, bit(25)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[25] + * FOREIGN_LINK_FAIL + */ + (PciNestFir_2, bit(25)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[26] + * FOREIGN_PB_HANG + */ + (PciNestFir_0, bit(26)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[26] + * FOREIGN_PB_HANG + */ + (PciNestFir_1, bit(26)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[26] + * FOREIGN_PB_HANG + */ + (PciNestFir_2, bit(26)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[27] + * CAPP_ERROR + */ + (PciNestFir_0, bit(27)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[27] + * CAPP_ERROR + */ + (PciNestFir_1, bit(27)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[27] + * CAPP_ERROR + */ + (PciNestFir_2, bit(27)) ? TBDDefaultCallout; + + /** PCINESTFIR_0[28] + * SYNC_SCOM_ERR + */ + (PciNestFir_0, bit(28)) ? TBDDefaultCallout; + + /** PCINESTFIR_1[28] + * SYNC_SCOM_ERR + */ + (PciNestFir_1, bit(28)) ? TBDDefaultCallout; + + /** PCINESTFIR_2[28] + * SYNC_SCOM_ERR + */ + (PciNestFir_2, bit(28)) ? TBDDefaultCallout; +}; + +################################################################################ +# PB Chiplet IOMCFIR_0 +################################################################################ + +# Venice only + +################################################################################ +# PB Chiplet IOMCFIR_1 +################################################################################ + +rule IomcFir_1 +{ + CHECK_STOP: IOMCFIR_1 & ~IOMCFIR_1_MASK & ~IOMCFIR_1_ACT0 & ~IOMCFIR_1_ACT1; + RECOVERABLE: IOMCFIR_1 & ~IOMCFIR_1_MASK & ~IOMCFIR_1_ACT0 & IOMCFIR_1_ACT1; +}; + +group gIomcFir_1 filter singlebit +{ +# FIXME:A temp fix to generate error signature by setting bit 0 + /** IOMCFIR_1[0] + * ERROR + */ + (IomcFir_1, bit(0)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to PB chiplet +################################################################################ + + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_acts_PCIE.rule b/src/usr/diag/prdf/plat/pegasus/Proc_acts_PCIE.rule new file mode 100644 index 000000000..b527c24c0 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_acts_PCIE.rule @@ -0,0 +1,1476 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_acts_PCIE.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# PCIE Chiplet Registers +################################################################################ + +rule PcieChipletFir +{ + CHECK_STOP: + (PCIE_CHIPLET_CS_FIR & `1EE0000000000000`) & ~PCIE_CHIPLET_FIR_MASK; + RECOVERABLE: + ((PCIE_CHIPLET_RE_FIR >> 2) & `1EE0000000000000`) & ~PCIE_CHIPLET_FIR_MASK; +}; + +group gPcieChipletFir filter singlebit +{ + /** PCIE_CHIPLET_FIR[3] + * Attention from LFIR + */ + (PcieChipletFir, bit(3)) ? analyze(gPcieLFir); + + /** PCIE_CHIPLET_FIR[4|5|6] + * Attention from PCICLOCKFIR (0-2) + */ + (PcieChipletFir, bit(4|5|6)) ? analyze(gPciClockFir); + + /** PCIE_CHIPLET_FIR[8] + * Attention from PBFFIR + */ + (PcieChipletFir, bit(8)) ? analyze(gPbfFir); + + /** PCIE_CHIPLET_FIR[9|10] + * Attention from IOPPCIFIR (0-1) + */ + (PcieChipletFir, bit(9|10)) ? analyze(gIopPciFir); +}; + +rule PcieChipletSpa +{ + SPECIAL: PCIE_CHIPLET_SPA & ~PCIE_CHIPLET_SPA_MASK; +}; + +group gPcieChipletSpa filter singlebit +{ + /** PCIE_CHIPLET_SPA[0] + * Attention from PBFFIR + */ + (PcieChipletSpa, bit(0)) ? analyze(gPbfFir); +}; + +################################################################################ +# PCIE Chiplet LFIR +################################################################################ + +rule PcieLFir +{ + CHECK_STOP: PCIE_LFIR & ~PCIE_LFIR_MASK & ~PCIE_LFIR_ACT0 & ~PCIE_LFIR_ACT1; + RECOVERABLE: PCIE_LFIR & ~PCIE_LFIR_MASK & ~PCIE_LFIR_ACT0 & PCIE_LFIR_ACT1; +}; + +group gPcieLFir filter singlebit +{ + /** PCIE_LFIR[0] + * CFIR internal parity error + */ + (PcieLFir, bit(0)) ? TBDDefaultCallout; + + /** PCIE_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (PcieLFir, bit(1)) ? TBDDefaultCallout; + + /** PCIE_LFIR[2] + * Local errors from CC (PCB error) + */ + (PcieLFir, bit(2)) ? TBDDefaultCallout; + + /** PCIE_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (PcieLFir, bit(3)) ? TBDDefaultCallout; + + /** PCIE_LFIR[4] + * Local errors from PSC (PCB error) + */ + (PcieLFir, bit(4)) ? TBDDefaultCallout; + + /** PCIE_LFIR[5] + * Local errors from PSC (parity error) + */ + (PcieLFir, bit(5)) ? TBDDefaultCallout; + + /** PCIE_LFIR[6] + * Local errors from Thermal (parity error) + */ + (PcieLFir, bit(6)) ? TBDDefaultCallout; + + /** PCIE_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (PcieLFir, bit(7)) ? TBDDefaultCallout; + + /** PCIE_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (PcieLFir, bit(8|9)) ? TBDDefaultCallout; + + /** PCIE_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (PcieLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# PCIE Chiplet PCICLOCKFIRs +################################################################################ + +# TODO - All these FIRs should have the same bit definition. Idealy, we will +# only want to have one copy of the bit definition. Unfortuately, the +# rule code parser does not have the support for something like this. +# Maybe we can add this as a later feature. + +rule PciClockFir_0 +{ + CHECK_STOP: + PCICLOCKFIR_0 & ~PCICLOCKFIR_0_MASK & ~PCICLOCKFIR_0_ACT0 & ~PCICLOCKFIR_0_ACT1; + RECOVERABLE: + PCICLOCKFIR_0 & ~PCICLOCKFIR_0_MASK & ~PCICLOCKFIR_0_ACT0 & PCICLOCKFIR_0_ACT1; +}; + +rule PciClockFir_1 +{ + CHECK_STOP: + PCICLOCKFIR_1 & ~PCICLOCKFIR_1_MASK & ~PCICLOCKFIR_1_ACT0 & ~PCICLOCKFIR_1_ACT1; + RECOVERABLE: + PCICLOCKFIR_1 & ~PCICLOCKFIR_1_MASK & ~PCICLOCKFIR_1_ACT0 & PCICLOCKFIR_1_ACT1; +}; + +rule PciClockFir_2 +{ + CHECK_STOP: + PCICLOCKFIR_2 & ~PCICLOCKFIR_2_MASK & ~PCICLOCKFIR_2_ACT0 & ~PCICLOCKFIR_2_ACT1; + RECOVERABLE: + PCICLOCKFIR_2 & ~PCICLOCKFIR_2_MASK & ~PCICLOCKFIR_2_ACT0 & PCICLOCKFIR_2_ACT1; +}; + +group gPciClockFir filter singlebit +{ + /** PCICLOCKFIR_0[0] + * AIB_COMMAND_INVALID + */ + (PciClockFir_0, bit(0)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[0] + * AIB_COMMAND_INVALID + */ + (PciClockFir_1, bit(0)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[0] + * AIB_COMMAND_INVALID + */ + (PciClockFir_2, bit(0)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[1] + * AIB_ADDRESSING_ERROR + */ + (PciClockFir_0, bit(1)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[1] + * AIB_ADDRESSING_ERROR + */ + (PciClockFir_1, bit(1)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[1] + * AIB_ADDRESSING_ERROR + */ + (PciClockFir_2, bit(1)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[2] + * AIB_SIZE_ALIGNMENT_ERROR + */ + (PciClockFir_0, bit(2)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[2] + * AIB_SIZE_ALIGNMENT_ERROR + */ + (PciClockFir_1, bit(2)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[2] + * AIB_SIZE_ALIGNMENT_ERROR + */ + (PciClockFir_2, bit(2)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[3] + * Reserved field (Access type is Reserved00) + */ + (PciClockFir_0, bit(3)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[3] + * Reserved field (Access type is Reserved00) + */ + (PciClockFir_1, bit(3)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[3] + * Reserved field (Access type is Reserved00) + */ + (PciClockFir_2, bit(3)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[4] + * AIB_CMD_CTRLS_PARITY_ERROR + */ + (PciClockFir_0, bit(4)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[4] + * AIB_CMD_CTRLS_PARITY_ERROR + */ + (PciClockFir_1, bit(4)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[4] + * AIB_CMD_CTRLS_PARITY_ERROR + */ + (PciClockFir_2, bit(4)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[5] + * AIB_DATA_CTRLS_PARITY_ERROR + */ + (PciClockFir_0, bit(5)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[5] + * AIB_DATA_CTRLS_PARITY_ERROR + */ + (PciClockFir_1, bit(5)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[5] + * AIB_DATA_CTRLS_PARITY_ERROR + */ + (PciClockFir_2, bit(5)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[6] + * MMIO_BAR_DOMAIN_TABLE_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_0, bit(6)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[6] + * MMIO_BAR_DOMAIN_TABLE_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_1, bit(6)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[6] + * MMIO_BAR_DOMAIN_TABLE_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_2, bit(6)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[7] + * MMIO_BAR_DOMAIN_TABLE_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_0, bit(7)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[7] + * MMIO_BAR_DOMAIN_TABLE_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_1, bit(7)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[7] + * MMIO_BAR_DOMAIN_TABLE_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_2, bit(7)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[8] + * AIB_BUS_PARITY_ERROR + */ + (PciClockFir_0, bit(8)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[8] + * AIB_BUS_PARITY_ERROR + */ + (PciClockFir_1, bit(8)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[8] + * AIB_BUS_PARITY_ERROR + */ + (PciClockFir_2, bit(8)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[9] + * Reserved field (Access type is Reserved01) + */ + (PciClockFir_0, bit(9)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[9] + * Reserved field (Access type is Reserved01) + */ + (PciClockFir_1, bit(9)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[9] + * Reserved field (Access type is Reserved01) + */ + (PciClockFir_2, bit(9)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[10] + * AIB_DATA_CTRLS_SEQUENCE_ERROR + */ + (PciClockFir_0, bit(10)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[10] + * AIB_DATA_CTRLS_SEQUENCE_ERROR + */ + (PciClockFir_1, bit(10)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[10] + * AIB_DATA_CTRLS_SEQUENCE_ERROR + */ + (PciClockFir_2, bit(10)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[11] + * MMIO_CMD_DATA_PARITY_ERROR + */ + (PciClockFir_0, bit(11)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[11] + * MMIO_CMD_DATA_PARITY_ERROR + */ + (PciClockFir_1, bit(11)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[11] + * MMIO_CMD_DATA_PARITY_ERROR + */ + (PciClockFir_2, bit(11)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[12] + * PCI_E_CFG_IO_WRITE_CA_OR_UR_RESPONSE + */ + (PciClockFir_0, bit(12)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[12] + * PCI_E_CFG_IO_WRITE_CA_OR_UR_RESPONSE + */ + (PciClockFir_1, bit(12)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[12] + * PCI_E_CFG_IO_WRITE_CA_OR_UR_RESPONSE + */ + (PciClockFir_2, bit(12)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[13] + * GBIF_TIMEOUT + */ + (PciClockFir_0, bit(13)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[13] + * GBIF_TIMEOUT + */ + (PciClockFir_1, bit(13)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[13] + * GBIF_TIMEOUT + */ + (PciClockFir_2, bit(13)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[14] + * MMIO_PENDING_ERROR + */ + (PciClockFir_0, bit(14)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[14] + * MMIO_PENDING_ERROR + */ + (PciClockFir_1, bit(14)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[14] + * MMIO_PENDING_ERROR + */ + (PciClockFir_2, bit(14)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[15] + * AIB_RX_DATA_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_0, bit(15)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[15] + * AIB_RX_DATA_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_1, bit(15)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[15] + * AIB_RX_DATA_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_2, bit(15)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[16] + * AIB_RX_DATA_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_0, bit(16)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[16] + * AIB_RX_DATA_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_1, bit(16)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[16] + * AIB_RX_DATA_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_2, bit(16)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[17] + * DCT_TABLE_ERROR + */ + (PciClockFir_0, bit(17)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[17] + * DCT_TABLE_ERROR + */ + (PciClockFir_1, bit(17)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[17] + * DCT_TABLE_ERROR + */ + (PciClockFir_2, bit(17)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[18] + * DMA_RESPONSE_DATA_ERROR + */ + (PciClockFir_0, bit(18)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[18] + * DMA_RESPONSE_DATA_ERROR + */ + (PciClockFir_1, bit(18)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[18] + * DMA_RESPONSE_DATA_ERROR + */ + (PciClockFir_2, bit(18)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[19] + * DMA_RESPONSE_TIMEOUT + */ + (PciClockFir_0, bit(19)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[19] + * DMA_RESPONSE_TIMEOUT + */ + (PciClockFir_1, bit(19)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[19] + * DMA_RESPONSE_TIMEOUT + */ + (PciClockFir_2, bit(19)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[20] + * TCE_RD_RESPONSE_ERROR_INDICATION + */ + (PciClockFir_0, bit(20)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[20] + * TCE_RD_RESPONSE_ERROR_INDICATION + */ + (PciClockFir_1, bit(20)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[20] + * TCE_RD_RESPONSE_ERROR_INDICATION + */ + (PciClockFir_2, bit(20)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[21] + * CFG_RETRY_TIMEOUT_ERROR + */ + (PciClockFir_0, bit(21)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[21] + * CFG_RETRY_TIMEOUT_ERROR + */ + (PciClockFir_1, bit(21)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[21] + * CFG_RETRY_TIMEOUT_ERROR + */ + (PciClockFir_2, bit(21)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[22] + * CFG_ACCESS_ERROR + */ + (PciClockFir_0, bit(22)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[22] + * CFG_ACCESS_ERROR + */ + (PciClockFir_1, bit(22)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[22] + * CFG_ACCESS_ERROR + */ + (PciClockFir_2, bit(22)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[24] + * RGA_MACRO_INTERNAL_ERROR + */ + (PciClockFir_0, bit(24)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[24] + * RGA_MACRO_INTERNAL_ERROR + */ + (PciClockFir_1, bit(24)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[24] + * RGA_MACRO_INTERNAL_ERROR + */ + (PciClockFir_2, bit(24)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[25] + * PHB3_REGISTER_PARITY_ERROR_RSM_ONE_HOT_ERROR + */ + (PciClockFir_0, bit(25)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[25] + * PHB3_REGISTER_PARITY_ERROR_RSM_ONE_HOT_ERROR + */ + (PciClockFir_1, bit(25)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[25] + * PHB3_REGISTER_PARITY_ERROR_RSM_ONE_HOT_ERROR + */ + (PciClockFir_2, bit(25)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[26] + * PHB3_REGISTER_ACCESS_ERROR + */ + (PciClockFir_0, bit(26)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[26] + * PHB3_REGISTER_ACCESS_ERROR + */ + (PciClockFir_1, bit(26)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[26] + * PHB3_REGISTER_ACCESS_ERROR + */ + (PciClockFir_2, bit(26)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[27] + * PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED + */ + (PciClockFir_0, bit(27)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[27] + * PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED + */ + (PciClockFir_1, bit(27)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[27] + * PAPR_OUTBOUND_INJECTION_ERROR_TRIGGERED + */ + (PciClockFir_2, bit(27)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[28] + * PCI_E_CORE_FATAL_ERROR + */ + (PciClockFir_0, bit(28)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[28] + * PCI_E_CORE_FATAL_ERROR + */ + (PciClockFir_1, bit(28)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[28] + * PCI_E_CORE_FATAL_ERROR + */ + (PciClockFir_2, bit(28)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[29] + * PCI_E_INBOUND_TLP_ECRC_ERROR + */ + (PciClockFir_0, bit(29)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[29] + * PCI_E_INBOUND_TLP_ECRC_ERROR + */ + (PciClockFir_1, bit(29)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[29] + * PCI_E_INBOUND_TLP_ECRC_ERROR + */ + (PciClockFir_2, bit(29)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[30] + * PCI_E_UTL_PRIMARY_INTERRUPT + */ + (PciClockFir_0, bit(30)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[30] + * PCI_E_UTL_PRIMARY_INTERRUPT + */ + (PciClockFir_1, bit(30)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[30] + * PCI_E_UTL_PRIMARY_INTERRUPT + */ + (PciClockFir_2, bit(30)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[31] + * PCI_E_UTL_SECONDARY_INTERRUPT + */ + (PciClockFir_0, bit(31)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[31] + * PCI_E_UTL_SECONDARY_INTERRUPT + */ + (PciClockFir_1, bit(31)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[31] + * PCI_E_UTL_SECONDARY_INTERRUPT + */ + (PciClockFir_2, bit(31)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[32] + * IODA_FATAL_ERROR + */ + (PciClockFir_0, bit(32)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[32] + * IODA_FATAL_ERROR + */ + (PciClockFir_1, bit(32)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[32] + * IODA_FATAL_ERROR + */ + (PciClockFir_2, bit(32)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[33] + * IODA_MSI_PE_MISMATCH_ERROR + */ + (PciClockFir_0, bit(33)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[33] + * IODA_MSI_PE_MISMATCH_ERROR + */ + (PciClockFir_1, bit(33)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[33] + * IODA_MSI_PE_MISMATCH_ERROR + */ + (PciClockFir_2, bit(33)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[34] + * IODA_IVT_ERROR + */ + (PciClockFir_0, bit(34)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[34] + * IODA_IVT_ERROR + */ + (PciClockFir_1, bit(34)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[34] + * IODA_IVT_ERROR + */ + (PciClockFir_2, bit(34)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[35] + * IODA_TVT_ERROR + */ + (PciClockFir_0, bit(35)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[35] + * IODA_TVT_ERROR + */ + (PciClockFir_1, bit(35)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[35] + * IODA_TVT_ERROR + */ + (PciClockFir_2, bit(35)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[36] + * IODA_TVT_ADDRESS_RANGE_ERROR + */ + (PciClockFir_0, bit(36)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[36] + * IODA_TVT_ADDRESS_RANGE_ERROR + */ + (PciClockFir_1, bit(36)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[36] + * IODA_TVT_ADDRESS_RANGE_ERROR + */ + (PciClockFir_2, bit(36)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[37] + * IODA_PAGE_ACCESS_ERROR + */ + (PciClockFir_0, bit(37)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[37] + * IODA_PAGE_ACCESS_ERROR + */ + (PciClockFir_1, bit(37)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[37] + * IODA_PAGE_ACCESS_ERROR + */ + (PciClockFir_2, bit(37)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[38] + * CFG_PAPR_INJECTION_TRIGGERED + */ + (PciClockFir_0, bit(38)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[38] + * CFG_PAPR_INJECTION_TRIGGERED + */ + (PciClockFir_1, bit(38)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[38] + * CFG_PAPR_INJECTION_TRIGGERED + */ + (PciClockFir_2, bit(38)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[39] + * PAPR_INBOUND_INJECTION_ERROR_TRIGGERED + */ + (PciClockFir_0, bit(39)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[39] + * PAPR_INBOUND_INJECTION_ERROR_TRIGGERED + */ + (PciClockFir_1, bit(39)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[39] + * PAPR_INBOUND_INJECTION_ERROR_TRIGGERED + */ + (PciClockFir_2, bit(39)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[40] + * INBOUND_FATAL_ERROR + */ + (PciClockFir_0, bit(40)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[40] + * INBOUND_FATAL_ERROR + */ + (PciClockFir_1, bit(40)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[40] + * INBOUND_FATAL_ERROR + */ + (PciClockFir_2, bit(40)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[41] + * MSI_ADDRESS_ALIGNMENT_ERROR + */ + (PciClockFir_0, bit(41)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[41] + * MSI_ADDRESS_ALIGNMENT_ERROR + */ + (PciClockFir_1, bit(41)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[41] + * MSI_ADDRESS_ALIGNMENT_ERROR + */ + (PciClockFir_2, bit(41)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[42] + * INTERNAL_BAR_DISABLED_ERROR + */ + (PciClockFir_0, bit(42)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[42] + * INTERNAL_BAR_DISABLED_ERROR + */ + (PciClockFir_1, bit(42)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[42] + * INTERNAL_BAR_DISABLED_ERROR + */ + (PciClockFir_2, bit(42)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[43] + * GBIF_INBOUND_COMPLETION_DONE_ERROR + */ + (PciClockFir_0, bit(43)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[43] + * GBIF_INBOUND_COMPLETION_DONE_ERROR + */ + (PciClockFir_1, bit(43)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[43] + * GBIF_INBOUND_COMPLETION_DONE_ERROR + */ + (PciClockFir_2, bit(43)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[44] + * PCT_TIMEOUT_ERROR + */ + (PciClockFir_0, bit(44)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[44] + * PCT_TIMEOUT_ERROR + */ + (PciClockFir_1, bit(44)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[44] + * PCT_TIMEOUT_ERROR + */ + (PciClockFir_2, bit(44)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[45] + * TCE_REQUEST_TIMEOUT_ERROR + */ + (PciClockFir_0, bit(45)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[45] + * TCE_REQUEST_TIMEOUT_ERROR + */ + (PciClockFir_1, bit(45)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[45] + * TCE_REQUEST_TIMEOUT_ERROR + */ + (PciClockFir_2, bit(45)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[47] + * AIB_TX_TIMEOUT_ERROR + */ + (PciClockFir_0, bit(47)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[47] + * AIB_TX_TIMEOUT_ERROR + */ + (PciClockFir_1, bit(47)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[47] + * AIB_TX_TIMEOUT_ERROR + */ + (PciClockFir_2, bit(47)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[48] + * AIB_TX_TIMEOUT_ERROR + */ + (PciClockFir_0, bit(48)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[48] + * AIB_TX_TIMEOUT_ERROR + */ + (PciClockFir_1, bit(48)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[48] + * AIB_TX_TIMEOUT_ERROR + */ + (PciClockFir_2, bit(48)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[49] + * TCE_REQUEST_UNEXPECTED_RESPONSE_ERROR + */ + (PciClockFir_0, bit(49)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[49] + * TCE_REQUEST_UNEXPECTED_RESPONSE_ERROR + */ + (PciClockFir_1, bit(49)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[49] + * TCE_REQUEST_UNEXPECTED_RESPONSE_ERROR + */ + (PciClockFir_2, bit(49)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[50] + * INBOUND_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_0, bit(50)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[50] + * INBOUND_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_1, bit(50)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[50] + * INBOUND_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_2, bit(50)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[51] + * INBOUND_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_0, bit(51)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[51] + * INBOUND_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_1, bit(51)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[51] + * INBOUND_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_2, bit(51)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[52] + * DMA_WRITE_MSI_INTERRUPT_DATA_POISONED_ERROR + */ + (PciClockFir_0, bit(52)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[52] + * DMA_WRITE_MSI_INTERRUPT_DATA_POISONED_ERROR + */ + (PciClockFir_1, bit(52)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[52] + * DMA_WRITE_MSI_INTERRUPT_DATA_POISONED_ERROR + */ + (PciClockFir_2, bit(52)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[55] + * DL_RX_MALFORMED + */ + (PciClockFir_0, bit(55)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[55] + * DL_RX_MALFORMED + */ + (PciClockFir_1, bit(55)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[55] + * DL_RX_MALFORMED + */ + (PciClockFir_2, bit(55)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[56] + * REPLAY_BUFFER_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_0, bit(56)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[56] + * REPLAY_BUFFER_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_1, bit(56)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[56] + * REPLAY_BUFFER_ECC_CORRECTABLE_ERROR + */ + (PciClockFir_2, bit(56)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[57] + * REPLAY_BUFFER_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_0, bit(57)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[57] + * REPLAY_BUFFER_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_1, bit(57)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[57] + * REPLAY_BUFFER_ECC_UNCORRECTABLE_ERROR + */ + (PciClockFir_2, bit(57)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[58] + * AIB_DAT_ERR_INDICATION + */ + (PciClockFir_0, bit(58)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[58] + * AIB_DAT_ERR_INDICATION + */ + (PciClockFir_1, bit(58)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[58] + * AIB_DAT_ERR_INDICATION + */ + (PciClockFir_2, bit(58)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[59] + * AIB_CREDITS_ERROR + */ + (PciClockFir_0, bit(59)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[59] + * AIB_CREDITS_ERROR + */ + (PciClockFir_1, bit(59)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[59] + * AIB_CREDITS_ERROR + */ + (PciClockFir_2, bit(59)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[60] + * CFG_EC08_FATAL_ERROR + */ + (PciClockFir_0, bit(60)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[60] + * CFG_EC08_FATAL_ERROR + */ + (PciClockFir_1, bit(60)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[60] + * CFG_EC08_FATAL_ERROR + */ + (PciClockFir_2, bit(60)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[61] + * CFG_EC08_NONFATAL_ERROR + */ + (PciClockFir_0, bit(61)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[61] + * CFG_EC08_NONFATAL_ERROR + */ + (PciClockFir_1, bit(61)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[61] + * CFG_EC08_NONFATAL_ERROR + */ + (PciClockFir_2, bit(61)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[62] + * CFG_EC08_CORR_ERROR + */ + (PciClockFir_0, bit(62)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[62] + * CFG_EC08_CORR_ERROR + */ + (PciClockFir_1, bit(62)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[62] + * CFG_EC08_CORR_ERROR + */ + (PciClockFir_2, bit(62)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_0[63] + * LEM_FIR_INTERNAL_PARITY_ERROR + */ + (PciClockFir_0, bit(63)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_1[63] + * LEM_FIR_INTERNAL_PARITY_ERROR + */ + (PciClockFir_1, bit(63)) ? TBDDefaultCallout; + + /** PCICLOCKFIR_2[63] + * LEM_FIR_INTERNAL_PARITY_ERROR + */ + (PciClockFir_2, bit(63)) ? TBDDefaultCallout; +}; + +################################################################################ +# PCIE Chiplet PBFFIR +################################################################################ + +rule PbfFir +{ + CHECK_STOP: PBFFIR & ~PBFFIR_MASK & ~PBFFIR_ACT0 & ~PBFFIR_ACT1; + RECOVERABLE: PBFFIR & ~PBFFIR_MASK & ~PBFFIR_ACT0 & PBFFIR_ACT1; + SPECIAL: PBFFIR & ~PBFFIR_MASK & PBFFIR_ACT0 & ~PBFFIR_ACT1; +}; + +group gPbfFir filter singlebit +{ + /** PBFFIR[0|1|2|3] + * F0_MAILBOX_WRITTEN + */ + (PbfFir, bit(0|1|2|3)) ? TBDDefaultCallout; + + /** PBFFIR[4] + * F0_RX_DETECT + */ + (PbfFir, bit(4)) ? TBDDefaultCallout; + + /** PBFFIR[5] + * F0_LINK_TRAINING_DONE + */ + (PbfFir, bit(5)) ? TBDDefaultCallout; + + /** PBFFIR[6] + * F0LINK_TRAINED + */ + (PbfFir, bit(6)) ? TBDDefaultCallout; + + /** PBFFIR[7] + * F0LINK_FIR_ERR + */ + (PbfFir, bit(7)) ? TBDDefaultCallout; + + /** PBFFIR[8] + * F0LINK_FMR_PSR_OBS_ERR + */ + (PbfFir, bit(8)) ? TBDDefaultCallout; + + /** PBFFIR[9] + * F0LINK_FMR_COR_ERR + */ + (PbfFir, bit(9)) ? TBDDefaultCallout; + + /** PBFFIR[10] + * F0LINK_FMR_SUE_ERR + */ + (PbfFir, bit(10)) ? TBDDefaultCallout; + + /** PBFFIR[11] + * F0LINK_FMR_UNC_ERR + */ + (PbfFir, bit(11)) ? TBDDefaultCallout; + + /** PBFFIR[12] + * F0_EQ_FAILED + */ + (PbfFir, bit(12)) ? TBDDefaultCallout; + + /** PBFFIR[13] + * F0_REPLAY_THRESHOLD + */ + (PbfFir, bit(13)) ? TBDDefaultCallout; + + /** PBFFIR[14] + * F0_CRC_ERROR + */ + (PbfFir, bit(14)) ? TBDDefaultCallout; + + /** PBFFIR[15] + * F0_LOST_PACKET + */ + (PbfFir, bit(15)) ? TBDDefaultCallout; + + /** PBFFIR[16] + * F0_NAK_RECEIVED + */ + (PbfFir, bit(16)) ? TBDDefaultCallout; + + /** PBFFIR[17] + * F0_REPLAY_TIMER_ERROR + */ + (PbfFir, bit(17)) ? TBDDefaultCallout; + + /** PBFFIR[18] + * F0_RETRAIN_THRESHOLD + */ + (PbfFir, bit(18)) ? TBDDefaultCallout; + + /** PBFFIR[19] + * F0_REPLAY_NUM_RETRAIN + */ + (PbfFir, bit(19)) ? TBDDefaultCallout; + + /** PBFFIR[20] + * F0_RX_ERROR + */ + (PbfFir, bit(20)) ? TBDDefaultCallout; + + /** PBFFIR[21] + * F0_DESKEW_ERROR + */ + (PbfFir, bit(21)) ? TBDDefaultCallout; + + /** PBFFIR[22] + * F0_FRAMING_ERROR + */ + (PbfFir, bit(22)) ? TBDDefaultCallout; + + /** PBFFIR[23] + * F0_OS_RECEIVED + */ + (PbfFir, bit(23)) ? TBDDefaultCallout; + + /** PBFFIR[24] + * F0_ECC_CE_ERR + */ + (PbfFir, bit(24)) ? TBDDefaultCallout; + + /** PBFFIR[25] + * F0_ECC_UE_ERR + */ + (PbfFir, bit(25)) ? TBDDefaultCallout; + + /** PBFFIR[26] + * F0_RETRAIN_ERR + */ + (PbfFir, bit(26)) ? TBDDefaultCallout; + + /** PBFFIR[27] + * F0_TRAINING_ERR + */ + (PbfFir, bit(27)) ? TBDDefaultCallout; + + /** PBFFIR[28] + * F0_UNRECOV_ERR + */ + (PbfFir, bit(28)) ? TBDDefaultCallout; + + /** PBFFIR[29] + * F0_INTERNAL_ERR + */ + (PbfFir, bit(29)) ? TBDDefaultCallout; + + /** PBFFIR[32|33|34|35] + * F1_MAILBOX_WRITTEN + */ + (PbfFir, bit(32|33|34|35)) ? TBDDefaultCallout; + + /** PBFFIR[36] + * F1_RX_DETECT + */ + (PbfFir, bit(36)) ? TBDDefaultCallout; + + /** PBFFIR[37] + * F1_LINK_TRAINING_DONE + */ + (PbfFir, bit(37)) ? TBDDefaultCallout; + + /** PBFFIR[38] + * F1LINK_TRAINED + */ + (PbfFir, bit(38)) ? TBDDefaultCallout; + + /** PBFFIR[39] + * F1LINK_FIR_ERR + */ + (PbfFir, bit(39)) ? TBDDefaultCallout; + + /** PBFFIR[40] + * F1LINK_FMR_PSR_OBS_ERR + */ + (PbfFir, bit(40)) ? TBDDefaultCallout; + + /** PBFFIR[41] + * F1LINK_FMR_COR_ERR + */ + (PbfFir, bit(41)) ? TBDDefaultCallout; + + /** PBFFIR[42] + * F1LINK_FMR_SUE_ERR + */ + (PbfFir, bit(42)) ? TBDDefaultCallout; + + /** PBFFIR[43] + * F1LINK_FMR_UNC_ERR + */ + (PbfFir, bit(43)) ? TBDDefaultCallout; + + /** PBFFIR[44] + * F1_EQ_FAILED + */ + (PbfFir, bit(44)) ? TBDDefaultCallout; + + /** PBFFIR[45] + * F1_REPLAY_THRESHOLD + */ + (PbfFir, bit(45)) ? TBDDefaultCallout; + + /** PBFFIR[46] + * F1_CRC_ERROR + */ + (PbfFir, bit(46)) ? TBDDefaultCallout; + + /** PBFFIR[47] + * F1_LOST_PACKET + */ + (PbfFir, bit(47)) ? TBDDefaultCallout; + + /** PBFFIR[48] + * F1_NAK_RECEIVED + */ + (PbfFir, bit(48)) ? TBDDefaultCallout; + + /** PBFFIR[49] + * F1_REPLAY_TIMER_ERROR + */ + (PbfFir, bit(49)) ? TBDDefaultCallout; + + /** PBFFIR[50] + * F1_RETRAIN_THRESHOLD + */ + (PbfFir, bit(50)) ? TBDDefaultCallout; + + /** PBFFIR[51] + * F1_REPLAY_NUM_RETRAIN + */ + (PbfFir, bit(51)) ? TBDDefaultCallout; + + /** PBFFIR[52] + * F1_RX_ERROR + */ + (PbfFir, bit(52)) ? TBDDefaultCallout; + + /** PBFFIR[53] + * F1_DESKEW_ERROR + */ + (PbfFir, bit(53)) ? TBDDefaultCallout; + + /** PBFFIR[54] + * F1_FRAMING_ERROR + */ + (PbfFir, bit(54)) ? TBDDefaultCallout; + + /** PBFFIR[55] + * F1_OS_RECEIVED + */ + (PbfFir, bit(55)) ? TBDDefaultCallout; + + /** PBFFIR[56] + * F1_ECC_CE_ERR + */ + (PbfFir, bit(56)) ? TBDDefaultCallout; + + /** PBFFIR[57] + * F1_ECC_UE_ERR + */ + (PbfFir, bit(57)) ? TBDDefaultCallout; + + /** PBFFIR[58] + * F1_RETRAIN_ERR + */ + (PbfFir, bit(58)) ? TBDDefaultCallout; + + /** PBFFIR[59] + * F1_TRAINING_ERR + */ + (PbfFir, bit(59)) ? TBDDefaultCallout; + + /** PBFFIR[60] + * F1_UNRECOV_ERR + */ + (PbfFir, bit(60)) ? TBDDefaultCallout; + + /** PBFFIR[61] + * F1_INTERNAL_ERR + */ + (PbfFir, bit(61)) ? TBDDefaultCallout; +}; + +################################################################################ +# PCIE Chiplet IOPPCIFIRs +################################################################################ + +# TODO - All these FIRs should have the same bit definition. Idealy, we will +# only want to have one copy of the bit definition. Unfortuately, the +# rule code parser does not have the support for something like this. +# Maybe we can add this as a later feature. + +rule IopPciFir_0 +{ + CHECK_STOP: + IOPPCIFIR_0 & ~IOPPCIFIR_0_MASK & ~IOPPCIFIR_0_ACT0 & ~IOPPCIFIR_0_ACT1; + RECOVERABLE: + IOPPCIFIR_0 & ~IOPPCIFIR_0_MASK & ~IOPPCIFIR_0_ACT0 & IOPPCIFIR_0_ACT1; +}; + +rule IopPciFir_1 +{ + CHECK_STOP: + IOPPCIFIR_1 & ~IOPPCIFIR_1_MASK & ~IOPPCIFIR_1_ACT0 & ~IOPPCIFIR_1_ACT1; + RECOVERABLE: + IOPPCIFIR_1 & ~IOPPCIFIR_1_MASK & ~IOPPCIFIR_1_ACT0 & IOPPCIFIR_1_ACT1; +}; + +group gIopPciFir filter singlebit +{ + /** IOPPCIFIR_0[0] + * FIR_STATUS_REG_G2_PLL_CCERR_STATUS + */ + (IopPciFir_0, bit(0)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[0] + * FIR_STATUS_REG_G2_PLL_CCERR_STATUS + */ + (IopPciFir_1, bit(0)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[1] + * FIR_STATUS_REG_G3_PLL_CCERR_STATUS + */ + (IopPciFir_0, bit(1)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[1] + * FIR_STATUS_REG_G3_PLL_CCERR_STATUS + */ + (IopPciFir_1, bit(1)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[2] + * FIR_STATUS_REG_TX_A_ERR_STATUS + */ + (IopPciFir_0, bit(2)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[2] + * FIR_STATUS_REG_TX_A_ERR_STATUS + */ + (IopPciFir_1, bit(2)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[3] + * FIR_STATUS_REG_TX_B_ERR_STATUS + */ + (IopPciFir_0, bit(3)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[3] + * FIR_STATUS_REG_TX_B_ERR_STATUS + */ + (IopPciFir_1, bit(3)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[4] + * FIR_STATUS_REG_RX_A_ERR_STATUS + */ + (IopPciFir_0, bit(4)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[4] + * FIR_STATUS_REG_RX_A_ERR_STATUS + */ + (IopPciFir_1, bit(4)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[5] + * FIR_STATUS_REG_RX_B_ERR_STATUS + */ + (IopPciFir_0, bit(5)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[5] + * FIR_STATUS_REG_RX_B_ERR_STATUS + */ + (IopPciFir_1, bit(5)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[6] + * FIR_STATUS_REG_ZCAL_B_ERR_STATUS + */ + (IopPciFir_0, bit(6)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[6] + * FIR_STATUS_REG_ZCAL_B_ERR_STATUS + */ + (IopPciFir_1, bit(6)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[7] + * FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS + */ + (IopPciFir_0, bit(7)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[7] + * FIR_STATUS_REG_SCOM_FIR_PERR0_STATUS + */ + (IopPciFir_1, bit(7)) ? TBDDefaultCallout; + + /** IOPPCIFIR_0[8] + * FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS + */ + (IopPciFir_0, bit(8)) ? TBDDefaultCallout; + + /** IOPPCIFIR_1[8] + * FIR_STATUS_REG_SCOM_FIR_PERR1_STATUS + */ + (IopPciFir_1, bit(8)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to PCIE chiplet +################################################################################ + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_acts_TP.rule b/src/usr/diag/prdf/plat/pegasus/Proc_acts_TP.rule new file mode 100644 index 000000000..5c11eea98 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_acts_TP.rule @@ -0,0 +1,780 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_acts_TP.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# TP Chiplet Registers +################################################################################ + +rule TpChipletFir +{ + CHECK_STOP: + (TP_CHIPLET_CS_FIR & `1FFFF80000000000`) & ~TP_CHIPLET_FIR_MASK; + RECOVERABLE: + ((TP_CHIPLET_RE_FIR >> 2) & `1FFFF80000000000`) & ~TP_CHIPLET_FIR_MASK; +}; + +group gTpChipletFir filter singlebit +{ + /** TP_CHIPLET_FIR[3] + * Attention from TP_LFIR + */ + (TpChipletFir, bit(3)) ? analyze(gTpLFir); + + /** TP_CHIPLET_FIR[4] + * Attention from OCCFIR + */ + (TpChipletFir, bit(4)) ? analyze(gOccFir); + + /** TP_CHIPLET_FIR[5] + * Attention from MCIFIR (MCS 00 Venice only) + */ + (TpChipletFir, bit(5)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[6] + * Attention from MCIFIR (MCS 01 Venice only) + */ + (TpChipletFir, bit(6)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[7] + * Attention from MCIFIR (MCS 10 Venice only) + */ + (TpChipletFir, bit(7)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[8] + * Attention from MCIFIR (MCS 11 Venice only) + */ + (TpChipletFir, bit(8)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[9] + * Attention from MCIFIR (MCS 20) + */ + (TpChipletFir, bit(9)) ? analyzeMcs20; + + /** TP_CHIPLET_FIR[10] + * Attention from MCIFIR (MCS 21) + */ + (TpChipletFir, bit(10)) ? analyzeMcs21; + + /** TP_CHIPLET_FIR[11] + * Attention from MCIFIR (MCS 30) + */ + (TpChipletFir, bit(11)) ? analyzeMcs30; + + /** TP_CHIPLET_FIR[12] + * Attention from MCIFIR (MCS 31) + */ + (TpChipletFir, bit(12)) ? analyzeMcs31; + + /** TP_CHIPLET_FIR[13] + * Attention from IOMCFIR_1 (Venice only) + */ + (TpChipletFir, bit(13)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[14] + * Attention from IOMCFIR_1 + */ + (TpChipletFir, bit(14)) ? analyze(gIomcFir_1); + + /** TP_CHIPLET_FIR[15] + * Attention from PBAMFIR + */ + (TpChipletFir, bit(15)) ? analyze(gPbamFir); + + /** TP_CHIPLET_FIR[16|17|18|19] + * Attention from CS from MC 0-3 + */ + (TpChipletFir, bit(16|17|18|19)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[20] + * Attention from PMCFIR + */ + (TpChipletFir, bit(20)) ? analyze(gPmcFir); +}; + +rule TpChipletSpa +{ + SPECIAL: TP_CHIPLET_SPA & ~TP_CHIPLET_SPA_MASK; +}; + +group gTpChipletSpa filter singlebit +{ + /** TP_CHIPLET_FIR[0] + * Attention from OCCFIR + */ + (TpChipletSpa, bit(0)) ? analyze(gOccFir); + + /** TP_CHIPLET_FIR[1] + * Attention from MCIFIR_00 (Venice only) + */ + (TpChipletSpa, bit(1)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[2] + * Attention from MCIFIR_01 (Venice only) + */ + (TpChipletSpa, bit(2)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[3] + * Attention from MCIFIR_10 (Venice only) + */ + (TpChipletSpa, bit(3)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[4] + * Attention from MCIFIR_10 (Venice only) + */ + (TpChipletSpa, bit(4)) ? defaultMaskedError; + + /** TP_CHIPLET_FIR[5] + * Attention from MCIFIR_20 + */ + (TpChipletSpa, bit(5)) ? analyzeMcs20; + + /** TP_CHIPLET_FIR[6] + * Attention from MCIFIR_21 + */ + (TpChipletSpa, bit(6)) ? analyzeMcs21; + + /** TP_CHIPLET_FIR[7] + * Attention from MCIFIR_30 + */ + (TpChipletSpa, bit(7)) ? analyzeMcs30; + + /** TP_CHIPLET_FIR[8] + * Attention from MCIFIR_31 + */ + (TpChipletSpa, bit(8)) ? analyzeMcs31; +}; + +################################################################################ +# TP Chiplet LFIR +################################################################################ + +rule TpLFir +{ + CHECK_STOP: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & ~TP_LFIR_ACT1; + RECOVERABLE: TP_LFIR & ~TP_LFIR_MASK & ~TP_LFIR_ACT0 & TP_LFIR_ACT1; +}; + +group gTpLFir filter singlebit +{ + /** TP_LFIR[0] + * CFIR internal parity error + */ + (TpLFir, bit(0)) ? TBDDefaultCallout; + + /** TP_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (TpLFir, bit(1)) ? TBDDefaultCallout; + + /** TP_LFIR[2] + * Local errors from CC (PCB error) + */ + (TpLFir, bit(2)) ? TBDDefaultCallout; + + /** TP_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (TpLFir, bit(3)) ? TBDDefaultCallout; + + /** TP_LFIR[4] + * Local errors from PSC (PCB error) + */ + (TpLFir, bit(4)) ? TBDDefaultCallout; + + /** TP_LFIR[5] + * Local errors from PSC (parity error) + */ + (TpLFir, bit(5)) ? TBDDefaultCallout; + + /** TP_LFIR[6] + * Local errors from Thermal (parity error) + */ + (TpLFir, bit(6)) ? TBDDefaultCallout; + + /** TP_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (TpLFir, bit(7)) ? TBDDefaultCallout; + + /** TP_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (TpLFir, bit(8|9)) ? TBDDefaultCallout; + + /** TP_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (TpLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# TP Chiplet OCCFIR +################################################################################ + +rule OccFir +{ + CHECK_STOP: OCCFIR & ~OCCFIR_MASK & ~OCCFIR_ACT0 & ~OCCFIR_ACT1; + RECOVERABLE: OCCFIR & ~OCCFIR_MASK & ~OCCFIR_ACT0 & OCCFIR_ACT1; + SPECIAL: OCCFIR & ~OCCFIR_MASK & OCCFIR_ACT0 & ~OCCFIR_ACT1; +}; + +group gOccFir filter singlebit +{ + /** OCCFIR[0] + * OCC_SCOM_OCCFIR_OCC_FW0 + */ + (OccFir, bit(0)) ? TBDDefaultCallout; + + /** OCCFIR[1] + * OCC_SCOM_OCCFIR_OCC_FW1 + */ + (OccFir, bit(1)) ? TBDDefaultCallout; + + /** OCCFIR[2] + * OCC_SCOM_OCCFIR_OCC_FW2 + */ + (OccFir, bit(2)) ? TBDDefaultCallout; + + /** OCCFIR[3] + * OCC_SCOM_OCCFIR_OCC_FW3 + */ + (OccFir, bit(3)) ? TBDDefaultCallout; + + /** OCCFIR[4] + * OCC_SCOM_OCCFIR_PMC_PORE_SW_MALF + */ + (OccFir, bit(4)) ? TBDDefaultCallout; + + /** OCCFIR[5] + * OCC_SCOM_OCCFIR_PMC_OCC_HB_MALF + */ + (OccFir, bit(5)) ? TBDDefaultCallout; + + /** OCCFIR[6] + * OCC_SCOM_OCCFIR_PORE_GPE0_FATAL_ERR + */ + (OccFir, bit(6)) ? TBDDefaultCallout; + + /** OCCFIR[7] + * OCC_SCOM_OCCFIR_PORE_GPE1_FATAL_ERR + */ + (OccFir, bit(7)) ? TBDDefaultCallout; + + /** OCCFIR[8] + * OCC_SCOM_OCCFIR_OCB_ERROR + */ + (OccFir, bit(8)) ? TBDDefaultCallout; + + /** OCCFIR[9] + * OCC_SCOM_OCCFIR_SRT_UE + */ + (OccFir, bit(9)) ? TBDDefaultCallout; + + /** OCCFIR[10] + * OCC_SCOM_OCCFIR_SRT_CE + */ + (OccFir, bit(10)) ? TBDDefaultCallout; + + /** OCCFIR[11] + * OCC_SCOM_OCCFIR_SRT_READ_ERROR + */ + (OccFir, bit(11)) ? TBDDefaultCallout; + + /** OCCFIR[12] + * OCC_SCOM_OCCFIR_SRT_WRITE_ERROR + */ + (OccFir, bit(12)) ? TBDDefaultCallout; + + /** OCCFIR[13] + * OCC_SCOM_OCCFIR_SRT_DATAOUT_PERR + */ + (OccFir, bit(13)) ? TBDDefaultCallout; + + /** OCCFIR[14] + * OCC_SCOM_OCCFIR_SRT_OCI_WRITE_DATA_PARITY + */ + (OccFir, bit(14)) ? TBDDefaultCallout; + + /** OCCFIR[15] + * OCC_SCOM_OCCFIR_SRT_OCI_BE_PARITY_ER + */ + (OccFir, bit(15)) ? TBDDefaultCallout; + + /** OCCFIR[16] + * OCC_SCOM_OCCFIR_SRT_OCI_ADDR_PARITY_ERR + */ + (OccFir, bit(16)) ? TBDDefaultCallout; + + /** OCCFIR[17] + * OCC_SCOM_OCCFIR_PORE_SW_ERROR_ERR + */ + (OccFir, bit(17)) ? TBDDefaultCallout; + + /** OCCFIR[18] + *OCC_SCOM_OCCFIR_PORE_GPE0_ERROR_ERR + */ + (OccFir, bit(18)) ? TBDDefaultCallout; + + /** OCCFIR[19] + * OCC_SCOM_OCCFIR_PORE_GPE1_ERROR_ERR + */ + (OccFir, bit(19)) ? TBDDefaultCallout; + + /** OCCFIR[20] + * OCC_SCOM_OCCFIR_EXTERNAL_TRAP + */ + (OccFir, bit(20)) ? TBDDefaultCallout; + + /** OCCFIR[21] + * OCC_SCOM_OCCFIR_PPC405_CORE_RESET + */ + (OccFir, bit(21)) ? TBDDefaultCallout; + + /** OCCFIR[22] + * OCC_SCOM_OCCFIR_PPC405_CHIP_RESET + */ + (OccFir, bit(22)) ? TBDDefaultCallout; + + /** OCCFIR[23] + * OCC_SCOM_OCCFIR_PPC405_SYSTEM_RESET + */ + (OccFir, bit(23)) ? TBDDefaultCallout; + + /** OCCFIR[24] + *OCC_SCOM_OCCFIR_PPC405_DBGMSRWE + */ + (OccFir, bit(24)) ? TBDDefaultCallout; + + /** OCCFIR[25] + * OCC_SCOM_OCCFIR_PPC405_DBGSTOPACK + */ + (OccFir, bit(25)) ? TBDDefaultCallout; + + /** OCCFIR[26] + * OCC_SCOM_OCCFIR_OCB_DB_OCI_TIMEOUT + */ + (OccFir, bit(26)) ? TBDDefaultCallout; + + /** OCCFIR[27] + * OCC_SCOM_OCCFIR_OCB_DB_OCI_READ_DATA_PARITY + */ + (OccFir, bit(27)) ? TBDDefaultCallout; + + /** OCCFIR[28] + * OCC_SCOM_OCCFIR_OCB_DB_OCI_SLAVE_ERROR + */ + (OccFir, bit(28)) ? TBDDefaultCallout; + + /** OCCFIR[29] + * OCC_SCOM_OCCFIR_OCB_PIB_ADDR_PARITY_ERR + */ + (OccFir, bit(29)) ? TBDDefaultCallout; + + /** OCCFIR[30] + * OCC_SCOM_OCCFIR_OCB_DB_PIB_DATA_PARITY_ERR + */ + (OccFir, bit(30)) ? TBDDefaultCallout; + + /** OCCFIR[31] + * OCC_SCOM_OCCFIR_OCB_IDC0_ERROR + */ + (OccFir, bit(31)) ? TBDDefaultCallout; + + /** OCCFIR[32] + * OCC_SCOM_OCCFIR_OCB_IDC1_ERROR + */ + (OccFir, bit(32)) ? TBDDefaultCallout; + + /** OCCFIR[33] + * OCC_SCOM_OCCFIR_OCB_IDC2_ERROR + */ + (OccFir, bit(33)) ? TBDDefaultCallout; + + /** OCCFIR[34] + * OCC_SCOM_OCCFIR_OCB_IDC3_ERROR + */ + (OccFir, bit(34)) ? TBDDefaultCallout; + + /** OCCFIR[35] + * OCC_SCOM_OCCFIR_SRT_FSM_ERR + */ + (OccFir, bit(35)) ? TBDDefaultCallout; + + /** OCCFIR[36] + * OCC_SCOM_OCCFIR_JTAGACC_ERR + */ + (OccFir, bit(36)) ? TBDDefaultCallout; + + /** OCCFIR[37] + * OCC_SCOM_OCCFIR_OCB_DW_ERR + */ + (OccFir, bit(37)) ? TBDDefaultCallout; + + /** OCCFIR[38] + * OCC_SCOM_OCCFIR_C405_ECC_UE + */ + (OccFir, bit(38)) ? TBDDefaultCallout; + + /** OCCFIR[39] + * OCC_SCOM_OCCFIR_C405_ECC_CE + */ + (OccFir, bit(39)) ? TBDDefaultCallout; + + /** OCCFIR[40] + * OCC_SCOM_OCCFIR_C405_OCI_MACHINECHECK + */ + (OccFir, bit(40)) ? TBDDefaultCallout; + + /** OCCFIR[41] + * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR0 + */ + (OccFir, bit(41)) ? TBDDefaultCallout; + + /** OCCFIR[42] + * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR1 + */ + (OccFir, bit(42)) ? TBDDefaultCallout; + + /** OCCFIR[43] + * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR2 + */ + (OccFir, bit(43)) ? TBDDefaultCallout; + + /** OCCFIR[44] + * OCC_SCOM_OCCFIR_SRAM_SPARE_DIRECT_ERROR3 + */ + (OccFir, bit(44)) ? TBDDefaultCallout; + + /** OCCFIR[45] + * OCC_SCOM_OCCFIR_SLW_OCISLV_ERR + */ + (OccFir, bit(45)) ? TBDDefaultCallout; + + /** OCCFIR[46] + * OCC_SCOM_OCCFIR_GPE_OCISLV_ERR + */ + (OccFir, bit(46)) ? TBDDefaultCallout; + + /** OCCFIR[47] + * OCC_SCOM_OCCFIR_OCB_OCISLV_ERR + */ + (OccFir, bit(47)) ? TBDDefaultCallout; + + /** OCCFIR[48] + * OCC_SCOM_OCCFIR_C405ICU_M_TIMEOUT + */ + (OccFir, bit(48)) ? TBDDefaultCallout; + + /** OCCFIR[49] + * OCC_SCOM_OCCFIR_C405DCU_M_TIMEOUT + */ + (OccFir, bit(49)) ? TBDDefaultCallout; + + /** OCCFIR[62|63] + * OCC_SCOM_OCCFIR_FIR_PARITY_ERR_DUP + */ + (OccFir, bit(62|63)) ? TBDDefaultCallout; +}; + +################################################################################ +# TP Chiplet PBAMFIR +################################################################################ + +rule PbamFir +{ + CHECK_STOP: PBAMFIR & ~PBAMFIR_MASK & ~PBAMFIR_ACT0 & ~PBAMFIR_ACT1; + RECOVERABLE: PBAMFIR & ~PBAMFIR_MASK & ~PBAMFIR_ACT0 & PBAMFIR_ACT1; +}; + +group gPbamFir filter singlebit +{ + /** PBAMFIR[0] + * INVALID_TRANSFER_SIZE + */ + (PbamFir, bit(0)) ? TBDDefaultCallout; + + /** PBAMFIR[1] + * INVALID_COMMAND + */ + (PbamFir, bit(1)) ? TBDDefaultCallout; + + /** PBAMFIR[2] + * INVALID_ADDRESS_ALIGNMENT + */ + (PbamFir, bit(2)) ? TBDDefaultCallout; + + /** PBAMFIR[3] + * OPB_ERROR + */ + (PbamFir, bit(3)) ? TBDDefaultCallout; + + /** PBAMFIR[4] + * OPB_TIMEOUT + */ + (PbamFir, bit(4)) ? TBDDefaultCallout; + + /** PBAMFIR[5] + * OPB_MASTER_HANG_TIMEOUT + */ + (PbamFir, bit(5)) ? TBDDefaultCallout; + + /** PBAMFIR[6] + * CMD_BUFFER_PAR_ERR + */ + (PbamFir, bit(6)) ? TBDDefaultCallout; + + /** PBAMFIR[7] + * DAT_BUFFER_PAR_ERR + */ + (PbamFir, bit(7)) ? TBDDefaultCallout; + + /** PBAMFIR[10] + * FIR_PARITY_ERR2 + */ + (PbamFir, bit(10)) ? TBDDefaultCallout; + + /** PBAMFIR[11] + * FIR_PARITY_ERR + */ + (PbamFir, bit(11)) ? TBDDefaultCallout; +}; + +################################################################################ +# TP Chiplet PMCFIR +################################################################################ + +rule PmcFir +{ + CHECK_STOP: PMCFIR & ~PMCFIR_MASK & ~PMCFIR_ACT0 & ~PMCFIR_ACT1; + RECOVERABLE: PMCFIR & ~PMCFIR_MASK & ~PMCFIR_ACT0 & PMCFIR_ACT1; +}; + +group gPmcFir filter singlebit +{ + /** PMCFIR[0] + * LFIR_PSTATE_OCI_MASTER_RDERR + */ + (PmcFir, bit(0)) ? TBDDefaultCallout; + + /** PMCFIR[1] + * LFIR_PSTATE_OCI_MASTER_RDDATA_PARITY_ERR + */ + (PmcFir, bit(1)) ? TBDDefaultCallout; + + /** PMCFIR[2] + * LFIR_PSTATE_GPST_CHECKBYTE_ERR + */ + (PmcFir, bit(2)) ? TBDDefaultCallout; + + /** PMCFIR[3] + * LFIR_PSTATE_GACK_TO_ERR + */ + (PmcFir, bit(3)) ? TBDDefaultCallout; + + /** PMCFIR[4] + * LFIR_PSTATE_PIB_MASTER_NONOFFLINE_ERR + */ + (PmcFir, bit(4)) ? TBDDefaultCallout; + + /** PMCFIR[5] + * LFIR_PSTATE_PIB_MASTER_OFFLINE_ERR + */ + (PmcFir, bit(5)) ? TBDDefaultCallout; + + /** PMCFIR[6] + * LFIR_PSTATE_OCI_MASTER_TO_ERR + */ + (PmcFir, bit(6)) ? TBDDefaultCallout; + + /** PMCFIR[7] + * LFIR_PSTATE_INTERCHIP_UE_ERR + */ + (PmcFir, bit(7)) ? TBDDefaultCallout; + + /** PMCFIR[8] + * LFIR_PSTATE_INTERCHIP_ERRORFRAME_ERR + */ + (PmcFir, bit(8)) ? TBDDefaultCallout; + + /** PMCFIR[9] + * LFIR_PSTATE_MS_FSM_ERR + */ + (PmcFir, bit(9)) ? TBDDefaultCallout; + + /** PMCFIR[10] + * LFIR_MS_COMP_PARITY_ERR + */ + (PmcFir, bit(10)) ? TBDDefaultCallout; + + /** PMCFIR[11] + * LFIR_IDLE_PORESW_FATAL_ERR + */ + (PmcFir, bit(11)) ? TBDDefaultCallout; + + /** PMCFIR[12] + * LFIR_IDLE_PORESW_STATUS_RC_ERR + */ + (PmcFir, bit(12)) ? TBDDefaultCallout; + + /** PMCFIR[13] + * LFIR_IDLE_PORESW_STATUS_VALUE_ERR + */ + (PmcFir, bit(13)) ? TBDDefaultCallout; + + /** PMCFIR[14] + * LFIR_IDLE_PORESW_WRITE_WHILE_INACTIVE_ERR + */ + (PmcFir, bit(14)) ? TBDDefaultCallout; + + /** PMCFIR[15] + * LFIR_IDLE_PORESW_TIMEOUT_ERR + */ + (PmcFir, bit(15)) ? TBDDefaultCallout; + + /** PMCFIR[16] + * LFIR_IDLE_OCI_MASTER_WRITE_TIMEOUT_ERR + */ + (PmcFir, bit(16)) ? TBDDefaultCallout; + + /** PMCFIR[17] + * LFIR_IDLE_INTERNAL_ERR + */ + (PmcFir, bit(17)) ? TBDDefaultCallout; + + /** PMCFIR[18] + * LFIR_INT_COMP_PARITY_ERR + */ + (PmcFir, bit(18)) ? TBDDefaultCallout; + + /** PMCFIR[19] + * LFIR_PMC_OCC_HEARTBEAT_TIMEOUT + */ + (PmcFir, bit(19)) ? TBDDefaultCallout; + + /** PMCFIR[20] + * LFIR_SPIVID_CRC_ERROR0 + */ + (PmcFir, bit(20)) ? TBDDefaultCallout; + + /** PMCFIR[21] + * LFIR_SPIVID_CRC_ERROR1 + */ + (PmcFir, bit(21)) ? TBDDefaultCallout; + + /** PMCFIR[22] + * LFIR_SPIVID_CRC_ERROR2 + */ + (PmcFir, bit(22)) ? TBDDefaultCallout; + + /** PMCFIR[23] + * LFIR_SPIVID_RETRY_TIMEOUT + */ + (PmcFir, bit(23)) ? TBDDefaultCallout; + + /** PMCFIR[24] + * LFIR_SPIVID_FSM_ERR + */ + (PmcFir, bit(24)) ? TBDDefaultCallout; + + /** PMCFIR[25] + * LFIR_SPIVID_MAJORITY_DETECTED_A_MINORITY + */ + (PmcFir, bit(25)) ? TBDDefaultCallout; + + /** PMCFIR[26] + * LFIR_O2S_CRC_ERROR0 + */ + (PmcFir, bit(26)) ? TBDDefaultCallout; + + /** PMCFIR[27] + * LFIR_O2S_CRC_ERROR1 + */ + (PmcFir, bit(27)) ? TBDDefaultCallout; + + /** PMCFIR[28] + *LFIR_O2S_CRC_ERROR1 + */ + (PmcFir, bit(28)) ? TBDDefaultCallout; + + /** PMCFIR[29] + * LFIR_O2S_RETRY_TIMEOUT + */ + (PmcFir, bit(29)) ? TBDDefaultCallout; + + /** PMCFIR[30] + * LFIR_O2S_WRITE_WHILE_BRIDGE_BUSY_ERR + */ + (PmcFir, bit(30)) ? TBDDefaultCallout; + + /** PMCFIR[31] + * LFIR_O2S_FSM_ERR + */ + (PmcFir, bit(31)) ? TBDDefaultCallout; + + /** PMCFIR[32] + * LFIR_O2S_MAJORITY_DETECTED_A_MINORITY + */ + (PmcFir, bit(32)) ? TBDDefaultCallout; + + /** PMCFIR[33] + * LFIR_O2P_WRITE_WHILE_BRIDGE_BUSY_ERR + */ + (PmcFir, bit(33)) ? TBDDefaultCallout; + + /** PMCFIR[34] + * LFIR_O2P_FSM_ERR + */ + (PmcFir, bit(34)) ? TBDDefaultCallout; + + /** PMCFIR[35] + * LFIR_OCI_SLAVE_ERR + */ + (PmcFir, bit(35)) ? TBDDefaultCallout; + + /** PMCFIR[36] + * LFIR_IF_COMP_PARITY_ERROR + */ + (PmcFir, bit(36)) ? TBDDefaultCallout; + + /** PMCFIR[47|48] + * FIR_PARITY_ERR + */ + (PmcFir, bit(47|48)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to TP chiplet +################################################################################ + +/** Analyze connected MCS 20 */ +actionclass analyzeMcs20 { analyze(connected(TYPE_MCS, 4)); }; + +/** Analyze connected MCS 21 */ +actionclass analyzeMcs21 { analyze(connected(TYPE_MCS, 5)); }; + +/** Analyze connected MCS 30 */ +actionclass analyzeMcs30 { analyze(connected(TYPE_MCS, 6)); }; + +/** Analyze connected MCS 31 */ +actionclass analyzeMcs31 { analyze(connected(TYPE_MCS, 7)); }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_acts_XBUS.rule b/src/usr/diag/prdf/plat/pegasus/Proc_acts_XBUS.rule new file mode 100644 index 000000000..d5bb006a0 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_acts_XBUS.rule @@ -0,0 +1,276 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_acts_XBUS.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + +################################################################################ +# XBUS Chiplet Registers +################################################################################ + +rule XbusChipletFir +{ + CHECK_STOP: + (XBUS_CHIPLET_CS_FIR & `1F90000000000000`) & ~XBUS_CHIPLET_FIR_MASK; + RECOVERABLE: + ((XBUS_CHIPLET_RE_FIR >> 2) & `1F90000000000000`) & ~XBUS_CHIPLET_FIR_MASK; +}; + +group gXbusChipletFir filter singlebit +{ + /** XbusChipletFir[3] + * Attention from LFIR + */ + (XbusChipletFir, bit(3)) ? analyze(gXbusLFir); + + /** XbusChipletFir[4] + * Attention from PBENFIR + */ + (XbusChipletFir, bit(4)) ? analyze(gPbenFir); + + /** XbusChipletFir[5] + * Attention from IOXFIR_0 (Venice only) + */ + (XbusChipletFir, bit(5)) ? defaultMaskedError; + + /** XbusChipletFir[6] + * Attention from IOXFIR_1 + */ + (XbusChipletFir, bit(6)) ? analyze(gIoxFir_1); + + /** XbusChipletFir[7] + * Attention from IOXFIR_2 (Venice only) + */ + (XbusChipletFir, bit(7)) ? defaultMaskedError; + + /** XbusChipletFir[8] + * Attention from IOXFIR_3 (Venice only) + */ + (XbusChipletFir, bit(8)) ? defaultMaskedError; +}; + +################################################################################ +# XBUS Chiplet LFIR +################################################################################ + +rule XbusLFir +{ + CHECK_STOP: XBUS_LFIR & ~XBUS_LFIR_MASK & ~XBUS_LFIR_ACT0 & ~XBUS_LFIR_ACT1; + RECOVERABLE: XBUS_LFIR & ~XBUS_LFIR_MASK & ~XBUS_LFIR_ACT0 & XBUS_LFIR_ACT1; +}; + +group gXbusLFir filter singlebit +{ + /** XBUS_LFIR[0] + * CFIR internal parity error + */ + (XbusLFir, bit(0)) ? TBDDefaultCallout; + + /** XBUS_LFIR[1] + * Local errors from GPIO (PCB error) + */ + (XbusLFir, bit(1)) ? TBDDefaultCallout; + + /** XBUS_LFIR[2] + * Local errors from CC (PCB error) + */ + (XbusLFir, bit(2)) ? TBDDefaultCallout; + + /** XBUS_LFIR[3] + * Local errors from CC (OPCG, parity, scan collision, ...) + */ + (XbusLFir, bit(3)) ? TBDDefaultCallout; + + /** XBUS_LFIR[4] + * Local errors from PSC (PCB error) + */ + (XbusLFir, bit(4)) ? TBDDefaultCallout; + + /** XBUS_LFIR[5] + * Local errors from PSC (parity error) + */ + (XbusLFir, bit(5)) ? TBDDefaultCallout; + + /** XBUS_LFIR[6] + * Local errors from Thermal (parity error) + */ + (XbusLFir, bit(6)) ? TBDDefaultCallout; + + /** XBUS_LFIR[7] + * Local errors from Thermal (PCB error) + */ + (XbusLFir, bit(7)) ? TBDDefaultCallout; + + /** XBUS_LFIR[8|9] + * Local errors from Thermal (Trip error) + */ + (XbusLFir, bit(8|9)) ? TBDDefaultCallout; + + /** XBUS_LFIR[10|11] + * Local errors from Trace Array ( error) + */ + (XbusLFir, bit(10|11)) ? TBDDefaultCallout; +}; + +################################################################################ +# XBUS Chiplet PBENFIR +################################################################################ + +rule PbenFir +{ + CHECK_STOP: PBENFIR & ~PBENFIR_MASK & ~PBENFIR_ACT0 & ~PBENFIR_ACT1; + RECOVERABLE: PBENFIR & ~PBENFIR_MASK & ~PBENFIR_ACT0 & PBENFIR_ACT1; +}; + +group gPbenFir filter singlebit +{ + /** PBENFIR[0] + * X0_LINK_RCV_CE: x0 link rcv ce + */ + (PbenFir, bit(0)) ? TBDDefaultCallout; + + /** PBENFIR[1] + * X0_LINK_RCV_DERR: x0 link rcv derr + */ + (PbenFir, bit(1)) ? TBDDefaultCallout; + + /** PBENFIR[2] + * X0_LINK_RCV_UE: x0 link rcv ue + */ + (PbenFir, bit(2)) ? TBDDefaultCallout; + + /** PBENFIR[3] + * X1_LINK_RCV_CE: x1 link rcv ce + */ + (PbenFir, bit(3)) ? TBDDefaultCallout; + + /** PBENFIR[4] + * X1_LINK_RCV_DERR: x1 link rcv derr + */ + (PbenFir, bit(4)) ? TBDDefaultCallout; + + /** PBENFIR[5] + * X1_LINK_RCV_UE: x1 link rcv ue + */ + (PbenFir, bit(5)) ? TBDDefaultCallout; + + /** PBENFIR[6] + * X2_LINK_RCV_CE: x2 link rcv ce + */ + (PbenFir, bit(6)) ? TBDDefaultCallout; + + /** PBENFIR[7] + * X2_LINK_RCV_DERR: x2 link rcv derr + */ + (PbenFir, bit(7)) ? TBDDefaultCallout; + + /** PBENFIR[8] + * X2_LINK_RCV_UE: x2 link rcv ue + */ + (PbenFir, bit(8)) ? TBDDefaultCallout; + + /** PBENFIR[9] + * X3_LINK_RCV_CE: x3 link rcv ce + */ + (PbenFir, bit(9)) ? TBDDefaultCallout; + + /** PBENFIR[10] + * X3_LINK_RCV_DERR: x3 link rcv derr + */ + (PbenFir, bit(10)) ? TBDDefaultCallout; + + /** PBENFIR[11] + * X3_LINK_RCV_UE: x3 link rcv ue + */ + (PbenFir, bit(11)) ? TBDDefaultCallout; + + /** PBENFIR[12] + * X_LINK_SND_CE: x link rcv ce + */ + (PbenFir, bit(12)) ? TBDDefaultCallout; + + /** PBENFIR[13] + * X_LINK_SND_SUE: x link rcv sue + */ + (PbenFir, bit(13)) ? TBDDefaultCallout; + + /** PBENFIR[14] + * X_LINK_SND_UE: x link rcv ue + */ + (PbenFir, bit(14)) ? TBDDefaultCallout; + + /** PBENFIR[15] + * X_LINK_CR_OVERFLOW: x link command/response/data buffer overflow + */ + (PbenFir, bit(15)) ? TBDDefaultCallout; + + /** PBENFIR[16] + * X0_LINK_FMR_ERR: x0 link framer error + */ + (PbenFir, bit(16)) ? TBDDefaultCallout; + + /** PBENFIR[17] + * X1_LINK_FMR_ERR: x1 link framer error + */ + (PbenFir, bit(17)) ? TBDDefaultCallout; + + /** PBENFIR[18] + * X2_LINK_FMR_ERR: x2 link framer error + */ + (PbenFir, bit(18)) ? TBDDefaultCallout; + + /** PBENFIR[19] + * X3_LINK_FMR_ERR: x3 link framer error + */ + (PbenFir, bit(19)) ? TBDDefaultCallout; + + /** PBENFIR[20] + * X_LINK_PSR_ERR: x link parser error + */ + (PbenFir, bit(20)) ? TBDDefaultCallout; + + /** PBENFIR[36] + * FIR_SCOM_ERR: pben iox fir_scom_err + */ + (PbenFir, bit(36)) ? TBDDefaultCallout; +}; + +################################################################################ +# XBUS Chiplet IOXFIR_1 +################################################################################ + +rule IoxFir_1 +{ + CHECK_STOP: IOXFIR_1 & ~IOXFIR_1_MASK & ~IOXFIR_1_ACT0 & ~IOXFIR_1_ACT1; + RECOVERABLE: IOXFIR_1 & ~IOXFIR_1_MASK & ~IOXFIR_1_ACT0 & IOXFIR_1_ACT1; +}; + +group gIoxFir_1 filter singlebit +{ + /** IOXFIR_1[0] + * TBD + */ + (IoxFir_1, bit(0)) ? TBDDefaultCallout; +}; + +################################################################################ +# Actions specific to XBUS chiplet +################################################################################ + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_regs_ABUS.rule b/src/usr/diag/prdf/plat/pegasus/Proc_regs_ABUS.rule new file mode 100644 index 000000000..8a0521daa --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_regs_ABUS.rule @@ -0,0 +1,160 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_regs_ABUS.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # ABUS Chiplet Registers + ############################################################################ + + register ABUS_CHIPLET_CS_FIR + { + name "ES.PBES_WRAP_TOP.TPC.XFIR"; + scomaddr 0x08040000; + capture group default; + }; + + register ABUS_CHIPLET_RE_FIR + { + name "ES.PBES_WRAP_TOP.TPC.RFIR"; + scomaddr 0x08040001; + capture group default; + }; + + register ABUS_CHIPLET_FIR_MASK + { + name "ES.PBES_WRAP_TOP.TPC.FIR_MASK"; + scomaddr 0x08040002; + capture type secondary; + capture group default; + }; + + ############################################################################ + # ABUS Chiplet LFIR + ############################################################################ + + register ABUS_LFIR + { + name "ES.PBES_WRAP_TOP.TPC.LOCAL_FIR"; + scomaddr 0x0804000a; + reset (&, 0x0804000b); + mask (|, 0x0804000f); + capture group default; + }; + + register ABUS_LFIR_MASK + { + name "ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0804000d; + capture type secondary; + capture group default; + }; + + register ABUS_LFIR_ACT0 + { + name "ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x08040010; + capture type secondary; + capture group default; + }; + + register ABUS_LFIR_ACT1 + { + name "ES.PBES_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x08040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # ABUS Chiplet PBESFIR + ############################################################################ + + register PBESFIR + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_REG"; + scomaddr 0x08010800; + reset (&, 0x08010801); + mask (|, 0x08010805); + capture group default; + }; + + register PBESFIR_MASK + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_MASK_REG"; + scomaddr 0x08010803; + capture type secondary; + capture group default; + }; + + register PBESFIR_ACT0 + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION0_REG"; + scomaddr 0x08010806; + capture type secondary; + capture group default; + }; + + register PBESFIR_ACT1 + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IO.SCOM.PB_IOA_FIR_ACTION1_REG"; + scomaddr 0x08010807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # ABUS Chiplet IOAFIR + ############################################################################ + + register IOAFIR + { + name "ABUS.BUSCTL.SCOM.FIR_REG"; + scomaddr 0x08010c00; + reset (&, 0x08010c01); + mask (|, 0x08010c05); + capture group default; + }; + + register IOAFIR_MASK + { + name "ABUS.BUSCTL.SCOM.FIR_MASK_REG"; + scomaddr 0x08010c03; + capture type secondary; + capture group default; + }; + + register IOAFIR_ACT0 + { + name "ABUS.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x08010c06; + capture type secondary; + capture group default; + }; + + register IOAFIR_ACT1 + { + name "ABUS.BUSCTL.SCOM.FIR_ACTION1_REG"; + scomaddr 0x08010c07; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_regs_PB.rule b/src/usr/diag/prdf/plat/pegasus/Proc_regs_PB.rule new file mode 100644 index 000000000..0e24ce898 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_regs_PB.rule @@ -0,0 +1,754 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_regs_PB.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # PB Chiplet Registers + ############################################################################ + + register PB_CHIPLET_CS_FIR + { + name "EH.TPC.XFIR"; + scomaddr 0x02040000; + capture group default; + }; + + register PB_CHIPLET_RE_FIR + { + name "EH.TPC.RFIR"; + scomaddr 0x02040001; + capture group default; + }; + + register PB_CHIPLET_FIR_MASK + { + name "EH.TPC.FIR_MASK"; + scomaddr 0x02040002; + capture type secondary; + capture group default; + }; + + register PB_CHIPLET_SPA + { + name "EH.TPC.EPS.FIR.SPATTN"; + scomaddr 0x02040004; + capture group default; + }; + + register PB_CHIPLET_SPA_MASK + { + name "EH.TPC.EPS.FIR.SPA_MASK"; + scomaddr 0x02040007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet LFIR + ############################################################################ + + register PB_LFIR + { + name "EH.TPC.LOCAL_FIR"; + scomaddr 0x0204000a; + reset (&, 0x0204000b); + mask (|, 0x0204000f); + capture group default; + }; + + register PB_LFIR_MASK + { + name "EH.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0204000d; + capture type secondary; + capture group default; + }; + + register PB_LFIR_ACT0 + { + name "EH.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x02040010; + capture type secondary; + capture group default; + }; + + register PB_LFIR_ACT1 + { + name "EH.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x02040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet NXDMAENGFIR + ############################################################################ + + register NXDMAENGFIR + { + name "EN.NX.DBG.NX_DMA_ENG_FIR"; + scomaddr 0x02013100; + reset (&, 0x02013101); + mask (|, 0x02013105); + capture group default; + }; + + register NXDMAENGFIR_MASK + { + name "EN.NX.DBG.NX_DMA_ENG_FIR_MASK"; + scomaddr 0x02013103; + capture type secondary; + capture group default; + }; + + register NXDMAENGFIR_ACT0 + { + name "EN.NX.DBG.NX_DMA_ENG_FIR_ACTION0"; + scomaddr 0x02013106; + capture type secondary; + capture group default; + }; + + register NXDMAENGFIR_ACT1 + { + name "EN.NX.DBG.NX_DMA_ENG_FIR_ACTION1"; + scomaddr 0x02013107; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet NXCQFIR + ############################################################################ + + register NXCQFIR + { + name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_REG"; + scomaddr 0x02013080; + reset (&, 0x02013081); + mask (|, 0x02013085); + capture group default; + }; + + register NXCQFIR_MASK + { + name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_MASK_REG"; + scomaddr 0x02013083; + capture type secondary; + capture group default; + }; + + register NXCQFIR_ACT0 + { + name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_ACTION0_REG"; + scomaddr 0x02013086; + capture type secondary; + capture group default; + }; + + register NXCQFIR_ACT1 + { + name "EN.NX.PBI.CQ_WRAP.NXCQ_SCOM.NX_CQ_FIR_ACTION1_REG"; + scomaddr 0x02013087; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet NXASFIR + ############################################################################ + + register NXASFIR + { + name "EN.NX.AS.FIR_REG"; + scomaddr 0x020130c0; + reset (&, 0x020130c1); + mask (|, 0x020130c5); + capture group default; + }; + + register NXASFIR_MASK + { + name "EN.NX.AS.FIR_MASK_REG"; + scomaddr 0x020130c3; + capture type secondary; + capture group default; + }; + + register NXASFIR_ACT0 + { + name "EN.NX.AS.FIR_ACTION0_REG"; + scomaddr 0x020130c6; + capture type secondary; + capture group default; + }; + + register NXASFIR_ACT1 + { + name "EN.NX.AS.FIR_ACTION1_REG"; + scomaddr 0x020130c7; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet NXCXAFIR + ############################################################################ + + register NXCXAFIR + { + name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_REG"; + scomaddr 0x02013000; + reset (&, 0x02013001); + mask (|, 0x02013005); + capture group default; + }; + + register NXCXAFIR_MASK + { + name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_MASK_REG"; + scomaddr 0x02013003; + capture type secondary; + capture group default; + }; + + register NXCXAFIR_ACT0 + { + name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_ACTION0_REG"; + scomaddr 0x02013006; + capture type secondary; + capture group default; + }; + + register NXCXAFIR_ACT1 + { + name "EN.NX.CXA.CXA_XPT.XPT_SCOMFIR.FIR_ACTION1_REG"; + scomaddr 0x02013007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet MCDFIR + ############################################################################ + + register MCDFIR + { + name "EH.PB.MCD.MCDCTL.FIR_REG"; + scomaddr 0x02013400; + reset (&, 0x02013401); + mask (|, 0x02013405); + capture group default; + }; + + register MCDFIR_MASK + { + name "EH.PB.MCD.MCDCTL.FIR_MASK_REG"; + scomaddr 0x02013403; + capture type secondary; + capture group default; + }; + + register MCDFIR_ACT0 + { + name "EH.PB.MCD.MCDCTL.FIR_ACTION0_REG"; + scomaddr 0x02013406; + capture type secondary; + capture group default; + }; + + register MCDFIR_ACT1 + { + name "EH.PB.MCD.MCDCTL.FIR_ACTION1_REG"; + scomaddr 0x02013407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PBWESTFIR + ############################################################################ + + register PBWESTFIR + { + name "EH.PB.MISC.PB_WEST_FIR_REG"; + scomaddr 0x02010c00; + reset (&, 0x02010c01); + mask (|, 0x02010c05); + capture group default; + }; + + register PBWESTFIR_MASK + { + name "EH.PB.MISC.PB_WEST_FIR_MASK_REG"; + scomaddr 0x02010c03; + capture type secondary; + capture group default; + }; + + register PBWESTFIR_ACT0 + { + name "EH.PB.MISC.PB_WEST_FIR_ACTION0_REG"; + scomaddr 0x02010c06; + capture type secondary; + capture group default; + }; + + register PBWESTFIR_ACT1 + { + name "EH.PB.MISC.PB_WEST_FIR_ACTION1_REG"; + scomaddr 0x02010c07; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PBCENTFIR + ############################################################################ + + register PBCENTFIR + { + name "EH.PB.MISC.PB_CENT_FIR_REG"; + scomaddr 0x02010c40; + reset (&, 0x02010c41); + mask (|, 0x02010c45); + capture group default; + }; + + register PBCENTFIR_MASK + { + name "EH.PB.MISC.PB_CENT_FIR_MASK_REG"; + scomaddr 0x02010c43; + capture type secondary; + capture group default; + }; + + register PBCENTFIR_ACT1 + { + name "EH.PB.MISC.PB_CENT_FIR_ACTION1_REG"; + scomaddr 0x02010c47; + capture type secondary; + capture group default; + }; + + register PBCENTFIR_ACT0 + { + name "EH.PB.MISC.PB_CENT_FIR_ACTION0_REG"; + scomaddr 0x02010c46; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PBEASTFIR + ############################################################################ + + register PBEASTFIR + { + name "EH.PB.MISC.PB_EAST_FIR_REG"; + scomaddr 0x02010c80; + reset (&, 0x02010c81); + mask (|, 0x02010c85); + capture group default; + }; + + register PBEASTFIR_MASK + { + name "EH.PB.MISC.PB_EAST_FIR_MASK_REG"; + scomaddr 0x02010c83; + capture type secondary; + capture group default; + }; + + register PBEASTFIR_ACT0 + { + name "EH.PB.MISC.PB_EAST_FIR_ACTION0_REG"; + scomaddr 0x02010c86; + capture type secondary; + capture group default; + }; + + register PBEASTFIR_ACT1 + { + name "EH.PB.MISC.PB_EAST_FIR_ACTION1_REG"; + scomaddr 0x02010c87; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PBEXTFIR + ############################################################################ + + # External checkstop register - Used for FFDC only + # Any attention generated from this FIR register indicates that there was a + # checkstop attention raised on another chip. Currently, we do not do any + # additional analysis in this FIR because we assume we will get an interrupt + # from the offending chip. This FIR will set PB_CHIPLET_FIR[2] which is + # currently ignored. + + register PBEXTFIR + { + name "EH.PB.MISC.EXTFIR_REG"; + scomaddr 0x02010c6e; + capture group default; + }; + + ############################################################################ + # PB Chiplet PSIFIR + ############################################################################ + + register PSIFIR + { + name "EN.TPC.PSIHB.PSIHB_FIR_REG"; + scomaddr 0x02010900; + reset (&, 0x02010901); + mask (|, 0x02010905); + capture group default; + }; + + register PSIFIR_MASK + { + name "EN.TPC.PSIHB.PSIHB_FIR_MASK_REG"; + scomaddr 0x02010903; + capture type secondary; + capture group default; + }; + + register PSIFIR_ACT0 + { + name "EN.TPC.PSIHB.PSIHB_FIR_ACTION0_REG"; + scomaddr 0x02010906; + capture type secondary; + capture group default; + }; + + register PSIFIR_ACT1 + { + name "EN.TPC.PSIHB.PSIHB_FIR_ACTION1_REG"; + scomaddr 0x02010907; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet ICPFIR + ############################################################################ + + register ICPFIR + { + name "EN.TPC.INTP.SYNC_FIR_REG"; + scomaddr 0x020109c0; + reset (&, 0x020109c1); + mask (|, 0x020109c5); + capture group default; + }; + + register ICPFIR_MASK + { + name "EN.TPC.INTP.SYNC_FIR_MASK_REG"; + scomaddr 0x020109c3; + capture type secondary; + capture group default; + }; + + register ICPFIR_ACT0 + { + name "EN.TPC.INTP.SYNC_FIR_ACTION0_REG"; + scomaddr 0x020109c6; + capture type secondary; + capture group default; + }; + + register ICPFIR_ACT1 + { + name "EN.TPC.INTP.SYNC_FIR_ACTION1_REG"; + scomaddr 0x020109c7; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PBAFIR + ############################################################################ + + register PBAFIR + { + name "EN.TPC.PBA.PBAFIR"; + scomaddr 0x02010840; + reset (&, 0x02010841); + mask (|, 0x02010845); + capture group default; + }; + + register PBAFIR_MASK + { + name "EN.TPC.PBA.PBAFIRMASK"; + scomaddr 0x02010843; + capture type secondary; + capture group default; + }; + + register PBAFIR_ACT0 + { + name "EN.TPC.PBA.PBAFIRACT0"; + scomaddr 0x02010846; + capture type secondary; + capture group default; + }; + + register PBAFIR_ACT1 + { + name "EN.TPC.PBA.PBAFIRACT1"; + scomaddr 0x02010847; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet EHHCAFIR + ############################################################################ + + register EHHCAFIR + { + name "EH.TPC.HCA.EHHCA_FIR_REG"; + scomaddr 0x02010980; + reset (&, 0x02010981); + mask (|, 0x02010985); + capture group default; + }; + + register EHHCAFIR_MASK + { + name "EH.TPC.HCA.EHHCA_FIR_MASK_REG"; + scomaddr 0x02010983; + capture type secondary; + capture group default; + }; + + register EHHCAFIR_ACT0 + { + name "EH.TPC.HCA.EHHCA_FIR_ACTION0_REG"; + scomaddr 0x02010986; + capture type secondary; + capture group default; + }; + + register EHHCAFIR_ACT1 + { + name "EH.TPC.HCA.EHHCA_FIR_ACTION1_REG"; + scomaddr 0x02010987; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet ENHCAFIR + ############################################################################ + + register ENHCAFIR + { + name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_REG"; + scomaddr 0x02010940; + reset (&, 0x02010941); + mask (|, 0x02010945); + capture group default; + }; + + register ENHCAFIR_MASK + { + name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_MASK_REG"; + scomaddr 0x02010943; + capture type secondary; + capture group default; + }; + + register ENHCAFIR_ACT0 + { + name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_ACTION0_REG"; + scomaddr 0x02010946; + capture type secondary; + capture group default; + }; + + register ENHCAFIR_ACT1 + { + name "EN.TPC.BRIDGE.HCA.ENHCA_FIR_ACTION1_REG"; + scomaddr 0x02010947; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PCINESTFIR_0 + ############################################################################ + + register PCINESTFIR_0 + { + name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_REG"; + scomaddr 0x02012000; + reset (&, 0x02012001); + mask (|, 0x02012005); + capture group default; + }; + + register PCINESTFIR_0_MASK + { + name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_MASK_REG"; + scomaddr 0x02012003; + capture type secondary; + capture group default; + }; + + register PCINESTFIR_0_ACT0 + { + name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_ACTION0_REG"; + scomaddr 0x02012006; + capture type secondary; + capture group default; + }; + + register PCINESTFIR_0_ACT1 + { + name "ES.PE_WRAP_TOP.PE0.PEPBCQ.PBCQ.FIR_ACTION1_REG"; + scomaddr 0x02012007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PCINESTFIR_1 + ############################################################################ + + register PCINESTFIR_1 + { + name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_REG"; + scomaddr 0x02012400; + reset (&, 0x02012401); + mask (|, 0x02012405); + capture group default; + }; + + register PCINESTFIR_1_MASK + { + name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_MASK_REG"; + scomaddr 0x02012403; + capture type secondary; + capture group default; + }; + + register PCINESTFIR_1_ACT0 + { + name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_ACTION0_REG"; + scomaddr 0x02012406; + capture type secondary; + capture group default; + }; + + register PCINESTFIR_1_ACT1 + { + name "ES.PE_WRAP_TOP.PE1.PEPBCQ.PBCQ.FIR_ACTION1_REG"; + scomaddr 0x02012407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet PCINESTFIR_2 + ############################################################################ + + register PCINESTFIR_2 + { + name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_REG"; + scomaddr 0x02012800; + reset (&, 0x02012801); + mask (|, 0x02012805); + capture group default; + }; + + register PCINESTFIR_2_MASK + { + name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_MASK_REG"; + scomaddr 0x02012803; + capture type secondary; + capture group default; + }; + + register PCINESTFIR_2_ACT0 + { + name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_ACTION0_REG"; + scomaddr 0x02012806; + capture type secondary; + capture group default; + }; + + register PCINESTFIR_2_ACT1 + { + name "ES.PE_WRAP_TOP.PE2.PEPBCQ.PBCQ.FIR_ACTION1_REG"; + scomaddr 0x02012807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PB Chiplet IOMCFIR_0 + ############################################################################ + + # Venice only scomaddr = 0x02011A00 + + ############################################################################ + # PB Chiplet IOMCFIR_1 + ############################################################################ + + register IOMCFIR_1 + { + name "IOMC1.BUSCTL.SCOM.FIR_REG"; + scomaddr 0x02011E00; + reset (&, 0x02011E01); + mask (|, 0x02011E05); + capture group default; + }; + + register IOMCFIR_1_MASK + { + name "IOMC1.BUSCTL.SCOM.FIR_MASK_REG"; + scomaddr 0x02011E03; + capture type secondary; + capture group default; + }; + + register IOMCFIR_1_ACT0 + { + name "IOMC1.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x02011E06; + capture type secondary; + capture group default; + }; + + register IOMCFIR_1_ACT1 + { + name "IOMC1.BUSCTL.SCOM.FIR_ACTION1_REG"; + scomaddr 0x02011E07; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_regs_PCIE.rule b/src/usr/diag/prdf/plat/pegasus/Proc_regs_PCIE.rule new file mode 100644 index 000000000..18c4d33ce --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_regs_PCIE.rule @@ -0,0 +1,323 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_regs_PCIE.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # PCIE Chiplet Registers + ############################################################################ + + register PCIE_CHIPLET_CS_FIR + { + name "ES.PE_WRAP_TOP.TPC.XFIR"; + scomaddr 0x09040000; + capture group default; + }; + + register PCIE_CHIPLET_RE_FIR + { + name "ES.PE_WRAP_TOP.TPC.RFIR"; + scomaddr 0x09040001; + capture group default; + }; + + register PCIE_CHIPLET_FIR_MASK + { + name "ES.PE_WRAP_TOP.TPC.FIR_MASK"; + scomaddr 0x09040002; + capture type secondary; + capture group default; + }; + + register PCIE_CHIPLET_SPA + { + name "ES.PE_WRAP_TOP.TPC.EPS.FIR.SPATTN"; + scomaddr 0x09040004; + capture group default; + }; + + register PCIE_CHIPLET_SPA_MASK + { + name "ES.PE_WRAP_TOP.TPC.EPS.FIR.SPA_MASK"; + scomaddr 0x09040007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet LFIR + ############################################################################ + + register PCIE_LFIR + { + name "ES.PE_WRAP_TOP.TPC.LOCAL_FIR"; + scomaddr 0x0904000a; + reset (&, 0x0904000b); + mask (|, 0x0904000f); + capture group default; + }; + + register PCIE_LFIR_MASK + { + name "ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0904000d; + capture type secondary; + capture group default; + }; + + register PCIE_LFIR_ACT0 + { + name "ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x09040010; + capture type secondary; + capture group default; + }; + + register PCIE_LFIR_ACT1 + { + name "ES.PE_WRAP_TOP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x09040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet PCICLOCKFIR_0 + ############################################################################ + + register PCICLOCKFIR_0 + { + name "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; + scomaddr 0x09012000; + reset (&, 0x09012001); + mask (|, 0x09012005); + capture group default; + }; + + register PCICLOCKFIR_0_MASK + { + name "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_MASK_REG"; + scomaddr 0x09012003; + capture type secondary; + capture group default; + }; + + register PCICLOCKFIR_0_ACT0 + { + name "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_ACTION0_REG"; + scomaddr 0x09012006; + capture type secondary; + capture group default; + }; + + register PCICLOCKFIR_0_ACT1 + { + name "ES.PE_WRAP_TOP.PE0.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_ACTION1_REG"; + scomaddr 0x09012007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet PCICLOCKFIR_1 + ############################################################################ + + register PCICLOCKFIR_1 + { + name "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; + scomaddr 0x09012400; + reset (&, 0x09012401); + mask (|, 0x09012405); + capture group default; + }; + + register PCICLOCKFIR_1_MASK + { + name "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_MASK_REG"; + scomaddr 0x09012403; + capture type secondary; + capture group default; + }; + + register PCICLOCKFIR_1_ACT0 + { + name "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_ACTION0_REG"; + scomaddr 0x09012406; + capture type secondary; + capture group default; + }; + + register PCICLOCKFIR_1_ACT1 + { + name "ES.PE_WRAP_TOP.PE1.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_ACTION1_REG"; + scomaddr 0x09012407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet PCICLOCKFIR_2 + ############################################################################ + + register PCICLOCKFIR_2 + { + name "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_REG"; + scomaddr 0x09012800; + reset (&, 0x09012801); + mask (|, 0x09012805); + capture group default; + }; + + register PCICLOCKFIR_2_MASK + { + name "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_MASK_REG"; + scomaddr 0x09012803; + capture type secondary; + capture group default; + }; + + register PCICLOCKFIR_2_ACT0 + { + name "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_ACTION0_REG"; + scomaddr 0x09012806; + capture type secondary; + capture group default; + }; + + register PCICLOCKFIR_2_ACT1 + { + name "ES.PE_WRAP_TOP.PE2.PH3_TOP.ETU.RSB.PR_REGS.LEM.FIR_ACTION1_REG"; + scomaddr 0x09012807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet PBFFIR + ############################################################################ + + register PBFFIR + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_REG"; + scomaddr 0x09010800; + reset (&, 0x09010801); + mask (|, 0x09010805); + capture group default; + }; + + register PBFFIR_MASK + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_MASK_REG"; + scomaddr 0x09010803; + capture type secondary; + capture group default; + }; + + register PBFFIR_ACT0 + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_ACTION0_REG"; + scomaddr 0x09010806; + capture type secondary; + capture group default; + }; + + register PBFFIR_ACT1 + { + name "ES.PBES_WRAP_TOP.PBES_TOP.MISC_IOF.SCOM.PB_IOF_FIR_ACTION1_REG"; + scomaddr 0x09010807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet IOPPCIFIR_0 + ############################################################################ + + register IOPPCIFIR_0 + { + name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_STATUS_REG"; + scomaddr 0x09011400; + reset (&, 0x09011401); + mask (|, 0x09011405); + capture group default; + }; + + register IOPPCIFIR_0_MASK + { + name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_MASK_REG"; + scomaddr 0x09011403; + capture type secondary; + capture group default; + }; + + register IOPPCIFIR_0_ACT0 + { + name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION0_REG"; + scomaddr 0x09011406; + capture type secondary; + capture group default; + }; + + register IOPPCIFIR_0_ACT1 + { + name "IOP.IOP_X880.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION1_REG"; + scomaddr 0x09011407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # PCIE Chiplet IOPPCIFIR_1 + ############################################################################ + + register IOPPCIFIR_1 + { + name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_STATUS_REG"; + scomaddr 0x09011840; + reset (&, 0x09011841); + mask (|, 0x09011845); + capture group default; + }; + + register IOPPCIFIR_1_MASK + { + name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_MASK_REG"; + scomaddr 0x09011843; + capture type secondary; + capture group default; + }; + + register IOPPCIFIR_1_ACT0 + { + name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION0_REG"; + scomaddr 0x09011846; + capture type secondary; + capture group default; + }; + + register IOPPCIFIR_1_ACT1 + { + name "IOP.IOP_X881.IOP_PMA0.IOP_PMA_PLL0.IOP_PMA_PLL_RLM.IOP_PMA_PLL_REG_CONTROL.FIR_ACTION1_REG"; + scomaddr 0x09011847; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule b/src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule new file mode 100644 index 000000000..8a1280c70 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule @@ -0,0 +1,212 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_regs_TP.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # TP Chiplet Registers + ############################################################################ + + register TP_CHIPLET_CS_FIR + { + name "EH.TPCHIP.TPC.XFIR"; + scomaddr 0x01040000; + capture group default; + }; + + register TP_CHIPLET_RE_FIR + { + name "EH.TPCHIP.TPC.RFIR"; + scomaddr 0x01040001; + capture group default; + }; + + register TP_CHIPLET_FIR_MASK + { + name "EH.TPCHIP.TPC.FIR_MASK"; + scomaddr 0x01040002; + capture type secondary; + capture group default; + }; + + register TP_CHIPLET_SPA + { + name "EH.TPCHIP.TPC.EPS.FIR.SPATTN"; + scomaddr 0x01040004; + capture group default; + }; + + register TP_CHIPLET_SPA_MASK + { + name "EH.TPCHIP.TPC.EPS.FIR.SPA_MASK"; + scomaddr 0x01040007; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet LFIR + ############################################################################ + + register TP_LFIR + { + name "EH.TPCHIP.TPC.LOCAL_FIR"; + scomaddr 0x0104000a; + reset (&, 0x0104000b); + mask (|, 0x0104000f); + capture group default; + }; + + register TP_LFIR_MASK + { + name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0104000d; + capture type secondary; + capture group default; + }; + + register TP_LFIR_ACT0 + { + name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x01040010; + capture type secondary; + capture group never; + }; + + register TP_LFIR_ACT1 + { + name "EH.TPCHIP.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x01040011; + capture type secondary; + capture group never; + }; + + ############################################################################ + # TP Chiplet OCCFIR + ############################################################################ + + register OCCFIR + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIR"; + scomaddr 0x01010800; + reset (&, 0x01010801); + mask (|, 0x01010805); + capture group default; + }; + + register OCCFIR_MASK + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRMASK"; + scomaddr 0x01010803; + capture type secondary; + capture group default; + }; + + register OCCFIR_ACT0 + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT0"; + scomaddr 0x01010806; + capture type secondary; + capture group default; + }; + + register OCCFIR_ACT1 + { + name "EH.TPCHIP.OCC.OCI.SCOM.OCC_SCOM_OCCLFIRACT1"; + scomaddr 0x01010807; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet PBAMFIR + ############################################################################ + + register PBAMFIR + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_REG"; + scomaddr 0x01010c00; + reset (&, 0x01010c01); + mask (|, 0x01010c05); + capture group default; + }; + + register PBAMFIR_MASK + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_MASK_REG"; + scomaddr 0x01010c03; + capture type secondary; + capture group default; + }; + + register PBAMFIR_ACT0 + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_ACTION0_REG"; + scomaddr 0x01010c06; + capture type secondary; + capture group default; + }; + + register PBAMFIR_ACT1 + { + name "EH.TPCHIP.PIB.LPCM.LPC.SYNC_FIR_ACTION1_REG"; + scomaddr 0x01010c07; + capture type secondary; + capture group default; + }; + + ############################################################################ + # TP Chiplet PMCFIR + ############################################################################ + + register PMCFIR + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ERR_REG"; + scomaddr 0x01010840; + reset (&, 0x01010841); + mask (|, 0x01010845); + capture group default; + }; + + register PMCFIR_MASK + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ERR_MASK_REG"; + scomaddr 0x01010843; + capture type secondary; + capture group default; + }; + + register PMCFIR_ACT0 + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ACTION0_REG"; + scomaddr 0x01010846; + capture type secondary; + capture group default; + }; + + register PMCFIR_ACT1 + { + name "EH.TPCHIP.OCC.PMC.PMC_LFIR_ACTION1_REG"; + scomaddr 0x01010847; + capture type secondary; + capture group default; + }; + diff --git a/src/usr/diag/prdf/plat/pegasus/Proc_regs_XBUS.rule b/src/usr/diag/prdf/plat/pegasus/Proc_regs_XBUS.rule new file mode 100644 index 000000000..afdb299ea --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/Proc_regs_XBUS.rule @@ -0,0 +1,178 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/usr/diag/prdf/plat/pegasus/Proc_regs_XBUS.rule $ +# +# IBM CONFIDENTIAL +# +# COPYRIGHT International Business Machines Corp. 2012 +# +# p1 +# +# Object Code Only (OCO) source materials +# Licensed Internal Code Source Materials +# IBM HostBoot Licensed Internal Code +# +# The source code for this program is not published or otherwise +# divested of its trade secrets, irrespective of what has been +# deposited with the U.S. Copyright Office. +# +# Origin: 30 +# +# IBM_PROLOG_END_TAG + + ############################################################################ + # XBUS Chiplet Registers + ############################################################################ + + register XBUS_CHIPLET_CS_FIR + { + name "EN.PB.TPC.XFIR"; + scomaddr 0x04040000; + capture group default; + }; + + register XBUS_CHIPLET_RE_FIR + { + name "EN.PB.TPC.RFIR"; + scomaddr 0x04040001; + capture group default; + }; + + register XBUS_CHIPLET_FIR_MASK + { + name "EN.PB.TPC.FIR_MASK"; + scomaddr 0x04040002; + capture type secondary; + capture group default; + }; + + ############################################################################ + # XBUS Chiplet LFIR + ############################################################################ + + register XBUS_LFIR + { + name "EN.PB.TPC.LOCAL_FIR"; + scomaddr 0x0404000a; + reset (&, 0x0404000b); + mask (|, 0x0404000f); + capture group default; + }; + + register XBUS_LFIR_MASK + { + name "EN.PB.TPC.EPS.FIR.LOCAL_FIR_MASK"; + scomaddr 0x0404000d; + capture type secondary; + capture group default; + }; + + register XBUS_LFIR_ACT0 + { + name "EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION0"; + scomaddr 0x04040010; + capture type secondary; + capture group default; + }; + + register XBUS_LFIR_ACT1 + { + name "EN.PB.TPC.EPS.FIR.LOCAL_FIR_ACTION1"; + scomaddr 0x04040011; + capture type secondary; + capture group default; + }; + + ############################################################################ + # XBUS Chiplet PBENFIR + ############################################################################ + + register PBENFIR + { + name "EN.PB.PBEN.MISC_IO.SCOM.FIR_REG"; + scomaddr 0x04010c00; + reset (&, 0x04010c01); + reset (|, 0x04010c05); + capture group default; + }; + + register PBENFIR_MASK + { + name "EN.PB.PBEN.MISC_IO.SCOM.FIR_MASK_REG"; + scomaddr 0x04010c03; + capture type secondary; + capture group default; + }; + + register PBENFIR_ACT0 + { + name "EN.PB.PBEN.MISC_IO.SCOM.FIR_REG_ACTION0"; + scomaddr 0x04010c06; + capture type secondary; + capture group default; + }; + + register PBENFIR_ACT1 + { + name "EN.PB.PBEN.MISC_IO.SCOM.FIR_REG_ACTION1"; + scomaddr 0x04010c07; + capture type secondary; + capture group default; + }; + + ############################################################################ + # XBUS Chiplet IOXFIR_0 + ############################################################################ + + # Venice only scomaddr = TBD + + ############################################################################ + # XBUS Chiplet IOXFIR_1 + ############################################################################ + + register IOXFIR_1 + { + name "XBUS1.BUSCTL.SCOM.FIR_REG"; + scomaddr 0x04011400; + reset (&, 0x04010c01); + reset (|, 0x04010c05); + capture group default; + }; + + register IOXFIR_1_MASK + { + name "XBUS1.BUSCTL.SCOM.FIR_MASK_REG"; + scomaddr 0x04011403; + capture type secondary; + capture group default; + }; + + register IOXFIR_1_ACT0 + { + name "XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x04011406; + capture type secondary; + capture group default; + }; + + register IOXFIR_1_ACT1 + { + name "XBUS1.BUSCTL.SCOM.FIR_ACTION0_REG"; + scomaddr 0x04011407; + capture type secondary; + capture group default; + }; + + ############################################################################ + # XBUS Chiplet IOXFIR_2 + ############################################################################ + + # Venice only scomaddr = TBD + + ############################################################################ + # XBUS Chiplet IOXFIR_3 + ############################################################################ + + # Venice only scomaddr = TBD + diff --git a/src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.C b/src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.C new file mode 100644 index 000000000..a96039006 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.C @@ -0,0 +1,44 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** @file prdfCalloutUtil.C */ + +#include <prdfCalloutUtil.H> + +#include <iipServiceDataCollector.h> + +namespace PRDF +{ +namespace CalloutUtil +{ + +void defaultError( STEP_CODE_DATA_STRUCT & i_sc ) +{ + i_sc.service_data->SetCallout( NextLevelSupport_ENUM ); + i_sc.service_data->SetCallout( SP_CODE ); + i_sc.service_data->SetServiceCall(); +} + +} // end namespace CalloutUtil +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.H b/src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.H new file mode 100644 index 000000000..9794239ee --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.H @@ -0,0 +1,49 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfCalloutUtil.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef prdfCalloutUtil_H +#define prdfCalloutUtil_H + +/** @file prdfCalloutUtil.H + * @brief Utility functions for common, non-trivial callouts. + */ + +struct STEP_CODE_DATA_STRUCT; + +namespace PRDF +{ +namespace CalloutUtil +{ + +/** + * @brief In many cases, an internal logic error may occur in which 2nd level + * support and FSP code need to be called out. This function is intented + * to help eliminate the need to constantly repeat the list of callouts. + * @param i_sc The step code data struct. + */ +void defaultError( STEP_CODE_DATA_STRUCT & i_sc ); + +} // end namespace CalloutUtil +} // end namespace PRDF + +#endif // prdfCalloutUtil_H diff --git a/src/usr/diag/prdf/plat/pegasus/prdfCenMba.C b/src/usr/diag/prdf/plat/pegasus/prdfCenMba.C new file mode 100755 index 000000000..9739a0b75 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfCenMba.C @@ -0,0 +1,145 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfCenMba.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** @file prdfCenMba.C + * @brief Contains all the plugin code for the PRD Centaur MBA + */ + +#include <iipServiceDataCollector.h> +#include <prdfCalloutUtil.H> +#include <prdfExtensibleChip.H> +#include <prdfMemUtil.H> +#include <prdfPlatServices.H> +#include <prdfPluginMap.H> + +#include <prdfCenMbaDataBundle.H> + +namespace PRDF +{ +namespace Mba +{ + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +/** + * @brief Plugin that initializes the P8 Centaur MBA data bundle. + * @param i_mbaChip A Centaur MBA chip. + * @return SUCCESS + */ +int32_t Initialize( PrdfExtensibleChip * i_mbaChip ) +{ + i_mbaChip->getDataBundle() = new CenMbaDataBundle( i_mbaChip ); + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Mba, Initialize ); + +//------------------------------------------------------------------------------ + +/** + * @brief Plugin function called after analysis is complete but before PRD + * exits. + * @param i_mbaChip A Centaur MBA chip. + * @param i_sc The step code data struct. + * @note This is especially useful for any analysis that still needs to be + * done after the framework clears the FIR bits that were at attention. + * @return SUCCESS. + */ +int32_t PostAnalysis( PrdfExtensibleChip * i_mbaChip, + STEP_CODE_DATA_STRUCT & i_sc ) +{ + #ifdef __HOSTBOOT_MODULE + + using namespace TARGETING; + + // In hostboot, we need to clear MCI Fir bits. Do we will get the mcs + // chiplet connected with Mba and call its plugin to clear those FIR bits + int32_t l_rc = MemUtil::clearHostAttns( i_mbaChip, i_sc ); + if ( SUCCESS != l_rc ) + PRDF_ERR( "[Mba::PostAnalysis] MemUtil::clearHostAttns failed" ); + + // Send command complete to MDIA. + // This must be done in post analysis after attentions have been cleared. + if ( PlatServices::isInMdiaMode() ) + { + TargetHandle_t mbaTarget = i_mbaChip->GetChipHandle(); + CenMbaDataBundle * mbadb = getMbaDataBundle( i_mbaChip ); + + mbadb->iv_sendCmdCompleteMsg = false; + PlatServices::mdiaSendCmdComplete( mbaTarget ); + } + + #endif // __HOSTBOOT_MODULE + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Mba, PostAnalysis ); + +//############################################################################## +// +// MBASPA +// +//############################################################################## + +/** + * @brief MBASPA[0] - Maintenance command complete. + * @param i_mbaChip A Centaur MBA chip. + * @param i_sc The step code data struct. + * @return SUCCESS + */ +int32_t MaintCmdComplete( PrdfExtensibleChip * i_mbaChip, + STEP_CODE_DATA_STRUCT & i_sc ) +{ + using namespace TARGETING; + + int32_t l_rc = SUCCESS; + TargetHandle_t mbaTarget = i_mbaChip->GetChipHandle(); + + do + { + #ifdef __HOSTBOOT_MODULE + + // TODO: Will need to change design once this for error path. + CenMbaDataBundle * mbadb = getMbaDataBundle( i_mbaChip ); + mbadb->iv_sendCmdCompleteMsg = true; + + #endif // __HOSTBOOT_MODULE + + } while (0); + + if ( SUCCESS != l_rc ) + { + PRDF_ERR( "[Mba::MaintCmdComplete] failed on MBA 0x%08x", + PlatServices::getHuid(mbaTarget) ); + CalloutUtil::defaultError( i_sc ); + } + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Mba, MaintCmdComplete ); + +} // end namespace Mba +} // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/pegasus/prdfCenMbaDataBundle.H b/src/usr/diag/prdf/plat/pegasus/prdfCenMbaDataBundle.H new file mode 100644 index 000000000..375bd61a4 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfCenMbaDataBundle.H @@ -0,0 +1,86 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfCenMbaDataBundle.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef prdfCenMbaDataBundle_H +#define prdfCenMbaDataBundle_H + +/** @file prdfCenMbaDataBundle.H + * @brief Contains the data bundle for a PRD Centaur MBA object. + */ + +#include <prdfExtensibleChip.H> + +//------------------------------------------------------------------------------ + +namespace PRDF +{ + +/** + * @brief The P7 Centaur MBA data bundle. + */ +class CenMbaDataBundle : public PrdfDataBundle +{ + public: // functions + + /** + * @brief Constructor. + * @param i_mbaChip The MBA chip. + */ + explicit CenMbaDataBundle( PrdfExtensibleChip * i_mbaChip ) : + iv_sendCmdCompleteMsg(false) + {} + + /** + * @brief Destructor. + */ + ~CenMbaDataBundle() {} + + private: // functions + + CenMbaDataBundle( const CenMbaDataBundle & ); + const CenMbaDataBundle & operator=( const CenMbaDataBundle & ); + + public: // instance variables + + /** TRUE if a maintenance command complete message needs to be sent in the + * post analysis plugin, FALSE otherwise. */ + bool iv_sendCmdCompleteMsg; + +}; + +//------------------------------------------------------------------------------ + +/** + * @brief Wrapper function for the CenMbaDataBundle. + * @param i_mbaChip The MBA chip. + * @return This MBA's data bundle. + */ +inline CenMbaDataBundle * getMbaDataBundle( PrdfExtensibleChip * i_mbaChip ) +{ + return static_cast<CenMbaDataBundle *>(i_mbaChip->getDataBundle()); +} + +} // end namespace PRDF + +#endif // prdfCenMbaDataBundle_H + diff --git a/src/usr/diag/prdf/plat/pegasus/prdfCenMembuf.C b/src/usr/diag/prdf/plat/pegasus/prdfCenMembuf.C new file mode 100755 index 000000000..55d2fb741 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfCenMembuf.C @@ -0,0 +1,101 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfCenMembuf.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** @file prdfCenMembuf.C + * @brief Contains all the plugin code for the PRD Centaur Membuf + */ + +#include <iipServiceDataCollector.h> +#include <prdfCalloutUtil.H> +#include <prdfExtensibleChip.H> +#include <prdfMemUtil.H> +#include <prdfPlatServices.H> +#include <prdfPluginMap.H> + + +namespace PRDF +{ +namespace Membuf +{ + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +/** + * @brief Plugin that initializes the P8 Centaur Membuf data bundle. + * @param i_mbaChip A Centaur Membuf chip. + * @return SUCCESS + */ +int32_t Initialize( PrdfExtensibleChip * i_mbaChip ) +{ + // FIXME: need to implement + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Membuf, Initialize ); + +//------------------------------------------------------------------------------ + +/** + * @fn CheckForRecovered + * @brief Used when the chip has a CHECK_STOP attention to check for the + * presence of recovered errors. + */ +int32_t CheckForRecovered(PrdfExtensibleChip * i_chip, + bool & o_hasRecovered) +{ + //FIXME: need to fully implement for Membuf + o_hasRecovered = false; + + return SUCCESS; +} PRDF_PLUGIN_DEFINE( Membuf, CheckForRecovered ); + +//------------------------------------------------------------------------------ + + + +//------------------------------------------------------------------------------ + +/** + * @brief Plugin function called after analysis is complete but before PRD + * exits. + * @param i_membufChip A Centaur Membuf chip. + * @param i_sc The step code data struct. + * @note This is especially useful for any analysis that still needs to be + * done after the framework clears the FIR bits that were at attention. + * @return SUCCESS. + */ +int32_t PostAnalysis( PrdfExtensibleChip * i_membufChip, + STEP_CODE_DATA_STRUCT & i_sc ) +{ + //FIXME: need to implement + + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Membuf, PostAnalysis ); + + +} // end namespace Membuf +} // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/pegasus/prdfMemUtil.C b/src/usr/diag/prdf/plat/pegasus/prdfMemUtil.C new file mode 100644 index 000000000..db09b8d72 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfMemUtil.C @@ -0,0 +1,114 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfMemUtil.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** @file prdfMemUtil.C */ + +#include <prdfMemUtil.H> + +#include <iipconst.h> +#include <iipglobl.h> +#include <iipSystem.h> +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPlatServices.H> + +namespace PRDF +{ +namespace MemUtil +{ + +#ifdef __HOSTBOOT_MODULE + +int32_t clearHostAttns( PrdfExtensibleChip * i_memChip, + STEP_CODE_DATA_STRUCT & i_sc ) +{ + using namespace TARGETING; + + int32_t o_rc = SUCCESS; + + TargetHandle_t memHandle = i_memChip->GetChipHandle(); + + do + { + // Get the attached MCS chip. + PrdfExtensibleChip * mcsChip = i_memChip; + if ( TYPE_MCS != PlatServices::getTargetType(memHandle) ) + { + TargetHandleList list = PlatServices::getConnected( memHandle, + TYPE_MCS ); + if ( 1 == list.size() ) + mcsChip = (PrdfExtensibleChip *)systemPtr->GetChip( list[0] ); + else + { + PRDF_ERR( "[MemUtil::clearHostAttns] getConnected() failed" ); + o_rc = FAIL; + break; + } + } + + // Clear FIR bits based on the cause attention type. + // Note: The cause attention type is different than the global attention + // type, in that it is the attention type that we actually + // isolated to. For example, the global attention type could be + // CHECK_STOP but the cause atttention type could be RECOVERABLE. + SCAN_COMM_REGISTER_CLASS * firand = mcsChip->getRegister("MCIFIR_AND"); + firand->setAllBits(); + + ATTENTION_TYPE l_attnType = i_sc.service_data->GetCauseAttentionType(); + switch ( l_attnType ) + { + case CHECK_STOP: firand->ClearBit(12); break; + case RECOVERABLE: firand->ClearBit(15); break; + case SPECIAL: firand->ClearBit(16); + firand->ClearBit(17); break; + default: + PRDF_ERR( "[MemUtil::clearHostAttns] Invalid attention type %d", + l_attnType ); + o_rc = FAIL; + break; + } + if ( SUCCESS != o_rc ) break; + + o_rc = firand->Write(); + if ( SUCCESS != o_rc) + { + PRDF_ERR( "[MemUtil::clearHostAttns] MCIFIR_AND write failed" ); + break; + } + + } while(0); + + if ( SUCCESS != o_rc ) + { + PRDF_ERR( "[MemUtil::clearHostAttns] Failed: i_memChip=0x%08x", + PlatServices::getHuid(memHandle) ); + } + + return o_rc; +} + +#endif // __HOSTBOOT_MODULE + +} // end namespace MemUtil +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/plat/pegasus/prdfMemUtil.H b/src/usr/diag/prdf/plat/pegasus/prdfMemUtil.H new file mode 100644 index 000000000..edf638eab --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfMemUtil.H @@ -0,0 +1,58 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfMemUtil.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef prdfMemUtil_H +#define prdfMemUtil_H + +/** @file prdfMemUtil.H + * @brief General utility functions for the memory subsystem. + */ + +#include <iipconst.h> + +class PrdfExtensibleChip; +struct STEP_CODE_DATA_STRUCT; + +namespace PRDF +{ +namespace MemUtil +{ + +//#ifdef __HOSTBOOT_MODULE + +/** + * @brief Clears bits in the MCIFIR that are triggered by centaur attentions + * that are reported to the host. + * @param i_memChip Any memory chip (MCS, MEMBUF, MBS, MBA, DIMM, etc.). + * @param i_sc The step code data struct. + * @return Non-SUCCESS for internal errors, SUCCESS otherwise. + */ +int32_t clearHostAttns( PrdfExtensibleChip * i_memChip, + STEP_CODE_DATA_STRUCT & i_sc ); + +//#endif // __HOSTBOOT_MODULE + +} // end namespace MemUtil +} // end namespace PRDF + +#endif // prdfMemUtil_H diff --git a/src/usr/diag/prdf/plat/pegasus/prdfP8Mcs.C b/src/usr/diag/prdf/plat/pegasus/prdfP8Mcs.C new file mode 100755 index 000000000..d62412466 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfP8Mcs.C @@ -0,0 +1,57 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfP8Mcs.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** @file prdfP8Mcs.C + * @brief Contains all the plugin code for the PRD P8 MCS + */ + +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPluginMap.H> + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +namespace PRDF +{ +namespace Mcs +{ + +/** + * @brief Plugin that initializes the MCS data bundle. + * @param i_mcsChip An MCS chip. + * @return SUCCESS + */ +int32_t Initialize( PrdfExtensibleChip * i_mcsChip ) +{ + // FIXME: Add proper initialization as per requirement + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Mcs, Initialize ); + +} // end namespace Mcs +} // end namespace PRDF + diff --git a/src/usr/diag/prdf/plat/pegasus/prdfP8Proc.C b/src/usr/diag/prdf/plat/pegasus/prdfP8Proc.C new file mode 100755 index 000000000..b921f7dc1 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfP8Proc.C @@ -0,0 +1,126 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfP8Proc.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +/** @file prdfP8Proc.C + * @brief Contains all the plugin code for the PRD P8 Proc + */ +#include <prdfPluginDef.H> +#include <iipServiceDataCollector.h> +#include <prdfExtensibleChip.H> +#include <prdfPlatServices.H> +#include <prdfPluginMap.H> + +namespace PRDF +{ +namespace Proc +{ + +//############################################################################## +// +// Special plugins +// +//############################################################################## + +/** + * @brief Plugin that initializes the P8 Mba data bundle. + * @param i_chip P8 chip. + * @return SUCCESS + */ +int32_t Initialize( PrdfExtensibleChip * i_chip ) +{ + // FIXME: Add proper initialization as per requirement + return SUCCESS; +} +PRDF_PLUGIN_DEFINE( Proc, Initialize ); + +/** + * @fn CheckForRecovered + * @brief Used when the chip has a CHECK_STOP attention to check for the + * presence of recovered errors. + */ +int32_t CheckForRecovered(PrdfExtensibleChip * i_chip, + bool & o_hasRecovered) +{ + //FIXME: need to fully implement for P8 + o_hasRecovered = false; + + return SUCCESS; +} PRDF_PLUGIN_DEFINE( Proc, CheckForRecovered ); + + + +//------------------------------------------------------------------------------ +/** + * @fn prdCheckForRecoveredSev + * @brief Used when the chip is queried, by the fabric domain, for RECOVERED + * attentions to assign a severity to the attention for sorting. + * @param[in] i_chip - P8 chip + * @param[out] o_sev - Priority order (lowest to highest): + * 1 - Core chiplet checkstop + * 2 - Core chiplet error + * 3 - PCB chiplet error (TOD logic) + * 4 - Other error + * 5 - Memory controller chiplet + * + * @return SUCCESS + * + */ +int32_t CheckForRecoveredSev(PrdfExtensibleChip * i_chip, + uint32_t & o_sev) +{ + //FIXME: need to fully implement for P8 + o_sev = 1; + + return SUCCESS; + +} PRDF_PLUGIN_DEFINE( Proc, CheckForRecoveredSev ); + +/** @func GetCheckstopInfo + * To be called from the fabric domain to gather Checkstop information. This + * information is used in a sorting algorithm. + * + * This is a plugin function: GetCheckstopInfo + * + * @param i_chip - The chip. + * @param o_wasInternal - True if this chip has an internal checkstop. + * @param o_externalChips - List of external fabrics driving checkstop. + * @param o_wofValue - Current WOF value (unused for now). + */ +int32_t GetCheckstopInfo(PrdfExtensibleChip * i_chip, + bool & o_wasInternal, + TARGETING::TargetHandleList & o_externalChips, + uint64_t & o_wofValue) +{ + // Clear parameters. + o_wasInternal = true; //FIXME: default to true until fabric sorting is done + o_externalChips.erase(o_externalChips.begin(), o_externalChips.end()); + o_wofValue = 0; + + // FIXME: this will need to implement under fabric sorting algo + + return SUCCESS; + +} PRDF_PLUGIN_DEFINE( Proc, GetCheckstopInfo ); + +} // end namespace Proc +} // end namespace PRDF diff --git a/src/usr/diag/prdf/plat/pegasus/prdfP8SystemSpecific.C b/src/usr/diag/prdf/plat/pegasus/prdfP8SystemSpecific.C new file mode 100644 index 000000000..074ddd3e6 --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfP8SystemSpecific.C @@ -0,0 +1,43 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfP8SystemSpecific.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#include <prdfSystemSpecific.H> + +#include <iipglobl.h> +#include <iipScanCommRegisterAccess.h> +#include <prdfPegasusConfigurator.H> +#include <prdfPlatServices.H> + + +namespace PrdfSystemSpecific +{ + Configurator * getConfiguratorPtr() + { + return new PrdfPegasusConfigurator; + } + + void postAnalysisWorkarounds(STEP_CODE_DATA_STRUCT & i_sdc) + { + return; + } +}; diff --git a/src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.C b/src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.C new file mode 100644 index 000000000..db5986adf --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.C @@ -0,0 +1,181 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.C $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ + +#include <iipglobl.h> +#include <prdfPegasusConfigurator.H> +#include <prdfRuleFiles.H> + +#include <prdfRuleChip.H> +#include <iipDomainContainer.h> +#include <prdfScanFacility.H> +#include <iipResolutionFactory.h> + +#include <prdfFabricDomain.H> +#include <prdfExDomain.H> +#include <prdfMcsDomain.H> +#include <prdfMembufDomain.H> +#include <prdfMbaDomain.H> +#include <prdfPlatServices.H> +#include <iipSystem.h> +#include <prdrLoadChipCache.H> // To flush chip-file cache. + +//------------------------------------------------------------------------------ + +// Resolution for no chips at attention. +CallAttnResolution PrdfPegasusConfigurator::noAttnResolution; + +//------------------------------------------------------------------------------ + +System * PrdfPegasusConfigurator::build() +{ + using namespace TARGETING; + + PRDF_ENTER( "PrdfPegasusConfigurator::build()" ); + + // Create System object to populate with domains. + System * l_system = new System(noAttnResolution); + + // Create domains. + FabricDomain * l_procDomain = new FabricDomain( FABRIC_DOMAIN ); + PrdfExDomain * l_exDomain = new PrdfExDomain( EX_DOMAIN ); + PrdfMcsDomain * l_mcsDomain = new PrdfMcsDomain( MCS_DOMAIN ); + PrdfMembufDomain * l_membufDomain = new PrdfMembufDomain( MEMBUF_DOMAIN ); + PrdfMbaDomain * l_mbaDomain = new PrdfMbaDomain( MBA_DOMAIN ); + + // Add chips to domains. + addDomainChips( TYPE_PROC, l_procDomain ); + addDomainChips( TYPE_EX, l_exDomain ); + addDomainChips( TYPE_MCS, l_mcsDomain ); + addDomainChips( TYPE_MEMBUF, l_membufDomain ); + addDomainChips( TYPE_MBA, l_mbaDomain ); + + // Add domains to domain list. NOTE: Order is important because this is the + // order the domains will be analyzed. + sysDmnLst.push_back( l_procDomain ); + sysDmnLst.push_back( l_exDomain ); + sysDmnLst.push_back( l_mcsDomain ); + sysDmnLst.push_back( l_membufDomain ); + sysDmnLst.push_back( l_mbaDomain ); + + // Add chips to the system. + Configurator::chipList & chips = getChipList(); + l_system->AddChips( chips.begin(), chips.end() ); + + // Add domains to the system. + Configurator::domainList & domains = getDomainList(); + l_system->AddDomains( domains.begin(), domains.end() ); + + PRDF_EXIT( "PrdfPegasusConfigurator::build()" ); + + return l_system; +} + +//------------------------------------------------------------------------------ + +void PrdfPegasusConfigurator::addDomainChips( TARGETING::TYPE i_type, + PrdfRuleChipDomain * io_domain ) +{ + using namespace TARGETING; + using namespace PRDF; + + int32_t l_rc = SUCCESS; + + // Get references to factory objects. + ScanFacility & scanFac = ScanFacility::Access(); + ResolutionFactory & resFac = ResolutionFactory::Access(); + + // Get rule filename based on type. + const char * fileName = ""; + switch ( i_type ) + { + case TYPE_PROC: fileName = PRDF::Proc; break; + case TYPE_EX: fileName = PRDF::Ex; break; + case TYPE_MCS: fileName = PRDF::Mcs; break; + case TYPE_MEMBUF: fileName = PRDF::Membuf; break; + case TYPE_MBA: fileName = PRDF::Mba; break; + + default: + // Print a trace statement, but do not fail the build. + PRDF_ERR( "[addDomainChips] Unsupported target type: %d", i_type ); + l_rc = FAIL; + } + + if ( SUCCESS == l_rc ) + { + /* + // Test code to vary the size of the target config + // so we can still run one simic system type but + // get different configs for memory measurements + + uint32_t PROC_LIMIT = 16; // set to no limit for now + uint32_t MEMBUF_PER_PROC_LIMIT = 4; + uint32_t CONFIG_LIMIT = 0; + uint32_t count = 0; + switch ( i_type ) + { + case TYPE_PROC: CONFIG_LIMIT = PROC_LIMIT; break; + case TYPE_EX: CONFIG_LIMIT = 6 * PROC_LIMIT; break; + case TYPE_ABUS: CONFIG_LIMIT = 3 * PROC_LIMIT; break; + case TYPE_XBUS: CONFIG_LIMIT = 4 * PROC_LIMIT; break; + case TYPE_MCS: CONFIG_LIMIT = MEMBUF_PER_PROC_LIMIT * PROC_LIMIT; break; + case TYPE_MEMBUF: CONFIG_LIMIT = MEMBUF_PER_PROC_LIMIT * PROC_LIMIT; break; + case TYPE_MBA: CONFIG_LIMIT = 2 * MEMBUF_PER_PROC_LIMIT * PROC_LIMIT; break; + + default: break; + } + //end Test code + */ + + // Get all targets of specified type and add to given domain. + TargetHandleList list = PlatServices::getFunctionalTargetList( i_type ); + for ( TargetHandleList::const_iterator itr = list.begin(); + itr != list.end(); ++itr ) + { + if ( NULL == *itr ) continue; + + // Test code to vary the target config + //if(count < CONFIG_LIMIT) + //{ + +// PRDF_TRAC( "[addDomainChips] build rule chip target: 0x%08x", +// PlatServices::getHuid(*itr) ); + + PrdfRuleChip * chip = new PrdfRuleChip( fileName, *itr, + scanFac, resFac ); + sysChipLst.push_back( chip ); + io_domain->AddChip( chip ); + + //} + //count++; + } + + // Flush rule table cache since objects are all built. + Prdr::LoadChipCache::flushCache(); + + } +} + diff --git a/src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.H b/src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.H new file mode 100644 index 000000000..8e638e64d --- /dev/null +++ b/src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.H @@ -0,0 +1,86 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/usr/diag/prdf/plat/pegasus/prdfPegasusConfigurator.H $ */ +/* */ +/* IBM CONFIDENTIAL */ +/* */ +/* COPYRIGHT International Business Machines Corp. 2012 */ +/* */ +/* p1 */ +/* */ +/* Object Code Only (OCO) source materials */ +/* Licensed Internal Code Source Materials */ +/* IBM HostBoot Licensed Internal Code */ +/* */ +/* The source code for this program is not published or otherwise */ +/* divested of its trade secrets, irrespective of what has been */ +/* deposited with the U.S. Copyright Office. */ +/* */ +/* Origin: 30 */ +/* */ +/* IBM_PROLOG_END_TAG */ + +#ifndef prdfPegasusConfigurator_H +#define prdfPegasusConfigurator_H + +/** @file prdfPegasusConfigurator.H + * @brief Builds the PRD system model for Pegasus (P8 based systems). + */ + +#include <iipConfigurator.h> +#include <iipCallAttnResolution.h> // For CallAttnResolution +#include <prdfRuleChipDomain.H> + +/** @brief PRD configurator for Pegasus (P8 systems) */ +class PrdfPegasusConfigurator : public Configurator +{ + public: + + /** + * @brief Constructor + */ + PrdfPegasusConfigurator() : + Configurator( PrdfRuleChipDomain::TOTAL_CHIPS, + PrdfRuleChipDomain::TOTAL_DOMAINS ) + {} + + /** + * @brief Destructor + * @note This configurator does not delete the objects it created during + * build(); that is the responsibility of the system object. + */ + ~PrdfPegasusConfigurator() {} + + /** + * @brief Create the PRD system object, all chip instances, and all domain + * instances. + * @return Pointer to configured system. + * @note The caller of this function owns the responsiblity of deleting + * the system object created. + */ + virtual System * build(); + + private: // functions + + /** @brief Copy not allowed. */ + PrdfPegasusConfigurator( const PrdfPegasusConfigurator & right ); + + /** @brief Assignment not allowed. */ + const PrdfPegasusConfigurator & operator=( const PrdfPegasusConfigurator & right ); + + /** + * @brief Will add all chips of a given type to a domain. + * @parm i_type The specified target type. + * @parm io_domain The associated domain. + */ + void addDomainChips( TARGETING::TYPE i_type, + PrdfRuleChipDomain * io_domain ); + + private: // data + + static CallAttnResolution noAttnResolution; + +}; + +#endif |
