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| author | Zane Shelley <zshelle@us.ibm.com> | 2018-03-08 21:42:46 -0600 |
|---|---|---|
| committer | Zane C. Shelley <zshelle@us.ibm.com> | 2018-03-09 15:30:54 -0500 |
| commit | 08379ab81944d9da11f6a0970b62990316f0c932 (patch) | |
| tree | ba29aa0131e112fe1fe4e9b8816fdffacb0d78eb /src/usr/diag/prdf/occ_firdata | |
| parent | f10101dc6c7e5be3e3fff9f0baff2c23b7436c06 (diff) | |
| download | talos-hostboot-08379ab81944d9da11f6a0970b62990316f0c932.tar.gz talos-hostboot-08379ab81944d9da11f6a0970b62990316f0c932.zip | |
PRD: extra FFDC for NPU0FIR
Change-Id: I3782e674a0ca23d179f2f5def5489faa39040275
CQ: SW420231
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55300
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55354
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Diffstat (limited to 'src/usr/diag/prdf/occ_firdata')
| -rw-r--r-- | src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C | 55 |
1 files changed, 41 insertions, 14 deletions
diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C index f9623a2f9..4bfe1de7c 100644 --- a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C +++ b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C @@ -309,20 +309,47 @@ void getAddresses( TrgtMap_t & io_targMap ) 0x04040018, // N2_CHIPLET_UCS_FIR 0x04040019, // N2_CHIPLET_UCS_FIR_MASK - 0x05011017, // NPU_STCK0_SM0_CERR - 0x05011047, // NPU_STCK0_SM1_CERR - 0x05011077, // NPU_STCK0_SM2_CERR - 0x050110A7, // NPU_STCK0_SM3_CERR - - 0x05011217, // NPU_STCK1_SM0_CERR - 0x05011247, // NPU_STCK1_SM1_CERR - 0x05011277, // NPU_STCK1_SM2_CERR - 0x050112A7, // NPU_STCK1_SM3_CERR - - 0x05011417, // NPU_STCK2_SM0_CERR - 0x05011447, // NPU_STCK2_SM1_CERR - 0x05011477, // NPU_STCK2_SM2_CERR - 0x050114A7, // NPU_STCK2_SM3_CERR + // There are over 90 registers captured for NPU0FIR, but that is too + // much for the limited space in the OP checkstop analysis design. The + // hardware team agreed this was the minimum set of registers needed + // for a checkstop. We have also been told most of these should have a + // zero value so they should not take up too much space. + 0x05011018, // NPU_S0_CS_SM0_CERR_1 + 0x05011019, // NPU_S0_CS_SM0_CERR_2 + 0x05011048, // NPU_S0_CS_SM1_CERR_1 + 0x05011049, // NPU_S0_CS_SM1_CERR_2 + 0x05011078, // NPU_S0_CS_SM2_CERR_1 + 0x05011079, // NPU_S0_CS_SM2_CERR_2 + 0x050110A8, // NPU_S0_CS_SM3_CERR_1 + 0x050110A9, // NPU_S0_CS_SM3_CERR_2 + 0x050110DB, // NPU_S0_CS_CTL_CERR_1 + 0x050110FA, // NPU_S0_DAT_CERR_LOG_HOLD + 0x050110FD, // NPU_S0_DAT_REM0 + 0x050110FE, // NPU_S0_DAT_REM1 + 0x05011218, // NPU_S1_CS_SM0_CERR_1 + 0x05011219, // NPU_S1_CS_SM0_CERR_2 + 0x05011248, // NPU_S1_CS_SM1_CERR_1 + 0x05011249, // NPU_S1_CS_SM1_CERR_2 + 0x05011278, // NPU_S1_CS_SM2_CERR_1 + 0x05011279, // NPU_S1_CS_SM2_CERR_2 + 0x050112A8, // NPU_S1_CS_SM3_CERR_1 + 0x050112A9, // NPU_S1_CS_SM3_CERR_2 + 0x050112DB, // NPU_S1_CS_CTL_CERR_1 + 0x050112FA, // NPU_S1_DAT_CERR_LOG_HOLD + 0x050112FD, // NPU_S1_DAT_REM0 + 0x050112FE, // NPU_S1_DAT_REM1 + 0x05011418, // NPU_S2_CS_SM0_CERR_1 + 0x05011419, // NPU_S2_CS_SM0_CERR_2 + 0x05011448, // NPU_S2_CS_SM1_CERR_1 + 0x05011449, // NPU_S2_CS_SM1_CERR_2 + 0x05011478, // NPU_S2_CS_SM2_CERR_1 + 0x05011479, // NPU_S2_CS_SM2_CERR_2 + 0x050114A8, // NPU_S2_CS_SM3_CERR_1 + 0x050114A9, // NPU_S2_CS_SM3_CERR_2 + 0x050114DB, // NPU_S2_CS_CTL_CERR_1 + 0x050114FA, // NPU_S2_DAT_CERR_LOG_HOLD + 0x050114FD, // NPU_S2_DAT_REM0 + 0x050114FE, // NPU_S2_DAT_REM1 0x05040000, // N3_CHIPLET_CS_FIR 0x05040001, // N3_CHIPLET_RE_FIR |
