PRD: extra FFDC for NPU0FIR

Change-Id: I3782e674a0ca23d179f2f5def5489faa39040275
CQ: SW420231
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55300
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55354
CI-Ready: Zane C. Shelley <zshelle@us.ibm.com>
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

5 files changed, 640 insertions, 63 deletions

diff --git a/src/usr/diag/prdf/common/plat/p9/p9_cumulus.rule b/src/usr/diag/prdf/common/plat/p9/p9_cumulus.rule
index b52ce9999..a77dd959a 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_cumulus.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_cumulus.rule
@@ -4138,7 +4138,7 @@ group gN3_CHIPLET_FIR filter singlebit
     /** N3_CHIPLET_FIR[10]
      *  Attention from NPU0FIR
      */
-    (rN3_CHIPLET_FIR, bit(10)) ? analyze(gNPU0FIR);
+    (rN3_CHIPLET_FIR, bit(10)) ? analyzeNPU0FIR;
 
     /** N3_CHIPLET_FIR[11]
      *  Attention from NPU1FIR
@@ -4232,7 +4232,7 @@ group gN3_CHIPLET_UCS_FIR filter singlebit
     /** N3_CHIPLET_UCS_FIR[7]
      *  Attention from NPU0FIR
      */
-    (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyze(gNPU0FIR);
+    (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyzeNPU0FIR;
 
     /** N3_CHIPLET_UCS_FIR[8]
      *  Attention from NPU1FIR
@@ -6807,7 +6807,7 @@ group gNPU0FIR filter singlebit, cs_root_cause( 1, 2, 3, 4, 5, 6, 7, 9, 10, 16,
     /** NPU0FIR[19]
      *  CQ CTL/SM NVF NVLink fatal error
      */
-    (rNPU0FIR, bit(19)) ? nvLinkAssist;
+    (rNPU0FIR, bit(19)) ? self_th_1;
 
     /** NPU0FIR[20]
      *  spare
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
index 0ab839311..bd653e65c 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_nimbus.rule
@@ -4118,7 +4118,7 @@ group gN3_CHIPLET_FIR filter singlebit
     /** N3_CHIPLET_FIR[10]
      *  Attention from NPU0FIR
      */
-    (rN3_CHIPLET_FIR, bit(10)) ? analyze(gNPU0FIR);
+    (rN3_CHIPLET_FIR, bit(10)) ? analyzeNPU0FIR;
 
     /** N3_CHIPLET_FIR[11]
      *  Attention from NPU1FIR
@@ -4212,7 +4212,7 @@ group gN3_CHIPLET_UCS_FIR filter singlebit
     /** N3_CHIPLET_UCS_FIR[7]
      *  Attention from NPU0FIR
      */
-    (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyze(gNPU0FIR);
+    (rN3_CHIPLET_UCS_FIR, bit(7)) ? analyzeNPU0FIR;
 
     /** N3_CHIPLET_UCS_FIR[8]
      *  Attention from NPU1FIR
@@ -6787,7 +6787,7 @@ group gNPU0FIR filter singlebit, cs_root_cause( 1, 2, 3, 4, 5, 6, 7, 9, 10, 16,
     /** NPU0FIR[19]
      *  CQ CTL/SM NVF NVLink fatal error
      */
-    (rNPU0FIR, bit(19)) ? nvLinkAssist;
+    (rNPU0FIR, bit(19)) ? self_th_1;
 
     /** NPU0FIR[20]
      *  spare
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_actions.rule b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_actions.rule
index 2ed66b637..23820b776 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_actions.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_actions.rule
@@ -115,12 +115,10 @@ actionclass pmRecovery
     threshold1;
 };
 
-/** Used for NVLINK errors (open power)
- *  which can be the cause of OPAL TIs
- */
-actionclass nvLinkAssist
+/** Special wrapper for NPU0FIR to collect extra FFDC */
+actionclass analyzeNPU0FIR
 {
-    capture(nvLinkErr);
-    self_th_1;
+    capture(npu0fir_ffdc);
+    analyze(gNPU0FIR);
 };
 
diff --git a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule
index afcf39977..6a6d644f0 100644
--- a/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule
+++ b/src/usr/diag/prdf/common/plat/p9/p9_proc_common_regs.rule
@@ -325,91 +325,643 @@
     };
 
     ############################################################################
-    # NPU CERR for NVLINK (open power systems)
+    # NPU CERR and debug registers for NVLINK and openCAPI
     ############################################################################
 
-    register NPU_0_0_CERR
+    register NPU_S0_CS_SM0_CERR_MSG0
     {
-        name        "NPU.STCK0.SM0.CERR";
+        name        "NPU.STCK0.CS.SM0.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011011;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM0_CERR_0
+    {
+        name        "NPU.STCK0.CS.SM0.MISC.CERR_FIRST0";
         scomaddr    0x05011017;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM0_CERR_1
+    {
+        name        "NPU.STCK0.CS.SM0.MISC.CERR_FIRST1";
+        scomaddr    0x05011018;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_0_1_CERR
+    register NPU_S0_CS_SM0_CERR_2
     {
-        name        "NPU.STCK0.SM1.CERR";
+        name        "NPU.STCK0.CS.SM0.MISC.CERR_FIRST2";
+        scomaddr    0x05011019;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM1_CERR_MSG0
+    {
+        name        "NPU.STCK0.CS.SM1.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011041;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM1_CERR_0
+    {
+        name        "NPU.STCK0.CS.SM1.MISC.CERR_FIRST0";
         scomaddr    0x05011047;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM1_CERR_1
+    {
+        name        "NPU.STCK0.CS.SM1.MISC.CERR_FIRST1";
+        scomaddr    0x05011048;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_0_2_CERR
+    register NPU_S0_CS_SM1_CERR_2
     {
-        name        "NPU.STCK0.SM2.CERR";
+        name        "NPU.STCK0.CS.SM1.MISC.CERR_FIRST2";
+        scomaddr    0x05011049;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM2_CERR_MSG0
+    {
+        name        "NPU.STCK0.CS.SM2.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011071;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM2_CERR_0
+    {
+        name        "NPU.STCK0.CS.SM2.MISC.CERR_FIRST0";
         scomaddr    0x05011077;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM2_CERR_1
+    {
+        name        "NPU.STCK0.CS.SM2.MISC.CERR_FIRST1";
+        scomaddr    0x05011078;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM2_CERR_2
+    {
+        name        "NPU.STCK0.CS.SM2.MISC.CERR_FIRST2";
+        scomaddr    0x05011079;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM3_CERR_MSG0
+    {
+        name        "NPU.STCK0.CS.SM3.MISC.CERR_MESSAGE0";
+        scomaddr    0x050110A1;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_0_3_CERR
+    register NPU_S0_CS_SM3_CERR_0
     {
-        name        "NPU.STCK0.SM3.CERR";
+        name        "NPU.STCK0.CS.SM3.MISC.CERR_FIRST0";
         scomaddr    0x050110A7;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM3_CERR_1
+    {
+        name        "NPU.STCK0.CS.SM3.MISC.CERR_FIRST1";
+        scomaddr    0x050110A8;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_SM3_CERR_2
+    {
+        name        "NPU.STCK0.CS.SM3.MISC.CERR_FIRST2";
+        scomaddr    0x050110A9;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_CTL_CERR_MSG0
+    {
+        name        "NPU.STCK0.CS.CTL.MISC.CERR_MESSAGE0";
+        scomaddr    0x050110D8;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_CTL_CERR_MSG1
+    {
+        name        "NPU.STCK0.CS.CTL.MISC.CERR_MESSAGE1";
+        scomaddr    0x050110D9;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_CTL_CERR_0
+    {
+        name        "NPU.STCK0.CS.CTL.MISC.CERR_FIRST0";
+        scomaddr    0x050110DA;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_CS_CTL_CERR_1
+    {
+        name        "NPU.STCK0.CS.CTL.MISC.CERR_FIRST1";
+        scomaddr    0x050110DB;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_DAT_CERR_ECC_HOLD
+    {
+        name        "NPU.STCK0.DAT.MISC.CERR_ECC_HOLD";
+        scomaddr    0x050110F4;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_DAT_CERR_ECC_MASK
+    {
+        name        "NPU.STCK0.DAT.MISC.CERR_ECC_MASK";
+        scomaddr    0x050110F5;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_DAT_CERR_ECC_
+    {
+        name        "NPU.STCK0.DAT.MISC.CERR_ECC_FIRST";
+        scomaddr    0x050110F6;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_DAT_CERR_LOG_HOLD
+    {
+        name        "NPU.STCK0.DAT.MISC.CERR_LOG_HOLD";
+        scomaddr    0x050110FA;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_DAT_REM0
+    {
+        name        "NPU.STCK0.DAT.MISC.REM0";
+        scomaddr    0x050110FD;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_DAT_REM1
+    {
+        name        "NPU.STCK0.DAT.MISC.REM1";
+        scomaddr    0x050110FE;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_NTL0_CERR_1
+    {
+        name        "NPU.STCK0.NTL0.REGS.CERR_FIRST1";
+        scomaddr    0x05011114;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_NTL0_CERR_2
+    {
+        name        "NPU.STCK0.NTL0.REGS.CERR_FIRST2";
+        scomaddr    0x05011118;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_NTL1_CERR_1
+    {
+        name        "NPU.STCK0.NTL1.REGS.CERR_FIRST1";
+        scomaddr    0x05011134;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S0_NTL1_CERR_2
+    {
+        name        "NPU.STCK0.NTL1.REGS.CERR_FIRST2";
+        scomaddr    0x05011138;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_1_0_CERR
+    register NPU_S1_CS_SM0_CERR_MSG0
     {
-        name        "NPU.STCK1.SM0.CERR";
+        name        "NPU.STCK1.CS.SM0.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011211;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM0_CERR_0
+    {
+        name        "NPU.STCK1.CS.SM0.MISC.CERR_FIRST0";
         scomaddr    0x05011217;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_1_1_CERR
+    register NPU_S1_CS_SM0_CERR_1
     {
-        name        "NPU.STCK1.SM1.CERR";
+        name        "NPU.STCK1.CS.SM0.MISC.CERR_FIRST1";
+        scomaddr    0x05011218;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM0_CERR_2
+    {
+        name        "NPU.STCK1.CS.SM0.MISC.CERR_FIRST2";
+        scomaddr    0x05011219;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM1_CERR_MSG0
+    {
+        name        "NPU.STCK1.CS.SM1.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011241;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM1_CERR_0
+    {
+        name        "NPU.STCK1.CS.SM1.MISC.CERR_FIRST0";
         scomaddr    0x05011247;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM1_CERR_1
+    {
+        name        "NPU.STCK1.CS.SM1.MISC.CERR_FIRST1";
+        scomaddr    0x05011248;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_1_2_CERR
+    register NPU_S1_CS_SM1_CERR_2
     {
-        name        "NPU.STCK1.SM2.CERR";
+        name        "NPU.STCK1.CS.SM1.MISC.CERR_FIRST2";
+        scomaddr    0x05011249;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM2_CERR_MSG0
+    {
+        name        "NPU.STCK1.CS.SM2.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011271;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM2_CERR_0
+    {
+        name        "NPU.STCK1.CS.SM2.MISC.CERR_FIRST0";
         scomaddr    0x05011277;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_1_3_CERR
+    register NPU_S1_CS_SM2_CERR_1
     {
-        name        "NPU.STCK1.SM3.CERR";
+        name        "NPU.STCK1.CS.SM2.MISC.CERR_FIRST1";
+        scomaddr    0x05011278;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM2_CERR_2
+    {
+        name        "NPU.STCK1.CS.SM2.MISC.CERR_FIRST2";
+        scomaddr    0x05011279;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM3_CERR_MSG0
+    {
+        name        "NPU.STCK1.CS.SM3.MISC.CERR_MESSAGE0";
+        scomaddr    0x050112A1;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM3_CERR_0
+    {
+        name        "NPU.STCK1.CS.SM3.MISC.CERR_FIRST0";
         scomaddr    0x050112A7;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM3_CERR_1
+    {
+        name        "NPU.STCK1.CS.SM3.MISC.CERR_FIRST1";
+        scomaddr    0x050112A8;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_SM3_CERR_2
+    {
+        name        "NPU.STCK1.CS.SM3.MISC.CERR_FIRST2";
+        scomaddr    0x050112A9;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_CTL_CERR_MSG0
+    {
+        name        "NPU.STCK1.CS.CTL.MISC.CERR_MESSAGE0";
+        scomaddr    0x050112D8;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_CTL_CERR_MSG1
+    {
+        name        "NPU.STCK1.CS.CTL.MISC.CERR_MESSAGE1";
+        scomaddr    0x050112D9;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_CTL_CERR_0
+    {
+        name        "NPU.STCK1.CS.CTL.MISC.CERR_FIRST0";
+        scomaddr    0x050112DA;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_CS_CTL_CERR_1
+    {
+        name        "NPU.STCK1.CS.CTL.MISC.CERR_FIRST1";
+        scomaddr    0x050112DB;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_DAT_CERR_ECC_HOLD
+    {
+        name        "NPU.STCK1.DAT.MISC.CERR_ECC_HOLD";
+        scomaddr    0x050112F4;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_DAT_CERR_ECC_MASK
+    {
+        name        "NPU.STCK1.DAT.MISC.CERR_ECC_MASK";
+        scomaddr    0x050112F5;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_DAT_CERR_ECC_
+    {
+        name        "NPU.STCK1.DAT.MISC.CERR_ECC_FIRST";
+        scomaddr    0x050112F6;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_DAT_CERR_LOG_HOLD
+    {
+        name        "NPU.STCK1.DAT.MISC.CERR_LOG_HOLD";
+        scomaddr    0x050112FA;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_DAT_REM0
+    {
+        name        "NPU.STCK1.DAT.MISC.REM0";
+        scomaddr    0x050112FD;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_2_0_CERR
+    register NPU_S1_DAT_REM1
     {
-        name        "NPU.STCK2.SM0.CERR";
+        name        "NPU.STCK1.DAT.MISC.REM1";
+        scomaddr    0x050112FE;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_NTL0_CERR_1
+    {
+        name        "NPU.STCK1.NTL0.REGS.CERR_FIRST1";
+        scomaddr    0x05011314;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_NTL0_CERR_2
+    {
+        name        "NPU.STCK1.NTL0.REGS.CERR_FIRST2";
+        scomaddr    0x05011318;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_NTL1_CERR_1
+    {
+        name        "NPU.STCK1.NTL1.REGS.CERR_FIRST1";
+        scomaddr    0x05011334;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S1_NTL1_CERR_2
+    {
+        name        "NPU.STCK1.NTL1.REGS.CERR_FIRST2";
+        scomaddr    0x05011338;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM0_CERR_MSG0
+    {
+        name        "NPU.STCK2.CS.SM0.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011411;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM0_CERR_0
+    {
+        name        "NPU.STCK2.CS.SM0.MISC.CERR_FIRST0";
         scomaddr    0x05011417;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_2_1_CERR
+    register NPU_S2_CS_SM0_CERR_1
     {
-        name        "NPU.STCK2.SM1.CERR";
+        name        "NPU.STCK2.CS.SM0.MISC.CERR_FIRST1";
+        scomaddr    0x05011418;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM0_CERR_2
+    {
+        name        "NPU.STCK2.CS.SM0.MISC.CERR_FIRST2";
+        scomaddr    0x05011419;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM1_CERR_MSG0
+    {
+        name        "NPU.STCK2.CS.SM1.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011441;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM1_CERR_0
+    {
+        name        "NPU.STCK2.CS.SM1.MISC.CERR_FIRST0";
         scomaddr    0x05011447;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM1_CERR_1
+    {
+        name        "NPU.STCK2.CS.SM1.MISC.CERR_FIRST1";
+        scomaddr    0x05011448;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM1_CERR_2
+    {
+        name        "NPU.STCK2.CS.SM1.MISC.CERR_FIRST2";
+        scomaddr    0x05011449;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM2_CERR_MSG0
+    {
+        name        "NPU.STCK2.CS.SM2.MISC.CERR_MESSAGE0";
+        scomaddr    0x05011471;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_2_2_CERR
+    register NPU_S2_CS_SM2_CERR_0
     {
-        name        "NPU.STCK2.SM2.CERR";
+        name        "NPU.STCK2.CS.SM2.MISC.CERR_FIRST0";
         scomaddr    0x05011477;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
     };
 
-    register NPU_2_3_CERR
+    register NPU_S2_CS_SM2_CERR_1
     {
-        name        "NPU.STCK2.SM3.CERR";
+        name        "NPU.STCK2.CS.SM2.MISC.CERR_FIRST1";
+        scomaddr    0x05011478;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM2_CERR_2
+    {
+        name        "NPU.STCK2.CS.SM2.MISC.CERR_FIRST2";
+        scomaddr    0x05011479;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM3_CERR_MSG0
+    {
+        name        "NPU.STCK2.CS.SM3.MISC.CERR_MESSAGE0";
+        scomaddr    0x050114A1;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM3_CERR_0
+    {
+        name        "NPU.STCK2.CS.SM3.MISC.CERR_FIRST0";
         scomaddr    0x050114A7;
-        capture     group nvLinkErr;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM3_CERR_1
+    {
+        name        "NPU.STCK2.CS.SM3.MISC.CERR_FIRST1";
+        scomaddr    0x050114A8;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_SM3_CERR_2
+    {
+        name        "NPU.STCK2.CS.SM3.MISC.CERR_FIRST2";
+        scomaddr    0x050114A9;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_CTL_CERR_MSG0
+    {
+        name        "NPU.STCK2.CS.CTL.MISC.CERR_MESSAGE0";
+        scomaddr    0x050114D8;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_CTL_CERR_MSG1
+    {
+        name        "NPU.STCK2.CS.CTL.MISC.CERR_MESSAGE1";
+        scomaddr    0x050114D9;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_CTL_CERR_0
+    {
+        name        "NPU.STCK2.CS.CTL.MISC.CERR_FIRST0";
+        scomaddr    0x050114DA;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_CS_CTL_CERR_1
+    {
+        name        "NPU.STCK2.CS.CTL.MISC.CERR_FIRST1";
+        scomaddr    0x050114DB;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_DAT_CERR_ECC_HOLD
+    {
+        name        "NPU.STCK2.DAT.MISC.CERR_ECC_HOLD";
+        scomaddr    0x050114F4;
+        capture     group npu0fir_ffdc;
     };
 
+    register NPU_S2_DAT_CERR_ECC_MASK
+    {
+        name        "NPU.STCK2.DAT.MISC.CERR_ECC_MASK";
+        scomaddr    0x050114F5;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_DAT_CERR_ECC_
+    {
+        name        "NPU.STCK2.DAT.MISC.CERR_ECC_FIRST";
+        scomaddr    0x050114F6;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_DAT_CERR_LOG_HOLD
+    {
+        name        "NPU.STCK2.DAT.MISC.CERR_LOG_HOLD";
+        scomaddr    0x050114FA;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_DAT_REM0
+    {
+        name        "NPU.STCK2.DAT.MISC.REM0";
+        scomaddr    0x050114FD;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_DAT_REM1
+    {
+        name        "NPU.STCK2.DAT.MISC.REM1";
+        scomaddr    0x050114FE;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_NTL0_CERR_1
+    {
+        name        "NPU.STCK2.NTL0.REGS.CERR_FIRST1";
+        scomaddr    0x05011514;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_NTL0_CERR_2
+    {
+        name        "NPU.STCK2.NTL0.REGS.CERR_FIRST2";
+        scomaddr    0x05011518;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_NTL1_CERR_1
+    {
+        name        "NPU.STCK2.NTL1.REGS.CERR_FIRST1";
+        scomaddr    0x05011534;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_S2_NTL1_CERR_2
+    {
+        name        "NPU.STCK2.NTL1.REGS.CERR_FIRST2";
+        scomaddr    0x05011538;
+        capture     group npu0fir_ffdc;
+    };
+
+    register NPU_XTS_REG_ERR_HOLD
+    {
+        name        "NPU.XTS.REG.ERR_HOLD";
+        scomaddr    0x05011640;
+        capture     group npu0fir_ffdc;
+    };
 
diff --git a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
index f9623a2f9..4bfe1de7c 100644
--- a/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
+++ b/src/usr/diag/prdf/occ_firdata/prdfWriteHomerFirData.C
@@ -309,20 +309,47 @@ void getAddresses( TrgtMap_t & io_targMap )
         0x04040018, // N2_CHIPLET_UCS_FIR
         0x04040019, // N2_CHIPLET_UCS_FIR_MASK
 
-        0x05011017, // NPU_STCK0_SM0_CERR
-        0x05011047, // NPU_STCK0_SM1_CERR
-        0x05011077, // NPU_STCK0_SM2_CERR
-        0x050110A7, // NPU_STCK0_SM3_CERR
-
-        0x05011217, // NPU_STCK1_SM0_CERR
-        0x05011247, // NPU_STCK1_SM1_CERR
-        0x05011277, // NPU_STCK1_SM2_CERR
-        0x050112A7, // NPU_STCK1_SM3_CERR
-
-        0x05011417, // NPU_STCK2_SM0_CERR
-        0x05011447, // NPU_STCK2_SM1_CERR
-        0x05011477, // NPU_STCK2_SM2_CERR
-        0x050114A7, // NPU_STCK2_SM3_CERR
+        // There are over 90 registers captured for NPU0FIR, but that is too
+        // much for the limited space in the OP checkstop analysis design. The
+        // hardware team agreed this was the minimum set of registers needed
+        // for a checkstop. We have also been told most of these should have a
+        // zero value so they should not take up too much space.
+        0x05011018, // NPU_S0_CS_SM0_CERR_1
+        0x05011019, // NPU_S0_CS_SM0_CERR_2
+        0x05011048, // NPU_S0_CS_SM1_CERR_1
+        0x05011049, // NPU_S0_CS_SM1_CERR_2
+        0x05011078, // NPU_S0_CS_SM2_CERR_1
+        0x05011079, // NPU_S0_CS_SM2_CERR_2
+        0x050110A8, // NPU_S0_CS_SM3_CERR_1
+        0x050110A9, // NPU_S0_CS_SM3_CERR_2
+        0x050110DB, // NPU_S0_CS_CTL_CERR_1
+        0x050110FA, // NPU_S0_DAT_CERR_LOG_HOLD
+        0x050110FD, // NPU_S0_DAT_REM0
+        0x050110FE, // NPU_S0_DAT_REM1
+        0x05011218, // NPU_S1_CS_SM0_CERR_1
+        0x05011219, // NPU_S1_CS_SM0_CERR_2
+        0x05011248, // NPU_S1_CS_SM1_CERR_1
+        0x05011249, // NPU_S1_CS_SM1_CERR_2
+        0x05011278, // NPU_S1_CS_SM2_CERR_1
+        0x05011279, // NPU_S1_CS_SM2_CERR_2
+        0x050112A8, // NPU_S1_CS_SM3_CERR_1
+        0x050112A9, // NPU_S1_CS_SM3_CERR_2
+        0x050112DB, // NPU_S1_CS_CTL_CERR_1
+        0x050112FA, // NPU_S1_DAT_CERR_LOG_HOLD
+        0x050112FD, // NPU_S1_DAT_REM0
+        0x050112FE, // NPU_S1_DAT_REM1
+        0x05011418, // NPU_S2_CS_SM0_CERR_1
+        0x05011419, // NPU_S2_CS_SM0_CERR_2
+        0x05011448, // NPU_S2_CS_SM1_CERR_1
+        0x05011449, // NPU_S2_CS_SM1_CERR_2
+        0x05011478, // NPU_S2_CS_SM2_CERR_1
+        0x05011479, // NPU_S2_CS_SM2_CERR_2
+        0x050114A8, // NPU_S2_CS_SM3_CERR_1
+        0x050114A9, // NPU_S2_CS_SM3_CERR_2
+        0x050114DB, // NPU_S2_CS_CTL_CERR_1
+        0x050114FA, // NPU_S2_DAT_CERR_LOG_HOLD
+        0x050114FD, // NPU_S2_DAT_REM0
+        0x050114FE, // NPU_S2_DAT_REM1
 
         0x05040000, // N3_CHIPLET_CS_FIR
         0x05040001, // N3_CHIPLET_RE_FIR