PRD: Initial Axone rule files

Change-Id: I46993aa204f525e84b42eaad861cd12154430ec7
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68739
Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com>
Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68846
Tested-by: Jenkins OP Build CI <op-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins OP HW <op-hw-jenkins+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>

1 files changed, 904 insertions, 0 deletions

diff --git a/src/usr/diag/prdf/common/plat/axone/axone_ex.rule b/src/usr/diag/prdf/common/plat/axone/axone_ex.rule
new file mode 100644
index 000000000..c943add56
--- /dev/null
+++ b/src/usr/diag/prdf/common/plat/axone/axone_ex.rule
@@ -0,0 +1,904 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: src/usr/diag/prdf/common/plat/axone/axone_ex.rule $
+#
+# OpenPOWER HostBoot Project
+#
+# Contributors Listed Below - COPYRIGHT 2018
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+
+chip axone_ex
+{
+    name        "AXONE EX target";
+    targettype  TYPE_EX;
+    sigoff      0x0000;
+    dump        DUMP_CONTENT_HW;
+    scomlen     64;
+
+# Import signatures
+.include "prdfP9ExExtraSig.H";
+
+ #############################################################################
+ #                                                                           #
+ #  ######                                                                   #
+ #  #     #  ######   ####     ###    ####    #####  ######  #####    ####   #
+ #  #     #  #       #    #     #    #          #    #       #    #  #       #
+ #  ######   #####   #          #     ####      #    #####   #    #   ####   #
+ #  #   #    #       #  ###     #         #     #    #       #####        #  #
+ #  #    #   #       #    #     #    #    #     #    #       #   #   #    #  #
+ #  #     #  ######   ####     ###    ####      #    ######  #    #   ####   #
+ #                                                                           #
+ #############################################################################
+
+    ############################################################################
+    # P9 EX target L2FIR
+    ############################################################################
+
+    register L2FIR
+    {
+        name        "P9 EX target L2FIR";
+        scomaddr    0x10010800;
+        reset       (&, 0x10010801);
+        mask        (|, 0x10010805);
+        capture     group default;
+    };
+
+    register L2FIR_MASK
+    {
+        name        "P9 EX target L2FIR MASK";
+        scomaddr    0x10010803;
+        capture     group default;
+    };
+
+    register L2FIR_ACT0
+    {
+        name        "P9 EX target L2FIR ACT0";
+        scomaddr    0x10010806;
+        capture     group default;
+        capture     req nonzero("L2FIR");
+    };
+
+    register L2FIR_ACT1
+    {
+        name        "P9 EX target L2FIR ACT1";
+        scomaddr    0x10010807;
+        capture     group default;
+        capture     req nonzero("L2FIR");
+    };
+
+    ############################################################################
+    # P9 EX target NCUFIR
+    ############################################################################
+
+    register NCUFIR
+    {
+        name        "P9 EX target NCUFIR";
+        scomaddr    0x10011000;
+        reset       (&, 0x10011001);
+        mask        (|, 0x10011005);
+        capture     group default;
+    };
+
+    register NCUFIR_MASK
+    {
+        name        "P9 EX target NCUFIR MASK";
+        scomaddr    0x10011003;
+        capture     group default;
+    };
+
+    register NCUFIR_ACT0
+    {
+        name        "P9 EX target NCUFIR ACT0";
+        scomaddr    0x10011006;
+        capture     group default;
+        capture     req nonzero("NCUFIR");
+    };
+
+    register NCUFIR_ACT1
+    {
+        name        "P9 EX target NCUFIR ACT1";
+        scomaddr    0x10011007;
+        capture     group default;
+        capture     req nonzero("NCUFIR");
+    };
+
+    ############################################################################
+    # P9 EX target L3FIR
+    ############################################################################
+
+    register L3FIR
+    {
+        name        "P9 EX target L3FIR";
+        scomaddr    0x10011800;
+        reset       (&, 0x10011801);
+        mask        (|, 0x10011805);
+        capture     group default;
+    };
+
+    register L3FIR_MASK
+    {
+        name        "P9 EX target L3FIR MASK";
+        scomaddr    0x10011803;
+        capture     group default;
+    };
+
+    register L3FIR_ACT0
+    {
+        name        "P9 EX target L3FIR ACT0";
+        scomaddr    0x10011806;
+        capture     group default;
+        capture     req nonzero("L3FIR");
+    };
+
+    register L3FIR_ACT1
+    {
+        name        "P9 EX target L3FIR ACT1";
+        scomaddr    0x10011807;
+        capture     group default;
+        capture     req nonzero("L3FIR");
+    };
+
+    ############################################################################
+    # P9 EX target CMEFIR
+    ############################################################################
+
+    register CMEFIR
+    {
+        name        "P9 EX target CMEFIR";
+        scomaddr    0x10012000;
+        reset       (&, 0x10012001);
+        mask        (|, 0x10012005);
+        capture     group default;
+    };
+
+    register CMEFIR_MASK
+    {
+        name        "P9 EX target CMEFIR MASK";
+        scomaddr    0x10012003;
+        capture     group default;
+    };
+
+    register CMEFIR_ACT0
+    {
+        name        "P9 EX target CMEFIR ACT0";
+        scomaddr    0x10012006;
+        capture     group default;
+        capture     req nonzero("CMEFIR");
+    };
+
+    register CMEFIR_ACT1
+    {
+        name        "P9 EX target CMEFIR ACT1";
+        scomaddr    0x10012007;
+        capture     group default;
+        capture     req nonzero("CMEFIR");
+    };
+
+# Include registers not defined by the xml
+.include "p9_common_ex_regs.rule";
+
+};
+
+ ##############################################################################
+ #                                                                            #
+ # ####                                 #                                     #
+ # #   # #   # #    #####  ###      #  # #    ##  ##### ###  ###  #   #  ###  #
+ # #   # #   # #    #     #        #  #   #  #  #   #    #  #   # ##  # #     #
+ # ####  #   # #    ####   ###    #  ####### #      #    #  #   # # # #  ###  #
+ # #  #  #   # #    #         #  #   #     # #  #   #    #  #   # #  ##     # #
+ # #   #  ###  #### #####  ###  #    #     #  ##    #   ###  ###  #   #  ###  #
+ #                                                                            #
+ ##############################################################################
+
+################################################################################
+# Summary for EX
+################################################################################
+
+rule rEX
+{
+  CHECK_STOP:
+    summary( 0, rL2FIR ) |
+    summary( 1, rNCUFIR ) |
+    summary( 2, rL3FIR ) |
+    summary( 3, rCMEFIR );
+
+  RECOVERABLE:
+    summary( 0, rL2FIR ) |
+    summary( 1, rNCUFIR ) |
+    summary( 2, rL3FIR ) |
+    summary( 3, rCMEFIR );
+
+};
+
+group gEX attntype CHECK_STOP, RECOVERABLE
+    filter singlebit
+{
+    (rEX, bit(0)) ? analyzeL2FIR;
+    (rEX, bit(1)) ? analyzeNCUFIR;
+    (rEX, bit(2)) ? analyzeL3FIR;
+    (rEX, bit(3)) ? analyzeCMEFIR;
+};
+
+################################################################################
+# P9 EX target L2FIR
+################################################################################
+
+rule rL2FIR
+{
+  CHECK_STOP:
+    L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 & ~L2FIR_ACT1;
+  RECOVERABLE:
+    L2FIR & ~L2FIR_MASK & ~L2FIR_ACT0 &  L2FIR_ACT1;
+};
+
+group gL2FIR
+    filter singlebit,
+           cs_root_cause(1,17,18,20)
+{
+    /** L2FIR[0]
+     *  L2 cache read CE
+     */
+    (rL2FIR, bit(0)) ? l2_cache_ce;
+
+    /** L2FIR[1]
+     *  L2 cache read UE
+     */
+    (rL2FIR, bit(1)) ? l2_cache_ue_UERE;
+
+    /** L2FIR[2]
+     *  L2 cache read SUE
+     */
+    (rL2FIR, bit(2)) ? defaultMaskedError;
+
+    /** L2FIR[3]
+     *  Hw directory initiated line delete
+     */
+    (rL2FIR, bit(3)) ? defaultMaskedError;
+
+    /** L2FIR[4]
+     *  ue or sue detected by on modified line
+     */
+    (rL2FIR, bit(4)) ? defaultMaskedError;
+
+    /** L2FIR[5]
+     *  ue or sue detected on non-modified line
+     */
+    (rL2FIR, bit(5)) ? defaultMaskedError;
+
+    /** L2FIR[6]
+     *  L2 directory read CE
+     */
+    (rL2FIR, bit(6)) ? l2_dir_ce;
+
+    /** L2FIR[7]
+     *  L2 directory read UE
+     */
+    (rL2FIR, bit(7)) ? self_th_1;
+
+    /** L2FIR[8]
+     *  L2 directory CE due to stuck bit
+     */
+    (rL2FIR, bit(8)) ? self_th_1;
+
+    /** L2FIR[9]
+     *  L2 directory stuck bit CE repair failed
+     */
+    (rL2FIR, bit(9)) ? self_th_1;
+
+    /** L2FIR[10]
+     *  Muliple l2 cache dir errors
+     */
+    (rL2FIR, bit(10)) ? defaultMaskedError;
+
+    /** L2FIR[11]
+     *  LRU read error detected
+     */
+    (rL2FIR, bit(11)) ? self_th_32perDay;
+
+    /** L2FIR[12]
+     *  RC Powerbus data timeout
+     */
+    (rL2FIR, bit(12)) ? level2_th_1;
+
+    /** L2FIR[13]
+     *  NCU Powerbus data timeout
+     */
+    (rL2FIR, bit(13)) ? level2_th_1;
+
+    /** L2FIR[14]
+     *  Hardware control error
+     */
+    (rL2FIR, bit(14)) ? level2_M_proc_L_th_1;
+
+    /** L2FIR[15]
+     *  LRU all members in a class line deleted
+     */
+    (rL2FIR, bit(15)) ? self_th_1;
+
+    /** L2FIR[16]
+     *  Cache line inhibited hit cacheable space
+     */
+    (rL2FIR, bit(16)) ? self_th_1;
+
+    /** L2FIR[17]
+     *  (RC) load received pb cresp addr error
+     */
+    (rL2FIR, bit(17)) ? self_M_level2_L_th_1;
+
+    /** L2FIR[18]
+     *  (RC) store received pb cresp addr error
+     */
+    (rL2FIR, bit(18)) ? self_M_level2_L_th_1;
+
+    /** L2FIR[19]
+     *  Rc or NCU Pb data CE error
+     */
+    (rL2FIR, bit(19)) ? l2_power_bus_ce;
+
+    /** L2FIR[20]
+     *  RC or NCU Pb data UE error
+     */
+    (rL2FIR, bit(20)) ? self_th_1_UERE;
+
+    /** L2FIR[21]
+     *  RC or NCU PB data SUE detected
+     */
+    (rL2FIR, bit(21)) ? defaultMaskedError;
+
+    /** L2FIR[22]
+     *  TGT_NODAL_REQ_DINC_ERR
+     */
+    (rL2FIR, bit(22)) ? self_th_1;
+
+    /** L2FIR[23]
+     *  RC fabric op Ld cresp addr error for hyp
+     */
+    (rL2FIR, bit(23)) ? defaultMaskedError;
+
+    /** L2FIR[24]
+     *  PE on data from RCDAT
+     */
+    (rL2FIR, bit(24)) ? self_th_1;
+
+    /** L2FIR[25]
+     *  L2 castout or CN cresp addr err
+     */
+    (rL2FIR, bit(25)) ? self_M_level2_L_th_1;
+
+    /** L2FIR[26]
+     *  LVDIR tracking PE
+     */
+    (rL2FIR, bit(26)) ? self_th_32perDay;
+
+    /** L2FIR[27]
+     *  RC fabric op cresp=ack_dead error
+     */
+    (rL2FIR, bit(27)) ? defaultMaskedError;
+
+    /** L2FIR[28]
+     *  Darn data timeout
+     */
+    (rL2FIR, bit(28)) ? self_th_1;
+
+    /** L2FIR[29]
+     *  RC fabric op store cresp/misc error
+     */
+    (rL2FIR, bit(29)) ? defaultMaskedError;
+
+    /** L2FIR[30:35]
+     *  spare
+     */
+    (rL2FIR, bit(30|31|32|33|34|35)) ? defaultMaskedError;
+
+    /** L2FIR[36]
+     *  Cache CE and UE in short time period
+     */
+    (rL2FIR, bit(36)) ? threshold_and_mask_self;
+
+    /** L2FIR[37:38]
+     *  spare
+     */
+    (rL2FIR, bit(37|38)) ? defaultMaskedError;
+
+    /** L2FIR[39]
+     *  reserved
+     */
+    (rL2FIR, bit(39)) ? defaultMaskedError;
+
+    /** L2FIR[40]
+     *  scom error
+     */
+    (rL2FIR, bit(40)) ? defaultMaskedError;
+
+    /** L2FIR[41]
+     *  scom error
+     */
+    (rL2FIR, bit(41)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# P9 EX target NCUFIR
+################################################################################
+
+rule rNCUFIR
+{
+  CHECK_STOP:
+    NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 & ~NCUFIR_ACT1;
+  RECOVERABLE:
+    NCUFIR & ~NCUFIR_MASK & ~NCUFIR_ACT0 &  NCUFIR_ACT1;
+};
+
+group gNCUFIR
+    filter singlebit,
+           cs_root_cause(3,4,7,8)
+{
+    /** NCUFIR[0]
+     *  NCU store queue control error
+     */
+    (rNCUFIR, bit(0)) ? self_th_1;
+
+    /** NCUFIR[1]
+     *  TLBIE control error.
+     */
+    (rNCUFIR, bit(1)) ? level2_M_self_L_th_1;
+
+    /** NCUFIR[2]
+     *  TL or SLBIEG illegal fields from core.
+     */
+    (rNCUFIR, bit(2)) ? level2_M_self_L_th_1;
+
+    /** NCUFIR[3]
+     *  NCU Store Address Error
+     */
+    (rNCUFIR, bit(3)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[4]
+     *  NCU load Address Error
+     */
+    (rNCUFIR, bit(4)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[5]
+     *  Store received ack_dead.
+     */
+    (rNCUFIR, bit(5)) ? defaultMaskedError;
+
+    /** NCUFIR[6]
+     *  Load received ack_dead.
+     */
+    (rNCUFIR, bit(6)) ? defaultMaskedError;
+
+    /** NCUFIR[7]
+     *  MSGSND received addr_err
+     */
+    (rNCUFIR, bit(7)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[8]
+     *  NCU Store Queue Data Parity Err
+     */
+    (rNCUFIR, bit(8)) ? self_th_1_UERE;
+
+    /** NCUFIR[9]
+     *  store timed out on pb
+     */
+    (rNCUFIR, bit(9)) ? threshold_and_mask_self;
+
+    /** NCUFIR[10]
+     *  tlbie master timeout
+     */
+    (rNCUFIR, bit(10)) ? level2_M_self_L_th_1;
+
+    /** NCUFIR[11]
+     *  NCU no response to snooped TLBIE
+     */
+    (rNCUFIR, bit(11)) ? level2_M_self_L_th_1;
+
+    /** NCUFIR[12]
+     *  ima cresp addr error
+     */
+    (rNCUFIR, bit(12)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[13]
+     *  ima received ack_dead
+     */
+    (rNCUFIR, bit(13)) ? defaultMaskedError;
+
+    /** NCUFIR[14]
+     *  pmisc cresp addr err
+     */
+    (rNCUFIR, bit(14)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[15]
+     *  PPE read cresp address error
+     */
+    (rNCUFIR, bit(15)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[16]
+     *  PPE write cresp address error
+     */
+    (rNCUFIR, bit(16)) ? self_M_level2_L_th_1;
+
+    /** NCUFIR[17]
+     *  ppe read received ack dead
+     */
+    (rNCUFIR, bit(17)) ? defaultMaskedError;
+
+    /** NCUFIR[18]
+     *  ppe write received ack dead
+     */
+    (rNCUFIR, bit(18)) ? defaultMaskedError;
+
+    /** NCUFIR[19]
+     *  tgt nodal ppe write received ack dead
+     */
+    (rNCUFIR, bit(19)) ? defaultMaskedError;
+
+    /** NCUFIR[20]
+     *  darn ttype while darn not enabled
+     */
+    (rNCUFIR, bit(20)) ? level2_M_self_L_th_1;
+
+    /** NCUFIR[21]
+     *  Darn cresp address error
+     */
+    (rNCUFIR, bit(21)) ? level2_M_self_L_th_1;
+
+    /** NCUFIR[22:28]
+     *  spare
+     */
+    (rNCUFIR, bit(22|23|24|25|26|27|28)) ? defaultMaskedError;
+
+    /** NCUFIR[29]
+     *  scom error
+     */
+    (rNCUFIR, bit(29)) ? defaultMaskedError;
+
+    /** NCUFIR[30]
+     *  scom error
+     */
+    (rNCUFIR, bit(30)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# P9 EX target L3FIR
+################################################################################
+
+rule rL3FIR
+{
+  CHECK_STOP:
+    L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 & ~L3FIR_ACT1;
+  RECOVERABLE:
+    L3FIR & ~L3FIR_MASK & ~L3FIR_ACT0 &  L3FIR_ACT1;
+};
+
+group gL3FIR
+    filter singlebit,
+           cs_root_cause(5,8,11,17,21)
+{
+    /** L3FIR[0]
+     *  L3_RDDSP_SEGR_LCO_ALL_MEM_UNAVAIL_ERR
+     */
+    (rL3FIR, bit(0)) ? self_th_1;
+
+    /** L3FIR[1:2]
+     *  spare
+     */
+    (rL3FIR, bit(1|2)) ? defaultMaskedError;
+
+    /** L3FIR[3]
+     *  L3 cache CE and UE within a short period
+     */
+    (rL3FIR, bit(3)) ? threshold_and_mask_self;
+
+    /** L3FIR[4]
+     *  CE detected on L3 cache read
+     */
+    (rL3FIR, bit(4)) ? l3_cache_ce;
+
+    /** L3FIR[5]
+     *  UE detected on L3 cache read
+     */
+    (rL3FIR, bit(5)) ? l3_cache_ue_UERE;
+
+    /** L3FIR[6]
+     *  SUE detected on L3 cache read
+     */
+    (rL3FIR, bit(6)) ? defaultMaskedError;
+
+    /** L3FIR[7]
+     *  L3 cache write data CE from Power Bus
+     */
+    (rL3FIR, bit(7)) ? self_th_32perDay;
+
+    /** L3FIR[8]
+     *  L3 cache write data UE from Power Bus
+     */
+    (rL3FIR, bit(8)) ? self_th_1_UERE;
+
+    /** L3FIR[9]
+     *  L3 cache write data sue from Power Bus
+     */
+    (rL3FIR, bit(9)) ? defaultMaskedError;
+
+    /** L3FIR[10]
+     *  L3 cache write data CE from L2
+     */
+    (rL3FIR, bit(10)) ? self_th_32perDay;
+
+    /** L3FIR[11]
+     *  L3 cache write data UE from L2
+     */
+    (rL3FIR, bit(11)) ? l3_cache_ue_UERE;
+
+    /** L3FIR[12]
+     *  L3 cache write SUE from L2
+     */
+    (rL3FIR, bit(12)) ? defaultMaskedError;
+
+    /** L3FIR[13]
+     *  L3 DIR read CE
+     */
+    (rL3FIR, bit(13)) ? l3_dir_ce;
+
+    /** L3FIR[14]
+     *  L3 Dir read UE
+     */
+    (rL3FIR, bit(14)) ? self_th_1;
+
+    /** L3FIR[15]
+     *  Dir error not found during corr seq.
+     */
+    (rL3FIR, bit(15)) ? defaultMaskedError;
+
+    /** L3FIR[16]
+     *  addr_error cresp for mem SN or CO
+     */
+    (rL3FIR, bit(16)) ? self_M_level2_L_th_1;
+
+    /** L3FIR[17]
+     *  Received addr_error cresp for Prefetch
+     */
+    (rL3FIR, bit(17)) ? self_M_level2_L_th_1;
+
+    /** L3FIR[18]
+     *  An L3 machine hung waiting for PB cresp
+     */
+    (rL3FIR, bit(18)) ? defaultMaskedError;
+
+    /** L3FIR[19]
+     *  Invalid LRU count error
+     */
+    (rL3FIR, bit(19)) ? defaultMaskedError;
+
+    /** L3FIR[20]
+     *  CE detected on PowerBus read for PPE
+     */
+    (rL3FIR, bit(20)) ? self_th_32perDay;
+
+    /** L3FIR[21]
+     *  UE detected on PowerBus read for PPE
+     */
+    (rL3FIR, bit(21)) ? self_th_1_UERE;
+
+    /** L3FIR[22]
+     *  L3 PPE SUE
+     */
+    (rL3FIR, bit(22)) ? defaultMaskedError;
+
+    /** L3FIR[23]
+     *  L3 mach hang
+     */
+    (rL3FIR, bit(23)) ? self_M_level2_L_th_1;
+
+    /** L3FIR[24]
+     *  L3 Hw control err
+     */
+    (rL3FIR, bit(24)) ? self_th_1;
+
+    /** L3FIR[25]
+     *  Cache inhitited op in L3 directory
+     */
+    (rL3FIR, bit(25)) ? self_M_level2_L_th_1;
+
+    /** L3FIR[26]
+     *  L3 line delete CE done
+     */
+    (rL3FIR, bit(26)) ? defaultMaskedError;
+
+    /** L3FIR[27]
+     *  L3 DRAM logic error
+     */
+    (rL3FIR, bit(27)) ? self_th_1;
+
+    /** L3FIR[28]
+     *  L3 LRU array parity error
+     */
+    (rL3FIR, bit(28)) ? l3_lru_parity_error;
+
+    /** L3FIR[29]
+     *  L3 cache congruence class deleted
+     */
+    (rL3FIR, bit(29)) ? self_th_1;
+
+    /** L3FIR[30]
+     *  L3 cache timer refresh error
+     */
+    (rL3FIR, bit(30)) ? self_th_1;
+
+    /** L3FIR[31]
+     *  L3 PowerBus Master Write CRESP ack_dead
+     */
+    (rL3FIR, bit(31)) ? defaultMaskedError;
+
+    /** L3FIR[32]
+     *  PB Master Read received ack_dead CRESP
+     */
+    (rL3FIR, bit(32)) ? defaultMaskedError;
+
+    /** L3FIR[33]
+     *  scom error
+     */
+    (rL3FIR, bit(33)) ? defaultMaskedError;
+
+    /** L3FIR[34]
+     *  scom error
+     */
+    (rL3FIR, bit(34)) ? defaultMaskedError;
+
+};
+
+################################################################################
+# P9 EX target CMEFIR
+################################################################################
+
+rule rCMEFIR
+{
+  CHECK_STOP:
+    CMEFIR & ~CMEFIR_MASK & ~CMEFIR_ACT0 & ~CMEFIR_ACT1;
+  RECOVERABLE:
+    CMEFIR & ~CMEFIR_MASK & ~CMEFIR_ACT0 &  CMEFIR_ACT1;
+};
+
+group gCMEFIR
+    filter singlebit,
+           cs_root_cause
+{
+    /** CMEFIR[0]
+     *  PPE asserted an internal error
+     */
+    (rCMEFIR, bit(0)) ? TBDDefaultCallout;
+
+    /** CMEFIR[1]
+     *  PPE  external interface error
+     */
+    (rCMEFIR, bit(1)) ? TBDDefaultCallout;
+
+    /** CMEFIR[2]
+     *  PPE  lack of forward progress
+     */
+    (rCMEFIR, bit(2)) ? TBDDefaultCallout;
+
+    /** CMEFIR[3]
+     *  PPE software-requested breakpoint event.
+     */
+    (rCMEFIR, bit(3)) ? TBDDefaultCallout;
+
+    /** CMEFIR[4]
+     *  PPE watchdog timeout
+     */
+    (rCMEFIR, bit(4)) ? TBDDefaultCallout;
+
+    /** CMEFIR[5]
+     *  PPE asserted a halt condition.
+     */
+    (rCMEFIR, bit(5)) ? defaultMaskedError;
+
+    /** CMEFIR[6]
+     *  PPE asserted a debug trigger
+     */
+    (rCMEFIR, bit(6)) ? defaultMaskedError;
+
+    /** CMEFIR[7]
+     *  PPE SRAM Uncorrectable Error.
+     */
+    (rCMEFIR, bit(7)) ? self_th_1;
+
+    /** CMEFIR[8]
+     *  SRAM Correctable Error
+     */
+    (rCMEFIR, bit(8)) ? threshold_and_mask_self;
+
+    /** CMEFIR[9]
+     *  Scrub timer tick, scrub still pending
+     */
+    (rCMEFIR, bit(9)) ? threshold_and_mask_self;
+
+    /** CMEFIR[10]
+     *  Block Copy Engine Error
+     */
+    (rCMEFIR, bit(10)) ? defaultMaskedError;
+
+    /** CMEFIR[11:12]
+     *  spare
+     */
+    (rCMEFIR, bit(11|12)) ? defaultMaskedError;
+
+    /** CMEFIR[13]
+     *  Dropout detected on Core0 Chiplet iVRM
+     */
+    (rCMEFIR, bit(13)) ? defaultMaskedError;
+
+    /** CMEFIR[14]
+     *  Dropout detected on Core1 Chiplet iVRM
+     */
+    (rCMEFIR, bit(14)) ? defaultMaskedError;
+
+    /** CMEFIR[15]
+     *  CME Dropout Cache Chiplet iVRM.
+     */
+    (rCMEFIR, bit(15)) ? defaultMaskedError;
+
+    /** CMEFIR[16]
+     *  CME Extreme Droop over time exceeded
+     */
+    (rCMEFIR, bit(16)) ? defaultMaskedError;
+
+    /** CMEFIR[17]
+     *  CME Large Droop exceeded
+     */
+    (rCMEFIR, bit(17)) ? defaultMaskedError;
+
+    /** CMEFIR[18]
+     *  CME Small Droop exceeded
+     */
+    (rCMEFIR, bit(18)) ? defaultMaskedError;
+
+    /** CMEFIR[19]
+     *  Detected non-thermometer code
+     */
+    (rCMEFIR, bit(19)) ? defaultMaskedError;
+
+    /** CMEFIR[20]
+     *  scom error
+     */
+    (rCMEFIR, bit(20)) ? defaultMaskedError;
+
+    /** CMEFIR[21]
+     *  scom error
+     */
+    (rCMEFIR, bit(21)) ? defaultMaskedError;
+
+};
+
+ ##############################################################################
+ #                                                                            #
+ #    #                                  ###                                  #
+ #   # #    ##  ##### ###  ###  #   #   #   # #     #    ###   ###  ###  ###  #
+ #  #   #  #  #   #    #  #   # ##  #   #     #    # #  #     #     #   #     #
+ # ####### #      #    #  #   # # # #   #     #   #####  ###   ###  ##   ###  #
+ # #     # #  #   #    #  #   # #  ##   #   # #   #   #     #     # #       # #
+ # #     #  ##    #   ###  ###  #   #    ###  ### #   #  ###   ###  ###  ###  #
+ #                                                                            #
+ ##############################################################################
+
+# Include the actions defined for this target
+.include "p9_common_actions.rule";
+.include "p9_common_ex_actions.rule";
+